Greg Steiert / pegasus_dev

Development mbed library for MAX32630FTHR

Dependents:   blinky_max32630fthr

cmsis/core_caFunc.h@3:1198227e6421, 2016-12-16 (annotated)

Committer:
switches
Date:
Fri Dec 16 16:27:57 2016 +0000
Revision:
3:1198227e6421
Parent:
0:5c4d7b2438d3 
Changed ADC scale for MAX32625 platforms to 1.2V full scale to match MAX32630 platforms

Who changed what in which revision?

UserRevisionLine numberNew contents of line
switches 0:5c4d7b2438d3 1 /**************************************************************************//**
switches 0:5c4d7b2438d3 2 * @file core_caFunc.h
switches 0:5c4d7b2438d3 3 * @brief CMSIS Cortex-A Core Function Access Header File
switches 0:5c4d7b2438d3 4 * @version V3.10
switches 0:5c4d7b2438d3 5 * @date 30 Oct 2013
switches 0:5c4d7b2438d3 6 *
switches 0:5c4d7b2438d3 7 * @note
switches 0:5c4d7b2438d3 8 *
switches 0:5c4d7b2438d3 9 ******************************************************************************/
switches 0:5c4d7b2438d3 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
switches 0:5c4d7b2438d3 11
switches 0:5c4d7b2438d3 12 All rights reserved.
switches 0:5c4d7b2438d3 13 Redistribution and use in source and binary forms, with or without
switches 0:5c4d7b2438d3 14 modification, are permitted provided that the following conditions are met:
switches 0:5c4d7b2438d3 15 - Redistributions of source code must retain the above copyright
switches 0:5c4d7b2438d3 16 notice, this list of conditions and the following disclaimer.
switches 0:5c4d7b2438d3 17 - Redistributions in binary form must reproduce the above copyright
switches 0:5c4d7b2438d3 18 notice, this list of conditions and the following disclaimer in the
switches 0:5c4d7b2438d3 19 documentation and/or other materials provided with the distribution.
switches 0:5c4d7b2438d3 20 - Neither the name of ARM nor the names of its contributors may be used
switches 0:5c4d7b2438d3 21 to endorse or promote products derived from this software without
switches 0:5c4d7b2438d3 22 specific prior written permission.
switches 0:5c4d7b2438d3 23 *
switches 0:5c4d7b2438d3 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
switches 0:5c4d7b2438d3 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
switches 0:5c4d7b2438d3 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
switches 0:5c4d7b2438d3 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
switches 0:5c4d7b2438d3 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
switches 0:5c4d7b2438d3 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
switches 0:5c4d7b2438d3 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
switches 0:5c4d7b2438d3 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
switches 0:5c4d7b2438d3 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
switches 0:5c4d7b2438d3 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
switches 0:5c4d7b2438d3 34 POSSIBILITY OF SUCH DAMAGE.
switches 0:5c4d7b2438d3 35 ---------------------------------------------------------------------------*/
switches 0:5c4d7b2438d3 36
switches 0:5c4d7b2438d3 37
switches 0:5c4d7b2438d3 38 #ifndef __CORE_CAFUNC_H__
switches 0:5c4d7b2438d3 39 #define __CORE_CAFUNC_H__
switches 0:5c4d7b2438d3 40
switches 0:5c4d7b2438d3 41
switches 0:5c4d7b2438d3 42 /* ########################### Core Function Access ########################### */
switches 0:5c4d7b2438d3 43 /** \ingroup CMSIS_Core_FunctionInterface
switches 0:5c4d7b2438d3 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
switches 0:5c4d7b2438d3 45 @{
switches 0:5c4d7b2438d3 46 */
switches 0:5c4d7b2438d3 47
switches 0:5c4d7b2438d3 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
switches 0:5c4d7b2438d3 49 /* ARM armcc specific functions */
switches 0:5c4d7b2438d3 50
switches 0:5c4d7b2438d3 51 #if (__ARMCC_VERSION < 400677)
switches 0:5c4d7b2438d3 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
switches 0:5c4d7b2438d3 53 #endif
switches 0:5c4d7b2438d3 54
switches 0:5c4d7b2438d3 55 #define MODE_USR 0x10
switches 0:5c4d7b2438d3 56 #define MODE_FIQ 0x11
switches 0:5c4d7b2438d3 57 #define MODE_IRQ 0x12
switches 0:5c4d7b2438d3 58 #define MODE_SVC 0x13
switches 0:5c4d7b2438d3 59 #define MODE_MON 0x16
switches 0:5c4d7b2438d3 60 #define MODE_ABT 0x17
switches 0:5c4d7b2438d3 61 #define MODE_HYP 0x1A
switches 0:5c4d7b2438d3 62 #define MODE_UND 0x1B
switches 0:5c4d7b2438d3 63 #define MODE_SYS 0x1F
switches 0:5c4d7b2438d3 64
switches 0:5c4d7b2438d3 65 /** \brief Get APSR Register
switches 0:5c4d7b2438d3 66
switches 0:5c4d7b2438d3 67 This function returns the content of the APSR Register.
switches 0:5c4d7b2438d3 68
switches 0:5c4d7b2438d3 69 \return APSR Register value
switches 0:5c4d7b2438d3 70 */
switches 0:5c4d7b2438d3 71 __STATIC_INLINE uint32_t __get_APSR(void)
switches 0:5c4d7b2438d3 72 {
switches 0:5c4d7b2438d3 73 register uint32_t __regAPSR __ASM("apsr");
switches 0:5c4d7b2438d3 74 return(__regAPSR);
switches 0:5c4d7b2438d3 75 }
switches 0:5c4d7b2438d3 76
switches 0:5c4d7b2438d3 77
switches 0:5c4d7b2438d3 78 /** \brief Get CPSR Register
switches 0:5c4d7b2438d3 79
switches 0:5c4d7b2438d3 80 This function returns the content of the CPSR Register.
switches 0:5c4d7b2438d3 81
switches 0:5c4d7b2438d3 82 \return CPSR Register value
switches 0:5c4d7b2438d3 83 */
switches 0:5c4d7b2438d3 84 __STATIC_INLINE uint32_t __get_CPSR(void)
switches 0:5c4d7b2438d3 85 {
switches 0:5c4d7b2438d3 86 register uint32_t __regCPSR __ASM("cpsr");
switches 0:5c4d7b2438d3 87 return(__regCPSR);
switches 0:5c4d7b2438d3 88 }
switches 0:5c4d7b2438d3 89
switches 0:5c4d7b2438d3 90 /** \brief Set Stack Pointer
switches 0:5c4d7b2438d3 91
switches 0:5c4d7b2438d3 92 This function assigns the given value to the current stack pointer.
switches 0:5c4d7b2438d3 93
switches 0:5c4d7b2438d3 94 \param [in] topOfStack Stack Pointer value to set
switches 0:5c4d7b2438d3 95 */
switches 0:5c4d7b2438d3 96 register uint32_t __regSP __ASM("sp");
switches 0:5c4d7b2438d3 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
switches 0:5c4d7b2438d3 98 {
switches 0:5c4d7b2438d3 99 __regSP = topOfStack;
switches 0:5c4d7b2438d3 100 }
switches 0:5c4d7b2438d3 101
switches 0:5c4d7b2438d3 102
switches 0:5c4d7b2438d3 103 /** \brief Get link register
switches 0:5c4d7b2438d3 104
switches 0:5c4d7b2438d3 105 This function returns the value of the link register
switches 0:5c4d7b2438d3 106
switches 0:5c4d7b2438d3 107 \return Value of link register
switches 0:5c4d7b2438d3 108 */
switches 0:5c4d7b2438d3 109 register uint32_t __reglr __ASM("lr");
switches 0:5c4d7b2438d3 110 __STATIC_INLINE uint32_t __get_LR(void)
switches 0:5c4d7b2438d3 111 {
switches 0:5c4d7b2438d3 112 return(__reglr);
switches 0:5c4d7b2438d3 113 }
switches 0:5c4d7b2438d3 114
switches 0:5c4d7b2438d3 115 /** \brief Set link register
switches 0:5c4d7b2438d3 116
switches 0:5c4d7b2438d3 117 This function sets the value of the link register
switches 0:5c4d7b2438d3 118
switches 0:5c4d7b2438d3 119 \param [in] lr LR value to set
switches 0:5c4d7b2438d3 120 */
switches 0:5c4d7b2438d3 121 __STATIC_INLINE void __set_LR(uint32_t lr)
switches 0:5c4d7b2438d3 122 {
switches 0:5c4d7b2438d3 123 __reglr = lr;
switches 0:5c4d7b2438d3 124 }
switches 0:5c4d7b2438d3 125
switches 0:5c4d7b2438d3 126 /** \brief Set Process Stack Pointer
switches 0:5c4d7b2438d3 127
switches 0:5c4d7b2438d3 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
switches 0:5c4d7b2438d3 129
switches 0:5c4d7b2438d3 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
switches 0:5c4d7b2438d3 131 */
switches 0:5c4d7b2438d3 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
switches 0:5c4d7b2438d3 133 {
switches 0:5c4d7b2438d3 134 ARM
switches 0:5c4d7b2438d3 135 PRESERVE8
switches 0:5c4d7b2438d3 136
switches 0:5c4d7b2438d3 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
switches 0:5c4d7b2438d3 138 MRS R1, CPSR
switches 0:5c4d7b2438d3 139 CPS #MODE_SYS ;no effect in USR mode
switches 0:5c4d7b2438d3 140 MOV SP, R0
switches 0:5c4d7b2438d3 141 MSR CPSR_c, R1 ;no effect in USR mode
switches 0:5c4d7b2438d3 142 ISB
switches 0:5c4d7b2438d3 143 BX LR
switches 0:5c4d7b2438d3 144
switches 0:5c4d7b2438d3 145 }
switches 0:5c4d7b2438d3 146
switches 0:5c4d7b2438d3 147 /** \brief Set User Mode
switches 0:5c4d7b2438d3 148
switches 0:5c4d7b2438d3 149 This function changes the processor state to User Mode
switches 0:5c4d7b2438d3 150 */
switches 0:5c4d7b2438d3 151 __STATIC_ASM void __set_CPS_USR(void)
switches 0:5c4d7b2438d3 152 {
switches 0:5c4d7b2438d3 153 ARM
switches 0:5c4d7b2438d3 154
switches 0:5c4d7b2438d3 155 CPS #MODE_USR
switches 0:5c4d7b2438d3 156 BX LR
switches 0:5c4d7b2438d3 157 }
switches 0:5c4d7b2438d3 158
switches 0:5c4d7b2438d3 159
switches 0:5c4d7b2438d3 160 /** \brief Enable FIQ
switches 0:5c4d7b2438d3 161
switches 0:5c4d7b2438d3 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
switches 0:5c4d7b2438d3 163 Can only be executed in Privileged modes.
switches 0:5c4d7b2438d3 164 */
switches 0:5c4d7b2438d3 165 #define __enable_fault_irq __enable_fiq
switches 0:5c4d7b2438d3 166
switches 0:5c4d7b2438d3 167
switches 0:5c4d7b2438d3 168 /** \brief Disable FIQ
switches 0:5c4d7b2438d3 169
switches 0:5c4d7b2438d3 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
switches 0:5c4d7b2438d3 171 Can only be executed in Privileged modes.
switches 0:5c4d7b2438d3 172 */
switches 0:5c4d7b2438d3 173 #define __disable_fault_irq __disable_fiq
switches 0:5c4d7b2438d3 174
switches 0:5c4d7b2438d3 175
switches 0:5c4d7b2438d3 176 /** \brief Get FPSCR
switches 0:5c4d7b2438d3 177
switches 0:5c4d7b2438d3 178 This function returns the current value of the Floating Point Status/Control register.
switches 0:5c4d7b2438d3 179
switches 0:5c4d7b2438d3 180 \return Floating Point Status/Control register value
switches 0:5c4d7b2438d3 181 */
switches 0:5c4d7b2438d3 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
switches 0:5c4d7b2438d3 183 {
switches 0:5c4d7b2438d3 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
switches 0:5c4d7b2438d3 185 register uint32_t __regfpscr __ASM("fpscr");
switches 0:5c4d7b2438d3 186 return(__regfpscr);
switches 0:5c4d7b2438d3 187 #else
switches 0:5c4d7b2438d3 188 return(0);
switches 0:5c4d7b2438d3 189 #endif
switches 0:5c4d7b2438d3 190 }
switches 0:5c4d7b2438d3 191
switches 0:5c4d7b2438d3 192
switches 0:5c4d7b2438d3 193 /** \brief Set FPSCR
switches 0:5c4d7b2438d3 194
switches 0:5c4d7b2438d3 195 This function assigns the given value to the Floating Point Status/Control register.
switches 0:5c4d7b2438d3 196
switches 0:5c4d7b2438d3 197 \param [in] fpscr Floating Point Status/Control value to set
switches 0:5c4d7b2438d3 198 */
switches 0:5c4d7b2438d3 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
switches 0:5c4d7b2438d3 200 {
switches 0:5c4d7b2438d3 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
switches 0:5c4d7b2438d3 202 register uint32_t __regfpscr __ASM("fpscr");
switches 0:5c4d7b2438d3 203 __regfpscr = (fpscr);
switches 0:5c4d7b2438d3 204 #endif
switches 0:5c4d7b2438d3 205 }
switches 0:5c4d7b2438d3 206
switches 0:5c4d7b2438d3 207 /** \brief Get FPEXC
switches 0:5c4d7b2438d3 208
switches 0:5c4d7b2438d3 209 This function returns the current value of the Floating Point Exception Control register.
switches 0:5c4d7b2438d3 210
switches 0:5c4d7b2438d3 211 \return Floating Point Exception Control register value
switches 0:5c4d7b2438d3 212 */
switches 0:5c4d7b2438d3 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
switches 0:5c4d7b2438d3 214 {
switches 0:5c4d7b2438d3 215 #if (__FPU_PRESENT == 1)
switches 0:5c4d7b2438d3 216 register uint32_t __regfpexc __ASM("fpexc");
switches 0:5c4d7b2438d3 217 return(__regfpexc);
switches 0:5c4d7b2438d3 218 #else
switches 0:5c4d7b2438d3 219 return(0);
switches 0:5c4d7b2438d3 220 #endif
switches 0:5c4d7b2438d3 221 }
switches 0:5c4d7b2438d3 222
switches 0:5c4d7b2438d3 223
switches 0:5c4d7b2438d3 224 /** \brief Set FPEXC
switches 0:5c4d7b2438d3 225
switches 0:5c4d7b2438d3 226 This function assigns the given value to the Floating Point Exception Control register.
switches 0:5c4d7b2438d3 227
switches 0:5c4d7b2438d3 228 \param [in] fpscr Floating Point Exception Control value to set
switches 0:5c4d7b2438d3 229 */
switches 0:5c4d7b2438d3 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
switches 0:5c4d7b2438d3 231 {
switches 0:5c4d7b2438d3 232 #if (__FPU_PRESENT == 1)
switches 0:5c4d7b2438d3 233 register uint32_t __regfpexc __ASM("fpexc");
switches 0:5c4d7b2438d3 234 __regfpexc = (fpexc);
switches 0:5c4d7b2438d3 235 #endif
switches 0:5c4d7b2438d3 236 }
switches 0:5c4d7b2438d3 237
switches 0:5c4d7b2438d3 238 /** \brief Get CPACR
switches 0:5c4d7b2438d3 239
switches 0:5c4d7b2438d3 240 This function returns the current value of the Coprocessor Access Control register.
switches 0:5c4d7b2438d3 241
switches 0:5c4d7b2438d3 242 \return Coprocessor Access Control register value
switches 0:5c4d7b2438d3 243 */
switches 0:5c4d7b2438d3 244 __STATIC_INLINE uint32_t __get_CPACR(void)
switches 0:5c4d7b2438d3 245 {
switches 0:5c4d7b2438d3 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
switches 0:5c4d7b2438d3 247 return __regCPACR;
switches 0:5c4d7b2438d3 248 }
switches 0:5c4d7b2438d3 249
switches 0:5c4d7b2438d3 250 /** \brief Set CPACR
switches 0:5c4d7b2438d3 251
switches 0:5c4d7b2438d3 252 This function assigns the given value to the Coprocessor Access Control register.
switches 0:5c4d7b2438d3 253
switches 0:5c4d7b2438d3 254 \param [in] cpacr Coprocessor Acccess Control value to set
switches 0:5c4d7b2438d3 255 */
switches 0:5c4d7b2438d3 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
switches 0:5c4d7b2438d3 257 {
switches 0:5c4d7b2438d3 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
switches 0:5c4d7b2438d3 259 __regCPACR = cpacr;
switches 0:5c4d7b2438d3 260 __ISB();
switches 0:5c4d7b2438d3 261 }
switches 0:5c4d7b2438d3 262
switches 0:5c4d7b2438d3 263 /** \brief Get CBAR
switches 0:5c4d7b2438d3 264
switches 0:5c4d7b2438d3 265 This function returns the value of the Configuration Base Address register.
switches 0:5c4d7b2438d3 266
switches 0:5c4d7b2438d3 267 \return Configuration Base Address register value
switches 0:5c4d7b2438d3 268 */
switches 0:5c4d7b2438d3 269 __STATIC_INLINE uint32_t __get_CBAR() {
switches 0:5c4d7b2438d3 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
switches 0:5c4d7b2438d3 271 return(__regCBAR);
switches 0:5c4d7b2438d3 272 }
switches 0:5c4d7b2438d3 273
switches 0:5c4d7b2438d3 274 /** \brief Get TTBR0
switches 0:5c4d7b2438d3 275
switches 0:5c4d7b2438d3 276 This function returns the value of the Translation Table Base Register 0.
switches 0:5c4d7b2438d3 277
switches 0:5c4d7b2438d3 278 \return Translation Table Base Register 0 value
switches 0:5c4d7b2438d3 279 */
switches 0:5c4d7b2438d3 280 __STATIC_INLINE uint32_t __get_TTBR0() {
switches 0:5c4d7b2438d3 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
switches 0:5c4d7b2438d3 282 return(__regTTBR0);
switches 0:5c4d7b2438d3 283 }
switches 0:5c4d7b2438d3 284
switches 0:5c4d7b2438d3 285 /** \brief Set TTBR0
switches 0:5c4d7b2438d3 286
switches 0:5c4d7b2438d3 287 This function assigns the given value to the Translation Table Base Register 0.
switches 0:5c4d7b2438d3 288
switches 0:5c4d7b2438d3 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
switches 0:5c4d7b2438d3 290 */
switches 0:5c4d7b2438d3 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
switches 0:5c4d7b2438d3 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
switches 0:5c4d7b2438d3 293 __regTTBR0 = ttbr0;
switches 0:5c4d7b2438d3 294 __ISB();
switches 0:5c4d7b2438d3 295 }
switches 0:5c4d7b2438d3 296
switches 0:5c4d7b2438d3 297 /** \brief Get DACR
switches 0:5c4d7b2438d3 298
switches 0:5c4d7b2438d3 299 This function returns the value of the Domain Access Control Register.
switches 0:5c4d7b2438d3 300
switches 0:5c4d7b2438d3 301 \return Domain Access Control Register value
switches 0:5c4d7b2438d3 302 */
switches 0:5c4d7b2438d3 303 __STATIC_INLINE uint32_t __get_DACR() {
switches 0:5c4d7b2438d3 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
switches 0:5c4d7b2438d3 305 return(__regDACR);
switches 0:5c4d7b2438d3 306 }
switches 0:5c4d7b2438d3 307
switches 0:5c4d7b2438d3 308 /** \brief Set DACR
switches 0:5c4d7b2438d3 309
switches 0:5c4d7b2438d3 310 This function assigns the given value to the Domain Access Control Register.
switches 0:5c4d7b2438d3 311
switches 0:5c4d7b2438d3 312 \param [in] dacr Domain Access Control Register value to set
switches 0:5c4d7b2438d3 313 */
switches 0:5c4d7b2438d3 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
switches 0:5c4d7b2438d3 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
switches 0:5c4d7b2438d3 316 __regDACR = dacr;
switches 0:5c4d7b2438d3 317 __ISB();
switches 0:5c4d7b2438d3 318 }
switches 0:5c4d7b2438d3 319
switches 0:5c4d7b2438d3 320 /******************************** Cache and BTAC enable ****************************************************/
switches 0:5c4d7b2438d3 321
switches 0:5c4d7b2438d3 322 /** \brief Set SCTLR
switches 0:5c4d7b2438d3 323
switches 0:5c4d7b2438d3 324 This function assigns the given value to the System Control Register.
switches 0:5c4d7b2438d3 325
switches 0:5c4d7b2438d3 326 \param [in] sctlr System Control Register value to set
switches 0:5c4d7b2438d3 327 */
switches 0:5c4d7b2438d3 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
switches 0:5c4d7b2438d3 329 {
switches 0:5c4d7b2438d3 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
switches 0:5c4d7b2438d3 331 __regSCTLR = sctlr;
switches 0:5c4d7b2438d3 332 }
switches 0:5c4d7b2438d3 333
switches 0:5c4d7b2438d3 334 /** \brief Get SCTLR
switches 0:5c4d7b2438d3 335
switches 0:5c4d7b2438d3 336 This function returns the value of the System Control Register.
switches 0:5c4d7b2438d3 337
switches 0:5c4d7b2438d3 338 \return System Control Register value
switches 0:5c4d7b2438d3 339 */
switches 0:5c4d7b2438d3 340 __STATIC_INLINE uint32_t __get_SCTLR() {
switches 0:5c4d7b2438d3 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
switches 0:5c4d7b2438d3 342 return(__regSCTLR);
switches 0:5c4d7b2438d3 343 }
switches 0:5c4d7b2438d3 344
switches 0:5c4d7b2438d3 345 /** \brief Enable Caches
switches 0:5c4d7b2438d3 346
switches 0:5c4d7b2438d3 347 Enable Caches
switches 0:5c4d7b2438d3 348 */
switches 0:5c4d7b2438d3 349 __STATIC_INLINE void __enable_caches(void) {
switches 0:5c4d7b2438d3 350 // Set I bit 12 to enable I Cache
switches 0:5c4d7b2438d3 351 // Set C bit 2 to enable D Cache
switches 0:5c4d7b2438d3 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
switches 0:5c4d7b2438d3 353 }
switches 0:5c4d7b2438d3 354
switches 0:5c4d7b2438d3 355 /** \brief Disable Caches
switches 0:5c4d7b2438d3 356
switches 0:5c4d7b2438d3 357 Disable Caches
switches 0:5c4d7b2438d3 358 */
switches 0:5c4d7b2438d3 359 __STATIC_INLINE void __disable_caches(void) {
switches 0:5c4d7b2438d3 360 // Clear I bit 12 to disable I Cache
switches 0:5c4d7b2438d3 361 // Clear C bit 2 to disable D Cache
switches 0:5c4d7b2438d3 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
switches 0:5c4d7b2438d3 363 __ISB();
switches 0:5c4d7b2438d3 364 }
switches 0:5c4d7b2438d3 365
switches 0:5c4d7b2438d3 366 /** \brief Enable BTAC
switches 0:5c4d7b2438d3 367
switches 0:5c4d7b2438d3 368 Enable BTAC
switches 0:5c4d7b2438d3 369 */
switches 0:5c4d7b2438d3 370 __STATIC_INLINE void __enable_btac(void) {
switches 0:5c4d7b2438d3 371 // Set Z bit 11 to enable branch prediction
switches 0:5c4d7b2438d3 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
switches 0:5c4d7b2438d3 373 __ISB();
switches 0:5c4d7b2438d3 374 }
switches 0:5c4d7b2438d3 375
switches 0:5c4d7b2438d3 376 /** \brief Disable BTAC
switches 0:5c4d7b2438d3 377
switches 0:5c4d7b2438d3 378 Disable BTAC
switches 0:5c4d7b2438d3 379 */
switches 0:5c4d7b2438d3 380 __STATIC_INLINE void __disable_btac(void) {
switches 0:5c4d7b2438d3 381 // Clear Z bit 11 to disable branch prediction
switches 0:5c4d7b2438d3 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
switches 0:5c4d7b2438d3 383 }
switches 0:5c4d7b2438d3 384
switches 0:5c4d7b2438d3 385
switches 0:5c4d7b2438d3 386 /** \brief Enable MMU
switches 0:5c4d7b2438d3 387
switches 0:5c4d7b2438d3 388 Enable MMU
switches 0:5c4d7b2438d3 389 */
switches 0:5c4d7b2438d3 390 __STATIC_INLINE void __enable_mmu(void) {
switches 0:5c4d7b2438d3 391 // Set M bit 0 to enable the MMU
switches 0:5c4d7b2438d3 392 // Set AFE bit to enable simplified access permissions model
switches 0:5c4d7b2438d3 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
switches 0:5c4d7b2438d3 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
switches 0:5c4d7b2438d3 395 __ISB();
switches 0:5c4d7b2438d3 396 }
switches 0:5c4d7b2438d3 397
switches 0:5c4d7b2438d3 398 /** \brief Disable MMU
switches 0:5c4d7b2438d3 399
switches 0:5c4d7b2438d3 400 Disable MMU
switches 0:5c4d7b2438d3 401 */
switches 0:5c4d7b2438d3 402 __STATIC_INLINE void __disable_mmu(void) {
switches 0:5c4d7b2438d3 403 // Clear M bit 0 to disable the MMU
switches 0:5c4d7b2438d3 404 __set_SCTLR( __get_SCTLR() & ~1);
switches 0:5c4d7b2438d3 405 __ISB();
switches 0:5c4d7b2438d3 406 }
switches 0:5c4d7b2438d3 407
switches 0:5c4d7b2438d3 408 /******************************** TLB maintenance operations ************************************************/
switches 0:5c4d7b2438d3 409 /** \brief Invalidate the whole tlb
switches 0:5c4d7b2438d3 410
switches 0:5c4d7b2438d3 411 TLBIALL. Invalidate the whole tlb
switches 0:5c4d7b2438d3 412 */
switches 0:5c4d7b2438d3 413
switches 0:5c4d7b2438d3 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
switches 0:5c4d7b2438d3 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
switches 0:5c4d7b2438d3 416 __TLBIALL = 0;
switches 0:5c4d7b2438d3 417 __DSB();
switches 0:5c4d7b2438d3 418 __ISB();
switches 0:5c4d7b2438d3 419 }
switches 0:5c4d7b2438d3 420
switches 0:5c4d7b2438d3 421 /******************************** BTB maintenance operations ************************************************/
switches 0:5c4d7b2438d3 422 /** \brief Invalidate entire branch predictor array
switches 0:5c4d7b2438d3 423
switches 0:5c4d7b2438d3 424 BPIALL. Branch Predictor Invalidate All.
switches 0:5c4d7b2438d3 425 */
switches 0:5c4d7b2438d3 426
switches 0:5c4d7b2438d3 427 __STATIC_INLINE void __v7_inv_btac(void) {
switches 0:5c4d7b2438d3 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
switches 0:5c4d7b2438d3 429 __BPIALL = 0;
switches 0:5c4d7b2438d3 430 __DSB(); //ensure completion of the invalidation
switches 0:5c4d7b2438d3 431 __ISB(); //ensure instruction fetch path sees new state
switches 0:5c4d7b2438d3 432 }
switches 0:5c4d7b2438d3 433
switches 0:5c4d7b2438d3 434
switches 0:5c4d7b2438d3 435 /******************************** L1 cache operations ******************************************************/
switches 0:5c4d7b2438d3 436
switches 0:5c4d7b2438d3 437 /** \brief Invalidate the whole I$
switches 0:5c4d7b2438d3 438
switches 0:5c4d7b2438d3 439 ICIALLU. Instruction Cache Invalidate All to PoU
switches 0:5c4d7b2438d3 440 */
switches 0:5c4d7b2438d3 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
switches 0:5c4d7b2438d3 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
switches 0:5c4d7b2438d3 443 __ICIALLU = 0;
switches 0:5c4d7b2438d3 444 __DSB(); //ensure completion of the invalidation
switches 0:5c4d7b2438d3 445 __ISB(); //ensure instruction fetch path sees new I cache state
switches 0:5c4d7b2438d3 446 }
switches 0:5c4d7b2438d3 447
switches 0:5c4d7b2438d3 448 /** \brief Clean D$ by MVA
switches 0:5c4d7b2438d3 449
switches 0:5c4d7b2438d3 450 DCCMVAC. Data cache clean by MVA to PoC
switches 0:5c4d7b2438d3 451 */
switches 0:5c4d7b2438d3 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
switches 0:5c4d7b2438d3 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
switches 0:5c4d7b2438d3 454 __DCCMVAC = (uint32_t)va;
switches 0:5c4d7b2438d3 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
switches 0:5c4d7b2438d3 456 }
switches 0:5c4d7b2438d3 457
switches 0:5c4d7b2438d3 458 /** \brief Invalidate D$ by MVA
switches 0:5c4d7b2438d3 459
switches 0:5c4d7b2438d3 460 DCIMVAC. Data cache invalidate by MVA to PoC
switches 0:5c4d7b2438d3 461 */
switches 0:5c4d7b2438d3 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
switches 0:5c4d7b2438d3 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
switches 0:5c4d7b2438d3 464 __DCIMVAC = (uint32_t)va;
switches 0:5c4d7b2438d3 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
switches 0:5c4d7b2438d3 466 }
switches 0:5c4d7b2438d3 467
switches 0:5c4d7b2438d3 468 /** \brief Clean and Invalidate D$ by MVA
switches 0:5c4d7b2438d3 469
switches 0:5c4d7b2438d3 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
switches 0:5c4d7b2438d3 471 */
switches 0:5c4d7b2438d3 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
switches 0:5c4d7b2438d3 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
switches 0:5c4d7b2438d3 474 __DCCIMVAC = (uint32_t)va;
switches 0:5c4d7b2438d3 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
switches 0:5c4d7b2438d3 476 }
switches 0:5c4d7b2438d3 477
switches 0:5c4d7b2438d3 478 /** \brief Clean and Invalidate the entire data or unified cache
switches 0:5c4d7b2438d3 479
switches 0:5c4d7b2438d3 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
switches 0:5c4d7b2438d3 481 */
switches 0:5c4d7b2438d3 482 #pragma push
switches 0:5c4d7b2438d3 483 #pragma arm
switches 0:5c4d7b2438d3 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
switches 0:5c4d7b2438d3 485 ARM
switches 0:5c4d7b2438d3 486
switches 0:5c4d7b2438d3 487 PUSH {R4-R11}
switches 0:5c4d7b2438d3 488
switches 0:5c4d7b2438d3 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
switches 0:5c4d7b2438d3 490 ANDS R3, R6, #0x07000000 // Extract coherency level
switches 0:5c4d7b2438d3 491 MOV R3, R3, LSR #23 // Total cache levels << 1
switches 0:5c4d7b2438d3 492 BEQ Finished // If 0, no need to clean
switches 0:5c4d7b2438d3 493
switches 0:5c4d7b2438d3 494 MOV R10, #0 // R10 holds current cache level << 1
switches 0:5c4d7b2438d3 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
switches 0:5c4d7b2438d3 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
switches 0:5c4d7b2438d3 497 AND R1, R1, #7 // Isolate those lower 3 bits
switches 0:5c4d7b2438d3 498 CMP R1, #2
switches 0:5c4d7b2438d3 499 BLT Skip // No cache or only instruction cache at this level
switches 0:5c4d7b2438d3 500
switches 0:5c4d7b2438d3 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
switches 0:5c4d7b2438d3 502 ISB // ISB to sync the change to the CacheSizeID reg
switches 0:5c4d7b2438d3 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
switches 0:5c4d7b2438d3 504 AND R2, R1, #7 // Extract the line length field
switches 0:5c4d7b2438d3 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
switches 0:5c4d7b2438d3 506 LDR R4, =0x3FF
switches 0:5c4d7b2438d3 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
switches 0:5c4d7b2438d3 508 CLZ R5, R4 // R5 is the bit position of the way size increment
switches 0:5c4d7b2438d3 509 LDR R7, =0x7FFF
switches 0:5c4d7b2438d3 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
switches 0:5c4d7b2438d3 511
switches 0:5c4d7b2438d3 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
switches 0:5c4d7b2438d3 513
switches 0:5c4d7b2438d3 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
switches 0:5c4d7b2438d3 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
switches 0:5c4d7b2438d3 516 CMP R0, #0
switches 0:5c4d7b2438d3 517 BNE Dccsw
switches 0:5c4d7b2438d3 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
switches 0:5c4d7b2438d3 519 B cont
switches 0:5c4d7b2438d3 520 Dccsw CMP R0, #1
switches 0:5c4d7b2438d3 521 BNE Dccisw
switches 0:5c4d7b2438d3 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
switches 0:5c4d7b2438d3 523 B cont
switches 0:5c4d7b2438d3 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
switches 0:5c4d7b2438d3 525 cont SUBS R9, R9, #1 // Decrement the Way number
switches 0:5c4d7b2438d3 526 BGE Loop3
switches 0:5c4d7b2438d3 527 SUBS R7, R7, #1 // Decrement the Set number
switches 0:5c4d7b2438d3 528 BGE Loop2
switches 0:5c4d7b2438d3 529 Skip ADD R10, R10, #2 // Increment the cache number
switches 0:5c4d7b2438d3 530 CMP R3, R10
switches 0:5c4d7b2438d3 531 BGT Loop1
switches 0:5c4d7b2438d3 532
switches 0:5c4d7b2438d3 533 Finished
switches 0:5c4d7b2438d3 534 DSB
switches 0:5c4d7b2438d3 535 POP {R4-R11}
switches 0:5c4d7b2438d3 536 BX lr
switches 0:5c4d7b2438d3 537
switches 0:5c4d7b2438d3 538 }
switches 0:5c4d7b2438d3 539 #pragma pop
switches 0:5c4d7b2438d3 540
switches 0:5c4d7b2438d3 541
switches 0:5c4d7b2438d3 542 /** \brief Invalidate the whole D$
switches 0:5c4d7b2438d3 543
switches 0:5c4d7b2438d3 544 DCISW. Invalidate by Set/Way
switches 0:5c4d7b2438d3 545 */
switches 0:5c4d7b2438d3 546
switches 0:5c4d7b2438d3 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
switches 0:5c4d7b2438d3 548 __v7_all_cache(0);
switches 0:5c4d7b2438d3 549 }
switches 0:5c4d7b2438d3 550
switches 0:5c4d7b2438d3 551 /** \brief Clean the whole D$
switches 0:5c4d7b2438d3 552
switches 0:5c4d7b2438d3 553 DCCSW. Clean by Set/Way
switches 0:5c4d7b2438d3 554 */
switches 0:5c4d7b2438d3 555
switches 0:5c4d7b2438d3 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
switches 0:5c4d7b2438d3 557 __v7_all_cache(1);
switches 0:5c4d7b2438d3 558 }
switches 0:5c4d7b2438d3 559
switches 0:5c4d7b2438d3 560 /** \brief Clean and invalidate the whole D$
switches 0:5c4d7b2438d3 561
switches 0:5c4d7b2438d3 562 DCCISW. Clean and Invalidate by Set/Way
switches 0:5c4d7b2438d3 563 */
switches 0:5c4d7b2438d3 564
switches 0:5c4d7b2438d3 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
switches 0:5c4d7b2438d3 566 __v7_all_cache(2);
switches 0:5c4d7b2438d3 567 }
switches 0:5c4d7b2438d3 568
switches 0:5c4d7b2438d3 569 #include "core_ca_mmu.h"
switches 0:5c4d7b2438d3 570
switches 0:5c4d7b2438d3 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
switches 0:5c4d7b2438d3 572
switches 0:5c4d7b2438d3 573 #define __inline inline
switches 0:5c4d7b2438d3 574
switches 0:5c4d7b2438d3 575 inline static uint32_t __disable_irq_iar() {
switches 0:5c4d7b2438d3 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
switches 0:5c4d7b2438d3 577 __disable_irq();
switches 0:5c4d7b2438d3 578 return irq_dis;
switches 0:5c4d7b2438d3 579 }
switches 0:5c4d7b2438d3 580
switches 0:5c4d7b2438d3 581 #define MODE_USR 0x10
switches 0:5c4d7b2438d3 582 #define MODE_FIQ 0x11
switches 0:5c4d7b2438d3 583 #define MODE_IRQ 0x12
switches 0:5c4d7b2438d3 584 #define MODE_SVC 0x13
switches 0:5c4d7b2438d3 585 #define MODE_MON 0x16
switches 0:5c4d7b2438d3 586 #define MODE_ABT 0x17
switches 0:5c4d7b2438d3 587 #define MODE_HYP 0x1A
switches 0:5c4d7b2438d3 588 #define MODE_UND 0x1B
switches 0:5c4d7b2438d3 589 #define MODE_SYS 0x1F
switches 0:5c4d7b2438d3 590
switches 0:5c4d7b2438d3 591 /** \brief Set Process Stack Pointer
switches 0:5c4d7b2438d3 592
switches 0:5c4d7b2438d3 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
switches 0:5c4d7b2438d3 594
switches 0:5c4d7b2438d3 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
switches 0:5c4d7b2438d3 596 */
switches 0:5c4d7b2438d3 597 // from rt_CMSIS.c
switches 0:5c4d7b2438d3 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
switches 0:5c4d7b2438d3 599 __asm(
switches 0:5c4d7b2438d3 600 " ARM\n"
switches 0:5c4d7b2438d3 601 // " PRESERVE8\n"
switches 0:5c4d7b2438d3 602
switches 0:5c4d7b2438d3 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
switches 0:5c4d7b2438d3 604 " MRS R1, CPSR \n"
switches 0:5c4d7b2438d3 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
switches 0:5c4d7b2438d3 606 " MOV SP, R0 \n"
switches 0:5c4d7b2438d3 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
switches 0:5c4d7b2438d3 608 " ISB \n"
switches 0:5c4d7b2438d3 609 " BX LR \n");
switches 0:5c4d7b2438d3 610 }
switches 0:5c4d7b2438d3 611
switches 0:5c4d7b2438d3 612 /** \brief Set User Mode
switches 0:5c4d7b2438d3 613
switches 0:5c4d7b2438d3 614 This function changes the processor state to User Mode
switches 0:5c4d7b2438d3 615 */
switches 0:5c4d7b2438d3 616 // from rt_CMSIS.c
switches 0:5c4d7b2438d3 617 __arm static inline void __set_CPS_USR(void) {
switches 0:5c4d7b2438d3 618 __asm(
switches 0:5c4d7b2438d3 619 " ARM \n"
switches 0:5c4d7b2438d3 620
switches 0:5c4d7b2438d3 621 " CPS #0x10 \n" // MODE_USR
switches 0:5c4d7b2438d3 622 " BX LR\n");
switches 0:5c4d7b2438d3 623 }
switches 0:5c4d7b2438d3 624
switches 0:5c4d7b2438d3 625 /** \brief Set TTBR0
switches 0:5c4d7b2438d3 626
switches 0:5c4d7b2438d3 627 This function assigns the given value to the Translation Table Base Register 0.
switches 0:5c4d7b2438d3 628
switches 0:5c4d7b2438d3 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
switches 0:5c4d7b2438d3 630 */
switches 0:5c4d7b2438d3 631 // from mmu_Renesas_RZ_A1.c
switches 0:5c4d7b2438d3 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
switches 0:5c4d7b2438d3 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
switches 0:5c4d7b2438d3 634 __ISB();
switches 0:5c4d7b2438d3 635 }
switches 0:5c4d7b2438d3 636
switches 0:5c4d7b2438d3 637 /** \brief Set DACR
switches 0:5c4d7b2438d3 638
switches 0:5c4d7b2438d3 639 This function assigns the given value to the Domain Access Control Register.
switches 0:5c4d7b2438d3 640
switches 0:5c4d7b2438d3 641 \param [in] dacr Domain Access Control Register value to set
switches 0:5c4d7b2438d3 642 */
switches 0:5c4d7b2438d3 643 // from mmu_Renesas_RZ_A1.c
switches 0:5c4d7b2438d3 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
switches 0:5c4d7b2438d3 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
switches 0:5c4d7b2438d3 646 __ISB();
switches 0:5c4d7b2438d3 647 }
switches 0:5c4d7b2438d3 648
switches 0:5c4d7b2438d3 649
switches 0:5c4d7b2438d3 650 /******************************** Cache and BTAC enable ****************************************************/
switches 0:5c4d7b2438d3 651 /** \brief Set SCTLR
switches 0:5c4d7b2438d3 652
switches 0:5c4d7b2438d3 653 This function assigns the given value to the System Control Register.
switches 0:5c4d7b2438d3 654
switches 0:5c4d7b2438d3 655 \param [in] sctlr System Control Register value to set
switches 0:5c4d7b2438d3 656 */
switches 0:5c4d7b2438d3 657 // from __enable_mmu()
switches 0:5c4d7b2438d3 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
switches 0:5c4d7b2438d3 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
switches 0:5c4d7b2438d3 660 }
switches 0:5c4d7b2438d3 661
switches 0:5c4d7b2438d3 662 /** \brief Get SCTLR
switches 0:5c4d7b2438d3 663
switches 0:5c4d7b2438d3 664 This function returns the value of the System Control Register.
switches 0:5c4d7b2438d3 665
switches 0:5c4d7b2438d3 666 \return System Control Register value
switches 0:5c4d7b2438d3 667 */
switches 0:5c4d7b2438d3 668 // from __enable_mmu()
switches 0:5c4d7b2438d3 669 __STATIC_INLINE uint32_t __get_SCTLR() {
switches 0:5c4d7b2438d3 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
switches 0:5c4d7b2438d3 671 return __regSCTLR;
switches 0:5c4d7b2438d3 672 }
switches 0:5c4d7b2438d3 673
switches 0:5c4d7b2438d3 674 /** \brief Enable Caches
switches 0:5c4d7b2438d3 675
switches 0:5c4d7b2438d3 676 Enable Caches
switches 0:5c4d7b2438d3 677 */
switches 0:5c4d7b2438d3 678 // from system_Renesas_RZ_A1.c
switches 0:5c4d7b2438d3 679 __STATIC_INLINE void __enable_caches(void) {
switches 0:5c4d7b2438d3 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
switches 0:5c4d7b2438d3 681 }
switches 0:5c4d7b2438d3 682
switches 0:5c4d7b2438d3 683 /** \brief Enable BTAC
switches 0:5c4d7b2438d3 684
switches 0:5c4d7b2438d3 685 Enable BTAC
switches 0:5c4d7b2438d3 686 */
switches 0:5c4d7b2438d3 687 // from system_Renesas_RZ_A1.c
switches 0:5c4d7b2438d3 688 __STATIC_INLINE void __enable_btac(void) {
switches 0:5c4d7b2438d3 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
switches 0:5c4d7b2438d3 690 __ISB();
switches 0:5c4d7b2438d3 691 }
switches 0:5c4d7b2438d3 692
switches 0:5c4d7b2438d3 693 /** \brief Enable MMU
switches 0:5c4d7b2438d3 694
switches 0:5c4d7b2438d3 695 Enable MMU
switches 0:5c4d7b2438d3 696 */
switches 0:5c4d7b2438d3 697 // from system_Renesas_RZ_A1.c
switches 0:5c4d7b2438d3 698 __STATIC_INLINE void __enable_mmu(void) {
switches 0:5c4d7b2438d3 699 // Set M bit 0 to enable the MMU
switches 0:5c4d7b2438d3 700 // Set AFE bit to enable simplified access permissions model
switches 0:5c4d7b2438d3 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
switches 0:5c4d7b2438d3 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
switches 0:5c4d7b2438d3 703 __ISB();
switches 0:5c4d7b2438d3 704 }
switches 0:5c4d7b2438d3 705
switches 0:5c4d7b2438d3 706 /******************************** TLB maintenance operations ************************************************/
switches 0:5c4d7b2438d3 707 /** \brief Invalidate the whole tlb
switches 0:5c4d7b2438d3 708
switches 0:5c4d7b2438d3 709 TLBIALL. Invalidate the whole tlb
switches 0:5c4d7b2438d3 710 */
switches 0:5c4d7b2438d3 711 // from system_Renesas_RZ_A1.c
switches 0:5c4d7b2438d3 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
switches 0:5c4d7b2438d3 713 uint32_t val = 0;
switches 0:5c4d7b2438d3 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
switches 0:5c4d7b2438d3 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
switches 0:5c4d7b2438d3 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
switches 0:5c4d7b2438d3 717 __DSB();
switches 0:5c4d7b2438d3 718 __ISB();
switches 0:5c4d7b2438d3 719 }
switches 0:5c4d7b2438d3 720
switches 0:5c4d7b2438d3 721 /******************************** BTB maintenance operations ************************************************/
switches 0:5c4d7b2438d3 722 /** \brief Invalidate entire branch predictor array
switches 0:5c4d7b2438d3 723
switches 0:5c4d7b2438d3 724 BPIALL. Branch Predictor Invalidate All.
switches 0:5c4d7b2438d3 725 */
switches 0:5c4d7b2438d3 726 // from system_Renesas_RZ_A1.c
switches 0:5c4d7b2438d3 727 __STATIC_INLINE void __v7_inv_btac(void) {
switches 0:5c4d7b2438d3 728 uint32_t val = 0;
switches 0:5c4d7b2438d3 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
switches 0:5c4d7b2438d3 730 __DSB(); //ensure completion of the invalidation
switches 0:5c4d7b2438d3 731 __ISB(); //ensure instruction fetch path sees new state
switches 0:5c4d7b2438d3 732 }
switches 0:5c4d7b2438d3 733
switches 0:5c4d7b2438d3 734
switches 0:5c4d7b2438d3 735 /******************************** L1 cache operations ******************************************************/
switches 0:5c4d7b2438d3 736
switches 0:5c4d7b2438d3 737 /** \brief Invalidate the whole I$
switches 0:5c4d7b2438d3 738
switches 0:5c4d7b2438d3 739 ICIALLU. Instruction Cache Invalidate All to PoU
switches 0:5c4d7b2438d3 740 */
switches 0:5c4d7b2438d3 741 // from system_Renesas_RZ_A1.c
switches 0:5c4d7b2438d3 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
switches 0:5c4d7b2438d3 743 uint32_t val = 0;
switches 0:5c4d7b2438d3 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
switches 0:5c4d7b2438d3 745 __DSB(); //ensure completion of the invalidation
switches 0:5c4d7b2438d3 746 __ISB(); //ensure instruction fetch path sees new I cache state
switches 0:5c4d7b2438d3 747 }
switches 0:5c4d7b2438d3 748
switches 0:5c4d7b2438d3 749 // from __v7_inv_dcache_all()
switches 0:5c4d7b2438d3 750 __arm static inline void __v7_all_cache(uint32_t op) {
switches 0:5c4d7b2438d3 751 __asm(
switches 0:5c4d7b2438d3 752 " ARM \n"
switches 0:5c4d7b2438d3 753
switches 0:5c4d7b2438d3 754 " PUSH {R4-R11} \n"
switches 0:5c4d7b2438d3 755
switches 0:5c4d7b2438d3 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
switches 0:5c4d7b2438d3 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
switches 0:5c4d7b2438d3 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
switches 0:5c4d7b2438d3 759 " BEQ Finished\n" // If 0, no need to clean
switches 0:5c4d7b2438d3 760
switches 0:5c4d7b2438d3 761 " MOV R10, #0\n" // R10 holds current cache level << 1
switches 0:5c4d7b2438d3 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
switches 0:5c4d7b2438d3 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
switches 0:5c4d7b2438d3 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
switches 0:5c4d7b2438d3 765 " CMP R1, #2 \n"
switches 0:5c4d7b2438d3 766 " BLT Skip \n" // No cache or only instruction cache at this level
switches 0:5c4d7b2438d3 767
switches 0:5c4d7b2438d3 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
switches 0:5c4d7b2438d3 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
switches 0:5c4d7b2438d3 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
switches 0:5c4d7b2438d3 771 " AND R2, R1, #7 \n" // Extract the line length field
switches 0:5c4d7b2438d3 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
switches 0:5c4d7b2438d3 773 " movw R4, #0x3FF \n"
switches 0:5c4d7b2438d3 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
switches 0:5c4d7b2438d3 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
switches 0:5c4d7b2438d3 776 " movw R7, #0x7FFF \n"
switches 0:5c4d7b2438d3 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
switches 0:5c4d7b2438d3 778
switches 0:5c4d7b2438d3 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
switches 0:5c4d7b2438d3 780
switches 0:5c4d7b2438d3 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
switches 0:5c4d7b2438d3 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
switches 0:5c4d7b2438d3 783 " CMP R0, #0 \n"
switches 0:5c4d7b2438d3 784 " BNE Dccsw \n"
switches 0:5c4d7b2438d3 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
switches 0:5c4d7b2438d3 786 " B cont \n"
switches 0:5c4d7b2438d3 787 "Dccsw: CMP R0, #1 \n"
switches 0:5c4d7b2438d3 788 " BNE Dccisw \n"
switches 0:5c4d7b2438d3 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
switches 0:5c4d7b2438d3 790 " B cont \n"
switches 0:5c4d7b2438d3 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
switches 0:5c4d7b2438d3 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
switches 0:5c4d7b2438d3 793 " BGE Loop3 \n"
switches 0:5c4d7b2438d3 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
switches 0:5c4d7b2438d3 795 " BGE Loop2 \n"
switches 0:5c4d7b2438d3 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
switches 0:5c4d7b2438d3 797 " CMP R3, R10 \n"
switches 0:5c4d7b2438d3 798 " BGT Loop1 \n"
switches 0:5c4d7b2438d3 799
switches 0:5c4d7b2438d3 800 "Finished: \n"
switches 0:5c4d7b2438d3 801 " DSB \n"
switches 0:5c4d7b2438d3 802 " POP {R4-R11} \n"
switches 0:5c4d7b2438d3 803 " BX lr \n" );
switches 0:5c4d7b2438d3 804 }
switches 0:5c4d7b2438d3 805
switches 0:5c4d7b2438d3 806 /** \brief Invalidate the whole D$
switches 0:5c4d7b2438d3 807
switches 0:5c4d7b2438d3 808 DCISW. Invalidate by Set/Way
switches 0:5c4d7b2438d3 809 */
switches 0:5c4d7b2438d3 810 // from system_Renesas_RZ_A1.c
switches 0:5c4d7b2438d3 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
switches 0:5c4d7b2438d3 812 __v7_all_cache(0);
switches 0:5c4d7b2438d3 813 }
switches 0:5c4d7b2438d3 814 /** \brief Clean and Invalidate D$ by MVA
switches 0:5c4d7b2438d3 815
switches 0:5c4d7b2438d3 816 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
switches 0:5c4d7b2438d3 817 */
switches 0:5c4d7b2438d3 818 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
switches 0:5c4d7b2438d3 819 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
switches 0:5c4d7b2438d3 820 __DMB();
switches 0:5c4d7b2438d3 821 }
switches 0:5c4d7b2438d3 822
switches 0:5c4d7b2438d3 823 #include "core_ca_mmu.h"
switches 0:5c4d7b2438d3 824
switches 0:5c4d7b2438d3 825 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
switches 0:5c4d7b2438d3 826 /* GNU gcc specific functions */
switches 0:5c4d7b2438d3 827
switches 0:5c4d7b2438d3 828 #define MODE_USR 0x10
switches 0:5c4d7b2438d3 829 #define MODE_FIQ 0x11
switches 0:5c4d7b2438d3 830 #define MODE_IRQ 0x12
switches 0:5c4d7b2438d3 831 #define MODE_SVC 0x13
switches 0:5c4d7b2438d3 832 #define MODE_MON 0x16
switches 0:5c4d7b2438d3 833 #define MODE_ABT 0x17
switches 0:5c4d7b2438d3 834 #define MODE_HYP 0x1A
switches 0:5c4d7b2438d3 835 #define MODE_UND 0x1B
switches 0:5c4d7b2438d3 836 #define MODE_SYS 0x1F
switches 0:5c4d7b2438d3 837
switches 0:5c4d7b2438d3 838
switches 0:5c4d7b2438d3 839 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
switches 0:5c4d7b2438d3 840 {
switches 0:5c4d7b2438d3 841 __ASM volatile ("cpsie i");
switches 0:5c4d7b2438d3 842 }
switches 0:5c4d7b2438d3 843
switches 0:5c4d7b2438d3 844 /** \brief Disable IRQ Interrupts
switches 0:5c4d7b2438d3 845
switches 0:5c4d7b2438d3 846 This function disables IRQ interrupts by setting the I-bit in the CPSR.
switches 0:5c4d7b2438d3 847 Can only be executed in Privileged modes.
switches 0:5c4d7b2438d3 848 */
switches 0:5c4d7b2438d3 849 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
switches 0:5c4d7b2438d3 850 {
switches 0:5c4d7b2438d3 851 uint32_t result;
switches 0:5c4d7b2438d3 852
switches 0:5c4d7b2438d3 853 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
switches 0:5c4d7b2438d3 854 __ASM volatile ("cpsid i");
switches 0:5c4d7b2438d3 855 return(result & 0x80);
switches 0:5c4d7b2438d3 856 }
switches 0:5c4d7b2438d3 857
switches 0:5c4d7b2438d3 858
switches 0:5c4d7b2438d3 859 /** \brief Get APSR Register
switches 0:5c4d7b2438d3 860
switches 0:5c4d7b2438d3 861 This function returns the content of the APSR Register.
switches 0:5c4d7b2438d3 862
switches 0:5c4d7b2438d3 863 \return APSR Register value
switches 0:5c4d7b2438d3 864 */
switches 0:5c4d7b2438d3 865 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
switches 0:5c4d7b2438d3 866 {
switches 0:5c4d7b2438d3 867 #if 1
switches 0:5c4d7b2438d3 868 register uint32_t __regAPSR;
switches 0:5c4d7b2438d3 869 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
switches 0:5c4d7b2438d3 870 #else
switches 0:5c4d7b2438d3 871 register uint32_t __regAPSR __ASM("apsr");
switches 0:5c4d7b2438d3 872 #endif
switches 0:5c4d7b2438d3 873 return(__regAPSR);
switches 0:5c4d7b2438d3 874 }
switches 0:5c4d7b2438d3 875
switches 0:5c4d7b2438d3 876
switches 0:5c4d7b2438d3 877 /** \brief Get CPSR Register
switches 0:5c4d7b2438d3 878
switches 0:5c4d7b2438d3 879 This function returns the content of the CPSR Register.
switches 0:5c4d7b2438d3 880
switches 0:5c4d7b2438d3 881 \return CPSR Register value
switches 0:5c4d7b2438d3 882 */
switches 0:5c4d7b2438d3 883 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
switches 0:5c4d7b2438d3 884 {
switches 0:5c4d7b2438d3 885 #if 1
switches 0:5c4d7b2438d3 886 register uint32_t __regCPSR;
switches 0:5c4d7b2438d3 887 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
switches 0:5c4d7b2438d3 888 #else
switches 0:5c4d7b2438d3 889 register uint32_t __regCPSR __ASM("cpsr");
switches 0:5c4d7b2438d3 890 #endif
switches 0:5c4d7b2438d3 891 return(__regCPSR);
switches 0:5c4d7b2438d3 892 }
switches 0:5c4d7b2438d3 893
switches 0:5c4d7b2438d3 894 #if 0
switches 0:5c4d7b2438d3 895 /** \brief Set Stack Pointer
switches 0:5c4d7b2438d3 896
switches 0:5c4d7b2438d3 897 This function assigns the given value to the current stack pointer.
switches 0:5c4d7b2438d3 898
switches 0:5c4d7b2438d3 899 \param [in] topOfStack Stack Pointer value to set
switches 0:5c4d7b2438d3 900 */
switches 0:5c4d7b2438d3 901 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
switches 0:5c4d7b2438d3 902 {
switches 0:5c4d7b2438d3 903 register uint32_t __regSP __ASM("sp");
switches 0:5c4d7b2438d3 904 __regSP = topOfStack;
switches 0:5c4d7b2438d3 905 }
switches 0:5c4d7b2438d3 906 #endif
switches 0:5c4d7b2438d3 907
switches 0:5c4d7b2438d3 908 /** \brief Get link register
switches 0:5c4d7b2438d3 909
switches 0:5c4d7b2438d3 910 This function returns the value of the link register
switches 0:5c4d7b2438d3 911
switches 0:5c4d7b2438d3 912 \return Value of link register
switches 0:5c4d7b2438d3 913 */
switches 0:5c4d7b2438d3 914 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
switches 0:5c4d7b2438d3 915 {
switches 0:5c4d7b2438d3 916 register uint32_t __reglr __ASM("lr");
switches 0:5c4d7b2438d3 917 return(__reglr);
switches 0:5c4d7b2438d3 918 }
switches 0:5c4d7b2438d3 919
switches 0:5c4d7b2438d3 920 #if 0
switches 0:5c4d7b2438d3 921 /** \brief Set link register
switches 0:5c4d7b2438d3 922
switches 0:5c4d7b2438d3 923 This function sets the value of the link register
switches 0:5c4d7b2438d3 924
switches 0:5c4d7b2438d3 925 \param [in] lr LR value to set
switches 0:5c4d7b2438d3 926 */
switches 0:5c4d7b2438d3 927 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
switches 0:5c4d7b2438d3 928 {
switches 0:5c4d7b2438d3 929 register uint32_t __reglr __ASM("lr");
switches 0:5c4d7b2438d3 930 __reglr = lr;
switches 0:5c4d7b2438d3 931 }
switches 0:5c4d7b2438d3 932 #endif
switches 0:5c4d7b2438d3 933
switches 0:5c4d7b2438d3 934 /** \brief Set Process Stack Pointer
switches 0:5c4d7b2438d3 935
switches 0:5c4d7b2438d3 936 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
switches 0:5c4d7b2438d3 937
switches 0:5c4d7b2438d3 938 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
switches 0:5c4d7b2438d3 939 */
switches 0:5c4d7b2438d3 940 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
switches 0:5c4d7b2438d3 941 {
switches 0:5c4d7b2438d3 942 __asm__ volatile (
switches 0:5c4d7b2438d3 943 ".ARM;"
switches 0:5c4d7b2438d3 944 ".eabi_attribute Tag_ABI_align8_preserved,1;"
switches 0:5c4d7b2438d3 945
switches 0:5c4d7b2438d3 946 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
switches 0:5c4d7b2438d3 947 "MRS R1, CPSR;"
switches 0:5c4d7b2438d3 948 "CPS %0;" /* ;no effect in USR mode */
switches 0:5c4d7b2438d3 949 "MOV SP, R0;"
switches 0:5c4d7b2438d3 950 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
switches 0:5c4d7b2438d3 951 "ISB;"
switches 0:5c4d7b2438d3 952 //"BX LR;"
switches 0:5c4d7b2438d3 953 :
switches 0:5c4d7b2438d3 954 : "i"(MODE_SYS)
switches 0:5c4d7b2438d3 955 : "r0", "r1");
switches 0:5c4d7b2438d3 956 return;
switches 0:5c4d7b2438d3 957 }
switches 0:5c4d7b2438d3 958
switches 0:5c4d7b2438d3 959 /** \brief Set User Mode
switches 0:5c4d7b2438d3 960
switches 0:5c4d7b2438d3 961 This function changes the processor state to User Mode
switches 0:5c4d7b2438d3 962 */
switches 0:5c4d7b2438d3 963 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
switches 0:5c4d7b2438d3 964 {
switches 0:5c4d7b2438d3 965 __asm__ volatile (
switches 0:5c4d7b2438d3 966 ".ARM;"
switches 0:5c4d7b2438d3 967
switches 0:5c4d7b2438d3 968 "CPS %0;"
switches 0:5c4d7b2438d3 969 //"BX LR;"
switches 0:5c4d7b2438d3 970 :
switches 0:5c4d7b2438d3 971 : "i"(MODE_USR)
switches 0:5c4d7b2438d3 972 : );
switches 0:5c4d7b2438d3 973 return;
switches 0:5c4d7b2438d3 974 }
switches 0:5c4d7b2438d3 975
switches 0:5c4d7b2438d3 976
switches 0:5c4d7b2438d3 977 /** \brief Enable FIQ
switches 0:5c4d7b2438d3 978
switches 0:5c4d7b2438d3 979 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
switches 0:5c4d7b2438d3 980 Can only be executed in Privileged modes.
switches 0:5c4d7b2438d3 981 */
switches 0:5c4d7b2438d3 982 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
switches 0:5c4d7b2438d3 983
switches 0:5c4d7b2438d3 984
switches 0:5c4d7b2438d3 985 /** \brief Disable FIQ
switches 0:5c4d7b2438d3 986
switches 0:5c4d7b2438d3 987 This function disables FIQ interrupts by setting the F-bit in the CPSR.
switches 0:5c4d7b2438d3 988 Can only be executed in Privileged modes.
switches 0:5c4d7b2438d3 989 */
switches 0:5c4d7b2438d3 990 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
switches 0:5c4d7b2438d3 991
switches 0:5c4d7b2438d3 992
switches 0:5c4d7b2438d3 993 /** \brief Get FPSCR
switches 0:5c4d7b2438d3 994
switches 0:5c4d7b2438d3 995 This function returns the current value of the Floating Point Status/Control register.
switches 0:5c4d7b2438d3 996
switches 0:5c4d7b2438d3 997 \return Floating Point Status/Control register value
switches 0:5c4d7b2438d3 998 */
switches 0:5c4d7b2438d3 999 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
switches 0:5c4d7b2438d3 1000 {
switches 0:5c4d7b2438d3 1001 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
switches 0:5c4d7b2438d3 1002 #if 1
switches 0:5c4d7b2438d3 1003 uint32_t result;
switches 0:5c4d7b2438d3 1004
switches 0:5c4d7b2438d3 1005 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
switches 0:5c4d7b2438d3 1006 return (result);
switches 0:5c4d7b2438d3 1007 #else
switches 0:5c4d7b2438d3 1008 register uint32_t __regfpscr __ASM("fpscr");
switches 0:5c4d7b2438d3 1009 return(__regfpscr);
switches 0:5c4d7b2438d3 1010 #endif
switches 0:5c4d7b2438d3 1011 #else
switches 0:5c4d7b2438d3 1012 return(0);
switches 0:5c4d7b2438d3 1013 #endif
switches 0:5c4d7b2438d3 1014 }
switches 0:5c4d7b2438d3 1015
switches 0:5c4d7b2438d3 1016
switches 0:5c4d7b2438d3 1017 /** \brief Set FPSCR
switches 0:5c4d7b2438d3 1018
switches 0:5c4d7b2438d3 1019 This function assigns the given value to the Floating Point Status/Control register.
switches 0:5c4d7b2438d3 1020
switches 0:5c4d7b2438d3 1021 \param [in] fpscr Floating Point Status/Control value to set
switches 0:5c4d7b2438d3 1022 */
switches 0:5c4d7b2438d3 1023 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
switches 0:5c4d7b2438d3 1024 {
switches 0:5c4d7b2438d3 1025 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
switches 0:5c4d7b2438d3 1026 #if 1
switches 0:5c4d7b2438d3 1027 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
switches 0:5c4d7b2438d3 1028 #else
switches 0:5c4d7b2438d3 1029 register uint32_t __regfpscr __ASM("fpscr");
switches 0:5c4d7b2438d3 1030 __regfpscr = (fpscr);
switches 0:5c4d7b2438d3 1031 #endif
switches 0:5c4d7b2438d3 1032 #endif
switches 0:5c4d7b2438d3 1033 }
switches 0:5c4d7b2438d3 1034
switches 0:5c4d7b2438d3 1035 /** \brief Get FPEXC
switches 0:5c4d7b2438d3 1036
switches 0:5c4d7b2438d3 1037 This function returns the current value of the Floating Point Exception Control register.
switches 0:5c4d7b2438d3 1038
switches 0:5c4d7b2438d3 1039 \return Floating Point Exception Control register value
switches 0:5c4d7b2438d3 1040 */
switches 0:5c4d7b2438d3 1041 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
switches 0:5c4d7b2438d3 1042 {
switches 0:5c4d7b2438d3 1043 #if (__FPU_PRESENT == 1)
switches 0:5c4d7b2438d3 1044 #if 1
switches 0:5c4d7b2438d3 1045 uint32_t result;
switches 0:5c4d7b2438d3 1046
switches 0:5c4d7b2438d3 1047 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
switches 0:5c4d7b2438d3 1048 return (result);
switches 0:5c4d7b2438d3 1049 #else
switches 0:5c4d7b2438d3 1050 register uint32_t __regfpexc __ASM("fpexc");
switches 0:5c4d7b2438d3 1051 return(__regfpexc);
switches 0:5c4d7b2438d3 1052 #endif
switches 0:5c4d7b2438d3 1053 #else
switches 0:5c4d7b2438d3 1054 return(0);
switches 0:5c4d7b2438d3 1055 #endif
switches 0:5c4d7b2438d3 1056 }
switches 0:5c4d7b2438d3 1057
switches 0:5c4d7b2438d3 1058
switches 0:5c4d7b2438d3 1059 /** \brief Set FPEXC
switches 0:5c4d7b2438d3 1060
switches 0:5c4d7b2438d3 1061 This function assigns the given value to the Floating Point Exception Control register.
switches 0:5c4d7b2438d3 1062
switches 0:5c4d7b2438d3 1063 \param [in] fpscr Floating Point Exception Control value to set
switches 0:5c4d7b2438d3 1064 */
switches 0:5c4d7b2438d3 1065 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
switches 0:5c4d7b2438d3 1066 {
switches 0:5c4d7b2438d3 1067 #if (__FPU_PRESENT == 1)
switches 0:5c4d7b2438d3 1068 #if 1
switches 0:5c4d7b2438d3 1069 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
switches 0:5c4d7b2438d3 1070 #else
switches 0:5c4d7b2438d3 1071 register uint32_t __regfpexc __ASM("fpexc");
switches 0:5c4d7b2438d3 1072 __regfpexc = (fpexc);
switches 0:5c4d7b2438d3 1073 #endif
switches 0:5c4d7b2438d3 1074 #endif
switches 0:5c4d7b2438d3 1075 }
switches 0:5c4d7b2438d3 1076
switches 0:5c4d7b2438d3 1077 /** \brief Get CPACR
switches 0:5c4d7b2438d3 1078
switches 0:5c4d7b2438d3 1079 This function returns the current value of the Coprocessor Access Control register.
switches 0:5c4d7b2438d3 1080
switches 0:5c4d7b2438d3 1081 \return Coprocessor Access Control register value
switches 0:5c4d7b2438d3 1082 */
switches 0:5c4d7b2438d3 1083 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
switches 0:5c4d7b2438d3 1084 {
switches 0:5c4d7b2438d3 1085 #if 1
switches 0:5c4d7b2438d3 1086 register uint32_t __regCPACR;
switches 0:5c4d7b2438d3 1087 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
switches 0:5c4d7b2438d3 1088 #else
switches 0:5c4d7b2438d3 1089 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
switches 0:5c4d7b2438d3 1090 #endif
switches 0:5c4d7b2438d3 1091 return __regCPACR;
switches 0:5c4d7b2438d3 1092 }
switches 0:5c4d7b2438d3 1093
switches 0:5c4d7b2438d3 1094 /** \brief Set CPACR
switches 0:5c4d7b2438d3 1095
switches 0:5c4d7b2438d3 1096 This function assigns the given value to the Coprocessor Access Control register.
switches 0:5c4d7b2438d3 1097
switches 0:5c4d7b2438d3 1098 \param [in] cpacr Coprocessor Acccess Control value to set
switches 0:5c4d7b2438d3 1099 */
switches 0:5c4d7b2438d3 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
switches 0:5c4d7b2438d3 1101 {
switches 0:5c4d7b2438d3 1102 #if 1
switches 0:5c4d7b2438d3 1103 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
switches 0:5c4d7b2438d3 1104 #else
switches 0:5c4d7b2438d3 1105 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
switches 0:5c4d7b2438d3 1106 __regCPACR = cpacr;
switches 0:5c4d7b2438d3 1107 #endif
switches 0:5c4d7b2438d3 1108 __ISB();
switches 0:5c4d7b2438d3 1109 }
switches 0:5c4d7b2438d3 1110
switches 0:5c4d7b2438d3 1111 /** \brief Get CBAR
switches 0:5c4d7b2438d3 1112
switches 0:5c4d7b2438d3 1113 This function returns the value of the Configuration Base Address register.
switches 0:5c4d7b2438d3 1114
switches 0:5c4d7b2438d3 1115 \return Configuration Base Address register value
switches 0:5c4d7b2438d3 1116 */
switches 0:5c4d7b2438d3 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
switches 0:5c4d7b2438d3 1118 #if 1
switches 0:5c4d7b2438d3 1119 register uint32_t __regCBAR;
switches 0:5c4d7b2438d3 1120 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
switches 0:5c4d7b2438d3 1121 #else
switches 0:5c4d7b2438d3 1122 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
switches 0:5c4d7b2438d3 1123 #endif
switches 0:5c4d7b2438d3 1124 return(__regCBAR);
switches 0:5c4d7b2438d3 1125 }
switches 0:5c4d7b2438d3 1126
switches 0:5c4d7b2438d3 1127 /** \brief Get TTBR0
switches 0:5c4d7b2438d3 1128
switches 0:5c4d7b2438d3 1129 This function returns the value of the Translation Table Base Register 0.
switches 0:5c4d7b2438d3 1130
switches 0:5c4d7b2438d3 1131 \return Translation Table Base Register 0 value
switches 0:5c4d7b2438d3 1132 */
switches 0:5c4d7b2438d3 1133 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
switches 0:5c4d7b2438d3 1134 #if 1
switches 0:5c4d7b2438d3 1135 register uint32_t __regTTBR0;
switches 0:5c4d7b2438d3 1136 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
switches 0:5c4d7b2438d3 1137 #else
switches 0:5c4d7b2438d3 1138 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
switches 0:5c4d7b2438d3 1139 #endif
switches 0:5c4d7b2438d3 1140 return(__regTTBR0);
switches 0:5c4d7b2438d3 1141 }
switches 0:5c4d7b2438d3 1142
switches 0:5c4d7b2438d3 1143 /** \brief Set TTBR0
switches 0:5c4d7b2438d3 1144
switches 0:5c4d7b2438d3 1145 This function assigns the given value to the Translation Table Base Register 0.
switches 0:5c4d7b2438d3 1146
switches 0:5c4d7b2438d3 1147 \param [in] ttbr0 Translation Table Base Register 0 value to set
switches 0:5c4d7b2438d3 1148 */
switches 0:5c4d7b2438d3 1149 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
switches 0:5c4d7b2438d3 1150 #if 1
switches 0:5c4d7b2438d3 1151 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
switches 0:5c4d7b2438d3 1152 #else
switches 0:5c4d7b2438d3 1153 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
switches 0:5c4d7b2438d3 1154 __regTTBR0 = ttbr0;
switches 0:5c4d7b2438d3 1155 #endif
switches 0:5c4d7b2438d3 1156 __ISB();
switches 0:5c4d7b2438d3 1157 }
switches 0:5c4d7b2438d3 1158
switches 0:5c4d7b2438d3 1159 /** \brief Get DACR
switches 0:5c4d7b2438d3 1160
switches 0:5c4d7b2438d3 1161 This function returns the value of the Domain Access Control Register.
switches 0:5c4d7b2438d3 1162
switches 0:5c4d7b2438d3 1163 \return Domain Access Control Register value
switches 0:5c4d7b2438d3 1164 */
switches 0:5c4d7b2438d3 1165 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
switches 0:5c4d7b2438d3 1166 #if 1
switches 0:5c4d7b2438d3 1167 register uint32_t __regDACR;
switches 0:5c4d7b2438d3 1168 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
switches 0:5c4d7b2438d3 1169 #else
switches 0:5c4d7b2438d3 1170 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
switches 0:5c4d7b2438d3 1171 #endif
switches 0:5c4d7b2438d3 1172 return(__regDACR);
switches 0:5c4d7b2438d3 1173 }
switches 0:5c4d7b2438d3 1174
switches 0:5c4d7b2438d3 1175 /** \brief Set DACR
switches 0:5c4d7b2438d3 1176
switches 0:5c4d7b2438d3 1177 This function assigns the given value to the Domain Access Control Register.
switches 0:5c4d7b2438d3 1178
switches 0:5c4d7b2438d3 1179 \param [in] dacr Domain Access Control Register value to set
switches 0:5c4d7b2438d3 1180 */
switches 0:5c4d7b2438d3 1181 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
switches 0:5c4d7b2438d3 1182 #if 1
switches 0:5c4d7b2438d3 1183 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
switches 0:5c4d7b2438d3 1184 #else
switches 0:5c4d7b2438d3 1185 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
switches 0:5c4d7b2438d3 1186 __regDACR = dacr;
switches 0:5c4d7b2438d3 1187 #endif
switches 0:5c4d7b2438d3 1188 __ISB();
switches 0:5c4d7b2438d3 1189 }
switches 0:5c4d7b2438d3 1190
switches 0:5c4d7b2438d3 1191 /******************************** Cache and BTAC enable ****************************************************/
switches 0:5c4d7b2438d3 1192
switches 0:5c4d7b2438d3 1193 /** \brief Set SCTLR
switches 0:5c4d7b2438d3 1194
switches 0:5c4d7b2438d3 1195 This function assigns the given value to the System Control Register.
switches 0:5c4d7b2438d3 1196
switches 0:5c4d7b2438d3 1197 \param [in] sctlr System Control Register value to set
switches 0:5c4d7b2438d3 1198 */
switches 0:5c4d7b2438d3 1199 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
switches 0:5c4d7b2438d3 1200 {
switches 0:5c4d7b2438d3 1201 #if 1
switches 0:5c4d7b2438d3 1202 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
switches 0:5c4d7b2438d3 1203 #else
switches 0:5c4d7b2438d3 1204 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
switches 0:5c4d7b2438d3 1205 __regSCTLR = sctlr;
switches 0:5c4d7b2438d3 1206 #endif
switches 0:5c4d7b2438d3 1207 }
switches 0:5c4d7b2438d3 1208
switches 0:5c4d7b2438d3 1209 /** \brief Get SCTLR
switches 0:5c4d7b2438d3 1210
switches 0:5c4d7b2438d3 1211 This function returns the value of the System Control Register.
switches 0:5c4d7b2438d3 1212
switches 0:5c4d7b2438d3 1213 \return System Control Register value
switches 0:5c4d7b2438d3 1214 */
switches 0:5c4d7b2438d3 1215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
switches 0:5c4d7b2438d3 1216 #if 1
switches 0:5c4d7b2438d3 1217 register uint32_t __regSCTLR;
switches 0:5c4d7b2438d3 1218 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
switches 0:5c4d7b2438d3 1219 #else
switches 0:5c4d7b2438d3 1220 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
switches 0:5c4d7b2438d3 1221 #endif
switches 0:5c4d7b2438d3 1222 return(__regSCTLR);
switches 0:5c4d7b2438d3 1223 }
switches 0:5c4d7b2438d3 1224
switches 0:5c4d7b2438d3 1225 /** \brief Enable Caches
switches 0:5c4d7b2438d3 1226
switches 0:5c4d7b2438d3 1227 Enable Caches
switches 0:5c4d7b2438d3 1228 */
switches 0:5c4d7b2438d3 1229 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
switches 0:5c4d7b2438d3 1230 // Set I bit 12 to enable I Cache
switches 0:5c4d7b2438d3 1231 // Set C bit 2 to enable D Cache
switches 0:5c4d7b2438d3 1232 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
switches 0:5c4d7b2438d3 1233 }
switches 0:5c4d7b2438d3 1234
switches 0:5c4d7b2438d3 1235 /** \brief Disable Caches
switches 0:5c4d7b2438d3 1236
switches 0:5c4d7b2438d3 1237 Disable Caches
switches 0:5c4d7b2438d3 1238 */
switches 0:5c4d7b2438d3 1239 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
switches 0:5c4d7b2438d3 1240 // Clear I bit 12 to disable I Cache
switches 0:5c4d7b2438d3 1241 // Clear C bit 2 to disable D Cache
switches 0:5c4d7b2438d3 1242 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
switches 0:5c4d7b2438d3 1243 __ISB();
switches 0:5c4d7b2438d3 1244 }
switches 0:5c4d7b2438d3 1245
switches 0:5c4d7b2438d3 1246 /** \brief Enable BTAC
switches 0:5c4d7b2438d3 1247
switches 0:5c4d7b2438d3 1248 Enable BTAC
switches 0:5c4d7b2438d3 1249 */
switches 0:5c4d7b2438d3 1250 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
switches 0:5c4d7b2438d3 1251 // Set Z bit 11 to enable branch prediction
switches 0:5c4d7b2438d3 1252 __set_SCTLR( __get_SCTLR() | (1 << 11));
switches 0:5c4d7b2438d3 1253 __ISB();
switches 0:5c4d7b2438d3 1254 }
switches 0:5c4d7b2438d3 1255
switches 0:5c4d7b2438d3 1256 /** \brief Disable BTAC
switches 0:5c4d7b2438d3 1257
switches 0:5c4d7b2438d3 1258 Disable BTAC
switches 0:5c4d7b2438d3 1259 */
switches 0:5c4d7b2438d3 1260 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
switches 0:5c4d7b2438d3 1261 // Clear Z bit 11 to disable branch prediction
switches 0:5c4d7b2438d3 1262 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
switches 0:5c4d7b2438d3 1263 }
switches 0:5c4d7b2438d3 1264
switches 0:5c4d7b2438d3 1265
switches 0:5c4d7b2438d3 1266 /** \brief Enable MMU
switches 0:5c4d7b2438d3 1267
switches 0:5c4d7b2438d3 1268 Enable MMU
switches 0:5c4d7b2438d3 1269 */
switches 0:5c4d7b2438d3 1270 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
switches 0:5c4d7b2438d3 1271 // Set M bit 0 to enable the MMU
switches 0:5c4d7b2438d3 1272 // Set AFE bit to enable simplified access permissions model
switches 0:5c4d7b2438d3 1273 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
switches 0:5c4d7b2438d3 1274 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
switches 0:5c4d7b2438d3 1275 __ISB();
switches 0:5c4d7b2438d3 1276 }
switches 0:5c4d7b2438d3 1277
switches 0:5c4d7b2438d3 1278 /** \brief Disable MMU
switches 0:5c4d7b2438d3 1279
switches 0:5c4d7b2438d3 1280 Disable MMU
switches 0:5c4d7b2438d3 1281 */
switches 0:5c4d7b2438d3 1282 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
switches 0:5c4d7b2438d3 1283 // Clear M bit 0 to disable the MMU
switches 0:5c4d7b2438d3 1284 __set_SCTLR( __get_SCTLR() & ~1);
switches 0:5c4d7b2438d3 1285 __ISB();
switches 0:5c4d7b2438d3 1286 }
switches 0:5c4d7b2438d3 1287
switches 0:5c4d7b2438d3 1288 /******************************** TLB maintenance operations ************************************************/
switches 0:5c4d7b2438d3 1289 /** \brief Invalidate the whole tlb
switches 0:5c4d7b2438d3 1290
switches 0:5c4d7b2438d3 1291 TLBIALL. Invalidate the whole tlb
switches 0:5c4d7b2438d3 1292 */
switches 0:5c4d7b2438d3 1293
switches 0:5c4d7b2438d3 1294 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
switches 0:5c4d7b2438d3 1295 #if 1
switches 0:5c4d7b2438d3 1296 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
switches 0:5c4d7b2438d3 1297 #else
switches 0:5c4d7b2438d3 1298 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
switches 0:5c4d7b2438d3 1299 __TLBIALL = 0;
switches 0:5c4d7b2438d3 1300 #endif
switches 0:5c4d7b2438d3 1301 __DSB();
switches 0:5c4d7b2438d3 1302 __ISB();
switches 0:5c4d7b2438d3 1303 }
switches 0:5c4d7b2438d3 1304
switches 0:5c4d7b2438d3 1305 /******************************** BTB maintenance operations ************************************************/
switches 0:5c4d7b2438d3 1306 /** \brief Invalidate entire branch predictor array
switches 0:5c4d7b2438d3 1307
switches 0:5c4d7b2438d3 1308 BPIALL. Branch Predictor Invalidate All.
switches 0:5c4d7b2438d3 1309 */
switches 0:5c4d7b2438d3 1310
switches 0:5c4d7b2438d3 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
switches 0:5c4d7b2438d3 1312 #if 1
switches 0:5c4d7b2438d3 1313 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
switches 0:5c4d7b2438d3 1314 #else
switches 0:5c4d7b2438d3 1315 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
switches 0:5c4d7b2438d3 1316 __BPIALL = 0;
switches 0:5c4d7b2438d3 1317 #endif
switches 0:5c4d7b2438d3 1318 __DSB(); //ensure completion of the invalidation
switches 0:5c4d7b2438d3 1319 __ISB(); //ensure instruction fetch path sees new state
switches 0:5c4d7b2438d3 1320 }
switches 0:5c4d7b2438d3 1321
switches 0:5c4d7b2438d3 1322
switches 0:5c4d7b2438d3 1323 /******************************** L1 cache operations ******************************************************/
switches 0:5c4d7b2438d3 1324
switches 0:5c4d7b2438d3 1325 /** \brief Invalidate the whole I$
switches 0:5c4d7b2438d3 1326
switches 0:5c4d7b2438d3 1327 ICIALLU. Instruction Cache Invalidate All to PoU
switches 0:5c4d7b2438d3 1328 */
switches 0:5c4d7b2438d3 1329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
switches 0:5c4d7b2438d3 1330 #if 1
switches 0:5c4d7b2438d3 1331 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
switches 0:5c4d7b2438d3 1332 #else
switches 0:5c4d7b2438d3 1333 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
switches 0:5c4d7b2438d3 1334 __ICIALLU = 0;
switches 0:5c4d7b2438d3 1335 #endif
switches 0:5c4d7b2438d3 1336 __DSB(); //ensure completion of the invalidation
switches 0:5c4d7b2438d3 1337 __ISB(); //ensure instruction fetch path sees new I cache state
switches 0:5c4d7b2438d3 1338 }
switches 0:5c4d7b2438d3 1339
switches 0:5c4d7b2438d3 1340 /** \brief Clean D$ by MVA
switches 0:5c4d7b2438d3 1341
switches 0:5c4d7b2438d3 1342 DCCMVAC. Data cache clean by MVA to PoC
switches 0:5c4d7b2438d3 1343 */
switches 0:5c4d7b2438d3 1344 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
switches 0:5c4d7b2438d3 1345 #if 1
switches 0:5c4d7b2438d3 1346 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
switches 0:5c4d7b2438d3 1347 #else
switches 0:5c4d7b2438d3 1348 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
switches 0:5c4d7b2438d3 1349 __DCCMVAC = (uint32_t)va;
switches 0:5c4d7b2438d3 1350 #endif
switches 0:5c4d7b2438d3 1351 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
switches 0:5c4d7b2438d3 1352 }
switches 0:5c4d7b2438d3 1353
switches 0:5c4d7b2438d3 1354 /** \brief Invalidate D$ by MVA
switches 0:5c4d7b2438d3 1355
switches 0:5c4d7b2438d3 1356 DCIMVAC. Data cache invalidate by MVA to PoC
switches 0:5c4d7b2438d3 1357 */
switches 0:5c4d7b2438d3 1358 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
switches 0:5c4d7b2438d3 1359 #if 1
switches 0:5c4d7b2438d3 1360 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
switches 0:5c4d7b2438d3 1361 #else
switches 0:5c4d7b2438d3 1362 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
switches 0:5c4d7b2438d3 1363 __DCIMVAC = (uint32_t)va;
switches 0:5c4d7b2438d3 1364 #endif
switches 0:5c4d7b2438d3 1365 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
switches 0:5c4d7b2438d3 1366 }
switches 0:5c4d7b2438d3 1367
switches 0:5c4d7b2438d3 1368 /** \brief Clean and Invalidate D$ by MVA
switches 0:5c4d7b2438d3 1369
switches 0:5c4d7b2438d3 1370 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
switches 0:5c4d7b2438d3 1371 */
switches 0:5c4d7b2438d3 1372 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
switches 0:5c4d7b2438d3 1373 #if 1
switches 0:5c4d7b2438d3 1374 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
switches 0:5c4d7b2438d3 1375 #else
switches 0:5c4d7b2438d3 1376 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
switches 0:5c4d7b2438d3 1377 __DCCIMVAC = (uint32_t)va;
switches 0:5c4d7b2438d3 1378 #endif
switches 0:5c4d7b2438d3 1379 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
switches 0:5c4d7b2438d3 1380 }
switches 0:5c4d7b2438d3 1381
switches 0:5c4d7b2438d3 1382 /** \brief Clean and Invalidate the entire data or unified cache
switches 0:5c4d7b2438d3 1383
switches 0:5c4d7b2438d3 1384 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
switches 0:5c4d7b2438d3 1385 */
switches 0:5c4d7b2438d3 1386 extern void __v7_all_cache(uint32_t op);
switches 0:5c4d7b2438d3 1387
switches 0:5c4d7b2438d3 1388
switches 0:5c4d7b2438d3 1389 /** \brief Invalidate the whole D$
switches 0:5c4d7b2438d3 1390
switches 0:5c4d7b2438d3 1391 DCISW. Invalidate by Set/Way
switches 0:5c4d7b2438d3 1392 */
switches 0:5c4d7b2438d3 1393
switches 0:5c4d7b2438d3 1394 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
switches 0:5c4d7b2438d3 1395 __v7_all_cache(0);
switches 0:5c4d7b2438d3 1396 }
switches 0:5c4d7b2438d3 1397
switches 0:5c4d7b2438d3 1398 /** \brief Clean the whole D$
switches 0:5c4d7b2438d3 1399
switches 0:5c4d7b2438d3 1400 DCCSW. Clean by Set/Way
switches 0:5c4d7b2438d3 1401 */
switches 0:5c4d7b2438d3 1402
switches 0:5c4d7b2438d3 1403 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
switches 0:5c4d7b2438d3 1404 __v7_all_cache(1);
switches 0:5c4d7b2438d3 1405 }
switches 0:5c4d7b2438d3 1406
switches 0:5c4d7b2438d3 1407 /** \brief Clean and invalidate the whole D$
switches 0:5c4d7b2438d3 1408
switches 0:5c4d7b2438d3 1409 DCCISW. Clean and Invalidate by Set/Way
switches 0:5c4d7b2438d3 1410 */
switches 0:5c4d7b2438d3 1411
switches 0:5c4d7b2438d3 1412 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
switches 0:5c4d7b2438d3 1413 __v7_all_cache(2);
switches 0:5c4d7b2438d3 1414 }
switches 0:5c4d7b2438d3 1415
switches 0:5c4d7b2438d3 1416 #include "core_ca_mmu.h"
switches 0:5c4d7b2438d3 1417
switches 0:5c4d7b2438d3 1418 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
switches 0:5c4d7b2438d3 1419
switches 0:5c4d7b2438d3 1420 #error TASKING Compiler support not implemented for Cortex-A
switches 0:5c4d7b2438d3 1421
switches 0:5c4d7b2438d3 1422 #endif
switches 0:5c4d7b2438d3 1423
switches 0:5c4d7b2438d3 1424 /*@} end of CMSIS_Core_RegAccFunctions */
switches 0:5c4d7b2438d3 1425
switches 0:5c4d7b2438d3 1426
switches 0:5c4d7b2438d3 1427 #endif /* __CORE_CAFUNC_H__ */