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targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /*
bogdanm 0:9b334a45a8ff 2 ** ###################################################################
bogdanm 0:9b334a45a8ff 3 ** Compilers: ARM Compiler
bogdanm 0:9b334a45a8ff 4 ** Freescale C/C++ for Embedded ARM
bogdanm 0:9b334a45a8ff 5 ** GNU C Compiler
bogdanm 0:9b334a45a8ff 6 ** IAR ANSI C/C++ Compiler for ARM
bogdanm 0:9b334a45a8ff 7 **
bogdanm 0:9b334a45a8ff 8 ** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011
bogdanm 0:9b334a45a8ff 9 ** K20P32M50SF0RM Rev. 1, Oct 2011
bogdanm 0:9b334a45a8ff 10 ** K20P48M50SF0RM Rev. 1, Oct 2011
bogdanm 0:9b334a45a8ff 11 **
bogdanm 0:9b334a45a8ff 12 ** Version: rev. 1.0, 2011-12-15
bogdanm 0:9b334a45a8ff 13 **
bogdanm 0:9b334a45a8ff 14 ** Abstract:
bogdanm 0:9b334a45a8ff 15 ** Provides a system configuration function and a global variable that
bogdanm 0:9b334a45a8ff 16 ** contains the system frequency. It configures the device and initializes
bogdanm 0:9b334a45a8ff 17 ** the oscillator (PLL) that is part of the microcontroller device.
bogdanm 0:9b334a45a8ff 18 **
bogdanm 0:9b334a45a8ff 19 ** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved.
bogdanm 0:9b334a45a8ff 20 **
bogdanm 0:9b334a45a8ff 21 ** http: www.freescale.com
bogdanm 0:9b334a45a8ff 22 ** mail: support@freescale.com
bogdanm 0:9b334a45a8ff 23 **
bogdanm 0:9b334a45a8ff 24 ** Revisions:
bogdanm 0:9b334a45a8ff 25 ** - rev. 1.0 (2011-12-15)
bogdanm 0:9b334a45a8ff 26 ** Initial version
bogdanm 0:9b334a45a8ff 27 **
bogdanm 0:9b334a45a8ff 28 ** ###################################################################
bogdanm 0:9b334a45a8ff 29 */
bogdanm 0:9b334a45a8ff 30
bogdanm 0:9b334a45a8ff 31 /**
bogdanm 0:9b334a45a8ff 32 * @file MK20D5
bogdanm 0:9b334a45a8ff 33 * @version 1.0
bogdanm 0:9b334a45a8ff 34 * @date 2011-12-15
bogdanm 0:9b334a45a8ff 35 * @brief Device specific configuration file for MK20D5 (implementation file)
bogdanm 0:9b334a45a8ff 36 *
bogdanm 0:9b334a45a8ff 37 * Provides a system configuration function and a global variable that contains
bogdanm 0:9b334a45a8ff 38 * the system frequency. It configures the device and initializes the oscillator
bogdanm 0:9b334a45a8ff 39 * (PLL) that is part of the microcontroller device.
bogdanm 0:9b334a45a8ff 40 */
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 #include <stdint.h>
bogdanm 0:9b334a45a8ff 43 #include "MK20D5.h"
bogdanm 0:9b334a45a8ff 44
bogdanm 0:9b334a45a8ff 45 #define DISABLE_WDOG 1
bogdanm 0:9b334a45a8ff 46
bogdanm 0:9b334a45a8ff 47 #define CLOCK_SETUP 1
bogdanm 0:9b334a45a8ff 48 /* Predefined clock setups
bogdanm 0:9b334a45a8ff 49 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
bogdanm 0:9b334a45a8ff 50 Reference clock source for MCG module is the slow internal clock source 32.768kHz
bogdanm 0:9b334a45a8ff 51 Core clock = 41.94MHz, BusClock = 41.94MHz
bogdanm 0:9b334a45a8ff 52 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
bogdanm 0:9b334a45a8ff 53 Reference clock source for MCG module is an external crystal 8MHz
bogdanm 0:9b334a45a8ff 54 Core clock = 48MHz, BusClock = 48MHz
bogdanm 0:9b334a45a8ff 55 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
bogdanm 0:9b334a45a8ff 56 Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
bogdanm 0:9b334a45a8ff 57 Core clock = 8MHz, BusClock = 8MHz
bogdanm 0:9b334a45a8ff 58 */
bogdanm 0:9b334a45a8ff 59
bogdanm 0:9b334a45a8ff 60 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 61 Define clock source values
bogdanm 0:9b334a45a8ff 62 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 63 #if (CLOCK_SETUP == 0)
bogdanm 0:9b334a45a8ff 64 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 65 #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 66 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 67 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 68 #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
bogdanm 0:9b334a45a8ff 69 #elif (CLOCK_SETUP == 1)
bogdanm 0:9b334a45a8ff 70 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 71 #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 72 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 73 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 74 #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
bogdanm 0:9b334a45a8ff 75 #elif (CLOCK_SETUP == 2)
bogdanm 0:9b334a45a8ff 76 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 77 #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 78 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 79 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 80 #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
bogdanm 0:9b334a45a8ff 81 #endif /* (CLOCK_SETUP == 2) */
bogdanm 0:9b334a45a8ff 82
bogdanm 0:9b334a45a8ff 83
bogdanm 0:9b334a45a8ff 84 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 85 -- Core clock
bogdanm 0:9b334a45a8ff 86 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 87
bogdanm 0:9b334a45a8ff 88 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 91 -- SystemInit()
bogdanm 0:9b334a45a8ff 92 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 93
bogdanm 0:9b334a45a8ff 94 void SystemInit (void) {
bogdanm 0:9b334a45a8ff 95 #if (DISABLE_WDOG)
bogdanm 0:9b334a45a8ff 96 /* Disable the WDOG module */
bogdanm 0:9b334a45a8ff 97 /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
bogdanm 0:9b334a45a8ff 98 WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */
bogdanm 0:9b334a45a8ff 99 /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
bogdanm 0:9b334a45a8ff 100 WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */
bogdanm 0:9b334a45a8ff 101 /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
bogdanm 0:9b334a45a8ff 102 WDOG->STCTRLH = (uint16_t)0x01D2u;
bogdanm 0:9b334a45a8ff 103 #endif /* (DISABLE_WDOG) */
bogdanm 0:9b334a45a8ff 104 #if (CLOCK_SETUP == 0)
bogdanm 0:9b334a45a8ff 105 /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
bogdanm 0:9b334a45a8ff 106 SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
bogdanm 0:9b334a45a8ff 107 /* Switch to FEI Mode */
bogdanm 0:9b334a45a8ff 108 /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
bogdanm 0:9b334a45a8ff 109 MCG->C1 = (uint8_t)0x06u;
bogdanm 0:9b334a45a8ff 110 /* MCG->C2: ??=0,??=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */
bogdanm 0:9b334a45a8ff 111 MCG->C2 = (uint8_t)0x00u;
bogdanm 0:9b334a45a8ff 112 /* MCG_C4: DMX32=0,DRST_DRS=1 */
bogdanm 0:9b334a45a8ff 113 MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u);
bogdanm 0:9b334a45a8ff 114 /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
bogdanm 0:9b334a45a8ff 115 MCG->C5 = (uint8_t)0x00u;
bogdanm 0:9b334a45a8ff 116 /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
bogdanm 0:9b334a45a8ff 117 MCG->C6 = (uint8_t)0x00u;
bogdanm 0:9b334a45a8ff 118 while((MCG->S & MCG_S_IREFST_MASK) == 0u) { /* Check that the source of the FLL reference clock is the internal reference clock. */
bogdanm 0:9b334a45a8ff 119 }
bogdanm 0:9b334a45a8ff 120 while((MCG->S & 0x0Cu) != 0x00u) { /* Wait until output of the FLL is selected */
bogdanm 0:9b334a45a8ff 121 }
bogdanm 0:9b334a45a8ff 122 #elif (CLOCK_SETUP == 1)
bogdanm 0:9b334a45a8ff 123 /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
bogdanm 0:9b334a45a8ff 124 SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
bogdanm 0:9b334a45a8ff 125 /* Switch to FBE Mode */
bogdanm 0:9b334a45a8ff 126 /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
bogdanm 0:9b334a45a8ff 127 OSC0->CR = (uint8_t)0x00u;
bogdanm 0:9b334a45a8ff 128 /* MCG->C7: OSCSEL=0 */
bogdanm 0:9b334a45a8ff 129 MCG->C7 = (uint8_t)0x00u;
bogdanm 0:9b334a45a8ff 130 /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
bogdanm 0:9b334a45a8ff 131 MCG->C2 = (uint8_t)0x24u;
bogdanm 0:9b334a45a8ff 132 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
bogdanm 0:9b334a45a8ff 133 MCG->C1 = (uint8_t)0x9Au;
bogdanm 0:9b334a45a8ff 134 /* MCG->C4: DMX32=0,DRST_DRS=0 */
bogdanm 0:9b334a45a8ff 135 MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
bogdanm 0:9b334a45a8ff 136 /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
bogdanm 0:9b334a45a8ff 137 MCG->C5 = (uint8_t)0x03u;
bogdanm 0:9b334a45a8ff 138 /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
bogdanm 0:9b334a45a8ff 139 MCG->C6 = (uint8_t)0x00u;
bogdanm 0:9b334a45a8ff 140 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */
bogdanm 0:9b334a45a8ff 141 }
bogdanm 0:9b334a45a8ff 142 #if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */
bogdanm 0:9b334a45a8ff 143 while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
bogdanm 0:9b334a45a8ff 144 }
bogdanm 0:9b334a45a8ff 145 #endif
bogdanm 0:9b334a45a8ff 146 while((MCG->S & 0x0Cu) != 0x08u) { /* Wait until external reference clock is selected as MCG output */
bogdanm 0:9b334a45a8ff 147 }
bogdanm 0:9b334a45a8ff 148 /* Switch to PBE Mode */
bogdanm 0:9b334a45a8ff 149 /* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
bogdanm 0:9b334a45a8ff 150 MCG->C5 = (uint8_t)0x03u;
bogdanm 0:9b334a45a8ff 151 /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */
bogdanm 0:9b334a45a8ff 152 MCG->C6 = (uint8_t)0x40u;
bogdanm 0:9b334a45a8ff 153 while((MCG->S & MCG_S_PLLST_MASK) == 0u) { /* Wait until the source of the PLLS clock has switched to the PLL */
bogdanm 0:9b334a45a8ff 154 }
bogdanm 0:9b334a45a8ff 155 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
bogdanm 0:9b334a45a8ff 156 }
bogdanm 0:9b334a45a8ff 157 /* Switch to PEE Mode */
bogdanm 0:9b334a45a8ff 158 /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
bogdanm 0:9b334a45a8ff 159 MCG->C1 = (uint8_t)0x1Au;
bogdanm 0:9b334a45a8ff 160 while((MCG->S & 0x0Cu) != 0x0Cu) { /* Wait until output of the PLL is selected */
bogdanm 0:9b334a45a8ff 161 }
bogdanm 0:9b334a45a8ff 162 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
bogdanm 0:9b334a45a8ff 163 }
bogdanm 0:9b334a45a8ff 164 #elif (CLOCK_SETUP == 2)
bogdanm 0:9b334a45a8ff 165 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
bogdanm 0:9b334a45a8ff 166 SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
bogdanm 0:9b334a45a8ff 167 /* Switch to FBE Mode */
bogdanm 0:9b334a45a8ff 168 /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
bogdanm 0:9b334a45a8ff 169 OSC0->CR = (uint8_t)0x00u;
bogdanm 0:9b334a45a8ff 170 /* MCG->C7: OSCSEL=0 */
bogdanm 0:9b334a45a8ff 171 MCG->C7 = (uint8_t)0x00u;
bogdanm 0:9b334a45a8ff 172 /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
bogdanm 0:9b334a45a8ff 173 MCG->C2 = (uint8_t)0x24u;
bogdanm 0:9b334a45a8ff 174 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
bogdanm 0:9b334a45a8ff 175 MCG->C1 = (uint8_t)0x9Au;
bogdanm 0:9b334a45a8ff 176 /* MCG->C4: DMX32=0,DRST_DRS=0 */
bogdanm 0:9b334a45a8ff 177 MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
bogdanm 0:9b334a45a8ff 178 /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
bogdanm 0:9b334a45a8ff 179 MCG->C5 = (uint8_t)0x00u;
bogdanm 0:9b334a45a8ff 180 /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
bogdanm 0:9b334a45a8ff 181 MCG->C6 = (uint8_t)0x00u;
bogdanm 0:9b334a45a8ff 182 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */
bogdanm 0:9b334a45a8ff 183 }
bogdanm 0:9b334a45a8ff 184 #if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */
bogdanm 0:9b334a45a8ff 185 while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
bogdanm 0:9b334a45a8ff 186 }
bogdanm 0:9b334a45a8ff 187 #endif
bogdanm 0:9b334a45a8ff 188 while((MCG->S & 0x0CU) != 0x08u) { /* Wait until external reference clock is selected as MCG output */
bogdanm 0:9b334a45a8ff 189 }
bogdanm 0:9b334a45a8ff 190 /* Switch to BLPE Mode */
bogdanm 0:9b334a45a8ff 191 /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
bogdanm 0:9b334a45a8ff 192 MCG->C2 = (uint8_t)0x24u;
bogdanm 0:9b334a45a8ff 193 #endif /* (CLOCK_SETUP == 2) */
bogdanm 0:9b334a45a8ff 194 }
bogdanm 0:9b334a45a8ff 195
bogdanm 0:9b334a45a8ff 196 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 197 -- SystemCoreClockUpdate()
bogdanm 0:9b334a45a8ff 198 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 199
bogdanm 0:9b334a45a8ff 200 void SystemCoreClockUpdate (void) {
bogdanm 0:9b334a45a8ff 201 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
bogdanm 0:9b334a45a8ff 202 uint8_t Divider;
bogdanm 0:9b334a45a8ff 203
bogdanm 0:9b334a45a8ff 204 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
bogdanm 0:9b334a45a8ff 205 /* Output of FLL or PLL is selected */
bogdanm 0:9b334a45a8ff 206 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
bogdanm 0:9b334a45a8ff 207 /* FLL is selected */
bogdanm 0:9b334a45a8ff 208 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
bogdanm 0:9b334a45a8ff 209 /* External reference clock is selected */
bogdanm 0:9b334a45a8ff 210 if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
bogdanm 0:9b334a45a8ff 211 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
bogdanm 0:9b334a45a8ff 212 } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
bogdanm 0:9b334a45a8ff 213 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
bogdanm 0:9b334a45a8ff 214 } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
bogdanm 0:9b334a45a8ff 215 Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
bogdanm 0:9b334a45a8ff 216 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
bogdanm 0:9b334a45a8ff 217 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
bogdanm 0:9b334a45a8ff 218 MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
bogdanm 0:9b334a45a8ff 219 } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
bogdanm 0:9b334a45a8ff 220 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
bogdanm 0:9b334a45a8ff 221 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
bogdanm 0:9b334a45a8ff 222 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
bogdanm 0:9b334a45a8ff 223 /* Select correct multiplier to calculate the MCG output clock */
bogdanm 0:9b334a45a8ff 224 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
bogdanm 0:9b334a45a8ff 225 case 0x0u:
bogdanm 0:9b334a45a8ff 226 MCGOUTClock *= 640u;
bogdanm 0:9b334a45a8ff 227 break;
bogdanm 0:9b334a45a8ff 228 case 0x20u:
bogdanm 0:9b334a45a8ff 229 MCGOUTClock *= 1280u;
bogdanm 0:9b334a45a8ff 230 break;
bogdanm 0:9b334a45a8ff 231 case 0x40u:
bogdanm 0:9b334a45a8ff 232 MCGOUTClock *= 1920u;
bogdanm 0:9b334a45a8ff 233 break;
bogdanm 0:9b334a45a8ff 234 case 0x60u:
bogdanm 0:9b334a45a8ff 235 MCGOUTClock *= 2560u;
bogdanm 0:9b334a45a8ff 236 break;
bogdanm 0:9b334a45a8ff 237 case 0x80u:
bogdanm 0:9b334a45a8ff 238 MCGOUTClock *= 732u;
bogdanm 0:9b334a45a8ff 239 break;
bogdanm 0:9b334a45a8ff 240 case 0xA0u:
bogdanm 0:9b334a45a8ff 241 MCGOUTClock *= 1464u;
bogdanm 0:9b334a45a8ff 242 break;
bogdanm 0:9b334a45a8ff 243 case 0xC0u:
bogdanm 0:9b334a45a8ff 244 MCGOUTClock *= 2197u;
bogdanm 0:9b334a45a8ff 245 break;
bogdanm 0:9b334a45a8ff 246 case 0xE0u:
bogdanm 0:9b334a45a8ff 247 MCGOUTClock *= 2929u;
bogdanm 0:9b334a45a8ff 248 break;
bogdanm 0:9b334a45a8ff 249 default:
bogdanm 0:9b334a45a8ff 250 break;
bogdanm 0:9b334a45a8ff 251 }
bogdanm 0:9b334a45a8ff 252 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
bogdanm 0:9b334a45a8ff 253 /* PLL is selected */
bogdanm 0:9b334a45a8ff 254 Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
bogdanm 0:9b334a45a8ff 255 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
bogdanm 0:9b334a45a8ff 256 Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
bogdanm 0:9b334a45a8ff 257 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
bogdanm 0:9b334a45a8ff 258 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
bogdanm 0:9b334a45a8ff 259 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
bogdanm 0:9b334a45a8ff 260 /* Internal reference clock is selected */
bogdanm 0:9b334a45a8ff 261 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
bogdanm 0:9b334a45a8ff 262 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
bogdanm 0:9b334a45a8ff 263 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
bogdanm 0:9b334a45a8ff 264 MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
bogdanm 0:9b334a45a8ff 265 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
bogdanm 0:9b334a45a8ff 266 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
bogdanm 0:9b334a45a8ff 267 /* External reference clock is selected */
bogdanm 0:9b334a45a8ff 268 if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
bogdanm 0:9b334a45a8ff 269 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
bogdanm 0:9b334a45a8ff 270 } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
bogdanm 0:9b334a45a8ff 271 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
bogdanm 0:9b334a45a8ff 272 } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
bogdanm 0:9b334a45a8ff 273 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
bogdanm 0:9b334a45a8ff 274 /* Reserved value */
bogdanm 0:9b334a45a8ff 275 return;
bogdanm 0:9b334a45a8ff 276 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
bogdanm 0:9b334a45a8ff 277 SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
bogdanm 0:9b334a45a8ff 278 }