Greg Steiert / maxim-dev

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targets/TARGET_Maxim/TARGET_MAX32620/device/pmu_regs.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /*******************************************************************************
<> 149:156823d33999 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 149:156823d33999 3 *
<> 149:156823d33999 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 149:156823d33999 5 * copy of this software and associated documentation files (the "Software"),
<> 149:156823d33999 6 * to deal in the Software without restriction, including without limitation
<> 149:156823d33999 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 149:156823d33999 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 149:156823d33999 9 * Software is furnished to do so, subject to the following conditions:
<> 149:156823d33999 10 *
<> 149:156823d33999 11 * The above copyright notice and this permission notice shall be included
<> 149:156823d33999 12 * in all copies or substantial portions of the Software.
<> 149:156823d33999 13 *
<> 149:156823d33999 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 149:156823d33999 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 149:156823d33999 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 149:156823d33999 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 149:156823d33999 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 149:156823d33999 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 149:156823d33999 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 149:156823d33999 21 *
<> 149:156823d33999 22 * Except as contained in this notice, the name of Maxim Integrated
<> 149:156823d33999 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 149:156823d33999 24 * Products, Inc. Branding Policy.
<> 149:156823d33999 25 *
<> 149:156823d33999 26 * The mere transfer of this software does not imply any licenses
<> 149:156823d33999 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 149:156823d33999 28 * trademarks, maskwork rights, or any other form of intellectual
<> 149:156823d33999 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 149:156823d33999 30 * ownership rights.
<> 149:156823d33999 31 *******************************************************************************
<> 149:156823d33999 32 */
<> 149:156823d33999 33
<> 149:156823d33999 34 #ifndef _MXC_PMU_REGS_H_
<> 149:156823d33999 35 #define _MXC_PMU_REGS_H_
<> 149:156823d33999 36
<> 149:156823d33999 37 #ifdef __cplusplus
<> 149:156823d33999 38 extern "C" {
<> 149:156823d33999 39 #endif
<> 149:156823d33999 40
<> 149:156823d33999 41 #include <stdint.h>
<> 149:156823d33999 42
<> 149:156823d33999 43 /*
<> 149:156823d33999 44 If types are not defined elsewhere (CMSIS) define them here
<> 149:156823d33999 45 */
<> 149:156823d33999 46 #ifndef __IO
<> 149:156823d33999 47 #define __IO volatile
<> 149:156823d33999 48 #endif
<> 149:156823d33999 49 #ifndef __I
<> 149:156823d33999 50 #define __I volatile const
<> 149:156823d33999 51 #endif
<> 149:156823d33999 52 #ifndef __O
<> 149:156823d33999 53 #define __O volatile
<> 149:156823d33999 54 #endif
<> 149:156823d33999 55
<> 149:156823d33999 56
<> 149:156823d33999 57 typedef struct {
<> 149:156823d33999 58 __IO uint32_t start_opcode[32];
<> 149:156823d33999 59 __IO uint32_t enable;
<> 149:156823d33999 60 __IO uint32_t rsvd0;
<> 149:156823d33999 61 __IO uint32_t ll_stopped;
<> 149:156823d33999 62 __IO uint32_t manual;
<> 149:156823d33999 63 __IO uint32_t bus_error;
<> 149:156823d33999 64 __IO uint32_t rsvd1;
<> 149:156823d33999 65 __IO uint32_t to_stat;
<> 149:156823d33999 66 __IO uint32_t rsvd2[4];
<> 149:156823d33999 67 __IO uint32_t to_sel[3];
<> 149:156823d33999 68 __IO uint32_t ps_sel[2];
<> 149:156823d33999 69 __IO uint32_t interrupt;
<> 149:156823d33999 70 __IO uint32_t int_enable;
<> 149:156823d33999 71 __IO uint32_t rsvd3[6];
<> 149:156823d33999 72 __IO uint32_t burst_size[5];
<> 149:156823d33999 73 __IO uint32_t rsvd4[3];
<> 149:156823d33999 74 __IO uint32_t padding[192]; /* Offset to next channel */
<> 149:156823d33999 75 } mxc_pmu_bits_t;
<> 149:156823d33999 76
<> 149:156823d33999 77
<> 149:156823d33999 78 /*
<> 149:156823d33999 79 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
<> 149:156823d33999 80 access to each register in module.
<> 149:156823d33999 81 */
<> 149:156823d33999 82
<> 149:156823d33999 83 /* Offset Register Description
<> 149:156823d33999 84 ============= ============================================================================ */
<> 149:156823d33999 85 typedef struct {
<> 149:156823d33999 86 __IO uint32_t dscadr; /* 0x0000 PMU Channel Next Descriptor Address */
<> 149:156823d33999 87 __IO uint32_t cfg; /* 0x0004 PMU Channel Configuration */
<> 149:156823d33999 88 __IO uint32_t loop; /* 0x0008 PMU Channel Loop Counters */
<> 149:156823d33999 89 __IO uint32_t op; /* 0x000C PMU Channel Current Descriptor DWORD 0 [INTERNAL TEST ONLY] */
<> 149:156823d33999 90 __IO uint32_t dsc1; /* 0x0010 PMU Channel Current Descriptor DWORD 1 [INTERNAL TEST ONLY] */
<> 149:156823d33999 91 __IO uint32_t dsc2; /* 0x0014 PMU Channel Current Descriptor DWORD 2 [INTERNAL TEST ONLY] */
<> 149:156823d33999 92 __IO uint32_t dsc3; /* 0x0018 PMU Channel Current Descriptor DWORD 3 [INTERNAL TEST ONLY] */
<> 149:156823d33999 93 __IO uint32_t dsc4; /* 0x001C PMU Channel Current Descriptor DWORD 4 [INTERNAL TEST ONLY] */
<> 149:156823d33999 94 } mxc_pmu_regs_t;
<> 149:156823d33999 95
<> 149:156823d33999 96
<> 149:156823d33999 97 /*
<> 149:156823d33999 98 Register offsets for module PMU.
<> 149:156823d33999 99 */
<> 149:156823d33999 100
<> 149:156823d33999 101 #define MXC_R_PMU_OFFS_DSCADR ((uint32_t)0x00000000UL)
<> 149:156823d33999 102 #define MXC_R_PMU_OFFS_CFG ((uint32_t)0x00000004UL)
<> 149:156823d33999 103 #define MXC_R_PMU_OFFS_LOOP ((uint32_t)0x00000008UL)
<> 149:156823d33999 104 #define MXC_R_PMU_OFFS_OP ((uint32_t)0x0000000CUL)
<> 149:156823d33999 105 #define MXC_R_PMU_OFFS_DSC1 ((uint32_t)0x00000010UL)
<> 149:156823d33999 106 #define MXC_R_PMU_OFFS_DSC2 ((uint32_t)0x00000014UL)
<> 149:156823d33999 107 #define MXC_R_PMU_OFFS_DSC3 ((uint32_t)0x00000018UL)
<> 149:156823d33999 108 #define MXC_R_PMU_OFFS_DSC4 ((uint32_t)0x0000001CUL)
<> 149:156823d33999 109
<> 149:156823d33999 110
<> 149:156823d33999 111 /*
<> 149:156823d33999 112 Field positions and masks for module PMU.
<> 149:156823d33999 113 */
<> 149:156823d33999 114
<> 149:156823d33999 115 #define MXC_F_PMU_CFG_ENABLE_POS 0
<> 149:156823d33999 116 #define MXC_F_PMU_CFG_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_ENABLE_POS))
<> 149:156823d33999 117 #define MXC_F_PMU_CFG_LL_STOPPED_POS 2
<> 149:156823d33999 118 #define MXC_F_PMU_CFG_LL_STOPPED ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_LL_STOPPED_POS))
<> 149:156823d33999 119 #define MXC_F_PMU_CFG_MANUAL_POS 3
<> 149:156823d33999 120 #define MXC_F_PMU_CFG_MANUAL ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_MANUAL_POS))
<> 149:156823d33999 121 #define MXC_F_PMU_CFG_BUS_ERROR_POS 4
<> 149:156823d33999 122 #define MXC_F_PMU_CFG_BUS_ERROR ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_BUS_ERROR_POS))
<> 149:156823d33999 123 #define MXC_F_PMU_CFG_TO_STAT_POS 6
<> 149:156823d33999 124 #define MXC_F_PMU_CFG_TO_STAT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_TO_STAT_POS))
<> 149:156823d33999 125 #define MXC_F_PMU_CFG_TO_SEL_POS 11
<> 149:156823d33999 126 #define MXC_F_PMU_CFG_TO_SEL ((uint32_t)(0x00000007UL << MXC_F_PMU_CFG_TO_SEL_POS))
<> 149:156823d33999 127 #define MXC_F_PMU_CFG_PS_SEL_POS 14
<> 149:156823d33999 128 #define MXC_F_PMU_CFG_PS_SEL ((uint32_t)(0x00000003UL << MXC_F_PMU_CFG_PS_SEL_POS))
<> 149:156823d33999 129 #define MXC_F_PMU_CFG_INTERRUPT_POS 16
<> 149:156823d33999 130 #define MXC_F_PMU_CFG_INTERRUPT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INTERRUPT_POS))
<> 149:156823d33999 131 #define MXC_F_PMU_CFG_INT_EN_POS 17
<> 149:156823d33999 132 #define MXC_F_PMU_CFG_INT_EN ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INT_EN_POS))
<> 149:156823d33999 133 #define MXC_F_PMU_CFG_BURST_SIZE_POS 24
<> 149:156823d33999 134 #define MXC_F_PMU_CFG_BURST_SIZE ((uint32_t)(0x0000001FUL << MXC_F_PMU_CFG_BURST_SIZE_POS))
<> 149:156823d33999 135
<> 149:156823d33999 136 #define MXC_F_PMU_LOOP_COUNTER_0_POS 0
<> 149:156823d33999 137 #define MXC_F_PMU_LOOP_COUNTER_0 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_0_POS))
<> 149:156823d33999 138 #define MXC_F_PMU_LOOP_COUNTER_1_POS 16
<> 149:156823d33999 139 #define MXC_F_PMU_LOOP_COUNTER_1 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_1_POS))
<> 149:156823d33999 140
<> 149:156823d33999 141
<> 149:156823d33999 142
<> 149:156823d33999 143 #ifdef __cplusplus
<> 149:156823d33999 144 }
<> 149:156823d33999 145 #endif
<> 149:156823d33999 146
<> 149:156823d33999 147 #endif /* _MXC_PMU_REGS_H_ */
<> 149:156823d33999 148