Greg Steiert / maxim-dev

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Dependents:   MAX34417_demo MAXREFDES1265 MAXREFDES1265

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targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_pwm.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file
<> 144:ef7eb2e8f9f7 4 * @author
<> 144:ef7eb2e8f9f7 5 * @version
<> 144:ef7eb2e8f9f7 6 * @date
<> 144:ef7eb2e8f9f7 7 * @brief This file contains all the functions prototypes for the UART
<> 144:ef7eb2e8f9f7 8 * firmware library.
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 ******************************************************************************
<> 144:ef7eb2e8f9f7 12 */
<> 144:ef7eb2e8f9f7 13
<> 144:ef7eb2e8f9f7 14 /* Includes -------------------------------------------*/
<> 144:ef7eb2e8f9f7 15 #include "W7500x.h"
<> 144:ef7eb2e8f9f7 16 #include "W7500x_pwm.h"
<> 144:ef7eb2e8f9f7 17
<> 144:ef7eb2e8f9f7 18 void PWM_DeInit(PWM_CHn_TypeDef* PWM_CHn)
<> 144:ef7eb2e8f9f7 19 {
<> 144:ef7eb2e8f9f7 20 if( PWM_CHn == PWM_CH0 )
<> 144:ef7eb2e8f9f7 21 {
<> 144:ef7eb2e8f9f7 22 PWM->IER &= PWM_IER_IE0_Disable; ///< Interrupt enable register
<> 144:ef7eb2e8f9f7 23 PWM->SSR &= PWM_SSR_SS0_Stop; ///< Start Stop register
<> 144:ef7eb2e8f9f7 24 PWM->PSR &= PWM_PSR_PS0_Restart; ///< Pause register
<> 144:ef7eb2e8f9f7 25 PWM_CH0->IER = 0; ///< Interrupt enable register
<> 144:ef7eb2e8f9f7 26 PWM_CH0->ICR = PWM_CHn_ICR_MatchInterruptClear |
<> 144:ef7eb2e8f9f7 27 PWM_CHn_ICR_OverflowInterruptClear |
<> 144:ef7eb2e8f9f7 28 PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
<> 144:ef7eb2e8f9f7 29 PWM_CH0->PR = 0; ///< Prescale register
<> 144:ef7eb2e8f9f7 30 PWM_CH0->MR = 0; ///< Match register
<> 144:ef7eb2e8f9f7 31 PWM_CH0->LR = 0xFFFFFFFF; ///< Limit register
<> 144:ef7eb2e8f9f7 32 PWM_CH0->UDMR = 0; ///< Up Dowm mode register
<> 144:ef7eb2e8f9f7 33 PWM_CH0->TCMR = 0; ///< Timer Counter mode register
<> 144:ef7eb2e8f9f7 34 PWM_CH0->PEEER = 0; ///< PWM output Enable and External input Enable register
<> 144:ef7eb2e8f9f7 35 PWM_CH0->CMR = 0; ///< Capture mode register
<> 144:ef7eb2e8f9f7 36 PWM_CH0->PDMR = 0; ///< Periodic Mode register
<> 144:ef7eb2e8f9f7 37 PWM_CH0->DZER = 0; ///< Dead Zone Enable register
<> 144:ef7eb2e8f9f7 38 PWM_CH0->DZCR = 0; ///< Dead Zone Counter register
<> 144:ef7eb2e8f9f7 39 }
<> 144:ef7eb2e8f9f7 40 else if( PWM_CHn == PWM_CH1 )
<> 144:ef7eb2e8f9f7 41 {
<> 144:ef7eb2e8f9f7 42 PWM->IER &= PWM_IER_IE1_Disable; ///< Reset Interrupt enable register
<> 144:ef7eb2e8f9f7 43 PWM->SSR &= PWM_SSR_SS1_Stop; ///< Reset Start Stop register
<> 144:ef7eb2e8f9f7 44 PWM->PSR &= PWM_PSR_PS1_Restart; ///< Reset Pause register
<> 144:ef7eb2e8f9f7 45 PWM_CH1->IER = 0; ///< Interrupt enable register
<> 144:ef7eb2e8f9f7 46 PWM_CH1->ICR = PWM_CHn_ICR_MatchInterruptClear |
<> 144:ef7eb2e8f9f7 47 PWM_CHn_ICR_OverflowInterruptClear |
<> 144:ef7eb2e8f9f7 48 PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
<> 144:ef7eb2e8f9f7 49 PWM_CH1->PR = 0; ///< Prescale register
<> 144:ef7eb2e8f9f7 50 PWM_CH1->MR = 0; ///< Match register
<> 144:ef7eb2e8f9f7 51 PWM_CH1->LR = 0xFFFFFFFF; ///< Limit register
<> 144:ef7eb2e8f9f7 52 PWM_CH1->UDMR = 0; ///< Up Dowm mode register
<> 144:ef7eb2e8f9f7 53 PWM_CH1->TCMR = 0; ///< Timer Counter mode register
<> 144:ef7eb2e8f9f7 54 PWM_CH1->PEEER = 0; ///< PWM output Enable and External input Enable register
<> 144:ef7eb2e8f9f7 55 PWM_CH1->CMR = 0; ///< Capture mode register
<> 144:ef7eb2e8f9f7 56 PWM_CH1->PDMR = 0; ///< Periodic Mode register
<> 144:ef7eb2e8f9f7 57 PWM_CH1->DZER = 0; ///< Dead Zone Enable register
<> 144:ef7eb2e8f9f7 58 PWM_CH1->DZCR = 0; ///< Dead Zone Counter register
<> 144:ef7eb2e8f9f7 59 }
<> 144:ef7eb2e8f9f7 60 else if( PWM_CHn == PWM_CH2)
<> 144:ef7eb2e8f9f7 61 {
<> 144:ef7eb2e8f9f7 62 PWM->IER &= PWM_IER_IE2_Disable; ///< Interrupt enable register
<> 144:ef7eb2e8f9f7 63 PWM->SSR &= PWM_SSR_SS2_Stop; ///< Start Stop register
<> 144:ef7eb2e8f9f7 64 PWM->PSR &= PWM_PSR_PS2_Restart; ///< Pause register
<> 144:ef7eb2e8f9f7 65 PWM_CH2->IER = 0; ///< Interrupt enable register
<> 144:ef7eb2e8f9f7 66 PWM_CH2->ICR = PWM_CHn_ICR_MatchInterruptClear |
<> 144:ef7eb2e8f9f7 67 PWM_CHn_ICR_OverflowInterruptClear |
<> 144:ef7eb2e8f9f7 68 PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
<> 144:ef7eb2e8f9f7 69 PWM_CH2->PR = 0; ///< Prescale register
<> 144:ef7eb2e8f9f7 70 PWM_CH2->MR = 0; ///< Match register
<> 144:ef7eb2e8f9f7 71 PWM_CH2->LR = 0xFFFFFFFF; ///< Limit register
<> 144:ef7eb2e8f9f7 72 PWM_CH2->UDMR = 0; ///< Up Dowm mode register
<> 144:ef7eb2e8f9f7 73 PWM_CH2->TCMR = 0; ///< Timer Counter mode register
<> 144:ef7eb2e8f9f7 74 PWM_CH2->PEEER = 0; ///< PWM output Enable and External input Enable register
<> 144:ef7eb2e8f9f7 75 PWM_CH2->CMR = 0; ///< Capture mode register
<> 144:ef7eb2e8f9f7 76 PWM_CH2->PDMR = 0; ///< Periodic Mode register
<> 144:ef7eb2e8f9f7 77 PWM_CH2->DZER = 0; ///< Dead Zone Enable register
<> 144:ef7eb2e8f9f7 78 PWM_CH2->DZCR = 0; ///< Dead Zone Counter register
<> 144:ef7eb2e8f9f7 79 }
<> 144:ef7eb2e8f9f7 80 else if( PWM_CHn == PWM_CH3 )
<> 144:ef7eb2e8f9f7 81 {
<> 144:ef7eb2e8f9f7 82 PWM->IER &= PWM_IER_IE3_Disable; ///< Interrupt enable register
<> 144:ef7eb2e8f9f7 83 PWM->SSR &= PWM_SSR_SS3_Stop; ///< Start Stop register
<> 144:ef7eb2e8f9f7 84 PWM->PSR &= PWM_PSR_PS3_Restart; ///< Pause register
<> 144:ef7eb2e8f9f7 85 PWM_CH3->IER = 0; ///< Interrupt enable register
<> 144:ef7eb2e8f9f7 86 PWM_CH3->ICR = PWM_CHn_ICR_MatchInterruptClear |
<> 144:ef7eb2e8f9f7 87 PWM_CHn_ICR_OverflowInterruptClear |
<> 144:ef7eb2e8f9f7 88 PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
<> 144:ef7eb2e8f9f7 89 PWM_CH3->MR = 0; ///< Match register
<> 144:ef7eb2e8f9f7 90 PWM_CH3->LR = 0xFFFFFFFF; ///< Limit register
<> 144:ef7eb2e8f9f7 91 PWM_CH3->UDMR = 0; ///< Up Dowm mode register
<> 144:ef7eb2e8f9f7 92 PWM_CH3->TCMR = 0; ///< Timer Counter mode register
<> 144:ef7eb2e8f9f7 93 PWM_CH3->PEEER = 0; ///< PWM output Enable and External input Enable register
<> 144:ef7eb2e8f9f7 94 PWM_CH3->CMR = 0; ///< Capture mode register
<> 144:ef7eb2e8f9f7 95 PWM_CH3->PDMR = 0; ///< Periodic Mode register
<> 144:ef7eb2e8f9f7 96 PWM_CH3->DZER = 0; ///< Dead Zone Enable register
<> 144:ef7eb2e8f9f7 97 PWM_CH3->DZCR = 0; ///< Dead Zone Counter register
<> 144:ef7eb2e8f9f7 98 }
<> 144:ef7eb2e8f9f7 99 else if( PWM_CHn == PWM_CH4 )
<> 144:ef7eb2e8f9f7 100 {
<> 144:ef7eb2e8f9f7 101 PWM->SSR &= PWM_IER_IE4_Disable; ///< Start Stop register
<> 144:ef7eb2e8f9f7 102 PWM->PSR &= PWM_SSR_SS4_Stop; ///< Pause register
<> 144:ef7eb2e8f9f7 103 PWM->IER &= PWM_PSR_PS4_Restart; ///< Interrupt enable register
<> 144:ef7eb2e8f9f7 104 PWM_CH4->IER = 0; ///< Interrupt enable register
<> 144:ef7eb2e8f9f7 105 PWM_CH4->ICR = PWM_CHn_ICR_MatchInterruptClear |
<> 144:ef7eb2e8f9f7 106 PWM_CHn_ICR_OverflowInterruptClear |
<> 144:ef7eb2e8f9f7 107 PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
<> 144:ef7eb2e8f9f7 108 PWM_CH4->PR = 0; ///< Prescale register
<> 144:ef7eb2e8f9f7 109 PWM_CH4->MR = 0; ///< Match register
<> 144:ef7eb2e8f9f7 110 PWM_CH4->LR = 0xFFFF; ///< Limit register
<> 144:ef7eb2e8f9f7 111 PWM_CH4->UDMR = 0; ///< Up Dowm mode register
<> 144:ef7eb2e8f9f7 112 PWM_CH4->TCMR = 0; ///< Timer Counter mode register
<> 144:ef7eb2e8f9f7 113 PWM_CH4->PEEER = 0; ///< PWM output Enable and External input Enable register
<> 144:ef7eb2e8f9f7 114 PWM_CH4->CMR = 0; ///< Capture mode register
<> 144:ef7eb2e8f9f7 115 PWM_CH4->PDMR = 0; ///< Periodic Mode register
<> 144:ef7eb2e8f9f7 116 PWM_CH4->DZER = 0; ///< Dead Zone Enable register
<> 144:ef7eb2e8f9f7 117 PWM_CH4->DZCR = 0; ///< Dead Zone Counter register
<> 144:ef7eb2e8f9f7 118 }
<> 144:ef7eb2e8f9f7 119 else if( PWM_CHn == PWM_CH5 )
<> 144:ef7eb2e8f9f7 120 {
<> 144:ef7eb2e8f9f7 121 PWM->SSR &= PWM_IER_IE5_Disable; ///< Start Stop register
<> 144:ef7eb2e8f9f7 122 PWM->PSR &= PWM_SSR_SS5_Stop; ///< Pause register
<> 144:ef7eb2e8f9f7 123 PWM->IER &= PWM_PSR_PS5_Restart; ///< Interrupt enable register
<> 144:ef7eb2e8f9f7 124 PWM_CH5->IER = 0; ///< Interrupt enable register
<> 144:ef7eb2e8f9f7 125 PWM_CH5->ICR = PWM_CHn_ICR_MatchInterruptClear |
<> 144:ef7eb2e8f9f7 126 PWM_CHn_ICR_OverflowInterruptClear |
<> 144:ef7eb2e8f9f7 127 PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
<> 144:ef7eb2e8f9f7 128 PWM_CH5->PR = 0; ///< Prescale register
<> 144:ef7eb2e8f9f7 129 PWM_CH5->MR = 0; ///< Match register
<> 144:ef7eb2e8f9f7 130 PWM_CH5->LR = 0xFFFFFFFF; ///< Limit register
<> 144:ef7eb2e8f9f7 131 PWM_CH5->UDMR = 0; ///< Up Dowm mode register
<> 144:ef7eb2e8f9f7 132 PWM_CH5->TCMR = 0; ///< Timer Counter mode register
<> 144:ef7eb2e8f9f7 133 PWM_CH5->PEEER = 0; ///< PWM output Enable and External input Enable register
<> 144:ef7eb2e8f9f7 134 PWM_CH5->CMR = 0; ///< Capture mode register
<> 144:ef7eb2e8f9f7 135 PWM_CH5->PDMR = 0; ///< Periodic Mode register
<> 144:ef7eb2e8f9f7 136 PWM_CH5->DZER = 0; ///< Dead Zone Enable register
<> 144:ef7eb2e8f9f7 137 PWM_CH5->DZCR = 0; ///< Dead Zone Counter register
<> 144:ef7eb2e8f9f7 138 }
<> 144:ef7eb2e8f9f7 139 else if( PWM_CHn == PWM_CH6 )
<> 144:ef7eb2e8f9f7 140 {
<> 144:ef7eb2e8f9f7 141 PWM->SSR &= PWM_IER_IE6_Disable; ///< Start Stop register
<> 144:ef7eb2e8f9f7 142 PWM->PSR &= PWM_SSR_SS6_Stop; ///< Pause register
<> 144:ef7eb2e8f9f7 143 PWM->IER &= PWM_PSR_PS6_Restart; ///< Interrupt enable register
<> 144:ef7eb2e8f9f7 144 PWM_CH6->IER = 0; ///< Interrupt enable register
<> 144:ef7eb2e8f9f7 145 PWM_CH6->ICR = PWM_CHn_ICR_MatchInterruptClear |
<> 144:ef7eb2e8f9f7 146 PWM_CHn_ICR_OverflowInterruptClear |
<> 144:ef7eb2e8f9f7 147 PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
<> 144:ef7eb2e8f9f7 148 PWM_CH6->PR = 0; ///< Prescale register
<> 144:ef7eb2e8f9f7 149 PWM_CH6->MR = 0; ///< Match register
<> 144:ef7eb2e8f9f7 150 PWM_CH6->LR = 0xFFFFFFFF; ///< Limit register
<> 144:ef7eb2e8f9f7 151 PWM_CH6->UDMR = 0; ///< Up Dowm mode register
<> 144:ef7eb2e8f9f7 152 PWM_CH6->TCMR = 0; ///< Timer Counter mode register
<> 144:ef7eb2e8f9f7 153 PWM_CH6->PEEER = 0; ///< PWM output Enable and External input Enable register
<> 144:ef7eb2e8f9f7 154 PWM_CH6->CMR = 0; ///< Capture mode register
<> 144:ef7eb2e8f9f7 155 PWM_CH6->PDMR = 0; ///< Periodic Mode register
<> 144:ef7eb2e8f9f7 156 PWM_CH6->DZER = 0; ///< Dead Zone Enable register
<> 144:ef7eb2e8f9f7 157 PWM_CH6->DZCR = 0; ///< Dead Zone Counter register
<> 144:ef7eb2e8f9f7 158 }
<> 144:ef7eb2e8f9f7 159 else if( PWM_CHn == PWM_CH7 )
<> 144:ef7eb2e8f9f7 160 {
<> 144:ef7eb2e8f9f7 161 PWM->SSR &= PWM_IER_IE7_Disable; ///< Start Stop register
<> 144:ef7eb2e8f9f7 162 PWM->PSR &= PWM_SSR_SS7_Stop; ///< Pause register
<> 144:ef7eb2e8f9f7 163 PWM->IER &= PWM_PSR_PS7_Restart; ///< Interrupt enable register
<> 144:ef7eb2e8f9f7 164 PWM_CH7->IER = 0; ///< Interrupt enable register
<> 144:ef7eb2e8f9f7 165 PWM_CH7->ICR = PWM_CHn_ICR_MatchInterruptClear |
<> 144:ef7eb2e8f9f7 166 PWM_CHn_ICR_OverflowInterruptClear |
<> 144:ef7eb2e8f9f7 167 PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
<> 144:ef7eb2e8f9f7 168 PWM_CH7->PR = 0; ///< Prescale register
<> 144:ef7eb2e8f9f7 169 PWM_CH7->MR = 0; ///< Match register
<> 144:ef7eb2e8f9f7 170 PWM_CH7->LR = 0xFFFFFFFF; ///< Limit register
<> 144:ef7eb2e8f9f7 171 PWM_CH7->UDMR = 0; ///< Up Dowm mode register
<> 144:ef7eb2e8f9f7 172 PWM_CH7->TCMR = 0; ///< Timer Counter mode register
<> 144:ef7eb2e8f9f7 173 PWM_CH7->PEEER = 0; ///< PWM output Enable and External input Enable register
<> 144:ef7eb2e8f9f7 174 PWM_CH7->CMR = 0; ///< Capture mode register
<> 144:ef7eb2e8f9f7 175 PWM_CH7->PDMR = 0; ///< Periodic Mode register
<> 144:ef7eb2e8f9f7 176 PWM_CH7->DZER = 0; ///< Dead Zone Enable register
<> 144:ef7eb2e8f9f7 177 PWM_CH7->DZCR = 0; ///< Dead Zone Counter register
<> 144:ef7eb2e8f9f7 178 }
<> 144:ef7eb2e8f9f7 179 }
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 void PWM_TimerModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_TimerModeInitTypeDef* PWM_TimerModeInitStruct) //complet
<> 144:ef7eb2e8f9f7 183 {
<> 144:ef7eb2e8f9f7 184 /* Stop PWM_CHn */
<> 144:ef7eb2e8f9f7 185 PWM_CHn_Stop(PWM_CHn);
<> 144:ef7eb2e8f9f7 186 /* Select Timer/Counter mode as Timer mode */
<> 144:ef7eb2e8f9f7 187 PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode;
<> 144:ef7eb2e8f9f7 188 /* Set Prescale register value */
<> 144:ef7eb2e8f9f7 189 PWM_CHn->PR = PWM_TimerModeInitStruct->PWM_CHn_PR;
<> 144:ef7eb2e8f9f7 190 /* Set Match register value */
<> 144:ef7eb2e8f9f7 191 PWM_CHn->MR = PWM_TimerModeInitStruct->PWM_CHn_MR;
<> 144:ef7eb2e8f9f7 192 /* Set Limit register value */
<> 144:ef7eb2e8f9f7 193 PWM_CHn->LR = PWM_TimerModeInitStruct->PWM_CHn_LR;
<> 144:ef7eb2e8f9f7 194 /* Select Up-down mode */
<> 144:ef7eb2e8f9f7 195 PWM_CHn->UDMR = PWM_TimerModeInitStruct->PWM_CHn_UDMR;
<> 144:ef7eb2e8f9f7 196 /* Select Periodic mode */
<> 144:ef7eb2e8f9f7 197 PWM_CHn->PDMR = PWM_TimerModeInitStruct->PWM_CHn_PDMR;
<> 144:ef7eb2e8f9f7 198 }
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 void PWM_CaptureModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CaptureModeInitTypeDef* PWM_CaptureModeInitStruct) //complete
<> 144:ef7eb2e8f9f7 201 {
<> 144:ef7eb2e8f9f7 202 /* Check the parameters */
<> 144:ef7eb2e8f9f7 203 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 204 assert_param(IS_PWM_PR_FILTER(PWM_CaptureModeInitStruct->PWM_CHn_PR));
<> 144:ef7eb2e8f9f7 205 assert_param(IS_PWM_MR_FILTER(PWM_CHn, PWM_CaptureModeInitStruct->PWM_CHn_MR));
<> 144:ef7eb2e8f9f7 206 assert_param(IS_PWM_LR_FILTER(PWM_CHn, PWM_CaptureModeInitStruct->PWM_CHn_LR));
<> 144:ef7eb2e8f9f7 207 assert_param(IS_PWM_CHn_UDMR(PWM_CaptureModeInitStruct->PWM_CHn_UDMR));
<> 144:ef7eb2e8f9f7 208 assert_param(IS_PWM_CHn_PDMR(PWM_CaptureModeInitStruct->PWM_CHn_PDMR));
<> 144:ef7eb2e8f9f7 209 assert_param(IS_PWM_CHn_CMR(PWM_CaptureModeInitStruct->PWM_CHn_CMR));
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /* Stop PWM_CHn */
<> 144:ef7eb2e8f9f7 212 PWM_CHn_Stop(PWM_CHn);
<> 144:ef7eb2e8f9f7 213 /* Select Timer/Counter mode as Timer mode */
<> 144:ef7eb2e8f9f7 214 PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode;
<> 144:ef7eb2e8f9f7 215 /* Set Prescale register value */
<> 144:ef7eb2e8f9f7 216 PWM_CHn->PR = PWM_CaptureModeInitStruct->PWM_CHn_PR;
<> 144:ef7eb2e8f9f7 217 /* Set Match register value */
<> 144:ef7eb2e8f9f7 218 PWM_CHn->MR = PWM_CaptureModeInitStruct->PWM_CHn_MR;
<> 144:ef7eb2e8f9f7 219 /* Set Limit register value */
<> 144:ef7eb2e8f9f7 220 PWM_CHn->LR = PWM_CaptureModeInitStruct->PWM_CHn_LR;
<> 144:ef7eb2e8f9f7 221 /* Select Up-down mode */
<> 144:ef7eb2e8f9f7 222 PWM_CHn->UDMR = PWM_CaptureModeInitStruct->PWM_CHn_UDMR;
<> 144:ef7eb2e8f9f7 223 /* Select Periodic mode */
<> 144:ef7eb2e8f9f7 224 PWM_CHn->PDMR = PWM_CaptureModeInitStruct->PWM_CHn_PDMR;
<> 144:ef7eb2e8f9f7 225 /* Select Capture mode */
<> 144:ef7eb2e8f9f7 226 PWM_CHn->CMR = PWM_CaptureModeInitStruct->PWM_CHn_CMR;
<> 144:ef7eb2e8f9f7 227 /* External input enable */
<> 144:ef7eb2e8f9f7 228 PWM_CHn->PEEER = PWM_CHn_PEEER_ExtEnable;
<> 144:ef7eb2e8f9f7 229 }
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 void PWM_CounterModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CounterModeInitTypeDef* PWM_CounterModeInitStruct) //complete
<> 144:ef7eb2e8f9f7 232 {
<> 144:ef7eb2e8f9f7 233 /* Check the parameters */
<> 144:ef7eb2e8f9f7 234 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /* Stop PWM_CHn */
<> 144:ef7eb2e8f9f7 237 PWM_CHn_Stop(PWM_CHn);
<> 144:ef7eb2e8f9f7 238 /* Select Timer/Counter mode as Timer mode */
<> 144:ef7eb2e8f9f7 239 PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode;
<> 144:ef7eb2e8f9f7 240 /* Set Match register value */
<> 144:ef7eb2e8f9f7 241 PWM_CHn->MR = PWM_CounterModeInitStruct->PWM_CHn_MR;
<> 144:ef7eb2e8f9f7 242 /* Set Limit register value */
<> 144:ef7eb2e8f9f7 243 PWM_CHn->LR = PWM_CounterModeInitStruct->PWM_CHn_LR;
<> 144:ef7eb2e8f9f7 244 /* Select Up-down mode */
<> 144:ef7eb2e8f9f7 245 PWM_CHn->UDMR = PWM_CounterModeInitStruct->PWM_CHn_UDMR;
<> 144:ef7eb2e8f9f7 246 /* Select Periodic mode */
<> 144:ef7eb2e8f9f7 247 PWM_CHn->PDMR = PWM_CounterModeInitStruct->PWM_CHn_PDMR;
<> 144:ef7eb2e8f9f7 248 /* Select Counter mode */
<> 144:ef7eb2e8f9f7 249 PWM_CHn->TCMR = PWM_CounterModeInitStruct->PWM_CHn_TCMR;
<> 144:ef7eb2e8f9f7 250 /* Enable external input */
<> 144:ef7eb2e8f9f7 251 PWM_CHn->PEEER = PWM_CHn_PEEER_ExtEnable;
<> 144:ef7eb2e8f9f7 252 }
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 void PWM_DeadzoneModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_DeadzoneModeInitTypDef* PWM_DeadzoneModeInitStruct) //complete
<> 144:ef7eb2e8f9f7 255 {
<> 144:ef7eb2e8f9f7 256 /* Check the parameters */
<> 144:ef7eb2e8f9f7 257 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 258 assert_param(IS_PWM_PR_FILTER(PWM_DeadzoneModeInitStruct->PWM_CHn_PR));
<> 144:ef7eb2e8f9f7 259 assert_param(IS_PWM_MR_FILTER(PWM_CHn, PWM_DeadzoneModeInitStruct->PWM_CHn_MR));
<> 144:ef7eb2e8f9f7 260 assert_param(IS_PWM_LR_FILTER(PWM_CHn, PWM_DeadzoneModeInitStruct->PWM_CHn_LR));
<> 144:ef7eb2e8f9f7 261 assert_param(IS_PWM_CHn_UDMR(PWM_DeadzoneModeInitStruct->PWM_CHn_UDMR));
<> 144:ef7eb2e8f9f7 262 assert_param(IS_PWM_CHn_PDMR(PWM_DeadzoneModeInitStruct->PWM_CHn_PDMR));
<> 144:ef7eb2e8f9f7 263 assert_param(IS_PWM_Deadznoe(PWM_CHn));
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /* Stop PWM_CHn */
<> 144:ef7eb2e8f9f7 266 PWM_CHn_Stop(PWM_CHn);
<> 144:ef7eb2e8f9f7 267 /* Select Timer/Counter mode as Timer mode */
<> 144:ef7eb2e8f9f7 268 PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode;
<> 144:ef7eb2e8f9f7 269 /* Set Prescale register value */
<> 144:ef7eb2e8f9f7 270 PWM_CHn->PR = PWM_DeadzoneModeInitStruct->PWM_CHn_PR;
<> 144:ef7eb2e8f9f7 271 /* Set Match register value */
<> 144:ef7eb2e8f9f7 272 PWM_CHn->MR = PWM_DeadzoneModeInitStruct->PWM_CHn_MR;
<> 144:ef7eb2e8f9f7 273 /* Set Limit register value */
<> 144:ef7eb2e8f9f7 274 PWM_CHn->LR = PWM_DeadzoneModeInitStruct->PWM_CHn_LR;
<> 144:ef7eb2e8f9f7 275 /* Select Up-down mode */
<> 144:ef7eb2e8f9f7 276 PWM_CHn->UDMR = PWM_DeadzoneModeInitStruct->PWM_CHn_UDMR;
<> 144:ef7eb2e8f9f7 277 /* Select Periodic mode */
<> 144:ef7eb2e8f9f7 278 PWM_CHn->PDMR = PWM_DeadzoneModeInitStruct->PWM_CHn_PDMR;
<> 144:ef7eb2e8f9f7 279 /* Enable Dead Zone generation */
<> 144:ef7eb2e8f9f7 280 PWM_CHn->DZER = PWM_CHn_DZER_Enable;
<> 144:ef7eb2e8f9f7 281 /* Set Dead Zone Counter */
<> 144:ef7eb2e8f9f7 282 PWM_CHn->DZCR = PWM_DeadzoneModeInitStruct->PWM_CHn_DZCR;
<> 144:ef7eb2e8f9f7 283 }
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 void PWM_CtrlPWMOutput(PWM_CHn_TypeDef* PWM_CHn, uint32_t outputEnDisable ) //complete
<> 144:ef7eb2e8f9f7 286 {
<> 144:ef7eb2e8f9f7 287 /* Check the parameters */
<> 144:ef7eb2e8f9f7 288 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 289 assert_param(IS_PWM_Output(outputEnDisable));
<> 144:ef7eb2e8f9f7 290 if( PWM_CHn->DZER )
<> 144:ef7eb2e8f9f7 291 assert_param(IS_PWM_Deadznoe(PWM_CHn));
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 /* Stop PWM_CHn */
<> 144:ef7eb2e8f9f7 294 PWM_CHn_Stop(PWM_CHn);
<> 144:ef7eb2e8f9f7 295 /*Config PWM output and External input */
<> 144:ef7eb2e8f9f7 296 PWM_CHn->PEEER = outputEnDisable;
<> 144:ef7eb2e8f9f7 297 }
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 void PWM_CtrlPWMOutputEnable(PWM_CHn_TypeDef* PWM_CHn)
<> 144:ef7eb2e8f9f7 300 {
<> 144:ef7eb2e8f9f7 301 PWM_CtrlPWMOutput(PWM_CHn, PWM_CHn_PEEER_PWMEnable);
<> 144:ef7eb2e8f9f7 302 }
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 void PWM_CtrlPWMOutputDisable(PWM_CHn_TypeDef* PWM_CHn)
<> 144:ef7eb2e8f9f7 305 {
<> 144:ef7eb2e8f9f7 306 PWM_CtrlPWMOutput(PWM_CHn, PWM_CHn_PEEER_Disable);
<> 144:ef7eb2e8f9f7 307 }
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 void PWM_IntConfig(PWM_CHn_TypeDef* PWM_CHn, FunctionalState state) //complete
<> 144:ef7eb2e8f9f7 310 {
<> 144:ef7eb2e8f9f7 311 /* Check the parameters */
<> 144:ef7eb2e8f9f7 312 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /* Stop PWM_CHn */
<> 144:ef7eb2e8f9f7 315 PWM_CHn_Stop(PWM_CHn);
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 if(state == ENABLE)
<> 144:ef7eb2e8f9f7 318 {
<> 144:ef7eb2e8f9f7 319 if(PWM_CHn == PWM_CH0) {
<> 144:ef7eb2e8f9f7 320 PWM->IER |= PWM_IER_IE0_Enable;
<> 144:ef7eb2e8f9f7 321 }
<> 144:ef7eb2e8f9f7 322 else if(PWM_CHn == PWM_CH1) {
<> 144:ef7eb2e8f9f7 323 PWM->IER |= PWM_IER_IE1_Enable;
<> 144:ef7eb2e8f9f7 324 }
<> 144:ef7eb2e8f9f7 325 else if(PWM_CHn == PWM_CH2) {
<> 144:ef7eb2e8f9f7 326 PWM->IER |= PWM_IER_IE2_Enable;
<> 144:ef7eb2e8f9f7 327 }
<> 144:ef7eb2e8f9f7 328 else if(PWM_CHn == PWM_CH3) {
<> 144:ef7eb2e8f9f7 329 PWM->IER |= PWM_IER_IE3_Enable;
<> 144:ef7eb2e8f9f7 330 }
<> 144:ef7eb2e8f9f7 331 else if(PWM_CHn == PWM_CH4) {
<> 144:ef7eb2e8f9f7 332 PWM->IER |= PWM_IER_IE4_Enable;
<> 144:ef7eb2e8f9f7 333 }
<> 144:ef7eb2e8f9f7 334 else if(PWM_CHn == PWM_CH5) {
<> 144:ef7eb2e8f9f7 335 PWM->IER |= PWM_IER_IE5_Enable;
<> 144:ef7eb2e8f9f7 336 }
<> 144:ef7eb2e8f9f7 337 else if(PWM_CHn == PWM_CH6) {
<> 144:ef7eb2e8f9f7 338 PWM->IER |= PWM_IER_IE6_Enable;
<> 144:ef7eb2e8f9f7 339 }
<> 144:ef7eb2e8f9f7 340 else if(PWM_CHn == PWM_CH7) {
<> 144:ef7eb2e8f9f7 341 PWM->IER |= PWM_IER_IE7_Enable;
<> 144:ef7eb2e8f9f7 342 }
<> 144:ef7eb2e8f9f7 343 }
<> 144:ef7eb2e8f9f7 344 else
<> 144:ef7eb2e8f9f7 345 {
<> 144:ef7eb2e8f9f7 346 if(PWM_CHn == PWM_CH0) {
<> 144:ef7eb2e8f9f7 347 PWM->IER &= PWM_IER_IE0_Disable;
<> 144:ef7eb2e8f9f7 348 }
<> 144:ef7eb2e8f9f7 349 else if(PWM_CHn == PWM_CH1) {
<> 144:ef7eb2e8f9f7 350 PWM->IER &= PWM_IER_IE1_Disable;
<> 144:ef7eb2e8f9f7 351 }
<> 144:ef7eb2e8f9f7 352 else if(PWM_CHn == PWM_CH2) {
<> 144:ef7eb2e8f9f7 353 PWM->IER &= PWM_IER_IE2_Disable;
<> 144:ef7eb2e8f9f7 354 }
<> 144:ef7eb2e8f9f7 355 else if(PWM_CHn == PWM_CH3) {
<> 144:ef7eb2e8f9f7 356 PWM->IER &= PWM_IER_IE3_Disable;
<> 144:ef7eb2e8f9f7 357 }
<> 144:ef7eb2e8f9f7 358 else if(PWM_CHn == PWM_CH4) {
<> 144:ef7eb2e8f9f7 359 PWM->IER &= PWM_IER_IE4_Disable;
<> 144:ef7eb2e8f9f7 360 }
<> 144:ef7eb2e8f9f7 361 else if(PWM_CHn == PWM_CH5) {
<> 144:ef7eb2e8f9f7 362 PWM->IER &= PWM_IER_IE5_Disable;
<> 144:ef7eb2e8f9f7 363 }
<> 144:ef7eb2e8f9f7 364 else if(PWM_CHn == PWM_CH6) {
<> 144:ef7eb2e8f9f7 365 PWM->IER &= PWM_IER_IE6_Disable;
<> 144:ef7eb2e8f9f7 366 }
<> 144:ef7eb2e8f9f7 367 else if(PWM_CHn == PWM_CH7) {
<> 144:ef7eb2e8f9f7 368 PWM->IER &= PWM_IER_IE7_Disable;
<> 144:ef7eb2e8f9f7 369 }
<> 144:ef7eb2e8f9f7 370 }
<> 144:ef7eb2e8f9f7 371 }
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 FlagStatus PWM_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn)
<> 144:ef7eb2e8f9f7 374 {
<> 144:ef7eb2e8f9f7 375 FlagStatus ret_val = RESET;
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /* Check the parameters */
<> 144:ef7eb2e8f9f7 378 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 if(PWM_CHn == PWM_CH0) {
<> 144:ef7eb2e8f9f7 381 ret_val = (FlagStatus)((PWM->IER & 0x01) >> 0);
<> 144:ef7eb2e8f9f7 382 }
<> 144:ef7eb2e8f9f7 383 else if(PWM_CHn == PWM_CH1) {
<> 144:ef7eb2e8f9f7 384 ret_val = (FlagStatus)((PWM->IER & 0x02) >> 1);
<> 144:ef7eb2e8f9f7 385 }
<> 144:ef7eb2e8f9f7 386 else if(PWM_CHn == PWM_CH2) {
<> 144:ef7eb2e8f9f7 387 ret_val = (FlagStatus)((PWM->IER & 0x04) >> 2);
<> 144:ef7eb2e8f9f7 388 }
<> 144:ef7eb2e8f9f7 389 else if(PWM_CHn == PWM_CH3) {
<> 144:ef7eb2e8f9f7 390 ret_val = (FlagStatus)((PWM->IER & 0x08) >> 3);
<> 144:ef7eb2e8f9f7 391 }
<> 144:ef7eb2e8f9f7 392 else if(PWM_CHn == PWM_CH4) {
<> 144:ef7eb2e8f9f7 393 ret_val = (FlagStatus)((PWM->IER & 0x10) >> 4);
<> 144:ef7eb2e8f9f7 394 }
<> 144:ef7eb2e8f9f7 395 else if(PWM_CHn == PWM_CH5) {
<> 144:ef7eb2e8f9f7 396 ret_val = (FlagStatus)((PWM->IER & 0x20) >> 5);
<> 144:ef7eb2e8f9f7 397 }
<> 144:ef7eb2e8f9f7 398 else if(PWM_CHn == PWM_CH6) {
<> 144:ef7eb2e8f9f7 399 ret_val = (FlagStatus)((PWM->IER & 0x40) >> 6);
<> 144:ef7eb2e8f9f7 400 }
<> 144:ef7eb2e8f9f7 401 else if(PWM_CHn == PWM_CH7) {
<> 144:ef7eb2e8f9f7 402 ret_val = (FlagStatus)((PWM->IER & 0x80) >> 7);
<> 144:ef7eb2e8f9f7 403 }
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 return ret_val;
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 void PWM_CHn_IntConfig(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_IER, FunctionalState state) //complete
<> 144:ef7eb2e8f9f7 409 {
<> 144:ef7eb2e8f9f7 410 /* Check the parameters */
<> 144:ef7eb2e8f9f7 411 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 assert_param(IS_PWM_CHn_IER(PWM_CHn_IER));
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /* Stop PWM_CHn */
<> 144:ef7eb2e8f9f7 417 PWM_CHn_Stop(PWM_CHn);
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 if(state == ENABLE)
<> 144:ef7eb2e8f9f7 420 PWM_CHn->IER |= PWM_CHn_IER;
<> 144:ef7eb2e8f9f7 421 else
<> 144:ef7eb2e8f9f7 422 PWM_CHn->IER &= ~PWM_CHn_IER;
<> 144:ef7eb2e8f9f7 423 }
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 uint32_t PWM_CHn_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn) //complete
<> 144:ef7eb2e8f9f7 426 {
<> 144:ef7eb2e8f9f7 427 /* Check the parameters */
<> 144:ef7eb2e8f9f7 428 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 return PWM_CHn->IER;
<> 144:ef7eb2e8f9f7 431 }
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 uint32_t PWM_CHn_GetIntFlagStatus(PWM_CHn_TypeDef* PWM_CHn) //complete
<> 144:ef7eb2e8f9f7 434 {
<> 144:ef7eb2e8f9f7 435 /* Check the parameters */
<> 144:ef7eb2e8f9f7 436 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 return PWM_CHn->IR;
<> 144:ef7eb2e8f9f7 439 }
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 void PWM_CHn_ClearInt(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_ICR)
<> 144:ef7eb2e8f9f7 442 {
<> 144:ef7eb2e8f9f7 443 /* Check the parameters */
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 PWM_CHn->ICR = PWM_CHn_ICR;
<> 144:ef7eb2e8f9f7 446 }
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 void PWM_CHn_Start(PWM_CHn_TypeDef* PWM_CHn) //complete
<> 144:ef7eb2e8f9f7 449 {
<> 144:ef7eb2e8f9f7 450 /* Check the parameters */
<> 144:ef7eb2e8f9f7 451 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /* Set Start Stop register */
<> 144:ef7eb2e8f9f7 454 if(PWM_CHn == PWM_CH0) {
<> 144:ef7eb2e8f9f7 455 PWM->SSR |= PWM_SSR_SS0_Start;
<> 144:ef7eb2e8f9f7 456 }
<> 144:ef7eb2e8f9f7 457 else if(PWM_CHn == PWM_CH1) {
<> 144:ef7eb2e8f9f7 458 PWM->SSR |= PWM_SSR_SS1_Start;
<> 144:ef7eb2e8f9f7 459 }
<> 144:ef7eb2e8f9f7 460 else if(PWM_CHn == PWM_CH2) {
<> 144:ef7eb2e8f9f7 461 PWM->SSR |= PWM_SSR_SS2_Start;
<> 144:ef7eb2e8f9f7 462 }
<> 144:ef7eb2e8f9f7 463 else if(PWM_CHn == PWM_CH3) {
<> 144:ef7eb2e8f9f7 464 PWM->SSR |= PWM_SSR_SS3_Start;
<> 144:ef7eb2e8f9f7 465 }
<> 144:ef7eb2e8f9f7 466 else if(PWM_CHn == PWM_CH4) {
<> 144:ef7eb2e8f9f7 467 PWM->SSR |= PWM_SSR_SS4_Start;
<> 144:ef7eb2e8f9f7 468 }
<> 144:ef7eb2e8f9f7 469 else if(PWM_CHn == PWM_CH5) {
<> 144:ef7eb2e8f9f7 470 PWM->SSR |= PWM_SSR_SS5_Start;
<> 144:ef7eb2e8f9f7 471 }
<> 144:ef7eb2e8f9f7 472 else if(PWM_CHn == PWM_CH6) {
<> 144:ef7eb2e8f9f7 473 PWM->SSR |= PWM_SSR_SS6_Start;
<> 144:ef7eb2e8f9f7 474 }
<> 144:ef7eb2e8f9f7 475 else if(PWM_CHn == PWM_CH7) {
<> 144:ef7eb2e8f9f7 476 PWM->SSR |= PWM_SSR_SS7_Start;
<> 144:ef7eb2e8f9f7 477 }
<> 144:ef7eb2e8f9f7 478 }
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 void PWM_Multi_Start(uint32_t ssr_bit_flag) //complete
<> 144:ef7eb2e8f9f7 481 {
<> 144:ef7eb2e8f9f7 482 /* Set Start Stop register */
<> 144:ef7eb2e8f9f7 483 PWM->SSR |= ssr_bit_flag;
<> 144:ef7eb2e8f9f7 484 }
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 void PWM_CHn_Stop(PWM_CHn_TypeDef* PWM_CHn) //complete
<> 144:ef7eb2e8f9f7 487 {
<> 144:ef7eb2e8f9f7 488 /* Reset Start Stop register */
<> 144:ef7eb2e8f9f7 489 if(PWM_CHn == PWM_CH0) {
<> 144:ef7eb2e8f9f7 490 PWM->SSR &= PWM_SSR_SS0_Stop;
<> 144:ef7eb2e8f9f7 491 }
<> 144:ef7eb2e8f9f7 492 else if(PWM_CHn == PWM_CH1) {
<> 144:ef7eb2e8f9f7 493 PWM->SSR &= PWM_SSR_SS1_Stop;
<> 144:ef7eb2e8f9f7 494 }
<> 144:ef7eb2e8f9f7 495 else if(PWM_CHn == PWM_CH2) {
<> 144:ef7eb2e8f9f7 496 PWM->SSR &= PWM_SSR_SS2_Stop;
<> 144:ef7eb2e8f9f7 497 }
<> 144:ef7eb2e8f9f7 498 else if(PWM_CHn == PWM_CH3) {
<> 144:ef7eb2e8f9f7 499 PWM->SSR &= PWM_SSR_SS3_Stop;
<> 144:ef7eb2e8f9f7 500 }
<> 144:ef7eb2e8f9f7 501 else if(PWM_CHn == PWM_CH4) {
<> 144:ef7eb2e8f9f7 502 PWM->SSR &= PWM_SSR_SS4_Stop;
<> 144:ef7eb2e8f9f7 503 }
<> 144:ef7eb2e8f9f7 504 else if(PWM_CHn == PWM_CH5) {
<> 144:ef7eb2e8f9f7 505 PWM->SSR &= PWM_SSR_SS5_Stop;
<> 144:ef7eb2e8f9f7 506 }
<> 144:ef7eb2e8f9f7 507 else if(PWM_CHn == PWM_CH6) {
<> 144:ef7eb2e8f9f7 508 PWM->SSR &= PWM_SSR_SS6_Stop;
<> 144:ef7eb2e8f9f7 509 }
<> 144:ef7eb2e8f9f7 510 else if(PWM_CHn == PWM_CH7) {
<> 144:ef7eb2e8f9f7 511 PWM->SSR &= PWM_SSR_SS7_Stop;
<> 144:ef7eb2e8f9f7 512 }
<> 144:ef7eb2e8f9f7 513 }
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 void PWM_Multi_Stop(uint32_t ssr_bit_flag) //complete
<> 144:ef7eb2e8f9f7 516 {
<> 144:ef7eb2e8f9f7 517 /* Reset Start Stop register */
<> 144:ef7eb2e8f9f7 518 PWM->SSR &= ~ssr_bit_flag;
<> 144:ef7eb2e8f9f7 519 }
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 void PWM_CHn_Pause(PWM_CHn_TypeDef* PWM_CHn)
<> 144:ef7eb2e8f9f7 522 {
<> 144:ef7eb2e8f9f7 523 /* Check the parameters */
<> 144:ef7eb2e8f9f7 524 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /* Set Pause register */
<> 144:ef7eb2e8f9f7 527 if(PWM_CHn == PWM_CH0) {
<> 144:ef7eb2e8f9f7 528 PWM->PSR |= PWM_PSR_PS0_Pause;
<> 144:ef7eb2e8f9f7 529 }
<> 144:ef7eb2e8f9f7 530 else if(PWM_CHn == PWM_CH1) {
<> 144:ef7eb2e8f9f7 531 PWM->PSR |= PWM_PSR_PS1_Pause;
<> 144:ef7eb2e8f9f7 532 }
<> 144:ef7eb2e8f9f7 533 else if(PWM_CHn == PWM_CH2) {
<> 144:ef7eb2e8f9f7 534 PWM->PSR |= PWM_PSR_PS2_Pause;
<> 144:ef7eb2e8f9f7 535 }
<> 144:ef7eb2e8f9f7 536 else if(PWM_CHn == PWM_CH3) {
<> 144:ef7eb2e8f9f7 537 PWM->PSR |= PWM_PSR_PS3_Pause;
<> 144:ef7eb2e8f9f7 538 }
<> 144:ef7eb2e8f9f7 539 else if(PWM_CHn == PWM_CH4) {
<> 144:ef7eb2e8f9f7 540 PWM->PSR |= PWM_PSR_PS4_Pause;
<> 144:ef7eb2e8f9f7 541 }
<> 144:ef7eb2e8f9f7 542 else if(PWM_CHn == PWM_CH5) {
<> 144:ef7eb2e8f9f7 543 PWM->PSR |= PWM_PSR_PS5_Pause;
<> 144:ef7eb2e8f9f7 544 }
<> 144:ef7eb2e8f9f7 545 else if(PWM_CHn == PWM_CH6) {
<> 144:ef7eb2e8f9f7 546 PWM->PSR |= PWM_PSR_PS6_Pause;
<> 144:ef7eb2e8f9f7 547 }
<> 144:ef7eb2e8f9f7 548 else if(PWM_CHn == PWM_CH7) {
<> 144:ef7eb2e8f9f7 549 PWM->PSR |= PWM_PSR_PS7_Pause;
<> 144:ef7eb2e8f9f7 550 }
<> 144:ef7eb2e8f9f7 551 }
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 void PWM_Multi_Pause(uint32_t psr_bit_flag)
<> 144:ef7eb2e8f9f7 554 {
<> 144:ef7eb2e8f9f7 555 PWM->PSR |= psr_bit_flag;
<> 144:ef7eb2e8f9f7 556 }
<> 144:ef7eb2e8f9f7 557
<> 144:ef7eb2e8f9f7 558 void PWM_CHn_Restart(PWM_CHn_TypeDef* PWM_CHn)
<> 144:ef7eb2e8f9f7 559 {
<> 144:ef7eb2e8f9f7 560 /* Check the parameters */
<> 144:ef7eb2e8f9f7 561 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 /* Reset Pause register */
<> 144:ef7eb2e8f9f7 564 if(PWM_CHn == PWM_CH0) {
<> 144:ef7eb2e8f9f7 565 PWM->PSR &= PWM_PSR_PS0_Restart;
<> 144:ef7eb2e8f9f7 566 }
<> 144:ef7eb2e8f9f7 567 else if(PWM_CHn == PWM_CH1) {
<> 144:ef7eb2e8f9f7 568 PWM->PSR &= PWM_PSR_PS1_Restart;
<> 144:ef7eb2e8f9f7 569 }
<> 144:ef7eb2e8f9f7 570 else if(PWM_CHn == PWM_CH2) {
<> 144:ef7eb2e8f9f7 571 PWM->PSR &= PWM_PSR_PS2_Restart;
<> 144:ef7eb2e8f9f7 572 }
<> 144:ef7eb2e8f9f7 573 else if(PWM_CHn == PWM_CH3) {
<> 144:ef7eb2e8f9f7 574 PWM->PSR &= PWM_PSR_PS3_Restart;
<> 144:ef7eb2e8f9f7 575 }
<> 144:ef7eb2e8f9f7 576 else if(PWM_CHn == PWM_CH4) {
<> 144:ef7eb2e8f9f7 577 PWM->PSR &= PWM_PSR_PS4_Restart;
<> 144:ef7eb2e8f9f7 578 }
<> 144:ef7eb2e8f9f7 579 else if(PWM_CHn == PWM_CH5) {
<> 144:ef7eb2e8f9f7 580 PWM->PSR &= PWM_PSR_PS5_Restart;
<> 144:ef7eb2e8f9f7 581 }
<> 144:ef7eb2e8f9f7 582 else if(PWM_CHn == PWM_CH6) {
<> 144:ef7eb2e8f9f7 583 PWM->PSR &= PWM_PSR_PS6_Restart;
<> 144:ef7eb2e8f9f7 584 }
<> 144:ef7eb2e8f9f7 585 else if(PWM_CHn == PWM_CH7) {
<> 144:ef7eb2e8f9f7 586 PWM->PSR &= PWM_PSR_PS7_Restart;
<> 144:ef7eb2e8f9f7 587 }
<> 144:ef7eb2e8f9f7 588 }
<> 144:ef7eb2e8f9f7 589
<> 144:ef7eb2e8f9f7 590 void PWM_Multi_Restart(uint32_t psr_bit_flag)
<> 144:ef7eb2e8f9f7 591 {
<> 144:ef7eb2e8f9f7 592 PWM->PSR &= ~psr_bit_flag;
<> 144:ef7eb2e8f9f7 593 }
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 uint32_t PWM_CHn_GetTCR(PWM_CHn_TypeDef* PWM_CHn) //complete
<> 144:ef7eb2e8f9f7 597 {
<> 144:ef7eb2e8f9f7 598 /* Check the parameters */
<> 144:ef7eb2e8f9f7 599 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 return PWM_CHn->TCR;
<> 144:ef7eb2e8f9f7 602 }
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 uint32_t PWM_CHn_GetPCR(PWM_CHn_TypeDef* PWM_CHn) //complete
<> 144:ef7eb2e8f9f7 605 {
<> 144:ef7eb2e8f9f7 606 /* Check the parameters */
<> 144:ef7eb2e8f9f7 607 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 return PWM_CHn->PCR;
<> 144:ef7eb2e8f9f7 610 }
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 uint32_t PWM_CHn_GetPR(PWM_CHn_TypeDef* PWM_CHn) //complete
<> 144:ef7eb2e8f9f7 613 {
<> 144:ef7eb2e8f9f7 614 /* Check the parameters */
<> 144:ef7eb2e8f9f7 615 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 616
<> 144:ef7eb2e8f9f7 617 return PWM_CHn->PR;
<> 144:ef7eb2e8f9f7 618 }
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 void PWM_CHn_SetPR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PR) //complete
<> 144:ef7eb2e8f9f7 621 {
<> 144:ef7eb2e8f9f7 622 /* Check the parameters */
<> 144:ef7eb2e8f9f7 623 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 624 assert_param(IS_PWM_PR_FILTER(PR));
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 PWM_CHn->PR = PR;
<> 144:ef7eb2e8f9f7 627 }
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 uint32_t PWM_CHn_GetMR(PWM_CHn_TypeDef* PWM_CHn) //complete
<> 144:ef7eb2e8f9f7 630 {
<> 144:ef7eb2e8f9f7 631 /* Check the parameters */
<> 144:ef7eb2e8f9f7 632 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 return PWM_CHn->MR;
<> 144:ef7eb2e8f9f7 635 }
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 void PWM_CHn_SetMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t MR) //complete
<> 144:ef7eb2e8f9f7 638 {
<> 144:ef7eb2e8f9f7 639 /* Check the parameters */
<> 144:ef7eb2e8f9f7 640 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 PWM_CHn->MR = MR;
<> 144:ef7eb2e8f9f7 643 }
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 uint32_t PWM_CHn_GetLR(PWM_CHn_TypeDef* PWM_CHn) //complete
<> 144:ef7eb2e8f9f7 646 {
<> 144:ef7eb2e8f9f7 647 /* Check the parameters */
<> 144:ef7eb2e8f9f7 648 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 return PWM_CHn->LR;
<> 144:ef7eb2e8f9f7 651 }
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 void PWM_CHn_SetLR(PWM_CHn_TypeDef* PWM_CHn, uint32_t LR) //complete
<> 144:ef7eb2e8f9f7 654 {
<> 144:ef7eb2e8f9f7 655 /* Check the parameters */
<> 144:ef7eb2e8f9f7 656 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 PWM_CHn->LR = LR;
<> 144:ef7eb2e8f9f7 659 }
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 uint32_t PWM_CHn_GetUDMR(PWM_CHn_TypeDef* PWM_CHn) //complete
<> 144:ef7eb2e8f9f7 662 {
<> 144:ef7eb2e8f9f7 663 /* Check the parameters */
<> 144:ef7eb2e8f9f7 664 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 return PWM_CHn->UDMR;
<> 144:ef7eb2e8f9f7 667 }
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 void PWM_CHn_SetUDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t UDMR) //complete
<> 144:ef7eb2e8f9f7 670 {
<> 144:ef7eb2e8f9f7 671 /* Check the parameters */
<> 144:ef7eb2e8f9f7 672 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 673 assert_param(IS_PWM_CHn_UDMR(UDMR));
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 PWM_CHn->UDMR = UDMR;
<> 144:ef7eb2e8f9f7 676 }
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 uint32_t PWM_CHn_GetTCMR(PWM_CHn_TypeDef* PWM_CHn) //complete
<> 144:ef7eb2e8f9f7 679 {
<> 144:ef7eb2e8f9f7 680 /* Check the parameters */
<> 144:ef7eb2e8f9f7 681 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 return PWM_CHn->TCMR;
<> 144:ef7eb2e8f9f7 684 }
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 void PWM_CHn_SetTCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t TCMR) //complete
<> 144:ef7eb2e8f9f7 687 {
<> 144:ef7eb2e8f9f7 688 /* Check the parameters */
<> 144:ef7eb2e8f9f7 689 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 690 assert_param(IS_PWM_CHn_TCMR(TCMR));
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692 PWM_CHn->TCMR = TCMR;
<> 144:ef7eb2e8f9f7 693 }
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 uint32_t PWM_CHn_GetPEEER(PWM_CHn_TypeDef* PWM_CHn) //complete
<> 144:ef7eb2e8f9f7 696 {
<> 144:ef7eb2e8f9f7 697 /* Check the parameters */
<> 144:ef7eb2e8f9f7 698 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 return PWM_CHn->PEEER;
<> 144:ef7eb2e8f9f7 701 }
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 void PWM_CHn_SetPEEER(PWM_CHn_TypeDef* PWM_CHn, uint32_t PEEER) //complete
<> 144:ef7eb2e8f9f7 704 {
<> 144:ef7eb2e8f9f7 705 /* Check the parameters */
<> 144:ef7eb2e8f9f7 706 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 707 assert_param(IS_PWM_CHn_PEEER(PEEER));
<> 144:ef7eb2e8f9f7 708
<> 144:ef7eb2e8f9f7 709 PWM_CHn->PEEER = PEEER;
<> 144:ef7eb2e8f9f7 710 }
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 uint32_t PWM_CHn_GetCMR(PWM_CHn_TypeDef* PWM_CHn) //complete
<> 144:ef7eb2e8f9f7 713 {
<> 144:ef7eb2e8f9f7 714 /* Check the parameters */
<> 144:ef7eb2e8f9f7 715 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 716
<> 144:ef7eb2e8f9f7 717 return PWM_CHn->CMR;
<> 144:ef7eb2e8f9f7 718 }
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 void PWM_CHn_SetCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t CMR) //complete
<> 144:ef7eb2e8f9f7 721 {
<> 144:ef7eb2e8f9f7 722 /* Check the parameters */
<> 144:ef7eb2e8f9f7 723 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 724 assert_param(IS_PWM_CHn_CMR(CMR));
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 PWM_CHn->CMR = CMR;
<> 144:ef7eb2e8f9f7 727 }
<> 144:ef7eb2e8f9f7 728
<> 144:ef7eb2e8f9f7 729 uint32_t PWM_CHn_GetCR(PWM_CHn_TypeDef* PWM_CHn)
<> 144:ef7eb2e8f9f7 730 {
<> 144:ef7eb2e8f9f7 731 /* Check the parameters */
<> 144:ef7eb2e8f9f7 732 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 return PWM_CHn->CR;
<> 144:ef7eb2e8f9f7 735 }
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 uint32_t PWM_CHn_GetPDMR(PWM_CHn_TypeDef* PWM_CHn) //complete
<> 144:ef7eb2e8f9f7 738 {
<> 144:ef7eb2e8f9f7 739 /* Check the parameters */
<> 144:ef7eb2e8f9f7 740 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 741
<> 144:ef7eb2e8f9f7 742 return PWM_CHn->PDMR;
<> 144:ef7eb2e8f9f7 743 }
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 void PWM_CHn_SetPDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PDMR) //complete
<> 144:ef7eb2e8f9f7 746 {
<> 144:ef7eb2e8f9f7 747 /* Check the parameters */
<> 144:ef7eb2e8f9f7 748 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 749 assert_param(IS_PWM_CHn_PDMR(PDMR));
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 PWM_CHn->PDMR = PDMR;
<> 144:ef7eb2e8f9f7 752 }
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 uint32_t PWM_CHn_GetDZER(PWM_CHn_TypeDef* PWM_CHn) //complete
<> 144:ef7eb2e8f9f7 755 {
<> 144:ef7eb2e8f9f7 756 /* Check the parameters */
<> 144:ef7eb2e8f9f7 757 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759 return PWM_CHn->DZER;
<> 144:ef7eb2e8f9f7 760 }
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 void PWM_CHn_SetDZER(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZER) //complete
<> 144:ef7eb2e8f9f7 763 {
<> 144:ef7eb2e8f9f7 764 /* Check the parameters */
<> 144:ef7eb2e8f9f7 765 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 766 assert_param(IS_PWM_CHn_DZER(DZER));
<> 144:ef7eb2e8f9f7 767
<> 144:ef7eb2e8f9f7 768 PWM_CHn->DZER = DZER;
<> 144:ef7eb2e8f9f7 769 }
<> 144:ef7eb2e8f9f7 770
<> 144:ef7eb2e8f9f7 771 uint32_t PWM_CHn_GetDZCR(PWM_CHn_TypeDef* PWM_CHn) //complete
<> 144:ef7eb2e8f9f7 772 {
<> 144:ef7eb2e8f9f7 773 /* Check the parameters */
<> 144:ef7eb2e8f9f7 774 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 return PWM_CHn->DZCR;
<> 144:ef7eb2e8f9f7 777 }
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 void PWM_CHn_SetDZCR(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZCR) //complete
<> 144:ef7eb2e8f9f7 780 {
<> 144:ef7eb2e8f9f7 781 /* Check the parameters */
<> 144:ef7eb2e8f9f7 782 assert_param(IS_PWM_ALL_CH(PWM_CHn));
<> 144:ef7eb2e8f9f7 783 assert_param(IS_PWM_CHn_DZCR_FILTER(DZCR));
<> 144:ef7eb2e8f9f7 784
<> 144:ef7eb2e8f9f7 785 PWM_CHn->DZCR = DZCR;
<> 144:ef7eb2e8f9f7 786 }
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 void PWM_CH0_ClearMatchInt(void)
<> 144:ef7eb2e8f9f7 789 {
<> 144:ef7eb2e8f9f7 790 PWM_CHn_ClearInt(PWM_CH0, PWM_CHn_ICR_MatchInterruptClear);
<> 144:ef7eb2e8f9f7 791 }
<> 144:ef7eb2e8f9f7 792
<> 144:ef7eb2e8f9f7 793 void PWM_CH0_ClearOverflowInt(void)
<> 144:ef7eb2e8f9f7 794 {
<> 144:ef7eb2e8f9f7 795 PWM_CHn_ClearInt(PWM_CH0, PWM_CHn_ICR_OverflowInterruptClear);
<> 144:ef7eb2e8f9f7 796 }
<> 144:ef7eb2e8f9f7 797
<> 144:ef7eb2e8f9f7 798 void PWM_CH0_ClearCaptureInt(void)
<> 144:ef7eb2e8f9f7 799 {
<> 144:ef7eb2e8f9f7 800 PWM_CHn_ClearInt(PWM_CH0, PWM_CHn_ICR_CaptureInterruptClear);
<> 144:ef7eb2e8f9f7 801 }
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 void PWM_CH1_ClearMatchInt(void)
<> 144:ef7eb2e8f9f7 804 {
<> 144:ef7eb2e8f9f7 805 PWM_CHn_ClearInt(PWM_CH1, PWM_CHn_ICR_MatchInterruptClear);
<> 144:ef7eb2e8f9f7 806 }
<> 144:ef7eb2e8f9f7 807
<> 144:ef7eb2e8f9f7 808 void PWM_CH1_ClearOverflowInt(void)
<> 144:ef7eb2e8f9f7 809 {
<> 144:ef7eb2e8f9f7 810 PWM_CHn_ClearInt(PWM_CH1, PWM_CHn_ICR_OverflowInterruptClear);
<> 144:ef7eb2e8f9f7 811 }
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813 void PWM_CH1_ClearCaptureInt(void)
<> 144:ef7eb2e8f9f7 814 {
<> 144:ef7eb2e8f9f7 815 PWM_CHn_ClearInt(PWM_CH1, PWM_CHn_ICR_CaptureInterruptClear);
<> 144:ef7eb2e8f9f7 816 }
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 void PWM_CH2_ClearMatchInt(void)
<> 144:ef7eb2e8f9f7 819 {
<> 144:ef7eb2e8f9f7 820 PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_ICR_MatchInterruptClear);
<> 144:ef7eb2e8f9f7 821 }
<> 144:ef7eb2e8f9f7 822
<> 144:ef7eb2e8f9f7 823 void PWM_CH2_ClearOverflowInt(void)
<> 144:ef7eb2e8f9f7 824 {
<> 144:ef7eb2e8f9f7 825 PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_ICR_OverflowInterruptClear);
<> 144:ef7eb2e8f9f7 826 }
<> 144:ef7eb2e8f9f7 827
<> 144:ef7eb2e8f9f7 828 void PWM_CH2_ClearCaptureInt(void)
<> 144:ef7eb2e8f9f7 829 {
<> 144:ef7eb2e8f9f7 830 PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_ICR_CaptureInterruptClear);
<> 144:ef7eb2e8f9f7 831 }
<> 144:ef7eb2e8f9f7 832
<> 144:ef7eb2e8f9f7 833 void PWM_CH3_ClearMatchInt(void)
<> 144:ef7eb2e8f9f7 834 {
<> 144:ef7eb2e8f9f7 835 PWM_CHn_ClearInt(PWM_CH3, PWM_CHn_ICR_MatchInterruptClear);
<> 144:ef7eb2e8f9f7 836 }
<> 144:ef7eb2e8f9f7 837
<> 144:ef7eb2e8f9f7 838 void PWM_CH3_ClearOverflowInt(void)
<> 144:ef7eb2e8f9f7 839 {
<> 144:ef7eb2e8f9f7 840 PWM_CHn_ClearInt(PWM_CH3, PWM_CHn_ICR_OverflowInterruptClear);
<> 144:ef7eb2e8f9f7 841 }
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 void PWM_CH3_ClearCaptureInt(void)
<> 144:ef7eb2e8f9f7 844 {
<> 144:ef7eb2e8f9f7 845 PWM_CHn_ClearInt(PWM_CH3, PWM_CHn_ICR_CaptureInterruptClear);
<> 144:ef7eb2e8f9f7 846 }
<> 144:ef7eb2e8f9f7 847
<> 144:ef7eb2e8f9f7 848 void PWM_CH4_ClearMatchInt(void)
<> 144:ef7eb2e8f9f7 849 {
<> 144:ef7eb2e8f9f7 850 PWM_CHn_ClearInt(PWM_CH4, PWM_CHn_ICR_MatchInterruptClear);
<> 144:ef7eb2e8f9f7 851 }
<> 144:ef7eb2e8f9f7 852
<> 144:ef7eb2e8f9f7 853 void PWM_CH4_ClearOverflowInt(void)
<> 144:ef7eb2e8f9f7 854 {
<> 144:ef7eb2e8f9f7 855 PWM_CHn_ClearInt(PWM_CH4, PWM_CHn_ICR_OverflowInterruptClear);
<> 144:ef7eb2e8f9f7 856 }
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 void PWM_CH4_ClearCaptureInt(void)
<> 144:ef7eb2e8f9f7 859 {
<> 144:ef7eb2e8f9f7 860 PWM_CHn_ClearInt(PWM_CH4, PWM_CHn_ICR_CaptureInterruptClear);
<> 144:ef7eb2e8f9f7 861 }
<> 144:ef7eb2e8f9f7 862
<> 144:ef7eb2e8f9f7 863 void PWM_CH5_ClearMatchInt(void)
<> 144:ef7eb2e8f9f7 864 {
<> 144:ef7eb2e8f9f7 865 PWM_CHn_ClearInt(PWM_CH5, PWM_CHn_ICR_MatchInterruptClear);
<> 144:ef7eb2e8f9f7 866 }
<> 144:ef7eb2e8f9f7 867
<> 144:ef7eb2e8f9f7 868 void PWM_CH5_ClearOverflowInt(void)
<> 144:ef7eb2e8f9f7 869 {
<> 144:ef7eb2e8f9f7 870 PWM_CHn_ClearInt(PWM_CH5, PWM_CHn_ICR_OverflowInterruptClear);
<> 144:ef7eb2e8f9f7 871 }
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873 void PWM_CH5_ClearCaptureInt(void)
<> 144:ef7eb2e8f9f7 874 {
<> 144:ef7eb2e8f9f7 875 PWM_CHn_ClearInt(PWM_CH5, PWM_CHn_ICR_CaptureInterruptClear);
<> 144:ef7eb2e8f9f7 876 }
<> 144:ef7eb2e8f9f7 877
<> 144:ef7eb2e8f9f7 878 void PWM_CH6_ClearMatchInt(void)
<> 144:ef7eb2e8f9f7 879 {
<> 144:ef7eb2e8f9f7 880 PWM_CHn_ClearInt(PWM_CH6, PWM_CHn_ICR_MatchInterruptClear);
<> 144:ef7eb2e8f9f7 881 }
<> 144:ef7eb2e8f9f7 882
<> 144:ef7eb2e8f9f7 883 void PWM_CH6_ClearOverflowInt(void)
<> 144:ef7eb2e8f9f7 884 {
<> 144:ef7eb2e8f9f7 885 PWM_CHn_ClearInt(PWM_CH6, PWM_CHn_ICR_OverflowInterruptClear);
<> 144:ef7eb2e8f9f7 886 }
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 void PWM_CH6_ClearCaptureInt(void)
<> 144:ef7eb2e8f9f7 889 {
<> 144:ef7eb2e8f9f7 890 PWM_CHn_ClearInt(PWM_CH6, PWM_CHn_ICR_CaptureInterruptClear);
<> 144:ef7eb2e8f9f7 891 }
<> 144:ef7eb2e8f9f7 892
<> 144:ef7eb2e8f9f7 893 void PWM_CH7_ClearMatchInt(void)
<> 144:ef7eb2e8f9f7 894 {
<> 144:ef7eb2e8f9f7 895 PWM_CHn_ClearInt(PWM_CH7, PWM_CHn_ICR_MatchInterruptClear);
<> 144:ef7eb2e8f9f7 896 }
<> 144:ef7eb2e8f9f7 897
<> 144:ef7eb2e8f9f7 898 void PWM_CH7_ClearOverflowInt(void)
<> 144:ef7eb2e8f9f7 899 {
<> 144:ef7eb2e8f9f7 900 PWM_CHn_ClearInt(PWM_CH7, PWM_CHn_ICR_OverflowInterruptClear);
<> 144:ef7eb2e8f9f7 901 }
<> 144:ef7eb2e8f9f7 902
<> 144:ef7eb2e8f9f7 903 void PWM_CH7_ClearCaptureInt(void)
<> 144:ef7eb2e8f9f7 904 {
<> 144:ef7eb2e8f9f7 905 PWM_CHn_ClearInt(PWM_CH7, PWM_CHn_ICR_CaptureInterruptClear);
<> 144:ef7eb2e8f9f7 906 }