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targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_ll_adc.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:: <>
Date:: Fri Sep 02 15:07:44 2016 +0100
Revision:: 144:ef7eb2e8f9f7

This updates the lib to the mbed lib v125

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32l4xx_ll_adc.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.5.1
<>	144:ef7eb2e8f9f7	6	* @date 31-May-2016
<>	144:ef7eb2e8f9f7	7	* @brief Header file of ADC LL module.
<>	144:ef7eb2e8f9f7	8	******************************************************************************
<>	144:ef7eb2e8f9f7	9	* @attention
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	12	*
<>	144:ef7eb2e8f9f7	13	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	14	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	18	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	19	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	21	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	22	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	23	*
<>	144:ef7eb2e8f9f7	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	34	*
<>	144:ef7eb2e8f9f7	35	******************************************************************************
<>	144:ef7eb2e8f9f7	36	*/
<>	144:ef7eb2e8f9f7	37
<>	144:ef7eb2e8f9f7	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	39	#ifndef __STM32L4xx_LL_ADC_H
<>	144:ef7eb2e8f9f7	40	#define __STM32L4xx_LL_ADC_H
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	43	extern "C" {
<>	144:ef7eb2e8f9f7	44	#endif
<>	144:ef7eb2e8f9f7	45
<>	144:ef7eb2e8f9f7	46	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	47	#include "stm32l4xx.h"
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	/** @addtogroup STM32L4xx_LL_Driver
<>	144:ef7eb2e8f9f7	50	* @{
<>	144:ef7eb2e8f9f7	51	*/
<>	144:ef7eb2e8f9f7	52
<>	144:ef7eb2e8f9f7	53	#if defined (ADC1) \|\| defined (ADC2) \|\| defined (ADC3)
<>	144:ef7eb2e8f9f7	54
<>	144:ef7eb2e8f9f7	55	/** @defgroup ADC_LL ADC
<>	144:ef7eb2e8f9f7	56	* @{
<>	144:ef7eb2e8f9f7	57	*/
<>	144:ef7eb2e8f9f7	58
<>	144:ef7eb2e8f9f7	59	/* Private types -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	60	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	61
<>	144:ef7eb2e8f9f7	62	/* Private constants ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	63	/** @defgroup ADC_LL_Private_Constants ADC Private Constants
<>	144:ef7eb2e8f9f7	64	* @{
<>	144:ef7eb2e8f9f7	65	*/
<>	144:ef7eb2e8f9f7	66
<>	144:ef7eb2e8f9f7	67	/* Internal mask for ADC group regular sequencer: */
<>	144:ef7eb2e8f9f7	68	/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
<>	144:ef7eb2e8f9f7	69	/* - sequencer register offset */
<>	144:ef7eb2e8f9f7	70	/* - sequencer rank bits position into the selected register */
<>	144:ef7eb2e8f9f7	71
<>	144:ef7eb2e8f9f7	72	/* Internal register offset for ADC group regular sequencer configuration */
<>	144:ef7eb2e8f9f7	73	/* (offset placed into a spare area of literal definition) */
<>	144:ef7eb2e8f9f7	74	#define ADC_SQR1_REGOFFSET ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	75	#define ADC_SQR2_REGOFFSET ((uint32_t)0x00000100U)
<>	144:ef7eb2e8f9f7	76	#define ADC_SQR3_REGOFFSET ((uint32_t)0x00000200U)
<>	144:ef7eb2e8f9f7	77	#define ADC_SQR4_REGOFFSET ((uint32_t)0x00000300U)
<>	144:ef7eb2e8f9f7	78
<>	144:ef7eb2e8f9f7	79	#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET \| ADC_SQR2_REGOFFSET \| ADC_SQR3_REGOFFSET \| ADC_SQR4_REGOFFSET)
<>	144:ef7eb2e8f9f7	80	#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
<>	144:ef7eb2e8f9f7	81
<>	144:ef7eb2e8f9f7	82	/* Definition of ADC group regular sequencer bits information to be inserted */
<>	144:ef7eb2e8f9f7	83	/* into ADC group regular sequencer ranks literals definition. */
<>	144:ef7eb2e8f9f7	84	#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ1) */
<>	144:ef7eb2e8f9f7	85	#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ2) */
<>	144:ef7eb2e8f9f7	86	#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ3) */
<>	144:ef7eb2e8f9f7	87	#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ4) */
<>	144:ef7eb2e8f9f7	88	#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ5) */
<>	144:ef7eb2e8f9f7	89	#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ6) */
<>	144:ef7eb2e8f9f7	90	#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
<>	144:ef7eb2e8f9f7	91	#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
<>	144:ef7eb2e8f9f7	92	#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
<>	144:ef7eb2e8f9f7	93	#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ10) */
<>	144:ef7eb2e8f9f7	94	#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ11) */
<>	144:ef7eb2e8f9f7	95	#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ12) */
<>	144:ef7eb2e8f9f7	96	#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */
<>	144:ef7eb2e8f9f7	97	#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */
<>	144:ef7eb2e8f9f7	98	#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ15) */
<>	144:ef7eb2e8f9f7	99	#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ16) */
<>	144:ef7eb2e8f9f7	100
<>	144:ef7eb2e8f9f7	101
<>	144:ef7eb2e8f9f7	102
<>	144:ef7eb2e8f9f7	103	/* Internal mask for ADC group injected sequencer: */
<>	144:ef7eb2e8f9f7	104	/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
<>	144:ef7eb2e8f9f7	105	/* - data register offset */
<>	144:ef7eb2e8f9f7	106	/* - sequencer rank bits position into the selected register */
<>	144:ef7eb2e8f9f7	107
<>	144:ef7eb2e8f9f7	108	/* Internal register offset for ADC group injected data register */
<>	144:ef7eb2e8f9f7	109	/* (offset placed into a spare area of literal definition) */
<>	144:ef7eb2e8f9f7	110	#define ADC_JDR1_REGOFFSET ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	111	#define ADC_JDR2_REGOFFSET ((uint32_t)0x00000100U)
<>	144:ef7eb2e8f9f7	112	#define ADC_JDR3_REGOFFSET ((uint32_t)0x00000200U)
<>	144:ef7eb2e8f9f7	113	#define ADC_JDR4_REGOFFSET ((uint32_t)0x00000300U)
<>	144:ef7eb2e8f9f7	114
<>	144:ef7eb2e8f9f7	115	#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET \| ADC_JDR2_REGOFFSET \| ADC_JDR3_REGOFFSET \| ADC_JDR4_REGOFFSET)
<>	144:ef7eb2e8f9f7	116	#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
<>	144:ef7eb2e8f9f7	117
<>	144:ef7eb2e8f9f7	118	/* Definition of ADC group injected sequencer bits information to be inserted */
<>	144:ef7eb2e8f9f7	119	/* into ADC group injected sequencer ranks literals definition. */
<>	144:ef7eb2e8f9f7	120	#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
<>	144:ef7eb2e8f9f7	121	#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS ((uint32_t)14U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
<>	144:ef7eb2e8f9f7	122	#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
<>	144:ef7eb2e8f9f7	123	#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS ((uint32_t)26U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
<>	144:ef7eb2e8f9f7	124
<>	144:ef7eb2e8f9f7	125
<>	144:ef7eb2e8f9f7	126
<>	144:ef7eb2e8f9f7	127	/* Internal mask for ADC group regular trigger: */
<>	144:ef7eb2e8f9f7	128	/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
<>	144:ef7eb2e8f9f7	129	/* - regular trigger source */
<>	144:ef7eb2e8f9f7	130	/* - regular trigger edge */
<>	144:ef7eb2e8f9f7	131	#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
<>	144:ef7eb2e8f9f7	132
<>	144:ef7eb2e8f9f7	133	/* Mask containing trigger source masks for each of possible */
<>	144:ef7eb2e8f9f7	134	/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
<>	144:ef7eb2e8f9f7	135	/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
<>	144:ef7eb2e8f9f7	136	#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0U)) \| \
<>	144:ef7eb2e8f9f7	137	((ADC_CFGR_EXTSEL) << (4U * 1U)) \| \
<>	144:ef7eb2e8f9f7	138	((ADC_CFGR_EXTSEL) << (4U * 2U)) \| \
<>	144:ef7eb2e8f9f7	139	((ADC_CFGR_EXTSEL) << (4U * 3U)) )
<>	144:ef7eb2e8f9f7	140
<>	144:ef7eb2e8f9f7	141	/* Mask containing trigger edge masks for each of possible */
<>	144:ef7eb2e8f9f7	142	/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
<>	144:ef7eb2e8f9f7	143	/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
<>	144:ef7eb2e8f9f7	144	#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0U)) \| \
<>	144:ef7eb2e8f9f7	145	((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) \| \
<>	144:ef7eb2e8f9f7	146	((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) \| \
<>	144:ef7eb2e8f9f7	147	((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) )
<>	144:ef7eb2e8f9f7	148
<>	144:ef7eb2e8f9f7	149	/* Definition of ADC group regular trigger bits information. */
<>	144:ef7eb2e8f9f7	150	#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTSEL) */
<>	144:ef7eb2e8f9f7	151	#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTEN) */
<>	144:ef7eb2e8f9f7	152
<>	144:ef7eb2e8f9f7	153
<>	144:ef7eb2e8f9f7	154
<>	144:ef7eb2e8f9f7	155	/* Internal mask for ADC group injected trigger: */
<>	144:ef7eb2e8f9f7	156	/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
<>	144:ef7eb2e8f9f7	157	/* - injected trigger source */
<>	144:ef7eb2e8f9f7	158	/* - injected trigger edge */
<>	144:ef7eb2e8f9f7	159	#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
<>	144:ef7eb2e8f9f7	160
<>	144:ef7eb2e8f9f7	161	/* Mask containing trigger source masks for each of possible */
<>	144:ef7eb2e8f9f7	162	/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
<>	144:ef7eb2e8f9f7	163	/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
<>	144:ef7eb2e8f9f7	164	#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0U)) \| \
<>	144:ef7eb2e8f9f7	165	((ADC_JSQR_JEXTSEL) << (4U * 1U)) \| \
<>	144:ef7eb2e8f9f7	166	((ADC_JSQR_JEXTSEL) << (4U * 2U)) \| \
<>	144:ef7eb2e8f9f7	167	((ADC_JSQR_JEXTSEL) << (4U * 3U)) )
<>	144:ef7eb2e8f9f7	168
<>	144:ef7eb2e8f9f7	169	/* Mask containing trigger edge masks for each of possible */
<>	144:ef7eb2e8f9f7	170	/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
<>	144:ef7eb2e8f9f7	171	/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
<>	144:ef7eb2e8f9f7	172	#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0U)) \| \
<>	144:ef7eb2e8f9f7	173	((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) \| \
<>	144:ef7eb2e8f9f7	174	((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) \| \
<>	144:ef7eb2e8f9f7	175	((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) )
<>	144:ef7eb2e8f9f7	176
<>	144:ef7eb2e8f9f7	177	/* Definition of ADC group injected trigger bits information. */
<>	144:ef7eb2e8f9f7	178	#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t) 2U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTSEL) */
<>	144:ef7eb2e8f9f7	179	#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTEN) */
<>	144:ef7eb2e8f9f7	180
<>	144:ef7eb2e8f9f7	181
<>	144:ef7eb2e8f9f7	182
<>	144:ef7eb2e8f9f7	183
<>	144:ef7eb2e8f9f7	184
<>	144:ef7eb2e8f9f7	185
<>	144:ef7eb2e8f9f7	186	/* Internal mask for ADC channel: */
<>	144:ef7eb2e8f9f7	187	/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
<>	144:ef7eb2e8f9f7	188	/* - channel identifier defined by number */
<>	144:ef7eb2e8f9f7	189	/* - channel identifier defined by bitfield */
<>	144:ef7eb2e8f9f7	190	/* - channel differentiation between external channels (connected to */
<>	144:ef7eb2e8f9f7	191	/* GPIO pins) and internal channels (connected to internal paths) */
<>	144:ef7eb2e8f9f7	192	/* - channel sampling time defined by SMPRx register offset */
<>	144:ef7eb2e8f9f7	193	/* and SMPx bits positions into SMPRx register */
<>	144:ef7eb2e8f9f7	194	#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
<>	144:ef7eb2e8f9f7	195	#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
<>	144:ef7eb2e8f9f7	196	#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t)26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
<>	144:ef7eb2e8f9f7	197	#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK \| ADC_CHANNEL_ID_BITFIELD_MASK \| ADC_CHANNEL_ID_INTERNAL_CH_MASK)
<>	144:ef7eb2e8f9f7	198	/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
<>	144:ef7eb2e8f9f7	199	#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
<>	144:ef7eb2e8f9f7	200
<>	144:ef7eb2e8f9f7	201	/* Channel differentiation between external and internal channels */
<>	144:ef7eb2e8f9f7	202	#define ADC_CHANNEL_ID_INTERNAL_CH ((uint32_t)0x80000000U) /* Marker of internal channel */
<>	144:ef7eb2e8f9f7	203	#define ADC_CHANNEL_ID_INTERNAL_CH_2 ((uint32_t)0x00080000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
<>	144:ef7eb2e8f9f7	204	#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH \| ADC_CHANNEL_ID_INTERNAL_CH_2)
<>	144:ef7eb2e8f9f7	205
<>	144:ef7eb2e8f9f7	206	/* Internal register offset for ADC channel sampling time configuration */
<>	144:ef7eb2e8f9f7	207	/* (offset placed into a spare area of literal definition) */
<>	144:ef7eb2e8f9f7	208	#define ADC_SMPR1_REGOFFSET ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	209	#define ADC_SMPR2_REGOFFSET ((uint32_t)0x02000000U)
<>	144:ef7eb2e8f9f7	210	#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET \| ADC_SMPR2_REGOFFSET)
<>	144:ef7eb2e8f9f7	211
<>	144:ef7eb2e8f9f7	212	#define ADC_CHANNEL_SMPx_BITOFFSET_MASK ((uint32_t)0x01F00000U)
<>	144:ef7eb2e8f9f7	213	#define ADC_CHANNEL_SMPx_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
<>	144:ef7eb2e8f9f7	214
<>	144:ef7eb2e8f9f7	215	/* Definition of channels ID number information to be inserted into */
<>	144:ef7eb2e8f9f7	216	/* channels literals definition. */
<>	144:ef7eb2e8f9f7	217	#define ADC_CHANNEL_0_NUMBER ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	218	#define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
<>	144:ef7eb2e8f9f7	219	#define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
<>	144:ef7eb2e8f9f7	220	#define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 \| ADC_CFGR_AWD1CH_0)
<>	144:ef7eb2e8f9f7	221	#define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
<>	144:ef7eb2e8f9f7	222	#define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 \| ADC_CFGR_AWD1CH_0)
<>	144:ef7eb2e8f9f7	223	#define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 \| ADC_CFGR_AWD1CH_1 )
<>	144:ef7eb2e8f9f7	224	#define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 \| ADC_CFGR_AWD1CH_1 \| ADC_CFGR_AWD1CH_0)
<>	144:ef7eb2e8f9f7	225	#define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
<>	144:ef7eb2e8f9f7	226	#define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_0)
<>	144:ef7eb2e8f9f7	227	#define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_1 )
<>	144:ef7eb2e8f9f7	228	#define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_1 \| ADC_CFGR_AWD1CH_0)
<>	144:ef7eb2e8f9f7	229	#define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_2 )
<>	144:ef7eb2e8f9f7	230	#define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_2 \| ADC_CFGR_AWD1CH_0)
<>	144:ef7eb2e8f9f7	231	#define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_2 \| ADC_CFGR_AWD1CH_1 )
<>	144:ef7eb2e8f9f7	232	#define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_2 \| ADC_CFGR_AWD1CH_1 \| ADC_CFGR_AWD1CH_0)
<>	144:ef7eb2e8f9f7	233	#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
<>	144:ef7eb2e8f9f7	234	#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 \| ADC_CFGR_AWD1CH_0)
<>	144:ef7eb2e8f9f7	235	#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 \| ADC_CFGR_AWD1CH_1 )
<>	144:ef7eb2e8f9f7	236
<>	144:ef7eb2e8f9f7	237	/* Definition of channels ID bitfield information to be inserted into */
<>	144:ef7eb2e8f9f7	238	/* channels literals definition. */
<>	144:ef7eb2e8f9f7	239	#define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
<>	144:ef7eb2e8f9f7	240	#define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
<>	144:ef7eb2e8f9f7	241	#define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
<>	144:ef7eb2e8f9f7	242	#define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
<>	144:ef7eb2e8f9f7	243	#define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
<>	144:ef7eb2e8f9f7	244	#define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
<>	144:ef7eb2e8f9f7	245	#define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
<>	144:ef7eb2e8f9f7	246	#define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
<>	144:ef7eb2e8f9f7	247	#define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
<>	144:ef7eb2e8f9f7	248	#define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
<>	144:ef7eb2e8f9f7	249	#define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
<>	144:ef7eb2e8f9f7	250	#define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
<>	144:ef7eb2e8f9f7	251	#define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
<>	144:ef7eb2e8f9f7	252	#define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
<>	144:ef7eb2e8f9f7	253	#define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
<>	144:ef7eb2e8f9f7	254	#define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
<>	144:ef7eb2e8f9f7	255	#define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
<>	144:ef7eb2e8f9f7	256	#define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
<>	144:ef7eb2e8f9f7	257	#define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
<>	144:ef7eb2e8f9f7	258
<>	144:ef7eb2e8f9f7	259	/* Definition of channels sampling time information to be inserted into */
<>	144:ef7eb2e8f9f7	260	/* channels literals definition. */
<>	144:ef7eb2e8f9f7	261	#define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP0) */
<>	144:ef7eb2e8f9f7	262	#define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP1) */
<>	144:ef7eb2e8f9f7	263	#define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP2) */
<>	144:ef7eb2e8f9f7	264	#define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP3) */
<>	144:ef7eb2e8f9f7	265	#define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP4) */
<>	144:ef7eb2e8f9f7	266	#define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP5) */
<>	144:ef7eb2e8f9f7	267	#define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP6) */
<>	144:ef7eb2e8f9f7	268	#define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP7) */
<>	144:ef7eb2e8f9f7	269	#define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP8) */
<>	144:ef7eb2e8f9f7	270	#define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET \| (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP9) */
<>	144:ef7eb2e8f9f7	271	#define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */
<>	144:ef7eb2e8f9f7	272	#define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */
<>	144:ef7eb2e8f9f7	273	#define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */
<>	144:ef7eb2e8f9f7	274	#define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */
<>	144:ef7eb2e8f9f7	275	#define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */
<>	144:ef7eb2e8f9f7	276	#define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */
<>	144:ef7eb2e8f9f7	277	#define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */
<>	144:ef7eb2e8f9f7	278	#define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */
<>	144:ef7eb2e8f9f7	279	#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET \| (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */
<>	144:ef7eb2e8f9f7	280
<>	144:ef7eb2e8f9f7	281
<>	144:ef7eb2e8f9f7	282	/* Internal mask for ADC mode single or differential ended: */
<>	144:ef7eb2e8f9f7	283	/* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
<>	144:ef7eb2e8f9f7	284	/* the relevant bits for: */
<>	144:ef7eb2e8f9f7	285	/* (concatenation of multiple bits used in different registers) */
<>	144:ef7eb2e8f9f7	286	/* - ADC calibration: calibration start, calibration factor get or set */
<>	144:ef7eb2e8f9f7	287	/* - ADC channels: set each ADC channel ending mode */
<>	144:ef7eb2e8f9f7	288	#define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
<>	144:ef7eb2e8f9f7	289	#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D \| ADC_CALFACT_CALFACT_S)
<>	144:ef7eb2e8f9f7	290	#define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
<>	144:ef7eb2e8f9f7	291	#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_5) /* Bit chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
<>	144:ef7eb2e8f9f7	292
<>	144:ef7eb2e8f9f7	293
<>	144:ef7eb2e8f9f7	294	/* Internal mask for ADC analog watchdog: */
<>	144:ef7eb2e8f9f7	295	/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
<>	144:ef7eb2e8f9f7	296	/* (concatenation of multiple bits used in different analog watchdogs, */
<>	144:ef7eb2e8f9f7	297	/* (feature of several watchdogs not available on all STM32 families)). */
<>	144:ef7eb2e8f9f7	298	/* - analog watchdog 1: monitored channel defined by number, */
<>	144:ef7eb2e8f9f7	299	/* selection of ADC group (ADC groups regular and-or injected). */
<>	144:ef7eb2e8f9f7	300	/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
<>	144:ef7eb2e8f9f7	301	/* selection on groups. */
<>	144:ef7eb2e8f9f7	302
<>	144:ef7eb2e8f9f7	303	/* Internal register offset for ADC analog watchdog channel configuration */
<>	144:ef7eb2e8f9f7	304	#define ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	305	#define ADC_AWD_CR2_REGOFFSET ((uint32_t)0x00100000U)
<>	144:ef7eb2e8f9f7	306	#define ADC_AWD_CR3_REGOFFSET ((uint32_t)0x00200000U)
<>	144:ef7eb2e8f9f7	307
<>	144:ef7eb2e8f9f7	308	/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
<>	144:ef7eb2e8f9f7	309	/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
<>	144:ef7eb2e8f9f7	310	#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
<>	144:ef7eb2e8f9f7	311	#define ADC_AWD_CR12_REGOFFSETGAP_VAL ((uint32_t)0x00000024U)
<>	144:ef7eb2e8f9f7	312
<>	144:ef7eb2e8f9f7	313	#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET \| ADC_AWD_CR2_REGOFFSET \| ADC_AWD_CR3_REGOFFSET)
<>	144:ef7eb2e8f9f7	314
<>	144:ef7eb2e8f9f7	315	#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
<>	144:ef7eb2e8f9f7	316	#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
<>	144:ef7eb2e8f9f7	317	#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK \| ADC_AWD_CR23_CHANNEL_MASK)
<>	144:ef7eb2e8f9f7	318
<>	144:ef7eb2e8f9f7	319	/* Internal register offset for ADC analog watchdog threshold configuration */
<>	144:ef7eb2e8f9f7	320	#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
<>	144:ef7eb2e8f9f7	321	#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
<>	144:ef7eb2e8f9f7	322	#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
<>	144:ef7eb2e8f9f7	323	#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET \| ADC_AWD_TR2_REGOFFSET \| ADC_AWD_TR3_REGOFFSET)
<>	144:ef7eb2e8f9f7	324
<>	144:ef7eb2e8f9f7	325
<>	144:ef7eb2e8f9f7	326	/* Internal mask for ADC offset: */
<>	144:ef7eb2e8f9f7	327	/* Internal register offset for ADC offset number configuration */
<>	144:ef7eb2e8f9f7	328	#define ADC_OFR1_REGOFFSET ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	329	#define ADC_OFR2_REGOFFSET ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	330	#define ADC_OFR3_REGOFFSET ((uint32_t)0x00000002U)
<>	144:ef7eb2e8f9f7	331	#define ADC_OFR4_REGOFFSET ((uint32_t)0x00000003U)
<>	144:ef7eb2e8f9f7	332	#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET \| ADC_OFR2_REGOFFSET \| ADC_OFR3_REGOFFSET \| ADC_OFR4_REGOFFSET)
<>	144:ef7eb2e8f9f7	333
<>	144:ef7eb2e8f9f7	334
<>	144:ef7eb2e8f9f7	335	/* ADC registers bits positions */
<>	144:ef7eb2e8f9f7	336	#define ADC_CFGR_RES_BITOFFSET_POS ((uint32_t) 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR_RES) */
<>	144:ef7eb2e8f9f7	337	#define ADC_CFGR_AWD1SGL_BITOFFSET_POS ((uint32_t)22U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1SGL) */
<>	144:ef7eb2e8f9f7	338	#define ADC_CFGR_AWD1EN_BITOFFSET_POS ((uint32_t)23U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1EN) */
<>	144:ef7eb2e8f9f7	339	#define ADC_CFGR_JAWD1EN_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_CFGR_JAWD1EN) */
<>	144:ef7eb2e8f9f7	340	#define ADC_TR1_HT1_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_TR1_HT1) */
<>	144:ef7eb2e8f9f7	341
<>	144:ef7eb2e8f9f7	342
<>	144:ef7eb2e8f9f7	343	/* ADC registers bits groups */
<>	144:ef7eb2e8f9f7	344	#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL \| ADC_CR_JADSTP \| ADC_CR_ADSTP \| ADC_CR_JADSTART \| ADC_CR_ADSTART \| ADC_CR_ADDIS \| ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
<>	144:ef7eb2e8f9f7	345
<>	144:ef7eb2e8f9f7	346
<>	144:ef7eb2e8f9f7	347	/* ADC internal channels related definitions */
<>	144:ef7eb2e8f9f7	348	/* Internal voltage reference VrefInt */
<>	144:ef7eb2e8f9f7	349	#define VREFINT_CAL_ADDR ((uint16_t) ((uint32_t)0x1FFF75AAU)) / Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
<>	144:ef7eb2e8f9f7	350	#define VREFINT_CAL_VREF ((uint32_t) 3000U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
<>	144:ef7eb2e8f9f7	351	/* Temperature sensor */
<>	144:ef7eb2e8f9f7	352	#define TEMPSENSOR_CAL1_ADDR ((uint16_t) ((uint32_t)0x1FFF75A8U)) / Internal temperature sensor, address of parameter TS_CAL1: On STM32L4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
<>	144:ef7eb2e8f9f7	353	#define TEMPSENSOR_CAL2_ADDR ((uint16_t) ((uint32_t)0x1FFF75CAU)) / Internal temperature sensor, address of parameter TS_CAL2: On STM32L4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
<>	144:ef7eb2e8f9f7	354	#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
<>	144:ef7eb2e8f9f7	355	#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
<>	144:ef7eb2e8f9f7	356	#define TEMPSENSOR_CAL_VREFANALOG ((uint32_t) 3000U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
<>	144:ef7eb2e8f9f7	357
<>	144:ef7eb2e8f9f7	358
<>	144:ef7eb2e8f9f7	359	/**
<>	144:ef7eb2e8f9f7	360	* @}
<>	144:ef7eb2e8f9f7	361	*/
<>	144:ef7eb2e8f9f7	362
<>	144:ef7eb2e8f9f7	363
<>	144:ef7eb2e8f9f7	364	/* Private macros ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	365	/** @defgroup ADC_LL_Private_Macros ADC Private Macros
<>	144:ef7eb2e8f9f7	366	* @{
<>	144:ef7eb2e8f9f7	367	*/
<>	144:ef7eb2e8f9f7	368
<>	144:ef7eb2e8f9f7	369	/**
<>	144:ef7eb2e8f9f7	370	* @brief Driver macro reserved for internal use: isolate bits with the
<>	144:ef7eb2e8f9f7	371	* selected mask and shift them to the register LSB
<>	144:ef7eb2e8f9f7	372	* (shift mask on register position bit 0).
<>	144:ef7eb2e8f9f7	373	* @param __BITS__ Bits in register 32 bits
<>	144:ef7eb2e8f9f7	374	* @param __MASK__ Mask in register 32 bits
<>	144:ef7eb2e8f9f7	375	* @retval Bits in register 32 bits
<>	144:ef7eb2e8f9f7	376	*/
<>	144:ef7eb2e8f9f7	377	#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
<>	144:ef7eb2e8f9f7	378	(((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
<>	144:ef7eb2e8f9f7	379
<>	144:ef7eb2e8f9f7	380	/**
<>	144:ef7eb2e8f9f7	381	* @brief Driver macro reserved for internal use: set a pointer to
<>	144:ef7eb2e8f9f7	382	* a register from a register basis from which an offset
<>	144:ef7eb2e8f9f7	383	* is applied.
<>	144:ef7eb2e8f9f7	384	* @param __REG__ Register basis from which the offset is applied.
<>	144:ef7eb2e8f9f7	385	* @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
<>	144:ef7eb2e8f9f7	386	* @retval Pointer to register address
<>	144:ef7eb2e8f9f7	387	*/
<>	144:ef7eb2e8f9f7	388	#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
<>	144:ef7eb2e8f9f7	389	((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
<>	144:ef7eb2e8f9f7	390
<>	144:ef7eb2e8f9f7	391	/**
<>	144:ef7eb2e8f9f7	392	* @}
<>	144:ef7eb2e8f9f7	393	*/
<>	144:ef7eb2e8f9f7	394
<>	144:ef7eb2e8f9f7	395
<>	144:ef7eb2e8f9f7	396	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	397	#if defined(USE_FULL_LL_DRIVER)
<>	144:ef7eb2e8f9f7	398	/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
<>	144:ef7eb2e8f9f7	399	* @{
<>	144:ef7eb2e8f9f7	400	*/
<>	144:ef7eb2e8f9f7	401
<>	144:ef7eb2e8f9f7	402	/**
<>	144:ef7eb2e8f9f7	403	* @brief Structure definition of some features of ADC common parameters
<>	144:ef7eb2e8f9f7	404	* and multimode
<>	144:ef7eb2e8f9f7	405	* (all ADC instances belonging to the same ADC common instance).
<>	144:ef7eb2e8f9f7	406	* @note The setting of these parameters by function @ref LL_ADC_CommonInit()
<>	144:ef7eb2e8f9f7	407	* is conditioned to ADC instances state (all ADC instances
<>	144:ef7eb2e8f9f7	408	* sharing the same ADC common instance):
<>	144:ef7eb2e8f9f7	409	* All ADC instances sharing the same ADC common instance must be
<>	144:ef7eb2e8f9f7	410	* disabled.
<>	144:ef7eb2e8f9f7	411	*/
<>	144:ef7eb2e8f9f7	412	typedef struct
<>	144:ef7eb2e8f9f7	413	{
<>	144:ef7eb2e8f9f7	414	uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
<>	144:ef7eb2e8f9f7	415	This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
<>	144:ef7eb2e8f9f7	416	@note On this STM32 serie, if ADC group injected is used, some
<>	144:ef7eb2e8f9f7	417	clock ratio constraints between ADC clock and AHB clock
<>	144:ef7eb2e8f9f7	418	must be respected. Refer to reference manual.
<>	144:ef7eb2e8f9f7	419
<>	144:ef7eb2e8f9f7	420	This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
<>	144:ef7eb2e8f9f7	421
<>	144:ef7eb2e8f9f7	422	#if defined(ADC_MULTIMODE_SUPPORT)
<>	144:ef7eb2e8f9f7	423	uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
<>	144:ef7eb2e8f9f7	424	This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
<>	144:ef7eb2e8f9f7	425
<>	144:ef7eb2e8f9f7	426	This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
<>	144:ef7eb2e8f9f7	427
<>	144:ef7eb2e8f9f7	428	uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
<>	144:ef7eb2e8f9f7	429	This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
<>	144:ef7eb2e8f9f7	430
<>	144:ef7eb2e8f9f7	431	This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
<>	144:ef7eb2e8f9f7	432
<>	144:ef7eb2e8f9f7	433	uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
<>	144:ef7eb2e8f9f7	434	This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
<>	144:ef7eb2e8f9f7	435
<>	144:ef7eb2e8f9f7	436	This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
<>	144:ef7eb2e8f9f7	437	#endif /* ADC_MULTIMODE_SUPPORT */
<>	144:ef7eb2e8f9f7	438
<>	144:ef7eb2e8f9f7	439	} LL_ADC_CommonInitTypeDef;
<>	144:ef7eb2e8f9f7	440
<>	144:ef7eb2e8f9f7	441	/**
<>	144:ef7eb2e8f9f7	442	* @brief Structure definition of some features of ADC instance.
<>	144:ef7eb2e8f9f7	443	* @note These parameters have an impact on ADC scope: ADC instance.
<>	144:ef7eb2e8f9f7	444	* Affects both group regular and group injected (availability
<>	144:ef7eb2e8f9f7	445	* of ADC group injected depends on STM32 families).
<>	144:ef7eb2e8f9f7	446	* Refer to corresponding unitary functions into
<>	144:ef7eb2e8f9f7	447	* @ref ADC_LL_EF_Configuration_ADC_Instance .
<>	144:ef7eb2e8f9f7	448	* @note The setting of these parameters by function @ref LL_ADC_Init()
<>	144:ef7eb2e8f9f7	449	* is conditioned to ADC state:
<>	144:ef7eb2e8f9f7	450	* ADC instance must be disabled.
<>	144:ef7eb2e8f9f7	451	* This condition is applied to all ADC features, for efficiency
<>	144:ef7eb2e8f9f7	452	* and compatibility over all STM32 families. However, the different
<>	144:ef7eb2e8f9f7	453	* features can be set under different ADC state conditions
<>	144:ef7eb2e8f9f7	454	* (setting possible with ADC enabled without conversion on going,
<>	144:ef7eb2e8f9f7	455	* ADC enabled with conversion on going, ...)
<>	144:ef7eb2e8f9f7	456	* Each feature can be updated afterwards with a unitary function
<>	144:ef7eb2e8f9f7	457	* and potentially with ADC in a different state than disabled,
<>	144:ef7eb2e8f9f7	458	* refer to description of each function for setting
<>	144:ef7eb2e8f9f7	459	* conditioned to ADC state.
<>	144:ef7eb2e8f9f7	460	*/
<>	144:ef7eb2e8f9f7	461	typedef struct
<>	144:ef7eb2e8f9f7	462	{
<>	144:ef7eb2e8f9f7	463	uint32_t Resolution; /*!< Set ADC resolution.
<>	144:ef7eb2e8f9f7	464	This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
<>	144:ef7eb2e8f9f7	465
<>	144:ef7eb2e8f9f7	466	This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
<>	144:ef7eb2e8f9f7	467
<>	144:ef7eb2e8f9f7	468	uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
<>	144:ef7eb2e8f9f7	469	This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
<>	144:ef7eb2e8f9f7	470
<>	144:ef7eb2e8f9f7	471	This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
<>	144:ef7eb2e8f9f7	472
<>	144:ef7eb2e8f9f7	473	uint32_t LowPowerMode; /*!< Set ADC low power mode.
<>	144:ef7eb2e8f9f7	474	This parameter can be a value of @ref ADC_LL_EC_LP_MODE
<>	144:ef7eb2e8f9f7	475
<>	144:ef7eb2e8f9f7	476	This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
<>	144:ef7eb2e8f9f7	477
<>	144:ef7eb2e8f9f7	478	} LL_ADC_InitTypeDef;
<>	144:ef7eb2e8f9f7	479
<>	144:ef7eb2e8f9f7	480	/**
<>	144:ef7eb2e8f9f7	481	* @brief Structure definition of some features of ADC group regular.
<>	144:ef7eb2e8f9f7	482	* @note These parameters have an impact on ADC scope: ADC group regular.
<>	144:ef7eb2e8f9f7	483	* Refer to corresponding unitary functions into
<>	144:ef7eb2e8f9f7	484	* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
<>	144:ef7eb2e8f9f7	485	* (functions with prefix "REG").
<>	144:ef7eb2e8f9f7	486	* @note The setting of these parameters by function @ref LL_ADC_REG_Init()
<>	144:ef7eb2e8f9f7	487	* is conditioned to ADC state:
<>	144:ef7eb2e8f9f7	488	* ADC instance must be disabled.
<>	144:ef7eb2e8f9f7	489	* This condition is applied to all ADC features, for efficiency
<>	144:ef7eb2e8f9f7	490	* and compatibility over all STM32 families. However, the different
<>	144:ef7eb2e8f9f7	491	* features can be set under different ADC state conditions
<>	144:ef7eb2e8f9f7	492	* (setting possible with ADC enabled without conversion on going,
<>	144:ef7eb2e8f9f7	493	* ADC enabled with conversion on going, ...)
<>	144:ef7eb2e8f9f7	494	* Each feature can be updated afterwards with a unitary function
<>	144:ef7eb2e8f9f7	495	* and potentially with ADC in a different state than disabled,
<>	144:ef7eb2e8f9f7	496	* refer to description of each function for setting
<>	144:ef7eb2e8f9f7	497	* conditioned to ADC state.
<>	144:ef7eb2e8f9f7	498	*/
<>	144:ef7eb2e8f9f7	499	typedef struct
<>	144:ef7eb2e8f9f7	500	{
<>	144:ef7eb2e8f9f7	501	uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
<>	144:ef7eb2e8f9f7	502	This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
<>	144:ef7eb2e8f9f7	503	@note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
<>	144:ef7eb2e8f9f7	504	(default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
<>	144:ef7eb2e8f9f7	505	In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
<>	144:ef7eb2e8f9f7	506
<>	144:ef7eb2e8f9f7	507	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
<>	144:ef7eb2e8f9f7	508
<>	144:ef7eb2e8f9f7	509	uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
<>	144:ef7eb2e8f9f7	510	This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
<>	144:ef7eb2e8f9f7	511
<>	144:ef7eb2e8f9f7	512	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
<>	144:ef7eb2e8f9f7	513
<>	144:ef7eb2e8f9f7	514	uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
<>	144:ef7eb2e8f9f7	515	This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
<>	144:ef7eb2e8f9f7	516	@note This parameter has an effect only if group regular sequencer is enabled
<>	144:ef7eb2e8f9f7	517	(scan length of 2 ranks or more).
<>	144:ef7eb2e8f9f7	518
<>	144:ef7eb2e8f9f7	519	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
<>	144:ef7eb2e8f9f7	520
<>	144:ef7eb2e8f9f7	521	uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
<>	144:ef7eb2e8f9f7	522	This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
<>	144:ef7eb2e8f9f7	523	Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
<>	144:ef7eb2e8f9f7	524
<>	144:ef7eb2e8f9f7	525	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
<>	144:ef7eb2e8f9f7	526
<>	144:ef7eb2e8f9f7	527	uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
<>	144:ef7eb2e8f9f7	528	This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
<>	144:ef7eb2e8f9f7	529
<>	144:ef7eb2e8f9f7	530	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
<>	144:ef7eb2e8f9f7	531
<>	144:ef7eb2e8f9f7	532	uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
<>	144:ef7eb2e8f9f7	533	data preserved or overwritten.
<>	144:ef7eb2e8f9f7	534	This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
<>	144:ef7eb2e8f9f7	535
<>	144:ef7eb2e8f9f7	536	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
<>	144:ef7eb2e8f9f7	537
<>	144:ef7eb2e8f9f7	538	} LL_ADC_REG_InitTypeDef;
<>	144:ef7eb2e8f9f7	539
<>	144:ef7eb2e8f9f7	540	/**
<>	144:ef7eb2e8f9f7	541	* @brief Structure definition of some features of ADC group injected.
<>	144:ef7eb2e8f9f7	542	* @note These parameters have an impact on ADC scope: ADC group injected.
<>	144:ef7eb2e8f9f7	543	* Refer to corresponding unitary functions into
<>	144:ef7eb2e8f9f7	544	* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
<>	144:ef7eb2e8f9f7	545	* (functions with prefix "INJ").
<>	144:ef7eb2e8f9f7	546	* @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
<>	144:ef7eb2e8f9f7	547	* is conditioned to ADC state:
<>	144:ef7eb2e8f9f7	548	* ADC instance must be disabled.
<>	144:ef7eb2e8f9f7	549	* This condition is applied to all ADC features, for efficiency
<>	144:ef7eb2e8f9f7	550	* and compatibility over all STM32 families. However, the different
<>	144:ef7eb2e8f9f7	551	* features can be set under different ADC state conditions
<>	144:ef7eb2e8f9f7	552	* (setting possible with ADC enabled without conversion on going,
<>	144:ef7eb2e8f9f7	553	* ADC enabled with conversion on going, ...)
<>	144:ef7eb2e8f9f7	554	* Each feature can be updated afterwards with a unitary function
<>	144:ef7eb2e8f9f7	555	* and potentially with ADC in a different state than disabled,
<>	144:ef7eb2e8f9f7	556	* refer to description of each function for setting
<>	144:ef7eb2e8f9f7	557	* conditioned to ADC state.
<>	144:ef7eb2e8f9f7	558	*/
<>	144:ef7eb2e8f9f7	559	typedef struct
<>	144:ef7eb2e8f9f7	560	{
<>	144:ef7eb2e8f9f7	561	uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
<>	144:ef7eb2e8f9f7	562	This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
<>	144:ef7eb2e8f9f7	563	@note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
<>	144:ef7eb2e8f9f7	564	(default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
<>	144:ef7eb2e8f9f7	565	In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().
<>	144:ef7eb2e8f9f7	566
<>	144:ef7eb2e8f9f7	567	This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
<>	144:ef7eb2e8f9f7	568
<>	144:ef7eb2e8f9f7	569	uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
<>	144:ef7eb2e8f9f7	570	This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
<>	144:ef7eb2e8f9f7	571
<>	144:ef7eb2e8f9f7	572	This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
<>	144:ef7eb2e8f9f7	573
<>	144:ef7eb2e8f9f7	574	uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
<>	144:ef7eb2e8f9f7	575	This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
<>	144:ef7eb2e8f9f7	576	@note This parameter has an effect only if group injected sequencer is enabled
<>	144:ef7eb2e8f9f7	577	(scan length of 2 ranks or more).
<>	144:ef7eb2e8f9f7	578
<>	144:ef7eb2e8f9f7	579	This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
<>	144:ef7eb2e8f9f7	580
<>	144:ef7eb2e8f9f7	581	uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
<>	144:ef7eb2e8f9f7	582	This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
<>	144:ef7eb2e8f9f7	583	Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
<>	144:ef7eb2e8f9f7	584
<>	144:ef7eb2e8f9f7	585	This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
<>	144:ef7eb2e8f9f7	586
<>	144:ef7eb2e8f9f7	587	} LL_ADC_INJ_InitTypeDef;
<>	144:ef7eb2e8f9f7	588
<>	144:ef7eb2e8f9f7	589	/**
<>	144:ef7eb2e8f9f7	590	* @}
<>	144:ef7eb2e8f9f7	591	*/
<>	144:ef7eb2e8f9f7	592	#endif /* USE_FULL_LL_DRIVER */
<>	144:ef7eb2e8f9f7	593
<>	144:ef7eb2e8f9f7	594	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	595	/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
<>	144:ef7eb2e8f9f7	596	* @{
<>	144:ef7eb2e8f9f7	597	*/
<>	144:ef7eb2e8f9f7	598
<>	144:ef7eb2e8f9f7	599	/** @defgroup ADC_LL_EC_FLAG ADC flags
<>	144:ef7eb2e8f9f7	600	* @brief Flags defines which can be used with LL_ADC_ReadReg function
<>	144:ef7eb2e8f9f7	601	* @{
<>	144:ef7eb2e8f9f7	602	*/
<>	144:ef7eb2e8f9f7	603	#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /!< ADC flag ADC instance ready /
<>	144:ef7eb2e8f9f7	604	#define LL_ADC_FLAG_EOC ADC_ISR_EOC /!< ADC flag ADC group regular end of unitary conversion /
<>	144:ef7eb2e8f9f7	605	#define LL_ADC_FLAG_EOS ADC_ISR_EOS /!< ADC flag ADC group regular end of sequence conversions /
<>	144:ef7eb2e8f9f7	606	#define LL_ADC_FLAG_OVR ADC_ISR_OVR /!< ADC flag ADC group regular overrun /
<>	144:ef7eb2e8f9f7	607	#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /!< ADC flag ADC group regular end of sampling phase /
<>	144:ef7eb2e8f9f7	608	#define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /!< ADC flag ADC group injected end of unitary conversion /
<>	144:ef7eb2e8f9f7	609	#define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /!< ADC flag ADC group injected end of sequence conversions /
<>	144:ef7eb2e8f9f7	610	#define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /!< ADC flag ADC group injected contexts queue overflow /
<>	144:ef7eb2e8f9f7	611	#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /!< ADC flag ADC analog watchdog 1 /
<>	144:ef7eb2e8f9f7	612	#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /!< ADC flag ADC analog watchdog 2 /
<>	144:ef7eb2e8f9f7	613	#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /!< ADC flag ADC analog watchdog 3 /
<>	144:ef7eb2e8f9f7	614	#if defined(ADC_MULTIMODE_SUPPORT)
<>	144:ef7eb2e8f9f7	615	#define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /!< ADC flag ADC multimode master instance ready /
<>	144:ef7eb2e8f9f7	616	#define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /!< ADC flag ADC multimode slave instance ready /
<>	144:ef7eb2e8f9f7	617	#define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /!< ADC flag ADC multimode master group regular end of unitary conversion /
<>	144:ef7eb2e8f9f7	618	#define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /!< ADC flag ADC multimode slave group regular end of unitary conversion /
<>	144:ef7eb2e8f9f7	619	#define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /!< ADC flag ADC multimode master group regular end of sequence conversions /
<>	144:ef7eb2e8f9f7	620	#define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /!< ADC flag ADC multimode slave group regular end of sequence conversions /
<>	144:ef7eb2e8f9f7	621	#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /!< ADC flag ADC multimode master group regular overrun /
<>	144:ef7eb2e8f9f7	622	#define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /!< ADC flag ADC multimode slave group regular overrun /
<>	144:ef7eb2e8f9f7	623	#define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /!< ADC flag ADC multimode master group regular end of sampling phase /
<>	144:ef7eb2e8f9f7	624	#define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /!< ADC flag ADC multimode slave group regular end of sampling phase /
<>	144:ef7eb2e8f9f7	625	#define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /!< ADC flag ADC multimode master group injected end of unitary conversion /
<>	144:ef7eb2e8f9f7	626	#define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /!< ADC flag ADC multimode slave group injected end of unitary conversion /
<>	144:ef7eb2e8f9f7	627	#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /!< ADC flag ADC multimode master group injected end of sequence conversions /
<>	144:ef7eb2e8f9f7	628	#define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /!< ADC flag ADC multimode slave group injected end of sequence conversions /
<>	144:ef7eb2e8f9f7	629	#define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /!< ADC flag ADC multimode master group injected contexts queue overflow /
<>	144:ef7eb2e8f9f7	630	#define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /!< ADC flag ADC multimode slave group injected contexts queue overflow /
<>	144:ef7eb2e8f9f7	631	#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /!< ADC flag ADC multimode master analog watchdog 1 of the ADC master /
<>	144:ef7eb2e8f9f7	632	#define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave /
<>	144:ef7eb2e8f9f7	633	#define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /!< ADC flag ADC multimode master analog watchdog 2 of the ADC master /
<>	144:ef7eb2e8f9f7	634	#define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave /
<>	144:ef7eb2e8f9f7	635	#define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /!< ADC flag ADC multimode master analog watchdog 3 of the ADC master /
<>	144:ef7eb2e8f9f7	636	#define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave /
<>	144:ef7eb2e8f9f7	637	#endif
<>	144:ef7eb2e8f9f7	638	/**
<>	144:ef7eb2e8f9f7	639	* @}
<>	144:ef7eb2e8f9f7	640	*/
<>	144:ef7eb2e8f9f7	641
<>	144:ef7eb2e8f9f7	642	/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
<>	144:ef7eb2e8f9f7	643	* @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
<>	144:ef7eb2e8f9f7	644	* @{
<>	144:ef7eb2e8f9f7	645	*/
<>	144:ef7eb2e8f9f7	646	#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /!< ADC interruption ADC instance ready /
<>	144:ef7eb2e8f9f7	647	#define LL_ADC_IT_EOC ADC_IER_EOCIE /!< ADC interruption ADC group regular end of unitary conversion /
<>	144:ef7eb2e8f9f7	648	#define LL_ADC_IT_EOS ADC_IER_EOSIE /!< ADC interruption ADC group regular end of sequence conversions /
<>	144:ef7eb2e8f9f7	649	#define LL_ADC_IT_OVR ADC_IER_OVRIE /!< ADC interruption ADC group regular overrun /
<>	144:ef7eb2e8f9f7	650	#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /!< ADC interruption ADC group regular end of sampling phase /
<>	144:ef7eb2e8f9f7	651	#define LL_ADC_IT_JEOC ADC_IER_JEOCIE /!< ADC interruption ADC group injected end of unitary conversion /
<>	144:ef7eb2e8f9f7	652	#define LL_ADC_IT_JEOS ADC_IER_JEOSIE /!< ADC interruption ADC group injected end of sequence conversions /
<>	144:ef7eb2e8f9f7	653	#define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /!< ADC interruption ADC group injected contexts queue overflow /
<>	144:ef7eb2e8f9f7	654	#define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /!< ADC interruption ADC analog watchdog 1 /
<>	144:ef7eb2e8f9f7	655	#define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /!< ADC interruption ADC analog watchdog 2 /
<>	144:ef7eb2e8f9f7	656	#define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /!< ADC interruption ADC analog watchdog 3 /
<>	144:ef7eb2e8f9f7	657	/**
<>	144:ef7eb2e8f9f7	658	* @}
<>	144:ef7eb2e8f9f7	659	*/
<>	144:ef7eb2e8f9f7	660
<>	144:ef7eb2e8f9f7	661	/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
<>	144:ef7eb2e8f9f7	662	* @{
<>	144:ef7eb2e8f9f7	663	*/
<>	144:ef7eb2e8f9f7	664	/* List of ADC registers intended to be used (most commonly) with */
<>	144:ef7eb2e8f9f7	665	/* DMA transfer. */
<>	144:ef7eb2e8f9f7	666	/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
<>	144:ef7eb2e8f9f7	667	#define LL_ADC_DMA_REG_REGULAR_DATA ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
<>	144:ef7eb2e8f9f7	668	#if defined(ADC_MULTIMODE_SUPPORT)
<>	144:ef7eb2e8f9f7	669	#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI ((uint32_t)0x00000001U) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
<>	144:ef7eb2e8f9f7	670	#endif
<>	144:ef7eb2e8f9f7	671	/**
<>	144:ef7eb2e8f9f7	672	* @}
<>	144:ef7eb2e8f9f7	673	*/
<>	144:ef7eb2e8f9f7	674
<>	144:ef7eb2e8f9f7	675	/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
<>	144:ef7eb2e8f9f7	676	* @{
<>	144:ef7eb2e8f9f7	677	*/
<>	144:ef7eb2e8f9f7	678	#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /!< ADC synchronous clock derived from AHB clock without prescaler /
<>	144:ef7eb2e8f9f7	679	#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /!< ADC synchronous clock derived from AHB clock with prescaler division by 2 /
<>	144:ef7eb2e8f9f7	680	#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 \| ADC_CCR_CKMODE_0) /!< ADC synchronous clock derived from AHB clock with prescaler division by 4 /
<>	144:ef7eb2e8f9f7	681	#define LL_ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000U) /!< ADC asynchronous clock without prescaler /
<>	144:ef7eb2e8f9f7	682	#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /!< ADC asynchronous clock with prescaler division by 2 /
<>	144:ef7eb2e8f9f7	683	#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /!< ADC asynchronous clock with prescaler division by 4 /
<>	144:ef7eb2e8f9f7	684	#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 \| ADC_CCR_PRESC_0) /!< ADC asynchronous clock with prescaler division by 6 /
<>	144:ef7eb2e8f9f7	685	#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /!< ADC asynchronous clock with prescaler division by 8 /
<>	144:ef7eb2e8f9f7	686	#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 \| ADC_CCR_PRESC_0) /!< ADC asynchronous clock with prescaler division by 10 /
<>	144:ef7eb2e8f9f7	687	#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 \| ADC_CCR_PRESC_1 ) /!< ADC asynchronous clock with prescaler division by 12 /
<>	144:ef7eb2e8f9f7	688	#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 \| ADC_CCR_PRESC_1 \| ADC_CCR_PRESC_0) /!< ADC asynchronous clock with prescaler division by 16 /
<>	144:ef7eb2e8f9f7	689	#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /!< ADC asynchronous clock with prescaler division by 32 /
<>	144:ef7eb2e8f9f7	690	#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 \| ADC_CCR_PRESC_0) /!< ADC asynchronous clock with prescaler division by 64 /
<>	144:ef7eb2e8f9f7	691	#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 \| ADC_CCR_PRESC_1) /!< ADC asynchronous clock with prescaler division by 128 /
<>	144:ef7eb2e8f9f7	692	#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 \| ADC_CCR_PRESC_1 \| ADC_CCR_PRESC_0) /!< ADC asynchronous clock with prescaler division by 256 /
<>	144:ef7eb2e8f9f7	693	/**
<>	144:ef7eb2e8f9f7	694	* @}
<>	144:ef7eb2e8f9f7	695	*/
<>	144:ef7eb2e8f9f7	696
<>	144:ef7eb2e8f9f7	697	/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
<>	144:ef7eb2e8f9f7	698	* @{
<>	144:ef7eb2e8f9f7	699	*/
<>	144:ef7eb2e8f9f7	700	/* Note: Other measurement paths to internal channels may be available */
<>	144:ef7eb2e8f9f7	701	/* (connections to other peripherals). */
<>	144:ef7eb2e8f9f7	702	/* If they are not listed below, they do not require any specific */
<>	144:ef7eb2e8f9f7	703	/* path enable. In this case, Access to measurement path is done */
<>	144:ef7eb2e8f9f7	704	/* only by selecting the corresponding ADC internal channel. */
<>	144:ef7eb2e8f9f7	705	#define LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)/!< ADC measurement pathes all disabled /
<>	144:ef7eb2e8f9f7	706	#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /!< ADC measurement path to internal channel VrefInt /
<>	144:ef7eb2e8f9f7	707	#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /!< ADC measurement path to internal channel temperature sensor /
<>	144:ef7eb2e8f9f7	708	#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /!< ADC measurement path to internal channel Vbat /
<>	144:ef7eb2e8f9f7	709	/**
<>	144:ef7eb2e8f9f7	710	* @}
<>	144:ef7eb2e8f9f7	711	*/
<>	144:ef7eb2e8f9f7	712
<>	144:ef7eb2e8f9f7	713	/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
<>	144:ef7eb2e8f9f7	714	* @{
<>	144:ef7eb2e8f9f7	715	*/
<>	144:ef7eb2e8f9f7	716	#define LL_ADC_RESOLUTION_12B ((uint32_t)0x00000000U) /!< ADC resolution 12 bits /
<>	144:ef7eb2e8f9f7	717	#define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0) /!< ADC resolution 10 bits /
<>	144:ef7eb2e8f9f7	718	#define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 ) /!< ADC resolution 8 bits /
<>	144:ef7eb2e8f9f7	719	#define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 \| ADC_CFGR_RES_0) /!< ADC resolution 6 bits /
<>	144:ef7eb2e8f9f7	720	/**
<>	144:ef7eb2e8f9f7	721	* @}
<>	144:ef7eb2e8f9f7	722	*/
<>	144:ef7eb2e8f9f7	723
<>	144:ef7eb2e8f9f7	724	/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
<>	144:ef7eb2e8f9f7	725	* @{
<>	144:ef7eb2e8f9f7	726	*/
<>	144:ef7eb2e8f9f7	727	#define LL_ADC_DATA_ALIGN_RIGHT ((uint32_t)0x00000000U)/!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)/
<>	144:ef7eb2e8f9f7	728	#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)/
<>	144:ef7eb2e8f9f7	729	/**
<>	144:ef7eb2e8f9f7	730	* @}
<>	144:ef7eb2e8f9f7	731	*/
<>	144:ef7eb2e8f9f7	732
<>	144:ef7eb2e8f9f7	733	/** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
<>	144:ef7eb2e8f9f7	734	* @{
<>	144:ef7eb2e8f9f7	735	*/
<>	144:ef7eb2e8f9f7	736	#define LL_ADC_LP_MODE_NONE ((uint32_t)0x00000000U) /!< No ADC low power mode activated /
<>	144:ef7eb2e8f9f7	737	#define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). /
<>	144:ef7eb2e8f9f7	738	/**
<>	144:ef7eb2e8f9f7	739	* @}
<>	144:ef7eb2e8f9f7	740	*/
<>	144:ef7eb2e8f9f7	741
<>	144:ef7eb2e8f9f7	742	/** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number
<>	144:ef7eb2e8f9f7	743	* @{
<>	144:ef7eb2e8f9f7	744	*/
<>	144:ef7eb2e8f9f7	745	#define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) /
<>	144:ef7eb2e8f9f7	746	#define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) /
<>	144:ef7eb2e8f9f7	747	#define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) /
<>	144:ef7eb2e8f9f7	748	#define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) /
<>	144:ef7eb2e8f9f7	749	/**
<>	144:ef7eb2e8f9f7	750	* @}
<>	144:ef7eb2e8f9f7	751	*/
<>	144:ef7eb2e8f9f7	752
<>	144:ef7eb2e8f9f7	753	/** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
<>	144:ef7eb2e8f9f7	754	* @{
<>	144:ef7eb2e8f9f7	755	*/
<>	144:ef7eb2e8f9f7	756	#define LL_ADC_OFFSET_DISABLE ((uint32_t)0x00000000U)/!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) /
<>	144:ef7eb2e8f9f7	757	#define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) /
<>	144:ef7eb2e8f9f7	758	/**
<>	144:ef7eb2e8f9f7	759	* @}
<>	144:ef7eb2e8f9f7	760	*/
<>	144:ef7eb2e8f9f7	761
<>	144:ef7eb2e8f9f7	762	/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
<>	144:ef7eb2e8f9f7	763	* @{
<>	144:ef7eb2e8f9f7	764	*/
<>	144:ef7eb2e8f9f7	765	#define LL_ADC_GROUP_REGULAR ((uint32_t)0x00000001U) /!< ADC group regular (available on all STM32 devices) /
<>	144:ef7eb2e8f9f7	766	#define LL_ADC_GROUP_INJECTED ((uint32_t)0x00000002U) /!< ADC group injected (not available on all STM32 devices)/
<>	144:ef7eb2e8f9f7	767	#define LL_ADC_GROUP_REGULAR_INJECTED ((uint32_t)0x00000003U) /!< ADC both groups regular and injected /
<>	144:ef7eb2e8f9f7	768	/**
<>	144:ef7eb2e8f9f7	769	* @}
<>	144:ef7eb2e8f9f7	770	*/
<>	144:ef7eb2e8f9f7	771
<>	144:ef7eb2e8f9f7	772	/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
<>	144:ef7eb2e8f9f7	773	* @{
<>	144:ef7eb2e8f9f7	774	*/
<>	144:ef7eb2e8f9f7	775	#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER \| ADC_CHANNEL_0_SMP \| ADC_CHANNEL_0_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 /
<>	144:ef7eb2e8f9f7	776	#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER \| ADC_CHANNEL_1_SMP \| ADC_CHANNEL_1_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 /
<>	144:ef7eb2e8f9f7	777	#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER \| ADC_CHANNEL_2_SMP \| ADC_CHANNEL_2_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 /
<>	144:ef7eb2e8f9f7	778	#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER \| ADC_CHANNEL_3_SMP \| ADC_CHANNEL_3_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 /
<>	144:ef7eb2e8f9f7	779	#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER \| ADC_CHANNEL_4_SMP \| ADC_CHANNEL_4_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 /
<>	144:ef7eb2e8f9f7	780	#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER \| ADC_CHANNEL_5_SMP \| ADC_CHANNEL_5_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 /
<>	144:ef7eb2e8f9f7	781	#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER \| ADC_CHANNEL_6_SMP \| ADC_CHANNEL_6_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 /
<>	144:ef7eb2e8f9f7	782	#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER \| ADC_CHANNEL_7_SMP \| ADC_CHANNEL_7_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 /
<>	144:ef7eb2e8f9f7	783	#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER \| ADC_CHANNEL_8_SMP \| ADC_CHANNEL_8_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 /
<>	144:ef7eb2e8f9f7	784	#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER \| ADC_CHANNEL_9_SMP \| ADC_CHANNEL_9_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 /
<>	144:ef7eb2e8f9f7	785	#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER \| ADC_CHANNEL_10_SMP \| ADC_CHANNEL_10_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 /
<>	144:ef7eb2e8f9f7	786	#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER \| ADC_CHANNEL_11_SMP \| ADC_CHANNEL_11_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 /
<>	144:ef7eb2e8f9f7	787	#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER \| ADC_CHANNEL_12_SMP \| ADC_CHANNEL_12_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 /
<>	144:ef7eb2e8f9f7	788	#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER \| ADC_CHANNEL_13_SMP \| ADC_CHANNEL_13_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 /
<>	144:ef7eb2e8f9f7	789	#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER \| ADC_CHANNEL_14_SMP \| ADC_CHANNEL_14_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 /
<>	144:ef7eb2e8f9f7	790	#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER \| ADC_CHANNEL_15_SMP \| ADC_CHANNEL_15_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 /
<>	144:ef7eb2e8f9f7	791	#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER \| ADC_CHANNEL_16_SMP \| ADC_CHANNEL_16_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 /
<>	144:ef7eb2e8f9f7	792	#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER \| ADC_CHANNEL_17_SMP \| ADC_CHANNEL_17_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 /
<>	144:ef7eb2e8f9f7	793	#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER \| ADC_CHANNEL_18_SMP \| ADC_CHANNEL_18_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 /
<>	144:ef7eb2e8f9f7	794	#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32L4, ADC channel available only on ADC instance: ADC1. /
<>	144:ef7eb2e8f9f7	795	#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_17 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to Temperature sensor. On STM32L4, ADC channel available only on ADC instances: ADC1, ADC3. /
<>	144:ef7eb2e8f9f7	796	#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32L4, ADC channel available only on ADC instances: ADC1, ADC3. /
<>	144:ef7eb2e8f9f7	797	#if defined(ADC1) && !defined(ADC2)
<>	144:ef7eb2e8f9f7	798	#define LL_ADC_CHANNEL_DAC1CH1 (LL_ADC_CHANNEL_17 \| ADC_CHANNEL_ID_INTERNAL_CH \| ADC_CHANNEL_ID_INTERNAL_CH_2) /!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC1. This channel is shared with ADC internal channel connected to temperature sensor, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). /
<>	144:ef7eb2e8f9f7	799	#define LL_ADC_CHANNEL_DAC1CH2 (LL_ADC_CHANNEL_18 \| ADC_CHANNEL_ID_INTERNAL_CH \| ADC_CHANNEL_ID_INTERNAL_CH_2) /!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC1. This channel is shared with ADC internal channel connected to Vbat, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). /
<>	144:ef7eb2e8f9f7	800	#elif defined(ADC2)
<>	144:ef7eb2e8f9f7	801	#define LL_ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_17 \| ADC_CHANNEL_ID_INTERNAL_CH \| ADC_CHANNEL_ID_INTERNAL_CH_2) /!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 /
<>	144:ef7eb2e8f9f7	802	#define LL_ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_18 \| ADC_CHANNEL_ID_INTERNAL_CH \| ADC_CHANNEL_ID_INTERNAL_CH_2) /!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 /
<>	144:ef7eb2e8f9f7	803	#if defined(ADC3)
<>	144:ef7eb2e8f9f7	804	#define LL_ADC_CHANNEL_DAC1CH1_ADC3 (LL_ADC_CHANNEL_14 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC3 /
<>	144:ef7eb2e8f9f7	805	#define LL_ADC_CHANNEL_DAC1CH2_ADC3 (LL_ADC_CHANNEL_15 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC3 /
<>	144:ef7eb2e8f9f7	806	#endif
<>	144:ef7eb2e8f9f7	807	#endif
<>	144:ef7eb2e8f9f7	808	/**
<>	144:ef7eb2e8f9f7	809	* @}
<>	144:ef7eb2e8f9f7	810	*/
<>	144:ef7eb2e8f9f7	811
<>	144:ef7eb2e8f9f7	812	/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
<>	144:ef7eb2e8f9f7	813	* @{
<>	144:ef7eb2e8f9f7	814	*/
<>	144:ef7eb2e8f9f7	815	#define LL_ADC_REG_TRIG_SOFTWARE ((uint32_t)0x00000000U) /!< ADC group regular conversion trigger internal: SW start. /
<>	144:ef7eb2e8f9f7	816	#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	817	#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	818	#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	819	#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	820	#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	821	#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_1 \| ADC_CFGR_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	822	#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 \| ADC_CFGR_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	823	#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	824	#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1 \| ADC_CFGR_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	825	#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	826	#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	827	#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	828	#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1 \| ADC_CFGR_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	829	#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	830	#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	831	#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	832	/**
<>	144:ef7eb2e8f9f7	833	* @}
<>	144:ef7eb2e8f9f7	834	*/
<>	144:ef7eb2e8f9f7	835
<>	144:ef7eb2e8f9f7	836	/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
<>	144:ef7eb2e8f9f7	837	* @{
<>	144:ef7eb2e8f9f7	838	*/
<>	144:ef7eb2e8f9f7	839	#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0) /!< ADC group regular conversion trigger polarity set to rising edge /
<>	144:ef7eb2e8f9f7	840	#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 ) /!< ADC group regular conversion trigger polarity set to falling edge /
<>	144:ef7eb2e8f9f7	841	#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 \| ADC_CFGR_EXTEN_0) /!< ADC group regular conversion trigger polarity set to both rising and falling edges /
<>	144:ef7eb2e8f9f7	842	/**
<>	144:ef7eb2e8f9f7	843	* @}
<>	144:ef7eb2e8f9f7	844	*/
<>	144:ef7eb2e8f9f7	845
<>	144:ef7eb2e8f9f7	846	/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
<>	144:ef7eb2e8f9f7	847	* @{
<>	144:ef7eb2e8f9f7	848	*/
<>	144:ef7eb2e8f9f7	849	#define LL_ADC_REG_CONV_SINGLE ((uint32_t)0x00000000U) /!< ADC conversions are performed in single mode: one conversion per trigger /
<>	144:ef7eb2e8f9f7	850	#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically /
<>	144:ef7eb2e8f9f7	851	/**
<>	144:ef7eb2e8f9f7	852	* @}
<>	144:ef7eb2e8f9f7	853	*/
<>	144:ef7eb2e8f9f7	854
<>	144:ef7eb2e8f9f7	855	/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
<>	144:ef7eb2e8f9f7	856	* @{
<>	144:ef7eb2e8f9f7	857	*/
<>	144:ef7eb2e8f9f7	858	#define LL_ADC_REG_DMA_TRANSFER_NONE ((uint32_t)0x00000000U) /!< ADC conversions are not transferred by DMA /
<>	144:ef7eb2e8f9f7	859	#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN) /!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. /
<>	144:ef7eb2e8f9f7	860	#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG \| ADC_CFGR_DMAEN) /!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. /
<>	144:ef7eb2e8f9f7	861	/**
<>	144:ef7eb2e8f9f7	862	* @}
<>	144:ef7eb2e8f9f7	863	*/
<>	144:ef7eb2e8f9f7	864
<>	144:ef7eb2e8f9f7	865	/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
<>	144:ef7eb2e8f9f7	866	* @{
<>	144:ef7eb2e8f9f7	867	*/
<>	144:ef7eb2e8f9f7	868	#define LL_ADC_REG_OVR_DATA_PRESERVED ((uint32_t)0x00000000U)/!< ADC group regular behavior in case of overrun: data preserved /
<>	144:ef7eb2e8f9f7	869	#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /!< ADC group regular behavior in case of overrun: data overwritten /
<>	144:ef7eb2e8f9f7	870	/**
<>	144:ef7eb2e8f9f7	871	* @}
<>	144:ef7eb2e8f9f7	872	*/
<>	144:ef7eb2e8f9f7	873
<>	144:ef7eb2e8f9f7	874	/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
<>	144:ef7eb2e8f9f7	875	* @{
<>	144:ef7eb2e8f9f7	876	*/
<>	144:ef7eb2e8f9f7	877	#define LL_ADC_REG_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) /
<>	144:ef7eb2e8f9f7	878	#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 2 ranks in the sequence /
<>	144:ef7eb2e8f9f7	879	#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /!< ADC group regular sequencer enable with 3 ranks in the sequence /
<>	144:ef7eb2e8f9f7	880	#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 4 ranks in the sequence /
<>	144:ef7eb2e8f9f7	881	#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /!< ADC group regular sequencer enable with 5 ranks in the sequence /
<>	144:ef7eb2e8f9f7	882	#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 6 ranks in the sequence /
<>	144:ef7eb2e8f9f7	883	#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 \| ADC_SQR1_L_1 ) /!< ADC group regular sequencer enable with 7 ranks in the sequence /
<>	144:ef7eb2e8f9f7	884	#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 \| ADC_SQR1_L_1 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 8 ranks in the sequence /
<>	144:ef7eb2e8f9f7	885	#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /!< ADC group regular sequencer enable with 9 ranks in the sequence /
<>	144:ef7eb2e8f9f7	886	#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 10 ranks in the sequence /
<>	144:ef7eb2e8f9f7	887	#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_1 ) /!< ADC group regular sequencer enable with 11 ranks in the sequence /
<>	144:ef7eb2e8f9f7	888	#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_1 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 12 ranks in the sequence /
<>	144:ef7eb2e8f9f7	889	#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 ) /!< ADC group regular sequencer enable with 13 ranks in the sequence /
<>	144:ef7eb2e8f9f7	890	#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 14 ranks in the sequence /
<>	144:ef7eb2e8f9f7	891	#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 \| ADC_SQR1_L_1 ) /!< ADC group regular sequencer enable with 15 ranks in the sequence /
<>	144:ef7eb2e8f9f7	892	#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 \| ADC_SQR1_L_1 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 16 ranks in the sequence /
<>	144:ef7eb2e8f9f7	893	/**
<>	144:ef7eb2e8f9f7	894	* @}
<>	144:ef7eb2e8f9f7	895	*/
<>	144:ef7eb2e8f9f7	896
<>	144:ef7eb2e8f9f7	897	/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
<>	144:ef7eb2e8f9f7	898	* @{
<>	144:ef7eb2e8f9f7	899	*/
<>	144:ef7eb2e8f9f7	900	#define LL_ADC_REG_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U) /!< ADC group regular sequencer discontinuous mode disable /
<>	144:ef7eb2e8f9f7	901	#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank /
<>	144:ef7eb2e8f9f7	902	#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 \| ADC_CFGR_DISCEN) /!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks /
<>	144:ef7eb2e8f9f7	903	#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 \| ADC_CFGR_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks /
<>	144:ef7eb2e8f9f7	904	#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 \| ADC_CFGR_DISCNUM_0 \| ADC_CFGR_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks /
<>	144:ef7eb2e8f9f7	905	#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 \| ADC_CFGR_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks /
<>	144:ef7eb2e8f9f7	906	#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 \| ADC_CFGR_DISCNUM_0 \| ADC_CFGR_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks /
<>	144:ef7eb2e8f9f7	907	#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 \| ADC_CFGR_DISCNUM_1 \| ADC_CFGR_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks /
<>	144:ef7eb2e8f9f7	908	#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 \| ADC_CFGR_DISCNUM_1 \| ADC_CFGR_DISCNUM_0 \| ADC_CFGR_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks /
<>	144:ef7eb2e8f9f7	909	/**
<>	144:ef7eb2e8f9f7	910	* @}
<>	144:ef7eb2e8f9f7	911	*/
<>	144:ef7eb2e8f9f7	912
<>	144:ef7eb2e8f9f7	913	/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
<>	144:ef7eb2e8f9f7	914	* @{
<>	144:ef7eb2e8f9f7	915	*/
<>	144:ef7eb2e8f9f7	916	#define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 1 /
<>	144:ef7eb2e8f9f7	917	#define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 2 /
<>	144:ef7eb2e8f9f7	918	#define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 3 /
<>	144:ef7eb2e8f9f7	919	#define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 4 /
<>	144:ef7eb2e8f9f7	920	#define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 5 /
<>	144:ef7eb2e8f9f7	921	#define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 6 /
<>	144:ef7eb2e8f9f7	922	#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 7 /
<>	144:ef7eb2e8f9f7	923	#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 8 /
<>	144:ef7eb2e8f9f7	924	#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 9 /
<>	144:ef7eb2e8f9f7	925	#define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 10 /
<>	144:ef7eb2e8f9f7	926	#define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 11 /
<>	144:ef7eb2e8f9f7	927	#define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 12 /
<>	144:ef7eb2e8f9f7	928	#define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 13 /
<>	144:ef7eb2e8f9f7	929	#define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 14 /
<>	144:ef7eb2e8f9f7	930	#define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET \| ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 15 /
<>	144:ef7eb2e8f9f7	931	#define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET \| ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 16 /
<>	144:ef7eb2e8f9f7	932	/**
<>	144:ef7eb2e8f9f7	933	* @}
<>	144:ef7eb2e8f9f7	934	*/
<>	144:ef7eb2e8f9f7	935
<>	144:ef7eb2e8f9f7	936	/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
<>	144:ef7eb2e8f9f7	937	* @{
<>	144:ef7eb2e8f9f7	938	*/
<>	144:ef7eb2e8f9f7	939	#define LL_ADC_INJ_TRIG_SOFTWARE ((uint32_t)0x00000000U) /!< ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	940	#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	941	#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	942	#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	943	#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	944	#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	945	#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	946	#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	947	#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	948	#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	949	#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	950	#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	951	#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	952	#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	953	#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_1 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	954	#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	955	#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). /
<>	144:ef7eb2e8f9f7	956	/**
<>	144:ef7eb2e8f9f7	957	* @}
<>	144:ef7eb2e8f9f7	958	*/
<>	144:ef7eb2e8f9f7	959
<>	144:ef7eb2e8f9f7	960	/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
<>	144:ef7eb2e8f9f7	961	* @{
<>	144:ef7eb2e8f9f7	962	*/
<>	144:ef7eb2e8f9f7	963	#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /!< ADC group injected conversion trigger polarity set to rising edge /
<>	144:ef7eb2e8f9f7	964	#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /!< ADC group injected conversion trigger polarity set to falling edge /
<>	144:ef7eb2e8f9f7	965	#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 \| ADC_JSQR_JEXTEN_0) /!< ADC group injected conversion trigger polarity set to both rising and falling edges /
<>	144:ef7eb2e8f9f7	966	/**
<>	144:ef7eb2e8f9f7	967	* @}
<>	144:ef7eb2e8f9f7	968	*/
<>	144:ef7eb2e8f9f7	969
<>	144:ef7eb2e8f9f7	970	/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
<>	144:ef7eb2e8f9f7	971	* @{
<>	144:ef7eb2e8f9f7	972	*/
<>	144:ef7eb2e8f9f7	973	#define LL_ADC_INJ_TRIG_INDEPENDENT ((uint32_t)0x00000000U)/!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. /
<>	144:ef7eb2e8f9f7	974	#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. /
<>	144:ef7eb2e8f9f7	975	/**
<>	144:ef7eb2e8f9f7	976	* @}
<>	144:ef7eb2e8f9f7	977	*/
<>	144:ef7eb2e8f9f7	978
<>	144:ef7eb2e8f9f7	979	/** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode
<>	144:ef7eb2e8f9f7	980	* @{
<>	144:ef7eb2e8f9f7	981	*/
<>	144:ef7eb2e8f9f7	982	#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE ((uint32_t)0x00000000U)/* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
<>	144:ef7eb2e8f9f7	983	#define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
<>	144:ef7eb2e8f9f7	984	#define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */
<>	144:ef7eb2e8f9f7	985	/**
<>	144:ef7eb2e8f9f7	986	* @}
<>	144:ef7eb2e8f9f7	987	*/
<>	144:ef7eb2e8f9f7	988
<>	144:ef7eb2e8f9f7	989	/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
<>	144:ef7eb2e8f9f7	990	* @{
<>	144:ef7eb2e8f9f7	991	*/
<>	144:ef7eb2e8f9f7	992	#define LL_ADC_INJ_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) /
<>	144:ef7eb2e8f9f7	993	#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /!< ADC group injected sequencer enable with 2 ranks in the sequence /
<>	144:ef7eb2e8f9f7	994	#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /!< ADC group injected sequencer enable with 3 ranks in the sequence /
<>	144:ef7eb2e8f9f7	995	#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 \| ADC_JSQR_JL_0) /!< ADC group injected sequencer enable with 4 ranks in the sequence /
<>	144:ef7eb2e8f9f7	996	/**
<>	144:ef7eb2e8f9f7	997	* @}
<>	144:ef7eb2e8f9f7	998	*/
<>	144:ef7eb2e8f9f7	999
<>	144:ef7eb2e8f9f7	1000	/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
<>	144:ef7eb2e8f9f7	1001	* @{
<>	144:ef7eb2e8f9f7	1002	*/
<>	144:ef7eb2e8f9f7	1003	#define LL_ADC_INJ_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U)/!< ADC group injected sequencer discontinuous mode disable /
<>	144:ef7eb2e8f9f7	1004	#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank /
<>	144:ef7eb2e8f9f7	1005	/**
<>	144:ef7eb2e8f9f7	1006	* @}
<>	144:ef7eb2e8f9f7	1007	*/
<>	144:ef7eb2e8f9f7	1008
<>	144:ef7eb2e8f9f7	1009	/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
<>	144:ef7eb2e8f9f7	1010	* @{
<>	144:ef7eb2e8f9f7	1011	*/
<>	144:ef7eb2e8f9f7	1012	#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET \| ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /!< ADC group injected sequencer rank 1 /
<>	144:ef7eb2e8f9f7	1013	#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET \| ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /!< ADC group injected sequencer rank 2 /
<>	144:ef7eb2e8f9f7	1014	#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET \| ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /!< ADC group injected sequencer rank 3 /
<>	144:ef7eb2e8f9f7	1015	#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET \| ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /!< ADC group injected sequencer rank 4 /
<>	144:ef7eb2e8f9f7	1016	/**
<>	144:ef7eb2e8f9f7	1017	* @}
<>	144:ef7eb2e8f9f7	1018	*/
<>	144:ef7eb2e8f9f7	1019
<>	144:ef7eb2e8f9f7	1020	/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
<>	144:ef7eb2e8f9f7	1021	* @{
<>	144:ef7eb2e8f9f7	1022	*/
<>	144:ef7eb2e8f9f7	1023	#define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000U) /!< Sampling time 2.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	1024	#define LL_ADC_SAMPLINGTIME_6CYCLES_5 ( ADC_SMPR2_SMP10_0) /!< Sampling time 6.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	1025	#define LL_ADC_SAMPLINGTIME_12CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /!< Sampling time 12.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	1026	#define LL_ADC_SAMPLINGTIME_24CYCLES_5 ( ADC_SMPR2_SMP10_1 \| ADC_SMPR2_SMP10_0) /!< Sampling time 24.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	1027	#define LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2 ) /!< Sampling time 47.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	1028	#define LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 \| ADC_SMPR2_SMP10_0) /!< Sampling time 92.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	1029	#define LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 \| ADC_SMPR2_SMP10_1 ) /!< Sampling time 247.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	1030	#define LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 \| ADC_SMPR2_SMP10_1 \| ADC_SMPR2_SMP10_0) /!< Sampling time 640.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	1031	/**
<>	144:ef7eb2e8f9f7	1032	* @}
<>	144:ef7eb2e8f9f7	1033	*/
<>	144:ef7eb2e8f9f7	1034
<>	144:ef7eb2e8f9f7	1035	/** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
<>	144:ef7eb2e8f9f7	1036	* @{
<>	144:ef7eb2e8f9f7	1037	*/
<>	144:ef7eb2e8f9f7	1038	#define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /!< ADC channel ending set to single ended (literal also used to set calibration mode) /
<>	144:ef7eb2e8f9f7	1039	#define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF \| ADC_CALFACT_CALFACT_D) /!< ADC channel ending set to differential (literal also used to set calibration mode) /
<>	144:ef7eb2e8f9f7	1040	#define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED \| LL_ADC_DIFFERENTIAL_ENDED) /!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) /
<>	144:ef7eb2e8f9f7	1041	/**
<>	144:ef7eb2e8f9f7	1042	* @}
<>	144:ef7eb2e8f9f7	1043	*/
<>	144:ef7eb2e8f9f7	1044
<>	144:ef7eb2e8f9f7	1045	/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
<>	144:ef7eb2e8f9f7	1046	* @{
<>	144:ef7eb2e8f9f7	1047	*/
<>	144:ef7eb2e8f9f7	1048	#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \| ADC_AWD_CR1_REGOFFSET) /!< ADC analog watchdog number 1 /
<>	144:ef7eb2e8f9f7	1049	#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK \| ADC_AWD_CR2_REGOFFSET) /!< ADC analog watchdog number 2 /
<>	144:ef7eb2e8f9f7	1050	#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK \| ADC_AWD_CR3_REGOFFSET) /!< ADC analog watchdog number 3 /
<>	144:ef7eb2e8f9f7	1051	/**
<>	144:ef7eb2e8f9f7	1052	* @}
<>	144:ef7eb2e8f9f7	1053	*/
<>	144:ef7eb2e8f9f7	1054
<>	144:ef7eb2e8f9f7	1055	/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
<>	144:ef7eb2e8f9f7	1056	* @{
<>	144:ef7eb2e8f9f7	1057	*/
<>	144:ef7eb2e8f9f7	1058	#define LL_ADC_AWD_DISABLE ((uint32_t)0x00000000U) /!< ADC analog watchdog monitoring disabled /
<>	144:ef7eb2e8f9f7	1059	#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK \| ADC_CFGR_AWD1EN ) /!< ADC analog watchdog monitoring of all channels, converted by group regular only /
<>	144:ef7eb2e8f9f7	1060	#define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK \| ADC_CFGR_JAWD1EN ) /!< ADC analog watchdog monitoring of all channels, converted by group injected only /
<>	144:ef7eb2e8f9f7	1061	#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN ) /!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1062	#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only /
<>	144:ef7eb2e8f9f7	1063	#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only /
<>	144:ef7eb2e8f9f7	1064	#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1065	#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only /
<>	144:ef7eb2e8f9f7	1066	#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only /
<>	144:ef7eb2e8f9f7	1067	#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1068	#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only /
<>	144:ef7eb2e8f9f7	1069	#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only /
<>	144:ef7eb2e8f9f7	1070	#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1071	#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only /
<>	144:ef7eb2e8f9f7	1072	#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only /
<>	144:ef7eb2e8f9f7	1073	#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1074	#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only /
<>	144:ef7eb2e8f9f7	1075	#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only /
<>	144:ef7eb2e8f9f7	1076	#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1077	#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only /
<>	144:ef7eb2e8f9f7	1078	#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only /
<>	144:ef7eb2e8f9f7	1079	#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1080	#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only /
<>	144:ef7eb2e8f9f7	1081	#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only /
<>	144:ef7eb2e8f9f7	1082	#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1083	#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only /
<>	144:ef7eb2e8f9f7	1084	#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only /
<>	144:ef7eb2e8f9f7	1085	#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1086	#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only /
<>	144:ef7eb2e8f9f7	1087	#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only /
<>	144:ef7eb2e8f9f7	1088	#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1089	#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only /
<>	144:ef7eb2e8f9f7	1090	#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only /
<>	144:ef7eb2e8f9f7	1091	#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1092	#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only /
<>	144:ef7eb2e8f9f7	1093	#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only /
<>	144:ef7eb2e8f9f7	1094	#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1095	#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only /
<>	144:ef7eb2e8f9f7	1096	#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only /
<>	144:ef7eb2e8f9f7	1097	#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1098	#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only /
<>	144:ef7eb2e8f9f7	1099	#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only /
<>	144:ef7eb2e8f9f7	1100	#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1101	#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only /
<>	144:ef7eb2e8f9f7	1102	#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only /
<>	144:ef7eb2e8f9f7	1103	#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1104	#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only /
<>	144:ef7eb2e8f9f7	1105	#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only /
<>	144:ef7eb2e8f9f7	1106	#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1107	#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only /
<>	144:ef7eb2e8f9f7	1108	#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only /
<>	144:ef7eb2e8f9f7	1109	#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1110	#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only /
<>	144:ef7eb2e8f9f7	1111	#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only /
<>	144:ef7eb2e8f9f7	1112	#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1113	#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only /
<>	144:ef7eb2e8f9f7	1114	#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only /
<>	144:ef7eb2e8f9f7	1115	#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1116	#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only /
<>	144:ef7eb2e8f9f7	1117	#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only /
<>	144:ef7eb2e8f9f7	1118	#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1119	#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only /
<>	144:ef7eb2e8f9f7	1120	#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only /
<>	144:ef7eb2e8f9f7	1121	#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1122	#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only /
<>	144:ef7eb2e8f9f7	1123	#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only /
<>	144:ef7eb2e8f9f7	1124	#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1125	#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only /
<>	144:ef7eb2e8f9f7	1126	#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only /
<>	144:ef7eb2e8f9f7	1127	#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda /
<>	144:ef7eb2e8f9f7	1128	#if defined(ADC1) && !defined(ADC2)
<>	144:ef7eb2e8f9f7	1129	#define LL_ADC_AWD_CH_DAC1CH1_REG ((LL_ADC_CHANNEL_DAC1CH1 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group regular only /
<>	144:ef7eb2e8f9f7	1130	#define LL_ADC_AWD_CH_DAC1CH1_INJ ((LL_ADC_CHANNEL_DAC1CH1 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group injected only /
<>	144:ef7eb2e8f9f7	1131	#define LL_ADC_AWD_CH_DAC1CH1_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1132	#define LL_ADC_AWD_CH_DAC1CH2_REG ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group regular only /
<>	144:ef7eb2e8f9f7	1133	#define LL_ADC_AWD_CH_DAC1CH2_INJ ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group injected only /
<>	144:ef7eb2e8f9f7	1134	#define LL_ADC_AWD_CH_DAC1CH2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1135	#elif defined(ADC2)
<>	144:ef7eb2e8f9f7	1136	#define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only /
<>	144:ef7eb2e8f9f7	1137	#define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only /
<>	144:ef7eb2e8f9f7	1138	#define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1139	#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only /
<>	144:ef7eb2e8f9f7	1140	#define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only /
<>	144:ef7eb2e8f9f7	1141	#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1142	#if defined(ADC3)
<>	144:ef7eb2e8f9f7	1143	#define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only /
<>	144:ef7eb2e8f9f7	1144	#define LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only /
<>	144:ef7eb2e8f9f7	1145	#define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1146	#define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only /
<>	144:ef7eb2e8f9f7	1147	#define LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only /
<>	144:ef7eb2e8f9f7	1148	#define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected /
<>	144:ef7eb2e8f9f7	1149	#endif
<>	144:ef7eb2e8f9f7	1150	#endif
<>	144:ef7eb2e8f9f7	1151	/**
<>	144:ef7eb2e8f9f7	1152	* @}
<>	144:ef7eb2e8f9f7	1153	*/
<>	144:ef7eb2e8f9f7	1154
<>	144:ef7eb2e8f9f7	1155	/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
<>	144:ef7eb2e8f9f7	1156	* @{
<>	144:ef7eb2e8f9f7	1157	*/
<>	144:ef7eb2e8f9f7	1158	#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 ) /!< ADC analog watchdog threshold high /
<>	144:ef7eb2e8f9f7	1159	#define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1) /!< ADC analog watchdog threshold low /
<>	144:ef7eb2e8f9f7	1160	#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 \| ADC_TR1_LT1) /!< ADC analog watchdog both thresholds high and low concatenated into the same data /
<>	144:ef7eb2e8f9f7	1161	/**
<>	144:ef7eb2e8f9f7	1162	* @}
<>	144:ef7eb2e8f9f7	1163	*/
<>	144:ef7eb2e8f9f7	1164
<>	144:ef7eb2e8f9f7	1165	/** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
<>	144:ef7eb2e8f9f7	1166	* @{
<>	144:ef7eb2e8f9f7	1167	*/
<>	144:ef7eb2e8f9f7	1168	#define LL_ADC_OVS_DISABLE ((uint32_t)0x00000000U) /!< ADC oversampling disabled. /
<>	144:ef7eb2e8f9f7	1169	#define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. /
<>	144:ef7eb2e8f9f7	1170	#define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM \| ADC_CFGR2_ROVSE) /!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). /
<>	144:ef7eb2e8f9f7	1171	#define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /!< ADC oversampling on conversions of ADC group injected. /
<>	144:ef7eb2e8f9f7	1172	#define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE \| ADC_CFGR2_ROVSE) /!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). /
<>	144:ef7eb2e8f9f7	1173	/**
<>	144:ef7eb2e8f9f7	1174	* @}
<>	144:ef7eb2e8f9f7	1175	*/
<>	144:ef7eb2e8f9f7	1176
<>	144:ef7eb2e8f9f7	1177	/** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
<>	144:ef7eb2e8f9f7	1178	* @{
<>	144:ef7eb2e8f9f7	1179	*/
<>	144:ef7eb2e8f9f7	1180	#define LL_ADC_OVS_REG_CONT ((uint32_t)0x00000000U)/!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) /
<>	144:ef7eb2e8f9f7	1181	#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) /
<>	144:ef7eb2e8f9f7	1182	/**
<>	144:ef7eb2e8f9f7	1183	* @}
<>	144:ef7eb2e8f9f7	1184	*/
<>	144:ef7eb2e8f9f7	1185
<>	144:ef7eb2e8f9f7	1186	/** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
<>	144:ef7eb2e8f9f7	1187	* @{
<>	144:ef7eb2e8f9f7	1188	*/
<>	144:ef7eb2e8f9f7	1189	#define LL_ADC_OVS_RATIO_2 ((uint32_t)0x00000000U) /!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) /
<>	144:ef7eb2e8f9f7	1190	#define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0) /!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) /
<>	144:ef7eb2e8f9f7	1191	#define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 ) /!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) /
<>	144:ef7eb2e8f9f7	1192	#define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 \| ADC_CFGR2_OVSR_0) /!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) /
<>	144:ef7eb2e8f9f7	1193	#define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 ) /!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) /
<>	144:ef7eb2e8f9f7	1194	#define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 \| ADC_CFGR2_OVSR_0) /!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) /
<>	144:ef7eb2e8f9f7	1195	#define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 \| ADC_CFGR2_OVSR_1 ) /!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) /
<>	144:ef7eb2e8f9f7	1196	#define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 \| ADC_CFGR2_OVSR_1 \| ADC_CFGR2_OVSR_0) /!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) /
<>	144:ef7eb2e8f9f7	1197	/**
<>	144:ef7eb2e8f9f7	1198	* @}
<>	144:ef7eb2e8f9f7	1199	*/
<>	144:ef7eb2e8f9f7	1200
<>	144:ef7eb2e8f9f7	1201	/** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift
<>	144:ef7eb2e8f9f7	1202	* @{
<>	144:ef7eb2e8f9f7	1203	*/
<>	144:ef7eb2e8f9f7	1204	#define LL_ADC_OVS_SHIFT_NONE ((uint32_t)0x00000000U) /!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) /
<>	144:ef7eb2e8f9f7	1205	#define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) /
<>	144:ef7eb2e8f9f7	1206	#define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) /
<>	144:ef7eb2e8f9f7	1207	#define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 \| ADC_CFGR2_OVSS_0) /!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) /
<>	144:ef7eb2e8f9f7	1208	#define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) /
<>	144:ef7eb2e8f9f7	1209	#define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 \| ADC_CFGR2_OVSS_0) /!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) /
<>	144:ef7eb2e8f9f7	1210	#define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 \| ADC_CFGR2_OVSS_1 ) /!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) /
<>	144:ef7eb2e8f9f7	1211	#define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 \| ADC_CFGR2_OVSS_1 \| ADC_CFGR2_OVSS_0) /!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) /
<>	144:ef7eb2e8f9f7	1212	#define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) /
<>	144:ef7eb2e8f9f7	1213	/**
<>	144:ef7eb2e8f9f7	1214	* @}
<>	144:ef7eb2e8f9f7	1215	*/
<>	144:ef7eb2e8f9f7	1216
<>	144:ef7eb2e8f9f7	1217	#if defined(ADC_MULTIMODE_SUPPORT)
<>	144:ef7eb2e8f9f7	1218	/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
<>	144:ef7eb2e8f9f7	1219	* @{
<>	144:ef7eb2e8f9f7	1220	*/
<>	144:ef7eb2e8f9f7	1221	#define LL_ADC_MULTI_INDEPENDENT ((uint32_t)0x00000000U) /!< ADC dual mode disabled (ADC independent mode) /
<>	144:ef7eb2e8f9f7	1222	#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 \| ADC_CCR_DUAL_1 ) /!< ADC dual mode enabled: group regular simultaneous /
<>	144:ef7eb2e8f9f7	1223	#define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 \| ADC_CCR_DUAL_1 \| ADC_CCR_DUAL_0) /!< ADC dual mode enabled: Combined group regular interleaved /
<>	144:ef7eb2e8f9f7	1224	#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 \| ADC_CCR_DUAL_0) /!< ADC dual mode enabled: group injected simultaneous /
<>	144:ef7eb2e8f9f7	1225	#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 \| ADC_CCR_DUAL_0) /!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) /
<>	144:ef7eb2e8f9f7	1226	#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0) /!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous /
<>	144:ef7eb2e8f9f7	1227	#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 ) /!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger /
<>	144:ef7eb2e8f9f7	1228	#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 \| ADC_CCR_DUAL_0) /!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous /
<>	144:ef7eb2e8f9f7	1229	/**
<>	144:ef7eb2e8f9f7	1230	* @}
<>	144:ef7eb2e8f9f7	1231	*/
<>	144:ef7eb2e8f9f7	1232
<>	144:ef7eb2e8f9f7	1233	/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
<>	144:ef7eb2e8f9f7	1234	* @{
<>	144:ef7eb2e8f9f7	1235	*/
<>	144:ef7eb2e8f9f7	1236	#define LL_ADC_MULTI_REG_DMA_EACH_ADC ((uint32_t)0x00000000U) /!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings /
<>	144:ef7eb2e8f9f7	1237	#define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B ( ADC_CCR_MDMA_1 ) /!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits /
<>	144:ef7eb2e8f9f7	1238	#define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B ( ADC_CCR_MDMA_1 \| ADC_CCR_MDMA_0) /!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits /
<>	144:ef7eb2e8f9f7	1239	#define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG \| ADC_CCR_MDMA_1 ) /!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits /
<>	144:ef7eb2e8f9f7	1240	#define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG \| ADC_CCR_MDMA_1 \| ADC_CCR_MDMA_0) /!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 8 and 6 bits /
<>	144:ef7eb2e8f9f7	1241	/**
<>	144:ef7eb2e8f9f7	1242	* @}
<>	144:ef7eb2e8f9f7	1243	*/
<>	144:ef7eb2e8f9f7	1244
<>	144:ef7eb2e8f9f7	1245	/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
<>	144:ef7eb2e8f9f7	1246	* @{
<>	144:ef7eb2e8f9f7	1247	*/
<>	144:ef7eb2e8f9f7	1248	#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE ((uint32_t)0x00000000U) /!< ADC multimode delay between two sampling phases: 1 ADC clock cycle /
<>	144:ef7eb2e8f9f7	1249	#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 2 ADC clock cycles /
<>	144:ef7eb2e8f9f7	1250	#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 ) /!< ADC multimode delay between two sampling phases: 3 ADC clock cycles /
<>	144:ef7eb2e8f9f7	1251	#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 4 ADC clock cycles /
<>	144:ef7eb2e8f9f7	1252	#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES ( ADC_CCR_DELAY_2 ) /!< ADC multimode delay between two sampling phases: 5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	1253	#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 6 ADC clock cycles /
<>	144:ef7eb2e8f9f7	1254	#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1 ) /!< ADC multimode delay between two sampling phases: 7 ADC clock cycles /
<>	144:ef7eb2e8f9f7	1255	#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 8 ADC clock cycles /
<>	144:ef7eb2e8f9f7	1256	#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 ) /!< ADC multimode delay between two sampling phases: 9 ADC clock cycles /
<>	144:ef7eb2e8f9f7	1257	#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 10 ADC clock cycles /
<>	144:ef7eb2e8f9f7	1258	#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_1 ) /!< ADC multimode delay between two sampling phases: 11 ADC clock cycles /
<>	144:ef7eb2e8f9f7	1259	#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 12 ADC clock cycles /
<>	144:ef7eb2e8f9f7	1260	/**
<>	144:ef7eb2e8f9f7	1261	* @}
<>	144:ef7eb2e8f9f7	1262	*/
<>	144:ef7eb2e8f9f7	1263
<>	144:ef7eb2e8f9f7	1264	/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
<>	144:ef7eb2e8f9f7	1265	* @{
<>	144:ef7eb2e8f9f7	1266	*/
<>	144:ef7eb2e8f9f7	1267	#define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /!< In multimode, selection among several ADC instances: ADC master /
<>	144:ef7eb2e8f9f7	1268	#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /!< In multimode, selection among several ADC instances: ADC slave /
<>	144:ef7eb2e8f9f7	1269	#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV \| ADC_CDR_RDATA_MST) /!< In multimode, selection among several ADC instances: both ADC master and ADC slave /
<>	144:ef7eb2e8f9f7	1270	/**
<>	144:ef7eb2e8f9f7	1271	* @}
<>	144:ef7eb2e8f9f7	1272	*/
<>	144:ef7eb2e8f9f7	1273
<>	144:ef7eb2e8f9f7	1274	#endif /* ADC_MULTIMODE_SUPPORT */
<>	144:ef7eb2e8f9f7	1275
<>	144:ef7eb2e8f9f7	1276	/** @defgroup ADC_LL_EC_LEGACY ADC literals legacy naming
<>	144:ef7eb2e8f9f7	1277	* @{
<>	144:ef7eb2e8f9f7	1278	*/
<>	144:ef7eb2e8f9f7	1279	#define LL_ADC_REG_TRIG_SW_START (LL_ADC_REG_TRIG_SOFTWARE)
<>	144:ef7eb2e8f9f7	1280	#define LL_ADC_REG_TRIG_EXT_TIM1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1)
<>	144:ef7eb2e8f9f7	1281	#define LL_ADC_REG_TRIG_EXT_TIM1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2)
<>	144:ef7eb2e8f9f7	1282	#define LL_ADC_REG_TRIG_EXT_TIM1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3)
<>	144:ef7eb2e8f9f7	1283	#define LL_ADC_REG_TRIG_EXT_TIM2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2)
<>	144:ef7eb2e8f9f7	1284	#define LL_ADC_REG_TRIG_EXT_TIM3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4)
<>	144:ef7eb2e8f9f7	1285	#define LL_ADC_REG_TRIG_EXT_TIM4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4)
<>	144:ef7eb2e8f9f7	1286
<>	144:ef7eb2e8f9f7	1287	#define LL_ADC_INJ_TRIG_SW_START (LL_ADC_INJ_TRIG_SOFTWARE)
<>	144:ef7eb2e8f9f7	1288	#define LL_ADC_INJ_TRIG_EXT_TIM1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)
<>	144:ef7eb2e8f9f7	1289	#define LL_ADC_INJ_TRIG_EXT_TIM2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)
<>	144:ef7eb2e8f9f7	1290	#define LL_ADC_INJ_TRIG_EXT_TIM3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)
<>	144:ef7eb2e8f9f7	1291	#define LL_ADC_INJ_TRIG_EXT_TIM3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)
<>	144:ef7eb2e8f9f7	1292	#define LL_ADC_INJ_TRIG_EXT_TIM3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)
<>	144:ef7eb2e8f9f7	1293	#define LL_ADC_INJ_TRIG_EXT_TIM8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4)
<>	144:ef7eb2e8f9f7	1294
<>	144:ef7eb2e8f9f7	1295	#define LL_ADC_OVS_DATA_SHIFT_NONE (LL_ADC_OVS_SHIFT_NONE)
<>	144:ef7eb2e8f9f7	1296	#define LL_ADC_OVS_DATA_SHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1)
<>	144:ef7eb2e8f9f7	1297	#define LL_ADC_OVS_DATA_SHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2)
<>	144:ef7eb2e8f9f7	1298	#define LL_ADC_OVS_DATA_SHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3)
<>	144:ef7eb2e8f9f7	1299	#define LL_ADC_OVS_DATA_SHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4)
<>	144:ef7eb2e8f9f7	1300	#define LL_ADC_OVS_DATA_SHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5)
<>	144:ef7eb2e8f9f7	1301	#define LL_ADC_OVS_DATA_SHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6)
<>	144:ef7eb2e8f9f7	1302	#define LL_ADC_OVS_DATA_SHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7)
<>	144:ef7eb2e8f9f7	1303	#define LL_ADC_OVS_DATA_SHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8)
<>	144:ef7eb2e8f9f7	1304
<>	144:ef7eb2e8f9f7	1305	/**
<>	144:ef7eb2e8f9f7	1306	* @}
<>	144:ef7eb2e8f9f7	1307	*/
<>	144:ef7eb2e8f9f7	1308
<>	144:ef7eb2e8f9f7	1309
<>	144:ef7eb2e8f9f7	1310	/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
<>	144:ef7eb2e8f9f7	1311	* @note Only ADC IP HW delays are defined in ADC LL driver driver,
<>	144:ef7eb2e8f9f7	1312	* not timeout values.
<>	144:ef7eb2e8f9f7	1313	* For details on delays values, refer to descriptions in source code
<>	144:ef7eb2e8f9f7	1314	* above each literal definition.
<>	144:ef7eb2e8f9f7	1315	* @{
<>	144:ef7eb2e8f9f7	1316	*/
<>	144:ef7eb2e8f9f7	1317
<>	144:ef7eb2e8f9f7	1318	/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
<>	144:ef7eb2e8f9f7	1319	/* not timeout values. */
<>	144:ef7eb2e8f9f7	1320	/* Timeout values for ADC operations are dependent to device clock */
<>	144:ef7eb2e8f9f7	1321	/* configuration (system clock versus ADC clock), */
<>	144:ef7eb2e8f9f7	1322	/* and therefore must be defined in user application. */
<>	144:ef7eb2e8f9f7	1323	/* Indications for estimation of ADC timeout delays, for this */
<>	144:ef7eb2e8f9f7	1324	/* STM32 serie: */
<>	144:ef7eb2e8f9f7	1325	/* - ADC calibration time: maximum delay is 112/fADC. */
<>	144:ef7eb2e8f9f7	1326	/* (refer to device datasheet, parameter "tCAL") */
<>	144:ef7eb2e8f9f7	1327	/* - ADC enable time: maximum delay is 1 conversion cycle. */
<>	144:ef7eb2e8f9f7	1328	/* (refer to device datasheet, parameter "tSTAB") */
<>	144:ef7eb2e8f9f7	1329	/* - ADC disable time: maximum delay should be a few ADC clock cycles */
<>	144:ef7eb2e8f9f7	1330	/* - ADC stop conversion time: maximum delay should be a few ADC clock */
<>	144:ef7eb2e8f9f7	1331	/* cycles */
<>	144:ef7eb2e8f9f7	1332	/* - ADC conversion time: duration depending on ADC clock and ADC */
<>	144:ef7eb2e8f9f7	1333	/* configuration. */
<>	144:ef7eb2e8f9f7	1334	/* (refer to device reference manual, section "Timing") */
<>	144:ef7eb2e8f9f7	1335
<>	144:ef7eb2e8f9f7	1336	/* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
<>	144:ef7eb2e8f9f7	1337	/* Delay set to maximum value (refer to device datasheet, */
<>	144:ef7eb2e8f9f7	1338	/* parameter "tADCVREG_STUP"). */
<>	144:ef7eb2e8f9f7	1339	/* Unit: us */
<>	144:ef7eb2e8f9f7	1340	#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ((uint32_t) 10U) /!< Delay for ADC stabilization time (ADC voltage regulator start-up time) /
<>	144:ef7eb2e8f9f7	1341
<>	144:ef7eb2e8f9f7	1342	/* Delay for internal voltage reference stabilization time. */
<>	144:ef7eb2e8f9f7	1343	/* Delay set to maximum value (refer to device datasheet, */
<>	144:ef7eb2e8f9f7	1344	/* parameter "tstart_vrefint"). */
<>	144:ef7eb2e8f9f7	1345	/* Unit: us */
<>	144:ef7eb2e8f9f7	1346	#define LL_ADC_DELAY_VREFINT_STAB_US ((uint32_t) 12U) /!< Delay for internal voltage reference stabilization time /
<>	144:ef7eb2e8f9f7	1347
<>	144:ef7eb2e8f9f7	1348	/* Delay for temperature sensor stabilization time. */
<>	144:ef7eb2e8f9f7	1349	/* Literal set to maximum value (refer to device datasheet, */
<>	144:ef7eb2e8f9f7	1350	/* parameter "tSTART"). */
<>	144:ef7eb2e8f9f7	1351	/* Unit: us */
<>	144:ef7eb2e8f9f7	1352	#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 120U) /!< Delay for temperature sensor stabilization time /
<>	144:ef7eb2e8f9f7	1353
<>	144:ef7eb2e8f9f7	1354	/* Delay required between ADC end of calibration and ADC enable. */
<>	144:ef7eb2e8f9f7	1355	/* Note: On this STM32 serie, a minimum number of ADC clock cycles */
<>	144:ef7eb2e8f9f7	1356	/* are required between ADC end of calibration and ADC enable. */
<>	144:ef7eb2e8f9f7	1357	/* Wait time can be computed in user application by waiting for the */
<>	144:ef7eb2e8f9f7	1358	/* equivalent number of CPU cycles, by taking into account */
<>	144:ef7eb2e8f9f7	1359	/* ratio of CPU clock versus ADC clock prescalers. */
<>	144:ef7eb2e8f9f7	1360	/* Unit: ADC clock cycles. */
<>	144:ef7eb2e8f9f7	1361	#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ((uint32_t) 4U) /!< Delay required between ADC end of calibration and ADC enable /
<>	144:ef7eb2e8f9f7	1362
<>	144:ef7eb2e8f9f7	1363	/**
<>	144:ef7eb2e8f9f7	1364	* @}
<>	144:ef7eb2e8f9f7	1365	*/
<>	144:ef7eb2e8f9f7	1366
<>	144:ef7eb2e8f9f7	1367	/**
<>	144:ef7eb2e8f9f7	1368	* @}
<>	144:ef7eb2e8f9f7	1369	*/
<>	144:ef7eb2e8f9f7	1370
<>	144:ef7eb2e8f9f7	1371
<>	144:ef7eb2e8f9f7	1372	/* Exported macro ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1373	/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
<>	144:ef7eb2e8f9f7	1374	* @{
<>	144:ef7eb2e8f9f7	1375	*/
<>	144:ef7eb2e8f9f7	1376
<>	144:ef7eb2e8f9f7	1377	/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
<>	144:ef7eb2e8f9f7	1378	* @{
<>	144:ef7eb2e8f9f7	1379	*/
<>	144:ef7eb2e8f9f7	1380
<>	144:ef7eb2e8f9f7	1381	/**
<>	144:ef7eb2e8f9f7	1382	* @brief Write a value in ADC register
<>	144:ef7eb2e8f9f7	1383	* @param __INSTANCE__ ADC Instance
<>	144:ef7eb2e8f9f7	1384	* @param __REG__ Register to be written
<>	144:ef7eb2e8f9f7	1385	* @param __VALUE__ Value to be written in the register
<>	144:ef7eb2e8f9f7	1386	* @retval None
<>	144:ef7eb2e8f9f7	1387	*/
<>	144:ef7eb2e8f9f7	1388	#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	144:ef7eb2e8f9f7	1389
<>	144:ef7eb2e8f9f7	1390	/**
<>	144:ef7eb2e8f9f7	1391	* @brief Read a value in ADC register
<>	144:ef7eb2e8f9f7	1392	* @param __INSTANCE__ ADC Instance
<>	144:ef7eb2e8f9f7	1393	* @param __REG__ Register to be read
<>	144:ef7eb2e8f9f7	1394	* @retval Register value
<>	144:ef7eb2e8f9f7	1395	*/
<>	144:ef7eb2e8f9f7	1396	#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	144:ef7eb2e8f9f7	1397	/**
<>	144:ef7eb2e8f9f7	1398	* @}
<>	144:ef7eb2e8f9f7	1399	*/
<>	144:ef7eb2e8f9f7	1400
<>	144:ef7eb2e8f9f7	1401	/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
<>	144:ef7eb2e8f9f7	1402	* @{
<>	144:ef7eb2e8f9f7	1403	*/
<>	144:ef7eb2e8f9f7	1404
<>	144:ef7eb2e8f9f7	1405	/**
<>	144:ef7eb2e8f9f7	1406	* @brief Helper macro to get ADC channel number in decimal format
<>	144:ef7eb2e8f9f7	1407	* from literals LL_ADC_CHANNEL_x.
<>	144:ef7eb2e8f9f7	1408	* @note Example:
<>	144:ef7eb2e8f9f7	1409	* __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
<>	144:ef7eb2e8f9f7	1410	* will return decimal number "4".
<>	144:ef7eb2e8f9f7	1411	* @note The input can be a value from functions where a channel
<>	144:ef7eb2e8f9f7	1412	* number is returned, either defined with number
<>	144:ef7eb2e8f9f7	1413	* or with bitfield (only one bit must be set).
<>	144:ef7eb2e8f9f7	1414	* @param __CHANNEL__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1415	* @arg @ref LL_ADC_CHANNEL_0
<>	144:ef7eb2e8f9f7	1416	* @arg @ref LL_ADC_CHANNEL_1 (7)
<>	144:ef7eb2e8f9f7	1417	* @arg @ref LL_ADC_CHANNEL_2 (7)
<>	144:ef7eb2e8f9f7	1418	* @arg @ref LL_ADC_CHANNEL_3 (7)
<>	144:ef7eb2e8f9f7	1419	* @arg @ref LL_ADC_CHANNEL_4 (7)
<>	144:ef7eb2e8f9f7	1420	* @arg @ref LL_ADC_CHANNEL_5 (7)
<>	144:ef7eb2e8f9f7	1421	* @arg @ref LL_ADC_CHANNEL_6
<>	144:ef7eb2e8f9f7	1422	* @arg @ref LL_ADC_CHANNEL_7
<>	144:ef7eb2e8f9f7	1423	* @arg @ref LL_ADC_CHANNEL_8
<>	144:ef7eb2e8f9f7	1424	* @arg @ref LL_ADC_CHANNEL_9
<>	144:ef7eb2e8f9f7	1425	* @arg @ref LL_ADC_CHANNEL_10
<>	144:ef7eb2e8f9f7	1426	* @arg @ref LL_ADC_CHANNEL_11
<>	144:ef7eb2e8f9f7	1427	* @arg @ref LL_ADC_CHANNEL_12
<>	144:ef7eb2e8f9f7	1428	* @arg @ref LL_ADC_CHANNEL_13
<>	144:ef7eb2e8f9f7	1429	* @arg @ref LL_ADC_CHANNEL_14
<>	144:ef7eb2e8f9f7	1430	* @arg @ref LL_ADC_CHANNEL_15
<>	144:ef7eb2e8f9f7	1431	* @arg @ref LL_ADC_CHANNEL_16
<>	144:ef7eb2e8f9f7	1432	* @arg @ref LL_ADC_CHANNEL_17
<>	144:ef7eb2e8f9f7	1433	* @arg @ref LL_ADC_CHANNEL_18
<>	144:ef7eb2e8f9f7	1434	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	144:ef7eb2e8f9f7	1435	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
<>	144:ef7eb2e8f9f7	1436	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
<>	144:ef7eb2e8f9f7	1437	* @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
<>	144:ef7eb2e8f9f7	1438	* @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
<>	144:ef7eb2e8f9f7	1439	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	1440	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	1441	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	1442	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	1443	*
<>	144:ef7eb2e8f9f7	1444	* (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
<>	144:ef7eb2e8f9f7	1445	* (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
<>	144:ef7eb2e8f9f7	1446	* (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
<>	144:ef7eb2e8f9f7	1447	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
<>	144:ef7eb2e8f9f7	1448	* (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
<>	144:ef7eb2e8f9f7	1449	* (6) On STM32L4, parameter available on devices with several ADC instances.\n
<>	144:ef7eb2e8f9f7	1450	* (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
<>	144:ef7eb2e8f9f7	1451	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
<>	144:ef7eb2e8f9f7	1452	* @retval Value between Min_Data=0 and Max_Data=18
<>	144:ef7eb2e8f9f7	1453	*/
<>	144:ef7eb2e8f9f7	1454	#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
<>	144:ef7eb2e8f9f7	1455	((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U) \
<>	144:ef7eb2e8f9f7	1456	? ( \
<>	144:ef7eb2e8f9f7	1457	((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
<>	144:ef7eb2e8f9f7	1458	) \
<>	144:ef7eb2e8f9f7	1459	: \
<>	144:ef7eb2e8f9f7	1460	( \
<>	144:ef7eb2e8f9f7	1461	POSITION_VAL((__CHANNEL__)) \
<>	144:ef7eb2e8f9f7	1462	) \
<>	144:ef7eb2e8f9f7	1463	)
<>	144:ef7eb2e8f9f7	1464
<>	144:ef7eb2e8f9f7	1465	/**
<>	144:ef7eb2e8f9f7	1466	* @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
<>	144:ef7eb2e8f9f7	1467	* from number in decimal format.
<>	144:ef7eb2e8f9f7	1468	* @note Example:
<>	144:ef7eb2e8f9f7	1469	* __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
<>	144:ef7eb2e8f9f7	1470	* will return a data equivalent to "LL_ADC_CHANNEL_4".
<>	144:ef7eb2e8f9f7	1471	* @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18
<>	144:ef7eb2e8f9f7	1472	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	1473	* @arg @ref LL_ADC_CHANNEL_0
<>	144:ef7eb2e8f9f7	1474	* @arg @ref LL_ADC_CHANNEL_1 (7)
<>	144:ef7eb2e8f9f7	1475	* @arg @ref LL_ADC_CHANNEL_2 (7)
<>	144:ef7eb2e8f9f7	1476	* @arg @ref LL_ADC_CHANNEL_3 (7)
<>	144:ef7eb2e8f9f7	1477	* @arg @ref LL_ADC_CHANNEL_4 (7)
<>	144:ef7eb2e8f9f7	1478	* @arg @ref LL_ADC_CHANNEL_5 (7)
<>	144:ef7eb2e8f9f7	1479	* @arg @ref LL_ADC_CHANNEL_6
<>	144:ef7eb2e8f9f7	1480	* @arg @ref LL_ADC_CHANNEL_7
<>	144:ef7eb2e8f9f7	1481	* @arg @ref LL_ADC_CHANNEL_8
<>	144:ef7eb2e8f9f7	1482	* @arg @ref LL_ADC_CHANNEL_9
<>	144:ef7eb2e8f9f7	1483	* @arg @ref LL_ADC_CHANNEL_10
<>	144:ef7eb2e8f9f7	1484	* @arg @ref LL_ADC_CHANNEL_11
<>	144:ef7eb2e8f9f7	1485	* @arg @ref LL_ADC_CHANNEL_12
<>	144:ef7eb2e8f9f7	1486	* @arg @ref LL_ADC_CHANNEL_13
<>	144:ef7eb2e8f9f7	1487	* @arg @ref LL_ADC_CHANNEL_14
<>	144:ef7eb2e8f9f7	1488	* @arg @ref LL_ADC_CHANNEL_15
<>	144:ef7eb2e8f9f7	1489	* @arg @ref LL_ADC_CHANNEL_16
<>	144:ef7eb2e8f9f7	1490	* @arg @ref LL_ADC_CHANNEL_17
<>	144:ef7eb2e8f9f7	1491	* @arg @ref LL_ADC_CHANNEL_18
<>	144:ef7eb2e8f9f7	1492	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	144:ef7eb2e8f9f7	1493	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
<>	144:ef7eb2e8f9f7	1494	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
<>	144:ef7eb2e8f9f7	1495	* @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
<>	144:ef7eb2e8f9f7	1496	* @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
<>	144:ef7eb2e8f9f7	1497	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	1498	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	1499	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	1500	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	1501	*
<>	144:ef7eb2e8f9f7	1502	* (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
<>	144:ef7eb2e8f9f7	1503	* (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
<>	144:ef7eb2e8f9f7	1504	* (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
<>	144:ef7eb2e8f9f7	1505	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
<>	144:ef7eb2e8f9f7	1506	* (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
<>	144:ef7eb2e8f9f7	1507	* (6) On STM32L4, parameter available on devices with several ADC instances.\n
<>	144:ef7eb2e8f9f7	1508	* (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
<>	144:ef7eb2e8f9f7	1509	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
<>	144:ef7eb2e8f9f7	1510	* (1, 2, 3, 4) For ADC channel read back from ADC register,
<>	144:ef7eb2e8f9f7	1511	* comparison with internal channel parameter to be done
<>	144:ef7eb2e8f9f7	1512	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
<>	144:ef7eb2e8f9f7	1513	*/
<>	144:ef7eb2e8f9f7	1514	#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
<>	144:ef7eb2e8f9f7	1515	(((__DECIMAL_NB__) <= 9U) \
<>	144:ef7eb2e8f9f7	1516	? ( \
<>	144:ef7eb2e8f9f7	1517	((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \| \
<>	144:ef7eb2e8f9f7	1518	(ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) \| \
<>	144:ef7eb2e8f9f7	1519	(ADC_SMPR1_REGOFFSET \| (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
<>	144:ef7eb2e8f9f7	1520	) \
<>	144:ef7eb2e8f9f7	1521	: \
<>	144:ef7eb2e8f9f7	1522	( \
<>	144:ef7eb2e8f9f7	1523	((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \| \
<>	144:ef7eb2e8f9f7	1524	(ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) \| \
<>	144:ef7eb2e8f9f7	1525	(ADC_SMPR2_REGOFFSET \| (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
<>	144:ef7eb2e8f9f7	1526	) \
<>	144:ef7eb2e8f9f7	1527	)
<>	144:ef7eb2e8f9f7	1528
<>	144:ef7eb2e8f9f7	1529	/**
<>	144:ef7eb2e8f9f7	1530	* @brief Helper macro to determine whether the selected channel
<>	144:ef7eb2e8f9f7	1531	* corresponds to literal definitions of driver.
<>	144:ef7eb2e8f9f7	1532	* @note The different literal definitions of ADC channels are:
<>	144:ef7eb2e8f9f7	1533	* - ADC internal channel:
<>	144:ef7eb2e8f9f7	1534	* LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
<>	144:ef7eb2e8f9f7	1535	* - ADC external channel (channel connected to a GPIO pin):
<>	144:ef7eb2e8f9f7	1536	* LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
<>	144:ef7eb2e8f9f7	1537	* @note The channel parameter must be a value defined from literal
<>	144:ef7eb2e8f9f7	1538	* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
<>	144:ef7eb2e8f9f7	1539	* LL_ADC_CHANNEL_TEMPSENSOR, ...),
<>	144:ef7eb2e8f9f7	1540	* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
<>	144:ef7eb2e8f9f7	1541	* must not be a value from functions where a channel number is
<>	144:ef7eb2e8f9f7	1542	* returned from ADC registers,
<>	144:ef7eb2e8f9f7	1543	* because internal and external channels share the same channel
<>	144:ef7eb2e8f9f7	1544	* number in ADC registers. The differentiation is made only with
<>	144:ef7eb2e8f9f7	1545	* parameters definitions of driver.
<>	144:ef7eb2e8f9f7	1546	* @param __CHANNEL__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1547	* @arg @ref LL_ADC_CHANNEL_0
<>	144:ef7eb2e8f9f7	1548	* @arg @ref LL_ADC_CHANNEL_1 (7)
<>	144:ef7eb2e8f9f7	1549	* @arg @ref LL_ADC_CHANNEL_2 (7)
<>	144:ef7eb2e8f9f7	1550	* @arg @ref LL_ADC_CHANNEL_3 (7)
<>	144:ef7eb2e8f9f7	1551	* @arg @ref LL_ADC_CHANNEL_4 (7)
<>	144:ef7eb2e8f9f7	1552	* @arg @ref LL_ADC_CHANNEL_5 (7)
<>	144:ef7eb2e8f9f7	1553	* @arg @ref LL_ADC_CHANNEL_6
<>	144:ef7eb2e8f9f7	1554	* @arg @ref LL_ADC_CHANNEL_7
<>	144:ef7eb2e8f9f7	1555	* @arg @ref LL_ADC_CHANNEL_8
<>	144:ef7eb2e8f9f7	1556	* @arg @ref LL_ADC_CHANNEL_9
<>	144:ef7eb2e8f9f7	1557	* @arg @ref LL_ADC_CHANNEL_10
<>	144:ef7eb2e8f9f7	1558	* @arg @ref LL_ADC_CHANNEL_11
<>	144:ef7eb2e8f9f7	1559	* @arg @ref LL_ADC_CHANNEL_12
<>	144:ef7eb2e8f9f7	1560	* @arg @ref LL_ADC_CHANNEL_13
<>	144:ef7eb2e8f9f7	1561	* @arg @ref LL_ADC_CHANNEL_14
<>	144:ef7eb2e8f9f7	1562	* @arg @ref LL_ADC_CHANNEL_15
<>	144:ef7eb2e8f9f7	1563	* @arg @ref LL_ADC_CHANNEL_16
<>	144:ef7eb2e8f9f7	1564	* @arg @ref LL_ADC_CHANNEL_17
<>	144:ef7eb2e8f9f7	1565	* @arg @ref LL_ADC_CHANNEL_18
<>	144:ef7eb2e8f9f7	1566	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	144:ef7eb2e8f9f7	1567	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
<>	144:ef7eb2e8f9f7	1568	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
<>	144:ef7eb2e8f9f7	1569	* @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
<>	144:ef7eb2e8f9f7	1570	* @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
<>	144:ef7eb2e8f9f7	1571	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	1572	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	1573	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	1574	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	1575	*
<>	144:ef7eb2e8f9f7	1576	* (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
<>	144:ef7eb2e8f9f7	1577	* (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
<>	144:ef7eb2e8f9f7	1578	* (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
<>	144:ef7eb2e8f9f7	1579	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
<>	144:ef7eb2e8f9f7	1580	* (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
<>	144:ef7eb2e8f9f7	1581	* (6) On STM32L4, parameter available on devices with several ADC instances.\n
<>	144:ef7eb2e8f9f7	1582	* (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
<>	144:ef7eb2e8f9f7	1583	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
<>	144:ef7eb2e8f9f7	1584	* @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
<>	144:ef7eb2e8f9f7	1585	* Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
<>	144:ef7eb2e8f9f7	1586	*/
<>	144:ef7eb2e8f9f7	1587	#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
<>	144:ef7eb2e8f9f7	1588	(((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
<>	144:ef7eb2e8f9f7	1589
<>	144:ef7eb2e8f9f7	1590	/**
<>	144:ef7eb2e8f9f7	1591	* @brief Helper macro to convert a channel defined from parameter
<>	144:ef7eb2e8f9f7	1592	* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
<>	144:ef7eb2e8f9f7	1593	* LL_ADC_CHANNEL_TEMPSENSOR, ...),
<>	144:ef7eb2e8f9f7	1594	* to its equivalent parameter definition of a ADC external channel
<>	144:ef7eb2e8f9f7	1595	* (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
<>	144:ef7eb2e8f9f7	1596	* @note The channel parameter can be, additionally to a value
<>	144:ef7eb2e8f9f7	1597	* defined from parameter definition of a ADC internal channel
<>	144:ef7eb2e8f9f7	1598	* (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
<>	144:ef7eb2e8f9f7	1599	* a value defined from parameter definition of
<>	144:ef7eb2e8f9f7	1600	* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
<>	144:ef7eb2e8f9f7	1601	* or a value from functions where a channel number is returned
<>	144:ef7eb2e8f9f7	1602	* from ADC registers.
<>	144:ef7eb2e8f9f7	1603	* @param __CHANNEL__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1604	* @arg @ref LL_ADC_CHANNEL_0
<>	144:ef7eb2e8f9f7	1605	* @arg @ref LL_ADC_CHANNEL_1 (7)
<>	144:ef7eb2e8f9f7	1606	* @arg @ref LL_ADC_CHANNEL_2 (7)
<>	144:ef7eb2e8f9f7	1607	* @arg @ref LL_ADC_CHANNEL_3 (7)
<>	144:ef7eb2e8f9f7	1608	* @arg @ref LL_ADC_CHANNEL_4 (7)
<>	144:ef7eb2e8f9f7	1609	* @arg @ref LL_ADC_CHANNEL_5 (7)
<>	144:ef7eb2e8f9f7	1610	* @arg @ref LL_ADC_CHANNEL_6
<>	144:ef7eb2e8f9f7	1611	* @arg @ref LL_ADC_CHANNEL_7
<>	144:ef7eb2e8f9f7	1612	* @arg @ref LL_ADC_CHANNEL_8
<>	144:ef7eb2e8f9f7	1613	* @arg @ref LL_ADC_CHANNEL_9
<>	144:ef7eb2e8f9f7	1614	* @arg @ref LL_ADC_CHANNEL_10
<>	144:ef7eb2e8f9f7	1615	* @arg @ref LL_ADC_CHANNEL_11
<>	144:ef7eb2e8f9f7	1616	* @arg @ref LL_ADC_CHANNEL_12
<>	144:ef7eb2e8f9f7	1617	* @arg @ref LL_ADC_CHANNEL_13
<>	144:ef7eb2e8f9f7	1618	* @arg @ref LL_ADC_CHANNEL_14
<>	144:ef7eb2e8f9f7	1619	* @arg @ref LL_ADC_CHANNEL_15
<>	144:ef7eb2e8f9f7	1620	* @arg @ref LL_ADC_CHANNEL_16
<>	144:ef7eb2e8f9f7	1621	* @arg @ref LL_ADC_CHANNEL_17
<>	144:ef7eb2e8f9f7	1622	* @arg @ref LL_ADC_CHANNEL_18
<>	144:ef7eb2e8f9f7	1623	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	144:ef7eb2e8f9f7	1624	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
<>	144:ef7eb2e8f9f7	1625	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
<>	144:ef7eb2e8f9f7	1626	* @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
<>	144:ef7eb2e8f9f7	1627	* @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
<>	144:ef7eb2e8f9f7	1628	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	1629	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	1630	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	1631	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	1632	*
<>	144:ef7eb2e8f9f7	1633	* (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
<>	144:ef7eb2e8f9f7	1634	* (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
<>	144:ef7eb2e8f9f7	1635	* (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
<>	144:ef7eb2e8f9f7	1636	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
<>	144:ef7eb2e8f9f7	1637	* (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
<>	144:ef7eb2e8f9f7	1638	* (6) On STM32L4, parameter available on devices with several ADC instances.\n
<>	144:ef7eb2e8f9f7	1639	* (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
<>	144:ef7eb2e8f9f7	1640	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
<>	144:ef7eb2e8f9f7	1641	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	1642	* @arg @ref LL_ADC_CHANNEL_0
<>	144:ef7eb2e8f9f7	1643	* @arg @ref LL_ADC_CHANNEL_1
<>	144:ef7eb2e8f9f7	1644	* @arg @ref LL_ADC_CHANNEL_2
<>	144:ef7eb2e8f9f7	1645	* @arg @ref LL_ADC_CHANNEL_3
<>	144:ef7eb2e8f9f7	1646	* @arg @ref LL_ADC_CHANNEL_4
<>	144:ef7eb2e8f9f7	1647	* @arg @ref LL_ADC_CHANNEL_5
<>	144:ef7eb2e8f9f7	1648	* @arg @ref LL_ADC_CHANNEL_6
<>	144:ef7eb2e8f9f7	1649	* @arg @ref LL_ADC_CHANNEL_7
<>	144:ef7eb2e8f9f7	1650	* @arg @ref LL_ADC_CHANNEL_8
<>	144:ef7eb2e8f9f7	1651	* @arg @ref LL_ADC_CHANNEL_9
<>	144:ef7eb2e8f9f7	1652	* @arg @ref LL_ADC_CHANNEL_10
<>	144:ef7eb2e8f9f7	1653	* @arg @ref LL_ADC_CHANNEL_11
<>	144:ef7eb2e8f9f7	1654	* @arg @ref LL_ADC_CHANNEL_12
<>	144:ef7eb2e8f9f7	1655	* @arg @ref LL_ADC_CHANNEL_13
<>	144:ef7eb2e8f9f7	1656	* @arg @ref LL_ADC_CHANNEL_14
<>	144:ef7eb2e8f9f7	1657	* @arg @ref LL_ADC_CHANNEL_15
<>	144:ef7eb2e8f9f7	1658	* @arg @ref LL_ADC_CHANNEL_16
<>	144:ef7eb2e8f9f7	1659	* @arg @ref LL_ADC_CHANNEL_17
<>	144:ef7eb2e8f9f7	1660	* @arg @ref LL_ADC_CHANNEL_18
<>	144:ef7eb2e8f9f7	1661	*/
<>	144:ef7eb2e8f9f7	1662	#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
<>	144:ef7eb2e8f9f7	1663	((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
<>	144:ef7eb2e8f9f7	1664
<>	144:ef7eb2e8f9f7	1665	/**
<>	144:ef7eb2e8f9f7	1666	* @brief Helper macro to determine whether the internal channel
<>	144:ef7eb2e8f9f7	1667	* selected is available on the ADC instance selected.
<>	144:ef7eb2e8f9f7	1668	* @note The channel parameter must be a value defined from parameter
<>	144:ef7eb2e8f9f7	1669	* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
<>	144:ef7eb2e8f9f7	1670	* LL_ADC_CHANNEL_TEMPSENSOR, ...),
<>	144:ef7eb2e8f9f7	1671	* must not be a value defined from parameter definition of
<>	144:ef7eb2e8f9f7	1672	* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
<>	144:ef7eb2e8f9f7	1673	* or a value from functions where a channel number is
<>	144:ef7eb2e8f9f7	1674	* returned from ADC registers,
<>	144:ef7eb2e8f9f7	1675	* because internal and external channels share the same channel
<>	144:ef7eb2e8f9f7	1676	* number in ADC registers. The differentiation is made only with
<>	144:ef7eb2e8f9f7	1677	* parameters definitions of driver.
<>	144:ef7eb2e8f9f7	1678	* @param __ADC_INSTANCE__ ADC instance
<>	144:ef7eb2e8f9f7	1679	* @param __CHANNEL__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1680	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	144:ef7eb2e8f9f7	1681	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
<>	144:ef7eb2e8f9f7	1682	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
<>	144:ef7eb2e8f9f7	1683	* @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
<>	144:ef7eb2e8f9f7	1684	* @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
<>	144:ef7eb2e8f9f7	1685	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	1686	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	1687	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	1688	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	1689	*
<>	144:ef7eb2e8f9f7	1690	* (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
<>	144:ef7eb2e8f9f7	1691	* (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
<>	144:ef7eb2e8f9f7	1692	* (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
<>	144:ef7eb2e8f9f7	1693	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
<>	144:ef7eb2e8f9f7	1694	* (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
<>	144:ef7eb2e8f9f7	1695	* (6) On STM32L4, parameter available on devices with several ADC instances.\n
<>	144:ef7eb2e8f9f7	1696	* @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
<>	144:ef7eb2e8f9f7	1697	* Value "1" if the internal channel selected is available on the ADC instance selected.
<>	144:ef7eb2e8f9f7	1698	*/
<>	144:ef7eb2e8f9f7	1699	#if defined (ADC1) && defined (ADC2) && defined (ADC3)
<>	144:ef7eb2e8f9f7	1700	#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
<>	144:ef7eb2e8f9f7	1701	(((__ADC_INSTANCE__) == ADC1) \
<>	144:ef7eb2e8f9f7	1702	? ( \
<>	144:ef7eb2e8f9f7	1703	((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \|\| \
<>	144:ef7eb2e8f9f7	1704	((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \|\| \
<>	144:ef7eb2e8f9f7	1705	((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
<>	144:ef7eb2e8f9f7	1706	) \
<>	144:ef7eb2e8f9f7	1707	: \
<>	144:ef7eb2e8f9f7	1708	((__ADC_INSTANCE__) == ADC2) \
<>	144:ef7eb2e8f9f7	1709	? ( \
<>	144:ef7eb2e8f9f7	1710	((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \|\| \
<>	144:ef7eb2e8f9f7	1711	((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) \|\| \
<>	144:ef7eb2e8f9f7	1712	((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \
<>	144:ef7eb2e8f9f7	1713	) \
<>	144:ef7eb2e8f9f7	1714	: \
<>	144:ef7eb2e8f9f7	1715	((__ADC_INSTANCE__) == ADC3) \
<>	144:ef7eb2e8f9f7	1716	? ( \
<>	144:ef7eb2e8f9f7	1717	((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \|\| \
<>	144:ef7eb2e8f9f7	1718	((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \|\| \
<>	144:ef7eb2e8f9f7	1719	((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \|\| \
<>	144:ef7eb2e8f9f7	1720	((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC3) \|\| \
<>	144:ef7eb2e8f9f7	1721	((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC3) \
<>	144:ef7eb2e8f9f7	1722	) \
<>	144:ef7eb2e8f9f7	1723	: \
<>	144:ef7eb2e8f9f7	1724	(0U) \
<>	144:ef7eb2e8f9f7	1725	)
<>	144:ef7eb2e8f9f7	1726	#elif defined (ADC1) && defined (ADC2)
<>	144:ef7eb2e8f9f7	1727	#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
<>	144:ef7eb2e8f9f7	1728	(((__ADC_INSTANCE__) == ADC1) \
<>	144:ef7eb2e8f9f7	1729	? ( \
<>	144:ef7eb2e8f9f7	1730	((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \|\| \
<>	144:ef7eb2e8f9f7	1731	((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \|\| \
<>	144:ef7eb2e8f9f7	1732	((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
<>	144:ef7eb2e8f9f7	1733	) \
<>	144:ef7eb2e8f9f7	1734	: \
<>	144:ef7eb2e8f9f7	1735	((__ADC_INSTANCE__) == ADC2) \
<>	144:ef7eb2e8f9f7	1736	? ( \
<>	144:ef7eb2e8f9f7	1737	((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \|\| \
<>	144:ef7eb2e8f9f7	1738	((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) \|\| \
<>	144:ef7eb2e8f9f7	1739	((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \
<>	144:ef7eb2e8f9f7	1740	) \
<>	144:ef7eb2e8f9f7	1741	: \
<>	144:ef7eb2e8f9f7	1742	(0U) \
<>	144:ef7eb2e8f9f7	1743	)
<>	144:ef7eb2e8f9f7	1744	#elif defined (ADC1)
<>	144:ef7eb2e8f9f7	1745	#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
<>	144:ef7eb2e8f9f7	1746	( \
<>	144:ef7eb2e8f9f7	1747	((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \|\| \
<>	144:ef7eb2e8f9f7	1748	((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \|\| \
<>	144:ef7eb2e8f9f7	1749	((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \|\| \
<>	144:ef7eb2e8f9f7	1750	((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1) \|\| \
<>	144:ef7eb2e8f9f7	1751	((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2) \
<>	144:ef7eb2e8f9f7	1752	)
<>	144:ef7eb2e8f9f7	1753	#endif
<>	144:ef7eb2e8f9f7	1754
<>	144:ef7eb2e8f9f7	1755	/**
<>	144:ef7eb2e8f9f7	1756	* @brief Helper macro to define ADC analog watchdog parameter:
<>	144:ef7eb2e8f9f7	1757	* define a single channel to monitor with analog watchdog
<>	144:ef7eb2e8f9f7	1758	* from sequencer channel and groups definition.
<>	144:ef7eb2e8f9f7	1759	* @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
<>	144:ef7eb2e8f9f7	1760	* Example:
<>	144:ef7eb2e8f9f7	1761	* LL_ADC_SetAnalogWDMonitChannels(
<>	144:ef7eb2e8f9f7	1762	* ADC1, LL_ADC_AWD1,
<>	144:ef7eb2e8f9f7	1763	* __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
<>	144:ef7eb2e8f9f7	1764	* @param __CHANNEL__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1765	* @arg @ref LL_ADC_CHANNEL_0
<>	144:ef7eb2e8f9f7	1766	* @arg @ref LL_ADC_CHANNEL_1 (7)
<>	144:ef7eb2e8f9f7	1767	* @arg @ref LL_ADC_CHANNEL_2 (7)
<>	144:ef7eb2e8f9f7	1768	* @arg @ref LL_ADC_CHANNEL_3 (7)
<>	144:ef7eb2e8f9f7	1769	* @arg @ref LL_ADC_CHANNEL_4 (7)
<>	144:ef7eb2e8f9f7	1770	* @arg @ref LL_ADC_CHANNEL_5 (7)
<>	144:ef7eb2e8f9f7	1771	* @arg @ref LL_ADC_CHANNEL_6
<>	144:ef7eb2e8f9f7	1772	* @arg @ref LL_ADC_CHANNEL_7
<>	144:ef7eb2e8f9f7	1773	* @arg @ref LL_ADC_CHANNEL_8
<>	144:ef7eb2e8f9f7	1774	* @arg @ref LL_ADC_CHANNEL_9
<>	144:ef7eb2e8f9f7	1775	* @arg @ref LL_ADC_CHANNEL_10
<>	144:ef7eb2e8f9f7	1776	* @arg @ref LL_ADC_CHANNEL_11
<>	144:ef7eb2e8f9f7	1777	* @arg @ref LL_ADC_CHANNEL_12
<>	144:ef7eb2e8f9f7	1778	* @arg @ref LL_ADC_CHANNEL_13
<>	144:ef7eb2e8f9f7	1779	* @arg @ref LL_ADC_CHANNEL_14
<>	144:ef7eb2e8f9f7	1780	* @arg @ref LL_ADC_CHANNEL_15
<>	144:ef7eb2e8f9f7	1781	* @arg @ref LL_ADC_CHANNEL_16
<>	144:ef7eb2e8f9f7	1782	* @arg @ref LL_ADC_CHANNEL_17
<>	144:ef7eb2e8f9f7	1783	* @arg @ref LL_ADC_CHANNEL_18
<>	144:ef7eb2e8f9f7	1784	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	144:ef7eb2e8f9f7	1785	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
<>	144:ef7eb2e8f9f7	1786	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
<>	144:ef7eb2e8f9f7	1787	* @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
<>	144:ef7eb2e8f9f7	1788	* @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
<>	144:ef7eb2e8f9f7	1789	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	1790	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	1791	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	1792	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	1793	*
<>	144:ef7eb2e8f9f7	1794	* (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
<>	144:ef7eb2e8f9f7	1795	* (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
<>	144:ef7eb2e8f9f7	1796	* (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
<>	144:ef7eb2e8f9f7	1797	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
<>	144:ef7eb2e8f9f7	1798	* (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
<>	144:ef7eb2e8f9f7	1799	* (6) On STM32L4, parameter available on devices with several ADC instances.\n
<>	144:ef7eb2e8f9f7	1800	* (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
<>	144:ef7eb2e8f9f7	1801	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
<>	144:ef7eb2e8f9f7	1802	* (1, 2, 3, 4) For ADC channel read back from ADC register,
<>	144:ef7eb2e8f9f7	1803	* comparison with internal channel parameter to be done
<>	144:ef7eb2e8f9f7	1804	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
<>	144:ef7eb2e8f9f7	1805	* @param __GROUP__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1806	* @arg @ref LL_ADC_GROUP_REGULAR
<>	144:ef7eb2e8f9f7	1807	* @arg @ref LL_ADC_GROUP_INJECTED
<>	144:ef7eb2e8f9f7	1808	* @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
<>	144:ef7eb2e8f9f7	1809	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	1810	* @arg @ref LL_ADC_AWD_DISABLE
<>	144:ef7eb2e8f9f7	1811	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
<>	144:ef7eb2e8f9f7	1812	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
<>	144:ef7eb2e8f9f7	1813	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
<>	144:ef7eb2e8f9f7	1814	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
<>	144:ef7eb2e8f9f7	1815	* @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
<>	144:ef7eb2e8f9f7	1816	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
<>	144:ef7eb2e8f9f7	1817	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
<>	144:ef7eb2e8f9f7	1818	* @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
<>	144:ef7eb2e8f9f7	1819	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
<>	144:ef7eb2e8f9f7	1820	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
<>	144:ef7eb2e8f9f7	1821	* @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
<>	144:ef7eb2e8f9f7	1822	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
<>	144:ef7eb2e8f9f7	1823	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
<>	144:ef7eb2e8f9f7	1824	* @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
<>	144:ef7eb2e8f9f7	1825	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
<>	144:ef7eb2e8f9f7	1826	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
<>	144:ef7eb2e8f9f7	1827	* @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
<>	144:ef7eb2e8f9f7	1828	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
<>	144:ef7eb2e8f9f7	1829	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
<>	144:ef7eb2e8f9f7	1830	* @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
<>	144:ef7eb2e8f9f7	1831	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
<>	144:ef7eb2e8f9f7	1832	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
<>	144:ef7eb2e8f9f7	1833	* @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
<>	144:ef7eb2e8f9f7	1834	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
<>	144:ef7eb2e8f9f7	1835	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
<>	144:ef7eb2e8f9f7	1836	* @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
<>	144:ef7eb2e8f9f7	1837	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
<>	144:ef7eb2e8f9f7	1838	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
<>	144:ef7eb2e8f9f7	1839	* @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
<>	144:ef7eb2e8f9f7	1840	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
<>	144:ef7eb2e8f9f7	1841	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
<>	144:ef7eb2e8f9f7	1842	* @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
<>	144:ef7eb2e8f9f7	1843	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
<>	144:ef7eb2e8f9f7	1844	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
<>	144:ef7eb2e8f9f7	1845	* @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
<>	144:ef7eb2e8f9f7	1846	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
<>	144:ef7eb2e8f9f7	1847	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
<>	144:ef7eb2e8f9f7	1848	* @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
<>	144:ef7eb2e8f9f7	1849	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
<>	144:ef7eb2e8f9f7	1850	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
<>	144:ef7eb2e8f9f7	1851	* @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
<>	144:ef7eb2e8f9f7	1852	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
<>	144:ef7eb2e8f9f7	1853	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
<>	144:ef7eb2e8f9f7	1854	* @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
<>	144:ef7eb2e8f9f7	1855	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
<>	144:ef7eb2e8f9f7	1856	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
<>	144:ef7eb2e8f9f7	1857	* @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
<>	144:ef7eb2e8f9f7	1858	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
<>	144:ef7eb2e8f9f7	1859	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
<>	144:ef7eb2e8f9f7	1860	* @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
<>	144:ef7eb2e8f9f7	1861	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
<>	144:ef7eb2e8f9f7	1862	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
<>	144:ef7eb2e8f9f7	1863	* @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
<>	144:ef7eb2e8f9f7	1864	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
<>	144:ef7eb2e8f9f7	1865	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
<>	144:ef7eb2e8f9f7	1866	* @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
<>	144:ef7eb2e8f9f7	1867	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
<>	144:ef7eb2e8f9f7	1868	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
<>	144:ef7eb2e8f9f7	1869	* @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
<>	144:ef7eb2e8f9f7	1870	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
<>	144:ef7eb2e8f9f7	1871	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
<>	144:ef7eb2e8f9f7	1872	* @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
<>	144:ef7eb2e8f9f7	1873	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
<>	144:ef7eb2e8f9f7	1874	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(4)
<>	144:ef7eb2e8f9f7	1875	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(4)
<>	144:ef7eb2e8f9f7	1876	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (4)
<>	144:ef7eb2e8f9f7	1877	* @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(4)
<>	144:ef7eb2e8f9f7	1878	* @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(4)
<>	144:ef7eb2e8f9f7	1879	* @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (4)
<>	144:ef7eb2e8f9f7	1880	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG (0)(2)(5)
<>	144:ef7eb2e8f9f7	1881	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_INJ (0)(2)(5)
<>	144:ef7eb2e8f9f7	1882	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG_INJ (2)(5)
<>	144:ef7eb2e8f9f7	1883	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG (0)(2)(5)
<>	144:ef7eb2e8f9f7	1884	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_INJ (0)(2)(5)
<>	144:ef7eb2e8f9f7	1885	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG_INJ (2)(5)
<>	144:ef7eb2e8f9f7	1886	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(2)(6)
<>	144:ef7eb2e8f9f7	1887	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(2)(6)
<>	144:ef7eb2e8f9f7	1888	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (2)(6)
<>	144:ef7eb2e8f9f7	1889	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)(6)
<>	144:ef7eb2e8f9f7	1890	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)(6)
<>	144:ef7eb2e8f9f7	1891	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)(6)
<>	144:ef7eb2e8f9f7	1892	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG (0)(3)(6)
<>	144:ef7eb2e8f9f7	1893	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ (0)(3)(6)
<>	144:ef7eb2e8f9f7	1894	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ (3)(6)
<>	144:ef7eb2e8f9f7	1895	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG (0)(3)(6)
<>	144:ef7eb2e8f9f7	1896	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ (0)(3)(6)
<>	144:ef7eb2e8f9f7	1897	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ (3)(6)
<>	144:ef7eb2e8f9f7	1898	*
<>	144:ef7eb2e8f9f7	1899	* (0) On STM32L4, parameter available only on analog watchdog number: AWD1.\n
<>	144:ef7eb2e8f9f7	1900	* (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
<>	144:ef7eb2e8f9f7	1901	* (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
<>	144:ef7eb2e8f9f7	1902	* (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
<>	144:ef7eb2e8f9f7	1903	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
<>	144:ef7eb2e8f9f7	1904	* (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
<>	144:ef7eb2e8f9f7	1905	* (6) On STM32L4, parameter available on devices with several ADC instances.
<>	144:ef7eb2e8f9f7	1906	*/
<>	144:ef7eb2e8f9f7	1907	#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
<>	144:ef7eb2e8f9f7	1908	(((__GROUP__) == LL_ADC_GROUP_REGULAR) \
<>	144:ef7eb2e8f9f7	1909	? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) \
<>	144:ef7eb2e8f9f7	1910	: \
<>	144:ef7eb2e8f9f7	1911	((__GROUP__) == LL_ADC_GROUP_INJECTED) \
<>	144:ef7eb2e8f9f7	1912	? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL) \
<>	144:ef7eb2e8f9f7	1913	: \
<>	144:ef7eb2e8f9f7	1914	(((__CHANNEL__) & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL) \
<>	144:ef7eb2e8f9f7	1915	)
<>	144:ef7eb2e8f9f7	1916
<>	144:ef7eb2e8f9f7	1917	/**
<>	144:ef7eb2e8f9f7	1918	* @brief Helper macro to set the value of ADC analog watchdog threshold high
<>	144:ef7eb2e8f9f7	1919	* or low in function of ADC resolution, when ADC resolution is
<>	144:ef7eb2e8f9f7	1920	* different of 12 bits.
<>	144:ef7eb2e8f9f7	1921	* @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
<>	144:ef7eb2e8f9f7	1922	* or @ref LL_ADC_SetAnalogWDThresholds().
<>	144:ef7eb2e8f9f7	1923	* Example, with a ADC resolution of 8 bits, to set the value of
<>	144:ef7eb2e8f9f7	1924	* analog watchdog threshold high (on 8 bits):
<>	144:ef7eb2e8f9f7	1925	* LL_ADC_SetAnalogWDThresholds
<>	144:ef7eb2e8f9f7	1926	* (< ADCx param >,
<>	144:ef7eb2e8f9f7	1927	* __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
<>	144:ef7eb2e8f9f7	1928	* );
<>	144:ef7eb2e8f9f7	1929	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1930	* @arg @ref LL_ADC_RESOLUTION_12B
<>	144:ef7eb2e8f9f7	1931	* @arg @ref LL_ADC_RESOLUTION_10B
<>	144:ef7eb2e8f9f7	1932	* @arg @ref LL_ADC_RESOLUTION_8B
<>	144:ef7eb2e8f9f7	1933	* @arg @ref LL_ADC_RESOLUTION_6B
<>	144:ef7eb2e8f9f7	1934	* @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
<>	144:ef7eb2e8f9f7	1935	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	144:ef7eb2e8f9f7	1936	*/
<>	144:ef7eb2e8f9f7	1937	#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
<>	144:ef7eb2e8f9f7	1938	((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
<>	144:ef7eb2e8f9f7	1939
<>	144:ef7eb2e8f9f7	1940	/**
<>	144:ef7eb2e8f9f7	1941	* @brief Helper macro to get the value of ADC analog watchdog threshold high
<>	144:ef7eb2e8f9f7	1942	* or low in function of ADC resolution, when ADC resolution is
<>	144:ef7eb2e8f9f7	1943	* different of 12 bits.
<>	144:ef7eb2e8f9f7	1944	* @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
<>	144:ef7eb2e8f9f7	1945	* Example, with a ADC resolution of 8 bits, to get the value of
<>	144:ef7eb2e8f9f7	1946	* analog watchdog threshold high (on 8 bits):
<>	144:ef7eb2e8f9f7	1947	* < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
<>	144:ef7eb2e8f9f7	1948	* (LL_ADC_RESOLUTION_8B,
<>	144:ef7eb2e8f9f7	1949	* LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
<>	144:ef7eb2e8f9f7	1950	* );
<>	144:ef7eb2e8f9f7	1951	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1952	* @arg @ref LL_ADC_RESOLUTION_12B
<>	144:ef7eb2e8f9f7	1953	* @arg @ref LL_ADC_RESOLUTION_10B
<>	144:ef7eb2e8f9f7	1954	* @arg @ref LL_ADC_RESOLUTION_8B
<>	144:ef7eb2e8f9f7	1955	* @arg @ref LL_ADC_RESOLUTION_6B
<>	144:ef7eb2e8f9f7	1956	* @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
<>	144:ef7eb2e8f9f7	1957	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	144:ef7eb2e8f9f7	1958	*/
<>	144:ef7eb2e8f9f7	1959	#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
<>	144:ef7eb2e8f9f7	1960	((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
<>	144:ef7eb2e8f9f7	1961
<>	144:ef7eb2e8f9f7	1962	/**
<>	144:ef7eb2e8f9f7	1963	* @brief Helper macro to get the ADC analog watchdog threshold high
<>	144:ef7eb2e8f9f7	1964	* or low from raw value containing both thresholds concatenated.
<>	144:ef7eb2e8f9f7	1965	* @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
<>	144:ef7eb2e8f9f7	1966	* Example, to get analog watchdog threshold high from the register raw value:
<>	144:ef7eb2e8f9f7	1967	* __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
<>	144:ef7eb2e8f9f7	1968	* @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1969	* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
<>	144:ef7eb2e8f9f7	1970	* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
<>	144:ef7eb2e8f9f7	1971	* @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
<>	144:ef7eb2e8f9f7	1972	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	144:ef7eb2e8f9f7	1973	*/
<>	144:ef7eb2e8f9f7	1974	#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
<>	144:ef7eb2e8f9f7	1975	(((__AWD_THRESHOLDS__) >> POSITION_VAL((__AWD_THRESHOLD_TYPE__))) & LL_ADC_AWD_THRESHOLD_LOW)
<>	144:ef7eb2e8f9f7	1976
<>	144:ef7eb2e8f9f7	1977	/**
<>	144:ef7eb2e8f9f7	1978	* @brief Helper macro to set the ADC calibration value with both single ended
<>	144:ef7eb2e8f9f7	1979	* and differential modes calibration factors concatenated.
<>	144:ef7eb2e8f9f7	1980	* @note To be used with function @ref LL_ADC_SetCalibrationFactor().
<>	144:ef7eb2e8f9f7	1981	* Example, to set calibration factors single ended to 0x55
<>	144:ef7eb2e8f9f7	1982	* and differential ended to 0x2A:
<>	144:ef7eb2e8f9f7	1983	* LL_ADC_SetCalibrationFactor(
<>	144:ef7eb2e8f9f7	1984	* ADC1,
<>	144:ef7eb2e8f9f7	1985	* __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
<>	144:ef7eb2e8f9f7	1986	* @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
<>	144:ef7eb2e8f9f7	1987	* @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
<>	144:ef7eb2e8f9f7	1988	* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
<>	144:ef7eb2e8f9f7	1989	*/
<>	144:ef7eb2e8f9f7	1990	#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
<>	144:ef7eb2e8f9f7	1991	(((__CALIB_FACTOR_DIFFERENTIAL__) << POSITION_VAL(ADC_CALFACT_CALFACT_D)) \| (__CALIB_FACTOR_SINGLE_ENDED__))
<>	144:ef7eb2e8f9f7	1992
<>	144:ef7eb2e8f9f7	1993	#if defined(ADC_MULTIMODE_SUPPORT)
<>	144:ef7eb2e8f9f7	1994	/**
<>	144:ef7eb2e8f9f7	1995	* @brief Helper macro to get the ADC multimode conversion data of ADC master
<>	144:ef7eb2e8f9f7	1996	* or ADC slave from raw value with both ADC conversion data concatenated.
<>	144:ef7eb2e8f9f7	1997	* @note This macro is intended to be used when multimode transfer by DMA
<>	144:ef7eb2e8f9f7	1998	* is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
<>	144:ef7eb2e8f9f7	1999	* In this case the transferred data need to processed with this macro
<>	144:ef7eb2e8f9f7	2000	* to separate the conversion data of ADC master and ADC slave.
<>	144:ef7eb2e8f9f7	2001	* @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2002	* @arg @ref LL_ADC_MULTI_MASTER
<>	144:ef7eb2e8f9f7	2003	* @arg @ref LL_ADC_MULTI_SLAVE
<>	144:ef7eb2e8f9f7	2004	* @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
<>	144:ef7eb2e8f9f7	2005	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	144:ef7eb2e8f9f7	2006	*/
<>	144:ef7eb2e8f9f7	2007	#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
<>	144:ef7eb2e8f9f7	2008	(((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
<>	144:ef7eb2e8f9f7	2009	#endif
<>	144:ef7eb2e8f9f7	2010
<>	144:ef7eb2e8f9f7	2011	/**
<>	144:ef7eb2e8f9f7	2012	* @brief Helper macro to select the ADC common instance
<>	144:ef7eb2e8f9f7	2013	* to which is belonging the selected ADC instance.
<>	144:ef7eb2e8f9f7	2014	* @note ADC common register instance can be used for:
<>	144:ef7eb2e8f9f7	2015	* - Set parameters common to several ADC instances
<>	144:ef7eb2e8f9f7	2016	* - Multimode (for devices with several ADC instances)
<>	144:ef7eb2e8f9f7	2017	* Refer to functions having argument "ADCxy_COMMON" as parameter.
<>	144:ef7eb2e8f9f7	2018	* @param __ADCx__ ADC instance
<>	144:ef7eb2e8f9f7	2019	* @retval ADC common register instance
<>	144:ef7eb2e8f9f7	2020	*/
<>	144:ef7eb2e8f9f7	2021	#if defined(ADC1) && defined(ADC2) && defined(ADC3)
<>	144:ef7eb2e8f9f7	2022	#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
<>	144:ef7eb2e8f9f7	2023	(ADC123_COMMON)
<>	144:ef7eb2e8f9f7	2024	#elif defined(ADC1) && defined(ADC2)
<>	144:ef7eb2e8f9f7	2025	#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
<>	144:ef7eb2e8f9f7	2026	(ADC12_COMMON)
<>	144:ef7eb2e8f9f7	2027	#else
<>	144:ef7eb2e8f9f7	2028	#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
<>	144:ef7eb2e8f9f7	2029	(ADC1_COMMON)
<>	144:ef7eb2e8f9f7	2030	#endif
<>	144:ef7eb2e8f9f7	2031
<>	144:ef7eb2e8f9f7	2032	/**
<>	144:ef7eb2e8f9f7	2033	* @brief Helper macro to check if all ADC instances sharing the same
<>	144:ef7eb2e8f9f7	2034	* ADC common instance are disabled.
<>	144:ef7eb2e8f9f7	2035	* @note This check is required by functions with setting conditioned to
<>	144:ef7eb2e8f9f7	2036	* ADC state:
<>	144:ef7eb2e8f9f7	2037	* All ADC instances of the ADC common group must be disabled.
<>	144:ef7eb2e8f9f7	2038	* Refer to functions having argument "ADCxy_COMMON" as parameter.
<>	144:ef7eb2e8f9f7	2039	* @note On devices with only 1 ADC common instance, parameter of this macro
<>	144:ef7eb2e8f9f7	2040	* is useless and can be ignored (parameter kept for compatibility
<>	144:ef7eb2e8f9f7	2041	* with devices featuring several ADC common instances).
<>	144:ef7eb2e8f9f7	2042	* @param __ADCXY_COMMON__ ADC common instance
<>	144:ef7eb2e8f9f7	2043	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	2044	* @retval Value "0" if all ADC instances sharing the same ADC common instance
<>	144:ef7eb2e8f9f7	2045	* are disabled.
<>	144:ef7eb2e8f9f7	2046	* Value "1" if at least one ADC instance sharing the same ADC common instance
<>	144:ef7eb2e8f9f7	2047	* is enabled.
<>	144:ef7eb2e8f9f7	2048	*/
<>	144:ef7eb2e8f9f7	2049	#if defined(ADC1) && defined(ADC2) && defined(ADC3)
<>	144:ef7eb2e8f9f7	2050	#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
<>	144:ef7eb2e8f9f7	2051	(LL_ADC_IsEnabled(ADC1) \| \
<>	144:ef7eb2e8f9f7	2052	LL_ADC_IsEnabled(ADC2) \| \
<>	144:ef7eb2e8f9f7	2053	LL_ADC_IsEnabled(ADC3) )
<>	144:ef7eb2e8f9f7	2054	#elif defined(ADC1) && defined(ADC2)
<>	144:ef7eb2e8f9f7	2055	#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
<>	144:ef7eb2e8f9f7	2056	(LL_ADC_IsEnabled(ADC1) \| \
<>	144:ef7eb2e8f9f7	2057	LL_ADC_IsEnabled(ADC2) )
<>	144:ef7eb2e8f9f7	2058	#else
<>	144:ef7eb2e8f9f7	2059	#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
<>	144:ef7eb2e8f9f7	2060	(LL_ADC_IsEnabled(ADC1))
<>	144:ef7eb2e8f9f7	2061	#endif
<>	144:ef7eb2e8f9f7	2062
<>	144:ef7eb2e8f9f7	2063	/**
<>	144:ef7eb2e8f9f7	2064	* @brief Helper macro to define the ADC conversion data full-scale digital
<>	144:ef7eb2e8f9f7	2065	* value corresponding to the selected ADC resolution.
<>	144:ef7eb2e8f9f7	2066	* @note ADC conversion data full-scale corresponds to voltage range
<>	144:ef7eb2e8f9f7	2067	* determined by analog voltage references Vref+ and Vref-
<>	144:ef7eb2e8f9f7	2068	* (refer to reference manual).
<>	144:ef7eb2e8f9f7	2069	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2070	* @arg @ref LL_ADC_RESOLUTION_12B
<>	144:ef7eb2e8f9f7	2071	* @arg @ref LL_ADC_RESOLUTION_10B
<>	144:ef7eb2e8f9f7	2072	* @arg @ref LL_ADC_RESOLUTION_8B
<>	144:ef7eb2e8f9f7	2073	* @arg @ref LL_ADC_RESOLUTION_6B
<>	144:ef7eb2e8f9f7	2074	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
<>	144:ef7eb2e8f9f7	2075	*/
<>	144:ef7eb2e8f9f7	2076	#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
<>	144:ef7eb2e8f9f7	2077	(((uint32_t)0xFFFU) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)))
<>	144:ef7eb2e8f9f7	2078
<>	144:ef7eb2e8f9f7	2079	/**
<>	144:ef7eb2e8f9f7	2080	* @brief Helper macro to convert the ADC conversion data from
<>	144:ef7eb2e8f9f7	2081	* a resolution to another resolution.
<>	144:ef7eb2e8f9f7	2082	* @param __DATA__ ADC conversion data to be converted
<>	144:ef7eb2e8f9f7	2083	* @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
<>	144:ef7eb2e8f9f7	2084	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2085	* @arg @ref LL_ADC_RESOLUTION_12B
<>	144:ef7eb2e8f9f7	2086	* @arg @ref LL_ADC_RESOLUTION_10B
<>	144:ef7eb2e8f9f7	2087	* @arg @ref LL_ADC_RESOLUTION_8B
<>	144:ef7eb2e8f9f7	2088	* @arg @ref LL_ADC_RESOLUTION_6B
<>	144:ef7eb2e8f9f7	2089	* @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
<>	144:ef7eb2e8f9f7	2090	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2091	* @arg @ref LL_ADC_RESOLUTION_12B
<>	144:ef7eb2e8f9f7	2092	* @arg @ref LL_ADC_RESOLUTION_10B
<>	144:ef7eb2e8f9f7	2093	* @arg @ref LL_ADC_RESOLUTION_8B
<>	144:ef7eb2e8f9f7	2094	* @arg @ref LL_ADC_RESOLUTION_6B
<>	144:ef7eb2e8f9f7	2095	* @retval ADC conversion data to the requested resolution
<>	144:ef7eb2e8f9f7	2096	*/
<>	144:ef7eb2e8f9f7	2097	#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
<>	144:ef7eb2e8f9f7	2098	__ADC_RESOLUTION_CURRENT__,\
<>	144:ef7eb2e8f9f7	2099	__ADC_RESOLUTION_TARGET__) \
<>	144:ef7eb2e8f9f7	2100	(((__DATA__) \
<>	144:ef7eb2e8f9f7	2101	<< ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U))) \
<>	144:ef7eb2e8f9f7	2102	>> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)) \
<>	144:ef7eb2e8f9f7	2103	)
<>	144:ef7eb2e8f9f7	2104
<>	144:ef7eb2e8f9f7	2105	/**
<>	144:ef7eb2e8f9f7	2106	* @brief Helper macro to calculate the voltage (unit: mVolt)
<>	144:ef7eb2e8f9f7	2107	* corresponding to a ADC conversion data (unit: digital value).
<>	144:ef7eb2e8f9f7	2108	* @note Analog reference voltage (Vref+) must be either known from
<>	144:ef7eb2e8f9f7	2109	* user board environment or can be calculated using ADC measurement
<>	144:ef7eb2e8f9f7	2110	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
<>	144:ef7eb2e8f9f7	2111	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
<>	144:ef7eb2e8f9f7	2112	* @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
<>	144:ef7eb2e8f9f7	2113	* (unit: digital value).
<>	144:ef7eb2e8f9f7	2114	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2115	* @arg @ref LL_ADC_RESOLUTION_12B
<>	144:ef7eb2e8f9f7	2116	* @arg @ref LL_ADC_RESOLUTION_10B
<>	144:ef7eb2e8f9f7	2117	* @arg @ref LL_ADC_RESOLUTION_8B
<>	144:ef7eb2e8f9f7	2118	* @arg @ref LL_ADC_RESOLUTION_6B
<>	144:ef7eb2e8f9f7	2119	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
<>	144:ef7eb2e8f9f7	2120	*/
<>	144:ef7eb2e8f9f7	2121	#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
<>	144:ef7eb2e8f9f7	2122	__ADC_DATA__,\
<>	144:ef7eb2e8f9f7	2123	__ADC_RESOLUTION__) \
<>	144:ef7eb2e8f9f7	2124	((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
<>	144:ef7eb2e8f9f7	2125	/ __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
<>	144:ef7eb2e8f9f7	2126	)
<>	144:ef7eb2e8f9f7	2127
<>	144:ef7eb2e8f9f7	2128	/* Legacy define */
<>	144:ef7eb2e8f9f7	2129	#define __LL_ADC_CALC_DATA_VOLTAGE() __LL_ADC_CALC_DATA_TO_VOLTAGE()
<>	144:ef7eb2e8f9f7	2130
<>	144:ef7eb2e8f9f7	2131	/**
<>	144:ef7eb2e8f9f7	2132	* @brief Helper macro to calculate analog reference voltage (Vref+)
<>	144:ef7eb2e8f9f7	2133	* (unit: mVolt) from ADC conversion data of internal voltage
<>	144:ef7eb2e8f9f7	2134	* reference VrefInt.
<>	144:ef7eb2e8f9f7	2135	* @note Computation is using VrefInt calibration value
<>	144:ef7eb2e8f9f7	2136	* stored in system memory for each device during production.
<>	144:ef7eb2e8f9f7	2137	* @note This voltage depends on user board environment: voltage level
<>	144:ef7eb2e8f9f7	2138	* connected to pin Vref+.
<>	144:ef7eb2e8f9f7	2139	* On devices with small package, the pin Vref+ is not present
<>	144:ef7eb2e8f9f7	2140	* and internally bonded to pin Vdda.
<>	144:ef7eb2e8f9f7	2141	* @note On this STM32 serie, calibration data of internal voltage reference
<>	144:ef7eb2e8f9f7	2142	* VrefInt corresponds to a resolution of 12 bits,
<>	144:ef7eb2e8f9f7	2143	* this is the recommended ADC resolution to convert voltage of
<>	144:ef7eb2e8f9f7	2144	* internal voltage reference VrefInt.
<>	144:ef7eb2e8f9f7	2145	* Otherwise, this macro performs the processing to scale
<>	144:ef7eb2e8f9f7	2146	* ADC conversion data to 12 bits.
<>	144:ef7eb2e8f9f7	2147	* @param __VREFINT_ADC_DATA__: ADC conversion data (resolution 12 bits)
<>	144:ef7eb2e8f9f7	2148	* of internal voltage reference VrefInt (unit: digital value).
<>	144:ef7eb2e8f9f7	2149	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2150	* @arg @ref LL_ADC_RESOLUTION_12B
<>	144:ef7eb2e8f9f7	2151	* @arg @ref LL_ADC_RESOLUTION_10B
<>	144:ef7eb2e8f9f7	2152	* @arg @ref LL_ADC_RESOLUTION_8B
<>	144:ef7eb2e8f9f7	2153	* @arg @ref LL_ADC_RESOLUTION_6B
<>	144:ef7eb2e8f9f7	2154	* @retval Analog reference voltage (unit: mV)
<>	144:ef7eb2e8f9f7	2155	*/
<>	144:ef7eb2e8f9f7	2156	#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
<>	144:ef7eb2e8f9f7	2157	__ADC_RESOLUTION__) \
<>	144:ef7eb2e8f9f7	2158	(((uint32_t)(VREFINT_CAL_ADDR) VREFINT_CAL_VREF) \
<>	144:ef7eb2e8f9f7	2159	/ __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
<>	144:ef7eb2e8f9f7	2160	(__ADC_RESOLUTION__), \
<>	144:ef7eb2e8f9f7	2161	LL_ADC_RESOLUTION_12B) \
<>	144:ef7eb2e8f9f7	2162	)
<>	144:ef7eb2e8f9f7	2163
<>	144:ef7eb2e8f9f7	2164	/**
<>	144:ef7eb2e8f9f7	2165	* @brief Helper macro to calculate the temperature (unit: degree Celsius)
<>	144:ef7eb2e8f9f7	2166	* from ADC conversion data of internal temperature sensor.
<>	144:ef7eb2e8f9f7	2167	* @note Computation is using temperature sensor calibration values
<>	144:ef7eb2e8f9f7	2168	* stored in system memory for each device during production.
<>	144:ef7eb2e8f9f7	2169	* @note Calculation formula:
<>	144:ef7eb2e8f9f7	2170	* Temperature = ((TS_ADC_DATA - TS_CAL1)
<>	144:ef7eb2e8f9f7	2171	* * (TS_CAL2_TEMP - TS_CAL1_TEMP))
<>	144:ef7eb2e8f9f7	2172	* / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
<>	144:ef7eb2e8f9f7	2173	* with TS_ADC_DATA = temperature sensor raw data measured by ADC
<>	144:ef7eb2e8f9f7	2174	* Avg_Slope = (TS_CAL2 - TS_CAL1)
<>	144:ef7eb2e8f9f7	2175	* / (TS_CAL2_TEMP - TS_CAL1_TEMP)
<>	144:ef7eb2e8f9f7	2176	* TS_CAL1 = equivalent TS_ADC_DATA at temperature
<>	144:ef7eb2e8f9f7	2177	* TEMP_DEGC_CAL1 (calibrated in factory)
<>	144:ef7eb2e8f9f7	2178	* TS_CAL2 = equivalent TS_ADC_DATA at temperature
<>	144:ef7eb2e8f9f7	2179	* TEMP_DEGC_CAL2 (calibrated in factory)
<>	144:ef7eb2e8f9f7	2180	* Caution: Calculation relevancy under reserve that calibration
<>	144:ef7eb2e8f9f7	2181	* parameters are correct (address and data).
<>	144:ef7eb2e8f9f7	2182	* To calculate temperature using temperature sensor
<>	144:ef7eb2e8f9f7	2183	* datasheet typical values (generic values less, therefore
<>	144:ef7eb2e8f9f7	2184	* less accurate than calibrated values),
<>	144:ef7eb2e8f9f7	2185	* use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
<>	144:ef7eb2e8f9f7	2186	* @note As calculation input, the analog reference voltage (Vref+) must be
<>	144:ef7eb2e8f9f7	2187	* defined as it impacts the ADC LSB equivalent voltage.
<>	144:ef7eb2e8f9f7	2188	* @note Analog reference voltage (Vref+) must be either known from
<>	144:ef7eb2e8f9f7	2189	* user board environment or can be calculated using ADC measurement
<>	144:ef7eb2e8f9f7	2190	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
<>	144:ef7eb2e8f9f7	2191	* @note On this STM32 serie, calibration data of temperature sensor
<>	144:ef7eb2e8f9f7	2192	* corresponds to a resolution of 12 bits,
<>	144:ef7eb2e8f9f7	2193	* this is the recommended ADC resolution to convert voltage of
<>	144:ef7eb2e8f9f7	2194	* temperature sensor.
<>	144:ef7eb2e8f9f7	2195	* Otherwise, this macro performs the processing to scale
<>	144:ef7eb2e8f9f7	2196	* ADC conversion data to 12 bits.
<>	144:ef7eb2e8f9f7	2197	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
<>	144:ef7eb2e8f9f7	2198	* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
<>	144:ef7eb2e8f9f7	2199	* temperature sensor (unit: digital value).
<>	144:ef7eb2e8f9f7	2200	* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
<>	144:ef7eb2e8f9f7	2201	* sensor voltage has been measured.
<>	144:ef7eb2e8f9f7	2202	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2203	* @arg @ref LL_ADC_RESOLUTION_12B
<>	144:ef7eb2e8f9f7	2204	* @arg @ref LL_ADC_RESOLUTION_10B
<>	144:ef7eb2e8f9f7	2205	* @arg @ref LL_ADC_RESOLUTION_8B
<>	144:ef7eb2e8f9f7	2206	* @arg @ref LL_ADC_RESOLUTION_6B
<>	144:ef7eb2e8f9f7	2207	* @retval Temperature (unit: degree Celsius)
<>	144:ef7eb2e8f9f7	2208	*/
<>	144:ef7eb2e8f9f7	2209	#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
<>	144:ef7eb2e8f9f7	2210	__TEMPSENSOR_ADC_DATA__,\
<>	144:ef7eb2e8f9f7	2211	__ADC_RESOLUTION__) \
<>	144:ef7eb2e8f9f7	2212	(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
<>	144:ef7eb2e8f9f7	2213	(__ADC_RESOLUTION__), \
<>	144:ef7eb2e8f9f7	2214	LL_ADC_RESOLUTION_12B) \
<>	144:ef7eb2e8f9f7	2215	* (__VREFANALOG_VOLTAGE__)) \
<>	144:ef7eb2e8f9f7	2216	/ TEMPSENSOR_CAL_VREFANALOG) \
<>	144:ef7eb2e8f9f7	2217	- (int32_t) *TEMPSENSOR_CAL1_ADDR) \
<>	144:ef7eb2e8f9f7	2218	) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
<>	144:ef7eb2e8f9f7	2219	) / (int32_t)((int32_t)TEMPSENSOR_CAL2_ADDR - (int32_t)TEMPSENSOR_CAL1_ADDR) \
<>	144:ef7eb2e8f9f7	2220	) + TEMPSENSOR_CAL1_TEMP \
<>	144:ef7eb2e8f9f7	2221	)
<>	144:ef7eb2e8f9f7	2222
<>	144:ef7eb2e8f9f7	2223	/**
<>	144:ef7eb2e8f9f7	2224	* @brief Helper macro to calculate the temperature (unit: degree Celsius)
<>	144:ef7eb2e8f9f7	2225	* from ADC conversion data of internal temperature sensor.
<>	144:ef7eb2e8f9f7	2226	* @note Computation is using temperature sensor typical values
<>	144:ef7eb2e8f9f7	2227	* (refer to device datasheet).
<>	144:ef7eb2e8f9f7	2228	* @note Calculation formula:
<>	144:ef7eb2e8f9f7	2229	* Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
<>	144:ef7eb2e8f9f7	2230	* / Avg_Slope + CALx_TEMP
<>	144:ef7eb2e8f9f7	2231	* with TS_ADC_DATA = temperature sensor raw data measured by ADC
<>	144:ef7eb2e8f9f7	2232	* (unit: digital value)
<>	144:ef7eb2e8f9f7	2233	* Avg_Slope = temperature sensor slope
<>	144:ef7eb2e8f9f7	2234	* (unit: uV/Degree Celsius)
<>	144:ef7eb2e8f9f7	2235	* TS_TYP_CALx_VOLT = temperature sensor digital value at
<>	144:ef7eb2e8f9f7	2236	* temperature CALx_TEMP (unit: mV)
<>	144:ef7eb2e8f9f7	2237	* Caution: Calculation relevancy under reserve the temperature sensor
<>	144:ef7eb2e8f9f7	2238	* of the current device has characteristics in line with
<>	144:ef7eb2e8f9f7	2239	* datasheet typical values.
<>	144:ef7eb2e8f9f7	2240	* If temperature sensor calibration values are available on
<>	144:ef7eb2e8f9f7	2241	* on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
<>	144:ef7eb2e8f9f7	2242	* temperature calculation will be more accurate using
<>	144:ef7eb2e8f9f7	2243	* helper macro @ref __LL_ADC_CALC_TEMPERATURE().
<>	144:ef7eb2e8f9f7	2244	* @note As calculation input, the analog reference voltage (Vref+) must be
<>	144:ef7eb2e8f9f7	2245	* defined as it impacts the ADC LSB equivalent voltage.
<>	144:ef7eb2e8f9f7	2246	* @note Analog reference voltage (Vref+) must be either known from
<>	144:ef7eb2e8f9f7	2247	* user board environment or can be calculated using ADC measurement
<>	144:ef7eb2e8f9f7	2248	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
<>	144:ef7eb2e8f9f7	2249	* @note ADC measurement data must correspond to a resolution of 12bits
<>	144:ef7eb2e8f9f7	2250	* (full scale digital value 4095). If not the case, the data must be
<>	144:ef7eb2e8f9f7	2251	* preliminarily rescaled to an equivalent resolution of 12 bits.
<>	144:ef7eb2e8f9f7	2252	* @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
<>	144:ef7eb2e8f9f7	2253	* On STM32L4, refer to device datasheet parameter "Avg_Slope".
<>	144:ef7eb2e8f9f7	2254	* @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
<>	144:ef7eb2e8f9f7	2255	* On STM32L4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
<>	144:ef7eb2e8f9f7	2256	* @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
<>	144:ef7eb2e8f9f7	2257	* @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
<>	144:ef7eb2e8f9f7	2258	* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
<>	144:ef7eb2e8f9f7	2259	* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
<>	144:ef7eb2e8f9f7	2260	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2261	* @arg @ref LL_ADC_RESOLUTION_12B
<>	144:ef7eb2e8f9f7	2262	* @arg @ref LL_ADC_RESOLUTION_10B
<>	144:ef7eb2e8f9f7	2263	* @arg @ref LL_ADC_RESOLUTION_8B
<>	144:ef7eb2e8f9f7	2264	* @arg @ref LL_ADC_RESOLUTION_6B
<>	144:ef7eb2e8f9f7	2265	* @retval Temperature (unit: degree Celsius)
<>	144:ef7eb2e8f9f7	2266	*/
<>	144:ef7eb2e8f9f7	2267	#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
<>	144:ef7eb2e8f9f7	2268	__TEMPSENSOR_TYP_CALX_V__,\
<>	144:ef7eb2e8f9f7	2269	__TEMPSENSOR_CALX_TEMP__,\
<>	144:ef7eb2e8f9f7	2270	__VREFANALOG_VOLTAGE__,\
<>	144:ef7eb2e8f9f7	2271	__TEMPSENSOR_ADC_DATA__,\
<>	144:ef7eb2e8f9f7	2272	__ADC_RESOLUTION__) \
<>	144:ef7eb2e8f9f7	2273	((( ( \
<>	144:ef7eb2e8f9f7	2274	(int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
<>	144:ef7eb2e8f9f7	2275	/ __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
<>	144:ef7eb2e8f9f7	2276	* 1000) \
<>	144:ef7eb2e8f9f7	2277	- \
<>	144:ef7eb2e8f9f7	2278	(int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
<>	144:ef7eb2e8f9f7	2279	* 1000) \
<>	144:ef7eb2e8f9f7	2280	) \
<>	144:ef7eb2e8f9f7	2281	) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
<>	144:ef7eb2e8f9f7	2282	) + (__TEMPSENSOR_CALX_TEMP__) \
<>	144:ef7eb2e8f9f7	2283	)
<>	144:ef7eb2e8f9f7	2284
<>	144:ef7eb2e8f9f7	2285	/**
<>	144:ef7eb2e8f9f7	2286	* @}
<>	144:ef7eb2e8f9f7	2287	*/
<>	144:ef7eb2e8f9f7	2288
<>	144:ef7eb2e8f9f7	2289	/**
<>	144:ef7eb2e8f9f7	2290	* @}
<>	144:ef7eb2e8f9f7	2291	*/
<>	144:ef7eb2e8f9f7	2292
<>	144:ef7eb2e8f9f7	2293
<>	144:ef7eb2e8f9f7	2294	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	2295	/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
<>	144:ef7eb2e8f9f7	2296	* @{
<>	144:ef7eb2e8f9f7	2297	*/
<>	144:ef7eb2e8f9f7	2298
<>	144:ef7eb2e8f9f7	2299	/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
<>	144:ef7eb2e8f9f7	2300	* @{
<>	144:ef7eb2e8f9f7	2301	*/
<>	144:ef7eb2e8f9f7	2302	/* Note: LL ADC functions to set DMA transfer are located into sections of */
<>	144:ef7eb2e8f9f7	2303	/* configuration of ADC instance, groups and multimode (if available): */
<>	144:ef7eb2e8f9f7	2304	/* @ref LL_ADC_REG_SetDMATransfer(), ... */
<>	144:ef7eb2e8f9f7	2305
<>	144:ef7eb2e8f9f7	2306	/**
<>	144:ef7eb2e8f9f7	2307	* @brief Function to help to configure DMA transfer from ADC: retrieve the
<>	144:ef7eb2e8f9f7	2308	* ADC register address from ADC instance and a list of ADC registers
<>	144:ef7eb2e8f9f7	2309	* intended to be used (most commonly) with DMA transfer.
<>	144:ef7eb2e8f9f7	2310	* @note These ADC registers are data registers:
<>	144:ef7eb2e8f9f7	2311	* when ADC conversion data is available in ADC data registers,
<>	144:ef7eb2e8f9f7	2312	* ADC generates a DMA transfer request.
<>	144:ef7eb2e8f9f7	2313	* @note This macro is intended to be used with LL DMA driver, refer to
<>	144:ef7eb2e8f9f7	2314	* function "LL_DMA_ConfigAddresses()".
<>	144:ef7eb2e8f9f7	2315	* Example:
<>	144:ef7eb2e8f9f7	2316	* LL_DMA_ConfigAddresses(DMA1,
<>	144:ef7eb2e8f9f7	2317	* LL_DMA_CHANNEL_1,
<>	144:ef7eb2e8f9f7	2318	* LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
<>	144:ef7eb2e8f9f7	2319	* (uint32_t)&< array or variable >,
<>	144:ef7eb2e8f9f7	2320	* LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
<>	144:ef7eb2e8f9f7	2321	* @note For devices with several ADC: in multimode, some devices
<>	144:ef7eb2e8f9f7	2322	* use a different data register outside of ADC instance scope
<>	144:ef7eb2e8f9f7	2323	* (common data register). This macro manages this register difference,
<>	144:ef7eb2e8f9f7	2324	* only ADC instance has to be set as parameter.
<>	144:ef7eb2e8f9f7	2325	* @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
<>	144:ef7eb2e8f9f7	2326	* CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
<>	144:ef7eb2e8f9f7	2327	* CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
<>	144:ef7eb2e8f9f7	2328	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	2329	* @param Register This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2330	* @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
<>	144:ef7eb2e8f9f7	2331	* @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
<>	144:ef7eb2e8f9f7	2332	*
<>	144:ef7eb2e8f9f7	2333	* (1) Available on devices with several ADC instances.
<>	144:ef7eb2e8f9f7	2334	* @retval ADC register address
<>	144:ef7eb2e8f9f7	2335	*/
<>	144:ef7eb2e8f9f7	2336	#if defined(ADC_MULTIMODE_SUPPORT)
<>	144:ef7eb2e8f9f7	2337	__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
<>	144:ef7eb2e8f9f7	2338	{
<>	144:ef7eb2e8f9f7	2339	register uint32_t data_reg_addr = 0U;
<>	144:ef7eb2e8f9f7	2340
<>	144:ef7eb2e8f9f7	2341	if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
<>	144:ef7eb2e8f9f7	2342	{
<>	144:ef7eb2e8f9f7	2343	/* Retrieve address of register DR */
<>	144:ef7eb2e8f9f7	2344	data_reg_addr = (uint32_t)&(ADCx->DR);
<>	144:ef7eb2e8f9f7	2345	}
<>	144:ef7eb2e8f9f7	2346	else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
<>	144:ef7eb2e8f9f7	2347	{
<>	144:ef7eb2e8f9f7	2348	/* Retrieve address of register CDR */
<>	144:ef7eb2e8f9f7	2349	data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
<>	144:ef7eb2e8f9f7	2350	}
<>	144:ef7eb2e8f9f7	2351
<>	144:ef7eb2e8f9f7	2352	return data_reg_addr;
<>	144:ef7eb2e8f9f7	2353	}
<>	144:ef7eb2e8f9f7	2354	#else
<>	144:ef7eb2e8f9f7	2355	__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
<>	144:ef7eb2e8f9f7	2356	{
<>	144:ef7eb2e8f9f7	2357	/* Retrieve address of register DR */
<>	144:ef7eb2e8f9f7	2358	return (uint32_t)&(ADCx->DR);
<>	144:ef7eb2e8f9f7	2359	}
<>	144:ef7eb2e8f9f7	2360	#endif
<>	144:ef7eb2e8f9f7	2361
<>	144:ef7eb2e8f9f7	2362	/**
<>	144:ef7eb2e8f9f7	2363	* @}
<>	144:ef7eb2e8f9f7	2364	*/
<>	144:ef7eb2e8f9f7	2365
<>	144:ef7eb2e8f9f7	2366	/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
<>	144:ef7eb2e8f9f7	2367	* @{
<>	144:ef7eb2e8f9f7	2368	*/
<>	144:ef7eb2e8f9f7	2369
<>	144:ef7eb2e8f9f7	2370	/**
<>	144:ef7eb2e8f9f7	2371	* @brief Set parameter common to several ADC: Clock source and prescaler.
<>	144:ef7eb2e8f9f7	2372	* @note On this STM32 serie, if ADC group injected is used, some
<>	144:ef7eb2e8f9f7	2373	* clock ratio constraints between ADC clock and AHB clock
<>	144:ef7eb2e8f9f7	2374	* must be respected.
<>	144:ef7eb2e8f9f7	2375	* Refer to reference manual.
<>	144:ef7eb2e8f9f7	2376	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	2377	* ADC state:
<>	144:ef7eb2e8f9f7	2378	* All ADC instances of the ADC common group must be disabled.
<>	144:ef7eb2e8f9f7	2379	* This check can be done with function @ref LL_ADC_IsEnabled() for each
<>	144:ef7eb2e8f9f7	2380	* ADC instance or by using helper macro helper macro
<>	144:ef7eb2e8f9f7	2381	* @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
<>	144:ef7eb2e8f9f7	2382	* @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n
<>	144:ef7eb2e8f9f7	2383	* CCR PRESC LL_ADC_SetCommonClock
<>	144:ef7eb2e8f9f7	2384	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	2385	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	2386	* @param CommonClock This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2387	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
<>	144:ef7eb2e8f9f7	2388	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
<>	144:ef7eb2e8f9f7	2389	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
<>	144:ef7eb2e8f9f7	2390	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
<>	144:ef7eb2e8f9f7	2391	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
<>	144:ef7eb2e8f9f7	2392	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
<>	144:ef7eb2e8f9f7	2393	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
<>	144:ef7eb2e8f9f7	2394	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
<>	144:ef7eb2e8f9f7	2395	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
<>	144:ef7eb2e8f9f7	2396	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
<>	144:ef7eb2e8f9f7	2397	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
<>	144:ef7eb2e8f9f7	2398	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
<>	144:ef7eb2e8f9f7	2399	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
<>	144:ef7eb2e8f9f7	2400	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
<>	144:ef7eb2e8f9f7	2401	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
<>	144:ef7eb2e8f9f7	2402	* @retval None
<>	144:ef7eb2e8f9f7	2403	*/
<>	144:ef7eb2e8f9f7	2404	__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
<>	144:ef7eb2e8f9f7	2405	{
<>	144:ef7eb2e8f9f7	2406	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE \| ADC_CCR_PRESC, CommonClock);
<>	144:ef7eb2e8f9f7	2407	}
<>	144:ef7eb2e8f9f7	2408
<>	144:ef7eb2e8f9f7	2409	/**
<>	144:ef7eb2e8f9f7	2410	* @brief Get parameter common to several ADC: Clock source and prescaler.
<>	144:ef7eb2e8f9f7	2411	* @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n
<>	144:ef7eb2e8f9f7	2412	* CCR PRESC LL_ADC_GetCommonClock
<>	144:ef7eb2e8f9f7	2413	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	2414	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	2415	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	2416	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
<>	144:ef7eb2e8f9f7	2417	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
<>	144:ef7eb2e8f9f7	2418	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
<>	144:ef7eb2e8f9f7	2419	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
<>	144:ef7eb2e8f9f7	2420	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
<>	144:ef7eb2e8f9f7	2421	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
<>	144:ef7eb2e8f9f7	2422	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
<>	144:ef7eb2e8f9f7	2423	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
<>	144:ef7eb2e8f9f7	2424	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
<>	144:ef7eb2e8f9f7	2425	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
<>	144:ef7eb2e8f9f7	2426	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
<>	144:ef7eb2e8f9f7	2427	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
<>	144:ef7eb2e8f9f7	2428	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
<>	144:ef7eb2e8f9f7	2429	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
<>	144:ef7eb2e8f9f7	2430	* @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
<>	144:ef7eb2e8f9f7	2431	*/
<>	144:ef7eb2e8f9f7	2432	__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
<>	144:ef7eb2e8f9f7	2433	{
<>	144:ef7eb2e8f9f7	2434	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE \| ADC_CCR_PRESC));
<>	144:ef7eb2e8f9f7	2435	}
<>	144:ef7eb2e8f9f7	2436
<>	144:ef7eb2e8f9f7	2437	/**
<>	144:ef7eb2e8f9f7	2438	* @brief Set parameter common to several ADC: measurement path to internal
<>	144:ef7eb2e8f9f7	2439	* channels (VrefInt, temperature sensor, ...).
<>	144:ef7eb2e8f9f7	2440	* @note One or several values can be selected.
<>	144:ef7eb2e8f9f7	2441	* Example: (LL_ADC_PATH_INTERNAL_VREFINT \|
<>	144:ef7eb2e8f9f7	2442	* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
<>	144:ef7eb2e8f9f7	2443	* @note Stabilization time of measurement path to internal channel:
<>	144:ef7eb2e8f9f7	2444	* After enabling internal paths, before starting ADC conversion,
<>	144:ef7eb2e8f9f7	2445	* a delay is required for internal voltage reference and
<>	144:ef7eb2e8f9f7	2446	* temperature sensor stabilization time.
<>	144:ef7eb2e8f9f7	2447	* Refer to device datasheet.
<>	144:ef7eb2e8f9f7	2448	* Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
<>	144:ef7eb2e8f9f7	2449	* Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
<>	144:ef7eb2e8f9f7	2450	* @note ADC internal channel sampling time constraint:
<>	144:ef7eb2e8f9f7	2451	* For ADC conversion of internal channels,
<>	144:ef7eb2e8f9f7	2452	* a sampling time minimum value is required.
<>	144:ef7eb2e8f9f7	2453	* Refer to device datasheet.
<>	144:ef7eb2e8f9f7	2454	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	2455	* ADC state:
<>	144:ef7eb2e8f9f7	2456	* All ADC instances of the ADC common group must be disabled.
<>	144:ef7eb2e8f9f7	2457	* This check can be done with function @ref LL_ADC_IsEnabled() for each
<>	144:ef7eb2e8f9f7	2458	* ADC instance or by using helper macro helper macro
<>	144:ef7eb2e8f9f7	2459	* @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
<>	144:ef7eb2e8f9f7	2460	* @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
<>	144:ef7eb2e8f9f7	2461	* CCR TSEN LL_ADC_SetCommonPathInternalCh\n
<>	144:ef7eb2e8f9f7	2462	* CCR VBATEN LL_ADC_SetCommonPathInternalCh
<>	144:ef7eb2e8f9f7	2463	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	2464	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	2465	* @param PathInternal This parameter can be a combination of the following values:
<>	144:ef7eb2e8f9f7	2466	* @arg @ref LL_ADC_PATH_INTERNAL_NONE
<>	144:ef7eb2e8f9f7	2467	* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
<>	144:ef7eb2e8f9f7	2468	* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
<>	144:ef7eb2e8f9f7	2469	* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
<>	144:ef7eb2e8f9f7	2470	* @retval None
<>	144:ef7eb2e8f9f7	2471	*/
<>	144:ef7eb2e8f9f7	2472	__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
<>	144:ef7eb2e8f9f7	2473	{
<>	144:ef7eb2e8f9f7	2474	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN \| ADC_CCR_TSEN \| ADC_CCR_VBATEN, PathInternal);
<>	144:ef7eb2e8f9f7	2475	}
<>	144:ef7eb2e8f9f7	2476
<>	144:ef7eb2e8f9f7	2477	/**
<>	144:ef7eb2e8f9f7	2478	* @brief Get parameter common to several ADC: measurement path to internal
<>	144:ef7eb2e8f9f7	2479	* channels (VrefInt, temperature sensor, ...).
<>	144:ef7eb2e8f9f7	2480	* @note One or several values can be selected.
<>	144:ef7eb2e8f9f7	2481	* Example: (LL_ADC_PATH_INTERNAL_VREFINT \|
<>	144:ef7eb2e8f9f7	2482	* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
<>	144:ef7eb2e8f9f7	2483	* @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
<>	144:ef7eb2e8f9f7	2484	* CCR TSEN LL_ADC_GetCommonPathInternalCh\n
<>	144:ef7eb2e8f9f7	2485	* CCR VBATEN LL_ADC_GetCommonPathInternalCh
<>	144:ef7eb2e8f9f7	2486	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	2487	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	2488	* @retval Returned value can be a combination of the following values:
<>	144:ef7eb2e8f9f7	2489	* @arg @ref LL_ADC_PATH_INTERNAL_NONE
<>	144:ef7eb2e8f9f7	2490	* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
<>	144:ef7eb2e8f9f7	2491	* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
<>	144:ef7eb2e8f9f7	2492	* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
<>	144:ef7eb2e8f9f7	2493	*/
<>	144:ef7eb2e8f9f7	2494	__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
<>	144:ef7eb2e8f9f7	2495	{
<>	144:ef7eb2e8f9f7	2496	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN \| ADC_CCR_TSEN \| ADC_CCR_VBATEN));
<>	144:ef7eb2e8f9f7	2497	}
<>	144:ef7eb2e8f9f7	2498
<>	144:ef7eb2e8f9f7	2499	/**
<>	144:ef7eb2e8f9f7	2500	* @}
<>	144:ef7eb2e8f9f7	2501	*/
<>	144:ef7eb2e8f9f7	2502
<>	144:ef7eb2e8f9f7	2503	/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
<>	144:ef7eb2e8f9f7	2504	* @{
<>	144:ef7eb2e8f9f7	2505	*/
<>	144:ef7eb2e8f9f7	2506
<>	144:ef7eb2e8f9f7	2507	/**
<>	144:ef7eb2e8f9f7	2508	* @brief Set ADC calibration factor in the mode single-ended
<>	144:ef7eb2e8f9f7	2509	* or differential (for devices with differential mode available).
<>	144:ef7eb2e8f9f7	2510	* @note This function is intended to set calibration parameters
<>	144:ef7eb2e8f9f7	2511	* without having to perform a new calibration using
<>	144:ef7eb2e8f9f7	2512	* @ref LL_ADC_StartCalibration().
<>	144:ef7eb2e8f9f7	2513	* @note For devices with differential mode available:
<>	144:ef7eb2e8f9f7	2514	* Calibration of offset is specific to each of
<>	144:ef7eb2e8f9f7	2515	* single-ended and differential modes
<>	144:ef7eb2e8f9f7	2516	* (calibration factor must be specified for each of these
<>	144:ef7eb2e8f9f7	2517	* differential modes, if used afterwards and if the application
<>	144:ef7eb2e8f9f7	2518	* requires their calibration).
<>	144:ef7eb2e8f9f7	2519	* @note In case of setting calibration factors of both modes single ended
<>	144:ef7eb2e8f9f7	2520	* and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
<>	144:ef7eb2e8f9f7	2521	* both calibration factors must be concatenated.
<>	144:ef7eb2e8f9f7	2522	* To perform this processing, use helper macro
<>	144:ef7eb2e8f9f7	2523	* @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
<>	144:ef7eb2e8f9f7	2524	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	2525	* ADC state:
<>	144:ef7eb2e8f9f7	2526	* ADC must be enabled, without calibration on going, without conversion
<>	144:ef7eb2e8f9f7	2527	* on going on group regular.
<>	144:ef7eb2e8f9f7	2528	* @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n
<>	144:ef7eb2e8f9f7	2529	* CALFACT CALFACT_D LL_ADC_SetCalibrationFactor
<>	144:ef7eb2e8f9f7	2530	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	2531	* @param SingleDiff This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2532	* @arg @ref LL_ADC_SINGLE_ENDED
<>	144:ef7eb2e8f9f7	2533	* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
<>	144:ef7eb2e8f9f7	2534	* @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
<>	144:ef7eb2e8f9f7	2535	* @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
<>	144:ef7eb2e8f9f7	2536	* @retval None
<>	144:ef7eb2e8f9f7	2537	*/
<>	144:ef7eb2e8f9f7	2538	__STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
<>	144:ef7eb2e8f9f7	2539	{
<>	144:ef7eb2e8f9f7	2540	MODIFY_REG(ADCx->CALFACT,
<>	144:ef7eb2e8f9f7	2541	SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
<>	144:ef7eb2e8f9f7	2542	CalibrationFactor << POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK));
<>	144:ef7eb2e8f9f7	2543	}
<>	144:ef7eb2e8f9f7	2544
<>	144:ef7eb2e8f9f7	2545	/**
<>	144:ef7eb2e8f9f7	2546	* @brief Get ADC calibration factor in the mode single-ended
<>	144:ef7eb2e8f9f7	2547	* or differential (for devices with differential mode available).
<>	144:ef7eb2e8f9f7	2548	* @note Calibration factors are set by hardware after performing
<>	144:ef7eb2e8f9f7	2549	* a calibration run using function @ref LL_ADC_StartCalibration().
<>	144:ef7eb2e8f9f7	2550	* @note For devices with differential mode available:
<>	144:ef7eb2e8f9f7	2551	* Calibration of offset is specific to each of
<>	144:ef7eb2e8f9f7	2552	* single-ended and differential modes
<>	144:ef7eb2e8f9f7	2553	* @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n
<>	144:ef7eb2e8f9f7	2554	* CALFACT CALFACT_D LL_ADC_GetCalibrationFactor
<>	144:ef7eb2e8f9f7	2555	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	2556	* @param SingleDiff This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2557	* @arg @ref LL_ADC_SINGLE_ENDED
<>	144:ef7eb2e8f9f7	2558	* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
<>	144:ef7eb2e8f9f7	2559	* @retval Value between Min_Data=0x00 and Max_Data=0x7F
<>	144:ef7eb2e8f9f7	2560	*/
<>	144:ef7eb2e8f9f7	2561	__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
<>	144:ef7eb2e8f9f7	2562	{
<>	144:ef7eb2e8f9f7	2563	/* Retrieve bits with position in register depending on parameter */
<>	144:ef7eb2e8f9f7	2564	/* "SingleDiff". */
<>	144:ef7eb2e8f9f7	2565	/* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
<>	144:ef7eb2e8f9f7	2566	/* containing other bits reserved for other purpose. */
<>	144:ef7eb2e8f9f7	2567	return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK));
<>	144:ef7eb2e8f9f7	2568	}
<>	144:ef7eb2e8f9f7	2569
<>	144:ef7eb2e8f9f7	2570	/**
<>	144:ef7eb2e8f9f7	2571	* @brief Set ADC resolution.
<>	144:ef7eb2e8f9f7	2572	* Refer to reference manual for alignments formats
<>	144:ef7eb2e8f9f7	2573	* dependencies to ADC resolutions.
<>	144:ef7eb2e8f9f7	2574	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	2575	* ADC state:
<>	144:ef7eb2e8f9f7	2576	* ADC must be disabled or enabled without conversion on going
<>	144:ef7eb2e8f9f7	2577	* on either groups regular or injected.
<>	144:ef7eb2e8f9f7	2578	* @rmtoll CFGR RES LL_ADC_SetResolution
<>	144:ef7eb2e8f9f7	2579	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	2580	* @param Resolution This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2581	* @arg @ref LL_ADC_RESOLUTION_12B
<>	144:ef7eb2e8f9f7	2582	* @arg @ref LL_ADC_RESOLUTION_10B
<>	144:ef7eb2e8f9f7	2583	* @arg @ref LL_ADC_RESOLUTION_8B
<>	144:ef7eb2e8f9f7	2584	* @arg @ref LL_ADC_RESOLUTION_6B
<>	144:ef7eb2e8f9f7	2585	* @retval None
<>	144:ef7eb2e8f9f7	2586	*/
<>	144:ef7eb2e8f9f7	2587	__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
<>	144:ef7eb2e8f9f7	2588	{
<>	144:ef7eb2e8f9f7	2589	MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
<>	144:ef7eb2e8f9f7	2590	}
<>	144:ef7eb2e8f9f7	2591
<>	144:ef7eb2e8f9f7	2592	/**
<>	144:ef7eb2e8f9f7	2593	* @brief Get ADC resolution.
<>	144:ef7eb2e8f9f7	2594	* Refer to reference manual for alignments formats
<>	144:ef7eb2e8f9f7	2595	* dependencies to ADC resolutions.
<>	144:ef7eb2e8f9f7	2596	* @rmtoll CFGR RES LL_ADC_GetResolution
<>	144:ef7eb2e8f9f7	2597	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	2598	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	2599	* @arg @ref LL_ADC_RESOLUTION_12B
<>	144:ef7eb2e8f9f7	2600	* @arg @ref LL_ADC_RESOLUTION_10B
<>	144:ef7eb2e8f9f7	2601	* @arg @ref LL_ADC_RESOLUTION_8B
<>	144:ef7eb2e8f9f7	2602	* @arg @ref LL_ADC_RESOLUTION_6B
<>	144:ef7eb2e8f9f7	2603	*/
<>	144:ef7eb2e8f9f7	2604	__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	2605	{
<>	144:ef7eb2e8f9f7	2606	return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
<>	144:ef7eb2e8f9f7	2607	}
<>	144:ef7eb2e8f9f7	2608
<>	144:ef7eb2e8f9f7	2609	/**
<>	144:ef7eb2e8f9f7	2610	* @brief Set ADC conversion data alignment.
<>	144:ef7eb2e8f9f7	2611	* @note Refer to reference manual for alignments formats
<>	144:ef7eb2e8f9f7	2612	* dependencies to ADC resolutions.
<>	144:ef7eb2e8f9f7	2613	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	2614	* ADC state:
<>	144:ef7eb2e8f9f7	2615	* ADC must be disabled or enabled without conversion on going
<>	144:ef7eb2e8f9f7	2616	* on either groups regular or injected.
<>	144:ef7eb2e8f9f7	2617	* @rmtoll CFGR ALIGN LL_ADC_SetDataAlignment
<>	144:ef7eb2e8f9f7	2618	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	2619	* @param DataAlignment This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2620	* @arg @ref LL_ADC_DATA_ALIGN_RIGHT
<>	144:ef7eb2e8f9f7	2621	* @arg @ref LL_ADC_DATA_ALIGN_LEFT
<>	144:ef7eb2e8f9f7	2622	* @retval None
<>	144:ef7eb2e8f9f7	2623	*/
<>	144:ef7eb2e8f9f7	2624	__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
<>	144:ef7eb2e8f9f7	2625	{
<>	144:ef7eb2e8f9f7	2626	MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
<>	144:ef7eb2e8f9f7	2627	}
<>	144:ef7eb2e8f9f7	2628
<>	144:ef7eb2e8f9f7	2629	/**
<>	144:ef7eb2e8f9f7	2630	* @brief Get ADC conversion data alignment.
<>	144:ef7eb2e8f9f7	2631	* @note Refer to reference manual for alignments formats
<>	144:ef7eb2e8f9f7	2632	* dependencies to ADC resolutions.
<>	144:ef7eb2e8f9f7	2633	* @rmtoll CFGR ALIGN LL_ADC_GetDataAlignment
<>	144:ef7eb2e8f9f7	2634	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	2635	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	2636	* @arg @ref LL_ADC_DATA_ALIGN_RIGHT
<>	144:ef7eb2e8f9f7	2637	* @arg @ref LL_ADC_DATA_ALIGN_LEFT
<>	144:ef7eb2e8f9f7	2638	*/
<>	144:ef7eb2e8f9f7	2639	__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	2640	{
<>	144:ef7eb2e8f9f7	2641	return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
<>	144:ef7eb2e8f9f7	2642	}
<>	144:ef7eb2e8f9f7	2643
<>	144:ef7eb2e8f9f7	2644	/**
<>	144:ef7eb2e8f9f7	2645	* @brief Set ADC low power mode.
<>	144:ef7eb2e8f9f7	2646	* @note Description of ADC low power modes:
<>	144:ef7eb2e8f9f7	2647	* - ADC low power mode "auto wait": Dynamic low power mode,
<>	144:ef7eb2e8f9f7	2648	* ADC conversions occurrences are limited to the minimum necessary
<>	144:ef7eb2e8f9f7	2649	* in order to reduce power consumption.
<>	144:ef7eb2e8f9f7	2650	* New ADC conversion starts only when the previous
<>	144:ef7eb2e8f9f7	2651	* unitary conversion data (for ADC group regular)
<>	144:ef7eb2e8f9f7	2652	* or previous sequence conversions data (for ADC group injected)
<>	144:ef7eb2e8f9f7	2653	* has been retrieved by user software.
<>	144:ef7eb2e8f9f7	2654	* In the meantime, ADC remains idle: does not performs any
<>	144:ef7eb2e8f9f7	2655	* other conversion.
<>	144:ef7eb2e8f9f7	2656	* This mode allows to automatically adapt the ADC conversions
<>	144:ef7eb2e8f9f7	2657	* triggers to the speed of the software that reads the data.
<>	144:ef7eb2e8f9f7	2658	* Moreover, this avoids risk of overrun for low frequency
<>	144:ef7eb2e8f9f7	2659	* applications.
<>	144:ef7eb2e8f9f7	2660	* How to use this low power mode:
<>	144:ef7eb2e8f9f7	2661	* - Do not use with interruption or DMA since these modes
<>	144:ef7eb2e8f9f7	2662	* have to clear immediately the EOC flag to free the
<>	144:ef7eb2e8f9f7	2663	* IRQ vector sequencer.
<>	144:ef7eb2e8f9f7	2664	* - Do use with polling: 1. Start conversion,
<>	144:ef7eb2e8f9f7	2665	* 2. Later on, when conversion data is needed: poll for end of
<>	144:ef7eb2e8f9f7	2666	* conversion to ensure that conversion is completed and
<>	144:ef7eb2e8f9f7	2667	* retrieve ADC conversion data. This will trig another
<>	144:ef7eb2e8f9f7	2668	* ADC conversion start.
<>	144:ef7eb2e8f9f7	2669	* - ADC low power mode "auto power-off" (feature available on
<>	144:ef7eb2e8f9f7	2670	* this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
<>	144:ef7eb2e8f9f7	2671	* the ADC automatically powers-off after a conversion and
<>	144:ef7eb2e8f9f7	2672	* automatically wakes up when a new conversion is triggered
<>	144:ef7eb2e8f9f7	2673	* (with startup time between trigger and start of sampling).
<>	144:ef7eb2e8f9f7	2674	* This feature can be combined with low power mode "auto wait".
<>	144:ef7eb2e8f9f7	2675	* @note With ADC low power mode "auto wait", the ADC conversion data read
<>	144:ef7eb2e8f9f7	2676	* is corresponding to previous ADC conversion start, independently
<>	144:ef7eb2e8f9f7	2677	* of delay during which ADC was idle.
<>	144:ef7eb2e8f9f7	2678	* Therefore, the ADC conversion data may be outdated: does not
<>	144:ef7eb2e8f9f7	2679	* correspond to the current voltage level on the selected
<>	144:ef7eb2e8f9f7	2680	* ADC channel.
<>	144:ef7eb2e8f9f7	2681	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	2682	* ADC state:
<>	144:ef7eb2e8f9f7	2683	* ADC must be disabled or enabled without conversion on going
<>	144:ef7eb2e8f9f7	2684	* on either groups regular or injected.
<>	144:ef7eb2e8f9f7	2685	* @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
<>	144:ef7eb2e8f9f7	2686	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	2687	* @param LowPowerMode This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2688	* @arg @ref LL_ADC_LP_MODE_NONE
<>	144:ef7eb2e8f9f7	2689	* @arg @ref LL_ADC_LP_AUTOWAIT
<>	144:ef7eb2e8f9f7	2690	* @retval None
<>	144:ef7eb2e8f9f7	2691	*/
<>	144:ef7eb2e8f9f7	2692	__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
<>	144:ef7eb2e8f9f7	2693	{
<>	144:ef7eb2e8f9f7	2694	MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
<>	144:ef7eb2e8f9f7	2695	}
<>	144:ef7eb2e8f9f7	2696
<>	144:ef7eb2e8f9f7	2697	/**
<>	144:ef7eb2e8f9f7	2698	* @brief Get ADC low power mode:
<>	144:ef7eb2e8f9f7	2699	* @note Description of ADC low power modes:
<>	144:ef7eb2e8f9f7	2700	* - ADC low power mode "auto wait": Dynamic low power mode,
<>	144:ef7eb2e8f9f7	2701	* ADC conversions occurrences are limited to the minimum necessary
<>	144:ef7eb2e8f9f7	2702	* in order to reduce power consumption.
<>	144:ef7eb2e8f9f7	2703	* New ADC conversion starts only when the previous
<>	144:ef7eb2e8f9f7	2704	* unitary conversion data (for ADC group regular)
<>	144:ef7eb2e8f9f7	2705	* or previous sequence conversions data (for ADC group injected)
<>	144:ef7eb2e8f9f7	2706	* has been retrieved by user software.
<>	144:ef7eb2e8f9f7	2707	* In the meantime, ADC remains idle: does not performs any
<>	144:ef7eb2e8f9f7	2708	* other conversion.
<>	144:ef7eb2e8f9f7	2709	* This mode allows to automatically adapt the ADC conversions
<>	144:ef7eb2e8f9f7	2710	* triggers to the speed of the software that reads the data.
<>	144:ef7eb2e8f9f7	2711	* Moreover, this avoids risk of overrun for low frequency
<>	144:ef7eb2e8f9f7	2712	* applications.
<>	144:ef7eb2e8f9f7	2713	* How to use this low power mode:
<>	144:ef7eb2e8f9f7	2714	* - Do not use with interruption or DMA since these modes
<>	144:ef7eb2e8f9f7	2715	* have to clear immediately the EOC flag to free the
<>	144:ef7eb2e8f9f7	2716	* IRQ vector sequencer.
<>	144:ef7eb2e8f9f7	2717	* - Do use with polling: 1. Start conversion,
<>	144:ef7eb2e8f9f7	2718	* 2. Later on, when conversion data is needed: poll for end of
<>	144:ef7eb2e8f9f7	2719	* conversion to ensure that conversion is completed and
<>	144:ef7eb2e8f9f7	2720	* retrieve ADC conversion data. This will trig another
<>	144:ef7eb2e8f9f7	2721	* ADC conversion start.
<>	144:ef7eb2e8f9f7	2722	* - ADC low power mode "auto power-off" (feature available on
<>	144:ef7eb2e8f9f7	2723	* this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
<>	144:ef7eb2e8f9f7	2724	* the ADC automatically powers-off after a conversion and
<>	144:ef7eb2e8f9f7	2725	* automatically wakes up when a new conversion is triggered
<>	144:ef7eb2e8f9f7	2726	* (with startup time between trigger and start of sampling).
<>	144:ef7eb2e8f9f7	2727	* This feature can be combined with low power mode "auto wait".
<>	144:ef7eb2e8f9f7	2728	* @note With ADC low power mode "auto wait", the ADC conversion data read
<>	144:ef7eb2e8f9f7	2729	* is corresponding to previous ADC conversion start, independently
<>	144:ef7eb2e8f9f7	2730	* of delay during which ADC was idle.
<>	144:ef7eb2e8f9f7	2731	* Therefore, the ADC conversion data may be outdated: does not
<>	144:ef7eb2e8f9f7	2732	* correspond to the current voltage level on the selected
<>	144:ef7eb2e8f9f7	2733	* ADC channel.
<>	144:ef7eb2e8f9f7	2734	* @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
<>	144:ef7eb2e8f9f7	2735	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	2736	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	2737	* @arg @ref LL_ADC_LP_MODE_NONE
<>	144:ef7eb2e8f9f7	2738	* @arg @ref LL_ADC_LP_AUTOWAIT
<>	144:ef7eb2e8f9f7	2739	*/
<>	144:ef7eb2e8f9f7	2740	__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	2741	{
<>	144:ef7eb2e8f9f7	2742	return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
<>	144:ef7eb2e8f9f7	2743	}
<>	144:ef7eb2e8f9f7	2744
<>	144:ef7eb2e8f9f7	2745	/**
<>	144:ef7eb2e8f9f7	2746	* @brief Set ADC selected offset number 1, 2, 3 or 4.
<>	144:ef7eb2e8f9f7	2747	* @note This function set the 2 items of offset configuration:
<>	144:ef7eb2e8f9f7	2748	* - ADC channel to which the offset programmed will be applied
<>	144:ef7eb2e8f9f7	2749	* (independently of channel mapped on ADC group regular
<>	144:ef7eb2e8f9f7	2750	* or group injected)
<>	144:ef7eb2e8f9f7	2751	* - Offset level (offset to be subtracted from the raw
<>	144:ef7eb2e8f9f7	2752	* converted data).
<>	144:ef7eb2e8f9f7	2753	* @note Caution: Offset format is dependent to ADC resolution:
<>	144:ef7eb2e8f9f7	2754	* offset has to be left-aligned on bit 11, the LSB (right bits)
<>	144:ef7eb2e8f9f7	2755	* are set to 0.
<>	144:ef7eb2e8f9f7	2756	* @note This function enables the offset, by default. It can be forced
<>	144:ef7eb2e8f9f7	2757	* to disable state using function LL_ADC_SetOffsetState().
<>	144:ef7eb2e8f9f7	2758	* @note If a channel is mapped on several offsets numbers, only the offset
<>	144:ef7eb2e8f9f7	2759	* with the lowest value is considered for the subtraction.
<>	144:ef7eb2e8f9f7	2760	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	2761	* ADC state:
<>	144:ef7eb2e8f9f7	2762	* ADC must be disabled or enabled without conversion on going
<>	144:ef7eb2e8f9f7	2763	* on either groups regular or injected.
<>	144:ef7eb2e8f9f7	2764	* @note On STM32L4, some fast channels are available: fast analog inputs
<>	144:ef7eb2e8f9f7	2765	* coming from GPIO pads (ADC_IN1..5).
<>	144:ef7eb2e8f9f7	2766	* @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n
<>	144:ef7eb2e8f9f7	2767	* OFR1 OFFSET1 LL_ADC_SetOffset\n
<>	144:ef7eb2e8f9f7	2768	* OFR1 OFFSET1_EN LL_ADC_SetOffset\n
<>	144:ef7eb2e8f9f7	2769	* OFR2 OFFSET2_CH LL_ADC_SetOffset\n
<>	144:ef7eb2e8f9f7	2770	* OFR2 OFFSET2 LL_ADC_SetOffset\n
<>	144:ef7eb2e8f9f7	2771	* OFR2 OFFSET2_EN LL_ADC_SetOffset\n
<>	144:ef7eb2e8f9f7	2772	* OFR3 OFFSET3_CH LL_ADC_SetOffset\n
<>	144:ef7eb2e8f9f7	2773	* OFR3 OFFSET3 LL_ADC_SetOffset\n
<>	144:ef7eb2e8f9f7	2774	* OFR3 OFFSET3_EN LL_ADC_SetOffset\n
<>	144:ef7eb2e8f9f7	2775	* OFR4 OFFSET4_CH LL_ADC_SetOffset\n
<>	144:ef7eb2e8f9f7	2776	* OFR4 OFFSET4 LL_ADC_SetOffset\n
<>	144:ef7eb2e8f9f7	2777	* OFR4 OFFSET4_EN LL_ADC_SetOffset
<>	144:ef7eb2e8f9f7	2778	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	2779	* @param Offsety This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2780	* @arg @ref LL_ADC_OFFSET_1
<>	144:ef7eb2e8f9f7	2781	* @arg @ref LL_ADC_OFFSET_2
<>	144:ef7eb2e8f9f7	2782	* @arg @ref LL_ADC_OFFSET_3
<>	144:ef7eb2e8f9f7	2783	* @arg @ref LL_ADC_OFFSET_4
<>	144:ef7eb2e8f9f7	2784	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2785	* @arg @ref LL_ADC_CHANNEL_0
<>	144:ef7eb2e8f9f7	2786	* @arg @ref LL_ADC_CHANNEL_1 (7)
<>	144:ef7eb2e8f9f7	2787	* @arg @ref LL_ADC_CHANNEL_2 (7)
<>	144:ef7eb2e8f9f7	2788	* @arg @ref LL_ADC_CHANNEL_3 (7)
<>	144:ef7eb2e8f9f7	2789	* @arg @ref LL_ADC_CHANNEL_4 (7)
<>	144:ef7eb2e8f9f7	2790	* @arg @ref LL_ADC_CHANNEL_5 (7)
<>	144:ef7eb2e8f9f7	2791	* @arg @ref LL_ADC_CHANNEL_6
<>	144:ef7eb2e8f9f7	2792	* @arg @ref LL_ADC_CHANNEL_7
<>	144:ef7eb2e8f9f7	2793	* @arg @ref LL_ADC_CHANNEL_8
<>	144:ef7eb2e8f9f7	2794	* @arg @ref LL_ADC_CHANNEL_9
<>	144:ef7eb2e8f9f7	2795	* @arg @ref LL_ADC_CHANNEL_10
<>	144:ef7eb2e8f9f7	2796	* @arg @ref LL_ADC_CHANNEL_11
<>	144:ef7eb2e8f9f7	2797	* @arg @ref LL_ADC_CHANNEL_12
<>	144:ef7eb2e8f9f7	2798	* @arg @ref LL_ADC_CHANNEL_13
<>	144:ef7eb2e8f9f7	2799	* @arg @ref LL_ADC_CHANNEL_14
<>	144:ef7eb2e8f9f7	2800	* @arg @ref LL_ADC_CHANNEL_15
<>	144:ef7eb2e8f9f7	2801	* @arg @ref LL_ADC_CHANNEL_16
<>	144:ef7eb2e8f9f7	2802	* @arg @ref LL_ADC_CHANNEL_17
<>	144:ef7eb2e8f9f7	2803	* @arg @ref LL_ADC_CHANNEL_18
<>	144:ef7eb2e8f9f7	2804	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	144:ef7eb2e8f9f7	2805	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
<>	144:ef7eb2e8f9f7	2806	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
<>	144:ef7eb2e8f9f7	2807	* @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
<>	144:ef7eb2e8f9f7	2808	* @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
<>	144:ef7eb2e8f9f7	2809	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	2810	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	2811	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	2812	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	2813	*
<>	144:ef7eb2e8f9f7	2814	* (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
<>	144:ef7eb2e8f9f7	2815	* (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
<>	144:ef7eb2e8f9f7	2816	* (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
<>	144:ef7eb2e8f9f7	2817	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
<>	144:ef7eb2e8f9f7	2818	* (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
<>	144:ef7eb2e8f9f7	2819	* (6) On STM32L4, parameter available on devices with several ADC instances.\n
<>	144:ef7eb2e8f9f7	2820	* (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
<>	144:ef7eb2e8f9f7	2821	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
<>	144:ef7eb2e8f9f7	2822	* @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
<>	144:ef7eb2e8f9f7	2823	* @retval None
<>	144:ef7eb2e8f9f7	2824	*/
<>	144:ef7eb2e8f9f7	2825	__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
<>	144:ef7eb2e8f9f7	2826	{
<>	144:ef7eb2e8f9f7	2827	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
<>	144:ef7eb2e8f9f7	2828
<>	144:ef7eb2e8f9f7	2829	MODIFY_REG(*preg,
<>	144:ef7eb2e8f9f7	2830	ADC_OFR1_OFFSET1_EN \| ADC_OFR1_OFFSET1_CH \| ADC_OFR1_OFFSET1,
<>	144:ef7eb2e8f9f7	2831	ADC_OFR1_OFFSET1_EN \| (Channel & ADC_CHANNEL_ID_NUMBER_MASK) \| OffsetLevel);
<>	144:ef7eb2e8f9f7	2832	}
<>	144:ef7eb2e8f9f7	2833
<>	144:ef7eb2e8f9f7	2834	/**
<>	144:ef7eb2e8f9f7	2835	* @brief Get for the ADC selected offset number 1, 2, 3 or 4:
<>	144:ef7eb2e8f9f7	2836	* Channel to which the offset programmed will be applied
<>	144:ef7eb2e8f9f7	2837	* (independently of channel mapped on ADC group regular
<>	144:ef7eb2e8f9f7	2838	* or group injected)
<>	144:ef7eb2e8f9f7	2839	* @note Usage of the returned channel number:
<>	144:ef7eb2e8f9f7	2840	* - To reinject this channel into another function LL_ADC_xxx:
<>	144:ef7eb2e8f9f7	2841	* the returned channel number is only partly formatted on definition
<>	144:ef7eb2e8f9f7	2842	* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
<>	144:ef7eb2e8f9f7	2843	* with parts of literals LL_ADC_CHANNEL_x or using
<>	144:ef7eb2e8f9f7	2844	* helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	144:ef7eb2e8f9f7	2845	* Then the selected literal LL_ADC_CHANNEL_x can be used
<>	144:ef7eb2e8f9f7	2846	* as parameter for another function.
<>	144:ef7eb2e8f9f7	2847	* - To get the channel number in decimal format:
<>	144:ef7eb2e8f9f7	2848	* process the returned value with the helper macro
<>	144:ef7eb2e8f9f7	2849	* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	144:ef7eb2e8f9f7	2850	* @note On STM32L4, some fast channels are available: fast analog inputs
<>	144:ef7eb2e8f9f7	2851	* coming from GPIO pads (ADC_IN1..5).
<>	144:ef7eb2e8f9f7	2852	* @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n
<>	144:ef7eb2e8f9f7	2853	* OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n
<>	144:ef7eb2e8f9f7	2854	* OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n
<>	144:ef7eb2e8f9f7	2855	* OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
<>	144:ef7eb2e8f9f7	2856	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	2857	* @param Offsety This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2858	* @arg @ref LL_ADC_OFFSET_1
<>	144:ef7eb2e8f9f7	2859	* @arg @ref LL_ADC_OFFSET_2
<>	144:ef7eb2e8f9f7	2860	* @arg @ref LL_ADC_OFFSET_3
<>	144:ef7eb2e8f9f7	2861	* @arg @ref LL_ADC_OFFSET_4
<>	144:ef7eb2e8f9f7	2862	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	2863	* @arg @ref LL_ADC_CHANNEL_0
<>	144:ef7eb2e8f9f7	2864	* @arg @ref LL_ADC_CHANNEL_1 (7)
<>	144:ef7eb2e8f9f7	2865	* @arg @ref LL_ADC_CHANNEL_2 (7)
<>	144:ef7eb2e8f9f7	2866	* @arg @ref LL_ADC_CHANNEL_3 (7)
<>	144:ef7eb2e8f9f7	2867	* @arg @ref LL_ADC_CHANNEL_4 (7)
<>	144:ef7eb2e8f9f7	2868	* @arg @ref LL_ADC_CHANNEL_5 (7)
<>	144:ef7eb2e8f9f7	2869	* @arg @ref LL_ADC_CHANNEL_6
<>	144:ef7eb2e8f9f7	2870	* @arg @ref LL_ADC_CHANNEL_7
<>	144:ef7eb2e8f9f7	2871	* @arg @ref LL_ADC_CHANNEL_8
<>	144:ef7eb2e8f9f7	2872	* @arg @ref LL_ADC_CHANNEL_9
<>	144:ef7eb2e8f9f7	2873	* @arg @ref LL_ADC_CHANNEL_10
<>	144:ef7eb2e8f9f7	2874	* @arg @ref LL_ADC_CHANNEL_11
<>	144:ef7eb2e8f9f7	2875	* @arg @ref LL_ADC_CHANNEL_12
<>	144:ef7eb2e8f9f7	2876	* @arg @ref LL_ADC_CHANNEL_13
<>	144:ef7eb2e8f9f7	2877	* @arg @ref LL_ADC_CHANNEL_14
<>	144:ef7eb2e8f9f7	2878	* @arg @ref LL_ADC_CHANNEL_15
<>	144:ef7eb2e8f9f7	2879	* @arg @ref LL_ADC_CHANNEL_16
<>	144:ef7eb2e8f9f7	2880	* @arg @ref LL_ADC_CHANNEL_17
<>	144:ef7eb2e8f9f7	2881	* @arg @ref LL_ADC_CHANNEL_18
<>	144:ef7eb2e8f9f7	2882	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	144:ef7eb2e8f9f7	2883	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
<>	144:ef7eb2e8f9f7	2884	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
<>	144:ef7eb2e8f9f7	2885	* @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
<>	144:ef7eb2e8f9f7	2886	* @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
<>	144:ef7eb2e8f9f7	2887	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	2888	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	2889	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	2890	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	2891	*
<>	144:ef7eb2e8f9f7	2892	* (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
<>	144:ef7eb2e8f9f7	2893	* (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
<>	144:ef7eb2e8f9f7	2894	* (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
<>	144:ef7eb2e8f9f7	2895	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
<>	144:ef7eb2e8f9f7	2896	* (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
<>	144:ef7eb2e8f9f7	2897	* (6) On STM32L4, parameter available on devices with several ADC instances.\n
<>	144:ef7eb2e8f9f7	2898	* (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
<>	144:ef7eb2e8f9f7	2899	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
<>	144:ef7eb2e8f9f7	2900	* (1, 2, 3, 4) For ADC channel read back from ADC register,
<>	144:ef7eb2e8f9f7	2901	* comparison with internal channel parameter to be done
<>	144:ef7eb2e8f9f7	2902	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
<>	144:ef7eb2e8f9f7	2903	*/
<>	144:ef7eb2e8f9f7	2904	__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
<>	144:ef7eb2e8f9f7	2905	{
<>	144:ef7eb2e8f9f7	2906	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
<>	144:ef7eb2e8f9f7	2907
<>	144:ef7eb2e8f9f7	2908	return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
<>	144:ef7eb2e8f9f7	2909	}
<>	144:ef7eb2e8f9f7	2910
<>	144:ef7eb2e8f9f7	2911	/**
<>	144:ef7eb2e8f9f7	2912	* @brief Get for the ADC selected offset number 1, 2, 3 or 4:
<>	144:ef7eb2e8f9f7	2913	* Offset level (offset to be subtracted from the raw
<>	144:ef7eb2e8f9f7	2914	* converted data).
<>	144:ef7eb2e8f9f7	2915	* @note Caution: Offset format is dependent to ADC resolution:
<>	144:ef7eb2e8f9f7	2916	* offset has to be left-aligned on bit 11, the LSB (right bits)
<>	144:ef7eb2e8f9f7	2917	* are set to 0.
<>	144:ef7eb2e8f9f7	2918	* @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n
<>	144:ef7eb2e8f9f7	2919	* OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n
<>	144:ef7eb2e8f9f7	2920	* OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n
<>	144:ef7eb2e8f9f7	2921	* OFR4 OFFSET4 LL_ADC_GetOffsetLevel
<>	144:ef7eb2e8f9f7	2922	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	2923	* @param Offsety This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2924	* @arg @ref LL_ADC_OFFSET_1
<>	144:ef7eb2e8f9f7	2925	* @arg @ref LL_ADC_OFFSET_2
<>	144:ef7eb2e8f9f7	2926	* @arg @ref LL_ADC_OFFSET_3
<>	144:ef7eb2e8f9f7	2927	* @arg @ref LL_ADC_OFFSET_4
<>	144:ef7eb2e8f9f7	2928	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	144:ef7eb2e8f9f7	2929	*/
<>	144:ef7eb2e8f9f7	2930	__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
<>	144:ef7eb2e8f9f7	2931	{
<>	144:ef7eb2e8f9f7	2932	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
<>	144:ef7eb2e8f9f7	2933
<>	144:ef7eb2e8f9f7	2934	return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
<>	144:ef7eb2e8f9f7	2935	}
<>	144:ef7eb2e8f9f7	2936
<>	144:ef7eb2e8f9f7	2937	/**
<>	144:ef7eb2e8f9f7	2938	* @brief Set for the ADC selected offset number 1, 2, 3 or 4:
<>	144:ef7eb2e8f9f7	2939	* force offset state disable or enable
<>	144:ef7eb2e8f9f7	2940	* without modifying offset channel or offset value.
<>	144:ef7eb2e8f9f7	2941	* @note This function should be needed only in case of offset to be
<>	144:ef7eb2e8f9f7	2942	* enabled-disabled dynamically, and should not be needed in other cases:
<>	144:ef7eb2e8f9f7	2943	* function LL_ADC_SetOffset() automatically enables the offset.
<>	144:ef7eb2e8f9f7	2944	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	2945	* ADC state:
<>	144:ef7eb2e8f9f7	2946	* ADC must be disabled or enabled without conversion on going
<>	144:ef7eb2e8f9f7	2947	* on either groups regular or injected.
<>	144:ef7eb2e8f9f7	2948	* @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n
<>	144:ef7eb2e8f9f7	2949	* OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n
<>	144:ef7eb2e8f9f7	2950	* OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n
<>	144:ef7eb2e8f9f7	2951	* OFR4 OFFSET4_EN LL_ADC_SetOffsetState
<>	144:ef7eb2e8f9f7	2952	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	2953	* @param Offsety This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2954	* @arg @ref LL_ADC_OFFSET_1
<>	144:ef7eb2e8f9f7	2955	* @arg @ref LL_ADC_OFFSET_2
<>	144:ef7eb2e8f9f7	2956	* @arg @ref LL_ADC_OFFSET_3
<>	144:ef7eb2e8f9f7	2957	* @arg @ref LL_ADC_OFFSET_4
<>	144:ef7eb2e8f9f7	2958	* @param OffsetState This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2959	* @arg @ref LL_ADC_OFFSET_DISABLE
<>	144:ef7eb2e8f9f7	2960	* @arg @ref LL_ADC_OFFSET_ENABLE
<>	144:ef7eb2e8f9f7	2961	* @retval None
<>	144:ef7eb2e8f9f7	2962	*/
<>	144:ef7eb2e8f9f7	2963	__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
<>	144:ef7eb2e8f9f7	2964	{
<>	144:ef7eb2e8f9f7	2965	register uint32_t preg = (uint32_t )((uint32_t)
<>	144:ef7eb2e8f9f7	2966	((uint32_t)(&ADCx->OFR1) + (Offsety*4U)));
<>	144:ef7eb2e8f9f7	2967
<>	144:ef7eb2e8f9f7	2968	MODIFY_REG(*preg,
<>	144:ef7eb2e8f9f7	2969	ADC_OFR1_OFFSET1_EN,
<>	144:ef7eb2e8f9f7	2970	OffsetState);
<>	144:ef7eb2e8f9f7	2971	}
<>	144:ef7eb2e8f9f7	2972
<>	144:ef7eb2e8f9f7	2973	/**
<>	144:ef7eb2e8f9f7	2974	* @brief Get for the ADC selected offset number 1, 2, 3 or 4:
<>	144:ef7eb2e8f9f7	2975	* offset state disabled or enabled.
<>	144:ef7eb2e8f9f7	2976	* @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n
<>	144:ef7eb2e8f9f7	2977	* OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n
<>	144:ef7eb2e8f9f7	2978	* OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n
<>	144:ef7eb2e8f9f7	2979	* OFR4 OFFSET4_EN LL_ADC_GetOffsetState
<>	144:ef7eb2e8f9f7	2980	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	2981	* @param Offsety This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2982	* @arg @ref LL_ADC_OFFSET_1
<>	144:ef7eb2e8f9f7	2983	* @arg @ref LL_ADC_OFFSET_2
<>	144:ef7eb2e8f9f7	2984	* @arg @ref LL_ADC_OFFSET_3
<>	144:ef7eb2e8f9f7	2985	* @arg @ref LL_ADC_OFFSET_4
<>	144:ef7eb2e8f9f7	2986	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	2987	* @arg @ref LL_ADC_OFFSET_DISABLE
<>	144:ef7eb2e8f9f7	2988	* @arg @ref LL_ADC_OFFSET_ENABLE
<>	144:ef7eb2e8f9f7	2989	*/
<>	144:ef7eb2e8f9f7	2990	__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
<>	144:ef7eb2e8f9f7	2991	{
<>	144:ef7eb2e8f9f7	2992	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
<>	144:ef7eb2e8f9f7	2993
<>	144:ef7eb2e8f9f7	2994	return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
<>	144:ef7eb2e8f9f7	2995	}
<>	144:ef7eb2e8f9f7	2996
<>	144:ef7eb2e8f9f7	2997	/**
<>	144:ef7eb2e8f9f7	2998	* @}
<>	144:ef7eb2e8f9f7	2999	*/
<>	144:ef7eb2e8f9f7	3000
<>	144:ef7eb2e8f9f7	3001	/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
<>	144:ef7eb2e8f9f7	3002	* @{
<>	144:ef7eb2e8f9f7	3003	*/
<>	144:ef7eb2e8f9f7	3004
<>	144:ef7eb2e8f9f7	3005	/**
<>	144:ef7eb2e8f9f7	3006	* @brief Set ADC group regular conversion trigger source:
<>	144:ef7eb2e8f9f7	3007	* internal (SW start) or from external IP (timer event,
<>	144:ef7eb2e8f9f7	3008	* external interrupt line).
<>	144:ef7eb2e8f9f7	3009	* @note On this STM32 serie, setting trigger source to external trigger
<>	144:ef7eb2e8f9f7	3010	* also set trigger polarity to rising edge
<>	144:ef7eb2e8f9f7	3011	* (default setting for compatibility with some ADC on other
<>	144:ef7eb2e8f9f7	3012	* STM32 families having this setting set by HW default value).
<>	144:ef7eb2e8f9f7	3013	* In case of need to modify trigger edge, use
<>	144:ef7eb2e8f9f7	3014	* function @ref LL_ADC_REG_SetTriggerEdge().
<>	144:ef7eb2e8f9f7	3015	* @note Availability of parameters of trigger sources from timer
<>	144:ef7eb2e8f9f7	3016	* depends on timers availability on the selected device.
<>	144:ef7eb2e8f9f7	3017	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	3018	* ADC state:
<>	144:ef7eb2e8f9f7	3019	* ADC must be disabled or enabled without conversion on going
<>	144:ef7eb2e8f9f7	3020	* on group regular.
<>	144:ef7eb2e8f9f7	3021	* @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n
<>	144:ef7eb2e8f9f7	3022	* CFGR EXTEN LL_ADC_REG_SetTriggerSource
<>	144:ef7eb2e8f9f7	3023	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	3024	* @param TriggerSource This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3025	* @arg @ref LL_ADC_REG_TRIG_SOFTWARE
<>	144:ef7eb2e8f9f7	3026	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
<>	144:ef7eb2e8f9f7	3027	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
<>	144:ef7eb2e8f9f7	3028	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
<>	144:ef7eb2e8f9f7	3029	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
<>	144:ef7eb2e8f9f7	3030	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
<>	144:ef7eb2e8f9f7	3031	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
<>	144:ef7eb2e8f9f7	3032	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
<>	144:ef7eb2e8f9f7	3033	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
<>	144:ef7eb2e8f9f7	3034	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
<>	144:ef7eb2e8f9f7	3035	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
<>	144:ef7eb2e8f9f7	3036	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
<>	144:ef7eb2e8f9f7	3037	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
<>	144:ef7eb2e8f9f7	3038	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
<>	144:ef7eb2e8f9f7	3039	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
<>	144:ef7eb2e8f9f7	3040	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
<>	144:ef7eb2e8f9f7	3041	* @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
<>	144:ef7eb2e8f9f7	3042	* @retval None
<>	144:ef7eb2e8f9f7	3043	*/
<>	144:ef7eb2e8f9f7	3044	__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
<>	144:ef7eb2e8f9f7	3045	{
<>	144:ef7eb2e8f9f7	3046	MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN \| ADC_CFGR_EXTSEL, TriggerSource);
<>	144:ef7eb2e8f9f7	3047	}
<>	144:ef7eb2e8f9f7	3048
<>	144:ef7eb2e8f9f7	3049	/**
<>	144:ef7eb2e8f9f7	3050	* @brief Get ADC group regular conversion trigger source:
<>	144:ef7eb2e8f9f7	3051	* internal (SW start) or from external IP (timer event,
<>	144:ef7eb2e8f9f7	3052	* external interrupt line).
<>	144:ef7eb2e8f9f7	3053	* @note To determine whether group regular trigger source is
<>	144:ef7eb2e8f9f7	3054	* internal (SW start) or external, without detail
<>	144:ef7eb2e8f9f7	3055	* of which peripheral is selected as external trigger,
<>	144:ef7eb2e8f9f7	3056	* (equivalent to
<>	144:ef7eb2e8f9f7	3057	* "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
<>	144:ef7eb2e8f9f7	3058	* use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
<>	144:ef7eb2e8f9f7	3059	* @note Availability of parameters of trigger sources from timer
<>	144:ef7eb2e8f9f7	3060	* depends on timers availability on the selected device.
<>	144:ef7eb2e8f9f7	3061	* @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n
<>	144:ef7eb2e8f9f7	3062	* CFGR EXTEN LL_ADC_REG_GetTriggerSource
<>	144:ef7eb2e8f9f7	3063	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	3064	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	3065	* @arg @ref LL_ADC_REG_TRIG_SOFTWARE
<>	144:ef7eb2e8f9f7	3066	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
<>	144:ef7eb2e8f9f7	3067	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
<>	144:ef7eb2e8f9f7	3068	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
<>	144:ef7eb2e8f9f7	3069	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
<>	144:ef7eb2e8f9f7	3070	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
<>	144:ef7eb2e8f9f7	3071	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
<>	144:ef7eb2e8f9f7	3072	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
<>	144:ef7eb2e8f9f7	3073	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
<>	144:ef7eb2e8f9f7	3074	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
<>	144:ef7eb2e8f9f7	3075	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
<>	144:ef7eb2e8f9f7	3076	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
<>	144:ef7eb2e8f9f7	3077	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
<>	144:ef7eb2e8f9f7	3078	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
<>	144:ef7eb2e8f9f7	3079	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
<>	144:ef7eb2e8f9f7	3080	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
<>	144:ef7eb2e8f9f7	3081	* @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
<>	144:ef7eb2e8f9f7	3082	*/
<>	144:ef7eb2e8f9f7	3083	__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	3084	{
<>	144:ef7eb2e8f9f7	3085	register uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL \| ADC_CFGR_EXTEN);
<>	144:ef7eb2e8f9f7	3086
<>	144:ef7eb2e8f9f7	3087	/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
<>	144:ef7eb2e8f9f7	3088	/* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
<>	144:ef7eb2e8f9f7	3089	register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
<>	144:ef7eb2e8f9f7	3090
<>	144:ef7eb2e8f9f7	3091	/* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
<>	144:ef7eb2e8f9f7	3092	/* to match with triggers literals definition. */
<>	144:ef7eb2e8f9f7	3093	return ((TriggerSource
<>	144:ef7eb2e8f9f7	3094	& (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
<>	144:ef7eb2e8f9f7	3095	\| ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
<>	144:ef7eb2e8f9f7	3096	);
<>	144:ef7eb2e8f9f7	3097	}
<>	144:ef7eb2e8f9f7	3098
<>	144:ef7eb2e8f9f7	3099	/**
<>	144:ef7eb2e8f9f7	3100	* @brief Get ADC group regular conversion trigger source internal (SW start)
<>	144:ef7eb2e8f9f7	3101	or external.
<>	144:ef7eb2e8f9f7	3102	* @note In case of group regular trigger source set to external trigger,
<>	144:ef7eb2e8f9f7	3103	* to determine which peripheral is selected as external trigger,
<>	144:ef7eb2e8f9f7	3104	* use function @ref LL_ADC_REG_GetTriggerSource().
<>	144:ef7eb2e8f9f7	3105	* @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
<>	144:ef7eb2e8f9f7	3106	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	3107	* @retval Value "0" if trigger source external trigger
<>	144:ef7eb2e8f9f7	3108	* Value "1" if trigger source SW start.
<>	144:ef7eb2e8f9f7	3109	*/
<>	144:ef7eb2e8f9f7	3110	__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	3111	{
<>	144:ef7eb2e8f9f7	3112	return (READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN));
<>	144:ef7eb2e8f9f7	3113	}
<>	144:ef7eb2e8f9f7	3114
<>	144:ef7eb2e8f9f7	3115	/**
<>	144:ef7eb2e8f9f7	3116	* @brief Set ADC group regular conversion trigger polarity.
<>	144:ef7eb2e8f9f7	3117	* @note Applicable only for trigger source set to external trigger.
<>	144:ef7eb2e8f9f7	3118	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	3119	* ADC state:
<>	144:ef7eb2e8f9f7	3120	* ADC must be disabled or enabled without conversion on going
<>	144:ef7eb2e8f9f7	3121	* on group regular.
<>	144:ef7eb2e8f9f7	3122	* @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge
<>	144:ef7eb2e8f9f7	3123	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	3124	* @param ExternalTriggerEdge This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3125	* @arg @ref LL_ADC_REG_TRIG_EXT_RISING
<>	144:ef7eb2e8f9f7	3126	* @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
<>	144:ef7eb2e8f9f7	3127	* @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
<>	144:ef7eb2e8f9f7	3128	* @retval None
<>	144:ef7eb2e8f9f7	3129	*/
<>	144:ef7eb2e8f9f7	3130	__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
<>	144:ef7eb2e8f9f7	3131	{
<>	144:ef7eb2e8f9f7	3132	MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
<>	144:ef7eb2e8f9f7	3133	}
<>	144:ef7eb2e8f9f7	3134
<>	144:ef7eb2e8f9f7	3135	/**
<>	144:ef7eb2e8f9f7	3136	* @brief Get ADC group regular conversion trigger polarity.
<>	144:ef7eb2e8f9f7	3137	* @note Applicable only for trigger source set to external trigger.
<>	144:ef7eb2e8f9f7	3138	* @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge
<>	144:ef7eb2e8f9f7	3139	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	3140	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	3141	* @arg @ref LL_ADC_REG_TRIG_EXT_RISING
<>	144:ef7eb2e8f9f7	3142	* @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
<>	144:ef7eb2e8f9f7	3143	* @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
<>	144:ef7eb2e8f9f7	3144	*/
<>	144:ef7eb2e8f9f7	3145	__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	3146	{
<>	144:ef7eb2e8f9f7	3147	return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
<>	144:ef7eb2e8f9f7	3148	}
<>	144:ef7eb2e8f9f7	3149
<>	144:ef7eb2e8f9f7	3150
<>	144:ef7eb2e8f9f7	3151	/**
<>	144:ef7eb2e8f9f7	3152	* @brief Set ADC group regular sequencer length and scan direction.
<>	144:ef7eb2e8f9f7	3153	* @note Description of ADC group regular sequencer features:
<>	144:ef7eb2e8f9f7	3154	* - For devices with sequencer fully configurable
<>	144:ef7eb2e8f9f7	3155	* (function "LL_ADC_REG_SetSequencerRanks()" available):
<>	144:ef7eb2e8f9f7	3156	* sequencer length and each rank affectation to a channel
<>	144:ef7eb2e8f9f7	3157	* are configurable.
<>	144:ef7eb2e8f9f7	3158	* This function performs configuration of:
<>	144:ef7eb2e8f9f7	3159	* - Sequence length: Number of ranks in the scan sequence.
<>	144:ef7eb2e8f9f7	3160	* - Sequence direction: Unless specified in parameters, sequencer
<>	144:ef7eb2e8f9f7	3161	* scan direction is forward (from rank 1 to rank n).
<>	144:ef7eb2e8f9f7	3162	* Sequencer ranks are selected using
<>	144:ef7eb2e8f9f7	3163	* function "LL_ADC_REG_SetSequencerRanks()".
<>	144:ef7eb2e8f9f7	3164	* - For devices with sequencer not fully configurable
<>	144:ef7eb2e8f9f7	3165	* (function "LL_ADC_REG_SetSequencerChannels()" available):
<>	144:ef7eb2e8f9f7	3166	* sequencer length and each rank affectation to a channel
<>	144:ef7eb2e8f9f7	3167	* are defined by channel number.
<>	144:ef7eb2e8f9f7	3168	* This function performs configuration of:
<>	144:ef7eb2e8f9f7	3169	* - Sequence length: Number of ranks in the scan sequence is
<>	144:ef7eb2e8f9f7	3170	* defined by number of channels set in the sequence,
<>	144:ef7eb2e8f9f7	3171	* rank of each channel is fixed by channel HW number.
<>	144:ef7eb2e8f9f7	3172	* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
<>	144:ef7eb2e8f9f7	3173	* - Sequence direction: Unless specified in parameters, sequencer
<>	144:ef7eb2e8f9f7	3174	* scan direction is forward (from lowest channel number to
<>	144:ef7eb2e8f9f7	3175	* highest channel number).
<>	144:ef7eb2e8f9f7	3176	* Sequencer ranks are selected using
<>	144:ef7eb2e8f9f7	3177	* function "LL_ADC_REG_SetSequencerChannels()".
<>	144:ef7eb2e8f9f7	3178	* @note Sequencer disabled is equivalent to sequencer of 1 rank:
<>	144:ef7eb2e8f9f7	3179	* ADC conversion on only 1 channel.
<>	144:ef7eb2e8f9f7	3180	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	3181	* ADC state:
<>	144:ef7eb2e8f9f7	3182	* ADC must be disabled or enabled without conversion on going
<>	144:ef7eb2e8f9f7	3183	* on group regular.
<>	144:ef7eb2e8f9f7	3184	* @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
<>	144:ef7eb2e8f9f7	3185	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	3186	* @param SequencerNbRanks This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3187	* @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
<>	144:ef7eb2e8f9f7	3188	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
<>	144:ef7eb2e8f9f7	3189	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
<>	144:ef7eb2e8f9f7	3190	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
<>	144:ef7eb2e8f9f7	3191	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
<>	144:ef7eb2e8f9f7	3192	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
<>	144:ef7eb2e8f9f7	3193	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
<>	144:ef7eb2e8f9f7	3194	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
<>	144:ef7eb2e8f9f7	3195	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
<>	144:ef7eb2e8f9f7	3196	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
<>	144:ef7eb2e8f9f7	3197	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
<>	144:ef7eb2e8f9f7	3198	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
<>	144:ef7eb2e8f9f7	3199	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
<>	144:ef7eb2e8f9f7	3200	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
<>	144:ef7eb2e8f9f7	3201	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
<>	144:ef7eb2e8f9f7	3202	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
<>	144:ef7eb2e8f9f7	3203	* @retval None
<>	144:ef7eb2e8f9f7	3204	*/
<>	144:ef7eb2e8f9f7	3205	__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
<>	144:ef7eb2e8f9f7	3206	{
<>	144:ef7eb2e8f9f7	3207	MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
<>	144:ef7eb2e8f9f7	3208	}
<>	144:ef7eb2e8f9f7	3209
<>	144:ef7eb2e8f9f7	3210	/**
<>	144:ef7eb2e8f9f7	3211	* @brief Get ADC group regular sequencer length and scan direction.
<>	144:ef7eb2e8f9f7	3212	* @note Description of ADC group regular sequencer features:
<>	144:ef7eb2e8f9f7	3213	* - For devices with sequencer fully configurable
<>	144:ef7eb2e8f9f7	3214	* (function "LL_ADC_REG_SetSequencerRanks()" available):
<>	144:ef7eb2e8f9f7	3215	* sequencer length and each rank affectation to a channel
<>	144:ef7eb2e8f9f7	3216	* are configurable.
<>	144:ef7eb2e8f9f7	3217	* This function retrieves:
<>	144:ef7eb2e8f9f7	3218	* - Sequence length: Number of ranks in the scan sequence.
<>	144:ef7eb2e8f9f7	3219	* - Sequence direction: Unless specified in parameters, sequencer
<>	144:ef7eb2e8f9f7	3220	* scan direction is forward (from rank 1 to rank n).
<>	144:ef7eb2e8f9f7	3221	* Sequencer ranks are selected using
<>	144:ef7eb2e8f9f7	3222	* function "LL_ADC_REG_SetSequencerRanks()".
<>	144:ef7eb2e8f9f7	3223	* - For devices with sequencer not fully configurable
<>	144:ef7eb2e8f9f7	3224	* (function "LL_ADC_REG_SetSequencerChannels()" available):
<>	144:ef7eb2e8f9f7	3225	* sequencer length and each rank affectation to a channel
<>	144:ef7eb2e8f9f7	3226	* are defined by channel number.
<>	144:ef7eb2e8f9f7	3227	* This function retrieves:
<>	144:ef7eb2e8f9f7	3228	* - Sequence length: Number of ranks in the scan sequence is
<>	144:ef7eb2e8f9f7	3229	* defined by number of channels set in the sequence,
<>	144:ef7eb2e8f9f7	3230	* rank of each channel is fixed by channel HW number.
<>	144:ef7eb2e8f9f7	3231	* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
<>	144:ef7eb2e8f9f7	3232	* - Sequence direction: Unless specified in parameters, sequencer
<>	144:ef7eb2e8f9f7	3233	* scan direction is forward (from lowest channel number to
<>	144:ef7eb2e8f9f7	3234	* highest channel number).
<>	144:ef7eb2e8f9f7	3235	* Sequencer ranks are selected using
<>	144:ef7eb2e8f9f7	3236	* function "LL_ADC_REG_SetSequencerChannels()".
<>	144:ef7eb2e8f9f7	3237	* @note Sequencer disabled is equivalent to sequencer of 1 rank:
<>	144:ef7eb2e8f9f7	3238	* ADC conversion on only 1 channel.
<>	144:ef7eb2e8f9f7	3239	* @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
<>	144:ef7eb2e8f9f7	3240	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	3241	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	3242	* @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
<>	144:ef7eb2e8f9f7	3243	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
<>	144:ef7eb2e8f9f7	3244	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
<>	144:ef7eb2e8f9f7	3245	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
<>	144:ef7eb2e8f9f7	3246	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
<>	144:ef7eb2e8f9f7	3247	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
<>	144:ef7eb2e8f9f7	3248	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
<>	144:ef7eb2e8f9f7	3249	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
<>	144:ef7eb2e8f9f7	3250	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
<>	144:ef7eb2e8f9f7	3251	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
<>	144:ef7eb2e8f9f7	3252	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
<>	144:ef7eb2e8f9f7	3253	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
<>	144:ef7eb2e8f9f7	3254	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
<>	144:ef7eb2e8f9f7	3255	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
<>	144:ef7eb2e8f9f7	3256	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
<>	144:ef7eb2e8f9f7	3257	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
<>	144:ef7eb2e8f9f7	3258	*/
<>	144:ef7eb2e8f9f7	3259	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	3260	{
<>	144:ef7eb2e8f9f7	3261	return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
<>	144:ef7eb2e8f9f7	3262	}
<>	144:ef7eb2e8f9f7	3263
<>	144:ef7eb2e8f9f7	3264	/**
<>	144:ef7eb2e8f9f7	3265	* @brief Set ADC group regular sequencer discontinuous mode:
<>	144:ef7eb2e8f9f7	3266	* sequence subdivided and scan conversions interrupted every selected
<>	144:ef7eb2e8f9f7	3267	* number of ranks.
<>	144:ef7eb2e8f9f7	3268	* @note It is not possible to enable both ADC group regular
<>	144:ef7eb2e8f9f7	3269	* continuous mode and sequencer discontinuous mode.
<>	144:ef7eb2e8f9f7	3270	* @note It is not possible to enable both ADC auto-injected mode
<>	144:ef7eb2e8f9f7	3271	* and ADC group regular sequencer discontinuous mode.
<>	144:ef7eb2e8f9f7	3272	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	3273	* ADC state:
<>	144:ef7eb2e8f9f7	3274	* ADC must be disabled or enabled without conversion on going
<>	144:ef7eb2e8f9f7	3275	* on group regular.
<>	144:ef7eb2e8f9f7	3276	* @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n
<>	144:ef7eb2e8f9f7	3277	* CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
<>	144:ef7eb2e8f9f7	3278	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	3279	* @param SeqDiscont This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3280	* @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
<>	144:ef7eb2e8f9f7	3281	* @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
<>	144:ef7eb2e8f9f7	3282	* @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
<>	144:ef7eb2e8f9f7	3283	* @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
<>	144:ef7eb2e8f9f7	3284	* @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
<>	144:ef7eb2e8f9f7	3285	* @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
<>	144:ef7eb2e8f9f7	3286	* @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
<>	144:ef7eb2e8f9f7	3287	* @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
<>	144:ef7eb2e8f9f7	3288	* @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
<>	144:ef7eb2e8f9f7	3289	* @retval None
<>	144:ef7eb2e8f9f7	3290	*/
<>	144:ef7eb2e8f9f7	3291	__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
<>	144:ef7eb2e8f9f7	3292	{
<>	144:ef7eb2e8f9f7	3293	MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN \| ADC_CFGR_DISCNUM, SeqDiscont);
<>	144:ef7eb2e8f9f7	3294	}
<>	144:ef7eb2e8f9f7	3295
<>	144:ef7eb2e8f9f7	3296	/**
<>	144:ef7eb2e8f9f7	3297	* @brief Get ADC group regular sequencer discontinuous mode:
<>	144:ef7eb2e8f9f7	3298	* sequence subdivided and scan conversions interrupted every selected
<>	144:ef7eb2e8f9f7	3299	* number of ranks.
<>	144:ef7eb2e8f9f7	3300	* @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n
<>	144:ef7eb2e8f9f7	3301	* CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
<>	144:ef7eb2e8f9f7	3302	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	3303	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	3304	* @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
<>	144:ef7eb2e8f9f7	3305	* @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
<>	144:ef7eb2e8f9f7	3306	* @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
<>	144:ef7eb2e8f9f7	3307	* @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
<>	144:ef7eb2e8f9f7	3308	* @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
<>	144:ef7eb2e8f9f7	3309	* @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
<>	144:ef7eb2e8f9f7	3310	* @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
<>	144:ef7eb2e8f9f7	3311	* @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
<>	144:ef7eb2e8f9f7	3312	* @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
<>	144:ef7eb2e8f9f7	3313	*/
<>	144:ef7eb2e8f9f7	3314	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	3315	{
<>	144:ef7eb2e8f9f7	3316	return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN \| ADC_CFGR_DISCNUM));
<>	144:ef7eb2e8f9f7	3317	}
<>	144:ef7eb2e8f9f7	3318
<>	144:ef7eb2e8f9f7	3319	/**
<>	144:ef7eb2e8f9f7	3320	* @brief Set ADC group regular sequence: channel on the selected
<>	144:ef7eb2e8f9f7	3321	* scan sequence rank.
<>	144:ef7eb2e8f9f7	3322	* @note This function performs configuration of:
<>	144:ef7eb2e8f9f7	3323	* - Channels ordering into each rank of scan sequence:
<>	144:ef7eb2e8f9f7	3324	* whatever channel can be placed into whatever rank.
<>	144:ef7eb2e8f9f7	3325	* @note On this STM32 serie, ADC group regular sequencer is
<>	144:ef7eb2e8f9f7	3326	* fully configurable: sequencer length and each rank
<>	144:ef7eb2e8f9f7	3327	* affectation to a channel are configurable.
<>	144:ef7eb2e8f9f7	3328	* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
<>	144:ef7eb2e8f9f7	3329	* @note Depending on devices and packages, some channels may not be available.
<>	144:ef7eb2e8f9f7	3330	* Refer to device datasheet for channels availability.
<>	144:ef7eb2e8f9f7	3331	* @note On this STM32 serie, to measure internal channels (VrefInt,
<>	144:ef7eb2e8f9f7	3332	* TempSensor, ...), measurement paths to internal channels must be
<>	144:ef7eb2e8f9f7	3333	* enabled separately.
<>	144:ef7eb2e8f9f7	3334	* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
<>	144:ef7eb2e8f9f7	3335	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	3336	* ADC state:
<>	144:ef7eb2e8f9f7	3337	* ADC must be disabled or enabled without conversion on going
<>	144:ef7eb2e8f9f7	3338	* on group regular.
<>	144:ef7eb2e8f9f7	3339	* @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3340	* SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3341	* SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3342	* SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3343	* SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3344	* SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3345	* SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3346	* SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3347	* SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3348	* SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3349	* SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3350	* SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3351	* SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3352	* SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3353	* SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3354	* SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
<>	144:ef7eb2e8f9f7	3355	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	3356	* @param Rank This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3357	* @arg @ref LL_ADC_REG_RANK_1
<>	144:ef7eb2e8f9f7	3358	* @arg @ref LL_ADC_REG_RANK_2
<>	144:ef7eb2e8f9f7	3359	* @arg @ref LL_ADC_REG_RANK_3
<>	144:ef7eb2e8f9f7	3360	* @arg @ref LL_ADC_REG_RANK_4
<>	144:ef7eb2e8f9f7	3361	* @arg @ref LL_ADC_REG_RANK_5
<>	144:ef7eb2e8f9f7	3362	* @arg @ref LL_ADC_REG_RANK_6
<>	144:ef7eb2e8f9f7	3363	* @arg @ref LL_ADC_REG_RANK_7
<>	144:ef7eb2e8f9f7	3364	* @arg @ref LL_ADC_REG_RANK_8
<>	144:ef7eb2e8f9f7	3365	* @arg @ref LL_ADC_REG_RANK_9
<>	144:ef7eb2e8f9f7	3366	* @arg @ref LL_ADC_REG_RANK_10
<>	144:ef7eb2e8f9f7	3367	* @arg @ref LL_ADC_REG_RANK_11
<>	144:ef7eb2e8f9f7	3368	* @arg @ref LL_ADC_REG_RANK_12
<>	144:ef7eb2e8f9f7	3369	* @arg @ref LL_ADC_REG_RANK_13
<>	144:ef7eb2e8f9f7	3370	* @arg @ref LL_ADC_REG_RANK_14
<>	144:ef7eb2e8f9f7	3371	* @arg @ref LL_ADC_REG_RANK_15
<>	144:ef7eb2e8f9f7	3372	* @arg @ref LL_ADC_REG_RANK_16
<>	144:ef7eb2e8f9f7	3373	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3374	* @arg @ref LL_ADC_CHANNEL_0
<>	144:ef7eb2e8f9f7	3375	* @arg @ref LL_ADC_CHANNEL_1 (7)
<>	144:ef7eb2e8f9f7	3376	* @arg @ref LL_ADC_CHANNEL_2 (7)
<>	144:ef7eb2e8f9f7	3377	* @arg @ref LL_ADC_CHANNEL_3 (7)
<>	144:ef7eb2e8f9f7	3378	* @arg @ref LL_ADC_CHANNEL_4 (7)
<>	144:ef7eb2e8f9f7	3379	* @arg @ref LL_ADC_CHANNEL_5 (7)
<>	144:ef7eb2e8f9f7	3380	* @arg @ref LL_ADC_CHANNEL_6
<>	144:ef7eb2e8f9f7	3381	* @arg @ref LL_ADC_CHANNEL_7
<>	144:ef7eb2e8f9f7	3382	* @arg @ref LL_ADC_CHANNEL_8
<>	144:ef7eb2e8f9f7	3383	* @arg @ref LL_ADC_CHANNEL_9
<>	144:ef7eb2e8f9f7	3384	* @arg @ref LL_ADC_CHANNEL_10
<>	144:ef7eb2e8f9f7	3385	* @arg @ref LL_ADC_CHANNEL_11
<>	144:ef7eb2e8f9f7	3386	* @arg @ref LL_ADC_CHANNEL_12
<>	144:ef7eb2e8f9f7	3387	* @arg @ref LL_ADC_CHANNEL_13
<>	144:ef7eb2e8f9f7	3388	* @arg @ref LL_ADC_CHANNEL_14
<>	144:ef7eb2e8f9f7	3389	* @arg @ref LL_ADC_CHANNEL_15
<>	144:ef7eb2e8f9f7	3390	* @arg @ref LL_ADC_CHANNEL_16
<>	144:ef7eb2e8f9f7	3391	* @arg @ref LL_ADC_CHANNEL_17
<>	144:ef7eb2e8f9f7	3392	* @arg @ref LL_ADC_CHANNEL_18
<>	144:ef7eb2e8f9f7	3393	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	144:ef7eb2e8f9f7	3394	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
<>	144:ef7eb2e8f9f7	3395	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
<>	144:ef7eb2e8f9f7	3396	* @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
<>	144:ef7eb2e8f9f7	3397	* @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
<>	144:ef7eb2e8f9f7	3398	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	3399	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	3400	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	3401	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	3402	*
<>	144:ef7eb2e8f9f7	3403	* (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
<>	144:ef7eb2e8f9f7	3404	* (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
<>	144:ef7eb2e8f9f7	3405	* (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
<>	144:ef7eb2e8f9f7	3406	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
<>	144:ef7eb2e8f9f7	3407	* (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
<>	144:ef7eb2e8f9f7	3408	* (6) On STM32L4, parameter available on devices with several ADC instances.\n
<>	144:ef7eb2e8f9f7	3409	* (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
<>	144:ef7eb2e8f9f7	3410	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
<>	144:ef7eb2e8f9f7	3411	* @retval None
<>	144:ef7eb2e8f9f7	3412	*/
<>	144:ef7eb2e8f9f7	3413	__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
<>	144:ef7eb2e8f9f7	3414	{
<>	144:ef7eb2e8f9f7	3415	/* Set bits with content of parameter "Channel" with bits position */
<>	144:ef7eb2e8f9f7	3416	/* in register and register position depending on parameter "Rank". */
<>	144:ef7eb2e8f9f7	3417	/* Parameters "Rank" and "Channel" are used with masks because containing */
<>	144:ef7eb2e8f9f7	3418	/* other bits reserved for other purpose. */
<>	144:ef7eb2e8f9f7	3419	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
<>	144:ef7eb2e8f9f7	3420
<>	144:ef7eb2e8f9f7	3421	MODIFY_REG(*preg,
<>	144:ef7eb2e8f9f7	3422	ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
<>	144:ef7eb2e8f9f7	3423	(Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_REG_RANK_ID_SQRX_MASK)));
<>	144:ef7eb2e8f9f7	3424	}
<>	144:ef7eb2e8f9f7	3425
<>	144:ef7eb2e8f9f7	3426	/**
<>	144:ef7eb2e8f9f7	3427	* @brief Get ADC group regular sequence: channel on the selected
<>	144:ef7eb2e8f9f7	3428	* scan sequence rank.
<>	144:ef7eb2e8f9f7	3429	* @note On this STM32 serie, ADC group regular sequencer is
<>	144:ef7eb2e8f9f7	3430	* fully configurable: sequencer length and each rank
<>	144:ef7eb2e8f9f7	3431	* affectation to a channel are configurable.
<>	144:ef7eb2e8f9f7	3432	* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
<>	144:ef7eb2e8f9f7	3433	* @note Depending on devices and packages, some channels may not be available.
<>	144:ef7eb2e8f9f7	3434	* Refer to device datasheet for channels availability.
<>	144:ef7eb2e8f9f7	3435	* @note Usage of the returned channel number:
<>	144:ef7eb2e8f9f7	3436	* - To reinject this channel into another function LL_ADC_xxx:
<>	144:ef7eb2e8f9f7	3437	* the returned channel number is only partly formatted on definition
<>	144:ef7eb2e8f9f7	3438	* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
<>	144:ef7eb2e8f9f7	3439	* with parts of literals LL_ADC_CHANNEL_x or using
<>	144:ef7eb2e8f9f7	3440	* helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	144:ef7eb2e8f9f7	3441	* Then the selected literal LL_ADC_CHANNEL_x can be used
<>	144:ef7eb2e8f9f7	3442	* as parameter for another function.
<>	144:ef7eb2e8f9f7	3443	* - To get the channel number in decimal format:
<>	144:ef7eb2e8f9f7	3444	* process the returned value with the helper macro
<>	144:ef7eb2e8f9f7	3445	* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	144:ef7eb2e8f9f7	3446	* @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3447	* SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3448	* SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3449	* SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3450	* SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3451	* SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3452	* SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3453	* SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3454	* SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3455	* SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3456	* SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3457	* SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3458	* SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3459	* SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3460	* SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3461	* SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
<>	144:ef7eb2e8f9f7	3462	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	3463	* @param Rank This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3464	* @arg @ref LL_ADC_REG_RANK_1
<>	144:ef7eb2e8f9f7	3465	* @arg @ref LL_ADC_REG_RANK_2
<>	144:ef7eb2e8f9f7	3466	* @arg @ref LL_ADC_REG_RANK_3
<>	144:ef7eb2e8f9f7	3467	* @arg @ref LL_ADC_REG_RANK_4
<>	144:ef7eb2e8f9f7	3468	* @arg @ref LL_ADC_REG_RANK_5
<>	144:ef7eb2e8f9f7	3469	* @arg @ref LL_ADC_REG_RANK_6
<>	144:ef7eb2e8f9f7	3470	* @arg @ref LL_ADC_REG_RANK_7
<>	144:ef7eb2e8f9f7	3471	* @arg @ref LL_ADC_REG_RANK_8
<>	144:ef7eb2e8f9f7	3472	* @arg @ref LL_ADC_REG_RANK_9
<>	144:ef7eb2e8f9f7	3473	* @arg @ref LL_ADC_REG_RANK_10
<>	144:ef7eb2e8f9f7	3474	* @arg @ref LL_ADC_REG_RANK_11
<>	144:ef7eb2e8f9f7	3475	* @arg @ref LL_ADC_REG_RANK_12
<>	144:ef7eb2e8f9f7	3476	* @arg @ref LL_ADC_REG_RANK_13
<>	144:ef7eb2e8f9f7	3477	* @arg @ref LL_ADC_REG_RANK_14
<>	144:ef7eb2e8f9f7	3478	* @arg @ref LL_ADC_REG_RANK_15
<>	144:ef7eb2e8f9f7	3479	* @arg @ref LL_ADC_REG_RANK_16
<>	144:ef7eb2e8f9f7	3480	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	3481	* @arg @ref LL_ADC_CHANNEL_0
<>	144:ef7eb2e8f9f7	3482	* @arg @ref LL_ADC_CHANNEL_1 (7)
<>	144:ef7eb2e8f9f7	3483	* @arg @ref LL_ADC_CHANNEL_2 (7)
<>	144:ef7eb2e8f9f7	3484	* @arg @ref LL_ADC_CHANNEL_3 (7)
<>	144:ef7eb2e8f9f7	3485	* @arg @ref LL_ADC_CHANNEL_4 (7)
<>	144:ef7eb2e8f9f7	3486	* @arg @ref LL_ADC_CHANNEL_5 (7)
<>	144:ef7eb2e8f9f7	3487	* @arg @ref LL_ADC_CHANNEL_6
<>	144:ef7eb2e8f9f7	3488	* @arg @ref LL_ADC_CHANNEL_7
<>	144:ef7eb2e8f9f7	3489	* @arg @ref LL_ADC_CHANNEL_8
<>	144:ef7eb2e8f9f7	3490	* @arg @ref LL_ADC_CHANNEL_9
<>	144:ef7eb2e8f9f7	3491	* @arg @ref LL_ADC_CHANNEL_10
<>	144:ef7eb2e8f9f7	3492	* @arg @ref LL_ADC_CHANNEL_11
<>	144:ef7eb2e8f9f7	3493	* @arg @ref LL_ADC_CHANNEL_12
<>	144:ef7eb2e8f9f7	3494	* @arg @ref LL_ADC_CHANNEL_13
<>	144:ef7eb2e8f9f7	3495	* @arg @ref LL_ADC_CHANNEL_14
<>	144:ef7eb2e8f9f7	3496	* @arg @ref LL_ADC_CHANNEL_15
<>	144:ef7eb2e8f9f7	3497	* @arg @ref LL_ADC_CHANNEL_16
<>	144:ef7eb2e8f9f7	3498	* @arg @ref LL_ADC_CHANNEL_17
<>	144:ef7eb2e8f9f7	3499	* @arg @ref LL_ADC_CHANNEL_18
<>	144:ef7eb2e8f9f7	3500	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	144:ef7eb2e8f9f7	3501	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
<>	144:ef7eb2e8f9f7	3502	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
<>	144:ef7eb2e8f9f7	3503	* @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
<>	144:ef7eb2e8f9f7	3504	* @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
<>	144:ef7eb2e8f9f7	3505	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	3506	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	3507	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	3508	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	3509	*
<>	144:ef7eb2e8f9f7	3510	* (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
<>	144:ef7eb2e8f9f7	3511	* (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
<>	144:ef7eb2e8f9f7	3512	* (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
<>	144:ef7eb2e8f9f7	3513	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
<>	144:ef7eb2e8f9f7	3514	* (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
<>	144:ef7eb2e8f9f7	3515	* (6) On STM32L4, parameter available on devices with several ADC instances.\n
<>	144:ef7eb2e8f9f7	3516	* (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
<>	144:ef7eb2e8f9f7	3517	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
<>	144:ef7eb2e8f9f7	3518	* (1, 2, 3, 4) For ADC channel read back from ADC register,
<>	144:ef7eb2e8f9f7	3519	* comparison with internal channel parameter to be done
<>	144:ef7eb2e8f9f7	3520	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
<>	144:ef7eb2e8f9f7	3521	*/
<>	144:ef7eb2e8f9f7	3522	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
<>	144:ef7eb2e8f9f7	3523	{
<>	144:ef7eb2e8f9f7	3524	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
<>	144:ef7eb2e8f9f7	3525
<>	144:ef7eb2e8f9f7	3526	return (uint32_t) (READ_BIT(*preg,
<>	144:ef7eb2e8f9f7	3527	ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
<>	144:ef7eb2e8f9f7	3528	<< (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_REG_RANK_ID_SQRX_MASK))
<>	144:ef7eb2e8f9f7	3529	);
<>	144:ef7eb2e8f9f7	3530	}
<>	144:ef7eb2e8f9f7	3531
<>	144:ef7eb2e8f9f7	3532	/**
<>	144:ef7eb2e8f9f7	3533	* @brief Set ADC continuous conversion mode on ADC group regular.
<>	144:ef7eb2e8f9f7	3534	* @note Description of ADC continuous conversion mode:
<>	144:ef7eb2e8f9f7	3535	* - single mode: one conversion per trigger
<>	144:ef7eb2e8f9f7	3536	* - continuous mode: after the first trigger, following
<>	144:ef7eb2e8f9f7	3537	* conversions launched successively automatically.
<>	144:ef7eb2e8f9f7	3538	* @note It is not possible to enable both ADC group regular
<>	144:ef7eb2e8f9f7	3539	* continuous mode and sequencer discontinuous mode.
<>	144:ef7eb2e8f9f7	3540	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	3541	* ADC state:
<>	144:ef7eb2e8f9f7	3542	* ADC must be disabled or enabled without conversion on going
<>	144:ef7eb2e8f9f7	3543	* on group regular.
<>	144:ef7eb2e8f9f7	3544	* @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
<>	144:ef7eb2e8f9f7	3545	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	3546	* @param Continuous This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3547	* @arg @ref LL_ADC_REG_CONV_SINGLE
<>	144:ef7eb2e8f9f7	3548	* @arg @ref LL_ADC_REG_CONV_CONTINUOUS
<>	144:ef7eb2e8f9f7	3549	* @retval None
<>	144:ef7eb2e8f9f7	3550	*/
<>	144:ef7eb2e8f9f7	3551	__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
<>	144:ef7eb2e8f9f7	3552	{
<>	144:ef7eb2e8f9f7	3553	MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
<>	144:ef7eb2e8f9f7	3554	}
<>	144:ef7eb2e8f9f7	3555
<>	144:ef7eb2e8f9f7	3556	/**
<>	144:ef7eb2e8f9f7	3557	* @brief Get ADC continuous conversion mode on ADC group regular.
<>	144:ef7eb2e8f9f7	3558	* @note Description of ADC continuous conversion mode:
<>	144:ef7eb2e8f9f7	3559	* - single mode: one conversion per trigger
<>	144:ef7eb2e8f9f7	3560	* - continuous mode: after the first trigger, following
<>	144:ef7eb2e8f9f7	3561	* conversions launched successively automatically.
<>	144:ef7eb2e8f9f7	3562	* @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
<>	144:ef7eb2e8f9f7	3563	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	3564	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	3565	* @arg @ref LL_ADC_REG_CONV_SINGLE
<>	144:ef7eb2e8f9f7	3566	* @arg @ref LL_ADC_REG_CONV_CONTINUOUS
<>	144:ef7eb2e8f9f7	3567	*/
<>	144:ef7eb2e8f9f7	3568	__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	3569	{
<>	144:ef7eb2e8f9f7	3570	return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
<>	144:ef7eb2e8f9f7	3571	}
<>	144:ef7eb2e8f9f7	3572
<>	144:ef7eb2e8f9f7	3573	/**
<>	144:ef7eb2e8f9f7	3574	* @brief Set ADC group regular conversion data transfer: no transfer or
<>	144:ef7eb2e8f9f7	3575	* transfer by DMA, and DMA requests mode.
<>	144:ef7eb2e8f9f7	3576	* @note If transfer by DMA selected, specifies the DMA requests
<>	144:ef7eb2e8f9f7	3577	* mode:
<>	144:ef7eb2e8f9f7	3578	* - Limited mode (One shot mode): DMA transfer requests are stopped
<>	144:ef7eb2e8f9f7	3579	* when number of DMA data transfers (number of
<>	144:ef7eb2e8f9f7	3580	* ADC conversions) is reached.
<>	144:ef7eb2e8f9f7	3581	* This ADC mode is intended to be used with DMA mode non-circular.
<>	144:ef7eb2e8f9f7	3582	* - Unlimited mode: DMA transfer requests are unlimited,
<>	144:ef7eb2e8f9f7	3583	* whatever number of DMA data transfers (number of
<>	144:ef7eb2e8f9f7	3584	* ADC conversions).
<>	144:ef7eb2e8f9f7	3585	* This ADC mode is intended to be used with DMA mode circular.
<>	144:ef7eb2e8f9f7	3586	* @note If ADC DMA requests mode is set to unlimited and DMA is set to
<>	144:ef7eb2e8f9f7	3587	* mode non-circular:
<>	144:ef7eb2e8f9f7	3588	* when DMA transfers size will be reached, DMA will stop transfers of
<>	144:ef7eb2e8f9f7	3589	* ADC conversions data ADC will raise an overrun error
<>	144:ef7eb2e8f9f7	3590	* (overrun flag and interruption if enabled).
<>	144:ef7eb2e8f9f7	3591	* @note For devices with several ADC instances: ADC multimode DMA
<>	144:ef7eb2e8f9f7	3592	* settings are available using function @ref LL_ADC_SetMultiDMATransfer().
<>	144:ef7eb2e8f9f7	3593	* @note To configure DMA source address (peripheral address),
<>	144:ef7eb2e8f9f7	3594	* use function @ref LL_ADC_DMA_GetRegAddr().
<>	144:ef7eb2e8f9f7	3595	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	3596	* ADC state:
<>	144:ef7eb2e8f9f7	3597	* ADC must be disabled or enabled without conversion on going
<>	144:ef7eb2e8f9f7	3598	* on either groups regular or injected.
<>	144:ef7eb2e8f9f7	3599	* @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n
<>	144:ef7eb2e8f9f7	3600	* CFGR DMACFG LL_ADC_REG_SetDMATransfer
<>	144:ef7eb2e8f9f7	3601	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	3602	* @param DMATransfer This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3603	* @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
<>	144:ef7eb2e8f9f7	3604	* @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
<>	144:ef7eb2e8f9f7	3605	* @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
<>	144:ef7eb2e8f9f7	3606	* @retval None
<>	144:ef7eb2e8f9f7	3607	*/
<>	144:ef7eb2e8f9f7	3608	__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
<>	144:ef7eb2e8f9f7	3609	{
<>	144:ef7eb2e8f9f7	3610	MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN \| ADC_CFGR_DMACFG, DMATransfer);
<>	144:ef7eb2e8f9f7	3611	}
<>	144:ef7eb2e8f9f7	3612
<>	144:ef7eb2e8f9f7	3613	/**
<>	144:ef7eb2e8f9f7	3614	* @brief Get ADC group regular conversion data transfer: no transfer or
<>	144:ef7eb2e8f9f7	3615	* transfer by DMA, and DMA requests mode.
<>	144:ef7eb2e8f9f7	3616	* @note If transfer by DMA selected, specifies the DMA requests
<>	144:ef7eb2e8f9f7	3617	* mode:
<>	144:ef7eb2e8f9f7	3618	* - Limited mode (One shot mode): DMA transfer requests are stopped
<>	144:ef7eb2e8f9f7	3619	* when number of DMA data transfers (number of
<>	144:ef7eb2e8f9f7	3620	* ADC conversions) is reached.
<>	144:ef7eb2e8f9f7	3621	* This ADC mode is intended to be used with DMA mode non-circular.
<>	144:ef7eb2e8f9f7	3622	* - Unlimited mode: DMA transfer requests are unlimited,
<>	144:ef7eb2e8f9f7	3623	* whatever number of DMA data transfers (number of
<>	144:ef7eb2e8f9f7	3624	* ADC conversions).
<>	144:ef7eb2e8f9f7	3625	* This ADC mode is intended to be used with DMA mode circular.
<>	144:ef7eb2e8f9f7	3626	* @note If ADC DMA requests mode is set to unlimited and DMA is set to
<>	144:ef7eb2e8f9f7	3627	* mode non-circular:
<>	144:ef7eb2e8f9f7	3628	* when DMA transfers size will be reached, DMA will stop transfers of
<>	144:ef7eb2e8f9f7	3629	* ADC conversions data ADC will raise an overrun error
<>	144:ef7eb2e8f9f7	3630	* (overrun flag and interruption if enabled).
<>	144:ef7eb2e8f9f7	3631	* @note For devices with several ADC instances: ADC multimode DMA
<>	144:ef7eb2e8f9f7	3632	* settings are available using function @ref LL_ADC_GetMultiDMATransfer().
<>	144:ef7eb2e8f9f7	3633	* @note To configure DMA source address (peripheral address),
<>	144:ef7eb2e8f9f7	3634	* use function @ref LL_ADC_DMA_GetRegAddr().
<>	144:ef7eb2e8f9f7	3635	* @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n
<>	144:ef7eb2e8f9f7	3636	* CFGR DMACFG LL_ADC_REG_GetDMATransfer
<>	144:ef7eb2e8f9f7	3637	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	3638	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	3639	* @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
<>	144:ef7eb2e8f9f7	3640	* @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
<>	144:ef7eb2e8f9f7	3641	* @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
<>	144:ef7eb2e8f9f7	3642	*/
<>	144:ef7eb2e8f9f7	3643	__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	3644	{
<>	144:ef7eb2e8f9f7	3645	return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN \| ADC_CFGR_DMACFG));
<>	144:ef7eb2e8f9f7	3646	}
<>	144:ef7eb2e8f9f7	3647
<>	144:ef7eb2e8f9f7	3648
<>	144:ef7eb2e8f9f7	3649	/**
<>	144:ef7eb2e8f9f7	3650	* @brief Set ADC group regular behavior in case of overrun:
<>	144:ef7eb2e8f9f7	3651	* data preserved or overwritten.
<>	144:ef7eb2e8f9f7	3652	* @note Compatibility with devices without feature overrun:
<>	144:ef7eb2e8f9f7	3653	* other devices without this feature have a behavior
<>	144:ef7eb2e8f9f7	3654	* equivalent to data overwritten.
<>	144:ef7eb2e8f9f7	3655	* The default setting of overrun is data preserved.
<>	144:ef7eb2e8f9f7	3656	* Therefore, for compatibility with all devices, parameter
<>	144:ef7eb2e8f9f7	3657	* overrun should be set to data overwritten.
<>	144:ef7eb2e8f9f7	3658	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	3659	* ADC state:
<>	144:ef7eb2e8f9f7	3660	* ADC must be disabled or enabled without conversion on going
<>	144:ef7eb2e8f9f7	3661	* on group regular.
<>	144:ef7eb2e8f9f7	3662	* @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
<>	144:ef7eb2e8f9f7	3663	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	3664	* @param Overrun This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3665	* @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
<>	144:ef7eb2e8f9f7	3666	* @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
<>	144:ef7eb2e8f9f7	3667	* @retval None
<>	144:ef7eb2e8f9f7	3668	*/
<>	144:ef7eb2e8f9f7	3669	__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
<>	144:ef7eb2e8f9f7	3670	{
<>	144:ef7eb2e8f9f7	3671	MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
<>	144:ef7eb2e8f9f7	3672	}
<>	144:ef7eb2e8f9f7	3673
<>	144:ef7eb2e8f9f7	3674	/**
<>	144:ef7eb2e8f9f7	3675	* @brief Get ADC group regular behavior in case of overrun:
<>	144:ef7eb2e8f9f7	3676	* data preserved or overwritten.
<>	144:ef7eb2e8f9f7	3677	* @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
<>	144:ef7eb2e8f9f7	3678	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	3679	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	3680	* @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
<>	144:ef7eb2e8f9f7	3681	* @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
<>	144:ef7eb2e8f9f7	3682	*/
<>	144:ef7eb2e8f9f7	3683	__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	3684	{
<>	144:ef7eb2e8f9f7	3685	return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
<>	144:ef7eb2e8f9f7	3686	}
<>	144:ef7eb2e8f9f7	3687
<>	144:ef7eb2e8f9f7	3688	/**
<>	144:ef7eb2e8f9f7	3689	* @}
<>	144:ef7eb2e8f9f7	3690	*/
<>	144:ef7eb2e8f9f7	3691
<>	144:ef7eb2e8f9f7	3692	/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
<>	144:ef7eb2e8f9f7	3693	* @{
<>	144:ef7eb2e8f9f7	3694	*/
<>	144:ef7eb2e8f9f7	3695
<>	144:ef7eb2e8f9f7	3696	/**
<>	144:ef7eb2e8f9f7	3697	* @brief Set ADC group injected conversion trigger source:
<>	144:ef7eb2e8f9f7	3698	* internal (SW start) or from external IP (timer event,
<>	144:ef7eb2e8f9f7	3699	* external interrupt line).
<>	144:ef7eb2e8f9f7	3700	* @note On this STM32 serie, setting trigger source to external trigger
<>	144:ef7eb2e8f9f7	3701	* also set trigger polarity to rising edge
<>	144:ef7eb2e8f9f7	3702	* (default setting for compatibility with some ADC on other
<>	144:ef7eb2e8f9f7	3703	* STM32 families having this setting set by HW default value).
<>	144:ef7eb2e8f9f7	3704	* In case of need to modify trigger edge, use
<>	144:ef7eb2e8f9f7	3705	* function @ref LL_ADC_INJ_SetTriggerEdge().
<>	144:ef7eb2e8f9f7	3706	* @note Availability of parameters of trigger sources from timer
<>	144:ef7eb2e8f9f7	3707	* depends on timers availability on the selected device.
<>	144:ef7eb2e8f9f7	3708	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	3709	* ADC state:
<>	144:ef7eb2e8f9f7	3710	* ADC must not be disabled. Can be enabled with or without conversion
<>	144:ef7eb2e8f9f7	3711	* on going on either groups regular or injected.
<>	144:ef7eb2e8f9f7	3712	* @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n
<>	144:ef7eb2e8f9f7	3713	* JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
<>	144:ef7eb2e8f9f7	3714	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	3715	* @param TriggerSource This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3716	* @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
<>	144:ef7eb2e8f9f7	3717	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
<>	144:ef7eb2e8f9f7	3718	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
<>	144:ef7eb2e8f9f7	3719	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
<>	144:ef7eb2e8f9f7	3720	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
<>	144:ef7eb2e8f9f7	3721	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
<>	144:ef7eb2e8f9f7	3722	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
<>	144:ef7eb2e8f9f7	3723	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
<>	144:ef7eb2e8f9f7	3724	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
<>	144:ef7eb2e8f9f7	3725	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
<>	144:ef7eb2e8f9f7	3726	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
<>	144:ef7eb2e8f9f7	3727	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
<>	144:ef7eb2e8f9f7	3728	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
<>	144:ef7eb2e8f9f7	3729	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
<>	144:ef7eb2e8f9f7	3730	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
<>	144:ef7eb2e8f9f7	3731	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
<>	144:ef7eb2e8f9f7	3732	* @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
<>	144:ef7eb2e8f9f7	3733	* @retval None
<>	144:ef7eb2e8f9f7	3734	*/
<>	144:ef7eb2e8f9f7	3735	__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
<>	144:ef7eb2e8f9f7	3736	{
<>	144:ef7eb2e8f9f7	3737	MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL \| ADC_JSQR_JEXTEN, TriggerSource);
<>	144:ef7eb2e8f9f7	3738	}
<>	144:ef7eb2e8f9f7	3739
<>	144:ef7eb2e8f9f7	3740	/**
<>	144:ef7eb2e8f9f7	3741	* @brief Get ADC group injected conversion trigger source:
<>	144:ef7eb2e8f9f7	3742	* internal (SW start) or from external IP (timer event,
<>	144:ef7eb2e8f9f7	3743	* external interrupt line).
<>	144:ef7eb2e8f9f7	3744	* @note To determine whether group injected trigger source is
<>	144:ef7eb2e8f9f7	3745	* internal (SW start) or external, without detail
<>	144:ef7eb2e8f9f7	3746	* of which peripheral is selected as external trigger,
<>	144:ef7eb2e8f9f7	3747	* (equivalent to
<>	144:ef7eb2e8f9f7	3748	* "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
<>	144:ef7eb2e8f9f7	3749	* use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
<>	144:ef7eb2e8f9f7	3750	* @note Availability of parameters of trigger sources from timer
<>	144:ef7eb2e8f9f7	3751	* depends on timers availability on the selected device.
<>	144:ef7eb2e8f9f7	3752	* @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n
<>	144:ef7eb2e8f9f7	3753	* JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
<>	144:ef7eb2e8f9f7	3754	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	3755	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	3756	* @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
<>	144:ef7eb2e8f9f7	3757	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
<>	144:ef7eb2e8f9f7	3758	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
<>	144:ef7eb2e8f9f7	3759	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
<>	144:ef7eb2e8f9f7	3760	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
<>	144:ef7eb2e8f9f7	3761	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
<>	144:ef7eb2e8f9f7	3762	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
<>	144:ef7eb2e8f9f7	3763	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
<>	144:ef7eb2e8f9f7	3764	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
<>	144:ef7eb2e8f9f7	3765	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
<>	144:ef7eb2e8f9f7	3766	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
<>	144:ef7eb2e8f9f7	3767	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
<>	144:ef7eb2e8f9f7	3768	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
<>	144:ef7eb2e8f9f7	3769	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
<>	144:ef7eb2e8f9f7	3770	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
<>	144:ef7eb2e8f9f7	3771	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
<>	144:ef7eb2e8f9f7	3772	* @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
<>	144:ef7eb2e8f9f7	3773	*/
<>	144:ef7eb2e8f9f7	3774	__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	3775	{
<>	144:ef7eb2e8f9f7	3776	register uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL \| ADC_JSQR_JEXTEN);
<>	144:ef7eb2e8f9f7	3777
<>	144:ef7eb2e8f9f7	3778	/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
<>	144:ef7eb2e8f9f7	3779	/* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
<>	144:ef7eb2e8f9f7	3780	register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));
<>	144:ef7eb2e8f9f7	3781
<>	144:ef7eb2e8f9f7	3782	/* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
<>	144:ef7eb2e8f9f7	3783	/* to match with triggers literals definition. */
<>	144:ef7eb2e8f9f7	3784	return ((TriggerSource
<>	144:ef7eb2e8f9f7	3785	& (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
<>	144:ef7eb2e8f9f7	3786	\| ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
<>	144:ef7eb2e8f9f7	3787	);
<>	144:ef7eb2e8f9f7	3788	}
<>	144:ef7eb2e8f9f7	3789
<>	144:ef7eb2e8f9f7	3790	/**
<>	144:ef7eb2e8f9f7	3791	* @brief Get ADC group injected conversion trigger source internal (SW start)
<>	144:ef7eb2e8f9f7	3792	or external
<>	144:ef7eb2e8f9f7	3793	* @note In case of group injected trigger source set to external trigger,
<>	144:ef7eb2e8f9f7	3794	* to determine which peripheral is selected as external trigger,
<>	144:ef7eb2e8f9f7	3795	* use function @ref LL_ADC_INJ_GetTriggerSource.
<>	144:ef7eb2e8f9f7	3796	* @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
<>	144:ef7eb2e8f9f7	3797	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	3798	* @retval Value "0" if trigger source external trigger
<>	144:ef7eb2e8f9f7	3799	* Value "1" if trigger source SW start.
<>	144:ef7eb2e8f9f7	3800	*/
<>	144:ef7eb2e8f9f7	3801	__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	3802	{
<>	144:ef7eb2e8f9f7	3803	return (READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN));
<>	144:ef7eb2e8f9f7	3804	}
<>	144:ef7eb2e8f9f7	3805
<>	144:ef7eb2e8f9f7	3806	/**
<>	144:ef7eb2e8f9f7	3807	* @brief Set ADC group injected conversion trigger polarity.
<>	144:ef7eb2e8f9f7	3808	* Applicable only for trigger source set to external trigger.
<>	144:ef7eb2e8f9f7	3809	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	3810	* ADC state:
<>	144:ef7eb2e8f9f7	3811	* ADC must not be disabled. Can be enabled with or without conversion
<>	144:ef7eb2e8f9f7	3812	* on going on either groups regular or injected.
<>	144:ef7eb2e8f9f7	3813	* @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
<>	144:ef7eb2e8f9f7	3814	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	3815	* @param ExternalTriggerEdge This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3816	* @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
<>	144:ef7eb2e8f9f7	3817	* @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
<>	144:ef7eb2e8f9f7	3818	* @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
<>	144:ef7eb2e8f9f7	3819	* @retval None
<>	144:ef7eb2e8f9f7	3820	*/
<>	144:ef7eb2e8f9f7	3821	__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
<>	144:ef7eb2e8f9f7	3822	{
<>	144:ef7eb2e8f9f7	3823	MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
<>	144:ef7eb2e8f9f7	3824	}
<>	144:ef7eb2e8f9f7	3825
<>	144:ef7eb2e8f9f7	3826	/**
<>	144:ef7eb2e8f9f7	3827	* @brief Get ADC group injected conversion trigger polarity.
<>	144:ef7eb2e8f9f7	3828	* Applicable only for trigger source set to external trigger.
<>	144:ef7eb2e8f9f7	3829	* @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
<>	144:ef7eb2e8f9f7	3830	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	3831	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	3832	* @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
<>	144:ef7eb2e8f9f7	3833	* @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
<>	144:ef7eb2e8f9f7	3834	* @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
<>	144:ef7eb2e8f9f7	3835	*/
<>	144:ef7eb2e8f9f7	3836	__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	3837	{
<>	144:ef7eb2e8f9f7	3838	return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
<>	144:ef7eb2e8f9f7	3839	}
<>	144:ef7eb2e8f9f7	3840
<>	144:ef7eb2e8f9f7	3841	/**
<>	144:ef7eb2e8f9f7	3842	* @brief Set ADC group injected sequencer length and scan direction.
<>	144:ef7eb2e8f9f7	3843	* @note This function performs configuration of:
<>	144:ef7eb2e8f9f7	3844	* - Sequence length: Number of ranks in the scan sequence.
<>	144:ef7eb2e8f9f7	3845	* - Sequence direction: Unless specified in parameters, sequencer
<>	144:ef7eb2e8f9f7	3846	* scan direction is forward (from rank 1 to rank n).
<>	144:ef7eb2e8f9f7	3847	* @note Sequencer disabled is equivalent to sequencer of 1 rank:
<>	144:ef7eb2e8f9f7	3848	* ADC conversion on only 1 channel.
<>	144:ef7eb2e8f9f7	3849	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	3850	* ADC state:
<>	144:ef7eb2e8f9f7	3851	* ADC must not be disabled. Can be enabled with or without conversion
<>	144:ef7eb2e8f9f7	3852	* on going on either groups regular or injected.
<>	144:ef7eb2e8f9f7	3853	* @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
<>	144:ef7eb2e8f9f7	3854	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	3855	* @param SequencerNbRanks This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3856	* @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
<>	144:ef7eb2e8f9f7	3857	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
<>	144:ef7eb2e8f9f7	3858	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
<>	144:ef7eb2e8f9f7	3859	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
<>	144:ef7eb2e8f9f7	3860	* @retval None
<>	144:ef7eb2e8f9f7	3861	*/
<>	144:ef7eb2e8f9f7	3862	__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
<>	144:ef7eb2e8f9f7	3863	{
<>	144:ef7eb2e8f9f7	3864	MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
<>	144:ef7eb2e8f9f7	3865	}
<>	144:ef7eb2e8f9f7	3866
<>	144:ef7eb2e8f9f7	3867	/**
<>	144:ef7eb2e8f9f7	3868	* @brief Get ADC group injected sequencer length and scan direction.
<>	144:ef7eb2e8f9f7	3869	* @note This function retrieves:
<>	144:ef7eb2e8f9f7	3870	* - Sequence length: Number of ranks in the scan sequence.
<>	144:ef7eb2e8f9f7	3871	* - Sequence direction: Unless specified in parameters, sequencer
<>	144:ef7eb2e8f9f7	3872	* scan direction is forward (from rank 1 to rank n).
<>	144:ef7eb2e8f9f7	3873	* @note Sequencer disabled is equivalent to sequencer of 1 rank:
<>	144:ef7eb2e8f9f7	3874	* ADC conversion on only 1 channel.
<>	144:ef7eb2e8f9f7	3875	* @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
<>	144:ef7eb2e8f9f7	3876	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	3877	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	3878	* @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
<>	144:ef7eb2e8f9f7	3879	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
<>	144:ef7eb2e8f9f7	3880	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
<>	144:ef7eb2e8f9f7	3881	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
<>	144:ef7eb2e8f9f7	3882	*/
<>	144:ef7eb2e8f9f7	3883	__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	3884	{
<>	144:ef7eb2e8f9f7	3885	return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
<>	144:ef7eb2e8f9f7	3886	}
<>	144:ef7eb2e8f9f7	3887
<>	144:ef7eb2e8f9f7	3888	/**
<>	144:ef7eb2e8f9f7	3889	* @brief Set ADC group injected sequencer discontinuous mode:
<>	144:ef7eb2e8f9f7	3890	* sequence subdivided and scan conversions interrupted every selected
<>	144:ef7eb2e8f9f7	3891	* number of ranks.
<>	144:ef7eb2e8f9f7	3892	* @note It is not possible to enable both ADC group injected
<>	144:ef7eb2e8f9f7	3893	* auto-injected mode and sequencer discontinuous mode.
<>	144:ef7eb2e8f9f7	3894	* @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
<>	144:ef7eb2e8f9f7	3895	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	3896	* @param SeqDiscont This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3897	* @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
<>	144:ef7eb2e8f9f7	3898	* @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
<>	144:ef7eb2e8f9f7	3899	* @retval None
<>	144:ef7eb2e8f9f7	3900	*/
<>	144:ef7eb2e8f9f7	3901	__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
<>	144:ef7eb2e8f9f7	3902	{
<>	144:ef7eb2e8f9f7	3903	MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
<>	144:ef7eb2e8f9f7	3904	}
<>	144:ef7eb2e8f9f7	3905
<>	144:ef7eb2e8f9f7	3906	/**
<>	144:ef7eb2e8f9f7	3907	* @brief Get ADC group injected sequencer discontinuous mode:
<>	144:ef7eb2e8f9f7	3908	* sequence subdivided and scan conversions interrupted every selected
<>	144:ef7eb2e8f9f7	3909	* number of ranks.
<>	144:ef7eb2e8f9f7	3910	* @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
<>	144:ef7eb2e8f9f7	3911	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	3912	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	3913	* @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
<>	144:ef7eb2e8f9f7	3914	* @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
<>	144:ef7eb2e8f9f7	3915	*/
<>	144:ef7eb2e8f9f7	3916	__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	3917	{
<>	144:ef7eb2e8f9f7	3918	return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
<>	144:ef7eb2e8f9f7	3919	}
<>	144:ef7eb2e8f9f7	3920
<>	144:ef7eb2e8f9f7	3921	/**
<>	144:ef7eb2e8f9f7	3922	* @brief Set ADC group injected sequence: channel on the selected
<>	144:ef7eb2e8f9f7	3923	* sequence rank.
<>	144:ef7eb2e8f9f7	3924	* @note Depending on devices and packages, some channels may not be available.
<>	144:ef7eb2e8f9f7	3925	* Refer to device datasheet for channels availability.
<>	144:ef7eb2e8f9f7	3926	* @note On this STM32 serie, to measure internal channels (VrefInt,
<>	144:ef7eb2e8f9f7	3927	* TempSensor, ...), measurement paths to internal channels must be
<>	144:ef7eb2e8f9f7	3928	* enabled separately.
<>	144:ef7eb2e8f9f7	3929	* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
<>	144:ef7eb2e8f9f7	3930	* @note On this STM32 serie, some fast channels are available: fast analog inputs
<>	144:ef7eb2e8f9f7	3931	* coming from GPIO pads (ADC_IN1..5).
<>	144:ef7eb2e8f9f7	3932	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	3933	* ADC state:
<>	144:ef7eb2e8f9f7	3934	* ADC must not be disabled. Can be enabled with or without conversion
<>	144:ef7eb2e8f9f7	3935	* on going on either groups regular or injected.
<>	144:ef7eb2e8f9f7	3936	* @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3937	* JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3938	* JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
<>	144:ef7eb2e8f9f7	3939	* JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
<>	144:ef7eb2e8f9f7	3940	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	3941	* @param Rank This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3942	* @arg @ref LL_ADC_INJ_RANK_1
<>	144:ef7eb2e8f9f7	3943	* @arg @ref LL_ADC_INJ_RANK_2
<>	144:ef7eb2e8f9f7	3944	* @arg @ref LL_ADC_INJ_RANK_3
<>	144:ef7eb2e8f9f7	3945	* @arg @ref LL_ADC_INJ_RANK_4
<>	144:ef7eb2e8f9f7	3946	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3947	* @arg @ref LL_ADC_CHANNEL_0
<>	144:ef7eb2e8f9f7	3948	* @arg @ref LL_ADC_CHANNEL_1 (7)
<>	144:ef7eb2e8f9f7	3949	* @arg @ref LL_ADC_CHANNEL_2 (7)
<>	144:ef7eb2e8f9f7	3950	* @arg @ref LL_ADC_CHANNEL_3 (7)
<>	144:ef7eb2e8f9f7	3951	* @arg @ref LL_ADC_CHANNEL_4 (7)
<>	144:ef7eb2e8f9f7	3952	* @arg @ref LL_ADC_CHANNEL_5 (7)
<>	144:ef7eb2e8f9f7	3953	* @arg @ref LL_ADC_CHANNEL_6
<>	144:ef7eb2e8f9f7	3954	* @arg @ref LL_ADC_CHANNEL_7
<>	144:ef7eb2e8f9f7	3955	* @arg @ref LL_ADC_CHANNEL_8
<>	144:ef7eb2e8f9f7	3956	* @arg @ref LL_ADC_CHANNEL_9
<>	144:ef7eb2e8f9f7	3957	* @arg @ref LL_ADC_CHANNEL_10
<>	144:ef7eb2e8f9f7	3958	* @arg @ref LL_ADC_CHANNEL_11
<>	144:ef7eb2e8f9f7	3959	* @arg @ref LL_ADC_CHANNEL_12
<>	144:ef7eb2e8f9f7	3960	* @arg @ref LL_ADC_CHANNEL_13
<>	144:ef7eb2e8f9f7	3961	* @arg @ref LL_ADC_CHANNEL_14
<>	144:ef7eb2e8f9f7	3962	* @arg @ref LL_ADC_CHANNEL_15
<>	144:ef7eb2e8f9f7	3963	* @arg @ref LL_ADC_CHANNEL_16
<>	144:ef7eb2e8f9f7	3964	* @arg @ref LL_ADC_CHANNEL_17
<>	144:ef7eb2e8f9f7	3965	* @arg @ref LL_ADC_CHANNEL_18
<>	144:ef7eb2e8f9f7	3966	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	144:ef7eb2e8f9f7	3967	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
<>	144:ef7eb2e8f9f7	3968	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
<>	144:ef7eb2e8f9f7	3969	* @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
<>	144:ef7eb2e8f9f7	3970	* @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
<>	144:ef7eb2e8f9f7	3971	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	3972	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	3973	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	3974	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	3975	*
<>	144:ef7eb2e8f9f7	3976	* (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
<>	144:ef7eb2e8f9f7	3977	* (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
<>	144:ef7eb2e8f9f7	3978	* (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
<>	144:ef7eb2e8f9f7	3979	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
<>	144:ef7eb2e8f9f7	3980	* (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
<>	144:ef7eb2e8f9f7	3981	* (6) On STM32L4, parameter available on devices with several ADC instances.\n
<>	144:ef7eb2e8f9f7	3982	* (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
<>	144:ef7eb2e8f9f7	3983	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
<>	144:ef7eb2e8f9f7	3984	* @retval None
<>	144:ef7eb2e8f9f7	3985	*/
<>	144:ef7eb2e8f9f7	3986	__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
<>	144:ef7eb2e8f9f7	3987	{
<>	144:ef7eb2e8f9f7	3988	/* Set bits with content of parameter "Channel" with bits position */
<>	144:ef7eb2e8f9f7	3989	/* in register depending on parameter "Rank". */
<>	144:ef7eb2e8f9f7	3990	/* Parameters "Rank" and "Channel" are used with masks because containing */
<>	144:ef7eb2e8f9f7	3991	/* other bits reserved for other purpose. */
<>	144:ef7eb2e8f9f7	3992	MODIFY_REG(ADCx->JSQR,
<>	144:ef7eb2e8f9f7	3993	ADC_CHANNEL_ID_NUMBER_MASK >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)),
<>	144:ef7eb2e8f9f7	3994	(Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)));
<>	144:ef7eb2e8f9f7	3995	}
<>	144:ef7eb2e8f9f7	3996
<>	144:ef7eb2e8f9f7	3997	/**
<>	144:ef7eb2e8f9f7	3998	* @brief Get ADC group injected sequence: channel on the selected
<>	144:ef7eb2e8f9f7	3999	* sequence rank.
<>	144:ef7eb2e8f9f7	4000	* @note Depending on devices and packages, some channels may not be available.
<>	144:ef7eb2e8f9f7	4001	* Refer to device datasheet for channels availability.
<>	144:ef7eb2e8f9f7	4002	* @note Usage of the returned channel number:
<>	144:ef7eb2e8f9f7	4003	* - To reinject this channel into another function LL_ADC_xxx:
<>	144:ef7eb2e8f9f7	4004	* the returned channel number is only partly formatted on definition
<>	144:ef7eb2e8f9f7	4005	* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
<>	144:ef7eb2e8f9f7	4006	* with parts of literals LL_ADC_CHANNEL_x or using
<>	144:ef7eb2e8f9f7	4007	* helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	144:ef7eb2e8f9f7	4008	* Then the selected literal LL_ADC_CHANNEL_x can be used
<>	144:ef7eb2e8f9f7	4009	* as parameter for another function.
<>	144:ef7eb2e8f9f7	4010	* - To get the channel number in decimal format:
<>	144:ef7eb2e8f9f7	4011	* process the returned value with the helper macro
<>	144:ef7eb2e8f9f7	4012	* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	144:ef7eb2e8f9f7	4013	* @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n
<>	144:ef7eb2e8f9f7	4014	* JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n
<>	144:ef7eb2e8f9f7	4015	* JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n
<>	144:ef7eb2e8f9f7	4016	* JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
<>	144:ef7eb2e8f9f7	4017	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	4018	* @param Rank This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4019	* @arg @ref LL_ADC_INJ_RANK_1
<>	144:ef7eb2e8f9f7	4020	* @arg @ref LL_ADC_INJ_RANK_2
<>	144:ef7eb2e8f9f7	4021	* @arg @ref LL_ADC_INJ_RANK_3
<>	144:ef7eb2e8f9f7	4022	* @arg @ref LL_ADC_INJ_RANK_4
<>	144:ef7eb2e8f9f7	4023	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	4024	* @arg @ref LL_ADC_CHANNEL_0
<>	144:ef7eb2e8f9f7	4025	* @arg @ref LL_ADC_CHANNEL_1 (7)
<>	144:ef7eb2e8f9f7	4026	* @arg @ref LL_ADC_CHANNEL_2 (7)
<>	144:ef7eb2e8f9f7	4027	* @arg @ref LL_ADC_CHANNEL_3 (7)
<>	144:ef7eb2e8f9f7	4028	* @arg @ref LL_ADC_CHANNEL_4 (7)
<>	144:ef7eb2e8f9f7	4029	* @arg @ref LL_ADC_CHANNEL_5 (7)
<>	144:ef7eb2e8f9f7	4030	* @arg @ref LL_ADC_CHANNEL_6
<>	144:ef7eb2e8f9f7	4031	* @arg @ref LL_ADC_CHANNEL_7
<>	144:ef7eb2e8f9f7	4032	* @arg @ref LL_ADC_CHANNEL_8
<>	144:ef7eb2e8f9f7	4033	* @arg @ref LL_ADC_CHANNEL_9
<>	144:ef7eb2e8f9f7	4034	* @arg @ref LL_ADC_CHANNEL_10
<>	144:ef7eb2e8f9f7	4035	* @arg @ref LL_ADC_CHANNEL_11
<>	144:ef7eb2e8f9f7	4036	* @arg @ref LL_ADC_CHANNEL_12
<>	144:ef7eb2e8f9f7	4037	* @arg @ref LL_ADC_CHANNEL_13
<>	144:ef7eb2e8f9f7	4038	* @arg @ref LL_ADC_CHANNEL_14
<>	144:ef7eb2e8f9f7	4039	* @arg @ref LL_ADC_CHANNEL_15
<>	144:ef7eb2e8f9f7	4040	* @arg @ref LL_ADC_CHANNEL_16
<>	144:ef7eb2e8f9f7	4041	* @arg @ref LL_ADC_CHANNEL_17
<>	144:ef7eb2e8f9f7	4042	* @arg @ref LL_ADC_CHANNEL_18
<>	144:ef7eb2e8f9f7	4043	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	144:ef7eb2e8f9f7	4044	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
<>	144:ef7eb2e8f9f7	4045	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
<>	144:ef7eb2e8f9f7	4046	* @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
<>	144:ef7eb2e8f9f7	4047	* @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
<>	144:ef7eb2e8f9f7	4048	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	4049	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	4050	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	4051	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	4052	*
<>	144:ef7eb2e8f9f7	4053	* (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
<>	144:ef7eb2e8f9f7	4054	* (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
<>	144:ef7eb2e8f9f7	4055	* (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
<>	144:ef7eb2e8f9f7	4056	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
<>	144:ef7eb2e8f9f7	4057	* (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
<>	144:ef7eb2e8f9f7	4058	* (6) On STM32L4, parameter available on devices with several ADC instances.\n
<>	144:ef7eb2e8f9f7	4059	* (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
<>	144:ef7eb2e8f9f7	4060	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
<>	144:ef7eb2e8f9f7	4061	* (1, 2, 3, 4) For ADC channel read back from ADC register,
<>	144:ef7eb2e8f9f7	4062	* comparison with internal channel parameter to be done
<>	144:ef7eb2e8f9f7	4063	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
<>	144:ef7eb2e8f9f7	4064	*/
<>	144:ef7eb2e8f9f7	4065	__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
<>	144:ef7eb2e8f9f7	4066	{
<>	144:ef7eb2e8f9f7	4067	return (uint32_t)(READ_BIT(ADCx->JSQR,
<>	144:ef7eb2e8f9f7	4068	ADC_CHANNEL_ID_NUMBER_MASK >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)))
<>	144:ef7eb2e8f9f7	4069	<< (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
<>	144:ef7eb2e8f9f7	4070	);
<>	144:ef7eb2e8f9f7	4071	}
<>	144:ef7eb2e8f9f7	4072
<>	144:ef7eb2e8f9f7	4073	/**
<>	144:ef7eb2e8f9f7	4074	* @brief Set ADC group injected conversion trigger:
<>	144:ef7eb2e8f9f7	4075	* independent or from ADC group regular.
<>	144:ef7eb2e8f9f7	4076	* @note This mode can be used to extend number of data registers
<>	144:ef7eb2e8f9f7	4077	* updated after one ADC conversion trigger and with data
<>	144:ef7eb2e8f9f7	4078	* permanently kept (not erased by successive conversions of scan of
<>	144:ef7eb2e8f9f7	4079	* ADC sequencer ranks), up to 5 data registers:
<>	144:ef7eb2e8f9f7	4080	* 1 data register on ADC group regular, 4 data registers
<>	144:ef7eb2e8f9f7	4081	* on ADC group injected.
<>	144:ef7eb2e8f9f7	4082	* @note If ADC group injected injected trigger source is set to an
<>	144:ef7eb2e8f9f7	4083	* external trigger, this feature must be must be set to
<>	144:ef7eb2e8f9f7	4084	* independent trigger.
<>	144:ef7eb2e8f9f7	4085	* ADC group injected automatic trigger is compliant only with
<>	144:ef7eb2e8f9f7	4086	* group injected trigger source set to SW start, without any
<>	144:ef7eb2e8f9f7	4087	* further action on ADC group injected conversion start or stop:
<>	144:ef7eb2e8f9f7	4088	* in this case, ADC group injected is controlled only
<>	144:ef7eb2e8f9f7	4089	* from ADC group regular.
<>	144:ef7eb2e8f9f7	4090	* @note It is not possible to enable both ADC group injected
<>	144:ef7eb2e8f9f7	4091	* auto-injected mode and sequencer discontinuous mode.
<>	144:ef7eb2e8f9f7	4092	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	4093	* ADC state:
<>	144:ef7eb2e8f9f7	4094	* ADC must be disabled or enabled without conversion on going
<>	144:ef7eb2e8f9f7	4095	* on either groups regular or injected.
<>	144:ef7eb2e8f9f7	4096	* @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
<>	144:ef7eb2e8f9f7	4097	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	4098	* @param TrigAuto This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4099	* @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
<>	144:ef7eb2e8f9f7	4100	* @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
<>	144:ef7eb2e8f9f7	4101	* @retval None
<>	144:ef7eb2e8f9f7	4102	*/
<>	144:ef7eb2e8f9f7	4103	__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
<>	144:ef7eb2e8f9f7	4104	{
<>	144:ef7eb2e8f9f7	4105	MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
<>	144:ef7eb2e8f9f7	4106	}
<>	144:ef7eb2e8f9f7	4107
<>	144:ef7eb2e8f9f7	4108	/**
<>	144:ef7eb2e8f9f7	4109	* @brief Get ADC group injected conversion trigger:
<>	144:ef7eb2e8f9f7	4110	* independent or from ADC group regular.
<>	144:ef7eb2e8f9f7	4111	* @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
<>	144:ef7eb2e8f9f7	4112	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	4113	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	4114	* @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
<>	144:ef7eb2e8f9f7	4115	* @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
<>	144:ef7eb2e8f9f7	4116	*/
<>	144:ef7eb2e8f9f7	4117	__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	4118	{
<>	144:ef7eb2e8f9f7	4119	return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
<>	144:ef7eb2e8f9f7	4120	}
<>	144:ef7eb2e8f9f7	4121
<>	144:ef7eb2e8f9f7	4122	/**
<>	144:ef7eb2e8f9f7	4123	* @brief Set ADC group injected contexts queue mode.
<>	144:ef7eb2e8f9f7	4124	* @note A context is a setting of group injected sequencer:
<>	144:ef7eb2e8f9f7	4125	* - group injected trigger
<>	144:ef7eb2e8f9f7	4126	* - sequencer length
<>	144:ef7eb2e8f9f7	4127	* - sequencer ranks
<>	144:ef7eb2e8f9f7	4128	* If contexts queue is disabled:
<>	144:ef7eb2e8f9f7	4129	* - only 1 sequence can be configured
<>	144:ef7eb2e8f9f7	4130	* and is active perpetually.
<>	144:ef7eb2e8f9f7	4131	* If contexts queue is enabled:
<>	144:ef7eb2e8f9f7	4132	* - up to 2 contexts can be queued
<>	144:ef7eb2e8f9f7	4133	* and are checked in and out as a FIFO stack (first-in, first-out).
<>	144:ef7eb2e8f9f7	4134	* - If a new context is set when queues is full, error is triggered
<>	144:ef7eb2e8f9f7	4135	* by interruption "Injected Queue Overflow".
<>	144:ef7eb2e8f9f7	4136	* - Two behaviors are possible when all contexts have been processed:
<>	144:ef7eb2e8f9f7	4137	* the contexts queue can maintain the last context active perpetually
<>	144:ef7eb2e8f9f7	4138	* or can be empty and injected group triggers are disabled.
<>	144:ef7eb2e8f9f7	4139	* - Triggers can be only external (not internal SW start)
<>	144:ef7eb2e8f9f7	4140	* - Caution: The sequence must be fully configured in one time
<>	144:ef7eb2e8f9f7	4141	* (one write of register JSQR makes a check-in of a new context
<>	144:ef7eb2e8f9f7	4142	* into the queue).
<>	144:ef7eb2e8f9f7	4143	* Therefore functions to set separately injected trigger and
<>	144:ef7eb2e8f9f7	4144	* sequencer channels cannot be used, register JSQR must be set
<>	144:ef7eb2e8f9f7	4145	* using function @ref LL_ADC_INJ_ConfigQueueContext().
<>	144:ef7eb2e8f9f7	4146	* @note This parameter can be modified only when no conversion is on going
<>	144:ef7eb2e8f9f7	4147	* on either groups regular or injected.
<>	144:ef7eb2e8f9f7	4148	* @note A modification of the context mode (bit JQDIS) causes the contexts
<>	144:ef7eb2e8f9f7	4149	* queue to be flushed and the register JSQR is cleared.
<>	144:ef7eb2e8f9f7	4150	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	4151	* ADC state:
<>	144:ef7eb2e8f9f7	4152	* ADC must be disabled or enabled without conversion on going
<>	144:ef7eb2e8f9f7	4153	* on either groups regular or injected.
<>	144:ef7eb2e8f9f7	4154	* @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode\n
<>	144:ef7eb2e8f9f7	4155	* CFGR JQDIS LL_ADC_INJ_SetQueueMode
<>	144:ef7eb2e8f9f7	4156	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	4157	* @param QueueMode This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4158	* @arg @ref LL_ADC_INJ_QUEUE_DISABLE
<>	144:ef7eb2e8f9f7	4159	* @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
<>	144:ef7eb2e8f9f7	4160	* @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
<>	144:ef7eb2e8f9f7	4161	* @retval None
<>	144:ef7eb2e8f9f7	4162	*/
<>	144:ef7eb2e8f9f7	4163	__STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
<>	144:ef7eb2e8f9f7	4164	{
<>	144:ef7eb2e8f9f7	4165	MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM \| ADC_CFGR_JQDIS, QueueMode);
<>	144:ef7eb2e8f9f7	4166	}
<>	144:ef7eb2e8f9f7	4167
<>	144:ef7eb2e8f9f7	4168	/**
<>	144:ef7eb2e8f9f7	4169	* @brief Get ADC group injected context queue mode.
<>	144:ef7eb2e8f9f7	4170	* @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode\n
<>	144:ef7eb2e8f9f7	4171	* CFGR JQDIS LL_ADC_INJ_GetQueueMode
<>	144:ef7eb2e8f9f7	4172	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	4173	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	4174	* @arg @ref LL_ADC_INJ_QUEUE_DISABLE
<>	144:ef7eb2e8f9f7	4175	* @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
<>	144:ef7eb2e8f9f7	4176	* @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
<>	144:ef7eb2e8f9f7	4177	*/
<>	144:ef7eb2e8f9f7	4178	__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	4179	{
<>	144:ef7eb2e8f9f7	4180	return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM \| ADC_CFGR_JQDIS));
<>	144:ef7eb2e8f9f7	4181	}
<>	144:ef7eb2e8f9f7	4182
<>	144:ef7eb2e8f9f7	4183	/**
<>	144:ef7eb2e8f9f7	4184	* @brief Set one context on ADC group injected that will be checked in
<>	144:ef7eb2e8f9f7	4185	* contexts queue.
<>	144:ef7eb2e8f9f7	4186	* @note A context is a setting of group injected sequencer:
<>	144:ef7eb2e8f9f7	4187	* - group injected trigger
<>	144:ef7eb2e8f9f7	4188	* - sequencer length
<>	144:ef7eb2e8f9f7	4189	* - sequencer ranks
<>	144:ef7eb2e8f9f7	4190	* This function is intended to be used when contexts queue is enabled,
<>	144:ef7eb2e8f9f7	4191	* because the sequence must be fully configured in one time
<>	144:ef7eb2e8f9f7	4192	* (functions to set separately injected trigger and sequencer channels
<>	144:ef7eb2e8f9f7	4193	* cannot be used):
<>	144:ef7eb2e8f9f7	4194	* Refer to function @ref LL_ADC_INJ_SetQueueMode().
<>	144:ef7eb2e8f9f7	4195	* @note In the contexts queue, only the active context can be read.
<>	144:ef7eb2e8f9f7	4196	* The parameters of this function can be read using functions:
<>	144:ef7eb2e8f9f7	4197	* @arg @ref LL_ADC_INJ_GetTriggerSource()
<>	144:ef7eb2e8f9f7	4198	* @arg @ref LL_ADC_INJ_GetTriggerEdge()
<>	144:ef7eb2e8f9f7	4199	* @arg @ref LL_ADC_INJ_GetSequencerRanks()
<>	144:ef7eb2e8f9f7	4200	* @note On this STM32 serie, to measure internal channels (VrefInt,
<>	144:ef7eb2e8f9f7	4201	* TempSensor, ...), measurement paths to internal channels must be
<>	144:ef7eb2e8f9f7	4202	* enabled separately.
<>	144:ef7eb2e8f9f7	4203	* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
<>	144:ef7eb2e8f9f7	4204	* @note On this STM32 serie, some fast channels are available: fast analog inputs
<>	144:ef7eb2e8f9f7	4205	* coming from GPIO pads (ADC_IN1..5).
<>	144:ef7eb2e8f9f7	4206	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	4207	* ADC state:
<>	144:ef7eb2e8f9f7	4208	* ADC must not be disabled. Can be enabled with or without conversion
<>	144:ef7eb2e8f9f7	4209	* on going on either groups regular or injected.
<>	144:ef7eb2e8f9f7	4210	* @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n
<>	144:ef7eb2e8f9f7	4211	* JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n
<>	144:ef7eb2e8f9f7	4212	* JSQR JL LL_ADC_INJ_ConfigQueueContext\n
<>	144:ef7eb2e8f9f7	4213	* JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n
<>	144:ef7eb2e8f9f7	4214	* JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n
<>	144:ef7eb2e8f9f7	4215	* JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n
<>	144:ef7eb2e8f9f7	4216	* JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
<>	144:ef7eb2e8f9f7	4217	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	4218	* @param TriggerSource This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4219	* @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
<>	144:ef7eb2e8f9f7	4220	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
<>	144:ef7eb2e8f9f7	4221	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
<>	144:ef7eb2e8f9f7	4222	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
<>	144:ef7eb2e8f9f7	4223	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
<>	144:ef7eb2e8f9f7	4224	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
<>	144:ef7eb2e8f9f7	4225	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
<>	144:ef7eb2e8f9f7	4226	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
<>	144:ef7eb2e8f9f7	4227	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
<>	144:ef7eb2e8f9f7	4228	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
<>	144:ef7eb2e8f9f7	4229	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
<>	144:ef7eb2e8f9f7	4230	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
<>	144:ef7eb2e8f9f7	4231	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
<>	144:ef7eb2e8f9f7	4232	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
<>	144:ef7eb2e8f9f7	4233	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
<>	144:ef7eb2e8f9f7	4234	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
<>	144:ef7eb2e8f9f7	4235	* @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
<>	144:ef7eb2e8f9f7	4236	* @param ExternalTriggerEdge This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4237	* @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
<>	144:ef7eb2e8f9f7	4238	* @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
<>	144:ef7eb2e8f9f7	4239	* @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
<>	144:ef7eb2e8f9f7	4240	*
<>	144:ef7eb2e8f9f7	4241	* Note: This parameter is discarded in case of SW start:
<>	144:ef7eb2e8f9f7	4242	* parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
<>	144:ef7eb2e8f9f7	4243	* @param SequencerNbRanks This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4244	* @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
<>	144:ef7eb2e8f9f7	4245	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
<>	144:ef7eb2e8f9f7	4246	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
<>	144:ef7eb2e8f9f7	4247	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
<>	144:ef7eb2e8f9f7	4248	* @param Rank1_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4249	* @arg @ref LL_ADC_CHANNEL_0
<>	144:ef7eb2e8f9f7	4250	* @arg @ref LL_ADC_CHANNEL_1 (7)
<>	144:ef7eb2e8f9f7	4251	* @arg @ref LL_ADC_CHANNEL_2 (7)
<>	144:ef7eb2e8f9f7	4252	* @arg @ref LL_ADC_CHANNEL_3 (7)
<>	144:ef7eb2e8f9f7	4253	* @arg @ref LL_ADC_CHANNEL_4 (7)
<>	144:ef7eb2e8f9f7	4254	* @arg @ref LL_ADC_CHANNEL_5 (7)
<>	144:ef7eb2e8f9f7	4255	* @arg @ref LL_ADC_CHANNEL_6
<>	144:ef7eb2e8f9f7	4256	* @arg @ref LL_ADC_CHANNEL_7
<>	144:ef7eb2e8f9f7	4257	* @arg @ref LL_ADC_CHANNEL_8
<>	144:ef7eb2e8f9f7	4258	* @arg @ref LL_ADC_CHANNEL_9
<>	144:ef7eb2e8f9f7	4259	* @arg @ref LL_ADC_CHANNEL_10
<>	144:ef7eb2e8f9f7	4260	* @arg @ref LL_ADC_CHANNEL_11
<>	144:ef7eb2e8f9f7	4261	* @arg @ref LL_ADC_CHANNEL_12
<>	144:ef7eb2e8f9f7	4262	* @arg @ref LL_ADC_CHANNEL_13
<>	144:ef7eb2e8f9f7	4263	* @arg @ref LL_ADC_CHANNEL_14
<>	144:ef7eb2e8f9f7	4264	* @arg @ref LL_ADC_CHANNEL_15
<>	144:ef7eb2e8f9f7	4265	* @arg @ref LL_ADC_CHANNEL_16
<>	144:ef7eb2e8f9f7	4266	* @arg @ref LL_ADC_CHANNEL_17
<>	144:ef7eb2e8f9f7	4267	* @arg @ref LL_ADC_CHANNEL_18
<>	144:ef7eb2e8f9f7	4268	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	144:ef7eb2e8f9f7	4269	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
<>	144:ef7eb2e8f9f7	4270	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
<>	144:ef7eb2e8f9f7	4271	* @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
<>	144:ef7eb2e8f9f7	4272	* @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
<>	144:ef7eb2e8f9f7	4273	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	4274	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	4275	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	4276	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	4277	*
<>	144:ef7eb2e8f9f7	4278	* (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
<>	144:ef7eb2e8f9f7	4279	* (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
<>	144:ef7eb2e8f9f7	4280	* (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
<>	144:ef7eb2e8f9f7	4281	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
<>	144:ef7eb2e8f9f7	4282	* (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
<>	144:ef7eb2e8f9f7	4283	* (6) On STM32L4, parameter available on devices with several ADC instances.\n
<>	144:ef7eb2e8f9f7	4284	* (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
<>	144:ef7eb2e8f9f7	4285	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
<>	144:ef7eb2e8f9f7	4286	* @param Rank2_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4287	* @arg @ref LL_ADC_CHANNEL_0
<>	144:ef7eb2e8f9f7	4288	* @arg @ref LL_ADC_CHANNEL_1 (7)
<>	144:ef7eb2e8f9f7	4289	* @arg @ref LL_ADC_CHANNEL_2 (7)
<>	144:ef7eb2e8f9f7	4290	* @arg @ref LL_ADC_CHANNEL_3 (7)
<>	144:ef7eb2e8f9f7	4291	* @arg @ref LL_ADC_CHANNEL_4 (7)
<>	144:ef7eb2e8f9f7	4292	* @arg @ref LL_ADC_CHANNEL_5 (7)
<>	144:ef7eb2e8f9f7	4293	* @arg @ref LL_ADC_CHANNEL_6
<>	144:ef7eb2e8f9f7	4294	* @arg @ref LL_ADC_CHANNEL_7
<>	144:ef7eb2e8f9f7	4295	* @arg @ref LL_ADC_CHANNEL_8
<>	144:ef7eb2e8f9f7	4296	* @arg @ref LL_ADC_CHANNEL_9
<>	144:ef7eb2e8f9f7	4297	* @arg @ref LL_ADC_CHANNEL_10
<>	144:ef7eb2e8f9f7	4298	* @arg @ref LL_ADC_CHANNEL_11
<>	144:ef7eb2e8f9f7	4299	* @arg @ref LL_ADC_CHANNEL_12
<>	144:ef7eb2e8f9f7	4300	* @arg @ref LL_ADC_CHANNEL_13
<>	144:ef7eb2e8f9f7	4301	* @arg @ref LL_ADC_CHANNEL_14
<>	144:ef7eb2e8f9f7	4302	* @arg @ref LL_ADC_CHANNEL_15
<>	144:ef7eb2e8f9f7	4303	* @arg @ref LL_ADC_CHANNEL_16
<>	144:ef7eb2e8f9f7	4304	* @arg @ref LL_ADC_CHANNEL_17
<>	144:ef7eb2e8f9f7	4305	* @arg @ref LL_ADC_CHANNEL_18
<>	144:ef7eb2e8f9f7	4306	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	144:ef7eb2e8f9f7	4307	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
<>	144:ef7eb2e8f9f7	4308	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
<>	144:ef7eb2e8f9f7	4309	* @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
<>	144:ef7eb2e8f9f7	4310	* @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
<>	144:ef7eb2e8f9f7	4311	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	4312	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	4313	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	4314	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	4315	*
<>	144:ef7eb2e8f9f7	4316	* (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
<>	144:ef7eb2e8f9f7	4317	* (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
<>	144:ef7eb2e8f9f7	4318	* (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
<>	144:ef7eb2e8f9f7	4319	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
<>	144:ef7eb2e8f9f7	4320	* (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
<>	144:ef7eb2e8f9f7	4321	* (6) On STM32L4, parameter available on devices with several ADC instances.\n
<>	144:ef7eb2e8f9f7	4322	* (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
<>	144:ef7eb2e8f9f7	4323	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
<>	144:ef7eb2e8f9f7	4324	* @param Rank3_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4325	* @arg @ref LL_ADC_CHANNEL_0
<>	144:ef7eb2e8f9f7	4326	* @arg @ref LL_ADC_CHANNEL_1 (7)
<>	144:ef7eb2e8f9f7	4327	* @arg @ref LL_ADC_CHANNEL_2 (7)
<>	144:ef7eb2e8f9f7	4328	* @arg @ref LL_ADC_CHANNEL_3 (7)
<>	144:ef7eb2e8f9f7	4329	* @arg @ref LL_ADC_CHANNEL_4 (7)
<>	144:ef7eb2e8f9f7	4330	* @arg @ref LL_ADC_CHANNEL_5 (7)
<>	144:ef7eb2e8f9f7	4331	* @arg @ref LL_ADC_CHANNEL_6
<>	144:ef7eb2e8f9f7	4332	* @arg @ref LL_ADC_CHANNEL_7
<>	144:ef7eb2e8f9f7	4333	* @arg @ref LL_ADC_CHANNEL_8
<>	144:ef7eb2e8f9f7	4334	* @arg @ref LL_ADC_CHANNEL_9
<>	144:ef7eb2e8f9f7	4335	* @arg @ref LL_ADC_CHANNEL_10
<>	144:ef7eb2e8f9f7	4336	* @arg @ref LL_ADC_CHANNEL_11
<>	144:ef7eb2e8f9f7	4337	* @arg @ref LL_ADC_CHANNEL_12
<>	144:ef7eb2e8f9f7	4338	* @arg @ref LL_ADC_CHANNEL_13
<>	144:ef7eb2e8f9f7	4339	* @arg @ref LL_ADC_CHANNEL_14
<>	144:ef7eb2e8f9f7	4340	* @arg @ref LL_ADC_CHANNEL_15
<>	144:ef7eb2e8f9f7	4341	* @arg @ref LL_ADC_CHANNEL_16
<>	144:ef7eb2e8f9f7	4342	* @arg @ref LL_ADC_CHANNEL_17
<>	144:ef7eb2e8f9f7	4343	* @arg @ref LL_ADC_CHANNEL_18
<>	144:ef7eb2e8f9f7	4344	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	144:ef7eb2e8f9f7	4345	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
<>	144:ef7eb2e8f9f7	4346	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
<>	144:ef7eb2e8f9f7	4347	* @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
<>	144:ef7eb2e8f9f7	4348	* @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
<>	144:ef7eb2e8f9f7	4349	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	4350	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	4351	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	4352	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	4353	*
<>	144:ef7eb2e8f9f7	4354	* (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
<>	144:ef7eb2e8f9f7	4355	* (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
<>	144:ef7eb2e8f9f7	4356	* (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
<>	144:ef7eb2e8f9f7	4357	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
<>	144:ef7eb2e8f9f7	4358	* (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
<>	144:ef7eb2e8f9f7	4359	* (6) On STM32L4, parameter available on devices with several ADC instances.\n
<>	144:ef7eb2e8f9f7	4360	* (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
<>	144:ef7eb2e8f9f7	4361	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
<>	144:ef7eb2e8f9f7	4362	* @param Rank4_Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4363	* @arg @ref LL_ADC_CHANNEL_0
<>	144:ef7eb2e8f9f7	4364	* @arg @ref LL_ADC_CHANNEL_1 (7)
<>	144:ef7eb2e8f9f7	4365	* @arg @ref LL_ADC_CHANNEL_2 (7)
<>	144:ef7eb2e8f9f7	4366	* @arg @ref LL_ADC_CHANNEL_3 (7)
<>	144:ef7eb2e8f9f7	4367	* @arg @ref LL_ADC_CHANNEL_4 (7)
<>	144:ef7eb2e8f9f7	4368	* @arg @ref LL_ADC_CHANNEL_5 (7)
<>	144:ef7eb2e8f9f7	4369	* @arg @ref LL_ADC_CHANNEL_6
<>	144:ef7eb2e8f9f7	4370	* @arg @ref LL_ADC_CHANNEL_7
<>	144:ef7eb2e8f9f7	4371	* @arg @ref LL_ADC_CHANNEL_8
<>	144:ef7eb2e8f9f7	4372	* @arg @ref LL_ADC_CHANNEL_9
<>	144:ef7eb2e8f9f7	4373	* @arg @ref LL_ADC_CHANNEL_10
<>	144:ef7eb2e8f9f7	4374	* @arg @ref LL_ADC_CHANNEL_11
<>	144:ef7eb2e8f9f7	4375	* @arg @ref LL_ADC_CHANNEL_12
<>	144:ef7eb2e8f9f7	4376	* @arg @ref LL_ADC_CHANNEL_13
<>	144:ef7eb2e8f9f7	4377	* @arg @ref LL_ADC_CHANNEL_14
<>	144:ef7eb2e8f9f7	4378	* @arg @ref LL_ADC_CHANNEL_15
<>	144:ef7eb2e8f9f7	4379	* @arg @ref LL_ADC_CHANNEL_16
<>	144:ef7eb2e8f9f7	4380	* @arg @ref LL_ADC_CHANNEL_17
<>	144:ef7eb2e8f9f7	4381	* @arg @ref LL_ADC_CHANNEL_18
<>	144:ef7eb2e8f9f7	4382	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	144:ef7eb2e8f9f7	4383	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
<>	144:ef7eb2e8f9f7	4384	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
<>	144:ef7eb2e8f9f7	4385	* @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
<>	144:ef7eb2e8f9f7	4386	* @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
<>	144:ef7eb2e8f9f7	4387	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	4388	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	4389	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	4390	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	4391	*
<>	144:ef7eb2e8f9f7	4392	* (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
<>	144:ef7eb2e8f9f7	4393	* (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
<>	144:ef7eb2e8f9f7	4394	* (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
<>	144:ef7eb2e8f9f7	4395	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
<>	144:ef7eb2e8f9f7	4396	* (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
<>	144:ef7eb2e8f9f7	4397	* (6) On STM32L4, parameter available on devices with several ADC instances.\n
<>	144:ef7eb2e8f9f7	4398	* (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
<>	144:ef7eb2e8f9f7	4399	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
<>	144:ef7eb2e8f9f7	4400	* @retval None
<>	144:ef7eb2e8f9f7	4401	*/
<>	144:ef7eb2e8f9f7	4402	__STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
<>	144:ef7eb2e8f9f7	4403	uint32_t TriggerSource,
<>	144:ef7eb2e8f9f7	4404	uint32_t ExternalTriggerEdge,
<>	144:ef7eb2e8f9f7	4405	uint32_t SequencerNbRanks,
<>	144:ef7eb2e8f9f7	4406	uint32_t Rank1_Channel,
<>	144:ef7eb2e8f9f7	4407	uint32_t Rank2_Channel,
<>	144:ef7eb2e8f9f7	4408	uint32_t Rank3_Channel,
<>	144:ef7eb2e8f9f7	4409	uint32_t Rank4_Channel)
<>	144:ef7eb2e8f9f7	4410	{
<>	144:ef7eb2e8f9f7	4411	/* Set bits with content of parameter "Rankx_Channel" with bits position */
<>	144:ef7eb2e8f9f7	4412	/* in register depending on literal "LL_ADC_INJ_RANK_x". */
<>	144:ef7eb2e8f9f7	4413	/* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
<>	144:ef7eb2e8f9f7	4414	/* because containing other bits reserved for other purpose. */
<>	144:ef7eb2e8f9f7	4415	/* If parameter "TriggerSource" is set to SW start, then parameter */
<>	144:ef7eb2e8f9f7	4416	/* "ExternalTriggerEdge" is discarded. */
<>	144:ef7eb2e8f9f7	4417	MODIFY_REG(ADCx->JSQR ,
<>	144:ef7eb2e8f9f7	4418	ADC_JSQR_JEXTSEL \|
<>	144:ef7eb2e8f9f7	4419	ADC_JSQR_JEXTEN \|
<>	144:ef7eb2e8f9f7	4420	ADC_JSQR_JSQ4 \|
<>	144:ef7eb2e8f9f7	4421	ADC_JSQR_JSQ3 \|
<>	144:ef7eb2e8f9f7	4422	ADC_JSQR_JSQ2 \|
<>	144:ef7eb2e8f9f7	4423	ADC_JSQR_JSQ1 \|
<>	144:ef7eb2e8f9f7	4424	ADC_JSQR_JL ,
<>	144:ef7eb2e8f9f7	4425	TriggerSource \|
<>	144:ef7eb2e8f9f7	4426	(ExternalTriggerEdge * ((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE))) \|
<>	144:ef7eb2e8f9f7	4427	((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK))) \|
<>	144:ef7eb2e8f9f7	4428	((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK))) \|
<>	144:ef7eb2e8f9f7	4429	((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK))) \|
<>	144:ef7eb2e8f9f7	4430	((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK))) \|
<>	144:ef7eb2e8f9f7	4431	SequencerNbRanks
<>	144:ef7eb2e8f9f7	4432	);
<>	144:ef7eb2e8f9f7	4433	}
<>	144:ef7eb2e8f9f7	4434
<>	144:ef7eb2e8f9f7	4435	/**
<>	144:ef7eb2e8f9f7	4436	* @}
<>	144:ef7eb2e8f9f7	4437	*/
<>	144:ef7eb2e8f9f7	4438
<>	144:ef7eb2e8f9f7	4439	/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
<>	144:ef7eb2e8f9f7	4440	* @{
<>	144:ef7eb2e8f9f7	4441	*/
<>	144:ef7eb2e8f9f7	4442
<>	144:ef7eb2e8f9f7	4443	/**
<>	144:ef7eb2e8f9f7	4444	* @brief Set sampling time of the selected ADC channel
<>	144:ef7eb2e8f9f7	4445	* Unit: ADC clock cycles.
<>	144:ef7eb2e8f9f7	4446	* @note On this device, sampling time is on channel scope: independently
<>	144:ef7eb2e8f9f7	4447	* of channel mapped on ADC group regular or injected.
<>	144:ef7eb2e8f9f7	4448	* @note In case of internal channel (VrefInt, TempSensor, ...) to be
<>	144:ef7eb2e8f9f7	4449	* converted:
<>	144:ef7eb2e8f9f7	4450	* sampling time constraints must be respected (sampling time can be
<>	144:ef7eb2e8f9f7	4451	* adjusted in function of ADC clock frequency and sampling time
<>	144:ef7eb2e8f9f7	4452	* setting).
<>	144:ef7eb2e8f9f7	4453	* Refer to device datasheet for timings values (parameters TS_vrefint,
<>	144:ef7eb2e8f9f7	4454	* TS_temp, ...).
<>	144:ef7eb2e8f9f7	4455	* @note Conversion time is the addition of sampling time and processing time.
<>	144:ef7eb2e8f9f7	4456	* On this STM32 serie, ADC processing time is:
<>	144:ef7eb2e8f9f7	4457	* - 12.5 ADC clock cycles at ADC resolution 12 bits
<>	144:ef7eb2e8f9f7	4458	* - 10.5 ADC clock cycles at ADC resolution 10 bits
<>	144:ef7eb2e8f9f7	4459	* - 8.5 ADC clock cycles at ADC resolution 8 bits
<>	144:ef7eb2e8f9f7	4460	* - 6.5 ADC clock cycles at ADC resolution 6 bits
<>	144:ef7eb2e8f9f7	4461	* @note In case of ADC conversion of internal channel (VrefInt,
<>	144:ef7eb2e8f9f7	4462	* temperature sensor, ...), a sampling time minimum value
<>	144:ef7eb2e8f9f7	4463	* is required.
<>	144:ef7eb2e8f9f7	4464	* Refer to device datasheet.
<>	144:ef7eb2e8f9f7	4465	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	4466	* ADC state:
<>	144:ef7eb2e8f9f7	4467	* ADC must be disabled or enabled without conversion on going
<>	144:ef7eb2e8f9f7	4468	* on either groups regular or injected.
<>	144:ef7eb2e8f9f7	4469	* @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4470	* SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4471	* SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4472	* SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4473	* SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4474	* SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4475	* SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4476	* SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4477	* SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4478	* SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4479	* SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4480	* SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4481	* SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4482	* SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4483	* SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4484	* SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4485	* SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4486	* SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4487	* SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
<>	144:ef7eb2e8f9f7	4488	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	4489	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4490	* @arg @ref LL_ADC_CHANNEL_0
<>	144:ef7eb2e8f9f7	4491	* @arg @ref LL_ADC_CHANNEL_1 (7)
<>	144:ef7eb2e8f9f7	4492	* @arg @ref LL_ADC_CHANNEL_2 (7)
<>	144:ef7eb2e8f9f7	4493	* @arg @ref LL_ADC_CHANNEL_3 (7)
<>	144:ef7eb2e8f9f7	4494	* @arg @ref LL_ADC_CHANNEL_4 (7)
<>	144:ef7eb2e8f9f7	4495	* @arg @ref LL_ADC_CHANNEL_5 (7)
<>	144:ef7eb2e8f9f7	4496	* @arg @ref LL_ADC_CHANNEL_6
<>	144:ef7eb2e8f9f7	4497	* @arg @ref LL_ADC_CHANNEL_7
<>	144:ef7eb2e8f9f7	4498	* @arg @ref LL_ADC_CHANNEL_8
<>	144:ef7eb2e8f9f7	4499	* @arg @ref LL_ADC_CHANNEL_9
<>	144:ef7eb2e8f9f7	4500	* @arg @ref LL_ADC_CHANNEL_10
<>	144:ef7eb2e8f9f7	4501	* @arg @ref LL_ADC_CHANNEL_11
<>	144:ef7eb2e8f9f7	4502	* @arg @ref LL_ADC_CHANNEL_12
<>	144:ef7eb2e8f9f7	4503	* @arg @ref LL_ADC_CHANNEL_13
<>	144:ef7eb2e8f9f7	4504	* @arg @ref LL_ADC_CHANNEL_14
<>	144:ef7eb2e8f9f7	4505	* @arg @ref LL_ADC_CHANNEL_15
<>	144:ef7eb2e8f9f7	4506	* @arg @ref LL_ADC_CHANNEL_16
<>	144:ef7eb2e8f9f7	4507	* @arg @ref LL_ADC_CHANNEL_17
<>	144:ef7eb2e8f9f7	4508	* @arg @ref LL_ADC_CHANNEL_18
<>	144:ef7eb2e8f9f7	4509	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	144:ef7eb2e8f9f7	4510	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
<>	144:ef7eb2e8f9f7	4511	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
<>	144:ef7eb2e8f9f7	4512	* @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
<>	144:ef7eb2e8f9f7	4513	* @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
<>	144:ef7eb2e8f9f7	4514	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	4515	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	4516	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	4517	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	4518	*
<>	144:ef7eb2e8f9f7	4519	* (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
<>	144:ef7eb2e8f9f7	4520	* (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
<>	144:ef7eb2e8f9f7	4521	* (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
<>	144:ef7eb2e8f9f7	4522	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
<>	144:ef7eb2e8f9f7	4523	* (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
<>	144:ef7eb2e8f9f7	4524	* (6) On STM32L4, parameter available on devices with several ADC instances.\n
<>	144:ef7eb2e8f9f7	4525	* (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
<>	144:ef7eb2e8f9f7	4526	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
<>	144:ef7eb2e8f9f7	4527	* @param SamplingTime This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4528	* @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
<>	144:ef7eb2e8f9f7	4529	* @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
<>	144:ef7eb2e8f9f7	4530	* @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
<>	144:ef7eb2e8f9f7	4531	* @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
<>	144:ef7eb2e8f9f7	4532	* @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
<>	144:ef7eb2e8f9f7	4533	* @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
<>	144:ef7eb2e8f9f7	4534	* @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
<>	144:ef7eb2e8f9f7	4535	* @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
<>	144:ef7eb2e8f9f7	4536	* @retval None
<>	144:ef7eb2e8f9f7	4537	*/
<>	144:ef7eb2e8f9f7	4538	__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
<>	144:ef7eb2e8f9f7	4539	{
<>	144:ef7eb2e8f9f7	4540	/* Set bits with content of parameter "SamplingTime" with bits position */
<>	144:ef7eb2e8f9f7	4541	/* in register and register position depending on parameter "Channel". */
<>	144:ef7eb2e8f9f7	4542	/* Parameter "Channel" is used with masks because containing */
<>	144:ef7eb2e8f9f7	4543	/* other bits reserved for other purpose. */
<>	144:ef7eb2e8f9f7	4544	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
<>	144:ef7eb2e8f9f7	4545
<>	144:ef7eb2e8f9f7	4546	MODIFY_REG(*preg,
<>	144:ef7eb2e8f9f7	4547	ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
<>	144:ef7eb2e8f9f7	4548	SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
<>	144:ef7eb2e8f9f7	4549	}
<>	144:ef7eb2e8f9f7	4550
<>	144:ef7eb2e8f9f7	4551	/**
<>	144:ef7eb2e8f9f7	4552	* @brief Get sampling time of the selected ADC channel
<>	144:ef7eb2e8f9f7	4553	* Unit: ADC clock cycles.
<>	144:ef7eb2e8f9f7	4554	* @note On this device, sampling time is on channel scope: independently
<>	144:ef7eb2e8f9f7	4555	* of channel mapped on ADC group regular or injected.
<>	144:ef7eb2e8f9f7	4556	* @note Conversion time is the addition of sampling time and processing time.
<>	144:ef7eb2e8f9f7	4557	* On this STM32 serie, ADC processing time is:
<>	144:ef7eb2e8f9f7	4558	* - 12.5 ADC clock cycles at ADC resolution 12 bits
<>	144:ef7eb2e8f9f7	4559	* - 10.5 ADC clock cycles at ADC resolution 10 bits
<>	144:ef7eb2e8f9f7	4560	* - 8.5 ADC clock cycles at ADC resolution 8 bits
<>	144:ef7eb2e8f9f7	4561	* - 6.5 ADC clock cycles at ADC resolution 6 bits
<>	144:ef7eb2e8f9f7	4562	* @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4563	* SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4564	* SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4565	* SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4566	* SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4567	* SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4568	* SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4569	* SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4570	* SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4571	* SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4572	* SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4573	* SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4574	* SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4575	* SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4576	* SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4577	* SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4578	* SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4579	* SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
<>	144:ef7eb2e8f9f7	4580	* SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
<>	144:ef7eb2e8f9f7	4581	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	4582	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4583	* @arg @ref LL_ADC_CHANNEL_0
<>	144:ef7eb2e8f9f7	4584	* @arg @ref LL_ADC_CHANNEL_1 (7)
<>	144:ef7eb2e8f9f7	4585	* @arg @ref LL_ADC_CHANNEL_2 (7)
<>	144:ef7eb2e8f9f7	4586	* @arg @ref LL_ADC_CHANNEL_3 (7)
<>	144:ef7eb2e8f9f7	4587	* @arg @ref LL_ADC_CHANNEL_4 (7)
<>	144:ef7eb2e8f9f7	4588	* @arg @ref LL_ADC_CHANNEL_5 (7)
<>	144:ef7eb2e8f9f7	4589	* @arg @ref LL_ADC_CHANNEL_6
<>	144:ef7eb2e8f9f7	4590	* @arg @ref LL_ADC_CHANNEL_7
<>	144:ef7eb2e8f9f7	4591	* @arg @ref LL_ADC_CHANNEL_8
<>	144:ef7eb2e8f9f7	4592	* @arg @ref LL_ADC_CHANNEL_9
<>	144:ef7eb2e8f9f7	4593	* @arg @ref LL_ADC_CHANNEL_10
<>	144:ef7eb2e8f9f7	4594	* @arg @ref LL_ADC_CHANNEL_11
<>	144:ef7eb2e8f9f7	4595	* @arg @ref LL_ADC_CHANNEL_12
<>	144:ef7eb2e8f9f7	4596	* @arg @ref LL_ADC_CHANNEL_13
<>	144:ef7eb2e8f9f7	4597	* @arg @ref LL_ADC_CHANNEL_14
<>	144:ef7eb2e8f9f7	4598	* @arg @ref LL_ADC_CHANNEL_15
<>	144:ef7eb2e8f9f7	4599	* @arg @ref LL_ADC_CHANNEL_16
<>	144:ef7eb2e8f9f7	4600	* @arg @ref LL_ADC_CHANNEL_17
<>	144:ef7eb2e8f9f7	4601	* @arg @ref LL_ADC_CHANNEL_18
<>	144:ef7eb2e8f9f7	4602	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	144:ef7eb2e8f9f7	4603	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
<>	144:ef7eb2e8f9f7	4604	* @arg @ref LL_ADC_CHANNEL_VBAT (4)
<>	144:ef7eb2e8f9f7	4605	* @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
<>	144:ef7eb2e8f9f7	4606	* @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
<>	144:ef7eb2e8f9f7	4607	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	4608	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
<>	144:ef7eb2e8f9f7	4609	* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	4610	* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
<>	144:ef7eb2e8f9f7	4611	*
<>	144:ef7eb2e8f9f7	4612	* (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
<>	144:ef7eb2e8f9f7	4613	* (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
<>	144:ef7eb2e8f9f7	4614	* (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
<>	144:ef7eb2e8f9f7	4615	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
<>	144:ef7eb2e8f9f7	4616	* (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
<>	144:ef7eb2e8f9f7	4617	* (6) On STM32L4, parameter available on devices with several ADC instances.\n
<>	144:ef7eb2e8f9f7	4618	* (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
<>	144:ef7eb2e8f9f7	4619	* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
<>	144:ef7eb2e8f9f7	4620	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	4621	* @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
<>	144:ef7eb2e8f9f7	4622	* @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
<>	144:ef7eb2e8f9f7	4623	* @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
<>	144:ef7eb2e8f9f7	4624	* @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
<>	144:ef7eb2e8f9f7	4625	* @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
<>	144:ef7eb2e8f9f7	4626	* @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
<>	144:ef7eb2e8f9f7	4627	* @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
<>	144:ef7eb2e8f9f7	4628	* @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
<>	144:ef7eb2e8f9f7	4629	*/
<>	144:ef7eb2e8f9f7	4630	__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
<>	144:ef7eb2e8f9f7	4631	{
<>	144:ef7eb2e8f9f7	4632	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
<>	144:ef7eb2e8f9f7	4633
<>	144:ef7eb2e8f9f7	4634	return (uint32_t)(READ_BIT(*preg,
<>	144:ef7eb2e8f9f7	4635	ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
<>	144:ef7eb2e8f9f7	4636	>> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
<>	144:ef7eb2e8f9f7	4637	);
<>	144:ef7eb2e8f9f7	4638	}
<>	144:ef7eb2e8f9f7	4639
<>	144:ef7eb2e8f9f7	4640	/**
<>	144:ef7eb2e8f9f7	4641	* @brief Set mode single-ended or differential input of the selected
<>	144:ef7eb2e8f9f7	4642	* ADC channel.
<>	144:ef7eb2e8f9f7	4643	* @note Channel ending is on channel scope: independently of channel mapped
<>	144:ef7eb2e8f9f7	4644	* on ADC group regular or injected.
<>	144:ef7eb2e8f9f7	4645	* In differential mode: Differential measurement is carried out
<>	144:ef7eb2e8f9f7	4646	* between the selected channel 'i' (positive input) and
<>	144:ef7eb2e8f9f7	4647	* channel 'i+1' (negative input). Only channel 'i' has to be
<>	144:ef7eb2e8f9f7	4648	* configured, channel 'i+1' is configured automatically.
<>	144:ef7eb2e8f9f7	4649	* @note Refer to Reference Manual to ensure the selected channel is
<>	144:ef7eb2e8f9f7	4650	* available in differential mode.
<>	144:ef7eb2e8f9f7	4651	* For example, internal channels (VrefInt, TempSensor, ...) are
<>	144:ef7eb2e8f9f7	4652	* not available in differential mode.
<>	144:ef7eb2e8f9f7	4653	* @note When configuring a channel 'i' in differential mode,
<>	144:ef7eb2e8f9f7	4654	* the channel 'i+1' is not usable separately.
<>	144:ef7eb2e8f9f7	4655	* @note On STM32L4, channels 15, 16, 17, 18 of ADC1, ADC2, ADC3 (if available)
<>	144:ef7eb2e8f9f7	4656	* are internally fixed to single-ended inputs configuration.
<>	144:ef7eb2e8f9f7	4657	* @note For ADC channels configured in differential mode, both inputs
<>	144:ef7eb2e8f9f7	4658	* should be biased at (Vref+)/2 +/-200mV.
<>	144:ef7eb2e8f9f7	4659	* (Vref+ is the analog voltage reference)
<>	144:ef7eb2e8f9f7	4660	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	4661	* ADC state:
<>	144:ef7eb2e8f9f7	4662	* ADC must be ADC disabled.
<>	144:ef7eb2e8f9f7	4663	* @note One or several values can be selected.
<>	144:ef7eb2e8f9f7	4664	* Example: (LL_ADC_CHANNEL_4 \| LL_ADC_CHANNEL_12 \| ...)
<>	144:ef7eb2e8f9f7	4665	* @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSamplingTime
<>	144:ef7eb2e8f9f7	4666	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	4667	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4668	* @arg @ref LL_ADC_CHANNEL_1
<>	144:ef7eb2e8f9f7	4669	* @arg @ref LL_ADC_CHANNEL_2
<>	144:ef7eb2e8f9f7	4670	* @arg @ref LL_ADC_CHANNEL_3
<>	144:ef7eb2e8f9f7	4671	* @arg @ref LL_ADC_CHANNEL_4
<>	144:ef7eb2e8f9f7	4672	* @arg @ref LL_ADC_CHANNEL_5
<>	144:ef7eb2e8f9f7	4673	* @arg @ref LL_ADC_CHANNEL_6
<>	144:ef7eb2e8f9f7	4674	* @arg @ref LL_ADC_CHANNEL_7
<>	144:ef7eb2e8f9f7	4675	* @arg @ref LL_ADC_CHANNEL_8
<>	144:ef7eb2e8f9f7	4676	* @arg @ref LL_ADC_CHANNEL_9
<>	144:ef7eb2e8f9f7	4677	* @arg @ref LL_ADC_CHANNEL_10
<>	144:ef7eb2e8f9f7	4678	* @arg @ref LL_ADC_CHANNEL_11
<>	144:ef7eb2e8f9f7	4679	* @arg @ref LL_ADC_CHANNEL_12
<>	144:ef7eb2e8f9f7	4680	* @arg @ref LL_ADC_CHANNEL_13
<>	144:ef7eb2e8f9f7	4681	* @arg @ref LL_ADC_CHANNEL_14
<>	144:ef7eb2e8f9f7	4682	* @param SingleDiff This parameter can be a combination of the following values:
<>	144:ef7eb2e8f9f7	4683	* @arg @ref LL_ADC_SINGLE_ENDED
<>	144:ef7eb2e8f9f7	4684	* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
<>	144:ef7eb2e8f9f7	4685	* @retval None
<>	144:ef7eb2e8f9f7	4686	*/
<>	144:ef7eb2e8f9f7	4687	__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
<>	144:ef7eb2e8f9f7	4688	{
<>	144:ef7eb2e8f9f7	4689	/* Bits of channels in single or differential mode are set only for */
<>	144:ef7eb2e8f9f7	4690	/* differential mode (for single mode, mask of bits allowed to be set is */
<>	144:ef7eb2e8f9f7	4691	/* shifted out of range of bits of channels in single or differential mode. */
<>	144:ef7eb2e8f9f7	4692	MODIFY_REG(ADCx->DIFSEL,
<>	144:ef7eb2e8f9f7	4693	Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
<>	144:ef7eb2e8f9f7	4694	(Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL << (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
<>	144:ef7eb2e8f9f7	4695	}
<>	144:ef7eb2e8f9f7	4696
<>	144:ef7eb2e8f9f7	4697	/**
<>	144:ef7eb2e8f9f7	4698	* @brief Get mode single-ended or differential input of the selected
<>	144:ef7eb2e8f9f7	4699	* ADC channel.
<>	144:ef7eb2e8f9f7	4700	* @note When configuring a channel 'i' in differential mode,
<>	144:ef7eb2e8f9f7	4701	* the channel 'i+1' is not usable separately.
<>	144:ef7eb2e8f9f7	4702	* Therefore, to ensure a channel is configured in single-ended mode,
<>	144:ef7eb2e8f9f7	4703	* the configuration of channel itself and the channel 'i-1' must be
<>	144:ef7eb2e8f9f7	4704	* read back (to ensure that the selected channel channel has not been
<>	144:ef7eb2e8f9f7	4705	* configured in differential mode by the previous channel).
<>	144:ef7eb2e8f9f7	4706	* @note Refer to Reference Manual to ensure the selected channel is
<>	144:ef7eb2e8f9f7	4707	* available in differential mode.
<>	144:ef7eb2e8f9f7	4708	* For example, internal channels (VrefInt, TempSensor, ...) are
<>	144:ef7eb2e8f9f7	4709	* not available in differential mode.
<>	144:ef7eb2e8f9f7	4710	* @note When configuring a channel 'i' in differential mode,
<>	144:ef7eb2e8f9f7	4711	* the channel 'i+1' is not usable separately.
<>	144:ef7eb2e8f9f7	4712	* @note On STM32L4, channels 15, 16, 17, 18 of ADC1, ADC2, ADC3 (if available)
<>	144:ef7eb2e8f9f7	4713	* are internally fixed to single-ended inputs configuration.
<>	144:ef7eb2e8f9f7	4714	* @note One or several values can be selected. In this case, the value
<>	144:ef7eb2e8f9f7	4715	* returned is null if all channels are in single ended-mode.
<>	144:ef7eb2e8f9f7	4716	* Example: (LL_ADC_CHANNEL_4 \| LL_ADC_CHANNEL_12 \| ...)
<>	144:ef7eb2e8f9f7	4717	* @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSamplingTime
<>	144:ef7eb2e8f9f7	4718	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	4719	* @param Channel This parameter can be a combination of the following values:
<>	144:ef7eb2e8f9f7	4720	* @arg @ref LL_ADC_CHANNEL_0
<>	144:ef7eb2e8f9f7	4721	* @arg @ref LL_ADC_CHANNEL_1
<>	144:ef7eb2e8f9f7	4722	* @arg @ref LL_ADC_CHANNEL_2
<>	144:ef7eb2e8f9f7	4723	* @arg @ref LL_ADC_CHANNEL_3
<>	144:ef7eb2e8f9f7	4724	* @arg @ref LL_ADC_CHANNEL_4
<>	144:ef7eb2e8f9f7	4725	* @arg @ref LL_ADC_CHANNEL_5
<>	144:ef7eb2e8f9f7	4726	* @arg @ref LL_ADC_CHANNEL_6
<>	144:ef7eb2e8f9f7	4727	* @arg @ref LL_ADC_CHANNEL_7
<>	144:ef7eb2e8f9f7	4728	* @arg @ref LL_ADC_CHANNEL_8
<>	144:ef7eb2e8f9f7	4729	* @arg @ref LL_ADC_CHANNEL_9
<>	144:ef7eb2e8f9f7	4730	* @arg @ref LL_ADC_CHANNEL_10
<>	144:ef7eb2e8f9f7	4731	* @arg @ref LL_ADC_CHANNEL_11
<>	144:ef7eb2e8f9f7	4732	* @arg @ref LL_ADC_CHANNEL_12
<>	144:ef7eb2e8f9f7	4733	* @arg @ref LL_ADC_CHANNEL_13
<>	144:ef7eb2e8f9f7	4734	* @arg @ref LL_ADC_CHANNEL_14
<>	144:ef7eb2e8f9f7	4735	* @retval 0: channel in single-ended mode, else: channel in differential mode
<>	144:ef7eb2e8f9f7	4736	*/
<>	144:ef7eb2e8f9f7	4737	__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
<>	144:ef7eb2e8f9f7	4738	{
<>	144:ef7eb2e8f9f7	4739	return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
<>	144:ef7eb2e8f9f7	4740	}
<>	144:ef7eb2e8f9f7	4741
<>	144:ef7eb2e8f9f7	4742	/**
<>	144:ef7eb2e8f9f7	4743	* @}
<>	144:ef7eb2e8f9f7	4744	*/
<>	144:ef7eb2e8f9f7	4745
<>	144:ef7eb2e8f9f7	4746	/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
<>	144:ef7eb2e8f9f7	4747	* @{
<>	144:ef7eb2e8f9f7	4748	*/
<>	144:ef7eb2e8f9f7	4749
<>	144:ef7eb2e8f9f7	4750	/**
<>	144:ef7eb2e8f9f7	4751	* @brief Set ADC analog watchdog monitored channels:
<>	144:ef7eb2e8f9f7	4752	* a single channel, multiple channels or all channels,
<>	144:ef7eb2e8f9f7	4753	* on ADC groups regular and-or injected.
<>	144:ef7eb2e8f9f7	4754	* @note Once monitored channels are selected, analog watchdog
<>	144:ef7eb2e8f9f7	4755	* is enabled.
<>	144:ef7eb2e8f9f7	4756	* @note In case of need to define a single channel to monitor
<>	144:ef7eb2e8f9f7	4757	* with analog watchdog from sequencer channel definition,
<>	144:ef7eb2e8f9f7	4758	* use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
<>	144:ef7eb2e8f9f7	4759	* @note On this STM32 serie, there are 2 kinds of analog watchdog
<>	144:ef7eb2e8f9f7	4760	* instance:
<>	144:ef7eb2e8f9f7	4761	* - AWD standard (instance AWD1):
<>	144:ef7eb2e8f9f7	4762	* - channels monitored: can monitor 1 channel or all channels.
<>	144:ef7eb2e8f9f7	4763	* - groups monitored: ADC groups regular and-or injected.
<>	144:ef7eb2e8f9f7	4764	* - resolution: resolution is not limited (corresponds to
<>	144:ef7eb2e8f9f7	4765	* ADC resolution configured).
<>	144:ef7eb2e8f9f7	4766	* - AWD flexible (instances AWD2, AWD3):
<>	144:ef7eb2e8f9f7	4767	* - channels monitored: flexible on channels monitored, selection is
<>	144:ef7eb2e8f9f7	4768	* channel wise, from from 1 to all channels.
<>	144:ef7eb2e8f9f7	4769	* Specificity of this analog watchdog: Multiple channels can
<>	144:ef7eb2e8f9f7	4770	* be selected. For example:
<>	144:ef7eb2e8f9f7	4771	* (LL_ADC_AWD_CHANNEL4_REG_INJ \| LL_ADC_AWD_CHANNEL5_REG_INJ \| ...)
<>	144:ef7eb2e8f9f7	4772	* - groups monitored: not selection possible (monitoring on both
<>	144:ef7eb2e8f9f7	4773	* groups regular and injected).
<>	144:ef7eb2e8f9f7	4774	* Channels selected are monitored on groups regular and injected:
<>	144:ef7eb2e8f9f7	4775	* LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
<>	144:ef7eb2e8f9f7	4776	* LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
<>	144:ef7eb2e8f9f7	4777	* - resolution: resolution is limited to 8 bits: if ADC resolution is
<>	144:ef7eb2e8f9f7	4778	* 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
<>	144:ef7eb2e8f9f7	4779	* the 2 LSB are ignored.
<>	144:ef7eb2e8f9f7	4780	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	4781	* ADC state:
<>	144:ef7eb2e8f9f7	4782	* ADC must be disabled or enabled without conversion on going
<>	144:ef7eb2e8f9f7	4783	* on either groups regular or injected.
<>	144:ef7eb2e8f9f7	4784	* @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
<>	144:ef7eb2e8f9f7	4785	* CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
<>	144:ef7eb2e8f9f7	4786	* CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
<>	144:ef7eb2e8f9f7	4787	* CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n
<>	144:ef7eb2e8f9f7	4788	* AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
<>	144:ef7eb2e8f9f7	4789	* AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
<>	144:ef7eb2e8f9f7	4790	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	4791	* @param AWDy This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4792	* @arg @ref LL_ADC_AWD1
<>	144:ef7eb2e8f9f7	4793	* @arg @ref LL_ADC_AWD2
<>	144:ef7eb2e8f9f7	4794	* @arg @ref LL_ADC_AWD3
<>	144:ef7eb2e8f9f7	4795	* @param AWDChannelGroup This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4796	* @arg @ref LL_ADC_AWD_DISABLE
<>	144:ef7eb2e8f9f7	4797	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
<>	144:ef7eb2e8f9f7	4798	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
<>	144:ef7eb2e8f9f7	4799	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
<>	144:ef7eb2e8f9f7	4800	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
<>	144:ef7eb2e8f9f7	4801	* @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
<>	144:ef7eb2e8f9f7	4802	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
<>	144:ef7eb2e8f9f7	4803	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
<>	144:ef7eb2e8f9f7	4804	* @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
<>	144:ef7eb2e8f9f7	4805	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
<>	144:ef7eb2e8f9f7	4806	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
<>	144:ef7eb2e8f9f7	4807	* @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
<>	144:ef7eb2e8f9f7	4808	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
<>	144:ef7eb2e8f9f7	4809	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
<>	144:ef7eb2e8f9f7	4810	* @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
<>	144:ef7eb2e8f9f7	4811	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
<>	144:ef7eb2e8f9f7	4812	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
<>	144:ef7eb2e8f9f7	4813	* @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
<>	144:ef7eb2e8f9f7	4814	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
<>	144:ef7eb2e8f9f7	4815	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
<>	144:ef7eb2e8f9f7	4816	* @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
<>	144:ef7eb2e8f9f7	4817	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
<>	144:ef7eb2e8f9f7	4818	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
<>	144:ef7eb2e8f9f7	4819	* @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
<>	144:ef7eb2e8f9f7	4820	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
<>	144:ef7eb2e8f9f7	4821	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
<>	144:ef7eb2e8f9f7	4822	* @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
<>	144:ef7eb2e8f9f7	4823	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
<>	144:ef7eb2e8f9f7	4824	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
<>	144:ef7eb2e8f9f7	4825	* @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
<>	144:ef7eb2e8f9f7	4826	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
<>	144:ef7eb2e8f9f7	4827	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
<>	144:ef7eb2e8f9f7	4828	* @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
<>	144:ef7eb2e8f9f7	4829	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
<>	144:ef7eb2e8f9f7	4830	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
<>	144:ef7eb2e8f9f7	4831	* @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
<>	144:ef7eb2e8f9f7	4832	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
<>	144:ef7eb2e8f9f7	4833	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
<>	144:ef7eb2e8f9f7	4834	* @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
<>	144:ef7eb2e8f9f7	4835	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
<>	144:ef7eb2e8f9f7	4836	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
<>	144:ef7eb2e8f9f7	4837	* @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
<>	144:ef7eb2e8f9f7	4838	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
<>	144:ef7eb2e8f9f7	4839	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
<>	144:ef7eb2e8f9f7	4840	* @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
<>	144:ef7eb2e8f9f7	4841	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
<>	144:ef7eb2e8f9f7	4842	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
<>	144:ef7eb2e8f9f7	4843	* @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
<>	144:ef7eb2e8f9f7	4844	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
<>	144:ef7eb2e8f9f7	4845	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
<>	144:ef7eb2e8f9f7	4846	* @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
<>	144:ef7eb2e8f9f7	4847	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
<>	144:ef7eb2e8f9f7	4848	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
<>	144:ef7eb2e8f9f7	4849	* @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
<>	144:ef7eb2e8f9f7	4850	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
<>	144:ef7eb2e8f9f7	4851	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
<>	144:ef7eb2e8f9f7	4852	* @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
<>	144:ef7eb2e8f9f7	4853	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
<>	144:ef7eb2e8f9f7	4854	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
<>	144:ef7eb2e8f9f7	4855	* @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
<>	144:ef7eb2e8f9f7	4856	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
<>	144:ef7eb2e8f9f7	4857	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
<>	144:ef7eb2e8f9f7	4858	* @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
<>	144:ef7eb2e8f9f7	4859	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
<>	144:ef7eb2e8f9f7	4860	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(4)
<>	144:ef7eb2e8f9f7	4861	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(4)
<>	144:ef7eb2e8f9f7	4862	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (4)
<>	144:ef7eb2e8f9f7	4863	* @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(4)
<>	144:ef7eb2e8f9f7	4864	* @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(4)
<>	144:ef7eb2e8f9f7	4865	* @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (4)
<>	144:ef7eb2e8f9f7	4866	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG (0)(2)(5)
<>	144:ef7eb2e8f9f7	4867	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_INJ (0)(2)(5)
<>	144:ef7eb2e8f9f7	4868	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG_INJ (2)(5)
<>	144:ef7eb2e8f9f7	4869	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG (0)(2)(5)
<>	144:ef7eb2e8f9f7	4870	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_INJ (0)(2)(5)
<>	144:ef7eb2e8f9f7	4871	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG_INJ (2)(5)
<>	144:ef7eb2e8f9f7	4872	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(2)(6)
<>	144:ef7eb2e8f9f7	4873	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(2)(6)
<>	144:ef7eb2e8f9f7	4874	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (2)(6)
<>	144:ef7eb2e8f9f7	4875	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)(6)
<>	144:ef7eb2e8f9f7	4876	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)(6)
<>	144:ef7eb2e8f9f7	4877	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)(6)
<>	144:ef7eb2e8f9f7	4878	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG (0)(3)(6)
<>	144:ef7eb2e8f9f7	4879	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ (0)(3)(6)
<>	144:ef7eb2e8f9f7	4880	* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ (3)(6)
<>	144:ef7eb2e8f9f7	4881	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG (0)(3)(6)
<>	144:ef7eb2e8f9f7	4882	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ (0)(3)(6)
<>	144:ef7eb2e8f9f7	4883	* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ (3)(6)
<>	144:ef7eb2e8f9f7	4884	*
<>	144:ef7eb2e8f9f7	4885	* (0) On STM32L4, parameter available only on analog watchdog number: AWD1.\n
<>	144:ef7eb2e8f9f7	4886	* (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
<>	144:ef7eb2e8f9f7	4887	* (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
<>	144:ef7eb2e8f9f7	4888	* (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
<>	144:ef7eb2e8f9f7	4889	* (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
<>	144:ef7eb2e8f9f7	4890	* (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
<>	144:ef7eb2e8f9f7	4891	* (6) On STM32L4, parameter available on devices with several ADC instances.
<>	144:ef7eb2e8f9f7	4892	* @retval None
<>	144:ef7eb2e8f9f7	4893	*/
<>	144:ef7eb2e8f9f7	4894	__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
<>	144:ef7eb2e8f9f7	4895	{
<>	144:ef7eb2e8f9f7	4896	/* Set bits with content of parameter "AWDChannelGroup" with bits position */
<>	144:ef7eb2e8f9f7	4897	/* in register and register position depending on parameter "AWDy". */
<>	144:ef7eb2e8f9f7	4898	/* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
<>	144:ef7eb2e8f9f7	4899	/* containing other bits reserved for other purpose. */
<>	144:ef7eb2e8f9f7	4900	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK)
<>	144:ef7eb2e8f9f7	4901	+ ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
<>	144:ef7eb2e8f9f7	4902
<>	144:ef7eb2e8f9f7	4903	MODIFY_REG(*preg,
<>	144:ef7eb2e8f9f7	4904	(AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
<>	144:ef7eb2e8f9f7	4905	AWDChannelGroup & AWDy);
<>	144:ef7eb2e8f9f7	4906	}
<>	144:ef7eb2e8f9f7	4907
<>	144:ef7eb2e8f9f7	4908	/**
<>	144:ef7eb2e8f9f7	4909	* @brief Get ADC analog watchdog monitored channel.
<>	144:ef7eb2e8f9f7	4910	* @note Usage of the returned channel number:
<>	144:ef7eb2e8f9f7	4911	* - To reinject this channel into another function LL_ADC_xxx:
<>	144:ef7eb2e8f9f7	4912	* the returned channel number is only partly formatted on definition
<>	144:ef7eb2e8f9f7	4913	* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
<>	144:ef7eb2e8f9f7	4914	* with parts of literals LL_ADC_CHANNEL_x or using
<>	144:ef7eb2e8f9f7	4915	* helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	144:ef7eb2e8f9f7	4916	* Then the selected literal LL_ADC_CHANNEL_x can be used
<>	144:ef7eb2e8f9f7	4917	* as parameter for another function.
<>	144:ef7eb2e8f9f7	4918	* - To get the channel number in decimal format:
<>	144:ef7eb2e8f9f7	4919	* process the returned value with the helper macro
<>	144:ef7eb2e8f9f7	4920	* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	144:ef7eb2e8f9f7	4921	* Applicable only when the analog watchdog is set to monitor
<>	144:ef7eb2e8f9f7	4922	* one channel.
<>	144:ef7eb2e8f9f7	4923	* @note On this STM32 serie, there are 2 kinds of analog watchdog
<>	144:ef7eb2e8f9f7	4924	* instance:
<>	144:ef7eb2e8f9f7	4925	* - AWD standard (instance AWD1):
<>	144:ef7eb2e8f9f7	4926	* - channels monitored: can monitor 1 channel or all channels.
<>	144:ef7eb2e8f9f7	4927	* - groups monitored: ADC groups regular and-or injected.
<>	144:ef7eb2e8f9f7	4928	* - resolution: resolution is not limited (corresponds to
<>	144:ef7eb2e8f9f7	4929	* ADC resolution configured).
<>	144:ef7eb2e8f9f7	4930	* - AWD flexible (instances AWD2, AWD3):
<>	144:ef7eb2e8f9f7	4931	* - channels monitored: flexible on channels monitored, selection is
<>	144:ef7eb2e8f9f7	4932	* channel wise, from from 1 to all channels.
<>	144:ef7eb2e8f9f7	4933	* Specificity of this analog watchdog: Multiple channels can
<>	144:ef7eb2e8f9f7	4934	* be selected. For example:
<>	144:ef7eb2e8f9f7	4935	* (LL_ADC_AWD_CHANNEL4_REG_INJ \| LL_ADC_AWD_CHANNEL5_REG_INJ \| ...)
<>	144:ef7eb2e8f9f7	4936	* - groups monitored: not selection possible (monitoring on both
<>	144:ef7eb2e8f9f7	4937	* groups regular and injected).
<>	144:ef7eb2e8f9f7	4938	* Channels selected are monitored on groups regular and injected:
<>	144:ef7eb2e8f9f7	4939	* LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
<>	144:ef7eb2e8f9f7	4940	* LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
<>	144:ef7eb2e8f9f7	4941	* - resolution: resolution is limited to 8 bits: if ADC resolution is
<>	144:ef7eb2e8f9f7	4942	* 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
<>	144:ef7eb2e8f9f7	4943	* the 2 LSB are ignored.
<>	144:ef7eb2e8f9f7	4944	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	4945	* ADC state:
<>	144:ef7eb2e8f9f7	4946	* ADC must be disabled or enabled without conversion on going
<>	144:ef7eb2e8f9f7	4947	* on either groups regular or injected.
<>	144:ef7eb2e8f9f7	4948	* @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
<>	144:ef7eb2e8f9f7	4949	* CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
<>	144:ef7eb2e8f9f7	4950	* CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
<>	144:ef7eb2e8f9f7	4951	* CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n
<>	144:ef7eb2e8f9f7	4952	* AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
<>	144:ef7eb2e8f9f7	4953	* AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
<>	144:ef7eb2e8f9f7	4954	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	4955	* @param AWDy This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4956	* @arg @ref LL_ADC_AWD1
<>	144:ef7eb2e8f9f7	4957	* @arg @ref LL_ADC_AWD2 (1)
<>	144:ef7eb2e8f9f7	4958	* @arg @ref LL_ADC_AWD3 (1)
<>	144:ef7eb2e8f9f7	4959	*
<>	144:ef7eb2e8f9f7	4960	* (1) On this AWD number, monitored channel can be retrieved
<>	144:ef7eb2e8f9f7	4961	* if only 1 channel is programmed (or none or all channels).
<>	144:ef7eb2e8f9f7	4962	* This function cannot retrieve monitored channel if
<>	144:ef7eb2e8f9f7	4963	* multiple channels are programmed simultaneously
<>	144:ef7eb2e8f9f7	4964	* by bitfield.
<>	144:ef7eb2e8f9f7	4965	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	4966	* @arg @ref LL_ADC_AWD_DISABLE
<>	144:ef7eb2e8f9f7	4967	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
<>	144:ef7eb2e8f9f7	4968	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
<>	144:ef7eb2e8f9f7	4969	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
<>	144:ef7eb2e8f9f7	4970	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
<>	144:ef7eb2e8f9f7	4971	* @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
<>	144:ef7eb2e8f9f7	4972	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
<>	144:ef7eb2e8f9f7	4973	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
<>	144:ef7eb2e8f9f7	4974	* @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
<>	144:ef7eb2e8f9f7	4975	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
<>	144:ef7eb2e8f9f7	4976	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
<>	144:ef7eb2e8f9f7	4977	* @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
<>	144:ef7eb2e8f9f7	4978	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
<>	144:ef7eb2e8f9f7	4979	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
<>	144:ef7eb2e8f9f7	4980	* @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
<>	144:ef7eb2e8f9f7	4981	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
<>	144:ef7eb2e8f9f7	4982	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
<>	144:ef7eb2e8f9f7	4983	* @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
<>	144:ef7eb2e8f9f7	4984	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
<>	144:ef7eb2e8f9f7	4985	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
<>	144:ef7eb2e8f9f7	4986	* @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
<>	144:ef7eb2e8f9f7	4987	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
<>	144:ef7eb2e8f9f7	4988	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
<>	144:ef7eb2e8f9f7	4989	* @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
<>	144:ef7eb2e8f9f7	4990	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
<>	144:ef7eb2e8f9f7	4991	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
<>	144:ef7eb2e8f9f7	4992	* @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
<>	144:ef7eb2e8f9f7	4993	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
<>	144:ef7eb2e8f9f7	4994	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
<>	144:ef7eb2e8f9f7	4995	* @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
<>	144:ef7eb2e8f9f7	4996	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
<>	144:ef7eb2e8f9f7	4997	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
<>	144:ef7eb2e8f9f7	4998	* @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
<>	144:ef7eb2e8f9f7	4999	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
<>	144:ef7eb2e8f9f7	5000	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
<>	144:ef7eb2e8f9f7	5001	* @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
<>	144:ef7eb2e8f9f7	5002	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
<>	144:ef7eb2e8f9f7	5003	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
<>	144:ef7eb2e8f9f7	5004	* @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
<>	144:ef7eb2e8f9f7	5005	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
<>	144:ef7eb2e8f9f7	5006	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
<>	144:ef7eb2e8f9f7	5007	* @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
<>	144:ef7eb2e8f9f7	5008	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
<>	144:ef7eb2e8f9f7	5009	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
<>	144:ef7eb2e8f9f7	5010	* @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
<>	144:ef7eb2e8f9f7	5011	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
<>	144:ef7eb2e8f9f7	5012	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
<>	144:ef7eb2e8f9f7	5013	* @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
<>	144:ef7eb2e8f9f7	5014	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
<>	144:ef7eb2e8f9f7	5015	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
<>	144:ef7eb2e8f9f7	5016	* @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
<>	144:ef7eb2e8f9f7	5017	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
<>	144:ef7eb2e8f9f7	5018	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
<>	144:ef7eb2e8f9f7	5019	* @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
<>	144:ef7eb2e8f9f7	5020	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
<>	144:ef7eb2e8f9f7	5021	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
<>	144:ef7eb2e8f9f7	5022	* @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
<>	144:ef7eb2e8f9f7	5023	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
<>	144:ef7eb2e8f9f7	5024	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
<>	144:ef7eb2e8f9f7	5025	* @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
<>	144:ef7eb2e8f9f7	5026	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
<>	144:ef7eb2e8f9f7	5027	*
<>	144:ef7eb2e8f9f7	5028	* (0) On STM32L4, parameter available only on analog watchdog number: AWD1.
<>	144:ef7eb2e8f9f7	5029	*/
<>	144:ef7eb2e8f9f7	5030	__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
<>	144:ef7eb2e8f9f7	5031	{
<>	144:ef7eb2e8f9f7	5032	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK)
<>	144:ef7eb2e8f9f7	5033	+ ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
<>	144:ef7eb2e8f9f7	5034
<>	144:ef7eb2e8f9f7	5035	/* Variable "AWDy" used to retrieve appropriate bitfield corresponding to */
<>	144:ef7eb2e8f9f7	5036	/* ADC_AWD_CR1_CHANNEL_MASK or ADC_AWD_CR23_CHANNEL_MASK. */
<>	144:ef7eb2e8f9f7	5037	register uint32_t AWD123ChannelGroup = READ_BIT(*preg, (AWDy \| ADC_AWD_CR_ALL_CHANNEL_MASK));
<>	144:ef7eb2e8f9f7	5038
<>	144:ef7eb2e8f9f7	5039	/* Set variable of AWD1 monitored channel according to AWD1 features */
<>	144:ef7eb2e8f9f7	5040	/* and ADC channel definition: */
<>	144:ef7eb2e8f9f7	5041	/* - channel ID with number */
<>	144:ef7eb2e8f9f7	5042	/* - channel ID with bitfield */
<>	144:ef7eb2e8f9f7	5043	/* - AWD1 single or all channels */
<>	144:ef7eb2e8f9f7	5044	/* - AWD1 enable or disable (also used to discard AWD1 bitfield in case of */
<>	144:ef7eb2e8f9f7	5045	/* AWD2 or AWD3 selected). */
<>	144:ef7eb2e8f9f7	5046	register uint32_t AWD1ChannelSingle = ((AWD123ChannelGroup & ADC_CFGR_AWD1SGL) >> ADC_CFGR_AWD1SGL_BITOFFSET_POS);
<>	144:ef7eb2e8f9f7	5047
<>	144:ef7eb2e8f9f7	5048	register uint32_t AWD1ChannelGroup = ( ( AWD123ChannelGroup
<>	144:ef7eb2e8f9f7	5049	\| ((ADC_CHANNEL_0_BITFIELD << ((AWD123ChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)) * AWD1ChannelSingle)
<>	144:ef7eb2e8f9f7	5050	\| (ADC_CHANNEL_ID_BITFIELD_MASK * (~AWD1ChannelSingle & ((uint32_t)0x00000001U)))
<>	144:ef7eb2e8f9f7	5051	)
<>	144:ef7eb2e8f9f7	5052	* (((AWD123ChannelGroup & ADC_CFGR_JAWD1EN) >> ADC_CFGR_JAWD1EN_BITOFFSET_POS) \| ((AWD123ChannelGroup & ADC_CFGR_AWD1EN) >> ADC_CFGR_AWD1EN_BITOFFSET_POS))
<>	144:ef7eb2e8f9f7	5053	);
<>	144:ef7eb2e8f9f7	5054
<>	144:ef7eb2e8f9f7	5055	/* Set variable of AWD2 and AWD3 monitored channel according to AWD2-3 */
<>	144:ef7eb2e8f9f7	5056	/* features and ADC channel definition: */
<>	144:ef7eb2e8f9f7	5057	/* - channel ID with number */
<>	144:ef7eb2e8f9f7	5058	/* - channel ID with bitfield */
<>	144:ef7eb2e8f9f7	5059	/* - AWD2-3 single or all channels (shift value 32 (0x1 shift 5) used to */
<>	144:ef7eb2e8f9f7	5060	/* shift AWD1 equivalent single-all channels out of register) */
<>	144:ef7eb2e8f9f7	5061	/* - AWD2-3 enable or disable */
<>	144:ef7eb2e8f9f7	5062	/* Note: Use modulo 3 to avoid a shift value too long. On AWD2 and AWD3, */
<>	144:ef7eb2e8f9f7	5063	/* channel can be read back if only 1 channel monitoring */
<>	144:ef7eb2e8f9f7	5064	/* is activated, therefore the channel monitoring value channel "3" */
<>	144:ef7eb2e8f9f7	5065	/* is not not supported by this function, there is no risk of */
<>	144:ef7eb2e8f9f7	5066	/* conflict. */
<>	144:ef7eb2e8f9f7	5067	register uint32_t AWD23Enabled = ((((uint32_t)0x00000001U) >> (AWD123ChannelGroup % 3U)) << 6U); /* Value "0" if AWD2-3 is enabled, value "32" if AWD2-3 is disabled */
<>	144:ef7eb2e8f9f7	5068
<>	144:ef7eb2e8f9f7	5069	register uint32_t AWD23ChannelGroup = ((( AWD123ChannelGroup
<>	144:ef7eb2e8f9f7	5070	\| ((uint32_t)POSITION_VAL(AWD123ChannelGroup) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
<>	144:ef7eb2e8f9f7	5071	\| ((ADC_CFGR_AWD1SGL) >> ((((uint32_t)0x00000001U) >> (ADC_AWD_CR23_CHANNEL_MASK - AWD123ChannelGroup)) << 5U))
<>	144:ef7eb2e8f9f7	5072	\| (ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN)
<>	144:ef7eb2e8f9f7	5073	) >> AWD23Enabled
<>	144:ef7eb2e8f9f7	5074	) >> (((AWDy & ADC_CFGR_AWD1SGL) >> ADC_CFGR_AWD1SGL_BITOFFSET_POS) << 5U));
<>	144:ef7eb2e8f9f7	5075
<>	144:ef7eb2e8f9f7	5076	return (AWD1ChannelGroup \| AWD23ChannelGroup);
<>	144:ef7eb2e8f9f7	5077	}
<>	144:ef7eb2e8f9f7	5078
<>	144:ef7eb2e8f9f7	5079	/**
<>	144:ef7eb2e8f9f7	5080	* @brief Set ADC analog watchdog thresholds value of both thresholds
<>	144:ef7eb2e8f9f7	5081	* high and low.
<>	144:ef7eb2e8f9f7	5082	* @note If value of only one threshold high or low must be set,
<>	144:ef7eb2e8f9f7	5083	* use function @ref LL_ADC_SetAnalogWDThresholds().
<>	144:ef7eb2e8f9f7	5084	* @note In case of ADC resolution different of 12 bits,
<>	144:ef7eb2e8f9f7	5085	* analog watchdog thresholds data require a specific shift.
<>	144:ef7eb2e8f9f7	5086	* Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
<>	144:ef7eb2e8f9f7	5087	* @note On this STM32 serie, there are 2 kinds of analog watchdog
<>	144:ef7eb2e8f9f7	5088	* instance:
<>	144:ef7eb2e8f9f7	5089	* - AWD standard (instance AWD1):
<>	144:ef7eb2e8f9f7	5090	* - channels monitored: can monitor 1 channel or all channels.
<>	144:ef7eb2e8f9f7	5091	* - groups monitored: ADC groups regular and-or injected.
<>	144:ef7eb2e8f9f7	5092	* - resolution: resolution is not limited (corresponds to
<>	144:ef7eb2e8f9f7	5093	* ADC resolution configured).
<>	144:ef7eb2e8f9f7	5094	* - AWD flexible (instances AWD2, AWD3):
<>	144:ef7eb2e8f9f7	5095	* - channels monitored: flexible on channels monitored, selection is
<>	144:ef7eb2e8f9f7	5096	* channel wise, from from 1 to all channels.
<>	144:ef7eb2e8f9f7	5097	* Specificity of this analog watchdog: Multiple channels can
<>	144:ef7eb2e8f9f7	5098	* be selected. For example:
<>	144:ef7eb2e8f9f7	5099	* (LL_ADC_AWD_CHANNEL4_REG_INJ \| LL_ADC_AWD_CHANNEL5_REG_INJ \| ...)
<>	144:ef7eb2e8f9f7	5100	* - groups monitored: not selection possible (monitoring on both
<>	144:ef7eb2e8f9f7	5101	* groups regular and injected).
<>	144:ef7eb2e8f9f7	5102	* Channels selected are monitored on groups regular and injected:
<>	144:ef7eb2e8f9f7	5103	* LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
<>	144:ef7eb2e8f9f7	5104	* LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
<>	144:ef7eb2e8f9f7	5105	* - resolution: resolution is limited to 8 bits: if ADC resolution is
<>	144:ef7eb2e8f9f7	5106	* 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
<>	144:ef7eb2e8f9f7	5107	* the 2 LSB are ignored.
<>	144:ef7eb2e8f9f7	5108	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	5109	* ADC state:
<>	144:ef7eb2e8f9f7	5110	* ADC must be disabled or enabled without conversion on going
<>	144:ef7eb2e8f9f7	5111	* on either groups regular or injected.
<>	144:ef7eb2e8f9f7	5112	* @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n
<>	144:ef7eb2e8f9f7	5113	* TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n
<>	144:ef7eb2e8f9f7	5114	* TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n
<>	144:ef7eb2e8f9f7	5115	* TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n
<>	144:ef7eb2e8f9f7	5116	* TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n
<>	144:ef7eb2e8f9f7	5117	* TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
<>	144:ef7eb2e8f9f7	5118	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	5119	* @param AWDy This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5120	* @arg @ref LL_ADC_AWD1
<>	144:ef7eb2e8f9f7	5121	* @arg @ref LL_ADC_AWD2
<>	144:ef7eb2e8f9f7	5122	* @arg @ref LL_ADC_AWD3
<>	144:ef7eb2e8f9f7	5123	* @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
<>	144:ef7eb2e8f9f7	5124	* @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
<>	144:ef7eb2e8f9f7	5125	* @retval None
<>	144:ef7eb2e8f9f7	5126	*/
<>	144:ef7eb2e8f9f7	5127	__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
<>	144:ef7eb2e8f9f7	5128	{
<>	144:ef7eb2e8f9f7	5129	/* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
<>	144:ef7eb2e8f9f7	5130	/* position in register and register position depending on parameter */
<>	144:ef7eb2e8f9f7	5131	/* "AWDy". */
<>	144:ef7eb2e8f9f7	5132	/* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
<>	144:ef7eb2e8f9f7	5133	/* containing other bits reserved for other purpose. */
<>	144:ef7eb2e8f9f7	5134	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
<>	144:ef7eb2e8f9f7	5135
<>	144:ef7eb2e8f9f7	5136	MODIFY_REG(*preg,
<>	144:ef7eb2e8f9f7	5137	ADC_TR1_HT1 \| ADC_TR1_LT1,
<>	144:ef7eb2e8f9f7	5138	(AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) \| AWDThresholdLowValue);
<>	144:ef7eb2e8f9f7	5139	}
<>	144:ef7eb2e8f9f7	5140
<>	144:ef7eb2e8f9f7	5141	/**
<>	144:ef7eb2e8f9f7	5142	* @brief Set ADC analog watchdog threshold value of threshold
<>	144:ef7eb2e8f9f7	5143	* high or low.
<>	144:ef7eb2e8f9f7	5144	* @note If values of both thresholds high or low must be set,
<>	144:ef7eb2e8f9f7	5145	* use function @ref LL_ADC_ConfigAnalogWDThresholds().
<>	144:ef7eb2e8f9f7	5146	* @note In case of ADC resolution different of 12 bits,
<>	144:ef7eb2e8f9f7	5147	* analog watchdog thresholds data require a specific shift.
<>	144:ef7eb2e8f9f7	5148	* Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
<>	144:ef7eb2e8f9f7	5149	* @note On this STM32 serie, there are 2 kinds of analog watchdog
<>	144:ef7eb2e8f9f7	5150	* instance:
<>	144:ef7eb2e8f9f7	5151	* - AWD standard (instance AWD1):
<>	144:ef7eb2e8f9f7	5152	* - channels monitored: can monitor 1 channel or all channels.
<>	144:ef7eb2e8f9f7	5153	* - groups monitored: ADC groups regular and-or injected.
<>	144:ef7eb2e8f9f7	5154	* - resolution: resolution is not limited (corresponds to
<>	144:ef7eb2e8f9f7	5155	* ADC resolution configured).
<>	144:ef7eb2e8f9f7	5156	* - AWD flexible (instances AWD2, AWD3):
<>	144:ef7eb2e8f9f7	5157	* - channels monitored: flexible on channels monitored, selection is
<>	144:ef7eb2e8f9f7	5158	* channel wise, from from 1 to all channels.
<>	144:ef7eb2e8f9f7	5159	* Specificity of this analog watchdog: Multiple channels can
<>	144:ef7eb2e8f9f7	5160	* be selected. For example:
<>	144:ef7eb2e8f9f7	5161	* (LL_ADC_AWD_CHANNEL4_REG_INJ \| LL_ADC_AWD_CHANNEL5_REG_INJ \| ...)
<>	144:ef7eb2e8f9f7	5162	* - groups monitored: not selection possible (monitoring on both
<>	144:ef7eb2e8f9f7	5163	* groups regular and injected).
<>	144:ef7eb2e8f9f7	5164	* Channels selected are monitored on groups regular and injected:
<>	144:ef7eb2e8f9f7	5165	* LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
<>	144:ef7eb2e8f9f7	5166	* LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
<>	144:ef7eb2e8f9f7	5167	* - resolution: resolution is limited to 8 bits: if ADC resolution is
<>	144:ef7eb2e8f9f7	5168	* 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
<>	144:ef7eb2e8f9f7	5169	* the 2 LSB are ignored.
<>	144:ef7eb2e8f9f7	5170	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	5171	* ADC state:
<>	144:ef7eb2e8f9f7	5172	* ADC must be disabled or enabled without conversion on going
<>	144:ef7eb2e8f9f7	5173	* on either groups regular or injected.
<>	144:ef7eb2e8f9f7	5174	* @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n
<>	144:ef7eb2e8f9f7	5175	* TR2 HT2 LL_ADC_SetAnalogWDThresholds\n
<>	144:ef7eb2e8f9f7	5176	* TR3 HT3 LL_ADC_SetAnalogWDThresholds\n
<>	144:ef7eb2e8f9f7	5177	* TR1 LT1 LL_ADC_SetAnalogWDThresholds\n
<>	144:ef7eb2e8f9f7	5178	* TR2 LT2 LL_ADC_SetAnalogWDThresholds\n
<>	144:ef7eb2e8f9f7	5179	* TR3 LT3 LL_ADC_SetAnalogWDThresholds
<>	144:ef7eb2e8f9f7	5180	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	5181	* @param AWDy This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5182	* @arg @ref LL_ADC_AWD1
<>	144:ef7eb2e8f9f7	5183	* @arg @ref LL_ADC_AWD2
<>	144:ef7eb2e8f9f7	5184	* @arg @ref LL_ADC_AWD3
<>	144:ef7eb2e8f9f7	5185	* @param AWDThresholdsHighLow This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5186	* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
<>	144:ef7eb2e8f9f7	5187	* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
<>	144:ef7eb2e8f9f7	5188	* @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF
<>	144:ef7eb2e8f9f7	5189	* @retval None
<>	144:ef7eb2e8f9f7	5190	*/
<>	144:ef7eb2e8f9f7	5191	__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
<>	144:ef7eb2e8f9f7	5192	{
<>	144:ef7eb2e8f9f7	5193	/* Set bits with content of parameter "AWDThresholdValue" with bits */
<>	144:ef7eb2e8f9f7	5194	/* position in register and register position depending on parameters */
<>	144:ef7eb2e8f9f7	5195	/* "AWDThresholdsHighLow" and "AWDy". */
<>	144:ef7eb2e8f9f7	5196	/* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
<>	144:ef7eb2e8f9f7	5197	/* containing other bits reserved for other purpose. */
<>	144:ef7eb2e8f9f7	5198	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
<>	144:ef7eb2e8f9f7	5199
<>	144:ef7eb2e8f9f7	5200	MODIFY_REG(*preg,
<>	144:ef7eb2e8f9f7	5201	AWDThresholdsHighLow,
<>	144:ef7eb2e8f9f7	5202	AWDThresholdValue << POSITION_VAL(AWDThresholdsHighLow));
<>	144:ef7eb2e8f9f7	5203	}
<>	144:ef7eb2e8f9f7	5204
<>	144:ef7eb2e8f9f7	5205	/**
<>	144:ef7eb2e8f9f7	5206	* @brief Get ADC analog watchdog threshold value of threshold high,
<>	144:ef7eb2e8f9f7	5207	* threshold low or raw data with ADC thresholds high and low
<>	144:ef7eb2e8f9f7	5208	* concatenated.
<>	144:ef7eb2e8f9f7	5209	* @note If raw data with ADC thresholds high and low is retrieved,
<>	144:ef7eb2e8f9f7	5210	* the data of each threshold high or low can be isolated
<>	144:ef7eb2e8f9f7	5211	* using helper macro:
<>	144:ef7eb2e8f9f7	5212	* @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
<>	144:ef7eb2e8f9f7	5213	* @note In case of ADC resolution different of 12 bits,
<>	144:ef7eb2e8f9f7	5214	* analog watchdog thresholds data require a specific shift.
<>	144:ef7eb2e8f9f7	5215	* Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
<>	144:ef7eb2e8f9f7	5216	* @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
<>	144:ef7eb2e8f9f7	5217	* TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
<>	144:ef7eb2e8f9f7	5218	* TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
<>	144:ef7eb2e8f9f7	5219	* TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
<>	144:ef7eb2e8f9f7	5220	* TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
<>	144:ef7eb2e8f9f7	5221	* TR3 LT3 LL_ADC_GetAnalogWDThresholds
<>	144:ef7eb2e8f9f7	5222	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	5223	* @param AWDy This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5224	* @arg @ref LL_ADC_AWD1
<>	144:ef7eb2e8f9f7	5225	* @arg @ref LL_ADC_AWD2
<>	144:ef7eb2e8f9f7	5226	* @arg @ref LL_ADC_AWD3
<>	144:ef7eb2e8f9f7	5227	* @param AWDThresholdsHighLow This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5228	* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
<>	144:ef7eb2e8f9f7	5229	* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
<>	144:ef7eb2e8f9f7	5230	* @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
<>	144:ef7eb2e8f9f7	5231	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	144:ef7eb2e8f9f7	5232	*/
<>	144:ef7eb2e8f9f7	5233	__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
<>	144:ef7eb2e8f9f7	5234	{
<>	144:ef7eb2e8f9f7	5235	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
<>	144:ef7eb2e8f9f7	5236
<>	144:ef7eb2e8f9f7	5237	return (uint32_t)(READ_BIT(*preg,
<>	144:ef7eb2e8f9f7	5238	(AWDThresholdsHighLow \| ADC_TR1_LT1))
<>	144:ef7eb2e8f9f7	5239	>> POSITION_VAL(AWDThresholdsHighLow)
<>	144:ef7eb2e8f9f7	5240	);
<>	144:ef7eb2e8f9f7	5241	}
<>	144:ef7eb2e8f9f7	5242
<>	144:ef7eb2e8f9f7	5243	/**
<>	144:ef7eb2e8f9f7	5244	* @}
<>	144:ef7eb2e8f9f7	5245	*/
<>	144:ef7eb2e8f9f7	5246
<>	144:ef7eb2e8f9f7	5247	/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
<>	144:ef7eb2e8f9f7	5248	* @{
<>	144:ef7eb2e8f9f7	5249	*/
<>	144:ef7eb2e8f9f7	5250
<>	144:ef7eb2e8f9f7	5251	/**
<>	144:ef7eb2e8f9f7	5252	* @brief Set ADC oversampling scope: ADC groups regular and-or injected
<>	144:ef7eb2e8f9f7	5253	* (availability of ADC group injected depends on STM32 families).
<>	144:ef7eb2e8f9f7	5254	* @note If both groups regular and injected are selected,
<>	144:ef7eb2e8f9f7	5255	* specify behavior of ADC group injected interrupting
<>	144:ef7eb2e8f9f7	5256	* group regular: when ADC group injected is triggered,
<>	144:ef7eb2e8f9f7	5257	* the oversampling on ADC group regular is either
<>	144:ef7eb2e8f9f7	5258	* temporary stopped and continued, or resumed from start
<>	144:ef7eb2e8f9f7	5259	* (oversampler buffer reset).
<>	144:ef7eb2e8f9f7	5260	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	5261	* ADC state:
<>	144:ef7eb2e8f9f7	5262	* ADC must be disabled or enabled without conversion on going
<>	144:ef7eb2e8f9f7	5263	* on either groups regular or injected.
<>	144:ef7eb2e8f9f7	5264	* @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n
<>	144:ef7eb2e8f9f7	5265	* CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n
<>	144:ef7eb2e8f9f7	5266	* CFGR2 ROVSM LL_ADC_SetOverSamplingScope
<>	144:ef7eb2e8f9f7	5267	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	5268	* @param OvsScope This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5269	* @arg @ref LL_ADC_OVS_DISABLE
<>	144:ef7eb2e8f9f7	5270	* @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
<>	144:ef7eb2e8f9f7	5271	* @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
<>	144:ef7eb2e8f9f7	5272	* @arg @ref LL_ADC_OVS_GRP_INJECTED
<>	144:ef7eb2e8f9f7	5273	* @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
<>	144:ef7eb2e8f9f7	5274	* @retval None
<>	144:ef7eb2e8f9f7	5275	*/
<>	144:ef7eb2e8f9f7	5276	__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
<>	144:ef7eb2e8f9f7	5277	{
<>	144:ef7eb2e8f9f7	5278	MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE \| ADC_CFGR2_JOVSE \| ADC_CFGR2_ROVSM, OvsScope);
<>	144:ef7eb2e8f9f7	5279	}
<>	144:ef7eb2e8f9f7	5280
<>	144:ef7eb2e8f9f7	5281	/**
<>	144:ef7eb2e8f9f7	5282	* @brief Get ADC oversampling scope: ADC groups regular and-or injected
<>	144:ef7eb2e8f9f7	5283	* (availability of ADC group injected depends on STM32 families).
<>	144:ef7eb2e8f9f7	5284	* @note If both groups regular and injected are selected,
<>	144:ef7eb2e8f9f7	5285	* specify behavior of ADC group injected interrupting
<>	144:ef7eb2e8f9f7	5286	* group regular: when ADC group injected is triggered,
<>	144:ef7eb2e8f9f7	5287	* the oversampling on ADC group regular is either
<>	144:ef7eb2e8f9f7	5288	* temporary stopped and continued, or resumed from start
<>	144:ef7eb2e8f9f7	5289	* (oversampler buffer reset).
<>	144:ef7eb2e8f9f7	5290	* @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n
<>	144:ef7eb2e8f9f7	5291	* CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n
<>	144:ef7eb2e8f9f7	5292	* CFGR2 ROVSM LL_ADC_GetOverSamplingScope
<>	144:ef7eb2e8f9f7	5293	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	5294	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	5295	* @arg @ref LL_ADC_OVS_DISABLE
<>	144:ef7eb2e8f9f7	5296	* @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
<>	144:ef7eb2e8f9f7	5297	* @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
<>	144:ef7eb2e8f9f7	5298	* @arg @ref LL_ADC_OVS_GRP_INJECTED
<>	144:ef7eb2e8f9f7	5299	* @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
<>	144:ef7eb2e8f9f7	5300	*/
<>	144:ef7eb2e8f9f7	5301	__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	5302	{
<>	144:ef7eb2e8f9f7	5303	return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE \| ADC_CFGR2_JOVSE \| ADC_CFGR2_ROVSM));
<>	144:ef7eb2e8f9f7	5304	}
<>	144:ef7eb2e8f9f7	5305
<>	144:ef7eb2e8f9f7	5306	/**
<>	144:ef7eb2e8f9f7	5307	* @brief Set ADC oversampling discontinuous mode (triggered mode)
<>	144:ef7eb2e8f9f7	5308	* on the selected ADC group.
<>	144:ef7eb2e8f9f7	5309	* @note Number of oversampled conversions are done either in:
<>	144:ef7eb2e8f9f7	5310	* - continuous mode (all conversions of oversampling ratio
<>	144:ef7eb2e8f9f7	5311	* are done from 1 trigger)
<>	144:ef7eb2e8f9f7	5312	* - discontinuous mode (each conversion of oversampling ratio
<>	144:ef7eb2e8f9f7	5313	* needs a trigger)
<>	144:ef7eb2e8f9f7	5314	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	5315	* ADC state:
<>	144:ef7eb2e8f9f7	5316	* ADC must be disabled or enabled without conversion on going
<>	144:ef7eb2e8f9f7	5317	* on group regular.
<>	144:ef7eb2e8f9f7	5318	* @note On this STM32 serie, oversampling discontinuous mode
<>	144:ef7eb2e8f9f7	5319	* (triggered mode) can be used only when oversampling is
<>	144:ef7eb2e8f9f7	5320	* set on group regular only and in resumed mode.
<>	144:ef7eb2e8f9f7	5321	* @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
<>	144:ef7eb2e8f9f7	5322	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	5323	* @param OverSamplingDiscont This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5324	* @arg @ref LL_ADC_OVS_REG_CONT
<>	144:ef7eb2e8f9f7	5325	* @arg @ref LL_ADC_OVS_REG_DISCONT
<>	144:ef7eb2e8f9f7	5326	* @retval None
<>	144:ef7eb2e8f9f7	5327	*/
<>	144:ef7eb2e8f9f7	5328	__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
<>	144:ef7eb2e8f9f7	5329	{
<>	144:ef7eb2e8f9f7	5330	MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
<>	144:ef7eb2e8f9f7	5331	}
<>	144:ef7eb2e8f9f7	5332
<>	144:ef7eb2e8f9f7	5333	/**
<>	144:ef7eb2e8f9f7	5334	* @brief Get ADC oversampling discontinuous mode (triggered mode)
<>	144:ef7eb2e8f9f7	5335	* on the selected ADC group.
<>	144:ef7eb2e8f9f7	5336	* @note Number of oversampled conversions are done either in:
<>	144:ef7eb2e8f9f7	5337	* - continuous mode (all conversions of oversampling ratio
<>	144:ef7eb2e8f9f7	5338	* are done from 1 trigger)
<>	144:ef7eb2e8f9f7	5339	* - discontinuous mode (each conversion of oversampling ratio
<>	144:ef7eb2e8f9f7	5340	* needs a trigger)
<>	144:ef7eb2e8f9f7	5341	* @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
<>	144:ef7eb2e8f9f7	5342	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	5343	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	5344	* @arg @ref LL_ADC_OVS_REG_CONT
<>	144:ef7eb2e8f9f7	5345	* @arg @ref LL_ADC_OVS_REG_DISCONT
<>	144:ef7eb2e8f9f7	5346	*/
<>	144:ef7eb2e8f9f7	5347	__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	5348	{
<>	144:ef7eb2e8f9f7	5349	return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
<>	144:ef7eb2e8f9f7	5350	}
<>	144:ef7eb2e8f9f7	5351
<>	144:ef7eb2e8f9f7	5352	/**
<>	144:ef7eb2e8f9f7	5353	* @brief Set ADC oversampling
<>	144:ef7eb2e8f9f7	5354	* (impacting both ADC groups regular and injected)
<>	144:ef7eb2e8f9f7	5355	* @note This function set the 2 items of oversampling configuration:
<>	144:ef7eb2e8f9f7	5356	* - ratio
<>	144:ef7eb2e8f9f7	5357	* - shift
<>	144:ef7eb2e8f9f7	5358	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	5359	* ADC state:
<>	144:ef7eb2e8f9f7	5360	* ADC must be disabled or enabled without conversion on going
<>	144:ef7eb2e8f9f7	5361	* on either groups regular or injected.
<>	144:ef7eb2e8f9f7	5362	* @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
<>	144:ef7eb2e8f9f7	5363	* CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
<>	144:ef7eb2e8f9f7	5364	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	5365	* @param Ratio This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5366	* @arg @ref LL_ADC_OVS_RATIO_2
<>	144:ef7eb2e8f9f7	5367	* @arg @ref LL_ADC_OVS_RATIO_4
<>	144:ef7eb2e8f9f7	5368	* @arg @ref LL_ADC_OVS_RATIO_8
<>	144:ef7eb2e8f9f7	5369	* @arg @ref LL_ADC_OVS_RATIO_16
<>	144:ef7eb2e8f9f7	5370	* @arg @ref LL_ADC_OVS_RATIO_32
<>	144:ef7eb2e8f9f7	5371	* @arg @ref LL_ADC_OVS_RATIO_64
<>	144:ef7eb2e8f9f7	5372	* @arg @ref LL_ADC_OVS_RATIO_128
<>	144:ef7eb2e8f9f7	5373	* @arg @ref LL_ADC_OVS_RATIO_256
<>	144:ef7eb2e8f9f7	5374	* @param Shift This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5375	* @arg @ref LL_ADC_OVS_SHIFT_NONE
<>	144:ef7eb2e8f9f7	5376	* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
<>	144:ef7eb2e8f9f7	5377	* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
<>	144:ef7eb2e8f9f7	5378	* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
<>	144:ef7eb2e8f9f7	5379	* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
<>	144:ef7eb2e8f9f7	5380	* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
<>	144:ef7eb2e8f9f7	5381	* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
<>	144:ef7eb2e8f9f7	5382	* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
<>	144:ef7eb2e8f9f7	5383	* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
<>	144:ef7eb2e8f9f7	5384	* @retval None
<>	144:ef7eb2e8f9f7	5385	*/
<>	144:ef7eb2e8f9f7	5386	__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
<>	144:ef7eb2e8f9f7	5387	{
<>	144:ef7eb2e8f9f7	5388	MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS \| ADC_CFGR2_OVSR), (Shift \| Ratio));
<>	144:ef7eb2e8f9f7	5389	}
<>	144:ef7eb2e8f9f7	5390
<>	144:ef7eb2e8f9f7	5391	/**
<>	144:ef7eb2e8f9f7	5392	* @brief Get ADC oversampling ratio
<>	144:ef7eb2e8f9f7	5393	* (impacting both ADC groups regular and injected)
<>	144:ef7eb2e8f9f7	5394	* @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
<>	144:ef7eb2e8f9f7	5395	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	5396	* @retval Ratio This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5397	* @arg @ref LL_ADC_OVS_RATIO_2
<>	144:ef7eb2e8f9f7	5398	* @arg @ref LL_ADC_OVS_RATIO_4
<>	144:ef7eb2e8f9f7	5399	* @arg @ref LL_ADC_OVS_RATIO_8
<>	144:ef7eb2e8f9f7	5400	* @arg @ref LL_ADC_OVS_RATIO_16
<>	144:ef7eb2e8f9f7	5401	* @arg @ref LL_ADC_OVS_RATIO_32
<>	144:ef7eb2e8f9f7	5402	* @arg @ref LL_ADC_OVS_RATIO_64
<>	144:ef7eb2e8f9f7	5403	* @arg @ref LL_ADC_OVS_RATIO_128
<>	144:ef7eb2e8f9f7	5404	* @arg @ref LL_ADC_OVS_RATIO_256
<>	144:ef7eb2e8f9f7	5405	*/
<>	144:ef7eb2e8f9f7	5406	__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	5407	{
<>	144:ef7eb2e8f9f7	5408	return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
<>	144:ef7eb2e8f9f7	5409	}
<>	144:ef7eb2e8f9f7	5410
<>	144:ef7eb2e8f9f7	5411	/**
<>	144:ef7eb2e8f9f7	5412	* @brief Get ADC oversampling shift
<>	144:ef7eb2e8f9f7	5413	* (impacting both ADC groups regular and injected)
<>	144:ef7eb2e8f9f7	5414	* @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
<>	144:ef7eb2e8f9f7	5415	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	5416	* @retval Shift This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5417	* @arg @ref LL_ADC_OVS_SHIFT_NONE
<>	144:ef7eb2e8f9f7	5418	* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
<>	144:ef7eb2e8f9f7	5419	* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
<>	144:ef7eb2e8f9f7	5420	* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
<>	144:ef7eb2e8f9f7	5421	* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
<>	144:ef7eb2e8f9f7	5422	* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
<>	144:ef7eb2e8f9f7	5423	* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
<>	144:ef7eb2e8f9f7	5424	* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
<>	144:ef7eb2e8f9f7	5425	* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
<>	144:ef7eb2e8f9f7	5426	*/
<>	144:ef7eb2e8f9f7	5427	__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	5428	{
<>	144:ef7eb2e8f9f7	5429	return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
<>	144:ef7eb2e8f9f7	5430	}
<>	144:ef7eb2e8f9f7	5431
<>	144:ef7eb2e8f9f7	5432	/**
<>	144:ef7eb2e8f9f7	5433	* @}
<>	144:ef7eb2e8f9f7	5434	*/
<>	144:ef7eb2e8f9f7	5435
<>	144:ef7eb2e8f9f7	5436	/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
<>	144:ef7eb2e8f9f7	5437	* @{
<>	144:ef7eb2e8f9f7	5438	*/
<>	144:ef7eb2e8f9f7	5439
<>	144:ef7eb2e8f9f7	5440	#if defined(ADC_MULTIMODE_SUPPORT)
<>	144:ef7eb2e8f9f7	5441	/**
<>	144:ef7eb2e8f9f7	5442	* @brief Set ADC multimode configuration to operate in independent mode
<>	144:ef7eb2e8f9f7	5443	* or multimode (for devices with several ADC instances).
<>	144:ef7eb2e8f9f7	5444	* @note If multimode configuration: the selected ADC instance is
<>	144:ef7eb2e8f9f7	5445	* either master or slave depending on hardware.
<>	144:ef7eb2e8f9f7	5446	* Refer to reference manual.
<>	144:ef7eb2e8f9f7	5447	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	5448	* ADC state:
<>	144:ef7eb2e8f9f7	5449	* All ADC instances of the ADC common group must be disabled.
<>	144:ef7eb2e8f9f7	5450	* This check can be done with function @ref LL_ADC_IsEnabled() for each
<>	144:ef7eb2e8f9f7	5451	* ADC instance or by using helper macro
<>	144:ef7eb2e8f9f7	5452	* @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
<>	144:ef7eb2e8f9f7	5453	* @rmtoll CCR DUAL LL_ADC_SetMultimode
<>	144:ef7eb2e8f9f7	5454	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	5455	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	5456	* @param Multimode This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5457	* @arg @ref LL_ADC_MULTI_INDEPENDENT
<>	144:ef7eb2e8f9f7	5458	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
<>	144:ef7eb2e8f9f7	5459	* @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
<>	144:ef7eb2e8f9f7	5460	* @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
<>	144:ef7eb2e8f9f7	5461	* @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
<>	144:ef7eb2e8f9f7	5462	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
<>	144:ef7eb2e8f9f7	5463	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
<>	144:ef7eb2e8f9f7	5464	* @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
<>	144:ef7eb2e8f9f7	5465	* @retval None
<>	144:ef7eb2e8f9f7	5466	*/
<>	144:ef7eb2e8f9f7	5467	__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
<>	144:ef7eb2e8f9f7	5468	{
<>	144:ef7eb2e8f9f7	5469	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
<>	144:ef7eb2e8f9f7	5470	}
<>	144:ef7eb2e8f9f7	5471
<>	144:ef7eb2e8f9f7	5472	/**
<>	144:ef7eb2e8f9f7	5473	* @brief Get ADC multimode configuration to operate in independent mode
<>	144:ef7eb2e8f9f7	5474	* or multimode (for devices with several ADC instances).
<>	144:ef7eb2e8f9f7	5475	* @note If multimode configuration: the selected ADC instance is
<>	144:ef7eb2e8f9f7	5476	* either master or slave depending on hardware.
<>	144:ef7eb2e8f9f7	5477	* Refer to reference manual.
<>	144:ef7eb2e8f9f7	5478	* @rmtoll CCR DUAL LL_ADC_GetMultimode
<>	144:ef7eb2e8f9f7	5479	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	5480	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	5481	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	5482	* @arg @ref LL_ADC_MULTI_INDEPENDENT
<>	144:ef7eb2e8f9f7	5483	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
<>	144:ef7eb2e8f9f7	5484	* @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
<>	144:ef7eb2e8f9f7	5485	* @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
<>	144:ef7eb2e8f9f7	5486	* @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
<>	144:ef7eb2e8f9f7	5487	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
<>	144:ef7eb2e8f9f7	5488	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
<>	144:ef7eb2e8f9f7	5489	* @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
<>	144:ef7eb2e8f9f7	5490	*/
<>	144:ef7eb2e8f9f7	5491	__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
<>	144:ef7eb2e8f9f7	5492	{
<>	144:ef7eb2e8f9f7	5493	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
<>	144:ef7eb2e8f9f7	5494	}
<>	144:ef7eb2e8f9f7	5495
<>	144:ef7eb2e8f9f7	5496	/**
<>	144:ef7eb2e8f9f7	5497	* @brief Set ADC multimode conversion data transfer: no transfer
<>	144:ef7eb2e8f9f7	5498	* or transfer by DMA.
<>	144:ef7eb2e8f9f7	5499	* @note If ADC multimode transfer by DMA is not selected:
<>	144:ef7eb2e8f9f7	5500	* each ADC uses its own DMA channel, with its individual
<>	144:ef7eb2e8f9f7	5501	* DMA transfer settings.
<>	144:ef7eb2e8f9f7	5502	* If ADC multimode transfer by DMA is selected:
<>	144:ef7eb2e8f9f7	5503	* One DMA channel is used for both ADC (DMA of ADC master)
<>	144:ef7eb2e8f9f7	5504	* Specifies the DMA requests mode:
<>	144:ef7eb2e8f9f7	5505	* - Limited mode (One shot mode): DMA transfer requests are stopped
<>	144:ef7eb2e8f9f7	5506	* when number of DMA data transfers (number of
<>	144:ef7eb2e8f9f7	5507	* ADC conversions) is reached.
<>	144:ef7eb2e8f9f7	5508	* This ADC mode is intended to be used with DMA mode non-circular.
<>	144:ef7eb2e8f9f7	5509	* - Unlimited mode: DMA transfer requests are unlimited,
<>	144:ef7eb2e8f9f7	5510	* whatever number of DMA data transfers (number of
<>	144:ef7eb2e8f9f7	5511	* ADC conversions).
<>	144:ef7eb2e8f9f7	5512	* This ADC mode is intended to be used with DMA mode circular.
<>	144:ef7eb2e8f9f7	5513	* @note If ADC DMA requests mode is set to unlimited and DMA is set to
<>	144:ef7eb2e8f9f7	5514	* mode non-circular:
<>	144:ef7eb2e8f9f7	5515	* when DMA transfers size will be reached, DMA will stop transfers of
<>	144:ef7eb2e8f9f7	5516	* ADC conversions data ADC will raise an overrun error
<>	144:ef7eb2e8f9f7	5517	* (overrun flag and interruption if enabled).
<>	144:ef7eb2e8f9f7	5518	* @note How to retrieve multimode conversion data:
<>	144:ef7eb2e8f9f7	5519	* Whatever multimode transfer by DMA setting: using function
<>	144:ef7eb2e8f9f7	5520	* @ref LL_ADC_REG_ReadMultiConversionData32().
<>	144:ef7eb2e8f9f7	5521	* If ADC multimode transfer by DMA is selected: conversion data
<>	144:ef7eb2e8f9f7	5522	* is a raw data with ADC master and slave concatenated.
<>	144:ef7eb2e8f9f7	5523	* A macro is available to get the conversion data of
<>	144:ef7eb2e8f9f7	5524	* ADC master or ADC slave: see helper macro
<>	144:ef7eb2e8f9f7	5525	* @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
<>	144:ef7eb2e8f9f7	5526	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	5527	* ADC state:
<>	144:ef7eb2e8f9f7	5528	* All ADC instances of the ADC common group must be disabled
<>	144:ef7eb2e8f9f7	5529	* or enabled without conversion on going on group regular.
<>	144:ef7eb2e8f9f7	5530	* @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
<>	144:ef7eb2e8f9f7	5531	* CCR DMACFG LL_ADC_SetMultiDMATransfer
<>	144:ef7eb2e8f9f7	5532	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	5533	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	5534	* @param MultiDMATransfer This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5535	* @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
<>	144:ef7eb2e8f9f7	5536	* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
<>	144:ef7eb2e8f9f7	5537	* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
<>	144:ef7eb2e8f9f7	5538	* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
<>	144:ef7eb2e8f9f7	5539	* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
<>	144:ef7eb2e8f9f7	5540	* @retval None
<>	144:ef7eb2e8f9f7	5541	*/
<>	144:ef7eb2e8f9f7	5542	__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
<>	144:ef7eb2e8f9f7	5543	{
<>	144:ef7eb2e8f9f7	5544	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA \| ADC_CCR_DMACFG, MultiDMATransfer);
<>	144:ef7eb2e8f9f7	5545	}
<>	144:ef7eb2e8f9f7	5546
<>	144:ef7eb2e8f9f7	5547	/**
<>	144:ef7eb2e8f9f7	5548	* @brief Get ADC multimode conversion data transfer: no transfer
<>	144:ef7eb2e8f9f7	5549	* or transfer by DMA.
<>	144:ef7eb2e8f9f7	5550	* @note If ADC multimode transfer by DMA is not selected:
<>	144:ef7eb2e8f9f7	5551	* each ADC uses its own DMA channel, with its individual
<>	144:ef7eb2e8f9f7	5552	* DMA transfer settings.
<>	144:ef7eb2e8f9f7	5553	* If ADC multimode transfer by DMA is selected:
<>	144:ef7eb2e8f9f7	5554	* One DMA channel is used for both ADC (DMA of ADC master)
<>	144:ef7eb2e8f9f7	5555	* Specifies the DMA requests mode:
<>	144:ef7eb2e8f9f7	5556	* - Limited mode (One shot mode): DMA transfer requests are stopped
<>	144:ef7eb2e8f9f7	5557	* when number of DMA data transfers (number of
<>	144:ef7eb2e8f9f7	5558	* ADC conversions) is reached.
<>	144:ef7eb2e8f9f7	5559	* This ADC mode is intended to be used with DMA mode non-circular.
<>	144:ef7eb2e8f9f7	5560	* - Unlimited mode: DMA transfer requests are unlimited,
<>	144:ef7eb2e8f9f7	5561	* whatever number of DMA data transfers (number of
<>	144:ef7eb2e8f9f7	5562	* ADC conversions).
<>	144:ef7eb2e8f9f7	5563	* This ADC mode is intended to be used with DMA mode circular.
<>	144:ef7eb2e8f9f7	5564	* @note If ADC DMA requests mode is set to unlimited and DMA is set to
<>	144:ef7eb2e8f9f7	5565	* mode non-circular:
<>	144:ef7eb2e8f9f7	5566	* when DMA transfers size will be reached, DMA will stop transfers of
<>	144:ef7eb2e8f9f7	5567	* ADC conversions data ADC will raise an overrun error
<>	144:ef7eb2e8f9f7	5568	* (overrun flag and interruption if enabled).
<>	144:ef7eb2e8f9f7	5569	* @note How to retrieve multimode conversion data:
<>	144:ef7eb2e8f9f7	5570	* Whatever multimode transfer by DMA setting: using function
<>	144:ef7eb2e8f9f7	5571	* @ref LL_ADC_REG_ReadMultiConversionData32().
<>	144:ef7eb2e8f9f7	5572	* If ADC multimode transfer by DMA is selected: conversion data
<>	144:ef7eb2e8f9f7	5573	* is a raw data with ADC master and slave concatenated.
<>	144:ef7eb2e8f9f7	5574	* A macro is available to get the conversion data of
<>	144:ef7eb2e8f9f7	5575	* ADC master or ADC slave: see helper macro
<>	144:ef7eb2e8f9f7	5576	* @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
<>	144:ef7eb2e8f9f7	5577	* @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
<>	144:ef7eb2e8f9f7	5578	* CCR DMACFG LL_ADC_GetMultiDMATransfer
<>	144:ef7eb2e8f9f7	5579	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	5580	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	5581	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	5582	* @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
<>	144:ef7eb2e8f9f7	5583	* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
<>	144:ef7eb2e8f9f7	5584	* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
<>	144:ef7eb2e8f9f7	5585	* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
<>	144:ef7eb2e8f9f7	5586	* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
<>	144:ef7eb2e8f9f7	5587	*/
<>	144:ef7eb2e8f9f7	5588	__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
<>	144:ef7eb2e8f9f7	5589	{
<>	144:ef7eb2e8f9f7	5590	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA \| ADC_CCR_DMACFG));
<>	144:ef7eb2e8f9f7	5591	}
<>	144:ef7eb2e8f9f7	5592
<>	144:ef7eb2e8f9f7	5593	/**
<>	144:ef7eb2e8f9f7	5594	* @brief Set ADC multimode delay between 2 sampling phases.
<>	144:ef7eb2e8f9f7	5595	* @note The sampling delay range depends on ADC resolution:
<>	144:ef7eb2e8f9f7	5596	* - ADC resolution 12 bits can have maximum delay of 12 cycles.
<>	144:ef7eb2e8f9f7	5597	* - ADC resolution 10 bits can have maximum delay of 10 cycles.
<>	144:ef7eb2e8f9f7	5598	* - ADC resolution 8 bits can have maximum delay of 8 cycles.
<>	144:ef7eb2e8f9f7	5599	* - ADC resolution 6 bits can have maximum delay of 6 cycles.
<>	144:ef7eb2e8f9f7	5600	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	5601	* ADC state:
<>	144:ef7eb2e8f9f7	5602	* All ADC instances of the ADC common group must be disabled.
<>	144:ef7eb2e8f9f7	5603	* This check can be done with function @ref LL_ADC_IsEnabled() for each
<>	144:ef7eb2e8f9f7	5604	* ADC instance or by using helper macro helper macro
<>	144:ef7eb2e8f9f7	5605	* @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
<>	144:ef7eb2e8f9f7	5606	* @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
<>	144:ef7eb2e8f9f7	5607	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	5608	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	5609	* @param MultiTwoSamplingDelay This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5610	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
<>	144:ef7eb2e8f9f7	5611	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
<>	144:ef7eb2e8f9f7	5612	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
<>	144:ef7eb2e8f9f7	5613	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
<>	144:ef7eb2e8f9f7	5614	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
<>	144:ef7eb2e8f9f7	5615	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
<>	144:ef7eb2e8f9f7	5616	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
<>	144:ef7eb2e8f9f7	5617	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
<>	144:ef7eb2e8f9f7	5618	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
<>	144:ef7eb2e8f9f7	5619	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
<>	144:ef7eb2e8f9f7	5620	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
<>	144:ef7eb2e8f9f7	5621	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
<>	144:ef7eb2e8f9f7	5622	*
<>	144:ef7eb2e8f9f7	5623	* (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
<>	144:ef7eb2e8f9f7	5624	* (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
<>	144:ef7eb2e8f9f7	5625	* (3) Parameter available only if ADC resolution is 12 bits.
<>	144:ef7eb2e8f9f7	5626	* @retval None
<>	144:ef7eb2e8f9f7	5627	*/
<>	144:ef7eb2e8f9f7	5628	__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
<>	144:ef7eb2e8f9f7	5629	{
<>	144:ef7eb2e8f9f7	5630	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
<>	144:ef7eb2e8f9f7	5631	}
<>	144:ef7eb2e8f9f7	5632
<>	144:ef7eb2e8f9f7	5633	/**
<>	144:ef7eb2e8f9f7	5634	* @brief Get ADC multimode delay between 2 sampling phases.
<>	144:ef7eb2e8f9f7	5635	* @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
<>	144:ef7eb2e8f9f7	5636	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	5637	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	5638	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	5639	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
<>	144:ef7eb2e8f9f7	5640	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
<>	144:ef7eb2e8f9f7	5641	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
<>	144:ef7eb2e8f9f7	5642	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
<>	144:ef7eb2e8f9f7	5643	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
<>	144:ef7eb2e8f9f7	5644	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
<>	144:ef7eb2e8f9f7	5645	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
<>	144:ef7eb2e8f9f7	5646	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
<>	144:ef7eb2e8f9f7	5647	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
<>	144:ef7eb2e8f9f7	5648	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
<>	144:ef7eb2e8f9f7	5649	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
<>	144:ef7eb2e8f9f7	5650	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
<>	144:ef7eb2e8f9f7	5651	*
<>	144:ef7eb2e8f9f7	5652	* (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
<>	144:ef7eb2e8f9f7	5653	* (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
<>	144:ef7eb2e8f9f7	5654	* (3) Parameter available only if ADC resolution is 12 bits.
<>	144:ef7eb2e8f9f7	5655	*/
<>	144:ef7eb2e8f9f7	5656	__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
<>	144:ef7eb2e8f9f7	5657	{
<>	144:ef7eb2e8f9f7	5658	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
<>	144:ef7eb2e8f9f7	5659	}
<>	144:ef7eb2e8f9f7	5660	#endif /* ADC_MULTIMODE_SUPPORT */
<>	144:ef7eb2e8f9f7	5661
<>	144:ef7eb2e8f9f7	5662	/**
<>	144:ef7eb2e8f9f7	5663	* @}
<>	144:ef7eb2e8f9f7	5664	*/
<>	144:ef7eb2e8f9f7	5665	/** @defgroup ADC_LL_EF_Configuration_Leg_Functions Configuration of ADC alternate functions name
<>	144:ef7eb2e8f9f7	5666	* @{
<>	144:ef7eb2e8f9f7	5667	*/
<>	144:ef7eb2e8f9f7	5668	/* Old functions name kept for legacy purpose, to be replaced by the */
<>	144:ef7eb2e8f9f7	5669	/* current functions name. */
<>	144:ef7eb2e8f9f7	5670	__STATIC_INLINE void LL_ADC_REG_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
<>	144:ef7eb2e8f9f7	5671	{
<>	144:ef7eb2e8f9f7	5672	LL_ADC_REG_SetTrigSource(ADCx, TriggerSource);
<>	144:ef7eb2e8f9f7	5673	}
<>	144:ef7eb2e8f9f7	5674	__STATIC_INLINE void LL_ADC_INJ_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
<>	144:ef7eb2e8f9f7	5675	{
<>	144:ef7eb2e8f9f7	5676	LL_ADC_INJ_SetTrigSource(ADCx, TriggerSource);
<>	144:ef7eb2e8f9f7	5677	}
<>	144:ef7eb2e8f9f7	5678
<>	144:ef7eb2e8f9f7	5679	/**
<>	144:ef7eb2e8f9f7	5680	* @}
<>	144:ef7eb2e8f9f7	5681	*/
<>	144:ef7eb2e8f9f7	5682
<>	144:ef7eb2e8f9f7	5683	/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
<>	144:ef7eb2e8f9f7	5684	* @{
<>	144:ef7eb2e8f9f7	5685	*/
<>	144:ef7eb2e8f9f7	5686
<>	144:ef7eb2e8f9f7	5687	/**
<>	144:ef7eb2e8f9f7	5688	* @brief Put ADC instance in deep power down state.
<>	144:ef7eb2e8f9f7	5689	* @note In case of ADC calibration necessary: When ADC is in deep-power-down
<>	144:ef7eb2e8f9f7	5690	* state, the internal analog calibration is lost. After exiting from
<>	144:ef7eb2e8f9f7	5691	* deep power down, calibration must be relaunched or calibration factor
<>	144:ef7eb2e8f9f7	5692	* (preliminarily saved) must be set back into calibration register.
<>	144:ef7eb2e8f9f7	5693	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	5694	* ADC state:
<>	144:ef7eb2e8f9f7	5695	* ADC must be ADC disabled.
<>	144:ef7eb2e8f9f7	5696	* @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
<>	144:ef7eb2e8f9f7	5697	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	5698	* @retval None
<>	144:ef7eb2e8f9f7	5699	*/
<>	144:ef7eb2e8f9f7	5700	__STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	5701	{
<>	144:ef7eb2e8f9f7	5702	/* Note: Write register with some additional bits forced to state reset */
<>	144:ef7eb2e8f9f7	5703	/* instead of modifying only the selected bit for this function, */
<>	144:ef7eb2e8f9f7	5704	/* to not interfere with bits with HW property "rs". */
<>	144:ef7eb2e8f9f7	5705	MODIFY_REG(ADCx->CR,
<>	144:ef7eb2e8f9f7	5706	ADC_CR_BITS_PROPERTY_RS,
<>	144:ef7eb2e8f9f7	5707	ADC_CR_DEEPPWD);
<>	144:ef7eb2e8f9f7	5708	}
<>	144:ef7eb2e8f9f7	5709
<>	144:ef7eb2e8f9f7	5710	/**
<>	144:ef7eb2e8f9f7	5711	* @brief Disable ADC deep power down mode.
<>	144:ef7eb2e8f9f7	5712	* @note In case of ADC calibration necessary: When ADC is in deep-power-down
<>	144:ef7eb2e8f9f7	5713	* state, the internal analog calibration is lost. After exiting from
<>	144:ef7eb2e8f9f7	5714	* deep power down, calibration must be relaunched or calibration factor
<>	144:ef7eb2e8f9f7	5715	* (preliminarily saved) must be set back into calibration register.
<>	144:ef7eb2e8f9f7	5716	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	5717	* ADC state:
<>	144:ef7eb2e8f9f7	5718	* ADC must be ADC disabled.
<>	144:ef7eb2e8f9f7	5719	* @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
<>	144:ef7eb2e8f9f7	5720	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	5721	* @retval None
<>	144:ef7eb2e8f9f7	5722	*/
<>	144:ef7eb2e8f9f7	5723	__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	5724	{
<>	144:ef7eb2e8f9f7	5725	/* Note: Write register with some additional bits forced to state reset */
<>	144:ef7eb2e8f9f7	5726	/* instead of modifying only the selected bit for this function, */
<>	144:ef7eb2e8f9f7	5727	/* to not interfere with bits with HW property "rs". */
<>	144:ef7eb2e8f9f7	5728	CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD \| ADC_CR_BITS_PROPERTY_RS));
<>	144:ef7eb2e8f9f7	5729	}
<>	144:ef7eb2e8f9f7	5730
<>	144:ef7eb2e8f9f7	5731	/**
<>	144:ef7eb2e8f9f7	5732	* @brief Get the selected ADC instance deep power down state.
<>	144:ef7eb2e8f9f7	5733	* @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
<>	144:ef7eb2e8f9f7	5734	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	5735	* @retval 0: deep power down is disabled, 1: deep power down is enabled.
<>	144:ef7eb2e8f9f7	5736	*/
<>	144:ef7eb2e8f9f7	5737	__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	5738	{
<>	144:ef7eb2e8f9f7	5739	return (READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD));
<>	144:ef7eb2e8f9f7	5740	}
<>	144:ef7eb2e8f9f7	5741
<>	144:ef7eb2e8f9f7	5742	/**
<>	144:ef7eb2e8f9f7	5743	* @brief Enable ADC instance internal voltage regulator.
<>	144:ef7eb2e8f9f7	5744	* @note On this STM32 serie, after ADC internal voltage regulator enable,
<>	144:ef7eb2e8f9f7	5745	* a delay for ADC internal voltage regulator stabilization
<>	144:ef7eb2e8f9f7	5746	* is required before performing a ADC calibration or ADC enable.
<>	144:ef7eb2e8f9f7	5747	* Refer to device datasheet, parameter tADCVREG_STUP.
<>	144:ef7eb2e8f9f7	5748	* Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
<>	144:ef7eb2e8f9f7	5749	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	5750	* ADC state:
<>	144:ef7eb2e8f9f7	5751	* ADC must be ADC disabled.
<>	144:ef7eb2e8f9f7	5752	* @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
<>	144:ef7eb2e8f9f7	5753	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	5754	* @retval None
<>	144:ef7eb2e8f9f7	5755	*/
<>	144:ef7eb2e8f9f7	5756	__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	5757	{
<>	144:ef7eb2e8f9f7	5758	/* Note: Write register with some additional bits forced to state reset */
<>	144:ef7eb2e8f9f7	5759	/* instead of modifying only the selected bit for this function, */
<>	144:ef7eb2e8f9f7	5760	/* to not interfere with bits with HW property "rs". */
<>	144:ef7eb2e8f9f7	5761	MODIFY_REG(ADCx->CR,
<>	144:ef7eb2e8f9f7	5762	ADC_CR_BITS_PROPERTY_RS,
<>	144:ef7eb2e8f9f7	5763	ADC_CR_ADVREGEN);
<>	144:ef7eb2e8f9f7	5764	}
<>	144:ef7eb2e8f9f7	5765
<>	144:ef7eb2e8f9f7	5766	/**
<>	144:ef7eb2e8f9f7	5767	* @brief Disable ADC internal voltage regulator.
<>	144:ef7eb2e8f9f7	5768	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	5769	* ADC state:
<>	144:ef7eb2e8f9f7	5770	* ADC must be ADC disabled.
<>	144:ef7eb2e8f9f7	5771	* @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
<>	144:ef7eb2e8f9f7	5772	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	5773	* @retval None
<>	144:ef7eb2e8f9f7	5774	*/
<>	144:ef7eb2e8f9f7	5775	__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	5776	{
<>	144:ef7eb2e8f9f7	5777	CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN \| ADC_CR_BITS_PROPERTY_RS));
<>	144:ef7eb2e8f9f7	5778	}
<>	144:ef7eb2e8f9f7	5779
<>	144:ef7eb2e8f9f7	5780	/**
<>	144:ef7eb2e8f9f7	5781	* @brief Get the selected ADC instance internal voltage regulator state.
<>	144:ef7eb2e8f9f7	5782	* @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
<>	144:ef7eb2e8f9f7	5783	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	5784	* @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
<>	144:ef7eb2e8f9f7	5785	*/
<>	144:ef7eb2e8f9f7	5786	__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	5787	{
<>	144:ef7eb2e8f9f7	5788	return (READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN));
<>	144:ef7eb2e8f9f7	5789	}
<>	144:ef7eb2e8f9f7	5790
<>	144:ef7eb2e8f9f7	5791	/**
<>	144:ef7eb2e8f9f7	5792	* @brief Enable the selected ADC instance.
<>	144:ef7eb2e8f9f7	5793	* @note On this STM32 serie, after ADC enable, a delay for
<>	144:ef7eb2e8f9f7	5794	* ADC internal analog stabilization is required before performing a
<>	144:ef7eb2e8f9f7	5795	* ADC conversion start.
<>	144:ef7eb2e8f9f7	5796	* Refer to device datasheet, parameter tSTAB.
<>	144:ef7eb2e8f9f7	5797	* @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
<>	144:ef7eb2e8f9f7	5798	* is enabled and when conversion clock is active.
<>	144:ef7eb2e8f9f7	5799	* (not only core clock: this ADC has a dual clock domain)
<>	144:ef7eb2e8f9f7	5800	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	5801	* ADC state:
<>	144:ef7eb2e8f9f7	5802	* ADC must be ADC disabled and ADC internal voltage regulator enabled.
<>	144:ef7eb2e8f9f7	5803	* @rmtoll CR ADEN LL_ADC_Enable
<>	144:ef7eb2e8f9f7	5804	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	5805	* @retval None
<>	144:ef7eb2e8f9f7	5806	*/
<>	144:ef7eb2e8f9f7	5807	__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	5808	{
<>	144:ef7eb2e8f9f7	5809	/* Note: Write register with some additional bits forced to state reset */
<>	144:ef7eb2e8f9f7	5810	/* instead of modifying only the selected bit for this function, */
<>	144:ef7eb2e8f9f7	5811	/* to not interfere with bits with HW property "rs". */
<>	144:ef7eb2e8f9f7	5812	MODIFY_REG(ADCx->CR,
<>	144:ef7eb2e8f9f7	5813	ADC_CR_BITS_PROPERTY_RS,
<>	144:ef7eb2e8f9f7	5814	ADC_CR_ADEN);
<>	144:ef7eb2e8f9f7	5815	}
<>	144:ef7eb2e8f9f7	5816
<>	144:ef7eb2e8f9f7	5817	/**
<>	144:ef7eb2e8f9f7	5818	* @brief Disable the selected ADC instance.
<>	144:ef7eb2e8f9f7	5819	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	5820	* ADC state:
<>	144:ef7eb2e8f9f7	5821	* ADC must be not disabled. Must be enabled without conversion on going
<>	144:ef7eb2e8f9f7	5822	* on either groups regular or injected.
<>	144:ef7eb2e8f9f7	5823	* @rmtoll CR ADDIS LL_ADC_Disable
<>	144:ef7eb2e8f9f7	5824	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	5825	* @retval None
<>	144:ef7eb2e8f9f7	5826	*/
<>	144:ef7eb2e8f9f7	5827	__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	5828	{
<>	144:ef7eb2e8f9f7	5829	/* Note: Write register with some additional bits forced to state reset */
<>	144:ef7eb2e8f9f7	5830	/* instead of modifying only the selected bit for this function, */
<>	144:ef7eb2e8f9f7	5831	/* to not interfere with bits with HW property "rs". */
<>	144:ef7eb2e8f9f7	5832	MODIFY_REG(ADCx->CR,
<>	144:ef7eb2e8f9f7	5833	ADC_CR_BITS_PROPERTY_RS,
<>	144:ef7eb2e8f9f7	5834	ADC_CR_ADDIS);
<>	144:ef7eb2e8f9f7	5835	}
<>	144:ef7eb2e8f9f7	5836
<>	144:ef7eb2e8f9f7	5837	/**
<>	144:ef7eb2e8f9f7	5838	* @brief Get the selected ADC instance enable state.
<>	144:ef7eb2e8f9f7	5839	* @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
<>	144:ef7eb2e8f9f7	5840	* is enabled and when conversion clock is active.
<>	144:ef7eb2e8f9f7	5841	* (not only core clock: this ADC has a dual clock domain)
<>	144:ef7eb2e8f9f7	5842	* @rmtoll CR ADEN LL_ADC_IsEnabled
<>	144:ef7eb2e8f9f7	5843	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	5844	* @retval 0: ADC is disabled, 1: ADC is enabled.
<>	144:ef7eb2e8f9f7	5845	*/
<>	144:ef7eb2e8f9f7	5846	__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	5847	{
<>	144:ef7eb2e8f9f7	5848	return (READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN));
<>	144:ef7eb2e8f9f7	5849	}
<>	144:ef7eb2e8f9f7	5850
<>	144:ef7eb2e8f9f7	5851	/**
<>	144:ef7eb2e8f9f7	5852	* @brief Get the selected ADC instance disable state.
<>	144:ef7eb2e8f9f7	5853	* @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
<>	144:ef7eb2e8f9f7	5854	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	5855	* @retval 0: no ADC disable command on going.
<>	144:ef7eb2e8f9f7	5856	*/
<>	144:ef7eb2e8f9f7	5857	__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	5858	{
<>	144:ef7eb2e8f9f7	5859	return (READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS));
<>	144:ef7eb2e8f9f7	5860	}
<>	144:ef7eb2e8f9f7	5861
<>	144:ef7eb2e8f9f7	5862	/**
<>	144:ef7eb2e8f9f7	5863	* @brief Start ADC calibration in the mode single-ended
<>	144:ef7eb2e8f9f7	5864	* or differential (for devices with differential mode available).
<>	144:ef7eb2e8f9f7	5865	* @note On this STM32 serie, a minimum number of ADC clock cycles
<>	144:ef7eb2e8f9f7	5866	* are required between ADC end of calibration and ADC enable.
<>	144:ef7eb2e8f9f7	5867	* Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
<>	144:ef7eb2e8f9f7	5868	* @note For devices with differential mode available:
<>	144:ef7eb2e8f9f7	5869	* Calibration of offset is specific to each of
<>	144:ef7eb2e8f9f7	5870	* single-ended and differential modes
<>	144:ef7eb2e8f9f7	5871	* (calibration run must be performed for each of these
<>	144:ef7eb2e8f9f7	5872	* differential modes, if used afterwards and if the application
<>	144:ef7eb2e8f9f7	5873	* requires their calibration).
<>	144:ef7eb2e8f9f7	5874	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	5875	* ADC state:
<>	144:ef7eb2e8f9f7	5876	* ADC must be ADC disabled.
<>	144:ef7eb2e8f9f7	5877	* @rmtoll CR ADCAL LL_ADC_StartCalibration\n
<>	144:ef7eb2e8f9f7	5878	* CR ADCALDIF LL_ADC_StartCalibration
<>	144:ef7eb2e8f9f7	5879	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	5880	* @param SingleDiff This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5881	* @arg @ref LL_ADC_SINGLE_ENDED
<>	144:ef7eb2e8f9f7	5882	* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
<>	144:ef7eb2e8f9f7	5883	* @retval None
<>	144:ef7eb2e8f9f7	5884	*/
<>	144:ef7eb2e8f9f7	5885	__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
<>	144:ef7eb2e8f9f7	5886	{
<>	144:ef7eb2e8f9f7	5887	/* Note: Write register with some additional bits forced to state reset */
<>	144:ef7eb2e8f9f7	5888	/* instead of modifying only the selected bit for this function, */
<>	144:ef7eb2e8f9f7	5889	/* to not interfere with bits with HW property "rs". */
<>	144:ef7eb2e8f9f7	5890	MODIFY_REG(ADCx->CR,
<>	144:ef7eb2e8f9f7	5891	ADC_CR_ADCALDIF \| ADC_CR_BITS_PROPERTY_RS,
<>	144:ef7eb2e8f9f7	5892	ADC_CR_ADCAL \| (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
<>	144:ef7eb2e8f9f7	5893	}
<>	144:ef7eb2e8f9f7	5894
<>	144:ef7eb2e8f9f7	5895	/**
<>	144:ef7eb2e8f9f7	5896	* @brief Get ADC calibration state.
<>	144:ef7eb2e8f9f7	5897	* @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
<>	144:ef7eb2e8f9f7	5898	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	5899	* @retval 0: calibration complete, 1: calibration in progress.
<>	144:ef7eb2e8f9f7	5900	*/
<>	144:ef7eb2e8f9f7	5901	__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	5902	{
<>	144:ef7eb2e8f9f7	5903	return (READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL));
<>	144:ef7eb2e8f9f7	5904	}
<>	144:ef7eb2e8f9f7	5905
<>	144:ef7eb2e8f9f7	5906	/**
<>	144:ef7eb2e8f9f7	5907	* @}
<>	144:ef7eb2e8f9f7	5908	*/
<>	144:ef7eb2e8f9f7	5909
<>	144:ef7eb2e8f9f7	5910	/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
<>	144:ef7eb2e8f9f7	5911	* @{
<>	144:ef7eb2e8f9f7	5912	*/
<>	144:ef7eb2e8f9f7	5913
<>	144:ef7eb2e8f9f7	5914	/**
<>	144:ef7eb2e8f9f7	5915	* @brief Start ADC group regular conversion.
<>	144:ef7eb2e8f9f7	5916	* @note On this STM32 serie, this function is relevant for both
<>	144:ef7eb2e8f9f7	5917	* internal trigger (SW start) and external trigger:
<>	144:ef7eb2e8f9f7	5918	* - If ADC trigger has been set to software start, ADC conversion
<>	144:ef7eb2e8f9f7	5919	* starts immediately.
<>	144:ef7eb2e8f9f7	5920	* - If ADC trigger has been set to external trigger, ADC conversion
<>	144:ef7eb2e8f9f7	5921	* will start at next trigger event (on the selected trigger edge)
<>	144:ef7eb2e8f9f7	5922	* following the ADC start conversion command.
<>	144:ef7eb2e8f9f7	5923	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	5924	* ADC state:
<>	144:ef7eb2e8f9f7	5925	* ADC must be enabled without conversion on going on group regular,
<>	144:ef7eb2e8f9f7	5926	* without conversion stop command on going on group regular.
<>	144:ef7eb2e8f9f7	5927	* @rmtoll CR ADSTART LL_ADC_REG_StartConversion
<>	144:ef7eb2e8f9f7	5928	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	5929	* @retval None
<>	144:ef7eb2e8f9f7	5930	*/
<>	144:ef7eb2e8f9f7	5931	__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	5932	{
<>	144:ef7eb2e8f9f7	5933	/* Note: Write register with some additional bits forced to state reset */
<>	144:ef7eb2e8f9f7	5934	/* instead of modifying only the selected bit for this function, */
<>	144:ef7eb2e8f9f7	5935	/* to not interfere with bits with HW property "rs". */
<>	144:ef7eb2e8f9f7	5936	MODIFY_REG(ADCx->CR,
<>	144:ef7eb2e8f9f7	5937	ADC_CR_BITS_PROPERTY_RS,
<>	144:ef7eb2e8f9f7	5938	ADC_CR_ADSTART);
<>	144:ef7eb2e8f9f7	5939	}
<>	144:ef7eb2e8f9f7	5940
<>	144:ef7eb2e8f9f7	5941	/**
<>	144:ef7eb2e8f9f7	5942	* @brief Stop ADC group regular conversion.
<>	144:ef7eb2e8f9f7	5943	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	5944	* ADC state:
<>	144:ef7eb2e8f9f7	5945	* ADC must be enabled with conversion on going on group regular,
<>	144:ef7eb2e8f9f7	5946	* without ADC disable command on going.
<>	144:ef7eb2e8f9f7	5947	* @rmtoll CR ADSTP LL_ADC_REG_StopConversion
<>	144:ef7eb2e8f9f7	5948	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	5949	* @retval None
<>	144:ef7eb2e8f9f7	5950	*/
<>	144:ef7eb2e8f9f7	5951	__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	5952	{
<>	144:ef7eb2e8f9f7	5953	/* Note: Write register with some additional bits forced to state reset */
<>	144:ef7eb2e8f9f7	5954	/* instead of modifying only the selected bit for this function, */
<>	144:ef7eb2e8f9f7	5955	/* to not interfere with bits with HW property "rs". */
<>	144:ef7eb2e8f9f7	5956	MODIFY_REG(ADCx->CR,
<>	144:ef7eb2e8f9f7	5957	ADC_CR_BITS_PROPERTY_RS,
<>	144:ef7eb2e8f9f7	5958	ADC_CR_ADSTP);
<>	144:ef7eb2e8f9f7	5959	}
<>	144:ef7eb2e8f9f7	5960
<>	144:ef7eb2e8f9f7	5961	/**
<>	144:ef7eb2e8f9f7	5962	* @brief Get ADC group regular conversion state.
<>	144:ef7eb2e8f9f7	5963	* @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
<>	144:ef7eb2e8f9f7	5964	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	5965	* @retval 0: no conversion is on going on ADC group regular.
<>	144:ef7eb2e8f9f7	5966	*/
<>	144:ef7eb2e8f9f7	5967	__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	5968	{
<>	144:ef7eb2e8f9f7	5969	return (READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART));
<>	144:ef7eb2e8f9f7	5970	}
<>	144:ef7eb2e8f9f7	5971
<>	144:ef7eb2e8f9f7	5972	/**
<>	144:ef7eb2e8f9f7	5973	* @brief Get ADC group regular command of conversion stop state
<>	144:ef7eb2e8f9f7	5974	* @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
<>	144:ef7eb2e8f9f7	5975	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	5976	* @retval 0: no command of conversion stop is on going on ADC group regular.
<>	144:ef7eb2e8f9f7	5977	*/
<>	144:ef7eb2e8f9f7	5978	__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	5979	{
<>	144:ef7eb2e8f9f7	5980	return (READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP));
<>	144:ef7eb2e8f9f7	5981	}
<>	144:ef7eb2e8f9f7	5982
<>	144:ef7eb2e8f9f7	5983	/**
<>	144:ef7eb2e8f9f7	5984	* @brief Get ADC group regular conversion data, range fit for
<>	144:ef7eb2e8f9f7	5985	* all ADC configurations: all ADC resolutions and
<>	144:ef7eb2e8f9f7	5986	* all oversampling increased data width (for devices
<>	144:ef7eb2e8f9f7	5987	* with feature oversampling).
<>	144:ef7eb2e8f9f7	5988	* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
<>	144:ef7eb2e8f9f7	5989	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	5990	* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
<>	144:ef7eb2e8f9f7	5991	*/
<>	144:ef7eb2e8f9f7	5992	__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	5993	{
<>	144:ef7eb2e8f9f7	5994	return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
<>	144:ef7eb2e8f9f7	5995	}
<>	144:ef7eb2e8f9f7	5996
<>	144:ef7eb2e8f9f7	5997	/**
<>	144:ef7eb2e8f9f7	5998	* @brief Get ADC group regular conversion data, range fit for
<>	144:ef7eb2e8f9f7	5999	* ADC resolution 12 bits.
<>	144:ef7eb2e8f9f7	6000	* @note For devices with feature oversampling: Oversampling
<>	144:ef7eb2e8f9f7	6001	* can increase data width, function for extended range
<>	144:ef7eb2e8f9f7	6002	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
<>	144:ef7eb2e8f9f7	6003	* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
<>	144:ef7eb2e8f9f7	6004	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6005	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	144:ef7eb2e8f9f7	6006	*/
<>	144:ef7eb2e8f9f7	6007	__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6008	{
<>	144:ef7eb2e8f9f7	6009	return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
<>	144:ef7eb2e8f9f7	6010	}
<>	144:ef7eb2e8f9f7	6011
<>	144:ef7eb2e8f9f7	6012	/**
<>	144:ef7eb2e8f9f7	6013	* @brief Get ADC group regular conversion data, range fit for
<>	144:ef7eb2e8f9f7	6014	* ADC resolution 10 bits.
<>	144:ef7eb2e8f9f7	6015	* @note For devices with feature oversampling: Oversampling
<>	144:ef7eb2e8f9f7	6016	* can increase data width, function for extended range
<>	144:ef7eb2e8f9f7	6017	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
<>	144:ef7eb2e8f9f7	6018	* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
<>	144:ef7eb2e8f9f7	6019	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6020	* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
<>	144:ef7eb2e8f9f7	6021	*/
<>	144:ef7eb2e8f9f7	6022	__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6023	{
<>	144:ef7eb2e8f9f7	6024	return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
<>	144:ef7eb2e8f9f7	6025	}
<>	144:ef7eb2e8f9f7	6026
<>	144:ef7eb2e8f9f7	6027	/**
<>	144:ef7eb2e8f9f7	6028	* @brief Get ADC group regular conversion data, range fit for
<>	144:ef7eb2e8f9f7	6029	* ADC resolution 8 bits.
<>	144:ef7eb2e8f9f7	6030	* @note For devices with feature oversampling: Oversampling
<>	144:ef7eb2e8f9f7	6031	* can increase data width, function for extended range
<>	144:ef7eb2e8f9f7	6032	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
<>	144:ef7eb2e8f9f7	6033	* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
<>	144:ef7eb2e8f9f7	6034	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6035	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	144:ef7eb2e8f9f7	6036	*/
<>	144:ef7eb2e8f9f7	6037	__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6038	{
<>	144:ef7eb2e8f9f7	6039	return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
<>	144:ef7eb2e8f9f7	6040	}
<>	144:ef7eb2e8f9f7	6041
<>	144:ef7eb2e8f9f7	6042	/**
<>	144:ef7eb2e8f9f7	6043	* @brief Get ADC group regular conversion data, range fit for
<>	144:ef7eb2e8f9f7	6044	* ADC resolution 6 bits.
<>	144:ef7eb2e8f9f7	6045	* @note For devices with feature oversampling: Oversampling
<>	144:ef7eb2e8f9f7	6046	* can increase data width, function for extended range
<>	144:ef7eb2e8f9f7	6047	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
<>	144:ef7eb2e8f9f7	6048	* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
<>	144:ef7eb2e8f9f7	6049	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6050	* @retval Value between Min_Data=0x00 and Max_Data=0x3F
<>	144:ef7eb2e8f9f7	6051	*/
<>	144:ef7eb2e8f9f7	6052	__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6053	{
<>	144:ef7eb2e8f9f7	6054	return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
<>	144:ef7eb2e8f9f7	6055	}
<>	144:ef7eb2e8f9f7	6056
<>	144:ef7eb2e8f9f7	6057	#if defined(ADC_MULTIMODE_SUPPORT)
<>	144:ef7eb2e8f9f7	6058	/**
<>	144:ef7eb2e8f9f7	6059	* @brief Get ADC multimode conversion data of ADC master, ADC slave
<>	144:ef7eb2e8f9f7	6060	* or raw data with ADC master and slave concatenated.
<>	144:ef7eb2e8f9f7	6061	* @note If raw data with ADC master and slave concatenated is retrieved,
<>	144:ef7eb2e8f9f7	6062	* a macro is available to get the conversion data of
<>	144:ef7eb2e8f9f7	6063	* ADC master or ADC slave: see helper macro
<>	144:ef7eb2e8f9f7	6064	* @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
<>	144:ef7eb2e8f9f7	6065	* (however this macro is mainly intended for multimode
<>	144:ef7eb2e8f9f7	6066	* transfer by DMA, because this function can do the same
<>	144:ef7eb2e8f9f7	6067	* by getting multimode conversion data of ADC master or ADC slave
<>	144:ef7eb2e8f9f7	6068	* separately).
<>	144:ef7eb2e8f9f7	6069	* @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n
<>	144:ef7eb2e8f9f7	6070	* CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
<>	144:ef7eb2e8f9f7	6071	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	6072	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	6073	* @param ConversionData This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	6074	* @arg @ref LL_ADC_MULTI_MASTER
<>	144:ef7eb2e8f9f7	6075	* @arg @ref LL_ADC_MULTI_SLAVE
<>	144:ef7eb2e8f9f7	6076	* @arg @ref LL_ADC_MULTI_MASTER_SLAVE
<>	144:ef7eb2e8f9f7	6077	* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
<>	144:ef7eb2e8f9f7	6078	*/
<>	144:ef7eb2e8f9f7	6079	__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
<>	144:ef7eb2e8f9f7	6080	{
<>	144:ef7eb2e8f9f7	6081	return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
<>	144:ef7eb2e8f9f7	6082	ConversionData)
<>	144:ef7eb2e8f9f7	6083	>> POSITION_VAL(ConversionData)
<>	144:ef7eb2e8f9f7	6084	);
<>	144:ef7eb2e8f9f7	6085	}
<>	144:ef7eb2e8f9f7	6086	#endif /* ADC_MULTIMODE_SUPPORT */
<>	144:ef7eb2e8f9f7	6087
<>	144:ef7eb2e8f9f7	6088	/**
<>	144:ef7eb2e8f9f7	6089	* @}
<>	144:ef7eb2e8f9f7	6090	*/
<>	144:ef7eb2e8f9f7	6091
<>	144:ef7eb2e8f9f7	6092	/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
<>	144:ef7eb2e8f9f7	6093	* @{
<>	144:ef7eb2e8f9f7	6094	*/
<>	144:ef7eb2e8f9f7	6095
<>	144:ef7eb2e8f9f7	6096	/**
<>	144:ef7eb2e8f9f7	6097	* @brief Start ADC group injected conversion.
<>	144:ef7eb2e8f9f7	6098	* @note On this STM32 serie, this function is relevant for both
<>	144:ef7eb2e8f9f7	6099	* internal trigger (SW start) and external trigger:
<>	144:ef7eb2e8f9f7	6100	* - If ADC trigger has been set to software start, ADC conversion
<>	144:ef7eb2e8f9f7	6101	* starts immediately.
<>	144:ef7eb2e8f9f7	6102	* - If ADC trigger has been set to external trigger, ADC conversion
<>	144:ef7eb2e8f9f7	6103	* will start at next trigger event (on the selected trigger edge)
<>	144:ef7eb2e8f9f7	6104	* following the ADC start conversion command.
<>	144:ef7eb2e8f9f7	6105	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	6106	* ADC state:
<>	144:ef7eb2e8f9f7	6107	* ADC must be enabled without conversion on going on group injected,
<>	144:ef7eb2e8f9f7	6108	* without conversion stop command on going on group injected.
<>	144:ef7eb2e8f9f7	6109	* @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
<>	144:ef7eb2e8f9f7	6110	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6111	* @retval None
<>	144:ef7eb2e8f9f7	6112	*/
<>	144:ef7eb2e8f9f7	6113	__STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6114	{
<>	144:ef7eb2e8f9f7	6115	/* Note: Write register with some additional bits forced to state reset */
<>	144:ef7eb2e8f9f7	6116	/* instead of modifying only the selected bit for this function, */
<>	144:ef7eb2e8f9f7	6117	/* to not interfere with bits with HW property "rs". */
<>	144:ef7eb2e8f9f7	6118	MODIFY_REG(ADCx->CR,
<>	144:ef7eb2e8f9f7	6119	ADC_CR_BITS_PROPERTY_RS,
<>	144:ef7eb2e8f9f7	6120	ADC_CR_JADSTART);
<>	144:ef7eb2e8f9f7	6121	}
<>	144:ef7eb2e8f9f7	6122
<>	144:ef7eb2e8f9f7	6123	/**
<>	144:ef7eb2e8f9f7	6124	* @brief Stop ADC group injected conversion.
<>	144:ef7eb2e8f9f7	6125	* @note On this STM32 serie, setting of this feature is conditioned to
<>	144:ef7eb2e8f9f7	6126	* ADC state:
<>	144:ef7eb2e8f9f7	6127	* ADC must be enabled with conversion on going on group injected,
<>	144:ef7eb2e8f9f7	6128	* without ADC disable command on going.
<>	144:ef7eb2e8f9f7	6129	* @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
<>	144:ef7eb2e8f9f7	6130	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6131	* @retval None
<>	144:ef7eb2e8f9f7	6132	*/
<>	144:ef7eb2e8f9f7	6133	__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6134	{
<>	144:ef7eb2e8f9f7	6135	/* Note: Write register with some additional bits forced to state reset */
<>	144:ef7eb2e8f9f7	6136	/* instead of modifying only the selected bit for this function, */
<>	144:ef7eb2e8f9f7	6137	/* to not interfere with bits with HW property "rs". */
<>	144:ef7eb2e8f9f7	6138	MODIFY_REG(ADCx->CR,
<>	144:ef7eb2e8f9f7	6139	ADC_CR_BITS_PROPERTY_RS,
<>	144:ef7eb2e8f9f7	6140	ADC_CR_JADSTP);
<>	144:ef7eb2e8f9f7	6141	}
<>	144:ef7eb2e8f9f7	6142
<>	144:ef7eb2e8f9f7	6143	/**
<>	144:ef7eb2e8f9f7	6144	* @brief Get ADC group injected conversion state.
<>	144:ef7eb2e8f9f7	6145	* @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
<>	144:ef7eb2e8f9f7	6146	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6147	* @retval 0: no conversion is on going on ADC group injected.
<>	144:ef7eb2e8f9f7	6148	*/
<>	144:ef7eb2e8f9f7	6149	__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6150	{
<>	144:ef7eb2e8f9f7	6151	return (READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART));
<>	144:ef7eb2e8f9f7	6152	}
<>	144:ef7eb2e8f9f7	6153
<>	144:ef7eb2e8f9f7	6154	/**
<>	144:ef7eb2e8f9f7	6155	* @brief Get ADC group injected command of conversion stop state
<>	144:ef7eb2e8f9f7	6156	* @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
<>	144:ef7eb2e8f9f7	6157	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6158	* @retval 0: no command of conversion stop is on going on ADC group injected.
<>	144:ef7eb2e8f9f7	6159	*/
<>	144:ef7eb2e8f9f7	6160	__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6161	{
<>	144:ef7eb2e8f9f7	6162	return (READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP));
<>	144:ef7eb2e8f9f7	6163	}
<>	144:ef7eb2e8f9f7	6164
<>	144:ef7eb2e8f9f7	6165	/**
<>	144:ef7eb2e8f9f7	6166	* @brief Get ADC group regular conversion data, range fit for
<>	144:ef7eb2e8f9f7	6167	* all ADC configurations: all ADC resolutions and
<>	144:ef7eb2e8f9f7	6168	* all oversampling increased data width (for devices
<>	144:ef7eb2e8f9f7	6169	* with feature oversampling).
<>	144:ef7eb2e8f9f7	6170	* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
<>	144:ef7eb2e8f9f7	6171	* JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
<>	144:ef7eb2e8f9f7	6172	* JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
<>	144:ef7eb2e8f9f7	6173	* JDR4 JDATA LL_ADC_INJ_ReadConversionData32
<>	144:ef7eb2e8f9f7	6174	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6175	* @param Rank This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	6176	* @arg @ref LL_ADC_INJ_RANK_1
<>	144:ef7eb2e8f9f7	6177	* @arg @ref LL_ADC_INJ_RANK_2
<>	144:ef7eb2e8f9f7	6178	* @arg @ref LL_ADC_INJ_RANK_3
<>	144:ef7eb2e8f9f7	6179	* @arg @ref LL_ADC_INJ_RANK_4
<>	144:ef7eb2e8f9f7	6180	* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
<>	144:ef7eb2e8f9f7	6181	*/
<>	144:ef7eb2e8f9f7	6182	__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
<>	144:ef7eb2e8f9f7	6183	{
<>	144:ef7eb2e8f9f7	6184	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
<>	144:ef7eb2e8f9f7	6185
<>	144:ef7eb2e8f9f7	6186	return (uint32_t)(READ_BIT(*preg,
<>	144:ef7eb2e8f9f7	6187	ADC_JDR1_JDATA)
<>	144:ef7eb2e8f9f7	6188	);
<>	144:ef7eb2e8f9f7	6189	}
<>	144:ef7eb2e8f9f7	6190
<>	144:ef7eb2e8f9f7	6191	/**
<>	144:ef7eb2e8f9f7	6192	* @brief Get ADC group injected conversion data, range fit for
<>	144:ef7eb2e8f9f7	6193	* ADC resolution 12 bits.
<>	144:ef7eb2e8f9f7	6194	* @note For devices with feature oversampling: Oversampling
<>	144:ef7eb2e8f9f7	6195	* can increase data width, function for extended range
<>	144:ef7eb2e8f9f7	6196	* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
<>	144:ef7eb2e8f9f7	6197	* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
<>	144:ef7eb2e8f9f7	6198	* JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
<>	144:ef7eb2e8f9f7	6199	* JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
<>	144:ef7eb2e8f9f7	6200	* JDR4 JDATA LL_ADC_INJ_ReadConversionData12
<>	144:ef7eb2e8f9f7	6201	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6202	* @param Rank This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	6203	* @arg @ref LL_ADC_INJ_RANK_1
<>	144:ef7eb2e8f9f7	6204	* @arg @ref LL_ADC_INJ_RANK_2
<>	144:ef7eb2e8f9f7	6205	* @arg @ref LL_ADC_INJ_RANK_3
<>	144:ef7eb2e8f9f7	6206	* @arg @ref LL_ADC_INJ_RANK_4
<>	144:ef7eb2e8f9f7	6207	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	144:ef7eb2e8f9f7	6208	*/
<>	144:ef7eb2e8f9f7	6209	__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
<>	144:ef7eb2e8f9f7	6210	{
<>	144:ef7eb2e8f9f7	6211	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
<>	144:ef7eb2e8f9f7	6212
<>	144:ef7eb2e8f9f7	6213	return (uint16_t)(READ_BIT(*preg,
<>	144:ef7eb2e8f9f7	6214	ADC_JDR1_JDATA)
<>	144:ef7eb2e8f9f7	6215	);
<>	144:ef7eb2e8f9f7	6216	}
<>	144:ef7eb2e8f9f7	6217
<>	144:ef7eb2e8f9f7	6218	/**
<>	144:ef7eb2e8f9f7	6219	* @brief Get ADC group injected conversion data, range fit for
<>	144:ef7eb2e8f9f7	6220	* ADC resolution 10 bits.
<>	144:ef7eb2e8f9f7	6221	* @note For devices with feature oversampling: Oversampling
<>	144:ef7eb2e8f9f7	6222	* can increase data width, function for extended range
<>	144:ef7eb2e8f9f7	6223	* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
<>	144:ef7eb2e8f9f7	6224	* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
<>	144:ef7eb2e8f9f7	6225	* JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
<>	144:ef7eb2e8f9f7	6226	* JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
<>	144:ef7eb2e8f9f7	6227	* JDR4 JDATA LL_ADC_INJ_ReadConversionData10
<>	144:ef7eb2e8f9f7	6228	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6229	* @param Rank This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	6230	* @arg @ref LL_ADC_INJ_RANK_1
<>	144:ef7eb2e8f9f7	6231	* @arg @ref LL_ADC_INJ_RANK_2
<>	144:ef7eb2e8f9f7	6232	* @arg @ref LL_ADC_INJ_RANK_3
<>	144:ef7eb2e8f9f7	6233	* @arg @ref LL_ADC_INJ_RANK_4
<>	144:ef7eb2e8f9f7	6234	* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
<>	144:ef7eb2e8f9f7	6235	*/
<>	144:ef7eb2e8f9f7	6236	__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
<>	144:ef7eb2e8f9f7	6237	{
<>	144:ef7eb2e8f9f7	6238	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
<>	144:ef7eb2e8f9f7	6239
<>	144:ef7eb2e8f9f7	6240	return (uint16_t)(READ_BIT(*preg,
<>	144:ef7eb2e8f9f7	6241	ADC_JDR1_JDATA)
<>	144:ef7eb2e8f9f7	6242	);
<>	144:ef7eb2e8f9f7	6243	}
<>	144:ef7eb2e8f9f7	6244
<>	144:ef7eb2e8f9f7	6245	/**
<>	144:ef7eb2e8f9f7	6246	* @brief Get ADC group injected conversion data, range fit for
<>	144:ef7eb2e8f9f7	6247	* ADC resolution 8 bits.
<>	144:ef7eb2e8f9f7	6248	* @note For devices with feature oversampling: Oversampling
<>	144:ef7eb2e8f9f7	6249	* can increase data width, function for extended range
<>	144:ef7eb2e8f9f7	6250	* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
<>	144:ef7eb2e8f9f7	6251	* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
<>	144:ef7eb2e8f9f7	6252	* JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
<>	144:ef7eb2e8f9f7	6253	* JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
<>	144:ef7eb2e8f9f7	6254	* JDR4 JDATA LL_ADC_INJ_ReadConversionData8
<>	144:ef7eb2e8f9f7	6255	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6256	* @param Rank This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	6257	* @arg @ref LL_ADC_INJ_RANK_1
<>	144:ef7eb2e8f9f7	6258	* @arg @ref LL_ADC_INJ_RANK_2
<>	144:ef7eb2e8f9f7	6259	* @arg @ref LL_ADC_INJ_RANK_3
<>	144:ef7eb2e8f9f7	6260	* @arg @ref LL_ADC_INJ_RANK_4
<>	144:ef7eb2e8f9f7	6261	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	144:ef7eb2e8f9f7	6262	*/
<>	144:ef7eb2e8f9f7	6263	__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
<>	144:ef7eb2e8f9f7	6264	{
<>	144:ef7eb2e8f9f7	6265	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
<>	144:ef7eb2e8f9f7	6266
<>	144:ef7eb2e8f9f7	6267	return (uint8_t)(READ_BIT(*preg,
<>	144:ef7eb2e8f9f7	6268	ADC_JDR1_JDATA)
<>	144:ef7eb2e8f9f7	6269	);
<>	144:ef7eb2e8f9f7	6270	}
<>	144:ef7eb2e8f9f7	6271
<>	144:ef7eb2e8f9f7	6272	/**
<>	144:ef7eb2e8f9f7	6273	* @brief Get ADC group injected conversion data, range fit for
<>	144:ef7eb2e8f9f7	6274	* ADC resolution 6 bits.
<>	144:ef7eb2e8f9f7	6275	* @note For devices with feature oversampling: Oversampling
<>	144:ef7eb2e8f9f7	6276	* can increase data width, function for extended range
<>	144:ef7eb2e8f9f7	6277	* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
<>	144:ef7eb2e8f9f7	6278	* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
<>	144:ef7eb2e8f9f7	6279	* JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
<>	144:ef7eb2e8f9f7	6280	* JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
<>	144:ef7eb2e8f9f7	6281	* JDR4 JDATA LL_ADC_INJ_ReadConversionData6
<>	144:ef7eb2e8f9f7	6282	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6283	* @param Rank This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	6284	* @arg @ref LL_ADC_INJ_RANK_1
<>	144:ef7eb2e8f9f7	6285	* @arg @ref LL_ADC_INJ_RANK_2
<>	144:ef7eb2e8f9f7	6286	* @arg @ref LL_ADC_INJ_RANK_3
<>	144:ef7eb2e8f9f7	6287	* @arg @ref LL_ADC_INJ_RANK_4
<>	144:ef7eb2e8f9f7	6288	* @retval Value between Min_Data=0x00 and Max_Data=0x3F
<>	144:ef7eb2e8f9f7	6289	*/
<>	144:ef7eb2e8f9f7	6290	__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
<>	144:ef7eb2e8f9f7	6291	{
<>	144:ef7eb2e8f9f7	6292	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
<>	144:ef7eb2e8f9f7	6293
<>	144:ef7eb2e8f9f7	6294	return (uint8_t)(READ_BIT(*preg,
<>	144:ef7eb2e8f9f7	6295	ADC_JDR1_JDATA)
<>	144:ef7eb2e8f9f7	6296	);
<>	144:ef7eb2e8f9f7	6297	}
<>	144:ef7eb2e8f9f7	6298
<>	144:ef7eb2e8f9f7	6299	/**
<>	144:ef7eb2e8f9f7	6300	* @}
<>	144:ef7eb2e8f9f7	6301	*/
<>	144:ef7eb2e8f9f7	6302
<>	144:ef7eb2e8f9f7	6303	/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
<>	144:ef7eb2e8f9f7	6304	* @{
<>	144:ef7eb2e8f9f7	6305	*/
<>	144:ef7eb2e8f9f7	6306
<>	144:ef7eb2e8f9f7	6307	/**
<>	144:ef7eb2e8f9f7	6308	* @brief Get flag ADC ready.
<>	144:ef7eb2e8f9f7	6309	* @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
<>	144:ef7eb2e8f9f7	6310	* is enabled and when conversion clock is active.
<>	144:ef7eb2e8f9f7	6311	* (not only core clock: this ADC has a dual clock domain)
<>	144:ef7eb2e8f9f7	6312	* @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
<>	144:ef7eb2e8f9f7	6313	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6314	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6315	*/
<>	144:ef7eb2e8f9f7	6316	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6317	{
<>	144:ef7eb2e8f9f7	6318	return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY));
<>	144:ef7eb2e8f9f7	6319	}
<>	144:ef7eb2e8f9f7	6320
<>	144:ef7eb2e8f9f7	6321	/**
<>	144:ef7eb2e8f9f7	6322	* @brief Get flag ADC group regular end of unitary conversion.
<>	144:ef7eb2e8f9f7	6323	* @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
<>	144:ef7eb2e8f9f7	6324	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6325	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6326	*/
<>	144:ef7eb2e8f9f7	6327	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6328	{
<>	144:ef7eb2e8f9f7	6329	return (READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC));
<>	144:ef7eb2e8f9f7	6330	}
<>	144:ef7eb2e8f9f7	6331
<>	144:ef7eb2e8f9f7	6332	/**
<>	144:ef7eb2e8f9f7	6333	* @brief Get flag ADC group regular end of sequence conversions.
<>	144:ef7eb2e8f9f7	6334	* @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
<>	144:ef7eb2e8f9f7	6335	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6336	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6337	*/
<>	144:ef7eb2e8f9f7	6338	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6339	{
<>	144:ef7eb2e8f9f7	6340	return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS));
<>	144:ef7eb2e8f9f7	6341	}
<>	144:ef7eb2e8f9f7	6342
<>	144:ef7eb2e8f9f7	6343	/**
<>	144:ef7eb2e8f9f7	6344	* @brief Get flag ADC group regular overrun.
<>	144:ef7eb2e8f9f7	6345	* @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
<>	144:ef7eb2e8f9f7	6346	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6347	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6348	*/
<>	144:ef7eb2e8f9f7	6349	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6350	{
<>	144:ef7eb2e8f9f7	6351	return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
<>	144:ef7eb2e8f9f7	6352	}
<>	144:ef7eb2e8f9f7	6353
<>	144:ef7eb2e8f9f7	6354	/**
<>	144:ef7eb2e8f9f7	6355	* @brief Get flag ADC group regular end of sampling phase.
<>	144:ef7eb2e8f9f7	6356	* @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
<>	144:ef7eb2e8f9f7	6357	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6358	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6359	*/
<>	144:ef7eb2e8f9f7	6360	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6361	{
<>	144:ef7eb2e8f9f7	6362	return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP));
<>	144:ef7eb2e8f9f7	6363	}
<>	144:ef7eb2e8f9f7	6364
<>	144:ef7eb2e8f9f7	6365	/**
<>	144:ef7eb2e8f9f7	6366	* @brief Get flag ADC group injected end of unitary conversion.
<>	144:ef7eb2e8f9f7	6367	* @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
<>	144:ef7eb2e8f9f7	6368	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6369	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6370	*/
<>	144:ef7eb2e8f9f7	6371	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6372	{
<>	144:ef7eb2e8f9f7	6373	return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC));
<>	144:ef7eb2e8f9f7	6374	}
<>	144:ef7eb2e8f9f7	6375
<>	144:ef7eb2e8f9f7	6376	/**
<>	144:ef7eb2e8f9f7	6377	* @brief Get flag ADC group injected end of sequence conversions.
<>	144:ef7eb2e8f9f7	6378	* @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
<>	144:ef7eb2e8f9f7	6379	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6380	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6381	*/
<>	144:ef7eb2e8f9f7	6382	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6383	{
<>	144:ef7eb2e8f9f7	6384	return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
<>	144:ef7eb2e8f9f7	6385	}
<>	144:ef7eb2e8f9f7	6386
<>	144:ef7eb2e8f9f7	6387	/**
<>	144:ef7eb2e8f9f7	6388	* @brief Get flag ADC group injected contexts queue overflow.
<>	144:ef7eb2e8f9f7	6389	* @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
<>	144:ef7eb2e8f9f7	6390	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6391	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6392	*/
<>	144:ef7eb2e8f9f7	6393	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6394	{
<>	144:ef7eb2e8f9f7	6395	return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF));
<>	144:ef7eb2e8f9f7	6396	}
<>	144:ef7eb2e8f9f7	6397
<>	144:ef7eb2e8f9f7	6398	/**
<>	144:ef7eb2e8f9f7	6399	* @brief Get flag ADC analog watchdog 1 flag
<>	144:ef7eb2e8f9f7	6400	* @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
<>	144:ef7eb2e8f9f7	6401	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6402	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6403	*/
<>	144:ef7eb2e8f9f7	6404	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6405	{
<>	144:ef7eb2e8f9f7	6406	return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
<>	144:ef7eb2e8f9f7	6407	}
<>	144:ef7eb2e8f9f7	6408
<>	144:ef7eb2e8f9f7	6409	/**
<>	144:ef7eb2e8f9f7	6410	* @brief Get flag ADC analog watchdog 2.
<>	144:ef7eb2e8f9f7	6411	* @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
<>	144:ef7eb2e8f9f7	6412	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6413	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6414	*/
<>	144:ef7eb2e8f9f7	6415	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6416	{
<>	144:ef7eb2e8f9f7	6417	return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2));
<>	144:ef7eb2e8f9f7	6418	}
<>	144:ef7eb2e8f9f7	6419
<>	144:ef7eb2e8f9f7	6420	/**
<>	144:ef7eb2e8f9f7	6421	* @brief Get flag ADC analog watchdog 3.
<>	144:ef7eb2e8f9f7	6422	* @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
<>	144:ef7eb2e8f9f7	6423	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6424	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6425	*/
<>	144:ef7eb2e8f9f7	6426	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6427	{
<>	144:ef7eb2e8f9f7	6428	return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3));
<>	144:ef7eb2e8f9f7	6429	}
<>	144:ef7eb2e8f9f7	6430
<>	144:ef7eb2e8f9f7	6431	/**
<>	144:ef7eb2e8f9f7	6432	* @brief Clear flag ADC ready.
<>	144:ef7eb2e8f9f7	6433	* @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
<>	144:ef7eb2e8f9f7	6434	* is enabled and when conversion clock is active.
<>	144:ef7eb2e8f9f7	6435	* (not only core clock: this ADC has a dual clock domain)
<>	144:ef7eb2e8f9f7	6436	* @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
<>	144:ef7eb2e8f9f7	6437	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6438	* @retval None
<>	144:ef7eb2e8f9f7	6439	*/
<>	144:ef7eb2e8f9f7	6440	__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6441	{
<>	144:ef7eb2e8f9f7	6442	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
<>	144:ef7eb2e8f9f7	6443	}
<>	144:ef7eb2e8f9f7	6444
<>	144:ef7eb2e8f9f7	6445	/**
<>	144:ef7eb2e8f9f7	6446	* @brief Clear flag ADC group regular end of unitary conversion.
<>	144:ef7eb2e8f9f7	6447	* @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
<>	144:ef7eb2e8f9f7	6448	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6449	* @retval None
<>	144:ef7eb2e8f9f7	6450	*/
<>	144:ef7eb2e8f9f7	6451	__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6452	{
<>	144:ef7eb2e8f9f7	6453	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
<>	144:ef7eb2e8f9f7	6454	}
<>	144:ef7eb2e8f9f7	6455
<>	144:ef7eb2e8f9f7	6456	/**
<>	144:ef7eb2e8f9f7	6457	* @brief Clear flag ADC group regular end of sequence conversions.
<>	144:ef7eb2e8f9f7	6458	* @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
<>	144:ef7eb2e8f9f7	6459	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6460	* @retval None
<>	144:ef7eb2e8f9f7	6461	*/
<>	144:ef7eb2e8f9f7	6462	__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6463	{
<>	144:ef7eb2e8f9f7	6464	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
<>	144:ef7eb2e8f9f7	6465	}
<>	144:ef7eb2e8f9f7	6466
<>	144:ef7eb2e8f9f7	6467	/**
<>	144:ef7eb2e8f9f7	6468	* @brief Clear flag ADC group regular overrun.
<>	144:ef7eb2e8f9f7	6469	* @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
<>	144:ef7eb2e8f9f7	6470	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6471	* @retval None
<>	144:ef7eb2e8f9f7	6472	*/
<>	144:ef7eb2e8f9f7	6473	__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6474	{
<>	144:ef7eb2e8f9f7	6475	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
<>	144:ef7eb2e8f9f7	6476	}
<>	144:ef7eb2e8f9f7	6477
<>	144:ef7eb2e8f9f7	6478	/**
<>	144:ef7eb2e8f9f7	6479	* @brief Clear flag ADC group regular end of sampling phase.
<>	144:ef7eb2e8f9f7	6480	* @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
<>	144:ef7eb2e8f9f7	6481	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6482	* @retval None
<>	144:ef7eb2e8f9f7	6483	*/
<>	144:ef7eb2e8f9f7	6484	__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6485	{
<>	144:ef7eb2e8f9f7	6486	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
<>	144:ef7eb2e8f9f7	6487	}
<>	144:ef7eb2e8f9f7	6488
<>	144:ef7eb2e8f9f7	6489	/**
<>	144:ef7eb2e8f9f7	6490	* @brief Clear flag ADC group injected end of unitary conversion.
<>	144:ef7eb2e8f9f7	6491	* @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
<>	144:ef7eb2e8f9f7	6492	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6493	* @retval None
<>	144:ef7eb2e8f9f7	6494	*/
<>	144:ef7eb2e8f9f7	6495	__STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6496	{
<>	144:ef7eb2e8f9f7	6497	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
<>	144:ef7eb2e8f9f7	6498	}
<>	144:ef7eb2e8f9f7	6499
<>	144:ef7eb2e8f9f7	6500	/**
<>	144:ef7eb2e8f9f7	6501	* @brief Clear flag ADC group injected end of sequence conversions.
<>	144:ef7eb2e8f9f7	6502	* @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
<>	144:ef7eb2e8f9f7	6503	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6504	* @retval None
<>	144:ef7eb2e8f9f7	6505	*/
<>	144:ef7eb2e8f9f7	6506	__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6507	{
<>	144:ef7eb2e8f9f7	6508	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
<>	144:ef7eb2e8f9f7	6509	}
<>	144:ef7eb2e8f9f7	6510
<>	144:ef7eb2e8f9f7	6511	/**
<>	144:ef7eb2e8f9f7	6512	* @brief Clear flag ADC group injected contexts queue overflow.
<>	144:ef7eb2e8f9f7	6513	* @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF
<>	144:ef7eb2e8f9f7	6514	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6515	* @retval None
<>	144:ef7eb2e8f9f7	6516	*/
<>	144:ef7eb2e8f9f7	6517	__STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6518	{
<>	144:ef7eb2e8f9f7	6519	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
<>	144:ef7eb2e8f9f7	6520	}
<>	144:ef7eb2e8f9f7	6521
<>	144:ef7eb2e8f9f7	6522	/**
<>	144:ef7eb2e8f9f7	6523	* @brief Clear flag ADC analog watchdog 1.
<>	144:ef7eb2e8f9f7	6524	* @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
<>	144:ef7eb2e8f9f7	6525	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6526	* @retval None
<>	144:ef7eb2e8f9f7	6527	*/
<>	144:ef7eb2e8f9f7	6528	__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6529	{
<>	144:ef7eb2e8f9f7	6530	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
<>	144:ef7eb2e8f9f7	6531	}
<>	144:ef7eb2e8f9f7	6532
<>	144:ef7eb2e8f9f7	6533	/**
<>	144:ef7eb2e8f9f7	6534	* @brief Clear flag ADC analog watchdog 2.
<>	144:ef7eb2e8f9f7	6535	* @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
<>	144:ef7eb2e8f9f7	6536	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6537	* @retval None
<>	144:ef7eb2e8f9f7	6538	*/
<>	144:ef7eb2e8f9f7	6539	__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6540	{
<>	144:ef7eb2e8f9f7	6541	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
<>	144:ef7eb2e8f9f7	6542	}
<>	144:ef7eb2e8f9f7	6543
<>	144:ef7eb2e8f9f7	6544	/**
<>	144:ef7eb2e8f9f7	6545	* @brief Clear flag ADC analog watchdog 3.
<>	144:ef7eb2e8f9f7	6546	* @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
<>	144:ef7eb2e8f9f7	6547	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6548	* @retval None
<>	144:ef7eb2e8f9f7	6549	*/
<>	144:ef7eb2e8f9f7	6550	__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6551	{
<>	144:ef7eb2e8f9f7	6552	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
<>	144:ef7eb2e8f9f7	6553	}
<>	144:ef7eb2e8f9f7	6554
<>	144:ef7eb2e8f9f7	6555	#if defined(ADC_MULTIMODE_SUPPORT)
<>	144:ef7eb2e8f9f7	6556	/**
<>	144:ef7eb2e8f9f7	6557	* @brief Get flag multimode ADC ready of the ADC master.
<>	144:ef7eb2e8f9f7	6558	* @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY
<>	144:ef7eb2e8f9f7	6559	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	6560	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	6561	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6562	*/
<>	144:ef7eb2e8f9f7	6563	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
<>	144:ef7eb2e8f9f7	6564	{
<>	144:ef7eb2e8f9f7	6565	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST));
<>	144:ef7eb2e8f9f7	6566	}
<>	144:ef7eb2e8f9f7	6567
<>	144:ef7eb2e8f9f7	6568	/**
<>	144:ef7eb2e8f9f7	6569	* @brief Get flag multimode ADC ready of the ADC slave.
<>	144:ef7eb2e8f9f7	6570	* @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY
<>	144:ef7eb2e8f9f7	6571	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	6572	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	6573	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6574	*/
<>	144:ef7eb2e8f9f7	6575	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
<>	144:ef7eb2e8f9f7	6576	{
<>	144:ef7eb2e8f9f7	6577	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV));
<>	144:ef7eb2e8f9f7	6578	}
<>	144:ef7eb2e8f9f7	6579
<>	144:ef7eb2e8f9f7	6580	/**
<>	144:ef7eb2e8f9f7	6581	* @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master.
<>	144:ef7eb2e8f9f7	6582	* @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC
<>	144:ef7eb2e8f9f7	6583	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	6584	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	6585	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6586	*/
<>	144:ef7eb2e8f9f7	6587	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
<>	144:ef7eb2e8f9f7	6588	{
<>	144:ef7eb2e8f9f7	6589	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV));
<>	144:ef7eb2e8f9f7	6590	}
<>	144:ef7eb2e8f9f7	6591
<>	144:ef7eb2e8f9f7	6592	/**
<>	144:ef7eb2e8f9f7	6593	* @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
<>	144:ef7eb2e8f9f7	6594	* @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC
<>	144:ef7eb2e8f9f7	6595	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	6596	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	6597	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6598	*/
<>	144:ef7eb2e8f9f7	6599	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
<>	144:ef7eb2e8f9f7	6600	{
<>	144:ef7eb2e8f9f7	6601	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV));
<>	144:ef7eb2e8f9f7	6602	}
<>	144:ef7eb2e8f9f7	6603
<>	144:ef7eb2e8f9f7	6604	/**
<>	144:ef7eb2e8f9f7	6605	* @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.
<>	144:ef7eb2e8f9f7	6606	* @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS
<>	144:ef7eb2e8f9f7	6607	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	6608	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	6609	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6610	*/
<>	144:ef7eb2e8f9f7	6611	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
<>	144:ef7eb2e8f9f7	6612	{
<>	144:ef7eb2e8f9f7	6613	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST));
<>	144:ef7eb2e8f9f7	6614	}
<>	144:ef7eb2e8f9f7	6615
<>	144:ef7eb2e8f9f7	6616	/**
<>	144:ef7eb2e8f9f7	6617	* @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
<>	144:ef7eb2e8f9f7	6618	* @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS
<>	144:ef7eb2e8f9f7	6619	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	6620	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	6621	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6622	*/
<>	144:ef7eb2e8f9f7	6623	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
<>	144:ef7eb2e8f9f7	6624	{
<>	144:ef7eb2e8f9f7	6625	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV));
<>	144:ef7eb2e8f9f7	6626	}
<>	144:ef7eb2e8f9f7	6627
<>	144:ef7eb2e8f9f7	6628	/**
<>	144:ef7eb2e8f9f7	6629	* @brief Get flag multimode ADC group regular overrun of the ADC master.
<>	144:ef7eb2e8f9f7	6630	* @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR
<>	144:ef7eb2e8f9f7	6631	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	6632	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	6633	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6634	*/
<>	144:ef7eb2e8f9f7	6635	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
<>	144:ef7eb2e8f9f7	6636	{
<>	144:ef7eb2e8f9f7	6637	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST));
<>	144:ef7eb2e8f9f7	6638	}
<>	144:ef7eb2e8f9f7	6639
<>	144:ef7eb2e8f9f7	6640	/**
<>	144:ef7eb2e8f9f7	6641	* @brief Get flag multimode ADC group regular overrun of the ADC slave.
<>	144:ef7eb2e8f9f7	6642	* @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR
<>	144:ef7eb2e8f9f7	6643	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	6644	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	6645	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6646	*/
<>	144:ef7eb2e8f9f7	6647	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
<>	144:ef7eb2e8f9f7	6648	{
<>	144:ef7eb2e8f9f7	6649	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV));
<>	144:ef7eb2e8f9f7	6650	}
<>	144:ef7eb2e8f9f7	6651
<>	144:ef7eb2e8f9f7	6652	/**
<>	144:ef7eb2e8f9f7	6653	* @brief Get flag multimode ADC group regular end of sampling of the ADC master.
<>	144:ef7eb2e8f9f7	6654	* @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP
<>	144:ef7eb2e8f9f7	6655	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	6656	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	6657	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6658	*/
<>	144:ef7eb2e8f9f7	6659	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
<>	144:ef7eb2e8f9f7	6660	{
<>	144:ef7eb2e8f9f7	6661	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST));
<>	144:ef7eb2e8f9f7	6662	}
<>	144:ef7eb2e8f9f7	6663
<>	144:ef7eb2e8f9f7	6664	/**
<>	144:ef7eb2e8f9f7	6665	* @brief Get flag multimode ADC group regular end of sampling of the ADC slave.
<>	144:ef7eb2e8f9f7	6666	* @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP
<>	144:ef7eb2e8f9f7	6667	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	6668	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	6669	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6670	*/
<>	144:ef7eb2e8f9f7	6671	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
<>	144:ef7eb2e8f9f7	6672	{
<>	144:ef7eb2e8f9f7	6673	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV));
<>	144:ef7eb2e8f9f7	6674	}
<>	144:ef7eb2e8f9f7	6675
<>	144:ef7eb2e8f9f7	6676	/**
<>	144:ef7eb2e8f9f7	6677	* @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master.
<>	144:ef7eb2e8f9f7	6678	* @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC
<>	144:ef7eb2e8f9f7	6679	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	6680	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	6681	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6682	*/
<>	144:ef7eb2e8f9f7	6683	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
<>	144:ef7eb2e8f9f7	6684	{
<>	144:ef7eb2e8f9f7	6685	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST));
<>	144:ef7eb2e8f9f7	6686	}
<>	144:ef7eb2e8f9f7	6687
<>	144:ef7eb2e8f9f7	6688	/**
<>	144:ef7eb2e8f9f7	6689	* @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
<>	144:ef7eb2e8f9f7	6690	* @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC
<>	144:ef7eb2e8f9f7	6691	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	6692	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	6693	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6694	*/
<>	144:ef7eb2e8f9f7	6695	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
<>	144:ef7eb2e8f9f7	6696	{
<>	144:ef7eb2e8f9f7	6697	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV));
<>	144:ef7eb2e8f9f7	6698	}
<>	144:ef7eb2e8f9f7	6699
<>	144:ef7eb2e8f9f7	6700	/**
<>	144:ef7eb2e8f9f7	6701	* @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
<>	144:ef7eb2e8f9f7	6702	* @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS
<>	144:ef7eb2e8f9f7	6703	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	6704	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	6705	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6706	*/
<>	144:ef7eb2e8f9f7	6707	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
<>	144:ef7eb2e8f9f7	6708	{
<>	144:ef7eb2e8f9f7	6709	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST));
<>	144:ef7eb2e8f9f7	6710	}
<>	144:ef7eb2e8f9f7	6711
<>	144:ef7eb2e8f9f7	6712	/**
<>	144:ef7eb2e8f9f7	6713	* @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
<>	144:ef7eb2e8f9f7	6714	* @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS
<>	144:ef7eb2e8f9f7	6715	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	6716	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	6717	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6718	*/
<>	144:ef7eb2e8f9f7	6719	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
<>	144:ef7eb2e8f9f7	6720	{
<>	144:ef7eb2e8f9f7	6721	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV));
<>	144:ef7eb2e8f9f7	6722	}
<>	144:ef7eb2e8f9f7	6723
<>	144:ef7eb2e8f9f7	6724	/**
<>	144:ef7eb2e8f9f7	6725	* @brief Get flag multimode ADC group injected context queue overflow of the ADC master.
<>	144:ef7eb2e8f9f7	6726	* @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF
<>	144:ef7eb2e8f9f7	6727	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	6728	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	6729	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6730	*/
<>	144:ef7eb2e8f9f7	6731	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
<>	144:ef7eb2e8f9f7	6732	{
<>	144:ef7eb2e8f9f7	6733	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST));
<>	144:ef7eb2e8f9f7	6734	}
<>	144:ef7eb2e8f9f7	6735
<>	144:ef7eb2e8f9f7	6736	/**
<>	144:ef7eb2e8f9f7	6737	* @brief Get flag multimode ADC group injected context queue overflow of the ADC slave.
<>	144:ef7eb2e8f9f7	6738	* @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF
<>	144:ef7eb2e8f9f7	6739	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	6740	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	6741	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6742	*/
<>	144:ef7eb2e8f9f7	6743	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
<>	144:ef7eb2e8f9f7	6744	{
<>	144:ef7eb2e8f9f7	6745	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV));
<>	144:ef7eb2e8f9f7	6746	}
<>	144:ef7eb2e8f9f7	6747
<>	144:ef7eb2e8f9f7	6748	/**
<>	144:ef7eb2e8f9f7	6749	* @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
<>	144:ef7eb2e8f9f7	6750	* @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1
<>	144:ef7eb2e8f9f7	6751	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	6752	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	6753	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6754	*/
<>	144:ef7eb2e8f9f7	6755	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
<>	144:ef7eb2e8f9f7	6756	{
<>	144:ef7eb2e8f9f7	6757	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST));
<>	144:ef7eb2e8f9f7	6758	}
<>	144:ef7eb2e8f9f7	6759
<>	144:ef7eb2e8f9f7	6760	/**
<>	144:ef7eb2e8f9f7	6761	* @brief Get flag multimode analog watchdog 1 of the ADC slave.
<>	144:ef7eb2e8f9f7	6762	* @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1
<>	144:ef7eb2e8f9f7	6763	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	6764	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	6765	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6766	*/
<>	144:ef7eb2e8f9f7	6767	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
<>	144:ef7eb2e8f9f7	6768	{
<>	144:ef7eb2e8f9f7	6769	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV));
<>	144:ef7eb2e8f9f7	6770	}
<>	144:ef7eb2e8f9f7	6771
<>	144:ef7eb2e8f9f7	6772	/**
<>	144:ef7eb2e8f9f7	6773	* @brief Get flag multimode ADC analog watchdog 2 of the ADC master.
<>	144:ef7eb2e8f9f7	6774	* @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2
<>	144:ef7eb2e8f9f7	6775	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	6776	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	6777	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6778	*/
<>	144:ef7eb2e8f9f7	6779	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
<>	144:ef7eb2e8f9f7	6780	{
<>	144:ef7eb2e8f9f7	6781	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST));
<>	144:ef7eb2e8f9f7	6782	}
<>	144:ef7eb2e8f9f7	6783
<>	144:ef7eb2e8f9f7	6784	/**
<>	144:ef7eb2e8f9f7	6785	* @brief Get flag multimode ADC analog watchdog 2 of the ADC slave.
<>	144:ef7eb2e8f9f7	6786	* @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2
<>	144:ef7eb2e8f9f7	6787	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	6788	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	6789	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6790	*/
<>	144:ef7eb2e8f9f7	6791	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
<>	144:ef7eb2e8f9f7	6792	{
<>	144:ef7eb2e8f9f7	6793	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV));
<>	144:ef7eb2e8f9f7	6794	}
<>	144:ef7eb2e8f9f7	6795
<>	144:ef7eb2e8f9f7	6796	/**
<>	144:ef7eb2e8f9f7	6797	* @brief Get flag multimode ADC analog watchdog 3 of the ADC master.
<>	144:ef7eb2e8f9f7	6798	* @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3
<>	144:ef7eb2e8f9f7	6799	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	6800	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	6801	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6802	*/
<>	144:ef7eb2e8f9f7	6803	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
<>	144:ef7eb2e8f9f7	6804	{
<>	144:ef7eb2e8f9f7	6805	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST));
<>	144:ef7eb2e8f9f7	6806	}
<>	144:ef7eb2e8f9f7	6807
<>	144:ef7eb2e8f9f7	6808	/**
<>	144:ef7eb2e8f9f7	6809	* @brief Get flag multimode ADC analog watchdog 3 of the ADC slave.
<>	144:ef7eb2e8f9f7	6810	* @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3
<>	144:ef7eb2e8f9f7	6811	* @param ADCxy_COMMON ADC common instance
<>	144:ef7eb2e8f9f7	6812	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	144:ef7eb2e8f9f7	6813	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	6814	*/
<>	144:ef7eb2e8f9f7	6815	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
<>	144:ef7eb2e8f9f7	6816	{
<>	144:ef7eb2e8f9f7	6817	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV));
<>	144:ef7eb2e8f9f7	6818	}
<>	144:ef7eb2e8f9f7	6819	#endif /* ADC_MULTIMODE_SUPPORT */
<>	144:ef7eb2e8f9f7	6820
<>	144:ef7eb2e8f9f7	6821	/**
<>	144:ef7eb2e8f9f7	6822	* @}
<>	144:ef7eb2e8f9f7	6823	*/
<>	144:ef7eb2e8f9f7	6824
<>	144:ef7eb2e8f9f7	6825	/** @defgroup ADC_LL_EF_IT_Management ADC IT management
<>	144:ef7eb2e8f9f7	6826	* @{
<>	144:ef7eb2e8f9f7	6827	*/
<>	144:ef7eb2e8f9f7	6828
<>	144:ef7eb2e8f9f7	6829	/**
<>	144:ef7eb2e8f9f7	6830	* @brief Enable ADC ready.
<>	144:ef7eb2e8f9f7	6831	* @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
<>	144:ef7eb2e8f9f7	6832	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6833	* @retval None
<>	144:ef7eb2e8f9f7	6834	*/
<>	144:ef7eb2e8f9f7	6835	__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6836	{
<>	144:ef7eb2e8f9f7	6837	SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
<>	144:ef7eb2e8f9f7	6838	}
<>	144:ef7eb2e8f9f7	6839
<>	144:ef7eb2e8f9f7	6840	/**
<>	144:ef7eb2e8f9f7	6841	* @brief Enable interruption ADC group regular end of unitary conversion.
<>	144:ef7eb2e8f9f7	6842	* @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
<>	144:ef7eb2e8f9f7	6843	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6844	* @retval None
<>	144:ef7eb2e8f9f7	6845	*/
<>	144:ef7eb2e8f9f7	6846	__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6847	{
<>	144:ef7eb2e8f9f7	6848	SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
<>	144:ef7eb2e8f9f7	6849	}
<>	144:ef7eb2e8f9f7	6850
<>	144:ef7eb2e8f9f7	6851	/**
<>	144:ef7eb2e8f9f7	6852	* @brief Enable interruption ADC group regular end of sequence conversions.
<>	144:ef7eb2e8f9f7	6853	* @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
<>	144:ef7eb2e8f9f7	6854	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6855	* @retval None
<>	144:ef7eb2e8f9f7	6856	*/
<>	144:ef7eb2e8f9f7	6857	__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6858	{
<>	144:ef7eb2e8f9f7	6859	SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
<>	144:ef7eb2e8f9f7	6860	}
<>	144:ef7eb2e8f9f7	6861
<>	144:ef7eb2e8f9f7	6862	/**
<>	144:ef7eb2e8f9f7	6863	* @brief Enable ADC group regular interruption overrun.
<>	144:ef7eb2e8f9f7	6864	* @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
<>	144:ef7eb2e8f9f7	6865	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6866	* @retval None
<>	144:ef7eb2e8f9f7	6867	*/
<>	144:ef7eb2e8f9f7	6868	__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6869	{
<>	144:ef7eb2e8f9f7	6870	SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
<>	144:ef7eb2e8f9f7	6871	}
<>	144:ef7eb2e8f9f7	6872
<>	144:ef7eb2e8f9f7	6873	/**
<>	144:ef7eb2e8f9f7	6874	* @brief Enable interruption ADC group regular end of sampling.
<>	144:ef7eb2e8f9f7	6875	* @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
<>	144:ef7eb2e8f9f7	6876	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6877	* @retval None
<>	144:ef7eb2e8f9f7	6878	*/
<>	144:ef7eb2e8f9f7	6879	__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6880	{
<>	144:ef7eb2e8f9f7	6881	SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
<>	144:ef7eb2e8f9f7	6882	}
<>	144:ef7eb2e8f9f7	6883
<>	144:ef7eb2e8f9f7	6884	/**
<>	144:ef7eb2e8f9f7	6885	* @brief Enable interruption ADC group injected end of unitary conversion.
<>	144:ef7eb2e8f9f7	6886	* @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
<>	144:ef7eb2e8f9f7	6887	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6888	* @retval None
<>	144:ef7eb2e8f9f7	6889	*/
<>	144:ef7eb2e8f9f7	6890	__STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6891	{
<>	144:ef7eb2e8f9f7	6892	SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
<>	144:ef7eb2e8f9f7	6893	}
<>	144:ef7eb2e8f9f7	6894
<>	144:ef7eb2e8f9f7	6895	/**
<>	144:ef7eb2e8f9f7	6896	* @brief Enable interruption ADC group injected end of sequence conversions.
<>	144:ef7eb2e8f9f7	6897	* @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
<>	144:ef7eb2e8f9f7	6898	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6899	* @retval None
<>	144:ef7eb2e8f9f7	6900	*/
<>	144:ef7eb2e8f9f7	6901	__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6902	{
<>	144:ef7eb2e8f9f7	6903	SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
<>	144:ef7eb2e8f9f7	6904	}
<>	144:ef7eb2e8f9f7	6905
<>	144:ef7eb2e8f9f7	6906	/**
<>	144:ef7eb2e8f9f7	6907	* @brief Enable interruption ADC group injected context queue overflow.
<>	144:ef7eb2e8f9f7	6908	* @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF
<>	144:ef7eb2e8f9f7	6909	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6910	* @retval None
<>	144:ef7eb2e8f9f7	6911	*/
<>	144:ef7eb2e8f9f7	6912	__STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6913	{
<>	144:ef7eb2e8f9f7	6914	SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
<>	144:ef7eb2e8f9f7	6915	}
<>	144:ef7eb2e8f9f7	6916
<>	144:ef7eb2e8f9f7	6917	/**
<>	144:ef7eb2e8f9f7	6918	* @brief Enable interruption ADC analog watchdog 1.
<>	144:ef7eb2e8f9f7	6919	* @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
<>	144:ef7eb2e8f9f7	6920	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6921	* @retval None
<>	144:ef7eb2e8f9f7	6922	*/
<>	144:ef7eb2e8f9f7	6923	__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6924	{
<>	144:ef7eb2e8f9f7	6925	SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
<>	144:ef7eb2e8f9f7	6926	}
<>	144:ef7eb2e8f9f7	6927
<>	144:ef7eb2e8f9f7	6928	/**
<>	144:ef7eb2e8f9f7	6929	* @brief Enable interruption ADC analog watchdog 2.
<>	144:ef7eb2e8f9f7	6930	* @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
<>	144:ef7eb2e8f9f7	6931	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6932	* @retval None
<>	144:ef7eb2e8f9f7	6933	*/
<>	144:ef7eb2e8f9f7	6934	__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6935	{
<>	144:ef7eb2e8f9f7	6936	SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
<>	144:ef7eb2e8f9f7	6937	}
<>	144:ef7eb2e8f9f7	6938
<>	144:ef7eb2e8f9f7	6939	/**
<>	144:ef7eb2e8f9f7	6940	* @brief Enable interruption ADC analog watchdog 3.
<>	144:ef7eb2e8f9f7	6941	* @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
<>	144:ef7eb2e8f9f7	6942	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6943	* @retval None
<>	144:ef7eb2e8f9f7	6944	*/
<>	144:ef7eb2e8f9f7	6945	__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6946	{
<>	144:ef7eb2e8f9f7	6947	SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
<>	144:ef7eb2e8f9f7	6948	}
<>	144:ef7eb2e8f9f7	6949
<>	144:ef7eb2e8f9f7	6950	/**
<>	144:ef7eb2e8f9f7	6951	* @brief Disable interruption ADC ready.
<>	144:ef7eb2e8f9f7	6952	* @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
<>	144:ef7eb2e8f9f7	6953	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6954	* @retval None
<>	144:ef7eb2e8f9f7	6955	*/
<>	144:ef7eb2e8f9f7	6956	__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6957	{
<>	144:ef7eb2e8f9f7	6958	CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
<>	144:ef7eb2e8f9f7	6959	}
<>	144:ef7eb2e8f9f7	6960
<>	144:ef7eb2e8f9f7	6961	/**
<>	144:ef7eb2e8f9f7	6962	* @brief Disable interruption ADC group regular end of unitary conversion.
<>	144:ef7eb2e8f9f7	6963	* @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
<>	144:ef7eb2e8f9f7	6964	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6965	* @retval None
<>	144:ef7eb2e8f9f7	6966	*/
<>	144:ef7eb2e8f9f7	6967	__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6968	{
<>	144:ef7eb2e8f9f7	6969	CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
<>	144:ef7eb2e8f9f7	6970	}
<>	144:ef7eb2e8f9f7	6971
<>	144:ef7eb2e8f9f7	6972	/**
<>	144:ef7eb2e8f9f7	6973	* @brief Disable interruption ADC group regular end of sequence conversions.
<>	144:ef7eb2e8f9f7	6974	* @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
<>	144:ef7eb2e8f9f7	6975	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6976	* @retval None
<>	144:ef7eb2e8f9f7	6977	*/
<>	144:ef7eb2e8f9f7	6978	__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6979	{
<>	144:ef7eb2e8f9f7	6980	CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
<>	144:ef7eb2e8f9f7	6981	}
<>	144:ef7eb2e8f9f7	6982
<>	144:ef7eb2e8f9f7	6983	/**
<>	144:ef7eb2e8f9f7	6984	* @brief Disable interruption ADC group regular overrun.
<>	144:ef7eb2e8f9f7	6985	* @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
<>	144:ef7eb2e8f9f7	6986	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6987	* @retval None
<>	144:ef7eb2e8f9f7	6988	*/
<>	144:ef7eb2e8f9f7	6989	__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	6990	{
<>	144:ef7eb2e8f9f7	6991	CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
<>	144:ef7eb2e8f9f7	6992	}
<>	144:ef7eb2e8f9f7	6993
<>	144:ef7eb2e8f9f7	6994	/**
<>	144:ef7eb2e8f9f7	6995	* @brief Disable interruption ADC group regular end of sampling.
<>	144:ef7eb2e8f9f7	6996	* @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
<>	144:ef7eb2e8f9f7	6997	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	6998	* @retval None
<>	144:ef7eb2e8f9f7	6999	*/
<>	144:ef7eb2e8f9f7	7000	__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	7001	{
<>	144:ef7eb2e8f9f7	7002	CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
<>	144:ef7eb2e8f9f7	7003	}
<>	144:ef7eb2e8f9f7	7004
<>	144:ef7eb2e8f9f7	7005	/**
<>	144:ef7eb2e8f9f7	7006	* @brief Disable interruption ADC group regular end of unitary conversion.
<>	144:ef7eb2e8f9f7	7007	* @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
<>	144:ef7eb2e8f9f7	7008	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	7009	* @retval None
<>	144:ef7eb2e8f9f7	7010	*/
<>	144:ef7eb2e8f9f7	7011	__STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	7012	{
<>	144:ef7eb2e8f9f7	7013	CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
<>	144:ef7eb2e8f9f7	7014	}
<>	144:ef7eb2e8f9f7	7015
<>	144:ef7eb2e8f9f7	7016	/**
<>	144:ef7eb2e8f9f7	7017	* @brief Disable interruption ADC group injected end of sequence conversions.
<>	144:ef7eb2e8f9f7	7018	* @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
<>	144:ef7eb2e8f9f7	7019	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	7020	* @retval None
<>	144:ef7eb2e8f9f7	7021	*/
<>	144:ef7eb2e8f9f7	7022	__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	7023	{
<>	144:ef7eb2e8f9f7	7024	CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
<>	144:ef7eb2e8f9f7	7025	}
<>	144:ef7eb2e8f9f7	7026
<>	144:ef7eb2e8f9f7	7027	/**
<>	144:ef7eb2e8f9f7	7028	* @brief Disable interruption ADC group injected context queue overflow.
<>	144:ef7eb2e8f9f7	7029	* @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF
<>	144:ef7eb2e8f9f7	7030	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	7031	* @retval None
<>	144:ef7eb2e8f9f7	7032	*/
<>	144:ef7eb2e8f9f7	7033	__STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	7034	{
<>	144:ef7eb2e8f9f7	7035	CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
<>	144:ef7eb2e8f9f7	7036	}
<>	144:ef7eb2e8f9f7	7037
<>	144:ef7eb2e8f9f7	7038	/**
<>	144:ef7eb2e8f9f7	7039	* @brief Disable interruption ADC analog watchdog 1.
<>	144:ef7eb2e8f9f7	7040	* @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
<>	144:ef7eb2e8f9f7	7041	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	7042	* @retval None
<>	144:ef7eb2e8f9f7	7043	*/
<>	144:ef7eb2e8f9f7	7044	__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	7045	{
<>	144:ef7eb2e8f9f7	7046	CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
<>	144:ef7eb2e8f9f7	7047	}
<>	144:ef7eb2e8f9f7	7048
<>	144:ef7eb2e8f9f7	7049	/**
<>	144:ef7eb2e8f9f7	7050	* @brief Disable interruption ADC analog watchdog 2.
<>	144:ef7eb2e8f9f7	7051	* @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
<>	144:ef7eb2e8f9f7	7052	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	7053	* @retval None
<>	144:ef7eb2e8f9f7	7054	*/
<>	144:ef7eb2e8f9f7	7055	__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	7056	{
<>	144:ef7eb2e8f9f7	7057	CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
<>	144:ef7eb2e8f9f7	7058	}
<>	144:ef7eb2e8f9f7	7059
<>	144:ef7eb2e8f9f7	7060	/**
<>	144:ef7eb2e8f9f7	7061	* @brief Disable interruption ADC analog watchdog 3.
<>	144:ef7eb2e8f9f7	7062	* @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
<>	144:ef7eb2e8f9f7	7063	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	7064	* @retval None
<>	144:ef7eb2e8f9f7	7065	*/
<>	144:ef7eb2e8f9f7	7066	__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	7067	{
<>	144:ef7eb2e8f9f7	7068	CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
<>	144:ef7eb2e8f9f7	7069	}
<>	144:ef7eb2e8f9f7	7070
<>	144:ef7eb2e8f9f7	7071	/**
<>	144:ef7eb2e8f9f7	7072	* @brief Get state of interruption ADC ready
<>	144:ef7eb2e8f9f7	7073	* (0: interrupt disabled, 1: interrupt enabled).
<>	144:ef7eb2e8f9f7	7074	* @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
<>	144:ef7eb2e8f9f7	7075	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	7076	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	7077	*/
<>	144:ef7eb2e8f9f7	7078	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	7079	{
<>	144:ef7eb2e8f9f7	7080	return (READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY));
<>	144:ef7eb2e8f9f7	7081	}
<>	144:ef7eb2e8f9f7	7082
<>	144:ef7eb2e8f9f7	7083	/**
<>	144:ef7eb2e8f9f7	7084	* @brief Get state of interruption ADC group regular end of unitary conversion
<>	144:ef7eb2e8f9f7	7085	* (0: interrupt disabled, 1: interrupt enabled).
<>	144:ef7eb2e8f9f7	7086	* @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
<>	144:ef7eb2e8f9f7	7087	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	7088	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	7089	*/
<>	144:ef7eb2e8f9f7	7090	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	7091	{
<>	144:ef7eb2e8f9f7	7092	return (READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC));
<>	144:ef7eb2e8f9f7	7093	}
<>	144:ef7eb2e8f9f7	7094
<>	144:ef7eb2e8f9f7	7095	/**
<>	144:ef7eb2e8f9f7	7096	* @brief Get state of interruption ADC group regular end of sequence conversions
<>	144:ef7eb2e8f9f7	7097	* (0: interrupt disabled, 1: interrupt enabled).
<>	144:ef7eb2e8f9f7	7098	* @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
<>	144:ef7eb2e8f9f7	7099	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	7100	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	7101	*/
<>	144:ef7eb2e8f9f7	7102	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	7103	{
<>	144:ef7eb2e8f9f7	7104	return (READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS));
<>	144:ef7eb2e8f9f7	7105	}
<>	144:ef7eb2e8f9f7	7106
<>	144:ef7eb2e8f9f7	7107	/**
<>	144:ef7eb2e8f9f7	7108	* @brief Get state of interruption ADC group regular overrun
<>	144:ef7eb2e8f9f7	7109	* (0: interrupt disabled, 1: interrupt enabled).
<>	144:ef7eb2e8f9f7	7110	* @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
<>	144:ef7eb2e8f9f7	7111	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	7112	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	7113	*/
<>	144:ef7eb2e8f9f7	7114	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	7115	{
<>	144:ef7eb2e8f9f7	7116	return (READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
<>	144:ef7eb2e8f9f7	7117	}
<>	144:ef7eb2e8f9f7	7118
<>	144:ef7eb2e8f9f7	7119	/**
<>	144:ef7eb2e8f9f7	7120	* @brief Get state of interruption ADC group regular end of sampling
<>	144:ef7eb2e8f9f7	7121	* (0: interrupt disabled, 1: interrupt enabled).
<>	144:ef7eb2e8f9f7	7122	* @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
<>	144:ef7eb2e8f9f7	7123	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	7124	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	7125	*/
<>	144:ef7eb2e8f9f7	7126	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	7127	{
<>	144:ef7eb2e8f9f7	7128	return (READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP));
<>	144:ef7eb2e8f9f7	7129	}
<>	144:ef7eb2e8f9f7	7130
<>	144:ef7eb2e8f9f7	7131	/**
<>	144:ef7eb2e8f9f7	7132	* @brief Get state of interruption ADC group injected end of unitary conversion
<>	144:ef7eb2e8f9f7	7133	* (0: interrupt disabled, 1: interrupt enabled).
<>	144:ef7eb2e8f9f7	7134	* @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
<>	144:ef7eb2e8f9f7	7135	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	7136	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	7137	*/
<>	144:ef7eb2e8f9f7	7138	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	7139	{
<>	144:ef7eb2e8f9f7	7140	return (READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC));
<>	144:ef7eb2e8f9f7	7141	}
<>	144:ef7eb2e8f9f7	7142
<>	144:ef7eb2e8f9f7	7143	/**
<>	144:ef7eb2e8f9f7	7144	* @brief Get state of interruption ADC group injected end of sequence conversions
<>	144:ef7eb2e8f9f7	7145	* (0: interrupt disabled, 1: interrupt enabled).
<>	144:ef7eb2e8f9f7	7146	* @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
<>	144:ef7eb2e8f9f7	7147	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	7148	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	7149	*/
<>	144:ef7eb2e8f9f7	7150	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	7151	{
<>	144:ef7eb2e8f9f7	7152	return (READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
<>	144:ef7eb2e8f9f7	7153	}
<>	144:ef7eb2e8f9f7	7154
<>	144:ef7eb2e8f9f7	7155	/**
<>	144:ef7eb2e8f9f7	7156	* @brief Get state of interruption ADC group injected context queue overflow interrupt state
<>	144:ef7eb2e8f9f7	7157	* (0: interrupt disabled, 1: interrupt enabled).
<>	144:ef7eb2e8f9f7	7158	* @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
<>	144:ef7eb2e8f9f7	7159	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	7160	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	7161	*/
<>	144:ef7eb2e8f9f7	7162	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	7163	{
<>	144:ef7eb2e8f9f7	7164	return (READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF));
<>	144:ef7eb2e8f9f7	7165	}
<>	144:ef7eb2e8f9f7	7166
<>	144:ef7eb2e8f9f7	7167	/**
<>	144:ef7eb2e8f9f7	7168	* @brief Get state of interruption ADC analog watchdog 1
<>	144:ef7eb2e8f9f7	7169	* (0: interrupt disabled, 1: interrupt enabled).
<>	144:ef7eb2e8f9f7	7170	* @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
<>	144:ef7eb2e8f9f7	7171	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	7172	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	7173	*/
<>	144:ef7eb2e8f9f7	7174	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	7175	{
<>	144:ef7eb2e8f9f7	7176	return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
<>	144:ef7eb2e8f9f7	7177	}
<>	144:ef7eb2e8f9f7	7178
<>	144:ef7eb2e8f9f7	7179	/**
<>	144:ef7eb2e8f9f7	7180	* @brief Get state of interruption Get ADC analog watchdog 2
<>	144:ef7eb2e8f9f7	7181	* (0: interrupt disabled, 1: interrupt enabled).
<>	144:ef7eb2e8f9f7	7182	* @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
<>	144:ef7eb2e8f9f7	7183	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	7184	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	7185	*/
<>	144:ef7eb2e8f9f7	7186	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	7187	{
<>	144:ef7eb2e8f9f7	7188	return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2));
<>	144:ef7eb2e8f9f7	7189	}
<>	144:ef7eb2e8f9f7	7190
<>	144:ef7eb2e8f9f7	7191	/**
<>	144:ef7eb2e8f9f7	7192	* @brief Get state of interruption Get ADC analog watchdog 3
<>	144:ef7eb2e8f9f7	7193	* (0: interrupt disabled, 1: interrupt enabled).
<>	144:ef7eb2e8f9f7	7194	* @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
<>	144:ef7eb2e8f9f7	7195	* @param ADCx ADC instance
<>	144:ef7eb2e8f9f7	7196	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	7197	*/
<>	144:ef7eb2e8f9f7	7198	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
<>	144:ef7eb2e8f9f7	7199	{
<>	144:ef7eb2e8f9f7	7200	return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3));
<>	144:ef7eb2e8f9f7	7201	}
<>	144:ef7eb2e8f9f7	7202
<>	144:ef7eb2e8f9f7	7203	/**
<>	144:ef7eb2e8f9f7	7204	* @}
<>	144:ef7eb2e8f9f7	7205	*/
<>	144:ef7eb2e8f9f7	7206
<>	144:ef7eb2e8f9f7	7207	#if defined(USE_FULL_LL_DRIVER)
<>	144:ef7eb2e8f9f7	7208	/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	7209	* @{
<>	144:ef7eb2e8f9f7	7210	*/
<>	144:ef7eb2e8f9f7	7211
<>	144:ef7eb2e8f9f7	7212	/* Initialization of some features of ADC common parameters and multimode */
<>	144:ef7eb2e8f9f7	7213	ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
<>	144:ef7eb2e8f9f7	7214	ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef ADCxy_COMMON, LL_ADC_CommonInitTypeDef ADC_CommonInitStruct);
<>	144:ef7eb2e8f9f7	7215	void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
<>	144:ef7eb2e8f9f7	7216
<>	144:ef7eb2e8f9f7	7217	/* De-initialization of ADC instance, ADC group regular and ADC group injected */
<>	144:ef7eb2e8f9f7	7218	/* (availability of ADC group injected depends on STM32 families) */
<>	144:ef7eb2e8f9f7	7219	ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
<>	144:ef7eb2e8f9f7	7220
<>	144:ef7eb2e8f9f7	7221	/* Initialization of some features of ADC instance */
<>	144:ef7eb2e8f9f7	7222	ErrorStatus LL_ADC_Init(ADC_TypeDef ADCx, LL_ADC_InitTypeDef ADC_InitStruct);
<>	144:ef7eb2e8f9f7	7223	void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
<>	144:ef7eb2e8f9f7	7224
<>	144:ef7eb2e8f9f7	7225	/* Initialization of some features of ADC instance and ADC group regular */
<>	144:ef7eb2e8f9f7	7226	ErrorStatus LL_ADC_REG_Init(ADC_TypeDef ADCx, LL_ADC_REG_InitTypeDef ADC_REG_InitStruct);
<>	144:ef7eb2e8f9f7	7227	void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
<>	144:ef7eb2e8f9f7	7228
<>	144:ef7eb2e8f9f7	7229	/* Initialization of some features of ADC instance and ADC group injected */
<>	144:ef7eb2e8f9f7	7230	ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef ADCx, LL_ADC_INJ_InitTypeDef ADC_INJ_InitStruct);
<>	144:ef7eb2e8f9f7	7231	void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
<>	144:ef7eb2e8f9f7	7232
<>	144:ef7eb2e8f9f7	7233	/**
<>	144:ef7eb2e8f9f7	7234	* @}
<>	144:ef7eb2e8f9f7	7235	*/
<>	144:ef7eb2e8f9f7	7236	#endif /* USE_FULL_LL_DRIVER */
<>	144:ef7eb2e8f9f7	7237
<>	144:ef7eb2e8f9f7	7238	/**
<>	144:ef7eb2e8f9f7	7239	* @}
<>	144:ef7eb2e8f9f7	7240	*/
<>	144:ef7eb2e8f9f7	7241
<>	144:ef7eb2e8f9f7	7242	/**
<>	144:ef7eb2e8f9f7	7243	* @}
<>	144:ef7eb2e8f9f7	7244	*/
<>	144:ef7eb2e8f9f7	7245
<>	144:ef7eb2e8f9f7	7246	#endif /* ADC1 \|\| ADC2 \|\| ADC3 */
<>	144:ef7eb2e8f9f7	7247
<>	144:ef7eb2e8f9f7	7248	/**
<>	144:ef7eb2e8f9f7	7249	* @}
<>	144:ef7eb2e8f9f7	7250	*/
<>	144:ef7eb2e8f9f7	7251
<>	144:ef7eb2e8f9f7	7252	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	7253	}
<>	144:ef7eb2e8f9f7	7254	#endif
<>	144:ef7eb2e8f9f7	7255
<>	144:ef7eb2e8f9f7	7256	#endif /* __STM32L4xx_LL_ADC_H */
<>	144:ef7eb2e8f9f7	7257
<>	144:ef7eb2e8f9f7	7258	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	08 Mar 2017
Imports:	12
Forks:	0
Commits:	165
Dependents:	3
Dependencies:	0
Followers:	5

This repository is Public (Unlisted).

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Greg Steiert

Jesse Marroquin

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targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_ll_adc.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

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targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_ll_adc.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

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