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Dependents: MAX34417_demo MAXREFDES1265 MAXREFDES1265

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_i2c.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:: <>
Date:: Fri Sep 02 15:07:44 2016 +0100
Revision:: 144:ef7eb2e8f9f7
Parent:: 0:9b334a45a8ff

This updates the lib to the mbed lib v125

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32l4xx_hal_i2c.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.5.1
<>	144:ef7eb2e8f9f7	6	* @date 31-May-2016
<>	144:ef7eb2e8f9f7	7	* @brief I2C HAL module driver.
<>	144:ef7eb2e8f9f7	8	* This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	9	* functionalities of the Inter Integrated Circuit (I2C) peripheral:
<>	144:ef7eb2e8f9f7	10	* + Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	11	* + IO operation functions
<>	144:ef7eb2e8f9f7	12	* + Peripheral State and Errors functions
<>	144:ef7eb2e8f9f7	13	*
<>	144:ef7eb2e8f9f7	14	@verbatim
<>	144:ef7eb2e8f9f7	15	==============================================================================
<>	144:ef7eb2e8f9f7	16	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	17	==============================================================================
<>	144:ef7eb2e8f9f7	18	[..]
<>	144:ef7eb2e8f9f7	19	The I2C HAL driver can be used as follows:
<>	144:ef7eb2e8f9f7	20
<>	144:ef7eb2e8f9f7	21	(#) Declare a I2C_HandleTypeDef handle structure, for example:
<>	144:ef7eb2e8f9f7	22	I2C_HandleTypeDef hi2c;
<>	144:ef7eb2e8f9f7	23
<>	144:ef7eb2e8f9f7	24	(#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
<>	144:ef7eb2e8f9f7	25	(##) Enable the I2Cx interface clock
<>	144:ef7eb2e8f9f7	26	(##) I2C pins configuration
<>	144:ef7eb2e8f9f7	27	(+++) Enable the clock for the I2C GPIOs
<>	144:ef7eb2e8f9f7	28	(+++) Configure I2C pins as alternate function open-drain
<>	144:ef7eb2e8f9f7	29	(##) NVIC configuration if you need to use interrupt process
<>	144:ef7eb2e8f9f7	30	(+++) Configure the I2Cx interrupt priority
<>	144:ef7eb2e8f9f7	31	(+++) Enable the NVIC I2C IRQ Channel
<>	144:ef7eb2e8f9f7	32	(##) DMA Configuration if you need to use DMA process
<>	144:ef7eb2e8f9f7	33	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
<>	144:ef7eb2e8f9f7	34	(+++) Enable the DMAx interface clock using
<>	144:ef7eb2e8f9f7	35	(+++) Configure the DMA handle parameters
<>	144:ef7eb2e8f9f7	36	(+++) Configure the DMA Tx or Rx channel
<>	144:ef7eb2e8f9f7	37	(+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
<>	144:ef7eb2e8f9f7	38	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
<>	144:ef7eb2e8f9f7	39	the DMA Tx or Rx channel
<>	144:ef7eb2e8f9f7	40
<>	144:ef7eb2e8f9f7	41	(#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
<>	144:ef7eb2e8f9f7	42	Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
<>	144:ef7eb2e8f9f7	43
<>	144:ef7eb2e8f9f7	44	(#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
<>	144:ef7eb2e8f9f7	45	(GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
<>	144:ef7eb2e8f9f7	46
<>	144:ef7eb2e8f9f7	47	(#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	(#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
<>	144:ef7eb2e8f9f7	50
<>	144:ef7eb2e8f9f7	51	* Polling mode IO operation *
<>	144:ef7eb2e8f9f7	52	=================================
<>	144:ef7eb2e8f9f7	53	[..]
<>	144:ef7eb2e8f9f7	54	(+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
<>	144:ef7eb2e8f9f7	55	(+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
<>	144:ef7eb2e8f9f7	56	(+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
<>	144:ef7eb2e8f9f7	57	(+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
<>	144:ef7eb2e8f9f7	58
<>	144:ef7eb2e8f9f7	59	* Polling mode IO MEM operation *
<>	144:ef7eb2e8f9f7	60	=====================================
<>	144:ef7eb2e8f9f7	61	[..]
<>	144:ef7eb2e8f9f7	62	(+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
<>	144:ef7eb2e8f9f7	63	(+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
<>	144:ef7eb2e8f9f7	64
<>	144:ef7eb2e8f9f7	65
<>	144:ef7eb2e8f9f7	66	* Interrupt mode IO operation *
<>	144:ef7eb2e8f9f7	67	===================================
<>	144:ef7eb2e8f9f7	68	[..]
<>	144:ef7eb2e8f9f7	69	(+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
<>	144:ef7eb2e8f9f7	70	(+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	71	add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
<>	144:ef7eb2e8f9f7	72	(+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
<>	144:ef7eb2e8f9f7	73	(+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	74	add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
<>	144:ef7eb2e8f9f7	75	(+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
<>	144:ef7eb2e8f9f7	76	(+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	77	add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
<>	144:ef7eb2e8f9f7	78	(+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
<>	144:ef7eb2e8f9f7	79	(+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	80	add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
<>	144:ef7eb2e8f9f7	81	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	82	add his own code by customization of function pointer HAL_I2C_ErrorCallback()
<>	144:ef7eb2e8f9f7	83	(+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
<>	144:ef7eb2e8f9f7	84	(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	85	add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
<>	144:ef7eb2e8f9f7	86	(+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
<>	144:ef7eb2e8f9f7	87	This action will inform Master to generate a Stop condition to discard the communication.
<>	144:ef7eb2e8f9f7	88
<>	144:ef7eb2e8f9f7	89
<>	144:ef7eb2e8f9f7	90	* Interrupt mode IO sequential operation *
<>	144:ef7eb2e8f9f7	91	===================================
<>	144:ef7eb2e8f9f7	92	[..]
<>	144:ef7eb2e8f9f7	93	(@) These interfaces allow to manage a sequential transfer with a repeated start condition
<>	144:ef7eb2e8f9f7	94	when a direction change during transfer
<>	144:ef7eb2e8f9f7	95	[..]
<>	144:ef7eb2e8f9f7	96	(+) A specific option field manage the different steps of a sequential transfer
<>	144:ef7eb2e8f9f7	97	(+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
<>	144:ef7eb2e8f9f7	98	(++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
<>	144:ef7eb2e8f9f7	99	(++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
<>	144:ef7eb2e8f9f7	100	and data to transfer without a final stop condition
<>	144:ef7eb2e8f9f7	101	(++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
<>	144:ef7eb2e8f9f7	102	and with new data to transfer if the direction change or manage only the new data to transfer
<>	144:ef7eb2e8f9f7	103	if no direction change and without a final stop condition in both cases
<>	144:ef7eb2e8f9f7	104	(++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
<>	144:ef7eb2e8f9f7	105	and with new data to transfer if the direction change or manage only the new data to transfer
<>	144:ef7eb2e8f9f7	106	if no direction change and with a final stop condition in both cases
<>	144:ef7eb2e8f9f7	107
<>	144:ef7eb2e8f9f7	108	(+) Differents sequential I2C interfaces are listed below:
<>	144:ef7eb2e8f9f7	109	(++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
<>	144:ef7eb2e8f9f7	110	(+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	111	add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
<>	144:ef7eb2e8f9f7	112	(++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
<>	144:ef7eb2e8f9f7	113	(+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	114	add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
<>	144:ef7eb2e8f9f7	115	(++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
<>	144:ef7eb2e8f9f7	116	(+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	117	add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
<>	144:ef7eb2e8f9f7	118	(+++) mean HAL_I2C_MasterTxCpltCallback() in case of previous state was master transmit
<>	144:ef7eb2e8f9f7	119	(+++) mean HAL_I2c_MasterRxCpltCallback() in case of previous state was master receive
<>	144:ef7eb2e8f9f7	120	(++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
<>	144:ef7eb2e8f9f7	121	(+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
<>	144:ef7eb2e8f9f7	122	add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
<>	144:ef7eb2e8f9f7	123	(+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	124	add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
<>	144:ef7eb2e8f9f7	125	(++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
<>	144:ef7eb2e8f9f7	126	(+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	127	add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
<>	144:ef7eb2e8f9f7	128	(++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
<>	144:ef7eb2e8f9f7	129	(+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	130	add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
<>	144:ef7eb2e8f9f7	131	(++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	132	add his own code by customization of function pointer HAL_I2C_ErrorCallback()
<>	144:ef7eb2e8f9f7	133	(++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
<>	144:ef7eb2e8f9f7	134	(++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	135	add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
<>	144:ef7eb2e8f9f7	136	(++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
<>	144:ef7eb2e8f9f7	137	This action will inform Master to generate a Stop condition to discard the communication.
<>	144:ef7eb2e8f9f7	138
<>	144:ef7eb2e8f9f7	139	* Interrupt mode IO MEM operation *
<>	144:ef7eb2e8f9f7	140	=======================================
<>	144:ef7eb2e8f9f7	141	[..]
<>	144:ef7eb2e8f9f7	142	(+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
<>	144:ef7eb2e8f9f7	143	HAL_I2C_Mem_Write_IT()
<>	144:ef7eb2e8f9f7	144	(+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	145	add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
<>	144:ef7eb2e8f9f7	146	(+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
<>	144:ef7eb2e8f9f7	147	HAL_I2C_Mem_Read_IT()
<>	144:ef7eb2e8f9f7	148	(+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	149	add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
<>	144:ef7eb2e8f9f7	150	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	151	add his own code by customization of function pointer HAL_I2C_ErrorCallback()
<>	144:ef7eb2e8f9f7	152
<>	144:ef7eb2e8f9f7	153	* DMA mode IO operation *
<>	144:ef7eb2e8f9f7	154	==============================
<>	144:ef7eb2e8f9f7	155	[..]
<>	144:ef7eb2e8f9f7	156	(+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
<>	144:ef7eb2e8f9f7	157	HAL_I2C_Master_Transmit_DMA()
<>	144:ef7eb2e8f9f7	158	(+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	159	add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
<>	144:ef7eb2e8f9f7	160	(+) Receive in master mode an amount of data in non-blocking mode (DMA) using
<>	144:ef7eb2e8f9f7	161	HAL_I2C_Master_Receive_DMA()
<>	144:ef7eb2e8f9f7	162	(+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	163	add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
<>	144:ef7eb2e8f9f7	164	(+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
<>	144:ef7eb2e8f9f7	165	HAL_I2C_Slave_Transmit_DMA()
<>	144:ef7eb2e8f9f7	166	(+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	167	add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
<>	144:ef7eb2e8f9f7	168	(+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
<>	144:ef7eb2e8f9f7	169	HAL_I2C_Slave_Receive_DMA()
<>	144:ef7eb2e8f9f7	170	(+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	171	add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
<>	144:ef7eb2e8f9f7	172	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	173	add his own code by customization of function pointer HAL_I2C_ErrorCallback()
<>	144:ef7eb2e8f9f7	174	(+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
<>	144:ef7eb2e8f9f7	175	(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	176	add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
<>	144:ef7eb2e8f9f7	177	(+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
<>	144:ef7eb2e8f9f7	178	This action will inform Master to generate a Stop condition to discard the communication.
<>	144:ef7eb2e8f9f7	179
<>	144:ef7eb2e8f9f7	180	* DMA mode IO MEM operation *
<>	144:ef7eb2e8f9f7	181	=================================
<>	144:ef7eb2e8f9f7	182	[..]
<>	144:ef7eb2e8f9f7	183	(+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
<>	144:ef7eb2e8f9f7	184	HAL_I2C_Mem_Write_DMA()
<>	144:ef7eb2e8f9f7	185	(+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	186	add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
<>	144:ef7eb2e8f9f7	187	(+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
<>	144:ef7eb2e8f9f7	188	HAL_I2C_Mem_Read_DMA()
<>	144:ef7eb2e8f9f7	189	(+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	190	add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
<>	144:ef7eb2e8f9f7	191	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	192	add his own code by customization of function pointer HAL_I2C_ErrorCallback()
<>	144:ef7eb2e8f9f7	193
<>	144:ef7eb2e8f9f7	194
<>	144:ef7eb2e8f9f7	195	* I2C HAL driver macros list *
<>	144:ef7eb2e8f9f7	196	==================================
<>	144:ef7eb2e8f9f7	197	[..]
<>	144:ef7eb2e8f9f7	198	Below the list of most used macros in I2C HAL driver.
<>	144:ef7eb2e8f9f7	199
<>	144:ef7eb2e8f9f7	200	(+) __HAL_I2C_ENABLE: Enable the I2C peripheral
<>	144:ef7eb2e8f9f7	201	(+) __HAL_I2C_DISABLE: Disable the I2C peripheral
<>	144:ef7eb2e8f9f7	202	(+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
<>	144:ef7eb2e8f9f7	203	(+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
<>	144:ef7eb2e8f9f7	204	(+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
<>	144:ef7eb2e8f9f7	205	(+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
<>	144:ef7eb2e8f9f7	206	(+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
<>	144:ef7eb2e8f9f7	207
<>	144:ef7eb2e8f9f7	208	[..]
<>	144:ef7eb2e8f9f7	209	(@) You can refer to the I2C HAL driver header file for more useful macros
<>	144:ef7eb2e8f9f7	210
<>	144:ef7eb2e8f9f7	211	@endverbatim
<>	144:ef7eb2e8f9f7	212	******************************************************************************
<>	144:ef7eb2e8f9f7	213	* @attention
<>	144:ef7eb2e8f9f7	214	*
<>	144:ef7eb2e8f9f7	215	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	216	*
<>	144:ef7eb2e8f9f7	217	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	218	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	219	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	220	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	221	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	222	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	223	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	224	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	225	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	226	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	227	*
<>	144:ef7eb2e8f9f7	228	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	229	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	230	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	231	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	232	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	233	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	234	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	235	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	236	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	237	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	238	*
<>	144:ef7eb2e8f9f7	239	******************************************************************************
<>	144:ef7eb2e8f9f7	240	*/
<>	144:ef7eb2e8f9f7	241
<>	144:ef7eb2e8f9f7	242	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	243	#include "stm32l4xx_hal.h"
<>	144:ef7eb2e8f9f7	244
<>	144:ef7eb2e8f9f7	245	/** @addtogroup STM32L4xx_HAL_Driver
<>	144:ef7eb2e8f9f7	246	* @{
<>	144:ef7eb2e8f9f7	247	*/
<>	144:ef7eb2e8f9f7	248
<>	144:ef7eb2e8f9f7	249	/** @defgroup I2C I2C
<>	144:ef7eb2e8f9f7	250	* @brief I2C HAL module driver
<>	144:ef7eb2e8f9f7	251	* @{
<>	144:ef7eb2e8f9f7	252	*/
<>	144:ef7eb2e8f9f7	253
<>	144:ef7eb2e8f9f7	254	#ifdef HAL_I2C_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	255
<>	144:ef7eb2e8f9f7	256	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	257	/* Private define ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	258
<>	144:ef7eb2e8f9f7	259	/** @defgroup I2C_Private_Define I2C Private Define
<>	144:ef7eb2e8f9f7	260	* @{
<>	144:ef7eb2e8f9f7	261	*/
<>	144:ef7eb2e8f9f7	262	#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /!< I2C TIMING clear register Mask /
<>	144:ef7eb2e8f9f7	263	#define I2C_TIMEOUT_ADDR (10000U) /!< 10 s /
<>	144:ef7eb2e8f9f7	264	#define I2C_TIMEOUT_BUSY (25U) /!< 25 ms /
<>	144:ef7eb2e8f9f7	265	#define I2C_TIMEOUT_DIR (25U) /!< 25 ms /
<>	144:ef7eb2e8f9f7	266	#define I2C_TIMEOUT_RXNE (25U) /!< 25 ms /
<>	144:ef7eb2e8f9f7	267	#define I2C_TIMEOUT_STOPF (25U) /!< 25 ms /
<>	144:ef7eb2e8f9f7	268	#define I2C_TIMEOUT_TC (25U) /!< 25 ms /
<>	144:ef7eb2e8f9f7	269	#define I2C_TIMEOUT_TCR (25U) /!< 25 ms /
<>	144:ef7eb2e8f9f7	270	#define I2C_TIMEOUT_TXIS (25U) /!< 25 ms /
<>	144:ef7eb2e8f9f7	271	#define I2C_TIMEOUT_FLAG (25U) /!< 25 ms /
<>	144:ef7eb2e8f9f7	272
<>	144:ef7eb2e8f9f7	273	#define MAX_NBYTE_SIZE 255U
<>	144:ef7eb2e8f9f7	274	#define SlaveAddr_SHIFT 7U
<>	144:ef7eb2e8f9f7	275	#define SlaveAddr_MSK 0x06U
<>	144:ef7eb2e8f9f7	276
<>	144:ef7eb2e8f9f7	277	/* Private define for @ref PreviousState usage */
<>	144:ef7eb2e8f9f7	278	#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX \| HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~HAL_I2C_STATE_READY))) /!< Mask State define, keep only RX and TX bits /
<>	144:ef7eb2e8f9f7	279	#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /!< Default Value /
<>	144:ef7eb2e8f9f7	280	#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) \| HAL_I2C_MODE_MASTER)) /!< Master Busy TX, combinaison of State LSB and Mode enum /
<>	144:ef7eb2e8f9f7	281	#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) \| HAL_I2C_MODE_MASTER)) /!< Master Busy RX, combinaison of State LSB and Mode enum /
<>	144:ef7eb2e8f9f7	282	#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) \| HAL_I2C_MODE_SLAVE)) /!< Slave Busy TX, combinaison of State LSB and Mode enum /
<>	144:ef7eb2e8f9f7	283	#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) \| HAL_I2C_MODE_SLAVE)) /!< Slave Busy RX, combinaison of State LSB and Mode enum /
<>	144:ef7eb2e8f9f7	284	#define I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) \| HAL_I2C_MODE_MEM)) /!< Memory Busy TX, combinaison of State LSB and Mode enum /
<>	144:ef7eb2e8f9f7	285	#define I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) \| HAL_I2C_MODE_MEM)) /!< Memory Busy RX, combinaison of State LSB and Mode enum /
<>	144:ef7eb2e8f9f7	286
<>	144:ef7eb2e8f9f7	287
<>	144:ef7eb2e8f9f7	288	/* Private define to centralize the enable/disable of Interrupts */
<>	144:ef7eb2e8f9f7	289	#define I2C_XFER_TX_IT (0x00000001U)
<>	144:ef7eb2e8f9f7	290	#define I2C_XFER_RX_IT (0x00000002U)
<>	144:ef7eb2e8f9f7	291	#define I2C_XFER_LISTEN_IT (0x00000004U)
<>	144:ef7eb2e8f9f7	292
<>	144:ef7eb2e8f9f7	293	#define I2C_XFER_ERROR_IT (0x00000011U)
<>	144:ef7eb2e8f9f7	294	#define I2C_XFER_CPLT_IT (0x00000012U)
<>	144:ef7eb2e8f9f7	295	#define I2C_XFER_RELOAD_IT (0x00000012U)
<>	144:ef7eb2e8f9f7	296	/**
<>	144:ef7eb2e8f9f7	297	* @}
<>	144:ef7eb2e8f9f7	298	*/
<>	144:ef7eb2e8f9f7	299
<>	144:ef7eb2e8f9f7	300	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	301	#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \
<>	144:ef7eb2e8f9f7	302	((uint32_t)((__HANDLE__)->hdmatx->Instance->CNDTR)) : \
<>	144:ef7eb2e8f9f7	303	((uint32_t)((__HANDLE__)->hdmarx->Instance->CNDTR)))
<>	144:ef7eb2e8f9f7	304
<>	144:ef7eb2e8f9f7	305	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	306	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	307
<>	144:ef7eb2e8f9f7	308	/** @defgroup I2C_Private_Functions I2C Private Functions
<>	144:ef7eb2e8f9f7	309	* @{
<>	144:ef7eb2e8f9f7	310	*/
<>	144:ef7eb2e8f9f7	311	/* Private functions to handle DMA transfer */
<>	144:ef7eb2e8f9f7	312	static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	313	static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	314	static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	315	static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	316	static void I2C_DMAError(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	317	static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	318
<>	144:ef7eb2e8f9f7	319	/* Private functions to handle IT transfer */
<>	144:ef7eb2e8f9f7	320	static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
<>	144:ef7eb2e8f9f7	321	static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	322	static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	323	static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
<>	144:ef7eb2e8f9f7	324	static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
<>	144:ef7eb2e8f9f7	325	static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
<>	144:ef7eb2e8f9f7	326	static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
<>	144:ef7eb2e8f9f7	327
<>	144:ef7eb2e8f9f7	328	/* Private functions to handle IT transfer */
<>	144:ef7eb2e8f9f7	329	static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	330	static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	331
<>	144:ef7eb2e8f9f7	332	/* Private functions for I2C transfer IRQ handler */
<>	144:ef7eb2e8f9f7	333	static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
<>	144:ef7eb2e8f9f7	334	static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
<>	144:ef7eb2e8f9f7	335	static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
<>	144:ef7eb2e8f9f7	336	static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
<>	144:ef7eb2e8f9f7	337
<>	144:ef7eb2e8f9f7	338	/* Private functions to handle flags during polling transfer */
<>	144:ef7eb2e8f9f7	339	static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	340	static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	341	static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	342	static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	343	static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	344
<>	144:ef7eb2e8f9f7	345	/* Private functions to centralize the enable/disable of Interrupts */
<>	144:ef7eb2e8f9f7	346	static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
<>	144:ef7eb2e8f9f7	347	static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
<>	144:ef7eb2e8f9f7	348
<>	144:ef7eb2e8f9f7	349	/* Private functions to flush TXDR register */
<>	144:ef7eb2e8f9f7	350	static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	351
<>	144:ef7eb2e8f9f7	352	/* Private functions to handle start, restart or stop a transfer */
<>	144:ef7eb2e8f9f7	353	static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
<>	144:ef7eb2e8f9f7	354	/**
<>	144:ef7eb2e8f9f7	355	* @}
<>	144:ef7eb2e8f9f7	356	*/
<>	144:ef7eb2e8f9f7	357
<>	144:ef7eb2e8f9f7	358	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	359
<>	144:ef7eb2e8f9f7	360	/** @defgroup I2C_Exported_Functions I2C Exported Functions
<>	144:ef7eb2e8f9f7	361	* @{
<>	144:ef7eb2e8f9f7	362	*/
<>	144:ef7eb2e8f9f7	363
<>	144:ef7eb2e8f9f7	364	/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	365	* @brief Initialization and Configuration functions
<>	144:ef7eb2e8f9f7	366	*
<>	144:ef7eb2e8f9f7	367	@verbatim
<>	144:ef7eb2e8f9f7	368	===============================================================================
<>	144:ef7eb2e8f9f7	369	##### Initialization and de-initialization functions #####
<>	144:ef7eb2e8f9f7	370	===============================================================================
<>	144:ef7eb2e8f9f7	371	[..] This subsection provides a set of functions allowing to initialize and
<>	144:ef7eb2e8f9f7	372	deinitialize the I2Cx peripheral:
<>	144:ef7eb2e8f9f7	373
<>	144:ef7eb2e8f9f7	374	(+) User must Implement HAL_I2C_MspInit() function in which he configures
<>	144:ef7eb2e8f9f7	375	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
<>	144:ef7eb2e8f9f7	376
<>	144:ef7eb2e8f9f7	377	(+) Call the function HAL_I2C_Init() to configure the selected device with
<>	144:ef7eb2e8f9f7	378	the selected configuration:
<>	144:ef7eb2e8f9f7	379	(++) Clock Timing
<>	144:ef7eb2e8f9f7	380	(++) Own Address 1
<>	144:ef7eb2e8f9f7	381	(++) Addressing mode (Master, Slave)
<>	144:ef7eb2e8f9f7	382	(++) Dual Addressing mode
<>	144:ef7eb2e8f9f7	383	(++) Own Address 2
<>	144:ef7eb2e8f9f7	384	(++) Own Address 2 Mask
<>	144:ef7eb2e8f9f7	385	(++) General call mode
<>	144:ef7eb2e8f9f7	386	(++) Nostretch mode
<>	144:ef7eb2e8f9f7	387
<>	144:ef7eb2e8f9f7	388	(+) Call the function HAL_I2C_DeInit() to restore the default configuration
<>	144:ef7eb2e8f9f7	389	of the selected I2Cx peripheral.
<>	144:ef7eb2e8f9f7	390
<>	144:ef7eb2e8f9f7	391	@endverbatim
<>	144:ef7eb2e8f9f7	392	* @{
<>	144:ef7eb2e8f9f7	393	*/
<>	144:ef7eb2e8f9f7	394
<>	144:ef7eb2e8f9f7	395	/**
<>	144:ef7eb2e8f9f7	396	* @brief Initializes the I2C according to the specified parameters
<>	144:ef7eb2e8f9f7	397	* in the I2C_InitTypeDef and initialize the associated handle.
<>	144:ef7eb2e8f9f7	398	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	399	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	400	* @retval HAL status
<>	144:ef7eb2e8f9f7	401	*/
<>	144:ef7eb2e8f9f7	402	HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	403	{
<>	144:ef7eb2e8f9f7	404	/* Check the I2C handle allocation */
<>	144:ef7eb2e8f9f7	405	if(hi2c == NULL)
<>	144:ef7eb2e8f9f7	406	{
<>	144:ef7eb2e8f9f7	407	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	408	}
<>	144:ef7eb2e8f9f7	409
<>	144:ef7eb2e8f9f7	410	/* Check the parameters */
<>	144:ef7eb2e8f9f7	411	assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
<>	144:ef7eb2e8f9f7	412	assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
<>	144:ef7eb2e8f9f7	413	assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
<>	144:ef7eb2e8f9f7	414	assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
<>	144:ef7eb2e8f9f7	415	assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
<>	144:ef7eb2e8f9f7	416	assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
<>	144:ef7eb2e8f9f7	417	assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
<>	144:ef7eb2e8f9f7	418	assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
<>	144:ef7eb2e8f9f7	419
<>	144:ef7eb2e8f9f7	420	if(hi2c->State == HAL_I2C_STATE_RESET)
<>	144:ef7eb2e8f9f7	421	{
<>	144:ef7eb2e8f9f7	422	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	423	hi2c->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	424
<>	144:ef7eb2e8f9f7	425	/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
<>	144:ef7eb2e8f9f7	426	HAL_I2C_MspInit(hi2c);
<>	144:ef7eb2e8f9f7	427	}
<>	144:ef7eb2e8f9f7	428
<>	144:ef7eb2e8f9f7	429	hi2c->State = HAL_I2C_STATE_BUSY;
<>	144:ef7eb2e8f9f7	430
<>	144:ef7eb2e8f9f7	431	/* Disable the selected I2C peripheral */
<>	144:ef7eb2e8f9f7	432	__HAL_I2C_DISABLE(hi2c);
<>	144:ef7eb2e8f9f7	433
<>	144:ef7eb2e8f9f7	434	/---------------------------- I2Cx TIMINGR Configuration ------------------/
<>	144:ef7eb2e8f9f7	435	/* Configure I2Cx: Frequency range */
<>	144:ef7eb2e8f9f7	436	hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
<>	144:ef7eb2e8f9f7	437
<>	144:ef7eb2e8f9f7	438	/---------------------------- I2Cx OAR1 Configuration ---------------------/
<>	144:ef7eb2e8f9f7	439	/* Configure I2Cx: Own Address1 and ack own address1 mode */
<>	144:ef7eb2e8f9f7	440	hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
<>	144:ef7eb2e8f9f7	441	if(hi2c->Init.OwnAddress1 != 0U)
<>	144:ef7eb2e8f9f7	442	{
<>	144:ef7eb2e8f9f7	443	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
<>	144:ef7eb2e8f9f7	444	{
<>	144:ef7eb2e8f9f7	445	hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN \| hi2c->Init.OwnAddress1);
<>	144:ef7eb2e8f9f7	446	}
<>	144:ef7eb2e8f9f7	447	else /* I2C_ADDRESSINGMODE_10BIT */
<>	144:ef7eb2e8f9f7	448	{
<>	144:ef7eb2e8f9f7	449	hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN \| I2C_OAR1_OA1MODE \| hi2c->Init.OwnAddress1);
<>	144:ef7eb2e8f9f7	450	}
<>	144:ef7eb2e8f9f7	451	}
<>	144:ef7eb2e8f9f7	452
<>	144:ef7eb2e8f9f7	453	/---------------------------- I2Cx CR2 Configuration ----------------------/
<>	144:ef7eb2e8f9f7	454	/* Configure I2Cx: Addressing Master mode */
<>	144:ef7eb2e8f9f7	455	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
<>	144:ef7eb2e8f9f7	456	{
<>	144:ef7eb2e8f9f7	457	hi2c->Instance->CR2 = (I2C_CR2_ADD10);
<>	144:ef7eb2e8f9f7	458	}
<>	144:ef7eb2e8f9f7	459	/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
<>	144:ef7eb2e8f9f7	460	hi2c->Instance->CR2 \|= (I2C_CR2_AUTOEND \| I2C_CR2_NACK);
<>	144:ef7eb2e8f9f7	461
<>	144:ef7eb2e8f9f7	462	/---------------------------- I2Cx OAR2 Configuration ---------------------/
<>	144:ef7eb2e8f9f7	463	/* Configure I2Cx: Dual mode and Own Address2 */
<>	144:ef7eb2e8f9f7	464	hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode \| hi2c->Init.OwnAddress2 \| (hi2c->Init.OwnAddress2Masks << 8));
<>	144:ef7eb2e8f9f7	465
<>	144:ef7eb2e8f9f7	466	/---------------------------- I2Cx CR1 Configuration ----------------------/
<>	144:ef7eb2e8f9f7	467	/* Configure I2Cx: Generalcall and NoStretch mode */
<>	144:ef7eb2e8f9f7	468	hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode \| hi2c->Init.NoStretchMode);
<>	144:ef7eb2e8f9f7	469
<>	144:ef7eb2e8f9f7	470	/* Enable the selected I2C peripheral */
<>	144:ef7eb2e8f9f7	471	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	472
<>	144:ef7eb2e8f9f7	473	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	474	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	475	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	476	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	477
<>	144:ef7eb2e8f9f7	478	return HAL_OK;
<>	144:ef7eb2e8f9f7	479	}
<>	144:ef7eb2e8f9f7	480
<>	144:ef7eb2e8f9f7	481	/**
<>	144:ef7eb2e8f9f7	482	* @brief DeInitialize the I2C peripheral.
<>	144:ef7eb2e8f9f7	483	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	484	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	485	* @retval HAL status
<>	144:ef7eb2e8f9f7	486	*/
<>	144:ef7eb2e8f9f7	487	HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	488	{
<>	144:ef7eb2e8f9f7	489	/* Check the I2C handle allocation */
<>	144:ef7eb2e8f9f7	490	if(hi2c == NULL)
<>	144:ef7eb2e8f9f7	491	{
<>	144:ef7eb2e8f9f7	492	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	493	}
<>	144:ef7eb2e8f9f7	494
<>	144:ef7eb2e8f9f7	495	/* Check the parameters */
<>	144:ef7eb2e8f9f7	496	assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
<>	144:ef7eb2e8f9f7	497
<>	144:ef7eb2e8f9f7	498	hi2c->State = HAL_I2C_STATE_BUSY;
<>	144:ef7eb2e8f9f7	499
<>	144:ef7eb2e8f9f7	500	/* Disable the I2C Peripheral Clock */
<>	144:ef7eb2e8f9f7	501	__HAL_I2C_DISABLE(hi2c);
<>	144:ef7eb2e8f9f7	502
<>	144:ef7eb2e8f9f7	503	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<>	144:ef7eb2e8f9f7	504	HAL_I2C_MspDeInit(hi2c);
<>	144:ef7eb2e8f9f7	505
<>	144:ef7eb2e8f9f7	506	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	507	hi2c->State = HAL_I2C_STATE_RESET;
<>	144:ef7eb2e8f9f7	508	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	509	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	510
<>	144:ef7eb2e8f9f7	511	/* Release Lock */
<>	144:ef7eb2e8f9f7	512	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	513
<>	144:ef7eb2e8f9f7	514	return HAL_OK;
<>	144:ef7eb2e8f9f7	515	}
<>	144:ef7eb2e8f9f7	516
<>	144:ef7eb2e8f9f7	517	/**
<>	144:ef7eb2e8f9f7	518	* @brief Initialize the I2C MSP.
<>	144:ef7eb2e8f9f7	519	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	520	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	521	* @retval None
<>	144:ef7eb2e8f9f7	522	*/
<>	144:ef7eb2e8f9f7	523	__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	524	{
<>	144:ef7eb2e8f9f7	525	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	526	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	527
<>	144:ef7eb2e8f9f7	528	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	529	the HAL_I2C_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	530	*/
<>	144:ef7eb2e8f9f7	531	}
<>	144:ef7eb2e8f9f7	532
<>	144:ef7eb2e8f9f7	533	/**
<>	144:ef7eb2e8f9f7	534	* @brief DeInitialize the I2C MSP.
<>	144:ef7eb2e8f9f7	535	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	536	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	537	* @retval None
<>	144:ef7eb2e8f9f7	538	*/
<>	144:ef7eb2e8f9f7	539	__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	540	{
<>	144:ef7eb2e8f9f7	541	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	542	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	543
<>	144:ef7eb2e8f9f7	544	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	545	the HAL_I2C_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	546	*/
<>	144:ef7eb2e8f9f7	547	}
<>	144:ef7eb2e8f9f7	548
<>	144:ef7eb2e8f9f7	549	/**
<>	144:ef7eb2e8f9f7	550	* @}
<>	144:ef7eb2e8f9f7	551	*/
<>	144:ef7eb2e8f9f7	552
<>	144:ef7eb2e8f9f7	553	/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
<>	144:ef7eb2e8f9f7	554	* @brief Data transfers functions
<>	144:ef7eb2e8f9f7	555	*
<>	144:ef7eb2e8f9f7	556	@verbatim
<>	144:ef7eb2e8f9f7	557	===============================================================================
<>	144:ef7eb2e8f9f7	558	##### IO operation functions #####
<>	144:ef7eb2e8f9f7	559	===============================================================================
<>	144:ef7eb2e8f9f7	560	[..]
<>	144:ef7eb2e8f9f7	561	This subsection provides a set of functions allowing to manage the I2C data
<>	144:ef7eb2e8f9f7	562	transfers.
<>	144:ef7eb2e8f9f7	563
<>	144:ef7eb2e8f9f7	564	(#) There are two modes of transfer:
<>	144:ef7eb2e8f9f7	565	(++) Blocking mode : The communication is performed in the polling mode.
<>	144:ef7eb2e8f9f7	566	The status of all data processing is returned by the same function
<>	144:ef7eb2e8f9f7	567	after finishing transfer.
<>	144:ef7eb2e8f9f7	568	(++) No-Blocking mode : The communication is performed using Interrupts
<>	144:ef7eb2e8f9f7	569	or DMA. These functions return the status of the transfer startup.
<>	144:ef7eb2e8f9f7	570	The end of the data processing will be indicated through the
<>	144:ef7eb2e8f9f7	571	dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
<>	144:ef7eb2e8f9f7	572	using DMA mode.
<>	144:ef7eb2e8f9f7	573
<>	144:ef7eb2e8f9f7	574	(#) Blocking mode functions are :
<>	144:ef7eb2e8f9f7	575	(++) HAL_I2C_Master_Transmit()
<>	144:ef7eb2e8f9f7	576	(++) HAL_I2C_Master_Receive()
<>	144:ef7eb2e8f9f7	577	(++) HAL_I2C_Slave_Transmit()
<>	144:ef7eb2e8f9f7	578	(++) HAL_I2C_Slave_Receive()
<>	144:ef7eb2e8f9f7	579	(++) HAL_I2C_Mem_Write()
<>	144:ef7eb2e8f9f7	580	(++) HAL_I2C_Mem_Read()
<>	144:ef7eb2e8f9f7	581	(++) HAL_I2C_IsDeviceReady()
<>	144:ef7eb2e8f9f7	582
<>	144:ef7eb2e8f9f7	583	(#) No-Blocking mode functions with Interrupt are :
<>	144:ef7eb2e8f9f7	584	(++) HAL_I2C_Master_Transmit_IT()
<>	144:ef7eb2e8f9f7	585	(++) HAL_I2C_Master_Receive_IT()
<>	144:ef7eb2e8f9f7	586	(++) HAL_I2C_Slave_Transmit_IT()
<>	144:ef7eb2e8f9f7	587	(++) HAL_I2C_Slave_Receive_IT()
<>	144:ef7eb2e8f9f7	588	(++) HAL_I2C_Mem_Write_IT()
<>	144:ef7eb2e8f9f7	589	(++) HAL_I2C_Mem_Read_IT()
<>	144:ef7eb2e8f9f7	590
<>	144:ef7eb2e8f9f7	591	(#) No-Blocking mode functions with DMA are :
<>	144:ef7eb2e8f9f7	592	(++) HAL_I2C_Master_Transmit_DMA()
<>	144:ef7eb2e8f9f7	593	(++) HAL_I2C_Master_Receive_DMA()
<>	144:ef7eb2e8f9f7	594	(++) HAL_I2C_Slave_Transmit_DMA()
<>	144:ef7eb2e8f9f7	595	(++) HAL_I2C_Slave_Receive_DMA()
<>	144:ef7eb2e8f9f7	596	(++) HAL_I2C_Mem_Write_DMA()
<>	144:ef7eb2e8f9f7	597	(++) HAL_I2C_Mem_Read_DMA()
<>	144:ef7eb2e8f9f7	598
<>	144:ef7eb2e8f9f7	599	(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
<>	144:ef7eb2e8f9f7	600	(++) HAL_I2C_MemTxCpltCallback()
<>	144:ef7eb2e8f9f7	601	(++) HAL_I2C_MemRxCpltCallback()
<>	144:ef7eb2e8f9f7	602	(++) HAL_I2C_MasterTxCpltCallback()
<>	144:ef7eb2e8f9f7	603	(++) HAL_I2C_MasterRxCpltCallback()
<>	144:ef7eb2e8f9f7	604	(++) HAL_I2C_SlaveTxCpltCallback()
<>	144:ef7eb2e8f9f7	605	(++) HAL_I2C_SlaveRxCpltCallback()
<>	144:ef7eb2e8f9f7	606	(++) HAL_I2C_ErrorCallback()
<>	144:ef7eb2e8f9f7	607
<>	144:ef7eb2e8f9f7	608	@endverbatim
<>	144:ef7eb2e8f9f7	609	* @{
<>	144:ef7eb2e8f9f7	610	*/
<>	144:ef7eb2e8f9f7	611
<>	144:ef7eb2e8f9f7	612	/**
<>	144:ef7eb2e8f9f7	613	* @brief Transmits in master mode an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	614	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	615	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	616	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	617	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	618	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	619	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	620	* @retval HAL status
<>	144:ef7eb2e8f9f7	621	*/
<>	144:ef7eb2e8f9f7	622	HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	623	{
<>	144:ef7eb2e8f9f7	624	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	625
<>	144:ef7eb2e8f9f7	626	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	627	{
<>	144:ef7eb2e8f9f7	628	/* Process Locked */
<>	144:ef7eb2e8f9f7	629	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	630
<>	144:ef7eb2e8f9f7	631	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	632	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	633
<>	144:ef7eb2e8f9f7	634	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	635	{
<>	144:ef7eb2e8f9f7	636	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	637	}
<>	144:ef7eb2e8f9f7	638
<>	144:ef7eb2e8f9f7	639	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	640	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	641	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	642
<>	144:ef7eb2e8f9f7	643	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	644	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	645	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	646	hi2c->XferISR = NULL;
<>	144:ef7eb2e8f9f7	647
<>	144:ef7eb2e8f9f7	648	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	649	/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
<>	144:ef7eb2e8f9f7	650	if(hi2c->XferCount > MAX_NBYTE_SIZE)
<>	144:ef7eb2e8f9f7	651	{
<>	144:ef7eb2e8f9f7	652	hi2c->XferSize = MAX_NBYTE_SIZE;
<>	144:ef7eb2e8f9f7	653	I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
<>	144:ef7eb2e8f9f7	654	}
<>	144:ef7eb2e8f9f7	655	else
<>	144:ef7eb2e8f9f7	656	{
<>	144:ef7eb2e8f9f7	657	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	658	I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
<>	144:ef7eb2e8f9f7	659	}
<>	144:ef7eb2e8f9f7	660
<>	144:ef7eb2e8f9f7	661	while(hi2c->XferCount > 0U)
<>	144:ef7eb2e8f9f7	662	{
<>	144:ef7eb2e8f9f7	663	/* Wait until TXIS flag is set */
<>	144:ef7eb2e8f9f7	664	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	665	{
<>	144:ef7eb2e8f9f7	666	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	667	{
<>	144:ef7eb2e8f9f7	668	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	669	}
<>	144:ef7eb2e8f9f7	670	else
<>	144:ef7eb2e8f9f7	671	{
<>	144:ef7eb2e8f9f7	672	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	673	}
<>	144:ef7eb2e8f9f7	674	}
<>	144:ef7eb2e8f9f7	675	/* Write data to TXDR */
<>	144:ef7eb2e8f9f7	676	hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	677	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	678	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	679
<>	144:ef7eb2e8f9f7	680	if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U))
<>	144:ef7eb2e8f9f7	681	{
<>	144:ef7eb2e8f9f7	682	/* Wait until TCR flag is set */
<>	144:ef7eb2e8f9f7	683	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	684	{
<>	144:ef7eb2e8f9f7	685	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	686	}
<>	144:ef7eb2e8f9f7	687
<>	144:ef7eb2e8f9f7	688	if(hi2c->XferCount > MAX_NBYTE_SIZE)
<>	144:ef7eb2e8f9f7	689	{
<>	144:ef7eb2e8f9f7	690	hi2c->XferSize = MAX_NBYTE_SIZE;
<>	144:ef7eb2e8f9f7	691	I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	692	}
<>	144:ef7eb2e8f9f7	693	else
<>	144:ef7eb2e8f9f7	694	{
<>	144:ef7eb2e8f9f7	695	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	696	I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	697	}
<>	144:ef7eb2e8f9f7	698	}
<>	144:ef7eb2e8f9f7	699	}
<>	144:ef7eb2e8f9f7	700
<>	144:ef7eb2e8f9f7	701	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<>	144:ef7eb2e8f9f7	702	/* Wait until STOPF flag is set */
<>	144:ef7eb2e8f9f7	703	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	704	{
<>	144:ef7eb2e8f9f7	705	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	706	{
<>	144:ef7eb2e8f9f7	707	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	708	}
<>	144:ef7eb2e8f9f7	709	else
<>	144:ef7eb2e8f9f7	710	{
<>	144:ef7eb2e8f9f7	711	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	712	}
<>	144:ef7eb2e8f9f7	713	}
<>	144:ef7eb2e8f9f7	714
<>	144:ef7eb2e8f9f7	715	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	716	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	717
<>	144:ef7eb2e8f9f7	718	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	719	I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	720
<>	144:ef7eb2e8f9f7	721	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	722	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	723
<>	144:ef7eb2e8f9f7	724	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	725	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	726
<>	144:ef7eb2e8f9f7	727	return HAL_OK;
<>	144:ef7eb2e8f9f7	728	}
<>	144:ef7eb2e8f9f7	729	else
<>	144:ef7eb2e8f9f7	730	{
<>	144:ef7eb2e8f9f7	731	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	732	}
<>	144:ef7eb2e8f9f7	733	}
<>	144:ef7eb2e8f9f7	734
<>	144:ef7eb2e8f9f7	735	/**
<>	144:ef7eb2e8f9f7	736	* @brief Receives in master mode an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	737	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	738	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	739	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	740	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	741	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	742	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	743	* @retval HAL status
<>	144:ef7eb2e8f9f7	744	*/
<>	144:ef7eb2e8f9f7	745	HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	746	{
<>	144:ef7eb2e8f9f7	747	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	748
<>	144:ef7eb2e8f9f7	749	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	750	{
<>	144:ef7eb2e8f9f7	751	/* Process Locked */
<>	144:ef7eb2e8f9f7	752	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	753
<>	144:ef7eb2e8f9f7	754	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	755	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	756
<>	144:ef7eb2e8f9f7	757	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	758	{
<>	144:ef7eb2e8f9f7	759	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	760	}
<>	144:ef7eb2e8f9f7	761
<>	144:ef7eb2e8f9f7	762	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	763	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	764	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	765
<>	144:ef7eb2e8f9f7	766	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	767	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	768	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	769	hi2c->XferISR = NULL;
<>	144:ef7eb2e8f9f7	770
<>	144:ef7eb2e8f9f7	771	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	772	/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
<>	144:ef7eb2e8f9f7	773	if(hi2c->XferCount > MAX_NBYTE_SIZE)
<>	144:ef7eb2e8f9f7	774	{
<>	144:ef7eb2e8f9f7	775	hi2c->XferSize = MAX_NBYTE_SIZE;
<>	144:ef7eb2e8f9f7	776	I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
<>	144:ef7eb2e8f9f7	777	}
<>	144:ef7eb2e8f9f7	778	else
<>	144:ef7eb2e8f9f7	779	{
<>	144:ef7eb2e8f9f7	780	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	781	I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
<>	144:ef7eb2e8f9f7	782	}
<>	144:ef7eb2e8f9f7	783
<>	144:ef7eb2e8f9f7	784	while(hi2c->XferCount > 0U)
<>	144:ef7eb2e8f9f7	785	{
<>	144:ef7eb2e8f9f7	786	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	787	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	788	{
<>	144:ef7eb2e8f9f7	789	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	790	{
<>	144:ef7eb2e8f9f7	791	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	792	}
<>	144:ef7eb2e8f9f7	793	else
<>	144:ef7eb2e8f9f7	794	{
<>	144:ef7eb2e8f9f7	795	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	796	}
<>	144:ef7eb2e8f9f7	797	}
<>	144:ef7eb2e8f9f7	798
<>	144:ef7eb2e8f9f7	799	/* Read data from RXDR */
<>	144:ef7eb2e8f9f7	800	(*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
<>	144:ef7eb2e8f9f7	801	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	802	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	803
<>	144:ef7eb2e8f9f7	804	if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
<>	144:ef7eb2e8f9f7	805	{
<>	144:ef7eb2e8f9f7	806	/* Wait until TCR flag is set */
<>	144:ef7eb2e8f9f7	807	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	808	{
<>	144:ef7eb2e8f9f7	809	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	810	}
<>	144:ef7eb2e8f9f7	811
<>	144:ef7eb2e8f9f7	812	if(hi2c->XferCount > MAX_NBYTE_SIZE)
<>	144:ef7eb2e8f9f7	813	{
<>	144:ef7eb2e8f9f7	814	hi2c->XferSize = MAX_NBYTE_SIZE;
<>	144:ef7eb2e8f9f7	815	I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	816	}
<>	144:ef7eb2e8f9f7	817	else
<>	144:ef7eb2e8f9f7	818	{
<>	144:ef7eb2e8f9f7	819	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	820	I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	821	}
<>	144:ef7eb2e8f9f7	822	}
<>	144:ef7eb2e8f9f7	823	}
<>	144:ef7eb2e8f9f7	824
<>	144:ef7eb2e8f9f7	825	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<>	144:ef7eb2e8f9f7	826	/* Wait until STOPF flag is set */
<>	144:ef7eb2e8f9f7	827	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	828	{
<>	144:ef7eb2e8f9f7	829	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	830	{
<>	144:ef7eb2e8f9f7	831	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	832	}
<>	144:ef7eb2e8f9f7	833	else
<>	144:ef7eb2e8f9f7	834	{
<>	144:ef7eb2e8f9f7	835	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	836	}
<>	144:ef7eb2e8f9f7	837	}
<>	144:ef7eb2e8f9f7	838
<>	144:ef7eb2e8f9f7	839	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	840	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	841
<>	144:ef7eb2e8f9f7	842	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	843	I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	844
<>	144:ef7eb2e8f9f7	845	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	846	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	847
<>	144:ef7eb2e8f9f7	848	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	849	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	850
<>	144:ef7eb2e8f9f7	851	return HAL_OK;
<>	144:ef7eb2e8f9f7	852	}
<>	144:ef7eb2e8f9f7	853	else
<>	144:ef7eb2e8f9f7	854	{
<>	144:ef7eb2e8f9f7	855	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	856	}
<>	144:ef7eb2e8f9f7	857	}
<>	144:ef7eb2e8f9f7	858
<>	144:ef7eb2e8f9f7	859	/**
<>	144:ef7eb2e8f9f7	860	* @brief Transmits in slave mode an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	861	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	862	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	863	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	864	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	865	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	866	* @retval HAL status
<>	144:ef7eb2e8f9f7	867	*/
<>	144:ef7eb2e8f9f7	868	HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	869	{
<>	144:ef7eb2e8f9f7	870	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	871
<>	144:ef7eb2e8f9f7	872	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	873	{
<>	144:ef7eb2e8f9f7	874	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	875	{
<>	144:ef7eb2e8f9f7	876	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	877	}
<>	144:ef7eb2e8f9f7	878	/* Process Locked */
<>	144:ef7eb2e8f9f7	879	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	880
<>	144:ef7eb2e8f9f7	881	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	882	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	883
<>	144:ef7eb2e8f9f7	884	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	885	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	886	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	887
<>	144:ef7eb2e8f9f7	888	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	889	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	890	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	891	hi2c->XferISR = NULL;
<>	144:ef7eb2e8f9f7	892
<>	144:ef7eb2e8f9f7	893	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	894	hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	895
<>	144:ef7eb2e8f9f7	896	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	897	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	898	{
<>	144:ef7eb2e8f9f7	899	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	900	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	901	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	902	}
<>	144:ef7eb2e8f9f7	903
<>	144:ef7eb2e8f9f7	904	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	905	__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
<>	144:ef7eb2e8f9f7	906
<>	144:ef7eb2e8f9f7	907	/* If 10bit addressing mode is selected */
<>	144:ef7eb2e8f9f7	908	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
<>	144:ef7eb2e8f9f7	909	{
<>	144:ef7eb2e8f9f7	910	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	911	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	912	{
<>	144:ef7eb2e8f9f7	913	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	914	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	915	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	916	}
<>	144:ef7eb2e8f9f7	917
<>	144:ef7eb2e8f9f7	918	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	919	__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
<>	144:ef7eb2e8f9f7	920	}
<>	144:ef7eb2e8f9f7	921
<>	144:ef7eb2e8f9f7	922	/* Wait until DIR flag is set Transmitter mode */
<>	144:ef7eb2e8f9f7	923	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	924	{
<>	144:ef7eb2e8f9f7	925	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	926	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	927	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	928	}
<>	144:ef7eb2e8f9f7	929
<>	144:ef7eb2e8f9f7	930	while(hi2c->XferCount > 0U)
<>	144:ef7eb2e8f9f7	931	{
<>	144:ef7eb2e8f9f7	932	/* Wait until TXIS flag is set */
<>	144:ef7eb2e8f9f7	933	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	934	{
<>	144:ef7eb2e8f9f7	935	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	936	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	937
<>	144:ef7eb2e8f9f7	938	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	939	{
<>	144:ef7eb2e8f9f7	940	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	941	}
<>	144:ef7eb2e8f9f7	942	else
<>	144:ef7eb2e8f9f7	943	{
<>	144:ef7eb2e8f9f7	944	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	945	}
<>	144:ef7eb2e8f9f7	946	}
<>	144:ef7eb2e8f9f7	947
<>	144:ef7eb2e8f9f7	948	/* Write data to TXDR */
<>	144:ef7eb2e8f9f7	949	hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	950	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	951	}
<>	144:ef7eb2e8f9f7	952
<>	144:ef7eb2e8f9f7	953	/* Wait until STOP flag is set */
<>	144:ef7eb2e8f9f7	954	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	955	{
<>	144:ef7eb2e8f9f7	956	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	957	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	958
<>	144:ef7eb2e8f9f7	959	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	960	{
<>	144:ef7eb2e8f9f7	961	/* Normal use case for Transmitter mode */
<>	144:ef7eb2e8f9f7	962	/* A NACK is generated to confirm the end of transfer */
<>	144:ef7eb2e8f9f7	963	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	964	}
<>	144:ef7eb2e8f9f7	965	else
<>	144:ef7eb2e8f9f7	966	{
<>	144:ef7eb2e8f9f7	967	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	968	}
<>	144:ef7eb2e8f9f7	969	}
<>	144:ef7eb2e8f9f7	970
<>	144:ef7eb2e8f9f7	971	/* Clear STOP flag */
<>	144:ef7eb2e8f9f7	972	__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	973
<>	144:ef7eb2e8f9f7	974	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	975	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	976	{
<>	144:ef7eb2e8f9f7	977	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	978	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	979	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	980	}
<>	144:ef7eb2e8f9f7	981
<>	144:ef7eb2e8f9f7	982	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	983	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	984
<>	144:ef7eb2e8f9f7	985	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	986	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	987
<>	144:ef7eb2e8f9f7	988	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	989	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	990
<>	144:ef7eb2e8f9f7	991	return HAL_OK;
<>	144:ef7eb2e8f9f7	992	}
<>	144:ef7eb2e8f9f7	993	else
<>	144:ef7eb2e8f9f7	994	{
<>	144:ef7eb2e8f9f7	995	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	996	}
<>	144:ef7eb2e8f9f7	997	}
<>	144:ef7eb2e8f9f7	998
<>	144:ef7eb2e8f9f7	999	/**
<>	144:ef7eb2e8f9f7	1000	* @brief Receive in slave mode an amount of data in blocking mode
<>	144:ef7eb2e8f9f7	1001	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1002	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1003	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1004	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1005	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	1006	* @retval HAL status
<>	144:ef7eb2e8f9f7	1007	*/
<>	144:ef7eb2e8f9f7	1008	HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	1009	{
<>	144:ef7eb2e8f9f7	1010	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	1011
<>	144:ef7eb2e8f9f7	1012	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1013	{
<>	144:ef7eb2e8f9f7	1014	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1015	{
<>	144:ef7eb2e8f9f7	1016	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1017	}
<>	144:ef7eb2e8f9f7	1018	/* Process Locked */
<>	144:ef7eb2e8f9f7	1019	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1020
<>	144:ef7eb2e8f9f7	1021	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	1022	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1023
<>	144:ef7eb2e8f9f7	1024	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	1025	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	1026	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1027
<>	144:ef7eb2e8f9f7	1028	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	1029	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1030	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1031	hi2c->XferISR = NULL;
<>	144:ef7eb2e8f9f7	1032
<>	144:ef7eb2e8f9f7	1033	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1034	hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	1035
<>	144:ef7eb2e8f9f7	1036	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	1037	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1038	{
<>	144:ef7eb2e8f9f7	1039	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1040	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	1041	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1042	}
<>	144:ef7eb2e8f9f7	1043
<>	144:ef7eb2e8f9f7	1044	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	1045	__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
<>	144:ef7eb2e8f9f7	1046
<>	144:ef7eb2e8f9f7	1047	/* Wait until DIR flag is reset Receiver mode */
<>	144:ef7eb2e8f9f7	1048	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1049	{
<>	144:ef7eb2e8f9f7	1050	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1051	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	1052	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1053	}
<>	144:ef7eb2e8f9f7	1054
<>	144:ef7eb2e8f9f7	1055	while(hi2c->XferCount > 0U)
<>	144:ef7eb2e8f9f7	1056	{
<>	144:ef7eb2e8f9f7	1057	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	1058	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1059	{
<>	144:ef7eb2e8f9f7	1060	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1061	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	1062
<>	144:ef7eb2e8f9f7	1063	/* Store Last receive data if any */
<>	144:ef7eb2e8f9f7	1064	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
<>	144:ef7eb2e8f9f7	1065	{
<>	144:ef7eb2e8f9f7	1066	/* Read data from RXDR */
<>	144:ef7eb2e8f9f7	1067	(*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
<>	144:ef7eb2e8f9f7	1068	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	1069	}
<>	144:ef7eb2e8f9f7	1070
<>	144:ef7eb2e8f9f7	1071	if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
<>	144:ef7eb2e8f9f7	1072	{
<>	144:ef7eb2e8f9f7	1073	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1074	}
<>	144:ef7eb2e8f9f7	1075	else
<>	144:ef7eb2e8f9f7	1076	{
<>	144:ef7eb2e8f9f7	1077	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1078	}
<>	144:ef7eb2e8f9f7	1079	}
<>	144:ef7eb2e8f9f7	1080
<>	144:ef7eb2e8f9f7	1081	/* Read data from RXDR */
<>	144:ef7eb2e8f9f7	1082	(*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
<>	144:ef7eb2e8f9f7	1083	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	1084	}
<>	144:ef7eb2e8f9f7	1085
<>	144:ef7eb2e8f9f7	1086	/* Wait until STOP flag is set */
<>	144:ef7eb2e8f9f7	1087	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1088	{
<>	144:ef7eb2e8f9f7	1089	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1090	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	1091
<>	144:ef7eb2e8f9f7	1092	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	1093	{
<>	144:ef7eb2e8f9f7	1094	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1095	}
<>	144:ef7eb2e8f9f7	1096	else
<>	144:ef7eb2e8f9f7	1097	{
<>	144:ef7eb2e8f9f7	1098	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1099	}
<>	144:ef7eb2e8f9f7	1100	}
<>	144:ef7eb2e8f9f7	1101
<>	144:ef7eb2e8f9f7	1102	/* Clear STOP flag */
<>	144:ef7eb2e8f9f7	1103	__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	1104
<>	144:ef7eb2e8f9f7	1105	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	1106	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1107	{
<>	144:ef7eb2e8f9f7	1108	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1109	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	1110	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1111	}
<>	144:ef7eb2e8f9f7	1112
<>	144:ef7eb2e8f9f7	1113	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1114	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	1115
<>	144:ef7eb2e8f9f7	1116	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1117	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	1118
<>	144:ef7eb2e8f9f7	1119	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1120	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1121
<>	144:ef7eb2e8f9f7	1122	return HAL_OK;
<>	144:ef7eb2e8f9f7	1123	}
<>	144:ef7eb2e8f9f7	1124	else
<>	144:ef7eb2e8f9f7	1125	{
<>	144:ef7eb2e8f9f7	1126	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1127	}
<>	144:ef7eb2e8f9f7	1128	}
<>	144:ef7eb2e8f9f7	1129
<>	144:ef7eb2e8f9f7	1130	/**
<>	144:ef7eb2e8f9f7	1131	* @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1132	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1133	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1134	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	1135	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1136	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1137	* @retval HAL status
<>	144:ef7eb2e8f9f7	1138	*/
<>	144:ef7eb2e8f9f7	1139	HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1140	{
<>	144:ef7eb2e8f9f7	1141	uint32_t xfermode = 0U;
<>	144:ef7eb2e8f9f7	1142
<>	144:ef7eb2e8f9f7	1143	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1144	{
<>	144:ef7eb2e8f9f7	1145	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<>	144:ef7eb2e8f9f7	1146	{
<>	144:ef7eb2e8f9f7	1147	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1148	}
<>	144:ef7eb2e8f9f7	1149
<>	144:ef7eb2e8f9f7	1150	/* Process Locked */
<>	144:ef7eb2e8f9f7	1151	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1152
<>	144:ef7eb2e8f9f7	1153	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	1154	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	1155	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1156
<>	144:ef7eb2e8f9f7	1157	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	1158	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1159	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1160	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	1161	hi2c->XferISR = I2C_Master_ISR_IT;
<>	144:ef7eb2e8f9f7	1162
<>	144:ef7eb2e8f9f7	1163	if(hi2c->XferCount > MAX_NBYTE_SIZE)
<>	144:ef7eb2e8f9f7	1164	{
<>	144:ef7eb2e8f9f7	1165	hi2c->XferSize = MAX_NBYTE_SIZE;
<>	144:ef7eb2e8f9f7	1166	xfermode = I2C_RELOAD_MODE;
<>	144:ef7eb2e8f9f7	1167	}
<>	144:ef7eb2e8f9f7	1168	else
<>	144:ef7eb2e8f9f7	1169	{
<>	144:ef7eb2e8f9f7	1170	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1171	xfermode = I2C_AUTOEND_MODE;
<>	144:ef7eb2e8f9f7	1172	}
<>	144:ef7eb2e8f9f7	1173
<>	144:ef7eb2e8f9f7	1174	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	1175	/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
<>	144:ef7eb2e8f9f7	1176	I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
<>	144:ef7eb2e8f9f7	1177
<>	144:ef7eb2e8f9f7	1178	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1179	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1180
<>	144:ef7eb2e8f9f7	1181	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1182	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1183	process unlock */
<>	144:ef7eb2e8f9f7	1184
<>	144:ef7eb2e8f9f7	1185	/* Enable ERR, TC, STOP, NACK, TXI interrupt */
<>	144:ef7eb2e8f9f7	1186	/* possible to enable all of these */
<>	144:ef7eb2e8f9f7	1187	/* I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_RXI \| I2C_IT_TXI */
<>	144:ef7eb2e8f9f7	1188	I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
<>	144:ef7eb2e8f9f7	1189
<>	144:ef7eb2e8f9f7	1190	return HAL_OK;
<>	144:ef7eb2e8f9f7	1191	}
<>	144:ef7eb2e8f9f7	1192	else
<>	144:ef7eb2e8f9f7	1193	{
<>	144:ef7eb2e8f9f7	1194	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1195	}
<>	144:ef7eb2e8f9f7	1196	}
<>	144:ef7eb2e8f9f7	1197
<>	144:ef7eb2e8f9f7	1198	/**
<>	144:ef7eb2e8f9f7	1199	* @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1200	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1201	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1202	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	1203	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1204	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1205	* @retval HAL status
<>	144:ef7eb2e8f9f7	1206	*/
<>	144:ef7eb2e8f9f7	1207	HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1208	{
<>	144:ef7eb2e8f9f7	1209	uint32_t xfermode = 0U;
<>	144:ef7eb2e8f9f7	1210
<>	144:ef7eb2e8f9f7	1211	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1212	{
<>	144:ef7eb2e8f9f7	1213	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<>	144:ef7eb2e8f9f7	1214	{
<>	144:ef7eb2e8f9f7	1215	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1216	}
<>	144:ef7eb2e8f9f7	1217
<>	144:ef7eb2e8f9f7	1218	/* Process Locked */
<>	144:ef7eb2e8f9f7	1219	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1220
<>	144:ef7eb2e8f9f7	1221	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	1222	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	1223	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1224
<>	144:ef7eb2e8f9f7	1225	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	1226	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1227	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1228	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	1229	hi2c->XferISR = I2C_Master_ISR_IT;
<>	144:ef7eb2e8f9f7	1230
<>	144:ef7eb2e8f9f7	1231	if(hi2c->XferCount > MAX_NBYTE_SIZE)
<>	144:ef7eb2e8f9f7	1232	{
<>	144:ef7eb2e8f9f7	1233	hi2c->XferSize = MAX_NBYTE_SIZE;
<>	144:ef7eb2e8f9f7	1234	xfermode = I2C_RELOAD_MODE;
<>	144:ef7eb2e8f9f7	1235	}
<>	144:ef7eb2e8f9f7	1236	else
<>	144:ef7eb2e8f9f7	1237	{
<>	144:ef7eb2e8f9f7	1238	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1239	xfermode = I2C_AUTOEND_MODE;
<>	144:ef7eb2e8f9f7	1240	}
<>	144:ef7eb2e8f9f7	1241
<>	144:ef7eb2e8f9f7	1242	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	1243	/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
<>	144:ef7eb2e8f9f7	1244	I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
<>	144:ef7eb2e8f9f7	1245
<>	144:ef7eb2e8f9f7	1246	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1247	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1248
<>	144:ef7eb2e8f9f7	1249	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1250	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1251	process unlock */
<>	144:ef7eb2e8f9f7	1252
<>	144:ef7eb2e8f9f7	1253	/* Enable ERR, TC, STOP, NACK, RXI interrupt */
<>	144:ef7eb2e8f9f7	1254	/* possible to enable all of these */
<>	144:ef7eb2e8f9f7	1255	/* I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_RXI \| I2C_IT_TXI */
<>	144:ef7eb2e8f9f7	1256	I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
<>	144:ef7eb2e8f9f7	1257
<>	144:ef7eb2e8f9f7	1258	return HAL_OK;
<>	144:ef7eb2e8f9f7	1259	}
<>	144:ef7eb2e8f9f7	1260	else
<>	144:ef7eb2e8f9f7	1261	{
<>	144:ef7eb2e8f9f7	1262	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1263	}
<>	144:ef7eb2e8f9f7	1264	}
<>	144:ef7eb2e8f9f7	1265
<>	144:ef7eb2e8f9f7	1266	/**
<>	144:ef7eb2e8f9f7	1267	* @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1268	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1269	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1270	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1271	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1272	* @retval HAL status
<>	144:ef7eb2e8f9f7	1273	*/
<>	144:ef7eb2e8f9f7	1274	HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1275	{
<>	144:ef7eb2e8f9f7	1276	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1277	{
<>	144:ef7eb2e8f9f7	1278	/* Process Locked */
<>	144:ef7eb2e8f9f7	1279	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1280
<>	144:ef7eb2e8f9f7	1281	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	1282	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	1283	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1284
<>	144:ef7eb2e8f9f7	1285	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1286	hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	1287
<>	144:ef7eb2e8f9f7	1288	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	1289	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1290	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1291	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1292	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	1293	hi2c->XferISR = I2C_Slave_ISR_IT;
<>	144:ef7eb2e8f9f7	1294
<>	144:ef7eb2e8f9f7	1295	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1296	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1297
<>	144:ef7eb2e8f9f7	1298	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1299	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1300	process unlock */
<>	144:ef7eb2e8f9f7	1301
<>	144:ef7eb2e8f9f7	1302	/* Enable ERR, TC, STOP, NACK, TXI interrupt */
<>	144:ef7eb2e8f9f7	1303	/* possible to enable all of these */
<>	144:ef7eb2e8f9f7	1304	/* I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_RXI \| I2C_IT_TXI */
<>	144:ef7eb2e8f9f7	1305	I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT \| I2C_XFER_LISTEN_IT);
<>	144:ef7eb2e8f9f7	1306
<>	144:ef7eb2e8f9f7	1307	return HAL_OK;
<>	144:ef7eb2e8f9f7	1308	}
<>	144:ef7eb2e8f9f7	1309	else
<>	144:ef7eb2e8f9f7	1310	{
<>	144:ef7eb2e8f9f7	1311	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1312	}
<>	144:ef7eb2e8f9f7	1313	}
<>	144:ef7eb2e8f9f7	1314
<>	144:ef7eb2e8f9f7	1315	/**
<>	144:ef7eb2e8f9f7	1316	* @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1317	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1318	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1319	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1320	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1321	* @retval HAL status
<>	144:ef7eb2e8f9f7	1322	*/
<>	144:ef7eb2e8f9f7	1323	HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1324	{
<>	144:ef7eb2e8f9f7	1325	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1326	{
<>	144:ef7eb2e8f9f7	1327	/* Process Locked */
<>	144:ef7eb2e8f9f7	1328	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1329
<>	144:ef7eb2e8f9f7	1330	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	1331	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	1332	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1333
<>	144:ef7eb2e8f9f7	1334	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1335	hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	1336
<>	144:ef7eb2e8f9f7	1337	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	1338	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1339	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1340	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1341	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	1342	hi2c->XferISR = I2C_Slave_ISR_IT;
<>	144:ef7eb2e8f9f7	1343
<>	144:ef7eb2e8f9f7	1344	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1345	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1346
<>	144:ef7eb2e8f9f7	1347	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1348	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1349	process unlock */
<>	144:ef7eb2e8f9f7	1350
<>	144:ef7eb2e8f9f7	1351	/* Enable ERR, TC, STOP, NACK, RXI interrupt */
<>	144:ef7eb2e8f9f7	1352	/* possible to enable all of these */
<>	144:ef7eb2e8f9f7	1353	/* I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_RXI \| I2C_IT_TXI */
<>	144:ef7eb2e8f9f7	1354	I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT \| I2C_XFER_LISTEN_IT);
<>	144:ef7eb2e8f9f7	1355
<>	144:ef7eb2e8f9f7	1356	return HAL_OK;
<>	144:ef7eb2e8f9f7	1357	}
<>	144:ef7eb2e8f9f7	1358	else
<>	144:ef7eb2e8f9f7	1359	{
<>	144:ef7eb2e8f9f7	1360	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1361	}
<>	144:ef7eb2e8f9f7	1362	}
<>	144:ef7eb2e8f9f7	1363
<>	144:ef7eb2e8f9f7	1364	/**
<>	144:ef7eb2e8f9f7	1365	* @brief Transmit in master mode an amount of data in non-blocking mode with DMA
<>	144:ef7eb2e8f9f7	1366	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1367	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1368	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	1369	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1370	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1371	* @retval HAL status
<>	144:ef7eb2e8f9f7	1372	*/
<>	144:ef7eb2e8f9f7	1373	HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1374	{
<>	144:ef7eb2e8f9f7	1375	uint32_t xfermode = 0U;
<>	144:ef7eb2e8f9f7	1376
<>	144:ef7eb2e8f9f7	1377	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1378	{
<>	144:ef7eb2e8f9f7	1379	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<>	144:ef7eb2e8f9f7	1380	{
<>	144:ef7eb2e8f9f7	1381	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1382	}
<>	144:ef7eb2e8f9f7	1383
<>	144:ef7eb2e8f9f7	1384	/* Process Locked */
<>	144:ef7eb2e8f9f7	1385	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1386
<>	144:ef7eb2e8f9f7	1387	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	1388	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	1389	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1390
<>	144:ef7eb2e8f9f7	1391	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	1392	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1393	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1394	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	1395	hi2c->XferISR = I2C_Master_ISR_DMA;
<>	144:ef7eb2e8f9f7	1396
<>	144:ef7eb2e8f9f7	1397	if(hi2c->XferCount > MAX_NBYTE_SIZE)
<>	144:ef7eb2e8f9f7	1398	{
<>	144:ef7eb2e8f9f7	1399	hi2c->XferSize = MAX_NBYTE_SIZE;
<>	144:ef7eb2e8f9f7	1400	xfermode = I2C_RELOAD_MODE;
<>	144:ef7eb2e8f9f7	1401	}
<>	144:ef7eb2e8f9f7	1402	else
<>	144:ef7eb2e8f9f7	1403	{
<>	144:ef7eb2e8f9f7	1404	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1405	xfermode = I2C_AUTOEND_MODE;
<>	144:ef7eb2e8f9f7	1406	}
<>	144:ef7eb2e8f9f7	1407
<>	144:ef7eb2e8f9f7	1408	if(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	1409	{
<>	144:ef7eb2e8f9f7	1410	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1411	hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
<>	144:ef7eb2e8f9f7	1412
<>	144:ef7eb2e8f9f7	1413	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1414	hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	1415
<>	144:ef7eb2e8f9f7	1416	/* Set the unused DMA callbacks to NULL */
<>	144:ef7eb2e8f9f7	1417	hi2c->hdmatx->XferHalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	1418	hi2c->hdmatx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	1419
<>	144:ef7eb2e8f9f7	1420	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1421	HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
<>	144:ef7eb2e8f9f7	1422
<>	144:ef7eb2e8f9f7	1423	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	1424	/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
<>	144:ef7eb2e8f9f7	1425	I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
<>	144:ef7eb2e8f9f7	1426
<>	144:ef7eb2e8f9f7	1427	/* Update XferCount value */
<>	144:ef7eb2e8f9f7	1428	hi2c->XferCount -= hi2c->XferSize;
<>	144:ef7eb2e8f9f7	1429
<>	144:ef7eb2e8f9f7	1430	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1431	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1432
<>	144:ef7eb2e8f9f7	1433	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1434	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1435	process unlock */
<>	144:ef7eb2e8f9f7	1436	/* Enable ERR and NACK interrupts */
<>	144:ef7eb2e8f9f7	1437	I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
<>	144:ef7eb2e8f9f7	1438
<>	144:ef7eb2e8f9f7	1439	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	1440	hi2c->Instance->CR1 \|= I2C_CR1_TXDMAEN;
<>	144:ef7eb2e8f9f7	1441	}
<>	144:ef7eb2e8f9f7	1442	else
<>	144:ef7eb2e8f9f7	1443	{
<>	144:ef7eb2e8f9f7	1444	/* Update Transfer ISR function pointer */
<>	144:ef7eb2e8f9f7	1445	hi2c->XferISR = I2C_Master_ISR_IT;
<>	144:ef7eb2e8f9f7	1446
<>	144:ef7eb2e8f9f7	1447	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	1448	/* Set NBYTES to write and generate START condition */
<>	144:ef7eb2e8f9f7	1449	I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
<>	144:ef7eb2e8f9f7	1450
<>	144:ef7eb2e8f9f7	1451	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1452	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1453
<>	144:ef7eb2e8f9f7	1454	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1455	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1456	process unlock */
<>	144:ef7eb2e8f9f7	1457	/* Enable ERR, TC, STOP, NACK, TXI interrupt */
<>	144:ef7eb2e8f9f7	1458	/* possible to enable all of these */
<>	144:ef7eb2e8f9f7	1459	/* I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_RXI \| I2C_IT_TXI */
<>	144:ef7eb2e8f9f7	1460	I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
<>	144:ef7eb2e8f9f7	1461	}
<>	144:ef7eb2e8f9f7	1462
<>	144:ef7eb2e8f9f7	1463	return HAL_OK;
<>	144:ef7eb2e8f9f7	1464	}
<>	144:ef7eb2e8f9f7	1465	else
<>	144:ef7eb2e8f9f7	1466	{
<>	144:ef7eb2e8f9f7	1467	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1468	}
<>	144:ef7eb2e8f9f7	1469	}
<>	144:ef7eb2e8f9f7	1470
<>	144:ef7eb2e8f9f7	1471	/**
<>	144:ef7eb2e8f9f7	1472	* @brief Receive in master mode an amount of data in non-blocking mode with DMA
<>	144:ef7eb2e8f9f7	1473	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1474	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1475	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	1476	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1477	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1478	* @retval HAL status
<>	144:ef7eb2e8f9f7	1479	*/
<>	144:ef7eb2e8f9f7	1480	HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1481	{
<>	144:ef7eb2e8f9f7	1482	uint32_t xfermode = 0U;
<>	144:ef7eb2e8f9f7	1483
<>	144:ef7eb2e8f9f7	1484	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1485	{
<>	144:ef7eb2e8f9f7	1486	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<>	144:ef7eb2e8f9f7	1487	{
<>	144:ef7eb2e8f9f7	1488	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1489	}
<>	144:ef7eb2e8f9f7	1490
<>	144:ef7eb2e8f9f7	1491	/* Process Locked */
<>	144:ef7eb2e8f9f7	1492	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1493
<>	144:ef7eb2e8f9f7	1494	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	1495	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	1496	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1497
<>	144:ef7eb2e8f9f7	1498	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	1499	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1500	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1501	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	1502	hi2c->XferISR = I2C_Master_ISR_DMA;
<>	144:ef7eb2e8f9f7	1503
<>	144:ef7eb2e8f9f7	1504	if(hi2c->XferCount > MAX_NBYTE_SIZE)
<>	144:ef7eb2e8f9f7	1505	{
<>	144:ef7eb2e8f9f7	1506	hi2c->XferSize = MAX_NBYTE_SIZE;
<>	144:ef7eb2e8f9f7	1507	xfermode = I2C_RELOAD_MODE;
<>	144:ef7eb2e8f9f7	1508	}
<>	144:ef7eb2e8f9f7	1509	else
<>	144:ef7eb2e8f9f7	1510	{
<>	144:ef7eb2e8f9f7	1511	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1512	xfermode = I2C_AUTOEND_MODE;
<>	144:ef7eb2e8f9f7	1513	}
<>	144:ef7eb2e8f9f7	1514
<>	144:ef7eb2e8f9f7	1515	if(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	1516	{
<>	144:ef7eb2e8f9f7	1517	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1518	hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
<>	144:ef7eb2e8f9f7	1519
<>	144:ef7eb2e8f9f7	1520	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1521	hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	1522
<>	144:ef7eb2e8f9f7	1523	/* Set the unused DMA callbacks to NULL */
<>	144:ef7eb2e8f9f7	1524	hi2c->hdmarx->XferHalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	1525	hi2c->hdmarx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	1526
<>	144:ef7eb2e8f9f7	1527	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1528	HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
<>	144:ef7eb2e8f9f7	1529
<>	144:ef7eb2e8f9f7	1530	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	1531	/* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
<>	144:ef7eb2e8f9f7	1532	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
<>	144:ef7eb2e8f9f7	1533
<>	144:ef7eb2e8f9f7	1534	/* Update XferCount value */
<>	144:ef7eb2e8f9f7	1535	hi2c->XferCount -= hi2c->XferSize;
<>	144:ef7eb2e8f9f7	1536
<>	144:ef7eb2e8f9f7	1537	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1538	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1539
<>	144:ef7eb2e8f9f7	1540	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1541	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1542	process unlock */
<>	144:ef7eb2e8f9f7	1543	/* Enable ERR and NACK interrupts */
<>	144:ef7eb2e8f9f7	1544	I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
<>	144:ef7eb2e8f9f7	1545
<>	144:ef7eb2e8f9f7	1546	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	1547	hi2c->Instance->CR1 \|= I2C_CR1_RXDMAEN;
<>	144:ef7eb2e8f9f7	1548	}
<>	144:ef7eb2e8f9f7	1549	else
<>	144:ef7eb2e8f9f7	1550	{
<>	144:ef7eb2e8f9f7	1551	/* Update Transfer ISR function pointer */
<>	144:ef7eb2e8f9f7	1552	hi2c->XferISR = I2C_Master_ISR_IT;
<>	144:ef7eb2e8f9f7	1553
<>	144:ef7eb2e8f9f7	1554	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	1555	/* Set NBYTES to read and generate START condition */
<>	144:ef7eb2e8f9f7	1556	I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
<>	144:ef7eb2e8f9f7	1557
<>	144:ef7eb2e8f9f7	1558	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1559	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1560
<>	144:ef7eb2e8f9f7	1561	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1562	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1563	process unlock */
<>	144:ef7eb2e8f9f7	1564	/* Enable ERR, TC, STOP, NACK, TXI interrupt */
<>	144:ef7eb2e8f9f7	1565	/* possible to enable all of these */
<>	144:ef7eb2e8f9f7	1566	/* I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_RXI \| I2C_IT_TXI */
<>	144:ef7eb2e8f9f7	1567	I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
<>	144:ef7eb2e8f9f7	1568	}
<>	144:ef7eb2e8f9f7	1569	return HAL_OK;
<>	144:ef7eb2e8f9f7	1570	}
<>	144:ef7eb2e8f9f7	1571	else
<>	144:ef7eb2e8f9f7	1572	{
<>	144:ef7eb2e8f9f7	1573	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1574	}
<>	144:ef7eb2e8f9f7	1575	}
<>	144:ef7eb2e8f9f7	1576
<>	144:ef7eb2e8f9f7	1577	/**
<>	144:ef7eb2e8f9f7	1578	* @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
<>	144:ef7eb2e8f9f7	1579	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1580	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1581	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1582	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1583	* @retval HAL status
<>	144:ef7eb2e8f9f7	1584	*/
<>	144:ef7eb2e8f9f7	1585	HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1586	{
<>	144:ef7eb2e8f9f7	1587	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1588	{
<>	144:ef7eb2e8f9f7	1589	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1590	{
<>	144:ef7eb2e8f9f7	1591	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1592	}
<>	144:ef7eb2e8f9f7	1593	/* Process Locked */
<>	144:ef7eb2e8f9f7	1594	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1595
<>	144:ef7eb2e8f9f7	1596	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	1597	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	1598	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1599
<>	144:ef7eb2e8f9f7	1600	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	1601	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1602	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1603	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1604	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	1605	hi2c->XferISR = I2C_Slave_ISR_DMA;
<>	144:ef7eb2e8f9f7	1606
<>	144:ef7eb2e8f9f7	1607	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1608	hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
<>	144:ef7eb2e8f9f7	1609
<>	144:ef7eb2e8f9f7	1610	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1611	hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	1612
<>	144:ef7eb2e8f9f7	1613	/* Set the unused DMA callbacks to NULL */
<>	144:ef7eb2e8f9f7	1614	hi2c->hdmatx->XferHalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	1615	hi2c->hdmatx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	1616
<>	144:ef7eb2e8f9f7	1617	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1618	HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
<>	144:ef7eb2e8f9f7	1619
<>	144:ef7eb2e8f9f7	1620	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1621	hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	1622
<>	144:ef7eb2e8f9f7	1623	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1624	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1625
<>	144:ef7eb2e8f9f7	1626	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1627	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1628	process unlock */
<>	144:ef7eb2e8f9f7	1629	/* Enable ERR, STOP, NACK, ADDR interrupts */
<>	144:ef7eb2e8f9f7	1630	I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
<>	144:ef7eb2e8f9f7	1631
<>	144:ef7eb2e8f9f7	1632	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	1633	hi2c->Instance->CR1 \|= I2C_CR1_TXDMAEN;
<>	144:ef7eb2e8f9f7	1634
<>	144:ef7eb2e8f9f7	1635	return HAL_OK;
<>	144:ef7eb2e8f9f7	1636	}
<>	144:ef7eb2e8f9f7	1637	else
<>	144:ef7eb2e8f9f7	1638	{
<>	144:ef7eb2e8f9f7	1639	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1640	}
<>	144:ef7eb2e8f9f7	1641	}
<>	144:ef7eb2e8f9f7	1642
<>	144:ef7eb2e8f9f7	1643	/**
<>	144:ef7eb2e8f9f7	1644	* @brief Receive in slave mode an amount of data in non-blocking mode with DMA
<>	144:ef7eb2e8f9f7	1645	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1646	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1647	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1648	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1649	* @retval HAL status
<>	144:ef7eb2e8f9f7	1650	*/
<>	144:ef7eb2e8f9f7	1651	HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1652	{
<>	144:ef7eb2e8f9f7	1653	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1654	{
<>	144:ef7eb2e8f9f7	1655	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1656	{
<>	144:ef7eb2e8f9f7	1657	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1658	}
<>	144:ef7eb2e8f9f7	1659	/* Process Locked */
<>	144:ef7eb2e8f9f7	1660	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1661
<>	144:ef7eb2e8f9f7	1662	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	1663	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	1664	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1665
<>	144:ef7eb2e8f9f7	1666	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	1667	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1668	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1669	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1670	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	1671	hi2c->XferISR = I2C_Slave_ISR_DMA;
<>	144:ef7eb2e8f9f7	1672
<>	144:ef7eb2e8f9f7	1673	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1674	hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
<>	144:ef7eb2e8f9f7	1675
<>	144:ef7eb2e8f9f7	1676	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1677	hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	1678
<>	144:ef7eb2e8f9f7	1679	/* Set the unused DMA callbacks to NULL */
<>	144:ef7eb2e8f9f7	1680	hi2c->hdmarx->XferHalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	1681	hi2c->hdmarx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	1682
<>	144:ef7eb2e8f9f7	1683	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1684	HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
<>	144:ef7eb2e8f9f7	1685
<>	144:ef7eb2e8f9f7	1686	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1687	hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	1688
<>	144:ef7eb2e8f9f7	1689	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1690	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1691
<>	144:ef7eb2e8f9f7	1692	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1693	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1694	process unlock */
<>	144:ef7eb2e8f9f7	1695	/* Enable ERR, STOP, NACK, ADDR interrupts */
<>	144:ef7eb2e8f9f7	1696	I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
<>	144:ef7eb2e8f9f7	1697
<>	144:ef7eb2e8f9f7	1698	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	1699	hi2c->Instance->CR1 \|= I2C_CR1_RXDMAEN;
<>	144:ef7eb2e8f9f7	1700
<>	144:ef7eb2e8f9f7	1701	return HAL_OK;
<>	144:ef7eb2e8f9f7	1702	}
<>	144:ef7eb2e8f9f7	1703	else
<>	144:ef7eb2e8f9f7	1704	{
<>	144:ef7eb2e8f9f7	1705	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1706	}
<>	144:ef7eb2e8f9f7	1707	}
<>	144:ef7eb2e8f9f7	1708	/**
<>	144:ef7eb2e8f9f7	1709	* @brief Write an amount of data in blocking mode to a specific memory address
<>	144:ef7eb2e8f9f7	1710	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1711	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1712	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	1713	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	1714	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	1715	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1716	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1717	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	1718	* @retval HAL status
<>	144:ef7eb2e8f9f7	1719	*/
<>	144:ef7eb2e8f9f7	1720	HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	1721	{
<>	144:ef7eb2e8f9f7	1722	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	1723
<>	144:ef7eb2e8f9f7	1724	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1725	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	1726
<>	144:ef7eb2e8f9f7	1727	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1728	{
<>	144:ef7eb2e8f9f7	1729	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1730	{
<>	144:ef7eb2e8f9f7	1731	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1732	}
<>	144:ef7eb2e8f9f7	1733
<>	144:ef7eb2e8f9f7	1734	/* Process Locked */
<>	144:ef7eb2e8f9f7	1735	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1736
<>	144:ef7eb2e8f9f7	1737	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	1738	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1739
<>	144:ef7eb2e8f9f7	1740	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1741	{
<>	144:ef7eb2e8f9f7	1742	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1743	}
<>	144:ef7eb2e8f9f7	1744
<>	144:ef7eb2e8f9f7	1745	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	1746	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	1747	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1748
<>	144:ef7eb2e8f9f7	1749	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	1750	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1751	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1752	hi2c->XferISR = NULL;
<>	144:ef7eb2e8f9f7	1753
<>	144:ef7eb2e8f9f7	1754	/* Send Slave Address and Memory Address */
<>	144:ef7eb2e8f9f7	1755	if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1756	{
<>	144:ef7eb2e8f9f7	1757	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	1758	{
<>	144:ef7eb2e8f9f7	1759	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1760	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1761	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1762	}
<>	144:ef7eb2e8f9f7	1763	else
<>	144:ef7eb2e8f9f7	1764	{
<>	144:ef7eb2e8f9f7	1765	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1766	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1767	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1768	}
<>	144:ef7eb2e8f9f7	1769	}
<>	144:ef7eb2e8f9f7	1770
<>	144:ef7eb2e8f9f7	1771	/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
<>	144:ef7eb2e8f9f7	1772	if(hi2c->XferCount > MAX_NBYTE_SIZE)
<>	144:ef7eb2e8f9f7	1773	{
<>	144:ef7eb2e8f9f7	1774	hi2c->XferSize = MAX_NBYTE_SIZE;
<>	144:ef7eb2e8f9f7	1775	I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	1776	}
<>	144:ef7eb2e8f9f7	1777	else
<>	144:ef7eb2e8f9f7	1778	{
<>	144:ef7eb2e8f9f7	1779	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1780	I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	1781	}
<>	144:ef7eb2e8f9f7	1782
<>	144:ef7eb2e8f9f7	1783	do
<>	144:ef7eb2e8f9f7	1784	{
<>	144:ef7eb2e8f9f7	1785	/* Wait until TXIS flag is set */
<>	144:ef7eb2e8f9f7	1786	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1787	{
<>	144:ef7eb2e8f9f7	1788	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	1789	{
<>	144:ef7eb2e8f9f7	1790	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1791	}
<>	144:ef7eb2e8f9f7	1792	else
<>	144:ef7eb2e8f9f7	1793	{
<>	144:ef7eb2e8f9f7	1794	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1795	}
<>	144:ef7eb2e8f9f7	1796	}
<>	144:ef7eb2e8f9f7	1797
<>	144:ef7eb2e8f9f7	1798	/* Write data to TXDR */
<>	144:ef7eb2e8f9f7	1799	hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	1800	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	1801	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	1802
<>	144:ef7eb2e8f9f7	1803	if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U))
<>	144:ef7eb2e8f9f7	1804	{
<>	144:ef7eb2e8f9f7	1805	/* Wait until TCR flag is set */
<>	144:ef7eb2e8f9f7	1806	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1807	{
<>	144:ef7eb2e8f9f7	1808	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1809	}
<>	144:ef7eb2e8f9f7	1810
<>	144:ef7eb2e8f9f7	1811	if(hi2c->XferCount > MAX_NBYTE_SIZE)
<>	144:ef7eb2e8f9f7	1812	{
<>	144:ef7eb2e8f9f7	1813	hi2c->XferSize = MAX_NBYTE_SIZE;
<>	144:ef7eb2e8f9f7	1814	I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	1815	}
<>	144:ef7eb2e8f9f7	1816	else
<>	144:ef7eb2e8f9f7	1817	{
<>	144:ef7eb2e8f9f7	1818	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1819	I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	1820	}
<>	144:ef7eb2e8f9f7	1821	}
<>	144:ef7eb2e8f9f7	1822
<>	144:ef7eb2e8f9f7	1823	}while(hi2c->XferCount > 0U);
<>	144:ef7eb2e8f9f7	1824
<>	144:ef7eb2e8f9f7	1825	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<>	144:ef7eb2e8f9f7	1826	/* Wait until STOPF flag is reset */
<>	144:ef7eb2e8f9f7	1827	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1828	{
<>	144:ef7eb2e8f9f7	1829	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	1830	{
<>	144:ef7eb2e8f9f7	1831	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1832	}
<>	144:ef7eb2e8f9f7	1833	else
<>	144:ef7eb2e8f9f7	1834	{
<>	144:ef7eb2e8f9f7	1835	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1836	}
<>	144:ef7eb2e8f9f7	1837	}
<>	144:ef7eb2e8f9f7	1838
<>	144:ef7eb2e8f9f7	1839	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	1840	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	1841
<>	144:ef7eb2e8f9f7	1842	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	1843	I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	1844
<>	144:ef7eb2e8f9f7	1845	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1846	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	1847
<>	144:ef7eb2e8f9f7	1848	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1849	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1850
<>	144:ef7eb2e8f9f7	1851	return HAL_OK;
<>	144:ef7eb2e8f9f7	1852	}
<>	144:ef7eb2e8f9f7	1853	else
<>	144:ef7eb2e8f9f7	1854	{
<>	144:ef7eb2e8f9f7	1855	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1856	}
<>	144:ef7eb2e8f9f7	1857	}
<>	144:ef7eb2e8f9f7	1858
<>	144:ef7eb2e8f9f7	1859	/**
<>	144:ef7eb2e8f9f7	1860	* @brief Read an amount of data in blocking mode from a specific memory address
<>	144:ef7eb2e8f9f7	1861	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1862	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1863	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	1864	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	1865	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	1866	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1867	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1868	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	1869	* @retval HAL status
<>	144:ef7eb2e8f9f7	1870	*/
<>	144:ef7eb2e8f9f7	1871	HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	1872	{
<>	144:ef7eb2e8f9f7	1873	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	1874
<>	144:ef7eb2e8f9f7	1875	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1876	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	1877
<>	144:ef7eb2e8f9f7	1878	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1879	{
<>	144:ef7eb2e8f9f7	1880	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1881	{
<>	144:ef7eb2e8f9f7	1882	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1883	}
<>	144:ef7eb2e8f9f7	1884
<>	144:ef7eb2e8f9f7	1885	/* Process Locked */
<>	144:ef7eb2e8f9f7	1886	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1887
<>	144:ef7eb2e8f9f7	1888	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	1889	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1890
<>	144:ef7eb2e8f9f7	1891	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1892	{
<>	144:ef7eb2e8f9f7	1893	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1894	}
<>	144:ef7eb2e8f9f7	1895
<>	144:ef7eb2e8f9f7	1896	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	1897	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	1898	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1899
<>	144:ef7eb2e8f9f7	1900	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	1901	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1902	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1903	hi2c->XferISR = NULL;
<>	144:ef7eb2e8f9f7	1904
<>	144:ef7eb2e8f9f7	1905	/* Send Slave Address and Memory Address */
<>	144:ef7eb2e8f9f7	1906	if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1907	{
<>	144:ef7eb2e8f9f7	1908	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	1909	{
<>	144:ef7eb2e8f9f7	1910	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1911	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1912	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1913	}
<>	144:ef7eb2e8f9f7	1914	else
<>	144:ef7eb2e8f9f7	1915	{
<>	144:ef7eb2e8f9f7	1916	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1917	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1918	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1919	}
<>	144:ef7eb2e8f9f7	1920	}
<>	144:ef7eb2e8f9f7	1921
<>	144:ef7eb2e8f9f7	1922	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	1923	/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
<>	144:ef7eb2e8f9f7	1924	if(hi2c->XferCount > MAX_NBYTE_SIZE)
<>	144:ef7eb2e8f9f7	1925	{
<>	144:ef7eb2e8f9f7	1926	hi2c->XferSize = MAX_NBYTE_SIZE;
<>	144:ef7eb2e8f9f7	1927	I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
<>	144:ef7eb2e8f9f7	1928	}
<>	144:ef7eb2e8f9f7	1929	else
<>	144:ef7eb2e8f9f7	1930	{
<>	144:ef7eb2e8f9f7	1931	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1932	I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
<>	144:ef7eb2e8f9f7	1933	}
<>	144:ef7eb2e8f9f7	1934
<>	144:ef7eb2e8f9f7	1935	do
<>	144:ef7eb2e8f9f7	1936	{
<>	144:ef7eb2e8f9f7	1937	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	1938	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1939	{
<>	144:ef7eb2e8f9f7	1940	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1941	}
<>	144:ef7eb2e8f9f7	1942
<>	144:ef7eb2e8f9f7	1943	/* Read data from RXDR */
<>	144:ef7eb2e8f9f7	1944	(*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
<>	144:ef7eb2e8f9f7	1945	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	1946	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	1947
<>	144:ef7eb2e8f9f7	1948	if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
<>	144:ef7eb2e8f9f7	1949	{
<>	144:ef7eb2e8f9f7	1950	/* Wait until TCR flag is set */
<>	144:ef7eb2e8f9f7	1951	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1952	{
<>	144:ef7eb2e8f9f7	1953	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1954	}
<>	144:ef7eb2e8f9f7	1955
<>	144:ef7eb2e8f9f7	1956	if(hi2c->XferCount > MAX_NBYTE_SIZE)
<>	144:ef7eb2e8f9f7	1957	{
<>	144:ef7eb2e8f9f7	1958	hi2c->XferSize = MAX_NBYTE_SIZE;
<>	144:ef7eb2e8f9f7	1959	I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	1960	}
<>	144:ef7eb2e8f9f7	1961	else
<>	144:ef7eb2e8f9f7	1962	{
<>	144:ef7eb2e8f9f7	1963	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1964	I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	1965	}
<>	144:ef7eb2e8f9f7	1966	}
<>	144:ef7eb2e8f9f7	1967	}while(hi2c->XferCount > 0U);
<>	144:ef7eb2e8f9f7	1968
<>	144:ef7eb2e8f9f7	1969	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<>	144:ef7eb2e8f9f7	1970	/* Wait until STOPF flag is reset */
<>	144:ef7eb2e8f9f7	1971	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1972	{
<>	144:ef7eb2e8f9f7	1973	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	1974	{
<>	144:ef7eb2e8f9f7	1975	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1976	}
<>	144:ef7eb2e8f9f7	1977	else
<>	144:ef7eb2e8f9f7	1978	{
<>	144:ef7eb2e8f9f7	1979	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1980	}
<>	144:ef7eb2e8f9f7	1981	}
<>	144:ef7eb2e8f9f7	1982
<>	144:ef7eb2e8f9f7	1983	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	1984	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	1985
<>	144:ef7eb2e8f9f7	1986	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	1987	I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	1988
<>	144:ef7eb2e8f9f7	1989	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1990	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	1991
<>	144:ef7eb2e8f9f7	1992	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1993	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1994
<>	144:ef7eb2e8f9f7	1995	return HAL_OK;
<>	144:ef7eb2e8f9f7	1996	}
<>	144:ef7eb2e8f9f7	1997	else
<>	144:ef7eb2e8f9f7	1998	{
<>	144:ef7eb2e8f9f7	1999	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2000	}
<>	144:ef7eb2e8f9f7	2001	}
<>	144:ef7eb2e8f9f7	2002	/**
<>	144:ef7eb2e8f9f7	2003	* @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
<>	144:ef7eb2e8f9f7	2004	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2005	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2006	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	2007	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	2008	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	2009	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2010	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2011	* @retval HAL status
<>	144:ef7eb2e8f9f7	2012	*/
<>	144:ef7eb2e8f9f7	2013	HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	2014	{
<>	144:ef7eb2e8f9f7	2015	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	2016	uint32_t xfermode = 0U;
<>	144:ef7eb2e8f9f7	2017
<>	144:ef7eb2e8f9f7	2018	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2019	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	2020
<>	144:ef7eb2e8f9f7	2021	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2022	{
<>	144:ef7eb2e8f9f7	2023	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	2024	{
<>	144:ef7eb2e8f9f7	2025	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2026	}
<>	144:ef7eb2e8f9f7	2027
<>	144:ef7eb2e8f9f7	2028	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<>	144:ef7eb2e8f9f7	2029	{
<>	144:ef7eb2e8f9f7	2030	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2031	}
<>	144:ef7eb2e8f9f7	2032
<>	144:ef7eb2e8f9f7	2033	/* Process Locked */
<>	144:ef7eb2e8f9f7	2034	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2035
<>	144:ef7eb2e8f9f7	2036	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	2037	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2038
<>	144:ef7eb2e8f9f7	2039	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	2040	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	2041	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2042
<>	144:ef7eb2e8f9f7	2043	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	2044	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	2045	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2046	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	2047	hi2c->XferISR = I2C_Master_ISR_IT;
<>	144:ef7eb2e8f9f7	2048
<>	144:ef7eb2e8f9f7	2049	if(hi2c->XferCount > MAX_NBYTE_SIZE)
<>	144:ef7eb2e8f9f7	2050	{
<>	144:ef7eb2e8f9f7	2051	hi2c->XferSize = MAX_NBYTE_SIZE;
<>	144:ef7eb2e8f9f7	2052	xfermode = I2C_RELOAD_MODE;
<>	144:ef7eb2e8f9f7	2053	}
<>	144:ef7eb2e8f9f7	2054	else
<>	144:ef7eb2e8f9f7	2055	{
<>	144:ef7eb2e8f9f7	2056	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	2057	xfermode = I2C_AUTOEND_MODE;
<>	144:ef7eb2e8f9f7	2058	}
<>	144:ef7eb2e8f9f7	2059
<>	144:ef7eb2e8f9f7	2060	/* Send Slave Address and Memory Address */
<>	144:ef7eb2e8f9f7	2061	if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2062	{
<>	144:ef7eb2e8f9f7	2063	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	2064	{
<>	144:ef7eb2e8f9f7	2065	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2066	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2067	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2068	}
<>	144:ef7eb2e8f9f7	2069	else
<>	144:ef7eb2e8f9f7	2070	{
<>	144:ef7eb2e8f9f7	2071	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2072	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2073	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2074	}
<>	144:ef7eb2e8f9f7	2075	}
<>	144:ef7eb2e8f9f7	2076
<>	144:ef7eb2e8f9f7	2077	/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
<>	144:ef7eb2e8f9f7	2078	I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	2079
<>	144:ef7eb2e8f9f7	2080	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2081	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2082
<>	144:ef7eb2e8f9f7	2083	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	2084	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	2085	process unlock */
<>	144:ef7eb2e8f9f7	2086
<>	144:ef7eb2e8f9f7	2087	/* Enable ERR, TC, STOP, NACK, TXI interrupt */
<>	144:ef7eb2e8f9f7	2088	/* possible to enable all of these */
<>	144:ef7eb2e8f9f7	2089	/* I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_RXI \| I2C_IT_TXI */
<>	144:ef7eb2e8f9f7	2090	I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
<>	144:ef7eb2e8f9f7	2091
<>	144:ef7eb2e8f9f7	2092	return HAL_OK;
<>	144:ef7eb2e8f9f7	2093	}
<>	144:ef7eb2e8f9f7	2094	else
<>	144:ef7eb2e8f9f7	2095	{
<>	144:ef7eb2e8f9f7	2096	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2097	}
<>	144:ef7eb2e8f9f7	2098	}
<>	144:ef7eb2e8f9f7	2099
<>	144:ef7eb2e8f9f7	2100	/**
<>	144:ef7eb2e8f9f7	2101	* @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
<>	144:ef7eb2e8f9f7	2102	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2103	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2104	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	2105	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	2106	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	2107	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2108	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2109	* @retval HAL status
<>	144:ef7eb2e8f9f7	2110	*/
<>	144:ef7eb2e8f9f7	2111	HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	2112	{
<>	144:ef7eb2e8f9f7	2113	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	2114	uint32_t xfermode = 0U;
<>	144:ef7eb2e8f9f7	2115
<>	144:ef7eb2e8f9f7	2116	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2117	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	2118
<>	144:ef7eb2e8f9f7	2119	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2120	{
<>	144:ef7eb2e8f9f7	2121	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	2122	{
<>	144:ef7eb2e8f9f7	2123	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2124	}
<>	144:ef7eb2e8f9f7	2125
<>	144:ef7eb2e8f9f7	2126	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<>	144:ef7eb2e8f9f7	2127	{
<>	144:ef7eb2e8f9f7	2128	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2129	}
<>	144:ef7eb2e8f9f7	2130
<>	144:ef7eb2e8f9f7	2131	/* Process Locked */
<>	144:ef7eb2e8f9f7	2132	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2133
<>	144:ef7eb2e8f9f7	2134	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	2135	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2136
<>	144:ef7eb2e8f9f7	2137	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	2138	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	2139	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2140
<>	144:ef7eb2e8f9f7	2141	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	2142	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	2143	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2144	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	2145	hi2c->XferISR = I2C_Master_ISR_IT;
<>	144:ef7eb2e8f9f7	2146
<>	144:ef7eb2e8f9f7	2147	if(hi2c->XferCount > MAX_NBYTE_SIZE)
<>	144:ef7eb2e8f9f7	2148	{
<>	144:ef7eb2e8f9f7	2149	hi2c->XferSize = MAX_NBYTE_SIZE;
<>	144:ef7eb2e8f9f7	2150	xfermode = I2C_RELOAD_MODE;
<>	144:ef7eb2e8f9f7	2151	}
<>	144:ef7eb2e8f9f7	2152	else
<>	144:ef7eb2e8f9f7	2153	{
<>	144:ef7eb2e8f9f7	2154	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	2155	xfermode = I2C_AUTOEND_MODE;
<>	144:ef7eb2e8f9f7	2156	}
<>	144:ef7eb2e8f9f7	2157
<>	144:ef7eb2e8f9f7	2158	/* Send Slave Address and Memory Address */
<>	144:ef7eb2e8f9f7	2159	if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2160	{
<>	144:ef7eb2e8f9f7	2161	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	2162	{
<>	144:ef7eb2e8f9f7	2163	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2164	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2165	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2166	}
<>	144:ef7eb2e8f9f7	2167	else
<>	144:ef7eb2e8f9f7	2168	{
<>	144:ef7eb2e8f9f7	2169	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2170	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2171	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2172	}
<>	144:ef7eb2e8f9f7	2173	}
<>	144:ef7eb2e8f9f7	2174
<>	144:ef7eb2e8f9f7	2175	/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
<>	144:ef7eb2e8f9f7	2176	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
<>	144:ef7eb2e8f9f7	2177
<>	144:ef7eb2e8f9f7	2178	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2179	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2180
<>	144:ef7eb2e8f9f7	2181	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	2182	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	2183	process unlock */
<>	144:ef7eb2e8f9f7	2184
<>	144:ef7eb2e8f9f7	2185	/* Enable ERR, TC, STOP, NACK, RXI interrupt */
<>	144:ef7eb2e8f9f7	2186	/* possible to enable all of these */
<>	144:ef7eb2e8f9f7	2187	/* I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_RXI \| I2C_IT_TXI */
<>	144:ef7eb2e8f9f7	2188	I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
<>	144:ef7eb2e8f9f7	2189
<>	144:ef7eb2e8f9f7	2190	return HAL_OK;
<>	144:ef7eb2e8f9f7	2191	}
<>	144:ef7eb2e8f9f7	2192	else
<>	144:ef7eb2e8f9f7	2193	{
<>	144:ef7eb2e8f9f7	2194	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2195	}
<>	144:ef7eb2e8f9f7	2196	}
<>	144:ef7eb2e8f9f7	2197	/**
<>	144:ef7eb2e8f9f7	2198	* @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
<>	144:ef7eb2e8f9f7	2199	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2200	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2201	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	2202	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	2203	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	2204	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2205	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2206	* @retval HAL status
<>	144:ef7eb2e8f9f7	2207	*/
<>	144:ef7eb2e8f9f7	2208	HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	2209	{
<>	144:ef7eb2e8f9f7	2210	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	2211	uint32_t xfermode = 0U;
<>	144:ef7eb2e8f9f7	2212
<>	144:ef7eb2e8f9f7	2213	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2214	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	2215
<>	144:ef7eb2e8f9f7	2216	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2217	{
<>	144:ef7eb2e8f9f7	2218	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	2219	{
<>	144:ef7eb2e8f9f7	2220	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2221	}
<>	144:ef7eb2e8f9f7	2222
<>	144:ef7eb2e8f9f7	2223	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<>	144:ef7eb2e8f9f7	2224	{
<>	144:ef7eb2e8f9f7	2225	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2226	}
<>	144:ef7eb2e8f9f7	2227
<>	144:ef7eb2e8f9f7	2228	/* Process Locked */
<>	144:ef7eb2e8f9f7	2229	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2230
<>	144:ef7eb2e8f9f7	2231	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	2232	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2233
<>	144:ef7eb2e8f9f7	2234	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	2235	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	2236	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2237
<>	144:ef7eb2e8f9f7	2238	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	2239	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	2240	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2241	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	2242	hi2c->XferISR = I2C_Master_ISR_DMA;
<>	144:ef7eb2e8f9f7	2243
<>	144:ef7eb2e8f9f7	2244	if(hi2c->XferCount > MAX_NBYTE_SIZE)
<>	144:ef7eb2e8f9f7	2245	{
<>	144:ef7eb2e8f9f7	2246	hi2c->XferSize = MAX_NBYTE_SIZE;
<>	144:ef7eb2e8f9f7	2247	xfermode = I2C_RELOAD_MODE;
<>	144:ef7eb2e8f9f7	2248	}
<>	144:ef7eb2e8f9f7	2249	else
<>	144:ef7eb2e8f9f7	2250	{
<>	144:ef7eb2e8f9f7	2251	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	2252	xfermode = I2C_AUTOEND_MODE;
<>	144:ef7eb2e8f9f7	2253	}
<>	144:ef7eb2e8f9f7	2254
<>	144:ef7eb2e8f9f7	2255	/* Send Slave Address and Memory Address */
<>	144:ef7eb2e8f9f7	2256	if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2257	{
<>	144:ef7eb2e8f9f7	2258	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	2259	{
<>	144:ef7eb2e8f9f7	2260	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2261	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2262	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2263	}
<>	144:ef7eb2e8f9f7	2264	else
<>	144:ef7eb2e8f9f7	2265	{
<>	144:ef7eb2e8f9f7	2266	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2267	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2268	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2269	}
<>	144:ef7eb2e8f9f7	2270	}
<>	144:ef7eb2e8f9f7	2271
<>	144:ef7eb2e8f9f7	2272	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	2273	hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
<>	144:ef7eb2e8f9f7	2274
<>	144:ef7eb2e8f9f7	2275	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2276	hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	2277
<>	144:ef7eb2e8f9f7	2278	/* Set the unused DMA callbacks to NULL */
<>	144:ef7eb2e8f9f7	2279	hi2c->hdmatx->XferHalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2280	hi2c->hdmatx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	2281
<>	144:ef7eb2e8f9f7	2282	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	2283	HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
<>	144:ef7eb2e8f9f7	2284
<>	144:ef7eb2e8f9f7	2285	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	2286	/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
<>	144:ef7eb2e8f9f7	2287	I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	2288
<>	144:ef7eb2e8f9f7	2289	/* Update XferCount value */
<>	144:ef7eb2e8f9f7	2290	hi2c->XferCount -= hi2c->XferSize;
<>	144:ef7eb2e8f9f7	2291
<>	144:ef7eb2e8f9f7	2292	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2293	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2294
<>	144:ef7eb2e8f9f7	2295	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	2296	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	2297	process unlock */
<>	144:ef7eb2e8f9f7	2298	/* Enable ERR and NACK interrupts */
<>	144:ef7eb2e8f9f7	2299	I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
<>	144:ef7eb2e8f9f7	2300
<>	144:ef7eb2e8f9f7	2301	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	2302	hi2c->Instance->CR1 \|= I2C_CR1_TXDMAEN;
<>	144:ef7eb2e8f9f7	2303
<>	144:ef7eb2e8f9f7	2304	return HAL_OK;
<>	144:ef7eb2e8f9f7	2305	}
<>	144:ef7eb2e8f9f7	2306	else
<>	144:ef7eb2e8f9f7	2307	{
<>	144:ef7eb2e8f9f7	2308	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2309	}
<>	144:ef7eb2e8f9f7	2310	}
<>	144:ef7eb2e8f9f7	2311
<>	144:ef7eb2e8f9f7	2312	/**
<>	144:ef7eb2e8f9f7	2313	* @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
<>	144:ef7eb2e8f9f7	2314	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2315	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2316	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	2317	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	2318	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	2319	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2320	* @param Size Amount of data to be read
<>	144:ef7eb2e8f9f7	2321	* @retval HAL status
<>	144:ef7eb2e8f9f7	2322	*/
<>	144:ef7eb2e8f9f7	2323	HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	2324	{
<>	144:ef7eb2e8f9f7	2325	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	2326	uint32_t xfermode = 0U;
<>	144:ef7eb2e8f9f7	2327
<>	144:ef7eb2e8f9f7	2328	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2329	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	2330
<>	144:ef7eb2e8f9f7	2331	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2332	{
<>	144:ef7eb2e8f9f7	2333	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	2334	{
<>	144:ef7eb2e8f9f7	2335	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2336	}
<>	144:ef7eb2e8f9f7	2337
<>	144:ef7eb2e8f9f7	2338	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<>	144:ef7eb2e8f9f7	2339	{
<>	144:ef7eb2e8f9f7	2340	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2341	}
<>	144:ef7eb2e8f9f7	2342
<>	144:ef7eb2e8f9f7	2343	/* Process Locked */
<>	144:ef7eb2e8f9f7	2344	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2345
<>	144:ef7eb2e8f9f7	2346	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	2347	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2348
<>	144:ef7eb2e8f9f7	2349	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	2350	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	2351	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2352
<>	144:ef7eb2e8f9f7	2353	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	2354	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	2355	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2356	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	2357	hi2c->XferISR = I2C_Master_ISR_DMA;
<>	144:ef7eb2e8f9f7	2358
<>	144:ef7eb2e8f9f7	2359	if(hi2c->XferCount > MAX_NBYTE_SIZE)
<>	144:ef7eb2e8f9f7	2360	{
<>	144:ef7eb2e8f9f7	2361	hi2c->XferSize = MAX_NBYTE_SIZE;
<>	144:ef7eb2e8f9f7	2362	xfermode = I2C_RELOAD_MODE;
<>	144:ef7eb2e8f9f7	2363	}
<>	144:ef7eb2e8f9f7	2364	else
<>	144:ef7eb2e8f9f7	2365	{
<>	144:ef7eb2e8f9f7	2366	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	2367	xfermode = I2C_AUTOEND_MODE;
<>	144:ef7eb2e8f9f7	2368	}
<>	144:ef7eb2e8f9f7	2369
<>	144:ef7eb2e8f9f7	2370	/* Send Slave Address and Memory Address */
<>	144:ef7eb2e8f9f7	2371	if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2372	{
<>	144:ef7eb2e8f9f7	2373	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	2374	{
<>	144:ef7eb2e8f9f7	2375	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2376	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2377	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2378	}
<>	144:ef7eb2e8f9f7	2379	else
<>	144:ef7eb2e8f9f7	2380	{
<>	144:ef7eb2e8f9f7	2381	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2382	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2383	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2384	}
<>	144:ef7eb2e8f9f7	2385	}
<>	144:ef7eb2e8f9f7	2386
<>	144:ef7eb2e8f9f7	2387	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	2388	hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
<>	144:ef7eb2e8f9f7	2389
<>	144:ef7eb2e8f9f7	2390	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2391	hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	2392
<>	144:ef7eb2e8f9f7	2393	/* Set the unused DMA callbacks to NULL */
<>	144:ef7eb2e8f9f7	2394	hi2c->hdmarx->XferHalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2395	hi2c->hdmarx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	2396
<>	144:ef7eb2e8f9f7	2397	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	2398	HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
<>	144:ef7eb2e8f9f7	2399
<>	144:ef7eb2e8f9f7	2400	/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
<>	144:ef7eb2e8f9f7	2401	I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
<>	144:ef7eb2e8f9f7	2402
<>	144:ef7eb2e8f9f7	2403	/* Update XferCount value */
<>	144:ef7eb2e8f9f7	2404	hi2c->XferCount -= hi2c->XferSize;
<>	144:ef7eb2e8f9f7	2405
<>	144:ef7eb2e8f9f7	2406	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2407	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2408
<>	144:ef7eb2e8f9f7	2409	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	2410	hi2c->Instance->CR1 \|= I2C_CR1_RXDMAEN;
<>	144:ef7eb2e8f9f7	2411
<>	144:ef7eb2e8f9f7	2412	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	2413	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	2414	process unlock */
<>	144:ef7eb2e8f9f7	2415	/* Enable ERR and NACK interrupts */
<>	144:ef7eb2e8f9f7	2416	I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
<>	144:ef7eb2e8f9f7	2417
<>	144:ef7eb2e8f9f7	2418	return HAL_OK;
<>	144:ef7eb2e8f9f7	2419	}
<>	144:ef7eb2e8f9f7	2420	else
<>	144:ef7eb2e8f9f7	2421	{
<>	144:ef7eb2e8f9f7	2422	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2423	}
<>	144:ef7eb2e8f9f7	2424	}
<>	144:ef7eb2e8f9f7	2425
<>	144:ef7eb2e8f9f7	2426	/**
<>	144:ef7eb2e8f9f7	2427	* @brief Checks if target device is ready for communication.
<>	144:ef7eb2e8f9f7	2428	* @note This function is used with Memory devices
<>	144:ef7eb2e8f9f7	2429	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2430	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2431	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	2432	* @param Trials Number of trials
<>	144:ef7eb2e8f9f7	2433	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	2434	* @retval HAL status
<>	144:ef7eb2e8f9f7	2435	*/
<>	144:ef7eb2e8f9f7	2436	HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	2437	{
<>	144:ef7eb2e8f9f7	2438	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	2439
<>	144:ef7eb2e8f9f7	2440	__IO uint32_t I2C_Trials = 0U;
<>	144:ef7eb2e8f9f7	2441
<>	144:ef7eb2e8f9f7	2442	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2443	{
<>	144:ef7eb2e8f9f7	2444	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<>	144:ef7eb2e8f9f7	2445	{
<>	144:ef7eb2e8f9f7	2446	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2447	}
<>	144:ef7eb2e8f9f7	2448
<>	144:ef7eb2e8f9f7	2449	/* Process Locked */
<>	144:ef7eb2e8f9f7	2450	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2451
<>	144:ef7eb2e8f9f7	2452	hi2c->State = HAL_I2C_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2453	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2454
<>	144:ef7eb2e8f9f7	2455	do
<>	144:ef7eb2e8f9f7	2456	{
<>	144:ef7eb2e8f9f7	2457	/* Generate Start */
<>	144:ef7eb2e8f9f7	2458	hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress);
<>	144:ef7eb2e8f9f7	2459
<>	144:ef7eb2e8f9f7	2460	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<>	144:ef7eb2e8f9f7	2461	/* Wait until STOPF flag is set or a NACK flag is set*/
<>	144:ef7eb2e8f9f7	2462	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2463	while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
<>	144:ef7eb2e8f9f7	2464	{
<>	144:ef7eb2e8f9f7	2465	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	2466	{
<>	144:ef7eb2e8f9f7	2467	if((Timeout == 0U) \|\| ((HAL_GetTick() - tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	2468	{
<>	144:ef7eb2e8f9f7	2469	/* Device is ready */
<>	144:ef7eb2e8f9f7	2470	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2471	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2472	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2473	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2474	}
<>	144:ef7eb2e8f9f7	2475	}
<>	144:ef7eb2e8f9f7	2476	}
<>	144:ef7eb2e8f9f7	2477
<>	144:ef7eb2e8f9f7	2478	/* Check if the NACKF flag has not been set */
<>	144:ef7eb2e8f9f7	2479	if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
<>	144:ef7eb2e8f9f7	2480	{
<>	144:ef7eb2e8f9f7	2481	/* Wait until STOPF flag is reset */
<>	144:ef7eb2e8f9f7	2482	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2483	{
<>	144:ef7eb2e8f9f7	2484	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2485	}
<>	144:ef7eb2e8f9f7	2486
<>	144:ef7eb2e8f9f7	2487	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	2488	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	2489
<>	144:ef7eb2e8f9f7	2490	/* Device is ready */
<>	144:ef7eb2e8f9f7	2491	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2492
<>	144:ef7eb2e8f9f7	2493	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2494	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2495
<>	144:ef7eb2e8f9f7	2496	return HAL_OK;
<>	144:ef7eb2e8f9f7	2497	}
<>	144:ef7eb2e8f9f7	2498	else
<>	144:ef7eb2e8f9f7	2499	{
<>	144:ef7eb2e8f9f7	2500	/* Wait until STOPF flag is reset */
<>	144:ef7eb2e8f9f7	2501	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2502	{
<>	144:ef7eb2e8f9f7	2503	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2504	}
<>	144:ef7eb2e8f9f7	2505
<>	144:ef7eb2e8f9f7	2506	/* Clear NACK Flag */
<>	144:ef7eb2e8f9f7	2507	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	2508
<>	144:ef7eb2e8f9f7	2509	/* Clear STOP Flag, auto generated with autoend*/
<>	144:ef7eb2e8f9f7	2510	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	2511	}
<>	144:ef7eb2e8f9f7	2512
<>	144:ef7eb2e8f9f7	2513	/* Check if the maximum allowed number of trials has been reached */
<>	144:ef7eb2e8f9f7	2514	if (I2C_Trials++ == Trials)
<>	144:ef7eb2e8f9f7	2515	{
<>	144:ef7eb2e8f9f7	2516	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2517	hi2c->Instance->CR2 \|= I2C_CR2_STOP;
<>	144:ef7eb2e8f9f7	2518
<>	144:ef7eb2e8f9f7	2519	/* Wait until STOPF flag is reset */
<>	144:ef7eb2e8f9f7	2520	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2521	{
<>	144:ef7eb2e8f9f7	2522	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2523	}
<>	144:ef7eb2e8f9f7	2524
<>	144:ef7eb2e8f9f7	2525	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	2526	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	2527	}
<>	144:ef7eb2e8f9f7	2528	}while(I2C_Trials < Trials);
<>	144:ef7eb2e8f9f7	2529
<>	144:ef7eb2e8f9f7	2530	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2531
<>	144:ef7eb2e8f9f7	2532	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2533	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2534
<>	144:ef7eb2e8f9f7	2535	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2536	}
<>	144:ef7eb2e8f9f7	2537	else
<>	144:ef7eb2e8f9f7	2538	{
<>	144:ef7eb2e8f9f7	2539	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2540	}
<>	144:ef7eb2e8f9f7	2541	}
<>	144:ef7eb2e8f9f7	2542
<>	144:ef7eb2e8f9f7	2543	/**
<>	144:ef7eb2e8f9f7	2544	* @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
<>	144:ef7eb2e8f9f7	2545	* @note This interface allow to manage repeated start condition when a direction change during transfer
<>	144:ef7eb2e8f9f7	2546	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2547	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2548	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	2549	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2550	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2551	* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
<>	144:ef7eb2e8f9f7	2552	* @retval HAL status
<>	144:ef7eb2e8f9f7	2553	*/
<>	144:ef7eb2e8f9f7	2554	HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t XferOptions)
<>	144:ef7eb2e8f9f7	2555	{
<>	144:ef7eb2e8f9f7	2556	uint32_t xfermode = 0U;
<>	144:ef7eb2e8f9f7	2557	uint32_t xferrequest = I2C_GENERATE_START_WRITE;
<>	144:ef7eb2e8f9f7	2558
<>	144:ef7eb2e8f9f7	2559	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2560	assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
<>	144:ef7eb2e8f9f7	2561
<>	144:ef7eb2e8f9f7	2562	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2563	{
<>	144:ef7eb2e8f9f7	2564	/* Process Locked */
<>	144:ef7eb2e8f9f7	2565	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2566
<>	144:ef7eb2e8f9f7	2567	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	2568	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	2569	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2570
<>	144:ef7eb2e8f9f7	2571	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	2572	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	2573	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2574	hi2c->XferOptions = XferOptions;
<>	144:ef7eb2e8f9f7	2575	hi2c->XferISR = I2C_Master_ISR_IT;
<>	144:ef7eb2e8f9f7	2576
<>	144:ef7eb2e8f9f7	2577	/* If size > MAX_NBYTE_SIZE, use reload mode */
<>	144:ef7eb2e8f9f7	2578	if(hi2c->XferCount > MAX_NBYTE_SIZE)
<>	144:ef7eb2e8f9f7	2579	{
<>	144:ef7eb2e8f9f7	2580	hi2c->XferSize = MAX_NBYTE_SIZE;
<>	144:ef7eb2e8f9f7	2581	xfermode = I2C_RELOAD_MODE;
<>	144:ef7eb2e8f9f7	2582	}
<>	144:ef7eb2e8f9f7	2583	else
<>	144:ef7eb2e8f9f7	2584	{
<>	144:ef7eb2e8f9f7	2585	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	2586	xfermode = hi2c->XferOptions;
<>	144:ef7eb2e8f9f7	2587
<>	144:ef7eb2e8f9f7	2588	/* If transfer direction not change, do not generate Restart Condition */
<>	144:ef7eb2e8f9f7	2589	/* Mean Previous state is same as current state */
<>	144:ef7eb2e8f9f7	2590	if(hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_TX)
<>	144:ef7eb2e8f9f7	2591	{
<>	144:ef7eb2e8f9f7	2592	xferrequest = I2C_NO_STARTSTOP;
<>	144:ef7eb2e8f9f7	2593	}
<>	144:ef7eb2e8f9f7	2594	}
<>	144:ef7eb2e8f9f7	2595
<>	144:ef7eb2e8f9f7	2596
<>	144:ef7eb2e8f9f7	2597	/* Send Slave Address and set NBYTES to write */
<>	144:ef7eb2e8f9f7	2598	I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
<>	144:ef7eb2e8f9f7	2599
<>	144:ef7eb2e8f9f7	2600	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2601	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2602
<>	144:ef7eb2e8f9f7	2603	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	2604	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	2605	process unlock */
<>	144:ef7eb2e8f9f7	2606	I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
<>	144:ef7eb2e8f9f7	2607
<>	144:ef7eb2e8f9f7	2608	return HAL_OK;
<>	144:ef7eb2e8f9f7	2609	}
<>	144:ef7eb2e8f9f7	2610	else
<>	144:ef7eb2e8f9f7	2611	{
<>	144:ef7eb2e8f9f7	2612	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2613	}
<>	144:ef7eb2e8f9f7	2614	}
<>	144:ef7eb2e8f9f7	2615
<>	144:ef7eb2e8f9f7	2616	/**
<>	144:ef7eb2e8f9f7	2617	* @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	2618	* @note This interface allow to manage repeated start condition when a direction change during transfer
<>	144:ef7eb2e8f9f7	2619	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2620	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2621	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	2622	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2623	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2624	* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
<>	144:ef7eb2e8f9f7	2625	* @retval HAL status
<>	144:ef7eb2e8f9f7	2626	*/
<>	144:ef7eb2e8f9f7	2627	HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t XferOptions)
<>	144:ef7eb2e8f9f7	2628	{
<>	144:ef7eb2e8f9f7	2629	uint32_t xfermode = 0U;
<>	144:ef7eb2e8f9f7	2630	uint32_t xferrequest = I2C_GENERATE_START_READ;
<>	144:ef7eb2e8f9f7	2631
<>	144:ef7eb2e8f9f7	2632	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2633	assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
<>	144:ef7eb2e8f9f7	2634
<>	144:ef7eb2e8f9f7	2635	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2636	{
<>	144:ef7eb2e8f9f7	2637	/* Process Locked */
<>	144:ef7eb2e8f9f7	2638	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2639
<>	144:ef7eb2e8f9f7	2640	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	2641	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	2642	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2643
<>	144:ef7eb2e8f9f7	2644	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	2645	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	2646	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2647	hi2c->XferOptions = XferOptions;
<>	144:ef7eb2e8f9f7	2648	hi2c->XferISR = I2C_Master_ISR_IT;
<>	144:ef7eb2e8f9f7	2649
<>	144:ef7eb2e8f9f7	2650	/* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
<>	144:ef7eb2e8f9f7	2651	if(hi2c->XferCount > MAX_NBYTE_SIZE)
<>	144:ef7eb2e8f9f7	2652	{
<>	144:ef7eb2e8f9f7	2653	hi2c->XferSize = MAX_NBYTE_SIZE;
<>	144:ef7eb2e8f9f7	2654	xfermode = I2C_RELOAD_MODE;
<>	144:ef7eb2e8f9f7	2655	}
<>	144:ef7eb2e8f9f7	2656	else
<>	144:ef7eb2e8f9f7	2657	{
<>	144:ef7eb2e8f9f7	2658	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	2659	xfermode = hi2c->XferOptions;
<>	144:ef7eb2e8f9f7	2660
<>	144:ef7eb2e8f9f7	2661	/* If transfer direction not change, do not generate Restart Condition */
<>	144:ef7eb2e8f9f7	2662	/* Mean Previous state is same as current state */
<>	144:ef7eb2e8f9f7	2663	if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
<>	144:ef7eb2e8f9f7	2664	{
<>	144:ef7eb2e8f9f7	2665	xferrequest = I2C_NO_STARTSTOP;
<>	144:ef7eb2e8f9f7	2666	}
<>	144:ef7eb2e8f9f7	2667	}
<>	144:ef7eb2e8f9f7	2668
<>	144:ef7eb2e8f9f7	2669	/* Send Slave Address and set NBYTES to read */
<>	144:ef7eb2e8f9f7	2670	I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, xferrequest);
<>	144:ef7eb2e8f9f7	2671
<>	144:ef7eb2e8f9f7	2672	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2673	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2674
<>	144:ef7eb2e8f9f7	2675	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	2676	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	2677	process unlock */
<>	144:ef7eb2e8f9f7	2678	I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
<>	144:ef7eb2e8f9f7	2679
<>	144:ef7eb2e8f9f7	2680	return HAL_OK;
<>	144:ef7eb2e8f9f7	2681	}
<>	144:ef7eb2e8f9f7	2682	else
<>	144:ef7eb2e8f9f7	2683	{
<>	144:ef7eb2e8f9f7	2684	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2685	}
<>	144:ef7eb2e8f9f7	2686	}
<>	144:ef7eb2e8f9f7	2687
<>	144:ef7eb2e8f9f7	2688	/**
<>	144:ef7eb2e8f9f7	2689	* @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	2690	* @note This interface allow to manage repeated start condition when a direction change during transfer
<>	144:ef7eb2e8f9f7	2691	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2692	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2693	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2694	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2695	* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
<>	144:ef7eb2e8f9f7	2696	* @retval HAL status
<>	144:ef7eb2e8f9f7	2697	*/
<>	144:ef7eb2e8f9f7	2698	HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size, uint32_t XferOptions)
<>	144:ef7eb2e8f9f7	2699	{
<>	144:ef7eb2e8f9f7	2700	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2701	assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
<>	144:ef7eb2e8f9f7	2702
<>	144:ef7eb2e8f9f7	2703	if(hi2c->State == HAL_I2C_STATE_LISTEN)
<>	144:ef7eb2e8f9f7	2704	{
<>	144:ef7eb2e8f9f7	2705	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	2706	{
<>	144:ef7eb2e8f9f7	2707	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2708	}
<>	144:ef7eb2e8f9f7	2709
<>	144:ef7eb2e8f9f7	2710	/* Disable Interrupts, to prevent preemption during treatment in case of multicall */
<>	144:ef7eb2e8f9f7	2711	I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT \| I2C_XFER_TX_IT);
<>	144:ef7eb2e8f9f7	2712
<>	144:ef7eb2e8f9f7	2713	/* Process Locked */
<>	144:ef7eb2e8f9f7	2714	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2715
<>	144:ef7eb2e8f9f7	2716	hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
<>	144:ef7eb2e8f9f7	2717	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	2718	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2719
<>	144:ef7eb2e8f9f7	2720	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	2721	hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	2722
<>	144:ef7eb2e8f9f7	2723	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	2724	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	2725	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2726	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	2727	hi2c->XferOptions = XferOptions;
<>	144:ef7eb2e8f9f7	2728	hi2c->XferISR = I2C_Slave_ISR_IT;
<>	144:ef7eb2e8f9f7	2729
<>	144:ef7eb2e8f9f7	2730	if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
<>	144:ef7eb2e8f9f7	2731	{
<>	144:ef7eb2e8f9f7	2732	/* Clear ADDR flag after prepare the transfer parameters */
<>	144:ef7eb2e8f9f7	2733	/* This action will generate an acknowledge to the Master */
<>	144:ef7eb2e8f9f7	2734	__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
<>	144:ef7eb2e8f9f7	2735	}
<>	144:ef7eb2e8f9f7	2736
<>	144:ef7eb2e8f9f7	2737	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2738	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2739
<>	144:ef7eb2e8f9f7	2740	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	2741	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	2742	process unlock */
<>	144:ef7eb2e8f9f7	2743	/* REnable ADDR interrupt */
<>	144:ef7eb2e8f9f7	2744	I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT \| I2C_XFER_LISTEN_IT);
<>	144:ef7eb2e8f9f7	2745
<>	144:ef7eb2e8f9f7	2746	return HAL_OK;
<>	144:ef7eb2e8f9f7	2747	}
<>	144:ef7eb2e8f9f7	2748	else
<>	144:ef7eb2e8f9f7	2749	{
<>	144:ef7eb2e8f9f7	2750	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2751	}
<>	144:ef7eb2e8f9f7	2752	}
<>	144:ef7eb2e8f9f7	2753
<>	144:ef7eb2e8f9f7	2754	/**
<>	144:ef7eb2e8f9f7	2755	* @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	2756	* @note This interface allow to manage repeated start condition when a direction change during transfer
<>	144:ef7eb2e8f9f7	2757	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2758	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2759	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2760	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2761	* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
<>	144:ef7eb2e8f9f7	2762	* @retval HAL status
<>	144:ef7eb2e8f9f7	2763	*/
<>	144:ef7eb2e8f9f7	2764	HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size, uint32_t XferOptions)
<>	144:ef7eb2e8f9f7	2765	{
<>	144:ef7eb2e8f9f7	2766	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2767	assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
<>	144:ef7eb2e8f9f7	2768
<>	144:ef7eb2e8f9f7	2769	if(hi2c->State == HAL_I2C_STATE_LISTEN)
<>	144:ef7eb2e8f9f7	2770	{
<>	144:ef7eb2e8f9f7	2771	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	2772	{
<>	144:ef7eb2e8f9f7	2773	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2774	}
<>	144:ef7eb2e8f9f7	2775
<>	144:ef7eb2e8f9f7	2776	/* Disable Interrupts, to prevent preemption during treatment in case of multicall */
<>	144:ef7eb2e8f9f7	2777	I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT \| I2C_XFER_RX_IT);
<>	144:ef7eb2e8f9f7	2778
<>	144:ef7eb2e8f9f7	2779	/* Process Locked */
<>	144:ef7eb2e8f9f7	2780	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2781
<>	144:ef7eb2e8f9f7	2782	hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
<>	144:ef7eb2e8f9f7	2783	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	2784	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2785
<>	144:ef7eb2e8f9f7	2786	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	2787	hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	2788
<>	144:ef7eb2e8f9f7	2789	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	2790	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	2791	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2792	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	2793	hi2c->XferOptions = XferOptions;
<>	144:ef7eb2e8f9f7	2794	hi2c->XferISR = I2C_Slave_ISR_IT;
<>	144:ef7eb2e8f9f7	2795
<>	144:ef7eb2e8f9f7	2796	if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
<>	144:ef7eb2e8f9f7	2797	{
<>	144:ef7eb2e8f9f7	2798	/* Clear ADDR flag after prepare the transfer parameters */
<>	144:ef7eb2e8f9f7	2799	/* This action will generate an acknowledge to the Master */
<>	144:ef7eb2e8f9f7	2800	__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
<>	144:ef7eb2e8f9f7	2801	}
<>	144:ef7eb2e8f9f7	2802
<>	144:ef7eb2e8f9f7	2803	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2804	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2805
<>	144:ef7eb2e8f9f7	2806	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	2807	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	2808	process unlock */
<>	144:ef7eb2e8f9f7	2809	/* REnable ADDR interrupt */
<>	144:ef7eb2e8f9f7	2810	I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT \| I2C_XFER_LISTEN_IT);
<>	144:ef7eb2e8f9f7	2811
<>	144:ef7eb2e8f9f7	2812	return HAL_OK;
<>	144:ef7eb2e8f9f7	2813	}
<>	144:ef7eb2e8f9f7	2814	else
<>	144:ef7eb2e8f9f7	2815	{
<>	144:ef7eb2e8f9f7	2816	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2817	}
<>	144:ef7eb2e8f9f7	2818	}
<>	144:ef7eb2e8f9f7	2819
<>	144:ef7eb2e8f9f7	2820	/**
<>	144:ef7eb2e8f9f7	2821	* @brief Enable the Address listen mode with Interrupt.
<>	144:ef7eb2e8f9f7	2822	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2823	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2824	* @retval HAL status
<>	144:ef7eb2e8f9f7	2825	*/
<>	144:ef7eb2e8f9f7	2826	HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	2827	{
<>	144:ef7eb2e8f9f7	2828	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2829	{
<>	144:ef7eb2e8f9f7	2830	hi2c->State = HAL_I2C_STATE_LISTEN;
<>	144:ef7eb2e8f9f7	2831	hi2c->XferISR = I2C_Slave_ISR_IT;
<>	144:ef7eb2e8f9f7	2832
<>	144:ef7eb2e8f9f7	2833	/* Enable the Address Match interrupt */
<>	144:ef7eb2e8f9f7	2834	I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
<>	144:ef7eb2e8f9f7	2835
<>	144:ef7eb2e8f9f7	2836	return HAL_OK;
<>	144:ef7eb2e8f9f7	2837	}
<>	144:ef7eb2e8f9f7	2838	else
<>	144:ef7eb2e8f9f7	2839	{
<>	144:ef7eb2e8f9f7	2840	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2841	}
<>	144:ef7eb2e8f9f7	2842	}
<>	144:ef7eb2e8f9f7	2843
<>	144:ef7eb2e8f9f7	2844	/**
<>	144:ef7eb2e8f9f7	2845	* @brief Disable the Address listen mode with Interrupt.
<>	144:ef7eb2e8f9f7	2846	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2847	* the configuration information for the specified I2C
<>	144:ef7eb2e8f9f7	2848	* @retval HAL status
<>	144:ef7eb2e8f9f7	2849	*/
<>	144:ef7eb2e8f9f7	2850	HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	2851	{
<>	144:ef7eb2e8f9f7	2852	/* Declaration of tmp to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	2853	uint32_t tmp;
<>	144:ef7eb2e8f9f7	2854
<>	144:ef7eb2e8f9f7	2855	/* Disable Address listen mode only if a transfer is not ongoing */
<>	144:ef7eb2e8f9f7	2856	if(hi2c->State == HAL_I2C_STATE_LISTEN)
<>	144:ef7eb2e8f9f7	2857	{
<>	144:ef7eb2e8f9f7	2858	tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
<>	144:ef7eb2e8f9f7	2859	hi2c->PreviousState = tmp \| (uint32_t)(hi2c->Mode);
<>	144:ef7eb2e8f9f7	2860	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2861	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	2862	hi2c->XferISR = NULL;
<>	144:ef7eb2e8f9f7	2863
<>	144:ef7eb2e8f9f7	2864	/* Disable the Address Match interrupt */
<>	144:ef7eb2e8f9f7	2865	I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
<>	144:ef7eb2e8f9f7	2866
<>	144:ef7eb2e8f9f7	2867	return HAL_OK;
<>	144:ef7eb2e8f9f7	2868	}
<>	144:ef7eb2e8f9f7	2869	else
<>	144:ef7eb2e8f9f7	2870	{
<>	144:ef7eb2e8f9f7	2871	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2872	}
<>	144:ef7eb2e8f9f7	2873	}
<>	144:ef7eb2e8f9f7	2874
<>	144:ef7eb2e8f9f7	2875	/**
<>	144:ef7eb2e8f9f7	2876	* @brief Abort a master I2C IT or DMA process communication with Interrupt.
<>	144:ef7eb2e8f9f7	2877	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2878	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2879	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	2880	* @retval HAL status
<>	144:ef7eb2e8f9f7	2881	*/
<>	144:ef7eb2e8f9f7	2882	HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
<>	144:ef7eb2e8f9f7	2883	{
<>	144:ef7eb2e8f9f7	2884	if(hi2c->Mode == HAL_I2C_MODE_MASTER)
<>	144:ef7eb2e8f9f7	2885	{
<>	144:ef7eb2e8f9f7	2886	/* Process Locked */
<>	144:ef7eb2e8f9f7	2887	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2888
<>	144:ef7eb2e8f9f7	2889	/* Disable Interrupts */
<>	144:ef7eb2e8f9f7	2890	I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
<>	144:ef7eb2e8f9f7	2891	I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
<>	144:ef7eb2e8f9f7	2892
<>	144:ef7eb2e8f9f7	2893	/* Set State at HAL_I2C_STATE_ABORT */
<>	144:ef7eb2e8f9f7	2894	hi2c->State = HAL_I2C_STATE_ABORT;
<>	144:ef7eb2e8f9f7	2895
<>	144:ef7eb2e8f9f7	2896	/* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
<>	144:ef7eb2e8f9f7	2897	/* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
<>	144:ef7eb2e8f9f7	2898	I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
<>	144:ef7eb2e8f9f7	2899
<>	144:ef7eb2e8f9f7	2900	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2901	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2902
<>	144:ef7eb2e8f9f7	2903	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	2904	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	2905	process unlock */
<>	144:ef7eb2e8f9f7	2906	I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
<>	144:ef7eb2e8f9f7	2907
<>	144:ef7eb2e8f9f7	2908	return HAL_OK;
<>	144:ef7eb2e8f9f7	2909	}
<>	144:ef7eb2e8f9f7	2910	else
<>	144:ef7eb2e8f9f7	2911	{
<>	144:ef7eb2e8f9f7	2912	/* Wrong usage of abort function */
<>	144:ef7eb2e8f9f7	2913	/* This function should be used only in case of abort monitored by master device */
<>	144:ef7eb2e8f9f7	2914	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2915	}
<>	144:ef7eb2e8f9f7	2916	}
<>	144:ef7eb2e8f9f7	2917
<>	144:ef7eb2e8f9f7	2918	/**
<>	144:ef7eb2e8f9f7	2919	* @}
<>	144:ef7eb2e8f9f7	2920	*/
<>	144:ef7eb2e8f9f7	2921
<>	144:ef7eb2e8f9f7	2922	/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
<>	144:ef7eb2e8f9f7	2923	* @{
<>	144:ef7eb2e8f9f7	2924	*/
<>	144:ef7eb2e8f9f7	2925
<>	144:ef7eb2e8f9f7	2926	/**
<>	144:ef7eb2e8f9f7	2927	* @brief This function handles I2C event interrupt request.
<>	144:ef7eb2e8f9f7	2928	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2929	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2930	* @retval None
<>	144:ef7eb2e8f9f7	2931	*/
<>	144:ef7eb2e8f9f7	2932	void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	2933	{
<>	144:ef7eb2e8f9f7	2934	/* Get current IT Flags and IT sources value */
<>	144:ef7eb2e8f9f7	2935	uint32_t itflags = READ_REG(hi2c->Instance->ISR);
<>	144:ef7eb2e8f9f7	2936	uint32_t itsources = READ_REG(hi2c->Instance->CR1);
<>	144:ef7eb2e8f9f7	2937
<>	144:ef7eb2e8f9f7	2938	/* I2C events treatment -------------------------------------*/
<>	144:ef7eb2e8f9f7	2939	if(hi2c->XferISR != NULL)
<>	144:ef7eb2e8f9f7	2940	{
<>	144:ef7eb2e8f9f7	2941	hi2c->XferISR(hi2c, itflags, itsources);
<>	144:ef7eb2e8f9f7	2942	}
<>	144:ef7eb2e8f9f7	2943	}
<>	144:ef7eb2e8f9f7	2944
<>	144:ef7eb2e8f9f7	2945	/**
<>	144:ef7eb2e8f9f7	2946	* @brief This function handles I2C error interrupt request.
<>	144:ef7eb2e8f9f7	2947	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2948	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2949	* @retval None
<>	144:ef7eb2e8f9f7	2950	*/
<>	144:ef7eb2e8f9f7	2951	void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	2952	{
<>	144:ef7eb2e8f9f7	2953	uint32_t itflags = READ_REG(hi2c->Instance->ISR);
<>	144:ef7eb2e8f9f7	2954	uint32_t itsources = READ_REG(hi2c->Instance->CR1);
<>	144:ef7eb2e8f9f7	2955
<>	144:ef7eb2e8f9f7	2956	/* I2C Bus error interrupt occurred ------------------------------------*/
<>	144:ef7eb2e8f9f7	2957	if(((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
<>	144:ef7eb2e8f9f7	2958	{
<>	144:ef7eb2e8f9f7	2959	hi2c->ErrorCode \|= HAL_I2C_ERROR_BERR;
<>	144:ef7eb2e8f9f7	2960
<>	144:ef7eb2e8f9f7	2961	/* Clear BERR flag */
<>	144:ef7eb2e8f9f7	2962	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
<>	144:ef7eb2e8f9f7	2963	}
<>	144:ef7eb2e8f9f7	2964
<>	144:ef7eb2e8f9f7	2965	/* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
<>	144:ef7eb2e8f9f7	2966	if(((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
<>	144:ef7eb2e8f9f7	2967	{
<>	144:ef7eb2e8f9f7	2968	hi2c->ErrorCode \|= HAL_I2C_ERROR_OVR;
<>	144:ef7eb2e8f9f7	2969
<>	144:ef7eb2e8f9f7	2970	/* Clear OVR flag */
<>	144:ef7eb2e8f9f7	2971	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
<>	144:ef7eb2e8f9f7	2972	}
<>	144:ef7eb2e8f9f7	2973
<>	144:ef7eb2e8f9f7	2974	/* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
<>	144:ef7eb2e8f9f7	2975	if(((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
<>	144:ef7eb2e8f9f7	2976	{
<>	144:ef7eb2e8f9f7	2977	hi2c->ErrorCode \|= HAL_I2C_ERROR_ARLO;
<>	144:ef7eb2e8f9f7	2978
<>	144:ef7eb2e8f9f7	2979	/* Clear ARLO flag */
<>	144:ef7eb2e8f9f7	2980	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
<>	144:ef7eb2e8f9f7	2981	}
<>	144:ef7eb2e8f9f7	2982
<>	144:ef7eb2e8f9f7	2983	/* Call the Error Callback in case of Error detected */
<>	144:ef7eb2e8f9f7	2984	if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR \| HAL_I2C_ERROR_OVR \| HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
<>	144:ef7eb2e8f9f7	2985	{
<>	144:ef7eb2e8f9f7	2986	I2C_ITError(hi2c, hi2c->ErrorCode);
<>	144:ef7eb2e8f9f7	2987	}
<>	144:ef7eb2e8f9f7	2988	}
<>	144:ef7eb2e8f9f7	2989
<>	144:ef7eb2e8f9f7	2990	/**
<>	144:ef7eb2e8f9f7	2991	* @brief Master Tx Transfer completed callback.
<>	144:ef7eb2e8f9f7	2992	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2993	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2994	* @retval None
<>	144:ef7eb2e8f9f7	2995	*/
<>	144:ef7eb2e8f9f7	2996	__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	2997	{
<>	144:ef7eb2e8f9f7	2998	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2999	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3000
<>	144:ef7eb2e8f9f7	3001	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3002	the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	3003	*/
<>	144:ef7eb2e8f9f7	3004	}
<>	144:ef7eb2e8f9f7	3005
<>	144:ef7eb2e8f9f7	3006	/**
<>	144:ef7eb2e8f9f7	3007	* @brief Master Rx Transfer completed callback.
<>	144:ef7eb2e8f9f7	3008	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3009	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3010	* @retval None
<>	144:ef7eb2e8f9f7	3011	*/
<>	144:ef7eb2e8f9f7	3012	__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3013	{
<>	144:ef7eb2e8f9f7	3014	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3015	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3016
<>	144:ef7eb2e8f9f7	3017	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3018	the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	3019	*/
<>	144:ef7eb2e8f9f7	3020	}
<>	144:ef7eb2e8f9f7	3021
<>	144:ef7eb2e8f9f7	3022	/** @brief Slave Tx Transfer completed callback.
<>	144:ef7eb2e8f9f7	3023	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3024	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3025	* @retval None
<>	144:ef7eb2e8f9f7	3026	*/
<>	144:ef7eb2e8f9f7	3027	__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3028	{
<>	144:ef7eb2e8f9f7	3029	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3030	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3031
<>	144:ef7eb2e8f9f7	3032	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3033	the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	3034	*/
<>	144:ef7eb2e8f9f7	3035	}
<>	144:ef7eb2e8f9f7	3036
<>	144:ef7eb2e8f9f7	3037	/**
<>	144:ef7eb2e8f9f7	3038	* @brief Slave Rx Transfer completed callback.
<>	144:ef7eb2e8f9f7	3039	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3040	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3041	* @retval None
<>	144:ef7eb2e8f9f7	3042	*/
<>	144:ef7eb2e8f9f7	3043	__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3044	{
<>	144:ef7eb2e8f9f7	3045	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3046	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3047
<>	144:ef7eb2e8f9f7	3048	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3049	the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	3050	*/
<>	144:ef7eb2e8f9f7	3051	}
<>	144:ef7eb2e8f9f7	3052
<>	144:ef7eb2e8f9f7	3053	/**
<>	144:ef7eb2e8f9f7	3054	* @brief Slave Address Match callback.
<>	144:ef7eb2e8f9f7	3055	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3056	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3057	* @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFEROPTIONS
<>	144:ef7eb2e8f9f7	3058	* @param AddrMatchCode: Address Match Code
<>	144:ef7eb2e8f9f7	3059	* @retval None
<>	144:ef7eb2e8f9f7	3060	*/
<>	144:ef7eb2e8f9f7	3061	__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
<>	144:ef7eb2e8f9f7	3062	{
<>	144:ef7eb2e8f9f7	3063	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3064	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3065	UNUSED(TransferDirection);
<>	144:ef7eb2e8f9f7	3066	UNUSED(AddrMatchCode);
<>	144:ef7eb2e8f9f7	3067
<>	144:ef7eb2e8f9f7	3068	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3069	the HAL_I2C_AddrCallback() could be implemented in the user file
<>	144:ef7eb2e8f9f7	3070	*/
<>	144:ef7eb2e8f9f7	3071	}
<>	144:ef7eb2e8f9f7	3072
<>	144:ef7eb2e8f9f7	3073	/**
<>	144:ef7eb2e8f9f7	3074	* @brief Listen Complete callback.
<>	144:ef7eb2e8f9f7	3075	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3076	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3077	* @retval None
<>	144:ef7eb2e8f9f7	3078	*/
<>	144:ef7eb2e8f9f7	3079	__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3080	{
<>	144:ef7eb2e8f9f7	3081	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3082	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3083
<>	144:ef7eb2e8f9f7	3084	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3085	the HAL_I2C_ListenCpltCallback() could be implemented in the user file
<>	144:ef7eb2e8f9f7	3086	*/
<>	144:ef7eb2e8f9f7	3087	}
<>	144:ef7eb2e8f9f7	3088
<>	144:ef7eb2e8f9f7	3089	/**
<>	144:ef7eb2e8f9f7	3090	* @brief Memory Tx Transfer completed callback.
<>	144:ef7eb2e8f9f7	3091	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3092	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3093	* @retval None
<>	144:ef7eb2e8f9f7	3094	*/
<>	144:ef7eb2e8f9f7	3095	__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3096	{
<>	144:ef7eb2e8f9f7	3097	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3098	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3099
<>	144:ef7eb2e8f9f7	3100	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3101	the HAL_I2C_MemTxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	3102	*/
<>	144:ef7eb2e8f9f7	3103	}
<>	144:ef7eb2e8f9f7	3104
<>	144:ef7eb2e8f9f7	3105	/**
<>	144:ef7eb2e8f9f7	3106	* @brief Memory Rx Transfer completed callback.
<>	144:ef7eb2e8f9f7	3107	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3108	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3109	* @retval None
<>	144:ef7eb2e8f9f7	3110	*/
<>	144:ef7eb2e8f9f7	3111	__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3112	{
<>	144:ef7eb2e8f9f7	3113	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3114	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3115
<>	144:ef7eb2e8f9f7	3116	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3117	the HAL_I2C_MemRxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	3118	*/
<>	144:ef7eb2e8f9f7	3119	}
<>	144:ef7eb2e8f9f7	3120
<>	144:ef7eb2e8f9f7	3121	/**
<>	144:ef7eb2e8f9f7	3122	* @brief I2C error callback.
<>	144:ef7eb2e8f9f7	3123	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3124	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3125	* @retval None
<>	144:ef7eb2e8f9f7	3126	*/
<>	144:ef7eb2e8f9f7	3127	__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3128	{
<>	144:ef7eb2e8f9f7	3129	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3130	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3131
<>	144:ef7eb2e8f9f7	3132	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3133	the HAL_I2C_ErrorCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	3134	*/
<>	144:ef7eb2e8f9f7	3135	}
<>	144:ef7eb2e8f9f7	3136
<>	144:ef7eb2e8f9f7	3137	/**
<>	144:ef7eb2e8f9f7	3138	* @brief I2C abort callback.
<>	144:ef7eb2e8f9f7	3139	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3140	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3141	* @retval None
<>	144:ef7eb2e8f9f7	3142	*/
<>	144:ef7eb2e8f9f7	3143	__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3144	{
<>	144:ef7eb2e8f9f7	3145	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3146	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3147
<>	144:ef7eb2e8f9f7	3148	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3149	the HAL_I2C_AbortCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	3150	*/
<>	144:ef7eb2e8f9f7	3151	}
<>	144:ef7eb2e8f9f7	3152
<>	144:ef7eb2e8f9f7	3153	/**
<>	144:ef7eb2e8f9f7	3154	* @}
<>	144:ef7eb2e8f9f7	3155	*/
<>	144:ef7eb2e8f9f7	3156
<>	144:ef7eb2e8f9f7	3157	/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
<>	144:ef7eb2e8f9f7	3158	* @brief Peripheral State, Mode and Error functions
<>	144:ef7eb2e8f9f7	3159	*
<>	144:ef7eb2e8f9f7	3160	@verbatim
<>	144:ef7eb2e8f9f7	3161	===============================================================================
<>	144:ef7eb2e8f9f7	3162	##### Peripheral State, Mode and Error functions #####
<>	144:ef7eb2e8f9f7	3163	===============================================================================
<>	144:ef7eb2e8f9f7	3164	[..]
<>	144:ef7eb2e8f9f7	3165	This subsection permit to get in run-time the status of the peripheral
<>	144:ef7eb2e8f9f7	3166	and the data flow.
<>	144:ef7eb2e8f9f7	3167
<>	144:ef7eb2e8f9f7	3168	@endverbatim
<>	144:ef7eb2e8f9f7	3169	* @{
<>	144:ef7eb2e8f9f7	3170	*/
<>	144:ef7eb2e8f9f7	3171
<>	144:ef7eb2e8f9f7	3172	/**
<>	144:ef7eb2e8f9f7	3173	* @brief Return the I2C handle state.
<>	144:ef7eb2e8f9f7	3174	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3175	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3176	* @retval HAL state
<>	144:ef7eb2e8f9f7	3177	*/
<>	144:ef7eb2e8f9f7	3178	HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3179	{
<>	144:ef7eb2e8f9f7	3180	/* Return I2C handle state */
<>	144:ef7eb2e8f9f7	3181	return hi2c->State;
<>	144:ef7eb2e8f9f7	3182	}
<>	144:ef7eb2e8f9f7	3183
<>	144:ef7eb2e8f9f7	3184	/**
<>	144:ef7eb2e8f9f7	3185	* @brief Returns the I2C Master, Slave, Memory or no mode.
<>	144:ef7eb2e8f9f7	3186	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3187	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3188	* @retval HAL mode
<>	144:ef7eb2e8f9f7	3189	*/
<>	144:ef7eb2e8f9f7	3190	HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3191	{
<>	144:ef7eb2e8f9f7	3192	return hi2c->Mode;
<>	144:ef7eb2e8f9f7	3193	}
<>	144:ef7eb2e8f9f7	3194
<>	144:ef7eb2e8f9f7	3195	/**
<>	144:ef7eb2e8f9f7	3196	* @brief Return the I2C error code.
<>	144:ef7eb2e8f9f7	3197	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3198	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3199	* @retval I2C Error Code
<>	144:ef7eb2e8f9f7	3200	*/
<>	144:ef7eb2e8f9f7	3201	uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3202	{
<>	144:ef7eb2e8f9f7	3203	return hi2c->ErrorCode;
<>	144:ef7eb2e8f9f7	3204	}
<>	144:ef7eb2e8f9f7	3205
<>	144:ef7eb2e8f9f7	3206	/**
<>	144:ef7eb2e8f9f7	3207	* @}
<>	144:ef7eb2e8f9f7	3208	*/
<>	144:ef7eb2e8f9f7	3209
<>	144:ef7eb2e8f9f7	3210	/**
<>	144:ef7eb2e8f9f7	3211	* @}
<>	144:ef7eb2e8f9f7	3212	*/
<>	144:ef7eb2e8f9f7	3213
<>	144:ef7eb2e8f9f7	3214	/** @addtogroup I2C_Private_Functions
<>	144:ef7eb2e8f9f7	3215	* @{
<>	144:ef7eb2e8f9f7	3216	*/
<>	144:ef7eb2e8f9f7	3217
<>	144:ef7eb2e8f9f7	3218	/**
<>	144:ef7eb2e8f9f7	3219	* @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
<>	144:ef7eb2e8f9f7	3220	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3221	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3222	* @param ITFlags Interrupt flags to handle.
<>	144:ef7eb2e8f9f7	3223	* @param ITSources Interrupt sources enabled.
<>	144:ef7eb2e8f9f7	3224	* @retval HAL status
<>	144:ef7eb2e8f9f7	3225	*/
<>	144:ef7eb2e8f9f7	3226	static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
<>	144:ef7eb2e8f9f7	3227	{
<>	144:ef7eb2e8f9f7	3228	uint16_t devaddress = 0U;
<>	144:ef7eb2e8f9f7	3229
<>	144:ef7eb2e8f9f7	3230	/* Process Locked */
<>	144:ef7eb2e8f9f7	3231	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	3232
<>	144:ef7eb2e8f9f7	3233	if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
<>	144:ef7eb2e8f9f7	3234	{
<>	144:ef7eb2e8f9f7	3235	/* Clear NACK Flag */
<>	144:ef7eb2e8f9f7	3236	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	3237
<>	144:ef7eb2e8f9f7	3238	/* Set corresponding Error Code */
<>	144:ef7eb2e8f9f7	3239	/* No need to generate STOP, it is automatically done */
<>	144:ef7eb2e8f9f7	3240	/* Error callback will be send during stop flag treatment */
<>	144:ef7eb2e8f9f7	3241	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	3242
<>	144:ef7eb2e8f9f7	3243	/* Flush TX register */
<>	144:ef7eb2e8f9f7	3244	I2C_Flush_TXDR(hi2c);
<>	144:ef7eb2e8f9f7	3245	}
<>	144:ef7eb2e8f9f7	3246	else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
<>	144:ef7eb2e8f9f7	3247	{
<>	144:ef7eb2e8f9f7	3248	/* Read data from RXDR */
<>	144:ef7eb2e8f9f7	3249	(*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
<>	144:ef7eb2e8f9f7	3250	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	3251	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	3252	}
<>	144:ef7eb2e8f9f7	3253	else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
<>	144:ef7eb2e8f9f7	3254	{
<>	144:ef7eb2e8f9f7	3255	/* Write data to TXDR */
<>	144:ef7eb2e8f9f7	3256	hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	3257	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	3258	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	3259	}
<>	144:ef7eb2e8f9f7	3260	else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
<>	144:ef7eb2e8f9f7	3261	{
<>	144:ef7eb2e8f9f7	3262	if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
<>	144:ef7eb2e8f9f7	3263	{
<>	144:ef7eb2e8f9f7	3264	devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
<>	144:ef7eb2e8f9f7	3265
<>	144:ef7eb2e8f9f7	3266	if(hi2c->XferCount > MAX_NBYTE_SIZE)
<>	144:ef7eb2e8f9f7	3267	{
<>	144:ef7eb2e8f9f7	3268	hi2c->XferSize = MAX_NBYTE_SIZE;
<>	144:ef7eb2e8f9f7	3269	I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	3270	}
<>	144:ef7eb2e8f9f7	3271	else
<>	144:ef7eb2e8f9f7	3272	{
<>	144:ef7eb2e8f9f7	3273	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	3274	if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
<>	144:ef7eb2e8f9f7	3275	{
<>	144:ef7eb2e8f9f7	3276	I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	3277	}
<>	144:ef7eb2e8f9f7	3278	else
<>	144:ef7eb2e8f9f7	3279	{
<>	144:ef7eb2e8f9f7	3280	I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	3281	}
<>	144:ef7eb2e8f9f7	3282	}
<>	144:ef7eb2e8f9f7	3283	}
<>	144:ef7eb2e8f9f7	3284	else
<>	144:ef7eb2e8f9f7	3285	{
<>	144:ef7eb2e8f9f7	3286	/* Call TxCpltCallback() if no stop mode is set */
<>	144:ef7eb2e8f9f7	3287	if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
<>	144:ef7eb2e8f9f7	3288	{
<>	144:ef7eb2e8f9f7	3289	/* Call I2C Master Sequential complete process */
<>	144:ef7eb2e8f9f7	3290	I2C_ITMasterSequentialCplt(hi2c);
<>	144:ef7eb2e8f9f7	3291	}
<>	144:ef7eb2e8f9f7	3292	else
<>	144:ef7eb2e8f9f7	3293	{
<>	144:ef7eb2e8f9f7	3294	/* Wrong size Status regarding TCR flag event */
<>	144:ef7eb2e8f9f7	3295	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	144:ef7eb2e8f9f7	3296	I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
<>	144:ef7eb2e8f9f7	3297	}
<>	144:ef7eb2e8f9f7	3298	}
<>	144:ef7eb2e8f9f7	3299	}
<>	144:ef7eb2e8f9f7	3300	else if(((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
<>	144:ef7eb2e8f9f7	3301	{
<>	144:ef7eb2e8f9f7	3302	if(hi2c->XferCount == 0U)
<>	144:ef7eb2e8f9f7	3303	{
<>	144:ef7eb2e8f9f7	3304	if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
<>	144:ef7eb2e8f9f7	3305	{
<>	144:ef7eb2e8f9f7	3306	/* Generate a stop condition in case of no transfer option */
<>	144:ef7eb2e8f9f7	3307	if(hi2c->XferOptions == I2C_NO_OPTION_FRAME)
<>	144:ef7eb2e8f9f7	3308	{
<>	144:ef7eb2e8f9f7	3309	/* Generate Stop */
<>	144:ef7eb2e8f9f7	3310	hi2c->Instance->CR2 \|= I2C_CR2_STOP;
<>	144:ef7eb2e8f9f7	3311	}
<>	144:ef7eb2e8f9f7	3312	else
<>	144:ef7eb2e8f9f7	3313	{
<>	144:ef7eb2e8f9f7	3314	/* Call I2C Master Sequential complete process */
<>	144:ef7eb2e8f9f7	3315	I2C_ITMasterSequentialCplt(hi2c);
<>	144:ef7eb2e8f9f7	3316	}
<>	144:ef7eb2e8f9f7	3317	}
<>	144:ef7eb2e8f9f7	3318	}
<>	144:ef7eb2e8f9f7	3319	else
<>	144:ef7eb2e8f9f7	3320	{
<>	144:ef7eb2e8f9f7	3321	/* Wrong size Status regarding TC flag event */
<>	144:ef7eb2e8f9f7	3322	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	144:ef7eb2e8f9f7	3323	I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
<>	144:ef7eb2e8f9f7	3324	}
<>	144:ef7eb2e8f9f7	3325	}
<>	144:ef7eb2e8f9f7	3326
<>	144:ef7eb2e8f9f7	3327	if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
<>	144:ef7eb2e8f9f7	3328	{
<>	144:ef7eb2e8f9f7	3329	/* Call I2C Master complete process */
<>	144:ef7eb2e8f9f7	3330	I2C_ITMasterCplt(hi2c, ITFlags);
<>	144:ef7eb2e8f9f7	3331	}
<>	144:ef7eb2e8f9f7	3332
<>	144:ef7eb2e8f9f7	3333	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3334	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3335
<>	144:ef7eb2e8f9f7	3336	return HAL_OK;
<>	144:ef7eb2e8f9f7	3337	}
<>	144:ef7eb2e8f9f7	3338
<>	144:ef7eb2e8f9f7	3339	/**
<>	144:ef7eb2e8f9f7	3340	* @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
<>	144:ef7eb2e8f9f7	3341	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3342	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3343	* @param ITFlags Interrupt flags to handle.
<>	144:ef7eb2e8f9f7	3344	* @param ITSources Interrupt sources enabled.
<>	144:ef7eb2e8f9f7	3345	* @retval HAL status
<>	144:ef7eb2e8f9f7	3346	*/
<>	144:ef7eb2e8f9f7	3347	static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
<>	144:ef7eb2e8f9f7	3348	{
<>	144:ef7eb2e8f9f7	3349	/* Process locked */
<>	144:ef7eb2e8f9f7	3350	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	3351
<>	144:ef7eb2e8f9f7	3352	if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
<>	144:ef7eb2e8f9f7	3353	{
<>	144:ef7eb2e8f9f7	3354	/* Check that I2C transfer finished */
<>	144:ef7eb2e8f9f7	3355	/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
<>	144:ef7eb2e8f9f7	3356	/* Mean XferCount == 0*/
<>	144:ef7eb2e8f9f7	3357	/* So clear Flag NACKF only */
<>	144:ef7eb2e8f9f7	3358	if(hi2c->XferCount == 0U)
<>	144:ef7eb2e8f9f7	3359	{
<>	144:ef7eb2e8f9f7	3360	if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (hi2c->XferOptions == I2C_LAST_FRAME)) && \
<>	144:ef7eb2e8f9f7	3361	(hi2c->State == HAL_I2C_STATE_LISTEN))
<>	144:ef7eb2e8f9f7	3362	{
<>	144:ef7eb2e8f9f7	3363	/* Call I2C Listen complete process */
<>	144:ef7eb2e8f9f7	3364	I2C_ITListenCplt(hi2c, ITFlags);
<>	144:ef7eb2e8f9f7	3365	}
<>	144:ef7eb2e8f9f7	3366	else if((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
<>	144:ef7eb2e8f9f7	3367	{
<>	144:ef7eb2e8f9f7	3368	/* Clear NACK Flag */
<>	144:ef7eb2e8f9f7	3369	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	3370
<>	144:ef7eb2e8f9f7	3371	/* Flush TX register */
<>	144:ef7eb2e8f9f7	3372	I2C_Flush_TXDR(hi2c);
<>	144:ef7eb2e8f9f7	3373
<>	144:ef7eb2e8f9f7	3374	/* Last Byte is Transmitted */
<>	144:ef7eb2e8f9f7	3375	/* Call I2C Slave Sequential complete process */
<>	144:ef7eb2e8f9f7	3376	I2C_ITSlaveSequentialCplt(hi2c);
<>	144:ef7eb2e8f9f7	3377	}
<>	144:ef7eb2e8f9f7	3378	else
<>	144:ef7eb2e8f9f7	3379	{
<>	144:ef7eb2e8f9f7	3380	/* Clear NACK Flag */
<>	144:ef7eb2e8f9f7	3381	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	3382	}
<>	144:ef7eb2e8f9f7	3383	}
<>	144:ef7eb2e8f9f7	3384	else
<>	144:ef7eb2e8f9f7	3385	{
<>	144:ef7eb2e8f9f7	3386	/* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
<>	144:ef7eb2e8f9f7	3387	/* Clear NACK Flag */
<>	144:ef7eb2e8f9f7	3388	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	3389
<>	144:ef7eb2e8f9f7	3390	/* Set ErrorCode corresponding to a Non-Acknowledge */
<>	144:ef7eb2e8f9f7	3391	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	3392	}
<>	144:ef7eb2e8f9f7	3393	}
<>	144:ef7eb2e8f9f7	3394	else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
<>	144:ef7eb2e8f9f7	3395	{
<>	144:ef7eb2e8f9f7	3396	if(hi2c->XferCount > 0U)
<>	144:ef7eb2e8f9f7	3397	{
<>	144:ef7eb2e8f9f7	3398	/* Read data from RXDR */
<>	144:ef7eb2e8f9f7	3399	(*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
<>	144:ef7eb2e8f9f7	3400	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	3401	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	3402	}
<>	144:ef7eb2e8f9f7	3403
<>	144:ef7eb2e8f9f7	3404	if((hi2c->XferCount == 0U) && \
<>	144:ef7eb2e8f9f7	3405	(hi2c->XferOptions != I2C_NO_OPTION_FRAME))
<>	144:ef7eb2e8f9f7	3406	{
<>	144:ef7eb2e8f9f7	3407	/* Call I2C Slave Sequential complete process */
<>	144:ef7eb2e8f9f7	3408	I2C_ITSlaveSequentialCplt(hi2c);
<>	144:ef7eb2e8f9f7	3409	}
<>	144:ef7eb2e8f9f7	3410	}
<>	144:ef7eb2e8f9f7	3411	else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
<>	144:ef7eb2e8f9f7	3412	{
<>	144:ef7eb2e8f9f7	3413	I2C_ITAddrCplt(hi2c, ITFlags);
<>	144:ef7eb2e8f9f7	3414	}
<>	144:ef7eb2e8f9f7	3415	else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
<>	144:ef7eb2e8f9f7	3416	{
<>	144:ef7eb2e8f9f7	3417	/* Write data to TXDR only if XferCount not reach "0" */
<>	144:ef7eb2e8f9f7	3418	/* A TXIS flag can be set, during STOP treatment */
<>	144:ef7eb2e8f9f7	3419	/* Check if all Datas have already been sent */
<>	144:ef7eb2e8f9f7	3420	/* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
<>	144:ef7eb2e8f9f7	3421	if(hi2c->XferCount > 0U)
<>	144:ef7eb2e8f9f7	3422	{
<>	144:ef7eb2e8f9f7	3423	/* Write data to TXDR */
<>	144:ef7eb2e8f9f7	3424	hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	3425	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	3426	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	3427	}
<>	144:ef7eb2e8f9f7	3428	else
<>	144:ef7eb2e8f9f7	3429	{
<>	144:ef7eb2e8f9f7	3430	if((hi2c->XferOptions == I2C_NEXT_FRAME) \|\| (hi2c->XferOptions == I2C_FIRST_FRAME))
<>	144:ef7eb2e8f9f7	3431	{
<>	144:ef7eb2e8f9f7	3432	/* Last Byte is Transmitted */
<>	144:ef7eb2e8f9f7	3433	/* Call I2C Slave Sequential complete process */
<>	144:ef7eb2e8f9f7	3434	I2C_ITSlaveSequentialCplt(hi2c);
<>	144:ef7eb2e8f9f7	3435	}
<>	144:ef7eb2e8f9f7	3436	}
<>	144:ef7eb2e8f9f7	3437	}
<>	144:ef7eb2e8f9f7	3438
<>	144:ef7eb2e8f9f7	3439	/* Check if STOPF is set */
<>	144:ef7eb2e8f9f7	3440	if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
<>	144:ef7eb2e8f9f7	3441	{
<>	144:ef7eb2e8f9f7	3442	/* Call I2C Slave complete process */
<>	144:ef7eb2e8f9f7	3443	I2C_ITSlaveCplt(hi2c, ITFlags);
<>	144:ef7eb2e8f9f7	3444	}
<>	144:ef7eb2e8f9f7	3445
<>	144:ef7eb2e8f9f7	3446	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3447	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3448
<>	144:ef7eb2e8f9f7	3449	return HAL_OK;
<>	144:ef7eb2e8f9f7	3450	}
<>	144:ef7eb2e8f9f7	3451
<>	144:ef7eb2e8f9f7	3452	/**
<>	144:ef7eb2e8f9f7	3453	* @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
<>	144:ef7eb2e8f9f7	3454	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3455	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3456	* @param ITFlags Interrupt flags to handle.
<>	144:ef7eb2e8f9f7	3457	* @param ITSources Interrupt sources enabled.
<>	144:ef7eb2e8f9f7	3458	* @retval HAL status
<>	144:ef7eb2e8f9f7	3459	*/
<>	144:ef7eb2e8f9f7	3460	static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
<>	144:ef7eb2e8f9f7	3461	{
<>	144:ef7eb2e8f9f7	3462	uint16_t devaddress = 0U;
<>	144:ef7eb2e8f9f7	3463	uint32_t xfermode = 0U;
<>	144:ef7eb2e8f9f7	3464
<>	144:ef7eb2e8f9f7	3465	/* Process Locked */
<>	144:ef7eb2e8f9f7	3466	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	3467
<>	144:ef7eb2e8f9f7	3468	if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
<>	144:ef7eb2e8f9f7	3469	{
<>	144:ef7eb2e8f9f7	3470	/* Clear NACK Flag */
<>	144:ef7eb2e8f9f7	3471	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	3472
<>	144:ef7eb2e8f9f7	3473	/* Set corresponding Error Code */
<>	144:ef7eb2e8f9f7	3474	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	3475
<>	144:ef7eb2e8f9f7	3476	/* No need to generate STOP, it is automatically done */
<>	144:ef7eb2e8f9f7	3477	/* But enable STOP interrupt, to treat it */
<>	144:ef7eb2e8f9f7	3478	/* Error callback will be send during stop flag treatment */
<>	144:ef7eb2e8f9f7	3479	I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
<>	144:ef7eb2e8f9f7	3480
<>	144:ef7eb2e8f9f7	3481	/* Flush TX register */
<>	144:ef7eb2e8f9f7	3482	I2C_Flush_TXDR(hi2c);
<>	144:ef7eb2e8f9f7	3483	}
<>	144:ef7eb2e8f9f7	3484	else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
<>	144:ef7eb2e8f9f7	3485	{
<>	144:ef7eb2e8f9f7	3486	/* Disable TC interrupt */
<>	144:ef7eb2e8f9f7	3487	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
<>	144:ef7eb2e8f9f7	3488
<>	144:ef7eb2e8f9f7	3489	if(hi2c->XferCount != 0U)
<>	144:ef7eb2e8f9f7	3490	{
<>	144:ef7eb2e8f9f7	3491	/* Recover Slave address */
<>	144:ef7eb2e8f9f7	3492	devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
<>	144:ef7eb2e8f9f7	3493
<>	144:ef7eb2e8f9f7	3494	/* Prepare the new XferSize to transfer */
<>	144:ef7eb2e8f9f7	3495	if(hi2c->XferCount > MAX_NBYTE_SIZE)
<>	144:ef7eb2e8f9f7	3496	{
<>	144:ef7eb2e8f9f7	3497	hi2c->XferSize = MAX_NBYTE_SIZE;
<>	144:ef7eb2e8f9f7	3498	xfermode = I2C_RELOAD_MODE;
<>	144:ef7eb2e8f9f7	3499	}
<>	144:ef7eb2e8f9f7	3500	else
<>	144:ef7eb2e8f9f7	3501	{
<>	144:ef7eb2e8f9f7	3502	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	3503	xfermode = I2C_AUTOEND_MODE;
<>	144:ef7eb2e8f9f7	3504	}
<>	144:ef7eb2e8f9f7	3505
<>	144:ef7eb2e8f9f7	3506	/* Set the new XferSize in Nbytes register */
<>	144:ef7eb2e8f9f7	3507	I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	3508
<>	144:ef7eb2e8f9f7	3509	/* Update XferCount value */
<>	144:ef7eb2e8f9f7	3510	hi2c->XferCount -= hi2c->XferSize;
<>	144:ef7eb2e8f9f7	3511
<>	144:ef7eb2e8f9f7	3512	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	3513	if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	3514	{
<>	144:ef7eb2e8f9f7	3515	hi2c->Instance->CR1 \|= I2C_CR1_RXDMAEN;
<>	144:ef7eb2e8f9f7	3516	}
<>	144:ef7eb2e8f9f7	3517	else
<>	144:ef7eb2e8f9f7	3518	{
<>	144:ef7eb2e8f9f7	3519	hi2c->Instance->CR1 \|= I2C_CR1_TXDMAEN;
<>	144:ef7eb2e8f9f7	3520	}
<>	144:ef7eb2e8f9f7	3521	}
<>	144:ef7eb2e8f9f7	3522	else
<>	144:ef7eb2e8f9f7	3523	{
<>	144:ef7eb2e8f9f7	3524	/* Wrong size Status regarding TCR flag event */
<>	144:ef7eb2e8f9f7	3525	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	144:ef7eb2e8f9f7	3526	I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
<>	144:ef7eb2e8f9f7	3527	}
<>	144:ef7eb2e8f9f7	3528	}
<>	144:ef7eb2e8f9f7	3529	else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
<>	144:ef7eb2e8f9f7	3530	{
<>	144:ef7eb2e8f9f7	3531	/* Call I2C Master complete process */
<>	144:ef7eb2e8f9f7	3532	I2C_ITMasterCplt(hi2c, ITFlags);
<>	144:ef7eb2e8f9f7	3533	}
<>	144:ef7eb2e8f9f7	3534
<>	144:ef7eb2e8f9f7	3535	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3536	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3537
<>	144:ef7eb2e8f9f7	3538	return HAL_OK;
<>	144:ef7eb2e8f9f7	3539	}
<>	144:ef7eb2e8f9f7	3540
<>	144:ef7eb2e8f9f7	3541	/**
<>	144:ef7eb2e8f9f7	3542	* @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
<>	144:ef7eb2e8f9f7	3543	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3544	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3545	* @param ITFlags Interrupt flags to handle.
<>	144:ef7eb2e8f9f7	3546	* @param ITSources Interrupt sources enabled.
<>	144:ef7eb2e8f9f7	3547	* @retval HAL status
<>	144:ef7eb2e8f9f7	3548	*/
<>	144:ef7eb2e8f9f7	3549	static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
<>	144:ef7eb2e8f9f7	3550	{
<>	144:ef7eb2e8f9f7	3551	/* Process locked */
<>	144:ef7eb2e8f9f7	3552	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	3553
<>	144:ef7eb2e8f9f7	3554	if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
<>	144:ef7eb2e8f9f7	3555	{
<>	144:ef7eb2e8f9f7	3556	/* Check that I2C transfer finished */
<>	144:ef7eb2e8f9f7	3557	/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
<>	144:ef7eb2e8f9f7	3558	/* Mean XferCount == 0 */
<>	144:ef7eb2e8f9f7	3559	/* So clear Flag NACKF only */
<>	144:ef7eb2e8f9f7	3560	if(I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U)
<>	144:ef7eb2e8f9f7	3561	{
<>	144:ef7eb2e8f9f7	3562	/* Clear NACK Flag */
<>	144:ef7eb2e8f9f7	3563	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	3564	}
<>	144:ef7eb2e8f9f7	3565	else
<>	144:ef7eb2e8f9f7	3566	{
<>	144:ef7eb2e8f9f7	3567	/* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
<>	144:ef7eb2e8f9f7	3568	/* Clear NACK Flag */
<>	144:ef7eb2e8f9f7	3569	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	3570
<>	144:ef7eb2e8f9f7	3571	/* Set ErrorCode corresponding to a Non-Acknowledge */
<>	144:ef7eb2e8f9f7	3572	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	3573	}
<>	144:ef7eb2e8f9f7	3574	}
<>	144:ef7eb2e8f9f7	3575	else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
<>	144:ef7eb2e8f9f7	3576	{
<>	144:ef7eb2e8f9f7	3577	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	3578	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
<>	144:ef7eb2e8f9f7	3579	}
<>	144:ef7eb2e8f9f7	3580	else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
<>	144:ef7eb2e8f9f7	3581	{
<>	144:ef7eb2e8f9f7	3582	/* Call I2C Slave complete process */
<>	144:ef7eb2e8f9f7	3583	I2C_ITSlaveCplt(hi2c, ITFlags);
<>	144:ef7eb2e8f9f7	3584	}
<>	144:ef7eb2e8f9f7	3585
<>	144:ef7eb2e8f9f7	3586	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3587	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3588
<>	144:ef7eb2e8f9f7	3589	return HAL_OK;
<>	144:ef7eb2e8f9f7	3590	}
<>	144:ef7eb2e8f9f7	3591
<>	144:ef7eb2e8f9f7	3592	/**
<>	144:ef7eb2e8f9f7	3593	* @brief Master sends target device address followed by internal memory address for write request.
<>	144:ef7eb2e8f9f7	3594	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3595	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3596	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	3597	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	3598	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	3599	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	3600	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	3601	* @retval HAL status
<>	144:ef7eb2e8f9f7	3602	*/
<>	144:ef7eb2e8f9f7	3603	static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	3604	{
<>	144:ef7eb2e8f9f7	3605	I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
<>	144:ef7eb2e8f9f7	3606
<>	144:ef7eb2e8f9f7	3607	/* Wait until TXIS flag is set */
<>	144:ef7eb2e8f9f7	3608	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3609	{
<>	144:ef7eb2e8f9f7	3610	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3611	{
<>	144:ef7eb2e8f9f7	3612	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3613	}
<>	144:ef7eb2e8f9f7	3614	else
<>	144:ef7eb2e8f9f7	3615	{
<>	144:ef7eb2e8f9f7	3616	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3617	}
<>	144:ef7eb2e8f9f7	3618	}
<>	144:ef7eb2e8f9f7	3619
<>	144:ef7eb2e8f9f7	3620	/* If Memory address size is 8Bit */
<>	144:ef7eb2e8f9f7	3621	if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
<>	144:ef7eb2e8f9f7	3622	{
<>	144:ef7eb2e8f9f7	3623	/* Send Memory Address */
<>	144:ef7eb2e8f9f7	3624	hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
<>	144:ef7eb2e8f9f7	3625	}
<>	144:ef7eb2e8f9f7	3626	/* If Memory address size is 16Bit */
<>	144:ef7eb2e8f9f7	3627	else
<>	144:ef7eb2e8f9f7	3628	{
<>	144:ef7eb2e8f9f7	3629	/* Send MSB of Memory Address */
<>	144:ef7eb2e8f9f7	3630	hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
<>	144:ef7eb2e8f9f7	3631
<>	144:ef7eb2e8f9f7	3632	/* Wait until TXIS flag is set */
<>	144:ef7eb2e8f9f7	3633	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3634	{
<>	144:ef7eb2e8f9f7	3635	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3636	{
<>	144:ef7eb2e8f9f7	3637	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3638	}
<>	144:ef7eb2e8f9f7	3639	else
<>	144:ef7eb2e8f9f7	3640	{
<>	144:ef7eb2e8f9f7	3641	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3642	}
<>	144:ef7eb2e8f9f7	3643	}
<>	144:ef7eb2e8f9f7	3644
<>	144:ef7eb2e8f9f7	3645	/* Send LSB of Memory Address */
<>	144:ef7eb2e8f9f7	3646	hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
<>	144:ef7eb2e8f9f7	3647	}
<>	144:ef7eb2e8f9f7	3648
<>	144:ef7eb2e8f9f7	3649	/* Wait until TCR flag is set */
<>	144:ef7eb2e8f9f7	3650	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3651	{
<>	144:ef7eb2e8f9f7	3652	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3653	}
<>	144:ef7eb2e8f9f7	3654
<>	144:ef7eb2e8f9f7	3655	return HAL_OK;
<>	144:ef7eb2e8f9f7	3656	}
<>	144:ef7eb2e8f9f7	3657
<>	144:ef7eb2e8f9f7	3658	/**
<>	144:ef7eb2e8f9f7	3659	* @brief Master sends target device address followed by internal memory address for read request.
<>	144:ef7eb2e8f9f7	3660	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3661	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3662	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	3663	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	3664	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	3665	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	3666	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	3667	* @retval HAL status
<>	144:ef7eb2e8f9f7	3668	*/
<>	144:ef7eb2e8f9f7	3669	static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	3670	{
<>	144:ef7eb2e8f9f7	3671	I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
<>	144:ef7eb2e8f9f7	3672
<>	144:ef7eb2e8f9f7	3673	/* Wait until TXIS flag is set */
<>	144:ef7eb2e8f9f7	3674	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3675	{
<>	144:ef7eb2e8f9f7	3676	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3677	{
<>	144:ef7eb2e8f9f7	3678	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3679	}
<>	144:ef7eb2e8f9f7	3680	else
<>	144:ef7eb2e8f9f7	3681	{
<>	144:ef7eb2e8f9f7	3682	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3683	}
<>	144:ef7eb2e8f9f7	3684	}
<>	144:ef7eb2e8f9f7	3685
<>	144:ef7eb2e8f9f7	3686	/* If Memory address size is 8Bit */
<>	144:ef7eb2e8f9f7	3687	if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
<>	144:ef7eb2e8f9f7	3688	{
<>	144:ef7eb2e8f9f7	3689	/* Send Memory Address */
<>	144:ef7eb2e8f9f7	3690	hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
<>	144:ef7eb2e8f9f7	3691	}
<>	144:ef7eb2e8f9f7	3692	/* If Memory address size is 16Bit */
<>	144:ef7eb2e8f9f7	3693	else
<>	144:ef7eb2e8f9f7	3694	{
<>	144:ef7eb2e8f9f7	3695	/* Send MSB of Memory Address */
<>	144:ef7eb2e8f9f7	3696	hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
<>	144:ef7eb2e8f9f7	3697
<>	144:ef7eb2e8f9f7	3698	/* Wait until TXIS flag is set */
<>	144:ef7eb2e8f9f7	3699	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3700	{
<>	144:ef7eb2e8f9f7	3701	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3702	{
<>	144:ef7eb2e8f9f7	3703	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3704	}
<>	144:ef7eb2e8f9f7	3705	else
<>	144:ef7eb2e8f9f7	3706	{
<>	144:ef7eb2e8f9f7	3707	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3708	}
<>	144:ef7eb2e8f9f7	3709	}
<>	144:ef7eb2e8f9f7	3710
<>	144:ef7eb2e8f9f7	3711	/* Send LSB of Memory Address */
<>	144:ef7eb2e8f9f7	3712	hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
<>	144:ef7eb2e8f9f7	3713	}
<>	144:ef7eb2e8f9f7	3714
<>	144:ef7eb2e8f9f7	3715	/* Wait until TC flag is set */
<>	144:ef7eb2e8f9f7	3716	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3717	{
<>	144:ef7eb2e8f9f7	3718	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3719	}
<>	144:ef7eb2e8f9f7	3720
<>	144:ef7eb2e8f9f7	3721	return HAL_OK;
<>	144:ef7eb2e8f9f7	3722	}
<>	144:ef7eb2e8f9f7	3723
<>	144:ef7eb2e8f9f7	3724	/**
<>	144:ef7eb2e8f9f7	3725	* @brief I2C Address complete process callback.
<>	144:ef7eb2e8f9f7	3726	* @param hi2c I2C handle.
<>	144:ef7eb2e8f9f7	3727	* @param ITFlags Interrupt flags to handle.
<>	144:ef7eb2e8f9f7	3728	* @retval None
<>	144:ef7eb2e8f9f7	3729	*/
<>	144:ef7eb2e8f9f7	3730	static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
<>	144:ef7eb2e8f9f7	3731	{
<>	144:ef7eb2e8f9f7	3732	uint8_t transferdirection = 0U;
<>	144:ef7eb2e8f9f7	3733	uint16_t slaveaddrcode = 0U;
<>	144:ef7eb2e8f9f7	3734	uint16_t ownadd1code = 0U;
<>	144:ef7eb2e8f9f7	3735	uint16_t ownadd2code = 0U;
<>	144:ef7eb2e8f9f7	3736
<>	144:ef7eb2e8f9f7	3737	/* In case of Listen state, need to inform upper layer of address match code event */
<>	144:ef7eb2e8f9f7	3738	if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
<>	144:ef7eb2e8f9f7	3739	{
<>	144:ef7eb2e8f9f7	3740	transferdirection = I2C_GET_DIR(hi2c);
<>	144:ef7eb2e8f9f7	3741	slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
<>	144:ef7eb2e8f9f7	3742	ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
<>	144:ef7eb2e8f9f7	3743	ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
<>	144:ef7eb2e8f9f7	3744
<>	144:ef7eb2e8f9f7	3745	/* If 10bits addressing mode is selected */
<>	144:ef7eb2e8f9f7	3746	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
<>	144:ef7eb2e8f9f7	3747	{
<>	144:ef7eb2e8f9f7	3748	if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
<>	144:ef7eb2e8f9f7	3749	{
<>	144:ef7eb2e8f9f7	3750	slaveaddrcode = ownadd1code;
<>	144:ef7eb2e8f9f7	3751	hi2c->AddrEventCount++;
<>	144:ef7eb2e8f9f7	3752	if(hi2c->AddrEventCount == 2U)
<>	144:ef7eb2e8f9f7	3753	{
<>	144:ef7eb2e8f9f7	3754	/* Reset Address Event counter */
<>	144:ef7eb2e8f9f7	3755	hi2c->AddrEventCount = 0U;
<>	144:ef7eb2e8f9f7	3756
<>	144:ef7eb2e8f9f7	3757	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	3758	__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
<>	144:ef7eb2e8f9f7	3759
<>	144:ef7eb2e8f9f7	3760	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3761	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3762
<>	144:ef7eb2e8f9f7	3763	/* Call Slave Addr callback */
<>	144:ef7eb2e8f9f7	3764	HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
<>	144:ef7eb2e8f9f7	3765	}
<>	144:ef7eb2e8f9f7	3766	}
<>	144:ef7eb2e8f9f7	3767	else
<>	144:ef7eb2e8f9f7	3768	{
<>	144:ef7eb2e8f9f7	3769	slaveaddrcode = ownadd2code;
<>	144:ef7eb2e8f9f7	3770
<>	144:ef7eb2e8f9f7	3771	/* Disable ADDR Interrupts */
<>	144:ef7eb2e8f9f7	3772	I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
<>	144:ef7eb2e8f9f7	3773
<>	144:ef7eb2e8f9f7	3774	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3775	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3776
<>	144:ef7eb2e8f9f7	3777	/* Call Slave Addr callback */
<>	144:ef7eb2e8f9f7	3778	HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
<>	144:ef7eb2e8f9f7	3779	}
<>	144:ef7eb2e8f9f7	3780	}
<>	144:ef7eb2e8f9f7	3781	/* else 7 bits addressing mode is selected */
<>	144:ef7eb2e8f9f7	3782	else
<>	144:ef7eb2e8f9f7	3783	{
<>	144:ef7eb2e8f9f7	3784	/* Disable ADDR Interrupts */
<>	144:ef7eb2e8f9f7	3785	I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
<>	144:ef7eb2e8f9f7	3786
<>	144:ef7eb2e8f9f7	3787	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3788	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3789
<>	144:ef7eb2e8f9f7	3790	/* Call Slave Addr callback */
<>	144:ef7eb2e8f9f7	3791	HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
<>	144:ef7eb2e8f9f7	3792	}
<>	144:ef7eb2e8f9f7	3793	}
<>	144:ef7eb2e8f9f7	3794	/* Else clear address flag only */
<>	144:ef7eb2e8f9f7	3795	else
<>	144:ef7eb2e8f9f7	3796	{
<>	144:ef7eb2e8f9f7	3797	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	3798	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
<>	144:ef7eb2e8f9f7	3799
<>	144:ef7eb2e8f9f7	3800	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3801	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3802	}
<>	144:ef7eb2e8f9f7	3803	}
<>	144:ef7eb2e8f9f7	3804
<>	144:ef7eb2e8f9f7	3805	/**
<>	144:ef7eb2e8f9f7	3806	* @brief I2C Master sequential complete process.
<>	144:ef7eb2e8f9f7	3807	* @param hi2c I2C handle.
<>	144:ef7eb2e8f9f7	3808	* @retval None
<>	144:ef7eb2e8f9f7	3809	*/
<>	144:ef7eb2e8f9f7	3810	static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3811	{
<>	144:ef7eb2e8f9f7	3812	/* Reset I2C handle mode */
<>	144:ef7eb2e8f9f7	3813	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3814
<>	144:ef7eb2e8f9f7	3815	/* No Generate Stop, to permit restart mode */
<>	144:ef7eb2e8f9f7	3816	/* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
<>	144:ef7eb2e8f9f7	3817	if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	3818	{
<>	144:ef7eb2e8f9f7	3819	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3820	hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
<>	144:ef7eb2e8f9f7	3821	hi2c->XferISR = NULL;
<>	144:ef7eb2e8f9f7	3822
<>	144:ef7eb2e8f9f7	3823	/* Disable Interrupts */
<>	144:ef7eb2e8f9f7	3824	I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
<>	144:ef7eb2e8f9f7	3825
<>	144:ef7eb2e8f9f7	3826	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3827	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3828
<>	144:ef7eb2e8f9f7	3829	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	144:ef7eb2e8f9f7	3830	HAL_I2C_MasterTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3831	}
<>	144:ef7eb2e8f9f7	3832	/* hi2c->State == HAL_I2C_STATE_BUSY_RX */
<>	144:ef7eb2e8f9f7	3833	else
<>	144:ef7eb2e8f9f7	3834	{
<>	144:ef7eb2e8f9f7	3835	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3836	hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
<>	144:ef7eb2e8f9f7	3837	hi2c->XferISR = NULL;
<>	144:ef7eb2e8f9f7	3838
<>	144:ef7eb2e8f9f7	3839	/* Disable Interrupts */
<>	144:ef7eb2e8f9f7	3840	I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
<>	144:ef7eb2e8f9f7	3841
<>	144:ef7eb2e8f9f7	3842	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3843	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3844
<>	144:ef7eb2e8f9f7	3845	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	144:ef7eb2e8f9f7	3846	HAL_I2C_MasterRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3847	}
<>	144:ef7eb2e8f9f7	3848	}
<>	144:ef7eb2e8f9f7	3849
<>	144:ef7eb2e8f9f7	3850	/**
<>	144:ef7eb2e8f9f7	3851	* @brief I2C Slave sequential complete process.
<>	144:ef7eb2e8f9f7	3852	* @param hi2c I2C handle.
<>	144:ef7eb2e8f9f7	3853	* @retval None
<>	144:ef7eb2e8f9f7	3854	*/
<>	144:ef7eb2e8f9f7	3855	static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3856	{
<>	144:ef7eb2e8f9f7	3857	/* Reset I2C handle mode */
<>	144:ef7eb2e8f9f7	3858	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3859
<>	144:ef7eb2e8f9f7	3860	if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
<>	144:ef7eb2e8f9f7	3861	{
<>	144:ef7eb2e8f9f7	3862	/* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
<>	144:ef7eb2e8f9f7	3863	hi2c->State = HAL_I2C_STATE_LISTEN;
<>	144:ef7eb2e8f9f7	3864	hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
<>	144:ef7eb2e8f9f7	3865
<>	144:ef7eb2e8f9f7	3866	/* Disable Interrupts */
<>	144:ef7eb2e8f9f7	3867	I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
<>	144:ef7eb2e8f9f7	3868
<>	144:ef7eb2e8f9f7	3869	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3870	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3871
<>	144:ef7eb2e8f9f7	3872	/* Call the Tx complete callback to inform upper layer of the end of transmit process */
<>	144:ef7eb2e8f9f7	3873	HAL_I2C_SlaveTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3874	}
<>	144:ef7eb2e8f9f7	3875
<>	144:ef7eb2e8f9f7	3876	else if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
<>	144:ef7eb2e8f9f7	3877	{
<>	144:ef7eb2e8f9f7	3878	/* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
<>	144:ef7eb2e8f9f7	3879	hi2c->State = HAL_I2C_STATE_LISTEN;
<>	144:ef7eb2e8f9f7	3880	hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
<>	144:ef7eb2e8f9f7	3881
<>	144:ef7eb2e8f9f7	3882	/* Disable Interrupts */
<>	144:ef7eb2e8f9f7	3883	I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
<>	144:ef7eb2e8f9f7	3884
<>	144:ef7eb2e8f9f7	3885	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3886	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3887
<>	144:ef7eb2e8f9f7	3888	/* Call the Rx complete callback to inform upper layer of the end of receive process */
<>	144:ef7eb2e8f9f7	3889	HAL_I2C_SlaveRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3890	}
<>	144:ef7eb2e8f9f7	3891	}
<>	144:ef7eb2e8f9f7	3892
<>	144:ef7eb2e8f9f7	3893	/**
<>	144:ef7eb2e8f9f7	3894	* @brief I2C Master complete process.
<>	144:ef7eb2e8f9f7	3895	* @param hi2c I2C handle.
<>	144:ef7eb2e8f9f7	3896	* @param ITFlags Interrupt flags to handle.
<>	144:ef7eb2e8f9f7	3897	* @retval None
<>	144:ef7eb2e8f9f7	3898	*/
<>	144:ef7eb2e8f9f7	3899	static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
<>	144:ef7eb2e8f9f7	3900	{
<>	144:ef7eb2e8f9f7	3901	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	3902	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	3903
<>	144:ef7eb2e8f9f7	3904	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	3905	I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	3906
<>	144:ef7eb2e8f9f7	3907	/* Reset handle parameters */
<>	144:ef7eb2e8f9f7	3908	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	3909	hi2c->XferISR = NULL;
<>	144:ef7eb2e8f9f7	3910	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	3911
<>	144:ef7eb2e8f9f7	3912	if((ITFlags & I2C_FLAG_AF) != RESET)
<>	144:ef7eb2e8f9f7	3913	{
<>	144:ef7eb2e8f9f7	3914	/* Clear NACK Flag */
<>	144:ef7eb2e8f9f7	3915	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	3916
<>	144:ef7eb2e8f9f7	3917	/* Set acknowledge error code */
<>	144:ef7eb2e8f9f7	3918	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	3919	}
<>	144:ef7eb2e8f9f7	3920
<>	144:ef7eb2e8f9f7	3921	/* Flush TX register */
<>	144:ef7eb2e8f9f7	3922	I2C_Flush_TXDR(hi2c);
<>	144:ef7eb2e8f9f7	3923
<>	144:ef7eb2e8f9f7	3924	/* Disable Interrupts */
<>	144:ef7eb2e8f9f7	3925	I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT\| I2C_XFER_RX_IT);
<>	144:ef7eb2e8f9f7	3926
<>	144:ef7eb2e8f9f7	3927	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	144:ef7eb2e8f9f7	3928	if((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) \|\| (hi2c->State == HAL_I2C_STATE_ABORT))
<>	144:ef7eb2e8f9f7	3929	{
<>	144:ef7eb2e8f9f7	3930	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	144:ef7eb2e8f9f7	3931	I2C_ITError(hi2c, hi2c->ErrorCode);
<>	144:ef7eb2e8f9f7	3932	}
<>	144:ef7eb2e8f9f7	3933	/* hi2c->State == HAL_I2C_STATE_BUSY_TX */
<>	144:ef7eb2e8f9f7	3934	else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	3935	{
<>	144:ef7eb2e8f9f7	3936	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3937
<>	144:ef7eb2e8f9f7	3938	if (hi2c->Mode == HAL_I2C_MODE_MEM)
<>	144:ef7eb2e8f9f7	3939	{
<>	144:ef7eb2e8f9f7	3940	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3941
<>	144:ef7eb2e8f9f7	3942	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3943	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3944
<>	144:ef7eb2e8f9f7	3945	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	144:ef7eb2e8f9f7	3946	HAL_I2C_MemTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3947	}
<>	144:ef7eb2e8f9f7	3948	else
<>	144:ef7eb2e8f9f7	3949	{
<>	144:ef7eb2e8f9f7	3950	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3951
<>	144:ef7eb2e8f9f7	3952	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3953	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3954
<>	144:ef7eb2e8f9f7	3955	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	144:ef7eb2e8f9f7	3956	HAL_I2C_MasterTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3957	}
<>	144:ef7eb2e8f9f7	3958	}
<>	144:ef7eb2e8f9f7	3959	/* hi2c->State == HAL_I2C_STATE_BUSY_RX */
<>	144:ef7eb2e8f9f7	3960	else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	3961	{
<>	144:ef7eb2e8f9f7	3962	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3963
<>	144:ef7eb2e8f9f7	3964	if (hi2c->Mode == HAL_I2C_MODE_MEM)
<>	144:ef7eb2e8f9f7	3965	{
<>	144:ef7eb2e8f9f7	3966	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3967
<>	144:ef7eb2e8f9f7	3968	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3969	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3970
<>	144:ef7eb2e8f9f7	3971	HAL_I2C_MemRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3972	}
<>	144:ef7eb2e8f9f7	3973	else
<>	144:ef7eb2e8f9f7	3974	{
<>	144:ef7eb2e8f9f7	3975	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3976
<>	144:ef7eb2e8f9f7	3977	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3978	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3979
<>	144:ef7eb2e8f9f7	3980	HAL_I2C_MasterRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3981	}
<>	144:ef7eb2e8f9f7	3982	}
<>	144:ef7eb2e8f9f7	3983	}
<>	144:ef7eb2e8f9f7	3984
<>	144:ef7eb2e8f9f7	3985	/**
<>	144:ef7eb2e8f9f7	3986	* @brief I2C Slave complete process.
<>	144:ef7eb2e8f9f7	3987	* @param hi2c I2C handle.
<>	144:ef7eb2e8f9f7	3988	* @param ITFlags Interrupt flags to handle.
<>	144:ef7eb2e8f9f7	3989	* @retval None
<>	144:ef7eb2e8f9f7	3990	*/
<>	144:ef7eb2e8f9f7	3991	static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
<>	144:ef7eb2e8f9f7	3992	{
<>	144:ef7eb2e8f9f7	3993	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	3994	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	3995
<>	144:ef7eb2e8f9f7	3996	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	3997	__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
<>	144:ef7eb2e8f9f7	3998
<>	144:ef7eb2e8f9f7	3999	/* Disable all interrupts */
<>	144:ef7eb2e8f9f7	4000	I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT \| I2C_XFER_TX_IT \| I2C_XFER_RX_IT);
<>	144:ef7eb2e8f9f7	4001
<>	144:ef7eb2e8f9f7	4002	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	4003	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	4004
<>	144:ef7eb2e8f9f7	4005	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	4006	I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	4007
<>	144:ef7eb2e8f9f7	4008	/* Flush TX register */
<>	144:ef7eb2e8f9f7	4009	I2C_Flush_TXDR(hi2c);
<>	144:ef7eb2e8f9f7	4010
<>	144:ef7eb2e8f9f7	4011	/* If a DMA is ongoing, Update handle size context */
<>	144:ef7eb2e8f9f7	4012	if(((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) \|\|
<>	144:ef7eb2e8f9f7	4013	((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN))
<>	144:ef7eb2e8f9f7	4014	{
<>	144:ef7eb2e8f9f7	4015	hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c);
<>	144:ef7eb2e8f9f7	4016	}
<>	144:ef7eb2e8f9f7	4017
<>	144:ef7eb2e8f9f7	4018	/* All data are not transferred, so set error code accordingly */
<>	144:ef7eb2e8f9f7	4019	if(hi2c->XferCount != 0U)
<>	144:ef7eb2e8f9f7	4020	{
<>	144:ef7eb2e8f9f7	4021	/* Set ErrorCode corresponding to a Non-Acknowledge */
<>	144:ef7eb2e8f9f7	4022	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	4023	}
<>	144:ef7eb2e8f9f7	4024
<>	144:ef7eb2e8f9f7	4025	/* Store Last receive data if any */
<>	144:ef7eb2e8f9f7	4026	if(((ITFlags & I2C_FLAG_RXNE) != RESET))
<>	144:ef7eb2e8f9f7	4027	{
<>	144:ef7eb2e8f9f7	4028	/* Read data from RXDR */
<>	144:ef7eb2e8f9f7	4029	(*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
<>	144:ef7eb2e8f9f7	4030
<>	144:ef7eb2e8f9f7	4031	if((hi2c->XferSize > 0U))
<>	144:ef7eb2e8f9f7	4032	{
<>	144:ef7eb2e8f9f7	4033	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	4034	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4035
<>	144:ef7eb2e8f9f7	4036	/* Set ErrorCode corresponding to a Non-Acknowledge */
<>	144:ef7eb2e8f9f7	4037	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	4038	}
<>	144:ef7eb2e8f9f7	4039	}
<>	144:ef7eb2e8f9f7	4040
<>	144:ef7eb2e8f9f7	4041	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	4042	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4043	hi2c->XferISR = NULL;
<>	144:ef7eb2e8f9f7	4044
<>	144:ef7eb2e8f9f7	4045	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<>	144:ef7eb2e8f9f7	4046	{
<>	144:ef7eb2e8f9f7	4047	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	144:ef7eb2e8f9f7	4048	I2C_ITError(hi2c, hi2c->ErrorCode);
<>	144:ef7eb2e8f9f7	4049
<>	144:ef7eb2e8f9f7	4050	/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
<>	144:ef7eb2e8f9f7	4051	if(hi2c->State == HAL_I2C_STATE_LISTEN)
<>	144:ef7eb2e8f9f7	4052	{
<>	144:ef7eb2e8f9f7	4053	/* Call I2C Listen complete process */
<>	144:ef7eb2e8f9f7	4054	I2C_ITListenCplt(hi2c, ITFlags);
<>	144:ef7eb2e8f9f7	4055	}
<>	144:ef7eb2e8f9f7	4056	}
<>	144:ef7eb2e8f9f7	4057	else if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
<>	144:ef7eb2e8f9f7	4058	{
<>	144:ef7eb2e8f9f7	4059	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	4060	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4061
<>	144:ef7eb2e8f9f7	4062	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	4063	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	4064
<>	144:ef7eb2e8f9f7	4065	/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
<>	144:ef7eb2e8f9f7	4066	HAL_I2C_ListenCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4067	}
<>	144:ef7eb2e8f9f7	4068	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	144:ef7eb2e8f9f7	4069	else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	4070	{
<>	144:ef7eb2e8f9f7	4071	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4072
<>	144:ef7eb2e8f9f7	4073	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	4074	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	4075
<>	144:ef7eb2e8f9f7	4076	/* Call the Slave Rx Complete callback */
<>	144:ef7eb2e8f9f7	4077	HAL_I2C_SlaveRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4078	}
<>	144:ef7eb2e8f9f7	4079	else
<>	144:ef7eb2e8f9f7	4080	{
<>	144:ef7eb2e8f9f7	4081	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4082
<>	144:ef7eb2e8f9f7	4083	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	4084	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	4085
<>	144:ef7eb2e8f9f7	4086	/* Call the Slave Tx Complete callback */
<>	144:ef7eb2e8f9f7	4087	HAL_I2C_SlaveTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4088	}
<>	144:ef7eb2e8f9f7	4089	}
<>	144:ef7eb2e8f9f7	4090
<>	144:ef7eb2e8f9f7	4091	/**
<>	144:ef7eb2e8f9f7	4092	* @brief I2C Listen complete process.
<>	144:ef7eb2e8f9f7	4093	* @param hi2c I2C handle.
<>	144:ef7eb2e8f9f7	4094	* @param ITFlags Interrupt flags to handle.
<>	144:ef7eb2e8f9f7	4095	* @retval None
<>	144:ef7eb2e8f9f7	4096	*/
<>	144:ef7eb2e8f9f7	4097	static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
<>	144:ef7eb2e8f9f7	4098	{
<>	144:ef7eb2e8f9f7	4099	/* Reset handle parameters */
<>	144:ef7eb2e8f9f7	4100	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	4101	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	4102	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4103	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4104	hi2c->XferISR = NULL;
<>	144:ef7eb2e8f9f7	4105
<>	144:ef7eb2e8f9f7	4106	/* Store Last receive data if any */
<>	144:ef7eb2e8f9f7	4107	if(((ITFlags & I2C_FLAG_RXNE) != RESET))
<>	144:ef7eb2e8f9f7	4108	{
<>	144:ef7eb2e8f9f7	4109	/* Read data from RXDR */
<>	144:ef7eb2e8f9f7	4110	(*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
<>	144:ef7eb2e8f9f7	4111
<>	144:ef7eb2e8f9f7	4112	if((hi2c->XferSize > 0U))
<>	144:ef7eb2e8f9f7	4113	{
<>	144:ef7eb2e8f9f7	4114	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	4115	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4116
<>	144:ef7eb2e8f9f7	4117	/* Set ErrorCode corresponding to a Non-Acknowledge */
<>	144:ef7eb2e8f9f7	4118	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	4119	}
<>	144:ef7eb2e8f9f7	4120	}
<>	144:ef7eb2e8f9f7	4121
<>	144:ef7eb2e8f9f7	4122	/* Disable all Interrupts*/
<>	144:ef7eb2e8f9f7	4123	I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT \| I2C_XFER_RX_IT \| I2C_XFER_TX_IT);
<>	144:ef7eb2e8f9f7	4124
<>	144:ef7eb2e8f9f7	4125	/* Clear NACK Flag */
<>	144:ef7eb2e8f9f7	4126	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	4127
<>	144:ef7eb2e8f9f7	4128	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	4129	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	4130
<>	144:ef7eb2e8f9f7	4131	/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
<>	144:ef7eb2e8f9f7	4132	HAL_I2C_ListenCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4133	}
<>	144:ef7eb2e8f9f7	4134
<>	144:ef7eb2e8f9f7	4135	/**
<>	144:ef7eb2e8f9f7	4136	* @brief I2C interrupts error process.
<>	144:ef7eb2e8f9f7	4137	* @param hi2c I2C handle.
<>	144:ef7eb2e8f9f7	4138	* @param ErrorCode Error code to handle.
<>	144:ef7eb2e8f9f7	4139	* @retval None
<>	144:ef7eb2e8f9f7	4140	*/
<>	144:ef7eb2e8f9f7	4141	static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
<>	144:ef7eb2e8f9f7	4142	{
<>	144:ef7eb2e8f9f7	4143	/* Reset handle parameters */
<>	144:ef7eb2e8f9f7	4144	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4145	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	4146	hi2c->XferCount = 0U;
<>	144:ef7eb2e8f9f7	4147
<>	144:ef7eb2e8f9f7	4148	/* Set new error code */
<>	144:ef7eb2e8f9f7	4149	hi2c->ErrorCode \|= ErrorCode;
<>	144:ef7eb2e8f9f7	4150
<>	144:ef7eb2e8f9f7	4151	/* Disable Interrupts */
<>	144:ef7eb2e8f9f7	4152	if((hi2c->State == HAL_I2C_STATE_LISTEN) \|\|
<>	144:ef7eb2e8f9f7	4153	(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) \|\|
<>	144:ef7eb2e8f9f7	4154	(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
<>	144:ef7eb2e8f9f7	4155	{
<>	144:ef7eb2e8f9f7	4156	/* Disable all interrupts, except interrupts related to LISTEN state */
<>	144:ef7eb2e8f9f7	4157	I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT \| I2C_XFER_TX_IT);
<>	144:ef7eb2e8f9f7	4158
<>	144:ef7eb2e8f9f7	4159	/* keep HAL_I2C_STATE_LISTEN if set */
<>	144:ef7eb2e8f9f7	4160	hi2c->State = HAL_I2C_STATE_LISTEN;
<>	144:ef7eb2e8f9f7	4161	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	4162	hi2c->XferISR = I2C_Slave_ISR_IT;
<>	144:ef7eb2e8f9f7	4163	}
<>	144:ef7eb2e8f9f7	4164	else
<>	144:ef7eb2e8f9f7	4165	{
<>	144:ef7eb2e8f9f7	4166	/* Disable all interrupts */
<>	144:ef7eb2e8f9f7	4167	I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT \| I2C_XFER_RX_IT \| I2C_XFER_TX_IT);
<>	144:ef7eb2e8f9f7	4168
<>	144:ef7eb2e8f9f7	4169	/* If state is an abort treatment on goind, don't change state */
<>	144:ef7eb2e8f9f7	4170	/* This change will be do later */
<>	144:ef7eb2e8f9f7	4171	if(hi2c->State != HAL_I2C_STATE_ABORT)
<>	144:ef7eb2e8f9f7	4172	{
<>	144:ef7eb2e8f9f7	4173	/* Set HAL_I2C_STATE_READY */
<>	144:ef7eb2e8f9f7	4174	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4175	}
<>	144:ef7eb2e8f9f7	4176	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	4177	hi2c->XferISR = NULL;
<>	144:ef7eb2e8f9f7	4178	}
<>	144:ef7eb2e8f9f7	4179
<>	144:ef7eb2e8f9f7	4180	/* Abort DMA TX transfer if any */
<>	144:ef7eb2e8f9f7	4181	if((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
<>	144:ef7eb2e8f9f7	4182	{
<>	144:ef7eb2e8f9f7	4183	hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
<>	144:ef7eb2e8f9f7	4184
<>	144:ef7eb2e8f9f7	4185	/* Set the I2C DMA Abort callback :
<>	144:ef7eb2e8f9f7	4186	will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
<>	144:ef7eb2e8f9f7	4187	hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
<>	144:ef7eb2e8f9f7	4188
<>	144:ef7eb2e8f9f7	4189	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	4190	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	4191
<>	144:ef7eb2e8f9f7	4192	/* Abort DMA TX */
<>	144:ef7eb2e8f9f7	4193	if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
<>	144:ef7eb2e8f9f7	4194	{
<>	144:ef7eb2e8f9f7	4195	/* Call Directly XferAbortCallback function in case of error */
<>	144:ef7eb2e8f9f7	4196	hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
<>	144:ef7eb2e8f9f7	4197	}
<>	144:ef7eb2e8f9f7	4198	}
<>	144:ef7eb2e8f9f7	4199	/* Abort DMA RX transfer if any */
<>	144:ef7eb2e8f9f7	4200	else if((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
<>	144:ef7eb2e8f9f7	4201	{
<>	144:ef7eb2e8f9f7	4202	hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
<>	144:ef7eb2e8f9f7	4203
<>	144:ef7eb2e8f9f7	4204	/* Set the I2C DMA Abort callback :
<>	144:ef7eb2e8f9f7	4205	will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
<>	144:ef7eb2e8f9f7	4206	hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
<>	144:ef7eb2e8f9f7	4207
<>	144:ef7eb2e8f9f7	4208	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	4209	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	4210
<>	144:ef7eb2e8f9f7	4211	/* Abort DMA RX */
<>	144:ef7eb2e8f9f7	4212	if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
<>	144:ef7eb2e8f9f7	4213	{
<>	144:ef7eb2e8f9f7	4214	/* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
<>	144:ef7eb2e8f9f7	4215	hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
<>	144:ef7eb2e8f9f7	4216	}
<>	144:ef7eb2e8f9f7	4217	}
<>	144:ef7eb2e8f9f7	4218	else if(hi2c->State == HAL_I2C_STATE_ABORT)
<>	144:ef7eb2e8f9f7	4219	{
<>	144:ef7eb2e8f9f7	4220	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4221
<>	144:ef7eb2e8f9f7	4222	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	4223	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	4224
<>	144:ef7eb2e8f9f7	4225	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	144:ef7eb2e8f9f7	4226	HAL_I2C_AbortCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4227	}
<>	144:ef7eb2e8f9f7	4228	else
<>	144:ef7eb2e8f9f7	4229	{
<>	144:ef7eb2e8f9f7	4230	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	4231	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	4232
<>	144:ef7eb2e8f9f7	4233	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	144:ef7eb2e8f9f7	4234	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	4235	}
<>	144:ef7eb2e8f9f7	4236	}
<>	144:ef7eb2e8f9f7	4237
<>	144:ef7eb2e8f9f7	4238	/**
<>	144:ef7eb2e8f9f7	4239	* @brief I2C Tx data register flush process.
<>	144:ef7eb2e8f9f7	4240	* @param hi2c I2C handle.
<>	144:ef7eb2e8f9f7	4241	* @retval None
<>	144:ef7eb2e8f9f7	4242	*/
<>	144:ef7eb2e8f9f7	4243	static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4244	{
<>	144:ef7eb2e8f9f7	4245	/* If a pending TXIS flag is set */
<>	144:ef7eb2e8f9f7	4246	/* Write a dummy data in TXDR to clear it */
<>	144:ef7eb2e8f9f7	4247	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
<>	144:ef7eb2e8f9f7	4248	{
<>	144:ef7eb2e8f9f7	4249	hi2c->Instance->TXDR = 0x00U;
<>	144:ef7eb2e8f9f7	4250	}
<>	144:ef7eb2e8f9f7	4251
<>	144:ef7eb2e8f9f7	4252	/* Flush TX register if not empty */
<>	144:ef7eb2e8f9f7	4253	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
<>	144:ef7eb2e8f9f7	4254	{
<>	144:ef7eb2e8f9f7	4255	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
<>	144:ef7eb2e8f9f7	4256	}
<>	144:ef7eb2e8f9f7	4257	}
<>	144:ef7eb2e8f9f7	4258
<>	144:ef7eb2e8f9f7	4259	/**
<>	144:ef7eb2e8f9f7	4260	* @brief DMA I2C master transmit process complete callback.
<>	144:ef7eb2e8f9f7	4261	* @param hdma DMA handle
<>	144:ef7eb2e8f9f7	4262	* @retval None
<>	144:ef7eb2e8f9f7	4263	*/
<>	144:ef7eb2e8f9f7	4264	static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4265	{
<>	144:ef7eb2e8f9f7	4266	I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
<>	144:ef7eb2e8f9f7	4267
<>	144:ef7eb2e8f9f7	4268	/* Disable DMA Request */
<>	144:ef7eb2e8f9f7	4269	hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
<>	144:ef7eb2e8f9f7	4270
<>	144:ef7eb2e8f9f7	4271	/* If last transfer, enable STOP interrupt */
<>	144:ef7eb2e8f9f7	4272	if(hi2c->XferCount == 0U)
<>	144:ef7eb2e8f9f7	4273	{
<>	144:ef7eb2e8f9f7	4274	/* Enable STOP interrupt */
<>	144:ef7eb2e8f9f7	4275	I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
<>	144:ef7eb2e8f9f7	4276	}
<>	144:ef7eb2e8f9f7	4277	/* else prepare a new DMA transfer and enable TCReload interrupt */
<>	144:ef7eb2e8f9f7	4278	else
<>	144:ef7eb2e8f9f7	4279	{
<>	144:ef7eb2e8f9f7	4280	/* Update Buffer pointer */
<>	144:ef7eb2e8f9f7	4281	hi2c->pBuffPtr += hi2c->XferSize;
<>	144:ef7eb2e8f9f7	4282
<>	144:ef7eb2e8f9f7	4283	/* Set the XferSize to transfer */
<>	144:ef7eb2e8f9f7	4284	if(hi2c->XferCount > MAX_NBYTE_SIZE)
<>	144:ef7eb2e8f9f7	4285	{
<>	144:ef7eb2e8f9f7	4286	hi2c->XferSize = MAX_NBYTE_SIZE;
<>	144:ef7eb2e8f9f7	4287	}
<>	144:ef7eb2e8f9f7	4288	else
<>	144:ef7eb2e8f9f7	4289	{
<>	144:ef7eb2e8f9f7	4290	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	4291	}
<>	144:ef7eb2e8f9f7	4292
<>	144:ef7eb2e8f9f7	4293	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	4294	HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
<>	144:ef7eb2e8f9f7	4295
<>	144:ef7eb2e8f9f7	4296	/* Enable TC interrupts */
<>	144:ef7eb2e8f9f7	4297	I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
<>	144:ef7eb2e8f9f7	4298	}
<>	144:ef7eb2e8f9f7	4299	}
<>	144:ef7eb2e8f9f7	4300
<>	144:ef7eb2e8f9f7	4301	/**
<>	144:ef7eb2e8f9f7	4302	* @brief DMA I2C slave transmit process complete callback.
<>	144:ef7eb2e8f9f7	4303	* @param hdma DMA handle
<>	144:ef7eb2e8f9f7	4304	* @retval None
<>	144:ef7eb2e8f9f7	4305	*/
<>	144:ef7eb2e8f9f7	4306	static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4307	{
<>	144:ef7eb2e8f9f7	4308	/* No specific action, Master fully manage the generation of STOP condition */
<>	144:ef7eb2e8f9f7	4309	/* Mean that this generation can arrive at any time, at the end or during DMA process */
<>	144:ef7eb2e8f9f7	4310	/* So STOP condition should be manage through Interrupt treatment */
<>	144:ef7eb2e8f9f7	4311	}
<>	144:ef7eb2e8f9f7	4312
<>	144:ef7eb2e8f9f7	4313	/**
<>	144:ef7eb2e8f9f7	4314	* @brief DMA I2C master receive process complete callback.
<>	144:ef7eb2e8f9f7	4315	* @param hdma DMA handle
<>	144:ef7eb2e8f9f7	4316	* @retval None
<>	144:ef7eb2e8f9f7	4317	*/
<>	144:ef7eb2e8f9f7	4318	static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4319	{
<>	144:ef7eb2e8f9f7	4320	I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
<>	144:ef7eb2e8f9f7	4321
<>	144:ef7eb2e8f9f7	4322	/* Disable DMA Request */
<>	144:ef7eb2e8f9f7	4323	hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
<>	144:ef7eb2e8f9f7	4324
<>	144:ef7eb2e8f9f7	4325	/* If last transfer, enable STOP interrupt */
<>	144:ef7eb2e8f9f7	4326	if(hi2c->XferCount == 0U)
<>	144:ef7eb2e8f9f7	4327	{
<>	144:ef7eb2e8f9f7	4328	/* Enable STOP interrupt */
<>	144:ef7eb2e8f9f7	4329	I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
<>	144:ef7eb2e8f9f7	4330	}
<>	144:ef7eb2e8f9f7	4331	/* else prepare a new DMA transfer and enable TCReload interrupt */
<>	144:ef7eb2e8f9f7	4332	else
<>	144:ef7eb2e8f9f7	4333	{
<>	144:ef7eb2e8f9f7	4334	/* Update Buffer pointer */
<>	144:ef7eb2e8f9f7	4335	hi2c->pBuffPtr += hi2c->XferSize;
<>	144:ef7eb2e8f9f7	4336
<>	144:ef7eb2e8f9f7	4337	/* Set the XferSize to transfer */
<>	144:ef7eb2e8f9f7	4338	if(hi2c->XferCount > MAX_NBYTE_SIZE)
<>	144:ef7eb2e8f9f7	4339	{
<>	144:ef7eb2e8f9f7	4340	hi2c->XferSize = MAX_NBYTE_SIZE;
<>	144:ef7eb2e8f9f7	4341	}
<>	144:ef7eb2e8f9f7	4342	else
<>	144:ef7eb2e8f9f7	4343	{
<>	144:ef7eb2e8f9f7	4344	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	4345	}
<>	144:ef7eb2e8f9f7	4346
<>	144:ef7eb2e8f9f7	4347	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	4348	HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
<>	144:ef7eb2e8f9f7	4349
<>	144:ef7eb2e8f9f7	4350	/* Enable TC interrupts */
<>	144:ef7eb2e8f9f7	4351	I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
<>	144:ef7eb2e8f9f7	4352	}
<>	144:ef7eb2e8f9f7	4353	}
<>	144:ef7eb2e8f9f7	4354
<>	144:ef7eb2e8f9f7	4355	/**
<>	144:ef7eb2e8f9f7	4356	* @brief DMA I2C slave receive process complete callback.
<>	144:ef7eb2e8f9f7	4357	* @param hdma DMA handle
<>	144:ef7eb2e8f9f7	4358	* @retval None
<>	144:ef7eb2e8f9f7	4359	*/
<>	144:ef7eb2e8f9f7	4360	static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4361	{
<>	144:ef7eb2e8f9f7	4362	/* No specific action, Master fully manage the generation of STOP condition */
<>	144:ef7eb2e8f9f7	4363	/* Mean that this generation can arrive at any time, at the end or during DMA process */
<>	144:ef7eb2e8f9f7	4364	/* So STOP condition should be manage through Interrupt treatment */
<>	144:ef7eb2e8f9f7	4365	}
<>	144:ef7eb2e8f9f7	4366
<>	144:ef7eb2e8f9f7	4367	/**
<>	144:ef7eb2e8f9f7	4368	* @brief DMA I2C communication error callback.
<>	144:ef7eb2e8f9f7	4369	* @param hdma DMA handle
<>	144:ef7eb2e8f9f7	4370	* @retval None
<>	144:ef7eb2e8f9f7	4371	*/
<>	144:ef7eb2e8f9f7	4372	static void I2C_DMAError(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4373	{
<>	144:ef7eb2e8f9f7	4374	I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	4375
<>	144:ef7eb2e8f9f7	4376	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	4377	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	4378
<>	144:ef7eb2e8f9f7	4379	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	144:ef7eb2e8f9f7	4380	I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
<>	144:ef7eb2e8f9f7	4381	}
<>	144:ef7eb2e8f9f7	4382
<>	144:ef7eb2e8f9f7	4383	/**
<>	144:ef7eb2e8f9f7	4384	* @brief DMA I2C communication abort callback
<>	144:ef7eb2e8f9f7	4385	* (To be called at end of DMA Abort procedure).
<>	144:ef7eb2e8f9f7	4386	* @param hdma: DMA handle.
<>	144:ef7eb2e8f9f7	4387	* @retval None
<>	144:ef7eb2e8f9f7	4388	*/
<>	144:ef7eb2e8f9f7	4389	static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4390	{
<>	144:ef7eb2e8f9f7	4391	I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	4392
<>	144:ef7eb2e8f9f7	4393	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	4394	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	4395
<>	144:ef7eb2e8f9f7	4396	/* Reset AbortCpltCallback */
<>	144:ef7eb2e8f9f7	4397	hi2c->hdmatx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	4398	hi2c->hdmarx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	4399
<>	144:ef7eb2e8f9f7	4400	/* Check if come from abort from user */
<>	144:ef7eb2e8f9f7	4401	if(hi2c->State == HAL_I2C_STATE_ABORT)
<>	144:ef7eb2e8f9f7	4402	{
<>	144:ef7eb2e8f9f7	4403	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4404
<>	144:ef7eb2e8f9f7	4405	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	144:ef7eb2e8f9f7	4406	HAL_I2C_AbortCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4407	}
<>	144:ef7eb2e8f9f7	4408	else
<>	144:ef7eb2e8f9f7	4409	{
<>	144:ef7eb2e8f9f7	4410	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	144:ef7eb2e8f9f7	4411	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	4412	}
<>	144:ef7eb2e8f9f7	4413	}
<>	144:ef7eb2e8f9f7	4414
<>	144:ef7eb2e8f9f7	4415	/**
<>	144:ef7eb2e8f9f7	4416	* @brief This function handles I2C Communication Timeout.
<>	144:ef7eb2e8f9f7	4417	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4418	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	4419	* @param Flag Specifies the I2C flag to check.
<>	144:ef7eb2e8f9f7	4420	* @param Status The new Flag status (SET or RESET).
<>	144:ef7eb2e8f9f7	4421	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	4422	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	4423	* @retval HAL status
<>	144:ef7eb2e8f9f7	4424	*/
<>	144:ef7eb2e8f9f7	4425	static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	4426	{
<>	144:ef7eb2e8f9f7	4427	while(__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
<>	144:ef7eb2e8f9f7	4428	{
<>	144:ef7eb2e8f9f7	4429	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	4430	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	4431	{
<>	144:ef7eb2e8f9f7	4432	if((Timeout == 0U)\|\|((HAL_GetTick() - Tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	4433	{
<>	144:ef7eb2e8f9f7	4434	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4435	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4436
<>	144:ef7eb2e8f9f7	4437	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	4438	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	4439	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4440	}
<>	144:ef7eb2e8f9f7	4441	}
<>	144:ef7eb2e8f9f7	4442	}
<>	144:ef7eb2e8f9f7	4443	return HAL_OK;
<>	144:ef7eb2e8f9f7	4444	}
<>	144:ef7eb2e8f9f7	4445
<>	144:ef7eb2e8f9f7	4446	/**
<>	144:ef7eb2e8f9f7	4447	* @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
<>	144:ef7eb2e8f9f7	4448	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4449	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	4450	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	4451	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	4452	* @retval HAL status
<>	144:ef7eb2e8f9f7	4453	*/
<>	144:ef7eb2e8f9f7	4454	static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	4455	{
<>	144:ef7eb2e8f9f7	4456	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
<>	144:ef7eb2e8f9f7	4457	{
<>	144:ef7eb2e8f9f7	4458	/* Check if a NACK is detected */
<>	144:ef7eb2e8f9f7	4459	if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4460	{
<>	144:ef7eb2e8f9f7	4461	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4462	}
<>	144:ef7eb2e8f9f7	4463
<>	144:ef7eb2e8f9f7	4464	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	4465	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	4466	{
<>	144:ef7eb2e8f9f7	4467	if((Timeout == 0U)\|\|((HAL_GetTick() - Tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	4468	{
<>	144:ef7eb2e8f9f7	4469	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	4470	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4471	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4472
<>	144:ef7eb2e8f9f7	4473	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	4474	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	4475
<>	144:ef7eb2e8f9f7	4476	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4477	}
<>	144:ef7eb2e8f9f7	4478	}
<>	144:ef7eb2e8f9f7	4479	}
<>	144:ef7eb2e8f9f7	4480	return HAL_OK;
<>	144:ef7eb2e8f9f7	4481	}
<>	144:ef7eb2e8f9f7	4482
<>	144:ef7eb2e8f9f7	4483	/**
<>	144:ef7eb2e8f9f7	4484	* @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
<>	144:ef7eb2e8f9f7	4485	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4486	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	4487	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	4488	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	4489	* @retval HAL status
<>	144:ef7eb2e8f9f7	4490	*/
<>	144:ef7eb2e8f9f7	4491	static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	4492	{
<>	144:ef7eb2e8f9f7	4493	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
<>	144:ef7eb2e8f9f7	4494	{
<>	144:ef7eb2e8f9f7	4495	/* Check if a NACK is detected */
<>	144:ef7eb2e8f9f7	4496	if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4497	{
<>	144:ef7eb2e8f9f7	4498	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4499	}
<>	144:ef7eb2e8f9f7	4500
<>	144:ef7eb2e8f9f7	4501	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	4502	if((Timeout == 0U)\|\|((HAL_GetTick() - Tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	4503	{
<>	144:ef7eb2e8f9f7	4504	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	4505	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4506	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4507
<>	144:ef7eb2e8f9f7	4508	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	4509	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	4510
<>	144:ef7eb2e8f9f7	4511	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4512	}
<>	144:ef7eb2e8f9f7	4513	}
<>	144:ef7eb2e8f9f7	4514	return HAL_OK;
<>	144:ef7eb2e8f9f7	4515	}
<>	144:ef7eb2e8f9f7	4516
<>	144:ef7eb2e8f9f7	4517	/**
<>	144:ef7eb2e8f9f7	4518	* @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
<>	144:ef7eb2e8f9f7	4519	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4520	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	4521	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	4522	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	4523	* @retval HAL status
<>	144:ef7eb2e8f9f7	4524	*/
<>	144:ef7eb2e8f9f7	4525	static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	4526	{
<>	144:ef7eb2e8f9f7	4527	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
<>	144:ef7eb2e8f9f7	4528	{
<>	144:ef7eb2e8f9f7	4529	/* Check if a NACK is detected */
<>	144:ef7eb2e8f9f7	4530	if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4531	{
<>	144:ef7eb2e8f9f7	4532	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4533	}
<>	144:ef7eb2e8f9f7	4534
<>	144:ef7eb2e8f9f7	4535	/* Check if a STOPF is detected */
<>	144:ef7eb2e8f9f7	4536	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
<>	144:ef7eb2e8f9f7	4537	{
<>	144:ef7eb2e8f9f7	4538	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	4539	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	4540
<>	144:ef7eb2e8f9f7	4541	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	4542	I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	4543
<>	144:ef7eb2e8f9f7	4544	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	4545	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4546	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4547
<>	144:ef7eb2e8f9f7	4548	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	4549	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	4550
<>	144:ef7eb2e8f9f7	4551	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4552	}
<>	144:ef7eb2e8f9f7	4553
<>	144:ef7eb2e8f9f7	4554	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	4555	if((Timeout == 0U)\|\|((HAL_GetTick() - Tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	4556	{
<>	144:ef7eb2e8f9f7	4557	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	4558	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4559
<>	144:ef7eb2e8f9f7	4560	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	4561	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	4562
<>	144:ef7eb2e8f9f7	4563	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4564	}
<>	144:ef7eb2e8f9f7	4565	}
<>	144:ef7eb2e8f9f7	4566	return HAL_OK;
<>	144:ef7eb2e8f9f7	4567	}
<>	144:ef7eb2e8f9f7	4568
<>	144:ef7eb2e8f9f7	4569	/**
<>	144:ef7eb2e8f9f7	4570	* @brief This function handles Acknowledge failed detection during an I2C Communication.
<>	144:ef7eb2e8f9f7	4571	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4572	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	4573	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	4574	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	4575	* @retval HAL status
<>	144:ef7eb2e8f9f7	4576	*/
<>	144:ef7eb2e8f9f7	4577	static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	4578	{
<>	144:ef7eb2e8f9f7	4579	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
<>	144:ef7eb2e8f9f7	4580	{
<>	144:ef7eb2e8f9f7	4581	/* Wait until STOP Flag is reset */
<>	144:ef7eb2e8f9f7	4582	/* AutoEnd should be initiate after AF */
<>	144:ef7eb2e8f9f7	4583	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
<>	144:ef7eb2e8f9f7	4584	{
<>	144:ef7eb2e8f9f7	4585	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	4586	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	4587	{
<>	144:ef7eb2e8f9f7	4588	if((Timeout == 0U)\|\|((HAL_GetTick() - Tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	4589	{
<>	144:ef7eb2e8f9f7	4590	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4591	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4592
<>	144:ef7eb2e8f9f7	4593	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	4594	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	4595	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4596	}
<>	144:ef7eb2e8f9f7	4597	}
<>	144:ef7eb2e8f9f7	4598	}
<>	144:ef7eb2e8f9f7	4599
<>	144:ef7eb2e8f9f7	4600	/* Clear NACKF Flag */
<>	144:ef7eb2e8f9f7	4601	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	4602
<>	144:ef7eb2e8f9f7	4603	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	4604	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	4605
<>	144:ef7eb2e8f9f7	4606	/* Flush TX register */
<>	144:ef7eb2e8f9f7	4607	I2C_Flush_TXDR(hi2c);
<>	144:ef7eb2e8f9f7	4608
<>	144:ef7eb2e8f9f7	4609	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	4610	I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	4611
<>	144:ef7eb2e8f9f7	4612	hi2c->ErrorCode = HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	4613	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4614	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4615
<>	144:ef7eb2e8f9f7	4616	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	4617	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	4618
<>	144:ef7eb2e8f9f7	4619	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4620	}
<>	144:ef7eb2e8f9f7	4621	return HAL_OK;
<>	144:ef7eb2e8f9f7	4622	}
<>	144:ef7eb2e8f9f7	4623
<>	144:ef7eb2e8f9f7	4624	/**
<>	144:ef7eb2e8f9f7	4625	* @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
<>	144:ef7eb2e8f9f7	4626	* @param hi2c I2C handle.
<>	144:ef7eb2e8f9f7	4627	* @param DevAddress Specifies the slave address to be programmed.
<>	144:ef7eb2e8f9f7	4628	* @param Size Specifies the number of bytes to be programmed.
<>	144:ef7eb2e8f9f7	4629	* This parameter must be a value between 0 and 255.
<>	144:ef7eb2e8f9f7	4630	* @param Mode New state of the I2C START condition generation.
<>	144:ef7eb2e8f9f7	4631	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4632	* @arg @ref I2C_RELOAD_MODE Enable Reload mode .
<>	144:ef7eb2e8f9f7	4633	* @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
<>	144:ef7eb2e8f9f7	4634	* @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
<>	144:ef7eb2e8f9f7	4635	* @param Request New state of the I2C START condition generation.
<>	144:ef7eb2e8f9f7	4636	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4637	* @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
<>	144:ef7eb2e8f9f7	4638	* @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
<>	144:ef7eb2e8f9f7	4639	* @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
<>	144:ef7eb2e8f9f7	4640	* @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
<>	144:ef7eb2e8f9f7	4641	* @retval None
<>	144:ef7eb2e8f9f7	4642	*/
<>	144:ef7eb2e8f9f7	4643	static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
<>	144:ef7eb2e8f9f7	4644	{
<>	144:ef7eb2e8f9f7	4645	uint32_t tmpreg = 0U;
<>	144:ef7eb2e8f9f7	4646
<>	144:ef7eb2e8f9f7	4647	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4648	assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
<>	144:ef7eb2e8f9f7	4649	assert_param(IS_TRANSFER_MODE(Mode));
<>	144:ef7eb2e8f9f7	4650	assert_param(IS_TRANSFER_REQUEST(Request));
<>	144:ef7eb2e8f9f7	4651
<>	144:ef7eb2e8f9f7	4652	/* Get the CR2 register value */
<>	144:ef7eb2e8f9f7	4653	tmpreg = hi2c->Instance->CR2;
<>	144:ef7eb2e8f9f7	4654
<>	144:ef7eb2e8f9f7	4655	/* clear tmpreg specific bits */
<>	144:ef7eb2e8f9f7	4656	tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD \| I2C_CR2_NBYTES \| I2C_CR2_RELOAD \| I2C_CR2_AUTOEND \| I2C_CR2_RD_WRN \| I2C_CR2_START \| I2C_CR2_STOP));
<>	144:ef7eb2e8f9f7	4657
<>	144:ef7eb2e8f9f7	4658	/* update tmpreg */
<>	144:ef7eb2e8f9f7	4659	tmpreg \|= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) \| (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) \| \
<>	144:ef7eb2e8f9f7	4660	(uint32_t)Mode \| (uint32_t)Request);
<>	144:ef7eb2e8f9f7	4661
<>	144:ef7eb2e8f9f7	4662	/* update CR2 register */
<>	144:ef7eb2e8f9f7	4663	hi2c->Instance->CR2 = tmpreg;
<>	144:ef7eb2e8f9f7	4664	}
<>	144:ef7eb2e8f9f7	4665
<>	144:ef7eb2e8f9f7	4666	/**
<>	144:ef7eb2e8f9f7	4667	* @brief Manage the enabling of Interrupts.
<>	144:ef7eb2e8f9f7	4668	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4669	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	4670	* @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
<>	144:ef7eb2e8f9f7	4671	* @retval HAL status
<>	144:ef7eb2e8f9f7	4672	*/
<>	144:ef7eb2e8f9f7	4673	static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
<>	144:ef7eb2e8f9f7	4674	{
<>	144:ef7eb2e8f9f7	4675	uint32_t tmpisr = 0U;
<>	144:ef7eb2e8f9f7	4676
<>	144:ef7eb2e8f9f7	4677	if((hi2c->XferISR == I2C_Master_ISR_DMA) \|\| \
<>	144:ef7eb2e8f9f7	4678	(hi2c->XferISR == I2C_Slave_ISR_DMA))
<>	144:ef7eb2e8f9f7	4679	{
<>	144:ef7eb2e8f9f7	4680	if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
<>	144:ef7eb2e8f9f7	4681	{
<>	144:ef7eb2e8f9f7	4682	/* Enable ERR, STOP, NACK and ADDR interrupts */
<>	144:ef7eb2e8f9f7	4683	tmpisr \|= I2C_IT_ADDRI \| I2C_IT_STOPI \| I2C_IT_NACKI \| I2C_IT_ERRI;
<>	144:ef7eb2e8f9f7	4684	}
<>	144:ef7eb2e8f9f7	4685
<>	144:ef7eb2e8f9f7	4686	if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
<>	144:ef7eb2e8f9f7	4687	{
<>	144:ef7eb2e8f9f7	4688	/* Enable ERR and NACK interrupts */
<>	144:ef7eb2e8f9f7	4689	tmpisr \|= I2C_IT_ERRI \| I2C_IT_NACKI;
<>	144:ef7eb2e8f9f7	4690	}
<>	144:ef7eb2e8f9f7	4691
<>	144:ef7eb2e8f9f7	4692	if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
<>	144:ef7eb2e8f9f7	4693	{
<>	144:ef7eb2e8f9f7	4694	/* Enable STOP interrupts */
<>	144:ef7eb2e8f9f7	4695	tmpisr \|= I2C_IT_STOPI;
<>	144:ef7eb2e8f9f7	4696	}
<>	144:ef7eb2e8f9f7	4697
<>	144:ef7eb2e8f9f7	4698	if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
<>	144:ef7eb2e8f9f7	4699	{
<>	144:ef7eb2e8f9f7	4700	/* Enable TC interrupts */
<>	144:ef7eb2e8f9f7	4701	tmpisr \|= I2C_IT_TCI;
<>	144:ef7eb2e8f9f7	4702	}
<>	144:ef7eb2e8f9f7	4703	}
<>	144:ef7eb2e8f9f7	4704	else
<>	144:ef7eb2e8f9f7	4705	{
<>	144:ef7eb2e8f9f7	4706	if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
<>	144:ef7eb2e8f9f7	4707	{
<>	144:ef7eb2e8f9f7	4708	/* Enable ERR, STOP, NACK, and ADDR interrupts */
<>	144:ef7eb2e8f9f7	4709	tmpisr \|= I2C_IT_ADDRI \| I2C_IT_STOPI \| I2C_IT_NACKI \| I2C_IT_ERRI;
<>	144:ef7eb2e8f9f7	4710	}
<>	144:ef7eb2e8f9f7	4711
<>	144:ef7eb2e8f9f7	4712	if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
<>	144:ef7eb2e8f9f7	4713	{
<>	144:ef7eb2e8f9f7	4714	/* Enable ERR, TC, STOP, NACK and RXI interrupts */
<>	144:ef7eb2e8f9f7	4715	tmpisr \|= I2C_IT_ERRI \| I2C_IT_TCI \| I2C_IT_STOPI \| I2C_IT_NACKI \| I2C_IT_TXI;
<>	144:ef7eb2e8f9f7	4716	}
<>	144:ef7eb2e8f9f7	4717
<>	144:ef7eb2e8f9f7	4718	if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
<>	144:ef7eb2e8f9f7	4719	{
<>	144:ef7eb2e8f9f7	4720	/* Enable ERR, TC, STOP, NACK and TXI interrupts */
<>	144:ef7eb2e8f9f7	4721	tmpisr \|= I2C_IT_ERRI \| I2C_IT_TCI \| I2C_IT_STOPI \| I2C_IT_NACKI \| I2C_IT_RXI;
<>	144:ef7eb2e8f9f7	4722	}
<>	144:ef7eb2e8f9f7	4723
<>	144:ef7eb2e8f9f7	4724	if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
<>	144:ef7eb2e8f9f7	4725	{
<>	144:ef7eb2e8f9f7	4726	/* Enable STOP interrupts */
<>	144:ef7eb2e8f9f7	4727	tmpisr \|= I2C_IT_STOPI;
<>	144:ef7eb2e8f9f7	4728	}
<>	144:ef7eb2e8f9f7	4729	}
<>	144:ef7eb2e8f9f7	4730
<>	144:ef7eb2e8f9f7	4731	/* Enable interrupts only at the end */
<>	144:ef7eb2e8f9f7	4732	/* to avoid the risk of I2C interrupt handle execution before */
<>	144:ef7eb2e8f9f7	4733	/* all interrupts requested done */
<>	144:ef7eb2e8f9f7	4734	__HAL_I2C_ENABLE_IT(hi2c, tmpisr);
<>	144:ef7eb2e8f9f7	4735
<>	144:ef7eb2e8f9f7	4736	return HAL_OK;
<>	144:ef7eb2e8f9f7	4737	}
<>	144:ef7eb2e8f9f7	4738
<>	144:ef7eb2e8f9f7	4739	/**
<>	144:ef7eb2e8f9f7	4740	* @brief Manage the disabling of Interrupts.
<>	144:ef7eb2e8f9f7	4741	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4742	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	4743	* @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
<>	144:ef7eb2e8f9f7	4744	* @retval HAL status
<>	144:ef7eb2e8f9f7	4745	*/
<>	144:ef7eb2e8f9f7	4746	static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
<>	144:ef7eb2e8f9f7	4747	{
<>	144:ef7eb2e8f9f7	4748	uint32_t tmpisr = 0U;
<>	144:ef7eb2e8f9f7	4749
<>	144:ef7eb2e8f9f7	4750	if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
<>	144:ef7eb2e8f9f7	4751	{
<>	144:ef7eb2e8f9f7	4752	/* Disable TC and TXI interrupts */
<>	144:ef7eb2e8f9f7	4753	tmpisr \|= I2C_IT_TCI \| I2C_IT_TXI;
<>	144:ef7eb2e8f9f7	4754
<>	144:ef7eb2e8f9f7	4755	if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
<>	144:ef7eb2e8f9f7	4756	{
<>	144:ef7eb2e8f9f7	4757	/* Disable NACK and STOP interrupts */
<>	144:ef7eb2e8f9f7	4758	tmpisr \|= I2C_IT_STOPI \| I2C_IT_NACKI \| I2C_IT_ERRI;
<>	144:ef7eb2e8f9f7	4759	}
<>	144:ef7eb2e8f9f7	4760	}
<>	144:ef7eb2e8f9f7	4761
<>	144:ef7eb2e8f9f7	4762	if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
<>	144:ef7eb2e8f9f7	4763	{
<>	144:ef7eb2e8f9f7	4764	/* Disable TC and RXI interrupts */
<>	144:ef7eb2e8f9f7	4765	tmpisr \|= I2C_IT_TCI \| I2C_IT_RXI;
<>	144:ef7eb2e8f9f7	4766
<>	144:ef7eb2e8f9f7	4767	if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
<>	144:ef7eb2e8f9f7	4768	{
<>	144:ef7eb2e8f9f7	4769	/* Disable NACK and STOP interrupts */
<>	144:ef7eb2e8f9f7	4770	tmpisr \|= I2C_IT_STOPI \| I2C_IT_NACKI \| I2C_IT_ERRI;
<>	144:ef7eb2e8f9f7	4771	}
<>	144:ef7eb2e8f9f7	4772	}
<>	144:ef7eb2e8f9f7	4773
<>	144:ef7eb2e8f9f7	4774	if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
<>	144:ef7eb2e8f9f7	4775	{
<>	144:ef7eb2e8f9f7	4776	/* Disable ADDR, NACK and STOP interrupts */
<>	144:ef7eb2e8f9f7	4777	tmpisr \|= I2C_IT_ADDRI \| I2C_IT_STOPI \| I2C_IT_NACKI \| I2C_IT_ERRI;
<>	144:ef7eb2e8f9f7	4778	}
<>	144:ef7eb2e8f9f7	4779
<>	144:ef7eb2e8f9f7	4780	if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
<>	144:ef7eb2e8f9f7	4781	{
<>	144:ef7eb2e8f9f7	4782	/* Enable ERR and NACK interrupts */
<>	144:ef7eb2e8f9f7	4783	tmpisr \|= I2C_IT_ERRI \| I2C_IT_NACKI;
<>	144:ef7eb2e8f9f7	4784	}
<>	144:ef7eb2e8f9f7	4785
<>	144:ef7eb2e8f9f7	4786	if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
<>	144:ef7eb2e8f9f7	4787	{
<>	144:ef7eb2e8f9f7	4788	/* Enable STOP interrupts */
<>	144:ef7eb2e8f9f7	4789	tmpisr \|= I2C_IT_STOPI;
<>	144:ef7eb2e8f9f7	4790	}
<>	144:ef7eb2e8f9f7	4791
<>	144:ef7eb2e8f9f7	4792	if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
<>	144:ef7eb2e8f9f7	4793	{
<>	144:ef7eb2e8f9f7	4794	/* Enable TC interrupts */
<>	144:ef7eb2e8f9f7	4795	tmpisr \|= I2C_IT_TCI;
<>	144:ef7eb2e8f9f7	4796	}
<>	144:ef7eb2e8f9f7	4797
<>	144:ef7eb2e8f9f7	4798	/* Disable interrupts only at the end */
<>	144:ef7eb2e8f9f7	4799	/* to avoid a breaking situation like at "t" time */
<>	144:ef7eb2e8f9f7	4800	/* all disable interrupts request are not done */
<>	144:ef7eb2e8f9f7	4801	__HAL_I2C_DISABLE_IT(hi2c, tmpisr);
<>	144:ef7eb2e8f9f7	4802
<>	144:ef7eb2e8f9f7	4803	return HAL_OK;
<>	144:ef7eb2e8f9f7	4804	}
<>	144:ef7eb2e8f9f7	4805
<>	144:ef7eb2e8f9f7	4806	/**
<>	144:ef7eb2e8f9f7	4807	* @}
<>	144:ef7eb2e8f9f7	4808	*/
<>	144:ef7eb2e8f9f7	4809
<>	144:ef7eb2e8f9f7	4810	#endif /* HAL_I2C_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	4811	/**
<>	144:ef7eb2e8f9f7	4812	* @}
<>	144:ef7eb2e8f9f7	4813	*/
<>	144:ef7eb2e8f9f7	4814
<>	144:ef7eb2e8f9f7	4815	/**
<>	144:ef7eb2e8f9f7	4816	* @}
<>	144:ef7eb2e8f9f7	4817	*/
<>	144:ef7eb2e8f9f7	4818
<>	144:ef7eb2e8f9f7	4819	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	08 Mar 2017
Imports:	12
Forks:	0
Commits:	165
Dependents:	3
Dependencies:	0
Followers:	5

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Greg Steiert

Jesse Marroquin

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targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_i2c.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

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targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_i2c.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

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