Greg Steiert / maxim-dev

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Dependents:   MAX34417_demo MAXREFDES1265 MAXREFDES1265

Fork of mbed-dev by mbed official

targets/hal/TARGET_NXP/TARGET_LPC43XX/serial_api.c@42:367d7b10ab62, 2016-01-04 (annotated)

Committer:
mbed_official
Date:
Mon Jan 04 09:30:11 2016 +0000
Revision:
42:367d7b10ab62
Parent:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Synchronized with git revision 7899cff5f676742c244cca2908aea850227f6b53



Full URL: https://github.com/mbedmicro/mbed/commit/7899cff5f676742c244cca2908aea850227f6b53/



LPC4337 stdio fixes for lpcxpresso board

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library
bogdanm 0:9b334a45a8ff 2 * Copyright (c) 2006-2013 ARM Limited
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 0:9b334a45a8ff 5 * you may not use this file except in compliance with the License.
bogdanm 0:9b334a45a8ff 6 * You may obtain a copy of the License at
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 0:9b334a45a8ff 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 0:9b334a45a8ff 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 0:9b334a45a8ff 13 * See the License for the specific language governing permissions and
bogdanm 0:9b334a45a8ff 14 * limitations under the License.
bogdanm 0:9b334a45a8ff 15 *
bogdanm 0:9b334a45a8ff 16 * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
bogdanm 0:9b334a45a8ff 17 */
bogdanm 0:9b334a45a8ff 18 // math.h required for floating point operations for baud rate calculation
bogdanm 0:9b334a45a8ff 19 #include <math.h>
bogdanm 0:9b334a45a8ff 20 #include <string.h>
bogdanm 0:9b334a45a8ff 21 #include <stdlib.h>
bogdanm 0:9b334a45a8ff 22
bogdanm 0:9b334a45a8ff 23 #include "serial_api.h"
bogdanm 0:9b334a45a8ff 24 #include "cmsis.h"
bogdanm 0:9b334a45a8ff 25 #include "pinmap.h"
bogdanm 0:9b334a45a8ff 26 #include "mbed_error.h"
bogdanm 0:9b334a45a8ff 27 #include "gpio_api.h"
bogdanm 0:9b334a45a8ff 28
bogdanm 0:9b334a45a8ff 29 /******************************************************************************
bogdanm 0:9b334a45a8ff 30 * INITIALIZATION
bogdanm 0:9b334a45a8ff 31 ******************************************************************************/
bogdanm 0:9b334a45a8ff 32 #define UART_NUM 4
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 // SCU mode for UART pins
bogdanm 0:9b334a45a8ff 35 #define SCU_PINIO_UART_TX SCU_MODE_PULLDOWN
bogdanm 0:9b334a45a8ff 36 #define SCU_PINIO_UART_RX SCU_PINIO_PULLNONE
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 static const PinMap PinMap_UART_TX[] = {
bogdanm 0:9b334a45a8ff 39 {P1_13, UART_1, (SCU_PINIO_UART_TX | 1)},
bogdanm 0:9b334a45a8ff 40 {P1_15, UART_2, (SCU_PINIO_UART_TX | 1)},
bogdanm 0:9b334a45a8ff 41 {P2_0, UART_0, (SCU_PINIO_UART_TX | 1)},
bogdanm 0:9b334a45a8ff 42 {P2_3, UART_3, (SCU_PINIO_UART_TX | 2)},
bogdanm 0:9b334a45a8ff 43 {P2_10, UART_2, (SCU_PINIO_UART_TX | 2)},
bogdanm 0:9b334a45a8ff 44 {P3_4, UART_1, (SCU_PINIO_UART_TX | 4)},
bogdanm 0:9b334a45a8ff 45 {P4_1, UART_3, (SCU_PINIO_UART_TX | 6)},
bogdanm 0:9b334a45a8ff 46 {P5_6, UART_1, (SCU_PINIO_UART_TX | 4)},
bogdanm 0:9b334a45a8ff 47 {P6_4, UART_0, (SCU_PINIO_UART_TX | 2)},
bogdanm 0:9b334a45a8ff 48 {P7_1, UART_2, (SCU_PINIO_UART_TX | 6)},
bogdanm 0:9b334a45a8ff 49 {P9_3, UART_3, (SCU_PINIO_UART_TX | 7)},
bogdanm 0:9b334a45a8ff 50 {P9_5, UART_0, (SCU_PINIO_UART_TX | 7)},
bogdanm 0:9b334a45a8ff 51 {PA_1, UART_2, (SCU_PINIO_UART_TX | 3)},
bogdanm 0:9b334a45a8ff 52 {PC_13, UART_1, (SCU_PINIO_UART_TX | 2)},
bogdanm 0:9b334a45a8ff 53 {PE_11, UART_1, (SCU_PINIO_UART_TX | 2)},
bogdanm 0:9b334a45a8ff 54 {PF_2, UART_3, (SCU_PINIO_UART_TX | 1)},
bogdanm 0:9b334a45a8ff 55 {PF_10, UART_0, (SCU_PINIO_UART_TX | 1)},
bogdanm 0:9b334a45a8ff 56 {NC, NC, 0}
bogdanm 0:9b334a45a8ff 57 };
bogdanm 0:9b334a45a8ff 58
bogdanm 0:9b334a45a8ff 59 static const PinMap PinMap_UART_RX[] = {
bogdanm 0:9b334a45a8ff 60 {P1_14, UART_1, (SCU_PINIO_UART_RX | 1)},
bogdanm 0:9b334a45a8ff 61 {P1_16, UART_2, (SCU_PINIO_UART_RX | 1)},
bogdanm 0:9b334a45a8ff 62 {P2_1, UART_0, (SCU_PINIO_UART_RX | 1)},
bogdanm 0:9b334a45a8ff 63 {P2_4, UART_3, (SCU_PINIO_UART_RX | 2)},
bogdanm 0:9b334a45a8ff 64 {P2_11, UART_2, (SCU_PINIO_UART_RX | 2)},
bogdanm 0:9b334a45a8ff 65 {P3_5, UART_1, (SCU_PINIO_UART_RX | 4)},
bogdanm 0:9b334a45a8ff 66 {P4_2, UART_3, (SCU_PINIO_UART_RX | 6)},
bogdanm 0:9b334a45a8ff 67 {P5_7, UART_1, (SCU_PINIO_UART_RX | 4)},
bogdanm 0:9b334a45a8ff 68 {P6_5, UART_0, (SCU_PINIO_UART_RX | 2)},
bogdanm 0:9b334a45a8ff 69 {P7_2, UART_2, (SCU_PINIO_UART_RX | 6)},
bogdanm 0:9b334a45a8ff 70 {P9_4, UART_3, (SCU_PINIO_UART_RX | 7)},
bogdanm 0:9b334a45a8ff 71 {P9_6, UART_0, (SCU_PINIO_UART_RX | 7)},
bogdanm 0:9b334a45a8ff 72 {PA_2, UART_2, (SCU_PINIO_UART_RX | 3)},
bogdanm 0:9b334a45a8ff 73 {PC_14, UART_1, (SCU_PINIO_UART_RX | 2)},
bogdanm 0:9b334a45a8ff 74 {PE_12, UART_1, (SCU_PINIO_UART_RX | 2)},
bogdanm 0:9b334a45a8ff 75 {PF_3, UART_3, (SCU_PINIO_UART_RX | 1)},
bogdanm 0:9b334a45a8ff 76 {PF_11, UART_0, (SCU_PINIO_UART_RX | 1)},
bogdanm 0:9b334a45a8ff 77 {NC, NC, 0}
bogdanm 0:9b334a45a8ff 78 };
bogdanm 0:9b334a45a8ff 79
bogdanm 0:9b334a45a8ff 80 #if (DEVICE_SERIAL_FC)
bogdanm 0:9b334a45a8ff 81 // RTS/CTS PinMap for flow control
bogdanm 0:9b334a45a8ff 82 static const PinMap PinMap_UART_RTS[] = {
bogdanm 0:9b334a45a8ff 83 {P1_9, UART_1, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 84 {P5_2, UART_1, (SCU_PINIO_FAST | 4)},
bogdanm 0:9b334a45a8ff 85 {PC_3, UART_1, (SCU_PINIO_FAST | 2)},
bogdanm 0:9b334a45a8ff 86 {PE_5, UART_1, (SCU_PINIO_FAST | 2)},
bogdanm 0:9b334a45a8ff 87 {NC, NC, 0}
bogdanm 0:9b334a45a8ff 88 };
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90 static const PinMap PinMap_UART_CTS[] = {
bogdanm 0:9b334a45a8ff 91 {P1_11, UART_1, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 92 {P5_4, UART_1, (SCU_PINIO_FAST | 4),
bogdanm 0:9b334a45a8ff 93 {PC_2, UART_1, (SCU_PINIO_FAST | 2)},
bogdanm 0:9b334a45a8ff 94 {PE_7, UART_1, (SCU_PINIO_FAST | 2)},
bogdanm 0:9b334a45a8ff 95 {NC, NC, 0}
bogdanm 0:9b334a45a8ff 96 };
bogdanm 0:9b334a45a8ff 97 #endif
bogdanm 0:9b334a45a8ff 98
bogdanm 0:9b334a45a8ff 99 static uart_irq_handler irq_handler;
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 int stdio_uart_inited = 0;
bogdanm 0:9b334a45a8ff 102 serial_t stdio_uart;
bogdanm 0:9b334a45a8ff 103
bogdanm 0:9b334a45a8ff 104 struct serial_global_data_s {
bogdanm 0:9b334a45a8ff 105 uint32_t serial_irq_id;
bogdanm 0:9b334a45a8ff 106 gpio_t sw_rts, sw_cts;
bogdanm 0:9b334a45a8ff 107 uint8_t count, rx_irq_set_flow, rx_irq_set_api;
bogdanm 0:9b334a45a8ff 108 };
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 static struct serial_global_data_s uart_data[UART_NUM];
bogdanm 0:9b334a45a8ff 111
bogdanm 0:9b334a45a8ff 112 void serial_init(serial_t *obj, PinName tx, PinName rx) {
bogdanm 0:9b334a45a8ff 113 int is_stdio_uart = 0;
bogdanm 0:9b334a45a8ff 114
bogdanm 0:9b334a45a8ff 115 // determine the UART to use
bogdanm 0:9b334a45a8ff 116 UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
bogdanm 0:9b334a45a8ff 117 UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
bogdanm 0:9b334a45a8ff 118 UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
bogdanm 0:9b334a45a8ff 119 if ((int)uart == NC) {
bogdanm 0:9b334a45a8ff 120 error("Serial pinout mapping failed");
bogdanm 0:9b334a45a8ff 121 }
bogdanm 0:9b334a45a8ff 122
bogdanm 0:9b334a45a8ff 123 obj->uart = (LPC_USART_T *)uart;
bogdanm 0:9b334a45a8ff 124
bogdanm 0:9b334a45a8ff 125 // enable fifos and default rx trigger level
bogdanm 0:9b334a45a8ff 126 obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
bogdanm 0:9b334a45a8ff 127 | 0 << 1 // Rx Fifo Reset
bogdanm 0:9b334a45a8ff 128 | 0 << 2 // Tx Fifo Reset
bogdanm 0:9b334a45a8ff 129 | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
bogdanm 0:9b334a45a8ff 130
bogdanm 0:9b334a45a8ff 131 // disable irqs
bogdanm 0:9b334a45a8ff 132 obj->uart->IER = 0 << 0 // Rx Data available irq enable
bogdanm 0:9b334a45a8ff 133 | 0 << 1 // Tx Fifo empty irq enable
bogdanm 0:9b334a45a8ff 134 | 0 << 2; // Rx Line Status irq enable
bogdanm 0:9b334a45a8ff 135
bogdanm 0:9b334a45a8ff 136 // set default baud rate and format
mbed_official 42:367d7b10ab62 137 serial_baud (obj, 9600);
bogdanm 0:9b334a45a8ff 138 serial_format(obj, 8, ParityNone, 1);
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 // pinout the chosen uart
bogdanm 0:9b334a45a8ff 141 pinmap_pinout(tx, PinMap_UART_TX);
bogdanm 0:9b334a45a8ff 142 pinmap_pinout(rx, PinMap_UART_RX);
bogdanm 0:9b334a45a8ff 143
bogdanm 0:9b334a45a8ff 144 // set rx/tx pins in PullUp mode
bogdanm 0:9b334a45a8ff 145 if (tx != NC) {
bogdanm 0:9b334a45a8ff 146 pin_mode(tx, PullUp);
bogdanm 0:9b334a45a8ff 147 }
bogdanm 0:9b334a45a8ff 148 if (rx != NC) {
bogdanm 0:9b334a45a8ff 149 pin_mode(rx, PullUp);
bogdanm 0:9b334a45a8ff 150 }
bogdanm 0:9b334a45a8ff 151
bogdanm 0:9b334a45a8ff 152 switch (uart) {
bogdanm 0:9b334a45a8ff 153 case UART_0: obj->index = 0; break;
bogdanm 0:9b334a45a8ff 154 case UART_1: obj->index = 1; break;
bogdanm 0:9b334a45a8ff 155 case UART_2: obj->index = 2; break;
bogdanm 0:9b334a45a8ff 156 case UART_3: obj->index = 3; break;
bogdanm 0:9b334a45a8ff 157 }
bogdanm 0:9b334a45a8ff 158 uart_data[obj->index].sw_rts.pin = NC;
bogdanm 0:9b334a45a8ff 159 uart_data[obj->index].sw_cts.pin = NC;
bogdanm 0:9b334a45a8ff 160 serial_set_flow_control(obj, FlowControlNone, NC, NC);
bogdanm 0:9b334a45a8ff 161
mbed_official 42:367d7b10ab62 162 is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
mbed_official 42:367d7b10ab62 163
bogdanm 0:9b334a45a8ff 164 if (is_stdio_uart) {
bogdanm 0:9b334a45a8ff 165 stdio_uart_inited = 1;
mbed_official 42:367d7b10ab62 166 serial_baud (obj, STDIO_BAUD);
bogdanm 0:9b334a45a8ff 167 memcpy(&stdio_uart, obj, sizeof(serial_t));
bogdanm 0:9b334a45a8ff 168 }
bogdanm 0:9b334a45a8ff 169 }
bogdanm 0:9b334a45a8ff 170
bogdanm 0:9b334a45a8ff 171 void serial_free(serial_t *obj) {
bogdanm 0:9b334a45a8ff 172 uart_data[obj->index].serial_irq_id = 0;
bogdanm 0:9b334a45a8ff 173 }
bogdanm 0:9b334a45a8ff 174
bogdanm 0:9b334a45a8ff 175 // serial_baud
bogdanm 0:9b334a45a8ff 176 // set the baud rate, taking in to account the current SystemFrequency
bogdanm 0:9b334a45a8ff 177 void serial_baud(serial_t *obj, int baudrate) {
bogdanm 0:9b334a45a8ff 178 uint32_t PCLK = SystemCoreClock;
bogdanm 0:9b334a45a8ff 179
bogdanm 0:9b334a45a8ff 180 // First we check to see if the basic divide with no DivAddVal/MulVal
bogdanm 0:9b334a45a8ff 181 // ratio gives us an integer result. If it does, we set DivAddVal = 0,
bogdanm 0:9b334a45a8ff 182 // MulVal = 1. Otherwise, we search the valid ratio value range to find
bogdanm 0:9b334a45a8ff 183 // the closest match. This could be more elegant, using search methods
bogdanm 0:9b334a45a8ff 184 // and/or lookup tables, but the brute force method is not that much
bogdanm 0:9b334a45a8ff 185 // slower, and is more maintainable.
bogdanm 0:9b334a45a8ff 186 uint16_t DL = PCLK / (16 * baudrate);
bogdanm 0:9b334a45a8ff 187
bogdanm 0:9b334a45a8ff 188 uint8_t DivAddVal = 0;
bogdanm 0:9b334a45a8ff 189 uint8_t MulVal = 1;
bogdanm 0:9b334a45a8ff 190 int hit = 0;
bogdanm 0:9b334a45a8ff 191 uint16_t dlv;
bogdanm 0:9b334a45a8ff 192 uint8_t mv, dav;
bogdanm 0:9b334a45a8ff 193 if ((PCLK % (16 * baudrate)) != 0) { // Checking for zero remainder
bogdanm 0:9b334a45a8ff 194 int err_best = baudrate, b;
bogdanm 0:9b334a45a8ff 195 for (mv = 1; mv < 16 && !hit; mv++)
bogdanm 0:9b334a45a8ff 196 {
bogdanm 0:9b334a45a8ff 197 for (dav = 0; dav < mv; dav++)
bogdanm 0:9b334a45a8ff 198 {
bogdanm 0:9b334a45a8ff 199 // baudrate = PCLK / (16 * dlv * (1 + (DivAdd / Mul))
bogdanm 0:9b334a45a8ff 200 // solving for dlv, we get dlv = mul * PCLK / (16 * baudrate * (divadd + mul))
bogdanm 0:9b334a45a8ff 201 // mul has 4 bits, PCLK has 27 so we have 1 bit headroom which can be used for rounding
bogdanm 0:9b334a45a8ff 202 // for many values of mul and PCLK we have 2 or more bits of headroom which can be used to improve precision
bogdanm 0:9b334a45a8ff 203 // note: X / 32 doesn't round correctly. Instead, we use ((X / 16) + 1) / 2 for correct rounding
bogdanm 0:9b334a45a8ff 204
bogdanm 0:9b334a45a8ff 205 if ((mv * PCLK * 2) & 0x80000000) // 1 bit headroom
bogdanm 0:9b334a45a8ff 206 dlv = ((((2 * mv * PCLK) / (baudrate * (dav + mv))) / 16) + 1) / 2;
bogdanm 0:9b334a45a8ff 207 else // 2 bits headroom, use more precision
bogdanm 0:9b334a45a8ff 208 dlv = ((((4 * mv * PCLK) / (baudrate * (dav + mv))) / 32) + 1) / 2;
bogdanm 0:9b334a45a8ff 209
bogdanm 0:9b334a45a8ff 210 // datasheet says if DLL==DLM==0, then 1 is used instead since divide by zero is ungood
bogdanm 0:9b334a45a8ff 211 if (dlv == 0)
bogdanm 0:9b334a45a8ff 212 dlv = 1;
bogdanm 0:9b334a45a8ff 213
bogdanm 0:9b334a45a8ff 214 // datasheet says if dav > 0 then DL must be >= 2
bogdanm 0:9b334a45a8ff 215 if ((dav > 0) && (dlv < 2))
bogdanm 0:9b334a45a8ff 216 dlv = 2;
bogdanm 0:9b334a45a8ff 217
bogdanm 0:9b334a45a8ff 218 // integer rearrangement of the baudrate equation (with rounding)
bogdanm 0:9b334a45a8ff 219 b = ((PCLK * mv / (dlv * (dav + mv) * 8)) + 1) / 2;
bogdanm 0:9b334a45a8ff 220
bogdanm 0:9b334a45a8ff 221 // check to see how we went
bogdanm 0:9b334a45a8ff 222 b = abs(b - baudrate);
bogdanm 0:9b334a45a8ff 223 if (b < err_best)
bogdanm 0:9b334a45a8ff 224 {
bogdanm 0:9b334a45a8ff 225 err_best = b;
bogdanm 0:9b334a45a8ff 226
bogdanm 0:9b334a45a8ff 227 DL = dlv;
bogdanm 0:9b334a45a8ff 228 MulVal = mv;
bogdanm 0:9b334a45a8ff 229 DivAddVal = dav;
bogdanm 0:9b334a45a8ff 230
bogdanm 0:9b334a45a8ff 231 if (b == baudrate)
bogdanm 0:9b334a45a8ff 232 {
bogdanm 0:9b334a45a8ff 233 hit = 1;
bogdanm 0:9b334a45a8ff 234 break;
bogdanm 0:9b334a45a8ff 235 }
bogdanm 0:9b334a45a8ff 236 }
bogdanm 0:9b334a45a8ff 237 }
bogdanm 0:9b334a45a8ff 238 }
bogdanm 0:9b334a45a8ff 239 }
bogdanm 0:9b334a45a8ff 240
bogdanm 0:9b334a45a8ff 241 // set LCR[DLAB] to enable writing to divider registers
bogdanm 0:9b334a45a8ff 242 obj->uart->LCR |= (1 << 7);
bogdanm 0:9b334a45a8ff 243
bogdanm 0:9b334a45a8ff 244 // set divider values
bogdanm 0:9b334a45a8ff 245 obj->uart->DLM = (DL >> 8) & 0xFF;
bogdanm 0:9b334a45a8ff 246 obj->uart->DLL = (DL >> 0) & 0xFF;
bogdanm 0:9b334a45a8ff 247 obj->uart->FDR = (uint32_t) DivAddVal << 0
bogdanm 0:9b334a45a8ff 248 | (uint32_t) MulVal << 4;
bogdanm 0:9b334a45a8ff 249
bogdanm 0:9b334a45a8ff 250 // clear LCR[DLAB]
bogdanm 0:9b334a45a8ff 251 obj->uart->LCR &= ~(1 << 7);
bogdanm 0:9b334a45a8ff 252 }
bogdanm 0:9b334a45a8ff 253
bogdanm 0:9b334a45a8ff 254 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
bogdanm 0:9b334a45a8ff 255 // 0: 1 stop bits, 1: 2 stop bits
bogdanm 0:9b334a45a8ff 256 if (stop_bits != 1 && stop_bits != 2) {
bogdanm 0:9b334a45a8ff 257 error("Invalid stop bits specified");
bogdanm 0:9b334a45a8ff 258 }
bogdanm 0:9b334a45a8ff 259 stop_bits -= 1;
bogdanm 0:9b334a45a8ff 260
bogdanm 0:9b334a45a8ff 261 // 0: 5 data bits ... 3: 8 data bits
bogdanm 0:9b334a45a8ff 262 if (data_bits < 5 || data_bits > 8) {
bogdanm 0:9b334a45a8ff 263 error("Invalid number of bits (%d) in serial format, should be 5..8", data_bits);
bogdanm 0:9b334a45a8ff 264 }
bogdanm 0:9b334a45a8ff 265 data_bits -= 5;
bogdanm 0:9b334a45a8ff 266
bogdanm 0:9b334a45a8ff 267 int parity_enable, parity_select;
bogdanm 0:9b334a45a8ff 268 switch (parity) {
bogdanm 0:9b334a45a8ff 269 case ParityNone: parity_enable = 0; parity_select = 0; break;
bogdanm 0:9b334a45a8ff 270 case ParityOdd : parity_enable = 1; parity_select = 0; break;
bogdanm 0:9b334a45a8ff 271 case ParityEven: parity_enable = 1; parity_select = 1; break;
bogdanm 0:9b334a45a8ff 272 case ParityForced1: parity_enable = 1; parity_select = 2; break;
bogdanm 0:9b334a45a8ff 273 case ParityForced0: parity_enable = 1; parity_select = 3; break;
bogdanm 0:9b334a45a8ff 274 default:
bogdanm 0:9b334a45a8ff 275 error("Invalid serial parity setting");
bogdanm 0:9b334a45a8ff 276 return;
bogdanm 0:9b334a45a8ff 277 }
bogdanm 0:9b334a45a8ff 278
bogdanm 0:9b334a45a8ff 279 obj->uart->LCR = data_bits << 0
bogdanm 0:9b334a45a8ff 280 | stop_bits << 2
bogdanm 0:9b334a45a8ff 281 | parity_enable << 3
bogdanm 0:9b334a45a8ff 282 | parity_select << 4;
bogdanm 0:9b334a45a8ff 283 }
bogdanm 0:9b334a45a8ff 284
bogdanm 0:9b334a45a8ff 285 /******************************************************************************
bogdanm 0:9b334a45a8ff 286 * INTERRUPTS HANDLING
bogdanm 0:9b334a45a8ff 287 ******************************************************************************/
bogdanm 0:9b334a45a8ff 288 static inline void uart_irq(uint32_t iir, uint32_t index, LPC_USART_T *puart) {
bogdanm 0:9b334a45a8ff 289 // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling
bogdanm 0:9b334a45a8ff 290 SerialIrq irq_type;
bogdanm 0:9b334a45a8ff 291 switch (iir) {
bogdanm 0:9b334a45a8ff 292 case 1: irq_type = TxIrq; break;
bogdanm 0:9b334a45a8ff 293 case 2: irq_type = RxIrq; break;
bogdanm 0:9b334a45a8ff 294 default: return;
bogdanm 0:9b334a45a8ff 295 }
bogdanm 0:9b334a45a8ff 296 if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) {
bogdanm 0:9b334a45a8ff 297 gpio_write(&uart_data[index].sw_rts, 1);
bogdanm 0:9b334a45a8ff 298 // Disable interrupt if it wasn't enabled by other part of the application
bogdanm 0:9b334a45a8ff 299 if (!uart_data[index].rx_irq_set_api)
bogdanm 0:9b334a45a8ff 300 puart->IER &= ~(1 << RxIrq);
bogdanm 0:9b334a45a8ff 301 }
bogdanm 0:9b334a45a8ff 302 if (uart_data[index].serial_irq_id != 0)
bogdanm 0:9b334a45a8ff 303 if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api))
bogdanm 0:9b334a45a8ff 304 irq_handler(uart_data[index].serial_irq_id, irq_type);
bogdanm 0:9b334a45a8ff 305 }
bogdanm 0:9b334a45a8ff 306
bogdanm 0:9b334a45a8ff 307 void uart0_irq() {uart_irq((LPC_USART0->IIR >> 1) & 0x7, 0, (LPC_USART_T*)LPC_USART0);}
bogdanm 0:9b334a45a8ff 308 void uart1_irq() {uart_irq((LPC_UART1->IIR >> 1) & 0x7, 1, (LPC_USART_T*)LPC_UART1);}
bogdanm 0:9b334a45a8ff 309 void uart2_irq() {uart_irq((LPC_USART2->IIR >> 1) & 0x7, 2, (LPC_USART_T*)LPC_USART2);}
bogdanm 0:9b334a45a8ff 310 void uart3_irq() {uart_irq((LPC_USART3->IIR >> 1) & 0x7, 3, (LPC_USART_T*)LPC_USART3);}
bogdanm 0:9b334a45a8ff 311
bogdanm 0:9b334a45a8ff 312 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
bogdanm 0:9b334a45a8ff 313 irq_handler = handler;
bogdanm 0:9b334a45a8ff 314 uart_data[obj->index].serial_irq_id = id;
bogdanm 0:9b334a45a8ff 315 }
bogdanm 0:9b334a45a8ff 316
bogdanm 0:9b334a45a8ff 317 static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) {
bogdanm 0:9b334a45a8ff 318 IRQn_Type irq_n = (IRQn_Type)0;
bogdanm 0:9b334a45a8ff 319 uint32_t vector = 0;
bogdanm 0:9b334a45a8ff 320 switch ((int)obj->uart) {
bogdanm 0:9b334a45a8ff 321 case UART_0: irq_n=USART0_IRQn; vector = (uint32_t)&uart0_irq; break;
bogdanm 0:9b334a45a8ff 322 case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
bogdanm 0:9b334a45a8ff 323 case UART_2: irq_n=USART2_IRQn; vector = (uint32_t)&uart2_irq; break;
bogdanm 0:9b334a45a8ff 324 case UART_3: irq_n=USART3_IRQn; vector = (uint32_t)&uart3_irq; break;
bogdanm 0:9b334a45a8ff 325 }
bogdanm 0:9b334a45a8ff 326
bogdanm 0:9b334a45a8ff 327 if (enable) {
bogdanm 0:9b334a45a8ff 328 obj->uart->IER |= 1 << irq;
bogdanm 0:9b334a45a8ff 329 NVIC_SetVector(irq_n, vector);
bogdanm 0:9b334a45a8ff 330 NVIC_EnableIRQ(irq_n);
bogdanm 0:9b334a45a8ff 331 } else if ((TxIrq == irq) || (uart_data[obj->index].rx_irq_set_api + uart_data[obj->index].rx_irq_set_flow == 0)) { // disable
bogdanm 0:9b334a45a8ff 332 int all_disabled = 0;
bogdanm 0:9b334a45a8ff 333 SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
bogdanm 0:9b334a45a8ff 334 obj->uart->IER &= ~(1 << irq);
bogdanm 0:9b334a45a8ff 335 all_disabled = (obj->uart->IER & (1 << other_irq)) == 0;
bogdanm 0:9b334a45a8ff 336 if (all_disabled)
bogdanm 0:9b334a45a8ff 337 NVIC_DisableIRQ(irq_n);
bogdanm 0:9b334a45a8ff 338 }
bogdanm 0:9b334a45a8ff 339 }
bogdanm 0:9b334a45a8ff 340
bogdanm 0:9b334a45a8ff 341 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
bogdanm 0:9b334a45a8ff 342 if (RxIrq == irq)
bogdanm 0:9b334a45a8ff 343 uart_data[obj->index].rx_irq_set_api = enable;
bogdanm 0:9b334a45a8ff 344 serial_irq_set_internal(obj, irq, enable);
bogdanm 0:9b334a45a8ff 345 }
bogdanm 0:9b334a45a8ff 346
bogdanm 0:9b334a45a8ff 347 #if (DEVICE_SERIAL_FC)
bogdanm 0:9b334a45a8ff 348 static void serial_flow_irq_set(serial_t *obj, uint32_t enable) {
bogdanm 0:9b334a45a8ff 349 uart_data[obj->index].rx_irq_set_flow = enable;
bogdanm 0:9b334a45a8ff 350 serial_irq_set_internal(obj, RxIrq, enable);
bogdanm 0:9b334a45a8ff 351 }
bogdanm 0:9b334a45a8ff 352 #endif
bogdanm 0:9b334a45a8ff 353
bogdanm 0:9b334a45a8ff 354 /******************************************************************************
bogdanm 0:9b334a45a8ff 355 * READ/WRITE
bogdanm 0:9b334a45a8ff 356 ******************************************************************************/
bogdanm 0:9b334a45a8ff 357 int serial_getc(serial_t *obj) {
bogdanm 0:9b334a45a8ff 358 while (!serial_readable(obj));
bogdanm 0:9b334a45a8ff 359 int data = obj->uart->RBR;
bogdanm 0:9b334a45a8ff 360 if (NC != uart_data[obj->index].sw_rts.pin) {
bogdanm 0:9b334a45a8ff 361 gpio_write(&uart_data[obj->index].sw_rts, 0);
bogdanm 0:9b334a45a8ff 362 obj->uart->IER |= 1 << RxIrq;
bogdanm 0:9b334a45a8ff 363 }
bogdanm 0:9b334a45a8ff 364 return data;
bogdanm 0:9b334a45a8ff 365 }
bogdanm 0:9b334a45a8ff 366
bogdanm 0:9b334a45a8ff 367 void serial_putc(serial_t *obj, int c) {
bogdanm 0:9b334a45a8ff 368 while (!serial_writable(obj));
bogdanm 0:9b334a45a8ff 369 obj->uart->THR = c;
bogdanm 0:9b334a45a8ff 370 uart_data[obj->index].count++;
bogdanm 0:9b334a45a8ff 371 }
bogdanm 0:9b334a45a8ff 372
bogdanm 0:9b334a45a8ff 373 int serial_readable(serial_t *obj) {
bogdanm 0:9b334a45a8ff 374 return obj->uart->LSR & 0x01;
bogdanm 0:9b334a45a8ff 375 }
bogdanm 0:9b334a45a8ff 376
bogdanm 0:9b334a45a8ff 377 int serial_writable(serial_t *obj) {
bogdanm 0:9b334a45a8ff 378 int isWritable = 1;
bogdanm 0:9b334a45a8ff 379 if (NC != uart_data[obj->index].sw_cts.pin)
bogdanm 0:9b334a45a8ff 380 isWritable = (gpio_read(&uart_data[obj->index].sw_cts) == 0) && (obj->uart->LSR & 0x40); //If flow control: writable if CTS low + UART done
bogdanm 0:9b334a45a8ff 381 else {
bogdanm 0:9b334a45a8ff 382 if (obj->uart->LSR & 0x20)
bogdanm 0:9b334a45a8ff 383 uart_data[obj->index].count = 0;
bogdanm 0:9b334a45a8ff 384 else if (uart_data[obj->index].count >= 16)
bogdanm 0:9b334a45a8ff 385 isWritable = 0;
bogdanm 0:9b334a45a8ff 386 }
bogdanm 0:9b334a45a8ff 387 return isWritable;
bogdanm 0:9b334a45a8ff 388 }
bogdanm 0:9b334a45a8ff 389
bogdanm 0:9b334a45a8ff 390 void serial_clear(serial_t *obj) {
bogdanm 0:9b334a45a8ff 391 obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
bogdanm 0:9b334a45a8ff 392 | 1 << 1 // rx FIFO reset
bogdanm 0:9b334a45a8ff 393 | 1 << 2 // tx FIFO reset
bogdanm 0:9b334a45a8ff 394 | 0 << 6; // interrupt depth
bogdanm 0:9b334a45a8ff 395 }
bogdanm 0:9b334a45a8ff 396
bogdanm 0:9b334a45a8ff 397 void serial_pinout_tx(PinName tx) {
bogdanm 0:9b334a45a8ff 398 pinmap_pinout(tx, PinMap_UART_TX);
bogdanm 0:9b334a45a8ff 399 }
bogdanm 0:9b334a45a8ff 400
bogdanm 0:9b334a45a8ff 401 void serial_break_set(serial_t *obj) {
bogdanm 0:9b334a45a8ff 402 obj->uart->LCR |= (1 << 6);
bogdanm 0:9b334a45a8ff 403 }
bogdanm 0:9b334a45a8ff 404
bogdanm 0:9b334a45a8ff 405 void serial_break_clear(serial_t *obj) {
bogdanm 0:9b334a45a8ff 406 obj->uart->LCR &= ~(1 << 6);
bogdanm 0:9b334a45a8ff 407 }
bogdanm 0:9b334a45a8ff 408
bogdanm 0:9b334a45a8ff 409 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
bogdanm 0:9b334a45a8ff 410 #if (DEVICE_SERIAL_FC)
bogdanm 0:9b334a45a8ff 411 #endif
bogdanm 0:9b334a45a8ff 412 }