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targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_tim.h@164:2e7515f8c45d, 2017-03-24 (annotated)

Committer:: switches
Date:: Fri Mar 24 15:15:13 2017 +0000
Revision:: 164:2e7515f8c45d
Parent:: 157:ff67d9f36b67

Added low level init to clear IO registers

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	157:ff67d9f36b67	1	/**
<>	157:ff67d9f36b67	2	******************************************************************************
<>	157:ff67d9f36b67	3	* @file stm32f3xx_ll_tim.h
<>	157:ff67d9f36b67	4	* @author MCD Application Team
<>	157:ff67d9f36b67	5	* @version V1.4.0
<>	157:ff67d9f36b67	6	* @date 16-December-2016
<>	157:ff67d9f36b67	7	* @brief Header file of TIM LL module.
<>	157:ff67d9f36b67	8	******************************************************************************
<>	157:ff67d9f36b67	9	* @attention
<>	157:ff67d9f36b67	10	*
<>	157:ff67d9f36b67	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	157:ff67d9f36b67	12	*
<>	157:ff67d9f36b67	13	* Redistribution and use in source and binary forms, with or without modification,
<>	157:ff67d9f36b67	14	* are permitted provided that the following conditions are met:
<>	157:ff67d9f36b67	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	157:ff67d9f36b67	16	* this list of conditions and the following disclaimer.
<>	157:ff67d9f36b67	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	157:ff67d9f36b67	18	* this list of conditions and the following disclaimer in the documentation
<>	157:ff67d9f36b67	19	* and/or other materials provided with the distribution.
<>	157:ff67d9f36b67	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	157:ff67d9f36b67	21	* may be used to endorse or promote products derived from this software
<>	157:ff67d9f36b67	22	* without specific prior written permission.
<>	157:ff67d9f36b67	23	*
<>	157:ff67d9f36b67	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	157:ff67d9f36b67	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	157:ff67d9f36b67	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	157:ff67d9f36b67	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	157:ff67d9f36b67	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	157:ff67d9f36b67	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	157:ff67d9f36b67	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	157:ff67d9f36b67	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	157:ff67d9f36b67	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	157:ff67d9f36b67	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	157:ff67d9f36b67	34	*
<>	157:ff67d9f36b67	35	******************************************************************************
<>	157:ff67d9f36b67	36	*/
<>	157:ff67d9f36b67	37
<>	157:ff67d9f36b67	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	157:ff67d9f36b67	39	#ifndef __STM32F3xx_LL_TIM_H
<>	157:ff67d9f36b67	40	#define __STM32F3xx_LL_TIM_H
<>	157:ff67d9f36b67	41
<>	157:ff67d9f36b67	42	#ifdef __cplusplus
<>	157:ff67d9f36b67	43	extern "C" {
<>	157:ff67d9f36b67	44	#endif
<>	157:ff67d9f36b67	45
<>	157:ff67d9f36b67	46	/* Includes ------------------------------------------------------------------*/
<>	157:ff67d9f36b67	47	#include "stm32f3xx.h"
<>	157:ff67d9f36b67	48
<>	157:ff67d9f36b67	49	/** @addtogroup STM32F3xx_LL_Driver
<>	157:ff67d9f36b67	50	* @{
<>	157:ff67d9f36b67	51	*/
<>	157:ff67d9f36b67	52
<>	157:ff67d9f36b67	53	#if defined (TIM1) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM4) \|\| defined (TIM5) \|\| defined (TIM6) \|\| defined (TIM7) \|\| defined (TIM8) \|\| defined (TIM12) \|\| defined (TIM13) \|\| defined (TIM14) \|\| defined (TIM15) \|\| defined (TIM16) \|\| defined (TIM17) \|\| defined (TIM18) \|\| defined (TIM19) \|\| defined (TIM20)
<>	157:ff67d9f36b67	54
<>	157:ff67d9f36b67	55	/** @defgroup TIM_LL TIM
<>	157:ff67d9f36b67	56	* @{
<>	157:ff67d9f36b67	57	*/
<>	157:ff67d9f36b67	58
<>	157:ff67d9f36b67	59	/* Private types -------------------------------------------------------------*/
<>	157:ff67d9f36b67	60	/* Private variables ---------------------------------------------------------*/
<>	157:ff67d9f36b67	61	/** @defgroup TIM_LL_Private_Variables TIM Private Variables
<>	157:ff67d9f36b67	62	* @{
<>	157:ff67d9f36b67	63	*/
<>	157:ff67d9f36b67	64	static const uint8_t OFFSET_TAB_CCMRx[] =
<>	157:ff67d9f36b67	65	{
<>	157:ff67d9f36b67	66	0x00U, /* 0: TIMx_CH1 */
<>	157:ff67d9f36b67	67	0x00U, /* 1: TIMx_CH1N */
<>	157:ff67d9f36b67	68	0x00U, /* 2: TIMx_CH2 */
<>	157:ff67d9f36b67	69	0x00U, /* 3: TIMx_CH2N */
<>	157:ff67d9f36b67	70	0x04U, /* 4: TIMx_CH3 */
<>	157:ff67d9f36b67	71	0x04U, /* 5: TIMx_CH3N */
<>	157:ff67d9f36b67	72	0x04U, /* 6: TIMx_CH4 */
<>	157:ff67d9f36b67	73	0x3CU, /* 7: TIMx_CH5 */
<>	157:ff67d9f36b67	74	0x3CU /* 8: TIMx_CH6 */
<>	157:ff67d9f36b67	75	};
<>	157:ff67d9f36b67	76
<>	157:ff67d9f36b67	77	static const uint8_t SHIFT_TAB_OCxx[] =
<>	157:ff67d9f36b67	78	{
<>	157:ff67d9f36b67	79	0U, /* 0: OC1M, OC1FE, OC1PE */
<>	157:ff67d9f36b67	80	0U, /* 1: - NA */
<>	157:ff67d9f36b67	81	8U, /* 2: OC2M, OC2FE, OC2PE */
<>	157:ff67d9f36b67	82	0U, /* 3: - NA */
<>	157:ff67d9f36b67	83	0U, /* 4: OC3M, OC3FE, OC3PE */
<>	157:ff67d9f36b67	84	0U, /* 5: - NA */
<>	157:ff67d9f36b67	85	8U, /* 6: OC4M, OC4FE, OC4PE */
<>	157:ff67d9f36b67	86	0U, /* 7: OC5M, OC5FE, OC5PE */
<>	157:ff67d9f36b67	87	8U /* 8: OC6M, OC6FE, OC6PE */
<>	157:ff67d9f36b67	88	};
<>	157:ff67d9f36b67	89
<>	157:ff67d9f36b67	90	static const uint8_t SHIFT_TAB_ICxx[] =
<>	157:ff67d9f36b67	91	{
<>	157:ff67d9f36b67	92	0U, /* 0: CC1S, IC1PSC, IC1F */
<>	157:ff67d9f36b67	93	0U, /* 1: - NA */
<>	157:ff67d9f36b67	94	8U, /* 2: CC2S, IC2PSC, IC2F */
<>	157:ff67d9f36b67	95	0U, /* 3: - NA */
<>	157:ff67d9f36b67	96	0U, /* 4: CC3S, IC3PSC, IC3F */
<>	157:ff67d9f36b67	97	0U, /* 5: - NA */
<>	157:ff67d9f36b67	98	8U, /* 6: CC4S, IC4PSC, IC4F */
<>	157:ff67d9f36b67	99	0U, /* 7: - NA */
<>	157:ff67d9f36b67	100	0U /* 8: - NA */
<>	157:ff67d9f36b67	101	};
<>	157:ff67d9f36b67	102
<>	157:ff67d9f36b67	103	static const uint8_t SHIFT_TAB_CCxP[] =
<>	157:ff67d9f36b67	104	{
<>	157:ff67d9f36b67	105	0U, /* 0: CC1P */
<>	157:ff67d9f36b67	106	2U, /* 1: CC1NP */
<>	157:ff67d9f36b67	107	4U, /* 2: CC2P */
<>	157:ff67d9f36b67	108	6U, /* 3: CC2NP */
<>	157:ff67d9f36b67	109	8U, /* 4: CC3P */
<>	157:ff67d9f36b67	110	10U, /* 5: CC3NP */
<>	157:ff67d9f36b67	111	12U, /* 6: CC4P */
<>	157:ff67d9f36b67	112	16U, /* 7: CC5P */
<>	157:ff67d9f36b67	113	20U /* 8: CC6P */
<>	157:ff67d9f36b67	114	};
<>	157:ff67d9f36b67	115
<>	157:ff67d9f36b67	116	static const uint8_t SHIFT_TAB_OISx[] =
<>	157:ff67d9f36b67	117	{
<>	157:ff67d9f36b67	118	0U, /* 0: OIS1 */
<>	157:ff67d9f36b67	119	1U, /* 1: OIS1N */
<>	157:ff67d9f36b67	120	2U, /* 2: OIS2 */
<>	157:ff67d9f36b67	121	3U, /* 3: OIS2N */
<>	157:ff67d9f36b67	122	4U, /* 4: OIS3 */
<>	157:ff67d9f36b67	123	5U, /* 5: OIS3N */
<>	157:ff67d9f36b67	124	6U, /* 6: OIS4 */
<>	157:ff67d9f36b67	125	8U, /* 7: OIS5 */
<>	157:ff67d9f36b67	126	10U /* 8: OIS6 */
<>	157:ff67d9f36b67	127	};
<>	157:ff67d9f36b67	128	/**
<>	157:ff67d9f36b67	129	* @}
<>	157:ff67d9f36b67	130	*/
<>	157:ff67d9f36b67	131
<>	157:ff67d9f36b67	132
<>	157:ff67d9f36b67	133	/* Private constants ---------------------------------------------------------*/
<>	157:ff67d9f36b67	134	/** @defgroup TIM_LL_Private_Constants TIM Private Constants
<>	157:ff67d9f36b67	135	* @{
<>	157:ff67d9f36b67	136	*/
<>	157:ff67d9f36b67	137
<>	157:ff67d9f36b67	138
<>	157:ff67d9f36b67	139	#define TIMx_OR_RMP_SHIFT (16U)
<>	157:ff67d9f36b67	140	#define TIMx_OR_RMP_MASK (0x0000FFFFU)
<>	157:ff67d9f36b67	141	#if defined(TIM1)
<>	157:ff67d9f36b67	142	#define TIM1_OR_RMP_MASK ((uint32_t)(TIM1_OR_ETR_RMP << TIMx_OR_RMP_SHIFT))
<>	157:ff67d9f36b67	143	#endif /* TIM1 */
<>	157:ff67d9f36b67	144	#if defined (TIM8)
<>	157:ff67d9f36b67	145	#define TIM8_OR_RMP_MASK ((uint32_t)(TIM8_OR_ETR_RMP << TIMx_OR_RMP_SHIFT))
<>	157:ff67d9f36b67	146	#endif /* TIM8 */
<>	157:ff67d9f36b67	147	#if defined(TIM14)
<>	157:ff67d9f36b67	148	#define TIM14_OR_RMP_MASK ((uint32_t)(TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT))
<>	157:ff67d9f36b67	149	#endif /* TIM14 */
<>	157:ff67d9f36b67	150	#if defined(TIM16)
<>	157:ff67d9f36b67	151	#define TIM16_OR_RMP_MASK ((uint32_t)(TIM16_OR_TI1_RMP << TIMx_OR_RMP_SHIFT))
<>	157:ff67d9f36b67	152	#endif /* TIM16 */
<>	157:ff67d9f36b67	153	#if defined(TIM20)
<>	157:ff67d9f36b67	154	#define TIM20_OR_RMP_MASK ((uint32_t)(TIM20_OR_ETR_RMP << TIMx_OR_RMP_SHIFT))
<>	157:ff67d9f36b67	155	#endif /* TIM20 */
<>	157:ff67d9f36b67	156
<>	157:ff67d9f36b67	157	/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
<>	157:ff67d9f36b67	158	#define DT_DELAY_1 ((uint8_t)0x7FU)
<>	157:ff67d9f36b67	159	#define DT_DELAY_2 ((uint8_t)0x3FU)
<>	157:ff67d9f36b67	160	#define DT_DELAY_3 ((uint8_t)0x1FU)
<>	157:ff67d9f36b67	161	#define DT_DELAY_4 ((uint8_t)0x1FU)
<>	157:ff67d9f36b67	162
<>	157:ff67d9f36b67	163	/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
<>	157:ff67d9f36b67	164	#define DT_RANGE_1 ((uint8_t)0x00U)
<>	157:ff67d9f36b67	165	#define DT_RANGE_2 ((uint8_t)0x80U)
<>	157:ff67d9f36b67	166	#define DT_RANGE_3 ((uint8_t)0xC0U)
<>	157:ff67d9f36b67	167	#define DT_RANGE_4 ((uint8_t)0xE0U)
<>	157:ff67d9f36b67	168
<>	157:ff67d9f36b67	169
<>	157:ff67d9f36b67	170	/**
<>	157:ff67d9f36b67	171	* @}
<>	157:ff67d9f36b67	172	*/
<>	157:ff67d9f36b67	173
<>	157:ff67d9f36b67	174
<>	157:ff67d9f36b67	175	/* Private macros ------------------------------------------------------------*/
<>	157:ff67d9f36b67	176	/** @defgroup TIM_LL_Private_Macros TIM Private Macros
<>	157:ff67d9f36b67	177	* @{
<>	157:ff67d9f36b67	178	*/
<>	157:ff67d9f36b67	179	/** @brief Convert channel id into channel index.
<>	157:ff67d9f36b67	180	* @param __CHANNEL__ This parameter can be one of the following values:
<>	157:ff67d9f36b67	181	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	182	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	157:ff67d9f36b67	183	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	184	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	157:ff67d9f36b67	185	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	186	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	157:ff67d9f36b67	187	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	188	* @arg @ref LL_TIM_CHANNEL_CH5
<>	157:ff67d9f36b67	189	* @arg @ref LL_TIM_CHANNEL_CH6
<>	157:ff67d9f36b67	190	* @note CH5 and CH6 channels are not available for all F3 devices
<>	157:ff67d9f36b67	191	* @retval none
<>	157:ff67d9f36b67	192	*/
<>	157:ff67d9f36b67	193	#if defined(TIM_CCR5_CCR5)
<>	157:ff67d9f36b67	194	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
<>	157:ff67d9f36b67	195	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
<>	157:ff67d9f36b67	196	((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
<>	157:ff67d9f36b67	197	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
<>	157:ff67d9f36b67	198	((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
<>	157:ff67d9f36b67	199	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
<>	157:ff67d9f36b67	200	((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
<>	157:ff67d9f36b67	201	((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
<>	157:ff67d9f36b67	202	((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
<>	157:ff67d9f36b67	203	#else
<>	157:ff67d9f36b67	204	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
<>	157:ff67d9f36b67	205	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
<>	157:ff67d9f36b67	206	((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
<>	157:ff67d9f36b67	207	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
<>	157:ff67d9f36b67	208	((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
<>	157:ff67d9f36b67	209	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
<>	157:ff67d9f36b67	210	((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
<>	157:ff67d9f36b67	211	#endif
<>	157:ff67d9f36b67	212
<>	157:ff67d9f36b67	213	/** @brief Calculate the deadtime sampling period(in ps).
<>	157:ff67d9f36b67	214	* @param __TIMCLK__ timer input clock frequency (in Hz).
<>	157:ff67d9f36b67	215	* @param __CKD__ This parameter can be one of the following values:
<>	157:ff67d9f36b67	216	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
<>	157:ff67d9f36b67	217	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
<>	157:ff67d9f36b67	218	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
<>	157:ff67d9f36b67	219	* @retval none
<>	157:ff67d9f36b67	220	*/
<>	157:ff67d9f36b67	221	#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
<>	157:ff67d9f36b67	222	(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
<>	157:ff67d9f36b67	223	((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
<>	157:ff67d9f36b67	224	((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
<>	157:ff67d9f36b67	225	/**
<>	157:ff67d9f36b67	226	* @}
<>	157:ff67d9f36b67	227	*/
<>	157:ff67d9f36b67	228
<>	157:ff67d9f36b67	229
<>	157:ff67d9f36b67	230	/* Exported types ------------------------------------------------------------*/
<>	157:ff67d9f36b67	231	#if defined(USE_FULL_LL_DRIVER)
<>	157:ff67d9f36b67	232	/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
<>	157:ff67d9f36b67	233	* @{
<>	157:ff67d9f36b67	234	*/
<>	157:ff67d9f36b67	235
<>	157:ff67d9f36b67	236	/**
<>	157:ff67d9f36b67	237	* @brief TIM Time Base configuration structure definition.
<>	157:ff67d9f36b67	238	*/
<>	157:ff67d9f36b67	239	typedef struct
<>	157:ff67d9f36b67	240	{
<>	157:ff67d9f36b67	241	uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
<>	157:ff67d9f36b67	242	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
<>	157:ff67d9f36b67	243
<>	157:ff67d9f36b67	244	This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
<>	157:ff67d9f36b67	245
<>	157:ff67d9f36b67	246	uint32_t CounterMode; /*!< Specifies the counter mode.
<>	157:ff67d9f36b67	247	This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
<>	157:ff67d9f36b67	248
<>	157:ff67d9f36b67	249	This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
<>	157:ff67d9f36b67	250
<>	157:ff67d9f36b67	251	uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
<>	157:ff67d9f36b67	252	Auto-Reload Register at the next update event.
<>	157:ff67d9f36b67	253	This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
<>	157:ff67d9f36b67	254	Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
<>	157:ff67d9f36b67	255
<>	157:ff67d9f36b67	256	This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
<>	157:ff67d9f36b67	257
<>	157:ff67d9f36b67	258	uint32_t ClockDivision; /*!< Specifies the clock division.
<>	157:ff67d9f36b67	259	This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
<>	157:ff67d9f36b67	260
<>	157:ff67d9f36b67	261	This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
<>	157:ff67d9f36b67	262
<>	157:ff67d9f36b67	263	uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
<>	157:ff67d9f36b67	264	reaches zero, an update event is generated and counting restarts
<>	157:ff67d9f36b67	265	from the RCR value (N).
<>	157:ff67d9f36b67	266	This means in PWM mode that (N+1) corresponds to:
<>	157:ff67d9f36b67	267	- the number of PWM periods in edge-aligned mode
<>	157:ff67d9f36b67	268	- the number of half PWM period in center-aligned mode
<>	157:ff67d9f36b67	269	This parameter must be a number between 0x00 and 0xFF.
<>	157:ff67d9f36b67	270
<>	157:ff67d9f36b67	271	This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
<>	157:ff67d9f36b67	272	} LL_TIM_InitTypeDef;
<>	157:ff67d9f36b67	273
<>	157:ff67d9f36b67	274	/**
<>	157:ff67d9f36b67	275	* @brief TIM Output Compare configuration structure definition.
<>	157:ff67d9f36b67	276	*/
<>	157:ff67d9f36b67	277	typedef struct
<>	157:ff67d9f36b67	278	{
<>	157:ff67d9f36b67	279	uint32_t OCMode; /*!< Specifies the output mode.
<>	157:ff67d9f36b67	280	This parameter can be a value of @ref TIM_LL_EC_OCMODE.
<>	157:ff67d9f36b67	281
<>	157:ff67d9f36b67	282	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
<>	157:ff67d9f36b67	283
<>	157:ff67d9f36b67	284	uint32_t OCState; /*!< Specifies the TIM Output Compare state.
<>	157:ff67d9f36b67	285	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
<>	157:ff67d9f36b67	286
<>	157:ff67d9f36b67	287	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
<>	157:ff67d9f36b67	288
<>	157:ff67d9f36b67	289	uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
<>	157:ff67d9f36b67	290	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
<>	157:ff67d9f36b67	291
<>	157:ff67d9f36b67	292	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
<>	157:ff67d9f36b67	293
<>	157:ff67d9f36b67	294	uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
<>	157:ff67d9f36b67	295	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
<>	157:ff67d9f36b67	296
<>	157:ff67d9f36b67	297	This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
<>	157:ff67d9f36b67	298
<>	157:ff67d9f36b67	299	uint32_t OCPolarity; /*!< Specifies the output polarity.
<>	157:ff67d9f36b67	300	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
<>	157:ff67d9f36b67	301
<>	157:ff67d9f36b67	302	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
<>	157:ff67d9f36b67	303
<>	157:ff67d9f36b67	304	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
<>	157:ff67d9f36b67	305	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
<>	157:ff67d9f36b67	306
<>	157:ff67d9f36b67	307	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
<>	157:ff67d9f36b67	308
<>	157:ff67d9f36b67	309
<>	157:ff67d9f36b67	310	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<>	157:ff67d9f36b67	311	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
<>	157:ff67d9f36b67	312
<>	157:ff67d9f36b67	313	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
<>	157:ff67d9f36b67	314
<>	157:ff67d9f36b67	315	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<>	157:ff67d9f36b67	316	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
<>	157:ff67d9f36b67	317
<>	157:ff67d9f36b67	318	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
<>	157:ff67d9f36b67	319	} LL_TIM_OC_InitTypeDef;
<>	157:ff67d9f36b67	320
<>	157:ff67d9f36b67	321	/**
<>	157:ff67d9f36b67	322	* @brief TIM Input Capture configuration structure definition.
<>	157:ff67d9f36b67	323	*/
<>	157:ff67d9f36b67	324
<>	157:ff67d9f36b67	325	typedef struct
<>	157:ff67d9f36b67	326	{
<>	157:ff67d9f36b67	327
<>	157:ff67d9f36b67	328	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
<>	157:ff67d9f36b67	329	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
<>	157:ff67d9f36b67	330
<>	157:ff67d9f36b67	331	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
<>	157:ff67d9f36b67	332
<>	157:ff67d9f36b67	333	uint32_t ICActiveInput; /*!< Specifies the input.
<>	157:ff67d9f36b67	334	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
<>	157:ff67d9f36b67	335
<>	157:ff67d9f36b67	336	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
<>	157:ff67d9f36b67	337
<>	157:ff67d9f36b67	338	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
<>	157:ff67d9f36b67	339	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
<>	157:ff67d9f36b67	340
<>	157:ff67d9f36b67	341	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
<>	157:ff67d9f36b67	342
<>	157:ff67d9f36b67	343	uint32_t ICFilter; /*!< Specifies the input capture filter.
<>	157:ff67d9f36b67	344	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
<>	157:ff67d9f36b67	345
<>	157:ff67d9f36b67	346	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
<>	157:ff67d9f36b67	347	} LL_TIM_IC_InitTypeDef;
<>	157:ff67d9f36b67	348
<>	157:ff67d9f36b67	349
<>	157:ff67d9f36b67	350	/**
<>	157:ff67d9f36b67	351	* @brief TIM Encoder interface configuration structure definition.
<>	157:ff67d9f36b67	352	*/
<>	157:ff67d9f36b67	353	typedef struct
<>	157:ff67d9f36b67	354	{
<>	157:ff67d9f36b67	355	uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
<>	157:ff67d9f36b67	356	This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
<>	157:ff67d9f36b67	357
<>	157:ff67d9f36b67	358	This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
<>	157:ff67d9f36b67	359
<>	157:ff67d9f36b67	360	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
<>	157:ff67d9f36b67	361	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
<>	157:ff67d9f36b67	362
<>	157:ff67d9f36b67	363	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
<>	157:ff67d9f36b67	364
<>	157:ff67d9f36b67	365	uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
<>	157:ff67d9f36b67	366	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
<>	157:ff67d9f36b67	367
<>	157:ff67d9f36b67	368	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
<>	157:ff67d9f36b67	369
<>	157:ff67d9f36b67	370	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
<>	157:ff67d9f36b67	371	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
<>	157:ff67d9f36b67	372
<>	157:ff67d9f36b67	373	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
<>	157:ff67d9f36b67	374
<>	157:ff67d9f36b67	375	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
<>	157:ff67d9f36b67	376	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
<>	157:ff67d9f36b67	377
<>	157:ff67d9f36b67	378	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
<>	157:ff67d9f36b67	379
<>	157:ff67d9f36b67	380	uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
<>	157:ff67d9f36b67	381	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
<>	157:ff67d9f36b67	382
<>	157:ff67d9f36b67	383	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
<>	157:ff67d9f36b67	384
<>	157:ff67d9f36b67	385	uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
<>	157:ff67d9f36b67	386	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
<>	157:ff67d9f36b67	387
<>	157:ff67d9f36b67	388	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
<>	157:ff67d9f36b67	389
<>	157:ff67d9f36b67	390	uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
<>	157:ff67d9f36b67	391	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
<>	157:ff67d9f36b67	392
<>	157:ff67d9f36b67	393	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
<>	157:ff67d9f36b67	394
<>	157:ff67d9f36b67	395	uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
<>	157:ff67d9f36b67	396	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
<>	157:ff67d9f36b67	397
<>	157:ff67d9f36b67	398	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
<>	157:ff67d9f36b67	399
<>	157:ff67d9f36b67	400	} LL_TIM_ENCODER_InitTypeDef;
<>	157:ff67d9f36b67	401
<>	157:ff67d9f36b67	402	/**
<>	157:ff67d9f36b67	403	* @brief TIM Hall sensor interface configuration structure definition.
<>	157:ff67d9f36b67	404	*/
<>	157:ff67d9f36b67	405	typedef struct
<>	157:ff67d9f36b67	406	{
<>	157:ff67d9f36b67	407
<>	157:ff67d9f36b67	408	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
<>	157:ff67d9f36b67	409	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
<>	157:ff67d9f36b67	410
<>	157:ff67d9f36b67	411	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
<>	157:ff67d9f36b67	412
<>	157:ff67d9f36b67	413	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
<>	157:ff67d9f36b67	414	Prescaler must be set to get a maximum counter period longer than the
<>	157:ff67d9f36b67	415	time interval between 2 consecutive changes on the Hall inputs.
<>	157:ff67d9f36b67	416	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
<>	157:ff67d9f36b67	417
<>	157:ff67d9f36b67	418	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
<>	157:ff67d9f36b67	419
<>	157:ff67d9f36b67	420	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
<>	157:ff67d9f36b67	421	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
<>	157:ff67d9f36b67	422
<>	157:ff67d9f36b67	423	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
<>	157:ff67d9f36b67	424
<>	157:ff67d9f36b67	425	uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
<>	157:ff67d9f36b67	426	A positive pulse (TRGO event) is generated with a programmable delay every time
<>	157:ff67d9f36b67	427	a change occurs on the Hall inputs.
<>	157:ff67d9f36b67	428	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
<>	157:ff67d9f36b67	429
<>	157:ff67d9f36b67	430	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
<>	157:ff67d9f36b67	431	} LL_TIM_HALLSENSOR_InitTypeDef;
<>	157:ff67d9f36b67	432
<>	157:ff67d9f36b67	433	/**
<>	157:ff67d9f36b67	434	* @brief BDTR (Break and Dead Time) structure definition
<>	157:ff67d9f36b67	435	*/
<>	157:ff67d9f36b67	436	typedef struct
<>	157:ff67d9f36b67	437	{
<>	157:ff67d9f36b67	438	uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
<>	157:ff67d9f36b67	439	This parameter can be a value of @ref TIM_LL_EC_OSSR
<>	157:ff67d9f36b67	440
<>	157:ff67d9f36b67	441	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
<>	157:ff67d9f36b67	442
<>	157:ff67d9f36b67	443	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
<>	157:ff67d9f36b67	444
<>	157:ff67d9f36b67	445	uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
<>	157:ff67d9f36b67	446	This parameter can be a value of @ref TIM_LL_EC_OSSI
<>	157:ff67d9f36b67	447
<>	157:ff67d9f36b67	448	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
<>	157:ff67d9f36b67	449
<>	157:ff67d9f36b67	450	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
<>	157:ff67d9f36b67	451
<>	157:ff67d9f36b67	452	uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
<>	157:ff67d9f36b67	453	This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
<>	157:ff67d9f36b67	454
<>	157:ff67d9f36b67	455	@note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
<>	157:ff67d9f36b67	456	has been written, their content is frozen until the next reset.*/
<>	157:ff67d9f36b67	457
<>	157:ff67d9f36b67	458	uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
<>	157:ff67d9f36b67	459	switching-on of the outputs.
<>	157:ff67d9f36b67	460	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
<>	157:ff67d9f36b67	461
<>	157:ff67d9f36b67	462	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
<>	157:ff67d9f36b67	463
<>	157:ff67d9f36b67	464	@note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
<>	157:ff67d9f36b67	465
<>	157:ff67d9f36b67	466	uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
<>	157:ff67d9f36b67	467	This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
<>	157:ff67d9f36b67	468
<>	157:ff67d9f36b67	469	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
<>	157:ff67d9f36b67	470
<>	157:ff67d9f36b67	471	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
<>	157:ff67d9f36b67	472
<>	157:ff67d9f36b67	473	uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
<>	157:ff67d9f36b67	474	This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
<>	157:ff67d9f36b67	475
<>	157:ff67d9f36b67	476	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
<>	157:ff67d9f36b67	477
<>	157:ff67d9f36b67	478	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
<>	157:ff67d9f36b67	479
<>	157:ff67d9f36b67	480	#if defined(TIM_BDTR_BKF)
<>	157:ff67d9f36b67	481	uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
<>	157:ff67d9f36b67	482	This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
<>	157:ff67d9f36b67	483
<>	157:ff67d9f36b67	484	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
<>	157:ff67d9f36b67	485
<>	157:ff67d9f36b67	486	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
<>	157:ff67d9f36b67	487
<>	157:ff67d9f36b67	488	#endif /* TIM_BDTR_BKF */
<>	157:ff67d9f36b67	489	#if defined(TIM_BDTR_BK2E)
<>	157:ff67d9f36b67	490	uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
<>	157:ff67d9f36b67	491	This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
<>	157:ff67d9f36b67	492
<>	157:ff67d9f36b67	493	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
<>	157:ff67d9f36b67	494
<>	157:ff67d9f36b67	495	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
<>	157:ff67d9f36b67	496
<>	157:ff67d9f36b67	497	uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
<>	157:ff67d9f36b67	498	This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
<>	157:ff67d9f36b67	499
<>	157:ff67d9f36b67	500	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
<>	157:ff67d9f36b67	501
<>	157:ff67d9f36b67	502	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
<>	157:ff67d9f36b67	503
<>	157:ff67d9f36b67	504	uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
<>	157:ff67d9f36b67	505	This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
<>	157:ff67d9f36b67	506
<>	157:ff67d9f36b67	507	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
<>	157:ff67d9f36b67	508
<>	157:ff67d9f36b67	509	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
<>	157:ff67d9f36b67	510
<>	157:ff67d9f36b67	511	#endif /* TIM_BDTR_BK2E */
<>	157:ff67d9f36b67	512	uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
<>	157:ff67d9f36b67	513	This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
<>	157:ff67d9f36b67	514
<>	157:ff67d9f36b67	515	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
<>	157:ff67d9f36b67	516
<>	157:ff67d9f36b67	517	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
<>	157:ff67d9f36b67	518	} LL_TIM_BDTR_InitTypeDef;
<>	157:ff67d9f36b67	519
<>	157:ff67d9f36b67	520	/**
<>	157:ff67d9f36b67	521	* @}
<>	157:ff67d9f36b67	522	*/
<>	157:ff67d9f36b67	523	#endif /* USE_FULL_LL_DRIVER */
<>	157:ff67d9f36b67	524
<>	157:ff67d9f36b67	525	/* Exported constants --------------------------------------------------------*/
<>	157:ff67d9f36b67	526	/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
<>	157:ff67d9f36b67	527	* @{
<>	157:ff67d9f36b67	528	*/
<>	157:ff67d9f36b67	529
<>	157:ff67d9f36b67	530	/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
<>	157:ff67d9f36b67	531	* @brief Flags defines which can be used with LL_TIM_ReadReg function.
<>	157:ff67d9f36b67	532	* @{
<>	157:ff67d9f36b67	533	*/
<>	157:ff67d9f36b67	534	#define LL_TIM_SR_UIF TIM_SR_UIF /!< Update interrupt flag /
<>	157:ff67d9f36b67	535	#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /!< Capture/compare 1 interrupt flag /
<>	157:ff67d9f36b67	536	#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /!< Capture/compare 2 interrupt flag /
<>	157:ff67d9f36b67	537	#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /!< Capture/compare 3 interrupt flag /
<>	157:ff67d9f36b67	538	#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /!< Capture/compare 4 interrupt flag /
<>	157:ff67d9f36b67	539	#if defined(TIM_CCMR1_OC1M_3)
<>	157:ff67d9f36b67	540	#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /!< Capture/compare 5 interrupt flag /
<>	157:ff67d9f36b67	541	#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /!< Capture/compare 6 interrupt flag /
<>	157:ff67d9f36b67	542	#endif /* TIM_CCMR1_OC1M_3 */
<>	157:ff67d9f36b67	543	#define LL_TIM_SR_COMIF TIM_SR_COMIF /!< COM interrupt flag /
<>	157:ff67d9f36b67	544	#define LL_TIM_SR_TIF TIM_SR_TIF /!< Trigger interrupt flag /
<>	157:ff67d9f36b67	545	#define LL_TIM_SR_BIF TIM_SR_BIF /!< Break interrupt flag /
<>	157:ff67d9f36b67	546	#define LL_TIM_SR_B2IF TIM_SR_B2IF /!< Second break interrupt flag /
<>	157:ff67d9f36b67	547	#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /!< Capture/Compare 1 overcapture flag /
<>	157:ff67d9f36b67	548	#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /!< Capture/Compare 2 overcapture flag /
<>	157:ff67d9f36b67	549	#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /!< Capture/Compare 3 overcapture flag /
<>	157:ff67d9f36b67	550	#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /!< Capture/Compare 4 overcapture flag /
<>	157:ff67d9f36b67	551	/**
<>	157:ff67d9f36b67	552	* @}
<>	157:ff67d9f36b67	553	*/
<>	157:ff67d9f36b67	554
<>	157:ff67d9f36b67	555	#if defined(USE_FULL_LL_DRIVER)
<>	157:ff67d9f36b67	556	/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
<>	157:ff67d9f36b67	557	* @{
<>	157:ff67d9f36b67	558	*/
<>	157:ff67d9f36b67	559	#define LL_TIM_BREAK_DISABLE ((uint32_t)0x00000000U) /!< Break function disabled /
<>	157:ff67d9f36b67	560	#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /!< Break function enabled /
<>	157:ff67d9f36b67	561	/**
<>	157:ff67d9f36b67	562	* @}
<>	157:ff67d9f36b67	563	*/
<>	157:ff67d9f36b67	564	#if defined(TIM_BDTR_BK2E)
<>	157:ff67d9f36b67	565
<>	157:ff67d9f36b67	566	/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
<>	157:ff67d9f36b67	567	* @{
<>	157:ff67d9f36b67	568	*/
<>	157:ff67d9f36b67	569	#define LL_TIM_BREAK2_DISABLE ((uint32_t)0x00000000U) /!< Break2 function disabled /
<>	157:ff67d9f36b67	570	#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /!< Break2 function enabled /
<>	157:ff67d9f36b67	571	/**
<>	157:ff67d9f36b67	572	* @}
<>	157:ff67d9f36b67	573	*/
<>	157:ff67d9f36b67	574	#endif /* TIM_BDTR_BK2E */
<>	157:ff67d9f36b67	575
<>	157:ff67d9f36b67	576	/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
<>	157:ff67d9f36b67	577	* @{
<>	157:ff67d9f36b67	578	*/
<>	157:ff67d9f36b67	579	#define LL_TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x00000000U) /!< MOE can be set only by software /
<>	157:ff67d9f36b67	580	#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /!< MOE can be set by software or automatically at the next update event /
<>	157:ff67d9f36b67	581	/**
<>	157:ff67d9f36b67	582	* @}
<>	157:ff67d9f36b67	583	*/
<>	157:ff67d9f36b67	584	#endif /* USE_FULL_LL_DRIVER */
<>	157:ff67d9f36b67	585
<>	157:ff67d9f36b67	586	/** @defgroup TIM_LL_EC_IT IT Defines
<>	157:ff67d9f36b67	587	* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
<>	157:ff67d9f36b67	588	* @{
<>	157:ff67d9f36b67	589	*/
<>	157:ff67d9f36b67	590	#define LL_TIM_DIER_UIE TIM_DIER_UIE /!< Update interrupt enable /
<>	157:ff67d9f36b67	591	#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /!< Capture/compare 1 interrupt enable /
<>	157:ff67d9f36b67	592	#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /!< Capture/compare 2 interrupt enable /
<>	157:ff67d9f36b67	593	#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /!< Capture/compare 3 interrupt enable /
<>	157:ff67d9f36b67	594	#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /!< Capture/compare 4 interrupt enable /
<>	157:ff67d9f36b67	595	#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /!< COM interrupt enable /
<>	157:ff67d9f36b67	596	#define LL_TIM_DIER_TIE TIM_DIER_TIE /!< Trigger interrupt enable /
<>	157:ff67d9f36b67	597	#define LL_TIM_DIER_BIE TIM_DIER_BIE /!< Break interrupt enable /
<>	157:ff67d9f36b67	598	/**
<>	157:ff67d9f36b67	599	* @}
<>	157:ff67d9f36b67	600	*/
<>	157:ff67d9f36b67	601
<>	157:ff67d9f36b67	602	/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
<>	157:ff67d9f36b67	603	* @{
<>	157:ff67d9f36b67	604	*/
<>	157:ff67d9f36b67	605	#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request /
<>	157:ff67d9f36b67	606	#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /!< Only counter overflow/underflow generates an update request /
<>	157:ff67d9f36b67	607	/**
<>	157:ff67d9f36b67	608	* @}
<>	157:ff67d9f36b67	609	*/
<>	157:ff67d9f36b67	610
<>	157:ff67d9f36b67	611	/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
<>	157:ff67d9f36b67	612	* @{
<>	157:ff67d9f36b67	613	*/
<>	157:ff67d9f36b67	614	#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /!< Counter is not stopped at update event /
<>	157:ff67d9f36b67	615	#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /!< Counter stops counting at the next update event /
<>	157:ff67d9f36b67	616	/**
<>	157:ff67d9f36b67	617	* @}
<>	157:ff67d9f36b67	618	*/
<>	157:ff67d9f36b67	619
<>	157:ff67d9f36b67	620	/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
<>	157:ff67d9f36b67	621	* @{
<>	157:ff67d9f36b67	622	*/
<>	157:ff67d9f36b67	623	#define LL_TIM_COUNTERMODE_UP 0x00000000U /!<Counter used as upcounter /
<>	157:ff67d9f36b67	624	#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as downcounter /
<>	157:ff67d9f36b67	625	#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. /
<>	157:ff67d9f36b67	626	#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up /
<>	157:ff67d9f36b67	627	#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. /
<>	157:ff67d9f36b67	628	/**
<>	157:ff67d9f36b67	629	* @}
<>	157:ff67d9f36b67	630	*/
<>	157:ff67d9f36b67	631
<>	157:ff67d9f36b67	632	/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
<>	157:ff67d9f36b67	633	* @{
<>	157:ff67d9f36b67	634	*/
<>	157:ff67d9f36b67	635	#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /!< tDTS=tCK_INT /
<>	157:ff67d9f36b67	636	#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< tDTS=2tCK_INT */
<>	157:ff67d9f36b67	637	#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< tDTS=4tCK_INT */
<>	157:ff67d9f36b67	638	/**
<>	157:ff67d9f36b67	639	* @}
<>	157:ff67d9f36b67	640	*/
<>	157:ff67d9f36b67	641
<>	157:ff67d9f36b67	642	/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
<>	157:ff67d9f36b67	643	* @{
<>	157:ff67d9f36b67	644	*/
<>	157:ff67d9f36b67	645	#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /!< Timer counter counts up /
<>	157:ff67d9f36b67	646	#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /!< Timer counter counts down /
<>	157:ff67d9f36b67	647	/**
<>	157:ff67d9f36b67	648	* @}
<>	157:ff67d9f36b67	649	*/
<>	157:ff67d9f36b67	650
<>	157:ff67d9f36b67	651	/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
<>	157:ff67d9f36b67	652	* @{
<>	157:ff67d9f36b67	653	*/
<>	157:ff67d9f36b67	654	#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /!< Capture/compare control bits are updated by setting the COMG bit only /
<>	157:ff67d9f36b67	655	#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) /
<>	157:ff67d9f36b67	656	/**
<>	157:ff67d9f36b67	657	* @}
<>	157:ff67d9f36b67	658	*/
<>	157:ff67d9f36b67	659
<>	157:ff67d9f36b67	660	/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
<>	157:ff67d9f36b67	661	* @{
<>	157:ff67d9f36b67	662	*/
<>	157:ff67d9f36b67	663	#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /!< CCx DMA request sent when CCx event occurs /
<>	157:ff67d9f36b67	664	#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
<>	157:ff67d9f36b67	665	/**
<>	157:ff67d9f36b67	666	* @}
<>	157:ff67d9f36b67	667	*/
<>	157:ff67d9f36b67	668
<>	157:ff67d9f36b67	669	/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
<>	157:ff67d9f36b67	670	* @{
<>	157:ff67d9f36b67	671	*/
<>	157:ff67d9f36b67	672	#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /!< LOCK OFF - No bit is write protected /
<>	157:ff67d9f36b67	673	#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /!< LOCK Level 1 /
<>	157:ff67d9f36b67	674	#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /!< LOCK Level 2 /
<>	157:ff67d9f36b67	675	#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /!< LOCK Level 3 /
<>	157:ff67d9f36b67	676	/**
<>	157:ff67d9f36b67	677	* @}
<>	157:ff67d9f36b67	678	*/
<>	157:ff67d9f36b67	679
<>	157:ff67d9f36b67	680	/** @defgroup TIM_LL_EC_CHANNEL Channel
<>	157:ff67d9f36b67	681	* @{
<>	157:ff67d9f36b67	682	*/
<>	157:ff67d9f36b67	683	#if defined(TIM_CCMR1_OC1M_3)
<>	157:ff67d9f36b67	684	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
<>	157:ff67d9f36b67	685	#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /!< Timer complementary output channel 1 /
<>	157:ff67d9f36b67	686	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
<>	157:ff67d9f36b67	687	#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /!< Timer complementary output channel 2 /
<>	157:ff67d9f36b67	688	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
<>	157:ff67d9f36b67	689	#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /!< Timer complementary output channel 3 /
<>	157:ff67d9f36b67	690	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
<>	157:ff67d9f36b67	691	#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /!< Timer output channel 5 /
<>	157:ff67d9f36b67	692	#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /!< Timer output channel 6 /
<>	157:ff67d9f36b67	693	#else
<>	157:ff67d9f36b67	694	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
<>	157:ff67d9f36b67	695	#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /!< Timer complementary output channel 1 /
<>	157:ff67d9f36b67	696	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
<>	157:ff67d9f36b67	697	#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /!< Timer complementary output channel 2 /
<>	157:ff67d9f36b67	698	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
<>	157:ff67d9f36b67	699	#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /!< Timer complementary output channel 3 /
<>	157:ff67d9f36b67	700	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
<>	157:ff67d9f36b67	701	#endif
<>	157:ff67d9f36b67	702	/**
<>	157:ff67d9f36b67	703	* @}
<>	157:ff67d9f36b67	704	*/
<>	157:ff67d9f36b67	705
<>	157:ff67d9f36b67	706	#if defined(USE_FULL_LL_DRIVER)
<>	157:ff67d9f36b67	707	/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
<>	157:ff67d9f36b67	708	* @{
<>	157:ff67d9f36b67	709	*/
<>	157:ff67d9f36b67	710	#define LL_TIM_OCSTATE_DISABLE 0x00000000U /!< OCx is not active /
<>	157:ff67d9f36b67	711	#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /!< OCx signal is output on the corresponding output pin /
<>	157:ff67d9f36b67	712	/**
<>	157:ff67d9f36b67	713	* @}
<>	157:ff67d9f36b67	714	*/
<>	157:ff67d9f36b67	715	#endif /* USE_FULL_LL_DRIVER */
<>	157:ff67d9f36b67	716
<>	157:ff67d9f36b67	717	/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
<>	157:ff67d9f36b67	718	* @{
<>	157:ff67d9f36b67	719	*/
<>	157:ff67d9f36b67	720	#define LL_TIM_OCMODE_FROZEN 0x00000000U /!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level /
<>	157:ff67d9f36b67	721	#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!<OCyREF is forced high on compare match/
<>	157:ff67d9f36b67	722	#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!<OCyREF is forced low on compare match/
<>	157:ff67d9f36b67	723	#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<OCyREF toggles on compare match/
<>	157:ff67d9f36b67	724	#define LL_TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) /!<OCyREF is forced low/
<>	157:ff67d9f36b67	725	#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!<OCyREF is forced high/
<>	157:ff67d9f36b67	726	#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active./
<>	157:ff67d9f36b67	727	#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive/
<>	157:ff67d9f36b67	728	#if defined(TIM_CCMR1_OC1M_3)
<>	157:ff67d9f36b67	729	#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /!<Retrigerrable OPM mode 1/
<>	157:ff67d9f36b67	730	#define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0) /!<Retrigerrable OPM mode 2/
<>	157:ff67d9f36b67	731	#endif
<>	157:ff67d9f36b67	732	#if defined(TIM_CCMR1_OC1M_3)
<>	157:ff67d9f36b67	733	#define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_2) /!<Combined PWM mode 1/
<>	157:ff67d9f36b67	734	#define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2) /!<Combined PWM mode 2/
<>	157:ff67d9f36b67	735	#endif
<>	157:ff67d9f36b67	736	#if defined(TIM_CCMR1_OC1M_3)
<>	157:ff67d9f36b67	737	#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2) /!<Asymmetric PWM mode 1/
<>	157:ff67d9f36b67	738	#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M) /!<Asymmetric PWM mode 2/
<>	157:ff67d9f36b67	739	#endif
<>	157:ff67d9f36b67	740	/**
<>	157:ff67d9f36b67	741	* @}
<>	157:ff67d9f36b67	742	*/
<>	157:ff67d9f36b67	743
<>	157:ff67d9f36b67	744	/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
<>	157:ff67d9f36b67	745	* @{
<>	157:ff67d9f36b67	746	*/
<>	157:ff67d9f36b67	747	#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /!< OCxactive high/
<>	157:ff67d9f36b67	748	#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< OCxactive low/
<>	157:ff67d9f36b67	749	/**
<>	157:ff67d9f36b67	750	* @}
<>	157:ff67d9f36b67	751	*/
<>	157:ff67d9f36b67	752
<>	157:ff67d9f36b67	753	/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
<>	157:ff67d9f36b67	754	* @{
<>	157:ff67d9f36b67	755	*/
<>	157:ff67d9f36b67	756	#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /!<OCx=0 (after a dead-time if OC is implemented) when MOE=0/
<>	157:ff67d9f36b67	757	#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /!<OCx=1 (after a dead-time if OC is implemented) when MOE=0/
<>	157:ff67d9f36b67	758	/**
<>	157:ff67d9f36b67	759	* @}
<>	157:ff67d9f36b67	760	*/
<>	157:ff67d9f36b67	761
<>	157:ff67d9f36b67	762	#if defined(TIM_CCR5_CCR5)
<>	157:ff67d9f36b67	763	/** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
<>	157:ff67d9f36b67	764	* @{
<>	157:ff67d9f36b67	765	*/
<>	157:ff67d9f36b67	766	#define LL_TIM_GROUPCH5_NONE 0x00000000U /!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC /
<>	157:ff67d9f36b67	767	#define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /!< OC1REFC is the logical AND of OC1REFC and OC5REF /
<>	157:ff67d9f36b67	768	#define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /!< OC2REFC is the logical AND of OC2REFC and OC5REF /
<>	157:ff67d9f36b67	769	#define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /!< OC3REFC is the logical AND of OC3REFC and OC5REF /
<>	157:ff67d9f36b67	770	/**
<>	157:ff67d9f36b67	771	* @}
<>	157:ff67d9f36b67	772	*/
<>	157:ff67d9f36b67	773	#endif /* TIM_CCR5_CCR5 */
<>	157:ff67d9f36b67	774
<>	157:ff67d9f36b67	775	/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
<>	157:ff67d9f36b67	776	* @{
<>	157:ff67d9f36b67	777	*/
<>	157:ff67d9f36b67	778	#define LL_TIM_ACTIVEINPUT_DIRECTTI TIM_CCMR1_CC1S_0 << 16U /!< ICx is mapped on TIx /
<>	157:ff67d9f36b67	779	#define LL_TIM_ACTIVEINPUT_INDIRECTTI TIM_CCMR1_CC1S_1 << 16U /!< ICx is mapped on TIy /
<>	157:ff67d9f36b67	780	#define LL_TIM_ACTIVEINPUT_TRC TIM_CCMR1_CC1S << 16U /!< ICx is mapped on TRC /
<>	157:ff67d9f36b67	781	/**
<>	157:ff67d9f36b67	782	* @}
<>	157:ff67d9f36b67	783	*/
<>	157:ff67d9f36b67	784
<>	157:ff67d9f36b67	785	/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
<>	157:ff67d9f36b67	786	* @{
<>	157:ff67d9f36b67	787	*/
<>	157:ff67d9f36b67	788	#define LL_TIM_ICPSC_DIV1 0x00000000U /!< No prescaler, capture is done each time an edge is detected on the capture input /
<>	157:ff67d9f36b67	789	#define LL_TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 << 16U /!< Capture is done once every 2 events /
<>	157:ff67d9f36b67	790	#define LL_TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 << 16U /!< Capture is done once every 4 events /
<>	157:ff67d9f36b67	791	#define LL_TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC << 16U /!< Capture is done once every 8 events /
<>	157:ff67d9f36b67	792	/**
<>	157:ff67d9f36b67	793	* @}
<>	157:ff67d9f36b67	794	*/
<>	157:ff67d9f36b67	795
<>	157:ff67d9f36b67	796	/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
<>	157:ff67d9f36b67	797	* @{
<>	157:ff67d9f36b67	798	*/
<>	157:ff67d9f36b67	799	#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
<>	157:ff67d9f36b67	800	#define LL_TIM_IC_FILTER_FDIV1_N2 TIM_CCMR1_IC1F_0 << 16U /!< fSAMPLING=fCK_INT, N=2 /
<>	157:ff67d9f36b67	801	#define LL_TIM_IC_FILTER_FDIV1_N4 TIM_CCMR1_IC1F_1 << 16U /!< fSAMPLING=fCK_INT, N=4 /
<>	157:ff67d9f36b67	802	#define LL_TIM_IC_FILTER_FDIV1_N8 (TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U /!< fSAMPLING=fCK_INT, N=8 /
<>	157:ff67d9f36b67	803	#define LL_TIM_IC_FILTER_FDIV2_N6 TIM_CCMR1_IC1F_2 << 16U /!< fSAMPLING=fDTS/2, N=6 /
<>	157:ff67d9f36b67	804	#define LL_TIM_IC_FILTER_FDIV2_N8 (TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U /!< fSAMPLING=fDTS/2, N=8 /
<>	157:ff67d9f36b67	805	#define LL_TIM_IC_FILTER_FDIV4_N6 (TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U /!< fSAMPLING=fDTS/4, N=6 /
<>	157:ff67d9f36b67	806	#define LL_TIM_IC_FILTER_FDIV4_N8 (TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U /!< fSAMPLING=fDTS/4, N=8 /
<>	157:ff67d9f36b67	807	#define LL_TIM_IC_FILTER_FDIV8_N6 TIM_CCMR1_IC1F_3 << 16U /!< fSAMPLING=fDTS/8, N=6 /
<>	157:ff67d9f36b67	808	#define LL_TIM_IC_FILTER_FDIV8_N8 (TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_0) << 16U /!< fSAMPLING=fDTS/8, N=8 /
<>	157:ff67d9f36b67	809	#define LL_TIM_IC_FILTER_FDIV16_N5 (TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1) << 16U /!< fSAMPLING=fDTS/16, N=5 /
<>	157:ff67d9f36b67	810	#define LL_TIM_IC_FILTER_FDIV16_N6 (TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U /!< fSAMPLING=fDTS/16, N=6 /
<>	157:ff67d9f36b67	811	#define LL_TIM_IC_FILTER_FDIV16_N8 (TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2) << 16U /!< fSAMPLING=fDTS/16, N=8 /
<>	157:ff67d9f36b67	812	#define LL_TIM_IC_FILTER_FDIV32_N5 (TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U /!< fSAMPLING=fDTS/32, N=5 /
<>	157:ff67d9f36b67	813	#define LL_TIM_IC_FILTER_FDIV32_N6 (TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U /!< fSAMPLING=fDTS/32, N=6 /
<>	157:ff67d9f36b67	814	#define LL_TIM_IC_FILTER_FDIV32_N8 TIM_CCMR1_IC1F << 16U /!< fSAMPLING=fDTS/32, N=8 /
<>	157:ff67d9f36b67	815	/**
<>	157:ff67d9f36b67	816	* @}
<>	157:ff67d9f36b67	817	*/
<>	157:ff67d9f36b67	818
<>	157:ff67d9f36b67	819	/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
<>	157:ff67d9f36b67	820	* @{
<>	157:ff67d9f36b67	821	*/
<>	157:ff67d9f36b67	822	#define LL_TIM_IC_POLARITY_RISING 0x00000000U /!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted /
<>	157:ff67d9f36b67	823	#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted /
<>	157:ff67d9f36b67	824	#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted /
<>	157:ff67d9f36b67	825	/**
<>	157:ff67d9f36b67	826	* @}
<>	157:ff67d9f36b67	827	*/
<>	157:ff67d9f36b67	828
<>	157:ff67d9f36b67	829	/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
<>	157:ff67d9f36b67	830	* @{
<>	157:ff67d9f36b67	831	*/
<>	157:ff67d9f36b67	832	#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /!< The timer is clocked by the internal clock provided from the RCC /
<>	157:ff67d9f36b67	833	#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0 ) /!< Counter counts at each rising or falling edge on a selected inpu t/
<>	157:ff67d9f36b67	834	#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /!< Counter counts at each rising or falling edge on the external trigger input ETR /
<>	157:ff67d9f36b67	835	/**
<>	157:ff67d9f36b67	836	* @}
<>	157:ff67d9f36b67	837	*/
<>	157:ff67d9f36b67	838
<>	157:ff67d9f36b67	839	/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
<>	157:ff67d9f36b67	840	* @{
<>	157:ff67d9f36b67	841	*/
<>	157:ff67d9f36b67	842	#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level /
<>	157:ff67d9f36b67	843	#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level /
<>	157:ff67d9f36b67	844	#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l /
<>	157:ff67d9f36b67	845	/**
<>	157:ff67d9f36b67	846	* @}
<>	157:ff67d9f36b67	847	*/
<>	157:ff67d9f36b67	848
<>	157:ff67d9f36b67	849	/** @defgroup TIM_LL_EC_TRGO Trigger Output
<>	157:ff67d9f36b67	850	* @{
<>	157:ff67d9f36b67	851	*/
<>	157:ff67d9f36b67	852	#define LL_TIM_TRGO_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output /
<>	157:ff67d9f36b67	853	#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< Counter Enable signal (CNT_EN) is used as trigger output /
<>	157:ff67d9f36b67	854	#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output /
<>	157:ff67d9f36b67	855	#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< CC1 capture or a compare match is used as trigger output /
<>	157:ff67d9f36b67	856	#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output /
<>	157:ff67d9f36b67	857	#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output /
<>	157:ff67d9f36b67	858	#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output /
<>	157:ff67d9f36b67	859	#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output /
<>	157:ff67d9f36b67	860	/**
<>	157:ff67d9f36b67	861	* @}
<>	157:ff67d9f36b67	862	*/
<>	157:ff67d9f36b67	863
<>	157:ff67d9f36b67	864	#if defined(TIM_CR2_MMS2)
<>	157:ff67d9f36b67	865	/** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
<>	157:ff67d9f36b67	866	* @{
<>	157:ff67d9f36b67	867	*/
<>	157:ff67d9f36b67	868	#define LL_TIM_TRGO2_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output 2 /
<>	157:ff67d9f36b67	869	#define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /!< Counter Enable signal (CNT_EN) is used as trigger output 2 /
<>	157:ff67d9f36b67	870	#define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /!< Update event is used as trigger output 2 /
<>	157:ff67d9f36b67	871	#define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< CC1 capture or a compare match is used as trigger output 2 /
<>	157:ff67d9f36b67	872	#define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /!< OC1REF signal is used as trigger output 2 /
<>	157:ff67d9f36b67	873	#define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0) /!< OC2REF signal is used as trigger output 2 /
<>	157:ff67d9f36b67	874	#define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1) /!< OC3REF signal is used as trigger output 2 /
<>	157:ff67d9f36b67	875	#define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC4REF signal is used as trigger output 2 /
<>	157:ff67d9f36b67	876	#define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /!< OC5REF signal is used as trigger output 2 /
<>	157:ff67d9f36b67	877	#define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_0) /!< OC6REF signal is used as trigger output 2 /
<>	157:ff67d9f36b67	878	#define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1) /!< OC4REF rising or falling edges are used as trigger output 2 /
<>	157:ff67d9f36b67	879	#define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC6REF rising or falling edges are used as trigger output 2 /
<>	157:ff67d9f36b67	880	#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2) /!< OC4REF or OC6REF rising edges are used as trigger output 2 /
<>	157:ff67d9f36b67	881	#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0) /!< OC4REF rising or OC6REF falling edges are used as trigger output 2 /
<>	157:ff67d9f36b67	882	#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \|TIM_CR2_MMS2_1) /!< OC5REF or OC6REF rising edges are used as trigger output 2 /
<>	157:ff67d9f36b67	883	#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC5REF rising or OC6REF falling edges are used as trigger output 2 /
<>	157:ff67d9f36b67	884	/**
<>	157:ff67d9f36b67	885	* @}
<>	157:ff67d9f36b67	886	*/
<>	157:ff67d9f36b67	887	#endif /* TIM_CR2_MMS2 */
<>	157:ff67d9f36b67	888
<>	157:ff67d9f36b67	889	/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
<>	157:ff67d9f36b67	890	* @{
<>	157:ff67d9f36b67	891	*/
<>	157:ff67d9f36b67	892	#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /!< Slave mode disabled /
<>	157:ff67d9f36b67	893	#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter /
<>	157:ff67d9f36b67	894	#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high /
<>	157:ff67d9f36b67	895	#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI /
<>	157:ff67d9f36b67	896	#if defined (TIM_SMCR_SMS_3)
<>	157:ff67d9f36b67	897	#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter /
<>	157:ff67d9f36b67	898	#endif /* TIM_SMCR_SMS_3 */
<>	157:ff67d9f36b67	899	/**
<>	157:ff67d9f36b67	900	* @}
<>	157:ff67d9f36b67	901	*/
<>	157:ff67d9f36b67	902
<>	157:ff67d9f36b67	903	/** @defgroup TIM_LL_EC_TS Trigger Selection
<>	157:ff67d9f36b67	904	* @{
<>	157:ff67d9f36b67	905	*/
<>	157:ff67d9f36b67	906	#define LL_TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) is used as trigger input /
<>	157:ff67d9f36b67	907	#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) is used as trigger input /
<>	157:ff67d9f36b67	908	#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) is used as trigger input /
<>	157:ff67d9f36b67	909	#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) is used as trigger input /
<>	157:ff67d9f36b67	910	#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) is used as trigger input /
<>	157:ff67d9f36b67	911	#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_0) /!< Filtered Timer Input 1 (TI1FP1) is used as trigger input /
<>	157:ff67d9f36b67	912	#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1) /!< Filtered Timer Input 2 (TI12P2) is used as trigger input /
<>	157:ff67d9f36b67	913	#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_0) /!< Filtered external Trigger (ETRF) is used as trigger input /
<>	157:ff67d9f36b67	914	/**
<>	157:ff67d9f36b67	915	* @}
<>	157:ff67d9f36b67	916	*/
<>	157:ff67d9f36b67	917
<>	157:ff67d9f36b67	918	/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
<>	157:ff67d9f36b67	919	* @{
<>	157:ff67d9f36b67	920	*/
<>	157:ff67d9f36b67	921	#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /!< ETR is non-inverted, active at high level or rising edge /
<>	157:ff67d9f36b67	922	#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /!< ETR is inverted, active at low level or falling edge /
<>	157:ff67d9f36b67	923	/**
<>	157:ff67d9f36b67	924	* @}
<>	157:ff67d9f36b67	925	*/
<>	157:ff67d9f36b67	926
<>	157:ff67d9f36b67	927	/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
<>	157:ff67d9f36b67	928	* @{
<>	157:ff67d9f36b67	929	*/
<>	157:ff67d9f36b67	930	#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /!< ETR prescaler OFF /
<>	157:ff67d9f36b67	931	#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR frequency is divided by 2 /
<>	157:ff67d9f36b67	932	#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR frequency is divided by 4 /
<>	157:ff67d9f36b67	933	#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR frequency is divided by 8 /
<>	157:ff67d9f36b67	934	/**
<>	157:ff67d9f36b67	935	* @}
<>	157:ff67d9f36b67	936	*/
<>	157:ff67d9f36b67	937
<>	157:ff67d9f36b67	938	/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
<>	157:ff67d9f36b67	939	* @{
<>	157:ff67d9f36b67	940	*/
<>	157:ff67d9f36b67	941	#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
<>	157:ff67d9f36b67	942	#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /!< fSAMPLING=fCK_INT, N=2 /
<>	157:ff67d9f36b67	943	#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /!< fSAMPLING=fCK_INT, N=4 /
<>	157:ff67d9f36b67	944	#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fCK_INT, N=8 /
<>	157:ff67d9f36b67	945	#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /!< fSAMPLING=fDTS/2, N=6 /
<>	157:ff67d9f36b67	946	#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/2, N=8 /
<>	157:ff67d9f36b67	947	#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 ) /!< fSAMPLING=fDTS/4, N=6 /
<>	157:ff67d9f36b67	948	#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/4, N=8 /
<>	157:ff67d9f36b67	949	#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /!< fSAMPLING=fDTS/8, N=8 /
<>	157:ff67d9f36b67	950	#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=5 /
<>	157:ff67d9f36b67	951	#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 ) /!< fSAMPLING=fDTS/16, N=6 /
<>	157:ff67d9f36b67	952	#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=8 /
<>	157:ff67d9f36b67	953	#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 ) /!< fSAMPLING=fDTS/16, N=5 /
<>	157:ff67d9f36b67	954	#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/32, N=5 /
<>	157:ff67d9f36b67	955	#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/32, N=6 /
<>	157:ff67d9f36b67	956	#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /!< fSAMPLING=fDTS/32, N=8 /
<>	157:ff67d9f36b67	957	/**
<>	157:ff67d9f36b67	958	* @}
<>	157:ff67d9f36b67	959	*/
<>	157:ff67d9f36b67	960
<>	157:ff67d9f36b67	961
<>	157:ff67d9f36b67	962	/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
<>	157:ff67d9f36b67	963	* @{
<>	157:ff67d9f36b67	964	*/
<>	157:ff67d9f36b67	965	#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /!< Break input BRK is active low /
<>	157:ff67d9f36b67	966	#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /!< Break input BRK is active high /
<>	157:ff67d9f36b67	967	/**
<>	157:ff67d9f36b67	968	* @}
<>	157:ff67d9f36b67	969	*/
<>	157:ff67d9f36b67	970
<>	157:ff67d9f36b67	971	#if defined(TIM_BDTR_BKF)
<>	157:ff67d9f36b67	972	/** @defgroup TIM_LL_EC_BREAK_FILTER break filter
<>	157:ff67d9f36b67	973	* @{
<>	157:ff67d9f36b67	974	*/
<>	157:ff67d9f36b67	975	#define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /!< No filter, BRK acts asynchronously /
<>	157:ff67d9f36b67	976	#define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /!< fSAMPLING=fCK_INT, N=2 /
<>	157:ff67d9f36b67	977	#define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /!< fSAMPLING=fCK_INT, N=4 /
<>	157:ff67d9f36b67	978	#define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /!< fSAMPLING=fCK_INT, N=8 /
<>	157:ff67d9f36b67	979	#define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /!< fSAMPLING=fDTS/2, N=6 /
<>	157:ff67d9f36b67	980	#define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /!< fSAMPLING=fDTS/2, N=8 /
<>	157:ff67d9f36b67	981	#define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /!< fSAMPLING=fDTS/4, N=6 /
<>	157:ff67d9f36b67	982	#define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /!< fSAMPLING=fDTS/4, N=8 /
<>	157:ff67d9f36b67	983	#define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /!< fSAMPLING=fDTS/8, N=6 /
<>	157:ff67d9f36b67	984	#define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /!< fSAMPLING=fDTS/8, N=8 /
<>	157:ff67d9f36b67	985	#define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /!< fSAMPLING=fDTS/16, N=5 /
<>	157:ff67d9f36b67	986	#define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /!< fSAMPLING=fDTS/16, N=6 /
<>	157:ff67d9f36b67	987	#define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /!< fSAMPLING=fDTS/16, N=8 /
<>	157:ff67d9f36b67	988	#define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /!< fSAMPLING=fDTS/32, N=5 /
<>	157:ff67d9f36b67	989	#define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /!< fSAMPLING=fDTS/32, N=6 /
<>	157:ff67d9f36b67	990	#define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /!< fSAMPLING=fDTS/32, N=8 /
<>	157:ff67d9f36b67	991	/**
<>	157:ff67d9f36b67	992	* @}
<>	157:ff67d9f36b67	993	*/
<>	157:ff67d9f36b67	994	#endif /* TIM_BDTR_BKF */
<>	157:ff67d9f36b67	995
<>	157:ff67d9f36b67	996	#if defined(TIM_BDTR_BK2P)
<>	157:ff67d9f36b67	997	/** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
<>	157:ff67d9f36b67	998	* @{
<>	157:ff67d9f36b67	999	*/
<>	157:ff67d9f36b67	1000	#define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /!< Break input BRK2 is active low /
<>	157:ff67d9f36b67	1001	#define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /!< Break input BRK2 is active high /
<>	157:ff67d9f36b67	1002	/**
<>	157:ff67d9f36b67	1003	* @}
<>	157:ff67d9f36b67	1004	*/
<>	157:ff67d9f36b67	1005	#endif /* TIM_BDTR_BK2P */
<>	157:ff67d9f36b67	1006
<>	157:ff67d9f36b67	1007	#if defined(TIM_BDTR_BK2F)
<>	157:ff67d9f36b67	1008	/** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
<>	157:ff67d9f36b67	1009	* @{
<>	157:ff67d9f36b67	1010	*/
<>	157:ff67d9f36b67	1011	#define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /!< No filter, BRK acts asynchronously /
<>	157:ff67d9f36b67	1012	#define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /!< fSAMPLING=fCK_INT, N=2 /
<>	157:ff67d9f36b67	1013	#define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /!< fSAMPLING=fCK_INT, N=4 /
<>	157:ff67d9f36b67	1014	#define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /!< fSAMPLING=fCK_INT, N=8 /
<>	157:ff67d9f36b67	1015	#define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /!< fSAMPLING=fDTS/2, N=6 /
<>	157:ff67d9f36b67	1016	#define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /!< fSAMPLING=fDTS/2, N=8 /
<>	157:ff67d9f36b67	1017	#define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /!< fSAMPLING=fDTS/4, N=6 /
<>	157:ff67d9f36b67	1018	#define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /!< fSAMPLING=fDTS/4, N=8 /
<>	157:ff67d9f36b67	1019	#define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /!< fSAMPLING=fDTS/8, N=6 /
<>	157:ff67d9f36b67	1020	#define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /!< fSAMPLING=fDTS/8, N=8 /
<>	157:ff67d9f36b67	1021	#define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /!< fSAMPLING=fDTS/16, N=5 /
<>	157:ff67d9f36b67	1022	#define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /!< fSAMPLING=fDTS/16, N=6 /
<>	157:ff67d9f36b67	1023	#define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /!< fSAMPLING=fDTS/16, N=8 /
<>	157:ff67d9f36b67	1024	#define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /!< fSAMPLING=fDTS/32, N=5 /
<>	157:ff67d9f36b67	1025	#define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /!< fSAMPLING=fDTS/32, N=6 /
<>	157:ff67d9f36b67	1026	#define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /!< fSAMPLING=fDTS/32, N=8 /
<>	157:ff67d9f36b67	1027	/**
<>	157:ff67d9f36b67	1028	* @}
<>	157:ff67d9f36b67	1029	*/
<>	157:ff67d9f36b67	1030	#endif /* TIM_BDTR_BK2F */
<>	157:ff67d9f36b67	1031
<>	157:ff67d9f36b67	1032	/** @defgroup TIM_LL_EC_OSSI OSSI
<>	157:ff67d9f36b67	1033	* @{
<>	157:ff67d9f36b67	1034	*/
<>	157:ff67d9f36b67	1035	#define LL_TIM_OSSI_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
<>	157:ff67d9f36b67	1036	#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime /
<>	157:ff67d9f36b67	1037	/**
<>	157:ff67d9f36b67	1038	* @}
<>	157:ff67d9f36b67	1039	*/
<>	157:ff67d9f36b67	1040
<>	157:ff67d9f36b67	1041	/** @defgroup TIM_LL_EC_OSSR OSSR
<>	157:ff67d9f36b67	1042	* @{
<>	157:ff67d9f36b67	1043	*/
<>	157:ff67d9f36b67	1044	#define LL_TIM_OSSR_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
<>	157:ff67d9f36b67	1045	#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 /
<>	157:ff67d9f36b67	1046	/**
<>	157:ff67d9f36b67	1047	* @}
<>	157:ff67d9f36b67	1048	*/
<>	157:ff67d9f36b67	1049
<>	157:ff67d9f36b67	1050
<>	157:ff67d9f36b67	1051	/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
<>	157:ff67d9f36b67	1052	* @{
<>	157:ff67d9f36b67	1053	*/
<>	157:ff67d9f36b67	1054	#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /!< TIMx_CR1 register is the DMA base address for DMA burst /
<>	157:ff67d9f36b67	1055	#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /!< TIMx_CR2 register is the DMA base address for DMA burst /
<>	157:ff67d9f36b67	1056	#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /!< TIMx_SMCR register is the DMA base address for DMA burst /
<>	157:ff67d9f36b67	1057	#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_DIER register is the DMA base address for DMA burst /
<>	157:ff67d9f36b67	1058	#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /!< TIMx_SR register is the DMA base address for DMA burst /
<>	157:ff67d9f36b67	1059	#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_EGR register is the DMA base address for DMA burst /
<>	157:ff67d9f36b67	1060	#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCMR1 register is the DMA base address for DMA burst /
<>	157:ff67d9f36b67	1061	#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCMR2 register is the DMA base address for DMA burst /
<>	157:ff67d9f36b67	1062	#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /!< TIMx_CCER register is the DMA base address for DMA burst /
<>	157:ff67d9f36b67	1063	#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_CNT register is the DMA base address for DMA burst /
<>	157:ff67d9f36b67	1064	#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_PSC register is the DMA base address for DMA burst /
<>	157:ff67d9f36b67	1065	#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_ARR register is the DMA base address for DMA burst /
<>	157:ff67d9f36b67	1066	#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2) /!< TIMx_RCR register is the DMA base address for DMA burst /
<>	157:ff67d9f36b67	1067	#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCR1 register is the DMA base address for DMA burst /
<>	157:ff67d9f36b67	1068	#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR2 register is the DMA base address for DMA burst /
<>	157:ff67d9f36b67	1069	#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR3 register is the DMA base address for DMA burst /
<>	157:ff67d9f36b67	1070	#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /!< TIMx_CCR4 register is the DMA base address for DMA burst /
<>	157:ff67d9f36b67	1071	#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) /!< TIMx_BDTR register is the DMA base address for DMA burst /
<>	157:ff67d9f36b67	1072	#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1) /!< TIMx_CCMR3 register is the DMA base address for DMA burst /
<>	157:ff67d9f36b67	1073	#if defined(TIM_CCR6_CCR6)
<>	157:ff67d9f36b67	1074	#define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR5 register is the DMA base address for DMA burst /
<>	157:ff67d9f36b67	1075	#define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) /!< TIMx_CCR6 register is the DMA base address for DMA burst /
<>	157:ff67d9f36b67	1076	#endif /* TIM_CCR6_CCR6 */
<>	157:ff67d9f36b67	1077	#define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_OR register is the DMA base address for DMA burst /
<>	157:ff67d9f36b67	1078	/**
<>	157:ff67d9f36b67	1079	* @}
<>	157:ff67d9f36b67	1080	*/
<>	157:ff67d9f36b67	1081
<>	157:ff67d9f36b67	1082	/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
<>	157:ff67d9f36b67	1083	* @{
<>	157:ff67d9f36b67	1084	*/
<>	157:ff67d9f36b67	1085	#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /!< Transfer is done to 1 register starting from the DMA burst base address /
<>	157:ff67d9f36b67	1086	#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /!< Transfer is done to 2 registers starting from the DMA burst base address /
<>	157:ff67d9f36b67	1087	#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /!< Transfer is done to 3 registers starting from the DMA burst base address /
<>	157:ff67d9f36b67	1088	#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 4 registers starting from the DMA burst base address /
<>	157:ff67d9f36b67	1089	#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /!< Transfer is done to 5 registers starting from the DMA burst base address /
<>	157:ff67d9f36b67	1090	#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 6 registers starting from the DMA burst base address /
<>	157:ff67d9f36b67	1091	#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 7 registers starting from the DMA burst base address /
<>	157:ff67d9f36b67	1092	#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 1 registers starting from the DMA burst base address /
<>	157:ff67d9f36b67	1093	#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /!< Transfer is done to 9 registers starting from the DMA burst base address /
<>	157:ff67d9f36b67	1094	#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_0) /!< Transfer is done to 10 registers starting from the DMA burst base address /
<>	157:ff67d9f36b67	1095	#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1) /!< Transfer is done to 11 registers starting from the DMA burst base address /
<>	157:ff67d9f36b67	1096	#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 12 registers starting from the DMA burst base address /
<>	157:ff67d9f36b67	1097	#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2) /!< Transfer is done to 13 registers starting from the DMA burst base address /
<>	157:ff67d9f36b67	1098	#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 14 registers starting from the DMA burst base address /
<>	157:ff67d9f36b67	1099	#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 15 registers starting from the DMA burst base address /
<>	157:ff67d9f36b67	1100	#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 16 registers starting from the DMA burst base address /
<>	157:ff67d9f36b67	1101	#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /!< Transfer is done to 17 registers starting from the DMA burst base address /
<>	157:ff67d9f36b67	1102	#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 \| TIM_DCR_DBL_0) /!< Transfer is done to 18 registers starting from the DMA burst base address /
<>	157:ff67d9f36b67	1103	/**
<>	157:ff67d9f36b67	1104	* @}
<>	157:ff67d9f36b67	1105	*/
<>	157:ff67d9f36b67	1106
<>	157:ff67d9f36b67	1107	#if defined(TIM1)
<>	157:ff67d9f36b67	1108	/** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP TIM1 External Trigger ADC1 Remap
<>	157:ff67d9f36b67	1109	* @{
<>	157:ff67d9f36b67	1110	*/
<>	157:ff67d9f36b67	1111	#define LL_TIM_TIM1_ETR_ADC1_RMP_NC (0x00000000U \| TIM1_OR_RMP_MASK) /!< TIM1_ETR is not connected to ADC1 analog watchdog x /
<>	157:ff67d9f36b67	1112	#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR_ETR_RMP_0 \| TIM1_OR_RMP_MASK) /!< TIM1_ETR is connected to ADC1 analog watchdog 1 /
<>	157:ff67d9f36b67	1113	#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR_ETR_RMP_1 \| TIM1_OR_RMP_MASK) /!< TIM1_ETR is connected to ADC1 analog watchdog 2 /
<>	157:ff67d9f36b67	1114	#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR_ETR_RMP_0 \| TIM1_OR_ETR_RMP_1\| TIM1_OR_RMP_MASK) /!< TIM1_ETR is connected to ADC1 analog watchdog 3 /
<>	157:ff67d9f36b67	1115	/**
<>	157:ff67d9f36b67	1116	* @}
<>	157:ff67d9f36b67	1117	*/
<>	157:ff67d9f36b67	1118	#if defined(ADC4)
<>	157:ff67d9f36b67	1119	/** @defgroup TIM_LL_EC_TIM1_ETR_ADC3_RMP TIM1 External Trigger ADC4 Remap
<>	157:ff67d9f36b67	1120	* @{
<>	157:ff67d9f36b67	1121	*/
<>	157:ff67d9f36b67	1122	#define LL_TIM_TIM1_ETR_ADC4_RMP_NC (0x00000000U \| TIM1_OR_RMP_MASK) /!< TIM1_ETR is not connected to ADC4 analog watchdog x/
<>	157:ff67d9f36b67	1123	#define LL_TIM_TIM1_ETR_ADC4_RMP_AWD1 (TIM1_OR_ETR_RMP_2 \| TIM1_OR_RMP_MASK) /!< TIM1_ETR is connected to ADC4 analog watchdog 1 /
<>	157:ff67d9f36b67	1124	#define LL_TIM_TIM1_ETR_ADC4_RMP_AWD2 (TIM1_OR_ETR_RMP_3 \| TIM1_OR_RMP_MASK) /!< TIM1_ETR is connected to ADC4 analog watchdog 2 /
<>	157:ff67d9f36b67	1125	#define LL_TIM_TIM1_ETR_ADC4_RMP_AWD3 (TIM1_OR_ETR_RMP_3 \| TIM1_OR_ETR_RMP_2 \| TIM1_OR_RMP_MASK) /!< TIM1_ETR is connected to ADC4 analog watchdog 3 /
<>	157:ff67d9f36b67	1126	/**
<>	157:ff67d9f36b67	1127	* @}
<>	157:ff67d9f36b67	1128	*/
<>	157:ff67d9f36b67	1129	#else
<>	157:ff67d9f36b67	1130	/** @defgroup TIM_LL_EC_TIM1_ETR_ADC2_RMP TIM1 External Trigger ADC3 Remap
<>	157:ff67d9f36b67	1131	* @{
<>	157:ff67d9f36b67	1132	*/
<>	157:ff67d9f36b67	1133	#define LL_TIM_TIM1_ETR_ADC2_RMP_NC (0x00000000U \| TIM1_OR_RMP_MASK) /!< TIM1_ETR is not connected to ADC2 analog watchdog x/
<>	157:ff67d9f36b67	1134	#define LL_TIM_TIM1_ETR_ADC2_RMP_AWD1 (TIM1_OR_ETR_RMP_2 \| TIM1_OR_RMP_MASK) /!< TIM1_ETR is connected to ADC2 analog watchdog 1 /
<>	157:ff67d9f36b67	1135	#define LL_TIM_TIM1_ETR_ADC2_RMP_AWD2 (TIM1_OR_ETR_RMP_3 \| TIM1_OR_RMP_MASK) /!< TIM1_ETR is connected to ADC2 analog watchdog 2 /
<>	157:ff67d9f36b67	1136	#define LL_TIM_TIM1_ETR_ADC2_RMP_AWD3 (TIM1_OR_ETR_RMP_3 \| TIM1_OR_ETR_RMP_2 \| TIM1_OR_RMP_MASK) /!< TIM1_ETR is connected to ADC2 analog watchdog 3 /
<>	157:ff67d9f36b67	1137	/**
<>	157:ff67d9f36b67	1138	* @}
<>	157:ff67d9f36b67	1139	*/
<>	157:ff67d9f36b67	1140	#endif /* ADC4 */
<>	157:ff67d9f36b67	1141	#endif /* TIM1 */
<>	157:ff67d9f36b67	1142	#if defined(TIM8)
<>	157:ff67d9f36b67	1143	/** @defgroup TIM_LL_EC_TIM8_ETR_ADC2_RMP TIM8 External Trigger ADC2 Remap
<>	157:ff67d9f36b67	1144	* @{
<>	157:ff67d9f36b67	1145	*/
<>	157:ff67d9f36b67	1146	#define LL_TIM_TIM8_ETR_ADC2_RMP_NC (0x00000000U \| TIM8_OR_RMP_MASK) /!< TIM8_ETR is not connected to ADC2 analog watchdog x /
<>	157:ff67d9f36b67	1147	#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (TIM8_OR_ETR_RMP_0 \| TIM8_OR_RMP_MASK) /!< TIM8_ETR is connected to ADC2 analog watchdog /
<>	157:ff67d9f36b67	1148	#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (TIM8_OR_ETR_RMP_1 \| TIM8_OR_RMP_MASK) /!< TIM8_ETR is connected to ADC2 analog watchdog 2 /
<>	157:ff67d9f36b67	1149	#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (TIM8_OR_ETR_RMP_0 \| TIM8_OR_ETR_RMP_1 \| TIM8_OR_RMP_MASK) /!< TIM8_ETR is connected to ADC2 analog watchdog 3 /
<>	157:ff67d9f36b67	1150	/**
<>	157:ff67d9f36b67	1151	* @}
<>	157:ff67d9f36b67	1152	*/
<>	157:ff67d9f36b67	1153
<>	157:ff67d9f36b67	1154	/** @defgroup TIM_LL_EC_TIM8_ETR_ADC3_RMP TIM8 External Trigger ADC3 Remap
<>	157:ff67d9f36b67	1155	* @{
<>	157:ff67d9f36b67	1156	*/
<>	157:ff67d9f36b67	1157	#define LL_TIM_TIM8_ETR_ADC3_RMP_NC (0x00000000U \| TIM8_OR_RMP_MASK) /!< TIM8_ETR is not connected to ADC3 analog watchdog x /
<>	157:ff67d9f36b67	1158	#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (TIM8_OR_ETR_RMP_2 \| TIM8_OR_RMP_MASK) /!< TIM8_ETR is connected to ADC3 analog watchdog 1 /
<>	157:ff67d9f36b67	1159	#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (TIM8_OR_ETR_RMP_3 \| TIM8_OR_RMP_MASK) /!< TIM8_ETR is connected to ADC3 analog watchdog 2 /
<>	157:ff67d9f36b67	1160	#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (TIM8_OR_ETR_RMP_2 \| TIM8_OR_ETR_RMP_3 \| TIM8_OR_RMP_MASK) /!< TIM8_ETR is connected to ADC3 analog watchdog 3 /
<>	157:ff67d9f36b67	1161	/**
<>	157:ff67d9f36b67	1162	* @}
<>	157:ff67d9f36b67	1163	*/
<>	157:ff67d9f36b67	1164	#endif /* TIM8 */
<>	157:ff67d9f36b67	1165	#if defined(TIM16)
<>	157:ff67d9f36b67	1166	/** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap
<>	157:ff67d9f36b67	1167	* @{
<>	157:ff67d9f36b67	1168	*/
<>	157:ff67d9f36b67	1169	#define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /!< TIM16 input capture 1 is connected to GPIO /
<>	157:ff67d9f36b67	1170	#define LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR_TI1_RMP_0 \| TIM16_OR_RMP_MASK) /!< TIM16 input capture 1 is connected to RTC wakeup interrupt /
<>	157:ff67d9f36b67	1171	#define LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM16_OR_TI1_RMP_1 \| TIM16_OR_RMP_MASK) /!< TIM16 input capture 1 is connected to HSE/32 clock /
<>	157:ff67d9f36b67	1172	#define LL_TIM_TIM16_TI1_RMP_MCO (TIM16_OR_TI1_RMP_1 \| TIM16_OR_TI1_RMP_0 \| TIM16_OR_RMP_MASK) /!< TIM16 input capture 1 is connected to MCO /
<>	157:ff67d9f36b67	1173	/**
<>	157:ff67d9f36b67	1174	* @}
<>	157:ff67d9f36b67	1175	*/
<>	157:ff67d9f36b67	1176	#endif /* TIM16 */
<>	157:ff67d9f36b67	1177	#if defined(TIM20)
<>	157:ff67d9f36b67	1178	/** @defgroup TIM_LL_EC_TIM20_ETR_ADC3_RMP TIM20 External Trigger ADC3 Remap
<>	157:ff67d9f36b67	1179	* @{
<>	157:ff67d9f36b67	1180	*/
<>	157:ff67d9f36b67	1181	#define LL_TIM_TIM20_ETR_ADC3_RMP_NC (0x00000000U \| TIM20_OR_RMP_MASK) /!< TIM20_ETR is not connected to ADC3 analog watchdog x /
<>	157:ff67d9f36b67	1182	#define LL_TIM_TIM20_ETR_ADC3_RMP_AWD1 (TIM20_OR_ETR_RMP_0 \| TIM20_OR_RMP_MASK) /!< TIM20_ETR is connected to ADC3 analog watchdog /
<>	157:ff67d9f36b67	1183	#define LL_TIM_TIM20_ETR_ADC3_RMP_AWD2 (TIM20_OR_ETR_RMP_1 \| TIM20_OR_RMP_MASK) /!< TIM20_ETR is connected to ADC3 analog watchdog 2 /
<>	157:ff67d9f36b67	1184	#define LL_TIM_TIM20_ETR_ADC3_RMP_AWD3 (TIM20_OR_ETR_RMP_0 \| TIM20_OR_ETR_RMP_1 \| TIM20_OR_RMP_MASK) /!< TIM20_ETR is connected to ADC3 analog watchdog 3 /
<>	157:ff67d9f36b67	1185	/**
<>	157:ff67d9f36b67	1186	* @}
<>	157:ff67d9f36b67	1187	*/
<>	157:ff67d9f36b67	1188
<>	157:ff67d9f36b67	1189	/** @defgroup TIM_LL_EC_TIM20_ETR_ADC4_RMP TIM20 External Trigger ADC4 Remap
<>	157:ff67d9f36b67	1190	* @{
<>	157:ff67d9f36b67	1191	*/
<>	157:ff67d9f36b67	1192	#define LL_TIM_TIM20_ETR_ADC4_RMP_NC (0x00000000U \| TIM20_OR_RMP_MASK) /!< TIM20_ETR is not connected to ADC4 analog watchdog x /
<>	157:ff67d9f36b67	1193	#define LL_TIM_TIM20_ETR_ADC4_RMP_AWD1 (TIM20_OR_ETR_RMP_2 \| TIM20_OR_RMP_MASK) /!< TIM20_ETR is connected to ADC4 analog watchdog 1 /
<>	157:ff67d9f36b67	1194	#define LL_TIM_TIM20_ETR_ADC4_RMP_AWD2 (TIM20_OR_ETR_RMP_3 \| TIM20_OR_RMP_MASK) /!< TIM20_ETR is connected to ADC4 analog watchdog 2 /
<>	157:ff67d9f36b67	1195	#define LL_TIM_TIM20_ETR_ADC4_RMP_AWD3 (TIM20_OR_ETR_RMP_2 \| TIM20_OR_ETR_RMP_3 \| TIM20_OR_RMP_MASK) /!< TIM20_ETR is connected to ADC4 analog watchdog 3 /
<>	157:ff67d9f36b67	1196	/**
<>	157:ff67d9f36b67	1197	* @}
<>	157:ff67d9f36b67	1198	*/
<>	157:ff67d9f36b67	1199	#endif /* TIM20 */
<>	157:ff67d9f36b67	1200	#if defined(TIM14)
<>	157:ff67d9f36b67	1201	/** @defgroup TIM_LL_EC_TIM14_TI1_RMP TIM14 Timer Input1 Remap
<>	157:ff67d9f36b67	1202	* @{
<>	157:ff67d9f36b67	1203	*/
<>	157:ff67d9f36b67	1204	#define LL_TIM_TIM14_TI1_RMP_GPIO (0x00000000U \| TIM14_OR_RMP_MASK) /!< TIM14_TI1 is connected to GPIO /
<>	157:ff67d9f36b67	1205	#define LL_TIM_TIM14_TI1_RMP_RTC_CLK (TIM14_OR_TI1_RMP_0 \| TIM14_OR_RMP_MASK) /!< TIM14_TI1 is connected to RTC Clock /
<>	157:ff67d9f36b67	1206	#define LL_TIM_TIM14_TI1_RMP_HSE (TIM14_OR_TI1_RMP_1 \| TIM14_OR_RMP_MASK) /!< TIM14_TI1 is connected to HSE/32 /
<>	157:ff67d9f36b67	1207	#define LL_TIM_TIM14_TI1_RMP_MCO (TIM14_OR_TI1_RMP_0 \| TIM14_OR_TI1_RMP_1 \| TIM14_OR_RMP_MASK) /!< TIM14_TI1 is connected to MCO /
<>	157:ff67d9f36b67	1208	/**
<>	157:ff67d9f36b67	1209	* @}
<>	157:ff67d9f36b67	1210	*/
<>	157:ff67d9f36b67	1211	#endif /* TIM14 */
<>	157:ff67d9f36b67	1212
<>	157:ff67d9f36b67	1213	#if defined(TIM_SMCR_OCCS)
<>	157:ff67d9f36b67	1214	/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
<>	157:ff67d9f36b67	1215	* @{
<>	157:ff67d9f36b67	1216	*/
<>	157:ff67d9f36b67	1217	#define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /!< OCREF_CLR_INT is connected to the OCREF_CLR input /
<>	157:ff67d9f36b67	1218	#define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /!< OCREF_CLR_INT is connected to ETRF /
<>	157:ff67d9f36b67	1219	/**
<>	157:ff67d9f36b67	1220	* @}
<>	157:ff67d9f36b67	1221	*/
<>	157:ff67d9f36b67	1222	#endif /* TIM_SMCR_OCCS*/
<>	157:ff67d9f36b67	1223
<>	157:ff67d9f36b67	1224	/**
<>	157:ff67d9f36b67	1225	* @}
<>	157:ff67d9f36b67	1226	*/
<>	157:ff67d9f36b67	1227
<>	157:ff67d9f36b67	1228	/* Exported macro ------------------------------------------------------------*/
<>	157:ff67d9f36b67	1229	/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
<>	157:ff67d9f36b67	1230	* @{
<>	157:ff67d9f36b67	1231	*/
<>	157:ff67d9f36b67	1232
<>	157:ff67d9f36b67	1233	/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
<>	157:ff67d9f36b67	1234	* @{
<>	157:ff67d9f36b67	1235	*/
<>	157:ff67d9f36b67	1236	/**
<>	157:ff67d9f36b67	1237	* @brief Write a value in TIM register.
<>	157:ff67d9f36b67	1238	* @param __INSTANCE__ TIM Instance
<>	157:ff67d9f36b67	1239	* @param __REG__ Register to be written
<>	157:ff67d9f36b67	1240	* @param __VALUE__ Value to be written in the register
<>	157:ff67d9f36b67	1241	* @retval None
<>	157:ff67d9f36b67	1242	*/
<>	157:ff67d9f36b67	1243	#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	157:ff67d9f36b67	1244
<>	157:ff67d9f36b67	1245	/**
<>	157:ff67d9f36b67	1246	* @brief Read a value in TIM register.
<>	157:ff67d9f36b67	1247	* @param __INSTANCE__ TIM Instance
<>	157:ff67d9f36b67	1248	* @param __REG__ Register to be read
<>	157:ff67d9f36b67	1249	* @retval Register value
<>	157:ff67d9f36b67	1250	*/
<>	157:ff67d9f36b67	1251	#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	157:ff67d9f36b67	1252	/**
<>	157:ff67d9f36b67	1253	* @}
<>	157:ff67d9f36b67	1254	*/
<>	157:ff67d9f36b67	1255
<>	157:ff67d9f36b67	1256	/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
<>	157:ff67d9f36b67	1257	* @{
<>	157:ff67d9f36b67	1258	*/
<>	157:ff67d9f36b67	1259	/**
<>	157:ff67d9f36b67	1260	* @brief HELPER macro retrieving the UIFCPY flag from the counter value.
<>	157:ff67d9f36b67	1261	* @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
<>	157:ff67d9f36b67	1262	* @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
<>	157:ff67d9f36b67	1263	* to TIMx_CNT register bit 31)
<>	157:ff67d9f36b67	1264	* @param __CNT__ Counter value
<>	157:ff67d9f36b67	1265	* @retval UIF status bit
<>	157:ff67d9f36b67	1266	*/
<>	157:ff67d9f36b67	1267	#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
<>	157:ff67d9f36b67	1268	(READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
<>	157:ff67d9f36b67	1269
<>	157:ff67d9f36b67	1270	/**
<>	157:ff67d9f36b67	1271	* @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
<>	157:ff67d9f36b67	1272	* @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
<>	157:ff67d9f36b67	1273	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	157:ff67d9f36b67	1274	* @param __CKD__ This parameter can be one of the following values:
<>	157:ff67d9f36b67	1275	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
<>	157:ff67d9f36b67	1276	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
<>	157:ff67d9f36b67	1277	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
<>	157:ff67d9f36b67	1278	* @param __DT__ deadtime duration (in ns)
<>	157:ff67d9f36b67	1279	* @retval DTG[0:7]
<>	157:ff67d9f36b67	1280	*/
<>	157:ff67d9f36b67	1281	#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
<>	157:ff67d9f36b67	1282	( (((uint64_t)((__DT__)1000U)) < ((DT_DELAY_1+1U) TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
<>	157:ff67d9f36b67	1283	(((uint64_t)((__DT__)1000U)) < (64U + (DT_DELAY_2+1U)) 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 \| ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\
<>	157:ff67d9f36b67	1284	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_3+1U)) 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\
<>	157:ff67d9f36b67	1285	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_4+1U)) 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\
<>	157:ff67d9f36b67	1286	0U)
<>	157:ff67d9f36b67	1287
<>	157:ff67d9f36b67	1288	/**
<>	157:ff67d9f36b67	1289	* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
<>	157:ff67d9f36b67	1290	* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
<>	157:ff67d9f36b67	1291	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	157:ff67d9f36b67	1292	* @param __CNTCLK__ counter clock frequency (in Hz)
<>	157:ff67d9f36b67	1293	* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
<>	157:ff67d9f36b67	1294	*/
<>	157:ff67d9f36b67	1295	#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
<>	157:ff67d9f36b67	1296	((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
<>	157:ff67d9f36b67	1297
<>	157:ff67d9f36b67	1298	/**
<>	157:ff67d9f36b67	1299	* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
<>	157:ff67d9f36b67	1300	* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
<>	157:ff67d9f36b67	1301	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	157:ff67d9f36b67	1302	* @param __PSC__ prescaler
<>	157:ff67d9f36b67	1303	* @param __FREQ__ output signal frequency (in Hz)
<>	157:ff67d9f36b67	1304	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
<>	157:ff67d9f36b67	1305	*/
<>	157:ff67d9f36b67	1306	#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
<>	157:ff67d9f36b67	1307	(((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
<>	157:ff67d9f36b67	1308
<>	157:ff67d9f36b67	1309	/**
<>	157:ff67d9f36b67	1310	* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
<>	157:ff67d9f36b67	1311	* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
<>	157:ff67d9f36b67	1312	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	157:ff67d9f36b67	1313	* @param __PSC__ prescaler
<>	157:ff67d9f36b67	1314	* @param __DELAY__ timer output compare active/inactive delay (in us)
<>	157:ff67d9f36b67	1315	* @retval Compare value (between Min_Data=0 and Max_Data=65535)
<>	157:ff67d9f36b67	1316	*/
<>	157:ff67d9f36b67	1317	#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
<>	157:ff67d9f36b67	1318	((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
<>	157:ff67d9f36b67	1319	/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
<>	157:ff67d9f36b67	1320
<>	157:ff67d9f36b67	1321	/**
<>	157:ff67d9f36b67	1322	* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
<>	157:ff67d9f36b67	1323	* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
<>	157:ff67d9f36b67	1324	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	157:ff67d9f36b67	1325	* @param __PSC__ prescaler
<>	157:ff67d9f36b67	1326	* @param __DELAY__ timer output compare active/inactive delay (in us)
<>	157:ff67d9f36b67	1327	* @param __PULSE__ pulse duration (in us)
<>	157:ff67d9f36b67	1328	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
<>	157:ff67d9f36b67	1329	*/
<>	157:ff67d9f36b67	1330	#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
<>	157:ff67d9f36b67	1331	((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
<>	157:ff67d9f36b67	1332	+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
<>	157:ff67d9f36b67	1333
<>	157:ff67d9f36b67	1334	/**
<>	157:ff67d9f36b67	1335	* @brief HELPER macro retrieving the ratio of the input capture prescaler
<>	157:ff67d9f36b67	1336	* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
<>	157:ff67d9f36b67	1337	* @param __ICPSC__ This parameter can be one of the following values:
<>	157:ff67d9f36b67	1338	* @arg @ref LL_TIM_ICPSC_DIV1
<>	157:ff67d9f36b67	1339	* @arg @ref LL_TIM_ICPSC_DIV2
<>	157:ff67d9f36b67	1340	* @arg @ref LL_TIM_ICPSC_DIV4
<>	157:ff67d9f36b67	1341	* @arg @ref LL_TIM_ICPSC_DIV8
<>	157:ff67d9f36b67	1342	* @retval Input capture prescaler ratio (1, 2, 4 or 8)
<>	157:ff67d9f36b67	1343	*/
<>	157:ff67d9f36b67	1344	#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
<>	157:ff67d9f36b67	1345	((uint32_t)((uint32_t)0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
<>	157:ff67d9f36b67	1346
<>	157:ff67d9f36b67	1347
<>	157:ff67d9f36b67	1348	/**
<>	157:ff67d9f36b67	1349	* @}
<>	157:ff67d9f36b67	1350	*/
<>	157:ff67d9f36b67	1351
<>	157:ff67d9f36b67	1352
<>	157:ff67d9f36b67	1353	/**
<>	157:ff67d9f36b67	1354	* @}
<>	157:ff67d9f36b67	1355	*/
<>	157:ff67d9f36b67	1356
<>	157:ff67d9f36b67	1357	/* Exported functions --------------------------------------------------------*/
<>	157:ff67d9f36b67	1358	/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
<>	157:ff67d9f36b67	1359	* @{
<>	157:ff67d9f36b67	1360	*/
<>	157:ff67d9f36b67	1361
<>	157:ff67d9f36b67	1362	/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
<>	157:ff67d9f36b67	1363	* @{
<>	157:ff67d9f36b67	1364	*/
<>	157:ff67d9f36b67	1365	/**
<>	157:ff67d9f36b67	1366	* @brief Enable timer counter.
<>	157:ff67d9f36b67	1367	* @rmtoll CR1 CEN LL_TIM_EnableCounter
<>	157:ff67d9f36b67	1368	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1369	* @retval None
<>	157:ff67d9f36b67	1370	*/
<>	157:ff67d9f36b67	1371	__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	1372	{
<>	157:ff67d9f36b67	1373	SET_BIT(TIMx->CR1, TIM_CR1_CEN);
<>	157:ff67d9f36b67	1374	}
<>	157:ff67d9f36b67	1375
<>	157:ff67d9f36b67	1376	/**
<>	157:ff67d9f36b67	1377	* @brief Disable timer counter.
<>	157:ff67d9f36b67	1378	* @rmtoll CR1 CEN LL_TIM_DisableCounter
<>	157:ff67d9f36b67	1379	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1380	* @retval None
<>	157:ff67d9f36b67	1381	*/
<>	157:ff67d9f36b67	1382	__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	1383	{
<>	157:ff67d9f36b67	1384	CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
<>	157:ff67d9f36b67	1385	}
<>	157:ff67d9f36b67	1386
<>	157:ff67d9f36b67	1387	/**
<>	157:ff67d9f36b67	1388	* @brief Indicates whether the timer counter is enabled.
<>	157:ff67d9f36b67	1389	* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
<>	157:ff67d9f36b67	1390	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1391	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1392	*/
<>	157:ff67d9f36b67	1393	__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	1394	{
<>	157:ff67d9f36b67	1395	return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
<>	157:ff67d9f36b67	1396	}
<>	157:ff67d9f36b67	1397
<>	157:ff67d9f36b67	1398	/**
<>	157:ff67d9f36b67	1399	* @brief Enable update event generation.
<>	157:ff67d9f36b67	1400	* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
<>	157:ff67d9f36b67	1401	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1402	* @retval None
<>	157:ff67d9f36b67	1403	*/
<>	157:ff67d9f36b67	1404	__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	1405	{
<>	157:ff67d9f36b67	1406	SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
<>	157:ff67d9f36b67	1407	}
<>	157:ff67d9f36b67	1408
<>	157:ff67d9f36b67	1409	/**
<>	157:ff67d9f36b67	1410	* @brief Disable update event generation.
<>	157:ff67d9f36b67	1411	* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
<>	157:ff67d9f36b67	1412	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1413	* @retval None
<>	157:ff67d9f36b67	1414	*/
<>	157:ff67d9f36b67	1415	__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	1416	{
<>	157:ff67d9f36b67	1417	CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
<>	157:ff67d9f36b67	1418	}
<>	157:ff67d9f36b67	1419
<>	157:ff67d9f36b67	1420	/**
<>	157:ff67d9f36b67	1421	* @brief Indicates whether update event generation is enabled.
<>	157:ff67d9f36b67	1422	* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
<>	157:ff67d9f36b67	1423	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1424	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1425	*/
<>	157:ff67d9f36b67	1426	__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	1427	{
<>	157:ff67d9f36b67	1428	return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
<>	157:ff67d9f36b67	1429	}
<>	157:ff67d9f36b67	1430
<>	157:ff67d9f36b67	1431	/**
<>	157:ff67d9f36b67	1432	* @brief Set update event source
<>	157:ff67d9f36b67	1433	* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
<>	157:ff67d9f36b67	1434	* generate an update interrupt or DMA request if enabled:
<>	157:ff67d9f36b67	1435	* - Counter overflow/underflow
<>	157:ff67d9f36b67	1436	* - Setting the UG bit
<>	157:ff67d9f36b67	1437	* - Update generation through the slave mode controller
<>	157:ff67d9f36b67	1438	* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
<>	157:ff67d9f36b67	1439	* overflow/underflow generates an update interrupt or DMA request if enabled.
<>	157:ff67d9f36b67	1440	* @rmtoll CR1 URS LL_TIM_SetUpdateSource
<>	157:ff67d9f36b67	1441	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1442	* @param UpdateSource This parameter can be one of the following values:
<>	157:ff67d9f36b67	1443	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
<>	157:ff67d9f36b67	1444	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
<>	157:ff67d9f36b67	1445	* @retval None
<>	157:ff67d9f36b67	1446	*/
<>	157:ff67d9f36b67	1447	__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
<>	157:ff67d9f36b67	1448	{
<>	157:ff67d9f36b67	1449	MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
<>	157:ff67d9f36b67	1450	}
<>	157:ff67d9f36b67	1451
<>	157:ff67d9f36b67	1452	/**
<>	157:ff67d9f36b67	1453	* @brief Get actual event update source
<>	157:ff67d9f36b67	1454	* @rmtoll CR1 URS LL_TIM_GetUpdateSource
<>	157:ff67d9f36b67	1455	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1456	* @retval Returned value can be one of the following values:
<>	157:ff67d9f36b67	1457	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
<>	157:ff67d9f36b67	1458	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
<>	157:ff67d9f36b67	1459	*/
<>	157:ff67d9f36b67	1460	__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	1461	{
<>	157:ff67d9f36b67	1462	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
<>	157:ff67d9f36b67	1463	}
<>	157:ff67d9f36b67	1464
<>	157:ff67d9f36b67	1465	/**
<>	157:ff67d9f36b67	1466	* @brief Set one pulse mode (one shot v.s. repetitive).
<>	157:ff67d9f36b67	1467	* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
<>	157:ff67d9f36b67	1468	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1469	* @param OnePulseMode This parameter can be one of the following values:
<>	157:ff67d9f36b67	1470	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
<>	157:ff67d9f36b67	1471	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
<>	157:ff67d9f36b67	1472	* @retval None
<>	157:ff67d9f36b67	1473	*/
<>	157:ff67d9f36b67	1474	__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
<>	157:ff67d9f36b67	1475	{
<>	157:ff67d9f36b67	1476	MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
<>	157:ff67d9f36b67	1477	}
<>	157:ff67d9f36b67	1478
<>	157:ff67d9f36b67	1479	/**
<>	157:ff67d9f36b67	1480	* @brief Get actual one pulse mode.
<>	157:ff67d9f36b67	1481	* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
<>	157:ff67d9f36b67	1482	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1483	* @retval Returned value can be one of the following values:
<>	157:ff67d9f36b67	1484	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
<>	157:ff67d9f36b67	1485	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
<>	157:ff67d9f36b67	1486	*/
<>	157:ff67d9f36b67	1487	__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	1488	{
<>	157:ff67d9f36b67	1489	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
<>	157:ff67d9f36b67	1490	}
<>	157:ff67d9f36b67	1491
<>	157:ff67d9f36b67	1492	/**
<>	157:ff67d9f36b67	1493	* @brief Set the timer counter counting mode.
<>	157:ff67d9f36b67	1494	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
<>	157:ff67d9f36b67	1495	* check whether or not the counter mode selection feature is supported
<>	157:ff67d9f36b67	1496	* by a timer instance.
<>	157:ff67d9f36b67	1497	* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
<>	157:ff67d9f36b67	1498	* CR1 CMS LL_TIM_SetCounterMode
<>	157:ff67d9f36b67	1499	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1500	* @param CounterMode This parameter can be one of the following values:
<>	157:ff67d9f36b67	1501	* @arg @ref LL_TIM_COUNTERMODE_UP
<>	157:ff67d9f36b67	1502	* @arg @ref LL_TIM_COUNTERMODE_DOWN
<>	157:ff67d9f36b67	1503	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
<>	157:ff67d9f36b67	1504	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
<>	157:ff67d9f36b67	1505	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
<>	157:ff67d9f36b67	1506	* @retval None
<>	157:ff67d9f36b67	1507	*/
<>	157:ff67d9f36b67	1508	__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
<>	157:ff67d9f36b67	1509	{
<>	157:ff67d9f36b67	1510	MODIFY_REG(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS, CounterMode);
<>	157:ff67d9f36b67	1511	}
<>	157:ff67d9f36b67	1512
<>	157:ff67d9f36b67	1513	/**
<>	157:ff67d9f36b67	1514	* @brief Get actual counter mode.
<>	157:ff67d9f36b67	1515	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
<>	157:ff67d9f36b67	1516	* check whether or not the counter mode selection feature is supported
<>	157:ff67d9f36b67	1517	* by a timer instance.
<>	157:ff67d9f36b67	1518	* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
<>	157:ff67d9f36b67	1519	* CR1 CMS LL_TIM_GetCounterMode
<>	157:ff67d9f36b67	1520	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1521	* @retval Returned value can be one of the following values:
<>	157:ff67d9f36b67	1522	* @arg @ref LL_TIM_COUNTERMODE_UP
<>	157:ff67d9f36b67	1523	* @arg @ref LL_TIM_COUNTERMODE_DOWN
<>	157:ff67d9f36b67	1524	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
<>	157:ff67d9f36b67	1525	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
<>	157:ff67d9f36b67	1526	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
<>	157:ff67d9f36b67	1527	*/
<>	157:ff67d9f36b67	1528	__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	1529	{
<>	157:ff67d9f36b67	1530	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS));
<>	157:ff67d9f36b67	1531	}
<>	157:ff67d9f36b67	1532
<>	157:ff67d9f36b67	1533	/**
<>	157:ff67d9f36b67	1534	* @brief Enable auto-reload (ARR) preload.
<>	157:ff67d9f36b67	1535	* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
<>	157:ff67d9f36b67	1536	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1537	* @retval None
<>	157:ff67d9f36b67	1538	*/
<>	157:ff67d9f36b67	1539	__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	1540	{
<>	157:ff67d9f36b67	1541	SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
<>	157:ff67d9f36b67	1542	}
<>	157:ff67d9f36b67	1543
<>	157:ff67d9f36b67	1544	/**
<>	157:ff67d9f36b67	1545	* @brief Disable auto-reload (ARR) preload.
<>	157:ff67d9f36b67	1546	* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
<>	157:ff67d9f36b67	1547	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1548	* @retval None
<>	157:ff67d9f36b67	1549	*/
<>	157:ff67d9f36b67	1550	__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	1551	{
<>	157:ff67d9f36b67	1552	CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
<>	157:ff67d9f36b67	1553	}
<>	157:ff67d9f36b67	1554
<>	157:ff67d9f36b67	1555	/**
<>	157:ff67d9f36b67	1556	* @brief Indicates whether auto-reload (ARR) preload is enabled.
<>	157:ff67d9f36b67	1557	* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
<>	157:ff67d9f36b67	1558	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1559	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1560	*/
<>	157:ff67d9f36b67	1561	__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	1562	{
<>	157:ff67d9f36b67	1563	return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
<>	157:ff67d9f36b67	1564	}
<>	157:ff67d9f36b67	1565
<>	157:ff67d9f36b67	1566	/**
<>	157:ff67d9f36b67	1567	* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
<>	157:ff67d9f36b67	1568	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	1569	* whether or not the clock division feature is supported by the timer
<>	157:ff67d9f36b67	1570	* instance.
<>	157:ff67d9f36b67	1571	* @rmtoll CR1 CKD LL_TIM_SetClockDivision
<>	157:ff67d9f36b67	1572	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1573	* @param ClockDivision This parameter can be one of the following values:
<>	157:ff67d9f36b67	1574	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
<>	157:ff67d9f36b67	1575	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
<>	157:ff67d9f36b67	1576	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
<>	157:ff67d9f36b67	1577	* @retval None
<>	157:ff67d9f36b67	1578	*/
<>	157:ff67d9f36b67	1579	__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
<>	157:ff67d9f36b67	1580	{
<>	157:ff67d9f36b67	1581	MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
<>	157:ff67d9f36b67	1582	}
<>	157:ff67d9f36b67	1583
<>	157:ff67d9f36b67	1584	/**
<>	157:ff67d9f36b67	1585	* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
<>	157:ff67d9f36b67	1586	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	1587	* whether or not the clock division feature is supported by the timer
<>	157:ff67d9f36b67	1588	* instance.
<>	157:ff67d9f36b67	1589	* @rmtoll CR1 CKD LL_TIM_GetClockDivision
<>	157:ff67d9f36b67	1590	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1591	* @retval Returned value can be one of the following values:
<>	157:ff67d9f36b67	1592	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
<>	157:ff67d9f36b67	1593	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
<>	157:ff67d9f36b67	1594	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
<>	157:ff67d9f36b67	1595	*/
<>	157:ff67d9f36b67	1596	__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	1597	{
<>	157:ff67d9f36b67	1598	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
<>	157:ff67d9f36b67	1599	}
<>	157:ff67d9f36b67	1600
<>	157:ff67d9f36b67	1601	/**
<>	157:ff67d9f36b67	1602	* @brief Set the counter value.
<>	157:ff67d9f36b67	1603	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	1604	* whether or not a timer instance supports a 32 bits counter.
<>	157:ff67d9f36b67	1605	* @rmtoll CNT CNT LL_TIM_SetCounter
<>	157:ff67d9f36b67	1606	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1607	* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
<>	157:ff67d9f36b67	1608	* @retval None
<>	157:ff67d9f36b67	1609	*/
<>	157:ff67d9f36b67	1610	__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
<>	157:ff67d9f36b67	1611	{
<>	157:ff67d9f36b67	1612	WRITE_REG(TIMx->CNT, Counter);
<>	157:ff67d9f36b67	1613	}
<>	157:ff67d9f36b67	1614
<>	157:ff67d9f36b67	1615	/**
<>	157:ff67d9f36b67	1616	* @brief Get the counter value.
<>	157:ff67d9f36b67	1617	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	1618	* whether or not a timer instance supports a 32 bits counter.
<>	157:ff67d9f36b67	1619	* @rmtoll CNT CNT LL_TIM_GetCounter
<>	157:ff67d9f36b67	1620	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1621	* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
<>	157:ff67d9f36b67	1622	*/
<>	157:ff67d9f36b67	1623	__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	1624	{
<>	157:ff67d9f36b67	1625	return (uint32_t)(READ_REG(TIMx->CNT));
<>	157:ff67d9f36b67	1626	}
<>	157:ff67d9f36b67	1627
<>	157:ff67d9f36b67	1628	/**
<>	157:ff67d9f36b67	1629	* @brief Get the current direction of the counter
<>	157:ff67d9f36b67	1630	* @rmtoll CR1 DIR LL_TIM_GetDirection
<>	157:ff67d9f36b67	1631	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1632	* @retval Returned value can be one of the following values:
<>	157:ff67d9f36b67	1633	* @arg @ref LL_TIM_COUNTERDIRECTION_UP
<>	157:ff67d9f36b67	1634	* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
<>	157:ff67d9f36b67	1635	*/
<>	157:ff67d9f36b67	1636	__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	1637	{
<>	157:ff67d9f36b67	1638	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
<>	157:ff67d9f36b67	1639	}
<>	157:ff67d9f36b67	1640
<>	157:ff67d9f36b67	1641	/**
<>	157:ff67d9f36b67	1642	* @brief Set the prescaler value.
<>	157:ff67d9f36b67	1643	* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
<>	157:ff67d9f36b67	1644	* @note The prescaler can be changed on the fly as this control register is buffered. The new
<>	157:ff67d9f36b67	1645	* prescaler ratio is taken into account at the next update event.
<>	157:ff67d9f36b67	1646	* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
<>	157:ff67d9f36b67	1647	* @rmtoll PSC PSC LL_TIM_SetPrescaler
<>	157:ff67d9f36b67	1648	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1649	* @param Prescaler between Min_Data=0 and Max_Data=65535
<>	157:ff67d9f36b67	1650	* @retval None
<>	157:ff67d9f36b67	1651	*/
<>	157:ff67d9f36b67	1652	__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
<>	157:ff67d9f36b67	1653	{
<>	157:ff67d9f36b67	1654	WRITE_REG(TIMx->PSC, Prescaler);
<>	157:ff67d9f36b67	1655	}
<>	157:ff67d9f36b67	1656
<>	157:ff67d9f36b67	1657	/**
<>	157:ff67d9f36b67	1658	* @brief Get the prescaler value.
<>	157:ff67d9f36b67	1659	* @rmtoll PSC PSC LL_TIM_GetPrescaler
<>	157:ff67d9f36b67	1660	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1661	* @retval Prescaler value between Min_Data=0 and Max_Data=65535
<>	157:ff67d9f36b67	1662	*/
<>	157:ff67d9f36b67	1663	__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	1664	{
<>	157:ff67d9f36b67	1665	return (uint32_t)(READ_REG(TIMx->PSC));
<>	157:ff67d9f36b67	1666	}
<>	157:ff67d9f36b67	1667
<>	157:ff67d9f36b67	1668	/**
<>	157:ff67d9f36b67	1669	* @brief Set the auto-reload value.
<>	157:ff67d9f36b67	1670	* @note The counter is blocked while the auto-reload value is null.
<>	157:ff67d9f36b67	1671	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	1672	* whether or not a timer instance supports a 32 bits counter.
<>	157:ff67d9f36b67	1673	* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
<>	157:ff67d9f36b67	1674	* @rmtoll ARR ARR LL_TIM_SetAutoReload
<>	157:ff67d9f36b67	1675	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1676	* @param AutoReload between Min_Data=0 and Max_Data=65535
<>	157:ff67d9f36b67	1677	* @retval None
<>	157:ff67d9f36b67	1678	*/
<>	157:ff67d9f36b67	1679	__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
<>	157:ff67d9f36b67	1680	{
<>	157:ff67d9f36b67	1681	WRITE_REG(TIMx->ARR, AutoReload);
<>	157:ff67d9f36b67	1682	}
<>	157:ff67d9f36b67	1683
<>	157:ff67d9f36b67	1684	/**
<>	157:ff67d9f36b67	1685	* @brief Get the auto-reload value.
<>	157:ff67d9f36b67	1686	* @rmtoll ARR ARR LL_TIM_GetAutoReload
<>	157:ff67d9f36b67	1687	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	1688	* whether or not a timer instance supports a 32 bits counter.
<>	157:ff67d9f36b67	1689	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1690	* @retval Auto-reload value
<>	157:ff67d9f36b67	1691	*/
<>	157:ff67d9f36b67	1692	__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	1693	{
<>	157:ff67d9f36b67	1694	return (uint32_t)(READ_REG(TIMx->ARR));
<>	157:ff67d9f36b67	1695	}
<>	157:ff67d9f36b67	1696
<>	157:ff67d9f36b67	1697	/**
<>	157:ff67d9f36b67	1698	* @brief Set the repetition counter value.
<>	157:ff67d9f36b67	1699	* @note For advanced timer instances RepetitionCounter can be up to 65535 except for STM32F373xC and STM32F378xx devices.
<>	157:ff67d9f36b67	1700	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	1701	* whether or not a timer instance supports a repetition counter.
<>	157:ff67d9f36b67	1702	* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
<>	157:ff67d9f36b67	1703	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1704	* @param RepetitionCounter between Min_Data=0 and Max_Data=255
<>	157:ff67d9f36b67	1705	* @retval None
<>	157:ff67d9f36b67	1706	*/
<>	157:ff67d9f36b67	1707	__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
<>	157:ff67d9f36b67	1708	{
<>	157:ff67d9f36b67	1709	WRITE_REG(TIMx->RCR, RepetitionCounter);
<>	157:ff67d9f36b67	1710	}
<>	157:ff67d9f36b67	1711
<>	157:ff67d9f36b67	1712	/**
<>	157:ff67d9f36b67	1713	* @brief Get the repetition counter value.
<>	157:ff67d9f36b67	1714	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	1715	* whether or not a timer instance supports a repetition counter.
<>	157:ff67d9f36b67	1716	* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
<>	157:ff67d9f36b67	1717	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1718	* @retval Repetition counter value
<>	157:ff67d9f36b67	1719	*/
<>	157:ff67d9f36b67	1720	__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	1721	{
<>	157:ff67d9f36b67	1722	return (uint32_t)(READ_REG(TIMx->RCR));
<>	157:ff67d9f36b67	1723	}
<>	157:ff67d9f36b67	1724
<>	157:ff67d9f36b67	1725	#if defined(TIM_CR1_UIFREMAP)
<>	157:ff67d9f36b67	1726	/**
<>	157:ff67d9f36b67	1727	* @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
<>	157:ff67d9f36b67	1728	* @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
<>	157:ff67d9f36b67	1729	* @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
<>	157:ff67d9f36b67	1730	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1731	* @retval None
<>	157:ff67d9f36b67	1732	*/
<>	157:ff67d9f36b67	1733	__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	1734	{
<>	157:ff67d9f36b67	1735	SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
<>	157:ff67d9f36b67	1736	}
<>	157:ff67d9f36b67	1737
<>	157:ff67d9f36b67	1738	/**
<>	157:ff67d9f36b67	1739	* @brief Disable update interrupt flag (UIF) remapping.
<>	157:ff67d9f36b67	1740	* @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
<>	157:ff67d9f36b67	1741	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1742	* @retval None
<>	157:ff67d9f36b67	1743	*/
<>	157:ff67d9f36b67	1744	__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	1745	{
<>	157:ff67d9f36b67	1746	CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
<>	157:ff67d9f36b67	1747	}
<>	157:ff67d9f36b67	1748
<>	157:ff67d9f36b67	1749	#endif /* TIM_CR1_UIFREMAP */
<>	157:ff67d9f36b67	1750	/**
<>	157:ff67d9f36b67	1751	* @}
<>	157:ff67d9f36b67	1752	*/
<>	157:ff67d9f36b67	1753
<>	157:ff67d9f36b67	1754	/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
<>	157:ff67d9f36b67	1755	* @{
<>	157:ff67d9f36b67	1756	*/
<>	157:ff67d9f36b67	1757	/**
<>	157:ff67d9f36b67	1758	* @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
<>	157:ff67d9f36b67	1759	* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
<>	157:ff67d9f36b67	1760	* they are updated only when a commutation event (COM) occurs.
<>	157:ff67d9f36b67	1761	* @note Only on channels that have a complementary output.
<>	157:ff67d9f36b67	1762	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	1763	* whether or not a timer instance is able to generate a commutation event.
<>	157:ff67d9f36b67	1764	* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
<>	157:ff67d9f36b67	1765	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1766	* @retval None
<>	157:ff67d9f36b67	1767	*/
<>	157:ff67d9f36b67	1768	__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	1769	{
<>	157:ff67d9f36b67	1770	SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
<>	157:ff67d9f36b67	1771	}
<>	157:ff67d9f36b67	1772
<>	157:ff67d9f36b67	1773	/**
<>	157:ff67d9f36b67	1774	* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
<>	157:ff67d9f36b67	1775	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	1776	* whether or not a timer instance is able to generate a commutation event.
<>	157:ff67d9f36b67	1777	* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
<>	157:ff67d9f36b67	1778	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1779	* @retval None
<>	157:ff67d9f36b67	1780	*/
<>	157:ff67d9f36b67	1781	__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	1782	{
<>	157:ff67d9f36b67	1783	CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
<>	157:ff67d9f36b67	1784	}
<>	157:ff67d9f36b67	1785
<>	157:ff67d9f36b67	1786	/**
<>	157:ff67d9f36b67	1787	* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
<>	157:ff67d9f36b67	1788	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	1789	* whether or not a timer instance is able to generate a commutation event.
<>	157:ff67d9f36b67	1790	* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
<>	157:ff67d9f36b67	1791	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1792	* @param CCUpdateSource This parameter can be one of the following values:
<>	157:ff67d9f36b67	1793	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
<>	157:ff67d9f36b67	1794	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
<>	157:ff67d9f36b67	1795	* @retval None
<>	157:ff67d9f36b67	1796	*/
<>	157:ff67d9f36b67	1797	__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
<>	157:ff67d9f36b67	1798	{
<>	157:ff67d9f36b67	1799	MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
<>	157:ff67d9f36b67	1800	}
<>	157:ff67d9f36b67	1801
<>	157:ff67d9f36b67	1802	/**
<>	157:ff67d9f36b67	1803	* @brief Set the trigger of the capture/compare DMA request.
<>	157:ff67d9f36b67	1804	* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
<>	157:ff67d9f36b67	1805	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1806	* @param DMAReqTrigger This parameter can be one of the following values:
<>	157:ff67d9f36b67	1807	* @arg @ref LL_TIM_CCDMAREQUEST_CC
<>	157:ff67d9f36b67	1808	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
<>	157:ff67d9f36b67	1809	* @retval None
<>	157:ff67d9f36b67	1810	*/
<>	157:ff67d9f36b67	1811	__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
<>	157:ff67d9f36b67	1812	{
<>	157:ff67d9f36b67	1813	MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
<>	157:ff67d9f36b67	1814	}
<>	157:ff67d9f36b67	1815
<>	157:ff67d9f36b67	1816	/**
<>	157:ff67d9f36b67	1817	* @brief Get actual trigger of the capture/compare DMA request.
<>	157:ff67d9f36b67	1818	* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
<>	157:ff67d9f36b67	1819	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1820	* @retval Returned value can be one of the following values:
<>	157:ff67d9f36b67	1821	* @arg @ref LL_TIM_CCDMAREQUEST_CC
<>	157:ff67d9f36b67	1822	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
<>	157:ff67d9f36b67	1823	*/
<>	157:ff67d9f36b67	1824	__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	1825	{
<>	157:ff67d9f36b67	1826	return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
<>	157:ff67d9f36b67	1827	}
<>	157:ff67d9f36b67	1828
<>	157:ff67d9f36b67	1829	/**
<>	157:ff67d9f36b67	1830	* @brief Set the lock level to freeze the
<>	157:ff67d9f36b67	1831	* configuration of several capture/compare parameters.
<>	157:ff67d9f36b67	1832	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	1833	* the lock mechanism is supported by a timer instance.
<>	157:ff67d9f36b67	1834	* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
<>	157:ff67d9f36b67	1835	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1836	* @param LockLevel This parameter can be one of the following values:
<>	157:ff67d9f36b67	1837	* @arg @ref LL_TIM_LOCKLEVEL_OFF
<>	157:ff67d9f36b67	1838	* @arg @ref LL_TIM_LOCKLEVEL_1
<>	157:ff67d9f36b67	1839	* @arg @ref LL_TIM_LOCKLEVEL_2
<>	157:ff67d9f36b67	1840	* @arg @ref LL_TIM_LOCKLEVEL_3
<>	157:ff67d9f36b67	1841	* @retval None
<>	157:ff67d9f36b67	1842	*/
<>	157:ff67d9f36b67	1843	__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
<>	157:ff67d9f36b67	1844	{
<>	157:ff67d9f36b67	1845	MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
<>	157:ff67d9f36b67	1846	}
<>	157:ff67d9f36b67	1847
<>	157:ff67d9f36b67	1848	/**
<>	157:ff67d9f36b67	1849	* @brief Enable capture/compare channels.
<>	157:ff67d9f36b67	1850	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
<>	157:ff67d9f36b67	1851	* CCER CC1NE LL_TIM_CC_EnableChannel\n
<>	157:ff67d9f36b67	1852	* CCER CC2E LL_TIM_CC_EnableChannel\n
<>	157:ff67d9f36b67	1853	* CCER CC2NE LL_TIM_CC_EnableChannel\n
<>	157:ff67d9f36b67	1854	* CCER CC3E LL_TIM_CC_EnableChannel\n
<>	157:ff67d9f36b67	1855	* CCER CC3NE LL_TIM_CC_EnableChannel\n
<>	157:ff67d9f36b67	1856	* CCER CC4E LL_TIM_CC_EnableChannel\n
<>	157:ff67d9f36b67	1857	* CCER CC5E LL_TIM_CC_EnableChannel\n
<>	157:ff67d9f36b67	1858	* CCER CC6E LL_TIM_CC_EnableChannel
<>	157:ff67d9f36b67	1859	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1860	* @param Channels This parameter can be a combination of the following values:
<>	157:ff67d9f36b67	1861	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	1862	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	157:ff67d9f36b67	1863	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	1864	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	157:ff67d9f36b67	1865	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	1866	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	157:ff67d9f36b67	1867	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	1868	* @arg @ref LL_TIM_CHANNEL_CH5
<>	157:ff67d9f36b67	1869	* @arg @ref LL_TIM_CHANNEL_CH6
<>	157:ff67d9f36b67	1870	* @note CH5 and CH6 channels are not available for all F3 devices
<>	157:ff67d9f36b67	1871	* @retval None
<>	157:ff67d9f36b67	1872	*/
<>	157:ff67d9f36b67	1873	__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
<>	157:ff67d9f36b67	1874	{
<>	157:ff67d9f36b67	1875	SET_BIT(TIMx->CCER, Channels);
<>	157:ff67d9f36b67	1876	}
<>	157:ff67d9f36b67	1877
<>	157:ff67d9f36b67	1878	/**
<>	157:ff67d9f36b67	1879	* @brief Disable capture/compare channels.
<>	157:ff67d9f36b67	1880	* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
<>	157:ff67d9f36b67	1881	* CCER CC1NE LL_TIM_CC_DisableChannel\n
<>	157:ff67d9f36b67	1882	* CCER CC2E LL_TIM_CC_DisableChannel\n
<>	157:ff67d9f36b67	1883	* CCER CC2NE LL_TIM_CC_DisableChannel\n
<>	157:ff67d9f36b67	1884	* CCER CC3E LL_TIM_CC_DisableChannel\n
<>	157:ff67d9f36b67	1885	* CCER CC3NE LL_TIM_CC_DisableChannel\n
<>	157:ff67d9f36b67	1886	* CCER CC4E LL_TIM_CC_DisableChannel\n
<>	157:ff67d9f36b67	1887	* CCER CC5E LL_TIM_CC_DisableChannel\n
<>	157:ff67d9f36b67	1888	* CCER CC6E LL_TIM_CC_DisableChannel
<>	157:ff67d9f36b67	1889	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1890	* @param Channels This parameter can be a combination of the following values:
<>	157:ff67d9f36b67	1891	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	1892	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	157:ff67d9f36b67	1893	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	1894	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	157:ff67d9f36b67	1895	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	1896	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	157:ff67d9f36b67	1897	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	1898	* @arg @ref LL_TIM_CHANNEL_CH5
<>	157:ff67d9f36b67	1899	* @arg @ref LL_TIM_CHANNEL_CH6
<>	157:ff67d9f36b67	1900	* @note CH5 and CH6 channels are not available for all F3 devices
<>	157:ff67d9f36b67	1901	* @retval None
<>	157:ff67d9f36b67	1902	*/
<>	157:ff67d9f36b67	1903	__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
<>	157:ff67d9f36b67	1904	{
<>	157:ff67d9f36b67	1905	CLEAR_BIT(TIMx->CCER, Channels);
<>	157:ff67d9f36b67	1906	}
<>	157:ff67d9f36b67	1907
<>	157:ff67d9f36b67	1908	/**
<>	157:ff67d9f36b67	1909	* @brief Indicate whether channel(s) is(are) enabled.
<>	157:ff67d9f36b67	1910	* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
<>	157:ff67d9f36b67	1911	* CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
<>	157:ff67d9f36b67	1912	* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
<>	157:ff67d9f36b67	1913	* CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
<>	157:ff67d9f36b67	1914	* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
<>	157:ff67d9f36b67	1915	* CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
<>	157:ff67d9f36b67	1916	* CCER CC4E LL_TIM_CC_IsEnabledChannel\n
<>	157:ff67d9f36b67	1917	* CCER CC5E LL_TIM_CC_IsEnabledChannel\n
<>	157:ff67d9f36b67	1918	* CCER CC6E LL_TIM_CC_IsEnabledChannel
<>	157:ff67d9f36b67	1919	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1920	* @param Channels This parameter can be a combination of the following values:
<>	157:ff67d9f36b67	1921	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	1922	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	157:ff67d9f36b67	1923	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	1924	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	157:ff67d9f36b67	1925	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	1926	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	157:ff67d9f36b67	1927	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	1928	* @arg @ref LL_TIM_CHANNEL_CH5
<>	157:ff67d9f36b67	1929	* @arg @ref LL_TIM_CHANNEL_CH6
<>	157:ff67d9f36b67	1930	* @note CH5 and CH6 channels are not available for all F3 devices
<>	157:ff67d9f36b67	1931	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	1932	*/
<>	157:ff67d9f36b67	1933	__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
<>	157:ff67d9f36b67	1934	{
<>	157:ff67d9f36b67	1935	return (READ_BIT(TIMx->CCER, Channels) == (Channels));
<>	157:ff67d9f36b67	1936	}
<>	157:ff67d9f36b67	1937
<>	157:ff67d9f36b67	1938	/**
<>	157:ff67d9f36b67	1939	* @}
<>	157:ff67d9f36b67	1940	*/
<>	157:ff67d9f36b67	1941
<>	157:ff67d9f36b67	1942	/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
<>	157:ff67d9f36b67	1943	* @{
<>	157:ff67d9f36b67	1944	*/
<>	157:ff67d9f36b67	1945	/**
<>	157:ff67d9f36b67	1946	* @brief Configure an output channel.
<>	157:ff67d9f36b67	1947	* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
<>	157:ff67d9f36b67	1948	* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
<>	157:ff67d9f36b67	1949	* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
<>	157:ff67d9f36b67	1950	* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
<>	157:ff67d9f36b67	1951	* @if STM32F334x8
<>	157:ff67d9f36b67	1952	* CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
<>	157:ff67d9f36b67	1953	* CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
<>	157:ff67d9f36b67	1954	* @elseif STM32F303xC
<>	157:ff67d9f36b67	1955	* CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
<>	157:ff67d9f36b67	1956	* CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
<>	157:ff67d9f36b67	1957	* @elseif STM32F302x8
<>	157:ff67d9f36b67	1958	* CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
<>	157:ff67d9f36b67	1959	* CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
<>	157:ff67d9f36b67	1960	* @endif
<>	157:ff67d9f36b67	1961	* CCER CC1P LL_TIM_OC_ConfigOutput\n
<>	157:ff67d9f36b67	1962	* CCER CC2P LL_TIM_OC_ConfigOutput\n
<>	157:ff67d9f36b67	1963	* CCER CC3P LL_TIM_OC_ConfigOutput\n
<>	157:ff67d9f36b67	1964	* CCER CC4P LL_TIM_OC_ConfigOutput\n
<>	157:ff67d9f36b67	1965	* CCER CC5P LL_TIM_OC_ConfigOutput\n
<>	157:ff67d9f36b67	1966	* CCER CC6P LL_TIM_OC_ConfigOutput\n
<>	157:ff67d9f36b67	1967	* CR2 OIS1 LL_TIM_OC_ConfigOutput\n
<>	157:ff67d9f36b67	1968	* CR2 OIS2 LL_TIM_OC_ConfigOutput\n
<>	157:ff67d9f36b67	1969	* CR2 OIS3 LL_TIM_OC_ConfigOutput\n
<>	157:ff67d9f36b67	1970	* CR2 OIS4 LL_TIM_OC_ConfigOutput\n
<>	157:ff67d9f36b67	1971	* CR2 OIS5 LL_TIM_OC_ConfigOutput\n
<>	157:ff67d9f36b67	1972	* CR2 OIS6 LL_TIM_OC_ConfigOutput
<>	157:ff67d9f36b67	1973	* @param TIMx Timer instance
<>	157:ff67d9f36b67	1974	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	1975	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	1976	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	1977	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	1978	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	1979	* @arg @ref LL_TIM_CHANNEL_CH5
<>	157:ff67d9f36b67	1980	* @arg @ref LL_TIM_CHANNEL_CH6
<>	157:ff67d9f36b67	1981	* @param Configuration This parameter must be a combination of all the following values:
<>	157:ff67d9f36b67	1982	* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
<>	157:ff67d9f36b67	1983	* @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
<>	157:ff67d9f36b67	1984	* @note CH3 CH4 CH5 and CH6 channels are not available for all F3 devices
<>	157:ff67d9f36b67	1985	* @retval None
<>	157:ff67d9f36b67	1986	*/
<>	157:ff67d9f36b67	1987	__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
<>	157:ff67d9f36b67	1988	{
<>	157:ff67d9f36b67	1989	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	157:ff67d9f36b67	1990	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	157:ff67d9f36b67	1991	CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
<>	157:ff67d9f36b67	1992	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
<>	157:ff67d9f36b67	1993	(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
<>	157:ff67d9f36b67	1994	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
<>	157:ff67d9f36b67	1995	(Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
<>	157:ff67d9f36b67	1996	}
<>	157:ff67d9f36b67	1997
<>	157:ff67d9f36b67	1998	/**
<>	157:ff67d9f36b67	1999	* @brief Define the behavior of the output reference signal OCxREF from which
<>	157:ff67d9f36b67	2000	* OCx and OCxN (when relevant) are derived.
<>	157:ff67d9f36b67	2001	* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
<>	157:ff67d9f36b67	2002	* CCMR1 OC2M LL_TIM_OC_SetMode\n
<>	157:ff67d9f36b67	2003	* CCMR2 OC3M LL_TIM_OC_SetMode\n
<>	157:ff67d9f36b67	2004	* CCMR2 OC4M LL_TIM_OC_SetMode\n
<>	157:ff67d9f36b67	2005	* @if STM32F334x8
<>	157:ff67d9f36b67	2006	* CCMR3 OC5M LL_TIM_OC_SetMode\n
<>	157:ff67d9f36b67	2007	* CCMR3 OC6M LL_TIM_OC_SetMode
<>	157:ff67d9f36b67	2008	* @elseif STM32F303xC
<>	157:ff67d9f36b67	2009	* CCMR3 OC5M LL_TIM_OC_SetMode\n
<>	157:ff67d9f36b67	2010	* CCMR3 OC6M LL_TIM_OC_SetMode
<>	157:ff67d9f36b67	2011	* @elseif STM32F302x8
<>	157:ff67d9f36b67	2012	* CCMR3 OC5M LL_TIM_OC_SetMode\n
<>	157:ff67d9f36b67	2013	* CCMR3 OC6M LL_TIM_OC_SetMode
<>	157:ff67d9f36b67	2014	* @endif
<>	157:ff67d9f36b67	2015	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2016	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	2017	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	2018	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	2019	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	2020	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	2021	* @arg @ref LL_TIM_CHANNEL_CH5
<>	157:ff67d9f36b67	2022	* @arg @ref LL_TIM_CHANNEL_CH6
<>	157:ff67d9f36b67	2023	* @param Mode This parameter can be one of the following values:
<>	157:ff67d9f36b67	2024	* @arg @ref LL_TIM_OCMODE_FROZEN
<>	157:ff67d9f36b67	2025	* @arg @ref LL_TIM_OCMODE_ACTIVE
<>	157:ff67d9f36b67	2026	* @arg @ref LL_TIM_OCMODE_INACTIVE
<>	157:ff67d9f36b67	2027	* @arg @ref LL_TIM_OCMODE_TOGGLE
<>	157:ff67d9f36b67	2028	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
<>	157:ff67d9f36b67	2029	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
<>	157:ff67d9f36b67	2030	* @arg @ref LL_TIM_OCMODE_PWM1
<>	157:ff67d9f36b67	2031	* @arg @ref LL_TIM_OCMODE_PWM2
<>	157:ff67d9f36b67	2032	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
<>	157:ff67d9f36b67	2033	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
<>	157:ff67d9f36b67	2034	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
<>	157:ff67d9f36b67	2035	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
<>	157:ff67d9f36b67	2036	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
<>	157:ff67d9f36b67	2037	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
<>	157:ff67d9f36b67	2038	* @note The following OC modes are not available on all F3 devices :
<>	157:ff67d9f36b67	2039	* - LL_TIM_OCMODE_RETRIG_OPM1
<>	157:ff67d9f36b67	2040	* - LL_TIM_OCMODE_RETRIG_OPM2
<>	157:ff67d9f36b67	2041	* - LL_TIM_OCMODE_COMBINED_PWM1
<>	157:ff67d9f36b67	2042	* - LL_TIM_OCMODE_COMBINED_PWM2
<>	157:ff67d9f36b67	2043	* - LL_TIM_OCMODE_ASSYMETRIC_PWM1
<>	157:ff67d9f36b67	2044	* - LL_TIM_OCMODE_ASSYMETRIC_PWM2
<>	157:ff67d9f36b67	2045	* @note CH5 and CH6 channels are not available for all F3 devices
<>	157:ff67d9f36b67	2046	* @retval None
<>	157:ff67d9f36b67	2047	*/
<>	157:ff67d9f36b67	2048	__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
<>	157:ff67d9f36b67	2049	{
<>	157:ff67d9f36b67	2050	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	157:ff67d9f36b67	2051	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	157:ff67d9f36b67	2052	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
<>	157:ff67d9f36b67	2053	}
<>	157:ff67d9f36b67	2054
<>	157:ff67d9f36b67	2055	/**
<>	157:ff67d9f36b67	2056	* @brief Get the output compare mode of an output channel.
<>	157:ff67d9f36b67	2057	* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
<>	157:ff67d9f36b67	2058	* CCMR1 OC2M LL_TIM_OC_GetMode\n
<>	157:ff67d9f36b67	2059	* CCMR2 OC3M LL_TIM_OC_GetMode\n
<>	157:ff67d9f36b67	2060	* CCMR2 OC4M LL_TIM_OC_GetMode\n
<>	157:ff67d9f36b67	2061	* @if STM32F334x8
<>	157:ff67d9f36b67	2062	* CCMR3 OC5M LL_TIM_OC_GetMode\n
<>	157:ff67d9f36b67	2063	* CCMR3 OC6M LL_TIM_OC_GetMode
<>	157:ff67d9f36b67	2064	* @elseif STM32F303xC
<>	157:ff67d9f36b67	2065	* CCMR3 OC5M LL_TIM_OC_GetMode\n
<>	157:ff67d9f36b67	2066	* CCMR3 OC6M LL_TIM_OC_GetMode
<>	157:ff67d9f36b67	2067	* @elseif STM32F302x8
<>	157:ff67d9f36b67	2068	* CCMR3 OC5M LL_TIM_OC_GetMode\n
<>	157:ff67d9f36b67	2069	* CCMR3 OC6M LL_TIM_OC_GetMode
<>	157:ff67d9f36b67	2070	* @endif
<>	157:ff67d9f36b67	2071	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2072	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	2073	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	2074	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	2075	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	2076	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	2077	* @arg @ref LL_TIM_CHANNEL_CH5
<>	157:ff67d9f36b67	2078	* @arg @ref LL_TIM_CHANNEL_CH6
<>	157:ff67d9f36b67	2079	* @note The following OC modes are not available on all F3 devices :
<>	157:ff67d9f36b67	2080	* - LL_TIM_OCMODE_RETRIG_OPM1
<>	157:ff67d9f36b67	2081	* - LL_TIM_OCMODE_RETRIG_OPM2
<>	157:ff67d9f36b67	2082	* - LL_TIM_OCMODE_COMBINED_PWM1
<>	157:ff67d9f36b67	2083	* - LL_TIM_OCMODE_COMBINED_PWM2
<>	157:ff67d9f36b67	2084	* - LL_TIM_OCMODE_ASSYMETRIC_PWM1
<>	157:ff67d9f36b67	2085	* - LL_TIM_OCMODE_ASSYMETRIC_PWM2
<>	157:ff67d9f36b67	2086	* @note CH5 and CH6 channels are not available for all F3 devices
<>	157:ff67d9f36b67	2087	* @retval Returned value can be one of the following values:
<>	157:ff67d9f36b67	2088	* @arg @ref LL_TIM_OCMODE_FROZEN
<>	157:ff67d9f36b67	2089	* @arg @ref LL_TIM_OCMODE_ACTIVE
<>	157:ff67d9f36b67	2090	* @arg @ref LL_TIM_OCMODE_INACTIVE
<>	157:ff67d9f36b67	2091	* @arg @ref LL_TIM_OCMODE_TOGGLE
<>	157:ff67d9f36b67	2092	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
<>	157:ff67d9f36b67	2093	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
<>	157:ff67d9f36b67	2094	* @arg @ref LL_TIM_OCMODE_PWM1
<>	157:ff67d9f36b67	2095	* @arg @ref LL_TIM_OCMODE_PWM2
<>	157:ff67d9f36b67	2096	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
<>	157:ff67d9f36b67	2097	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
<>	157:ff67d9f36b67	2098	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
<>	157:ff67d9f36b67	2099	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
<>	157:ff67d9f36b67	2100	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
<>	157:ff67d9f36b67	2101	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
<>	157:ff67d9f36b67	2102	*/
<>	157:ff67d9f36b67	2103	__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
<>	157:ff67d9f36b67	2104	{
<>	157:ff67d9f36b67	2105	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	157:ff67d9f36b67	2106	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	157:ff67d9f36b67	2107	return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
<>	157:ff67d9f36b67	2108	}
<>	157:ff67d9f36b67	2109
<>	157:ff67d9f36b67	2110	/**
<>	157:ff67d9f36b67	2111	* @brief Set the polarity of an output channel.
<>	157:ff67d9f36b67	2112	* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
<>	157:ff67d9f36b67	2113	* CCER CC1NP LL_TIM_OC_SetPolarity\n
<>	157:ff67d9f36b67	2114	* CCER CC2P LL_TIM_OC_SetPolarity\n
<>	157:ff67d9f36b67	2115	* CCER CC2NP LL_TIM_OC_SetPolarity\n
<>	157:ff67d9f36b67	2116	* CCER CC3P LL_TIM_OC_SetPolarity\n
<>	157:ff67d9f36b67	2117	* CCER CC3NP LL_TIM_OC_SetPolarity\n
<>	157:ff67d9f36b67	2118	* CCER CC4P LL_TIM_OC_SetPolarity\n
<>	157:ff67d9f36b67	2119	* CCER CC5P LL_TIM_OC_SetPolarity\n
<>	157:ff67d9f36b67	2120	* CCER CC6P LL_TIM_OC_SetPolarity
<>	157:ff67d9f36b67	2121	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2122	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	2123	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	2124	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	157:ff67d9f36b67	2125	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	2126	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	157:ff67d9f36b67	2127	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	2128	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	157:ff67d9f36b67	2129	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	2130	* @arg @ref LL_TIM_CHANNEL_CH5
<>	157:ff67d9f36b67	2131	* @arg @ref LL_TIM_CHANNEL_CH6
<>	157:ff67d9f36b67	2132	* @param Polarity This parameter can be one of the following values:
<>	157:ff67d9f36b67	2133	* @arg @ref LL_TIM_OCPOLARITY_HIGH
<>	157:ff67d9f36b67	2134	* @arg @ref LL_TIM_OCPOLARITY_LOW
<>	157:ff67d9f36b67	2135	* @note CH5 and CH6 channels are not available for all F3 devices
<>	157:ff67d9f36b67	2136	* @retval None
<>	157:ff67d9f36b67	2137	*/
<>	157:ff67d9f36b67	2138	__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
<>	157:ff67d9f36b67	2139	{
<>	157:ff67d9f36b67	2140	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	157:ff67d9f36b67	2141	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
<>	157:ff67d9f36b67	2142	}
<>	157:ff67d9f36b67	2143
<>	157:ff67d9f36b67	2144	/**
<>	157:ff67d9f36b67	2145	* @brief Get the polarity of an output channel.
<>	157:ff67d9f36b67	2146	* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
<>	157:ff67d9f36b67	2147	* CCER CC1NP LL_TIM_OC_GetPolarity\n
<>	157:ff67d9f36b67	2148	* CCER CC2P LL_TIM_OC_GetPolarity\n
<>	157:ff67d9f36b67	2149	* CCER CC2NP LL_TIM_OC_GetPolarity\n
<>	157:ff67d9f36b67	2150	* CCER CC3P LL_TIM_OC_GetPolarity\n
<>	157:ff67d9f36b67	2151	* CCER CC3NP LL_TIM_OC_GetPolarity\n
<>	157:ff67d9f36b67	2152	* CCER CC4P LL_TIM_OC_GetPolarity\n
<>	157:ff67d9f36b67	2153	* CCER CC5P LL_TIM_OC_GetPolarity\n
<>	157:ff67d9f36b67	2154	* CCER CC6P LL_TIM_OC_GetPolarity
<>	157:ff67d9f36b67	2155	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2156	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	2157	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	2158	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	157:ff67d9f36b67	2159	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	2160	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	157:ff67d9f36b67	2161	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	2162	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	157:ff67d9f36b67	2163	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	2164	* @arg @ref LL_TIM_CHANNEL_CH5
<>	157:ff67d9f36b67	2165	* @arg @ref LL_TIM_CHANNEL_CH6
<>	157:ff67d9f36b67	2166	* @note CH5 and CH6 channels are not available for all F3 devices
<>	157:ff67d9f36b67	2167	* @retval Returned value can be one of the following values:
<>	157:ff67d9f36b67	2168	* @arg @ref LL_TIM_OCPOLARITY_HIGH
<>	157:ff67d9f36b67	2169	* @arg @ref LL_TIM_OCPOLARITY_LOW
<>	157:ff67d9f36b67	2170	*/
<>	157:ff67d9f36b67	2171	__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
<>	157:ff67d9f36b67	2172	{
<>	157:ff67d9f36b67	2173	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	157:ff67d9f36b67	2174	return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
<>	157:ff67d9f36b67	2175	}
<>	157:ff67d9f36b67	2176
<>	157:ff67d9f36b67	2177	/**
<>	157:ff67d9f36b67	2178	* @brief Set the IDLE state of an output channel
<>	157:ff67d9f36b67	2179	* @note This function is significant only for the timer instances
<>	157:ff67d9f36b67	2180	* supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
<>	157:ff67d9f36b67	2181	* can be used to check whether or not a timer instance provides
<>	157:ff67d9f36b67	2182	* a break input.
<>	157:ff67d9f36b67	2183	* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
<>	157:ff67d9f36b67	2184	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
<>	157:ff67d9f36b67	2185	* CR2 OIS2 LL_TIM_OC_SetIdleState\n
<>	157:ff67d9f36b67	2186	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
<>	157:ff67d9f36b67	2187	* CR2 OIS3 LL_TIM_OC_SetIdleState\n
<>	157:ff67d9f36b67	2188	* CR2 OIS3N LL_TIM_OC_SetIdleState\n
<>	157:ff67d9f36b67	2189	* CR2 OIS4 LL_TIM_OC_SetIdleState\n
<>	157:ff67d9f36b67	2190	* CR2 OIS5 LL_TIM_OC_SetIdleState\n
<>	157:ff67d9f36b67	2191	* CR2 OIS6 LL_TIM_OC_SetIdleState
<>	157:ff67d9f36b67	2192	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2193	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	2194	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	2195	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	157:ff67d9f36b67	2196	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	2197	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	157:ff67d9f36b67	2198	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	2199	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	157:ff67d9f36b67	2200	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	2201	* @arg @ref LL_TIM_CHANNEL_CH5
<>	157:ff67d9f36b67	2202	* @arg @ref LL_TIM_CHANNEL_CH6
<>	157:ff67d9f36b67	2203	* @param IdleState This parameter can be one of the following values:
<>	157:ff67d9f36b67	2204	* @arg @ref LL_TIM_OCIDLESTATE_LOW
<>	157:ff67d9f36b67	2205	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
<>	157:ff67d9f36b67	2206	* @note CH5 and CH6 channels are not available for all F3 devices
<>	157:ff67d9f36b67	2207	* @retval None
<>	157:ff67d9f36b67	2208	*/
<>	157:ff67d9f36b67	2209	__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
<>	157:ff67d9f36b67	2210	{
<>	157:ff67d9f36b67	2211	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	157:ff67d9f36b67	2212	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
<>	157:ff67d9f36b67	2213	}
<>	157:ff67d9f36b67	2214
<>	157:ff67d9f36b67	2215	/**
<>	157:ff67d9f36b67	2216	* @brief Get the IDLE state of an output channel
<>	157:ff67d9f36b67	2217	* @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
<>	157:ff67d9f36b67	2218	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
<>	157:ff67d9f36b67	2219	* CR2 OIS2 LL_TIM_OC_GetIdleState\n
<>	157:ff67d9f36b67	2220	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
<>	157:ff67d9f36b67	2221	* CR2 OIS3 LL_TIM_OC_GetIdleState\n
<>	157:ff67d9f36b67	2222	* CR2 OIS3N LL_TIM_OC_GetIdleState\n
<>	157:ff67d9f36b67	2223	* CR2 OIS4 LL_TIM_OC_GetIdleState\n
<>	157:ff67d9f36b67	2224	* CR2 OIS5 LL_TIM_OC_GetIdleState\n
<>	157:ff67d9f36b67	2225	* CR2 OIS6 LL_TIM_OC_GetIdleState
<>	157:ff67d9f36b67	2226	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2227	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	2228	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	2229	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	157:ff67d9f36b67	2230	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	2231	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	157:ff67d9f36b67	2232	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	2233	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	157:ff67d9f36b67	2234	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	2235	* @arg @ref LL_TIM_CHANNEL_CH5
<>	157:ff67d9f36b67	2236	* @arg @ref LL_TIM_CHANNEL_CH6
<>	157:ff67d9f36b67	2237	* @note CH5 and CH6 channels are not available for all F3 devices
<>	157:ff67d9f36b67	2238	* @retval Returned value can be one of the following values:
<>	157:ff67d9f36b67	2239	* @arg @ref LL_TIM_OCIDLESTATE_LOW
<>	157:ff67d9f36b67	2240	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
<>	157:ff67d9f36b67	2241	*/
<>	157:ff67d9f36b67	2242	__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
<>	157:ff67d9f36b67	2243	{
<>	157:ff67d9f36b67	2244	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	157:ff67d9f36b67	2245	return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
<>	157:ff67d9f36b67	2246	}
<>	157:ff67d9f36b67	2247
<>	157:ff67d9f36b67	2248	/**
<>	157:ff67d9f36b67	2249	* @brief Enable fast mode for the output channel.
<>	157:ff67d9f36b67	2250	* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
<>	157:ff67d9f36b67	2251	* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
<>	157:ff67d9f36b67	2252	* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
<>	157:ff67d9f36b67	2253	* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
<>	157:ff67d9f36b67	2254	* CCMR2 OC4FE LL_TIM_OC_EnableFast\n
<>	157:ff67d9f36b67	2255	* @if STM32F334x8
<>	157:ff67d9f36b67	2256	* CCMR3 OC5FE LL_TIM_OC_EnableFast\n
<>	157:ff67d9f36b67	2257	* CCMR3 OC6FE LL_TIM_OC_EnableFast
<>	157:ff67d9f36b67	2258	* @elseif STM32F303xC
<>	157:ff67d9f36b67	2259	* CCMR3 OC5FE LL_TIM_OC_EnableFast\n
<>	157:ff67d9f36b67	2260	* CCMR3 OC6FE LL_TIM_OC_EnableFast
<>	157:ff67d9f36b67	2261	* @elseif STM32F302x8
<>	157:ff67d9f36b67	2262	* CCMR3 OC5FE LL_TIM_OC_EnableFast\n
<>	157:ff67d9f36b67	2263	* CCMR3 OC6FE LL_TIM_OC_EnableFast
<>	157:ff67d9f36b67	2264	* @endif
<>	157:ff67d9f36b67	2265	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2266	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	2267	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	2268	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	2269	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	2270	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	2271	* @arg @ref LL_TIM_CHANNEL_CH5
<>	157:ff67d9f36b67	2272	* @arg @ref LL_TIM_CHANNEL_CH6
<>	157:ff67d9f36b67	2273	* @note OC5FE and OC6FE are not available for all F3 devices
<>	157:ff67d9f36b67	2274	* @note CH5 and CH6 channels are not available for all F3 devices
<>	157:ff67d9f36b67	2275	* @retval None
<>	157:ff67d9f36b67	2276	*/
<>	157:ff67d9f36b67	2277	__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
<>	157:ff67d9f36b67	2278	{
<>	157:ff67d9f36b67	2279	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	157:ff67d9f36b67	2280	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	157:ff67d9f36b67	2281	SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
<>	157:ff67d9f36b67	2282
<>	157:ff67d9f36b67	2283	}
<>	157:ff67d9f36b67	2284
<>	157:ff67d9f36b67	2285	/**
<>	157:ff67d9f36b67	2286	* @brief Disable fast mode for the output channel.
<>	157:ff67d9f36b67	2287	* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
<>	157:ff67d9f36b67	2288	* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
<>	157:ff67d9f36b67	2289	* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
<>	157:ff67d9f36b67	2290	* CCMR2 OC4FE LL_TIM_OC_DisableFast\n
<>	157:ff67d9f36b67	2291	* @if STM32F334x8
<>	157:ff67d9f36b67	2292	* CCMR3 OC5FE LL_TIM_OC_DisableFast\n
<>	157:ff67d9f36b67	2293	* CCMR3 OC6FE LL_TIM_OC_DisableFast
<>	157:ff67d9f36b67	2294	* @elseif STM32F303xC
<>	157:ff67d9f36b67	2295	* CCMR3 OC5FE LL_TIM_OC_DisableFast\n
<>	157:ff67d9f36b67	2296	* CCMR3 OC6FE LL_TIM_OC_DisableFast
<>	157:ff67d9f36b67	2297	* @elseif STM32F302x8
<>	157:ff67d9f36b67	2298	* CCMR3 OC5FE LL_TIM_OC_DisableFast\n
<>	157:ff67d9f36b67	2299	* CCMR3 OC6FE LL_TIM_OC_DisableFast
<>	157:ff67d9f36b67	2300	* @endif
<>	157:ff67d9f36b67	2301	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2302	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	2303	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	2304	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	2305	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	2306	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	2307	* @arg @ref LL_TIM_CHANNEL_CH5
<>	157:ff67d9f36b67	2308	* @arg @ref LL_TIM_CHANNEL_CH6
<>	157:ff67d9f36b67	2309	* @note OC5FE and OC6FE are not available for all F3 devices
<>	157:ff67d9f36b67	2310	* @note CH5 and CH6 channels are not available for all F3 devices
<>	157:ff67d9f36b67	2311	* @retval None
<>	157:ff67d9f36b67	2312	*/
<>	157:ff67d9f36b67	2313	__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
<>	157:ff67d9f36b67	2314	{
<>	157:ff67d9f36b67	2315	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	157:ff67d9f36b67	2316	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	157:ff67d9f36b67	2317	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
<>	157:ff67d9f36b67	2318
<>	157:ff67d9f36b67	2319	}
<>	157:ff67d9f36b67	2320
<>	157:ff67d9f36b67	2321	/**
<>	157:ff67d9f36b67	2322	* @brief Indicates whether fast mode is enabled for the output channel.
<>	157:ff67d9f36b67	2323	* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
<>	157:ff67d9f36b67	2324	* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
<>	157:ff67d9f36b67	2325	* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
<>	157:ff67d9f36b67	2326	* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
<>	157:ff67d9f36b67	2327	* @if STM32F334x8
<>	157:ff67d9f36b67	2328	* CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
<>	157:ff67d9f36b67	2329	* CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
<>	157:ff67d9f36b67	2330	* @elseif STM32F303xC
<>	157:ff67d9f36b67	2331	* CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
<>	157:ff67d9f36b67	2332	* CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
<>	157:ff67d9f36b67	2333	* @elseif STM32F302x8
<>	157:ff67d9f36b67	2334	* CCMR3 OC5FE LL_TIM_OC_DisableFast\n
<>	157:ff67d9f36b67	2335	* CCMR3 OC6FE LL_TIM_OC_DisableFast
<>	157:ff67d9f36b67	2336	* @endif
<>	157:ff67d9f36b67	2337	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2338	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	2339	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	2340	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	2341	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	2342	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	2343	* @arg @ref LL_TIM_CHANNEL_CH5
<>	157:ff67d9f36b67	2344	* @arg @ref LL_TIM_CHANNEL_CH6
<>	157:ff67d9f36b67	2345	* @note OC5FE and OC6FE are not available for all F3 devices
<>	157:ff67d9f36b67	2346	* @note CH5 and CH6 channels are not available for all F3 devices
<>	157:ff67d9f36b67	2347	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	2348	*/
<>	157:ff67d9f36b67	2349	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
<>	157:ff67d9f36b67	2350	{
<>	157:ff67d9f36b67	2351	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	157:ff67d9f36b67	2352	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	157:ff67d9f36b67	2353	register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
<>	157:ff67d9f36b67	2354	return (READ_BIT(*pReg, bitfield) == bitfield);
<>	157:ff67d9f36b67	2355	}
<>	157:ff67d9f36b67	2356
<>	157:ff67d9f36b67	2357	/**
<>	157:ff67d9f36b67	2358	* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
<>	157:ff67d9f36b67	2359	* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
<>	157:ff67d9f36b67	2360	* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
<>	157:ff67d9f36b67	2361	* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
<>	157:ff67d9f36b67	2362	* CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
<>	157:ff67d9f36b67	2363	* @if STM32F334x8
<>	157:ff67d9f36b67	2364	* CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
<>	157:ff67d9f36b67	2365	* CCMR3 OC6PE LL_TIM_OC_EnablePreload
<>	157:ff67d9f36b67	2366	* @elseif STM32F303xC
<>	157:ff67d9f36b67	2367	* CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
<>	157:ff67d9f36b67	2368	* CCMR3 OC6PE LL_TIM_OC_EnablePreload
<>	157:ff67d9f36b67	2369	* @elseif STM32F302x8
<>	157:ff67d9f36b67	2370	* CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
<>	157:ff67d9f36b67	2371	* CCMR3 OC6PE LL_TIM_OC_EnablePreload
<>	157:ff67d9f36b67	2372	* @endif
<>	157:ff67d9f36b67	2373	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2374	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	2375	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	2376	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	2377	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	2378	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	2379	* @arg @ref LL_TIM_CHANNEL_CH5
<>	157:ff67d9f36b67	2380	* @arg @ref LL_TIM_CHANNEL_CH6
<>	157:ff67d9f36b67	2381	* @note OC5PE and OC6PE are not available for all F3 devices
<>	157:ff67d9f36b67	2382	* @note CH5 and CH6 channels are not available for all F3 devices
<>	157:ff67d9f36b67	2383	* @retval None
<>	157:ff67d9f36b67	2384	*/
<>	157:ff67d9f36b67	2385	__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
<>	157:ff67d9f36b67	2386	{
<>	157:ff67d9f36b67	2387	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	157:ff67d9f36b67	2388	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	157:ff67d9f36b67	2389	SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
<>	157:ff67d9f36b67	2390	}
<>	157:ff67d9f36b67	2391
<>	157:ff67d9f36b67	2392	/**
<>	157:ff67d9f36b67	2393	* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
<>	157:ff67d9f36b67	2394	* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
<>	157:ff67d9f36b67	2395	* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
<>	157:ff67d9f36b67	2396	* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
<>	157:ff67d9f36b67	2397	* CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
<>	157:ff67d9f36b67	2398	* @if STM32F334x8
<>	157:ff67d9f36b67	2399	* CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
<>	157:ff67d9f36b67	2400	* CCMR3 OC6PE LL_TIM_OC_DisablePreload
<>	157:ff67d9f36b67	2401	* @elseif STM32F303xC
<>	157:ff67d9f36b67	2402	* CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
<>	157:ff67d9f36b67	2403	* CCMR3 OC6PE LL_TIM_OC_DisablePreload
<>	157:ff67d9f36b67	2404	* @elseif STM32F302x8
<>	157:ff67d9f36b67	2405	* CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
<>	157:ff67d9f36b67	2406	* CCMR3 OC6PE LL_TIM_OC_DisablePreload
<>	157:ff67d9f36b67	2407	* @endif
<>	157:ff67d9f36b67	2408	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2409	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	2410	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	2411	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	2412	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	2413	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	2414	* @arg @ref LL_TIM_CHANNEL_CH5
<>	157:ff67d9f36b67	2415	* @arg @ref LL_TIM_CHANNEL_CH6
<>	157:ff67d9f36b67	2416	* @note OC5PE and OC6PE are not available for all F3 devices
<>	157:ff67d9f36b67	2417	* @note CH5 and CH6 channels are not available for all F3 devices
<>	157:ff67d9f36b67	2418	* @retval None
<>	157:ff67d9f36b67	2419	*/
<>	157:ff67d9f36b67	2420	__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
<>	157:ff67d9f36b67	2421	{
<>	157:ff67d9f36b67	2422	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	157:ff67d9f36b67	2423	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	157:ff67d9f36b67	2424	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
<>	157:ff67d9f36b67	2425	}
<>	157:ff67d9f36b67	2426
<>	157:ff67d9f36b67	2427	/**
<>	157:ff67d9f36b67	2428	* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
<>	157:ff67d9f36b67	2429	* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
<>	157:ff67d9f36b67	2430	* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
<>	157:ff67d9f36b67	2431	* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
<>	157:ff67d9f36b67	2432	* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
<>	157:ff67d9f36b67	2433	* @if STM32F334x8
<>	157:ff67d9f36b67	2434	* CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
<>	157:ff67d9f36b67	2435	* CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
<>	157:ff67d9f36b67	2436	* @elseif STM32F303xC
<>	157:ff67d9f36b67	2437	* CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
<>	157:ff67d9f36b67	2438	* CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
<>	157:ff67d9f36b67	2439	* @elseif STM32F302x8
<>	157:ff67d9f36b67	2440	* CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
<>	157:ff67d9f36b67	2441	* CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
<>	157:ff67d9f36b67	2442	* @endif
<>	157:ff67d9f36b67	2443	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2444	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	2445	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	2446	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	2447	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	2448	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	2449	* @arg @ref LL_TIM_CHANNEL_CH5
<>	157:ff67d9f36b67	2450	* @arg @ref LL_TIM_CHANNEL_CH6
<>	157:ff67d9f36b67	2451	* @note OC5PE and OC6PE are not available for all F3 devices
<>	157:ff67d9f36b67	2452	* @note CH5 and CH6 channels are not available for all F3 devices
<>	157:ff67d9f36b67	2453	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	2454	*/
<>	157:ff67d9f36b67	2455	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
<>	157:ff67d9f36b67	2456	{
<>	157:ff67d9f36b67	2457	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	157:ff67d9f36b67	2458	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	157:ff67d9f36b67	2459	register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
<>	157:ff67d9f36b67	2460	return (READ_BIT(*pReg, bitfield) == bitfield);
<>	157:ff67d9f36b67	2461	}
<>	157:ff67d9f36b67	2462
<>	157:ff67d9f36b67	2463	/**
<>	157:ff67d9f36b67	2464	* @brief Enable clearing the output channel on an external event.
<>	157:ff67d9f36b67	2465	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
<>	157:ff67d9f36b67	2466	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
<>	157:ff67d9f36b67	2467	* or not a timer instance can clear the OCxREF signal on an external event.
<>	157:ff67d9f36b67	2468	* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
<>	157:ff67d9f36b67	2469	* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
<>	157:ff67d9f36b67	2470	* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
<>	157:ff67d9f36b67	2471	* CCMR2 OC4CE LL_TIM_OC_EnableClear\n
<>	157:ff67d9f36b67	2472	* @if STM32F334x8
<>	157:ff67d9f36b67	2473	* CCMR3 OC5CE LL_TIM_OC_EnableClear\n
<>	157:ff67d9f36b67	2474	* CCMR3 OC6CE LL_TIM_OC_EnableClear
<>	157:ff67d9f36b67	2475	* @elseif STM32F303xC
<>	157:ff67d9f36b67	2476	* CCMR3 OC5CE LL_TIM_OC_EnableClear\n
<>	157:ff67d9f36b67	2477	* CCMR3 OC6CE LL_TIM_OC_EnableClear
<>	157:ff67d9f36b67	2478	* @elseif STM32F302x8
<>	157:ff67d9f36b67	2479	* CCMR3 OC5CE LL_TIM_OC_EnableClear\n
<>	157:ff67d9f36b67	2480	* CCMR3 OC6CE LL_TIM_OC_EnableClear
<>	157:ff67d9f36b67	2481	* @endif
<>	157:ff67d9f36b67	2482	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2483	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	2484	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	2485	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	2486	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	2487	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	2488	* @arg @ref LL_TIM_CHANNEL_CH5
<>	157:ff67d9f36b67	2489	* @arg @ref LL_TIM_CHANNEL_CH6
<>	157:ff67d9f36b67	2490	* @note OC5CE and OC6CE are not available for all F3 devices
<>	157:ff67d9f36b67	2491	* @note CH5 and CH6 channels are not available for all F3 devices
<>	157:ff67d9f36b67	2492	* @retval None
<>	157:ff67d9f36b67	2493	*/
<>	157:ff67d9f36b67	2494	__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
<>	157:ff67d9f36b67	2495	{
<>	157:ff67d9f36b67	2496	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	157:ff67d9f36b67	2497	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	157:ff67d9f36b67	2498	SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
<>	157:ff67d9f36b67	2499	}
<>	157:ff67d9f36b67	2500
<>	157:ff67d9f36b67	2501	/**
<>	157:ff67d9f36b67	2502	* @brief Disable clearing the output channel on an external event.
<>	157:ff67d9f36b67	2503	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
<>	157:ff67d9f36b67	2504	* or not a timer instance can clear the OCxREF signal on an external event.
<>	157:ff67d9f36b67	2505	* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
<>	157:ff67d9f36b67	2506	* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
<>	157:ff67d9f36b67	2507	* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
<>	157:ff67d9f36b67	2508	* CCMR2 OC4CE LL_TIM_OC_DisableClear\n
<>	157:ff67d9f36b67	2509	* @if STM32F334x8
<>	157:ff67d9f36b67	2510	* CCMR3 OC5CE LL_TIM_OC_DisableClear\n
<>	157:ff67d9f36b67	2511	* CCMR3 OC6CE LL_TIM_OC_DisableClear
<>	157:ff67d9f36b67	2512	* @elseif STM32F303xC
<>	157:ff67d9f36b67	2513	* CCMR3 OC5CE LL_TIM_OC_DisableClear\n
<>	157:ff67d9f36b67	2514	* CCMR3 OC6CE LL_TIM_OC_DisableClear
<>	157:ff67d9f36b67	2515	* @elseif STM32F302x8
<>	157:ff67d9f36b67	2516	* CCMR3 OC5CE LL_TIM_OC_DisableClear\n
<>	157:ff67d9f36b67	2517	* CCMR3 OC6CE LL_TIM_OC_DisableClear
<>	157:ff67d9f36b67	2518	* @endif
<>	157:ff67d9f36b67	2519	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2520	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	2521	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	2522	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	2523	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	2524	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	2525	* @arg @ref LL_TIM_CHANNEL_CH5
<>	157:ff67d9f36b67	2526	* @arg @ref LL_TIM_CHANNEL_CH6
<>	157:ff67d9f36b67	2527	* @note OC5CE and OC6CE are not available for all F3 devices
<>	157:ff67d9f36b67	2528	* @note CH5 and CH6 channels are not available for all F3 devices
<>	157:ff67d9f36b67	2529	* @retval None
<>	157:ff67d9f36b67	2530	*/
<>	157:ff67d9f36b67	2531	__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
<>	157:ff67d9f36b67	2532	{
<>	157:ff67d9f36b67	2533	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	157:ff67d9f36b67	2534	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	157:ff67d9f36b67	2535	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
<>	157:ff67d9f36b67	2536	}
<>	157:ff67d9f36b67	2537
<>	157:ff67d9f36b67	2538	/**
<>	157:ff67d9f36b67	2539	* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
<>	157:ff67d9f36b67	2540	* @note This function enables clearing the output channel on an external event.
<>	157:ff67d9f36b67	2541	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
<>	157:ff67d9f36b67	2542	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
<>	157:ff67d9f36b67	2543	* or not a timer instance can clear the OCxREF signal on an external event.
<>	157:ff67d9f36b67	2544	* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
<>	157:ff67d9f36b67	2545	* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
<>	157:ff67d9f36b67	2546	* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
<>	157:ff67d9f36b67	2547	* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
<>	157:ff67d9f36b67	2548	* @if STM32F334x8
<>	157:ff67d9f36b67	2549	* CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
<>	157:ff67d9f36b67	2550	* CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
<>	157:ff67d9f36b67	2551	* @elseif STM32F303xC
<>	157:ff67d9f36b67	2552	* CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
<>	157:ff67d9f36b67	2553	* CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
<>	157:ff67d9f36b67	2554	* @elseif STM32F302x8
<>	157:ff67d9f36b67	2555	* CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
<>	157:ff67d9f36b67	2556	* CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
<>	157:ff67d9f36b67	2557	* @endif
<>	157:ff67d9f36b67	2558	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2559	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	2560	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	2561	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	2562	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	2563	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	2564	* @arg @ref LL_TIM_CHANNEL_CH5
<>	157:ff67d9f36b67	2565	* @arg @ref LL_TIM_CHANNEL_CH6
<>	157:ff67d9f36b67	2566	* @note OC5CE and OC6CE are not available for all F3 devices
<>	157:ff67d9f36b67	2567	* @note CH5 and CH6 channels are not available for all F3 devices
<>	157:ff67d9f36b67	2568	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	2569	*/
<>	157:ff67d9f36b67	2570	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
<>	157:ff67d9f36b67	2571	{
<>	157:ff67d9f36b67	2572	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	157:ff67d9f36b67	2573	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	157:ff67d9f36b67	2574	register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
<>	157:ff67d9f36b67	2575	return (READ_BIT(*pReg, bitfield) == bitfield);
<>	157:ff67d9f36b67	2576	}
<>	157:ff67d9f36b67	2577
<>	157:ff67d9f36b67	2578	/**
<>	157:ff67d9f36b67	2579	* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
<>	157:ff67d9f36b67	2580	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	2581	* dead-time insertion feature is supported by a timer instance.
<>	157:ff67d9f36b67	2582	* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
<>	157:ff67d9f36b67	2583	* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
<>	157:ff67d9f36b67	2584	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2585	* @param DeadTime between Min_Data=0 and Max_Data=255
<>	157:ff67d9f36b67	2586	* @retval None
<>	157:ff67d9f36b67	2587	*/
<>	157:ff67d9f36b67	2588	__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
<>	157:ff67d9f36b67	2589	{
<>	157:ff67d9f36b67	2590	MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
<>	157:ff67d9f36b67	2591	}
<>	157:ff67d9f36b67	2592
<>	157:ff67d9f36b67	2593	/**
<>	157:ff67d9f36b67	2594	* @brief Set compare value for output channel 1 (TIMx_CCR1).
<>	157:ff67d9f36b67	2595	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	157:ff67d9f36b67	2596	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	2597	* whether or not a timer instance supports a 32 bits counter.
<>	157:ff67d9f36b67	2598	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	2599	* output channel 1 is supported by a timer instance.
<>	157:ff67d9f36b67	2600	* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
<>	157:ff67d9f36b67	2601	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2602	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	157:ff67d9f36b67	2603	* @retval None
<>	157:ff67d9f36b67	2604	*/
<>	157:ff67d9f36b67	2605	__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
<>	157:ff67d9f36b67	2606	{
<>	157:ff67d9f36b67	2607	WRITE_REG(TIMx->CCR1, CompareValue);
<>	157:ff67d9f36b67	2608	}
<>	157:ff67d9f36b67	2609
<>	157:ff67d9f36b67	2610	/**
<>	157:ff67d9f36b67	2611	* @brief Set compare value for output channel 2 (TIMx_CCR2).
<>	157:ff67d9f36b67	2612	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	157:ff67d9f36b67	2613	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	2614	* whether or not a timer instance supports a 32 bits counter.
<>	157:ff67d9f36b67	2615	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	2616	* output channel 2 is supported by a timer instance.
<>	157:ff67d9f36b67	2617	* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
<>	157:ff67d9f36b67	2618	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2619	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	157:ff67d9f36b67	2620	* @retval None
<>	157:ff67d9f36b67	2621	*/
<>	157:ff67d9f36b67	2622	__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
<>	157:ff67d9f36b67	2623	{
<>	157:ff67d9f36b67	2624	WRITE_REG(TIMx->CCR2, CompareValue);
<>	157:ff67d9f36b67	2625	}
<>	157:ff67d9f36b67	2626
<>	157:ff67d9f36b67	2627	/**
<>	157:ff67d9f36b67	2628	* @brief Set compare value for output channel 3 (TIMx_CCR3).
<>	157:ff67d9f36b67	2629	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	157:ff67d9f36b67	2630	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	2631	* whether or not a timer instance supports a 32 bits counter.
<>	157:ff67d9f36b67	2632	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	2633	* output channel is supported by a timer instance.
<>	157:ff67d9f36b67	2634	* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
<>	157:ff67d9f36b67	2635	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2636	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	157:ff67d9f36b67	2637	* @retval None
<>	157:ff67d9f36b67	2638	*/
<>	157:ff67d9f36b67	2639	__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
<>	157:ff67d9f36b67	2640	{
<>	157:ff67d9f36b67	2641	WRITE_REG(TIMx->CCR3, CompareValue);
<>	157:ff67d9f36b67	2642	}
<>	157:ff67d9f36b67	2643
<>	157:ff67d9f36b67	2644	/**
<>	157:ff67d9f36b67	2645	* @brief Set compare value for output channel 4 (TIMx_CCR4).
<>	157:ff67d9f36b67	2646	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	157:ff67d9f36b67	2647	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	2648	* whether or not a timer instance supports a 32 bits counter.
<>	157:ff67d9f36b67	2649	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	2650	* output channel 4 is supported by a timer instance.
<>	157:ff67d9f36b67	2651	* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
<>	157:ff67d9f36b67	2652	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2653	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	157:ff67d9f36b67	2654	* @retval None
<>	157:ff67d9f36b67	2655	*/
<>	157:ff67d9f36b67	2656	__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
<>	157:ff67d9f36b67	2657	{
<>	157:ff67d9f36b67	2658	WRITE_REG(TIMx->CCR4, CompareValue);
<>	157:ff67d9f36b67	2659	}
<>	157:ff67d9f36b67	2660
<>	157:ff67d9f36b67	2661	#if defined(TIM_CCR5_CCR5)
<>	157:ff67d9f36b67	2662	/**
<>	157:ff67d9f36b67	2663	* @brief Set compare value for output channel 5 (TIMx_CCR5).
<>	157:ff67d9f36b67	2664	* @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	2665	* output channel 5 is supported by a timer instance.
<>	157:ff67d9f36b67	2666	* @if STM32F334x8
<>	157:ff67d9f36b67	2667	* @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
<>	157:ff67d9f36b67	2668	* @elseif STM32F303xC
<>	157:ff67d9f36b67	2669	* @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
<>	157:ff67d9f36b67	2670	* @elseif STM32F302x8
<>	157:ff67d9f36b67	2671	* @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
<>	157:ff67d9f36b67	2672	* @endif
<>	157:ff67d9f36b67	2673	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2674	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	157:ff67d9f36b67	2675	* @note CH5 channel is not available for all F3 devices
<>	157:ff67d9f36b67	2676	* @retval None
<>	157:ff67d9f36b67	2677	*/
<>	157:ff67d9f36b67	2678	__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
<>	157:ff67d9f36b67	2679	{
<>	157:ff67d9f36b67	2680	WRITE_REG(TIMx->CCR5, CompareValue);
<>	157:ff67d9f36b67	2681	}
<>	157:ff67d9f36b67	2682
<>	157:ff67d9f36b67	2683	#endif /* TIM_CCR5_CCR5 */
<>	157:ff67d9f36b67	2684	#if defined(TIM_CCR6_CCR6)
<>	157:ff67d9f36b67	2685	/**
<>	157:ff67d9f36b67	2686	* @brief Set compare value for output channel 6 (TIMx_CCR6).
<>	157:ff67d9f36b67	2687	* @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	2688	* output channel 6 is supported by a timer instance.
<>	157:ff67d9f36b67	2689	* @if STM32F344x8
<>	157:ff67d9f36b67	2690	* @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
<>	157:ff67d9f36b67	2691	* @elseif STM32F303xC
<>	157:ff67d9f36b67	2692	* CCR6 CCR6 LL_TIM_OC_SetCompareCH6
<>	157:ff67d9f36b67	2693	* @elseif STM32F302x8
<>	157:ff67d9f36b67	2694	* CCR6 CCR6 LL_TIM_OC_SetCompareCH6
<>	157:ff67d9f36b67	2695	* @endif
<>	157:ff67d9f36b67	2696	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2697	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	157:ff67d9f36b67	2698	* @note CH6 channel is not available for all F3 devices
<>	157:ff67d9f36b67	2699	* @retval None
<>	157:ff67d9f36b67	2700	*/
<>	157:ff67d9f36b67	2701	__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
<>	157:ff67d9f36b67	2702	{
<>	157:ff67d9f36b67	2703	WRITE_REG(TIMx->CCR6, CompareValue);
<>	157:ff67d9f36b67	2704	}
<>	157:ff67d9f36b67	2705
<>	157:ff67d9f36b67	2706	#endif /* TIM_CCR6_CCR6 */
<>	157:ff67d9f36b67	2707	/**
<>	157:ff67d9f36b67	2708	* @brief Get compare value (TIMx_CCR1) set for output channel 1.
<>	157:ff67d9f36b67	2709	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	157:ff67d9f36b67	2710	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	2711	* whether or not a timer instance supports a 32 bits counter.
<>	157:ff67d9f36b67	2712	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	2713	* output channel 1 is supported by a timer instance.
<>	157:ff67d9f36b67	2714	* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
<>	157:ff67d9f36b67	2715	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2716	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	157:ff67d9f36b67	2717	*/
<>	157:ff67d9f36b67	2718	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	2719	{
<>	157:ff67d9f36b67	2720	return (uint32_t)(READ_REG(TIMx->CCR1));
<>	157:ff67d9f36b67	2721	}
<>	157:ff67d9f36b67	2722
<>	157:ff67d9f36b67	2723	/**
<>	157:ff67d9f36b67	2724	* @brief Get compare value (TIMx_CCR2) set for output channel 2.
<>	157:ff67d9f36b67	2725	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	157:ff67d9f36b67	2726	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	2727	* whether or not a timer instance supports a 32 bits counter.
<>	157:ff67d9f36b67	2728	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	2729	* output channel 2 is supported by a timer instance.
<>	157:ff67d9f36b67	2730	* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
<>	157:ff67d9f36b67	2731	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2732	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	157:ff67d9f36b67	2733	*/
<>	157:ff67d9f36b67	2734	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	2735	{
<>	157:ff67d9f36b67	2736	return (uint32_t)(READ_REG(TIMx->CCR2));
<>	157:ff67d9f36b67	2737	}
<>	157:ff67d9f36b67	2738
<>	157:ff67d9f36b67	2739	/**
<>	157:ff67d9f36b67	2740	* @brief Get compare value (TIMx_CCR3) set for output channel 3.
<>	157:ff67d9f36b67	2741	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	157:ff67d9f36b67	2742	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	2743	* whether or not a timer instance supports a 32 bits counter.
<>	157:ff67d9f36b67	2744	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	2745	* output channel 3 is supported by a timer instance.
<>	157:ff67d9f36b67	2746	* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
<>	157:ff67d9f36b67	2747	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2748	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	157:ff67d9f36b67	2749	*/
<>	157:ff67d9f36b67	2750	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	2751	{
<>	157:ff67d9f36b67	2752	return (uint32_t)(READ_REG(TIMx->CCR3));
<>	157:ff67d9f36b67	2753	}
<>	157:ff67d9f36b67	2754
<>	157:ff67d9f36b67	2755	/**
<>	157:ff67d9f36b67	2756	* @brief Get compare value (TIMx_CCR4) set for output channel 4.
<>	157:ff67d9f36b67	2757	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	157:ff67d9f36b67	2758	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	2759	* whether or not a timer instance supports a 32 bits counter.
<>	157:ff67d9f36b67	2760	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	2761	* output channel 4 is supported by a timer instance.
<>	157:ff67d9f36b67	2762	* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
<>	157:ff67d9f36b67	2763	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2764	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	157:ff67d9f36b67	2765	*/
<>	157:ff67d9f36b67	2766	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	2767	{
<>	157:ff67d9f36b67	2768	return (uint32_t)(READ_REG(TIMx->CCR4));
<>	157:ff67d9f36b67	2769	}
<>	157:ff67d9f36b67	2770
<>	157:ff67d9f36b67	2771	#if defined(TIM_CCR5_CCR5)
<>	157:ff67d9f36b67	2772	/**
<>	157:ff67d9f36b67	2773	* @brief Get compare value (TIMx_CCR5) set for output channel 5.
<>	157:ff67d9f36b67	2774	* @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	2775	* output channel 5 is supported by a timer instance.
<>	157:ff67d9f36b67	2776	* @if STM32F334x8
<>	157:ff67d9f36b67	2777	* @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
<>	157:ff67d9f36b67	2778	* @elseif STM32F303xC
<>	157:ff67d9f36b67	2779	* CCR5 CCR5 LL_TIM_OC_GetCompareCH5
<>	157:ff67d9f36b67	2780	* @elseif STM32F302x8
<>	157:ff67d9f36b67	2781	* CCR5 CCR5 LL_TIM_OC_GetCompareCH5
<>	157:ff67d9f36b67	2782	* @endif
<>	157:ff67d9f36b67	2783	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2784	* @note CH5 channel is not available for all F3 devices
<>	157:ff67d9f36b67	2785	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	157:ff67d9f36b67	2786	*/
<>	157:ff67d9f36b67	2787	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	2788	{
<>	157:ff67d9f36b67	2789	return (uint32_t)(READ_REG(TIMx->CCR5));
<>	157:ff67d9f36b67	2790	}
<>	157:ff67d9f36b67	2791
<>	157:ff67d9f36b67	2792	#endif /* TIM_CCR5_CCR5 */
<>	157:ff67d9f36b67	2793	#if defined(TIM_CCR6_CCR6)
<>	157:ff67d9f36b67	2794	/**
<>	157:ff67d9f36b67	2795	* @brief Get compare value (TIMx_CCR6) set for output channel 6.
<>	157:ff67d9f36b67	2796	* @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	2797	* output channel 6 is supported by a timer instance.
<>	157:ff67d9f36b67	2798	* @if STM32F334x8
<>	157:ff67d9f36b67	2799	* @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
<>	157:ff67d9f36b67	2800	* @elseif STM32F303xC
<>	157:ff67d9f36b67	2801	* CCR6 CCR6 LL_TIM_OC_GetCompareCH6
<>	157:ff67d9f36b67	2802	* @elseif STM32F302x8
<>	157:ff67d9f36b67	2803	* CCR6 CCR6 LL_TIM_OC_GetCompareCH6
<>	157:ff67d9f36b67	2804	* @endif
<>	157:ff67d9f36b67	2805	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2806	* @note CH6 channel is not available for all F3 devices
<>	157:ff67d9f36b67	2807	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	157:ff67d9f36b67	2808	*/
<>	157:ff67d9f36b67	2809	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	2810	{
<>	157:ff67d9f36b67	2811	return (uint32_t)(READ_REG(TIMx->CCR6));
<>	157:ff67d9f36b67	2812	}
<>	157:ff67d9f36b67	2813
<>	157:ff67d9f36b67	2814	#endif /* TIM_CCR6_CCR6 */
<>	157:ff67d9f36b67	2815	#if defined(TIM_CCR5_CCR5)
<>	157:ff67d9f36b67	2816	/**
<>	157:ff67d9f36b67	2817	* @brief Select on which reference signal the OC5REF is combined to.
<>	157:ff67d9f36b67	2818	* @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	2819	* whether or not a timer instance supports the combined 3-phase PWM mode.
<>	157:ff67d9f36b67	2820	* @if STM32F334x8
<>	157:ff67d9f36b67	2821	* @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
<>	157:ff67d9f36b67	2822	* CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
<>	157:ff67d9f36b67	2823	* CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
<>	157:ff67d9f36b67	2824	* @elseif STM32F303xC
<>	157:ff67d9f36b67	2825	* CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
<>	157:ff67d9f36b67	2826	* CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
<>	157:ff67d9f36b67	2827	* CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
<>	157:ff67d9f36b67	2828	* @elseif STM32F302x8
<>	157:ff67d9f36b67	2829	* CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
<>	157:ff67d9f36b67	2830	* CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
<>	157:ff67d9f36b67	2831	* CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
<>	157:ff67d9f36b67	2832	* @endif
<>	157:ff67d9f36b67	2833	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2834	* @param GroupCH5 This parameter can be one of the following values:
<>	157:ff67d9f36b67	2835	* @arg @ref LL_TIM_GROUPCH5_NONE
<>	157:ff67d9f36b67	2836	* @arg @ref LL_TIM_GROUPCH5_OC1REFC
<>	157:ff67d9f36b67	2837	* @arg @ref LL_TIM_GROUPCH5_OC2REFC
<>	157:ff67d9f36b67	2838	* @arg @ref LL_TIM_GROUPCH5_OC3REFC
<>	157:ff67d9f36b67	2839	* @note CH5 channel is not available for all F3 devices
<>	157:ff67d9f36b67	2840	* @retval None
<>	157:ff67d9f36b67	2841	*/
<>	157:ff67d9f36b67	2842	__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
<>	157:ff67d9f36b67	2843	{
<>	157:ff67d9f36b67	2844	MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, GroupCH5);
<>	157:ff67d9f36b67	2845	}
<>	157:ff67d9f36b67	2846
<>	157:ff67d9f36b67	2847	#endif /* TIM_CCR5_CCR5 */
<>	157:ff67d9f36b67	2848	/**
<>	157:ff67d9f36b67	2849	* @}
<>	157:ff67d9f36b67	2850	*/
<>	157:ff67d9f36b67	2851
<>	157:ff67d9f36b67	2852	/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
<>	157:ff67d9f36b67	2853	* @{
<>	157:ff67d9f36b67	2854	*/
<>	157:ff67d9f36b67	2855	/**
<>	157:ff67d9f36b67	2856	* @brief Configure input channel.
<>	157:ff67d9f36b67	2857	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
<>	157:ff67d9f36b67	2858	* CCMR1 IC1PSC LL_TIM_IC_Config\n
<>	157:ff67d9f36b67	2859	* CCMR1 IC1F LL_TIM_IC_Config\n
<>	157:ff67d9f36b67	2860	* CCMR1 CC2S LL_TIM_IC_Config\n
<>	157:ff67d9f36b67	2861	* CCMR1 IC2PSC LL_TIM_IC_Config\n
<>	157:ff67d9f36b67	2862	* CCMR1 IC2F LL_TIM_IC_Config\n
<>	157:ff67d9f36b67	2863	* CCMR2 CC3S LL_TIM_IC_Config\n
<>	157:ff67d9f36b67	2864	* CCMR2 IC3PSC LL_TIM_IC_Config\n
<>	157:ff67d9f36b67	2865	* CCMR2 IC3F LL_TIM_IC_Config\n
<>	157:ff67d9f36b67	2866	* CCMR2 CC4S LL_TIM_IC_Config\n
<>	157:ff67d9f36b67	2867	* CCMR2 IC4PSC LL_TIM_IC_Config\n
<>	157:ff67d9f36b67	2868	* CCMR2 IC4F LL_TIM_IC_Config\n
<>	157:ff67d9f36b67	2869	* CCER CC1P LL_TIM_IC_Config\n
<>	157:ff67d9f36b67	2870	* CCER CC1NP LL_TIM_IC_Config\n
<>	157:ff67d9f36b67	2871	* CCER CC2P LL_TIM_IC_Config\n
<>	157:ff67d9f36b67	2872	* CCER CC2NP LL_TIM_IC_Config\n
<>	157:ff67d9f36b67	2873	* CCER CC3P LL_TIM_IC_Config\n
<>	157:ff67d9f36b67	2874	* CCER CC3NP LL_TIM_IC_Config\n
<>	157:ff67d9f36b67	2875	* CCER CC4P LL_TIM_IC_Config\n
<>	157:ff67d9f36b67	2876	* CCER CC4NP LL_TIM_IC_Config
<>	157:ff67d9f36b67	2877	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2878	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	2879	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	2880	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	2881	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	2882	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	2883	* @param Configuration This parameter must be a combination of all the following values:
<>	157:ff67d9f36b67	2884	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
<>	157:ff67d9f36b67	2885	* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
<>	157:ff67d9f36b67	2886	* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
<>	157:ff67d9f36b67	2887	* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
<>	157:ff67d9f36b67	2888	* @retval None
<>	157:ff67d9f36b67	2889	*/
<>	157:ff67d9f36b67	2890	__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
<>	157:ff67d9f36b67	2891	{
<>	157:ff67d9f36b67	2892	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	157:ff67d9f36b67	2893	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	157:ff67d9f36b67	2894	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
<>	157:ff67d9f36b67	2895	((Configuration >> 16U) & (TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
<>	157:ff67d9f36b67	2896	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
<>	157:ff67d9f36b67	2897	(Configuration & (TIM_CCER_CC1NP \| TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
<>	157:ff67d9f36b67	2898	}
<>	157:ff67d9f36b67	2899
<>	157:ff67d9f36b67	2900	/**
<>	157:ff67d9f36b67	2901	* @brief Set the active input.
<>	157:ff67d9f36b67	2902	* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
<>	157:ff67d9f36b67	2903	* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
<>	157:ff67d9f36b67	2904	* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
<>	157:ff67d9f36b67	2905	* CCMR2 CC4S LL_TIM_IC_SetActiveInput
<>	157:ff67d9f36b67	2906	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2907	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	2908	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	2909	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	2910	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	2911	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	2912	* @param ICActiveInput This parameter can be one of the following values:
<>	157:ff67d9f36b67	2913	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
<>	157:ff67d9f36b67	2914	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
<>	157:ff67d9f36b67	2915	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
<>	157:ff67d9f36b67	2916	* @retval None
<>	157:ff67d9f36b67	2917	*/
<>	157:ff67d9f36b67	2918	__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
<>	157:ff67d9f36b67	2919	{
<>	157:ff67d9f36b67	2920	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	157:ff67d9f36b67	2921	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	157:ff67d9f36b67	2922	MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
<>	157:ff67d9f36b67	2923	}
<>	157:ff67d9f36b67	2924
<>	157:ff67d9f36b67	2925	/**
<>	157:ff67d9f36b67	2926	* @brief Get the current active input.
<>	157:ff67d9f36b67	2927	* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
<>	157:ff67d9f36b67	2928	* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
<>	157:ff67d9f36b67	2929	* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
<>	157:ff67d9f36b67	2930	* CCMR2 CC4S LL_TIM_IC_GetActiveInput
<>	157:ff67d9f36b67	2931	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2932	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	2933	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	2934	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	2935	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	2936	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	2937	* @retval Returned value can be one of the following values:
<>	157:ff67d9f36b67	2938	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
<>	157:ff67d9f36b67	2939	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
<>	157:ff67d9f36b67	2940	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
<>	157:ff67d9f36b67	2941	*/
<>	157:ff67d9f36b67	2942	__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
<>	157:ff67d9f36b67	2943	{
<>	157:ff67d9f36b67	2944	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	157:ff67d9f36b67	2945	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	157:ff67d9f36b67	2946	return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
<>	157:ff67d9f36b67	2947	}
<>	157:ff67d9f36b67	2948
<>	157:ff67d9f36b67	2949	/**
<>	157:ff67d9f36b67	2950	* @brief Set the prescaler of input channel.
<>	157:ff67d9f36b67	2951	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
<>	157:ff67d9f36b67	2952	* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
<>	157:ff67d9f36b67	2953	* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
<>	157:ff67d9f36b67	2954	* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
<>	157:ff67d9f36b67	2955	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2956	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	2957	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	2958	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	2959	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	2960	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	2961	* @param ICPrescaler This parameter can be one of the following values:
<>	157:ff67d9f36b67	2962	* @arg @ref LL_TIM_ICPSC_DIV1
<>	157:ff67d9f36b67	2963	* @arg @ref LL_TIM_ICPSC_DIV2
<>	157:ff67d9f36b67	2964	* @arg @ref LL_TIM_ICPSC_DIV4
<>	157:ff67d9f36b67	2965	* @arg @ref LL_TIM_ICPSC_DIV8
<>	157:ff67d9f36b67	2966	* @retval None
<>	157:ff67d9f36b67	2967	*/
<>	157:ff67d9f36b67	2968	__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
<>	157:ff67d9f36b67	2969	{
<>	157:ff67d9f36b67	2970	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	157:ff67d9f36b67	2971	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	157:ff67d9f36b67	2972	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
<>	157:ff67d9f36b67	2973	}
<>	157:ff67d9f36b67	2974
<>	157:ff67d9f36b67	2975	/**
<>	157:ff67d9f36b67	2976	* @brief Get the current prescaler value acting on an input channel.
<>	157:ff67d9f36b67	2977	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
<>	157:ff67d9f36b67	2978	* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
<>	157:ff67d9f36b67	2979	* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
<>	157:ff67d9f36b67	2980	* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
<>	157:ff67d9f36b67	2981	* @param TIMx Timer instance
<>	157:ff67d9f36b67	2982	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	2983	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	2984	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	2985	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	2986	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	2987	* @retval Returned value can be one of the following values:
<>	157:ff67d9f36b67	2988	* @arg @ref LL_TIM_ICPSC_DIV1
<>	157:ff67d9f36b67	2989	* @arg @ref LL_TIM_ICPSC_DIV2
<>	157:ff67d9f36b67	2990	* @arg @ref LL_TIM_ICPSC_DIV4
<>	157:ff67d9f36b67	2991	* @arg @ref LL_TIM_ICPSC_DIV8
<>	157:ff67d9f36b67	2992	*/
<>	157:ff67d9f36b67	2993	__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
<>	157:ff67d9f36b67	2994	{
<>	157:ff67d9f36b67	2995	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	157:ff67d9f36b67	2996	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	157:ff67d9f36b67	2997	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
<>	157:ff67d9f36b67	2998	}
<>	157:ff67d9f36b67	2999
<>	157:ff67d9f36b67	3000	/**
<>	157:ff67d9f36b67	3001	* @brief Set the input filter duration.
<>	157:ff67d9f36b67	3002	* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
<>	157:ff67d9f36b67	3003	* CCMR1 IC2F LL_TIM_IC_SetFilter\n
<>	157:ff67d9f36b67	3004	* CCMR2 IC3F LL_TIM_IC_SetFilter\n
<>	157:ff67d9f36b67	3005	* CCMR2 IC4F LL_TIM_IC_SetFilter
<>	157:ff67d9f36b67	3006	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3007	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	3008	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	3009	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	3010	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	3011	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	3012	* @param ICFilter This parameter can be one of the following values:
<>	157:ff67d9f36b67	3013	* @arg @ref LL_TIM_IC_FILTER_FDIV1
<>	157:ff67d9f36b67	3014	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
<>	157:ff67d9f36b67	3015	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
<>	157:ff67d9f36b67	3016	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
<>	157:ff67d9f36b67	3017	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
<>	157:ff67d9f36b67	3018	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
<>	157:ff67d9f36b67	3019	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
<>	157:ff67d9f36b67	3020	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
<>	157:ff67d9f36b67	3021	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
<>	157:ff67d9f36b67	3022	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
<>	157:ff67d9f36b67	3023	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
<>	157:ff67d9f36b67	3024	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
<>	157:ff67d9f36b67	3025	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
<>	157:ff67d9f36b67	3026	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
<>	157:ff67d9f36b67	3027	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
<>	157:ff67d9f36b67	3028	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
<>	157:ff67d9f36b67	3029	* @retval None
<>	157:ff67d9f36b67	3030	*/
<>	157:ff67d9f36b67	3031	__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
<>	157:ff67d9f36b67	3032	{
<>	157:ff67d9f36b67	3033	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	157:ff67d9f36b67	3034	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	157:ff67d9f36b67	3035	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
<>	157:ff67d9f36b67	3036	}
<>	157:ff67d9f36b67	3037
<>	157:ff67d9f36b67	3038	/**
<>	157:ff67d9f36b67	3039	* @brief Get the input filter duration.
<>	157:ff67d9f36b67	3040	* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
<>	157:ff67d9f36b67	3041	* CCMR1 IC2F LL_TIM_IC_GetFilter\n
<>	157:ff67d9f36b67	3042	* CCMR2 IC3F LL_TIM_IC_GetFilter\n
<>	157:ff67d9f36b67	3043	* CCMR2 IC4F LL_TIM_IC_GetFilter
<>	157:ff67d9f36b67	3044	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3045	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	3046	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	3047	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	3048	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	3049	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	3050	* @retval Returned value can be one of the following values:
<>	157:ff67d9f36b67	3051	* @arg @ref LL_TIM_IC_FILTER_FDIV1
<>	157:ff67d9f36b67	3052	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
<>	157:ff67d9f36b67	3053	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
<>	157:ff67d9f36b67	3054	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
<>	157:ff67d9f36b67	3055	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
<>	157:ff67d9f36b67	3056	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
<>	157:ff67d9f36b67	3057	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
<>	157:ff67d9f36b67	3058	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
<>	157:ff67d9f36b67	3059	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
<>	157:ff67d9f36b67	3060	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
<>	157:ff67d9f36b67	3061	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
<>	157:ff67d9f36b67	3062	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
<>	157:ff67d9f36b67	3063	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
<>	157:ff67d9f36b67	3064	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
<>	157:ff67d9f36b67	3065	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
<>	157:ff67d9f36b67	3066	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
<>	157:ff67d9f36b67	3067	*/
<>	157:ff67d9f36b67	3068	__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
<>	157:ff67d9f36b67	3069	{
<>	157:ff67d9f36b67	3070	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	157:ff67d9f36b67	3071	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	157:ff67d9f36b67	3072	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
<>	157:ff67d9f36b67	3073	}
<>	157:ff67d9f36b67	3074
<>	157:ff67d9f36b67	3075	/**
<>	157:ff67d9f36b67	3076	* @brief Set the input channel polarity.
<>	157:ff67d9f36b67	3077	* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
<>	157:ff67d9f36b67	3078	* CCER CC1NP LL_TIM_IC_SetPolarity\n
<>	157:ff67d9f36b67	3079	* CCER CC2P LL_TIM_IC_SetPolarity\n
<>	157:ff67d9f36b67	3080	* CCER CC2NP LL_TIM_IC_SetPolarity\n
<>	157:ff67d9f36b67	3081	* CCER CC3P LL_TIM_IC_SetPolarity\n
<>	157:ff67d9f36b67	3082	* CCER CC3NP LL_TIM_IC_SetPolarity\n
<>	157:ff67d9f36b67	3083	* CCER CC4P LL_TIM_IC_SetPolarity\n
<>	157:ff67d9f36b67	3084	* CCER CC4NP LL_TIM_IC_SetPolarity
<>	157:ff67d9f36b67	3085	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3086	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	3087	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	3088	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	3089	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	3090	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	3091	* @param ICPolarity This parameter can be one of the following values:
<>	157:ff67d9f36b67	3092	* @arg @ref LL_TIM_IC_POLARITY_RISING
<>	157:ff67d9f36b67	3093	* @arg @ref LL_TIM_IC_POLARITY_FALLING
<>	157:ff67d9f36b67	3094	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
<>	157:ff67d9f36b67	3095	* @retval None
<>	157:ff67d9f36b67	3096	*/
<>	157:ff67d9f36b67	3097	__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
<>	157:ff67d9f36b67	3098	{
<>	157:ff67d9f36b67	3099	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	157:ff67d9f36b67	3100	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
<>	157:ff67d9f36b67	3101	ICPolarity << SHIFT_TAB_CCxP[iChannel]);
<>	157:ff67d9f36b67	3102	}
<>	157:ff67d9f36b67	3103
<>	157:ff67d9f36b67	3104	/**
<>	157:ff67d9f36b67	3105	* @brief Get the current input channel polarity.
<>	157:ff67d9f36b67	3106	* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
<>	157:ff67d9f36b67	3107	* CCER CC1NP LL_TIM_IC_GetPolarity\n
<>	157:ff67d9f36b67	3108	* CCER CC2P LL_TIM_IC_GetPolarity\n
<>	157:ff67d9f36b67	3109	* CCER CC2NP LL_TIM_IC_GetPolarity\n
<>	157:ff67d9f36b67	3110	* CCER CC3P LL_TIM_IC_GetPolarity\n
<>	157:ff67d9f36b67	3111	* CCER CC3NP LL_TIM_IC_GetPolarity\n
<>	157:ff67d9f36b67	3112	* CCER CC4P LL_TIM_IC_GetPolarity\n
<>	157:ff67d9f36b67	3113	* CCER CC4NP LL_TIM_IC_GetPolarity
<>	157:ff67d9f36b67	3114	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3115	* @param Channel This parameter can be one of the following values:
<>	157:ff67d9f36b67	3116	* @arg @ref LL_TIM_CHANNEL_CH1
<>	157:ff67d9f36b67	3117	* @arg @ref LL_TIM_CHANNEL_CH2
<>	157:ff67d9f36b67	3118	* @arg @ref LL_TIM_CHANNEL_CH3
<>	157:ff67d9f36b67	3119	* @arg @ref LL_TIM_CHANNEL_CH4
<>	157:ff67d9f36b67	3120	* @retval Returned value can be one of the following values:
<>	157:ff67d9f36b67	3121	* @arg @ref LL_TIM_IC_POLARITY_RISING
<>	157:ff67d9f36b67	3122	* @arg @ref LL_TIM_IC_POLARITY_FALLING
<>	157:ff67d9f36b67	3123	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
<>	157:ff67d9f36b67	3124	*/
<>	157:ff67d9f36b67	3125	__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
<>	157:ff67d9f36b67	3126	{
<>	157:ff67d9f36b67	3127	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	157:ff67d9f36b67	3128	return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
<>	157:ff67d9f36b67	3129	SHIFT_TAB_CCxP[iChannel]);
<>	157:ff67d9f36b67	3130	}
<>	157:ff67d9f36b67	3131
<>	157:ff67d9f36b67	3132	/**
<>	157:ff67d9f36b67	3133	* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
<>	157:ff67d9f36b67	3134	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3135	* a timer instance provides an XOR input.
<>	157:ff67d9f36b67	3136	* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
<>	157:ff67d9f36b67	3137	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3138	* @retval None
<>	157:ff67d9f36b67	3139	*/
<>	157:ff67d9f36b67	3140	__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3141	{
<>	157:ff67d9f36b67	3142	SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
<>	157:ff67d9f36b67	3143	}
<>	157:ff67d9f36b67	3144
<>	157:ff67d9f36b67	3145	/**
<>	157:ff67d9f36b67	3146	* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
<>	157:ff67d9f36b67	3147	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3148	* a timer instance provides an XOR input.
<>	157:ff67d9f36b67	3149	* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
<>	157:ff67d9f36b67	3150	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3151	* @retval None
<>	157:ff67d9f36b67	3152	*/
<>	157:ff67d9f36b67	3153	__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3154	{
<>	157:ff67d9f36b67	3155	CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
<>	157:ff67d9f36b67	3156	}
<>	157:ff67d9f36b67	3157
<>	157:ff67d9f36b67	3158	/**
<>	157:ff67d9f36b67	3159	* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
<>	157:ff67d9f36b67	3160	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3161	* a timer instance provides an XOR input.
<>	157:ff67d9f36b67	3162	* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
<>	157:ff67d9f36b67	3163	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3164	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	3165	*/
<>	157:ff67d9f36b67	3166	__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3167	{
<>	157:ff67d9f36b67	3168	return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
<>	157:ff67d9f36b67	3169	}
<>	157:ff67d9f36b67	3170
<>	157:ff67d9f36b67	3171	/**
<>	157:ff67d9f36b67	3172	* @brief Get captured value for input channel 1.
<>	157:ff67d9f36b67	3173	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<>	157:ff67d9f36b67	3174	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	3175	* whether or not a timer instance supports a 32 bits counter.
<>	157:ff67d9f36b67	3176	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3177	* input channel 1 is supported by a timer instance.
<>	157:ff67d9f36b67	3178	* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
<>	157:ff67d9f36b67	3179	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3180	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<>	157:ff67d9f36b67	3181	*/
<>	157:ff67d9f36b67	3182	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3183	{
<>	157:ff67d9f36b67	3184	return (uint32_t)(READ_REG(TIMx->CCR1));
<>	157:ff67d9f36b67	3185	}
<>	157:ff67d9f36b67	3186
<>	157:ff67d9f36b67	3187	/**
<>	157:ff67d9f36b67	3188	* @brief Get captured value for input channel 2.
<>	157:ff67d9f36b67	3189	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<>	157:ff67d9f36b67	3190	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	3191	* whether or not a timer instance supports a 32 bits counter.
<>	157:ff67d9f36b67	3192	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3193	* input channel 2 is supported by a timer instance.
<>	157:ff67d9f36b67	3194	* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
<>	157:ff67d9f36b67	3195	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3196	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<>	157:ff67d9f36b67	3197	*/
<>	157:ff67d9f36b67	3198	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3199	{
<>	157:ff67d9f36b67	3200	return (uint32_t)(READ_REG(TIMx->CCR2));
<>	157:ff67d9f36b67	3201	}
<>	157:ff67d9f36b67	3202
<>	157:ff67d9f36b67	3203	/**
<>	157:ff67d9f36b67	3204	* @brief Get captured value for input channel 3.
<>	157:ff67d9f36b67	3205	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<>	157:ff67d9f36b67	3206	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	3207	* whether or not a timer instance supports a 32 bits counter.
<>	157:ff67d9f36b67	3208	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3209	* input channel 3 is supported by a timer instance.
<>	157:ff67d9f36b67	3210	* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
<>	157:ff67d9f36b67	3211	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3212	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<>	157:ff67d9f36b67	3213	*/
<>	157:ff67d9f36b67	3214	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3215	{
<>	157:ff67d9f36b67	3216	return (uint32_t)(READ_REG(TIMx->CCR3));
<>	157:ff67d9f36b67	3217	}
<>	157:ff67d9f36b67	3218
<>	157:ff67d9f36b67	3219	/**
<>	157:ff67d9f36b67	3220	* @brief Get captured value for input channel 4.
<>	157:ff67d9f36b67	3221	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<>	157:ff67d9f36b67	3222	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	3223	* whether or not a timer instance supports a 32 bits counter.
<>	157:ff67d9f36b67	3224	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3225	* input channel 4 is supported by a timer instance.
<>	157:ff67d9f36b67	3226	* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
<>	157:ff67d9f36b67	3227	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3228	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<>	157:ff67d9f36b67	3229	*/
<>	157:ff67d9f36b67	3230	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3231	{
<>	157:ff67d9f36b67	3232	return (uint32_t)(READ_REG(TIMx->CCR4));
<>	157:ff67d9f36b67	3233	}
<>	157:ff67d9f36b67	3234
<>	157:ff67d9f36b67	3235	/**
<>	157:ff67d9f36b67	3236	* @}
<>	157:ff67d9f36b67	3237	*/
<>	157:ff67d9f36b67	3238
<>	157:ff67d9f36b67	3239	/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
<>	157:ff67d9f36b67	3240	* @{
<>	157:ff67d9f36b67	3241	*/
<>	157:ff67d9f36b67	3242	/**
<>	157:ff67d9f36b67	3243	* @brief Enable external clock mode 2.
<>	157:ff67d9f36b67	3244	* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
<>	157:ff67d9f36b67	3245	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	3246	* whether or not a timer instance supports external clock mode2.
<>	157:ff67d9f36b67	3247	* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
<>	157:ff67d9f36b67	3248	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3249	* @retval None
<>	157:ff67d9f36b67	3250	*/
<>	157:ff67d9f36b67	3251	__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3252	{
<>	157:ff67d9f36b67	3253	SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
<>	157:ff67d9f36b67	3254	}
<>	157:ff67d9f36b67	3255
<>	157:ff67d9f36b67	3256	/**
<>	157:ff67d9f36b67	3257	* @brief Disable external clock mode 2.
<>	157:ff67d9f36b67	3258	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	3259	* whether or not a timer instance supports external clock mode2.
<>	157:ff67d9f36b67	3260	* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
<>	157:ff67d9f36b67	3261	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3262	* @retval None
<>	157:ff67d9f36b67	3263	*/
<>	157:ff67d9f36b67	3264	__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3265	{
<>	157:ff67d9f36b67	3266	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
<>	157:ff67d9f36b67	3267	}
<>	157:ff67d9f36b67	3268
<>	157:ff67d9f36b67	3269	/**
<>	157:ff67d9f36b67	3270	* @brief Indicate whether external clock mode 2 is enabled.
<>	157:ff67d9f36b67	3271	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	3272	* whether or not a timer instance supports external clock mode2.
<>	157:ff67d9f36b67	3273	* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
<>	157:ff67d9f36b67	3274	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3275	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	3276	*/
<>	157:ff67d9f36b67	3277	__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3278	{
<>	157:ff67d9f36b67	3279	return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
<>	157:ff67d9f36b67	3280	}
<>	157:ff67d9f36b67	3281
<>	157:ff67d9f36b67	3282	/**
<>	157:ff67d9f36b67	3283	* @brief Set the clock source of the counter clock.
<>	157:ff67d9f36b67	3284	* @note when selected clock source is external clock mode 1, the timer input
<>	157:ff67d9f36b67	3285	* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
<>	157:ff67d9f36b67	3286	* function. This timer input must be configured by calling
<>	157:ff67d9f36b67	3287	* the @ref LL_TIM_IC_Config() function.
<>	157:ff67d9f36b67	3288	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	3289	* whether or not a timer instance supports external clock mode1.
<>	157:ff67d9f36b67	3290	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	3291	* whether or not a timer instance supports external clock mode2.
<>	157:ff67d9f36b67	3292	* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
<>	157:ff67d9f36b67	3293	* SMCR ECE LL_TIM_SetClockSource
<>	157:ff67d9f36b67	3294	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3295	* @param ClockSource This parameter can be one of the following values:
<>	157:ff67d9f36b67	3296	* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
<>	157:ff67d9f36b67	3297	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
<>	157:ff67d9f36b67	3298	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
<>	157:ff67d9f36b67	3299	* @retval None
<>	157:ff67d9f36b67	3300	*/
<>	157:ff67d9f36b67	3301	__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
<>	157:ff67d9f36b67	3302	{
<>	157:ff67d9f36b67	3303	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS \| TIM_SMCR_ECE, ClockSource);
<>	157:ff67d9f36b67	3304	}
<>	157:ff67d9f36b67	3305
<>	157:ff67d9f36b67	3306	/**
<>	157:ff67d9f36b67	3307	* @brief Set the encoder interface mode.
<>	157:ff67d9f36b67	3308	* @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	3309	* whether or not a timer instance supports the encoder mode.
<>	157:ff67d9f36b67	3310	* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
<>	157:ff67d9f36b67	3311	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3312	* @param EncoderMode This parameter can be one of the following values:
<>	157:ff67d9f36b67	3313	* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
<>	157:ff67d9f36b67	3314	* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
<>	157:ff67d9f36b67	3315	* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
<>	157:ff67d9f36b67	3316	* @retval None
<>	157:ff67d9f36b67	3317	*/
<>	157:ff67d9f36b67	3318	__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
<>	157:ff67d9f36b67	3319	{
<>	157:ff67d9f36b67	3320	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
<>	157:ff67d9f36b67	3321	}
<>	157:ff67d9f36b67	3322
<>	157:ff67d9f36b67	3323	/**
<>	157:ff67d9f36b67	3324	* @}
<>	157:ff67d9f36b67	3325	*/
<>	157:ff67d9f36b67	3326
<>	157:ff67d9f36b67	3327	/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
<>	157:ff67d9f36b67	3328	* @{
<>	157:ff67d9f36b67	3329	*/
<>	157:ff67d9f36b67	3330	/**
<>	157:ff67d9f36b67	3331	* @brief Set the trigger output (TRGO) used for timer synchronization .
<>	157:ff67d9f36b67	3332	* @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	3333	* whether or not a timer instance can operate as a master timer.
<>	157:ff67d9f36b67	3334	* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
<>	157:ff67d9f36b67	3335	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3336	* @param TimerSynchronization This parameter can be one of the following values:
<>	157:ff67d9f36b67	3337	* @arg @ref LL_TIM_TRGO_RESET
<>	157:ff67d9f36b67	3338	* @arg @ref LL_TIM_TRGO_ENABLE
<>	157:ff67d9f36b67	3339	* @arg @ref LL_TIM_TRGO_UPDATE
<>	157:ff67d9f36b67	3340	* @arg @ref LL_TIM_TRGO_CC1IF
<>	157:ff67d9f36b67	3341	* @arg @ref LL_TIM_TRGO_OC1REF
<>	157:ff67d9f36b67	3342	* @arg @ref LL_TIM_TRGO_OC2REF
<>	157:ff67d9f36b67	3343	* @arg @ref LL_TIM_TRGO_OC3REF
<>	157:ff67d9f36b67	3344	* @arg @ref LL_TIM_TRGO_OC4REF
<>	157:ff67d9f36b67	3345	* @retval None
<>	157:ff67d9f36b67	3346	*/
<>	157:ff67d9f36b67	3347	__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
<>	157:ff67d9f36b67	3348	{
<>	157:ff67d9f36b67	3349	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
<>	157:ff67d9f36b67	3350	}
<>	157:ff67d9f36b67	3351
<>	157:ff67d9f36b67	3352	#if defined(TIM_CR2_MMS2)
<>	157:ff67d9f36b67	3353	/**
<>	157:ff67d9f36b67	3354	* @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
<>	157:ff67d9f36b67	3355	* @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
<>	157:ff67d9f36b67	3356	* whether or not a timer instance can be used for ADC synchronization.
<>	157:ff67d9f36b67	3357	* @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
<>	157:ff67d9f36b67	3358	* @param TIMx Timer Instance
<>	157:ff67d9f36b67	3359	* @param ADCSynchronization This parameter can be one of the following values:
<>	157:ff67d9f36b67	3360	* @arg @ref LL_TIM_TRGO2_RESET
<>	157:ff67d9f36b67	3361	* @arg @ref LL_TIM_TRGO2_ENABLE
<>	157:ff67d9f36b67	3362	* @arg @ref LL_TIM_TRGO2_UPDATE
<>	157:ff67d9f36b67	3363	* @arg @ref LL_TIM_TRGO2_CC1F
<>	157:ff67d9f36b67	3364	* @arg @ref LL_TIM_TRGO2_OC1
<>	157:ff67d9f36b67	3365	* @arg @ref LL_TIM_TRGO2_OC2
<>	157:ff67d9f36b67	3366	* @arg @ref LL_TIM_TRGO2_OC3
<>	157:ff67d9f36b67	3367	* @arg @ref LL_TIM_TRGO2_OC4
<>	157:ff67d9f36b67	3368	* @arg @ref LL_TIM_TRGO2_OC5
<>	157:ff67d9f36b67	3369	* @arg @ref LL_TIM_TRGO2_OC6
<>	157:ff67d9f36b67	3370	* @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
<>	157:ff67d9f36b67	3371	* @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
<>	157:ff67d9f36b67	3372	* @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
<>	157:ff67d9f36b67	3373	* @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
<>	157:ff67d9f36b67	3374	* @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
<>	157:ff67d9f36b67	3375	* @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
<>	157:ff67d9f36b67	3376	* @note OC5 and OC6 are not available for all F3 devices
<>	157:ff67d9f36b67	3377	* @retval None
<>	157:ff67d9f36b67	3378	*/
<>	157:ff67d9f36b67	3379	__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
<>	157:ff67d9f36b67	3380	{
<>	157:ff67d9f36b67	3381	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
<>	157:ff67d9f36b67	3382	}
<>	157:ff67d9f36b67	3383
<>	157:ff67d9f36b67	3384	#endif /* TIM_CR2_MMS2 */
<>	157:ff67d9f36b67	3385	/**
<>	157:ff67d9f36b67	3386	* @brief Set the synchronization mode of a slave timer.
<>	157:ff67d9f36b67	3387	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3388	* a timer instance can operate as a slave timer.
<>	157:ff67d9f36b67	3389	* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
<>	157:ff67d9f36b67	3390	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3391	* @param SlaveMode This parameter can be one of the following values:
<>	157:ff67d9f36b67	3392	* @arg @ref LL_TIM_SLAVEMODE_DISABLED
<>	157:ff67d9f36b67	3393	* @arg @ref LL_TIM_SLAVEMODE_RESET
<>	157:ff67d9f36b67	3394	* @arg @ref LL_TIM_SLAVEMODE_GATED
<>	157:ff67d9f36b67	3395	* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
<>	157:ff67d9f36b67	3396	* @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
<>	157:ff67d9f36b67	3397	* @retval None
<>	157:ff67d9f36b67	3398	*/
<>	157:ff67d9f36b67	3399	__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
<>	157:ff67d9f36b67	3400	{
<>	157:ff67d9f36b67	3401	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
<>	157:ff67d9f36b67	3402	}
<>	157:ff67d9f36b67	3403
<>	157:ff67d9f36b67	3404	/**
<>	157:ff67d9f36b67	3405	* @brief Set the selects the trigger input to be used to synchronize the counter.
<>	157:ff67d9f36b67	3406	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3407	* a timer instance can operate as a slave timer.
<>	157:ff67d9f36b67	3408	* @rmtoll SMCR TS LL_TIM_SetTriggerInput
<>	157:ff67d9f36b67	3409	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3410	* @param TriggerInput This parameter can be one of the following values:
<>	157:ff67d9f36b67	3411	* @arg @ref LL_TIM_TS_ITR0
<>	157:ff67d9f36b67	3412	* @arg @ref LL_TIM_TS_ITR1
<>	157:ff67d9f36b67	3413	* @arg @ref LL_TIM_TS_ITR2
<>	157:ff67d9f36b67	3414	* @arg @ref LL_TIM_TS_ITR3
<>	157:ff67d9f36b67	3415	* @arg @ref LL_TIM_TS_TI1F_ED
<>	157:ff67d9f36b67	3416	* @arg @ref LL_TIM_TS_TI1FP1
<>	157:ff67d9f36b67	3417	* @arg @ref LL_TIM_TS_TI2FP2
<>	157:ff67d9f36b67	3418	* @arg @ref LL_TIM_TS_ETRF
<>	157:ff67d9f36b67	3419	* @retval None
<>	157:ff67d9f36b67	3420	*/
<>	157:ff67d9f36b67	3421	__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
<>	157:ff67d9f36b67	3422	{
<>	157:ff67d9f36b67	3423	MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
<>	157:ff67d9f36b67	3424	}
<>	157:ff67d9f36b67	3425
<>	157:ff67d9f36b67	3426	/**
<>	157:ff67d9f36b67	3427	* @brief Enable the Master/Slave mode.
<>	157:ff67d9f36b67	3428	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3429	* a timer instance can operate as a slave timer.
<>	157:ff67d9f36b67	3430	* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
<>	157:ff67d9f36b67	3431	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3432	* @retval None
<>	157:ff67d9f36b67	3433	*/
<>	157:ff67d9f36b67	3434	__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3435	{
<>	157:ff67d9f36b67	3436	SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
<>	157:ff67d9f36b67	3437	}
<>	157:ff67d9f36b67	3438
<>	157:ff67d9f36b67	3439	/**
<>	157:ff67d9f36b67	3440	* @brief Disable the Master/Slave mode.
<>	157:ff67d9f36b67	3441	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3442	* a timer instance can operate as a slave timer.
<>	157:ff67d9f36b67	3443	* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
<>	157:ff67d9f36b67	3444	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3445	* @retval None
<>	157:ff67d9f36b67	3446	*/
<>	157:ff67d9f36b67	3447	__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3448	{
<>	157:ff67d9f36b67	3449	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
<>	157:ff67d9f36b67	3450	}
<>	157:ff67d9f36b67	3451
<>	157:ff67d9f36b67	3452	/**
<>	157:ff67d9f36b67	3453	* @brief Indicates whether the Master/Slave mode is enabled.
<>	157:ff67d9f36b67	3454	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3455	* a timer instance can operate as a slave timer.
<>	157:ff67d9f36b67	3456	* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
<>	157:ff67d9f36b67	3457	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3458	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	3459	*/
<>	157:ff67d9f36b67	3460	__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3461	{
<>	157:ff67d9f36b67	3462	return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
<>	157:ff67d9f36b67	3463	}
<>	157:ff67d9f36b67	3464
<>	157:ff67d9f36b67	3465	/**
<>	157:ff67d9f36b67	3466	* @brief Configure the external trigger (ETR) input.
<>	157:ff67d9f36b67	3467	* @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3468	* a timer instance provides an external trigger input.
<>	157:ff67d9f36b67	3469	* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
<>	157:ff67d9f36b67	3470	* SMCR ETPS LL_TIM_ConfigETR\n
<>	157:ff67d9f36b67	3471	* SMCR ETF LL_TIM_ConfigETR
<>	157:ff67d9f36b67	3472	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3473	* @param ETRPolarity This parameter can be one of the following values:
<>	157:ff67d9f36b67	3474	* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
<>	157:ff67d9f36b67	3475	* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
<>	157:ff67d9f36b67	3476	* @param ETRPrescaler This parameter can be one of the following values:
<>	157:ff67d9f36b67	3477	* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
<>	157:ff67d9f36b67	3478	* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
<>	157:ff67d9f36b67	3479	* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
<>	157:ff67d9f36b67	3480	* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
<>	157:ff67d9f36b67	3481	* @param ETRFilter This parameter can be one of the following values:
<>	157:ff67d9f36b67	3482	* @arg @ref LL_TIM_ETR_FILTER_FDIV1
<>	157:ff67d9f36b67	3483	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
<>	157:ff67d9f36b67	3484	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
<>	157:ff67d9f36b67	3485	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
<>	157:ff67d9f36b67	3486	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
<>	157:ff67d9f36b67	3487	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
<>	157:ff67d9f36b67	3488	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
<>	157:ff67d9f36b67	3489	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
<>	157:ff67d9f36b67	3490	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
<>	157:ff67d9f36b67	3491	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
<>	157:ff67d9f36b67	3492	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
<>	157:ff67d9f36b67	3493	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
<>	157:ff67d9f36b67	3494	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
<>	157:ff67d9f36b67	3495	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
<>	157:ff67d9f36b67	3496	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
<>	157:ff67d9f36b67	3497	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
<>	157:ff67d9f36b67	3498	* @retval None
<>	157:ff67d9f36b67	3499	*/
<>	157:ff67d9f36b67	3500	__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
<>	157:ff67d9f36b67	3501	uint32_t ETRFilter)
<>	157:ff67d9f36b67	3502	{
<>	157:ff67d9f36b67	3503	MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP \| TIM_SMCR_ETPS \| TIM_SMCR_ETF, ETRPolarity \| ETRPrescaler \| ETRFilter);
<>	157:ff67d9f36b67	3504	}
<>	157:ff67d9f36b67	3505
<>	157:ff67d9f36b67	3506	/**
<>	157:ff67d9f36b67	3507	* @}
<>	157:ff67d9f36b67	3508	*/
<>	157:ff67d9f36b67	3509
<>	157:ff67d9f36b67	3510	/** @defgroup TIM_LL_EF_Break_Function Break function configuration
<>	157:ff67d9f36b67	3511	* @{
<>	157:ff67d9f36b67	3512	*/
<>	157:ff67d9f36b67	3513	/**
<>	157:ff67d9f36b67	3514	* @brief Enable the break function.
<>	157:ff67d9f36b67	3515	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3516	* a timer instance provides a break input.
<>	157:ff67d9f36b67	3517	* @rmtoll BDTR BKE LL_TIM_EnableBRK
<>	157:ff67d9f36b67	3518	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3519	* @retval None
<>	157:ff67d9f36b67	3520	*/
<>	157:ff67d9f36b67	3521	__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3522	{
<>	157:ff67d9f36b67	3523	SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
<>	157:ff67d9f36b67	3524	}
<>	157:ff67d9f36b67	3525
<>	157:ff67d9f36b67	3526	/**
<>	157:ff67d9f36b67	3527	* @brief Disable the break function.
<>	157:ff67d9f36b67	3528	* @rmtoll BDTR BKE LL_TIM_DisableBRK
<>	157:ff67d9f36b67	3529	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3530	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3531	* a timer instance provides a break input.
<>	157:ff67d9f36b67	3532	* @retval None
<>	157:ff67d9f36b67	3533	*/
<>	157:ff67d9f36b67	3534	__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3535	{
<>	157:ff67d9f36b67	3536	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
<>	157:ff67d9f36b67	3537	}
<>	157:ff67d9f36b67	3538
<>	157:ff67d9f36b67	3539	#if defined(TIM_BDTR_BKF)
<>	157:ff67d9f36b67	3540	/**
<>	157:ff67d9f36b67	3541	* @brief Configure the break input.
<>	157:ff67d9f36b67	3542	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3543	* a timer instance provides a break input.
<>	157:ff67d9f36b67	3544	* @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
<>	157:ff67d9f36b67	3545	* BDTR BKF LL_TIM_ConfigBRK
<>	157:ff67d9f36b67	3546	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3547	* @param BreakPolarity This parameter can be one of the following values:
<>	157:ff67d9f36b67	3548	* @arg @ref LL_TIM_BREAK_POLARITY_LOW
<>	157:ff67d9f36b67	3549	* @arg @ref LL_TIM_BREAK_POLARITY_HIGH
<>	157:ff67d9f36b67	3550	* @param BreakFilter This parameter can be one of the following values:
<>	157:ff67d9f36b67	3551	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1
<>	157:ff67d9f36b67	3552	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
<>	157:ff67d9f36b67	3553	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
<>	157:ff67d9f36b67	3554	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
<>	157:ff67d9f36b67	3555	* @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
<>	157:ff67d9f36b67	3556	* @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
<>	157:ff67d9f36b67	3557	* @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
<>	157:ff67d9f36b67	3558	* @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
<>	157:ff67d9f36b67	3559	* @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
<>	157:ff67d9f36b67	3560	* @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
<>	157:ff67d9f36b67	3561	* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
<>	157:ff67d9f36b67	3562	* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
<>	157:ff67d9f36b67	3563	* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
<>	157:ff67d9f36b67	3564	* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
<>	157:ff67d9f36b67	3565	* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
<>	157:ff67d9f36b67	3566	* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
<>	157:ff67d9f36b67	3567	* @retval None
<>	157:ff67d9f36b67	3568	*/
<>	157:ff67d9f36b67	3569	__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter)
<>	157:ff67d9f36b67	3570	{
<>	157:ff67d9f36b67	3571	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP \| TIM_BDTR_BKF, BreakPolarity \| BreakFilter);
<>	157:ff67d9f36b67	3572	}
<>	157:ff67d9f36b67	3573
<>	157:ff67d9f36b67	3574	#else
<>	157:ff67d9f36b67	3575	/**
<>	157:ff67d9f36b67	3576	* @brief Configure the break input.
<>	157:ff67d9f36b67	3577	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3578	* a timer instance provides a break input.
<>	157:ff67d9f36b67	3579	* @rmtoll BDTR BKP LL_TIM_ConfigBRK
<>	157:ff67d9f36b67	3580	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3581	* @param BreakPolarity This parameter can be one of the following values:
<>	157:ff67d9f36b67	3582	* @arg @ref LL_TIM_BREAK_POLARITY_LOW
<>	157:ff67d9f36b67	3583	* @arg @ref LL_TIM_BREAK_POLARITY_HIGH
<>	157:ff67d9f36b67	3584	* @retval None
<>	157:ff67d9f36b67	3585	*/
<>	157:ff67d9f36b67	3586	__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
<>	157:ff67d9f36b67	3587	{
<>	157:ff67d9f36b67	3588	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
<>	157:ff67d9f36b67	3589	}
<>	157:ff67d9f36b67	3590
<>	157:ff67d9f36b67	3591	#endif /* TIM_BDTR_BKF */
<>	157:ff67d9f36b67	3592	#if defined(TIM_BDTR_BK2E)
<>	157:ff67d9f36b67	3593	/**
<>	157:ff67d9f36b67	3594	* @brief Enable the break 2 function.
<>	157:ff67d9f36b67	3595	* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3596	* a timer instance provides a second break input.
<>	157:ff67d9f36b67	3597	* @rmtoll BDTR BK2E LL_TIM_EnableBRK2
<>	157:ff67d9f36b67	3598	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3599	* @retval None
<>	157:ff67d9f36b67	3600	*/
<>	157:ff67d9f36b67	3601	__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3602	{
<>	157:ff67d9f36b67	3603	SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
<>	157:ff67d9f36b67	3604	}
<>	157:ff67d9f36b67	3605
<>	157:ff67d9f36b67	3606	/**
<>	157:ff67d9f36b67	3607	* @brief Disable the break 2 function.
<>	157:ff67d9f36b67	3608	* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3609	* a timer instance provides a second break input.
<>	157:ff67d9f36b67	3610	* @rmtoll BDTR BK2E LL_TIM_DisableBRK2
<>	157:ff67d9f36b67	3611	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3612	* @retval None
<>	157:ff67d9f36b67	3613	*/
<>	157:ff67d9f36b67	3614	__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3615	{
<>	157:ff67d9f36b67	3616	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
<>	157:ff67d9f36b67	3617	}
<>	157:ff67d9f36b67	3618
<>	157:ff67d9f36b67	3619	/**
<>	157:ff67d9f36b67	3620	* @brief Configure the break 2 input.
<>	157:ff67d9f36b67	3621	* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3622	* a timer instance provides a second break input.
<>	157:ff67d9f36b67	3623	* @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
<>	157:ff67d9f36b67	3624	* BDTR BK2F LL_TIM_ConfigBRK2
<>	157:ff67d9f36b67	3625	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3626	* @param Break2Polarity This parameter can be one of the following values:
<>	157:ff67d9f36b67	3627	* @arg @ref LL_TIM_BREAK2_POLARITY_LOW
<>	157:ff67d9f36b67	3628	* @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
<>	157:ff67d9f36b67	3629	* @param Break2Filter This parameter can be one of the following values:
<>	157:ff67d9f36b67	3630	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
<>	157:ff67d9f36b67	3631	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
<>	157:ff67d9f36b67	3632	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
<>	157:ff67d9f36b67	3633	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
<>	157:ff67d9f36b67	3634	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
<>	157:ff67d9f36b67	3635	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
<>	157:ff67d9f36b67	3636	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
<>	157:ff67d9f36b67	3637	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
<>	157:ff67d9f36b67	3638	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
<>	157:ff67d9f36b67	3639	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
<>	157:ff67d9f36b67	3640	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
<>	157:ff67d9f36b67	3641	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
<>	157:ff67d9f36b67	3642	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
<>	157:ff67d9f36b67	3643	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
<>	157:ff67d9f36b67	3644	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
<>	157:ff67d9f36b67	3645	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
<>	157:ff67d9f36b67	3646	* @retval None
<>	157:ff67d9f36b67	3647	*/
<>	157:ff67d9f36b67	3648	__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
<>	157:ff67d9f36b67	3649	{
<>	157:ff67d9f36b67	3650	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P \| TIM_BDTR_BK2F, Break2Polarity \| Break2Filter);
<>	157:ff67d9f36b67	3651	}
<>	157:ff67d9f36b67	3652
<>	157:ff67d9f36b67	3653	#endif /* TIM_BDTR_BK2E */
<>	157:ff67d9f36b67	3654	/**
<>	157:ff67d9f36b67	3655	* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
<>	157:ff67d9f36b67	3656	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3657	* a timer instance provides a break input.
<>	157:ff67d9f36b67	3658	* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
<>	157:ff67d9f36b67	3659	* BDTR OSSR LL_TIM_SetOffStates
<>	157:ff67d9f36b67	3660	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3661	* @param OffStateIdle This parameter can be one of the following values:
<>	157:ff67d9f36b67	3662	* @arg @ref LL_TIM_OSSI_DISABLE
<>	157:ff67d9f36b67	3663	* @arg @ref LL_TIM_OSSI_ENABLE
<>	157:ff67d9f36b67	3664	* @param OffStateRun This parameter can be one of the following values:
<>	157:ff67d9f36b67	3665	* @arg @ref LL_TIM_OSSR_DISABLE
<>	157:ff67d9f36b67	3666	* @arg @ref LL_TIM_OSSR_ENABLE
<>	157:ff67d9f36b67	3667	* @retval None
<>	157:ff67d9f36b67	3668	*/
<>	157:ff67d9f36b67	3669	__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
<>	157:ff67d9f36b67	3670	{
<>	157:ff67d9f36b67	3671	MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI \| TIM_BDTR_OSSR, OffStateIdle \| OffStateRun);
<>	157:ff67d9f36b67	3672	}
<>	157:ff67d9f36b67	3673
<>	157:ff67d9f36b67	3674	/**
<>	157:ff67d9f36b67	3675	* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
<>	157:ff67d9f36b67	3676	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3677	* a timer instance provides a break input.
<>	157:ff67d9f36b67	3678	* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
<>	157:ff67d9f36b67	3679	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3680	* @retval None
<>	157:ff67d9f36b67	3681	*/
<>	157:ff67d9f36b67	3682	__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3683	{
<>	157:ff67d9f36b67	3684	SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
<>	157:ff67d9f36b67	3685	}
<>	157:ff67d9f36b67	3686
<>	157:ff67d9f36b67	3687	/**
<>	157:ff67d9f36b67	3688	* @brief Disable automatic output (MOE can be set only by software).
<>	157:ff67d9f36b67	3689	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3690	* a timer instance provides a break input.
<>	157:ff67d9f36b67	3691	* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
<>	157:ff67d9f36b67	3692	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3693	* @retval None
<>	157:ff67d9f36b67	3694	*/
<>	157:ff67d9f36b67	3695	__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3696	{
<>	157:ff67d9f36b67	3697	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
<>	157:ff67d9f36b67	3698	}
<>	157:ff67d9f36b67	3699
<>	157:ff67d9f36b67	3700	/**
<>	157:ff67d9f36b67	3701	* @brief Indicate whether automatic output is enabled.
<>	157:ff67d9f36b67	3702	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3703	* a timer instance provides a break input.
<>	157:ff67d9f36b67	3704	* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
<>	157:ff67d9f36b67	3705	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3706	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	3707	*/
<>	157:ff67d9f36b67	3708	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3709	{
<>	157:ff67d9f36b67	3710	return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
<>	157:ff67d9f36b67	3711	}
<>	157:ff67d9f36b67	3712
<>	157:ff67d9f36b67	3713	/**
<>	157:ff67d9f36b67	3714	* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
<>	157:ff67d9f36b67	3715	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
<>	157:ff67d9f36b67	3716	* software and is reset in case of break or break2 event
<>	157:ff67d9f36b67	3717	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3718	* a timer instance provides a break input.
<>	157:ff67d9f36b67	3719	* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
<>	157:ff67d9f36b67	3720	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3721	* @retval None
<>	157:ff67d9f36b67	3722	*/
<>	157:ff67d9f36b67	3723	__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3724	{
<>	157:ff67d9f36b67	3725	SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
<>	157:ff67d9f36b67	3726	}
<>	157:ff67d9f36b67	3727
<>	157:ff67d9f36b67	3728	/**
<>	157:ff67d9f36b67	3729	* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
<>	157:ff67d9f36b67	3730	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
<>	157:ff67d9f36b67	3731	* software and is reset in case of break or break2 event.
<>	157:ff67d9f36b67	3732	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3733	* a timer instance provides a break input.
<>	157:ff67d9f36b67	3734	* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
<>	157:ff67d9f36b67	3735	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3736	* @retval None
<>	157:ff67d9f36b67	3737	*/
<>	157:ff67d9f36b67	3738	__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3739	{
<>	157:ff67d9f36b67	3740	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
<>	157:ff67d9f36b67	3741	}
<>	157:ff67d9f36b67	3742
<>	157:ff67d9f36b67	3743	/**
<>	157:ff67d9f36b67	3744	* @brief Indicates whether outputs are enabled.
<>	157:ff67d9f36b67	3745	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3746	* a timer instance provides a break input.
<>	157:ff67d9f36b67	3747	* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
<>	157:ff67d9f36b67	3748	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3749	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	3750	*/
<>	157:ff67d9f36b67	3751	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3752	{
<>	157:ff67d9f36b67	3753	return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
<>	157:ff67d9f36b67	3754	}
<>	157:ff67d9f36b67	3755
<>	157:ff67d9f36b67	3756	/**
<>	157:ff67d9f36b67	3757	* @}
<>	157:ff67d9f36b67	3758	*/
<>	157:ff67d9f36b67	3759
<>	157:ff67d9f36b67	3760	/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
<>	157:ff67d9f36b67	3761	* @{
<>	157:ff67d9f36b67	3762	*/
<>	157:ff67d9f36b67	3763	/**
<>	157:ff67d9f36b67	3764	* @brief Configures the timer DMA burst feature.
<>	157:ff67d9f36b67	3765	* @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
<>	157:ff67d9f36b67	3766	* not a timer instance supports the DMA burst mode.
<>	157:ff67d9f36b67	3767	* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
<>	157:ff67d9f36b67	3768	* DCR DBA LL_TIM_ConfigDMABurst
<>	157:ff67d9f36b67	3769	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3770	* @param DMABurstBaseAddress This parameter can be one of the following values:
<>	157:ff67d9f36b67	3771	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
<>	157:ff67d9f36b67	3772	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
<>	157:ff67d9f36b67	3773	* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
<>	157:ff67d9f36b67	3774	* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
<>	157:ff67d9f36b67	3775	* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
<>	157:ff67d9f36b67	3776	* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
<>	157:ff67d9f36b67	3777	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
<>	157:ff67d9f36b67	3778	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
<>	157:ff67d9f36b67	3779	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
<>	157:ff67d9f36b67	3780	* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
<>	157:ff67d9f36b67	3781	* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
<>	157:ff67d9f36b67	3782	* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
<>	157:ff67d9f36b67	3783	* @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
<>	157:ff67d9f36b67	3784	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
<>	157:ff67d9f36b67	3785	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
<>	157:ff67d9f36b67	3786	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
<>	157:ff67d9f36b67	3787	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
<>	157:ff67d9f36b67	3788	* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
<>	157:ff67d9f36b67	3789	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 (*)
<>	157:ff67d9f36b67	3790	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 (*)
<>	157:ff67d9f36b67	3791	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 (*)
<>	157:ff67d9f36b67	3792	* (*) value not defined in all devices
<>	157:ff67d9f36b67	3793	* @arg @ref LL_TIM_DMABURST_BASEADDR_OR
<>	157:ff67d9f36b67	3794	* @param DMABurstLength This parameter can be one of the following values:
<>	157:ff67d9f36b67	3795	* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
<>	157:ff67d9f36b67	3796	* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
<>	157:ff67d9f36b67	3797	* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
<>	157:ff67d9f36b67	3798	* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
<>	157:ff67d9f36b67	3799	* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
<>	157:ff67d9f36b67	3800	* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
<>	157:ff67d9f36b67	3801	* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
<>	157:ff67d9f36b67	3802	* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
<>	157:ff67d9f36b67	3803	* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
<>	157:ff67d9f36b67	3804	* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
<>	157:ff67d9f36b67	3805	* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
<>	157:ff67d9f36b67	3806	* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
<>	157:ff67d9f36b67	3807	* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
<>	157:ff67d9f36b67	3808	* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
<>	157:ff67d9f36b67	3809	* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
<>	157:ff67d9f36b67	3810	* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
<>	157:ff67d9f36b67	3811	* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
<>	157:ff67d9f36b67	3812	* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
<>	157:ff67d9f36b67	3813	* @retval None
<>	157:ff67d9f36b67	3814	*/
<>	157:ff67d9f36b67	3815	__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
<>	157:ff67d9f36b67	3816	{
<>	157:ff67d9f36b67	3817	MODIFY_REG(TIMx->DCR, TIM_DCR_DBL \| TIM_DCR_DBA, DMABurstBaseAddress \| DMABurstLength);
<>	157:ff67d9f36b67	3818	}
<>	157:ff67d9f36b67	3819
<>	157:ff67d9f36b67	3820	/**
<>	157:ff67d9f36b67	3821	* @}
<>	157:ff67d9f36b67	3822	*/
<>	157:ff67d9f36b67	3823
<>	157:ff67d9f36b67	3824	/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
<>	157:ff67d9f36b67	3825	* @{
<>	157:ff67d9f36b67	3826	*/
<>	157:ff67d9f36b67	3827	/**
<>	157:ff67d9f36b67	3828	* @brief Remap TIM inputs (input channel, internal/external triggers).
<>	157:ff67d9f36b67	3829	* @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
<>	157:ff67d9f36b67	3830	* a some timer inputs can be remapped.
<>	157:ff67d9f36b67	3831	* @if STM32F334x8
<>	157:ff67d9f36b67	3832	* @rmtoll TIM1_OR ETR_RMP LL_TIM_SetRemap\n
<>	157:ff67d9f36b67	3833	* TIM16_OR TI1_RMP LL_TIM_SetRemap\n
<>	157:ff67d9f36b67	3834	* @elseif STM32F302x8
<>	157:ff67d9f36b67	3835	* @rmtoll TIM1_OR ETR_RMP LL_TIM_SetRemap\n
<>	157:ff67d9f36b67	3836	* TIM16_OR TI1_RMP LL_TIM_SetRemap\n
<>	157:ff67d9f36b67	3837	* @elseif STM32F303xC
<>	157:ff67d9f36b67	3838	* @rmtoll TIM1_OR ETR_RMP LL_TIM_SetRemap\n
<>	157:ff67d9f36b67	3839	* TIM8_OR ETR_RMP LL_TIM_SetRemap\n
<>	157:ff67d9f36b67	3840	* TIM20_OR ETR_RMP LL_TIM_SetRemap\n
<>	157:ff67d9f36b67	3841	* @elseif STM32F373xC
<>	157:ff67d9f36b67	3842	* @rmtoll TIM14_OR TI1_RMP LL_TIM_SetRemap
<>	157:ff67d9f36b67	3843	* @endif
<>	157:ff67d9f36b67	3844	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3845	* @param Remap Remap params depends on the TIMx. Description available only
<>	157:ff67d9f36b67	3846	* in CHM version of the User Manual (not in .pdf).
<>	157:ff67d9f36b67	3847	* Otherwise see Reference Manual description of OR registers.
<>	157:ff67d9f36b67	3848	*
<>	157:ff67d9f36b67	3849	* Below description summarizes "Timer Instance" and "Remap" param combinations:
<>	157:ff67d9f36b67	3850	*
<>	157:ff67d9f36b67	3851	* TIM1: any combination of ETR_RMP where (**)
<>	157:ff67d9f36b67	3852	*
<>	157:ff67d9f36b67	3853	* . . ETR_RMP can be one of the following values
<>	157:ff67d9f36b67	3854	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
<>	157:ff67d9f36b67	3855	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (*)
<>	157:ff67d9f36b67	3856	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (*)
<>	157:ff67d9f36b67	3857	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (*)
<>	157:ff67d9f36b67	3858	* @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_NC (*)
<>	157:ff67d9f36b67	3859	* @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD1 (*)
<>	157:ff67d9f36b67	3860	* @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD2 (*)
<>	157:ff67d9f36b67	3861	* @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD3 (*)
<>	157:ff67d9f36b67	3862	* @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_NC (*)
<>	157:ff67d9f36b67	3863	* @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 (*)
<>	157:ff67d9f36b67	3864	* @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 (*)
<>	157:ff67d9f36b67	3865	* @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 (*)
<>	157:ff67d9f36b67	3866	*
<>	157:ff67d9f36b67	3867	* TIM8: any combination of ETR_RMP where (**)
<>	157:ff67d9f36b67	3868	*
<>	157:ff67d9f36b67	3869	* . . ETR_RMP can be one of the following values
<>	157:ff67d9f36b67	3870	* @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_NC (*)
<>	157:ff67d9f36b67	3871	* @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (*)
<>	157:ff67d9f36b67	3872	* @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (*)
<>	157:ff67d9f36b67	3873	* @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (*)
<>	157:ff67d9f36b67	3874	* @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_NC (*)
<>	157:ff67d9f36b67	3875	* @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (*)
<>	157:ff67d9f36b67	3876	* @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (*)
<>	157:ff67d9f36b67	3877	* @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (*)
<>	157:ff67d9f36b67	3878	*
<>	157:ff67d9f36b67	3879	* TIM14: any combination of TI1_RMP where (**)
<>	157:ff67d9f36b67	3880	*
<>	157:ff67d9f36b67	3881	* . . TI1_RMP can be one of the following values
<>	157:ff67d9f36b67	3882	* @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO (*)
<>	157:ff67d9f36b67	3883	* @arg @ref LL_TIM_TIM14_TI1_RMP_RTC_CLK (*)
<>	157:ff67d9f36b67	3884	* @arg @ref LL_TIM_TIM14_TI1_RMP_HSE (*)
<>	157:ff67d9f36b67	3885	* @arg @ref LL_TIM_TIM14_TI1_RMP_MCO (*)
<>	157:ff67d9f36b67	3886	*
<>	157:ff67d9f36b67	3887	* TIM16: any combination of TI1_RMP where (**)
<>	157:ff67d9f36b67	3888	*
<>	157:ff67d9f36b67	3889	* . . TI1_RMP can be one of the following values
<>	157:ff67d9f36b67	3890	* @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO (*)
<>	157:ff67d9f36b67	3891	* @arg @ref LL_TIM_TIM16_TI1_RMP_LSI (*)
<>	157:ff67d9f36b67	3892	* @arg @ref LL_TIM_TIM16_TI1_RMP_LSE (*)
<>	157:ff67d9f36b67	3893	* @arg @ref LL_TIM_TIM16_TI1_RMP_RTC (*)
<>	157:ff67d9f36b67	3894	*
<>	157:ff67d9f36b67	3895	* TIM20: any combination of ETR_RMP where (**)
<>	157:ff67d9f36b67	3896	*
<>	157:ff67d9f36b67	3897	* . . ETR_RMP can be one of the following values
<>	157:ff67d9f36b67	3898	* @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_NC (*)
<>	157:ff67d9f36b67	3899	* @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD1 (*)
<>	157:ff67d9f36b67	3900	* @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD2 (*)
<>	157:ff67d9f36b67	3901	* @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD3 (*)
<>	157:ff67d9f36b67	3902	* @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_NC (*)
<>	157:ff67d9f36b67	3903	* @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD1 (*)
<>	157:ff67d9f36b67	3904	* @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD2 (*)
<>	157:ff67d9f36b67	3905	* @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD3 (*)
<>	157:ff67d9f36b67	3906	*
<>	157:ff67d9f36b67	3907	* (*) Value not defined in all devices. \n
<>	157:ff67d9f36b67	3908	* (**) Register not available in all devices.
<>	157:ff67d9f36b67	3909	* @retval None
<>	157:ff67d9f36b67	3910	*/
<>	157:ff67d9f36b67	3911	__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
<>	157:ff67d9f36b67	3912	{
<>	157:ff67d9f36b67	3913	MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
<>	157:ff67d9f36b67	3914	}
<>	157:ff67d9f36b67	3915
<>	157:ff67d9f36b67	3916	/**
<>	157:ff67d9f36b67	3917	* @}
<>	157:ff67d9f36b67	3918	*/
<>	157:ff67d9f36b67	3919
<>	157:ff67d9f36b67	3920	#if defined(TIM_SMCR_OCCS)
<>	157:ff67d9f36b67	3921	/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
<>	157:ff67d9f36b67	3922	* @{
<>	157:ff67d9f36b67	3923	*/
<>	157:ff67d9f36b67	3924	/**
<>	157:ff67d9f36b67	3925	* @brief Set the OCREF clear input source
<>	157:ff67d9f36b67	3926	* @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
<>	157:ff67d9f36b67	3927	* @note This function can only be used in Output compare and PWM modes.
<>	157:ff67d9f36b67	3928	* @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
<>	157:ff67d9f36b67	3929	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3930	* @param OCRefClearInputSource This parameter can be one of the following values:
<>	157:ff67d9f36b67	3931	* @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
<>	157:ff67d9f36b67	3932	* @arg @ref LL_TIM_OCREF_CLR_INT_ETR
<>	157:ff67d9f36b67	3933	* @retval None
<>	157:ff67d9f36b67	3934	*/
<>	157:ff67d9f36b67	3935	__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
<>	157:ff67d9f36b67	3936	{
<>	157:ff67d9f36b67	3937	MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
<>	157:ff67d9f36b67	3938	}
<>	157:ff67d9f36b67	3939	/**
<>	157:ff67d9f36b67	3940	* @}
<>	157:ff67d9f36b67	3941	*/
<>	157:ff67d9f36b67	3942	#endif /* TIM_SMCR_OCCS */
<>	157:ff67d9f36b67	3943
<>	157:ff67d9f36b67	3944	/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
<>	157:ff67d9f36b67	3945	* @{
<>	157:ff67d9f36b67	3946	*/
<>	157:ff67d9f36b67	3947	/**
<>	157:ff67d9f36b67	3948	* @brief Clear the update interrupt flag (UIF).
<>	157:ff67d9f36b67	3949	* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
<>	157:ff67d9f36b67	3950	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3951	* @retval None
<>	157:ff67d9f36b67	3952	*/
<>	157:ff67d9f36b67	3953	__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3954	{
<>	157:ff67d9f36b67	3955	WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
<>	157:ff67d9f36b67	3956	}
<>	157:ff67d9f36b67	3957
<>	157:ff67d9f36b67	3958	/**
<>	157:ff67d9f36b67	3959	* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
<>	157:ff67d9f36b67	3960	* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
<>	157:ff67d9f36b67	3961	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3962	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	3963	*/
<>	157:ff67d9f36b67	3964	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3965	{
<>	157:ff67d9f36b67	3966	return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
<>	157:ff67d9f36b67	3967	}
<>	157:ff67d9f36b67	3968
<>	157:ff67d9f36b67	3969	/**
<>	157:ff67d9f36b67	3970	* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
<>	157:ff67d9f36b67	3971	* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
<>	157:ff67d9f36b67	3972	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3973	* @retval None
<>	157:ff67d9f36b67	3974	*/
<>	157:ff67d9f36b67	3975	__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3976	{
<>	157:ff67d9f36b67	3977	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
<>	157:ff67d9f36b67	3978	}
<>	157:ff67d9f36b67	3979
<>	157:ff67d9f36b67	3980	/**
<>	157:ff67d9f36b67	3981	* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
<>	157:ff67d9f36b67	3982	* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
<>	157:ff67d9f36b67	3983	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3984	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	3985	*/
<>	157:ff67d9f36b67	3986	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3987	{
<>	157:ff67d9f36b67	3988	return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
<>	157:ff67d9f36b67	3989	}
<>	157:ff67d9f36b67	3990
<>	157:ff67d9f36b67	3991	/**
<>	157:ff67d9f36b67	3992	* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
<>	157:ff67d9f36b67	3993	* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
<>	157:ff67d9f36b67	3994	* @param TIMx Timer instance
<>	157:ff67d9f36b67	3995	* @retval None
<>	157:ff67d9f36b67	3996	*/
<>	157:ff67d9f36b67	3997	__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	3998	{
<>	157:ff67d9f36b67	3999	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
<>	157:ff67d9f36b67	4000	}
<>	157:ff67d9f36b67	4001
<>	157:ff67d9f36b67	4002	/**
<>	157:ff67d9f36b67	4003	* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
<>	157:ff67d9f36b67	4004	* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
<>	157:ff67d9f36b67	4005	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4006	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4007	*/
<>	157:ff67d9f36b67	4008	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4009	{
<>	157:ff67d9f36b67	4010	return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
<>	157:ff67d9f36b67	4011	}
<>	157:ff67d9f36b67	4012
<>	157:ff67d9f36b67	4013	/**
<>	157:ff67d9f36b67	4014	* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
<>	157:ff67d9f36b67	4015	* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
<>	157:ff67d9f36b67	4016	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4017	* @retval None
<>	157:ff67d9f36b67	4018	*/
<>	157:ff67d9f36b67	4019	__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4020	{
<>	157:ff67d9f36b67	4021	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
<>	157:ff67d9f36b67	4022	}
<>	157:ff67d9f36b67	4023
<>	157:ff67d9f36b67	4024	/**
<>	157:ff67d9f36b67	4025	* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
<>	157:ff67d9f36b67	4026	* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
<>	157:ff67d9f36b67	4027	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4028	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4029	*/
<>	157:ff67d9f36b67	4030	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4031	{
<>	157:ff67d9f36b67	4032	return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
<>	157:ff67d9f36b67	4033	}
<>	157:ff67d9f36b67	4034
<>	157:ff67d9f36b67	4035	/**
<>	157:ff67d9f36b67	4036	* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
<>	157:ff67d9f36b67	4037	* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
<>	157:ff67d9f36b67	4038	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4039	* @retval None
<>	157:ff67d9f36b67	4040	*/
<>	157:ff67d9f36b67	4041	__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4042	{
<>	157:ff67d9f36b67	4043	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
<>	157:ff67d9f36b67	4044	}
<>	157:ff67d9f36b67	4045
<>	157:ff67d9f36b67	4046	/**
<>	157:ff67d9f36b67	4047	* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
<>	157:ff67d9f36b67	4048	* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
<>	157:ff67d9f36b67	4049	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4050	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4051	*/
<>	157:ff67d9f36b67	4052	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4053	{
<>	157:ff67d9f36b67	4054	return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
<>	157:ff67d9f36b67	4055	}
<>	157:ff67d9f36b67	4056
<>	157:ff67d9f36b67	4057	#if defined (TIM_SR_CC5IF)
<>	157:ff67d9f36b67	4058	/**
<>	157:ff67d9f36b67	4059	* @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
<>	157:ff67d9f36b67	4060	* @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
<>	157:ff67d9f36b67	4061	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4062	* @retval None
<>	157:ff67d9f36b67	4063	*/
<>	157:ff67d9f36b67	4064	__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4065	{
<>	157:ff67d9f36b67	4066	WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
<>	157:ff67d9f36b67	4067	}
<>	157:ff67d9f36b67	4068
<>	157:ff67d9f36b67	4069	/**
<>	157:ff67d9f36b67	4070	* @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
<>	157:ff67d9f36b67	4071	* @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
<>	157:ff67d9f36b67	4072	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4073	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4074	*/
<>	157:ff67d9f36b67	4075	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4076	{
<>	157:ff67d9f36b67	4077	return (READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF));
<>	157:ff67d9f36b67	4078	}
<>	157:ff67d9f36b67	4079
<>	157:ff67d9f36b67	4080	#endif /* TIM_SR_CC5IF */
<>	157:ff67d9f36b67	4081	#if defined (TIM_SR_CC6IF)
<>	157:ff67d9f36b67	4082	/**
<>	157:ff67d9f36b67	4083	* @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
<>	157:ff67d9f36b67	4084	* @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
<>	157:ff67d9f36b67	4085	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4086	* @retval None
<>	157:ff67d9f36b67	4087	*/
<>	157:ff67d9f36b67	4088	__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4089	{
<>	157:ff67d9f36b67	4090	WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
<>	157:ff67d9f36b67	4091	}
<>	157:ff67d9f36b67	4092
<>	157:ff67d9f36b67	4093	/**
<>	157:ff67d9f36b67	4094	* @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
<>	157:ff67d9f36b67	4095	* @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
<>	157:ff67d9f36b67	4096	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4097	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4098	*/
<>	157:ff67d9f36b67	4099	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4100	{
<>	157:ff67d9f36b67	4101	return (READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF));
<>	157:ff67d9f36b67	4102	}
<>	157:ff67d9f36b67	4103
<>	157:ff67d9f36b67	4104	#endif /* TIM_SR_CC6IF */
<>	157:ff67d9f36b67	4105	/**
<>	157:ff67d9f36b67	4106	* @brief Clear the commutation interrupt flag (COMIF).
<>	157:ff67d9f36b67	4107	* @rmtoll SR COMIF LL_TIM_ClearFlag_COM
<>	157:ff67d9f36b67	4108	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4109	* @retval None
<>	157:ff67d9f36b67	4110	*/
<>	157:ff67d9f36b67	4111	__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4112	{
<>	157:ff67d9f36b67	4113	WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
<>	157:ff67d9f36b67	4114	}
<>	157:ff67d9f36b67	4115
<>	157:ff67d9f36b67	4116	/**
<>	157:ff67d9f36b67	4117	* @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
<>	157:ff67d9f36b67	4118	* @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
<>	157:ff67d9f36b67	4119	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4120	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4121	*/
<>	157:ff67d9f36b67	4122	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4123	{
<>	157:ff67d9f36b67	4124	return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
<>	157:ff67d9f36b67	4125	}
<>	157:ff67d9f36b67	4126
<>	157:ff67d9f36b67	4127	/**
<>	157:ff67d9f36b67	4128	* @brief Clear the trigger interrupt flag (TIF).
<>	157:ff67d9f36b67	4129	* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
<>	157:ff67d9f36b67	4130	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4131	* @retval None
<>	157:ff67d9f36b67	4132	*/
<>	157:ff67d9f36b67	4133	__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4134	{
<>	157:ff67d9f36b67	4135	WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
<>	157:ff67d9f36b67	4136	}
<>	157:ff67d9f36b67	4137
<>	157:ff67d9f36b67	4138	/**
<>	157:ff67d9f36b67	4139	* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
<>	157:ff67d9f36b67	4140	* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
<>	157:ff67d9f36b67	4141	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4142	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4143	*/
<>	157:ff67d9f36b67	4144	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4145	{
<>	157:ff67d9f36b67	4146	return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
<>	157:ff67d9f36b67	4147	}
<>	157:ff67d9f36b67	4148
<>	157:ff67d9f36b67	4149	/**
<>	157:ff67d9f36b67	4150	* @brief Clear the break interrupt flag (BIF).
<>	157:ff67d9f36b67	4151	* @rmtoll SR BIF LL_TIM_ClearFlag_BRK
<>	157:ff67d9f36b67	4152	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4153	* @retval None
<>	157:ff67d9f36b67	4154	*/
<>	157:ff67d9f36b67	4155	__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4156	{
<>	157:ff67d9f36b67	4157	WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
<>	157:ff67d9f36b67	4158	}
<>	157:ff67d9f36b67	4159
<>	157:ff67d9f36b67	4160	/**
<>	157:ff67d9f36b67	4161	* @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
<>	157:ff67d9f36b67	4162	* @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
<>	157:ff67d9f36b67	4163	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4164	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4165	*/
<>	157:ff67d9f36b67	4166	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4167	{
<>	157:ff67d9f36b67	4168	return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
<>	157:ff67d9f36b67	4169	}
<>	157:ff67d9f36b67	4170
<>	157:ff67d9f36b67	4171	#if defined(TIM_SR_B2IF)
<>	157:ff67d9f36b67	4172	/**
<>	157:ff67d9f36b67	4173	* @brief Clear the break 2 interrupt flag (B2IF).
<>	157:ff67d9f36b67	4174	* @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
<>	157:ff67d9f36b67	4175	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4176	* @retval None
<>	157:ff67d9f36b67	4177	*/
<>	157:ff67d9f36b67	4178	__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4179	{
<>	157:ff67d9f36b67	4180	WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
<>	157:ff67d9f36b67	4181	}
<>	157:ff67d9f36b67	4182
<>	157:ff67d9f36b67	4183	/**
<>	157:ff67d9f36b67	4184	* @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
<>	157:ff67d9f36b67	4185	* @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
<>	157:ff67d9f36b67	4186	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4187	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4188	*/
<>	157:ff67d9f36b67	4189	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4190	{
<>	157:ff67d9f36b67	4191	return (READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF));
<>	157:ff67d9f36b67	4192	}
<>	157:ff67d9f36b67	4193
<>	157:ff67d9f36b67	4194	#endif /* TIM_SR_B2IF */
<>	157:ff67d9f36b67	4195	/**
<>	157:ff67d9f36b67	4196	* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
<>	157:ff67d9f36b67	4197	* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
<>	157:ff67d9f36b67	4198	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4199	* @retval None
<>	157:ff67d9f36b67	4200	*/
<>	157:ff67d9f36b67	4201	__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4202	{
<>	157:ff67d9f36b67	4203	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
<>	157:ff67d9f36b67	4204	}
<>	157:ff67d9f36b67	4205
<>	157:ff67d9f36b67	4206	/**
<>	157:ff67d9f36b67	4207	* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
<>	157:ff67d9f36b67	4208	* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
<>	157:ff67d9f36b67	4209	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4210	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4211	*/
<>	157:ff67d9f36b67	4212	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4213	{
<>	157:ff67d9f36b67	4214	return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
<>	157:ff67d9f36b67	4215	}
<>	157:ff67d9f36b67	4216
<>	157:ff67d9f36b67	4217	/**
<>	157:ff67d9f36b67	4218	* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
<>	157:ff67d9f36b67	4219	* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
<>	157:ff67d9f36b67	4220	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4221	* @retval None
<>	157:ff67d9f36b67	4222	*/
<>	157:ff67d9f36b67	4223	__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4224	{
<>	157:ff67d9f36b67	4225	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
<>	157:ff67d9f36b67	4226	}
<>	157:ff67d9f36b67	4227
<>	157:ff67d9f36b67	4228	/**
<>	157:ff67d9f36b67	4229	* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
<>	157:ff67d9f36b67	4230	* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
<>	157:ff67d9f36b67	4231	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4232	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4233	*/
<>	157:ff67d9f36b67	4234	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4235	{
<>	157:ff67d9f36b67	4236	return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
<>	157:ff67d9f36b67	4237	}
<>	157:ff67d9f36b67	4238
<>	157:ff67d9f36b67	4239	/**
<>	157:ff67d9f36b67	4240	* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
<>	157:ff67d9f36b67	4241	* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
<>	157:ff67d9f36b67	4242	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4243	* @retval None
<>	157:ff67d9f36b67	4244	*/
<>	157:ff67d9f36b67	4245	__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4246	{
<>	157:ff67d9f36b67	4247	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
<>	157:ff67d9f36b67	4248	}
<>	157:ff67d9f36b67	4249
<>	157:ff67d9f36b67	4250	/**
<>	157:ff67d9f36b67	4251	* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
<>	157:ff67d9f36b67	4252	* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
<>	157:ff67d9f36b67	4253	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4254	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4255	*/
<>	157:ff67d9f36b67	4256	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4257	{
<>	157:ff67d9f36b67	4258	return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
<>	157:ff67d9f36b67	4259	}
<>	157:ff67d9f36b67	4260
<>	157:ff67d9f36b67	4261	/**
<>	157:ff67d9f36b67	4262	* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
<>	157:ff67d9f36b67	4263	* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
<>	157:ff67d9f36b67	4264	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4265	* @retval None
<>	157:ff67d9f36b67	4266	*/
<>	157:ff67d9f36b67	4267	__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4268	{
<>	157:ff67d9f36b67	4269	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
<>	157:ff67d9f36b67	4270	}
<>	157:ff67d9f36b67	4271
<>	157:ff67d9f36b67	4272	/**
<>	157:ff67d9f36b67	4273	* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
<>	157:ff67d9f36b67	4274	* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
<>	157:ff67d9f36b67	4275	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4276	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4277	*/
<>	157:ff67d9f36b67	4278	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4279	{
<>	157:ff67d9f36b67	4280	return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
<>	157:ff67d9f36b67	4281	}
<>	157:ff67d9f36b67	4282
<>	157:ff67d9f36b67	4283	/**
<>	157:ff67d9f36b67	4284	* @}
<>	157:ff67d9f36b67	4285	*/
<>	157:ff67d9f36b67	4286
<>	157:ff67d9f36b67	4287	/** @defgroup TIM_LL_EF_IT_Management IT-Management
<>	157:ff67d9f36b67	4288	* @{
<>	157:ff67d9f36b67	4289	*/
<>	157:ff67d9f36b67	4290	/**
<>	157:ff67d9f36b67	4291	* @brief Enable update interrupt (UIE).
<>	157:ff67d9f36b67	4292	* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
<>	157:ff67d9f36b67	4293	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4294	* @retval None
<>	157:ff67d9f36b67	4295	*/
<>	157:ff67d9f36b67	4296	__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4297	{
<>	157:ff67d9f36b67	4298	SET_BIT(TIMx->DIER, TIM_DIER_UIE);
<>	157:ff67d9f36b67	4299	}
<>	157:ff67d9f36b67	4300
<>	157:ff67d9f36b67	4301	/**
<>	157:ff67d9f36b67	4302	* @brief Disable update interrupt (UIE).
<>	157:ff67d9f36b67	4303	* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
<>	157:ff67d9f36b67	4304	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4305	* @retval None
<>	157:ff67d9f36b67	4306	*/
<>	157:ff67d9f36b67	4307	__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4308	{
<>	157:ff67d9f36b67	4309	CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
<>	157:ff67d9f36b67	4310	}
<>	157:ff67d9f36b67	4311
<>	157:ff67d9f36b67	4312	/**
<>	157:ff67d9f36b67	4313	* @brief Indicates whether the update interrupt (UIE) is enabled.
<>	157:ff67d9f36b67	4314	* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
<>	157:ff67d9f36b67	4315	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4316	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4317	*/
<>	157:ff67d9f36b67	4318	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4319	{
<>	157:ff67d9f36b67	4320	return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
<>	157:ff67d9f36b67	4321	}
<>	157:ff67d9f36b67	4322
<>	157:ff67d9f36b67	4323	/**
<>	157:ff67d9f36b67	4324	* @brief Enable capture/compare 1 interrupt (CC1IE).
<>	157:ff67d9f36b67	4325	* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
<>	157:ff67d9f36b67	4326	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4327	* @retval None
<>	157:ff67d9f36b67	4328	*/
<>	157:ff67d9f36b67	4329	__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4330	{
<>	157:ff67d9f36b67	4331	SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
<>	157:ff67d9f36b67	4332	}
<>	157:ff67d9f36b67	4333
<>	157:ff67d9f36b67	4334	/**
<>	157:ff67d9f36b67	4335	* @brief Disable capture/compare 1 interrupt (CC1IE).
<>	157:ff67d9f36b67	4336	* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
<>	157:ff67d9f36b67	4337	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4338	* @retval None
<>	157:ff67d9f36b67	4339	*/
<>	157:ff67d9f36b67	4340	__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4341	{
<>	157:ff67d9f36b67	4342	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
<>	157:ff67d9f36b67	4343	}
<>	157:ff67d9f36b67	4344
<>	157:ff67d9f36b67	4345	/**
<>	157:ff67d9f36b67	4346	* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
<>	157:ff67d9f36b67	4347	* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
<>	157:ff67d9f36b67	4348	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4349	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4350	*/
<>	157:ff67d9f36b67	4351	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4352	{
<>	157:ff67d9f36b67	4353	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
<>	157:ff67d9f36b67	4354	}
<>	157:ff67d9f36b67	4355
<>	157:ff67d9f36b67	4356	/**
<>	157:ff67d9f36b67	4357	* @brief Enable capture/compare 2 interrupt (CC2IE).
<>	157:ff67d9f36b67	4358	* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
<>	157:ff67d9f36b67	4359	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4360	* @retval None
<>	157:ff67d9f36b67	4361	*/
<>	157:ff67d9f36b67	4362	__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4363	{
<>	157:ff67d9f36b67	4364	SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
<>	157:ff67d9f36b67	4365	}
<>	157:ff67d9f36b67	4366
<>	157:ff67d9f36b67	4367	/**
<>	157:ff67d9f36b67	4368	* @brief Disable capture/compare 2 interrupt (CC2IE).
<>	157:ff67d9f36b67	4369	* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
<>	157:ff67d9f36b67	4370	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4371	* @retval None
<>	157:ff67d9f36b67	4372	*/
<>	157:ff67d9f36b67	4373	__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4374	{
<>	157:ff67d9f36b67	4375	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
<>	157:ff67d9f36b67	4376	}
<>	157:ff67d9f36b67	4377
<>	157:ff67d9f36b67	4378	/**
<>	157:ff67d9f36b67	4379	* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
<>	157:ff67d9f36b67	4380	* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
<>	157:ff67d9f36b67	4381	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4382	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4383	*/
<>	157:ff67d9f36b67	4384	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4385	{
<>	157:ff67d9f36b67	4386	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
<>	157:ff67d9f36b67	4387	}
<>	157:ff67d9f36b67	4388
<>	157:ff67d9f36b67	4389	/**
<>	157:ff67d9f36b67	4390	* @brief Enable capture/compare 3 interrupt (CC3IE).
<>	157:ff67d9f36b67	4391	* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
<>	157:ff67d9f36b67	4392	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4393	* @retval None
<>	157:ff67d9f36b67	4394	*/
<>	157:ff67d9f36b67	4395	__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4396	{
<>	157:ff67d9f36b67	4397	SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
<>	157:ff67d9f36b67	4398	}
<>	157:ff67d9f36b67	4399
<>	157:ff67d9f36b67	4400	/**
<>	157:ff67d9f36b67	4401	* @brief Disable capture/compare 3 interrupt (CC3IE).
<>	157:ff67d9f36b67	4402	* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
<>	157:ff67d9f36b67	4403	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4404	* @retval None
<>	157:ff67d9f36b67	4405	*/
<>	157:ff67d9f36b67	4406	__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4407	{
<>	157:ff67d9f36b67	4408	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
<>	157:ff67d9f36b67	4409	}
<>	157:ff67d9f36b67	4410
<>	157:ff67d9f36b67	4411	/**
<>	157:ff67d9f36b67	4412	* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
<>	157:ff67d9f36b67	4413	* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
<>	157:ff67d9f36b67	4414	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4415	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4416	*/
<>	157:ff67d9f36b67	4417	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4418	{
<>	157:ff67d9f36b67	4419	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
<>	157:ff67d9f36b67	4420	}
<>	157:ff67d9f36b67	4421
<>	157:ff67d9f36b67	4422	/**
<>	157:ff67d9f36b67	4423	* @brief Enable capture/compare 4 interrupt (CC4IE).
<>	157:ff67d9f36b67	4424	* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
<>	157:ff67d9f36b67	4425	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4426	* @retval None
<>	157:ff67d9f36b67	4427	*/
<>	157:ff67d9f36b67	4428	__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4429	{
<>	157:ff67d9f36b67	4430	SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
<>	157:ff67d9f36b67	4431	}
<>	157:ff67d9f36b67	4432
<>	157:ff67d9f36b67	4433	/**
<>	157:ff67d9f36b67	4434	* @brief Disable capture/compare 4 interrupt (CC4IE).
<>	157:ff67d9f36b67	4435	* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
<>	157:ff67d9f36b67	4436	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4437	* @retval None
<>	157:ff67d9f36b67	4438	*/
<>	157:ff67d9f36b67	4439	__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4440	{
<>	157:ff67d9f36b67	4441	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
<>	157:ff67d9f36b67	4442	}
<>	157:ff67d9f36b67	4443
<>	157:ff67d9f36b67	4444	/**
<>	157:ff67d9f36b67	4445	* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
<>	157:ff67d9f36b67	4446	* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
<>	157:ff67d9f36b67	4447	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4448	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4449	*/
<>	157:ff67d9f36b67	4450	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4451	{
<>	157:ff67d9f36b67	4452	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
<>	157:ff67d9f36b67	4453	}
<>	157:ff67d9f36b67	4454
<>	157:ff67d9f36b67	4455	/**
<>	157:ff67d9f36b67	4456	* @brief Enable commutation interrupt (COMIE).
<>	157:ff67d9f36b67	4457	* @rmtoll DIER COMIE LL_TIM_EnableIT_COM
<>	157:ff67d9f36b67	4458	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4459	* @retval None
<>	157:ff67d9f36b67	4460	*/
<>	157:ff67d9f36b67	4461	__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4462	{
<>	157:ff67d9f36b67	4463	SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
<>	157:ff67d9f36b67	4464	}
<>	157:ff67d9f36b67	4465
<>	157:ff67d9f36b67	4466	/**
<>	157:ff67d9f36b67	4467	* @brief Disable commutation interrupt (COMIE).
<>	157:ff67d9f36b67	4468	* @rmtoll DIER COMIE LL_TIM_DisableIT_COM
<>	157:ff67d9f36b67	4469	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4470	* @retval None
<>	157:ff67d9f36b67	4471	*/
<>	157:ff67d9f36b67	4472	__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4473	{
<>	157:ff67d9f36b67	4474	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
<>	157:ff67d9f36b67	4475	}
<>	157:ff67d9f36b67	4476
<>	157:ff67d9f36b67	4477	/**
<>	157:ff67d9f36b67	4478	* @brief Indicates whether the commutation interrupt (COMIE) is enabled.
<>	157:ff67d9f36b67	4479	* @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
<>	157:ff67d9f36b67	4480	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4481	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4482	*/
<>	157:ff67d9f36b67	4483	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4484	{
<>	157:ff67d9f36b67	4485	return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
<>	157:ff67d9f36b67	4486	}
<>	157:ff67d9f36b67	4487
<>	157:ff67d9f36b67	4488	/**
<>	157:ff67d9f36b67	4489	* @brief Enable trigger interrupt (TIE).
<>	157:ff67d9f36b67	4490	* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
<>	157:ff67d9f36b67	4491	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4492	* @retval None
<>	157:ff67d9f36b67	4493	*/
<>	157:ff67d9f36b67	4494	__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4495	{
<>	157:ff67d9f36b67	4496	SET_BIT(TIMx->DIER, TIM_DIER_TIE);
<>	157:ff67d9f36b67	4497	}
<>	157:ff67d9f36b67	4498
<>	157:ff67d9f36b67	4499	/**
<>	157:ff67d9f36b67	4500	* @brief Disable trigger interrupt (TIE).
<>	157:ff67d9f36b67	4501	* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
<>	157:ff67d9f36b67	4502	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4503	* @retval None
<>	157:ff67d9f36b67	4504	*/
<>	157:ff67d9f36b67	4505	__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4506	{
<>	157:ff67d9f36b67	4507	CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
<>	157:ff67d9f36b67	4508	}
<>	157:ff67d9f36b67	4509
<>	157:ff67d9f36b67	4510	/**
<>	157:ff67d9f36b67	4511	* @brief Indicates whether the trigger interrupt (TIE) is enabled.
<>	157:ff67d9f36b67	4512	* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
<>	157:ff67d9f36b67	4513	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4514	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4515	*/
<>	157:ff67d9f36b67	4516	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4517	{
<>	157:ff67d9f36b67	4518	return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
<>	157:ff67d9f36b67	4519	}
<>	157:ff67d9f36b67	4520
<>	157:ff67d9f36b67	4521	/**
<>	157:ff67d9f36b67	4522	* @brief Enable break interrupt (BIE).
<>	157:ff67d9f36b67	4523	* @rmtoll DIER BIE LL_TIM_EnableIT_BRK
<>	157:ff67d9f36b67	4524	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4525	* @retval None
<>	157:ff67d9f36b67	4526	*/
<>	157:ff67d9f36b67	4527	__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4528	{
<>	157:ff67d9f36b67	4529	SET_BIT(TIMx->DIER, TIM_DIER_BIE);
<>	157:ff67d9f36b67	4530	}
<>	157:ff67d9f36b67	4531
<>	157:ff67d9f36b67	4532	/**
<>	157:ff67d9f36b67	4533	* @brief Disable break interrupt (BIE).
<>	157:ff67d9f36b67	4534	* @rmtoll DIER BIE LL_TIM_DisableIT_BRK
<>	157:ff67d9f36b67	4535	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4536	* @retval None
<>	157:ff67d9f36b67	4537	*/
<>	157:ff67d9f36b67	4538	__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4539	{
<>	157:ff67d9f36b67	4540	CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
<>	157:ff67d9f36b67	4541	}
<>	157:ff67d9f36b67	4542
<>	157:ff67d9f36b67	4543	/**
<>	157:ff67d9f36b67	4544	* @brief Indicates whether the break interrupt (BIE) is enabled.
<>	157:ff67d9f36b67	4545	* @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
<>	157:ff67d9f36b67	4546	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4547	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4548	*/
<>	157:ff67d9f36b67	4549	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4550	{
<>	157:ff67d9f36b67	4551	return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
<>	157:ff67d9f36b67	4552	}
<>	157:ff67d9f36b67	4553
<>	157:ff67d9f36b67	4554	/**
<>	157:ff67d9f36b67	4555	* @}
<>	157:ff67d9f36b67	4556	*/
<>	157:ff67d9f36b67	4557
<>	157:ff67d9f36b67	4558	/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
<>	157:ff67d9f36b67	4559	* @{
<>	157:ff67d9f36b67	4560	*/
<>	157:ff67d9f36b67	4561	/**
<>	157:ff67d9f36b67	4562	* @brief Enable update DMA request (UDE).
<>	157:ff67d9f36b67	4563	* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
<>	157:ff67d9f36b67	4564	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4565	* @retval None
<>	157:ff67d9f36b67	4566	*/
<>	157:ff67d9f36b67	4567	__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4568	{
<>	157:ff67d9f36b67	4569	SET_BIT(TIMx->DIER, TIM_DIER_UDE);
<>	157:ff67d9f36b67	4570	}
<>	157:ff67d9f36b67	4571
<>	157:ff67d9f36b67	4572	/**
<>	157:ff67d9f36b67	4573	* @brief Disable update DMA request (UDE).
<>	157:ff67d9f36b67	4574	* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
<>	157:ff67d9f36b67	4575	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4576	* @retval None
<>	157:ff67d9f36b67	4577	*/
<>	157:ff67d9f36b67	4578	__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4579	{
<>	157:ff67d9f36b67	4580	CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
<>	157:ff67d9f36b67	4581	}
<>	157:ff67d9f36b67	4582
<>	157:ff67d9f36b67	4583	/**
<>	157:ff67d9f36b67	4584	* @brief Indicates whether the update DMA request (UDE) is enabled.
<>	157:ff67d9f36b67	4585	* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
<>	157:ff67d9f36b67	4586	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4587	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4588	*/
<>	157:ff67d9f36b67	4589	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4590	{
<>	157:ff67d9f36b67	4591	return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
<>	157:ff67d9f36b67	4592	}
<>	157:ff67d9f36b67	4593
<>	157:ff67d9f36b67	4594	/**
<>	157:ff67d9f36b67	4595	* @brief Enable capture/compare 1 DMA request (CC1DE).
<>	157:ff67d9f36b67	4596	* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
<>	157:ff67d9f36b67	4597	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4598	* @retval None
<>	157:ff67d9f36b67	4599	*/
<>	157:ff67d9f36b67	4600	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4601	{
<>	157:ff67d9f36b67	4602	SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
<>	157:ff67d9f36b67	4603	}
<>	157:ff67d9f36b67	4604
<>	157:ff67d9f36b67	4605	/**
<>	157:ff67d9f36b67	4606	* @brief Disable capture/compare 1 DMA request (CC1DE).
<>	157:ff67d9f36b67	4607	* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
<>	157:ff67d9f36b67	4608	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4609	* @retval None
<>	157:ff67d9f36b67	4610	*/
<>	157:ff67d9f36b67	4611	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4612	{
<>	157:ff67d9f36b67	4613	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
<>	157:ff67d9f36b67	4614	}
<>	157:ff67d9f36b67	4615
<>	157:ff67d9f36b67	4616	/**
<>	157:ff67d9f36b67	4617	* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
<>	157:ff67d9f36b67	4618	* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
<>	157:ff67d9f36b67	4619	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4620	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4621	*/
<>	157:ff67d9f36b67	4622	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4623	{
<>	157:ff67d9f36b67	4624	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
<>	157:ff67d9f36b67	4625	}
<>	157:ff67d9f36b67	4626
<>	157:ff67d9f36b67	4627	/**
<>	157:ff67d9f36b67	4628	* @brief Enable capture/compare 2 DMA request (CC2DE).
<>	157:ff67d9f36b67	4629	* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
<>	157:ff67d9f36b67	4630	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4631	* @retval None
<>	157:ff67d9f36b67	4632	*/
<>	157:ff67d9f36b67	4633	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4634	{
<>	157:ff67d9f36b67	4635	SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
<>	157:ff67d9f36b67	4636	}
<>	157:ff67d9f36b67	4637
<>	157:ff67d9f36b67	4638	/**
<>	157:ff67d9f36b67	4639	* @brief Disable capture/compare 2 DMA request (CC2DE).
<>	157:ff67d9f36b67	4640	* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
<>	157:ff67d9f36b67	4641	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4642	* @retval None
<>	157:ff67d9f36b67	4643	*/
<>	157:ff67d9f36b67	4644	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4645	{
<>	157:ff67d9f36b67	4646	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
<>	157:ff67d9f36b67	4647	}
<>	157:ff67d9f36b67	4648
<>	157:ff67d9f36b67	4649	/**
<>	157:ff67d9f36b67	4650	* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
<>	157:ff67d9f36b67	4651	* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
<>	157:ff67d9f36b67	4652	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4653	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4654	*/
<>	157:ff67d9f36b67	4655	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4656	{
<>	157:ff67d9f36b67	4657	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
<>	157:ff67d9f36b67	4658	}
<>	157:ff67d9f36b67	4659
<>	157:ff67d9f36b67	4660	/**
<>	157:ff67d9f36b67	4661	* @brief Enable capture/compare 3 DMA request (CC3DE).
<>	157:ff67d9f36b67	4662	* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
<>	157:ff67d9f36b67	4663	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4664	* @retval None
<>	157:ff67d9f36b67	4665	*/
<>	157:ff67d9f36b67	4666	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4667	{
<>	157:ff67d9f36b67	4668	SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
<>	157:ff67d9f36b67	4669	}
<>	157:ff67d9f36b67	4670
<>	157:ff67d9f36b67	4671	/**
<>	157:ff67d9f36b67	4672	* @brief Disable capture/compare 3 DMA request (CC3DE).
<>	157:ff67d9f36b67	4673	* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
<>	157:ff67d9f36b67	4674	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4675	* @retval None
<>	157:ff67d9f36b67	4676	*/
<>	157:ff67d9f36b67	4677	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4678	{
<>	157:ff67d9f36b67	4679	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
<>	157:ff67d9f36b67	4680	}
<>	157:ff67d9f36b67	4681
<>	157:ff67d9f36b67	4682	/**
<>	157:ff67d9f36b67	4683	* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
<>	157:ff67d9f36b67	4684	* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
<>	157:ff67d9f36b67	4685	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4686	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4687	*/
<>	157:ff67d9f36b67	4688	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4689	{
<>	157:ff67d9f36b67	4690	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
<>	157:ff67d9f36b67	4691	}
<>	157:ff67d9f36b67	4692
<>	157:ff67d9f36b67	4693	/**
<>	157:ff67d9f36b67	4694	* @brief Enable capture/compare 4 DMA request (CC4DE).
<>	157:ff67d9f36b67	4695	* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
<>	157:ff67d9f36b67	4696	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4697	* @retval None
<>	157:ff67d9f36b67	4698	*/
<>	157:ff67d9f36b67	4699	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4700	{
<>	157:ff67d9f36b67	4701	SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
<>	157:ff67d9f36b67	4702	}
<>	157:ff67d9f36b67	4703
<>	157:ff67d9f36b67	4704	/**
<>	157:ff67d9f36b67	4705	* @brief Disable capture/compare 4 DMA request (CC4DE).
<>	157:ff67d9f36b67	4706	* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
<>	157:ff67d9f36b67	4707	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4708	* @retval None
<>	157:ff67d9f36b67	4709	*/
<>	157:ff67d9f36b67	4710	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4711	{
<>	157:ff67d9f36b67	4712	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
<>	157:ff67d9f36b67	4713	}
<>	157:ff67d9f36b67	4714
<>	157:ff67d9f36b67	4715	/**
<>	157:ff67d9f36b67	4716	* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
<>	157:ff67d9f36b67	4717	* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
<>	157:ff67d9f36b67	4718	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4719	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4720	*/
<>	157:ff67d9f36b67	4721	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4722	{
<>	157:ff67d9f36b67	4723	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
<>	157:ff67d9f36b67	4724	}
<>	157:ff67d9f36b67	4725
<>	157:ff67d9f36b67	4726	/**
<>	157:ff67d9f36b67	4727	* @brief Enable commutation DMA request (COMDE).
<>	157:ff67d9f36b67	4728	* @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
<>	157:ff67d9f36b67	4729	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4730	* @retval None
<>	157:ff67d9f36b67	4731	*/
<>	157:ff67d9f36b67	4732	__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4733	{
<>	157:ff67d9f36b67	4734	SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
<>	157:ff67d9f36b67	4735	}
<>	157:ff67d9f36b67	4736
<>	157:ff67d9f36b67	4737	/**
<>	157:ff67d9f36b67	4738	* @brief Disable commutation DMA request (COMDE).
<>	157:ff67d9f36b67	4739	* @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
<>	157:ff67d9f36b67	4740	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4741	* @retval None
<>	157:ff67d9f36b67	4742	*/
<>	157:ff67d9f36b67	4743	__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4744	{
<>	157:ff67d9f36b67	4745	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
<>	157:ff67d9f36b67	4746	}
<>	157:ff67d9f36b67	4747
<>	157:ff67d9f36b67	4748	/**
<>	157:ff67d9f36b67	4749	* @brief Indicates whether the commutation DMA request (COMDE) is enabled.
<>	157:ff67d9f36b67	4750	* @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
<>	157:ff67d9f36b67	4751	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4752	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4753	*/
<>	157:ff67d9f36b67	4754	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4755	{
<>	157:ff67d9f36b67	4756	return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
<>	157:ff67d9f36b67	4757	}
<>	157:ff67d9f36b67	4758
<>	157:ff67d9f36b67	4759	/**
<>	157:ff67d9f36b67	4760	* @brief Enable trigger interrupt (TDE).
<>	157:ff67d9f36b67	4761	* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
<>	157:ff67d9f36b67	4762	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4763	* @retval None
<>	157:ff67d9f36b67	4764	*/
<>	157:ff67d9f36b67	4765	__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4766	{
<>	157:ff67d9f36b67	4767	SET_BIT(TIMx->DIER, TIM_DIER_TDE);
<>	157:ff67d9f36b67	4768	}
<>	157:ff67d9f36b67	4769
<>	157:ff67d9f36b67	4770	/**
<>	157:ff67d9f36b67	4771	* @brief Disable trigger interrupt (TDE).
<>	157:ff67d9f36b67	4772	* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
<>	157:ff67d9f36b67	4773	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4774	* @retval None
<>	157:ff67d9f36b67	4775	*/
<>	157:ff67d9f36b67	4776	__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4777	{
<>	157:ff67d9f36b67	4778	CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
<>	157:ff67d9f36b67	4779	}
<>	157:ff67d9f36b67	4780
<>	157:ff67d9f36b67	4781	/**
<>	157:ff67d9f36b67	4782	* @brief Indicates whether the trigger interrupt (TDE) is enabled.
<>	157:ff67d9f36b67	4783	* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
<>	157:ff67d9f36b67	4784	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4785	* @retval State of bit (1 or 0).
<>	157:ff67d9f36b67	4786	*/
<>	157:ff67d9f36b67	4787	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4788	{
<>	157:ff67d9f36b67	4789	return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
<>	157:ff67d9f36b67	4790	}
<>	157:ff67d9f36b67	4791
<>	157:ff67d9f36b67	4792	/**
<>	157:ff67d9f36b67	4793	* @}
<>	157:ff67d9f36b67	4794	*/
<>	157:ff67d9f36b67	4795
<>	157:ff67d9f36b67	4796	/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
<>	157:ff67d9f36b67	4797	* @{
<>	157:ff67d9f36b67	4798	*/
<>	157:ff67d9f36b67	4799	/**
<>	157:ff67d9f36b67	4800	* @brief Generate an update event.
<>	157:ff67d9f36b67	4801	* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
<>	157:ff67d9f36b67	4802	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4803	* @retval None
<>	157:ff67d9f36b67	4804	*/
<>	157:ff67d9f36b67	4805	__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4806	{
<>	157:ff67d9f36b67	4807	SET_BIT(TIMx->EGR, TIM_EGR_UG);
<>	157:ff67d9f36b67	4808	}
<>	157:ff67d9f36b67	4809
<>	157:ff67d9f36b67	4810	/**
<>	157:ff67d9f36b67	4811	* @brief Generate Capture/Compare 1 event.
<>	157:ff67d9f36b67	4812	* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
<>	157:ff67d9f36b67	4813	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4814	* @retval None
<>	157:ff67d9f36b67	4815	*/
<>	157:ff67d9f36b67	4816	__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4817	{
<>	157:ff67d9f36b67	4818	SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
<>	157:ff67d9f36b67	4819	}
<>	157:ff67d9f36b67	4820
<>	157:ff67d9f36b67	4821	/**
<>	157:ff67d9f36b67	4822	* @brief Generate Capture/Compare 2 event.
<>	157:ff67d9f36b67	4823	* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
<>	157:ff67d9f36b67	4824	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4825	* @retval None
<>	157:ff67d9f36b67	4826	*/
<>	157:ff67d9f36b67	4827	__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4828	{
<>	157:ff67d9f36b67	4829	SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
<>	157:ff67d9f36b67	4830	}
<>	157:ff67d9f36b67	4831
<>	157:ff67d9f36b67	4832	/**
<>	157:ff67d9f36b67	4833	* @brief Generate Capture/Compare 3 event.
<>	157:ff67d9f36b67	4834	* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
<>	157:ff67d9f36b67	4835	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4836	* @retval None
<>	157:ff67d9f36b67	4837	*/
<>	157:ff67d9f36b67	4838	__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4839	{
<>	157:ff67d9f36b67	4840	SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
<>	157:ff67d9f36b67	4841	}
<>	157:ff67d9f36b67	4842
<>	157:ff67d9f36b67	4843	/**
<>	157:ff67d9f36b67	4844	* @brief Generate Capture/Compare 4 event.
<>	157:ff67d9f36b67	4845	* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
<>	157:ff67d9f36b67	4846	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4847	* @retval None
<>	157:ff67d9f36b67	4848	*/
<>	157:ff67d9f36b67	4849	__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4850	{
<>	157:ff67d9f36b67	4851	SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
<>	157:ff67d9f36b67	4852	}
<>	157:ff67d9f36b67	4853
<>	157:ff67d9f36b67	4854	/**
<>	157:ff67d9f36b67	4855	* @brief Generate commutation event.
<>	157:ff67d9f36b67	4856	* @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
<>	157:ff67d9f36b67	4857	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4858	* @retval None
<>	157:ff67d9f36b67	4859	*/
<>	157:ff67d9f36b67	4860	__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4861	{
<>	157:ff67d9f36b67	4862	SET_BIT(TIMx->EGR, TIM_EGR_COMG);
<>	157:ff67d9f36b67	4863	}
<>	157:ff67d9f36b67	4864
<>	157:ff67d9f36b67	4865	/**
<>	157:ff67d9f36b67	4866	* @brief Generate trigger event.
<>	157:ff67d9f36b67	4867	* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
<>	157:ff67d9f36b67	4868	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4869	* @retval None
<>	157:ff67d9f36b67	4870	*/
<>	157:ff67d9f36b67	4871	__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4872	{
<>	157:ff67d9f36b67	4873	SET_BIT(TIMx->EGR, TIM_EGR_TG);
<>	157:ff67d9f36b67	4874	}
<>	157:ff67d9f36b67	4875
<>	157:ff67d9f36b67	4876	/**
<>	157:ff67d9f36b67	4877	* @brief Generate break event.
<>	157:ff67d9f36b67	4878	* @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
<>	157:ff67d9f36b67	4879	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4880	* @retval None
<>	157:ff67d9f36b67	4881	*/
<>	157:ff67d9f36b67	4882	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4883	{
<>	157:ff67d9f36b67	4884	SET_BIT(TIMx->EGR, TIM_EGR_BG);
<>	157:ff67d9f36b67	4885	}
<>	157:ff67d9f36b67	4886
<>	157:ff67d9f36b67	4887	#if defined(TIM_EGR_B2G)
<>	157:ff67d9f36b67	4888	/**
<>	157:ff67d9f36b67	4889	* @brief Generate break 2 event.
<>	157:ff67d9f36b67	4890	* @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
<>	157:ff67d9f36b67	4891	* @param TIMx Timer instance
<>	157:ff67d9f36b67	4892	* @retval None
<>	157:ff67d9f36b67	4893	*/
<>	157:ff67d9f36b67	4894	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
<>	157:ff67d9f36b67	4895	{
<>	157:ff67d9f36b67	4896	SET_BIT(TIMx->EGR, TIM_EGR_B2G);
<>	157:ff67d9f36b67	4897	}
<>	157:ff67d9f36b67	4898
<>	157:ff67d9f36b67	4899	#endif /* TIM_EGR_B2G */
<>	157:ff67d9f36b67	4900	/**
<>	157:ff67d9f36b67	4901	* @}
<>	157:ff67d9f36b67	4902	*/
<>	157:ff67d9f36b67	4903
<>	157:ff67d9f36b67	4904	#if defined(USE_FULL_LL_DRIVER)
<>	157:ff67d9f36b67	4905	/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
<>	157:ff67d9f36b67	4906	* @{
<>	157:ff67d9f36b67	4907	*/
<>	157:ff67d9f36b67	4908
<>	157:ff67d9f36b67	4909	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
<>	157:ff67d9f36b67	4910	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
<>	157:ff67d9f36b67	4911	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct);
<>	157:ff67d9f36b67	4912	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
<>	157:ff67d9f36b67	4913	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct);
<>	157:ff67d9f36b67	4914	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
<>	157:ff67d9f36b67	4915	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct);
<>	157:ff67d9f36b67	4916	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
<>	157:ff67d9f36b67	4917	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct);
<>	157:ff67d9f36b67	4918	void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
<>	157:ff67d9f36b67	4919	ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef TIMx, LL_TIM_HALLSENSOR_InitTypeDef TIM_HallSensorInitStruct);
<>	157:ff67d9f36b67	4920	void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
<>	157:ff67d9f36b67	4921	ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef TIMx, LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct);
<>	157:ff67d9f36b67	4922	/**
<>	157:ff67d9f36b67	4923	* @}
<>	157:ff67d9f36b67	4924	*/
<>	157:ff67d9f36b67	4925	#endif /* USE_FULL_LL_DRIVER */
<>	157:ff67d9f36b67	4926
<>	157:ff67d9f36b67	4927	/**
<>	157:ff67d9f36b67	4928	* @}
<>	157:ff67d9f36b67	4929	*/
<>	157:ff67d9f36b67	4930
<>	157:ff67d9f36b67	4931	/**
<>	157:ff67d9f36b67	4932	* @}
<>	157:ff67d9f36b67	4933	*/
<>	157:ff67d9f36b67	4934
<>	157:ff67d9f36b67	4935	#endif /* TIM1 \|\| TIM2 \|\| TIM3 \|\| TIM4 \|\| TIM5 \|\| TIM6 \|\| TIM7 \|\| TIM8 \|\| TIM12 \|\| TIM13 \|\| TIM14 \|\| TIM15 \|\| TIM16 \|\| TIM17 \|\| TIM18 \|\| TIM19 \|\| TIM20 */
<>	157:ff67d9f36b67	4936
<>	157:ff67d9f36b67	4937	/**
<>	157:ff67d9f36b67	4938	* @}
<>	157:ff67d9f36b67	4939	*/
<>	157:ff67d9f36b67	4940
<>	157:ff67d9f36b67	4941	#ifdef __cplusplus
<>	157:ff67d9f36b67	4942	}
<>	157:ff67d9f36b67	4943	#endif
<>	157:ff67d9f36b67	4944
<>	157:ff67d9f36b67	4945	#endif /* __STM32F3xx_LL_TIM_H */
<>	157:ff67d9f36b67	4946	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	08 Mar 2017
Imports:	12
Forks:	0
Commits:	165
Dependents:	3
Dependencies:	0
Followers:	5

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Greg Steiert

Jesse Marroquin

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targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_tim.h@164:2e7515f8c45d, 2017-03-24 (annotated)

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targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_tim.h@164:2e7515f8c45d, 2017-03-24 (annotated)

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