Greg Steiert / maxim-dev

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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_ll_i2c.c@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_ll_i2c.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.5.1
<> 144:ef7eb2e8f9f7 6 * @date 31-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief I2C LL module driver.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37 #if defined(USE_FULL_LL_DRIVER)
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 40 #include "stm32l4xx_ll_i2c.h"
<> 144:ef7eb2e8f9f7 41 #include "stm32l4xx_ll_bus.h"
<> 144:ef7eb2e8f9f7 42 #ifdef USE_FULL_ASSERT
<> 144:ef7eb2e8f9f7 43 #include "stm32_assert.h"
<> 144:ef7eb2e8f9f7 44 #else
<> 144:ef7eb2e8f9f7 45 #define assert_param(expr) ((void)0U)
<> 144:ef7eb2e8f9f7 46 #endif
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 /** @addtogroup STM32L4xx_LL_Driver
<> 144:ef7eb2e8f9f7 49 * @{
<> 144:ef7eb2e8f9f7 50 */
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 #if defined (I2C1) || defined (I2C2) || defined (I2C3)
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /** @defgroup I2C_LL I2C
<> 144:ef7eb2e8f9f7 55 * @{
<> 144:ef7eb2e8f9f7 56 */
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 60 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 61 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 62 /** @addtogroup I2C_LL_Private_Macros
<> 144:ef7eb2e8f9f7 63 * @{
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 #define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__) (((__VALUE__) == LL_I2C_MODE_I2C) || \
<> 144:ef7eb2e8f9f7 67 ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST) || \
<> 144:ef7eb2e8f9f7 68 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
<> 144:ef7eb2e8f9f7 69 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 #define IS_LL_I2C_ANALOG_FILTER(__VALUE__) (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
<> 144:ef7eb2e8f9f7 72 ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 #define IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU)
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 #define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= (uint32_t)0x000003FFU)
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 #define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_I2C_ACK) || \
<> 144:ef7eb2e8f9f7 79 ((__VALUE__) == LL_I2C_NACK))
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 #define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__) (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
<> 144:ef7eb2e8f9f7 82 ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
<> 144:ef7eb2e8f9f7 83 /**
<> 144:ef7eb2e8f9f7 84 * @}
<> 144:ef7eb2e8f9f7 85 */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 90 /** @addtogroup I2C_LL_Exported_Functions
<> 144:ef7eb2e8f9f7 91 * @{
<> 144:ef7eb2e8f9f7 92 */
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /** @addtogroup I2C_LL_EF_Init
<> 144:ef7eb2e8f9f7 95 * @{
<> 144:ef7eb2e8f9f7 96 */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /**
<> 144:ef7eb2e8f9f7 99 * @brief De-initialize the I2C registers to their default reset values.
<> 144:ef7eb2e8f9f7 100 * @param I2Cx I2C Instance.
<> 144:ef7eb2e8f9f7 101 * @retval An ErrorStatus enumeration value:
<> 144:ef7eb2e8f9f7 102 * - SUCCESS: I2C registers are de-initialized
<> 144:ef7eb2e8f9f7 103 * - ERROR: I2C registers are not de-initialized
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105 uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx)
<> 144:ef7eb2e8f9f7 106 {
<> 144:ef7eb2e8f9f7 107 ErrorStatus status = SUCCESS;
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /* Check the I2C Instance I2Cx */
<> 144:ef7eb2e8f9f7 110 assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 if (I2Cx == I2C1)
<> 144:ef7eb2e8f9f7 113 {
<> 144:ef7eb2e8f9f7 114 /* Force reset of I2C clock */
<> 144:ef7eb2e8f9f7 115 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 /* Release reset of I2C clock */
<> 144:ef7eb2e8f9f7 118 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
<> 144:ef7eb2e8f9f7 119 }
<> 144:ef7eb2e8f9f7 120 #if defined(I2C2)
<> 144:ef7eb2e8f9f7 121 else if (I2Cx == I2C2)
<> 144:ef7eb2e8f9f7 122 {
<> 144:ef7eb2e8f9f7 123 /* Force reset of I2C clock */
<> 144:ef7eb2e8f9f7 124 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /* Release reset of I2C clock */
<> 144:ef7eb2e8f9f7 127 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 }
<> 144:ef7eb2e8f9f7 130 #endif
<> 144:ef7eb2e8f9f7 131 else if (I2Cx == I2C3)
<> 144:ef7eb2e8f9f7 132 {
<> 144:ef7eb2e8f9f7 133 /* Force reset of I2C clock */
<> 144:ef7eb2e8f9f7 134 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3);
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 /* Release reset of I2C clock */
<> 144:ef7eb2e8f9f7 137 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3);
<> 144:ef7eb2e8f9f7 138 }
<> 144:ef7eb2e8f9f7 139 else
<> 144:ef7eb2e8f9f7 140 {
<> 144:ef7eb2e8f9f7 141 status = ERROR;
<> 144:ef7eb2e8f9f7 142 }
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 return status;
<> 144:ef7eb2e8f9f7 145 }
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /**
<> 144:ef7eb2e8f9f7 148 * @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
<> 144:ef7eb2e8f9f7 149 * @param I2Cx I2C Instance.
<> 144:ef7eb2e8f9f7 150 * @param I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
<> 144:ef7eb2e8f9f7 151 * @retval An ErrorStatus enumeration value:
<> 144:ef7eb2e8f9f7 152 * - SUCCESS: I2C registers are initialized
<> 144:ef7eb2e8f9f7 153 * - ERROR: Not applicable
<> 144:ef7eb2e8f9f7 154 */
<> 144:ef7eb2e8f9f7 155 uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
<> 144:ef7eb2e8f9f7 156 {
<> 144:ef7eb2e8f9f7 157 /* Check the I2C Instance I2Cx */
<> 144:ef7eb2e8f9f7 158 assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /* Check the I2C parameters from I2C_InitStruct */
<> 144:ef7eb2e8f9f7 161 assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
<> 144:ef7eb2e8f9f7 162 assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter));
<> 144:ef7eb2e8f9f7 163 assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter));
<> 144:ef7eb2e8f9f7 164 assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
<> 144:ef7eb2e8f9f7 165 assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
<> 144:ef7eb2e8f9f7 166 assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /* Disable the selected I2Cx Peripheral */
<> 144:ef7eb2e8f9f7 169 LL_I2C_Disable(I2Cx);
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /*---------------------------- I2Cx CR1 Configuration ------------------------
<> 144:ef7eb2e8f9f7 172 * Configure the analog and digital noise filters with parameters :
<> 144:ef7eb2e8f9f7 173 * - AnalogFilter: I2C_CR1_ANFOFF bit
<> 144:ef7eb2e8f9f7 174 * - DigitalFilter: I2C_CR1_DNF[3:0] bits
<> 144:ef7eb2e8f9f7 175 */
<> 144:ef7eb2e8f9f7 176 LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter);
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /*---------------------------- I2Cx TIMINGR Configuration --------------------
<> 144:ef7eb2e8f9f7 179 * Configure the SDA setup, hold time and the SCL high, low period with parameter :
<> 144:ef7eb2e8f9f7 180 * - Timing: I2C_TIMINGR_PRESC[3:0], I2C_TIMINGR_SCLDEL[3:0], I2C_TIMINGR_SDADEL[3:0],
<> 144:ef7eb2e8f9f7 181 * I2C_TIMINGR_SCLH[7:0] and I2C_TIMINGR_SCLL[7:0] bits
<> 144:ef7eb2e8f9f7 182 */
<> 144:ef7eb2e8f9f7 183 LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing);
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /* Enable the selected I2Cx Peripheral */
<> 144:ef7eb2e8f9f7 186 LL_I2C_Enable(I2Cx);
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /*---------------------------- I2Cx OAR1 Configuration -----------------------
<> 144:ef7eb2e8f9f7 189 * Disable, Configure and Enable I2Cx device own address 1 with parameters :
<> 144:ef7eb2e8f9f7 190 * - OwnAddress1: I2C_OAR1_OA1[9:0] bits
<> 144:ef7eb2e8f9f7 191 * - OwnAddrSize: I2C_OAR1_OA1MODE bit
<> 144:ef7eb2e8f9f7 192 */
<> 144:ef7eb2e8f9f7 193 LL_I2C_DisableOwnAddress1(I2Cx);
<> 144:ef7eb2e8f9f7 194 LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
<> 144:ef7eb2e8f9f7 195 LL_I2C_EnableOwnAddress1(I2Cx);
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /*---------------------------- I2Cx MODE Configuration -----------------------
<> 144:ef7eb2e8f9f7 198 * Configure I2Cx peripheral mode with parameter :
<> 144:ef7eb2e8f9f7 199 * - PeripheralMode: I2C_CR1_SMBDEN and I2C_CR1_SMBHEN bits
<> 144:ef7eb2e8f9f7 200 */
<> 144:ef7eb2e8f9f7 201 LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /*---------------------------- I2Cx CR2 Configuration ------------------------
<> 144:ef7eb2e8f9f7 204 * Configure the ACKnowledge or Non ACKnowledge condition
<> 144:ef7eb2e8f9f7 205 * after the address receive match code or next received byte with parameter :
<> 144:ef7eb2e8f9f7 206 * - TypeAcknowledge: I2C_CR2_NACK bit
<> 144:ef7eb2e8f9f7 207 */
<> 144:ef7eb2e8f9f7 208 LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 return SUCCESS;
<> 144:ef7eb2e8f9f7 211 }
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /**
<> 144:ef7eb2e8f9f7 214 * @brief Set each @ref LL_I2C_InitTypeDef field to default value.
<> 144:ef7eb2e8f9f7 215 * @param I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
<> 144:ef7eb2e8f9f7 216 * @retval None
<> 144:ef7eb2e8f9f7 217 */
<> 144:ef7eb2e8f9f7 218 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
<> 144:ef7eb2e8f9f7 219 {
<> 144:ef7eb2e8f9f7 220 /* Set I2C_InitStruct fields to default values */
<> 144:ef7eb2e8f9f7 221 I2C_InitStruct->PeripheralMode = LL_I2C_MODE_I2C;
<> 144:ef7eb2e8f9f7 222 I2C_InitStruct->Timing = 0U;
<> 144:ef7eb2e8f9f7 223 I2C_InitStruct->AnalogFilter = LL_I2C_ANALOGFILTER_ENABLE;
<> 144:ef7eb2e8f9f7 224 I2C_InitStruct->DigitalFilter = 0U;
<> 144:ef7eb2e8f9f7 225 I2C_InitStruct->OwnAddress1 = 0U;
<> 144:ef7eb2e8f9f7 226 I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
<> 144:ef7eb2e8f9f7 227 I2C_InitStruct->OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT;
<> 144:ef7eb2e8f9f7 228 }
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /**
<> 144:ef7eb2e8f9f7 231 * @}
<> 144:ef7eb2e8f9f7 232 */
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 /**
<> 144:ef7eb2e8f9f7 235 * @}
<> 144:ef7eb2e8f9f7 236 */
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /**
<> 144:ef7eb2e8f9f7 239 * @}
<> 144:ef7eb2e8f9f7 240 */
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 #endif /* I2C1 || I2C2 || I2C3 */
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /**
<> 144:ef7eb2e8f9f7 245 * @}
<> 144:ef7eb2e8f9f7 246 */
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 #endif /* USE_FULL_LL_DRIVER */
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/