Suad Suljic / Mbed OS KOPIRANO_cell_locker

commit

Dependencies:   MPU6050_SIM5320_TEST

Fork of MPU_SDCARD by Suad Suljic

MFRC522.cpp@1:75966605a6a3, 2017-11-10 (annotated)

Committer:
suads
Date:
Fri Nov 10 15:35:26 2017 +0000
Revision:
1:75966605a6a3
mbed cli

Who changed what in which revision?

UserRevisionLine numberNew contents of line
suads 1:75966605a6a3 1 /*
suads 1:75966605a6a3 2 * MFRC522.cpp - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT.
suads 1:75966605a6a3 3 * _Please_ see the comments in MFRC522.h - they give useful hints and background.
suads 1:75966605a6a3 4 * Released into the public domain.
suads 1:75966605a6a3 5 */
suads 1:75966605a6a3 6
suads 1:75966605a6a3 7 #include "MFRC522.h"
suads 1:75966605a6a3 8
suads 1:75966605a6a3 9 static const char* const _TypeNamePICC[] =
suads 1:75966605a6a3 10 {
suads 1:75966605a6a3 11 "Unknown type",
suads 1:75966605a6a3 12 "PICC compliant with ISO/IEC 14443-4",
suads 1:75966605a6a3 13 "PICC compliant with ISO/IEC 18092 (NFC)",
suads 1:75966605a6a3 14 "MIFARE Mini, 320 bytes",
suads 1:75966605a6a3 15 "MIFARE 1KB",
suads 1:75966605a6a3 16 "MIFARE 4KB",
suads 1:75966605a6a3 17 "MIFARE Ultralight or Ultralight C",
suads 1:75966605a6a3 18 "MIFARE Plus",
suads 1:75966605a6a3 19 "MIFARE TNP3XXX",
suads 1:75966605a6a3 20
suads 1:75966605a6a3 21 /* not complete UID */
suads 1:75966605a6a3 22 "SAK indicates UID is not complete"
suads 1:75966605a6a3 23 };
suads 1:75966605a6a3 24
suads 1:75966605a6a3 25 static const char* const _ErrorMessage[] =
suads 1:75966605a6a3 26 {
suads 1:75966605a6a3 27 "Unknown error",
suads 1:75966605a6a3 28 "Success",
suads 1:75966605a6a3 29 "Error in communication",
suads 1:75966605a6a3 30 "Collision detected",
suads 1:75966605a6a3 31 "Timeout in communication",
suads 1:75966605a6a3 32 "A buffer is not big enough",
suads 1:75966605a6a3 33 "Internal error in the code, should not happen",
suads 1:75966605a6a3 34 "Invalid argument",
suads 1:75966605a6a3 35 "The CRC_A does not match",
suads 1:75966605a6a3 36 "A MIFARE PICC responded with NAK"
suads 1:75966605a6a3 37 };
suads 1:75966605a6a3 38
suads 1:75966605a6a3 39 #define MFRC522_MaxPICCs (sizeof(_TypeNamePICC)/sizeof(_TypeNamePICC[0]))
suads 1:75966605a6a3 40 #define MFRC522_MaxError (sizeof(_ErrorMessage)/sizeof(_ErrorMessage[0]))
suads 1:75966605a6a3 41
suads 1:75966605a6a3 42 /////////////////////////////////////////////////////////////////////////////////////
suads 1:75966605a6a3 43 // Functions for setting up the driver
suads 1:75966605a6a3 44 /////////////////////////////////////////////////////////////////////////////////////
suads 1:75966605a6a3 45
suads 1:75966605a6a3 46 /**
suads 1:75966605a6a3 47 * Constructor.
suads 1:75966605a6a3 48 * Prepares the output pins.
suads 1:75966605a6a3 49 */
suads 1:75966605a6a3 50 MFRC522::MFRC522(PinName mosi,
suads 1:75966605a6a3 51 PinName miso,
suads 1:75966605a6a3 52 PinName sclk,
suads 1:75966605a6a3 53 PinName cs,
suads 1:75966605a6a3 54 PinName reset) : m_SPI(mosi, miso, sclk), m_CS(cs), m_RESET(reset)
suads 1:75966605a6a3 55 {
suads 1:75966605a6a3 56 /* Configure SPI bus */
suads 1:75966605a6a3 57 m_SPI.format(8, 0);
suads 1:75966605a6a3 58 m_SPI.frequency(8000000);
suads 1:75966605a6a3 59
suads 1:75966605a6a3 60 /* Release SPI-CS pin */
suads 1:75966605a6a3 61 m_CS = 1;
suads 1:75966605a6a3 62
suads 1:75966605a6a3 63 /* Release RESET pin */
suads 1:75966605a6a3 64 m_RESET = 1;
suads 1:75966605a6a3 65 } // End constructor
suads 1:75966605a6a3 66
suads 1:75966605a6a3 67
suads 1:75966605a6a3 68 /**
suads 1:75966605a6a3 69 * Destructor.
suads 1:75966605a6a3 70 */
suads 1:75966605a6a3 71 MFRC522::~MFRC522()
suads 1:75966605a6a3 72 {
suads 1:75966605a6a3 73
suads 1:75966605a6a3 74 }
suads 1:75966605a6a3 75
suads 1:75966605a6a3 76
suads 1:75966605a6a3 77 /////////////////////////////////////////////////////////////////////////////////////
suads 1:75966605a6a3 78 // Basic interface functions for communicating with the MFRC522
suads 1:75966605a6a3 79 /////////////////////////////////////////////////////////////////////////////////////
suads 1:75966605a6a3 80
suads 1:75966605a6a3 81 /**
suads 1:75966605a6a3 82 * Writes a byte to the specified register in the MFRC522 chip.
suads 1:75966605a6a3 83 * The interface is described in the datasheet section 8.1.2.
suads 1:75966605a6a3 84 */
suads 1:75966605a6a3 85 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t value)
suads 1:75966605a6a3 86 {
suads 1:75966605a6a3 87 m_CS = 0; /* Select SPI Chip MFRC522 */
suads 1:75966605a6a3 88
suads 1:75966605a6a3 89 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
suads 1:75966605a6a3 90 (void) m_SPI.write(reg & 0x7E);
suads 1:75966605a6a3 91 (void) m_SPI.write(value);
suads 1:75966605a6a3 92
suads 1:75966605a6a3 93 m_CS = 1; /* Release SPI Chip MFRC522 */
suads 1:75966605a6a3 94 } // End PCD_WriteRegister()
suads 1:75966605a6a3 95
suads 1:75966605a6a3 96 /**
suads 1:75966605a6a3 97 * Writes a number of bytes to the specified register in the MFRC522 chip.
suads 1:75966605a6a3 98 * The interface is described in the datasheet section 8.1.2.
suads 1:75966605a6a3 99 */
suads 1:75966605a6a3 100 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t count, uint8_t *values)
suads 1:75966605a6a3 101 {
suads 1:75966605a6a3 102 m_CS = 0; /* Select SPI Chip MFRC522 */
suads 1:75966605a6a3 103
suads 1:75966605a6a3 104 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
suads 1:75966605a6a3 105 (void) m_SPI.write(reg & 0x7E);
suads 1:75966605a6a3 106 for (uint8_t index = 0; index < count; index++)
suads 1:75966605a6a3 107 {
suads 1:75966605a6a3 108 (void) m_SPI.write(values[index]);
suads 1:75966605a6a3 109 }
suads 1:75966605a6a3 110
suads 1:75966605a6a3 111 m_CS = 1; /* Release SPI Chip MFRC522 */
suads 1:75966605a6a3 112 } // End PCD_WriteRegister()
suads 1:75966605a6a3 113
suads 1:75966605a6a3 114 /**
suads 1:75966605a6a3 115 * Reads a byte from the specified register in the MFRC522 chip.
suads 1:75966605a6a3 116 * The interface is described in the datasheet section 8.1.2.
suads 1:75966605a6a3 117 */
suads 1:75966605a6a3 118 uint8_t MFRC522::PCD_ReadRegister(uint8_t reg)
suads 1:75966605a6a3 119 {
suads 1:75966605a6a3 120 uint8_t value;
suads 1:75966605a6a3 121 m_CS = 0; /* Select SPI Chip MFRC522 */
suads 1:75966605a6a3 122
suads 1:75966605a6a3 123 // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
suads 1:75966605a6a3 124 (void) m_SPI.write(0x80 | reg);
suads 1:75966605a6a3 125
suads 1:75966605a6a3 126 // Read the value back. Send 0 to stop reading.
suads 1:75966605a6a3 127 value = m_SPI.write(0);
suads 1:75966605a6a3 128
suads 1:75966605a6a3 129 m_CS = 1; /* Release SPI Chip MFRC522 */
suads 1:75966605a6a3 130
suads 1:75966605a6a3 131 return value;
suads 1:75966605a6a3 132 } // End PCD_ReadRegister()
suads 1:75966605a6a3 133
suads 1:75966605a6a3 134 /**
suads 1:75966605a6a3 135 * Reads a number of bytes from the specified register in the MFRC522 chip.
suads 1:75966605a6a3 136 * The interface is described in the datasheet section 8.1.2.
suads 1:75966605a6a3 137 */
suads 1:75966605a6a3 138 void MFRC522::PCD_ReadRegister(uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign)
suads 1:75966605a6a3 139 {
suads 1:75966605a6a3 140 if (count == 0) { return; }
suads 1:75966605a6a3 141
suads 1:75966605a6a3 142 uint8_t address = 0x80 | reg; // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
suads 1:75966605a6a3 143 uint8_t index = 0; // Index in values array.
suads 1:75966605a6a3 144
suads 1:75966605a6a3 145 m_CS = 0; /* Select SPI Chip MFRC522 */
suads 1:75966605a6a3 146 count--; // One read is performed outside of the loop
suads 1:75966605a6a3 147 (void) m_SPI.write(address); // Tell MFRC522 which address we want to read
suads 1:75966605a6a3 148
suads 1:75966605a6a3 149 while (index < count)
suads 1:75966605a6a3 150 {
suads 1:75966605a6a3 151 if ((index == 0) && rxAlign) // Only update bit positions rxAlign..7 in values[0]
suads 1:75966605a6a3 152 {
suads 1:75966605a6a3 153 // Create bit mask for bit positions rxAlign..7
suads 1:75966605a6a3 154 uint8_t mask = 0;
suads 1:75966605a6a3 155 for (uint8_t i = rxAlign; i <= 7; i++)
suads 1:75966605a6a3 156 {
suads 1:75966605a6a3 157 mask |= (1 << i);
suads 1:75966605a6a3 158 }
suads 1:75966605a6a3 159
suads 1:75966605a6a3 160 // Read value and tell that we want to read the same address again.
suads 1:75966605a6a3 161 uint8_t value = m_SPI.write(address);
suads 1:75966605a6a3 162
suads 1:75966605a6a3 163 // Apply mask to both current value of values[0] and the new data in value.
suads 1:75966605a6a3 164 values[0] = (values[index] & ~mask) | (value & mask);
suads 1:75966605a6a3 165 }
suads 1:75966605a6a3 166 else
suads 1:75966605a6a3 167 {
suads 1:75966605a6a3 168 // Read value and tell that we want to read the same address again.
suads 1:75966605a6a3 169 values[index] = m_SPI.write(address);
suads 1:75966605a6a3 170 }
suads 1:75966605a6a3 171
suads 1:75966605a6a3 172 index++;
suads 1:75966605a6a3 173 }
suads 1:75966605a6a3 174
suads 1:75966605a6a3 175 values[index] = m_SPI.write(0); // Read the final byte. Send 0 to stop reading.
suads 1:75966605a6a3 176
suads 1:75966605a6a3 177 m_CS = 1; /* Release SPI Chip MFRC522 */
suads 1:75966605a6a3 178 } // End PCD_ReadRegister()
suads 1:75966605a6a3 179
suads 1:75966605a6a3 180 /**
suads 1:75966605a6a3 181 * Sets the bits given in mask in register reg.
suads 1:75966605a6a3 182 */
suads 1:75966605a6a3 183 void MFRC522::PCD_SetRegisterBits(uint8_t reg, uint8_t mask)
suads 1:75966605a6a3 184 {
suads 1:75966605a6a3 185 uint8_t tmp = PCD_ReadRegister(reg);
suads 1:75966605a6a3 186 PCD_WriteRegister(reg, tmp | mask); // set bit mask
suads 1:75966605a6a3 187 } // End PCD_SetRegisterBitMask()
suads 1:75966605a6a3 188
suads 1:75966605a6a3 189 /**
suads 1:75966605a6a3 190 * Clears the bits given in mask from register reg.
suads 1:75966605a6a3 191 */
suads 1:75966605a6a3 192 void MFRC522::PCD_ClrRegisterBits(uint8_t reg, uint8_t mask)
suads 1:75966605a6a3 193 {
suads 1:75966605a6a3 194 uint8_t tmp = PCD_ReadRegister(reg);
suads 1:75966605a6a3 195 PCD_WriteRegister(reg, tmp & (~mask)); // clear bit mask
suads 1:75966605a6a3 196 } // End PCD_ClearRegisterBitMask()
suads 1:75966605a6a3 197
suads 1:75966605a6a3 198
suads 1:75966605a6a3 199 /**
suads 1:75966605a6a3 200 * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
suads 1:75966605a6a3 201 */
suads 1:75966605a6a3 202 uint8_t MFRC522::PCD_CalculateCRC(uint8_t *data, uint8_t length, uint8_t *result)
suads 1:75966605a6a3 203 {
suads 1:75966605a6a3 204 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
suads 1:75966605a6a3 205 PCD_WriteRegister(DivIrqReg, 0x04); // Clear the CRCIRq interrupt request bit
suads 1:75966605a6a3 206 PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
suads 1:75966605a6a3 207 PCD_WriteRegister(FIFODataReg, length, data); // Write data to the FIFO
suads 1:75966605a6a3 208 PCD_WriteRegister(CommandReg, PCD_CalcCRC); // Start the calculation
suads 1:75966605a6a3 209
suads 1:75966605a6a3 210 // Wait for the CRC calculation to complete. Each iteration of the while-loop takes 17.73us.
suads 1:75966605a6a3 211 uint16_t i = 5000;
suads 1:75966605a6a3 212 uint8_t n;
suads 1:75966605a6a3 213 while (1)
suads 1:75966605a6a3 214 {
suads 1:75966605a6a3 215 n = PCD_ReadRegister(DivIrqReg); // DivIrqReg[7..0] bits are: Set2 reserved reserved MfinActIRq reserved CRCIRq reserved reserved
suads 1:75966605a6a3 216 if (n & 0x04)
suads 1:75966605a6a3 217 {
suads 1:75966605a6a3 218 // CRCIRq bit set - calculation done
suads 1:75966605a6a3 219 break;
suads 1:75966605a6a3 220 }
suads 1:75966605a6a3 221
suads 1:75966605a6a3 222 if (--i == 0)
suads 1:75966605a6a3 223 {
suads 1:75966605a6a3 224 // The emergency break. We will eventually terminate on this one after 89ms.
suads 1:75966605a6a3 225 // Communication with the MFRC522 might be down.
suads 1:75966605a6a3 226 return STATUS_TIMEOUT;
suads 1:75966605a6a3 227 }
suads 1:75966605a6a3 228 }
suads 1:75966605a6a3 229
suads 1:75966605a6a3 230 // Stop calculating CRC for new content in the FIFO.
suads 1:75966605a6a3 231 PCD_WriteRegister(CommandReg, PCD_Idle);
suads 1:75966605a6a3 232
suads 1:75966605a6a3 233 // Transfer the result from the registers to the result buffer
suads 1:75966605a6a3 234 result[0] = PCD_ReadRegister(CRCResultRegL);
suads 1:75966605a6a3 235 result[1] = PCD_ReadRegister(CRCResultRegH);
suads 1:75966605a6a3 236 return STATUS_OK;
suads 1:75966605a6a3 237 } // End PCD_CalculateCRC()
suads 1:75966605a6a3 238
suads 1:75966605a6a3 239
suads 1:75966605a6a3 240 /////////////////////////////////////////////////////////////////////////////////////
suads 1:75966605a6a3 241 // Functions for manipulating the MFRC522
suads 1:75966605a6a3 242 /////////////////////////////////////////////////////////////////////////////////////
suads 1:75966605a6a3 243
suads 1:75966605a6a3 244 /**
suads 1:75966605a6a3 245 * Initializes the MFRC522 chip.
suads 1:75966605a6a3 246 */
suads 1:75966605a6a3 247 void MFRC522::PCD_Init()
suads 1:75966605a6a3 248 {
suads 1:75966605a6a3 249 /* Reset MFRC522 */
suads 1:75966605a6a3 250 m_RESET = 0;
suads 1:75966605a6a3 251 wait_ms(10);
suads 1:75966605a6a3 252 m_RESET = 1;
suads 1:75966605a6a3 253
suads 1:75966605a6a3 254 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms.
suads 1:75966605a6a3 255 wait_ms(50);
suads 1:75966605a6a3 256
suads 1:75966605a6a3 257 // When communicating with a PICC we need a timeout if something goes wrong.
suads 1:75966605a6a3 258 // f_timer = 13.56 MHz / (2*TPreScaler+1) where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo].
suads 1:75966605a6a3 259 // TPrescaler_Hi are the four low bits in TModeReg. TPrescaler_Lo is TPrescalerReg.
suads 1:75966605a6a3 260 PCD_WriteRegister(TModeReg, 0x80); // TAuto=1; timer starts automatically at the end of the transmission in all communication modes at all speeds
suads 1:75966605a6a3 261 PCD_WriteRegister(TPrescalerReg, 0xA9); // TPreScaler = TModeReg[3..0]:TPrescalerReg, ie 0x0A9 = 169 => f_timer=40kHz, ie a timer period of 25us.
suads 1:75966605a6a3 262 PCD_WriteRegister(TReloadRegH, 0x03); // Reload timer with 0x3E8 = 1000, ie 25ms before timeout.
suads 1:75966605a6a3 263 PCD_WriteRegister(TReloadRegL, 0xE8);
suads 1:75966605a6a3 264
suads 1:75966605a6a3 265 PCD_WriteRegister(TxASKReg, 0x40); // Default 0x00. Force a 100 % ASK modulation independent of the ModGsPReg register setting
suads 1:75966605a6a3 266 PCD_WriteRegister(ModeReg, 0x3D); // Default 0x3F. Set the preset value for the CRC coprocessor for the CalcCRC command to 0x6363 (ISO 14443-3 part 6.2.4)
suads 1:75966605a6a3 267
suads 1:75966605a6a3 268 PCD_WriteRegister(RFCfgReg, (0x07<<4)); // Set Rx Gain to max
suads 1:75966605a6a3 269
suads 1:75966605a6a3 270 PCD_AntennaOn(); // Enable the antenna driver pins TX1 and TX2 (they were disabled by the reset)
suads 1:75966605a6a3 271 } // End PCD_Init()
suads 1:75966605a6a3 272
suads 1:75966605a6a3 273 /**
suads 1:75966605a6a3 274 * Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
suads 1:75966605a6a3 275 */
suads 1:75966605a6a3 276 void MFRC522::PCD_Reset()
suads 1:75966605a6a3 277 {
suads 1:75966605a6a3 278 PCD_WriteRegister(CommandReg, PCD_SoftReset); // Issue the SoftReset command.
suads 1:75966605a6a3 279 // The datasheet does not mention how long the SoftRest command takes to complete.
suads 1:75966605a6a3 280 // But the MFRC522 might have been in soft power-down mode (triggered by bit 4 of CommandReg)
suads 1:75966605a6a3 281 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms.
suads 1:75966605a6a3 282 wait_ms(50);
suads 1:75966605a6a3 283
suads 1:75966605a6a3 284 // Wait for the PowerDown bit in CommandReg to be cleared
suads 1:75966605a6a3 285 while (PCD_ReadRegister(CommandReg) & (1<<4))
suads 1:75966605a6a3 286 {
suads 1:75966605a6a3 287 // PCD still restarting - unlikely after waiting 50ms, but better safe than sorry.
suads 1:75966605a6a3 288 }
suads 1:75966605a6a3 289 } // End PCD_Reset()
suads 1:75966605a6a3 290
suads 1:75966605a6a3 291 /**
suads 1:75966605a6a3 292 * Turns the antenna on by enabling pins TX1 and TX2.
suads 1:75966605a6a3 293 * After a reset these pins disabled.
suads 1:75966605a6a3 294 */
suads 1:75966605a6a3 295 void MFRC522::PCD_AntennaOn()
suads 1:75966605a6a3 296 {
suads 1:75966605a6a3 297 uint8_t value = PCD_ReadRegister(TxControlReg);
suads 1:75966605a6a3 298 if ((value & 0x03) != 0x03)
suads 1:75966605a6a3 299 {
suads 1:75966605a6a3 300 PCD_WriteRegister(TxControlReg, value | 0x03);
suads 1:75966605a6a3 301 }
suads 1:75966605a6a3 302 } // End PCD_AntennaOn()
suads 1:75966605a6a3 303
suads 1:75966605a6a3 304 /////////////////////////////////////////////////////////////////////////////////////
suads 1:75966605a6a3 305 // Functions for communicating with PICCs
suads 1:75966605a6a3 306 /////////////////////////////////////////////////////////////////////////////////////
suads 1:75966605a6a3 307
suads 1:75966605a6a3 308 /**
suads 1:75966605a6a3 309 * Executes the Transceive command.
suads 1:75966605a6a3 310 * CRC validation can only be done if backData and backLen are specified.
suads 1:75966605a6a3 311 */
suads 1:75966605a6a3 312 uint8_t MFRC522::PCD_TransceiveData(uint8_t *sendData,
suads 1:75966605a6a3 313 uint8_t sendLen,
suads 1:75966605a6a3 314 uint8_t *backData,
suads 1:75966605a6a3 315 uint8_t *backLen,
suads 1:75966605a6a3 316 uint8_t *validBits,
suads 1:75966605a6a3 317 uint8_t rxAlign,
suads 1:75966605a6a3 318 bool checkCRC)
suads 1:75966605a6a3 319 {
suads 1:75966605a6a3 320 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
suads 1:75966605a6a3 321 return PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, sendData, sendLen, backData, backLen, validBits, rxAlign, checkCRC);
suads 1:75966605a6a3 322 } // End PCD_TransceiveData()
suads 1:75966605a6a3 323
suads 1:75966605a6a3 324 /**
suads 1:75966605a6a3 325 * Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO.
suads 1:75966605a6a3 326 * CRC validation can only be done if backData and backLen are specified.
suads 1:75966605a6a3 327 */
suads 1:75966605a6a3 328 uint8_t MFRC522::PCD_CommunicateWithPICC(uint8_t command,
suads 1:75966605a6a3 329 uint8_t waitIRq,
suads 1:75966605a6a3 330 uint8_t *sendData,
suads 1:75966605a6a3 331 uint8_t sendLen,
suads 1:75966605a6a3 332 uint8_t *backData,
suads 1:75966605a6a3 333 uint8_t *backLen,
suads 1:75966605a6a3 334 uint8_t *validBits,
suads 1:75966605a6a3 335 uint8_t rxAlign,
suads 1:75966605a6a3 336 bool checkCRC)
suads 1:75966605a6a3 337 {
suads 1:75966605a6a3 338 uint8_t n, _validBits = 0;
suads 1:75966605a6a3 339 uint32_t i;
suads 1:75966605a6a3 340
suads 1:75966605a6a3 341 // Prepare values for BitFramingReg
suads 1:75966605a6a3 342 uint8_t txLastBits = validBits ? *validBits : 0;
suads 1:75966605a6a3 343 uint8_t bitFraming = (rxAlign << 4) + txLastBits; // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
suads 1:75966605a6a3 344
suads 1:75966605a6a3 345 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
suads 1:75966605a6a3 346 PCD_WriteRegister(ComIrqReg, 0x7F); // Clear all seven interrupt request bits
suads 1:75966605a6a3 347 PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
suads 1:75966605a6a3 348 PCD_WriteRegister(FIFODataReg, sendLen, sendData); // Write sendData to the FIFO
suads 1:75966605a6a3 349 PCD_WriteRegister(BitFramingReg, bitFraming); // Bit adjustments
suads 1:75966605a6a3 350 PCD_WriteRegister(CommandReg, command); // Execute the command
suads 1:75966605a6a3 351 if (command == PCD_Transceive)
suads 1:75966605a6a3 352 {
suads 1:75966605a6a3 353 PCD_SetRegisterBits(BitFramingReg, 0x80); // StartSend=1, transmission of data starts
suads 1:75966605a6a3 354 }
suads 1:75966605a6a3 355
suads 1:75966605a6a3 356 // Wait for the command to complete.
suads 1:75966605a6a3 357 // In PCD_Init() we set the TAuto flag in TModeReg. This means the timer automatically starts when the PCD stops transmitting.
suads 1:75966605a6a3 358 // Each iteration of the do-while-loop takes 17.86us.
suads 1:75966605a6a3 359 i = 2000;
suads 1:75966605a6a3 360 while (1)
suads 1:75966605a6a3 361 {
suads 1:75966605a6a3 362 n = PCD_ReadRegister(ComIrqReg); // ComIrqReg[7..0] bits are: Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq
suads 1:75966605a6a3 363 if (n & waitIRq)
suads 1:75966605a6a3 364 { // One of the interrupts that signal success has been set.
suads 1:75966605a6a3 365 break;
suads 1:75966605a6a3 366 }
suads 1:75966605a6a3 367
suads 1:75966605a6a3 368 if (n & 0x01)
suads 1:75966605a6a3 369 { // Timer interrupt - nothing received in 25ms
suads 1:75966605a6a3 370 return STATUS_TIMEOUT;
suads 1:75966605a6a3 371 }
suads 1:75966605a6a3 372
suads 1:75966605a6a3 373 if (--i == 0)
suads 1:75966605a6a3 374 { // The emergency break. If all other condions fail we will eventually terminate on this one after 35.7ms. Communication with the MFRC522 might be down.
suads 1:75966605a6a3 375 return STATUS_TIMEOUT;
suads 1:75966605a6a3 376 }
suads 1:75966605a6a3 377 }
suads 1:75966605a6a3 378
suads 1:75966605a6a3 379 // Stop now if any errors except collisions were detected.
suads 1:75966605a6a3 380 uint8_t errorRegValue = PCD_ReadRegister(ErrorReg); // ErrorReg[7..0] bits are: WrErr TempErr reserved BufferOvfl CollErr CRCErr ParityErr ProtocolErr
suads 1:75966605a6a3 381 if (errorRegValue & 0x13)
suads 1:75966605a6a3 382 { // BufferOvfl ParityErr ProtocolErr
suads 1:75966605a6a3 383 return STATUS_ERROR;
suads 1:75966605a6a3 384 }
suads 1:75966605a6a3 385
suads 1:75966605a6a3 386 // If the caller wants data back, get it from the MFRC522.
suads 1:75966605a6a3 387 if (backData && backLen)
suads 1:75966605a6a3 388 {
suads 1:75966605a6a3 389 n = PCD_ReadRegister(FIFOLevelReg); // Number of bytes in the FIFO
suads 1:75966605a6a3 390 if (n > *backLen)
suads 1:75966605a6a3 391 {
suads 1:75966605a6a3 392 return STATUS_NO_ROOM;
suads 1:75966605a6a3 393 }
suads 1:75966605a6a3 394
suads 1:75966605a6a3 395 *backLen = n; // Number of bytes returned
suads 1:75966605a6a3 396 PCD_ReadRegister(FIFODataReg, n, backData, rxAlign); // Get received data from FIFO
suads 1:75966605a6a3 397 _validBits = PCD_ReadRegister(ControlReg) & 0x07; // RxLastBits[2:0] indicates the number of valid bits in the last received byte. If this value is 000b, the whole byte is valid.
suads 1:75966605a6a3 398 if (validBits)
suads 1:75966605a6a3 399 {
suads 1:75966605a6a3 400 *validBits = _validBits;
suads 1:75966605a6a3 401 }
suads 1:75966605a6a3 402 }
suads 1:75966605a6a3 403
suads 1:75966605a6a3 404 // Tell about collisions
suads 1:75966605a6a3 405 if (errorRegValue & 0x08)
suads 1:75966605a6a3 406 { // CollErr
suads 1:75966605a6a3 407 return STATUS_COLLISION;
suads 1:75966605a6a3 408 }
suads 1:75966605a6a3 409
suads 1:75966605a6a3 410 // Perform CRC_A validation if requested.
suads 1:75966605a6a3 411 if (backData && backLen && checkCRC)
suads 1:75966605a6a3 412 {
suads 1:75966605a6a3 413 // In this case a MIFARE Classic NAK is not OK.
suads 1:75966605a6a3 414 if ((*backLen == 1) && (_validBits == 4))
suads 1:75966605a6a3 415 {
suads 1:75966605a6a3 416 return STATUS_MIFARE_NACK;
suads 1:75966605a6a3 417 }
suads 1:75966605a6a3 418
suads 1:75966605a6a3 419 // We need at least the CRC_A value and all 8 bits of the last byte must be received.
suads 1:75966605a6a3 420 if ((*backLen < 2) || (_validBits != 0))
suads 1:75966605a6a3 421 {
suads 1:75966605a6a3 422 return STATUS_CRC_WRONG;
suads 1:75966605a6a3 423 }
suads 1:75966605a6a3 424
suads 1:75966605a6a3 425 // Verify CRC_A - do our own calculation and store the control in controlBuffer.
suads 1:75966605a6a3 426 uint8_t controlBuffer[2];
suads 1:75966605a6a3 427 n = PCD_CalculateCRC(&backData[0], *backLen - 2, &controlBuffer[0]);
suads 1:75966605a6a3 428 if (n != STATUS_OK)
suads 1:75966605a6a3 429 {
suads 1:75966605a6a3 430 return n;
suads 1:75966605a6a3 431 }
suads 1:75966605a6a3 432
suads 1:75966605a6a3 433 if ((backData[*backLen - 2] != controlBuffer[0]) || (backData[*backLen - 1] != controlBuffer[1]))
suads 1:75966605a6a3 434 {
suads 1:75966605a6a3 435 return STATUS_CRC_WRONG;
suads 1:75966605a6a3 436 }
suads 1:75966605a6a3 437 }
suads 1:75966605a6a3 438
suads 1:75966605a6a3 439 return STATUS_OK;
suads 1:75966605a6a3 440 } // End PCD_CommunicateWithPICC()
suads 1:75966605a6a3 441
suads 1:75966605a6a3 442 /*
suads 1:75966605a6a3 443 * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
suads 1:75966605a6a3 444 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
suads 1:75966605a6a3 445 */
suads 1:75966605a6a3 446 uint8_t MFRC522::PICC_RequestA(uint8_t *bufferATQA, uint8_t *bufferSize)
suads 1:75966605a6a3 447 {
suads 1:75966605a6a3 448 return PICC_REQA_or_WUPA(PICC_CMD_REQA, bufferATQA, bufferSize);
suads 1:75966605a6a3 449 } // End PICC_RequestA()
suads 1:75966605a6a3 450
suads 1:75966605a6a3 451 /**
suads 1:75966605a6a3 452 * Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
suads 1:75966605a6a3 453 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
suads 1:75966605a6a3 454 */
suads 1:75966605a6a3 455 uint8_t MFRC522::PICC_WakeupA(uint8_t *bufferATQA, uint8_t *bufferSize)
suads 1:75966605a6a3 456 {
suads 1:75966605a6a3 457 return PICC_REQA_or_WUPA(PICC_CMD_WUPA, bufferATQA, bufferSize);
suads 1:75966605a6a3 458 } // End PICC_WakeupA()
suads 1:75966605a6a3 459
suads 1:75966605a6a3 460 /*
suads 1:75966605a6a3 461 * Transmits REQA or WUPA commands.
suads 1:75966605a6a3 462 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
suads 1:75966605a6a3 463 */
suads 1:75966605a6a3 464 uint8_t MFRC522::PICC_REQA_or_WUPA(uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize)
suads 1:75966605a6a3 465 {
suads 1:75966605a6a3 466 uint8_t validBits;
suads 1:75966605a6a3 467 uint8_t status;
suads 1:75966605a6a3 468
suads 1:75966605a6a3 469 if (bufferATQA == NULL || *bufferSize < 2)
suads 1:75966605a6a3 470 { // The ATQA response is 2 bytes long.
suads 1:75966605a6a3 471 return STATUS_NO_ROOM;
suads 1:75966605a6a3 472 }
suads 1:75966605a6a3 473
suads 1:75966605a6a3 474 // ValuesAfterColl=1 => Bits received after collision are cleared.
suads 1:75966605a6a3 475 PCD_ClrRegisterBits(CollReg, 0x80);
suads 1:75966605a6a3 476
suads 1:75966605a6a3 477 // For REQA and WUPA we need the short frame format
suads 1:75966605a6a3 478 // - transmit only 7 bits of the last (and only) byte. TxLastBits = BitFramingReg[2..0]
suads 1:75966605a6a3 479 validBits = 7;
suads 1:75966605a6a3 480
suads 1:75966605a6a3 481 status = PCD_TransceiveData(&command, 1, bufferATQA, bufferSize, &validBits);
suads 1:75966605a6a3 482 if (status != STATUS_OK)
suads 1:75966605a6a3 483 {
suads 1:75966605a6a3 484 return status;
suads 1:75966605a6a3 485 }
suads 1:75966605a6a3 486
suads 1:75966605a6a3 487 if ((*bufferSize != 2) || (validBits != 0))
suads 1:75966605a6a3 488 { // ATQA must be exactly 16 bits.
suads 1:75966605a6a3 489 return STATUS_ERROR;
suads 1:75966605a6a3 490 }
suads 1:75966605a6a3 491
suads 1:75966605a6a3 492 return STATUS_OK;
suads 1:75966605a6a3 493 } // End PICC_REQA_or_WUPA()
suads 1:75966605a6a3 494
suads 1:75966605a6a3 495 /*
suads 1:75966605a6a3 496 * Transmits SELECT/ANTICOLLISION commands to select a single PICC.
suads 1:75966605a6a3 497 */
suads 1:75966605a6a3 498 uint8_t MFRC522::PICC_Select(Uid *uid, uint8_t validBits)
suads 1:75966605a6a3 499 {
suads 1:75966605a6a3 500 bool uidComplete;
suads 1:75966605a6a3 501 bool selectDone;
suads 1:75966605a6a3 502 bool useCascadeTag;
suads 1:75966605a6a3 503 uint8_t cascadeLevel = 1;
suads 1:75966605a6a3 504 uint8_t result;
suads 1:75966605a6a3 505 uint8_t count;
suads 1:75966605a6a3 506 uint8_t index;
suads 1:75966605a6a3 507 uint8_t uidIndex; // The first index in uid->uidByte[] that is used in the current Cascade Level.
suads 1:75966605a6a3 508 uint8_t currentLevelKnownBits; // The number of known UID bits in the current Cascade Level.
suads 1:75966605a6a3 509 uint8_t buffer[9]; // The SELECT/ANTICOLLISION commands uses a 7 byte standard frame + 2 bytes CRC_A
suads 1:75966605a6a3 510 uint8_t bufferUsed; // The number of bytes used in the buffer, ie the number of bytes to transfer to the FIFO.
suads 1:75966605a6a3 511 uint8_t rxAlign; // Used in BitFramingReg. Defines the bit position for the first bit received.
suads 1:75966605a6a3 512 uint8_t txLastBits; // Used in BitFramingReg. The number of valid bits in the last transmitted byte.
suads 1:75966605a6a3 513 uint8_t *responseBuffer;
suads 1:75966605a6a3 514 uint8_t responseLength;
suads 1:75966605a6a3 515
suads 1:75966605a6a3 516 // Description of buffer structure:
suads 1:75966605a6a3 517 // Byte 0: SEL Indicates the Cascade Level: PICC_CMD_SEL_CL1, PICC_CMD_SEL_CL2 or PICC_CMD_SEL_CL3
suads 1:75966605a6a3 518 // Byte 1: NVB Number of Valid Bits (in complete command, not just the UID): High nibble: complete bytes, Low nibble: Extra bits.
suads 1:75966605a6a3 519 // Byte 2: UID-data or CT See explanation below. CT means Cascade Tag.
suads 1:75966605a6a3 520 // Byte 3: UID-data
suads 1:75966605a6a3 521 // Byte 4: UID-data
suads 1:75966605a6a3 522 // Byte 5: UID-data
suads 1:75966605a6a3 523 // Byte 6: BCC Block Check Character - XOR of bytes 2-5
suads 1:75966605a6a3 524 // Byte 7: CRC_A
suads 1:75966605a6a3 525 // Byte 8: CRC_A
suads 1:75966605a6a3 526 // The BCC and CRC_A is only transmitted if we know all the UID bits of the current Cascade Level.
suads 1:75966605a6a3 527 //
suads 1:75966605a6a3 528 // Description of bytes 2-5: (Section 6.5.4 of the ISO/IEC 14443-3 draft: UID contents and cascade levels)
suads 1:75966605a6a3 529 // UID size Cascade level Byte2 Byte3 Byte4 Byte5
suads 1:75966605a6a3 530 // ======== ============= ===== ===== ===== =====
suads 1:75966605a6a3 531 // 4 bytes 1 uid0 uid1 uid2 uid3
suads 1:75966605a6a3 532 // 7 bytes 1 CT uid0 uid1 uid2
suads 1:75966605a6a3 533 // 2 uid3 uid4 uid5 uid6
suads 1:75966605a6a3 534 // 10 bytes 1 CT uid0 uid1 uid2
suads 1:75966605a6a3 535 // 2 CT uid3 uid4 uid5
suads 1:75966605a6a3 536 // 3 uid6 uid7 uid8 uid9
suads 1:75966605a6a3 537
suads 1:75966605a6a3 538 // Sanity checks
suads 1:75966605a6a3 539 if (validBits > 80)
suads 1:75966605a6a3 540 {
suads 1:75966605a6a3 541 return STATUS_INVALID;
suads 1:75966605a6a3 542 }
suads 1:75966605a6a3 543
suads 1:75966605a6a3 544 // Prepare MFRC522
suads 1:75966605a6a3 545 // ValuesAfterColl=1 => Bits received after collision are cleared.
suads 1:75966605a6a3 546 PCD_ClrRegisterBits(CollReg, 0x80);
suads 1:75966605a6a3 547
suads 1:75966605a6a3 548 // Repeat Cascade Level loop until we have a complete UID.
suads 1:75966605a6a3 549 uidComplete = false;
suads 1:75966605a6a3 550 while ( ! uidComplete)
suads 1:75966605a6a3 551 {
suads 1:75966605a6a3 552 // Set the Cascade Level in the SEL byte, find out if we need to use the Cascade Tag in byte 2.
suads 1:75966605a6a3 553 switch (cascadeLevel)
suads 1:75966605a6a3 554 {
suads 1:75966605a6a3 555 case 1:
suads 1:75966605a6a3 556 buffer[0] = PICC_CMD_SEL_CL1;
suads 1:75966605a6a3 557 uidIndex = 0;
suads 1:75966605a6a3 558 useCascadeTag = validBits && (uid->size > 4); // When we know that the UID has more than 4 bytes
suads 1:75966605a6a3 559 break;
suads 1:75966605a6a3 560
suads 1:75966605a6a3 561 case 2:
suads 1:75966605a6a3 562 buffer[0] = PICC_CMD_SEL_CL2;
suads 1:75966605a6a3 563 uidIndex = 3;
suads 1:75966605a6a3 564 useCascadeTag = validBits && (uid->size > 7); // When we know that the UID has more than 7 bytes
suads 1:75966605a6a3 565 break;
suads 1:75966605a6a3 566
suads 1:75966605a6a3 567 case 3:
suads 1:75966605a6a3 568 buffer[0] = PICC_CMD_SEL_CL3;
suads 1:75966605a6a3 569 uidIndex = 6;
suads 1:75966605a6a3 570 useCascadeTag = false; // Never used in CL3.
suads 1:75966605a6a3 571 break;
suads 1:75966605a6a3 572
suads 1:75966605a6a3 573 default:
suads 1:75966605a6a3 574 return STATUS_INTERNAL_ERROR;
suads 1:75966605a6a3 575 //break;
suads 1:75966605a6a3 576 }
suads 1:75966605a6a3 577
suads 1:75966605a6a3 578 // How many UID bits are known in this Cascade Level?
suads 1:75966605a6a3 579 if(validBits > (8 * uidIndex))
suads 1:75966605a6a3 580 {
suads 1:75966605a6a3 581 currentLevelKnownBits = validBits - (8 * uidIndex);
suads 1:75966605a6a3 582 }
suads 1:75966605a6a3 583 else
suads 1:75966605a6a3 584 {
suads 1:75966605a6a3 585 currentLevelKnownBits = 0;
suads 1:75966605a6a3 586 }
suads 1:75966605a6a3 587
suads 1:75966605a6a3 588 // Copy the known bits from uid->uidByte[] to buffer[]
suads 1:75966605a6a3 589 index = 2; // destination index in buffer[]
suads 1:75966605a6a3 590 if (useCascadeTag)
suads 1:75966605a6a3 591 {
suads 1:75966605a6a3 592 buffer[index++] = PICC_CMD_CT;
suads 1:75966605a6a3 593 }
suads 1:75966605a6a3 594
suads 1:75966605a6a3 595 uint8_t bytesToCopy = currentLevelKnownBits / 8 + (currentLevelKnownBits % 8 ? 1 : 0); // The number of bytes needed to represent the known bits for this level.
suads 1:75966605a6a3 596 if (bytesToCopy)
suads 1:75966605a6a3 597 {
suads 1:75966605a6a3 598 // Max 4 bytes in each Cascade Level. Only 3 left if we use the Cascade Tag
suads 1:75966605a6a3 599 uint8_t maxBytes = useCascadeTag ? 3 : 4;
suads 1:75966605a6a3 600 if (bytesToCopy > maxBytes)
suads 1:75966605a6a3 601 {
suads 1:75966605a6a3 602 bytesToCopy = maxBytes;
suads 1:75966605a6a3 603 }
suads 1:75966605a6a3 604
suads 1:75966605a6a3 605 for (count = 0; count < bytesToCopy; count++)
suads 1:75966605a6a3 606 {
suads 1:75966605a6a3 607 buffer[index++] = uid->uidByte[uidIndex + count];
suads 1:75966605a6a3 608 }
suads 1:75966605a6a3 609 }
suads 1:75966605a6a3 610
suads 1:75966605a6a3 611 // Now that the data has been copied we need to include the 8 bits in CT in currentLevelKnownBits
suads 1:75966605a6a3 612 if (useCascadeTag)
suads 1:75966605a6a3 613 {
suads 1:75966605a6a3 614 currentLevelKnownBits += 8;
suads 1:75966605a6a3 615 }
suads 1:75966605a6a3 616
suads 1:75966605a6a3 617 // Repeat anti collision loop until we can transmit all UID bits + BCC and receive a SAK - max 32 iterations.
suads 1:75966605a6a3 618 selectDone = false;
suads 1:75966605a6a3 619 while ( ! selectDone)
suads 1:75966605a6a3 620 {
suads 1:75966605a6a3 621 // Find out how many bits and bytes to send and receive.
suads 1:75966605a6a3 622 if (currentLevelKnownBits >= 32)
suads 1:75966605a6a3 623 { // All UID bits in this Cascade Level are known. This is a SELECT.
suads 1:75966605a6a3 624 //Serial.print("SELECT: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
suads 1:75966605a6a3 625 buffer[1] = 0x70; // NVB - Number of Valid Bits: Seven whole bytes
suads 1:75966605a6a3 626
suads 1:75966605a6a3 627 // Calulate BCC - Block Check Character
suads 1:75966605a6a3 628 buffer[6] = buffer[2] ^ buffer[3] ^ buffer[4] ^ buffer[5];
suads 1:75966605a6a3 629
suads 1:75966605a6a3 630 // Calculate CRC_A
suads 1:75966605a6a3 631 result = PCD_CalculateCRC(buffer, 7, &buffer[7]);
suads 1:75966605a6a3 632 if (result != STATUS_OK)
suads 1:75966605a6a3 633 {
suads 1:75966605a6a3 634 return result;
suads 1:75966605a6a3 635 }
suads 1:75966605a6a3 636
suads 1:75966605a6a3 637 txLastBits = 0; // 0 => All 8 bits are valid.
suads 1:75966605a6a3 638 bufferUsed = 9;
suads 1:75966605a6a3 639
suads 1:75966605a6a3 640 // Store response in the last 3 bytes of buffer (BCC and CRC_A - not needed after tx)
suads 1:75966605a6a3 641 responseBuffer = &buffer[6];
suads 1:75966605a6a3 642 responseLength = 3;
suads 1:75966605a6a3 643 }
suads 1:75966605a6a3 644 else
suads 1:75966605a6a3 645 { // This is an ANTICOLLISION.
suads 1:75966605a6a3 646 //Serial.print("ANTICOLLISION: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
suads 1:75966605a6a3 647 txLastBits = currentLevelKnownBits % 8;
suads 1:75966605a6a3 648 count = currentLevelKnownBits / 8; // Number of whole bytes in the UID part.
suads 1:75966605a6a3 649 index = 2 + count; // Number of whole bytes: SEL + NVB + UIDs
suads 1:75966605a6a3 650 buffer[1] = (index << 4) + txLastBits; // NVB - Number of Valid Bits
suads 1:75966605a6a3 651 bufferUsed = index + (txLastBits ? 1 : 0);
suads 1:75966605a6a3 652
suads 1:75966605a6a3 653 // Store response in the unused part of buffer
suads 1:75966605a6a3 654 responseBuffer = &buffer[index];
suads 1:75966605a6a3 655 responseLength = sizeof(buffer) - index;
suads 1:75966605a6a3 656 }
suads 1:75966605a6a3 657
suads 1:75966605a6a3 658 // Set bit adjustments
suads 1:75966605a6a3 659 rxAlign = txLastBits; // Having a seperate variable is overkill. But it makes the next line easier to read.
suads 1:75966605a6a3 660 PCD_WriteRegister(BitFramingReg, (rxAlign << 4) + txLastBits); // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
suads 1:75966605a6a3 661
suads 1:75966605a6a3 662 // Transmit the buffer and receive the response.
suads 1:75966605a6a3 663 result = PCD_TransceiveData(buffer, bufferUsed, responseBuffer, &responseLength, &txLastBits, rxAlign);
suads 1:75966605a6a3 664 if (result == STATUS_COLLISION)
suads 1:75966605a6a3 665 { // More than one PICC in the field => collision.
suads 1:75966605a6a3 666 result = PCD_ReadRegister(CollReg); // CollReg[7..0] bits are: ValuesAfterColl reserved CollPosNotValid CollPos[4:0]
suads 1:75966605a6a3 667 if (result & 0x20)
suads 1:75966605a6a3 668 { // CollPosNotValid
suads 1:75966605a6a3 669 return STATUS_COLLISION; // Without a valid collision position we cannot continue
suads 1:75966605a6a3 670 }
suads 1:75966605a6a3 671
suads 1:75966605a6a3 672 uint8_t collisionPos = result & 0x1F; // Values 0-31, 0 means bit 32.
suads 1:75966605a6a3 673 if (collisionPos == 0)
suads 1:75966605a6a3 674 {
suads 1:75966605a6a3 675 collisionPos = 32;
suads 1:75966605a6a3 676 }
suads 1:75966605a6a3 677
suads 1:75966605a6a3 678 if (collisionPos <= currentLevelKnownBits)
suads 1:75966605a6a3 679 { // No progress - should not happen
suads 1:75966605a6a3 680 return STATUS_INTERNAL_ERROR;
suads 1:75966605a6a3 681 }
suads 1:75966605a6a3 682
suads 1:75966605a6a3 683 // Choose the PICC with the bit set.
suads 1:75966605a6a3 684 currentLevelKnownBits = collisionPos;
suads 1:75966605a6a3 685 count = (currentLevelKnownBits - 1) % 8; // The bit to modify
suads 1:75966605a6a3 686 index = 1 + (currentLevelKnownBits / 8) + (count ? 1 : 0); // First byte is index 0.
suads 1:75966605a6a3 687 buffer[index] |= (1 << count);
suads 1:75966605a6a3 688 }
suads 1:75966605a6a3 689 else if (result != STATUS_OK)
suads 1:75966605a6a3 690 {
suads 1:75966605a6a3 691 return result;
suads 1:75966605a6a3 692 }
suads 1:75966605a6a3 693 else
suads 1:75966605a6a3 694 { // STATUS_OK
suads 1:75966605a6a3 695 if (currentLevelKnownBits >= 32)
suads 1:75966605a6a3 696 { // This was a SELECT.
suads 1:75966605a6a3 697 selectDone = true; // No more anticollision
suads 1:75966605a6a3 698 // We continue below outside the while.
suads 1:75966605a6a3 699 }
suads 1:75966605a6a3 700 else
suads 1:75966605a6a3 701 { // This was an ANTICOLLISION.
suads 1:75966605a6a3 702 // We now have all 32 bits of the UID in this Cascade Level
suads 1:75966605a6a3 703 currentLevelKnownBits = 32;
suads 1:75966605a6a3 704 // Run loop again to do the SELECT.
suads 1:75966605a6a3 705 }
suads 1:75966605a6a3 706 }
suads 1:75966605a6a3 707 } // End of while ( ! selectDone)
suads 1:75966605a6a3 708
suads 1:75966605a6a3 709 // We do not check the CBB - it was constructed by us above.
suads 1:75966605a6a3 710
suads 1:75966605a6a3 711 // Copy the found UID bytes from buffer[] to uid->uidByte[]
suads 1:75966605a6a3 712 index = (buffer[2] == PICC_CMD_CT) ? 3 : 2; // source index in buffer[]
suads 1:75966605a6a3 713 bytesToCopy = (buffer[2] == PICC_CMD_CT) ? 3 : 4;
suads 1:75966605a6a3 714 for (count = 0; count < bytesToCopy; count++)
suads 1:75966605a6a3 715 {
suads 1:75966605a6a3 716 uid->uidByte[uidIndex + count] = buffer[index++];
suads 1:75966605a6a3 717 }
suads 1:75966605a6a3 718
suads 1:75966605a6a3 719 // Check response SAK (Select Acknowledge)
suads 1:75966605a6a3 720 if (responseLength != 3 || txLastBits != 0)
suads 1:75966605a6a3 721 { // SAK must be exactly 24 bits (1 byte + CRC_A).
suads 1:75966605a6a3 722 return STATUS_ERROR;
suads 1:75966605a6a3 723 }
suads 1:75966605a6a3 724
suads 1:75966605a6a3 725 // Verify CRC_A - do our own calculation and store the control in buffer[2..3] - those bytes are not needed anymore.
suads 1:75966605a6a3 726 result = PCD_CalculateCRC(responseBuffer, 1, &buffer[2]);
suads 1:75966605a6a3 727 if (result != STATUS_OK)
suads 1:75966605a6a3 728 {
suads 1:75966605a6a3 729 return result;
suads 1:75966605a6a3 730 }
suads 1:75966605a6a3 731
suads 1:75966605a6a3 732 if ((buffer[2] != responseBuffer[1]) || (buffer[3] != responseBuffer[2]))
suads 1:75966605a6a3 733 {
suads 1:75966605a6a3 734 return STATUS_CRC_WRONG;
suads 1:75966605a6a3 735 }
suads 1:75966605a6a3 736
suads 1:75966605a6a3 737 if (responseBuffer[0] & 0x04)
suads 1:75966605a6a3 738 { // Cascade bit set - UID not complete yes
suads 1:75966605a6a3 739 cascadeLevel++;
suads 1:75966605a6a3 740 }
suads 1:75966605a6a3 741 else
suads 1:75966605a6a3 742 {
suads 1:75966605a6a3 743 uidComplete = true;
suads 1:75966605a6a3 744 uid->sak = responseBuffer[0];
suads 1:75966605a6a3 745 }
suads 1:75966605a6a3 746 } // End of while ( ! uidComplete)
suads 1:75966605a6a3 747
suads 1:75966605a6a3 748 // Set correct uid->size
suads 1:75966605a6a3 749 uid->size = 3 * cascadeLevel + 1;
suads 1:75966605a6a3 750
suads 1:75966605a6a3 751 return STATUS_OK;
suads 1:75966605a6a3 752 } // End PICC_Select()
suads 1:75966605a6a3 753
suads 1:75966605a6a3 754 /*
suads 1:75966605a6a3 755 * Instructs a PICC in state ACTIVE(*) to go to state HALT.
suads 1:75966605a6a3 756 */
suads 1:75966605a6a3 757 uint8_t MFRC522::PICC_HaltA()
suads 1:75966605a6a3 758 {
suads 1:75966605a6a3 759 uint8_t result;
suads 1:75966605a6a3 760 uint8_t buffer[4];
suads 1:75966605a6a3 761
suads 1:75966605a6a3 762 // Build command buffer
suads 1:75966605a6a3 763 buffer[0] = PICC_CMD_HLTA;
suads 1:75966605a6a3 764 buffer[1] = 0;
suads 1:75966605a6a3 765
suads 1:75966605a6a3 766 // Calculate CRC_A
suads 1:75966605a6a3 767 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
suads 1:75966605a6a3 768 if (result == STATUS_OK)
suads 1:75966605a6a3 769 {
suads 1:75966605a6a3 770 // Send the command.
suads 1:75966605a6a3 771 // The standard says:
suads 1:75966605a6a3 772 // If the PICC responds with any modulation during a period of 1 ms after the end of the frame containing the
suads 1:75966605a6a3 773 // HLTA command, this response shall be interpreted as 'not acknowledge'.
suads 1:75966605a6a3 774 // We interpret that this way: Only STATUS_TIMEOUT is an success.
suads 1:75966605a6a3 775 result = PCD_TransceiveData(buffer, sizeof(buffer), NULL, 0);
suads 1:75966605a6a3 776 if (result == STATUS_TIMEOUT)
suads 1:75966605a6a3 777 {
suads 1:75966605a6a3 778 result = STATUS_OK;
suads 1:75966605a6a3 779 }
suads 1:75966605a6a3 780 else if (result == STATUS_OK)
suads 1:75966605a6a3 781 { // That is ironically NOT ok in this case ;-)
suads 1:75966605a6a3 782 result = STATUS_ERROR;
suads 1:75966605a6a3 783 }
suads 1:75966605a6a3 784 }
suads 1:75966605a6a3 785
suads 1:75966605a6a3 786 return result;
suads 1:75966605a6a3 787 } // End PICC_HaltA()
suads 1:75966605a6a3 788
suads 1:75966605a6a3 789
suads 1:75966605a6a3 790 /////////////////////////////////////////////////////////////////////////////////////
suads 1:75966605a6a3 791 // Functions for communicating with MIFARE PICCs
suads 1:75966605a6a3 792 /////////////////////////////////////////////////////////////////////////////////////
suads 1:75966605a6a3 793
suads 1:75966605a6a3 794 /*
suads 1:75966605a6a3 795 * Executes the MFRC522 MFAuthent command.
suads 1:75966605a6a3 796 */
suads 1:75966605a6a3 797 uint8_t MFRC522::PCD_Authenticate(uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid)
suads 1:75966605a6a3 798 {
suads 1:75966605a6a3 799 uint8_t i, waitIRq = 0x10; // IdleIRq
suads 1:75966605a6a3 800
suads 1:75966605a6a3 801 // Build command buffer
suads 1:75966605a6a3 802 uint8_t sendData[12];
suads 1:75966605a6a3 803 sendData[0] = command;
suads 1:75966605a6a3 804 sendData[1] = blockAddr;
suads 1:75966605a6a3 805
suads 1:75966605a6a3 806 for (i = 0; i < MF_KEY_SIZE; i++)
suads 1:75966605a6a3 807 { // 6 key bytes
suads 1:75966605a6a3 808 sendData[2+i] = key->keyByte[i];
suads 1:75966605a6a3 809 }
suads 1:75966605a6a3 810
suads 1:75966605a6a3 811 for (i = 0; i < 4; i++)
suads 1:75966605a6a3 812 { // The first 4 bytes of the UID
suads 1:75966605a6a3 813 sendData[8+i] = uid->uidByte[i];
suads 1:75966605a6a3 814 }
suads 1:75966605a6a3 815
suads 1:75966605a6a3 816 // Start the authentication.
suads 1:75966605a6a3 817 return PCD_CommunicateWithPICC(PCD_MFAuthent, waitIRq, &sendData[0], sizeof(sendData));
suads 1:75966605a6a3 818 } // End PCD_Authenticate()
suads 1:75966605a6a3 819
suads 1:75966605a6a3 820 /*
suads 1:75966605a6a3 821 * Used to exit the PCD from its authenticated state.
suads 1:75966605a6a3 822 * Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
suads 1:75966605a6a3 823 */
suads 1:75966605a6a3 824 void MFRC522::PCD_StopCrypto1()
suads 1:75966605a6a3 825 {
suads 1:75966605a6a3 826 // Clear MFCrypto1On bit
suads 1:75966605a6a3 827 PCD_ClrRegisterBits(Status2Reg, 0x08); // Status2Reg[7..0] bits are: TempSensClear I2CForceHS reserved reserved MFCrypto1On ModemState[2:0]
suads 1:75966605a6a3 828 } // End PCD_StopCrypto1()
suads 1:75966605a6a3 829
suads 1:75966605a6a3 830 /*
suads 1:75966605a6a3 831 * Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
suads 1:75966605a6a3 832 */
suads 1:75966605a6a3 833 uint8_t MFRC522::MIFARE_Read(uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize)
suads 1:75966605a6a3 834 {
suads 1:75966605a6a3 835 uint8_t result = STATUS_NO_ROOM;
suads 1:75966605a6a3 836
suads 1:75966605a6a3 837 // Sanity check
suads 1:75966605a6a3 838 if ((buffer == NULL) || (*bufferSize < 18))
suads 1:75966605a6a3 839 {
suads 1:75966605a6a3 840 return result;
suads 1:75966605a6a3 841 }
suads 1:75966605a6a3 842
suads 1:75966605a6a3 843 // Build command buffer
suads 1:75966605a6a3 844 buffer[0] = PICC_CMD_MF_READ;
suads 1:75966605a6a3 845 buffer[1] = blockAddr;
suads 1:75966605a6a3 846
suads 1:75966605a6a3 847 // Calculate CRC_A
suads 1:75966605a6a3 848 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
suads 1:75966605a6a3 849 if (result != STATUS_OK)
suads 1:75966605a6a3 850 {
suads 1:75966605a6a3 851 return result;
suads 1:75966605a6a3 852 }
suads 1:75966605a6a3 853
suads 1:75966605a6a3 854 // Transmit the buffer and receive the response, validate CRC_A.
suads 1:75966605a6a3 855 return PCD_TransceiveData(buffer, 4, buffer, bufferSize, NULL, 0, true);
suads 1:75966605a6a3 856 } // End MIFARE_Read()
suads 1:75966605a6a3 857
suads 1:75966605a6a3 858 /*
suads 1:75966605a6a3 859 * Writes 16 bytes to the active PICC.
suads 1:75966605a6a3 860 */
suads 1:75966605a6a3 861 uint8_t MFRC522::MIFARE_Write(uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize)
suads 1:75966605a6a3 862 {
suads 1:75966605a6a3 863 uint8_t result;
suads 1:75966605a6a3 864
suads 1:75966605a6a3 865 // Sanity check
suads 1:75966605a6a3 866 if (buffer == NULL || bufferSize < 16)
suads 1:75966605a6a3 867 {
suads 1:75966605a6a3 868 return STATUS_INVALID;
suads 1:75966605a6a3 869 }
suads 1:75966605a6a3 870
suads 1:75966605a6a3 871 // Mifare Classic protocol requires two communications to perform a write.
suads 1:75966605a6a3 872 // Step 1: Tell the PICC we want to write to block blockAddr.
suads 1:75966605a6a3 873 uint8_t cmdBuffer[2];
suads 1:75966605a6a3 874 cmdBuffer[0] = PICC_CMD_MF_WRITE;
suads 1:75966605a6a3 875 cmdBuffer[1] = blockAddr;
suads 1:75966605a6a3 876 // Adds CRC_A and checks that the response is MF_ACK.
suads 1:75966605a6a3 877 result = PCD_MIFARE_Transceive(cmdBuffer, 2);
suads 1:75966605a6a3 878 if (result != STATUS_OK)
suads 1:75966605a6a3 879 {
suads 1:75966605a6a3 880 return result;
suads 1:75966605a6a3 881 }
suads 1:75966605a6a3 882
suads 1:75966605a6a3 883 // Step 2: Transfer the data
suads 1:75966605a6a3 884 // Adds CRC_A and checks that the response is MF_ACK.
suads 1:75966605a6a3 885 result = PCD_MIFARE_Transceive(buffer, bufferSize);
suads 1:75966605a6a3 886 if (result != STATUS_OK)
suads 1:75966605a6a3 887 {
suads 1:75966605a6a3 888 return result;
suads 1:75966605a6a3 889 }
suads 1:75966605a6a3 890
suads 1:75966605a6a3 891 return STATUS_OK;
suads 1:75966605a6a3 892 } // End MIFARE_Write()
suads 1:75966605a6a3 893
suads 1:75966605a6a3 894 /*
suads 1:75966605a6a3 895 * Writes a 4 byte page to the active MIFARE Ultralight PICC.
suads 1:75966605a6a3 896 */
suads 1:75966605a6a3 897 uint8_t MFRC522::MIFARE_UltralightWrite(uint8_t page, uint8_t *buffer, uint8_t bufferSize)
suads 1:75966605a6a3 898 {
suads 1:75966605a6a3 899 uint8_t result;
suads 1:75966605a6a3 900
suads 1:75966605a6a3 901 // Sanity check
suads 1:75966605a6a3 902 if (buffer == NULL || bufferSize < 4)
suads 1:75966605a6a3 903 {
suads 1:75966605a6a3 904 return STATUS_INVALID;
suads 1:75966605a6a3 905 }
suads 1:75966605a6a3 906
suads 1:75966605a6a3 907 // Build commmand buffer
suads 1:75966605a6a3 908 uint8_t cmdBuffer[6];
suads 1:75966605a6a3 909 cmdBuffer[0] = PICC_CMD_UL_WRITE;
suads 1:75966605a6a3 910 cmdBuffer[1] = page;
suads 1:75966605a6a3 911 memcpy(&cmdBuffer[2], buffer, 4);
suads 1:75966605a6a3 912
suads 1:75966605a6a3 913 // Perform the write
suads 1:75966605a6a3 914 result = PCD_MIFARE_Transceive(cmdBuffer, 6); // Adds CRC_A and checks that the response is MF_ACK.
suads 1:75966605a6a3 915 if (result != STATUS_OK)
suads 1:75966605a6a3 916 {
suads 1:75966605a6a3 917 return result;
suads 1:75966605a6a3 918 }
suads 1:75966605a6a3 919
suads 1:75966605a6a3 920 return STATUS_OK;
suads 1:75966605a6a3 921 } // End MIFARE_Ultralight_Write()
suads 1:75966605a6a3 922
suads 1:75966605a6a3 923 /*
suads 1:75966605a6a3 924 * MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory.
suads 1:75966605a6a3 925 */
suads 1:75966605a6a3 926 uint8_t MFRC522::MIFARE_Decrement(uint8_t blockAddr, uint32_t delta)
suads 1:75966605a6a3 927 {
suads 1:75966605a6a3 928 return MIFARE_TwoStepHelper(PICC_CMD_MF_DECREMENT, blockAddr, delta);
suads 1:75966605a6a3 929 } // End MIFARE_Decrement()
suads 1:75966605a6a3 930
suads 1:75966605a6a3 931 /*
suads 1:75966605a6a3 932 * MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory.
suads 1:75966605a6a3 933 */
suads 1:75966605a6a3 934 uint8_t MFRC522::MIFARE_Increment(uint8_t blockAddr, uint32_t delta)
suads 1:75966605a6a3 935 {
suads 1:75966605a6a3 936 return MIFARE_TwoStepHelper(PICC_CMD_MF_INCREMENT, blockAddr, delta);
suads 1:75966605a6a3 937 } // End MIFARE_Increment()
suads 1:75966605a6a3 938
suads 1:75966605a6a3 939 /**
suads 1:75966605a6a3 940 * MIFARE Restore copies the value of the addressed block into a volatile memory.
suads 1:75966605a6a3 941 */
suads 1:75966605a6a3 942 uint8_t MFRC522::MIFARE_Restore(uint8_t blockAddr)
suads 1:75966605a6a3 943 {
suads 1:75966605a6a3 944 // The datasheet describes Restore as a two step operation, but does not explain what data to transfer in step 2.
suads 1:75966605a6a3 945 // Doing only a single step does not work, so I chose to transfer 0L in step two.
suads 1:75966605a6a3 946 return MIFARE_TwoStepHelper(PICC_CMD_MF_RESTORE, blockAddr, 0L);
suads 1:75966605a6a3 947 } // End MIFARE_Restore()
suads 1:75966605a6a3 948
suads 1:75966605a6a3 949 /*
suads 1:75966605a6a3 950 * Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore.
suads 1:75966605a6a3 951 */
suads 1:75966605a6a3 952 uint8_t MFRC522::MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data)
suads 1:75966605a6a3 953 {
suads 1:75966605a6a3 954 uint8_t result;
suads 1:75966605a6a3 955 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
suads 1:75966605a6a3 956
suads 1:75966605a6a3 957 // Step 1: Tell the PICC the command and block address
suads 1:75966605a6a3 958 cmdBuffer[0] = command;
suads 1:75966605a6a3 959 cmdBuffer[1] = blockAddr;
suads 1:75966605a6a3 960
suads 1:75966605a6a3 961 // Adds CRC_A and checks that the response is MF_ACK.
suads 1:75966605a6a3 962 result = PCD_MIFARE_Transceive(cmdBuffer, 2);
suads 1:75966605a6a3 963 if (result != STATUS_OK)
suads 1:75966605a6a3 964 {
suads 1:75966605a6a3 965 return result;
suads 1:75966605a6a3 966 }
suads 1:75966605a6a3 967
suads 1:75966605a6a3 968 // Step 2: Transfer the data
suads 1:75966605a6a3 969 // Adds CRC_A and accept timeout as success.
suads 1:75966605a6a3 970 result = PCD_MIFARE_Transceive((uint8_t *) &data, 4, true);
suads 1:75966605a6a3 971 if (result != STATUS_OK)
suads 1:75966605a6a3 972 {
suads 1:75966605a6a3 973 return result;
suads 1:75966605a6a3 974 }
suads 1:75966605a6a3 975
suads 1:75966605a6a3 976 return STATUS_OK;
suads 1:75966605a6a3 977 } // End MIFARE_TwoStepHelper()
suads 1:75966605a6a3 978
suads 1:75966605a6a3 979 /*
suads 1:75966605a6a3 980 * MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block.
suads 1:75966605a6a3 981 */
suads 1:75966605a6a3 982 uint8_t MFRC522::MIFARE_Transfer(uint8_t blockAddr)
suads 1:75966605a6a3 983 {
suads 1:75966605a6a3 984 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
suads 1:75966605a6a3 985
suads 1:75966605a6a3 986 // Tell the PICC we want to transfer the result into block blockAddr.
suads 1:75966605a6a3 987 cmdBuffer[0] = PICC_CMD_MF_TRANSFER;
suads 1:75966605a6a3 988 cmdBuffer[1] = blockAddr;
suads 1:75966605a6a3 989
suads 1:75966605a6a3 990 // Adds CRC_A and checks that the response is MF_ACK.
suads 1:75966605a6a3 991 return PCD_MIFARE_Transceive(cmdBuffer, 2);
suads 1:75966605a6a3 992 } // End MIFARE_Transfer()
suads 1:75966605a6a3 993
suads 1:75966605a6a3 994
suads 1:75966605a6a3 995 /////////////////////////////////////////////////////////////////////////////////////
suads 1:75966605a6a3 996 // Support functions
suads 1:75966605a6a3 997 /////////////////////////////////////////////////////////////////////////////////////
suads 1:75966605a6a3 998
suads 1:75966605a6a3 999 /*
suads 1:75966605a6a3 1000 * Wrapper for MIFARE protocol communication.
suads 1:75966605a6a3 1001 * Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout.
suads 1:75966605a6a3 1002 */
suads 1:75966605a6a3 1003 uint8_t MFRC522::PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout)
suads 1:75966605a6a3 1004 {
suads 1:75966605a6a3 1005 uint8_t result;
suads 1:75966605a6a3 1006 uint8_t cmdBuffer[18]; // We need room for 16 bytes data and 2 bytes CRC_A.
suads 1:75966605a6a3 1007
suads 1:75966605a6a3 1008 // Sanity check
suads 1:75966605a6a3 1009 if (sendData == NULL || sendLen > 16)
suads 1:75966605a6a3 1010 {
suads 1:75966605a6a3 1011 return STATUS_INVALID;
suads 1:75966605a6a3 1012 }
suads 1:75966605a6a3 1013
suads 1:75966605a6a3 1014 // Copy sendData[] to cmdBuffer[] and add CRC_A
suads 1:75966605a6a3 1015 memcpy(cmdBuffer, sendData, sendLen);
suads 1:75966605a6a3 1016 result = PCD_CalculateCRC(cmdBuffer, sendLen, &cmdBuffer[sendLen]);
suads 1:75966605a6a3 1017 if (result != STATUS_OK)
suads 1:75966605a6a3 1018 {
suads 1:75966605a6a3 1019 return result;
suads 1:75966605a6a3 1020 }
suads 1:75966605a6a3 1021
suads 1:75966605a6a3 1022 sendLen += 2;
suads 1:75966605a6a3 1023
suads 1:75966605a6a3 1024 // Transceive the data, store the reply in cmdBuffer[]
suads 1:75966605a6a3 1025 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
suads 1:75966605a6a3 1026 uint8_t cmdBufferSize = sizeof(cmdBuffer);
suads 1:75966605a6a3 1027 uint8_t validBits = 0;
suads 1:75966605a6a3 1028 result = PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, cmdBuffer, sendLen, cmdBuffer, &cmdBufferSize, &validBits);
suads 1:75966605a6a3 1029 if (acceptTimeout && result == STATUS_TIMEOUT)
suads 1:75966605a6a3 1030 {
suads 1:75966605a6a3 1031 return STATUS_OK;
suads 1:75966605a6a3 1032 }
suads 1:75966605a6a3 1033
suads 1:75966605a6a3 1034 if (result != STATUS_OK)
suads 1:75966605a6a3 1035 {
suads 1:75966605a6a3 1036 return result;
suads 1:75966605a6a3 1037 }
suads 1:75966605a6a3 1038
suads 1:75966605a6a3 1039 // The PICC must reply with a 4 bit ACK
suads 1:75966605a6a3 1040 if (cmdBufferSize != 1 || validBits != 4)
suads 1:75966605a6a3 1041 {
suads 1:75966605a6a3 1042 return STATUS_ERROR;
suads 1:75966605a6a3 1043 }
suads 1:75966605a6a3 1044
suads 1:75966605a6a3 1045 if (cmdBuffer[0] != MF_ACK)
suads 1:75966605a6a3 1046 {
suads 1:75966605a6a3 1047 return STATUS_MIFARE_NACK;
suads 1:75966605a6a3 1048 }
suads 1:75966605a6a3 1049
suads 1:75966605a6a3 1050 return STATUS_OK;
suads 1:75966605a6a3 1051 } // End PCD_MIFARE_Transceive()
suads 1:75966605a6a3 1052
suads 1:75966605a6a3 1053
suads 1:75966605a6a3 1054 /*
suads 1:75966605a6a3 1055 * Translates the SAK (Select Acknowledge) to a PICC type.
suads 1:75966605a6a3 1056 */
suads 1:75966605a6a3 1057 uint8_t MFRC522::PICC_GetType(uint8_t sak)
suads 1:75966605a6a3 1058 {
suads 1:75966605a6a3 1059 uint8_t retType = PICC_TYPE_UNKNOWN;
suads 1:75966605a6a3 1060
suads 1:75966605a6a3 1061 if (sak & 0x04)
suads 1:75966605a6a3 1062 { // UID not complete
suads 1:75966605a6a3 1063 retType = PICC_TYPE_NOT_COMPLETE;
suads 1:75966605a6a3 1064 }
suads 1:75966605a6a3 1065 else
suads 1:75966605a6a3 1066 {
suads 1:75966605a6a3 1067 switch (sak)
suads 1:75966605a6a3 1068 {
suads 1:75966605a6a3 1069 case 0x09: retType = PICC_TYPE_MIFARE_MINI; break;
suads 1:75966605a6a3 1070 case 0x08: retType = PICC_TYPE_MIFARE_1K; break;
suads 1:75966605a6a3 1071 case 0x18: retType = PICC_TYPE_MIFARE_4K; break;
suads 1:75966605a6a3 1072 case 0x00: retType = PICC_TYPE_MIFARE_UL; break;
suads 1:75966605a6a3 1073 case 0x10:
suads 1:75966605a6a3 1074 case 0x11: retType = PICC_TYPE_MIFARE_PLUS; break;
suads 1:75966605a6a3 1075 case 0x01: retType = PICC_TYPE_TNP3XXX; break;
suads 1:75966605a6a3 1076 default:
suads 1:75966605a6a3 1077 if (sak & 0x20)
suads 1:75966605a6a3 1078 {
suads 1:75966605a6a3 1079 retType = PICC_TYPE_ISO_14443_4;
suads 1:75966605a6a3 1080 }
suads 1:75966605a6a3 1081 else if (sak & 0x40)
suads 1:75966605a6a3 1082 {
suads 1:75966605a6a3 1083 retType = PICC_TYPE_ISO_18092;
suads 1:75966605a6a3 1084 }
suads 1:75966605a6a3 1085 break;
suads 1:75966605a6a3 1086 }
suads 1:75966605a6a3 1087 }
suads 1:75966605a6a3 1088
suads 1:75966605a6a3 1089 return (retType);
suads 1:75966605a6a3 1090 } // End PICC_GetType()
suads 1:75966605a6a3 1091
suads 1:75966605a6a3 1092 /*
suads 1:75966605a6a3 1093 * Returns a string pointer to the PICC type name.
suads 1:75966605a6a3 1094 */
suads 1:75966605a6a3 1095 char* MFRC522::PICC_GetTypeName(uint8_t piccType)
suads 1:75966605a6a3 1096 {
suads 1:75966605a6a3 1097 if(piccType == PICC_TYPE_NOT_COMPLETE)
suads 1:75966605a6a3 1098 {
suads 1:75966605a6a3 1099 piccType = MFRC522_MaxPICCs - 1;
suads 1:75966605a6a3 1100 }
suads 1:75966605a6a3 1101
suads 1:75966605a6a3 1102 return((char *) _TypeNamePICC[piccType]);
suads 1:75966605a6a3 1103 } // End PICC_GetTypeName()
suads 1:75966605a6a3 1104
suads 1:75966605a6a3 1105 /*
suads 1:75966605a6a3 1106 * Returns a string pointer to a status code name.
suads 1:75966605a6a3 1107 */
suads 1:75966605a6a3 1108 char* MFRC522::GetStatusCodeName(uint8_t code)
suads 1:75966605a6a3 1109 {
suads 1:75966605a6a3 1110 return((char *) _ErrorMessage[code]);
suads 1:75966605a6a3 1111 } // End GetStatusCodeName()
suads 1:75966605a6a3 1112
suads 1:75966605a6a3 1113 /*
suads 1:75966605a6a3 1114 * Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1).
suads 1:75966605a6a3 1115 */
suads 1:75966605a6a3 1116 void MFRC522::MIFARE_SetAccessBits(uint8_t *accessBitBuffer,
suads 1:75966605a6a3 1117 uint8_t g0,
suads 1:75966605a6a3 1118 uint8_t g1,
suads 1:75966605a6a3 1119 uint8_t g2,
suads 1:75966605a6a3 1120 uint8_t g3)
suads 1:75966605a6a3 1121 {
suads 1:75966605a6a3 1122 uint8_t c1 = ((g3 & 4) << 1) | ((g2 & 4) << 0) | ((g1 & 4) >> 1) | ((g0 & 4) >> 2);
suads 1:75966605a6a3 1123 uint8_t c2 = ((g3 & 2) << 2) | ((g2 & 2) << 1) | ((g1 & 2) << 0) | ((g0 & 2) >> 1);
suads 1:75966605a6a3 1124 uint8_t c3 = ((g3 & 1) << 3) | ((g2 & 1) << 2) | ((g1 & 1) << 1) | ((g0 & 1) << 0);
suads 1:75966605a6a3 1125
suads 1:75966605a6a3 1126 accessBitBuffer[0] = (~c2 & 0xF) << 4 | (~c1 & 0xF);
suads 1:75966605a6a3 1127 accessBitBuffer[1] = c1 << 4 | (~c3 & 0xF);
suads 1:75966605a6a3 1128 accessBitBuffer[2] = c3 << 4 | c2;
suads 1:75966605a6a3 1129 } // End MIFARE_SetAccessBits()
suads 1:75966605a6a3 1130
suads 1:75966605a6a3 1131 /////////////////////////////////////////////////////////////////////////////////////
suads 1:75966605a6a3 1132 // Convenience functions - does not add extra functionality
suads 1:75966605a6a3 1133 /////////////////////////////////////////////////////////////////////////////////////
suads 1:75966605a6a3 1134
suads 1:75966605a6a3 1135 /*
suads 1:75966605a6a3 1136 * Returns true if a PICC responds to PICC_CMD_REQA.
suads 1:75966605a6a3 1137 * Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
suads 1:75966605a6a3 1138 */
suads 1:75966605a6a3 1139 bool MFRC522::PICC_IsNewCardPresent(void)
suads 1:75966605a6a3 1140 {
suads 1:75966605a6a3 1141 uint8_t bufferATQA[2];
suads 1:75966605a6a3 1142 uint8_t bufferSize = sizeof(bufferATQA);
suads 1:75966605a6a3 1143 uint8_t result = PICC_RequestA(bufferATQA, &bufferSize);
suads 1:75966605a6a3 1144 return ((result == STATUS_OK) || (result == STATUS_COLLISION));
suads 1:75966605a6a3 1145 } // End PICC_IsNewCardPresent()
suads 1:75966605a6a3 1146
suads 1:75966605a6a3 1147 /*
suads 1:75966605a6a3 1148 * Simple wrapper around PICC_Select.
suads 1:75966605a6a3 1149 */
suads 1:75966605a6a3 1150 bool MFRC522::PICC_ReadCardSerial(void)
suads 1:75966605a6a3 1151 {
suads 1:75966605a6a3 1152 uint8_t result = PICC_Select(&uid);
suads 1:75966605a6a3 1153 return (result == STATUS_OK);
suads 1:75966605a6a3 1154 } // End PICC_ReadCardSerial()
suads 1:75966605a6a3 1155
suads 1:75966605a6a3 1156