stm32469i_discovery_sdram.c

00001 /**
00002   ******************************************************************************
00003   * @file    stm32469i_discovery_sdram.c
00004   * @author  MCD Application Team
00005   * @brief   This file includes the SDRAM driver for the MT48LC4M32B2B5-7 memory
00006   *          device mounted on STM32469I-Discovery board.
00007   ******************************************************************************
00008   * @attention
00009   *
00010   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00011   *
00012   * Redistribution and use in source and binary forms, with or without modification,
00013   * are permitted provided that the following conditions are met:
00014   *   1. Redistributions of source code must retain the above copyright notice,
00015   *      this list of conditions and the following disclaimer.
00016   *   2. Redistributions in binary form must reproduce the above copyright notice,
00017   *      this list of conditions and the following disclaimer in the documentation
00018   *      and/or other materials provided with the distribution.
00019   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00020   *      may be used to endorse or promote products derived from this software
00021   *      without specific prior written permission.
00022   *
00023   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00024   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00025   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00026   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00027   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00028   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00029   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00030   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00031   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00032   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00033   *
00034   ******************************************************************************
00035   */
00036 
00037 /* File Info : -----------------------------------------------------------------
00038                                    User NOTES
00039 1. How To use this driver:
00040 --------------------------
00041    - This driver is used to drive the MT48LC4M32B2B5-7 SDRAM external memory mounted
00042      on STM32469I-Discovery board.
00043    - This driver does not need a specific component driver for the SDRAM device
00044      to be included with.
00045 
00046 2. Driver description:
00047 ---------------------
00048   + Initialization steps:
00049      o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This
00050        function includes the MSP layer hardware resources initialization and the
00051        FMC controller configuration to interface with the external SDRAM memory.
00052      o It contains the SDRAM initialization sequence to program the SDRAM external
00053        device using the function BSP_SDRAM_Initialization_sequence(). Note that this
00054        sequence is standard for all SDRAM devices, but can include some differences
00055        from a device to another. If it is the case, the right sequence should be
00056        implemented separately.
00057 
00058   + SDRAM read/write operations
00059      o SDRAM external memory can be accessed with read/write operations once it is
00060        initialized.
00061        Read/write operation can be performed with AHB access using the functions
00062        BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by DMA transfer using the functions
00063        BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA().
00064      o The AHB access is performed with 32-bit width transaction, the DMA transfer
00065        configuration is fixed at single (no burst) word transfer (see the
00066        BSP_SDRAM_MspInit() weak function).
00067      o User can implement his own functions for read/write access with his desired
00068        configurations.
00069      o If interrupt mode is used for DMA transfer, the function BSP_SDRAM_DMA_IRQHandler()
00070        is called in IRQ handler file, to serve the generated interrupt once the DMA
00071        transfer is complete.
00072      o You can send a command to the SDRAM device in runtime using the function
00073        BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between
00074        the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure.
00075 
00076 ------------------------------------------------------------------------------*/
00077 
00078 /* Includes ------------------------------------------------------------------*/
00079 #include "stm32469i_discovery_sdram.h"
00080 
00081 // mbed
00082 void wait_ms(int ms);
00083 
00084 /** @addtogroup BSP
00085   * @{
00086   */
00087 
00088 /** @addtogroup STM32469I_Discovery
00089   * @{
00090   */
00091 
00092 /** @defgroup STM32469I-Discovery_SDRAM STM32469I Discovery SDRAM
00093   * @{
00094   */
00095 
00096 /** @defgroup STM32469I-Discovery_SDRAM_Private_Types_Definitions STM32469I Discovery SDRAM Private TypesDef
00097   * @{
00098   */
00099 /**
00100   * @}
00101   */
00102 
00103 /** @defgroup STM32469I-Discovery_SDRAM_Private_Defines STM32469I Discovery SDRAM Private Defines
00104   * @{
00105   */
00106 /**
00107   * @}
00108   */
00109 
00110 /** @defgroup STM32469I-Discovery_SDRAM_Private_Macros STM32469I Discovery SDRAM Private Macros
00111   * @{
00112   */
00113 /**
00114   * @}
00115   */
00116 
00117 /** @defgroup STM32469I-Discovery_SDRAM_Private_Variables STM32469I Discovery SDRAM Private Variables
00118   * @{
00119   */
00120 static SDRAM_HandleTypeDef sdramHandle;
00121 static FMC_SDRAM_TimingTypeDef Timing;
00122 static FMC_SDRAM_CommandTypeDef Command;
00123 /**
00124   * @}
00125   */
00126 
00127 /** @defgroup STM32469I-Discovery_SDRAM_Private_Function_Prototypes STM32469I Discovery SDRAM Private Prototypes
00128   * @{
00129   */
00130 
00131 /**
00132   * @}
00133   */
00134 
00135 /** @defgroup STM32469I-Discovery_SDRAM_Private_Functions STM32469I Discovery SDRAM Private Functions
00136   * @{
00137   */
00138 
00139 /**
00140   * @}
00141   */
00142 
00143 /** @defgroup STM32469I_Discovery_SDRAM_Exported_Functions STM32469I Discovery SDRAM Exported Functions
00144   * @{
00145   */
00146 
00147 /**
00148   * @brief  Initializes the SDRAM device.
00149   * @retval SDRAM status
00150   */
00151 uint8_t BSP_SDRAM_Init(void)
00152 {
00153   static uint8_t sdramstatus = SDRAM_ERROR;
00154 
00155   /* SDRAM device configuration */
00156   sdramHandle.Instance = FMC_SDRAM_DEVICE;
00157 
00158   /* Timing configuration for 90 MHz as SD clock frequency (System clock is up to 180 MHz) */
00159   Timing.LoadToActiveDelay    = 2;
00160   Timing.ExitSelfRefreshDelay = 7;
00161   Timing.SelfRefreshTime      = 4;
00162   Timing.RowCycleDelay        = 7;
00163   Timing.WriteRecoveryTime    = 2;
00164   Timing.RPDelay              = 2;
00165   Timing.RCDDelay             = 2;
00166 
00167   sdramHandle.Init.SDBank             = FMC_SDRAM_BANK1;
00168   sdramHandle.Init.ColumnBitsNumber   = FMC_SDRAM_COLUMN_BITS_NUM_8;
00169   sdramHandle.Init.RowBitsNumber      = FMC_SDRAM_ROW_BITS_NUM_12;
00170   sdramHandle.Init.MemoryDataWidth    = SDRAM_MEMORY_WIDTH;
00171   sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
00172   sdramHandle.Init.CASLatency         = FMC_SDRAM_CAS_LATENCY_3;
00173   sdramHandle.Init.WriteProtection    = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
00174   sdramHandle.Init.SDClockPeriod      = SDCLOCK_PERIOD;
00175   sdramHandle.Init.ReadBurst          = FMC_SDRAM_RBURST_ENABLE;
00176   sdramHandle.Init.ReadPipeDelay      = FMC_SDRAM_RPIPE_DELAY_0;
00177 
00178   /* SDRAM controller initialization */
00179   /* __weak function can be surcharged by the application code */
00180   BSP_SDRAM_MspInit(&sdramHandle, (void *)NULL);
00181   if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK)
00182   {
00183     sdramstatus = SDRAM_ERROR;
00184   }
00185   else
00186   {
00187     sdramstatus = SDRAM_OK;
00188   }
00189 
00190   /* SDRAM initialization sequence */
00191   BSP_SDRAM_Initialization_sequence(REFRESH_COUNT);
00192 
00193   return sdramstatus;
00194 }
00195 
00196 /**
00197   * @brief  DeInitializes the SDRAM device.
00198   * @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
00199   */
00200 uint8_t BSP_SDRAM_DeInit(void)
00201 {
00202   static uint8_t sdramstatus = SDRAM_ERROR;
00203 
00204   /* SDRAM device configuration */
00205   sdramHandle.Instance = FMC_SDRAM_DEVICE;
00206 
00207   if(HAL_SDRAM_DeInit(&sdramHandle) == HAL_OK)
00208   {
00209     sdramstatus = SDRAM_OK;
00210 
00211   /* SDRAM controller De-initialization */
00212    BSP_SDRAM_MspDeInit(&sdramHandle, (void *)NULL);
00213   }
00214 
00215   return sdramstatus;
00216 }
00217 
00218 
00219 /**
00220   * @brief  Programs the SDRAM device.
00221   * @param  RefreshCount: SDRAM refresh counter value
00222   */
00223 void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
00224 {
00225   __IO uint32_t tmpmrd = 0;
00226 
00227   /* Step 1: Configure a clock configuration enable command */
00228   Command.CommandMode            = FMC_SDRAM_CMD_CLK_ENABLE;
00229   Command.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK1;
00230   Command.AutoRefreshNumber      = 1;
00231   Command.ModeRegisterDefinition = 0;
00232 
00233   /* Send the command */
00234   HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
00235 
00236   /* Step 2: Insert 100 us minimum delay */
00237   /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */
00238   //HAL_Delay(1);
00239   wait_ms(1);
00240 
00241   /* Step 3: Configure a PALL (precharge all) command */
00242   Command.CommandMode            = FMC_SDRAM_CMD_PALL;
00243   Command.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK1;
00244   Command.AutoRefreshNumber      = 1;
00245   Command.ModeRegisterDefinition = 0;
00246 
00247   /* Send the command */
00248   HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
00249 
00250   /* Step 4: Configure an Auto Refresh command */
00251   Command.CommandMode            = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
00252   Command.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK1;
00253   Command.AutoRefreshNumber      = 8;
00254   Command.ModeRegisterDefinition = 0;
00255 
00256   /* Send the command */
00257   HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
00258 
00259   /* Step 5: Program the external memory mode register */
00260   tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1          |\
00261                      SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL   |\
00262                      SDRAM_MODEREG_CAS_LATENCY_3           |\
00263                      SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
00264                      SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
00265 
00266   Command.CommandMode            = FMC_SDRAM_CMD_LOAD_MODE;
00267   Command.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK1;
00268   Command.AutoRefreshNumber      = 1;
00269   Command.ModeRegisterDefinition = tmpmrd;
00270 
00271   /* Send the command */
00272   HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
00273 
00274   /* Step 6: Set the refresh rate counter */
00275   /* Set the device refresh rate */
00276   HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount);
00277 }
00278 
00279 /**
00280   * @brief  Reads an mount of data from the SDRAM memory in polling mode.
00281   * @param  uwStartAddress: Read start address
00282   * @param  pData: Pointer to data to be read
00283   * @param  uwDataSize: Size of read data from the memory
00284   * @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
00285   */
00286 uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
00287 {
00288   if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
00289   {
00290     return SDRAM_ERROR;
00291   }
00292   else
00293   {
00294     return SDRAM_OK;
00295   }
00296 }
00297 
00298 /**
00299   * @brief  Reads an mount of data from the SDRAM memory in DMA mode.
00300   * @param  uwStartAddress: Read start address
00301   * @param  pData: Pointer to data to be read
00302   * @param  uwDataSize: Size of read data from the memory
00303   * @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
00304   */
00305 uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
00306 {
00307   if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
00308   {
00309     return SDRAM_ERROR;
00310   }
00311   else
00312   {
00313     return SDRAM_OK;
00314   }
00315 }
00316 
00317 /**
00318   * @brief  Writes an mount of data to the SDRAM memory in polling mode.
00319   * @param  uwStartAddress: Write start address
00320   * @param  pData: Pointer to data to be written
00321   * @param  uwDataSize: Size of written data from the memory
00322   * @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
00323   */
00324 uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
00325 {
00326   if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
00327   {
00328     return SDRAM_ERROR;
00329   }
00330   else
00331   {
00332     return SDRAM_OK;
00333   }
00334 }
00335 
00336 /**
00337   * @brief  Writes an mount of data to the SDRAM memory in DMA mode.
00338   * @param  uwStartAddress: Write start address
00339   * @param  pData: Pointer to data to be written
00340   * @param  uwDataSize: Size of written data from the memory
00341   * @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
00342   */
00343 uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
00344 {
00345   if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
00346   {
00347     return SDRAM_ERROR;
00348   }
00349   else
00350   {
00351     return SDRAM_OK;
00352   }
00353 }
00354 
00355 /**
00356   * @brief  Sends command to the SDRAM bank.
00357   * @param  SdramCmd: Pointer to SDRAM command structure
00358   * @retval HAL status : SDRAM_OK or SDRAM_ERROR.
00359   */
00360 uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd)
00361 {
00362   if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK)
00363   {
00364     return SDRAM_ERROR;
00365   }
00366   else
00367   {
00368     return SDRAM_OK;
00369   }
00370 }
00371 
00372 /**
00373   * @brief  Handles SDRAM DMA transfer interrupt request.
00374   */
00375 void BSP_SDRAM_DMA_IRQHandler(void)
00376 {
00377   HAL_DMA_IRQHandler(sdramHandle.hdma);
00378 }
00379 
00380 /**
00381   * @brief  Initializes SDRAM MSP.
00382   * @note   This function can be surcharged by application code.
00383   * @param  hsdram: pointer on SDRAM handle
00384   * @param  Params: pointer on additional configuration parameters, can be NULL.
00385   */
00386 __weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef  *hsdram, void *Params)
00387 {
00388   static DMA_HandleTypeDef dma_handle;
00389   GPIO_InitTypeDef gpio_init_structure;
00390 
00391   if(hsdram != (SDRAM_HandleTypeDef  *)NULL)
00392   {
00393     /* Enable FMC clock */
00394     __HAL_RCC_FMC_CLK_ENABLE();
00395 
00396     /* Enable chosen DMAx clock */
00397     __DMAx_CLK_ENABLE();
00398 
00399     /* Enable GPIOs clock */
00400     __HAL_RCC_GPIOC_CLK_ENABLE();
00401     __HAL_RCC_GPIOD_CLK_ENABLE();
00402     __HAL_RCC_GPIOE_CLK_ENABLE();
00403     __HAL_RCC_GPIOF_CLK_ENABLE();
00404     __HAL_RCC_GPIOG_CLK_ENABLE();
00405     __HAL_RCC_GPIOH_CLK_ENABLE();
00406     __HAL_RCC_GPIOI_CLK_ENABLE();
00407 
00408     /* Common GPIO configuration */
00409     gpio_init_structure.Mode      = GPIO_MODE_AF_PP;
00410     gpio_init_structure.Pull      = GPIO_PULLUP;
00411     gpio_init_structure.Speed     = GPIO_SPEED_FAST;
00412     gpio_init_structure.Alternate = GPIO_AF12_FMC;
00413 
00414     /* GPIOC configuration : PC0 is SDNWE */
00415     gpio_init_structure.Pin   = GPIO_PIN_0;
00416     HAL_GPIO_Init(GPIOC, &gpio_init_structure);
00417 
00418     /* GPIOD configuration */
00419     gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8| GPIO_PIN_9 | GPIO_PIN_10 |\
00420                                 GPIO_PIN_14 | GPIO_PIN_15;
00421 
00422 
00423     HAL_GPIO_Init(GPIOD, &gpio_init_structure);
00424 
00425     /* GPIOE configuration */
00426     gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\
00427                                 GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
00428                                 GPIO_PIN_15;
00429 
00430     HAL_GPIO_Init(GPIOE, &gpio_init_structure);
00431 
00432     /* GPIOF configuration */
00433     gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
00434                                 GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
00435                                 GPIO_PIN_15;
00436 
00437     HAL_GPIO_Init(GPIOF, &gpio_init_structure);
00438 
00439     /* GPIOG configuration */
00440     gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\
00441                                 GPIO_PIN_15;
00442     HAL_GPIO_Init(GPIOG, &gpio_init_structure);
00443 
00444     /* GPIOH configuration */
00445     gpio_init_structure.Pin   = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_8 | GPIO_PIN_9 |\
00446                                 GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
00447                                 GPIO_PIN_15;
00448     HAL_GPIO_Init(GPIOH, &gpio_init_structure);
00449 
00450     /* GPIOI configuration */
00451     gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 |\
00452                                 GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_9 | GPIO_PIN_10;
00453     HAL_GPIO_Init(GPIOI, &gpio_init_structure);
00454 
00455     /* Configure common DMA parameters */
00456     dma_handle.Init.Channel             = SDRAM_DMAx_CHANNEL;
00457     dma_handle.Init.Direction           = DMA_MEMORY_TO_MEMORY;
00458     dma_handle.Init.PeriphInc           = DMA_PINC_ENABLE;
00459     dma_handle.Init.MemInc              = DMA_MINC_ENABLE;
00460     dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
00461     dma_handle.Init.MemDataAlignment    = DMA_MDATAALIGN_WORD;
00462     dma_handle.Init.Mode                = DMA_NORMAL;
00463     dma_handle.Init.Priority            = DMA_PRIORITY_HIGH;
00464     dma_handle.Init.FIFOMode            = DMA_FIFOMODE_DISABLE;
00465     dma_handle.Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;
00466     dma_handle.Init.MemBurst            = DMA_MBURST_SINGLE;
00467     dma_handle.Init.PeriphBurst         = DMA_PBURST_SINGLE;
00468 
00469     dma_handle.Instance = SDRAM_DMAx_STREAM;
00470 
00471     /* Associate the DMA handle */
00472     __HAL_LINKDMA(hsdram, hdma, dma_handle);
00473 
00474     /* Deinitialize the stream for new transfer */
00475     HAL_DMA_DeInit(&dma_handle);
00476 
00477     /* Configure the DMA stream */
00478     HAL_DMA_Init(&dma_handle);
00479 
00480     /* NVIC configuration for DMA transfer complete interrupt */
00481     HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 5, 0);
00482     HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn);
00483 
00484   } /* of if(hsdram != (SDRAM_HandleTypeDef  *)NULL) */
00485 }
00486 
00487 /**
00488   * @brief  DeInitializes SDRAM MSP.
00489   * @note   This function can be surcharged by application code.
00490   * @param  hsdram: pointer on SDRAM handle
00491   * @param  Params: pointer on additional configuration parameters, can be NULL.
00492   */
00493 __weak void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef  *hsdram, void *Params)
00494 {
00495     static DMA_HandleTypeDef dma_handle;
00496 
00497     if(hsdram != (SDRAM_HandleTypeDef  *)NULL)
00498     {
00499       /* Disable NVIC configuration for DMA interrupt */
00500       HAL_NVIC_DisableIRQ(SDRAM_DMAx_IRQn);
00501 
00502       /* Deinitialize the stream for new transfer */
00503       dma_handle.Instance = SDRAM_DMAx_STREAM;
00504       HAL_DMA_DeInit(&dma_handle);
00505 
00506       /* DeInit GPIO pins can be done in the application
00507        (by surcharging this __weak function) */
00508 
00509       /* GPIO pins clock, FMC clock and DMA clock can be shut down in the application
00510        by surcharging this __weak function */
00511 
00512     } /* of if(hsdram != (SDRAM_HandleTypeDef  *)NULL) */
00513 }
00514 
00515 /**
00516   * @}
00517   */
00518 
00519 /**
00520   * @}
00521   */
00522 
00523 /**
00524   * @}
00525   */
00526 
00527 /**
00528   * @}
00529   */
00530 
00531 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/