steven niu / LPC1768_DMA

implement LPC1768 GPDMA API

Dependents:   LPC1768_DMA_implementation

Currently, only LPC1768 HAL level API have been implemented. You can also find the test code to test the m2p and m2m here http://mbed.org/users/steniu01/code/LPC1768_DMA_implementation/. The target is to implement the user side platform agnostic API to make it more easily to use DMA.

There are still quite a few things undone (list in priority order):

1. Implement user side API to provide platform agnostic user friendly API

2. Tidy up the codes and add more comments

3. Create more test cases

4. Fully test the codes using mbed sdk automated test suits

5. Implement LLI

LPC1768_dma.h@1:86b13bfcbe46, 2014-08-21 (annotated)

Committer:
steniu01
Date:
Thu Aug 21 00:03:00 2014 +0000
Revision:
1:86b13bfcbe46
Parent:
0:226ca65983a2 
first workable version

Who changed what in which revision?

UserRevisionLine numberNew contents of line
steniu01 1:86b13bfcbe46 1 #ifndef LPC1768_DMA_H
steniu01 1:86b13bfcbe46 2 #define LPC1768_DMA_H
steniu01 1:86b13bfcbe46 3
steniu01 1:86b13bfcbe46 4 #include "mbed.h"
steniu01 0:226ca65983a2 5 /**
steniu01 0:226ca65983a2 6 * @brief DMA Init structure definition
steniu01 0:226ca65983a2 7 */
steniu01 0:226ca65983a2 8 /*DMA channel control register*/
steniu01 0:226ca65983a2 9 #define DMA_CCxControl_TransferSize_Pos 0
steniu01 0:226ca65983a2 10 #define DMA_CCxControl_SBSize_Pos 12
steniu01 0:226ca65983a2 11 #define DMA_CCxControl_DBSize_Pos 15
steniu01 0:226ca65983a2 12 #define DMA_CCxControl_SWidth_Pos 18
steniu01 0:226ca65983a2 13 #define DMA_CCxControl_DWidth_Pos 21
steniu01 0:226ca65983a2 14 #define DMA_CCxControl_SI_Pos 26
steniu01 0:226ca65983a2 15 #define DMA_CCxControl_DI_Pos 27
steniu01 0:226ca65983a2 16 #define DMA_CCxControl_I_Pos 31
steniu01 0:226ca65983a2 17
steniu01 0:226ca65983a2 18 /*DMA Channel config register*/
steniu01 0:226ca65983a2 19 #define DMA_CCxConfig_E_Pos 0
steniu01 0:226ca65983a2 20 #define DMA_CCxConfig_SrcPeripheral_Pos 1
steniu01 0:226ca65983a2 21 #define DMA_CCxConfig_DestPeripheral_Pos 6
steniu01 0:226ca65983a2 22 #define DMA_CCxConfig_TransferType_Pos 11
steniu01 0:226ca65983a2 23 #define DMA_CCxConfig_IE_Pos 14
steniu01 0:226ca65983a2 24 #define DMA_CCxConfig_ITC_Pos 15
steniu01 0:226ca65983a2 25 #define DMA_CCxConfig_L_Pos 16
steniu01 0:226ca65983a2 26 #define DMA_CCxConfig_A_Pos 17
steniu01 0:226ca65983a2 27 #define DMA_CCxConfig_H_Pos 18
steniu01 0:226ca65983a2 28
steniu01 1:86b13bfcbe46 29 /*DMA Interrupt*/
steniu01 1:86b13bfcbe46 30 #define DMA_IE ((uint32_t)0x00004000)
steniu01 1:86b13bfcbe46 31 #define DMA_ITC ((uint32_t)0x00008000)
steniu01 1:86b13bfcbe46 32
steniu01 1:86b13bfcbe46 33 typedef enum
steniu01 1:86b13bfcbe46 34 {
steniu01 1:86b13bfcbe46 35 M2M = 0x00,
steniu01 1:86b13bfcbe46 36 M2P = 0x01,
steniu01 1:86b13bfcbe46 37 P2M = 0x02,
steniu01 1:86b13bfcbe46 38 P2P = 0x03
steniu01 1:86b13bfcbe46 39 } TransferType;
steniu01 0:226ca65983a2 40
steniu01 0:226ca65983a2 41
steniu01 1:86b13bfcbe46 42 typedef struct
steniu01 1:86b13bfcbe46 43 {
steniu01 1:86b13bfcbe46 44 uint32_t DestAddr;
steniu01 1:86b13bfcbe46 45 uint32_t SrcAddr;
steniu01 1:86b13bfcbe46 46 uint32_t next;
steniu01 1:86b13bfcbe46 47 uint32_t control;
steniu01 1:86b13bfcbe46 48 } DMA_LLI;
steniu01 0:226ca65983a2 49
steniu01 0:226ca65983a2 50 typedef struct
steniu01 0:226ca65983a2 51 {
steniu01 0:226ca65983a2 52 uint32_t DMA_DestAddr; /*!< Specifies the destination base address for DMAy Channelx. */
steniu01 0:226ca65983a2 53 uint32_t DMA_SrcAddr; /*!< Specifies the source base address for DMAy Channelx. */
steniu01 1:86b13bfcbe46 54 // DMA_LLI LLI; /UNDO *!< Specifies the next linked item */
steniu01 1:86b13bfcbe46 55 uint32_t DMA_TransferSize;/*!< Specifies the source transfer size */
steniu01 0:226ca65983a2 56 uint32_t DMA_SrcBurst; /*!< Specifies the source burst size */
steniu01 0:226ca65983a2 57 uint32_t DMA_DestBurst; /*!< Specifies the destination burst size */
steniu01 0:226ca65983a2 58 uint32_t DMA_SrcWidth; /*!< Specifies the source transfer width */
steniu01 0:226ca65983a2 59 uint32_t DMA_DestWidth; /*!< Specifies the destination transfer width */
steniu01 0:226ca65983a2 60 uint32_t DMA_SrcInc; /*!< Specifies whether the source is incremented or not */
steniu01 0:226ca65983a2 61 uint32_t DMA_DestInc; /*!< Specifies whether the destination is incremented or not */
steniu01 0:226ca65983a2 62 uint32_t DMA_TermInt; /*!< Specifies whether the terminal count interrupt enabled or not */
steniu01 0:226ca65983a2 63
steniu01 0:226ca65983a2 64 /*!< Specifies the features set by channel config register */
steniu01 0:226ca65983a2 65 uint32_t DMA_SrcPeripheral;
steniu01 0:226ca65983a2 66 uint32_t DMA_DestPeripheral;
steniu01 1:86b13bfcbe46 67 TransferType DMA_TransferType;
steniu01 1:86b13bfcbe46 68 } DMA_InitTypeDef;
steniu01 0:226ca65983a2 69
steniu01 1:86b13bfcbe46 70
steniu01 0:226ca65983a2 71
steniu01 0:226ca65983a2 72 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
steniu01 1:86b13bfcbe46 73 typedef enum {COUNTER, ERR} DMA_IT;
steniu01 1:86b13bfcbe46 74
steniu01 1:86b13bfcbe46 75
steniu01 1:86b13bfcbe46 76 void DMA_init(LPC_GPDMACH_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
steniu01 1:86b13bfcbe46 77 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
steniu01 1:86b13bfcbe46 78 void DMA_Cmd(LPC_GPDMACH_TypeDef* DMAy_Channelx, FunctionalState NewState);
steniu01 1:86b13bfcbe46 79 void DMA_ITConfig (LPC_GPDMACH_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
steniu01 1:86b13bfcbe46 80 void DMA_ClearITPendingBit(LPC_GPDMACH_TypeDef* DMAy_Channelx, uint32_t DMA_IT);
steniu01 1:86b13bfcbe46 81 uint32_t DMA_EnabledChannels(void);
steniu01 1:86b13bfcbe46 82 bool DMA_ChannelActive (LPC_GPDMACH_TypeDef* DMAy_Channelx);
steniu01 1:86b13bfcbe46 83
steniu01 1:86b13bfcbe46 84 #endif