steven niu / LPC1768_DMA

implement LPC1768 GPDMA API

Dependents:   LPC1768_DMA_implementation

Currently, only LPC1768 HAL level API have been implemented. You can also find the test code to test the m2p and m2m here http://mbed.org/users/steniu01/code/LPC1768_DMA_implementation/. The target is to implement the user side platform agnostic API to make it more easily to use DMA.

There are still quite a few things undone (list in priority order):

1. Implement user side API to provide platform agnostic user friendly API

2. Tidy up the codes and add more comments

3. Create more test cases

4. Fully test the codes using mbed sdk automated test suits

5. Implement LLI

LPC1768_dma.h@0:226ca65983a2, 2014-08-14 (annotated)

Committer:
steniu01
Date:
Thu Aug 14 01:58:45 2014 +0000
Revision:
0:226ca65983a2
Child:
1:86b13bfcbe46
first version

Who changed what in which revision?

UserRevisionLine numberNew contents of line
steniu01 0:226ca65983a2 1 #ifdef TARGET_LPC1768
steniu01 0:226ca65983a2 2 /**
steniu01 0:226ca65983a2 3 * @brief DMA Init structure definition
steniu01 0:226ca65983a2 4 */
steniu01 0:226ca65983a2 5 /*DMA channel control register*/
steniu01 0:226ca65983a2 6 #define DMA_CCxControl_TransferSize_Pos 0
steniu01 0:226ca65983a2 7 #define DMA_CCxControl_SBSize_Pos 12
steniu01 0:226ca65983a2 8 #define DMA_CCxControl_DBSize_Pos 15
steniu01 0:226ca65983a2 9 #define DMA_CCxControl_SWidth_Pos 18
steniu01 0:226ca65983a2 10 #define DMA_CCxControl_DWidth_Pos 21
steniu01 0:226ca65983a2 11 #define DMA_CCxControl_SI_Pos 26
steniu01 0:226ca65983a2 12 #define DMA_CCxControl_DI_Pos 27
steniu01 0:226ca65983a2 13 #define DMA_CCxControl_I_Pos 31
steniu01 0:226ca65983a2 14
steniu01 0:226ca65983a2 15 /*DMA Channel config register*/
steniu01 0:226ca65983a2 16 #define DMA_CCxConfig_E_Pos 0
steniu01 0:226ca65983a2 17 #define DMA_CCxConfig_SrcPeripheral_Pos 1
steniu01 0:226ca65983a2 18 #define DMA_CCxConfig_DestPeripheral_Pos 6
steniu01 0:226ca65983a2 19 #define DMA_CCxConfig_TransferType_Pos 11
steniu01 0:226ca65983a2 20 #define DMA_CCxConfig_IE_Pos 14
steniu01 0:226ca65983a2 21 #define DMA_CCxConfig_ITC_Pos 15
steniu01 0:226ca65983a2 22 #define DMA_CCxConfig_L_Pos 16
steniu01 0:226ca65983a2 23 #define DMA_CCxConfig_A_Pos 17
steniu01 0:226ca65983a2 24 #define DMA_CCxConfig_H_Pos 18
steniu01 0:226ca65983a2 25
steniu01 0:226ca65983a2 26
steniu01 0:226ca65983a2 27
steniu01 0:226ca65983a2 28
steniu01 0:226ca65983a2 29 typedef struct
steniu01 0:226ca65983a2 30 {
steniu01 0:226ca65983a2 31 uint32_t DMA_DestAddr; /*!< Specifies the destination base address for DMAy Channelx. */
steniu01 0:226ca65983a2 32 uint32_t DMA_SrcAddr; /*!< Specifies the source base address for DMAy Channelx. */
steniu01 0:226ca65983a2 33 DMA_LLI LLI; /*!< Specifies the next linked item */
steniu01 0:226ca65983a2 34 uint32_t DMA_TransSize;/*!< Specifies the source transfer size */
steniu01 0:226ca65983a2 35 uint32_t DMA_SrcBurst; /*!< Specifies the source burst size */
steniu01 0:226ca65983a2 36 uint32_t DMA_DestBurst; /*!< Specifies the destination burst size */
steniu01 0:226ca65983a2 37 uint32_t DMA_SrcWidth; /*!< Specifies the source transfer width */
steniu01 0:226ca65983a2 38 uint32_t DMA_DestWidth; /*!< Specifies the destination transfer width */
steniu01 0:226ca65983a2 39 uint32_t DMA_SrcInc; /*!< Specifies whether the source is incremented or not */
steniu01 0:226ca65983a2 40 uint32_t DMA_DestInc; /*!< Specifies whether the destination is incremented or not */
steniu01 0:226ca65983a2 41 uint32_t DMA_TermInt; /*!< Specifies whether the terminal count interrupt enabled or not */
steniu01 0:226ca65983a2 42
steniu01 0:226ca65983a2 43 /*!< Specifies the features set by channel config register */
steniu01 0:226ca65983a2 44 uint32_t DMA_SrcPeripheral;
steniu01 0:226ca65983a2 45 uint32_t DMA_DestPeripheral;
steniu01 0:226ca65983a2 46 uint32_t DMA_TransferType;
steniu01 0:226ca65983a2 47
steniu01 0:226ca65983a2 48 }DMA_InitTypeDef;
steniu01 0:226ca65983a2 49
steniu01 0:226ca65983a2 50 typedef struct
steniu01 0:226ca65983a2 51 {
steniu01 0:226ca65983a2 52 uint32_t DestAddr;
steniu01 0:226ca65983a2 53 uint32_t SrcAddr;
steniu01 0:226ca65983a2 54 uint32_t next;
steniu01 0:226ca65983a2 55 uint32_t control;
steniu01 0:226ca65983a2 56
steniu01 0:226ca65983a2 57 }DMA_LLI;
steniu01 0:226ca65983a2 58
steniu01 0:226ca65983a2 59 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
steniu01 0:226ca65983a2 60 #endif