steven niu / LPC1768_DMA

implement LPC1768 GPDMA API

Dependents:   LPC1768_DMA_implementation

Currently, only LPC1768 HAL level API have been implemented. You can also find the test code to test the m2p and m2m here http://mbed.org/users/steniu01/code/LPC1768_DMA_implementation/. The target is to implement the user side platform agnostic API to make it more easily to use DMA.

There are still quite a few things undone (list in priority order):

1. Implement user side API to provide platform agnostic user friendly API

2. Tidy up the codes and add more comments

3. Create more test cases

4. Fully test the codes using mbed sdk automated test suits

5. Implement LLI

user_LPC17xx.h@0:226ca65983a2, 2014-08-14 (annotated)

Committer:
steniu01
Date:
Thu Aug 14 01:58:45 2014 +0000
Revision:
0:226ca65983a2
first version

Who changed what in which revision?

UserRevisionLine numberNew contents of line
steniu01 0:226ca65983a2 1
steniu01 0:226ca65983a2 2 /** @defgroup DMA_Exported_Constants
steniu01 0:226ca65983a2 3 * @{
steniu01 0:226ca65983a2 4 */
steniu01 0:226ca65983a2 5
steniu01 0:226ca65983a2 6 #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
steniu01 0:226ca65983a2 7 ((PERIPH) == DMA1_Channel2) || \
steniu01 0:226ca65983a2 8 ((PERIPH) == DMA1_Channel3) || \
steniu01 0:226ca65983a2 9 ((PERIPH) == DMA1_Channel4) || \
steniu01 0:226ca65983a2 10 ((PERIPH) == DMA1_Channel5) || \
steniu01 0:226ca65983a2 11 ((PERIPH) == DMA1_Channel6) || \
steniu01 0:226ca65983a2 12 ((PERIPH) == DMA1_Channel7) || \
steniu01 0:226ca65983a2 13 ((PERIPH) == DMA2_Channel1) || \
steniu01 0:226ca65983a2 14 ((PERIPH) == DMA2_Channel2) || \
steniu01 0:226ca65983a2 15 ((PERIPH) == DMA2_Channel3) || \
steniu01 0:226ca65983a2 16 ((PERIPH) == DMA2_Channel4) || \
steniu01 0:226ca65983a2 17 ((PERIPH) == DMA2_Channel5))
steniu01 0:226ca65983a2 18
steniu01 0:226ca65983a2 19 /** @defgroup DMA_data_transfer_direction
steniu01 0:226ca65983a2 20 * @{
steniu01 0:226ca65983a2 21 */
steniu01 0:226ca65983a2 22
steniu01 0:226ca65983a2 23 #define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
steniu01 0:226ca65983a2 24 #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
steniu01 0:226ca65983a2 25 #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
steniu01 0:226ca65983a2 26 ((DIR) == DMA_DIR_PeripheralSRC))
steniu01 0:226ca65983a2 27 /**
steniu01 0:226ca65983a2 28 * @}
steniu01 0:226ca65983a2 29 */
steniu01 0:226ca65983a2 30
steniu01 0:226ca65983a2 31
steniu01 0:226ca65983a2 32
steniu01 0:226ca65983a2 33 /** @defgroup DMA_peripheral_incremented_mode
steniu01 0:226ca65983a2 34 * @{
steniu01 0:226ca65983a2 35 */
steniu01 0:226ca65983a2 36
steniu01 0:226ca65983a2 37 #define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
steniu01 0:226ca65983a2 38 #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
steniu01 0:226ca65983a2 39 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
steniu01 0:226ca65983a2 40 ((STATE) == DMA_PeripheralInc_Disable))
steniu01 0:226ca65983a2 41 /**
steniu01 0:226ca65983a2 42 * @}
steniu01 0:226ca65983a2 43 */
steniu01 0:226ca65983a2 44
steniu01 0:226ca65983a2 45 /** @defgroup DMA_memory_incremented_mode
steniu01 0:226ca65983a2 46 * @{
steniu01 0:226ca65983a2 47 */
steniu01 0:226ca65983a2 48
steniu01 0:226ca65983a2 49 #define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
steniu01 0:226ca65983a2 50 #define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
steniu01 0:226ca65983a2 51 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
steniu01 0:226ca65983a2 52 ((STATE) == DMA_MemoryInc_Disable))
steniu01 0:226ca65983a2 53 /**
steniu01 0:226ca65983a2 54 * @}
steniu01 0:226ca65983a2 55 */
steniu01 0:226ca65983a2 56
steniu01 0:226ca65983a2 57 /** @defgroup DMA_peripheral_data_size
steniu01 0:226ca65983a2 58 * @{
steniu01 0:226ca65983a2 59 */
steniu01 0:226ca65983a2 60
steniu01 0:226ca65983a2 61 #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
steniu01 0:226ca65983a2 62 #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
steniu01 0:226ca65983a2 63 #define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
steniu01 0:226ca65983a2 64 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
steniu01 0:226ca65983a2 65 ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
steniu01 0:226ca65983a2 66 ((SIZE) == DMA_PeripheralDataSize_Word))
steniu01 0:226ca65983a2 67 /**
steniu01 0:226ca65983a2 68 * @}
steniu01 0:226ca65983a2 69 */
steniu01 0:226ca65983a2 70
steniu01 0:226ca65983a2 71 /** @defgroup DMA_memory_data_size
steniu01 0:226ca65983a2 72 * @{
steniu01 0:226ca65983a2 73 */
steniu01 0:226ca65983a2 74
steniu01 0:226ca65983a2 75 #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
steniu01 0:226ca65983a2 76 #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
steniu01 0:226ca65983a2 77 #define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
steniu01 0:226ca65983a2 78 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
steniu01 0:226ca65983a2 79 ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
steniu01 0:226ca65983a2 80 ((SIZE) == DMA_MemoryDataSize_Word))
steniu01 0:226ca65983a2 81 /**
steniu01 0:226ca65983a2 82 * @}
steniu01 0:226ca65983a2 83 */
steniu01 0:226ca65983a2 84
steniu01 0:226ca65983a2 85 /** @defgroup DMA_circular_normal_mode
steniu01 0:226ca65983a2 86 * @{
steniu01 0:226ca65983a2 87 */
steniu01 0:226ca65983a2 88
steniu01 0:226ca65983a2 89 #define DMA_Mode_Circular ((uint32_t)0x00000020)
steniu01 0:226ca65983a2 90 #define DMA_Mode_Normal ((uint32_t)0x00000000)
steniu01 0:226ca65983a2 91 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
steniu01 0:226ca65983a2 92 /**
steniu01 0:226ca65983a2 93 * @}
steniu01 0:226ca65983a2 94 */
steniu01 0:226ca65983a2 95
steniu01 0:226ca65983a2 96 /** @defgroup DMA_priority_level
steniu01 0:226ca65983a2 97 * @{
steniu01 0:226ca65983a2 98 */
steniu01 0:226ca65983a2 99
steniu01 0:226ca65983a2 100 #define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
steniu01 0:226ca65983a2 101 #define DMA_Priority_High ((uint32_t)0x00002000)
steniu01 0:226ca65983a2 102 #define DMA_Priority_Medium ((uint32_t)0x00001000)
steniu01 0:226ca65983a2 103 #define DMA_Priority_Low ((uint32_t)0x00000000)
steniu01 0:226ca65983a2 104 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
steniu01 0:226ca65983a2 105 ((PRIORITY) == DMA_Priority_High) || \
steniu01 0:226ca65983a2 106 ((PRIORITY) == DMA_Priority_Medium) || \
steniu01 0:226ca65983a2 107 ((PRIORITY) == DMA_Priority_Low))
steniu01 0:226ca65983a2 108 /**
steniu01 0:226ca65983a2 109 * @}
steniu01 0:226ca65983a2 110 */
steniu01 0:226ca65983a2 111
steniu01 0:226ca65983a2 112 /** @defgroup DMA_memory_to_memory
steniu01 0:226ca65983a2 113 * @{
steniu01 0:226ca65983a2 114 */
steniu01 0:226ca65983a2 115
steniu01 0:226ca65983a2 116 #define DMA_M2M_Enable ((uint32_t)0x00004000)
steniu01 0:226ca65983a2 117 #define DMA_M2M_Disable ((uint32_t)0x00000000)
steniu01 0:226ca65983a2 118 #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
steniu01 0:226ca65983a2 119
steniu01 0:226ca65983a2 120 /**
steniu01 0:226ca65983a2 121 * @}
steniu01 0:226ca65983a2 122 */