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LPC_DMA_COMMON_T Struct Reference
[CHIP: LPC11u6x DMA Controller driver]
DMA Controller shared registers structure. More...
#include <dma_11u6x.h>
Data Fields | |
| __IO uint32_t | ENABLESET |
| __O uint32_t | ENABLECLR |
| __I uint32_t | ACTIVE |
| __I uint32_t | BUSY |
| __IO uint32_t | ERRINT |
| __IO uint32_t | INTENSET |
| __O uint32_t | INTENCLR |
| __IO uint32_t | INTA |
| __IO uint32_t | INTB |
| __O uint32_t | SETVALID |
| __O uint32_t | SETTRIG |
| __O uint32_t | ABORT |
Detailed Description
DMA Controller shared registers structure.
Definition at line 50 of file dma_11u6x.h.
Field Documentation
| __O uint32_t ABORT |
DMA Channel Abort control for all DMA channels
Definition at line 73 of file dma_11u6x.h.
| __I uint32_t ACTIVE |
DMA Channel Active status for all DMA channels
Definition at line 55 of file dma_11u6x.h.
| __I uint32_t BUSY |
DMA Channel Busy status for all DMA channels
Definition at line 57 of file dma_11u6x.h.
| __O uint32_t ENABLECLR |
DMA Channel Enable Clear for all DMA channels
Definition at line 53 of file dma_11u6x.h.
| __IO uint32_t ENABLESET |
< DMA shared registers structure DMA Channel Enable read and Set for all DMA channels
Definition at line 51 of file dma_11u6x.h.
| __IO uint32_t ERRINT |
DMA Error Interrupt status for all DMA channels
Definition at line 59 of file dma_11u6x.h.
| __IO uint32_t INTA |
DMA Interrupt A status for all DMA channels
Definition at line 65 of file dma_11u6x.h.
| __IO uint32_t INTB |
DMA Interrupt B status for all DMA channels
Definition at line 67 of file dma_11u6x.h.
| __O uint32_t INTENCLR |
DMA Interrupt Enable Clear for all DMA channels
Definition at line 63 of file dma_11u6x.h.
| __IO uint32_t INTENSET |
DMA Interrupt Enable read and Set for all DMA channels
Definition at line 61 of file dma_11u6x.h.
| __O uint32_t SETTRIG |
DMA Set Trigger control bits for all DMA channels
Definition at line 71 of file dma_11u6x.h.
| __O uint32_t SETVALID |
DMA Set ValidPending control bits for all DMA channels
Definition at line 69 of file dma_11u6x.h.
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