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PokittoLib is the library needed for programming the Pokitto DIY game console (www.pokitto.com)

mbed-pokitto/targets/cmsis/core_cm7.h@15:0bbe8f6fae32, 2017-10-18 (annotated)

Committer:: spinal
Date:: Wed Oct 18 14:47:54 2017 +0000
Revision:: 15:0bbe8f6fae32
Parent:: 6:ea7377f3d1af

direct lcd stuff used by sensitive

Who changed what in which revision?

User	Revision	Line number	New contents of line
Pokitto	6:ea7377f3d1af	1	/************************************************************************//
Pokitto	6:ea7377f3d1af	2	* @file core_cm7.h
Pokitto	6:ea7377f3d1af	3	* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
Pokitto	6:ea7377f3d1af	4	* @version V4.10
Pokitto	6:ea7377f3d1af	5	* @date 18. March 2015
Pokitto	6:ea7377f3d1af	6	*
Pokitto	6:ea7377f3d1af	7	* @note
Pokitto	6:ea7377f3d1af	8	*
Pokitto	6:ea7377f3d1af	9	******************************************************************************/
Pokitto	6:ea7377f3d1af	10	/* Copyright (c) 2009 - 2015 ARM LIMITED
Pokitto	6:ea7377f3d1af	11
Pokitto	6:ea7377f3d1af	12	All rights reserved.
Pokitto	6:ea7377f3d1af	13	Redistribution and use in source and binary forms, with or without
Pokitto	6:ea7377f3d1af	14	modification, are permitted provided that the following conditions are met:
Pokitto	6:ea7377f3d1af	15	- Redistributions of source code must retain the above copyright
Pokitto	6:ea7377f3d1af	16	notice, this list of conditions and the following disclaimer.
Pokitto	6:ea7377f3d1af	17	- Redistributions in binary form must reproduce the above copyright
Pokitto	6:ea7377f3d1af	18	notice, this list of conditions and the following disclaimer in the
Pokitto	6:ea7377f3d1af	19	documentation and/or other materials provided with the distribution.
Pokitto	6:ea7377f3d1af	20	- Neither the name of ARM nor the names of its contributors may be used
Pokitto	6:ea7377f3d1af	21	to endorse or promote products derived from this software without
Pokitto	6:ea7377f3d1af	22	specific prior written permission.
Pokitto	6:ea7377f3d1af	23	*
Pokitto	6:ea7377f3d1af	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Pokitto	6:ea7377f3d1af	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Pokitto	6:ea7377f3d1af	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Pokitto	6:ea7377f3d1af	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Pokitto	6:ea7377f3d1af	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Pokitto	6:ea7377f3d1af	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Pokitto	6:ea7377f3d1af	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Pokitto	6:ea7377f3d1af	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Pokitto	6:ea7377f3d1af	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Pokitto	6:ea7377f3d1af	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Pokitto	6:ea7377f3d1af	34	POSSIBILITY OF SUCH DAMAGE.
Pokitto	6:ea7377f3d1af	35	---------------------------------------------------------------------------*/
Pokitto	6:ea7377f3d1af	36
Pokitto	6:ea7377f3d1af	37
Pokitto	6:ea7377f3d1af	38	#if defined ( __ICCARM__ )
Pokitto	6:ea7377f3d1af	39	#pragma system_include /* treat file as system include file for MISRA check */
Pokitto	6:ea7377f3d1af	40	#endif
Pokitto	6:ea7377f3d1af	41
Pokitto	6:ea7377f3d1af	42	#ifndef __CORE_CM7_H_GENERIC
Pokitto	6:ea7377f3d1af	43	#define __CORE_CM7_H_GENERIC
Pokitto	6:ea7377f3d1af	44
Pokitto	6:ea7377f3d1af	45	#ifdef __cplusplus
Pokitto	6:ea7377f3d1af	46	extern "C" {
Pokitto	6:ea7377f3d1af	47	#endif
Pokitto	6:ea7377f3d1af	48
Pokitto	6:ea7377f3d1af	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Pokitto	6:ea7377f3d1af	50	CMSIS violates the following MISRA-C:2004 rules:
Pokitto	6:ea7377f3d1af	51
Pokitto	6:ea7377f3d1af	52	\li Required Rule 8.5, object/function definition in header file.<br>
Pokitto	6:ea7377f3d1af	53	Function definitions in header files are used to allow 'inlining'.
Pokitto	6:ea7377f3d1af	54
Pokitto	6:ea7377f3d1af	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Pokitto	6:ea7377f3d1af	56	Unions are used for effective representation of core registers.
Pokitto	6:ea7377f3d1af	57
Pokitto	6:ea7377f3d1af	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
Pokitto	6:ea7377f3d1af	59	Function-like macros are used to allow more efficient code.
Pokitto	6:ea7377f3d1af	60	*/
Pokitto	6:ea7377f3d1af	61
Pokitto	6:ea7377f3d1af	62
Pokitto	6:ea7377f3d1af	63	/*******************************************************************************
Pokitto	6:ea7377f3d1af	64	* CMSIS definitions
Pokitto	6:ea7377f3d1af	65	******************************************************************************/
Pokitto	6:ea7377f3d1af	66	/** \ingroup Cortex_M7
Pokitto	6:ea7377f3d1af	67	@{
Pokitto	6:ea7377f3d1af	68	*/
Pokitto	6:ea7377f3d1af	69
Pokitto	6:ea7377f3d1af	70	/* CMSIS CM7 definitions */
Pokitto	6:ea7377f3d1af	71	#define __CM7_CMSIS_VERSION_MAIN (0x04) /!< [31:16] CMSIS HAL main version /
Pokitto	6:ea7377f3d1af	72	#define __CM7_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
Pokitto	6:ea7377f3d1af	73	#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) \| \
Pokitto	6:ea7377f3d1af	74	__CM7_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
Pokitto	6:ea7377f3d1af	75
Pokitto	6:ea7377f3d1af	76	#define __CORTEX_M (0x07) /!< Cortex-M Core /
Pokitto	6:ea7377f3d1af	77
Pokitto	6:ea7377f3d1af	78
Pokitto	6:ea7377f3d1af	79	#if defined ( __CC_ARM )
Pokitto	6:ea7377f3d1af	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
Pokitto	6:ea7377f3d1af	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
Pokitto	6:ea7377f3d1af	82	#define __STATIC_INLINE static __inline
Pokitto	6:ea7377f3d1af	83
Pokitto	6:ea7377f3d1af	84	#elif defined ( __GNUC__ )
Pokitto	6:ea7377f3d1af	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
Pokitto	6:ea7377f3d1af	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
Pokitto	6:ea7377f3d1af	87	#define __STATIC_INLINE static inline
Pokitto	6:ea7377f3d1af	88
Pokitto	6:ea7377f3d1af	89	#elif defined ( __ICCARM__ )
Pokitto	6:ea7377f3d1af	90	#define __ASM __asm /!< asm keyword for IAR Compiler /
Pokitto	6:ea7377f3d1af	91	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
Pokitto	6:ea7377f3d1af	92	#define __STATIC_INLINE static inline
Pokitto	6:ea7377f3d1af	93
Pokitto	6:ea7377f3d1af	94	#elif defined ( __TMS470__ )
Pokitto	6:ea7377f3d1af	95	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
Pokitto	6:ea7377f3d1af	96	#define __STATIC_INLINE static inline
Pokitto	6:ea7377f3d1af	97
Pokitto	6:ea7377f3d1af	98	#elif defined ( __TASKING__ )
Pokitto	6:ea7377f3d1af	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
Pokitto	6:ea7377f3d1af	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
Pokitto	6:ea7377f3d1af	101	#define __STATIC_INLINE static inline
Pokitto	6:ea7377f3d1af	102
Pokitto	6:ea7377f3d1af	103	#elif defined ( __CSMC__ )
Pokitto	6:ea7377f3d1af	104	#define __packed
Pokitto	6:ea7377f3d1af	105	#define __ASM _asm /!< asm keyword for COSMIC Compiler /
Pokitto	6:ea7377f3d1af	106	#define __INLINE inline /use -pc99 on compile line !< inline keyword for COSMIC Compiler /
Pokitto	6:ea7377f3d1af	107	#define __STATIC_INLINE static inline
Pokitto	6:ea7377f3d1af	108
Pokitto	6:ea7377f3d1af	109	#endif
Pokitto	6:ea7377f3d1af	110
Pokitto	6:ea7377f3d1af	111	/** __FPU_USED indicates whether an FPU is used or not.
Pokitto	6:ea7377f3d1af	112	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
Pokitto	6:ea7377f3d1af	113	*/
Pokitto	6:ea7377f3d1af	114	#if defined ( __CC_ARM )
Pokitto	6:ea7377f3d1af	115	#if defined __TARGET_FPU_VFP
Pokitto	6:ea7377f3d1af	116	#if (__FPU_PRESENT == 1)
Pokitto	6:ea7377f3d1af	117	#define __FPU_USED 1
Pokitto	6:ea7377f3d1af	118	#else
Pokitto	6:ea7377f3d1af	119	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Pokitto	6:ea7377f3d1af	120	#define __FPU_USED 0
Pokitto	6:ea7377f3d1af	121	#endif
Pokitto	6:ea7377f3d1af	122	#else
Pokitto	6:ea7377f3d1af	123	#define __FPU_USED 0
Pokitto	6:ea7377f3d1af	124	#endif
Pokitto	6:ea7377f3d1af	125
Pokitto	6:ea7377f3d1af	126	#elif defined ( __GNUC__ )
Pokitto	6:ea7377f3d1af	127	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
Pokitto	6:ea7377f3d1af	128	#if (__FPU_PRESENT == 1)
Pokitto	6:ea7377f3d1af	129	#define __FPU_USED 1
Pokitto	6:ea7377f3d1af	130	#else
Pokitto	6:ea7377f3d1af	131	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Pokitto	6:ea7377f3d1af	132	#define __FPU_USED 0
Pokitto	6:ea7377f3d1af	133	#endif
Pokitto	6:ea7377f3d1af	134	#else
Pokitto	6:ea7377f3d1af	135	#define __FPU_USED 0
Pokitto	6:ea7377f3d1af	136	#endif
Pokitto	6:ea7377f3d1af	137
Pokitto	6:ea7377f3d1af	138	#elif defined ( __ICCARM__ )
Pokitto	6:ea7377f3d1af	139	#if defined __ARMVFP__
Pokitto	6:ea7377f3d1af	140	#if (__FPU_PRESENT == 1)
Pokitto	6:ea7377f3d1af	141	#define __FPU_USED 1
Pokitto	6:ea7377f3d1af	142	#else
Pokitto	6:ea7377f3d1af	143	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Pokitto	6:ea7377f3d1af	144	#define __FPU_USED 0
Pokitto	6:ea7377f3d1af	145	#endif
Pokitto	6:ea7377f3d1af	146	#else
Pokitto	6:ea7377f3d1af	147	#define __FPU_USED 0
Pokitto	6:ea7377f3d1af	148	#endif
Pokitto	6:ea7377f3d1af	149
Pokitto	6:ea7377f3d1af	150	#elif defined ( __TMS470__ )
Pokitto	6:ea7377f3d1af	151	#if defined __TI_VFP_SUPPORT__
Pokitto	6:ea7377f3d1af	152	#if (__FPU_PRESENT == 1)
Pokitto	6:ea7377f3d1af	153	#define __FPU_USED 1
Pokitto	6:ea7377f3d1af	154	#else
Pokitto	6:ea7377f3d1af	155	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Pokitto	6:ea7377f3d1af	156	#define __FPU_USED 0
Pokitto	6:ea7377f3d1af	157	#endif
Pokitto	6:ea7377f3d1af	158	#else
Pokitto	6:ea7377f3d1af	159	#define __FPU_USED 0
Pokitto	6:ea7377f3d1af	160	#endif
Pokitto	6:ea7377f3d1af	161
Pokitto	6:ea7377f3d1af	162	#elif defined ( __TASKING__ )
Pokitto	6:ea7377f3d1af	163	#if defined __FPU_VFP__
Pokitto	6:ea7377f3d1af	164	#if (__FPU_PRESENT == 1)
Pokitto	6:ea7377f3d1af	165	#define __FPU_USED 1
Pokitto	6:ea7377f3d1af	166	#else
Pokitto	6:ea7377f3d1af	167	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Pokitto	6:ea7377f3d1af	168	#define __FPU_USED 0
Pokitto	6:ea7377f3d1af	169	#endif
Pokitto	6:ea7377f3d1af	170	#else
Pokitto	6:ea7377f3d1af	171	#define __FPU_USED 0
Pokitto	6:ea7377f3d1af	172	#endif
Pokitto	6:ea7377f3d1af	173
Pokitto	6:ea7377f3d1af	174	#elif defined ( __CSMC__ ) /* Cosmic */
Pokitto	6:ea7377f3d1af	175	#if ( __CSMC__ & 0x400) // FPU present for parser
Pokitto	6:ea7377f3d1af	176	#if (__FPU_PRESENT == 1)
Pokitto	6:ea7377f3d1af	177	#define __FPU_USED 1
Pokitto	6:ea7377f3d1af	178	#else
Pokitto	6:ea7377f3d1af	179	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Pokitto	6:ea7377f3d1af	180	#define __FPU_USED 0
Pokitto	6:ea7377f3d1af	181	#endif
Pokitto	6:ea7377f3d1af	182	#else
Pokitto	6:ea7377f3d1af	183	#define __FPU_USED 0
Pokitto	6:ea7377f3d1af	184	#endif
Pokitto	6:ea7377f3d1af	185	#endif
Pokitto	6:ea7377f3d1af	186
Pokitto	6:ea7377f3d1af	187	#include <stdint.h> /* standard types definitions */
Pokitto	6:ea7377f3d1af	188	#include <core_cmInstr.h> /* Core Instruction Access */
Pokitto	6:ea7377f3d1af	189	#include <core_cmFunc.h> /* Core Function Access */
Pokitto	6:ea7377f3d1af	190	#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
Pokitto	6:ea7377f3d1af	191
Pokitto	6:ea7377f3d1af	192	#ifdef __cplusplus
Pokitto	6:ea7377f3d1af	193	}
Pokitto	6:ea7377f3d1af	194	#endif
Pokitto	6:ea7377f3d1af	195
Pokitto	6:ea7377f3d1af	196	#endif /* __CORE_CM7_H_GENERIC */
Pokitto	6:ea7377f3d1af	197
Pokitto	6:ea7377f3d1af	198	#ifndef __CMSIS_GENERIC
Pokitto	6:ea7377f3d1af	199
Pokitto	6:ea7377f3d1af	200	#ifndef __CORE_CM7_H_DEPENDANT
Pokitto	6:ea7377f3d1af	201	#define __CORE_CM7_H_DEPENDANT
Pokitto	6:ea7377f3d1af	202
Pokitto	6:ea7377f3d1af	203	#ifdef __cplusplus
Pokitto	6:ea7377f3d1af	204	extern "C" {
Pokitto	6:ea7377f3d1af	205	#endif
Pokitto	6:ea7377f3d1af	206
Pokitto	6:ea7377f3d1af	207	/* check device defines and use defaults */
Pokitto	6:ea7377f3d1af	208	#if defined __CHECK_DEVICE_DEFINES
Pokitto	6:ea7377f3d1af	209	#ifndef __CM7_REV
Pokitto	6:ea7377f3d1af	210	#define __CM7_REV 0x0000
Pokitto	6:ea7377f3d1af	211	#warning "__CM7_REV not defined in device header file; using default!"
Pokitto	6:ea7377f3d1af	212	#endif
Pokitto	6:ea7377f3d1af	213
Pokitto	6:ea7377f3d1af	214	#ifndef __FPU_PRESENT
Pokitto	6:ea7377f3d1af	215	#define __FPU_PRESENT 0
Pokitto	6:ea7377f3d1af	216	#warning "__FPU_PRESENT not defined in device header file; using default!"
Pokitto	6:ea7377f3d1af	217	#endif
Pokitto	6:ea7377f3d1af	218
Pokitto	6:ea7377f3d1af	219	#ifndef __MPU_PRESENT
Pokitto	6:ea7377f3d1af	220	#define __MPU_PRESENT 0
Pokitto	6:ea7377f3d1af	221	#warning "__MPU_PRESENT not defined in device header file; using default!"
Pokitto	6:ea7377f3d1af	222	#endif
Pokitto	6:ea7377f3d1af	223
Pokitto	6:ea7377f3d1af	224	#ifndef __ICACHE_PRESENT
Pokitto	6:ea7377f3d1af	225	#define __ICACHE_PRESENT 0
Pokitto	6:ea7377f3d1af	226	#warning "__ICACHE_PRESENT not defined in device header file; using default!"
Pokitto	6:ea7377f3d1af	227	#endif
Pokitto	6:ea7377f3d1af	228
Pokitto	6:ea7377f3d1af	229	#ifndef __DCACHE_PRESENT
Pokitto	6:ea7377f3d1af	230	#define __DCACHE_PRESENT 0
Pokitto	6:ea7377f3d1af	231	#warning "__DCACHE_PRESENT not defined in device header file; using default!"
Pokitto	6:ea7377f3d1af	232	#endif
Pokitto	6:ea7377f3d1af	233
Pokitto	6:ea7377f3d1af	234	#ifndef __DTCM_PRESENT
Pokitto	6:ea7377f3d1af	235	#define __DTCM_PRESENT 0
Pokitto	6:ea7377f3d1af	236	#warning "__DTCM_PRESENT not defined in device header file; using default!"
Pokitto	6:ea7377f3d1af	237	#endif
Pokitto	6:ea7377f3d1af	238
Pokitto	6:ea7377f3d1af	239	#ifndef __NVIC_PRIO_BITS
Pokitto	6:ea7377f3d1af	240	#define __NVIC_PRIO_BITS 3
Pokitto	6:ea7377f3d1af	241	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Pokitto	6:ea7377f3d1af	242	#endif
Pokitto	6:ea7377f3d1af	243
Pokitto	6:ea7377f3d1af	244	#ifndef __Vendor_SysTickConfig
Pokitto	6:ea7377f3d1af	245	#define __Vendor_SysTickConfig 0
Pokitto	6:ea7377f3d1af	246	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Pokitto	6:ea7377f3d1af	247	#endif
Pokitto	6:ea7377f3d1af	248	#endif
Pokitto	6:ea7377f3d1af	249
Pokitto	6:ea7377f3d1af	250	/* IO definitions (access restrictions to peripheral registers) */
Pokitto	6:ea7377f3d1af	251	/**
Pokitto	6:ea7377f3d1af	252	\defgroup CMSIS_glob_defs CMSIS Global Defines
Pokitto	6:ea7377f3d1af	253
Pokitto	6:ea7377f3d1af	254	<strong>IO Type Qualifiers</strong> are used
Pokitto	6:ea7377f3d1af	255	\li to specify the access to peripheral variables.
Pokitto	6:ea7377f3d1af	256	\li for automatic generation of peripheral register debug information.
Pokitto	6:ea7377f3d1af	257	*/
Pokitto	6:ea7377f3d1af	258	#ifdef __cplusplus
Pokitto	6:ea7377f3d1af	259	#define __I volatile /!< Defines 'read only' permissions /
Pokitto	6:ea7377f3d1af	260	#else
Pokitto	6:ea7377f3d1af	261	#define __I volatile const /!< Defines 'read only' permissions /
Pokitto	6:ea7377f3d1af	262	#endif
Pokitto	6:ea7377f3d1af	263	#define __O volatile /!< Defines 'write only' permissions /
Pokitto	6:ea7377f3d1af	264	#define __IO volatile /!< Defines 'read / write' permissions /
Pokitto	6:ea7377f3d1af	265
Pokitto	6:ea7377f3d1af	266	/@} end of group Cortex_M7 /
Pokitto	6:ea7377f3d1af	267
Pokitto	6:ea7377f3d1af	268
Pokitto	6:ea7377f3d1af	269
Pokitto	6:ea7377f3d1af	270	/*******************************************************************************
Pokitto	6:ea7377f3d1af	271	* Register Abstraction
Pokitto	6:ea7377f3d1af	272	Core Register contain:
Pokitto	6:ea7377f3d1af	273	- Core Register
Pokitto	6:ea7377f3d1af	274	- Core NVIC Register
Pokitto	6:ea7377f3d1af	275	- Core SCB Register
Pokitto	6:ea7377f3d1af	276	- Core SysTick Register
Pokitto	6:ea7377f3d1af	277	- Core Debug Register
Pokitto	6:ea7377f3d1af	278	- Core MPU Register
Pokitto	6:ea7377f3d1af	279	- Core FPU Register
Pokitto	6:ea7377f3d1af	280	******************************************************************************/
Pokitto	6:ea7377f3d1af	281	/** \defgroup CMSIS_core_register Defines and Type Definitions
Pokitto	6:ea7377f3d1af	282	\brief Type definitions and defines for Cortex-M processor based devices.
Pokitto	6:ea7377f3d1af	283	*/
Pokitto	6:ea7377f3d1af	284
Pokitto	6:ea7377f3d1af	285	/** \ingroup CMSIS_core_register
Pokitto	6:ea7377f3d1af	286	\defgroup CMSIS_CORE Status and Control Registers
Pokitto	6:ea7377f3d1af	287	\brief Core Register type definitions.
Pokitto	6:ea7377f3d1af	288	@{
Pokitto	6:ea7377f3d1af	289	*/
Pokitto	6:ea7377f3d1af	290
Pokitto	6:ea7377f3d1af	291	/** \brief Union type to access the Application Program Status Register (APSR).
Pokitto	6:ea7377f3d1af	292	*/
Pokitto	6:ea7377f3d1af	293	typedef union
Pokitto	6:ea7377f3d1af	294	{
Pokitto	6:ea7377f3d1af	295	struct
Pokitto	6:ea7377f3d1af	296	{
Pokitto	6:ea7377f3d1af	297	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
Pokitto	6:ea7377f3d1af	298	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
Pokitto	6:ea7377f3d1af	299	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
Pokitto	6:ea7377f3d1af	300	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Pokitto	6:ea7377f3d1af	301	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Pokitto	6:ea7377f3d1af	302	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Pokitto	6:ea7377f3d1af	303	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Pokitto	6:ea7377f3d1af	304	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Pokitto	6:ea7377f3d1af	305	} b; /!< Structure used for bit access /
Pokitto	6:ea7377f3d1af	306	uint32_t w; /!< Type used for word access /
Pokitto	6:ea7377f3d1af	307	} APSR_Type;
Pokitto	6:ea7377f3d1af	308
Pokitto	6:ea7377f3d1af	309	/* APSR Register Definitions */
Pokitto	6:ea7377f3d1af	310	#define APSR_N_Pos 31 /!< APSR: N Position /
Pokitto	6:ea7377f3d1af	311	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
Pokitto	6:ea7377f3d1af	312
Pokitto	6:ea7377f3d1af	313	#define APSR_Z_Pos 30 /!< APSR: Z Position /
Pokitto	6:ea7377f3d1af	314	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
Pokitto	6:ea7377f3d1af	315
Pokitto	6:ea7377f3d1af	316	#define APSR_C_Pos 29 /!< APSR: C Position /
Pokitto	6:ea7377f3d1af	317	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
Pokitto	6:ea7377f3d1af	318
Pokitto	6:ea7377f3d1af	319	#define APSR_V_Pos 28 /!< APSR: V Position /
Pokitto	6:ea7377f3d1af	320	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
Pokitto	6:ea7377f3d1af	321
Pokitto	6:ea7377f3d1af	322	#define APSR_Q_Pos 27 /!< APSR: Q Position /
Pokitto	6:ea7377f3d1af	323	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
Pokitto	6:ea7377f3d1af	324
Pokitto	6:ea7377f3d1af	325	#define APSR_GE_Pos 16 /!< APSR: GE Position /
Pokitto	6:ea7377f3d1af	326	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
Pokitto	6:ea7377f3d1af	327
Pokitto	6:ea7377f3d1af	328
Pokitto	6:ea7377f3d1af	329	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
Pokitto	6:ea7377f3d1af	330	*/
Pokitto	6:ea7377f3d1af	331	typedef union
Pokitto	6:ea7377f3d1af	332	{
Pokitto	6:ea7377f3d1af	333	struct
Pokitto	6:ea7377f3d1af	334	{
Pokitto	6:ea7377f3d1af	335	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Pokitto	6:ea7377f3d1af	336	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
Pokitto	6:ea7377f3d1af	337	} b; /!< Structure used for bit access /
Pokitto	6:ea7377f3d1af	338	uint32_t w; /!< Type used for word access /
Pokitto	6:ea7377f3d1af	339	} IPSR_Type;
Pokitto	6:ea7377f3d1af	340
Pokitto	6:ea7377f3d1af	341	/* IPSR Register Definitions */
Pokitto	6:ea7377f3d1af	342	#define IPSR_ISR_Pos 0 /!< IPSR: ISR Position /
Pokitto	6:ea7377f3d1af	343	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
Pokitto	6:ea7377f3d1af	344
Pokitto	6:ea7377f3d1af	345
Pokitto	6:ea7377f3d1af	346	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Pokitto	6:ea7377f3d1af	347	*/
Pokitto	6:ea7377f3d1af	348	typedef union
Pokitto	6:ea7377f3d1af	349	{
Pokitto	6:ea7377f3d1af	350	struct
Pokitto	6:ea7377f3d1af	351	{
Pokitto	6:ea7377f3d1af	352	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Pokitto	6:ea7377f3d1af	353	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
Pokitto	6:ea7377f3d1af	354	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
Pokitto	6:ea7377f3d1af	355	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
Pokitto	6:ea7377f3d1af	356	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
Pokitto	6:ea7377f3d1af	357	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
Pokitto	6:ea7377f3d1af	358	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Pokitto	6:ea7377f3d1af	359	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Pokitto	6:ea7377f3d1af	360	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Pokitto	6:ea7377f3d1af	361	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Pokitto	6:ea7377f3d1af	362	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Pokitto	6:ea7377f3d1af	363	} b; /!< Structure used for bit access /
Pokitto	6:ea7377f3d1af	364	uint32_t w; /!< Type used for word access /
Pokitto	6:ea7377f3d1af	365	} xPSR_Type;
Pokitto	6:ea7377f3d1af	366
Pokitto	6:ea7377f3d1af	367	/* xPSR Register Definitions */
Pokitto	6:ea7377f3d1af	368	#define xPSR_N_Pos 31 /!< xPSR: N Position /
Pokitto	6:ea7377f3d1af	369	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
Pokitto	6:ea7377f3d1af	370
Pokitto	6:ea7377f3d1af	371	#define xPSR_Z_Pos 30 /!< xPSR: Z Position /
Pokitto	6:ea7377f3d1af	372	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
Pokitto	6:ea7377f3d1af	373
Pokitto	6:ea7377f3d1af	374	#define xPSR_C_Pos 29 /!< xPSR: C Position /
Pokitto	6:ea7377f3d1af	375	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
Pokitto	6:ea7377f3d1af	376
Pokitto	6:ea7377f3d1af	377	#define xPSR_V_Pos 28 /!< xPSR: V Position /
Pokitto	6:ea7377f3d1af	378	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
Pokitto	6:ea7377f3d1af	379
Pokitto	6:ea7377f3d1af	380	#define xPSR_Q_Pos 27 /!< xPSR: Q Position /
Pokitto	6:ea7377f3d1af	381	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
Pokitto	6:ea7377f3d1af	382
Pokitto	6:ea7377f3d1af	383	#define xPSR_IT_Pos 25 /!< xPSR: IT Position /
Pokitto	6:ea7377f3d1af	384	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
Pokitto	6:ea7377f3d1af	385
Pokitto	6:ea7377f3d1af	386	#define xPSR_T_Pos 24 /!< xPSR: T Position /
Pokitto	6:ea7377f3d1af	387	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
Pokitto	6:ea7377f3d1af	388
Pokitto	6:ea7377f3d1af	389	#define xPSR_GE_Pos 16 /!< xPSR: GE Position /
Pokitto	6:ea7377f3d1af	390	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
Pokitto	6:ea7377f3d1af	391
Pokitto	6:ea7377f3d1af	392	#define xPSR_ISR_Pos 0 /!< xPSR: ISR Position /
Pokitto	6:ea7377f3d1af	393	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
Pokitto	6:ea7377f3d1af	394
Pokitto	6:ea7377f3d1af	395
Pokitto	6:ea7377f3d1af	396	/** \brief Union type to access the Control Registers (CONTROL).
Pokitto	6:ea7377f3d1af	397	*/
Pokitto	6:ea7377f3d1af	398	typedef union
Pokitto	6:ea7377f3d1af	399	{
Pokitto	6:ea7377f3d1af	400	struct
Pokitto	6:ea7377f3d1af	401	{
Pokitto	6:ea7377f3d1af	402	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
Pokitto	6:ea7377f3d1af	403	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
Pokitto	6:ea7377f3d1af	404	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
Pokitto	6:ea7377f3d1af	405	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
Pokitto	6:ea7377f3d1af	406	} b; /!< Structure used for bit access /
Pokitto	6:ea7377f3d1af	407	uint32_t w; /!< Type used for word access /
Pokitto	6:ea7377f3d1af	408	} CONTROL_Type;
Pokitto	6:ea7377f3d1af	409
Pokitto	6:ea7377f3d1af	410	/* CONTROL Register Definitions */
Pokitto	6:ea7377f3d1af	411	#define CONTROL_FPCA_Pos 2 /!< CONTROL: FPCA Position /
Pokitto	6:ea7377f3d1af	412	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
Pokitto	6:ea7377f3d1af	413
Pokitto	6:ea7377f3d1af	414	#define CONTROL_SPSEL_Pos 1 /!< CONTROL: SPSEL Position /
Pokitto	6:ea7377f3d1af	415	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
Pokitto	6:ea7377f3d1af	416
Pokitto	6:ea7377f3d1af	417	#define CONTROL_nPRIV_Pos 0 /!< CONTROL: nPRIV Position /
Pokitto	6:ea7377f3d1af	418	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
Pokitto	6:ea7377f3d1af	419
Pokitto	6:ea7377f3d1af	420	/@} end of group CMSIS_CORE /
Pokitto	6:ea7377f3d1af	421
Pokitto	6:ea7377f3d1af	422
Pokitto	6:ea7377f3d1af	423	/** \ingroup CMSIS_core_register
Pokitto	6:ea7377f3d1af	424	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Pokitto	6:ea7377f3d1af	425	\brief Type definitions for the NVIC Registers
Pokitto	6:ea7377f3d1af	426	@{
Pokitto	6:ea7377f3d1af	427	*/
Pokitto	6:ea7377f3d1af	428
Pokitto	6:ea7377f3d1af	429	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Pokitto	6:ea7377f3d1af	430	*/
Pokitto	6:ea7377f3d1af	431	typedef struct
Pokitto	6:ea7377f3d1af	432	{
Pokitto	6:ea7377f3d1af	433	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
Pokitto	6:ea7377f3d1af	434	uint32_t RESERVED0[24];
Pokitto	6:ea7377f3d1af	435	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
Pokitto	6:ea7377f3d1af	436	uint32_t RSERVED1[24];
Pokitto	6:ea7377f3d1af	437	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
Pokitto	6:ea7377f3d1af	438	uint32_t RESERVED2[24];
Pokitto	6:ea7377f3d1af	439	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
Pokitto	6:ea7377f3d1af	440	uint32_t RESERVED3[24];
Pokitto	6:ea7377f3d1af	441	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
Pokitto	6:ea7377f3d1af	442	uint32_t RESERVED4[56];
Pokitto	6:ea7377f3d1af	443	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
Pokitto	6:ea7377f3d1af	444	uint32_t RESERVED5[644];
Pokitto	6:ea7377f3d1af	445	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
Pokitto	6:ea7377f3d1af	446	} NVIC_Type;
Pokitto	6:ea7377f3d1af	447
Pokitto	6:ea7377f3d1af	448	/* Software Triggered Interrupt Register Definitions */
Pokitto	6:ea7377f3d1af	449	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
Pokitto	6:ea7377f3d1af	450	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
Pokitto	6:ea7377f3d1af	451
Pokitto	6:ea7377f3d1af	452	/@} end of group CMSIS_NVIC /
Pokitto	6:ea7377f3d1af	453
Pokitto	6:ea7377f3d1af	454
Pokitto	6:ea7377f3d1af	455	/** \ingroup CMSIS_core_register
Pokitto	6:ea7377f3d1af	456	\defgroup CMSIS_SCB System Control Block (SCB)
Pokitto	6:ea7377f3d1af	457	\brief Type definitions for the System Control Block Registers
Pokitto	6:ea7377f3d1af	458	@{
Pokitto	6:ea7377f3d1af	459	*/
Pokitto	6:ea7377f3d1af	460
Pokitto	6:ea7377f3d1af	461	/** \brief Structure type to access the System Control Block (SCB).
Pokitto	6:ea7377f3d1af	462	*/
Pokitto	6:ea7377f3d1af	463	typedef struct
Pokitto	6:ea7377f3d1af	464	{
Pokitto	6:ea7377f3d1af	465	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
Pokitto	6:ea7377f3d1af	466	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
Pokitto	6:ea7377f3d1af	467	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
Pokitto	6:ea7377f3d1af	468	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
Pokitto	6:ea7377f3d1af	469	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
Pokitto	6:ea7377f3d1af	470	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
Pokitto	6:ea7377f3d1af	471	__IO uint8_t SHPR[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
Pokitto	6:ea7377f3d1af	472	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
Pokitto	6:ea7377f3d1af	473	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
Pokitto	6:ea7377f3d1af	474	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
Pokitto	6:ea7377f3d1af	475	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
Pokitto	6:ea7377f3d1af	476	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
Pokitto	6:ea7377f3d1af	477	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
Pokitto	6:ea7377f3d1af	478	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
Pokitto	6:ea7377f3d1af	479	__I uint32_t ID_PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
Pokitto	6:ea7377f3d1af	480	__I uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
Pokitto	6:ea7377f3d1af	481	__I uint32_t ID_AFR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
Pokitto	6:ea7377f3d1af	482	__I uint32_t ID_MFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
Pokitto	6:ea7377f3d1af	483	__I uint32_t ID_ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
Pokitto	6:ea7377f3d1af	484	uint32_t RESERVED0[1];
Pokitto	6:ea7377f3d1af	485	__I uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
Pokitto	6:ea7377f3d1af	486	__I uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
Pokitto	6:ea7377f3d1af	487	__I uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
Pokitto	6:ea7377f3d1af	488	__IO uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
Pokitto	6:ea7377f3d1af	489	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
Pokitto	6:ea7377f3d1af	490	uint32_t RESERVED3[93];
Pokitto	6:ea7377f3d1af	491	__O uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
Pokitto	6:ea7377f3d1af	492	uint32_t RESERVED4[15];
Pokitto	6:ea7377f3d1af	493	__I uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
Pokitto	6:ea7377f3d1af	494	__I uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
Pokitto	6:ea7377f3d1af	495	__I uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 /
Pokitto	6:ea7377f3d1af	496	uint32_t RESERVED5[1];
Pokitto	6:ea7377f3d1af	497	__O uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
Pokitto	6:ea7377f3d1af	498	uint32_t RESERVED6[1];
Pokitto	6:ea7377f3d1af	499	__O uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
Pokitto	6:ea7377f3d1af	500	__O uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
Pokitto	6:ea7377f3d1af	501	__O uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
Pokitto	6:ea7377f3d1af	502	__O uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
Pokitto	6:ea7377f3d1af	503	__O uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
Pokitto	6:ea7377f3d1af	504	__O uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
Pokitto	6:ea7377f3d1af	505	__O uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
Pokitto	6:ea7377f3d1af	506	__O uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
Pokitto	6:ea7377f3d1af	507	uint32_t RESERVED7[6];
Pokitto	6:ea7377f3d1af	508	__IO uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
Pokitto	6:ea7377f3d1af	509	__IO uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
Pokitto	6:ea7377f3d1af	510	__IO uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
Pokitto	6:ea7377f3d1af	511	__IO uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
Pokitto	6:ea7377f3d1af	512	__IO uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
Pokitto	6:ea7377f3d1af	513	uint32_t RESERVED8[1];
Pokitto	6:ea7377f3d1af	514	__IO uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
Pokitto	6:ea7377f3d1af	515	} SCB_Type;
Pokitto	6:ea7377f3d1af	516
Pokitto	6:ea7377f3d1af	517	/* SCB CPUID Register Definitions */
Pokitto	6:ea7377f3d1af	518	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
Pokitto	6:ea7377f3d1af	519	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
Pokitto	6:ea7377f3d1af	520
Pokitto	6:ea7377f3d1af	521	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
Pokitto	6:ea7377f3d1af	522	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
Pokitto	6:ea7377f3d1af	523
Pokitto	6:ea7377f3d1af	524	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
Pokitto	6:ea7377f3d1af	525	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
Pokitto	6:ea7377f3d1af	526
Pokitto	6:ea7377f3d1af	527	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
Pokitto	6:ea7377f3d1af	528	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
Pokitto	6:ea7377f3d1af	529
Pokitto	6:ea7377f3d1af	530	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
Pokitto	6:ea7377f3d1af	531	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
Pokitto	6:ea7377f3d1af	532
Pokitto	6:ea7377f3d1af	533	/* SCB Interrupt Control State Register Definitions */
Pokitto	6:ea7377f3d1af	534	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
Pokitto	6:ea7377f3d1af	535	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
Pokitto	6:ea7377f3d1af	536
Pokitto	6:ea7377f3d1af	537	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
Pokitto	6:ea7377f3d1af	538	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
Pokitto	6:ea7377f3d1af	539
Pokitto	6:ea7377f3d1af	540	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
Pokitto	6:ea7377f3d1af	541	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
Pokitto	6:ea7377f3d1af	542
Pokitto	6:ea7377f3d1af	543	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
Pokitto	6:ea7377f3d1af	544	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
Pokitto	6:ea7377f3d1af	545
Pokitto	6:ea7377f3d1af	546	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
Pokitto	6:ea7377f3d1af	547	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
Pokitto	6:ea7377f3d1af	548
Pokitto	6:ea7377f3d1af	549	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
Pokitto	6:ea7377f3d1af	550	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
Pokitto	6:ea7377f3d1af	551
Pokitto	6:ea7377f3d1af	552	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
Pokitto	6:ea7377f3d1af	553	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
Pokitto	6:ea7377f3d1af	554
Pokitto	6:ea7377f3d1af	555	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
Pokitto	6:ea7377f3d1af	556	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
Pokitto	6:ea7377f3d1af	557
Pokitto	6:ea7377f3d1af	558	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
Pokitto	6:ea7377f3d1af	559	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
Pokitto	6:ea7377f3d1af	560
Pokitto	6:ea7377f3d1af	561	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
Pokitto	6:ea7377f3d1af	562	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
Pokitto	6:ea7377f3d1af	563
Pokitto	6:ea7377f3d1af	564	/* SCB Vector Table Offset Register Definitions */
Pokitto	6:ea7377f3d1af	565	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
Pokitto	6:ea7377f3d1af	566	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
Pokitto	6:ea7377f3d1af	567
Pokitto	6:ea7377f3d1af	568	/* SCB Application Interrupt and Reset Control Register Definitions */
Pokitto	6:ea7377f3d1af	569	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
Pokitto	6:ea7377f3d1af	570	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
Pokitto	6:ea7377f3d1af	571
Pokitto	6:ea7377f3d1af	572	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
Pokitto	6:ea7377f3d1af	573	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
Pokitto	6:ea7377f3d1af	574
Pokitto	6:ea7377f3d1af	575	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
Pokitto	6:ea7377f3d1af	576	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
Pokitto	6:ea7377f3d1af	577
Pokitto	6:ea7377f3d1af	578	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
Pokitto	6:ea7377f3d1af	579	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
Pokitto	6:ea7377f3d1af	580
Pokitto	6:ea7377f3d1af	581	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
Pokitto	6:ea7377f3d1af	582	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
Pokitto	6:ea7377f3d1af	583
Pokitto	6:ea7377f3d1af	584	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
Pokitto	6:ea7377f3d1af	585	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
Pokitto	6:ea7377f3d1af	586
Pokitto	6:ea7377f3d1af	587	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
Pokitto	6:ea7377f3d1af	588	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
Pokitto	6:ea7377f3d1af	589
Pokitto	6:ea7377f3d1af	590	/* SCB System Control Register Definitions */
Pokitto	6:ea7377f3d1af	591	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
Pokitto	6:ea7377f3d1af	592	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
Pokitto	6:ea7377f3d1af	593
Pokitto	6:ea7377f3d1af	594	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
Pokitto	6:ea7377f3d1af	595	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
Pokitto	6:ea7377f3d1af	596
Pokitto	6:ea7377f3d1af	597	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
Pokitto	6:ea7377f3d1af	598	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
Pokitto	6:ea7377f3d1af	599
Pokitto	6:ea7377f3d1af	600	/* SCB Configuration Control Register Definitions */
Pokitto	6:ea7377f3d1af	601	#define SCB_CCR_BP_Pos 18 /!< SCB CCR: Branch prediction enable bit Position /
Pokitto	6:ea7377f3d1af	602	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: Branch prediction enable bit Mask /
Pokitto	6:ea7377f3d1af	603
Pokitto	6:ea7377f3d1af	604	#define SCB_CCR_IC_Pos 17 /!< SCB CCR: Instruction cache enable bit Position /
Pokitto	6:ea7377f3d1af	605	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: Instruction cache enable bit Mask /
Pokitto	6:ea7377f3d1af	606
Pokitto	6:ea7377f3d1af	607	#define SCB_CCR_DC_Pos 16 /!< SCB CCR: Cache enable bit Position /
Pokitto	6:ea7377f3d1af	608	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: Cache enable bit Mask /
Pokitto	6:ea7377f3d1af	609
Pokitto	6:ea7377f3d1af	610	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
Pokitto	6:ea7377f3d1af	611	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
Pokitto	6:ea7377f3d1af	612
Pokitto	6:ea7377f3d1af	613	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
Pokitto	6:ea7377f3d1af	614	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
Pokitto	6:ea7377f3d1af	615
Pokitto	6:ea7377f3d1af	616	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
Pokitto	6:ea7377f3d1af	617	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
Pokitto	6:ea7377f3d1af	618
Pokitto	6:ea7377f3d1af	619	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
Pokitto	6:ea7377f3d1af	620	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
Pokitto	6:ea7377f3d1af	621
Pokitto	6:ea7377f3d1af	622	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
Pokitto	6:ea7377f3d1af	623	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
Pokitto	6:ea7377f3d1af	624
Pokitto	6:ea7377f3d1af	625	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
Pokitto	6:ea7377f3d1af	626	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
Pokitto	6:ea7377f3d1af	627
Pokitto	6:ea7377f3d1af	628	/* SCB System Handler Control and State Register Definitions */
Pokitto	6:ea7377f3d1af	629	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
Pokitto	6:ea7377f3d1af	630	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
Pokitto	6:ea7377f3d1af	631
Pokitto	6:ea7377f3d1af	632	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
Pokitto	6:ea7377f3d1af	633	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
Pokitto	6:ea7377f3d1af	634
Pokitto	6:ea7377f3d1af	635	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
Pokitto	6:ea7377f3d1af	636	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
Pokitto	6:ea7377f3d1af	637
Pokitto	6:ea7377f3d1af	638	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
Pokitto	6:ea7377f3d1af	639	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
Pokitto	6:ea7377f3d1af	640
Pokitto	6:ea7377f3d1af	641	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
Pokitto	6:ea7377f3d1af	642	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
Pokitto	6:ea7377f3d1af	643
Pokitto	6:ea7377f3d1af	644	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
Pokitto	6:ea7377f3d1af	645	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
Pokitto	6:ea7377f3d1af	646
Pokitto	6:ea7377f3d1af	647	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
Pokitto	6:ea7377f3d1af	648	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
Pokitto	6:ea7377f3d1af	649
Pokitto	6:ea7377f3d1af	650	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
Pokitto	6:ea7377f3d1af	651	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
Pokitto	6:ea7377f3d1af	652
Pokitto	6:ea7377f3d1af	653	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
Pokitto	6:ea7377f3d1af	654	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
Pokitto	6:ea7377f3d1af	655
Pokitto	6:ea7377f3d1af	656	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
Pokitto	6:ea7377f3d1af	657	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
Pokitto	6:ea7377f3d1af	658
Pokitto	6:ea7377f3d1af	659	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
Pokitto	6:ea7377f3d1af	660	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
Pokitto	6:ea7377f3d1af	661
Pokitto	6:ea7377f3d1af	662	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
Pokitto	6:ea7377f3d1af	663	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
Pokitto	6:ea7377f3d1af	664
Pokitto	6:ea7377f3d1af	665	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
Pokitto	6:ea7377f3d1af	666	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
Pokitto	6:ea7377f3d1af	667
Pokitto	6:ea7377f3d1af	668	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
Pokitto	6:ea7377f3d1af	669	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
Pokitto	6:ea7377f3d1af	670
Pokitto	6:ea7377f3d1af	671	/* SCB Configurable Fault Status Registers Definitions */
Pokitto	6:ea7377f3d1af	672	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
Pokitto	6:ea7377f3d1af	673	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
Pokitto	6:ea7377f3d1af	674
Pokitto	6:ea7377f3d1af	675	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
Pokitto	6:ea7377f3d1af	676	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
Pokitto	6:ea7377f3d1af	677
Pokitto	6:ea7377f3d1af	678	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
Pokitto	6:ea7377f3d1af	679	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
Pokitto	6:ea7377f3d1af	680
Pokitto	6:ea7377f3d1af	681	/* SCB Hard Fault Status Registers Definitions */
Pokitto	6:ea7377f3d1af	682	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
Pokitto	6:ea7377f3d1af	683	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
Pokitto	6:ea7377f3d1af	684
Pokitto	6:ea7377f3d1af	685	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
Pokitto	6:ea7377f3d1af	686	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
Pokitto	6:ea7377f3d1af	687
Pokitto	6:ea7377f3d1af	688	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
Pokitto	6:ea7377f3d1af	689	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
Pokitto	6:ea7377f3d1af	690
Pokitto	6:ea7377f3d1af	691	/* SCB Debug Fault Status Register Definitions */
Pokitto	6:ea7377f3d1af	692	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
Pokitto	6:ea7377f3d1af	693	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
Pokitto	6:ea7377f3d1af	694
Pokitto	6:ea7377f3d1af	695	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
Pokitto	6:ea7377f3d1af	696	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
Pokitto	6:ea7377f3d1af	697
Pokitto	6:ea7377f3d1af	698	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
Pokitto	6:ea7377f3d1af	699	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
Pokitto	6:ea7377f3d1af	700
Pokitto	6:ea7377f3d1af	701	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
Pokitto	6:ea7377f3d1af	702	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
Pokitto	6:ea7377f3d1af	703
Pokitto	6:ea7377f3d1af	704	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
Pokitto	6:ea7377f3d1af	705	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
Pokitto	6:ea7377f3d1af	706
Pokitto	6:ea7377f3d1af	707	/* Cache Level ID register */
Pokitto	6:ea7377f3d1af	708	#define SCB_CLIDR_LOUU_Pos 27 /!< SCB CLIDR: LoUU Position /
Pokitto	6:ea7377f3d1af	709	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
Pokitto	6:ea7377f3d1af	710
Pokitto	6:ea7377f3d1af	711	#define SCB_CLIDR_LOC_Pos 24 /!< SCB CLIDR: LoC Position /
Pokitto	6:ea7377f3d1af	712	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /!< SCB CLIDR: LoC Mask /
Pokitto	6:ea7377f3d1af	713
Pokitto	6:ea7377f3d1af	714	/* Cache Type register */
Pokitto	6:ea7377f3d1af	715	#define SCB_CTR_FORMAT_Pos 29 /!< SCB CTR: Format Position /
Pokitto	6:ea7377f3d1af	716	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
Pokitto	6:ea7377f3d1af	717
Pokitto	6:ea7377f3d1af	718	#define SCB_CTR_CWG_Pos 24 /!< SCB CTR: CWG Position /
Pokitto	6:ea7377f3d1af	719	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
Pokitto	6:ea7377f3d1af	720
Pokitto	6:ea7377f3d1af	721	#define SCB_CTR_ERG_Pos 20 /!< SCB CTR: ERG Position /
Pokitto	6:ea7377f3d1af	722	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
Pokitto	6:ea7377f3d1af	723
Pokitto	6:ea7377f3d1af	724	#define SCB_CTR_DMINLINE_Pos 16 /!< SCB CTR: DminLine Position /
Pokitto	6:ea7377f3d1af	725	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
Pokitto	6:ea7377f3d1af	726
Pokitto	6:ea7377f3d1af	727	#define SCB_CTR_IMINLINE_Pos 0 /!< SCB CTR: ImInLine Position /
Pokitto	6:ea7377f3d1af	728	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
Pokitto	6:ea7377f3d1af	729
Pokitto	6:ea7377f3d1af	730	/* Cache Size ID Register */
Pokitto	6:ea7377f3d1af	731	#define SCB_CCSIDR_WT_Pos 31 /!< SCB CCSIDR: WT Position /
Pokitto	6:ea7377f3d1af	732	#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
Pokitto	6:ea7377f3d1af	733
Pokitto	6:ea7377f3d1af	734	#define SCB_CCSIDR_WB_Pos 30 /!< SCB CCSIDR: WB Position /
Pokitto	6:ea7377f3d1af	735	#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
Pokitto	6:ea7377f3d1af	736
Pokitto	6:ea7377f3d1af	737	#define SCB_CCSIDR_RA_Pos 29 /!< SCB CCSIDR: RA Position /
Pokitto	6:ea7377f3d1af	738	#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
Pokitto	6:ea7377f3d1af	739
Pokitto	6:ea7377f3d1af	740	#define SCB_CCSIDR_WA_Pos 28 /!< SCB CCSIDR: WA Position /
Pokitto	6:ea7377f3d1af	741	#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
Pokitto	6:ea7377f3d1af	742
Pokitto	6:ea7377f3d1af	743	#define SCB_CCSIDR_NUMSETS_Pos 13 /!< SCB CCSIDR: NumSets Position /
Pokitto	6:ea7377f3d1af	744	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
Pokitto	6:ea7377f3d1af	745
Pokitto	6:ea7377f3d1af	746	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /!< SCB CCSIDR: Associativity Position /
Pokitto	6:ea7377f3d1af	747	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
Pokitto	6:ea7377f3d1af	748
Pokitto	6:ea7377f3d1af	749	#define SCB_CCSIDR_LINESIZE_Pos 0 /!< SCB CCSIDR: LineSize Position /
Pokitto	6:ea7377f3d1af	750	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
Pokitto	6:ea7377f3d1af	751
Pokitto	6:ea7377f3d1af	752	/* Cache Size Selection Register */
Pokitto	6:ea7377f3d1af	753	#define SCB_CSSELR_LEVEL_Pos 1 /!< SCB CSSELR: Level Position /
Pokitto	6:ea7377f3d1af	754	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
Pokitto	6:ea7377f3d1af	755
Pokitto	6:ea7377f3d1af	756	#define SCB_CSSELR_IND_Pos 0 /!< SCB CSSELR: InD Position /
Pokitto	6:ea7377f3d1af	757	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
Pokitto	6:ea7377f3d1af	758
Pokitto	6:ea7377f3d1af	759	/* SCB Software Triggered Interrupt Register */
Pokitto	6:ea7377f3d1af	760	#define SCB_STIR_INTID_Pos 0 /!< SCB STIR: INTID Position /
Pokitto	6:ea7377f3d1af	761	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
Pokitto	6:ea7377f3d1af	762
Pokitto	6:ea7377f3d1af	763	/* Instruction Tightly-Coupled Memory Control Register*/
Pokitto	6:ea7377f3d1af	764	#define SCB_ITCMCR_SZ_Pos 3 /!< SCB ITCMCR: SZ Position /
Pokitto	6:ea7377f3d1af	765	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
Pokitto	6:ea7377f3d1af	766
Pokitto	6:ea7377f3d1af	767	#define SCB_ITCMCR_RETEN_Pos 2 /!< SCB ITCMCR: RETEN Position /
Pokitto	6:ea7377f3d1af	768	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
Pokitto	6:ea7377f3d1af	769
Pokitto	6:ea7377f3d1af	770	#define SCB_ITCMCR_RMW_Pos 1 /!< SCB ITCMCR: RMW Position /
Pokitto	6:ea7377f3d1af	771	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
Pokitto	6:ea7377f3d1af	772
Pokitto	6:ea7377f3d1af	773	#define SCB_ITCMCR_EN_Pos 0 /!< SCB ITCMCR: EN Position /
Pokitto	6:ea7377f3d1af	774	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
Pokitto	6:ea7377f3d1af	775
Pokitto	6:ea7377f3d1af	776	/* Data Tightly-Coupled Memory Control Registers */
Pokitto	6:ea7377f3d1af	777	#define SCB_DTCMCR_SZ_Pos 3 /!< SCB DTCMCR: SZ Position /
Pokitto	6:ea7377f3d1af	778	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
Pokitto	6:ea7377f3d1af	779
Pokitto	6:ea7377f3d1af	780	#define SCB_DTCMCR_RETEN_Pos 2 /!< SCB DTCMCR: RETEN Position /
Pokitto	6:ea7377f3d1af	781	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
Pokitto	6:ea7377f3d1af	782
Pokitto	6:ea7377f3d1af	783	#define SCB_DTCMCR_RMW_Pos 1 /!< SCB DTCMCR: RMW Position /
Pokitto	6:ea7377f3d1af	784	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
Pokitto	6:ea7377f3d1af	785
Pokitto	6:ea7377f3d1af	786	#define SCB_DTCMCR_EN_Pos 0 /!< SCB DTCMCR: EN Position /
Pokitto	6:ea7377f3d1af	787	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
Pokitto	6:ea7377f3d1af	788
Pokitto	6:ea7377f3d1af	789	/* AHBP Control Register */
Pokitto	6:ea7377f3d1af	790	#define SCB_AHBPCR_SZ_Pos 1 /!< SCB AHBPCR: SZ Position /
Pokitto	6:ea7377f3d1af	791	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
Pokitto	6:ea7377f3d1af	792
Pokitto	6:ea7377f3d1af	793	#define SCB_AHBPCR_EN_Pos 0 /!< SCB AHBPCR: EN Position /
Pokitto	6:ea7377f3d1af	794	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
Pokitto	6:ea7377f3d1af	795
Pokitto	6:ea7377f3d1af	796	/* L1 Cache Control Register */
Pokitto	6:ea7377f3d1af	797	#define SCB_CACR_FORCEWT_Pos 2 /!< SCB CACR: FORCEWT Position /
Pokitto	6:ea7377f3d1af	798	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
Pokitto	6:ea7377f3d1af	799
Pokitto	6:ea7377f3d1af	800	#define SCB_CACR_ECCEN_Pos 1 /!< SCB CACR: ECCEN Position /
Pokitto	6:ea7377f3d1af	801	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
Pokitto	6:ea7377f3d1af	802
Pokitto	6:ea7377f3d1af	803	#define SCB_CACR_SIWT_Pos 0 /!< SCB CACR: SIWT Position /
Pokitto	6:ea7377f3d1af	804	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
Pokitto	6:ea7377f3d1af	805
Pokitto	6:ea7377f3d1af	806	/* AHBS control register */
Pokitto	6:ea7377f3d1af	807	#define SCB_AHBSCR_INITCOUNT_Pos 11 /!< SCB AHBSCR: INITCOUNT Position /
Pokitto	6:ea7377f3d1af	808	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
Pokitto	6:ea7377f3d1af	809
Pokitto	6:ea7377f3d1af	810	#define SCB_AHBSCR_TPRI_Pos 2 /!< SCB AHBSCR: TPRI Position /
Pokitto	6:ea7377f3d1af	811	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
Pokitto	6:ea7377f3d1af	812
Pokitto	6:ea7377f3d1af	813	#define SCB_AHBSCR_CTL_Pos 0 /!< SCB AHBSCR: CTL Position/
Pokitto	6:ea7377f3d1af	814	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
Pokitto	6:ea7377f3d1af	815
Pokitto	6:ea7377f3d1af	816	/* Auxiliary Bus Fault Status Register */
Pokitto	6:ea7377f3d1af	817	#define SCB_ABFSR_AXIMTYPE_Pos 8 /!< SCB ABFSR: AXIMTYPE Position/
Pokitto	6:ea7377f3d1af	818	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
Pokitto	6:ea7377f3d1af	819
Pokitto	6:ea7377f3d1af	820	#define SCB_ABFSR_EPPB_Pos 4 /!< SCB ABFSR: EPPB Position/
Pokitto	6:ea7377f3d1af	821	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
Pokitto	6:ea7377f3d1af	822
Pokitto	6:ea7377f3d1af	823	#define SCB_ABFSR_AXIM_Pos 3 /!< SCB ABFSR: AXIM Position/
Pokitto	6:ea7377f3d1af	824	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
Pokitto	6:ea7377f3d1af	825
Pokitto	6:ea7377f3d1af	826	#define SCB_ABFSR_AHBP_Pos 2 /!< SCB ABFSR: AHBP Position/
Pokitto	6:ea7377f3d1af	827	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
Pokitto	6:ea7377f3d1af	828
Pokitto	6:ea7377f3d1af	829	#define SCB_ABFSR_DTCM_Pos 1 /!< SCB ABFSR: DTCM Position/
Pokitto	6:ea7377f3d1af	830	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
Pokitto	6:ea7377f3d1af	831
Pokitto	6:ea7377f3d1af	832	#define SCB_ABFSR_ITCM_Pos 0 /!< SCB ABFSR: ITCM Position/
Pokitto	6:ea7377f3d1af	833	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
Pokitto	6:ea7377f3d1af	834
Pokitto	6:ea7377f3d1af	835	/@} end of group CMSIS_SCB /
Pokitto	6:ea7377f3d1af	836
Pokitto	6:ea7377f3d1af	837
Pokitto	6:ea7377f3d1af	838	/** \ingroup CMSIS_core_register
Pokitto	6:ea7377f3d1af	839	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Pokitto	6:ea7377f3d1af	840	\brief Type definitions for the System Control and ID Register not in the SCB
Pokitto	6:ea7377f3d1af	841	@{
Pokitto	6:ea7377f3d1af	842	*/
Pokitto	6:ea7377f3d1af	843
Pokitto	6:ea7377f3d1af	844	/** \brief Structure type to access the System Control and ID Register not in the SCB.
Pokitto	6:ea7377f3d1af	845	*/
Pokitto	6:ea7377f3d1af	846	typedef struct
Pokitto	6:ea7377f3d1af	847	{
Pokitto	6:ea7377f3d1af	848	uint32_t RESERVED0[1];
Pokitto	6:ea7377f3d1af	849	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
Pokitto	6:ea7377f3d1af	850	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
Pokitto	6:ea7377f3d1af	851	} SCnSCB_Type;
Pokitto	6:ea7377f3d1af	852
Pokitto	6:ea7377f3d1af	853	/* Interrupt Controller Type Register Definitions */
Pokitto	6:ea7377f3d1af	854	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
Pokitto	6:ea7377f3d1af	855	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
Pokitto	6:ea7377f3d1af	856
Pokitto	6:ea7377f3d1af	857	/* Auxiliary Control Register Definitions */
Pokitto	6:ea7377f3d1af	858	#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /!< ACTLR: DISITMATBFLUSH Position /
Pokitto	6:ea7377f3d1af	859	#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /!< ACTLR: DISITMATBFLUSH Mask /
Pokitto	6:ea7377f3d1af	860
Pokitto	6:ea7377f3d1af	861	#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /!< ACTLR: DISRAMODE Position /
Pokitto	6:ea7377f3d1af	862	#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /!< ACTLR: DISRAMODE Mask /
Pokitto	6:ea7377f3d1af	863
Pokitto	6:ea7377f3d1af	864	#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /!< ACTLR: FPEXCODIS Position /
Pokitto	6:ea7377f3d1af	865	#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /!< ACTLR: FPEXCODIS Mask /
Pokitto	6:ea7377f3d1af	866
Pokitto	6:ea7377f3d1af	867	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
Pokitto	6:ea7377f3d1af	868	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
Pokitto	6:ea7377f3d1af	869
Pokitto	6:ea7377f3d1af	870	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
Pokitto	6:ea7377f3d1af	871	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
Pokitto	6:ea7377f3d1af	872
Pokitto	6:ea7377f3d1af	873	/@} end of group CMSIS_SCnotSCB /
Pokitto	6:ea7377f3d1af	874
Pokitto	6:ea7377f3d1af	875
Pokitto	6:ea7377f3d1af	876	/** \ingroup CMSIS_core_register
Pokitto	6:ea7377f3d1af	877	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
Pokitto	6:ea7377f3d1af	878	\brief Type definitions for the System Timer Registers.
Pokitto	6:ea7377f3d1af	879	@{
Pokitto	6:ea7377f3d1af	880	*/
Pokitto	6:ea7377f3d1af	881
Pokitto	6:ea7377f3d1af	882	/** \brief Structure type to access the System Timer (SysTick).
Pokitto	6:ea7377f3d1af	883	*/
Pokitto	6:ea7377f3d1af	884	typedef struct
Pokitto	6:ea7377f3d1af	885	{
Pokitto	6:ea7377f3d1af	886	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
Pokitto	6:ea7377f3d1af	887	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
Pokitto	6:ea7377f3d1af	888	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
Pokitto	6:ea7377f3d1af	889	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
Pokitto	6:ea7377f3d1af	890	} SysTick_Type;
Pokitto	6:ea7377f3d1af	891
Pokitto	6:ea7377f3d1af	892	/* SysTick Control / Status Register Definitions */
Pokitto	6:ea7377f3d1af	893	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
Pokitto	6:ea7377f3d1af	894	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
Pokitto	6:ea7377f3d1af	895
Pokitto	6:ea7377f3d1af	896	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
Pokitto	6:ea7377f3d1af	897	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
Pokitto	6:ea7377f3d1af	898
Pokitto	6:ea7377f3d1af	899	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
Pokitto	6:ea7377f3d1af	900	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
Pokitto	6:ea7377f3d1af	901
Pokitto	6:ea7377f3d1af	902	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
Pokitto	6:ea7377f3d1af	903	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
Pokitto	6:ea7377f3d1af	904
Pokitto	6:ea7377f3d1af	905	/* SysTick Reload Register Definitions */
Pokitto	6:ea7377f3d1af	906	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
Pokitto	6:ea7377f3d1af	907	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
Pokitto	6:ea7377f3d1af	908
Pokitto	6:ea7377f3d1af	909	/* SysTick Current Register Definitions */
Pokitto	6:ea7377f3d1af	910	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
Pokitto	6:ea7377f3d1af	911	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
Pokitto	6:ea7377f3d1af	912
Pokitto	6:ea7377f3d1af	913	/* SysTick Calibration Register Definitions */
Pokitto	6:ea7377f3d1af	914	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
Pokitto	6:ea7377f3d1af	915	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
Pokitto	6:ea7377f3d1af	916
Pokitto	6:ea7377f3d1af	917	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
Pokitto	6:ea7377f3d1af	918	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
Pokitto	6:ea7377f3d1af	919
Pokitto	6:ea7377f3d1af	920	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
Pokitto	6:ea7377f3d1af	921	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
Pokitto	6:ea7377f3d1af	922
Pokitto	6:ea7377f3d1af	923	/@} end of group CMSIS_SysTick /
Pokitto	6:ea7377f3d1af	924
Pokitto	6:ea7377f3d1af	925
Pokitto	6:ea7377f3d1af	926	/** \ingroup CMSIS_core_register
Pokitto	6:ea7377f3d1af	927	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Pokitto	6:ea7377f3d1af	928	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Pokitto	6:ea7377f3d1af	929	@{
Pokitto	6:ea7377f3d1af	930	*/
Pokitto	6:ea7377f3d1af	931
Pokitto	6:ea7377f3d1af	932	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Pokitto	6:ea7377f3d1af	933	*/
Pokitto	6:ea7377f3d1af	934	typedef struct
Pokitto	6:ea7377f3d1af	935	{
Pokitto	6:ea7377f3d1af	936	__O union
Pokitto	6:ea7377f3d1af	937	{
Pokitto	6:ea7377f3d1af	938	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
Pokitto	6:ea7377f3d1af	939	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
Pokitto	6:ea7377f3d1af	940	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
Pokitto	6:ea7377f3d1af	941	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
Pokitto	6:ea7377f3d1af	942	uint32_t RESERVED0[864];
Pokitto	6:ea7377f3d1af	943	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
Pokitto	6:ea7377f3d1af	944	uint32_t RESERVED1[15];
Pokitto	6:ea7377f3d1af	945	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
Pokitto	6:ea7377f3d1af	946	uint32_t RESERVED2[15];
Pokitto	6:ea7377f3d1af	947	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
Pokitto	6:ea7377f3d1af	948	uint32_t RESERVED3[29];
Pokitto	6:ea7377f3d1af	949	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
Pokitto	6:ea7377f3d1af	950	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
Pokitto	6:ea7377f3d1af	951	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
Pokitto	6:ea7377f3d1af	952	uint32_t RESERVED4[43];
Pokitto	6:ea7377f3d1af	953	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
Pokitto	6:ea7377f3d1af	954	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
Pokitto	6:ea7377f3d1af	955	uint32_t RESERVED5[6];
Pokitto	6:ea7377f3d1af	956	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
Pokitto	6:ea7377f3d1af	957	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
Pokitto	6:ea7377f3d1af	958	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
Pokitto	6:ea7377f3d1af	959	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
Pokitto	6:ea7377f3d1af	960	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
Pokitto	6:ea7377f3d1af	961	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
Pokitto	6:ea7377f3d1af	962	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
Pokitto	6:ea7377f3d1af	963	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
Pokitto	6:ea7377f3d1af	964	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
Pokitto	6:ea7377f3d1af	965	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
Pokitto	6:ea7377f3d1af	966	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
Pokitto	6:ea7377f3d1af	967	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
Pokitto	6:ea7377f3d1af	968	} ITM_Type;
Pokitto	6:ea7377f3d1af	969
Pokitto	6:ea7377f3d1af	970	/* ITM Trace Privilege Register Definitions */
Pokitto	6:ea7377f3d1af	971	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
Pokitto	6:ea7377f3d1af	972	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
Pokitto	6:ea7377f3d1af	973
Pokitto	6:ea7377f3d1af	974	/* ITM Trace Control Register Definitions */
Pokitto	6:ea7377f3d1af	975	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
Pokitto	6:ea7377f3d1af	976	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
Pokitto	6:ea7377f3d1af	977
Pokitto	6:ea7377f3d1af	978	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
Pokitto	6:ea7377f3d1af	979	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
Pokitto	6:ea7377f3d1af	980
Pokitto	6:ea7377f3d1af	981	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
Pokitto	6:ea7377f3d1af	982	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
Pokitto	6:ea7377f3d1af	983
Pokitto	6:ea7377f3d1af	984	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
Pokitto	6:ea7377f3d1af	985	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
Pokitto	6:ea7377f3d1af	986
Pokitto	6:ea7377f3d1af	987	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
Pokitto	6:ea7377f3d1af	988	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
Pokitto	6:ea7377f3d1af	989
Pokitto	6:ea7377f3d1af	990	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
Pokitto	6:ea7377f3d1af	991	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
Pokitto	6:ea7377f3d1af	992
Pokitto	6:ea7377f3d1af	993	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
Pokitto	6:ea7377f3d1af	994	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
Pokitto	6:ea7377f3d1af	995
Pokitto	6:ea7377f3d1af	996	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
Pokitto	6:ea7377f3d1af	997	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
Pokitto	6:ea7377f3d1af	998
Pokitto	6:ea7377f3d1af	999	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
Pokitto	6:ea7377f3d1af	1000	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
Pokitto	6:ea7377f3d1af	1001
Pokitto	6:ea7377f3d1af	1002	/* ITM Integration Write Register Definitions */
Pokitto	6:ea7377f3d1af	1003	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
Pokitto	6:ea7377f3d1af	1004	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
Pokitto	6:ea7377f3d1af	1005
Pokitto	6:ea7377f3d1af	1006	/* ITM Integration Read Register Definitions */
Pokitto	6:ea7377f3d1af	1007	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
Pokitto	6:ea7377f3d1af	1008	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
Pokitto	6:ea7377f3d1af	1009
Pokitto	6:ea7377f3d1af	1010	/* ITM Integration Mode Control Register Definitions */
Pokitto	6:ea7377f3d1af	1011	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
Pokitto	6:ea7377f3d1af	1012	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
Pokitto	6:ea7377f3d1af	1013
Pokitto	6:ea7377f3d1af	1014	/* ITM Lock Status Register Definitions */
Pokitto	6:ea7377f3d1af	1015	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
Pokitto	6:ea7377f3d1af	1016	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
Pokitto	6:ea7377f3d1af	1017
Pokitto	6:ea7377f3d1af	1018	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
Pokitto	6:ea7377f3d1af	1019	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
Pokitto	6:ea7377f3d1af	1020
Pokitto	6:ea7377f3d1af	1021	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
Pokitto	6:ea7377f3d1af	1022	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
Pokitto	6:ea7377f3d1af	1023
Pokitto	6:ea7377f3d1af	1024	/@}/ /* end of group CMSIS_ITM */
Pokitto	6:ea7377f3d1af	1025
Pokitto	6:ea7377f3d1af	1026
Pokitto	6:ea7377f3d1af	1027	/** \ingroup CMSIS_core_register
Pokitto	6:ea7377f3d1af	1028	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Pokitto	6:ea7377f3d1af	1029	\brief Type definitions for the Data Watchpoint and Trace (DWT)
Pokitto	6:ea7377f3d1af	1030	@{
Pokitto	6:ea7377f3d1af	1031	*/
Pokitto	6:ea7377f3d1af	1032
Pokitto	6:ea7377f3d1af	1033	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Pokitto	6:ea7377f3d1af	1034	*/
Pokitto	6:ea7377f3d1af	1035	typedef struct
Pokitto	6:ea7377f3d1af	1036	{
Pokitto	6:ea7377f3d1af	1037	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
Pokitto	6:ea7377f3d1af	1038	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
Pokitto	6:ea7377f3d1af	1039	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
Pokitto	6:ea7377f3d1af	1040	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
Pokitto	6:ea7377f3d1af	1041	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
Pokitto	6:ea7377f3d1af	1042	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
Pokitto	6:ea7377f3d1af	1043	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
Pokitto	6:ea7377f3d1af	1044	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
Pokitto	6:ea7377f3d1af	1045	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
Pokitto	6:ea7377f3d1af	1046	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
Pokitto	6:ea7377f3d1af	1047	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
Pokitto	6:ea7377f3d1af	1048	uint32_t RESERVED0[1];
Pokitto	6:ea7377f3d1af	1049	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
Pokitto	6:ea7377f3d1af	1050	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
Pokitto	6:ea7377f3d1af	1051	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
Pokitto	6:ea7377f3d1af	1052	uint32_t RESERVED1[1];
Pokitto	6:ea7377f3d1af	1053	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
Pokitto	6:ea7377f3d1af	1054	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
Pokitto	6:ea7377f3d1af	1055	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
Pokitto	6:ea7377f3d1af	1056	uint32_t RESERVED2[1];
Pokitto	6:ea7377f3d1af	1057	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
Pokitto	6:ea7377f3d1af	1058	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
Pokitto	6:ea7377f3d1af	1059	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
Pokitto	6:ea7377f3d1af	1060	uint32_t RESERVED3[981];
Pokitto	6:ea7377f3d1af	1061	__O uint32_t LAR; /!< Offset: 0xFB0 ( W) Lock Access Register /
Pokitto	6:ea7377f3d1af	1062	__I uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
Pokitto	6:ea7377f3d1af	1063	} DWT_Type;
Pokitto	6:ea7377f3d1af	1064
Pokitto	6:ea7377f3d1af	1065	/* DWT Control Register Definitions */
Pokitto	6:ea7377f3d1af	1066	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
Pokitto	6:ea7377f3d1af	1067	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
Pokitto	6:ea7377f3d1af	1068
Pokitto	6:ea7377f3d1af	1069	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
Pokitto	6:ea7377f3d1af	1070	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
Pokitto	6:ea7377f3d1af	1071
Pokitto	6:ea7377f3d1af	1072	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
Pokitto	6:ea7377f3d1af	1073	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
Pokitto	6:ea7377f3d1af	1074
Pokitto	6:ea7377f3d1af	1075	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
Pokitto	6:ea7377f3d1af	1076	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
Pokitto	6:ea7377f3d1af	1077
Pokitto	6:ea7377f3d1af	1078	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
Pokitto	6:ea7377f3d1af	1079	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
Pokitto	6:ea7377f3d1af	1080
Pokitto	6:ea7377f3d1af	1081	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
Pokitto	6:ea7377f3d1af	1082	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
Pokitto	6:ea7377f3d1af	1083
Pokitto	6:ea7377f3d1af	1084	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
Pokitto	6:ea7377f3d1af	1085	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
Pokitto	6:ea7377f3d1af	1086
Pokitto	6:ea7377f3d1af	1087	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
Pokitto	6:ea7377f3d1af	1088	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
Pokitto	6:ea7377f3d1af	1089
Pokitto	6:ea7377f3d1af	1090	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
Pokitto	6:ea7377f3d1af	1091	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
Pokitto	6:ea7377f3d1af	1092
Pokitto	6:ea7377f3d1af	1093	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
Pokitto	6:ea7377f3d1af	1094	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
Pokitto	6:ea7377f3d1af	1095
Pokitto	6:ea7377f3d1af	1096	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
Pokitto	6:ea7377f3d1af	1097	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
Pokitto	6:ea7377f3d1af	1098
Pokitto	6:ea7377f3d1af	1099	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
Pokitto	6:ea7377f3d1af	1100	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
Pokitto	6:ea7377f3d1af	1101
Pokitto	6:ea7377f3d1af	1102	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
Pokitto	6:ea7377f3d1af	1103	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
Pokitto	6:ea7377f3d1af	1104
Pokitto	6:ea7377f3d1af	1105	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
Pokitto	6:ea7377f3d1af	1106	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
Pokitto	6:ea7377f3d1af	1107
Pokitto	6:ea7377f3d1af	1108	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
Pokitto	6:ea7377f3d1af	1109	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
Pokitto	6:ea7377f3d1af	1110
Pokitto	6:ea7377f3d1af	1111	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
Pokitto	6:ea7377f3d1af	1112	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
Pokitto	6:ea7377f3d1af	1113
Pokitto	6:ea7377f3d1af	1114	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
Pokitto	6:ea7377f3d1af	1115	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
Pokitto	6:ea7377f3d1af	1116
Pokitto	6:ea7377f3d1af	1117	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
Pokitto	6:ea7377f3d1af	1118	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
Pokitto	6:ea7377f3d1af	1119
Pokitto	6:ea7377f3d1af	1120	/* DWT CPI Count Register Definitions */
Pokitto	6:ea7377f3d1af	1121	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
Pokitto	6:ea7377f3d1af	1122	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
Pokitto	6:ea7377f3d1af	1123
Pokitto	6:ea7377f3d1af	1124	/* DWT Exception Overhead Count Register Definitions */
Pokitto	6:ea7377f3d1af	1125	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
Pokitto	6:ea7377f3d1af	1126	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
Pokitto	6:ea7377f3d1af	1127
Pokitto	6:ea7377f3d1af	1128	/* DWT Sleep Count Register Definitions */
Pokitto	6:ea7377f3d1af	1129	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
Pokitto	6:ea7377f3d1af	1130	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
Pokitto	6:ea7377f3d1af	1131
Pokitto	6:ea7377f3d1af	1132	/* DWT LSU Count Register Definitions */
Pokitto	6:ea7377f3d1af	1133	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
Pokitto	6:ea7377f3d1af	1134	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
Pokitto	6:ea7377f3d1af	1135
Pokitto	6:ea7377f3d1af	1136	/* DWT Folded-instruction Count Register Definitions */
Pokitto	6:ea7377f3d1af	1137	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
Pokitto	6:ea7377f3d1af	1138	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
Pokitto	6:ea7377f3d1af	1139
Pokitto	6:ea7377f3d1af	1140	/* DWT Comparator Mask Register Definitions */
Pokitto	6:ea7377f3d1af	1141	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
Pokitto	6:ea7377f3d1af	1142	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
Pokitto	6:ea7377f3d1af	1143
Pokitto	6:ea7377f3d1af	1144	/* DWT Comparator Function Register Definitions */
Pokitto	6:ea7377f3d1af	1145	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
Pokitto	6:ea7377f3d1af	1146	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
Pokitto	6:ea7377f3d1af	1147
Pokitto	6:ea7377f3d1af	1148	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
Pokitto	6:ea7377f3d1af	1149	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
Pokitto	6:ea7377f3d1af	1150
Pokitto	6:ea7377f3d1af	1151	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
Pokitto	6:ea7377f3d1af	1152	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
Pokitto	6:ea7377f3d1af	1153
Pokitto	6:ea7377f3d1af	1154	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
Pokitto	6:ea7377f3d1af	1155	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
Pokitto	6:ea7377f3d1af	1156
Pokitto	6:ea7377f3d1af	1157	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
Pokitto	6:ea7377f3d1af	1158	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
Pokitto	6:ea7377f3d1af	1159
Pokitto	6:ea7377f3d1af	1160	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
Pokitto	6:ea7377f3d1af	1161	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
Pokitto	6:ea7377f3d1af	1162
Pokitto	6:ea7377f3d1af	1163	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
Pokitto	6:ea7377f3d1af	1164	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
Pokitto	6:ea7377f3d1af	1165
Pokitto	6:ea7377f3d1af	1166	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
Pokitto	6:ea7377f3d1af	1167	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
Pokitto	6:ea7377f3d1af	1168
Pokitto	6:ea7377f3d1af	1169	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
Pokitto	6:ea7377f3d1af	1170	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
Pokitto	6:ea7377f3d1af	1171
Pokitto	6:ea7377f3d1af	1172	/@}/ /* end of group CMSIS_DWT */
Pokitto	6:ea7377f3d1af	1173
Pokitto	6:ea7377f3d1af	1174
Pokitto	6:ea7377f3d1af	1175	/** \ingroup CMSIS_core_register
Pokitto	6:ea7377f3d1af	1176	\defgroup CMSIS_TPI Trace Port Interface (TPI)
Pokitto	6:ea7377f3d1af	1177	\brief Type definitions for the Trace Port Interface (TPI)
Pokitto	6:ea7377f3d1af	1178	@{
Pokitto	6:ea7377f3d1af	1179	*/
Pokitto	6:ea7377f3d1af	1180
Pokitto	6:ea7377f3d1af	1181	/** \brief Structure type to access the Trace Port Interface Register (TPI).
Pokitto	6:ea7377f3d1af	1182	*/
Pokitto	6:ea7377f3d1af	1183	typedef struct
Pokitto	6:ea7377f3d1af	1184	{
Pokitto	6:ea7377f3d1af	1185	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
Pokitto	6:ea7377f3d1af	1186	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
Pokitto	6:ea7377f3d1af	1187	uint32_t RESERVED0[2];
Pokitto	6:ea7377f3d1af	1188	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
Pokitto	6:ea7377f3d1af	1189	uint32_t RESERVED1[55];
Pokitto	6:ea7377f3d1af	1190	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
Pokitto	6:ea7377f3d1af	1191	uint32_t RESERVED2[131];
Pokitto	6:ea7377f3d1af	1192	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
Pokitto	6:ea7377f3d1af	1193	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
Pokitto	6:ea7377f3d1af	1194	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
Pokitto	6:ea7377f3d1af	1195	uint32_t RESERVED3[759];
Pokitto	6:ea7377f3d1af	1196	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
Pokitto	6:ea7377f3d1af	1197	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
Pokitto	6:ea7377f3d1af	1198	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
Pokitto	6:ea7377f3d1af	1199	uint32_t RESERVED4[1];
Pokitto	6:ea7377f3d1af	1200	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
Pokitto	6:ea7377f3d1af	1201	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
Pokitto	6:ea7377f3d1af	1202	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
Pokitto	6:ea7377f3d1af	1203	uint32_t RESERVED5[39];
Pokitto	6:ea7377f3d1af	1204	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
Pokitto	6:ea7377f3d1af	1205	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
Pokitto	6:ea7377f3d1af	1206	uint32_t RESERVED7[8];
Pokitto	6:ea7377f3d1af	1207	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
Pokitto	6:ea7377f3d1af	1208	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
Pokitto	6:ea7377f3d1af	1209	} TPI_Type;
Pokitto	6:ea7377f3d1af	1210
Pokitto	6:ea7377f3d1af	1211	/* TPI Asynchronous Clock Prescaler Register Definitions */
Pokitto	6:ea7377f3d1af	1212	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
Pokitto	6:ea7377f3d1af	1213	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
Pokitto	6:ea7377f3d1af	1214
Pokitto	6:ea7377f3d1af	1215	/* TPI Selected Pin Protocol Register Definitions */
Pokitto	6:ea7377f3d1af	1216	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
Pokitto	6:ea7377f3d1af	1217	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
Pokitto	6:ea7377f3d1af	1218
Pokitto	6:ea7377f3d1af	1219	/* TPI Formatter and Flush Status Register Definitions */
Pokitto	6:ea7377f3d1af	1220	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
Pokitto	6:ea7377f3d1af	1221	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
Pokitto	6:ea7377f3d1af	1222
Pokitto	6:ea7377f3d1af	1223	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
Pokitto	6:ea7377f3d1af	1224	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
Pokitto	6:ea7377f3d1af	1225
Pokitto	6:ea7377f3d1af	1226	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
Pokitto	6:ea7377f3d1af	1227	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
Pokitto	6:ea7377f3d1af	1228
Pokitto	6:ea7377f3d1af	1229	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
Pokitto	6:ea7377f3d1af	1230	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
Pokitto	6:ea7377f3d1af	1231
Pokitto	6:ea7377f3d1af	1232	/* TPI Formatter and Flush Control Register Definitions */
Pokitto	6:ea7377f3d1af	1233	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
Pokitto	6:ea7377f3d1af	1234	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
Pokitto	6:ea7377f3d1af	1235
Pokitto	6:ea7377f3d1af	1236	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
Pokitto	6:ea7377f3d1af	1237	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
Pokitto	6:ea7377f3d1af	1238
Pokitto	6:ea7377f3d1af	1239	/* TPI TRIGGER Register Definitions */
Pokitto	6:ea7377f3d1af	1240	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
Pokitto	6:ea7377f3d1af	1241	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
Pokitto	6:ea7377f3d1af	1242
Pokitto	6:ea7377f3d1af	1243	/* TPI Integration ETM Data Register Definitions (FIFO0) */
Pokitto	6:ea7377f3d1af	1244	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
Pokitto	6:ea7377f3d1af	1245	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
Pokitto	6:ea7377f3d1af	1246
Pokitto	6:ea7377f3d1af	1247	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
Pokitto	6:ea7377f3d1af	1248	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
Pokitto	6:ea7377f3d1af	1249
Pokitto	6:ea7377f3d1af	1250	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
Pokitto	6:ea7377f3d1af	1251	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
Pokitto	6:ea7377f3d1af	1252
Pokitto	6:ea7377f3d1af	1253	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
Pokitto	6:ea7377f3d1af	1254	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
Pokitto	6:ea7377f3d1af	1255
Pokitto	6:ea7377f3d1af	1256	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
Pokitto	6:ea7377f3d1af	1257	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
Pokitto	6:ea7377f3d1af	1258
Pokitto	6:ea7377f3d1af	1259	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
Pokitto	6:ea7377f3d1af	1260	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
Pokitto	6:ea7377f3d1af	1261
Pokitto	6:ea7377f3d1af	1262	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
Pokitto	6:ea7377f3d1af	1263	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
Pokitto	6:ea7377f3d1af	1264
Pokitto	6:ea7377f3d1af	1265	/* TPI ITATBCTR2 Register Definitions */
Pokitto	6:ea7377f3d1af	1266	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
Pokitto	6:ea7377f3d1af	1267	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
Pokitto	6:ea7377f3d1af	1268
Pokitto	6:ea7377f3d1af	1269	/* TPI Integration ITM Data Register Definitions (FIFO1) */
Pokitto	6:ea7377f3d1af	1270	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
Pokitto	6:ea7377f3d1af	1271	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
Pokitto	6:ea7377f3d1af	1272
Pokitto	6:ea7377f3d1af	1273	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
Pokitto	6:ea7377f3d1af	1274	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
Pokitto	6:ea7377f3d1af	1275
Pokitto	6:ea7377f3d1af	1276	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
Pokitto	6:ea7377f3d1af	1277	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
Pokitto	6:ea7377f3d1af	1278
Pokitto	6:ea7377f3d1af	1279	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
Pokitto	6:ea7377f3d1af	1280	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
Pokitto	6:ea7377f3d1af	1281
Pokitto	6:ea7377f3d1af	1282	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
Pokitto	6:ea7377f3d1af	1283	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
Pokitto	6:ea7377f3d1af	1284
Pokitto	6:ea7377f3d1af	1285	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
Pokitto	6:ea7377f3d1af	1286	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
Pokitto	6:ea7377f3d1af	1287
Pokitto	6:ea7377f3d1af	1288	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
Pokitto	6:ea7377f3d1af	1289	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
Pokitto	6:ea7377f3d1af	1290
Pokitto	6:ea7377f3d1af	1291	/* TPI ITATBCTR0 Register Definitions */
Pokitto	6:ea7377f3d1af	1292	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
Pokitto	6:ea7377f3d1af	1293	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
Pokitto	6:ea7377f3d1af	1294
Pokitto	6:ea7377f3d1af	1295	/* TPI Integration Mode Control Register Definitions */
Pokitto	6:ea7377f3d1af	1296	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
Pokitto	6:ea7377f3d1af	1297	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
Pokitto	6:ea7377f3d1af	1298
Pokitto	6:ea7377f3d1af	1299	/* TPI DEVID Register Definitions */
Pokitto	6:ea7377f3d1af	1300	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
Pokitto	6:ea7377f3d1af	1301	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
Pokitto	6:ea7377f3d1af	1302
Pokitto	6:ea7377f3d1af	1303	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
Pokitto	6:ea7377f3d1af	1304	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
Pokitto	6:ea7377f3d1af	1305
Pokitto	6:ea7377f3d1af	1306	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
Pokitto	6:ea7377f3d1af	1307	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
Pokitto	6:ea7377f3d1af	1308
Pokitto	6:ea7377f3d1af	1309	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
Pokitto	6:ea7377f3d1af	1310	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
Pokitto	6:ea7377f3d1af	1311
Pokitto	6:ea7377f3d1af	1312	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
Pokitto	6:ea7377f3d1af	1313	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
Pokitto	6:ea7377f3d1af	1314
Pokitto	6:ea7377f3d1af	1315	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
Pokitto	6:ea7377f3d1af	1316	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
Pokitto	6:ea7377f3d1af	1317
Pokitto	6:ea7377f3d1af	1318	/* TPI DEVTYPE Register Definitions */
Pokitto	6:ea7377f3d1af	1319	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
Pokitto	6:ea7377f3d1af	1320	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
Pokitto	6:ea7377f3d1af	1321
Pokitto	6:ea7377f3d1af	1322	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
Pokitto	6:ea7377f3d1af	1323	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
Pokitto	6:ea7377f3d1af	1324
Pokitto	6:ea7377f3d1af	1325	/@}/ /* end of group CMSIS_TPI */
Pokitto	6:ea7377f3d1af	1326
Pokitto	6:ea7377f3d1af	1327
Pokitto	6:ea7377f3d1af	1328	#if (__MPU_PRESENT == 1)
Pokitto	6:ea7377f3d1af	1329	/** \ingroup CMSIS_core_register
Pokitto	6:ea7377f3d1af	1330	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
Pokitto	6:ea7377f3d1af	1331	\brief Type definitions for the Memory Protection Unit (MPU)
Pokitto	6:ea7377f3d1af	1332	@{
Pokitto	6:ea7377f3d1af	1333	*/
Pokitto	6:ea7377f3d1af	1334
Pokitto	6:ea7377f3d1af	1335	/** \brief Structure type to access the Memory Protection Unit (MPU).
Pokitto	6:ea7377f3d1af	1336	*/
Pokitto	6:ea7377f3d1af	1337	typedef struct
Pokitto	6:ea7377f3d1af	1338	{
Pokitto	6:ea7377f3d1af	1339	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
Pokitto	6:ea7377f3d1af	1340	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
Pokitto	6:ea7377f3d1af	1341	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
Pokitto	6:ea7377f3d1af	1342	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
Pokitto	6:ea7377f3d1af	1343	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
Pokitto	6:ea7377f3d1af	1344	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
Pokitto	6:ea7377f3d1af	1345	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
Pokitto	6:ea7377f3d1af	1346	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
Pokitto	6:ea7377f3d1af	1347	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
Pokitto	6:ea7377f3d1af	1348	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
Pokitto	6:ea7377f3d1af	1349	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
Pokitto	6:ea7377f3d1af	1350	} MPU_Type;
Pokitto	6:ea7377f3d1af	1351
Pokitto	6:ea7377f3d1af	1352	/* MPU Type Register */
Pokitto	6:ea7377f3d1af	1353	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
Pokitto	6:ea7377f3d1af	1354	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
Pokitto	6:ea7377f3d1af	1355
Pokitto	6:ea7377f3d1af	1356	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
Pokitto	6:ea7377f3d1af	1357	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
Pokitto	6:ea7377f3d1af	1358
Pokitto	6:ea7377f3d1af	1359	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
Pokitto	6:ea7377f3d1af	1360	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
Pokitto	6:ea7377f3d1af	1361
Pokitto	6:ea7377f3d1af	1362	/* MPU Control Register */
Pokitto	6:ea7377f3d1af	1363	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
Pokitto	6:ea7377f3d1af	1364	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
Pokitto	6:ea7377f3d1af	1365
Pokitto	6:ea7377f3d1af	1366	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
Pokitto	6:ea7377f3d1af	1367	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
Pokitto	6:ea7377f3d1af	1368
Pokitto	6:ea7377f3d1af	1369	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
Pokitto	6:ea7377f3d1af	1370	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
Pokitto	6:ea7377f3d1af	1371
Pokitto	6:ea7377f3d1af	1372	/* MPU Region Number Register */
Pokitto	6:ea7377f3d1af	1373	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
Pokitto	6:ea7377f3d1af	1374	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
Pokitto	6:ea7377f3d1af	1375
Pokitto	6:ea7377f3d1af	1376	/* MPU Region Base Address Register */
Pokitto	6:ea7377f3d1af	1377	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
Pokitto	6:ea7377f3d1af	1378	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
Pokitto	6:ea7377f3d1af	1379
Pokitto	6:ea7377f3d1af	1380	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
Pokitto	6:ea7377f3d1af	1381	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
Pokitto	6:ea7377f3d1af	1382
Pokitto	6:ea7377f3d1af	1383	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
Pokitto	6:ea7377f3d1af	1384	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
Pokitto	6:ea7377f3d1af	1385
Pokitto	6:ea7377f3d1af	1386	/* MPU Region Attribute and Size Register */
Pokitto	6:ea7377f3d1af	1387	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
Pokitto	6:ea7377f3d1af	1388	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
Pokitto	6:ea7377f3d1af	1389
Pokitto	6:ea7377f3d1af	1390	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
Pokitto	6:ea7377f3d1af	1391	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
Pokitto	6:ea7377f3d1af	1392
Pokitto	6:ea7377f3d1af	1393	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
Pokitto	6:ea7377f3d1af	1394	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
Pokitto	6:ea7377f3d1af	1395
Pokitto	6:ea7377f3d1af	1396	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
Pokitto	6:ea7377f3d1af	1397	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
Pokitto	6:ea7377f3d1af	1398
Pokitto	6:ea7377f3d1af	1399	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
Pokitto	6:ea7377f3d1af	1400	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
Pokitto	6:ea7377f3d1af	1401
Pokitto	6:ea7377f3d1af	1402	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
Pokitto	6:ea7377f3d1af	1403	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
Pokitto	6:ea7377f3d1af	1404
Pokitto	6:ea7377f3d1af	1405	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
Pokitto	6:ea7377f3d1af	1406	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
Pokitto	6:ea7377f3d1af	1407
Pokitto	6:ea7377f3d1af	1408	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
Pokitto	6:ea7377f3d1af	1409	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
Pokitto	6:ea7377f3d1af	1410
Pokitto	6:ea7377f3d1af	1411	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
Pokitto	6:ea7377f3d1af	1412	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
Pokitto	6:ea7377f3d1af	1413
Pokitto	6:ea7377f3d1af	1414	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
Pokitto	6:ea7377f3d1af	1415	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
Pokitto	6:ea7377f3d1af	1416
Pokitto	6:ea7377f3d1af	1417	/@} end of group CMSIS_MPU /
Pokitto	6:ea7377f3d1af	1418	#endif
Pokitto	6:ea7377f3d1af	1419
Pokitto	6:ea7377f3d1af	1420
Pokitto	6:ea7377f3d1af	1421	#if (__FPU_PRESENT == 1)
Pokitto	6:ea7377f3d1af	1422	/** \ingroup CMSIS_core_register
Pokitto	6:ea7377f3d1af	1423	\defgroup CMSIS_FPU Floating Point Unit (FPU)
Pokitto	6:ea7377f3d1af	1424	\brief Type definitions for the Floating Point Unit (FPU)
Pokitto	6:ea7377f3d1af	1425	@{
Pokitto	6:ea7377f3d1af	1426	*/
Pokitto	6:ea7377f3d1af	1427
Pokitto	6:ea7377f3d1af	1428	/** \brief Structure type to access the Floating Point Unit (FPU).
Pokitto	6:ea7377f3d1af	1429	*/
Pokitto	6:ea7377f3d1af	1430	typedef struct
Pokitto	6:ea7377f3d1af	1431	{
Pokitto	6:ea7377f3d1af	1432	uint32_t RESERVED0[1];
Pokitto	6:ea7377f3d1af	1433	__IO uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
Pokitto	6:ea7377f3d1af	1434	__IO uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
Pokitto	6:ea7377f3d1af	1435	__IO uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
Pokitto	6:ea7377f3d1af	1436	__I uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
Pokitto	6:ea7377f3d1af	1437	__I uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
Pokitto	6:ea7377f3d1af	1438	__I uint32_t MVFR2; /!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 /
Pokitto	6:ea7377f3d1af	1439	} FPU_Type;
Pokitto	6:ea7377f3d1af	1440
Pokitto	6:ea7377f3d1af	1441	/* Floating-Point Context Control Register */
Pokitto	6:ea7377f3d1af	1442	#define FPU_FPCCR_ASPEN_Pos 31 /!< FPCCR: ASPEN bit Position /
Pokitto	6:ea7377f3d1af	1443	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
Pokitto	6:ea7377f3d1af	1444
Pokitto	6:ea7377f3d1af	1445	#define FPU_FPCCR_LSPEN_Pos 30 /!< FPCCR: LSPEN Position /
Pokitto	6:ea7377f3d1af	1446	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
Pokitto	6:ea7377f3d1af	1447
Pokitto	6:ea7377f3d1af	1448	#define FPU_FPCCR_MONRDY_Pos 8 /!< FPCCR: MONRDY Position /
Pokitto	6:ea7377f3d1af	1449	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
Pokitto	6:ea7377f3d1af	1450
Pokitto	6:ea7377f3d1af	1451	#define FPU_FPCCR_BFRDY_Pos 6 /!< FPCCR: BFRDY Position /
Pokitto	6:ea7377f3d1af	1452	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
Pokitto	6:ea7377f3d1af	1453
Pokitto	6:ea7377f3d1af	1454	#define FPU_FPCCR_MMRDY_Pos 5 /!< FPCCR: MMRDY Position /
Pokitto	6:ea7377f3d1af	1455	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
Pokitto	6:ea7377f3d1af	1456
Pokitto	6:ea7377f3d1af	1457	#define FPU_FPCCR_HFRDY_Pos 4 /!< FPCCR: HFRDY Position /
Pokitto	6:ea7377f3d1af	1458	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
Pokitto	6:ea7377f3d1af	1459
Pokitto	6:ea7377f3d1af	1460	#define FPU_FPCCR_THREAD_Pos 3 /!< FPCCR: processor mode bit Position /
Pokitto	6:ea7377f3d1af	1461	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
Pokitto	6:ea7377f3d1af	1462
Pokitto	6:ea7377f3d1af	1463	#define FPU_FPCCR_USER_Pos 1 /!< FPCCR: privilege level bit Position /
Pokitto	6:ea7377f3d1af	1464	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
Pokitto	6:ea7377f3d1af	1465
Pokitto	6:ea7377f3d1af	1466	#define FPU_FPCCR_LSPACT_Pos 0 /!< FPCCR: Lazy state preservation active bit Position /
Pokitto	6:ea7377f3d1af	1467	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
Pokitto	6:ea7377f3d1af	1468
Pokitto	6:ea7377f3d1af	1469	/* Floating-Point Context Address Register */
Pokitto	6:ea7377f3d1af	1470	#define FPU_FPCAR_ADDRESS_Pos 3 /!< FPCAR: ADDRESS bit Position /
Pokitto	6:ea7377f3d1af	1471	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
Pokitto	6:ea7377f3d1af	1472
Pokitto	6:ea7377f3d1af	1473	/* Floating-Point Default Status Control Register */
Pokitto	6:ea7377f3d1af	1474	#define FPU_FPDSCR_AHP_Pos 26 /!< FPDSCR: AHP bit Position /
Pokitto	6:ea7377f3d1af	1475	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
Pokitto	6:ea7377f3d1af	1476
Pokitto	6:ea7377f3d1af	1477	#define FPU_FPDSCR_DN_Pos 25 /!< FPDSCR: DN bit Position /
Pokitto	6:ea7377f3d1af	1478	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
Pokitto	6:ea7377f3d1af	1479
Pokitto	6:ea7377f3d1af	1480	#define FPU_FPDSCR_FZ_Pos 24 /!< FPDSCR: FZ bit Position /
Pokitto	6:ea7377f3d1af	1481	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
Pokitto	6:ea7377f3d1af	1482
Pokitto	6:ea7377f3d1af	1483	#define FPU_FPDSCR_RMode_Pos 22 /!< FPDSCR: RMode bit Position /
Pokitto	6:ea7377f3d1af	1484	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
Pokitto	6:ea7377f3d1af	1485
Pokitto	6:ea7377f3d1af	1486	/* Media and FP Feature Register 0 */
Pokitto	6:ea7377f3d1af	1487	#define FPU_MVFR0_FP_rounding_modes_Pos 28 /!< MVFR0: FP rounding modes bits Position /
Pokitto	6:ea7377f3d1af	1488	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
Pokitto	6:ea7377f3d1af	1489
Pokitto	6:ea7377f3d1af	1490	#define FPU_MVFR0_Short_vectors_Pos 24 /!< MVFR0: Short vectors bits Position /
Pokitto	6:ea7377f3d1af	1491	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
Pokitto	6:ea7377f3d1af	1492
Pokitto	6:ea7377f3d1af	1493	#define FPU_MVFR0_Square_root_Pos 20 /!< MVFR0: Square root bits Position /
Pokitto	6:ea7377f3d1af	1494	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
Pokitto	6:ea7377f3d1af	1495
Pokitto	6:ea7377f3d1af	1496	#define FPU_MVFR0_Divide_Pos 16 /!< MVFR0: Divide bits Position /
Pokitto	6:ea7377f3d1af	1497	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
Pokitto	6:ea7377f3d1af	1498
Pokitto	6:ea7377f3d1af	1499	#define FPU_MVFR0_FP_excep_trapping_Pos 12 /!< MVFR0: FP exception trapping bits Position /
Pokitto	6:ea7377f3d1af	1500	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
Pokitto	6:ea7377f3d1af	1501
Pokitto	6:ea7377f3d1af	1502	#define FPU_MVFR0_Double_precision_Pos 8 /!< MVFR0: Double-precision bits Position /
Pokitto	6:ea7377f3d1af	1503	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
Pokitto	6:ea7377f3d1af	1504
Pokitto	6:ea7377f3d1af	1505	#define FPU_MVFR0_Single_precision_Pos 4 /!< MVFR0: Single-precision bits Position /
Pokitto	6:ea7377f3d1af	1506	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
Pokitto	6:ea7377f3d1af	1507
Pokitto	6:ea7377f3d1af	1508	#define FPU_MVFR0_A_SIMD_registers_Pos 0 /!< MVFR0: A_SIMD registers bits Position /
Pokitto	6:ea7377f3d1af	1509	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
Pokitto	6:ea7377f3d1af	1510
Pokitto	6:ea7377f3d1af	1511	/* Media and FP Feature Register 1 */
Pokitto	6:ea7377f3d1af	1512	#define FPU_MVFR1_FP_fused_MAC_Pos 28 /!< MVFR1: FP fused MAC bits Position /
Pokitto	6:ea7377f3d1af	1513	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
Pokitto	6:ea7377f3d1af	1514
Pokitto	6:ea7377f3d1af	1515	#define FPU_MVFR1_FP_HPFP_Pos 24 /!< MVFR1: FP HPFP bits Position /
Pokitto	6:ea7377f3d1af	1516	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
Pokitto	6:ea7377f3d1af	1517
Pokitto	6:ea7377f3d1af	1518	#define FPU_MVFR1_D_NaN_mode_Pos 4 /!< MVFR1: D_NaN mode bits Position /
Pokitto	6:ea7377f3d1af	1519	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
Pokitto	6:ea7377f3d1af	1520
Pokitto	6:ea7377f3d1af	1521	#define FPU_MVFR1_FtZ_mode_Pos 0 /!< MVFR1: FtZ mode bits Position /
Pokitto	6:ea7377f3d1af	1522	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
Pokitto	6:ea7377f3d1af	1523
Pokitto	6:ea7377f3d1af	1524	/* Media and FP Feature Register 2 */
Pokitto	6:ea7377f3d1af	1525
Pokitto	6:ea7377f3d1af	1526	/@} end of group CMSIS_FPU /
Pokitto	6:ea7377f3d1af	1527	#endif
Pokitto	6:ea7377f3d1af	1528
Pokitto	6:ea7377f3d1af	1529
Pokitto	6:ea7377f3d1af	1530	/** \ingroup CMSIS_core_register
Pokitto	6:ea7377f3d1af	1531	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Pokitto	6:ea7377f3d1af	1532	\brief Type definitions for the Core Debug Registers
Pokitto	6:ea7377f3d1af	1533	@{
Pokitto	6:ea7377f3d1af	1534	*/
Pokitto	6:ea7377f3d1af	1535
Pokitto	6:ea7377f3d1af	1536	/** \brief Structure type to access the Core Debug Register (CoreDebug).
Pokitto	6:ea7377f3d1af	1537	*/
Pokitto	6:ea7377f3d1af	1538	typedef struct
Pokitto	6:ea7377f3d1af	1539	{
Pokitto	6:ea7377f3d1af	1540	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
Pokitto	6:ea7377f3d1af	1541	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
Pokitto	6:ea7377f3d1af	1542	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
Pokitto	6:ea7377f3d1af	1543	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
Pokitto	6:ea7377f3d1af	1544	} CoreDebug_Type;
Pokitto	6:ea7377f3d1af	1545
Pokitto	6:ea7377f3d1af	1546	/* Debug Halting Control and Status Register */
Pokitto	6:ea7377f3d1af	1547	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
Pokitto	6:ea7377f3d1af	1548	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
Pokitto	6:ea7377f3d1af	1549
Pokitto	6:ea7377f3d1af	1550	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
Pokitto	6:ea7377f3d1af	1551	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
Pokitto	6:ea7377f3d1af	1552
Pokitto	6:ea7377f3d1af	1553	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
Pokitto	6:ea7377f3d1af	1554	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
Pokitto	6:ea7377f3d1af	1555
Pokitto	6:ea7377f3d1af	1556	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
Pokitto	6:ea7377f3d1af	1557	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
Pokitto	6:ea7377f3d1af	1558
Pokitto	6:ea7377f3d1af	1559	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
Pokitto	6:ea7377f3d1af	1560	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
Pokitto	6:ea7377f3d1af	1561
Pokitto	6:ea7377f3d1af	1562	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
Pokitto	6:ea7377f3d1af	1563	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
Pokitto	6:ea7377f3d1af	1564
Pokitto	6:ea7377f3d1af	1565	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
Pokitto	6:ea7377f3d1af	1566	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
Pokitto	6:ea7377f3d1af	1567
Pokitto	6:ea7377f3d1af	1568	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
Pokitto	6:ea7377f3d1af	1569	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
Pokitto	6:ea7377f3d1af	1570
Pokitto	6:ea7377f3d1af	1571	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
Pokitto	6:ea7377f3d1af	1572	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
Pokitto	6:ea7377f3d1af	1573
Pokitto	6:ea7377f3d1af	1574	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
Pokitto	6:ea7377f3d1af	1575	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
Pokitto	6:ea7377f3d1af	1576
Pokitto	6:ea7377f3d1af	1577	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
Pokitto	6:ea7377f3d1af	1578	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
Pokitto	6:ea7377f3d1af	1579
Pokitto	6:ea7377f3d1af	1580	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
Pokitto	6:ea7377f3d1af	1581	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
Pokitto	6:ea7377f3d1af	1582
Pokitto	6:ea7377f3d1af	1583	/* Debug Core Register Selector Register */
Pokitto	6:ea7377f3d1af	1584	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
Pokitto	6:ea7377f3d1af	1585	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
Pokitto	6:ea7377f3d1af	1586
Pokitto	6:ea7377f3d1af	1587	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
Pokitto	6:ea7377f3d1af	1588	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
Pokitto	6:ea7377f3d1af	1589
Pokitto	6:ea7377f3d1af	1590	/* Debug Exception and Monitor Control Register */
Pokitto	6:ea7377f3d1af	1591	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
Pokitto	6:ea7377f3d1af	1592	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
Pokitto	6:ea7377f3d1af	1593
Pokitto	6:ea7377f3d1af	1594	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
Pokitto	6:ea7377f3d1af	1595	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
Pokitto	6:ea7377f3d1af	1596
Pokitto	6:ea7377f3d1af	1597	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
Pokitto	6:ea7377f3d1af	1598	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
Pokitto	6:ea7377f3d1af	1599
Pokitto	6:ea7377f3d1af	1600	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
Pokitto	6:ea7377f3d1af	1601	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
Pokitto	6:ea7377f3d1af	1602
Pokitto	6:ea7377f3d1af	1603	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
Pokitto	6:ea7377f3d1af	1604	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
Pokitto	6:ea7377f3d1af	1605
Pokitto	6:ea7377f3d1af	1606	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
Pokitto	6:ea7377f3d1af	1607	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
Pokitto	6:ea7377f3d1af	1608
Pokitto	6:ea7377f3d1af	1609	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
Pokitto	6:ea7377f3d1af	1610	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
Pokitto	6:ea7377f3d1af	1611
Pokitto	6:ea7377f3d1af	1612	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
Pokitto	6:ea7377f3d1af	1613	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
Pokitto	6:ea7377f3d1af	1614
Pokitto	6:ea7377f3d1af	1615	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
Pokitto	6:ea7377f3d1af	1616	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
Pokitto	6:ea7377f3d1af	1617
Pokitto	6:ea7377f3d1af	1618	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
Pokitto	6:ea7377f3d1af	1619	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
Pokitto	6:ea7377f3d1af	1620
Pokitto	6:ea7377f3d1af	1621	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
Pokitto	6:ea7377f3d1af	1622	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
Pokitto	6:ea7377f3d1af	1623
Pokitto	6:ea7377f3d1af	1624	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
Pokitto	6:ea7377f3d1af	1625	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
Pokitto	6:ea7377f3d1af	1626
Pokitto	6:ea7377f3d1af	1627	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
Pokitto	6:ea7377f3d1af	1628	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
Pokitto	6:ea7377f3d1af	1629
Pokitto	6:ea7377f3d1af	1630	/@} end of group CMSIS_CoreDebug /
Pokitto	6:ea7377f3d1af	1631
Pokitto	6:ea7377f3d1af	1632
Pokitto	6:ea7377f3d1af	1633	/** \ingroup CMSIS_core_register
Pokitto	6:ea7377f3d1af	1634	\defgroup CMSIS_core_base Core Definitions
Pokitto	6:ea7377f3d1af	1635	\brief Definitions for base addresses, unions, and structures.
Pokitto	6:ea7377f3d1af	1636	@{
Pokitto	6:ea7377f3d1af	1637	*/
Pokitto	6:ea7377f3d1af	1638
Pokitto	6:ea7377f3d1af	1639	/* Memory mapping of Cortex-M4 Hardware */
Pokitto	6:ea7377f3d1af	1640	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
Pokitto	6:ea7377f3d1af	1641	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
Pokitto	6:ea7377f3d1af	1642	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
Pokitto	6:ea7377f3d1af	1643	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
Pokitto	6:ea7377f3d1af	1644	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
Pokitto	6:ea7377f3d1af	1645	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
Pokitto	6:ea7377f3d1af	1646	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
Pokitto	6:ea7377f3d1af	1647	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
Pokitto	6:ea7377f3d1af	1648
Pokitto	6:ea7377f3d1af	1649	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
Pokitto	6:ea7377f3d1af	1650	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
Pokitto	6:ea7377f3d1af	1651	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
Pokitto	6:ea7377f3d1af	1652	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
Pokitto	6:ea7377f3d1af	1653	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
Pokitto	6:ea7377f3d1af	1654	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
Pokitto	6:ea7377f3d1af	1655	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
Pokitto	6:ea7377f3d1af	1656	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
Pokitto	6:ea7377f3d1af	1657
Pokitto	6:ea7377f3d1af	1658	#if (__MPU_PRESENT == 1)
Pokitto	6:ea7377f3d1af	1659	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
Pokitto	6:ea7377f3d1af	1660	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
Pokitto	6:ea7377f3d1af	1661	#endif
Pokitto	6:ea7377f3d1af	1662
Pokitto	6:ea7377f3d1af	1663	#if (__FPU_PRESENT == 1)
Pokitto	6:ea7377f3d1af	1664	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
Pokitto	6:ea7377f3d1af	1665	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
Pokitto	6:ea7377f3d1af	1666	#endif
Pokitto	6:ea7377f3d1af	1667
Pokitto	6:ea7377f3d1af	1668	/@} /
Pokitto	6:ea7377f3d1af	1669
Pokitto	6:ea7377f3d1af	1670
Pokitto	6:ea7377f3d1af	1671
Pokitto	6:ea7377f3d1af	1672	/*******************************************************************************
Pokitto	6:ea7377f3d1af	1673	* Hardware Abstraction Layer
Pokitto	6:ea7377f3d1af	1674	Core Function Interface contains:
Pokitto	6:ea7377f3d1af	1675	- Core NVIC Functions
Pokitto	6:ea7377f3d1af	1676	- Core SysTick Functions
Pokitto	6:ea7377f3d1af	1677	- Core Debug Functions
Pokitto	6:ea7377f3d1af	1678	- Core Register Access Functions
Pokitto	6:ea7377f3d1af	1679	******************************************************************************/
Pokitto	6:ea7377f3d1af	1680	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Pokitto	6:ea7377f3d1af	1681	*/
Pokitto	6:ea7377f3d1af	1682
Pokitto	6:ea7377f3d1af	1683
Pokitto	6:ea7377f3d1af	1684
Pokitto	6:ea7377f3d1af	1685	/* ########################## NVIC functions #################################### */
Pokitto	6:ea7377f3d1af	1686	/** \ingroup CMSIS_Core_FunctionInterface
Pokitto	6:ea7377f3d1af	1687	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
Pokitto	6:ea7377f3d1af	1688	\brief Functions that manage interrupts and exceptions via the NVIC.
Pokitto	6:ea7377f3d1af	1689	@{
Pokitto	6:ea7377f3d1af	1690	*/
Pokitto	6:ea7377f3d1af	1691
Pokitto	6:ea7377f3d1af	1692	/** \brief Set Priority Grouping
Pokitto	6:ea7377f3d1af	1693
Pokitto	6:ea7377f3d1af	1694	The function sets the priority grouping field using the required unlock sequence.
Pokitto	6:ea7377f3d1af	1695	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Pokitto	6:ea7377f3d1af	1696	Only values from 0..7 are used.
Pokitto	6:ea7377f3d1af	1697	In case of a conflict between priority grouping and available
Pokitto	6:ea7377f3d1af	1698	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Pokitto	6:ea7377f3d1af	1699
Pokitto	6:ea7377f3d1af	1700	\param [in] PriorityGroup Priority grouping field.
Pokitto	6:ea7377f3d1af	1701	*/
Pokitto	6:ea7377f3d1af	1702	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Pokitto	6:ea7377f3d1af	1703	{
Pokitto	6:ea7377f3d1af	1704	uint32_t reg_value;
Pokitto	6:ea7377f3d1af	1705	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Pokitto	6:ea7377f3d1af	1706
Pokitto	6:ea7377f3d1af	1707	reg_value = SCB->AIRCR; /* read old register configuration */
Pokitto	6:ea7377f3d1af	1708	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Pokitto	6:ea7377f3d1af	1709	reg_value = (reg_value \|
Pokitto	6:ea7377f3d1af	1710	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Pokitto	6:ea7377f3d1af	1711	(PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
Pokitto	6:ea7377f3d1af	1712	SCB->AIRCR = reg_value;
Pokitto	6:ea7377f3d1af	1713	}
Pokitto	6:ea7377f3d1af	1714
Pokitto	6:ea7377f3d1af	1715
Pokitto	6:ea7377f3d1af	1716	/** \brief Get Priority Grouping
Pokitto	6:ea7377f3d1af	1717
Pokitto	6:ea7377f3d1af	1718	The function reads the priority grouping field from the NVIC Interrupt Controller.
Pokitto	6:ea7377f3d1af	1719
Pokitto	6:ea7377f3d1af	1720	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Pokitto	6:ea7377f3d1af	1721	*/
Pokitto	6:ea7377f3d1af	1722	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Pokitto	6:ea7377f3d1af	1723	{
Pokitto	6:ea7377f3d1af	1724	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Pokitto	6:ea7377f3d1af	1725	}
Pokitto	6:ea7377f3d1af	1726
Pokitto	6:ea7377f3d1af	1727
Pokitto	6:ea7377f3d1af	1728	/** \brief Enable External Interrupt
Pokitto	6:ea7377f3d1af	1729
Pokitto	6:ea7377f3d1af	1730	The function enables a device-specific interrupt in the NVIC interrupt controller.
Pokitto	6:ea7377f3d1af	1731
Pokitto	6:ea7377f3d1af	1732	\param [in] IRQn External interrupt number. Value cannot be negative.
Pokitto	6:ea7377f3d1af	1733	*/
Pokitto	6:ea7377f3d1af	1734	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Pokitto	6:ea7377f3d1af	1735	{
Pokitto	6:ea7377f3d1af	1736	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Pokitto	6:ea7377f3d1af	1737	}
Pokitto	6:ea7377f3d1af	1738
Pokitto	6:ea7377f3d1af	1739
Pokitto	6:ea7377f3d1af	1740	/** \brief Disable External Interrupt
Pokitto	6:ea7377f3d1af	1741
Pokitto	6:ea7377f3d1af	1742	The function disables a device-specific interrupt in the NVIC interrupt controller.
Pokitto	6:ea7377f3d1af	1743
Pokitto	6:ea7377f3d1af	1744	\param [in] IRQn External interrupt number. Value cannot be negative.
Pokitto	6:ea7377f3d1af	1745	*/
Pokitto	6:ea7377f3d1af	1746	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Pokitto	6:ea7377f3d1af	1747	{
Pokitto	6:ea7377f3d1af	1748	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Pokitto	6:ea7377f3d1af	1749	}
Pokitto	6:ea7377f3d1af	1750
Pokitto	6:ea7377f3d1af	1751
Pokitto	6:ea7377f3d1af	1752	/** \brief Get Pending Interrupt
Pokitto	6:ea7377f3d1af	1753
Pokitto	6:ea7377f3d1af	1754	The function reads the pending register in the NVIC and returns the pending bit
Pokitto	6:ea7377f3d1af	1755	for the specified interrupt.
Pokitto	6:ea7377f3d1af	1756
Pokitto	6:ea7377f3d1af	1757	\param [in] IRQn Interrupt number.
Pokitto	6:ea7377f3d1af	1758
Pokitto	6:ea7377f3d1af	1759	\return 0 Interrupt status is not pending.
Pokitto	6:ea7377f3d1af	1760	\return 1 Interrupt status is pending.
Pokitto	6:ea7377f3d1af	1761	*/
Pokitto	6:ea7377f3d1af	1762	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Pokitto	6:ea7377f3d1af	1763	{
Pokitto	6:ea7377f3d1af	1764	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Pokitto	6:ea7377f3d1af	1765	}
Pokitto	6:ea7377f3d1af	1766
Pokitto	6:ea7377f3d1af	1767
Pokitto	6:ea7377f3d1af	1768	/** \brief Set Pending Interrupt
Pokitto	6:ea7377f3d1af	1769
Pokitto	6:ea7377f3d1af	1770	The function sets the pending bit of an external interrupt.
Pokitto	6:ea7377f3d1af	1771
Pokitto	6:ea7377f3d1af	1772	\param [in] IRQn Interrupt number. Value cannot be negative.
Pokitto	6:ea7377f3d1af	1773	*/
Pokitto	6:ea7377f3d1af	1774	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Pokitto	6:ea7377f3d1af	1775	{
Pokitto	6:ea7377f3d1af	1776	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Pokitto	6:ea7377f3d1af	1777	}
Pokitto	6:ea7377f3d1af	1778
Pokitto	6:ea7377f3d1af	1779
Pokitto	6:ea7377f3d1af	1780	/** \brief Clear Pending Interrupt
Pokitto	6:ea7377f3d1af	1781
Pokitto	6:ea7377f3d1af	1782	The function clears the pending bit of an external interrupt.
Pokitto	6:ea7377f3d1af	1783
Pokitto	6:ea7377f3d1af	1784	\param [in] IRQn External interrupt number. Value cannot be negative.
Pokitto	6:ea7377f3d1af	1785	*/
Pokitto	6:ea7377f3d1af	1786	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Pokitto	6:ea7377f3d1af	1787	{
Pokitto	6:ea7377f3d1af	1788	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Pokitto	6:ea7377f3d1af	1789	}
Pokitto	6:ea7377f3d1af	1790
Pokitto	6:ea7377f3d1af	1791
Pokitto	6:ea7377f3d1af	1792	/** \brief Get Active Interrupt
Pokitto	6:ea7377f3d1af	1793
Pokitto	6:ea7377f3d1af	1794	The function reads the active register in NVIC and returns the active bit.
Pokitto	6:ea7377f3d1af	1795
Pokitto	6:ea7377f3d1af	1796	\param [in] IRQn Interrupt number.
Pokitto	6:ea7377f3d1af	1797
Pokitto	6:ea7377f3d1af	1798	\return 0 Interrupt status is not active.
Pokitto	6:ea7377f3d1af	1799	\return 1 Interrupt status is active.
Pokitto	6:ea7377f3d1af	1800	*/
Pokitto	6:ea7377f3d1af	1801	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Pokitto	6:ea7377f3d1af	1802	{
Pokitto	6:ea7377f3d1af	1803	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Pokitto	6:ea7377f3d1af	1804	}
Pokitto	6:ea7377f3d1af	1805
Pokitto	6:ea7377f3d1af	1806
Pokitto	6:ea7377f3d1af	1807	/** \brief Set Interrupt Priority
Pokitto	6:ea7377f3d1af	1808
Pokitto	6:ea7377f3d1af	1809	The function sets the priority of an interrupt.
Pokitto	6:ea7377f3d1af	1810
Pokitto	6:ea7377f3d1af	1811	\note The priority cannot be set for every core interrupt.
Pokitto	6:ea7377f3d1af	1812
Pokitto	6:ea7377f3d1af	1813	\param [in] IRQn Interrupt number.
Pokitto	6:ea7377f3d1af	1814	\param [in] priority Priority to set.
Pokitto	6:ea7377f3d1af	1815	*/
Pokitto	6:ea7377f3d1af	1816	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Pokitto	6:ea7377f3d1af	1817	{
Pokitto	6:ea7377f3d1af	1818	if((int32_t)IRQn < 0) {
Pokitto	6:ea7377f3d1af	1819	SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Pokitto	6:ea7377f3d1af	1820	}
Pokitto	6:ea7377f3d1af	1821	else {
Pokitto	6:ea7377f3d1af	1822	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Pokitto	6:ea7377f3d1af	1823	}
Pokitto	6:ea7377f3d1af	1824	}
Pokitto	6:ea7377f3d1af	1825
Pokitto	6:ea7377f3d1af	1826
Pokitto	6:ea7377f3d1af	1827	/** \brief Get Interrupt Priority
Pokitto	6:ea7377f3d1af	1828
Pokitto	6:ea7377f3d1af	1829	The function reads the priority of an interrupt. The interrupt
Pokitto	6:ea7377f3d1af	1830	number can be positive to specify an external (device specific)
Pokitto	6:ea7377f3d1af	1831	interrupt, or negative to specify an internal (core) interrupt.
Pokitto	6:ea7377f3d1af	1832
Pokitto	6:ea7377f3d1af	1833
Pokitto	6:ea7377f3d1af	1834	\param [in] IRQn Interrupt number.
Pokitto	6:ea7377f3d1af	1835	\return Interrupt Priority. Value is aligned automatically to the implemented
Pokitto	6:ea7377f3d1af	1836	priority bits of the microcontroller.
Pokitto	6:ea7377f3d1af	1837	*/
Pokitto	6:ea7377f3d1af	1838	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Pokitto	6:ea7377f3d1af	1839	{
Pokitto	6:ea7377f3d1af	1840
Pokitto	6:ea7377f3d1af	1841	if((int32_t)IRQn < 0) {
Pokitto	6:ea7377f3d1af	1842	return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
Pokitto	6:ea7377f3d1af	1843	}
Pokitto	6:ea7377f3d1af	1844	else {
Pokitto	6:ea7377f3d1af	1845	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
Pokitto	6:ea7377f3d1af	1846	}
Pokitto	6:ea7377f3d1af	1847	}
Pokitto	6:ea7377f3d1af	1848
Pokitto	6:ea7377f3d1af	1849
Pokitto	6:ea7377f3d1af	1850	/** \brief Encode Priority
Pokitto	6:ea7377f3d1af	1851
Pokitto	6:ea7377f3d1af	1852	The function encodes the priority for an interrupt with the given priority group,
Pokitto	6:ea7377f3d1af	1853	preemptive priority value, and subpriority value.
Pokitto	6:ea7377f3d1af	1854	In case of a conflict between priority grouping and available
Pokitto	6:ea7377f3d1af	1855	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Pokitto	6:ea7377f3d1af	1856
Pokitto	6:ea7377f3d1af	1857	\param [in] PriorityGroup Used priority group.
Pokitto	6:ea7377f3d1af	1858	\param [in] PreemptPriority Preemptive priority value (starting from 0).
Pokitto	6:ea7377f3d1af	1859	\param [in] SubPriority Subpriority value (starting from 0).
Pokitto	6:ea7377f3d1af	1860	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Pokitto	6:ea7377f3d1af	1861	*/
Pokitto	6:ea7377f3d1af	1862	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Pokitto	6:ea7377f3d1af	1863	{
Pokitto	6:ea7377f3d1af	1864	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Pokitto	6:ea7377f3d1af	1865	uint32_t PreemptPriorityBits;
Pokitto	6:ea7377f3d1af	1866	uint32_t SubPriorityBits;
Pokitto	6:ea7377f3d1af	1867
Pokitto	6:ea7377f3d1af	1868	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Pokitto	6:ea7377f3d1af	1869	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Pokitto	6:ea7377f3d1af	1870
Pokitto	6:ea7377f3d1af	1871	return (
Pokitto	6:ea7377f3d1af	1872	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
Pokitto	6:ea7377f3d1af	1873	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
Pokitto	6:ea7377f3d1af	1874	);
Pokitto	6:ea7377f3d1af	1875	}
Pokitto	6:ea7377f3d1af	1876
Pokitto	6:ea7377f3d1af	1877
Pokitto	6:ea7377f3d1af	1878	/** \brief Decode Priority
Pokitto	6:ea7377f3d1af	1879
Pokitto	6:ea7377f3d1af	1880	The function decodes an interrupt priority value with a given priority group to
Pokitto	6:ea7377f3d1af	1881	preemptive priority value and subpriority value.
Pokitto	6:ea7377f3d1af	1882	In case of a conflict between priority grouping and available
Pokitto	6:ea7377f3d1af	1883	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Pokitto	6:ea7377f3d1af	1884
Pokitto	6:ea7377f3d1af	1885	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Pokitto	6:ea7377f3d1af	1886	\param [in] PriorityGroup Used priority group.
Pokitto	6:ea7377f3d1af	1887	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
Pokitto	6:ea7377f3d1af	1888	\param [out] pSubPriority Subpriority value (starting from 0).
Pokitto	6:ea7377f3d1af	1889	*/
Pokitto	6:ea7377f3d1af	1890	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
Pokitto	6:ea7377f3d1af	1891	{
Pokitto	6:ea7377f3d1af	1892	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Pokitto	6:ea7377f3d1af	1893	uint32_t PreemptPriorityBits;
Pokitto	6:ea7377f3d1af	1894	uint32_t SubPriorityBits;
Pokitto	6:ea7377f3d1af	1895
Pokitto	6:ea7377f3d1af	1896	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Pokitto	6:ea7377f3d1af	1897	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Pokitto	6:ea7377f3d1af	1898
Pokitto	6:ea7377f3d1af	1899	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Pokitto	6:ea7377f3d1af	1900	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
Pokitto	6:ea7377f3d1af	1901	}
Pokitto	6:ea7377f3d1af	1902
Pokitto	6:ea7377f3d1af	1903
Pokitto	6:ea7377f3d1af	1904	/** \brief System Reset
Pokitto	6:ea7377f3d1af	1905
Pokitto	6:ea7377f3d1af	1906	The function initiates a system reset request to reset the MCU.
Pokitto	6:ea7377f3d1af	1907	*/
Pokitto	6:ea7377f3d1af	1908	__STATIC_INLINE void NVIC_SystemReset(void)
Pokitto	6:ea7377f3d1af	1909	{
Pokitto	6:ea7377f3d1af	1910	__DSB(); /* Ensure all outstanding memory accesses included
Pokitto	6:ea7377f3d1af	1911	buffered write are completed before reset */
Pokitto	6:ea7377f3d1af	1912	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Pokitto	6:ea7377f3d1af	1913	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
Pokitto	6:ea7377f3d1af	1914	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Pokitto	6:ea7377f3d1af	1915	__DSB(); /* Ensure completion of memory access */
Pokitto	6:ea7377f3d1af	1916	while(1) { __NOP(); } /* wait until reset */
Pokitto	6:ea7377f3d1af	1917	}
Pokitto	6:ea7377f3d1af	1918
Pokitto	6:ea7377f3d1af	1919	/@} end of CMSIS_Core_NVICFunctions /
Pokitto	6:ea7377f3d1af	1920
Pokitto	6:ea7377f3d1af	1921
Pokitto	6:ea7377f3d1af	1922	/* ########################## FPU functions #################################### */
Pokitto	6:ea7377f3d1af	1923	/** \ingroup CMSIS_Core_FunctionInterface
Pokitto	6:ea7377f3d1af	1924	\defgroup CMSIS_Core_FpuFunctions FPU Functions
Pokitto	6:ea7377f3d1af	1925	\brief Function that provides FPU type.
Pokitto	6:ea7377f3d1af	1926	@{
Pokitto	6:ea7377f3d1af	1927	*/
Pokitto	6:ea7377f3d1af	1928
Pokitto	6:ea7377f3d1af	1929	/**
Pokitto	6:ea7377f3d1af	1930	\fn uint32_t SCB_GetFPUType(void)
Pokitto	6:ea7377f3d1af	1931	\brief get FPU type
Pokitto	6:ea7377f3d1af	1932	\returns
Pokitto	6:ea7377f3d1af	1933	- \b 0: No FPU
Pokitto	6:ea7377f3d1af	1934	- \b 1: Single precision FPU
Pokitto	6:ea7377f3d1af	1935	- \b 2: Double + Single precision FPU
Pokitto	6:ea7377f3d1af	1936	*/
Pokitto	6:ea7377f3d1af	1937	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
Pokitto	6:ea7377f3d1af	1938	{
Pokitto	6:ea7377f3d1af	1939	uint32_t mvfr0;
Pokitto	6:ea7377f3d1af	1940
Pokitto	6:ea7377f3d1af	1941	mvfr0 = SCB->MVFR0;
Pokitto	6:ea7377f3d1af	1942	if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
Pokitto	6:ea7377f3d1af	1943	return 2UL; // Double + Single precision FPU
Pokitto	6:ea7377f3d1af	1944	} else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
Pokitto	6:ea7377f3d1af	1945	return 1UL; // Single precision FPU
Pokitto	6:ea7377f3d1af	1946	} else {
Pokitto	6:ea7377f3d1af	1947	return 0UL; // No FPU
Pokitto	6:ea7377f3d1af	1948	}
Pokitto	6:ea7377f3d1af	1949	}
Pokitto	6:ea7377f3d1af	1950
Pokitto	6:ea7377f3d1af	1951
Pokitto	6:ea7377f3d1af	1952	/@} end of CMSIS_Core_FpuFunctions /
Pokitto	6:ea7377f3d1af	1953
Pokitto	6:ea7377f3d1af	1954
Pokitto	6:ea7377f3d1af	1955
Pokitto	6:ea7377f3d1af	1956	/* ########################## Cache functions #################################### */
Pokitto	6:ea7377f3d1af	1957	/** \ingroup CMSIS_Core_FunctionInterface
Pokitto	6:ea7377f3d1af	1958	\defgroup CMSIS_Core_CacheFunctions Cache Functions
Pokitto	6:ea7377f3d1af	1959	\brief Functions that configure Instruction and Data cache.
Pokitto	6:ea7377f3d1af	1960	@{
Pokitto	6:ea7377f3d1af	1961	*/
Pokitto	6:ea7377f3d1af	1962
Pokitto	6:ea7377f3d1af	1963	/* Cache Size ID Register Macros */
Pokitto	6:ea7377f3d1af	1964	#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
Pokitto	6:ea7377f3d1af	1965	#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
Pokitto	6:ea7377f3d1af	1966	#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) />> SCB_CCSIDR_LINESIZE_Pos/ )
Pokitto	6:ea7377f3d1af	1967
Pokitto	6:ea7377f3d1af	1968
Pokitto	6:ea7377f3d1af	1969	/** \brief Enable I-Cache
Pokitto	6:ea7377f3d1af	1970
Pokitto	6:ea7377f3d1af	1971	The function turns on I-Cache
Pokitto	6:ea7377f3d1af	1972	*/
Pokitto	6:ea7377f3d1af	1973	__STATIC_INLINE void SCB_EnableICache (void)
Pokitto	6:ea7377f3d1af	1974	{
Pokitto	6:ea7377f3d1af	1975	#if (__ICACHE_PRESENT == 1)
Pokitto	6:ea7377f3d1af	1976	__DSB();
Pokitto	6:ea7377f3d1af	1977	__ISB();
Pokitto	6:ea7377f3d1af	1978	SCB->ICIALLU = 0UL; // invalidate I-Cache
Pokitto	6:ea7377f3d1af	1979	SCB->CCR \|= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache
Pokitto	6:ea7377f3d1af	1980	__DSB();
Pokitto	6:ea7377f3d1af	1981	__ISB();
Pokitto	6:ea7377f3d1af	1982	#endif
Pokitto	6:ea7377f3d1af	1983	}
Pokitto	6:ea7377f3d1af	1984
Pokitto	6:ea7377f3d1af	1985
Pokitto	6:ea7377f3d1af	1986	/** \brief Disable I-Cache
Pokitto	6:ea7377f3d1af	1987
Pokitto	6:ea7377f3d1af	1988	The function turns off I-Cache
Pokitto	6:ea7377f3d1af	1989	*/
Pokitto	6:ea7377f3d1af	1990	__STATIC_INLINE void SCB_DisableICache (void)
Pokitto	6:ea7377f3d1af	1991	{
Pokitto	6:ea7377f3d1af	1992	#if (__ICACHE_PRESENT == 1)
Pokitto	6:ea7377f3d1af	1993	__DSB();
Pokitto	6:ea7377f3d1af	1994	__ISB();
Pokitto	6:ea7377f3d1af	1995	SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache
Pokitto	6:ea7377f3d1af	1996	SCB->ICIALLU = 0UL; // invalidate I-Cache
Pokitto	6:ea7377f3d1af	1997	__DSB();
Pokitto	6:ea7377f3d1af	1998	__ISB();
Pokitto	6:ea7377f3d1af	1999	#endif
Pokitto	6:ea7377f3d1af	2000	}
Pokitto	6:ea7377f3d1af	2001
Pokitto	6:ea7377f3d1af	2002
Pokitto	6:ea7377f3d1af	2003	/** \brief Invalidate I-Cache
Pokitto	6:ea7377f3d1af	2004
Pokitto	6:ea7377f3d1af	2005	The function invalidates I-Cache
Pokitto	6:ea7377f3d1af	2006	*/
Pokitto	6:ea7377f3d1af	2007	__STATIC_INLINE void SCB_InvalidateICache (void)
Pokitto	6:ea7377f3d1af	2008	{
Pokitto	6:ea7377f3d1af	2009	#if (__ICACHE_PRESENT == 1)
Pokitto	6:ea7377f3d1af	2010	__DSB();
Pokitto	6:ea7377f3d1af	2011	__ISB();
Pokitto	6:ea7377f3d1af	2012	SCB->ICIALLU = 0UL;
Pokitto	6:ea7377f3d1af	2013	__DSB();
Pokitto	6:ea7377f3d1af	2014	__ISB();
Pokitto	6:ea7377f3d1af	2015	#endif
Pokitto	6:ea7377f3d1af	2016	}
Pokitto	6:ea7377f3d1af	2017
Pokitto	6:ea7377f3d1af	2018
Pokitto	6:ea7377f3d1af	2019	/** \brief Enable D-Cache
Pokitto	6:ea7377f3d1af	2020
Pokitto	6:ea7377f3d1af	2021	The function turns on D-Cache
Pokitto	6:ea7377f3d1af	2022	*/
Pokitto	6:ea7377f3d1af	2023	__STATIC_INLINE void SCB_EnableDCache (void)
Pokitto	6:ea7377f3d1af	2024	{
Pokitto	6:ea7377f3d1af	2025	#if (__DCACHE_PRESENT == 1)
Pokitto	6:ea7377f3d1af	2026	uint32_t ccsidr, sshift, wshift, sw;
Pokitto	6:ea7377f3d1af	2027	uint32_t sets, ways;
Pokitto	6:ea7377f3d1af	2028
Pokitto	6:ea7377f3d1af	2029	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
Pokitto	6:ea7377f3d1af	2030	ccsidr = SCB->CCSIDR;
Pokitto	6:ea7377f3d1af	2031	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Pokitto	6:ea7377f3d1af	2032	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Pokitto	6:ea7377f3d1af	2033	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Pokitto	6:ea7377f3d1af	2034	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Pokitto	6:ea7377f3d1af	2035
Pokitto	6:ea7377f3d1af	2036	__DSB();
Pokitto	6:ea7377f3d1af	2037
Pokitto	6:ea7377f3d1af	2038	do { // invalidate D-Cache
Pokitto	6:ea7377f3d1af	2039	uint32_t tmpways = ways;
Pokitto	6:ea7377f3d1af	2040	do {
Pokitto	6:ea7377f3d1af	2041	sw = ((tmpways << wshift) \| (sets << sshift));
Pokitto	6:ea7377f3d1af	2042	SCB->DCISW = sw;
Pokitto	6:ea7377f3d1af	2043	} while(tmpways--);
Pokitto	6:ea7377f3d1af	2044	} while(sets--);
Pokitto	6:ea7377f3d1af	2045	__DSB();
Pokitto	6:ea7377f3d1af	2046
Pokitto	6:ea7377f3d1af	2047	SCB->CCR \|= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache
Pokitto	6:ea7377f3d1af	2048
Pokitto	6:ea7377f3d1af	2049	__DSB();
Pokitto	6:ea7377f3d1af	2050	__ISB();
Pokitto	6:ea7377f3d1af	2051	#endif
Pokitto	6:ea7377f3d1af	2052	}
Pokitto	6:ea7377f3d1af	2053
Pokitto	6:ea7377f3d1af	2054
Pokitto	6:ea7377f3d1af	2055	/** \brief Disable D-Cache
Pokitto	6:ea7377f3d1af	2056
Pokitto	6:ea7377f3d1af	2057	The function turns off D-Cache
Pokitto	6:ea7377f3d1af	2058	*/
Pokitto	6:ea7377f3d1af	2059	__STATIC_INLINE void SCB_DisableDCache (void)
Pokitto	6:ea7377f3d1af	2060	{
Pokitto	6:ea7377f3d1af	2061	#if (__DCACHE_PRESENT == 1)
Pokitto	6:ea7377f3d1af	2062	uint32_t ccsidr, sshift, wshift, sw;
Pokitto	6:ea7377f3d1af	2063	uint32_t sets, ways;
Pokitto	6:ea7377f3d1af	2064
Pokitto	6:ea7377f3d1af	2065	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
Pokitto	6:ea7377f3d1af	2066	ccsidr = SCB->CCSIDR;
Pokitto	6:ea7377f3d1af	2067	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Pokitto	6:ea7377f3d1af	2068	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Pokitto	6:ea7377f3d1af	2069	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Pokitto	6:ea7377f3d1af	2070	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Pokitto	6:ea7377f3d1af	2071
Pokitto	6:ea7377f3d1af	2072	__DSB();
Pokitto	6:ea7377f3d1af	2073
Pokitto	6:ea7377f3d1af	2074	SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache
Pokitto	6:ea7377f3d1af	2075
Pokitto	6:ea7377f3d1af	2076	do { // clean & invalidate D-Cache
Pokitto	6:ea7377f3d1af	2077	uint32_t tmpways = ways;
Pokitto	6:ea7377f3d1af	2078	do {
Pokitto	6:ea7377f3d1af	2079	sw = ((tmpways << wshift) \| (sets << sshift));
Pokitto	6:ea7377f3d1af	2080	SCB->DCCISW = sw;
Pokitto	6:ea7377f3d1af	2081	} while(tmpways--);
Pokitto	6:ea7377f3d1af	2082	} while(sets--);
Pokitto	6:ea7377f3d1af	2083
Pokitto	6:ea7377f3d1af	2084
Pokitto	6:ea7377f3d1af	2085	__DSB();
Pokitto	6:ea7377f3d1af	2086	__ISB();
Pokitto	6:ea7377f3d1af	2087	#endif
Pokitto	6:ea7377f3d1af	2088	}
Pokitto	6:ea7377f3d1af	2089
Pokitto	6:ea7377f3d1af	2090
Pokitto	6:ea7377f3d1af	2091	/** \brief Invalidate D-Cache
Pokitto	6:ea7377f3d1af	2092
Pokitto	6:ea7377f3d1af	2093	The function invalidates D-Cache
Pokitto	6:ea7377f3d1af	2094	*/
Pokitto	6:ea7377f3d1af	2095	__STATIC_INLINE void SCB_InvalidateDCache (void)
Pokitto	6:ea7377f3d1af	2096	{
Pokitto	6:ea7377f3d1af	2097	#if (__DCACHE_PRESENT == 1)
Pokitto	6:ea7377f3d1af	2098	uint32_t ccsidr, sshift, wshift, sw;
Pokitto	6:ea7377f3d1af	2099	uint32_t sets, ways;
Pokitto	6:ea7377f3d1af	2100
Pokitto	6:ea7377f3d1af	2101	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
Pokitto	6:ea7377f3d1af	2102	ccsidr = SCB->CCSIDR;
Pokitto	6:ea7377f3d1af	2103	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Pokitto	6:ea7377f3d1af	2104	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Pokitto	6:ea7377f3d1af	2105	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Pokitto	6:ea7377f3d1af	2106	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Pokitto	6:ea7377f3d1af	2107
Pokitto	6:ea7377f3d1af	2108	__DSB();
Pokitto	6:ea7377f3d1af	2109
Pokitto	6:ea7377f3d1af	2110	do { // invalidate D-Cache
Pokitto	6:ea7377f3d1af	2111	uint32_t tmpways = ways;
Pokitto	6:ea7377f3d1af	2112	do {
Pokitto	6:ea7377f3d1af	2113	sw = ((tmpways << wshift) \| (sets << sshift));
Pokitto	6:ea7377f3d1af	2114	SCB->DCISW = sw;
Pokitto	6:ea7377f3d1af	2115	} while(tmpways--);
Pokitto	6:ea7377f3d1af	2116	} while(sets--);
Pokitto	6:ea7377f3d1af	2117
Pokitto	6:ea7377f3d1af	2118	__DSB();
Pokitto	6:ea7377f3d1af	2119	__ISB();
Pokitto	6:ea7377f3d1af	2120	#endif
Pokitto	6:ea7377f3d1af	2121	}
Pokitto	6:ea7377f3d1af	2122
Pokitto	6:ea7377f3d1af	2123
Pokitto	6:ea7377f3d1af	2124	/** \brief Clean D-Cache
Pokitto	6:ea7377f3d1af	2125
Pokitto	6:ea7377f3d1af	2126	The function cleans D-Cache
Pokitto	6:ea7377f3d1af	2127	*/
Pokitto	6:ea7377f3d1af	2128	__STATIC_INLINE void SCB_CleanDCache (void)
Pokitto	6:ea7377f3d1af	2129	{
Pokitto	6:ea7377f3d1af	2130	#if (__DCACHE_PRESENT == 1)
Pokitto	6:ea7377f3d1af	2131	uint32_t ccsidr, sshift, wshift, sw;
Pokitto	6:ea7377f3d1af	2132	uint32_t sets, ways;
Pokitto	6:ea7377f3d1af	2133
Pokitto	6:ea7377f3d1af	2134	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
Pokitto	6:ea7377f3d1af	2135	ccsidr = SCB->CCSIDR;
Pokitto	6:ea7377f3d1af	2136	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Pokitto	6:ea7377f3d1af	2137	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Pokitto	6:ea7377f3d1af	2138	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Pokitto	6:ea7377f3d1af	2139	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Pokitto	6:ea7377f3d1af	2140
Pokitto	6:ea7377f3d1af	2141	__DSB();
Pokitto	6:ea7377f3d1af	2142
Pokitto	6:ea7377f3d1af	2143	do { // clean D-Cache
Pokitto	6:ea7377f3d1af	2144	uint32_t tmpways = ways;
Pokitto	6:ea7377f3d1af	2145	do {
Pokitto	6:ea7377f3d1af	2146	sw = ((tmpways << wshift) \| (sets << sshift));
Pokitto	6:ea7377f3d1af	2147	SCB->DCCSW = sw;
Pokitto	6:ea7377f3d1af	2148	} while(tmpways--);
Pokitto	6:ea7377f3d1af	2149	} while(sets--);
Pokitto	6:ea7377f3d1af	2150
Pokitto	6:ea7377f3d1af	2151	__DSB();
Pokitto	6:ea7377f3d1af	2152	__ISB();
Pokitto	6:ea7377f3d1af	2153	#endif
Pokitto	6:ea7377f3d1af	2154	}
Pokitto	6:ea7377f3d1af	2155
Pokitto	6:ea7377f3d1af	2156
Pokitto	6:ea7377f3d1af	2157	/** \brief Clean & Invalidate D-Cache
Pokitto	6:ea7377f3d1af	2158
Pokitto	6:ea7377f3d1af	2159	The function cleans and Invalidates D-Cache
Pokitto	6:ea7377f3d1af	2160	*/
Pokitto	6:ea7377f3d1af	2161	__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
Pokitto	6:ea7377f3d1af	2162	{
Pokitto	6:ea7377f3d1af	2163	#if (__DCACHE_PRESENT == 1)
Pokitto	6:ea7377f3d1af	2164	uint32_t ccsidr, sshift, wshift, sw;
Pokitto	6:ea7377f3d1af	2165	uint32_t sets, ways;
Pokitto	6:ea7377f3d1af	2166
Pokitto	6:ea7377f3d1af	2167	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
Pokitto	6:ea7377f3d1af	2168	ccsidr = SCB->CCSIDR;
Pokitto	6:ea7377f3d1af	2169	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Pokitto	6:ea7377f3d1af	2170	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Pokitto	6:ea7377f3d1af	2171	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Pokitto	6:ea7377f3d1af	2172	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Pokitto	6:ea7377f3d1af	2173
Pokitto	6:ea7377f3d1af	2174	__DSB();
Pokitto	6:ea7377f3d1af	2175
Pokitto	6:ea7377f3d1af	2176	do { // clean & invalidate D-Cache
Pokitto	6:ea7377f3d1af	2177	uint32_t tmpways = ways;
Pokitto	6:ea7377f3d1af	2178	do {
Pokitto	6:ea7377f3d1af	2179	sw = ((tmpways << wshift) \| (sets << sshift));
Pokitto	6:ea7377f3d1af	2180	SCB->DCCISW = sw;
Pokitto	6:ea7377f3d1af	2181	} while(tmpways--);
Pokitto	6:ea7377f3d1af	2182	} while(sets--);
Pokitto	6:ea7377f3d1af	2183
Pokitto	6:ea7377f3d1af	2184	__DSB();
Pokitto	6:ea7377f3d1af	2185	__ISB();
Pokitto	6:ea7377f3d1af	2186	#endif
Pokitto	6:ea7377f3d1af	2187	}
Pokitto	6:ea7377f3d1af	2188
Pokitto	6:ea7377f3d1af	2189
Pokitto	6:ea7377f3d1af	2190	/**
Pokitto	6:ea7377f3d1af	2191	\fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
Pokitto	6:ea7377f3d1af	2192	\brief D-Cache Invalidate by address
Pokitto	6:ea7377f3d1af	2193	\param[in] addr address (aligned to 32-byte boundary)
Pokitto	6:ea7377f3d1af	2194	\param[in] dsize size of memory block (in number of bytes)
Pokitto	6:ea7377f3d1af	2195	*/
Pokitto	6:ea7377f3d1af	2196	__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
Pokitto	6:ea7377f3d1af	2197	{
Pokitto	6:ea7377f3d1af	2198	#if (__DCACHE_PRESENT == 1)
Pokitto	6:ea7377f3d1af	2199	int32_t op_size = dsize;
Pokitto	6:ea7377f3d1af	2200	uint32_t op_addr = (uint32_t)addr;
Pokitto	6:ea7377f3d1af	2201	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
Pokitto	6:ea7377f3d1af	2202
Pokitto	6:ea7377f3d1af	2203	__DSB();
Pokitto	6:ea7377f3d1af	2204
Pokitto	6:ea7377f3d1af	2205	while (op_size > 0) {
Pokitto	6:ea7377f3d1af	2206	SCB->DCIMVAC = op_addr;
Pokitto	6:ea7377f3d1af	2207	op_addr += linesize;
Pokitto	6:ea7377f3d1af	2208	op_size -= (int32_t)linesize;
Pokitto	6:ea7377f3d1af	2209	}
Pokitto	6:ea7377f3d1af	2210
Pokitto	6:ea7377f3d1af	2211	__DSB();
Pokitto	6:ea7377f3d1af	2212	__ISB();
Pokitto	6:ea7377f3d1af	2213	#endif
Pokitto	6:ea7377f3d1af	2214	}
Pokitto	6:ea7377f3d1af	2215
Pokitto	6:ea7377f3d1af	2216
Pokitto	6:ea7377f3d1af	2217	/**
Pokitto	6:ea7377f3d1af	2218	\fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
Pokitto	6:ea7377f3d1af	2219	\brief D-Cache Clean by address
Pokitto	6:ea7377f3d1af	2220	\param[in] addr address (aligned to 32-byte boundary)
Pokitto	6:ea7377f3d1af	2221	\param[in] dsize size of memory block (in number of bytes)
Pokitto	6:ea7377f3d1af	2222	*/
Pokitto	6:ea7377f3d1af	2223	__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
Pokitto	6:ea7377f3d1af	2224	{
Pokitto	6:ea7377f3d1af	2225	#if (__DCACHE_PRESENT == 1)
Pokitto	6:ea7377f3d1af	2226	int32_t op_size = dsize;
Pokitto	6:ea7377f3d1af	2227	uint32_t op_addr = (uint32_t) addr;
Pokitto	6:ea7377f3d1af	2228	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
Pokitto	6:ea7377f3d1af	2229
Pokitto	6:ea7377f3d1af	2230	__DSB();
Pokitto	6:ea7377f3d1af	2231
Pokitto	6:ea7377f3d1af	2232	while (op_size > 0) {
Pokitto	6:ea7377f3d1af	2233	SCB->DCCMVAC = op_addr;
Pokitto	6:ea7377f3d1af	2234	op_addr += linesize;
Pokitto	6:ea7377f3d1af	2235	op_size -= (int32_t)linesize;
Pokitto	6:ea7377f3d1af	2236	}
Pokitto	6:ea7377f3d1af	2237
Pokitto	6:ea7377f3d1af	2238	__DSB();
Pokitto	6:ea7377f3d1af	2239	__ISB();
Pokitto	6:ea7377f3d1af	2240	#endif
Pokitto	6:ea7377f3d1af	2241	}
Pokitto	6:ea7377f3d1af	2242
Pokitto	6:ea7377f3d1af	2243
Pokitto	6:ea7377f3d1af	2244	/**
Pokitto	6:ea7377f3d1af	2245	\fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
Pokitto	6:ea7377f3d1af	2246	\brief D-Cache Clean and Invalidate by address
Pokitto	6:ea7377f3d1af	2247	\param[in] addr address (aligned to 32-byte boundary)
Pokitto	6:ea7377f3d1af	2248	\param[in] dsize size of memory block (in number of bytes)
Pokitto	6:ea7377f3d1af	2249	*/
Pokitto	6:ea7377f3d1af	2250	__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
Pokitto	6:ea7377f3d1af	2251	{
Pokitto	6:ea7377f3d1af	2252	#if (__DCACHE_PRESENT == 1)
Pokitto	6:ea7377f3d1af	2253	int32_t op_size = dsize;
Pokitto	6:ea7377f3d1af	2254	uint32_t op_addr = (uint32_t) addr;
Pokitto	6:ea7377f3d1af	2255	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
Pokitto	6:ea7377f3d1af	2256
Pokitto	6:ea7377f3d1af	2257	__DSB();
Pokitto	6:ea7377f3d1af	2258
Pokitto	6:ea7377f3d1af	2259	while (op_size > 0) {
Pokitto	6:ea7377f3d1af	2260	SCB->DCCIMVAC = op_addr;
Pokitto	6:ea7377f3d1af	2261	op_addr += linesize;
Pokitto	6:ea7377f3d1af	2262	op_size -= (int32_t)linesize;
Pokitto	6:ea7377f3d1af	2263	}
Pokitto	6:ea7377f3d1af	2264
Pokitto	6:ea7377f3d1af	2265	__DSB();
Pokitto	6:ea7377f3d1af	2266	__ISB();
Pokitto	6:ea7377f3d1af	2267	#endif
Pokitto	6:ea7377f3d1af	2268	}
Pokitto	6:ea7377f3d1af	2269
Pokitto	6:ea7377f3d1af	2270
Pokitto	6:ea7377f3d1af	2271	/@} end of CMSIS_Core_CacheFunctions /
Pokitto	6:ea7377f3d1af	2272
Pokitto	6:ea7377f3d1af	2273
Pokitto	6:ea7377f3d1af	2274
Pokitto	6:ea7377f3d1af	2275	/* ################################## SysTick function ############################################ */
Pokitto	6:ea7377f3d1af	2276	/** \ingroup CMSIS_Core_FunctionInterface
Pokitto	6:ea7377f3d1af	2277	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Pokitto	6:ea7377f3d1af	2278	\brief Functions that configure the System.
Pokitto	6:ea7377f3d1af	2279	@{
Pokitto	6:ea7377f3d1af	2280	*/
Pokitto	6:ea7377f3d1af	2281
Pokitto	6:ea7377f3d1af	2282	#if (__Vendor_SysTickConfig == 0)
Pokitto	6:ea7377f3d1af	2283
Pokitto	6:ea7377f3d1af	2284	/** \brief System Tick Configuration
Pokitto	6:ea7377f3d1af	2285
Pokitto	6:ea7377f3d1af	2286	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Pokitto	6:ea7377f3d1af	2287	Counter is in free running mode to generate periodic interrupts.
Pokitto	6:ea7377f3d1af	2288
Pokitto	6:ea7377f3d1af	2289	\param [in] ticks Number of ticks between two interrupts.
Pokitto	6:ea7377f3d1af	2290
Pokitto	6:ea7377f3d1af	2291	\return 0 Function succeeded.
Pokitto	6:ea7377f3d1af	2292	\return 1 Function failed.
Pokitto	6:ea7377f3d1af	2293
Pokitto	6:ea7377f3d1af	2294	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Pokitto	6:ea7377f3d1af	2295	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Pokitto	6:ea7377f3d1af	2296	must contain a vendor-specific implementation of this function.
Pokitto	6:ea7377f3d1af	2297
Pokitto	6:ea7377f3d1af	2298	*/
Pokitto	6:ea7377f3d1af	2299	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Pokitto	6:ea7377f3d1af	2300	{
Pokitto	6:ea7377f3d1af	2301	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
Pokitto	6:ea7377f3d1af	2302
Pokitto	6:ea7377f3d1af	2303	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Pokitto	6:ea7377f3d1af	2304	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Pokitto	6:ea7377f3d1af	2305	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Pokitto	6:ea7377f3d1af	2306	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
Pokitto	6:ea7377f3d1af	2307	SysTick_CTRL_TICKINT_Msk \|
Pokitto	6:ea7377f3d1af	2308	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Pokitto	6:ea7377f3d1af	2309	return (0UL); /* Function successful */
Pokitto	6:ea7377f3d1af	2310	}
Pokitto	6:ea7377f3d1af	2311
Pokitto	6:ea7377f3d1af	2312	#endif
Pokitto	6:ea7377f3d1af	2313
Pokitto	6:ea7377f3d1af	2314	/@} end of CMSIS_Core_SysTickFunctions /
Pokitto	6:ea7377f3d1af	2315
Pokitto	6:ea7377f3d1af	2316
Pokitto	6:ea7377f3d1af	2317
Pokitto	6:ea7377f3d1af	2318	/* ##################################### Debug In/Output function ########################################### */
Pokitto	6:ea7377f3d1af	2319	/** \ingroup CMSIS_Core_FunctionInterface
Pokitto	6:ea7377f3d1af	2320	\defgroup CMSIS_core_DebugFunctions ITM Functions
Pokitto	6:ea7377f3d1af	2321	\brief Functions that access the ITM debug interface.
Pokitto	6:ea7377f3d1af	2322	@{
Pokitto	6:ea7377f3d1af	2323	*/
Pokitto	6:ea7377f3d1af	2324
Pokitto	6:ea7377f3d1af	2325	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
Pokitto	6:ea7377f3d1af	2326	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
Pokitto	6:ea7377f3d1af	2327
Pokitto	6:ea7377f3d1af	2328
Pokitto	6:ea7377f3d1af	2329	/** \brief ITM Send Character
Pokitto	6:ea7377f3d1af	2330
Pokitto	6:ea7377f3d1af	2331	The function transmits a character via the ITM channel 0, and
Pokitto	6:ea7377f3d1af	2332	\li Just returns when no debugger is connected that has booked the output.
Pokitto	6:ea7377f3d1af	2333	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Pokitto	6:ea7377f3d1af	2334
Pokitto	6:ea7377f3d1af	2335	\param [in] ch Character to transmit.
Pokitto	6:ea7377f3d1af	2336
Pokitto	6:ea7377f3d1af	2337	\returns Character to transmit.
Pokitto	6:ea7377f3d1af	2338	*/
Pokitto	6:ea7377f3d1af	2339	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Pokitto	6:ea7377f3d1af	2340	{
Pokitto	6:ea7377f3d1af	2341	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Pokitto	6:ea7377f3d1af	2342	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
Pokitto	6:ea7377f3d1af	2343	{
Pokitto	6:ea7377f3d1af	2344	while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
Pokitto	6:ea7377f3d1af	2345	ITM->PORT[0].u8 = (uint8_t)ch;
Pokitto	6:ea7377f3d1af	2346	}
Pokitto	6:ea7377f3d1af	2347	return (ch);
Pokitto	6:ea7377f3d1af	2348	}
Pokitto	6:ea7377f3d1af	2349
Pokitto	6:ea7377f3d1af	2350
Pokitto	6:ea7377f3d1af	2351	/** \brief ITM Receive Character
Pokitto	6:ea7377f3d1af	2352
Pokitto	6:ea7377f3d1af	2353	The function inputs a character via the external variable \ref ITM_RxBuffer.
Pokitto	6:ea7377f3d1af	2354
Pokitto	6:ea7377f3d1af	2355	\return Received character.
Pokitto	6:ea7377f3d1af	2356	\return -1 No character pending.
Pokitto	6:ea7377f3d1af	2357	*/
Pokitto	6:ea7377f3d1af	2358	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
Pokitto	6:ea7377f3d1af	2359	int32_t ch = -1; /* no character available */
Pokitto	6:ea7377f3d1af	2360
Pokitto	6:ea7377f3d1af	2361	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
Pokitto	6:ea7377f3d1af	2362	ch = ITM_RxBuffer;
Pokitto	6:ea7377f3d1af	2363	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Pokitto	6:ea7377f3d1af	2364	}
Pokitto	6:ea7377f3d1af	2365
Pokitto	6:ea7377f3d1af	2366	return (ch);
Pokitto	6:ea7377f3d1af	2367	}
Pokitto	6:ea7377f3d1af	2368
Pokitto	6:ea7377f3d1af	2369
Pokitto	6:ea7377f3d1af	2370	/** \brief ITM Check Character
Pokitto	6:ea7377f3d1af	2371
Pokitto	6:ea7377f3d1af	2372	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Pokitto	6:ea7377f3d1af	2373
Pokitto	6:ea7377f3d1af	2374	\return 0 No character available.
Pokitto	6:ea7377f3d1af	2375	\return 1 Character available.
Pokitto	6:ea7377f3d1af	2376	*/
Pokitto	6:ea7377f3d1af	2377	__STATIC_INLINE int32_t ITM_CheckChar (void) {
Pokitto	6:ea7377f3d1af	2378
Pokitto	6:ea7377f3d1af	2379	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
Pokitto	6:ea7377f3d1af	2380	return (0); /* no character available */
Pokitto	6:ea7377f3d1af	2381	} else {
Pokitto	6:ea7377f3d1af	2382	return (1); /* character available */
Pokitto	6:ea7377f3d1af	2383	}
Pokitto	6:ea7377f3d1af	2384	}
Pokitto	6:ea7377f3d1af	2385
Pokitto	6:ea7377f3d1af	2386	/@} end of CMSIS_core_DebugFunctions /
Pokitto	6:ea7377f3d1af	2387
Pokitto	6:ea7377f3d1af	2388
Pokitto	6:ea7377f3d1af	2389
Pokitto	6:ea7377f3d1af	2390
Pokitto	6:ea7377f3d1af	2391	#ifdef __cplusplus
Pokitto	6:ea7377f3d1af	2392	}
Pokitto	6:ea7377f3d1af	2393	#endif
Pokitto	6:ea7377f3d1af	2394
Pokitto	6:ea7377f3d1af	2395	#endif /* __CORE_CM7_H_DEPENDANT */
Pokitto	6:ea7377f3d1af	2396
Pokitto	6:ea7377f3d1af	2397	#endif /* __CMSIS_GENERIC */

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Type:	Library
Created:	18 Oct 2017
Imports:	4
Forks:	0
Commits:	16
Dependents:	1
Dependencies:	0
Followers:	1

mbed-pokitto/targets/cmsis/core_cm7.h@15:0bbe8f6fae32, 2017-10-18 (annotated)

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