spinal cord / PokittoLib

PokittoLib is the library needed for programming the Pokitto DIY game console (www.pokitto.com)

Dependents:   Sensitive

Fork of PokittoLib by Jonne Valola

mbed-pokitto/targets/cmsis/core_cm0.h@15:0bbe8f6fae32, 2017-10-18 (annotated)

Committer:
spinal
Date:
Wed Oct 18 14:47:54 2017 +0000
Revision:
15:0bbe8f6fae32
Parent:
6:ea7377f3d1af 
direct lcd stuff used by sensitive

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Pokitto 6:ea7377f3d1af 1 /**************************************************************************//**
Pokitto 6:ea7377f3d1af 2 * @file core_cm0.h
Pokitto 6:ea7377f3d1af 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
Pokitto 6:ea7377f3d1af 4 * @version V3.20
Pokitto 6:ea7377f3d1af 5 * @date 25. February 2013
Pokitto 6:ea7377f3d1af 6 *
Pokitto 6:ea7377f3d1af 7 * @note
Pokitto 6:ea7377f3d1af 8 *
Pokitto 6:ea7377f3d1af 9 ******************************************************************************/
Pokitto 6:ea7377f3d1af 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Pokitto 6:ea7377f3d1af 11
Pokitto 6:ea7377f3d1af 12 All rights reserved.
Pokitto 6:ea7377f3d1af 13 Redistribution and use in source and binary forms, with or without
Pokitto 6:ea7377f3d1af 14 modification, are permitted provided that the following conditions are met:
Pokitto 6:ea7377f3d1af 15 - Redistributions of source code must retain the above copyright
Pokitto 6:ea7377f3d1af 16 notice, this list of conditions and the following disclaimer.
Pokitto 6:ea7377f3d1af 17 - Redistributions in binary form must reproduce the above copyright
Pokitto 6:ea7377f3d1af 18 notice, this list of conditions and the following disclaimer in the
Pokitto 6:ea7377f3d1af 19 documentation and/or other materials provided with the distribution.
Pokitto 6:ea7377f3d1af 20 - Neither the name of ARM nor the names of its contributors may be used
Pokitto 6:ea7377f3d1af 21 to endorse or promote products derived from this software without
Pokitto 6:ea7377f3d1af 22 specific prior written permission.
Pokitto 6:ea7377f3d1af 23 *
Pokitto 6:ea7377f3d1af 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Pokitto 6:ea7377f3d1af 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Pokitto 6:ea7377f3d1af 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Pokitto 6:ea7377f3d1af 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Pokitto 6:ea7377f3d1af 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Pokitto 6:ea7377f3d1af 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Pokitto 6:ea7377f3d1af 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Pokitto 6:ea7377f3d1af 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Pokitto 6:ea7377f3d1af 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Pokitto 6:ea7377f3d1af 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Pokitto 6:ea7377f3d1af 34 POSSIBILITY OF SUCH DAMAGE.
Pokitto 6:ea7377f3d1af 35 ---------------------------------------------------------------------------*/
Pokitto 6:ea7377f3d1af 36
Pokitto 6:ea7377f3d1af 37
Pokitto 6:ea7377f3d1af 38 #if defined ( __ICCARM__ )
Pokitto 6:ea7377f3d1af 39 #pragma system_include /* treat file as system include file for MISRA check */
Pokitto 6:ea7377f3d1af 40 #endif
Pokitto 6:ea7377f3d1af 41
Pokitto 6:ea7377f3d1af 42 #ifdef __cplusplus
Pokitto 6:ea7377f3d1af 43 extern "C" {
Pokitto 6:ea7377f3d1af 44 #endif
Pokitto 6:ea7377f3d1af 45
Pokitto 6:ea7377f3d1af 46 #ifndef __CORE_CM0_H_GENERIC
Pokitto 6:ea7377f3d1af 47 #define __CORE_CM0_H_GENERIC
Pokitto 6:ea7377f3d1af 48
Pokitto 6:ea7377f3d1af 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Pokitto 6:ea7377f3d1af 50 CMSIS violates the following MISRA-C:2004 rules:
Pokitto 6:ea7377f3d1af 51
Pokitto 6:ea7377f3d1af 52 \li Required Rule 8.5, object/function definition in header file.<br>
Pokitto 6:ea7377f3d1af 53 Function definitions in header files are used to allow 'inlining'.
Pokitto 6:ea7377f3d1af 54
Pokitto 6:ea7377f3d1af 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Pokitto 6:ea7377f3d1af 56 Unions are used for effective representation of core registers.
Pokitto 6:ea7377f3d1af 57
Pokitto 6:ea7377f3d1af 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Pokitto 6:ea7377f3d1af 59 Function-like macros are used to allow more efficient code.
Pokitto 6:ea7377f3d1af 60 */
Pokitto 6:ea7377f3d1af 61
Pokitto 6:ea7377f3d1af 62
Pokitto 6:ea7377f3d1af 63 /*******************************************************************************
Pokitto 6:ea7377f3d1af 64 * CMSIS definitions
Pokitto 6:ea7377f3d1af 65 ******************************************************************************/
Pokitto 6:ea7377f3d1af 66 /** \ingroup Cortex_M0
Pokitto 6:ea7377f3d1af 67 @{
Pokitto 6:ea7377f3d1af 68 */
Pokitto 6:ea7377f3d1af 69
Pokitto 6:ea7377f3d1af 70 /* CMSIS CM0 definitions */
Pokitto 6:ea7377f3d1af 71 #define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
Pokitto 6:ea7377f3d1af 72 #define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
Pokitto 6:ea7377f3d1af 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
Pokitto 6:ea7377f3d1af 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
Pokitto 6:ea7377f3d1af 75
Pokitto 6:ea7377f3d1af 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Pokitto 6:ea7377f3d1af 77
Pokitto 6:ea7377f3d1af 78
Pokitto 6:ea7377f3d1af 79 #if defined ( __CC_ARM )
Pokitto 6:ea7377f3d1af 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Pokitto 6:ea7377f3d1af 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Pokitto 6:ea7377f3d1af 82 #define __STATIC_INLINE static __inline
Pokitto 6:ea7377f3d1af 83
Pokitto 6:ea7377f3d1af 84 #elif defined ( __ICCARM__ )
Pokitto 6:ea7377f3d1af 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Pokitto 6:ea7377f3d1af 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Pokitto 6:ea7377f3d1af 87 #define __STATIC_INLINE static inline
Pokitto 6:ea7377f3d1af 88
Pokitto 6:ea7377f3d1af 89 #elif defined ( __GNUC__ )
Pokitto 6:ea7377f3d1af 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Pokitto 6:ea7377f3d1af 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Pokitto 6:ea7377f3d1af 92 #define __STATIC_INLINE static inline
Pokitto 6:ea7377f3d1af 93
Pokitto 6:ea7377f3d1af 94 #elif defined ( __TASKING__ )
Pokitto 6:ea7377f3d1af 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Pokitto 6:ea7377f3d1af 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Pokitto 6:ea7377f3d1af 97 #define __STATIC_INLINE static inline
Pokitto 6:ea7377f3d1af 98
Pokitto 6:ea7377f3d1af 99 #endif
Pokitto 6:ea7377f3d1af 100
Pokitto 6:ea7377f3d1af 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
Pokitto 6:ea7377f3d1af 102 */
Pokitto 6:ea7377f3d1af 103 #define __FPU_USED 0
Pokitto 6:ea7377f3d1af 104
Pokitto 6:ea7377f3d1af 105 #if defined ( __CC_ARM )
Pokitto 6:ea7377f3d1af 106 #if defined __TARGET_FPU_VFP
Pokitto 6:ea7377f3d1af 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Pokitto 6:ea7377f3d1af 108 #endif
Pokitto 6:ea7377f3d1af 109
Pokitto 6:ea7377f3d1af 110 #elif defined ( __ICCARM__ )
Pokitto 6:ea7377f3d1af 111 #if defined __ARMVFP__
Pokitto 6:ea7377f3d1af 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Pokitto 6:ea7377f3d1af 113 #endif
Pokitto 6:ea7377f3d1af 114
Pokitto 6:ea7377f3d1af 115 #elif defined ( __GNUC__ )
Pokitto 6:ea7377f3d1af 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Pokitto 6:ea7377f3d1af 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Pokitto 6:ea7377f3d1af 118 #endif
Pokitto 6:ea7377f3d1af 119
Pokitto 6:ea7377f3d1af 120 #elif defined ( __TASKING__ )
Pokitto 6:ea7377f3d1af 121 #if defined __FPU_VFP__
Pokitto 6:ea7377f3d1af 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Pokitto 6:ea7377f3d1af 123 #endif
Pokitto 6:ea7377f3d1af 124 #endif
Pokitto 6:ea7377f3d1af 125
Pokitto 6:ea7377f3d1af 126 #include <stdint.h> /* standard types definitions */
Pokitto 6:ea7377f3d1af 127 #include <core_cmInstr.h> /* Core Instruction Access */
Pokitto 6:ea7377f3d1af 128 #include <core_cmFunc.h> /* Core Function Access */
Pokitto 6:ea7377f3d1af 129
Pokitto 6:ea7377f3d1af 130 #endif /* __CORE_CM0_H_GENERIC */
Pokitto 6:ea7377f3d1af 131
Pokitto 6:ea7377f3d1af 132 #ifndef __CMSIS_GENERIC
Pokitto 6:ea7377f3d1af 133
Pokitto 6:ea7377f3d1af 134 #ifndef __CORE_CM0_H_DEPENDANT
Pokitto 6:ea7377f3d1af 135 #define __CORE_CM0_H_DEPENDANT
Pokitto 6:ea7377f3d1af 136
Pokitto 6:ea7377f3d1af 137 /* check device defines and use defaults */
Pokitto 6:ea7377f3d1af 138 #if defined __CHECK_DEVICE_DEFINES
Pokitto 6:ea7377f3d1af 139 #ifndef __CM0_REV
Pokitto 6:ea7377f3d1af 140 #define __CM0_REV 0x0000
Pokitto 6:ea7377f3d1af 141 #warning "__CM0_REV not defined in device header file; using default!"
Pokitto 6:ea7377f3d1af 142 #endif
Pokitto 6:ea7377f3d1af 143
Pokitto 6:ea7377f3d1af 144 #ifndef __NVIC_PRIO_BITS
Pokitto 6:ea7377f3d1af 145 #define __NVIC_PRIO_BITS 2
Pokitto 6:ea7377f3d1af 146 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Pokitto 6:ea7377f3d1af 147 #endif
Pokitto 6:ea7377f3d1af 148
Pokitto 6:ea7377f3d1af 149 #ifndef __Vendor_SysTickConfig
Pokitto 6:ea7377f3d1af 150 #define __Vendor_SysTickConfig 0
Pokitto 6:ea7377f3d1af 151 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Pokitto 6:ea7377f3d1af 152 #endif
Pokitto 6:ea7377f3d1af 153 #endif
Pokitto 6:ea7377f3d1af 154
Pokitto 6:ea7377f3d1af 155 /* IO definitions (access restrictions to peripheral registers) */
Pokitto 6:ea7377f3d1af 156 /**
Pokitto 6:ea7377f3d1af 157 \defgroup CMSIS_glob_defs CMSIS Global Defines
Pokitto 6:ea7377f3d1af 158
Pokitto 6:ea7377f3d1af 159 <strong>IO Type Qualifiers</strong> are used
Pokitto 6:ea7377f3d1af 160 \li to specify the access to peripheral variables.
Pokitto 6:ea7377f3d1af 161 \li for automatic generation of peripheral register debug information.
Pokitto 6:ea7377f3d1af 162 */
Pokitto 6:ea7377f3d1af 163 #ifdef __cplusplus
Pokitto 6:ea7377f3d1af 164 #define __I volatile /*!< Defines 'read only' permissions */
Pokitto 6:ea7377f3d1af 165 #else
Pokitto 6:ea7377f3d1af 166 #define __I volatile const /*!< Defines 'read only' permissions */
Pokitto 6:ea7377f3d1af 167 #endif
Pokitto 6:ea7377f3d1af 168 #define __O volatile /*!< Defines 'write only' permissions */
Pokitto 6:ea7377f3d1af 169 #define __IO volatile /*!< Defines 'read / write' permissions */
Pokitto 6:ea7377f3d1af 170
Pokitto 6:ea7377f3d1af 171 /*@} end of group Cortex_M0 */
Pokitto 6:ea7377f3d1af 172
Pokitto 6:ea7377f3d1af 173
Pokitto 6:ea7377f3d1af 174
Pokitto 6:ea7377f3d1af 175 /*******************************************************************************
Pokitto 6:ea7377f3d1af 176 * Register Abstraction
Pokitto 6:ea7377f3d1af 177 Core Register contain:
Pokitto 6:ea7377f3d1af 178 - Core Register
Pokitto 6:ea7377f3d1af 179 - Core NVIC Register
Pokitto 6:ea7377f3d1af 180 - Core SCB Register
Pokitto 6:ea7377f3d1af 181 - Core SysTick Register
Pokitto 6:ea7377f3d1af 182 ******************************************************************************/
Pokitto 6:ea7377f3d1af 183 /** \defgroup CMSIS_core_register Defines and Type Definitions
Pokitto 6:ea7377f3d1af 184 \brief Type definitions and defines for Cortex-M processor based devices.
Pokitto 6:ea7377f3d1af 185 */
Pokitto 6:ea7377f3d1af 186
Pokitto 6:ea7377f3d1af 187 /** \ingroup CMSIS_core_register
Pokitto 6:ea7377f3d1af 188 \defgroup CMSIS_CORE Status and Control Registers
Pokitto 6:ea7377f3d1af 189 \brief Core Register type definitions.
Pokitto 6:ea7377f3d1af 190 @{
Pokitto 6:ea7377f3d1af 191 */
Pokitto 6:ea7377f3d1af 192
Pokitto 6:ea7377f3d1af 193 /** \brief Union type to access the Application Program Status Register (APSR).
Pokitto 6:ea7377f3d1af 194 */
Pokitto 6:ea7377f3d1af 195 typedef union
Pokitto 6:ea7377f3d1af 196 {
Pokitto 6:ea7377f3d1af 197 struct
Pokitto 6:ea7377f3d1af 198 {
Pokitto 6:ea7377f3d1af 199 #if (__CORTEX_M != 0x04)
Pokitto 6:ea7377f3d1af 200 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
Pokitto 6:ea7377f3d1af 201 #else
Pokitto 6:ea7377f3d1af 202 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
Pokitto 6:ea7377f3d1af 203 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Pokitto 6:ea7377f3d1af 204 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
Pokitto 6:ea7377f3d1af 205 #endif
Pokitto 6:ea7377f3d1af 206 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Pokitto 6:ea7377f3d1af 207 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Pokitto 6:ea7377f3d1af 208 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Pokitto 6:ea7377f3d1af 209 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Pokitto 6:ea7377f3d1af 210 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Pokitto 6:ea7377f3d1af 211 } b; /*!< Structure used for bit access */
Pokitto 6:ea7377f3d1af 212 uint32_t w; /*!< Type used for word access */
Pokitto 6:ea7377f3d1af 213 } APSR_Type;
Pokitto 6:ea7377f3d1af 214
Pokitto 6:ea7377f3d1af 215
Pokitto 6:ea7377f3d1af 216 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Pokitto 6:ea7377f3d1af 217 */
Pokitto 6:ea7377f3d1af 218 typedef union
Pokitto 6:ea7377f3d1af 219 {
Pokitto 6:ea7377f3d1af 220 struct
Pokitto 6:ea7377f3d1af 221 {
Pokitto 6:ea7377f3d1af 222 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Pokitto 6:ea7377f3d1af 223 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Pokitto 6:ea7377f3d1af 224 } b; /*!< Structure used for bit access */
Pokitto 6:ea7377f3d1af 225 uint32_t w; /*!< Type used for word access */
Pokitto 6:ea7377f3d1af 226 } IPSR_Type;
Pokitto 6:ea7377f3d1af 227
Pokitto 6:ea7377f3d1af 228
Pokitto 6:ea7377f3d1af 229 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Pokitto 6:ea7377f3d1af 230 */
Pokitto 6:ea7377f3d1af 231 typedef union
Pokitto 6:ea7377f3d1af 232 {
Pokitto 6:ea7377f3d1af 233 struct
Pokitto 6:ea7377f3d1af 234 {
Pokitto 6:ea7377f3d1af 235 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Pokitto 6:ea7377f3d1af 236 #if (__CORTEX_M != 0x04)
Pokitto 6:ea7377f3d1af 237 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Pokitto 6:ea7377f3d1af 238 #else
Pokitto 6:ea7377f3d1af 239 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
Pokitto 6:ea7377f3d1af 240 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Pokitto 6:ea7377f3d1af 241 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
Pokitto 6:ea7377f3d1af 242 #endif
Pokitto 6:ea7377f3d1af 243 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Pokitto 6:ea7377f3d1af 244 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
Pokitto 6:ea7377f3d1af 245 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Pokitto 6:ea7377f3d1af 246 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Pokitto 6:ea7377f3d1af 247 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Pokitto 6:ea7377f3d1af 248 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Pokitto 6:ea7377f3d1af 249 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Pokitto 6:ea7377f3d1af 250 } b; /*!< Structure used for bit access */
Pokitto 6:ea7377f3d1af 251 uint32_t w; /*!< Type used for word access */
Pokitto 6:ea7377f3d1af 252 } xPSR_Type;
Pokitto 6:ea7377f3d1af 253
Pokitto 6:ea7377f3d1af 254
Pokitto 6:ea7377f3d1af 255 /** \brief Union type to access the Control Registers (CONTROL).
Pokitto 6:ea7377f3d1af 256 */
Pokitto 6:ea7377f3d1af 257 typedef union
Pokitto 6:ea7377f3d1af 258 {
Pokitto 6:ea7377f3d1af 259 struct
Pokitto 6:ea7377f3d1af 260 {
Pokitto 6:ea7377f3d1af 261 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Pokitto 6:ea7377f3d1af 262 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Pokitto 6:ea7377f3d1af 263 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
Pokitto 6:ea7377f3d1af 264 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
Pokitto 6:ea7377f3d1af 265 } b; /*!< Structure used for bit access */
Pokitto 6:ea7377f3d1af 266 uint32_t w; /*!< Type used for word access */
Pokitto 6:ea7377f3d1af 267 } CONTROL_Type;
Pokitto 6:ea7377f3d1af 268
Pokitto 6:ea7377f3d1af 269 /*@} end of group CMSIS_CORE */
Pokitto 6:ea7377f3d1af 270
Pokitto 6:ea7377f3d1af 271
Pokitto 6:ea7377f3d1af 272 /** \ingroup CMSIS_core_register
Pokitto 6:ea7377f3d1af 273 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Pokitto 6:ea7377f3d1af 274 \brief Type definitions for the NVIC Registers
Pokitto 6:ea7377f3d1af 275 @{
Pokitto 6:ea7377f3d1af 276 */
Pokitto 6:ea7377f3d1af 277
Pokitto 6:ea7377f3d1af 278 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Pokitto 6:ea7377f3d1af 279 */
Pokitto 6:ea7377f3d1af 280 typedef struct
Pokitto 6:ea7377f3d1af 281 {
Pokitto 6:ea7377f3d1af 282 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Pokitto 6:ea7377f3d1af 283 uint32_t RESERVED0[31];
Pokitto 6:ea7377f3d1af 284 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Pokitto 6:ea7377f3d1af 285 uint32_t RSERVED1[31];
Pokitto 6:ea7377f3d1af 286 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Pokitto 6:ea7377f3d1af 287 uint32_t RESERVED2[31];
Pokitto 6:ea7377f3d1af 288 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Pokitto 6:ea7377f3d1af 289 uint32_t RESERVED3[31];
Pokitto 6:ea7377f3d1af 290 uint32_t RESERVED4[64];
Pokitto 6:ea7377f3d1af 291 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Pokitto 6:ea7377f3d1af 292 } NVIC_Type;
Pokitto 6:ea7377f3d1af 293
Pokitto 6:ea7377f3d1af 294 /*@} end of group CMSIS_NVIC */
Pokitto 6:ea7377f3d1af 295
Pokitto 6:ea7377f3d1af 296
Pokitto 6:ea7377f3d1af 297 /** \ingroup CMSIS_core_register
Pokitto 6:ea7377f3d1af 298 \defgroup CMSIS_SCB System Control Block (SCB)
Pokitto 6:ea7377f3d1af 299 \brief Type definitions for the System Control Block Registers
Pokitto 6:ea7377f3d1af 300 @{
Pokitto 6:ea7377f3d1af 301 */
Pokitto 6:ea7377f3d1af 302
Pokitto 6:ea7377f3d1af 303 /** \brief Structure type to access the System Control Block (SCB).
Pokitto 6:ea7377f3d1af 304 */
Pokitto 6:ea7377f3d1af 305 typedef struct
Pokitto 6:ea7377f3d1af 306 {
Pokitto 6:ea7377f3d1af 307 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Pokitto 6:ea7377f3d1af 308 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Pokitto 6:ea7377f3d1af 309 uint32_t RESERVED0;
Pokitto 6:ea7377f3d1af 310 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Pokitto 6:ea7377f3d1af 311 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Pokitto 6:ea7377f3d1af 312 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Pokitto 6:ea7377f3d1af 313 uint32_t RESERVED1;
Pokitto 6:ea7377f3d1af 314 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Pokitto 6:ea7377f3d1af 315 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Pokitto 6:ea7377f3d1af 316 } SCB_Type;
Pokitto 6:ea7377f3d1af 317
Pokitto 6:ea7377f3d1af 318 /* SCB CPUID Register Definitions */
Pokitto 6:ea7377f3d1af 319 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Pokitto 6:ea7377f3d1af 320 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Pokitto 6:ea7377f3d1af 321
Pokitto 6:ea7377f3d1af 322 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Pokitto 6:ea7377f3d1af 323 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Pokitto 6:ea7377f3d1af 324
Pokitto 6:ea7377f3d1af 325 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Pokitto 6:ea7377f3d1af 326 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Pokitto 6:ea7377f3d1af 327
Pokitto 6:ea7377f3d1af 328 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Pokitto 6:ea7377f3d1af 329 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Pokitto 6:ea7377f3d1af 330
Pokitto 6:ea7377f3d1af 331 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Pokitto 6:ea7377f3d1af 332 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
Pokitto 6:ea7377f3d1af 333
Pokitto 6:ea7377f3d1af 334 /* SCB Interrupt Control State Register Definitions */
Pokitto 6:ea7377f3d1af 335 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Pokitto 6:ea7377f3d1af 336 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Pokitto 6:ea7377f3d1af 337
Pokitto 6:ea7377f3d1af 338 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Pokitto 6:ea7377f3d1af 339 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Pokitto 6:ea7377f3d1af 340
Pokitto 6:ea7377f3d1af 341 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Pokitto 6:ea7377f3d1af 342 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Pokitto 6:ea7377f3d1af 343
Pokitto 6:ea7377f3d1af 344 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Pokitto 6:ea7377f3d1af 345 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Pokitto 6:ea7377f3d1af 346
Pokitto 6:ea7377f3d1af 347 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Pokitto 6:ea7377f3d1af 348 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Pokitto 6:ea7377f3d1af 349
Pokitto 6:ea7377f3d1af 350 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Pokitto 6:ea7377f3d1af 351 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Pokitto 6:ea7377f3d1af 352
Pokitto 6:ea7377f3d1af 353 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Pokitto 6:ea7377f3d1af 354 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Pokitto 6:ea7377f3d1af 355
Pokitto 6:ea7377f3d1af 356 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Pokitto 6:ea7377f3d1af 357 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Pokitto 6:ea7377f3d1af 358
Pokitto 6:ea7377f3d1af 359 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Pokitto 6:ea7377f3d1af 360 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
Pokitto 6:ea7377f3d1af 361
Pokitto 6:ea7377f3d1af 362 /* SCB Application Interrupt and Reset Control Register Definitions */
Pokitto 6:ea7377f3d1af 363 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Pokitto 6:ea7377f3d1af 364 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Pokitto 6:ea7377f3d1af 365
Pokitto 6:ea7377f3d1af 366 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Pokitto 6:ea7377f3d1af 367 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Pokitto 6:ea7377f3d1af 368
Pokitto 6:ea7377f3d1af 369 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Pokitto 6:ea7377f3d1af 370 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Pokitto 6:ea7377f3d1af 371
Pokitto 6:ea7377f3d1af 372 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Pokitto 6:ea7377f3d1af 373 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Pokitto 6:ea7377f3d1af 374
Pokitto 6:ea7377f3d1af 375 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Pokitto 6:ea7377f3d1af 376 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Pokitto 6:ea7377f3d1af 377
Pokitto 6:ea7377f3d1af 378 /* SCB System Control Register Definitions */
Pokitto 6:ea7377f3d1af 379 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Pokitto 6:ea7377f3d1af 380 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Pokitto 6:ea7377f3d1af 381
Pokitto 6:ea7377f3d1af 382 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Pokitto 6:ea7377f3d1af 383 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Pokitto 6:ea7377f3d1af 384
Pokitto 6:ea7377f3d1af 385 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Pokitto 6:ea7377f3d1af 386 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Pokitto 6:ea7377f3d1af 387
Pokitto 6:ea7377f3d1af 388 /* SCB Configuration Control Register Definitions */
Pokitto 6:ea7377f3d1af 389 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Pokitto 6:ea7377f3d1af 390 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Pokitto 6:ea7377f3d1af 391
Pokitto 6:ea7377f3d1af 392 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Pokitto 6:ea7377f3d1af 393 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Pokitto 6:ea7377f3d1af 394
Pokitto 6:ea7377f3d1af 395 /* SCB System Handler Control and State Register Definitions */
Pokitto 6:ea7377f3d1af 396 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Pokitto 6:ea7377f3d1af 397 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Pokitto 6:ea7377f3d1af 398
Pokitto 6:ea7377f3d1af 399 /*@} end of group CMSIS_SCB */
Pokitto 6:ea7377f3d1af 400
Pokitto 6:ea7377f3d1af 401
Pokitto 6:ea7377f3d1af 402 /** \ingroup CMSIS_core_register
Pokitto 6:ea7377f3d1af 403 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Pokitto 6:ea7377f3d1af 404 \brief Type definitions for the System Timer Registers.
Pokitto 6:ea7377f3d1af 405 @{
Pokitto 6:ea7377f3d1af 406 */
Pokitto 6:ea7377f3d1af 407
Pokitto 6:ea7377f3d1af 408 /** \brief Structure type to access the System Timer (SysTick).
Pokitto 6:ea7377f3d1af 409 */
Pokitto 6:ea7377f3d1af 410 typedef struct
Pokitto 6:ea7377f3d1af 411 {
Pokitto 6:ea7377f3d1af 412 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Pokitto 6:ea7377f3d1af 413 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Pokitto 6:ea7377f3d1af 414 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Pokitto 6:ea7377f3d1af 415 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Pokitto 6:ea7377f3d1af 416 } SysTick_Type;
Pokitto 6:ea7377f3d1af 417
Pokitto 6:ea7377f3d1af 418 /* SysTick Control / Status Register Definitions */
Pokitto 6:ea7377f3d1af 419 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Pokitto 6:ea7377f3d1af 420 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Pokitto 6:ea7377f3d1af 421
Pokitto 6:ea7377f3d1af 422 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Pokitto 6:ea7377f3d1af 423 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Pokitto 6:ea7377f3d1af 424
Pokitto 6:ea7377f3d1af 425 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Pokitto 6:ea7377f3d1af 426 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Pokitto 6:ea7377f3d1af 427
Pokitto 6:ea7377f3d1af 428 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Pokitto 6:ea7377f3d1af 429 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
Pokitto 6:ea7377f3d1af 430
Pokitto 6:ea7377f3d1af 431 /* SysTick Reload Register Definitions */
Pokitto 6:ea7377f3d1af 432 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Pokitto 6:ea7377f3d1af 433 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
Pokitto 6:ea7377f3d1af 434
Pokitto 6:ea7377f3d1af 435 /* SysTick Current Register Definitions */
Pokitto 6:ea7377f3d1af 436 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Pokitto 6:ea7377f3d1af 437 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
Pokitto 6:ea7377f3d1af 438
Pokitto 6:ea7377f3d1af 439 /* SysTick Calibration Register Definitions */
Pokitto 6:ea7377f3d1af 440 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Pokitto 6:ea7377f3d1af 441 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Pokitto 6:ea7377f3d1af 442
Pokitto 6:ea7377f3d1af 443 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Pokitto 6:ea7377f3d1af 444 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Pokitto 6:ea7377f3d1af 445
Pokitto 6:ea7377f3d1af 446 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Pokitto 6:ea7377f3d1af 447 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
Pokitto 6:ea7377f3d1af 448
Pokitto 6:ea7377f3d1af 449 /*@} end of group CMSIS_SysTick */
Pokitto 6:ea7377f3d1af 450
Pokitto 6:ea7377f3d1af 451
Pokitto 6:ea7377f3d1af 452 /** \ingroup CMSIS_core_register
Pokitto 6:ea7377f3d1af 453 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Pokitto 6:ea7377f3d1af 454 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
Pokitto 6:ea7377f3d1af 455 are only accessible over DAP and not via processor. Therefore
Pokitto 6:ea7377f3d1af 456 they are not covered by the Cortex-M0 header file.
Pokitto 6:ea7377f3d1af 457 @{
Pokitto 6:ea7377f3d1af 458 */
Pokitto 6:ea7377f3d1af 459 /*@} end of group CMSIS_CoreDebug */
Pokitto 6:ea7377f3d1af 460
Pokitto 6:ea7377f3d1af 461
Pokitto 6:ea7377f3d1af 462 /** \ingroup CMSIS_core_register
Pokitto 6:ea7377f3d1af 463 \defgroup CMSIS_core_base Core Definitions
Pokitto 6:ea7377f3d1af 464 \brief Definitions for base addresses, unions, and structures.
Pokitto 6:ea7377f3d1af 465 @{
Pokitto 6:ea7377f3d1af 466 */
Pokitto 6:ea7377f3d1af 467
Pokitto 6:ea7377f3d1af 468 /* Memory mapping of Cortex-M0 Hardware */
Pokitto 6:ea7377f3d1af 469 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Pokitto 6:ea7377f3d1af 470 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Pokitto 6:ea7377f3d1af 471 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Pokitto 6:ea7377f3d1af 472 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Pokitto 6:ea7377f3d1af 473
Pokitto 6:ea7377f3d1af 474 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Pokitto 6:ea7377f3d1af 475 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Pokitto 6:ea7377f3d1af 476 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Pokitto 6:ea7377f3d1af 477
Pokitto 6:ea7377f3d1af 478
Pokitto 6:ea7377f3d1af 479 /*@} */
Pokitto 6:ea7377f3d1af 480
Pokitto 6:ea7377f3d1af 481
Pokitto 6:ea7377f3d1af 482
Pokitto 6:ea7377f3d1af 483 /*******************************************************************************
Pokitto 6:ea7377f3d1af 484 * Hardware Abstraction Layer
Pokitto 6:ea7377f3d1af 485 Core Function Interface contains:
Pokitto 6:ea7377f3d1af 486 - Core NVIC Functions
Pokitto 6:ea7377f3d1af 487 - Core SysTick Functions
Pokitto 6:ea7377f3d1af 488 - Core Register Access Functions
Pokitto 6:ea7377f3d1af 489 ******************************************************************************/
Pokitto 6:ea7377f3d1af 490 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Pokitto 6:ea7377f3d1af 491 */
Pokitto 6:ea7377f3d1af 492
Pokitto 6:ea7377f3d1af 493
Pokitto 6:ea7377f3d1af 494
Pokitto 6:ea7377f3d1af 495 /* ########################## NVIC functions #################################### */
Pokitto 6:ea7377f3d1af 496 /** \ingroup CMSIS_Core_FunctionInterface
Pokitto 6:ea7377f3d1af 497 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Pokitto 6:ea7377f3d1af 498 \brief Functions that manage interrupts and exceptions via the NVIC.
Pokitto 6:ea7377f3d1af 499 @{
Pokitto 6:ea7377f3d1af 500 */
Pokitto 6:ea7377f3d1af 501
Pokitto 6:ea7377f3d1af 502 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Pokitto 6:ea7377f3d1af 503 /* The following MACROS handle generation of the register offset and byte masks */
Pokitto 6:ea7377f3d1af 504 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
Pokitto 6:ea7377f3d1af 505 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
Pokitto 6:ea7377f3d1af 506 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
Pokitto 6:ea7377f3d1af 507
Pokitto 6:ea7377f3d1af 508
Pokitto 6:ea7377f3d1af 509 /** \brief Enable External Interrupt
Pokitto 6:ea7377f3d1af 510
Pokitto 6:ea7377f3d1af 511 The function enables a device-specific interrupt in the NVIC interrupt controller.
Pokitto 6:ea7377f3d1af 512
Pokitto 6:ea7377f3d1af 513 \param [in] IRQn External interrupt number. Value cannot be negative.
Pokitto 6:ea7377f3d1af 514 */
Pokitto 6:ea7377f3d1af 515 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Pokitto 6:ea7377f3d1af 516 {
Pokitto 6:ea7377f3d1af 517 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Pokitto 6:ea7377f3d1af 518 }
Pokitto 6:ea7377f3d1af 519
Pokitto 6:ea7377f3d1af 520
Pokitto 6:ea7377f3d1af 521 /** \brief Disable External Interrupt
Pokitto 6:ea7377f3d1af 522
Pokitto 6:ea7377f3d1af 523 The function disables a device-specific interrupt in the NVIC interrupt controller.
Pokitto 6:ea7377f3d1af 524
Pokitto 6:ea7377f3d1af 525 \param [in] IRQn External interrupt number. Value cannot be negative.
Pokitto 6:ea7377f3d1af 526 */
Pokitto 6:ea7377f3d1af 527 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Pokitto 6:ea7377f3d1af 528 {
Pokitto 6:ea7377f3d1af 529 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Pokitto 6:ea7377f3d1af 530 }
Pokitto 6:ea7377f3d1af 531
Pokitto 6:ea7377f3d1af 532
Pokitto 6:ea7377f3d1af 533 /** \brief Get Pending Interrupt
Pokitto 6:ea7377f3d1af 534
Pokitto 6:ea7377f3d1af 535 The function reads the pending register in the NVIC and returns the pending bit
Pokitto 6:ea7377f3d1af 536 for the specified interrupt.
Pokitto 6:ea7377f3d1af 537
Pokitto 6:ea7377f3d1af 538 \param [in] IRQn Interrupt number.
Pokitto 6:ea7377f3d1af 539
Pokitto 6:ea7377f3d1af 540 \return 0 Interrupt status is not pending.
Pokitto 6:ea7377f3d1af 541 \return 1 Interrupt status is pending.
Pokitto 6:ea7377f3d1af 542 */
Pokitto 6:ea7377f3d1af 543 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Pokitto 6:ea7377f3d1af 544 {
Pokitto 6:ea7377f3d1af 545 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
Pokitto 6:ea7377f3d1af 546 }
Pokitto 6:ea7377f3d1af 547
Pokitto 6:ea7377f3d1af 548
Pokitto 6:ea7377f3d1af 549 /** \brief Set Pending Interrupt
Pokitto 6:ea7377f3d1af 550
Pokitto 6:ea7377f3d1af 551 The function sets the pending bit of an external interrupt.
Pokitto 6:ea7377f3d1af 552
Pokitto 6:ea7377f3d1af 553 \param [in] IRQn Interrupt number. Value cannot be negative.
Pokitto 6:ea7377f3d1af 554 */
Pokitto 6:ea7377f3d1af 555 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Pokitto 6:ea7377f3d1af 556 {
Pokitto 6:ea7377f3d1af 557 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Pokitto 6:ea7377f3d1af 558 }
Pokitto 6:ea7377f3d1af 559
Pokitto 6:ea7377f3d1af 560
Pokitto 6:ea7377f3d1af 561 /** \brief Clear Pending Interrupt
Pokitto 6:ea7377f3d1af 562
Pokitto 6:ea7377f3d1af 563 The function clears the pending bit of an external interrupt.
Pokitto 6:ea7377f3d1af 564
Pokitto 6:ea7377f3d1af 565 \param [in] IRQn External interrupt number. Value cannot be negative.
Pokitto 6:ea7377f3d1af 566 */
Pokitto 6:ea7377f3d1af 567 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Pokitto 6:ea7377f3d1af 568 {
Pokitto 6:ea7377f3d1af 569 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
Pokitto 6:ea7377f3d1af 570 }
Pokitto 6:ea7377f3d1af 571
Pokitto 6:ea7377f3d1af 572
Pokitto 6:ea7377f3d1af 573 /** \brief Set Interrupt Priority
Pokitto 6:ea7377f3d1af 574
Pokitto 6:ea7377f3d1af 575 The function sets the priority of an interrupt.
Pokitto 6:ea7377f3d1af 576
Pokitto 6:ea7377f3d1af 577 \note The priority cannot be set for every core interrupt.
Pokitto 6:ea7377f3d1af 578
Pokitto 6:ea7377f3d1af 579 \param [in] IRQn Interrupt number.
Pokitto 6:ea7377f3d1af 580 \param [in] priority Priority to set.
Pokitto 6:ea7377f3d1af 581 */
Pokitto 6:ea7377f3d1af 582 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Pokitto 6:ea7377f3d1af 583 {
Pokitto 6:ea7377f3d1af 584 if(IRQn < 0) {
Pokitto 6:ea7377f3d1af 585 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
Pokitto 6:ea7377f3d1af 586 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
Pokitto 6:ea7377f3d1af 587 else {
Pokitto 6:ea7377f3d1af 588 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
Pokitto 6:ea7377f3d1af 589 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
Pokitto 6:ea7377f3d1af 590 }
Pokitto 6:ea7377f3d1af 591
Pokitto 6:ea7377f3d1af 592
Pokitto 6:ea7377f3d1af 593 /** \brief Get Interrupt Priority
Pokitto 6:ea7377f3d1af 594
Pokitto 6:ea7377f3d1af 595 The function reads the priority of an interrupt. The interrupt
Pokitto 6:ea7377f3d1af 596 number can be positive to specify an external (device specific)
Pokitto 6:ea7377f3d1af 597 interrupt, or negative to specify an internal (core) interrupt.
Pokitto 6:ea7377f3d1af 598
Pokitto 6:ea7377f3d1af 599
Pokitto 6:ea7377f3d1af 600 \param [in] IRQn Interrupt number.
Pokitto 6:ea7377f3d1af 601 \return Interrupt Priority. Value is aligned automatically to the implemented
Pokitto 6:ea7377f3d1af 602 priority bits of the microcontroller.
Pokitto 6:ea7377f3d1af 603 */
Pokitto 6:ea7377f3d1af 604 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Pokitto 6:ea7377f3d1af 605 {
Pokitto 6:ea7377f3d1af 606
Pokitto 6:ea7377f3d1af 607 if(IRQn < 0) {
Pokitto 6:ea7377f3d1af 608 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
Pokitto 6:ea7377f3d1af 609 else {
Pokitto 6:ea7377f3d1af 610 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
Pokitto 6:ea7377f3d1af 611 }
Pokitto 6:ea7377f3d1af 612
Pokitto 6:ea7377f3d1af 613
Pokitto 6:ea7377f3d1af 614 /** \brief System Reset
Pokitto 6:ea7377f3d1af 615
Pokitto 6:ea7377f3d1af 616 The function initiates a system reset request to reset the MCU.
Pokitto 6:ea7377f3d1af 617 */
Pokitto 6:ea7377f3d1af 618 __STATIC_INLINE void NVIC_SystemReset(void)
Pokitto 6:ea7377f3d1af 619 {
Pokitto 6:ea7377f3d1af 620 __DSB(); /* Ensure all outstanding memory accesses included
Pokitto 6:ea7377f3d1af 621 buffered write are completed before reset */
Pokitto 6:ea7377f3d1af 622 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
Pokitto 6:ea7377f3d1af 623 SCB_AIRCR_SYSRESETREQ_Msk);
Pokitto 6:ea7377f3d1af 624 __DSB(); /* Ensure completion of memory access */
Pokitto 6:ea7377f3d1af 625 while(1); /* wait until reset */
Pokitto 6:ea7377f3d1af 626 }
Pokitto 6:ea7377f3d1af 627
Pokitto 6:ea7377f3d1af 628 /*@} end of CMSIS_Core_NVICFunctions */
Pokitto 6:ea7377f3d1af 629
Pokitto 6:ea7377f3d1af 630
Pokitto 6:ea7377f3d1af 631
Pokitto 6:ea7377f3d1af 632 /* ################################## SysTick function ############################################ */
Pokitto 6:ea7377f3d1af 633 /** \ingroup CMSIS_Core_FunctionInterface
Pokitto 6:ea7377f3d1af 634 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Pokitto 6:ea7377f3d1af 635 \brief Functions that configure the System.
Pokitto 6:ea7377f3d1af 636 @{
Pokitto 6:ea7377f3d1af 637 */
Pokitto 6:ea7377f3d1af 638
Pokitto 6:ea7377f3d1af 639 #if (__Vendor_SysTickConfig == 0)
Pokitto 6:ea7377f3d1af 640
Pokitto 6:ea7377f3d1af 641 /** \brief System Tick Configuration
Pokitto 6:ea7377f3d1af 642
Pokitto 6:ea7377f3d1af 643 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Pokitto 6:ea7377f3d1af 644 Counter is in free running mode to generate periodic interrupts.
Pokitto 6:ea7377f3d1af 645
Pokitto 6:ea7377f3d1af 646 \param [in] ticks Number of ticks between two interrupts.
Pokitto 6:ea7377f3d1af 647
Pokitto 6:ea7377f3d1af 648 \return 0 Function succeeded.
Pokitto 6:ea7377f3d1af 649 \return 1 Function failed.
Pokitto 6:ea7377f3d1af 650
Pokitto 6:ea7377f3d1af 651 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Pokitto 6:ea7377f3d1af 652 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Pokitto 6:ea7377f3d1af 653 must contain a vendor-specific implementation of this function.
Pokitto 6:ea7377f3d1af 654
Pokitto 6:ea7377f3d1af 655 */
Pokitto 6:ea7377f3d1af 656 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Pokitto 6:ea7377f3d1af 657 {
Pokitto 6:ea7377f3d1af 658 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
Pokitto 6:ea7377f3d1af 659
Pokitto 6:ea7377f3d1af 660 SysTick->LOAD = ticks - 1; /* set reload register */
Pokitto 6:ea7377f3d1af 661 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
Pokitto 6:ea7377f3d1af 662 SysTick->VAL = 0; /* Load the SysTick Counter Value */
Pokitto 6:ea7377f3d1af 663 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Pokitto 6:ea7377f3d1af 664 SysTick_CTRL_TICKINT_Msk |
Pokitto 6:ea7377f3d1af 665 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Pokitto 6:ea7377f3d1af 666 return (0); /* Function successful */
Pokitto 6:ea7377f3d1af 667 }
Pokitto 6:ea7377f3d1af 668
Pokitto 6:ea7377f3d1af 669 #endif
Pokitto 6:ea7377f3d1af 670
Pokitto 6:ea7377f3d1af 671 /*@} end of CMSIS_Core_SysTickFunctions */
Pokitto 6:ea7377f3d1af 672
Pokitto 6:ea7377f3d1af 673
Pokitto 6:ea7377f3d1af 674
Pokitto 6:ea7377f3d1af 675
Pokitto 6:ea7377f3d1af 676 #endif /* __CORE_CM0_H_DEPENDANT */
Pokitto 6:ea7377f3d1af 677
Pokitto 6:ea7377f3d1af 678 #endif /* __CMSIS_GENERIC */
Pokitto 6:ea7377f3d1af 679
Pokitto 6:ea7377f3d1af 680 #ifdef __cplusplus
Pokitto 6:ea7377f3d1af 681 }
Pokitto 6:ea7377f3d1af 682 #endif