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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cec.h@150:da61ba4e9755, 2016-11-25 (annotated)

Committer:
sivasuren
Date:
Fri Nov 25 07:57:40 2016 +0000
Revision:
150:da61ba4e9755
Parent:
149:156823d33999 
surendar changes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_cec.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.4.0
<> 144:ef7eb2e8f9f7 6 * @date 27-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of CEC HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F0xx_HAL_CEC_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F0xx_HAL_CEC_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 #if defined(STM32F042x6) || defined(STM32F048xx) ||\
<> 144:ef7eb2e8f9f7 47 defined(STM32F051x8) || defined(STM32F058xx) ||\
<> 144:ef7eb2e8f9f7 48 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) ||\
<> 144:ef7eb2e8f9f7 49 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 50 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 51 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /** @addtogroup CEC CEC
<> 144:ef7eb2e8f9f7 58 * @{
<> 144:ef7eb2e8f9f7 59 */
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 62 /** @defgroup CEC_Exported_Types CEC Exported Types
<> 144:ef7eb2e8f9f7 63 * @{
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 /**
<> 144:ef7eb2e8f9f7 67 * @brief CEC Init Structure definition
<> 144:ef7eb2e8f9f7 68 */
<> 144:ef7eb2e8f9f7 69 typedef struct
<> 144:ef7eb2e8f9f7 70 {
<> 144:ef7eb2e8f9f7 71 uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
<> 144:ef7eb2e8f9f7 72 It can be one of @ref CEC_Signal_Free_Time
<> 144:ef7eb2e8f9f7 73 and belongs to the set {0,...,7} where
<> 144:ef7eb2e8f9f7 74 0x0 is the default configuration
<> 144:ef7eb2e8f9f7 75 else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
<> 144:ef7eb2e8f9f7 78 it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
<> 144:ef7eb2e8f9f7 79 or CEC_EXTENDED_TOLERANCE */
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
<> 144:ef7eb2e8f9f7 82 CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
<> 144:ef7eb2e8f9f7 83 CEC_RX_STOP_ON_BRE: reception is stopped. */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
<> 144:ef7eb2e8f9f7 86 CEC line upon Bit Rising Error detection.
<> 144:ef7eb2e8f9f7 87 CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
<> 144:ef7eb2e8f9f7 88 CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
<> 144:ef7eb2e8f9f7 91 CEC line upon Long Bit Period Error detection.
<> 144:ef7eb2e8f9f7 92 CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
<> 144:ef7eb2e8f9f7 93 CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
<> 144:ef7eb2e8f9f7 96 upon an error detected on a broadcast message.
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
<> 144:ef7eb2e8f9f7 101 a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
<> 144:ef7eb2e8f9f7 102 and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
<> 144:ef7eb2e8f9f7 103 b) LBPE detection: error-bit generation on the CEC line
<> 144:ef7eb2e8f9f7 104 if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
<> 144:ef7eb2e8f9f7 107 no error-bit generation in case neither a) nor b) are satisfied. Additionally,
<> 144:ef7eb2e8f9f7 108 there is no error-bit generation in case of Short Bit Period Error detection in
<> 144:ef7eb2e8f9f7 109 a broadcast message while LSTN bit is set. */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
<> 144:ef7eb2e8f9f7 112 CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
<> 144:ef7eb2e8f9f7 113 CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 uint32_t OwnAddress; /*!< Set OAR field, specifies CEC device address within a 15-bit long field */
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
<> 144:ef7eb2e8f9f7 120 own address (OAR). Messages addressed to different destination are ignored.
<> 144:ef7eb2e8f9f7 121 Broadcast messages are always received.
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
<> 144:ef7eb2e8f9f7 124 address (OAR) with positive acknowledge. Messages addressed to different destination
<> 144:ef7eb2e8f9f7 125 are received, but without interfering with the CEC bus: no acknowledge sent. */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 uint8_t InitiatorAddress; /* Initiator address (source logical address, sent in each header) */
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 }CEC_InitTypeDef;
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /**
<> 144:ef7eb2e8f9f7 132 * @brief HAL CEC State structures definition
<> 144:ef7eb2e8f9f7 133 */
<> 144:ef7eb2e8f9f7 134 typedef enum
<> 144:ef7eb2e8f9f7 135 {
<> 144:ef7eb2e8f9f7 136 HAL_CEC_STATE_RESET = 0x00, /*!< Peripheral Reset state */
<> 144:ef7eb2e8f9f7 137 HAL_CEC_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
<> 144:ef7eb2e8f9f7 138 HAL_CEC_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
<> 144:ef7eb2e8f9f7 139 HAL_CEC_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
<> 144:ef7eb2e8f9f7 140 HAL_CEC_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
<> 144:ef7eb2e8f9f7 141 HAL_CEC_STATE_STANDBY_RX = 0x05, /*!< IP ready to receive, doesn't prevent IP to transmit */
<> 144:ef7eb2e8f9f7 142 HAL_CEC_STATE_TIMEOUT = 0x06, /*!< Timeout state */
<> 144:ef7eb2e8f9f7 143 HAL_CEC_STATE_ERROR = 0x07 /*!< State Error */
<> 144:ef7eb2e8f9f7 144 }HAL_CEC_StateTypeDef;
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /**
<> 144:ef7eb2e8f9f7 147 * @brief CEC handle Structure definition
<> 144:ef7eb2e8f9f7 148 */
<> 144:ef7eb2e8f9f7 149 typedef struct
<> 144:ef7eb2e8f9f7 150 {
<> 144:ef7eb2e8f9f7 151 CEC_TypeDef *Instance; /* CEC registers base address */
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 CEC_InitTypeDef Init; /* CEC communication parameters */
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 uint8_t *pTxBuffPtr; /* Pointer to CEC Tx transfer Buffer */
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 uint16_t TxXferCount; /* CEC Tx Transfer Counter */
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 uint8_t *pRxBuffPtr; /* Pointer to CEC Rx transfer Buffer */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 uint16_t RxXferSize; /* CEC Rx Transfer size, 0: header received only */
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 uint32_t ErrorCode; /* For errors handling purposes, copy of ISR register
<> 144:ef7eb2e8f9f7 164 in case error is reported */
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 HAL_LockTypeDef Lock; /* Locking object */
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 HAL_CEC_StateTypeDef State; /* CEC communication state */
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 }CEC_HandleTypeDef;
<> 144:ef7eb2e8f9f7 171 /**
<> 144:ef7eb2e8f9f7 172 * @}
<> 144:ef7eb2e8f9f7 173 */
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 176 /** @defgroup CEC_Exported_Constants CEC Exported Constants
<> 144:ef7eb2e8f9f7 177 * @{
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /** @defgroup CEC_Error_Code CEC Error Code
<> 144:ef7eb2e8f9f7 181 * @{
<> 144:ef7eb2e8f9f7 182 */
<> 144:ef7eb2e8f9f7 183 #define HAL_CEC_ERROR_NONE (uint32_t) 0x0 /*!< no error */
<> 144:ef7eb2e8f9f7 184 #define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
<> 144:ef7eb2e8f9f7 185 #define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
<> 144:ef7eb2e8f9f7 186 #define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
<> 144:ef7eb2e8f9f7 187 #define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */
<> 144:ef7eb2e8f9f7 188 #define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */
<> 144:ef7eb2e8f9f7 189 #define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */
<> 144:ef7eb2e8f9f7 190 #define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */
<> 144:ef7eb2e8f9f7 191 #define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */
<> 144:ef7eb2e8f9f7 192 #define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
<> 144:ef7eb2e8f9f7 193 /**
<> 144:ef7eb2e8f9f7 194 * @}
<> 144:ef7eb2e8f9f7 195 */
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /** @defgroup CEC_Signal_Free_Time Signal Free Time setting parameter
<> 144:ef7eb2e8f9f7 198 * @{
<> 144:ef7eb2e8f9f7 199 */
<> 144:ef7eb2e8f9f7 200 #define CEC_DEFAULT_SFT ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 201 #define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 202 #define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002)
<> 144:ef7eb2e8f9f7 203 #define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003)
<> 144:ef7eb2e8f9f7 204 #define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004)
<> 144:ef7eb2e8f9f7 205 #define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005)
<> 144:ef7eb2e8f9f7 206 #define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006)
<> 144:ef7eb2e8f9f7 207 #define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007)
<> 144:ef7eb2e8f9f7 208 /**
<> 144:ef7eb2e8f9f7 209 * @}
<> 144:ef7eb2e8f9f7 210 */
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /** @defgroup CEC_Tolerance Receiver Tolerance
<> 144:ef7eb2e8f9f7 213 * @{
<> 144:ef7eb2e8f9f7 214 */
<> 144:ef7eb2e8f9f7 215 #define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 216 #define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
<> 144:ef7eb2e8f9f7 217 /**
<> 144:ef7eb2e8f9f7 218 * @}
<> 144:ef7eb2e8f9f7 219 */
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /** @defgroup CEC_BRERxStop Reception Stop on Error
<> 144:ef7eb2e8f9f7 222 * @{
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224 #define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 225 #define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
<> 144:ef7eb2e8f9f7 226 /**
<> 144:ef7eb2e8f9f7 227 * @}
<> 144:ef7eb2e8f9f7 228 */
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /** @defgroup CEC_BREErrorBitGen Error Bit Generation if Bit Rise Error reported
<> 144:ef7eb2e8f9f7 231 * @{
<> 144:ef7eb2e8f9f7 232 */
<> 144:ef7eb2e8f9f7 233 #define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 234 #define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
<> 144:ef7eb2e8f9f7 235 /**
<> 144:ef7eb2e8f9f7 236 * @}
<> 144:ef7eb2e8f9f7 237 */
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /** @defgroup CEC_LBPEErrorBitGen Error Bit Generation if Long Bit Period Error reported
<> 144:ef7eb2e8f9f7 240 * @{
<> 144:ef7eb2e8f9f7 241 */
<> 144:ef7eb2e8f9f7 242 #define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 243 #define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
<> 144:ef7eb2e8f9f7 244 /**
<> 144:ef7eb2e8f9f7 245 * @}
<> 144:ef7eb2e8f9f7 246 */
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /** @defgroup CEC_BroadCastMsgErrorBitGen Error Bit Generation on Broadcast message
<> 144:ef7eb2e8f9f7 249 * @{
<> 144:ef7eb2e8f9f7 250 */
<> 144:ef7eb2e8f9f7 251 #define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 252 #define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
<> 144:ef7eb2e8f9f7 253 /**
<> 144:ef7eb2e8f9f7 254 * @}
<> 144:ef7eb2e8f9f7 255 */
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /** @defgroup CEC_SFT_Option Signal Free Time start option
<> 144:ef7eb2e8f9f7 258 * @{
<> 144:ef7eb2e8f9f7 259 */
<> 144:ef7eb2e8f9f7 260 #define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 261 #define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
<> 144:ef7eb2e8f9f7 262 /**
<> 144:ef7eb2e8f9f7 263 * @}
<> 144:ef7eb2e8f9f7 264 */
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /** @defgroup CEC_Listening_Mode Listening mode option
<> 144:ef7eb2e8f9f7 267 * @{
<> 144:ef7eb2e8f9f7 268 */
<> 144:ef7eb2e8f9f7 269 #define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 270 #define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
<> 144:ef7eb2e8f9f7 271 /**
<> 144:ef7eb2e8f9f7 272 * @}
<> 144:ef7eb2e8f9f7 273 */
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 /** @defgroup CEC_OAR_Position Device Own Address position in CEC CFGR register
<> 144:ef7eb2e8f9f7 276 * @{
<> 144:ef7eb2e8f9f7 277 */
<> 144:ef7eb2e8f9f7 278 #define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16)
<> 144:ef7eb2e8f9f7 279 /**
<> 144:ef7eb2e8f9f7 280 * @}
<> 144:ef7eb2e8f9f7 281 */
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /** @defgroup CEC_Initiator_Position Initiator logical address position in message header
<> 144:ef7eb2e8f9f7 284 * @{
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286 #define CEC_INITIATOR_LSB_POS ((uint32_t) 4)
<> 144:ef7eb2e8f9f7 287 /**
<> 144:ef7eb2e8f9f7 288 * @}
<> 144:ef7eb2e8f9f7 289 */
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition
<> 144:ef7eb2e8f9f7 292 * @{
<> 144:ef7eb2e8f9f7 293 */
<> 144:ef7eb2e8f9f7 294 #define CEC_IT_TXACKE CEC_IER_TXACKEIE
<> 144:ef7eb2e8f9f7 295 #define CEC_IT_TXERR CEC_IER_TXERRIE
<> 144:ef7eb2e8f9f7 296 #define CEC_IT_TXUDR CEC_IER_TXUDRIE
<> 144:ef7eb2e8f9f7 297 #define CEC_IT_TXEND CEC_IER_TXENDIE
<> 144:ef7eb2e8f9f7 298 #define CEC_IT_TXBR CEC_IER_TXBRIE
<> 144:ef7eb2e8f9f7 299 #define CEC_IT_ARBLST CEC_IER_ARBLSTIE
<> 144:ef7eb2e8f9f7 300 #define CEC_IT_RXACKE CEC_IER_RXACKEIE
<> 144:ef7eb2e8f9f7 301 #define CEC_IT_LBPE CEC_IER_LBPEIE
<> 144:ef7eb2e8f9f7 302 #define CEC_IT_SBPE CEC_IER_SBPEIE
<> 144:ef7eb2e8f9f7 303 #define CEC_IT_BRE CEC_IER_BREIE
<> 144:ef7eb2e8f9f7 304 #define CEC_IT_RXOVR CEC_IER_RXOVRIE
<> 144:ef7eb2e8f9f7 305 #define CEC_IT_RXEND CEC_IER_RXENDIE
<> 144:ef7eb2e8f9f7 306 #define CEC_IT_RXBR CEC_IER_RXBRIE
<> 144:ef7eb2e8f9f7 307 /**
<> 144:ef7eb2e8f9f7 308 * @}
<> 144:ef7eb2e8f9f7 309 */
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /** @defgroup CEC_Flags_Definitions CEC Flags definition
<> 144:ef7eb2e8f9f7 312 * @{
<> 144:ef7eb2e8f9f7 313 */
<> 144:ef7eb2e8f9f7 314 #define CEC_FLAG_TXACKE CEC_ISR_TXACKE
<> 144:ef7eb2e8f9f7 315 #define CEC_FLAG_TXERR CEC_ISR_TXERR
<> 144:ef7eb2e8f9f7 316 #define CEC_FLAG_TXUDR CEC_ISR_TXUDR
<> 144:ef7eb2e8f9f7 317 #define CEC_FLAG_TXEND CEC_ISR_TXEND
<> 144:ef7eb2e8f9f7 318 #define CEC_FLAG_TXBR CEC_ISR_TXBR
<> 144:ef7eb2e8f9f7 319 #define CEC_FLAG_ARBLST CEC_ISR_ARBLST
<> 144:ef7eb2e8f9f7 320 #define CEC_FLAG_RXACKE CEC_ISR_RXACKE
<> 144:ef7eb2e8f9f7 321 #define CEC_FLAG_LBPE CEC_ISR_LBPE
<> 144:ef7eb2e8f9f7 322 #define CEC_FLAG_SBPE CEC_ISR_SBPE
<> 144:ef7eb2e8f9f7 323 #define CEC_FLAG_BRE CEC_ISR_BRE
<> 144:ef7eb2e8f9f7 324 #define CEC_FLAG_RXOVR CEC_ISR_RXOVR
<> 144:ef7eb2e8f9f7 325 #define CEC_FLAG_RXEND CEC_ISR_RXEND
<> 144:ef7eb2e8f9f7 326 #define CEC_FLAG_RXBR CEC_ISR_RXBR
<> 144:ef7eb2e8f9f7 327 /**
<> 144:ef7eb2e8f9f7 328 * @}
<> 144:ef7eb2e8f9f7 329 */
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /** @defgroup CEC_ALL_ERROR all RX or TX errors flags in CEC ISR register
<> 144:ef7eb2e8f9f7 333 * @{
<> 144:ef7eb2e8f9f7 334 */
<> 144:ef7eb2e8f9f7 335 #define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
<> 144:ef7eb2e8f9f7 336 CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
<> 144:ef7eb2e8f9f7 337 /**
<> 144:ef7eb2e8f9f7 338 * @}
<> 144:ef7eb2e8f9f7 339 */
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /** @defgroup CEC_IER_ALL_RX all RX errors interrupts enabling flag
<> 144:ef7eb2e8f9f7 342 * @{
<> 144:ef7eb2e8f9f7 343 */
<> 144:ef7eb2e8f9f7 344 #define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
<> 144:ef7eb2e8f9f7 345 /**
<> 144:ef7eb2e8f9f7 346 * @}
<> 144:ef7eb2e8f9f7 347 */
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /** @defgroup CEC_IER_ALL_TX all TX errors interrupts enabling flag
<> 144:ef7eb2e8f9f7 350 * @{
<> 144:ef7eb2e8f9f7 351 */
<> 144:ef7eb2e8f9f7 352 #define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
<> 144:ef7eb2e8f9f7 353 /**
<> 144:ef7eb2e8f9f7 354 * @}
<> 144:ef7eb2e8f9f7 355 */
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /**
<> 144:ef7eb2e8f9f7 358 * @}
<> 144:ef7eb2e8f9f7 359 */
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 362 /** @defgroup CEC_Exported_Macros CEC Exported Macros
<> 144:ef7eb2e8f9f7 363 * @{
<> 144:ef7eb2e8f9f7 364 */
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /** @brief Reset CEC handle state
<> 144:ef7eb2e8f9f7 367 * @param __HANDLE__: CEC handle.
<> 144:ef7eb2e8f9f7 368 * @retval None
<> 144:ef7eb2e8f9f7 369 */
<> 144:ef7eb2e8f9f7 370 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CEC_STATE_RESET)
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 /** @brief Checks whether or not the specified CEC interrupt flag is set.
<> 144:ef7eb2e8f9f7 373 * @param __HANDLE__: specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 374 * @param __FLAG__: specifies the interrupt to check.
<> 144:ef7eb2e8f9f7 375 * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
<> 144:ef7eb2e8f9f7 376 * @arg CEC_FLAG_TXERR: Tx Error.
<> 144:ef7eb2e8f9f7 377 * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
<> 144:ef7eb2e8f9f7 378 * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
<> 144:ef7eb2e8f9f7 379 * @arg CEC_FLAG_TXBR: Tx-Byte Request.
<> 144:ef7eb2e8f9f7 380 * @arg CEC_FLAG_ARBLST: Arbitration Lost
<> 144:ef7eb2e8f9f7 381 * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
<> 144:ef7eb2e8f9f7 382 * @arg CEC_FLAG_LBPE: Rx Long period Error
<> 144:ef7eb2e8f9f7 383 * @arg CEC_FLAG_SBPE: Rx Short period Error
<> 144:ef7eb2e8f9f7 384 * @arg CEC_FLAG_BRE: Rx Bit Rissing Error
<> 144:ef7eb2e8f9f7 385 * @arg CEC_FLAG_RXOVR: Rx Overrun.
<> 144:ef7eb2e8f9f7 386 * @arg CEC_FLAG_RXEND: End Of Reception.
<> 144:ef7eb2e8f9f7 387 * @arg CEC_FLAG_RXBR: Rx-Byte Received.
<> 144:ef7eb2e8f9f7 388 * @retval None
<> 144:ef7eb2e8f9f7 389 */
<> 144:ef7eb2e8f9f7 390 #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 /** @brief Clears the interrupt or status flag when raised (write at 1)
<> 144:ef7eb2e8f9f7 393 * @param __HANDLE__: specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 394 * @param __FLAG__: specifies the interrupt/status flag to clear.
<> 144:ef7eb2e8f9f7 395 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 396 * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
<> 144:ef7eb2e8f9f7 397 * @arg CEC_FLAG_TXERR: Tx Error.
<> 144:ef7eb2e8f9f7 398 * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
<> 144:ef7eb2e8f9f7 399 * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
<> 144:ef7eb2e8f9f7 400 * @arg CEC_FLAG_TXBR: Tx-Byte Request.
<> 144:ef7eb2e8f9f7 401 * @arg CEC_FLAG_ARBLST: Arbitration Lost
<> 144:ef7eb2e8f9f7 402 * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
<> 144:ef7eb2e8f9f7 403 * @arg CEC_FLAG_LBPE: Rx Long period Error
<> 144:ef7eb2e8f9f7 404 * @arg CEC_FLAG_SBPE: Rx Short period Error
<> 144:ef7eb2e8f9f7 405 * @arg CEC_FLAG_BRE: Rx Bit Rissing Error
<> 144:ef7eb2e8f9f7 406 * @arg CEC_FLAG_RXOVR: Rx Overrun.
<> 144:ef7eb2e8f9f7 407 * @arg CEC_FLAG_RXEND: End Of Reception.
<> 144:ef7eb2e8f9f7 408 * @arg CEC_FLAG_RXBR: Rx-Byte Received.
<> 144:ef7eb2e8f9f7 409 * @retval none
<> 144:ef7eb2e8f9f7 410 */
<> 144:ef7eb2e8f9f7 411 #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 /** @brief Enables the specified CEC interrupt.
<> 144:ef7eb2e8f9f7 414 * @param __HANDLE__: specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 415 * @param __INTERRUPT__: specifies the CEC interrupt to enable.
<> 144:ef7eb2e8f9f7 416 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 417 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
<> 144:ef7eb2e8f9f7 418 * @arg CEC_IT_TXERR: Tx Error IT Enable
<> 144:ef7eb2e8f9f7 419 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
<> 144:ef7eb2e8f9f7 420 * @arg CEC_IT_TXEND: End of transmission IT Enable
<> 144:ef7eb2e8f9f7 421 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
<> 144:ef7eb2e8f9f7 422 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
<> 144:ef7eb2e8f9f7 423 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
<> 144:ef7eb2e8f9f7 424 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
<> 144:ef7eb2e8f9f7 425 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
<> 144:ef7eb2e8f9f7 426 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
<> 144:ef7eb2e8f9f7 427 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
<> 144:ef7eb2e8f9f7 428 * @arg CEC_IT_RXEND: End Of Reception IT Enable
<> 144:ef7eb2e8f9f7 429 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
<> 144:ef7eb2e8f9f7 430 * @retval none
<> 144:ef7eb2e8f9f7 431 */
<> 144:ef7eb2e8f9f7 432 #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 /** @brief Disables the specified CEC interrupt.
<> 144:ef7eb2e8f9f7 435 * @param __HANDLE__: specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 436 * @param __INTERRUPT__: specifies the CEC interrupt to disable.
<> 144:ef7eb2e8f9f7 437 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 438 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
<> 144:ef7eb2e8f9f7 439 * @arg CEC_IT_TXERR: Tx Error IT Enable
<> 144:ef7eb2e8f9f7 440 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
<> 144:ef7eb2e8f9f7 441 * @arg CEC_IT_TXEND: End of transmission IT Enable
<> 144:ef7eb2e8f9f7 442 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
<> 144:ef7eb2e8f9f7 443 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
<> 144:ef7eb2e8f9f7 444 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
<> 144:ef7eb2e8f9f7 445 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
<> 144:ef7eb2e8f9f7 446 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
<> 144:ef7eb2e8f9f7 447 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
<> 144:ef7eb2e8f9f7 448 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
<> 144:ef7eb2e8f9f7 449 * @arg CEC_IT_RXEND: End Of Reception IT Enable
<> 144:ef7eb2e8f9f7 450 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
<> 144:ef7eb2e8f9f7 451 * @retval none
<> 144:ef7eb2e8f9f7 452 */
<> 144:ef7eb2e8f9f7 453 #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /** @brief Checks whether or not the specified CEC interrupt is enabled.
<> 144:ef7eb2e8f9f7 456 * @param __HANDLE__: specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 457 * @param __INTERRUPT__: specifies the CEC interrupt to check.
<> 144:ef7eb2e8f9f7 458 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 459 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
<> 144:ef7eb2e8f9f7 460 * @arg CEC_IT_TXERR: Tx Error IT Enable
<> 144:ef7eb2e8f9f7 461 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
<> 144:ef7eb2e8f9f7 462 * @arg CEC_IT_TXEND: End of transmission IT Enable
<> 144:ef7eb2e8f9f7 463 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
<> 144:ef7eb2e8f9f7 464 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
<> 144:ef7eb2e8f9f7 465 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
<> 144:ef7eb2e8f9f7 466 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
<> 144:ef7eb2e8f9f7 467 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
<> 144:ef7eb2e8f9f7 468 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
<> 144:ef7eb2e8f9f7 469 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
<> 144:ef7eb2e8f9f7 470 * @arg CEC_IT_RXEND: End Of Reception IT Enable
<> 144:ef7eb2e8f9f7 471 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
<> 144:ef7eb2e8f9f7 472 * @retval FlagStatus
<> 144:ef7eb2e8f9f7 473 */
<> 144:ef7eb2e8f9f7 474 #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 /** @brief Enables the CEC device
<> 144:ef7eb2e8f9f7 477 * @param __HANDLE__: specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 478 * @retval none
<> 144:ef7eb2e8f9f7 479 */
<> 144:ef7eb2e8f9f7 480 #define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 /** @brief Disables the CEC device
<> 144:ef7eb2e8f9f7 483 * @param __HANDLE__: specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 484 * @retval none
<> 144:ef7eb2e8f9f7 485 */
<> 144:ef7eb2e8f9f7 486 #define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /** @brief Set Transmission Start flag
<> 144:ef7eb2e8f9f7 489 * @param __HANDLE__: specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 490 * @retval none
<> 144:ef7eb2e8f9f7 491 */
<> 144:ef7eb2e8f9f7 492 #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /** @brief Set Transmission End flag
<> 144:ef7eb2e8f9f7 495 * @param __HANDLE__: specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 496 * @retval none
<> 144:ef7eb2e8f9f7 497 * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
<> 144:ef7eb2e8f9f7 498 */
<> 144:ef7eb2e8f9f7 499 #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 /** @brief Get Transmission Start flag
<> 144:ef7eb2e8f9f7 502 * @param __HANDLE__: specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 503 * @retval FlagStatus
<> 144:ef7eb2e8f9f7 504 */
<> 144:ef7eb2e8f9f7 505 #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 /** @brief Get Transmission End flag
<> 144:ef7eb2e8f9f7 508 * @param __HANDLE__: specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 509 * @retval FlagStatus
<> 144:ef7eb2e8f9f7 510 */
<> 144:ef7eb2e8f9f7 511 #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 /** @brief Clear OAR register
<> 144:ef7eb2e8f9f7 514 * @param __HANDLE__: specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 515 * @retval none
<> 144:ef7eb2e8f9f7 516 */
<> 144:ef7eb2e8f9f7 517 #define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 /** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
<> 144:ef7eb2e8f9f7 520 * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
<> 144:ef7eb2e8f9f7 521 * @param __HANDLE__: specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 522 * @param __ADDRESS__: Own Address value (CEC logical address is identified by bit position)
<> 144:ef7eb2e8f9f7 523 * @retval none
<> 144:ef7eb2e8f9f7 524 */
<> 144:ef7eb2e8f9f7 525 #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
<> 144:ef7eb2e8f9f7 526 /**
<> 144:ef7eb2e8f9f7 527 * @}
<> 144:ef7eb2e8f9f7 528 */
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 531 /** @addtogroup CEC_Exported_Functions
<> 144:ef7eb2e8f9f7 532 * @{
<> 144:ef7eb2e8f9f7 533 */
<> 144:ef7eb2e8f9f7 534 /** @addtogroup CEC_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 535 * @{
<> 144:ef7eb2e8f9f7 536 */
<> 144:ef7eb2e8f9f7 537 /* Initialization and de-initialization functions ****************************/
<> 144:ef7eb2e8f9f7 538 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 539 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 540 void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 541 void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 542 /**
<> 144:ef7eb2e8f9f7 543 * @}
<> 144:ef7eb2e8f9f7 544 */
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 /** @addtogroup CEC_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 547 * @{
<> 144:ef7eb2e8f9f7 548 */
<> 144:ef7eb2e8f9f7 549 /* I/O operation functions ***************************************************/
<> 144:ef7eb2e8f9f7 550 HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 551 HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 552 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
<> 144:ef7eb2e8f9f7 553 HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData);
<> 144:ef7eb2e8f9f7 554 uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 555 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 556 void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 557 void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 558 void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 559 /**
<> 144:ef7eb2e8f9f7 560 * @}
<> 144:ef7eb2e8f9f7 561 */
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 /** @addtogroup CEC_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 564 * @{
<> 144:ef7eb2e8f9f7 565 */
<> 144:ef7eb2e8f9f7 566 /* Peripheral State functions ************************************************/
<> 144:ef7eb2e8f9f7 567 HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 568 uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 569 /**
<> 144:ef7eb2e8f9f7 570 * @}
<> 144:ef7eb2e8f9f7 571 */
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 /**
<> 144:ef7eb2e8f9f7 574 * @}
<> 144:ef7eb2e8f9f7 575 */
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 578 /** @defgroup CEC_Private_Types CEC Private Types
<> 144:ef7eb2e8f9f7 579 * @{
<> 144:ef7eb2e8f9f7 580 */
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 /**
<> 144:ef7eb2e8f9f7 583 * @}
<> 144:ef7eb2e8f9f7 584 */
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 587 /** @defgroup CEC_Private_Variables CEC Private Variables
<> 144:ef7eb2e8f9f7 588 * @{
<> 144:ef7eb2e8f9f7 589 */
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 /**
<> 144:ef7eb2e8f9f7 592 * @}
<> 144:ef7eb2e8f9f7 593 */
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 596 /** @defgroup CEC_Private_Constants CEC Private Constants
<> 144:ef7eb2e8f9f7 597 * @{
<> 144:ef7eb2e8f9f7 598 */
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 /**
<> 144:ef7eb2e8f9f7 601 * @}
<> 144:ef7eb2e8f9f7 602 */
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 605 /** @defgroup CEC_Private_Macros CEC Private Macros
<> 144:ef7eb2e8f9f7 606 * @{
<> 144:ef7eb2e8f9f7 607 */
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 #define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 #define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
<> 144:ef7eb2e8f9f7 612 ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 #define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
<> 144:ef7eb2e8f9f7 615 ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
<> 144:ef7eb2e8f9f7 616
<> 144:ef7eb2e8f9f7 617 #define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
<> 144:ef7eb2e8f9f7 618 ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 #define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
<> 144:ef7eb2e8f9f7 621 ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 #define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
<> 144:ef7eb2e8f9f7 624 ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 #define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
<> 144:ef7eb2e8f9f7 627 ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 #define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
<> 144:ef7eb2e8f9f7 630 ((__MODE__) == CEC_FULL_LISTENING_MODE))
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 /** @brief Check CEC device Own Address Register (OAR) setting.
<> 144:ef7eb2e8f9f7 633 * OAR address is written in a 15-bit field within CEC_CFGR register.
<> 144:ef7eb2e8f9f7 634 * @param __ADDRESS__: CEC own address.
<> 144:ef7eb2e8f9f7 635 * @retval Test result (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 636 */
<> 144:ef7eb2e8f9f7 637 #define IS_CEC_OAR_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x07FFF)
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 /** @brief Check CEC initiator or destination logical address setting.
<> 144:ef7eb2e8f9f7 640 * Initiator and destination addresses are coded over 4 bits.
<> 144:ef7eb2e8f9f7 641 * @param __ADDRESS__: CEC initiator or logical address.
<> 144:ef7eb2e8f9f7 642 * @retval Test result (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 643 */
<> 144:ef7eb2e8f9f7 644 #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 /** @brief Check CEC message size.
<> 144:ef7eb2e8f9f7 647 * The message size is the payload size: without counting the header,
<> 144:ef7eb2e8f9f7 648 * it varies from 0 byte (ping operation, one header only, no payload) to
<> 144:ef7eb2e8f9f7 649 * 15 bytes (1 opcode and up to 14 operands following the header).
<> 144:ef7eb2e8f9f7 650 * @param __SIZE__: CEC message size.
<> 144:ef7eb2e8f9f7 651 * @retval Test result (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 652 */
<> 144:ef7eb2e8f9f7 653 #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF)
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 /**
<> 144:ef7eb2e8f9f7 656 * @}
<> 144:ef7eb2e8f9f7 657 */
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 660 /** @defgroup CEC_Private_Functions CEC Private Functions
<> 144:ef7eb2e8f9f7 661 * @{
<> 144:ef7eb2e8f9f7 662 */
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 /**
<> 144:ef7eb2e8f9f7 665 * @}
<> 144:ef7eb2e8f9f7 666 */
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 /**
<> 144:ef7eb2e8f9f7 669 * @}
<> 144:ef7eb2e8f9f7 670 */
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 /**
<> 144:ef7eb2e8f9f7 673 * @}
<> 144:ef7eb2e8f9f7 674 */
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 #endif /* defined(STM32F042x6) || defined(STM32F048xx) || */
<> 144:ef7eb2e8f9f7 677 /* defined(STM32F051x8) || defined(STM32F058xx) || */
<> 144:ef7eb2e8f9f7 678 /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || */
<> 144:ef7eb2e8f9f7 679 /* defined(STM32F091xC) || defined(STM32F098xx) */
<> 144:ef7eb2e8f9f7 680 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 681 }
<> 144:ef7eb2e8f9f7 682 #endif
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684 #endif /* __STM32F0xx_HAL_CEC_H */
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 687