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targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_tpm.h@150:da61ba4e9755, 2016-11-25 (annotated)

Committer:
sivasuren
Date:
Fri Nov 25 07:57:40 2016 +0000
Revision:
150:da61ba4e9755
Parent:
149:156823d33999 
surendar changes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /*
<> 149:156823d33999 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 149:156823d33999 3 * All rights reserved.
<> 149:156823d33999 4 *
<> 149:156823d33999 5 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 6 * are permitted provided that the following conditions are met:
<> 149:156823d33999 7 *
<> 149:156823d33999 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 149:156823d33999 9 * of conditions and the following disclaimer.
<> 149:156823d33999 10 *
<> 149:156823d33999 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 149:156823d33999 12 * list of conditions and the following disclaimer in the documentation and/or
<> 149:156823d33999 13 * other materials provided with the distribution.
<> 149:156823d33999 14 *
<> 149:156823d33999 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 149:156823d33999 16 * contributors may be used to endorse or promote products derived from this
<> 149:156823d33999 17 * software without specific prior written permission.
<> 149:156823d33999 18 *
<> 149:156823d33999 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 149:156823d33999 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 149:156823d33999 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 149:156823d33999 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 149:156823d33999 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 149:156823d33999 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 149:156823d33999 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 149:156823d33999 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 149:156823d33999 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 29 */
<> 149:156823d33999 30 #ifndef _FSL_TPM_H_
<> 149:156823d33999 31 #define _FSL_TPM_H_
<> 149:156823d33999 32
<> 149:156823d33999 33 #include "fsl_common.h"
<> 149:156823d33999 34
<> 149:156823d33999 35 /*!
<> 149:156823d33999 36 * @addtogroup tpm
<> 149:156823d33999 37 * @{
<> 149:156823d33999 38 */
<> 149:156823d33999 39
<> 149:156823d33999 40
<> 149:156823d33999 41 /*******************************************************************************
<> 149:156823d33999 42 * Definitions
<> 149:156823d33999 43 ******************************************************************************/
<> 149:156823d33999 44
<> 149:156823d33999 45 /*! @name Driver version */
<> 149:156823d33999 46 /*@{*/
<> 149:156823d33999 47 #define FSL_TPM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */
<> 149:156823d33999 48 /*@}*/
<> 149:156823d33999 49
<> 149:156823d33999 50 /*!
<> 149:156823d33999 51 * @brief List of TPM channels.
<> 149:156823d33999 52 * @note Actual number of available channels is SoC dependent
<> 149:156823d33999 53 */
<> 149:156823d33999 54 typedef enum _tpm_chnl
<> 149:156823d33999 55 {
<> 149:156823d33999 56 kTPM_Chnl_0 = 0U, /*!< TPM channel number 0*/
<> 149:156823d33999 57 kTPM_Chnl_1, /*!< TPM channel number 1 */
<> 149:156823d33999 58 kTPM_Chnl_2, /*!< TPM channel number 2 */
<> 149:156823d33999 59 kTPM_Chnl_3, /*!< TPM channel number 3 */
<> 149:156823d33999 60 kTPM_Chnl_4, /*!< TPM channel number 4 */
<> 149:156823d33999 61 kTPM_Chnl_5, /*!< TPM channel number 5 */
<> 149:156823d33999 62 kTPM_Chnl_6, /*!< TPM channel number 6 */
<> 149:156823d33999 63 kTPM_Chnl_7 /*!< TPM channel number 7 */
<> 149:156823d33999 64 } tpm_chnl_t;
<> 149:156823d33999 65
<> 149:156823d33999 66 /*! @brief TPM PWM operation modes */
<> 149:156823d33999 67 typedef enum _tpm_pwm_mode
<> 149:156823d33999 68 {
<> 149:156823d33999 69 kTPM_EdgeAlignedPwm = 0U, /*!< Edge aligned PWM */
<> 149:156823d33999 70 kTPM_CenterAlignedPwm, /*!< Center aligned PWM */
<> 149:156823d33999 71 #if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
<> 149:156823d33999 72 kTPM_CombinedPwm /*!< Combined PWM */
<> 149:156823d33999 73 #endif
<> 149:156823d33999 74 } tpm_pwm_mode_t;
<> 149:156823d33999 75
<> 149:156823d33999 76 /*! @brief TPM PWM output pulse mode: high-true, low-true or no output */
<> 149:156823d33999 77 typedef enum _tpm_pwm_level_select
<> 149:156823d33999 78 {
<> 149:156823d33999 79 kTPM_NoPwmSignal = 0U, /*!< No PWM output on pin */
<> 149:156823d33999 80 kTPM_LowTrue, /*!< Low true pulses */
<> 149:156823d33999 81 kTPM_HighTrue /*!< High true pulses */
<> 149:156823d33999 82 } tpm_pwm_level_select_t;
<> 149:156823d33999 83
<> 149:156823d33999 84 /*! @brief Options to configure a TPM channel's PWM signal */
<> 149:156823d33999 85 typedef struct _tpm_chnl_pwm_signal_param
<> 149:156823d33999 86 {
<> 149:156823d33999 87 tpm_chnl_t chnlNumber; /*!< TPM channel to configure.
<> 149:156823d33999 88 In combined mode (available in some SoC's, this represents the
<> 149:156823d33999 89 channel pair number */
<> 149:156823d33999 90 tpm_pwm_level_select_t level; /*!< PWM output active level select */
<> 149:156823d33999 91 uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100
<> 149:156823d33999 92 0=inactive signal(0% duty cycle)...
<> 149:156823d33999 93 100=always active signal (100% duty cycle)*/
<> 149:156823d33999 94 #if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
<> 149:156823d33999 95 uint8_t firstEdgeDelayPercent; /*!< Used only in combined PWM mode to generate asymmetrical PWM.
<> 149:156823d33999 96 Specifies the delay to the first edge in a PWM period.
<> 149:156823d33999 97 If unsure, leave as 0; Should be specified as
<> 149:156823d33999 98 percentage of the PWM period */
<> 149:156823d33999 99 #endif
<> 149:156823d33999 100 } tpm_chnl_pwm_signal_param_t;
<> 149:156823d33999 101
<> 149:156823d33999 102 /*!
<> 149:156823d33999 103 * @brief Trigger options available.
<> 149:156823d33999 104 *
<> 149:156823d33999 105 * This is used for both internal & external trigger sources (external option available in certain SoC's)
<> 149:156823d33999 106 *
<> 149:156823d33999 107 * @note The actual trigger options available is SoC-specific.
<> 149:156823d33999 108 */
<> 149:156823d33999 109 typedef enum _tpm_trigger_select
<> 149:156823d33999 110 {
<> 149:156823d33999 111 kTPM_Trigger_Select_0 = 0U,
<> 149:156823d33999 112 kTPM_Trigger_Select_1,
<> 149:156823d33999 113 kTPM_Trigger_Select_2,
<> 149:156823d33999 114 kTPM_Trigger_Select_3,
<> 149:156823d33999 115 kTPM_Trigger_Select_4,
<> 149:156823d33999 116 kTPM_Trigger_Select_5,
<> 149:156823d33999 117 kTPM_Trigger_Select_6,
<> 149:156823d33999 118 kTPM_Trigger_Select_7,
<> 149:156823d33999 119 kTPM_Trigger_Select_8,
<> 149:156823d33999 120 kTPM_Trigger_Select_9,
<> 149:156823d33999 121 kTPM_Trigger_Select_10,
<> 149:156823d33999 122 kTPM_Trigger_Select_11,
<> 149:156823d33999 123 kTPM_Trigger_Select_12,
<> 149:156823d33999 124 kTPM_Trigger_Select_13,
<> 149:156823d33999 125 kTPM_Trigger_Select_14,
<> 149:156823d33999 126 kTPM_Trigger_Select_15
<> 149:156823d33999 127 } tpm_trigger_select_t;
<> 149:156823d33999 128
<> 149:156823d33999 129 #if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION
<> 149:156823d33999 130 /*!
<> 149:156823d33999 131 * @brief Trigger source options available
<> 149:156823d33999 132 *
<> 149:156823d33999 133 * @note This selection is available only on some SoC's. For SoC's without this selection, the only
<> 149:156823d33999 134 * trigger source available is internal triger.
<> 149:156823d33999 135 */
<> 149:156823d33999 136 typedef enum _tpm_trigger_source
<> 149:156823d33999 137 {
<> 149:156823d33999 138 kTPM_TriggerSource_External = 0U, /*!< Use external trigger input */
<> 149:156823d33999 139 kTPM_TriggerSource_Internal /*!< Use internal trigger */
<> 149:156823d33999 140 } tpm_trigger_source_t;
<> 149:156823d33999 141 #endif
<> 149:156823d33999 142
<> 149:156823d33999 143 /*! @brief TPM output compare modes */
<> 149:156823d33999 144 typedef enum _tpm_output_compare_mode
<> 149:156823d33999 145 {
<> 149:156823d33999 146 kTPM_NoOutputSignal = (1U << TPM_CnSC_MSA_SHIFT), /*!< No channel output when counter reaches CnV */
<> 149:156823d33999 147 kTPM_ToggleOnMatch = ((1U << TPM_CnSC_MSA_SHIFT) | (1U << TPM_CnSC_ELSA_SHIFT)), /*!< Toggle output */
<> 149:156823d33999 148 kTPM_ClearOnMatch = ((1U << TPM_CnSC_MSA_SHIFT) | (2U << TPM_CnSC_ELSA_SHIFT)), /*!< Clear output */
<> 149:156823d33999 149 kTPM_SetOnMatch = ((1U << TPM_CnSC_MSA_SHIFT) | (3U << TPM_CnSC_ELSA_SHIFT)), /*!< Set output */
<> 149:156823d33999 150 kTPM_HighPulseOutput = ((3U << TPM_CnSC_MSA_SHIFT) | (1U << TPM_CnSC_ELSA_SHIFT)), /*!< Pulse output high */
<> 149:156823d33999 151 kTPM_LowPulseOutput = ((3U << TPM_CnSC_MSA_SHIFT) | (2U << TPM_CnSC_ELSA_SHIFT)) /*!< Pulse output low */
<> 149:156823d33999 152 } tpm_output_compare_mode_t;
<> 149:156823d33999 153
<> 149:156823d33999 154 /*! @brief TPM input capture edge */
<> 149:156823d33999 155 typedef enum _tpm_input_capture_edge
<> 149:156823d33999 156 {
<> 149:156823d33999 157 kTPM_RisingEdge = (1U << TPM_CnSC_ELSA_SHIFT), /*!< Capture on rising edge only */
<> 149:156823d33999 158 kTPM_FallingEdge = (2U << TPM_CnSC_ELSA_SHIFT), /*!< Capture on falling edge only */
<> 149:156823d33999 159 kTPM_RiseAndFallEdge = (3U << TPM_CnSC_ELSA_SHIFT) /*!< Capture on rising or falling edge */
<> 149:156823d33999 160 } tpm_input_capture_edge_t;
<> 149:156823d33999 161
<> 149:156823d33999 162 #if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
<> 149:156823d33999 163 /*!
<> 149:156823d33999 164 * @brief TPM dual edge capture parameters
<> 149:156823d33999 165 *
<> 149:156823d33999 166 * @note This mode is available only on some SoC's.
<> 149:156823d33999 167 */
<> 149:156823d33999 168 typedef struct _tpm_dual_edge_capture_param
<> 149:156823d33999 169 {
<> 149:156823d33999 170 bool enableSwap; /*!< true: Use channel n+1 input, channel n input is ignored;
<> 149:156823d33999 171 false: Use channel n input, channel n+1 input is ignored */
<> 149:156823d33999 172 tpm_input_capture_edge_t currChanEdgeMode; /*!< Input capture edge select for channel n */
<> 149:156823d33999 173 tpm_input_capture_edge_t nextChanEdgeMode; /*!< Input capture edge select for channel n+1 */
<> 149:156823d33999 174 } tpm_dual_edge_capture_param_t;
<> 149:156823d33999 175 #endif
<> 149:156823d33999 176
<> 149:156823d33999 177 #if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
<> 149:156823d33999 178 /*!
<> 149:156823d33999 179 * @brief TPM quadrature decode modes
<> 149:156823d33999 180 *
<> 149:156823d33999 181 * @note This mode is available only on some SoC's.
<> 149:156823d33999 182 */
<> 149:156823d33999 183 typedef enum _tpm_quad_decode_mode
<> 149:156823d33999 184 {
<> 149:156823d33999 185 kTPM_QuadPhaseEncode = 0U, /*!< Phase A and Phase B encoding mode */
<> 149:156823d33999 186 kTPM_QuadCountAndDir /*!< Count and direction encoding mode */
<> 149:156823d33999 187 } tpm_quad_decode_mode_t;
<> 149:156823d33999 188
<> 149:156823d33999 189 /*! @brief TPM quadrature phase polarities */
<> 149:156823d33999 190 typedef enum _tpm_phase_polarity
<> 149:156823d33999 191 {
<> 149:156823d33999 192 kTPM_QuadPhaseNormal = 0U, /*!< Phase input signal is not inverted */
<> 149:156823d33999 193 kTPM_QuadPhaseInvert /*!< Phase input signal is inverted */
<> 149:156823d33999 194 } tpm_phase_polarity_t;
<> 149:156823d33999 195
<> 149:156823d33999 196 /*! @brief TPM quadrature decode phase parameters */
<> 149:156823d33999 197 typedef struct _tpm_phase_param
<> 149:156823d33999 198 {
<> 149:156823d33999 199 uint32_t phaseFilterVal; /*!< Filter value, filter is disabled when the value is zero */
<> 149:156823d33999 200 tpm_phase_polarity_t phasePolarity; /*!< Phase polarity */
<> 149:156823d33999 201 } tpm_phase_params_t;
<> 149:156823d33999 202 #endif
<> 149:156823d33999 203
<> 149:156823d33999 204 /*! @brief TPM clock source selection*/
<> 149:156823d33999 205 typedef enum _tpm_clock_source
<> 149:156823d33999 206 {
<> 149:156823d33999 207 kTPM_SystemClock = 1U, /*!< System clock */
<> 149:156823d33999 208 kTPM_ExternalClock /*!< External clock */
<> 149:156823d33999 209 } tpm_clock_source_t;
<> 149:156823d33999 210
<> 149:156823d33999 211 /*! @brief TPM prescale value selection for the clock source*/
<> 149:156823d33999 212 typedef enum _tpm_clock_prescale
<> 149:156823d33999 213 {
<> 149:156823d33999 214 kTPM_Prescale_Divide_1 = 0U, /*!< Divide by 1 */
<> 149:156823d33999 215 kTPM_Prescale_Divide_2, /*!< Divide by 2 */
<> 149:156823d33999 216 kTPM_Prescale_Divide_4, /*!< Divide by 4 */
<> 149:156823d33999 217 kTPM_Prescale_Divide_8, /*!< Divide by 8 */
<> 149:156823d33999 218 kTPM_Prescale_Divide_16, /*!< Divide by 16 */
<> 149:156823d33999 219 kTPM_Prescale_Divide_32, /*!< Divide by 32 */
<> 149:156823d33999 220 kTPM_Prescale_Divide_64, /*!< Divide by 64 */
<> 149:156823d33999 221 kTPM_Prescale_Divide_128 /*!< Divide by 128 */
<> 149:156823d33999 222 } tpm_clock_prescale_t;
<> 149:156823d33999 223
<> 149:156823d33999 224 /*!
<> 149:156823d33999 225 * @brief TPM config structure
<> 149:156823d33999 226 *
<> 149:156823d33999 227 * This structure holds the configuration settings for the TPM peripheral. To initialize this
<> 149:156823d33999 228 * structure to reasonable defaults, call the TPM_GetDefaultConfig() function and pass a
<> 149:156823d33999 229 * pointer to your config structure instance.
<> 149:156823d33999 230 *
<> 149:156823d33999 231 * The config struct can be made const so it resides in flash
<> 149:156823d33999 232 */
<> 149:156823d33999 233 typedef struct _tpm_config
<> 149:156823d33999 234 {
<> 149:156823d33999 235 tpm_clock_prescale_t prescale; /*!< Select TPM clock prescale value */
<> 149:156823d33999 236 bool useGlobalTimeBase; /*!< true: Use of an external global time base is enabled;
<> 149:156823d33999 237 false: disabled */
<> 149:156823d33999 238 tpm_trigger_select_t triggerSelect; /*!< Input trigger to use for controlling the counter operation */
<> 149:156823d33999 239 #if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION
<> 149:156823d33999 240 tpm_trigger_source_t triggerSource; /*!< Decides if we use external or internal trigger. */
<> 149:156823d33999 241 #endif
<> 149:156823d33999 242 bool enableDoze; /*!< true: TPM counter is paused in doze mode;
<> 149:156823d33999 243 false: TPM counter continues in doze mode */
<> 149:156823d33999 244 bool enableDebugMode; /*!< true: TPM counter continues in debug mode;
<> 149:156823d33999 245 false: TPM counter is paused in debug mode */
<> 149:156823d33999 246 bool enableReloadOnTrigger; /*!< true: TPM counter is reloaded on trigger;
<> 149:156823d33999 247 false: TPM counter not reloaded */
<> 149:156823d33999 248 bool enableStopOnOverflow; /*!< true: TPM counter stops after overflow;
<> 149:156823d33999 249 false: TPM counter continues running after overflow */
<> 149:156823d33999 250 bool enableStartOnTrigger; /*!< true: TPM counter only starts when a trigger is detected;
<> 149:156823d33999 251 false: TPM counter starts immediately */
<> 149:156823d33999 252 #if defined(FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER) && FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER
<> 149:156823d33999 253 bool enablePauseOnTrigger; /*!< true: TPM counter will pause while trigger remains asserted;
<> 149:156823d33999 254 false: TPM counter continues running */
<> 149:156823d33999 255 #endif
<> 149:156823d33999 256 } tpm_config_t;
<> 149:156823d33999 257
<> 149:156823d33999 258 /*! @brief List of TPM interrupts */
<> 149:156823d33999 259 typedef enum _tpm_interrupt_enable
<> 149:156823d33999 260 {
<> 149:156823d33999 261 kTPM_Chnl0InterruptEnable = (1U << 0), /*!< Channel 0 interrupt.*/
<> 149:156823d33999 262 kTPM_Chnl1InterruptEnable = (1U << 1), /*!< Channel 1 interrupt.*/
<> 149:156823d33999 263 kTPM_Chnl2InterruptEnable = (1U << 2), /*!< Channel 2 interrupt.*/
<> 149:156823d33999 264 kTPM_Chnl3InterruptEnable = (1U << 3), /*!< Channel 3 interrupt.*/
<> 149:156823d33999 265 kTPM_Chnl4InterruptEnable = (1U << 4), /*!< Channel 4 interrupt.*/
<> 149:156823d33999 266 kTPM_Chnl5InterruptEnable = (1U << 5), /*!< Channel 5 interrupt.*/
<> 149:156823d33999 267 kTPM_Chnl6InterruptEnable = (1U << 6), /*!< Channel 6 interrupt.*/
<> 149:156823d33999 268 kTPM_Chnl7InterruptEnable = (1U << 7), /*!< Channel 7 interrupt.*/
<> 149:156823d33999 269 kTPM_TimeOverflowInterruptEnable = (1U << 8) /*!< Time overflow interrupt.*/
<> 149:156823d33999 270 } tpm_interrupt_enable_t;
<> 149:156823d33999 271
<> 149:156823d33999 272 /*! @brief List of TPM flags */
<> 149:156823d33999 273 typedef enum _tpm_status_flags
<> 149:156823d33999 274 {
<> 149:156823d33999 275 kTPM_Chnl0Flag = (1U << 0), /*!< Channel 0 flag */
<> 149:156823d33999 276 kTPM_Chnl1Flag = (1U << 1), /*!< Channel 1 flag */
<> 149:156823d33999 277 kTPM_Chnl2Flag = (1U << 2), /*!< Channel 2 flag */
<> 149:156823d33999 278 kTPM_Chnl3Flag = (1U << 3), /*!< Channel 3 flag */
<> 149:156823d33999 279 kTPM_Chnl4Flag = (1U << 4), /*!< Channel 4 flag */
<> 149:156823d33999 280 kTPM_Chnl5Flag = (1U << 5), /*!< Channel 5 flag */
<> 149:156823d33999 281 kTPM_Chnl6Flag = (1U << 6), /*!< Channel 6 flag */
<> 149:156823d33999 282 kTPM_Chnl7Flag = (1U << 7), /*!< Channel 7 flag */
<> 149:156823d33999 283 kTPM_TimeOverflowFlag = (1U << 8) /*!< Time overflow flag */
<> 149:156823d33999 284 } tpm_status_flags_t;
<> 149:156823d33999 285
<> 149:156823d33999 286 /*******************************************************************************
<> 149:156823d33999 287 * API
<> 149:156823d33999 288 ******************************************************************************/
<> 149:156823d33999 289
<> 149:156823d33999 290 #if defined(__cplusplus)
<> 149:156823d33999 291 extern "C" {
<> 149:156823d33999 292 #endif
<> 149:156823d33999 293
<> 149:156823d33999 294 /*!
<> 149:156823d33999 295 * @name Initialization and deinitialization
<> 149:156823d33999 296 * @{
<> 149:156823d33999 297 */
<> 149:156823d33999 298
<> 149:156823d33999 299 /*!
<> 149:156823d33999 300 * @brief Ungates the TPM clock and configures the peripheral for basic operation.
<> 149:156823d33999 301 *
<> 149:156823d33999 302 * @note This API should be called at the beginning of the application using the TPM driver.
<> 149:156823d33999 303 *
<> 149:156823d33999 304 * @param base TPM peripheral base address
<> 149:156823d33999 305 * @param config Pointer to user's TPM config structure.
<> 149:156823d33999 306 */
<> 149:156823d33999 307 void TPM_Init(TPM_Type *base, const tpm_config_t *config);
<> 149:156823d33999 308
<> 149:156823d33999 309 /*!
<> 149:156823d33999 310 * @brief Stops the counter and gates the TPM clock
<> 149:156823d33999 311 *
<> 149:156823d33999 312 * @param base TPM peripheral base address
<> 149:156823d33999 313 */
<> 149:156823d33999 314 void TPM_Deinit(TPM_Type *base);
<> 149:156823d33999 315
<> 149:156823d33999 316 /*!
<> 149:156823d33999 317 * @brief Fill in the TPM config struct with the default settings
<> 149:156823d33999 318 *
<> 149:156823d33999 319 * The default values are:
<> 149:156823d33999 320 * @code
<> 149:156823d33999 321 * config->prescale = kTPM_Prescale_Divide_1;
<> 149:156823d33999 322 * config->useGlobalTimeBase = false;
<> 149:156823d33999 323 * config->dozeEnable = false;
<> 149:156823d33999 324 * config->dbgMode = false;
<> 149:156823d33999 325 * config->enableReloadOnTrigger = false;
<> 149:156823d33999 326 * config->enableStopOnOverflow = false;
<> 149:156823d33999 327 * config->enableStartOnTrigger = false;
<> 149:156823d33999 328 *#if FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER
<> 149:156823d33999 329 * config->enablePauseOnTrigger = false;
<> 149:156823d33999 330 *#endif
<> 149:156823d33999 331 * config->triggerSelect = kTPM_Trigger_Select_0;
<> 149:156823d33999 332 *#if FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION
<> 149:156823d33999 333 * config->triggerSource = kTPM_TriggerSource_External;
<> 149:156823d33999 334 *#endif
<> 149:156823d33999 335 * @endcode
<> 149:156823d33999 336 * @param config Pointer to user's TPM config structure.
<> 149:156823d33999 337 */
<> 149:156823d33999 338 void TPM_GetDefaultConfig(tpm_config_t *config);
<> 149:156823d33999 339
<> 149:156823d33999 340 /*! @}*/
<> 149:156823d33999 341
<> 149:156823d33999 342 /*!
<> 149:156823d33999 343 * @name Channel mode operations
<> 149:156823d33999 344 * @{
<> 149:156823d33999 345 */
<> 149:156823d33999 346
<> 149:156823d33999 347 /*!
<> 149:156823d33999 348 * @brief Configures the PWM signal parameters
<> 149:156823d33999 349 *
<> 149:156823d33999 350 * User calls this function to configure the PWM signals period, mode, dutycycle and edge. Use this
<> 149:156823d33999 351 * function to configure all the TPM channels that will be used to output a PWM signal
<> 149:156823d33999 352 *
<> 149:156823d33999 353 * @param base TPM peripheral base address
<> 149:156823d33999 354 * @param chnlParams Array of PWM channel parameters to configure the channel(s)
<> 149:156823d33999 355 * @param numOfChnls Number of channels to configure, this should be the size of the array passed in
<> 149:156823d33999 356 * @param mode PWM operation mode, options available in enumeration ::tpm_pwm_mode_t
<> 149:156823d33999 357 * @param pwmFreq_Hz PWM signal frequency in Hz
<> 149:156823d33999 358 * @param srcClock_Hz TPM counter clock in Hz
<> 149:156823d33999 359 *
<> 149:156823d33999 360 * @return kStatus_Success if the PWM setup was successful,
<> 149:156823d33999 361 * kStatus_Error on failure
<> 149:156823d33999 362 */
<> 149:156823d33999 363 status_t TPM_SetupPwm(TPM_Type *base,
<> 149:156823d33999 364 const tpm_chnl_pwm_signal_param_t *chnlParams,
<> 149:156823d33999 365 uint8_t numOfChnls,
<> 149:156823d33999 366 tpm_pwm_mode_t mode,
<> 149:156823d33999 367 uint32_t pwmFreq_Hz,
<> 149:156823d33999 368 uint32_t srcClock_Hz);
<> 149:156823d33999 369
<> 149:156823d33999 370 /*!
<> 149:156823d33999 371 * @brief Update the duty cycle of an active PWM signal
<> 149:156823d33999 372 *
<> 149:156823d33999 373 * @param base TPM peripheral base address
<> 149:156823d33999 374 * @param chnlNumber The channel number. In combined mode, this represents
<> 149:156823d33999 375 * the channel pair number
<> 149:156823d33999 376 * @param currentPwmMode The current PWM mode set during PWM setup
<> 149:156823d33999 377 * @param dutyCyclePercent New PWM pulse width, value should be between 0 to 100
<> 149:156823d33999 378 * 0=inactive signal(0% duty cycle)...
<> 149:156823d33999 379 * 100=active signal (100% duty cycle)
<> 149:156823d33999 380 */
<> 149:156823d33999 381 void TPM_UpdatePwmDutycycle(TPM_Type *base,
<> 149:156823d33999 382 tpm_chnl_t chnlNumber,
<> 149:156823d33999 383 tpm_pwm_mode_t currentPwmMode,
<> 149:156823d33999 384 uint8_t dutyCyclePercent);
<> 149:156823d33999 385
<> 149:156823d33999 386 /*!
<> 149:156823d33999 387 * @brief Update the edge level selection for a channel
<> 149:156823d33999 388 *
<> 149:156823d33999 389 * @param base TPM peripheral base address
<> 149:156823d33999 390 * @param chnlNumber The channel number
<> 149:156823d33999 391 * @param level The level to be set to the ELSnB:ELSnA field; valid values are 00, 01, 10, 11.
<> 149:156823d33999 392 * See the appropriate SoC reference manual for details about this field.
<> 149:156823d33999 393 */
<> 149:156823d33999 394 void TPM_UpdateChnlEdgeLevelSelect(TPM_Type *base, tpm_chnl_t chnlNumber, uint8_t level);
<> 149:156823d33999 395
<> 149:156823d33999 396 /*!
<> 149:156823d33999 397 * @brief Enables capturing an input signal on the channel using the function parameters.
<> 149:156823d33999 398 *
<> 149:156823d33999 399 * When the edge specified in the captureMode argument occurs on the channel, the TPM counter is captured into
<> 149:156823d33999 400 * the CnV register. The user has to read the CnV register separately to get this value.
<> 149:156823d33999 401 *
<> 149:156823d33999 402 * @param base TPM peripheral base address
<> 149:156823d33999 403 * @param chnlNumber The channel number
<> 149:156823d33999 404 * @param captureMode Specifies which edge to capture
<> 149:156823d33999 405 */
<> 149:156823d33999 406 void TPM_SetupInputCapture(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_input_capture_edge_t captureMode);
<> 149:156823d33999 407
<> 149:156823d33999 408 /*!
<> 149:156823d33999 409 * @brief Configures the TPM to generate timed pulses.
<> 149:156823d33999 410 *
<> 149:156823d33999 411 * When the TPM counter matches the value of compareVal argument (this is written into CnV reg), the channel
<> 149:156823d33999 412 * output is changed based on what is specified in the compareMode argument.
<> 149:156823d33999 413 *
<> 149:156823d33999 414 * @param base TPM peripheral base address
<> 149:156823d33999 415 * @param chnlNumber The channel number
<> 149:156823d33999 416 * @param compareMode Action to take on the channel output when the compare condition is met
<> 149:156823d33999 417 * @param compareValue Value to be programmed in the CnV register.
<> 149:156823d33999 418 */
<> 149:156823d33999 419 void TPM_SetupOutputCompare(TPM_Type *base,
<> 149:156823d33999 420 tpm_chnl_t chnlNumber,
<> 149:156823d33999 421 tpm_output_compare_mode_t compareMode,
<> 149:156823d33999 422 uint32_t compareValue);
<> 149:156823d33999 423
<> 149:156823d33999 424 #if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
<> 149:156823d33999 425 /*!
<> 149:156823d33999 426 * @brief Configures the dual edge capture mode of the TPM.
<> 149:156823d33999 427 *
<> 149:156823d33999 428 * This function allows to measure a pulse width of the signal on the input of channel of a
<> 149:156823d33999 429 * channel pair. The filter function is disabled if the filterVal argument passed is zero.
<> 149:156823d33999 430 *
<> 149:156823d33999 431 * @param base TPM peripheral base address
<> 149:156823d33999 432 * @param chnlPairNumber The TPM channel pair number; options are 0, 1, 2, 3
<> 149:156823d33999 433 * @param edgeParam Sets up the dual edge capture function
<> 149:156823d33999 434 * @param filterValue Filter value, specify 0 to disable filter.
<> 149:156823d33999 435 */
<> 149:156823d33999 436 void TPM_SetupDualEdgeCapture(TPM_Type *base,
<> 149:156823d33999 437 tpm_chnl_t chnlPairNumber,
<> 149:156823d33999 438 const tpm_dual_edge_capture_param_t *edgeParam,
<> 149:156823d33999 439 uint32_t filterValue);
<> 149:156823d33999 440 #endif
<> 149:156823d33999 441
<> 149:156823d33999 442 #if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
<> 149:156823d33999 443 /*!
<> 149:156823d33999 444 * @brief Configures the parameters and activates the quadrature decode mode.
<> 149:156823d33999 445 *
<> 149:156823d33999 446 * @param base TPM peripheral base address
<> 149:156823d33999 447 * @param phaseAParams Phase A configuration parameters
<> 149:156823d33999 448 * @param phaseBParams Phase B configuration parameters
<> 149:156823d33999 449 * @param quadMode Selects encoding mode used in quadrature decoder mode
<> 149:156823d33999 450 */
<> 149:156823d33999 451 void TPM_SetupQuadDecode(TPM_Type *base,
<> 149:156823d33999 452 const tpm_phase_params_t *phaseAParams,
<> 149:156823d33999 453 const tpm_phase_params_t *phaseBParams,
<> 149:156823d33999 454 tpm_quad_decode_mode_t quadMode);
<> 149:156823d33999 455 #endif
<> 149:156823d33999 456
<> 149:156823d33999 457 /*! @}*/
<> 149:156823d33999 458
<> 149:156823d33999 459 /*!
<> 149:156823d33999 460 * @name Interrupt Interface
<> 149:156823d33999 461 * @{
<> 149:156823d33999 462 */
<> 149:156823d33999 463
<> 149:156823d33999 464 /*!
<> 149:156823d33999 465 * @brief Enables the selected TPM interrupts.
<> 149:156823d33999 466 *
<> 149:156823d33999 467 * @param base TPM peripheral base address
<> 149:156823d33999 468 * @param mask The interrupts to enable. This is a logical OR of members of the
<> 149:156823d33999 469 * enumeration ::tpm_interrupt_enable_t
<> 149:156823d33999 470 */
<> 149:156823d33999 471 void TPM_EnableInterrupts(TPM_Type *base, uint32_t mask);
<> 149:156823d33999 472
<> 149:156823d33999 473 /*!
<> 149:156823d33999 474 * @brief Disables the selected TPM interrupts.
<> 149:156823d33999 475 *
<> 149:156823d33999 476 * @param base TPM peripheral base address
<> 149:156823d33999 477 * @param mask The interrupts to disable. This is a logical OR of members of the
<> 149:156823d33999 478 * enumeration ::tpm_interrupt_enable_t
<> 149:156823d33999 479 */
<> 149:156823d33999 480 void TPM_DisableInterrupts(TPM_Type *base, uint32_t mask);
<> 149:156823d33999 481
<> 149:156823d33999 482 /*!
<> 149:156823d33999 483 * @brief Gets the enabled TPM interrupts.
<> 149:156823d33999 484 *
<> 149:156823d33999 485 * @param base TPM peripheral base address
<> 149:156823d33999 486 *
<> 149:156823d33999 487 * @return The enabled interrupts. This is the logical OR of members of the
<> 149:156823d33999 488 * enumeration ::tpm_interrupt_enable_t
<> 149:156823d33999 489 */
<> 149:156823d33999 490 uint32_t TPM_GetEnabledInterrupts(TPM_Type *base);
<> 149:156823d33999 491
<> 149:156823d33999 492 /*! @}*/
<> 149:156823d33999 493
<> 149:156823d33999 494 /*!
<> 149:156823d33999 495 * @name Status Interface
<> 149:156823d33999 496 * @{
<> 149:156823d33999 497 */
<> 149:156823d33999 498
<> 149:156823d33999 499 /*!
<> 149:156823d33999 500 * @brief Gets the TPM status flags
<> 149:156823d33999 501 *
<> 149:156823d33999 502 * @param base TPM peripheral base address
<> 149:156823d33999 503 *
<> 149:156823d33999 504 * @return The status flags. This is the logical OR of members of the
<> 149:156823d33999 505 * enumeration ::tpm_status_flags_t
<> 149:156823d33999 506 */
<> 149:156823d33999 507 static inline uint32_t TPM_GetStatusFlags(TPM_Type *base)
<> 149:156823d33999 508 {
<> 149:156823d33999 509 return base->STATUS;
<> 149:156823d33999 510 }
<> 149:156823d33999 511
<> 149:156823d33999 512 /*!
<> 149:156823d33999 513 * @brief Clears the TPM status flags
<> 149:156823d33999 514 *
<> 149:156823d33999 515 * @param base TPM peripheral base address
<> 149:156823d33999 516 * @param mask The status flags to clear. This is a logical OR of members of the
<> 149:156823d33999 517 * enumeration ::tpm_status_flags_t
<> 149:156823d33999 518 */
<> 149:156823d33999 519 static inline void TPM_ClearStatusFlags(TPM_Type *base, uint32_t mask)
<> 149:156823d33999 520 {
<> 149:156823d33999 521 /* Clear the status flags */
<> 149:156823d33999 522 base->STATUS = mask;
<> 149:156823d33999 523 }
<> 149:156823d33999 524
<> 149:156823d33999 525 /*! @}*/
<> 149:156823d33999 526
<> 149:156823d33999 527 /*!
<> 149:156823d33999 528 * @name Timer Start and Stop
<> 149:156823d33999 529 * @{
<> 149:156823d33999 530 */
<> 149:156823d33999 531
<> 149:156823d33999 532 /*!
<> 149:156823d33999 533 * @brief Starts the TPM counter.
<> 149:156823d33999 534 *
<> 149:156823d33999 535 *
<> 149:156823d33999 536 * @param base TPM peripheral base address
<> 149:156823d33999 537 * @param clockSource TPM clock source; once clock source is set the counter will start running
<> 149:156823d33999 538 */
<> 149:156823d33999 539 static inline void TPM_StartTimer(TPM_Type *base, tpm_clock_source_t clockSource)
<> 149:156823d33999 540 {
<> 149:156823d33999 541 uint32_t reg = base->SC;
<> 149:156823d33999 542
<> 149:156823d33999 543 reg &= ~(TPM_SC_CMOD_MASK);
<> 149:156823d33999 544 reg |= TPM_SC_CMOD(clockSource);
<> 149:156823d33999 545 base->SC = reg;
<> 149:156823d33999 546 }
<> 149:156823d33999 547
<> 149:156823d33999 548 /*!
<> 149:156823d33999 549 * @brief Stops the TPM counter.
<> 149:156823d33999 550 *
<> 149:156823d33999 551 * @param base TPM peripheral base address
<> 149:156823d33999 552 */
<> 149:156823d33999 553 static inline void TPM_StopTimer(TPM_Type *base)
<> 149:156823d33999 554 {
<> 149:156823d33999 555 /* Set clock source to none to disable counter */
<> 149:156823d33999 556 base->SC &= ~(TPM_SC_CMOD_MASK);
<> 149:156823d33999 557
<> 149:156823d33999 558 /* Wait till this reads as zero acknowledging the counter is disabled */
<> 149:156823d33999 559 while (base->SC & TPM_SC_CMOD_MASK)
<> 149:156823d33999 560 {
<> 149:156823d33999 561 }
<> 149:156823d33999 562 }
<> 149:156823d33999 563
<> 149:156823d33999 564 /*! @}*/
<> 149:156823d33999 565
<> 149:156823d33999 566 #if defined(FSL_FEATURE_TPM_HAS_GLOBAL) && FSL_FEATURE_TPM_HAS_GLOBAL
<> 149:156823d33999 567 /*!
<> 149:156823d33999 568 * @brief Performs a software reset on the TPM module.
<> 149:156823d33999 569 *
<> 149:156823d33999 570 * Reset all internal logic and registers, except the Global Register. Remains set until cleared by software..
<> 149:156823d33999 571 *
<> 149:156823d33999 572 * @note TPM software reset is available on certain SoC's only
<> 149:156823d33999 573 *
<> 149:156823d33999 574 * @param base TPM peripheral base address
<> 149:156823d33999 575 */
<> 149:156823d33999 576 static inline void TPM_Reset(TPM_Type *base)
<> 149:156823d33999 577 {
<> 149:156823d33999 578 base->GLOBAL |= TPM_GLOBAL_RST_MASK;
<> 149:156823d33999 579 base->GLOBAL &= ~TPM_GLOBAL_RST_MASK;
<> 149:156823d33999 580 }
<> 149:156823d33999 581 #endif
<> 149:156823d33999 582
<> 149:156823d33999 583 #if defined(__cplusplus)
<> 149:156823d33999 584 }
<> 149:156823d33999 585 #endif
<> 149:156823d33999 586
<> 149:156823d33999 587 /*! @}*/
<> 149:156823d33999 588
<> 149:156823d33999 589 #endif /* _FSL_TPM_H_ */