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targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_lpuart.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /*
<> 149:156823d33999 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 149:156823d33999 3 * All rights reserved.
<> 149:156823d33999 4 *
<> 149:156823d33999 5 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 6 * are permitted provided that the following conditions are met:
<> 149:156823d33999 7 *
<> 149:156823d33999 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 149:156823d33999 9 * of conditions and the following disclaimer.
<> 149:156823d33999 10 *
<> 149:156823d33999 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 149:156823d33999 12 * list of conditions and the following disclaimer in the documentation and/or
<> 149:156823d33999 13 * other materials provided with the distribution.
<> 149:156823d33999 14 *
<> 149:156823d33999 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 149:156823d33999 16 * contributors may be used to endorse or promote products derived from this
<> 149:156823d33999 17 * software without specific prior written permission.
<> 149:156823d33999 18 *
<> 149:156823d33999 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 149:156823d33999 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 149:156823d33999 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 149:156823d33999 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 149:156823d33999 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 149:156823d33999 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 149:156823d33999 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 149:156823d33999 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 149:156823d33999 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 29 */
<> 149:156823d33999 30
<> 149:156823d33999 31 #include "fsl_lpuart.h"
<> 149:156823d33999 32
<> 149:156823d33999 33 /*******************************************************************************
<> 149:156823d33999 34 * Definitions
<> 149:156823d33999 35 ******************************************************************************/
<> 149:156823d33999 36 /* LPUART transfer state. */
<> 149:156823d33999 37 enum _lpuart_transfer_states
<> 149:156823d33999 38 {
<> 149:156823d33999 39 kLPUART_TxIdle, /*!< TX idle. */
<> 149:156823d33999 40 kLPUART_TxBusy, /*!< TX busy. */
<> 149:156823d33999 41 kLPUART_RxIdle, /*!< RX idle. */
<> 149:156823d33999 42 kLPUART_RxBusy /*!< RX busy. */
<> 149:156823d33999 43 };
<> 149:156823d33999 44
<> 149:156823d33999 45 /* Typedef for interrupt handler. */
<> 149:156823d33999 46 typedef void (*lpuart_isr_t)(LPUART_Type *base, lpuart_handle_t *handle);
<> 149:156823d33999 47
<> 149:156823d33999 48 /*******************************************************************************
<> 149:156823d33999 49 * Prototypes
<> 149:156823d33999 50 ******************************************************************************/
<> 149:156823d33999 51 /*!
<> 149:156823d33999 52 * @brief Get the LPUART instance from peripheral base address.
<> 149:156823d33999 53 *
<> 149:156823d33999 54 * @param base LPUART peripheral base address.
<> 149:156823d33999 55 * @return LPUART instance.
<> 149:156823d33999 56 */
<> 149:156823d33999 57 uint32_t LPUART_GetInstance(LPUART_Type *base);
<> 149:156823d33999 58
<> 149:156823d33999 59 /*!
<> 149:156823d33999 60 * @brief Get the length of received data in RX ring buffer.
<> 149:156823d33999 61 *
<> 149:156823d33999 62 * @userData handle LPUART handle pointer.
<> 149:156823d33999 63 * @return Length of received data in RX ring buffer.
<> 149:156823d33999 64 */
<> 149:156823d33999 65 static size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle);
<> 149:156823d33999 66
<> 149:156823d33999 67 /*!
<> 149:156823d33999 68 * @brief Check whether the RX ring buffer is full.
<> 149:156823d33999 69 *
<> 149:156823d33999 70 * @userData handle LPUART handle pointer.
<> 149:156823d33999 71 * @retval true RX ring buffer is full.
<> 149:156823d33999 72 * @retval false RX ring buffer is not full.
<> 149:156823d33999 73 */
<> 149:156823d33999 74 static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle);
<> 149:156823d33999 75
<> 149:156823d33999 76 /*!
<> 149:156823d33999 77 * @brief Write to TX register using non-blocking method.
<> 149:156823d33999 78 *
<> 149:156823d33999 79 * This function writes data to the TX register directly, upper layer must make
<> 149:156823d33999 80 * sure the TX register is empty or TX FIFO has empty room before calling this function.
<> 149:156823d33999 81 *
<> 149:156823d33999 82 * @note This function does not check whether all the data has been sent out to bus,
<> 149:156823d33999 83 * so before disable TX, check kLPUART_TransmissionCompleteFlag to ensure the TX is
<> 149:156823d33999 84 * finished.
<> 149:156823d33999 85 *
<> 149:156823d33999 86 * @param base LPUART peripheral base address.
<> 149:156823d33999 87 * @param data Start addresss of the data to write.
<> 149:156823d33999 88 * @param length Size of the buffer to be sent.
<> 149:156823d33999 89 */
<> 149:156823d33999 90 static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length);
<> 149:156823d33999 91
<> 149:156823d33999 92 /*!
<> 149:156823d33999 93 * @brief Read RX register using non-blocking method.
<> 149:156823d33999 94 *
<> 149:156823d33999 95 * This function reads data from the TX register directly, upper layer must make
<> 149:156823d33999 96 * sure the RX register is full or TX FIFO has data before calling this function.
<> 149:156823d33999 97 *
<> 149:156823d33999 98 * @param base LPUART peripheral base address.
<> 149:156823d33999 99 * @param data Start addresss of the buffer to store the received data.
<> 149:156823d33999 100 * @param length Size of the buffer.
<> 149:156823d33999 101 */
<> 149:156823d33999 102 static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length);
<> 149:156823d33999 103
<> 149:156823d33999 104 /*******************************************************************************
<> 149:156823d33999 105 * Variables
<> 149:156823d33999 106 ******************************************************************************/
<> 149:156823d33999 107 /* Array of LPUART handle. */
<> 149:156823d33999 108 static lpuart_handle_t *s_lpuartHandle[FSL_FEATURE_SOC_LPUART_COUNT];
<> 149:156823d33999 109 /* Array of LPUART peripheral base address. */
<> 149:156823d33999 110 static LPUART_Type *const s_lpuartBases[] = LPUART_BASE_PTRS;
<> 149:156823d33999 111 /* Array of LPUART IRQ number. */
<> 149:156823d33999 112 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
<> 149:156823d33999 113 static const IRQn_Type s_lpuartRxIRQ[] = LPUART_RX_IRQS;
<> 149:156823d33999 114 static const IRQn_Type s_lpuartTxIRQ[] = LPUART_TX_IRQS;
<> 149:156823d33999 115 #else
<> 149:156823d33999 116 static const IRQn_Type s_lpuartIRQ[] = LPUART_RX_TX_IRQS;
<> 149:156823d33999 117 #endif
<> 149:156823d33999 118 /* Array of LPUART clock name. */
<> 149:156823d33999 119 static const clock_ip_name_t s_lpuartClock[] = LPUART_CLOCKS;
<> 149:156823d33999 120 /* LPUART ISR for transactional APIs. */
<> 149:156823d33999 121 static lpuart_isr_t s_lpuartIsr;
<> 149:156823d33999 122
<> 149:156823d33999 123 /*******************************************************************************
<> 149:156823d33999 124 * Code
<> 149:156823d33999 125 ******************************************************************************/
<> 149:156823d33999 126 uint32_t LPUART_GetInstance(LPUART_Type *base)
<> 149:156823d33999 127 {
<> 149:156823d33999 128 uint32_t instance;
<> 149:156823d33999 129
<> 149:156823d33999 130 /* Find the instance index from base address mappings. */
<> 149:156823d33999 131 for (instance = 0; instance < FSL_FEATURE_SOC_LPUART_COUNT; instance++)
<> 149:156823d33999 132 {
<> 149:156823d33999 133 if (s_lpuartBases[instance] == base)
<> 149:156823d33999 134 {
<> 149:156823d33999 135 break;
<> 149:156823d33999 136 }
<> 149:156823d33999 137 }
<> 149:156823d33999 138
<> 149:156823d33999 139 assert(instance < FSL_FEATURE_SOC_LPUART_COUNT);
<> 149:156823d33999 140
<> 149:156823d33999 141 return instance;
<> 149:156823d33999 142 }
<> 149:156823d33999 143
<> 149:156823d33999 144 static size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle)
<> 149:156823d33999 145 {
<> 149:156823d33999 146 assert(handle);
<> 149:156823d33999 147
<> 149:156823d33999 148 size_t size;
<> 149:156823d33999 149
<> 149:156823d33999 150 if (handle->rxRingBufferTail > handle->rxRingBufferHead)
<> 149:156823d33999 151 {
<> 149:156823d33999 152 size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail);
<> 149:156823d33999 153 }
<> 149:156823d33999 154 else
<> 149:156823d33999 155 {
<> 149:156823d33999 156 size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail);
<> 149:156823d33999 157 }
<> 149:156823d33999 158
<> 149:156823d33999 159 return size;
<> 149:156823d33999 160 }
<> 149:156823d33999 161
<> 149:156823d33999 162 static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle)
<> 149:156823d33999 163 {
<> 149:156823d33999 164 assert(handle);
<> 149:156823d33999 165
<> 149:156823d33999 166 bool full;
<> 149:156823d33999 167
<> 149:156823d33999 168 if (LPUART_TransferGetRxRingBufferLength(base, handle) == (handle->rxRingBufferSize - 1U))
<> 149:156823d33999 169 {
<> 149:156823d33999 170 full = true;
<> 149:156823d33999 171 }
<> 149:156823d33999 172 else
<> 149:156823d33999 173 {
<> 149:156823d33999 174 full = false;
<> 149:156823d33999 175 }
<> 149:156823d33999 176 return full;
<> 149:156823d33999 177 }
<> 149:156823d33999 178
<> 149:156823d33999 179 static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length)
<> 149:156823d33999 180 {
<> 149:156823d33999 181 assert(data);
<> 149:156823d33999 182
<> 149:156823d33999 183 size_t i;
<> 149:156823d33999 184
<> 149:156823d33999 185 /* The Non Blocking write data API assume user have ensured there is enough space in
<> 149:156823d33999 186 peripheral to write. */
<> 149:156823d33999 187 for (i = 0; i < length; i++)
<> 149:156823d33999 188 {
<> 149:156823d33999 189 base->DATA = data[i];
<> 149:156823d33999 190 }
<> 149:156823d33999 191 }
<> 149:156823d33999 192
<> 149:156823d33999 193 static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length)
<> 149:156823d33999 194 {
<> 149:156823d33999 195 assert(data);
<> 149:156823d33999 196
<> 149:156823d33999 197 size_t i;
<> 149:156823d33999 198 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
<> 149:156823d33999 199 uint32_t ctrl = base->CTRL;
<> 149:156823d33999 200 bool isSevenDataBits =
<> 149:156823d33999 201 ((ctrl & LPUART_CTRL_M7_MASK) ||
<> 149:156823d33999 202 ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
<> 149:156823d33999 203 #endif
<> 149:156823d33999 204
<> 149:156823d33999 205 /* The Non Blocking read data API assume user have ensured there is enough space in
<> 149:156823d33999 206 peripheral to write. */
<> 149:156823d33999 207 for (i = 0; i < length; i++)
<> 149:156823d33999 208 {
<> 149:156823d33999 209 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
<> 149:156823d33999 210 if (isSevenDataBits)
<> 149:156823d33999 211 {
<> 149:156823d33999 212 data[i] = (base->DATA & 0x7F);
<> 149:156823d33999 213 }
<> 149:156823d33999 214 else
<> 149:156823d33999 215 {
<> 149:156823d33999 216 data[i] = base->DATA;
<> 149:156823d33999 217 }
<> 149:156823d33999 218 #else
<> 149:156823d33999 219 data[i] = base->DATA;
<> 149:156823d33999 220 #endif
<> 149:156823d33999 221 }
<> 149:156823d33999 222 }
<> 149:156823d33999 223
<> 149:156823d33999 224 status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz)
<> 149:156823d33999 225 {
<> 149:156823d33999 226 assert(config);
<> 149:156823d33999 227 assert(config->baudRate_Bps);
<> 149:156823d33999 228 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 149:156823d33999 229 assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->txFifoWatermark);
<> 149:156823d33999 230 assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->rxFifoWatermark);
<> 149:156823d33999 231 #endif
<> 149:156823d33999 232
<> 149:156823d33999 233 uint32_t temp;
<> 149:156823d33999 234 uint16_t sbr, sbrTemp;
<> 149:156823d33999 235 uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff;
<> 149:156823d33999 236
<> 149:156823d33999 237 /* This LPUART instantiation uses a slightly different baud rate calculation
<> 149:156823d33999 238 * The idea is to use the best OSR (over-sampling rate) possible
<> 149:156823d33999 239 * Note, OSR is typically hard-set to 16 in other LPUART instantiations
<> 149:156823d33999 240 * loop to find the best OSR value possible, one that generates minimum baudDiff
<> 149:156823d33999 241 * iterate through the rest of the supported values of OSR */
<> 149:156823d33999 242
<> 149:156823d33999 243 baudDiff = config->baudRate_Bps;
<> 149:156823d33999 244 osr = 0;
<> 149:156823d33999 245 sbr = 0;
<> 149:156823d33999 246 for (osrTemp = 4; osrTemp <= 32; osrTemp++)
<> 149:156823d33999 247 {
<> 149:156823d33999 248 /* calculate the temporary sbr value */
<> 149:156823d33999 249 sbrTemp = (srcClock_Hz / (config->baudRate_Bps * osrTemp));
<> 149:156823d33999 250 /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/
<> 149:156823d33999 251 if (sbrTemp == 0)
<> 149:156823d33999 252 {
<> 149:156823d33999 253 sbrTemp = 1;
<> 149:156823d33999 254 }
<> 149:156823d33999 255 /* Calculate the baud rate based on the temporary OSR and SBR values */
<> 149:156823d33999 256 calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp));
<> 149:156823d33999 257
<> 149:156823d33999 258 tempDiff = calculatedBaud - config->baudRate_Bps;
<> 149:156823d33999 259
<> 149:156823d33999 260 /* Select the better value between srb and (sbr + 1) */
<> 149:156823d33999 261 if (tempDiff > (config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)))))
<> 149:156823d33999 262 {
<> 149:156823d33999 263 tempDiff = config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)));
<> 149:156823d33999 264 sbrTemp++;
<> 149:156823d33999 265 }
<> 149:156823d33999 266
<> 149:156823d33999 267 if (tempDiff <= baudDiff)
<> 149:156823d33999 268 {
<> 149:156823d33999 269 baudDiff = tempDiff;
<> 149:156823d33999 270 osr = osrTemp; /* update and store the best OSR value calculated */
<> 149:156823d33999 271 sbr = sbrTemp; /* update store the best SBR value calculated */
<> 149:156823d33999 272 }
<> 149:156823d33999 273 }
<> 149:156823d33999 274
<> 149:156823d33999 275 /* Check to see if actual baud rate is within 3% of desired baud rate
<> 149:156823d33999 276 * based on the best calculate OSR value */
<> 149:156823d33999 277 if (baudDiff > ((config->baudRate_Bps / 100) * 3))
<> 149:156823d33999 278 {
<> 149:156823d33999 279 /* Unacceptable baud rate difference of more than 3%*/
<> 149:156823d33999 280 return kStatus_LPUART_BaudrateNotSupport;
<> 149:156823d33999 281 }
<> 149:156823d33999 282
<> 149:156823d33999 283 /* Enable lpuart clock */
<> 149:156823d33999 284 CLOCK_EnableClock(s_lpuartClock[LPUART_GetInstance(base)]);
<> 149:156823d33999 285
<> 149:156823d33999 286 /* Disable LPUART TX RX before setting. */
<> 149:156823d33999 287 base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
<> 149:156823d33999 288
<> 149:156823d33999 289 temp = base->BAUD;
<> 149:156823d33999 290
<> 149:156823d33999 291 /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling.
<> 149:156823d33999 292 * If so, then "BOTHEDGE" sampling must be turned on */
<> 149:156823d33999 293 if ((osr > 3) && (osr < 8))
<> 149:156823d33999 294 {
<> 149:156823d33999 295 temp |= LPUART_BAUD_BOTHEDGE_MASK;
<> 149:156823d33999 296 }
<> 149:156823d33999 297
<> 149:156823d33999 298 /* program the osr value (bit value is one less than actual value) */
<> 149:156823d33999 299 temp &= ~LPUART_BAUD_OSR_MASK;
<> 149:156823d33999 300 temp |= LPUART_BAUD_OSR(osr - 1);
<> 149:156823d33999 301
<> 149:156823d33999 302 /* write the sbr value to the BAUD registers */
<> 149:156823d33999 303 temp &= ~LPUART_BAUD_SBR_MASK;
<> 149:156823d33999 304 base->BAUD = temp | LPUART_BAUD_SBR(sbr);
<> 149:156823d33999 305
<> 149:156823d33999 306 /* Set bit count and parity mode. */
<> 149:156823d33999 307 base->BAUD &= ~LPUART_BAUD_M10_MASK;
<> 149:156823d33999 308
<> 149:156823d33999 309 temp = base->CTRL & ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK);
<> 149:156823d33999 310
<> 149:156823d33999 311 temp |= (uint8_t)config->parityMode;
<> 149:156823d33999 312
<> 149:156823d33999 313 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
<> 149:156823d33999 314 if (kLPUART_SevenDataBits == config->dataBitsCount)
<> 149:156823d33999 315 {
<> 149:156823d33999 316 if (kLPUART_ParityDisabled != config->parityMode)
<> 149:156823d33999 317 {
<> 149:156823d33999 318 temp &= ~LPUART_CTRL_M7_MASK; /* Seven data bits and one parity bit */
<> 149:156823d33999 319 }
<> 149:156823d33999 320 else
<> 149:156823d33999 321 {
<> 149:156823d33999 322 temp |= LPUART_CTRL_M7_MASK;
<> 149:156823d33999 323 }
<> 149:156823d33999 324 }
<> 149:156823d33999 325 else
<> 149:156823d33999 326 #endif
<> 149:156823d33999 327 {
<> 149:156823d33999 328 if (kLPUART_ParityDisabled != config->parityMode)
<> 149:156823d33999 329 {
<> 149:156823d33999 330 temp |= LPUART_CTRL_M_MASK; /* Eight data bits and one parity bit */
<> 149:156823d33999 331 }
<> 149:156823d33999 332 }
<> 149:156823d33999 333
<> 149:156823d33999 334 base->CTRL = temp;
<> 149:156823d33999 335
<> 149:156823d33999 336 #if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
<> 149:156823d33999 337 /* set stop bit per char */
<> 149:156823d33999 338 temp = base->BAUD & ~LPUART_BAUD_SBNS_MASK;
<> 149:156823d33999 339 base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)config->stopBitCount);
<> 149:156823d33999 340 #endif
<> 149:156823d33999 341
<> 149:156823d33999 342 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 149:156823d33999 343 /* Set tx/rx WATER watermark */
<> 149:156823d33999 344 base->WATER = (((uint32_t)(config->rxFifoWatermark) << 16) | config->txFifoWatermark);
<> 149:156823d33999 345
<> 149:156823d33999 346 /* Enable tx/rx FIFO */
<> 149:156823d33999 347 base->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK);
<> 149:156823d33999 348
<> 149:156823d33999 349 /* Flush FIFO */
<> 149:156823d33999 350 base->FIFO |= (LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK);
<> 149:156823d33999 351 #endif
<> 149:156823d33999 352
<> 149:156823d33999 353 /* Clear all status flags */
<> 149:156823d33999 354 temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
<> 149:156823d33999 355 LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
<> 149:156823d33999 356
<> 149:156823d33999 357 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
<> 149:156823d33999 358 temp |= LPUART_STAT_LBKDIF_MASK;
<> 149:156823d33999 359 #endif
<> 149:156823d33999 360
<> 149:156823d33999 361 #if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
<> 149:156823d33999 362 temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK);
<> 149:156823d33999 363 #endif
<> 149:156823d33999 364
<> 149:156823d33999 365 /* Set data bits order. */
<> 149:156823d33999 366 if (config->isMsb)
<> 149:156823d33999 367 {
<> 149:156823d33999 368 temp |= LPUART_STAT_MSBF_MASK;
<> 149:156823d33999 369 }
<> 149:156823d33999 370 else
<> 149:156823d33999 371 {
<> 149:156823d33999 372 temp &= ~LPUART_STAT_MSBF_MASK;
<> 149:156823d33999 373 }
<> 149:156823d33999 374
<> 149:156823d33999 375 base->STAT |= temp;
<> 149:156823d33999 376
<> 149:156823d33999 377 /* Enable TX/RX base on configure structure. */
<> 149:156823d33999 378 temp = base->CTRL;
<> 149:156823d33999 379 if (config->enableTx)
<> 149:156823d33999 380 {
<> 149:156823d33999 381 temp |= LPUART_CTRL_TE_MASK;
<> 149:156823d33999 382 }
<> 149:156823d33999 383
<> 149:156823d33999 384 if (config->enableRx)
<> 149:156823d33999 385 {
<> 149:156823d33999 386 temp |= LPUART_CTRL_RE_MASK;
<> 149:156823d33999 387 }
<> 149:156823d33999 388
<> 149:156823d33999 389 base->CTRL = temp;
<> 149:156823d33999 390
<> 149:156823d33999 391 return kStatus_Success;
<> 149:156823d33999 392 }
<> 149:156823d33999 393 void LPUART_Deinit(LPUART_Type *base)
<> 149:156823d33999 394 {
<> 149:156823d33999 395 uint32_t temp;
<> 149:156823d33999 396
<> 149:156823d33999 397 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 149:156823d33999 398 /* Wait tx FIFO send out*/
<> 149:156823d33999 399 while (0 != ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXWATER_SHIFT))
<> 149:156823d33999 400 {
<> 149:156823d33999 401 }
<> 149:156823d33999 402 #endif
<> 149:156823d33999 403 /* Wait last char shoft out */
<> 149:156823d33999 404 while (0 == (base->STAT & LPUART_STAT_TC_MASK))
<> 149:156823d33999 405 {
<> 149:156823d33999 406 }
<> 149:156823d33999 407
<> 149:156823d33999 408 /* Clear all status flags */
<> 149:156823d33999 409 temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
<> 149:156823d33999 410 LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
<> 149:156823d33999 411
<> 149:156823d33999 412 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
<> 149:156823d33999 413 temp |= LPUART_STAT_LBKDIF_MASK;
<> 149:156823d33999 414 #endif
<> 149:156823d33999 415
<> 149:156823d33999 416 #if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
<> 149:156823d33999 417 temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK);
<> 149:156823d33999 418 #endif
<> 149:156823d33999 419
<> 149:156823d33999 420 base->STAT |= temp;
<> 149:156823d33999 421
<> 149:156823d33999 422 /* Disable the module. */
<> 149:156823d33999 423 base->CTRL = 0;
<> 149:156823d33999 424
<> 149:156823d33999 425 /* Disable lpuart clock */
<> 149:156823d33999 426 CLOCK_DisableClock(s_lpuartClock[LPUART_GetInstance(base)]);
<> 149:156823d33999 427 }
<> 149:156823d33999 428
<> 149:156823d33999 429 void LPUART_GetDefaultConfig(lpuart_config_t *config)
<> 149:156823d33999 430 {
<> 149:156823d33999 431 assert(config);
<> 149:156823d33999 432
<> 149:156823d33999 433 config->baudRate_Bps = 115200U;
<> 149:156823d33999 434 config->parityMode = kLPUART_ParityDisabled;
<> 149:156823d33999 435 config->dataBitsCount = kLPUART_EightDataBits;
<> 149:156823d33999 436 config->isMsb = false;
<> 149:156823d33999 437 #if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
<> 149:156823d33999 438 config->stopBitCount = kLPUART_OneStopBit;
<> 149:156823d33999 439 #endif
<> 149:156823d33999 440 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 149:156823d33999 441 config->txFifoWatermark = 0;
<> 149:156823d33999 442 config->rxFifoWatermark = 0;
<> 149:156823d33999 443 #endif
<> 149:156823d33999 444 config->enableTx = false;
<> 149:156823d33999 445 config->enableRx = false;
<> 149:156823d33999 446 }
<> 149:156823d33999 447
<> 149:156823d33999 448 status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
<> 149:156823d33999 449 {
<> 149:156823d33999 450 assert(baudRate_Bps);
<> 149:156823d33999 451
<> 149:156823d33999 452 uint32_t temp, oldCtrl;
<> 149:156823d33999 453 uint16_t sbr, sbrTemp;
<> 149:156823d33999 454 uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff;
<> 149:156823d33999 455
<> 149:156823d33999 456 /* This LPUART instantiation uses a slightly different baud rate calculation
<> 149:156823d33999 457 * The idea is to use the best OSR (over-sampling rate) possible
<> 149:156823d33999 458 * Note, OSR is typically hard-set to 16 in other LPUART instantiations
<> 149:156823d33999 459 * loop to find the best OSR value possible, one that generates minimum baudDiff
<> 149:156823d33999 460 * iterate through the rest of the supported values of OSR */
<> 149:156823d33999 461
<> 149:156823d33999 462 baudDiff = baudRate_Bps;
<> 149:156823d33999 463 osr = 0;
<> 149:156823d33999 464 sbr = 0;
<> 149:156823d33999 465 for (osrTemp = 4; osrTemp <= 32; osrTemp++)
<> 149:156823d33999 466 {
<> 149:156823d33999 467 /* calculate the temporary sbr value */
<> 149:156823d33999 468 sbrTemp = (srcClock_Hz / (baudRate_Bps * osrTemp));
<> 149:156823d33999 469 /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/
<> 149:156823d33999 470 if (sbrTemp == 0)
<> 149:156823d33999 471 {
<> 149:156823d33999 472 sbrTemp = 1;
<> 149:156823d33999 473 }
<> 149:156823d33999 474 /* Calculate the baud rate based on the temporary OSR and SBR values */
<> 149:156823d33999 475 calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp));
<> 149:156823d33999 476
<> 149:156823d33999 477 tempDiff = calculatedBaud - baudRate_Bps;
<> 149:156823d33999 478
<> 149:156823d33999 479 /* Select the better value between srb and (sbr + 1) */
<> 149:156823d33999 480 if (tempDiff > (baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)))))
<> 149:156823d33999 481 {
<> 149:156823d33999 482 tempDiff = baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)));
<> 149:156823d33999 483 sbrTemp++;
<> 149:156823d33999 484 }
<> 149:156823d33999 485
<> 149:156823d33999 486 if (tempDiff <= baudDiff)
<> 149:156823d33999 487 {
<> 149:156823d33999 488 baudDiff = tempDiff;
<> 149:156823d33999 489 osr = osrTemp; /* update and store the best OSR value calculated */
<> 149:156823d33999 490 sbr = sbrTemp; /* update store the best SBR value calculated */
<> 149:156823d33999 491 }
<> 149:156823d33999 492 }
<> 149:156823d33999 493
<> 149:156823d33999 494 /* Check to see if actual baud rate is within 3% of desired baud rate
<> 149:156823d33999 495 * based on the best calculate OSR value */
<> 149:156823d33999 496 if (baudDiff < ((baudRate_Bps / 100) * 3))
<> 149:156823d33999 497 {
<> 149:156823d33999 498 /* Store CTRL before disable Tx and Rx */
<> 149:156823d33999 499 oldCtrl = base->CTRL;
<> 149:156823d33999 500
<> 149:156823d33999 501 /* Disable LPUART TX RX before setting. */
<> 149:156823d33999 502 base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
<> 149:156823d33999 503
<> 149:156823d33999 504 temp = base->BAUD;
<> 149:156823d33999 505
<> 149:156823d33999 506 /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling.
<> 149:156823d33999 507 * If so, then "BOTHEDGE" sampling must be turned on */
<> 149:156823d33999 508 if ((osr > 3) && (osr < 8))
<> 149:156823d33999 509 {
<> 149:156823d33999 510 temp |= LPUART_BAUD_BOTHEDGE_MASK;
<> 149:156823d33999 511 }
<> 149:156823d33999 512
<> 149:156823d33999 513 /* program the osr value (bit value is one less than actual value) */
<> 149:156823d33999 514 temp &= ~LPUART_BAUD_OSR_MASK;
<> 149:156823d33999 515 temp |= LPUART_BAUD_OSR(osr - 1);
<> 149:156823d33999 516
<> 149:156823d33999 517 /* write the sbr value to the BAUD registers */
<> 149:156823d33999 518 temp &= ~LPUART_BAUD_SBR_MASK;
<> 149:156823d33999 519 base->BAUD = temp | LPUART_BAUD_SBR(sbr);
<> 149:156823d33999 520
<> 149:156823d33999 521 /* Restore CTRL. */
<> 149:156823d33999 522 base->CTRL = oldCtrl;
<> 149:156823d33999 523
<> 149:156823d33999 524 return kStatus_Success;
<> 149:156823d33999 525 }
<> 149:156823d33999 526 else
<> 149:156823d33999 527 {
<> 149:156823d33999 528 /* Unacceptable baud rate difference of more than 3%*/
<> 149:156823d33999 529 return kStatus_LPUART_BaudrateNotSupport;
<> 149:156823d33999 530 }
<> 149:156823d33999 531 }
<> 149:156823d33999 532
<> 149:156823d33999 533 void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)
<> 149:156823d33999 534 {
<> 149:156823d33999 535 base->BAUD |= ((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK));
<> 149:156823d33999 536 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 149:156823d33999 537 base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) |
<> 149:156823d33999 538 ((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
<> 149:156823d33999 539 #endif
<> 149:156823d33999 540 mask &= 0xFFFFFF00U;
<> 149:156823d33999 541 base->CTRL |= mask;
<> 149:156823d33999 542 }
<> 149:156823d33999 543
<> 149:156823d33999 544 void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask)
<> 149:156823d33999 545 {
<> 149:156823d33999 546 base->BAUD &= ~((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK));
<> 149:156823d33999 547 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 149:156823d33999 548 base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) &
<> 149:156823d33999 549 ~((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
<> 149:156823d33999 550 #endif
<> 149:156823d33999 551 mask &= 0xFFFFFF00U;
<> 149:156823d33999 552 base->CTRL &= ~mask;
<> 149:156823d33999 553 }
<> 149:156823d33999 554
<> 149:156823d33999 555 uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base)
<> 149:156823d33999 556 {
<> 149:156823d33999 557 uint32_t temp;
<> 149:156823d33999 558 temp = (base->BAUD & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)) >> 8;
<> 149:156823d33999 559 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 149:156823d33999 560 temp |= (base->FIFO & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)) >> 8;
<> 149:156823d33999 561 #endif
<> 149:156823d33999 562 temp |= (base->CTRL & 0xFF0C000);
<> 149:156823d33999 563
<> 149:156823d33999 564 return temp;
<> 149:156823d33999 565 }
<> 149:156823d33999 566
<> 149:156823d33999 567 uint32_t LPUART_GetStatusFlags(LPUART_Type *base)
<> 149:156823d33999 568 {
<> 149:156823d33999 569 uint32_t temp;
<> 149:156823d33999 570 temp = base->STAT;
<> 149:156823d33999 571 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 149:156823d33999 572 temp |= (base->FIFO &
<> 149:156823d33999 573 (LPUART_FIFO_TXEMPT_MASK | LPUART_FIFO_RXEMPT_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) >>
<> 149:156823d33999 574 16;
<> 149:156823d33999 575 #endif
<> 149:156823d33999 576 return temp;
<> 149:156823d33999 577 }
<> 149:156823d33999 578
<> 149:156823d33999 579 status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask)
<> 149:156823d33999 580 {
<> 149:156823d33999 581 uint32_t temp;
<> 149:156823d33999 582 status_t status;
<> 149:156823d33999 583 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 149:156823d33999 584 temp = (uint32_t)base->FIFO;
<> 149:156823d33999 585 temp &= (uint32_t)(~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK));
<> 149:156823d33999 586 temp |= (mask << 16) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK);
<> 149:156823d33999 587 base->FIFO = temp;
<> 149:156823d33999 588 #endif
<> 149:156823d33999 589 temp = (uint32_t)base->STAT;
<> 149:156823d33999 590 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
<> 149:156823d33999 591 temp &= (uint32_t)(~(LPUART_STAT_LBKDIF_MASK));
<> 149:156823d33999 592 temp |= mask & LPUART_STAT_LBKDIF_MASK;
<> 149:156823d33999 593 #endif
<> 149:156823d33999 594 temp &= (uint32_t)(~(LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
<> 149:156823d33999 595 LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK));
<> 149:156823d33999 596 temp |= mask & (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
<> 149:156823d33999 597 LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
<> 149:156823d33999 598 #if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
<> 149:156823d33999 599 temp &= (uint32_t)(~(LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK));
<> 149:156823d33999 600 temp |= mask & (LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK);
<> 149:156823d33999 601 #endif
<> 149:156823d33999 602 base->STAT = temp;
<> 149:156823d33999 603 /* If some flags still pending. */
<> 149:156823d33999 604 if (mask & LPUART_GetStatusFlags(base))
<> 149:156823d33999 605 {
<> 149:156823d33999 606 /* Some flags can only clear or set by the hardware itself, these flags are: kLPUART_TxDataRegEmptyFlag,
<> 149:156823d33999 607 kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, kLPUART_RxActiveFlag,
<> 149:156823d33999 608 kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag,
<> 149:156823d33999 609 kLPUART_TxFifoEmptyFlag, kLPUART_RxFifoEmptyFlag. */
<> 149:156823d33999 610 status = kStatus_LPUART_FlagCannotClearManually; /* flags can not clear manually */
<> 149:156823d33999 611 }
<> 149:156823d33999 612 else
<> 149:156823d33999 613 {
<> 149:156823d33999 614 status = kStatus_Success;
<> 149:156823d33999 615 }
<> 149:156823d33999 616
<> 149:156823d33999 617 return status;
<> 149:156823d33999 618 }
<> 149:156823d33999 619
<> 149:156823d33999 620 void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length)
<> 149:156823d33999 621 {
<> 149:156823d33999 622 assert(data);
<> 149:156823d33999 623
<> 149:156823d33999 624 /* This API can only ensure that the data is written into the data buffer but can't
<> 149:156823d33999 625 ensure all data in the data buffer are sent into the transmit shift buffer. */
<> 149:156823d33999 626 while (length--)
<> 149:156823d33999 627 {
<> 149:156823d33999 628 while (!(base->STAT & LPUART_STAT_TDRE_MASK))
<> 149:156823d33999 629 {
<> 149:156823d33999 630 }
<> 149:156823d33999 631 base->DATA = *(data++);
<> 149:156823d33999 632 }
<> 149:156823d33999 633 }
<> 149:156823d33999 634
<> 149:156823d33999 635 status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length)
<> 149:156823d33999 636 {
<> 149:156823d33999 637 assert(data);
<> 149:156823d33999 638
<> 149:156823d33999 639 uint32_t statusFlag;
<> 149:156823d33999 640 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
<> 149:156823d33999 641 uint32_t ctrl = base->CTRL;
<> 149:156823d33999 642 bool isSevenDataBits =
<> 149:156823d33999 643 ((ctrl & LPUART_CTRL_M7_MASK) ||
<> 149:156823d33999 644 ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
<> 149:156823d33999 645 #endif
<> 149:156823d33999 646
<> 149:156823d33999 647 while (length--)
<> 149:156823d33999 648 {
<> 149:156823d33999 649 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 149:156823d33999 650 while (0 == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT))
<> 149:156823d33999 651 #else
<> 149:156823d33999 652 while (!(base->STAT & LPUART_STAT_RDRF_MASK))
<> 149:156823d33999 653 #endif
<> 149:156823d33999 654 {
<> 149:156823d33999 655 statusFlag = LPUART_GetStatusFlags(base);
<> 149:156823d33999 656
<> 149:156823d33999 657 if (statusFlag & kLPUART_RxOverrunFlag)
<> 149:156823d33999 658 {
<> 149:156823d33999 659 LPUART_ClearStatusFlags(base, kLPUART_RxOverrunFlag);
<> 149:156823d33999 660 return kStatus_LPUART_RxHardwareOverrun;
<> 149:156823d33999 661 }
<> 149:156823d33999 662
<> 149:156823d33999 663 if (statusFlag & kLPUART_NoiseErrorFlag)
<> 149:156823d33999 664 {
<> 149:156823d33999 665 LPUART_ClearStatusFlags(base, kLPUART_NoiseErrorFlag);
<> 149:156823d33999 666 return kStatus_LPUART_NoiseError;
<> 149:156823d33999 667 }
<> 149:156823d33999 668
<> 149:156823d33999 669 if (statusFlag & kLPUART_FramingErrorFlag)
<> 149:156823d33999 670 {
<> 149:156823d33999 671 LPUART_ClearStatusFlags(base, kLPUART_FramingErrorFlag);
<> 149:156823d33999 672 return kStatus_LPUART_FramingError;
<> 149:156823d33999 673 }
<> 149:156823d33999 674
<> 149:156823d33999 675 if (statusFlag & kLPUART_ParityErrorFlag)
<> 149:156823d33999 676 {
<> 149:156823d33999 677 LPUART_ClearStatusFlags(base, kLPUART_ParityErrorFlag);
<> 149:156823d33999 678 return kStatus_LPUART_ParityError;
<> 149:156823d33999 679 }
<> 149:156823d33999 680 }
<> 149:156823d33999 681 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
<> 149:156823d33999 682 if (isSevenDataBits)
<> 149:156823d33999 683 {
<> 149:156823d33999 684 *(data++) = (base->DATA & 0x7F);
<> 149:156823d33999 685 }
<> 149:156823d33999 686 else
<> 149:156823d33999 687 {
<> 149:156823d33999 688 *(data++) = base->DATA;
<> 149:156823d33999 689 }
<> 149:156823d33999 690 #else
<> 149:156823d33999 691 *(data++) = base->DATA;
<> 149:156823d33999 692 #endif
<> 149:156823d33999 693 }
<> 149:156823d33999 694
<> 149:156823d33999 695 return kStatus_Success;
<> 149:156823d33999 696 }
<> 149:156823d33999 697
<> 149:156823d33999 698 void LPUART_TransferCreateHandle(LPUART_Type *base,
<> 149:156823d33999 699 lpuart_handle_t *handle,
<> 149:156823d33999 700 lpuart_transfer_callback_t callback,
<> 149:156823d33999 701 void *userData)
<> 149:156823d33999 702 {
<> 149:156823d33999 703 assert(handle);
<> 149:156823d33999 704
<> 149:156823d33999 705 uint32_t instance;
<> 149:156823d33999 706 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
<> 149:156823d33999 707 uint32_t ctrl = base->CTRL;
<> 149:156823d33999 708 bool isSevenDataBits =
<> 149:156823d33999 709 ((ctrl & LPUART_CTRL_M7_MASK) ||
<> 149:156823d33999 710 ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
<> 149:156823d33999 711 #endif
<> 149:156823d33999 712
<> 149:156823d33999 713 /* Zero the handle. */
<> 149:156823d33999 714 memset(handle, 0, sizeof(lpuart_handle_t));
<> 149:156823d33999 715
<> 149:156823d33999 716 /* Set the TX/RX state. */
<> 149:156823d33999 717 handle->rxState = kLPUART_RxIdle;
<> 149:156823d33999 718 handle->txState = kLPUART_TxIdle;
<> 149:156823d33999 719
<> 149:156823d33999 720 /* Set the callback and user data. */
<> 149:156823d33999 721 handle->callback = callback;
<> 149:156823d33999 722 handle->userData = userData;
<> 149:156823d33999 723
<> 149:156823d33999 724 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
<> 149:156823d33999 725 /* Initial seven data bits flag */
<> 149:156823d33999 726 handle->isSevenDataBits = isSevenDataBits;
<> 149:156823d33999 727 #endif
<> 149:156823d33999 728
<> 149:156823d33999 729 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 149:156823d33999 730 /* Note:
<> 149:156823d33999 731 Take care of the RX FIFO, RX interrupt request only assert when received bytes
<> 149:156823d33999 732 equal or more than RX water mark, there is potential issue if RX water
<> 149:156823d33999 733 mark larger than 1.
<> 149:156823d33999 734 For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and
<> 149:156823d33999 735 5 bytes are received. the last byte will be saved in FIFO but not trigger
<> 149:156823d33999 736 RX interrupt because the water mark is 2.
<> 149:156823d33999 737 */
<> 149:156823d33999 738 base->WATER &= (~LPUART_WATER_RXWATER_MASK);
<> 149:156823d33999 739 #endif
<> 149:156823d33999 740
<> 149:156823d33999 741 /* Get instance from peripheral base address. */
<> 149:156823d33999 742 instance = LPUART_GetInstance(base);
<> 149:156823d33999 743
<> 149:156823d33999 744 /* Save the handle in global variables to support the double weak mechanism. */
<> 149:156823d33999 745 s_lpuartHandle[instance] = handle;
<> 149:156823d33999 746
<> 149:156823d33999 747 s_lpuartIsr = LPUART_TransferHandleIRQ;
<> 149:156823d33999 748
<> 149:156823d33999 749 /* Enable interrupt in NVIC. */
<> 149:156823d33999 750 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
<> 149:156823d33999 751 EnableIRQ(s_lpuartRxIRQ[instance]);
<> 149:156823d33999 752 EnableIRQ(s_lpuartTxIRQ[instance]);
<> 149:156823d33999 753 #else
<> 149:156823d33999 754 EnableIRQ(s_lpuartIRQ[instance]);
<> 149:156823d33999 755 #endif
<> 149:156823d33999 756 }
<> 149:156823d33999 757
<> 149:156823d33999 758 void LPUART_TransferStartRingBuffer(LPUART_Type *base,
<> 149:156823d33999 759 lpuart_handle_t *handle,
<> 149:156823d33999 760 uint8_t *ringBuffer,
<> 149:156823d33999 761 size_t ringBufferSize)
<> 149:156823d33999 762 {
<> 149:156823d33999 763 assert(handle);
<> 149:156823d33999 764 assert(ringBuffer);
<> 149:156823d33999 765
<> 149:156823d33999 766 /* Setup the ring buffer address */
<> 149:156823d33999 767 handle->rxRingBuffer = ringBuffer;
<> 149:156823d33999 768 handle->rxRingBufferSize = ringBufferSize;
<> 149:156823d33999 769 handle->rxRingBufferHead = 0U;
<> 149:156823d33999 770 handle->rxRingBufferTail = 0U;
<> 149:156823d33999 771
<> 149:156823d33999 772 /* Enable the interrupt to accept the data when user need the ring buffer. */
<> 149:156823d33999 773 LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
<> 149:156823d33999 774 }
<> 149:156823d33999 775
<> 149:156823d33999 776 void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle)
<> 149:156823d33999 777 {
<> 149:156823d33999 778 assert(handle);
<> 149:156823d33999 779
<> 149:156823d33999 780 if (handle->rxState == kLPUART_RxIdle)
<> 149:156823d33999 781 {
<> 149:156823d33999 782 LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
<> 149:156823d33999 783 }
<> 149:156823d33999 784
<> 149:156823d33999 785 handle->rxRingBuffer = NULL;
<> 149:156823d33999 786 handle->rxRingBufferSize = 0U;
<> 149:156823d33999 787 handle->rxRingBufferHead = 0U;
<> 149:156823d33999 788 handle->rxRingBufferTail = 0U;
<> 149:156823d33999 789 }
<> 149:156823d33999 790
<> 149:156823d33999 791 status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer)
<> 149:156823d33999 792 {
<> 149:156823d33999 793 assert(handle);
<> 149:156823d33999 794 assert(xfer);
<> 149:156823d33999 795 assert(xfer->data);
<> 149:156823d33999 796 assert(xfer->dataSize);
<> 149:156823d33999 797
<> 149:156823d33999 798 status_t status;
<> 149:156823d33999 799
<> 149:156823d33999 800 /* Return error if current TX busy. */
<> 149:156823d33999 801 if (kLPUART_TxBusy == handle->txState)
<> 149:156823d33999 802 {
<> 149:156823d33999 803 status = kStatus_LPUART_TxBusy;
<> 149:156823d33999 804 }
<> 149:156823d33999 805 else
<> 149:156823d33999 806 {
<> 149:156823d33999 807 handle->txData = xfer->data;
<> 149:156823d33999 808 handle->txDataSize = xfer->dataSize;
<> 149:156823d33999 809 handle->txDataSizeAll = xfer->dataSize;
<> 149:156823d33999 810 handle->txState = kLPUART_TxBusy;
<> 149:156823d33999 811
<> 149:156823d33999 812 /* Enable transmiter interrupt. */
<> 149:156823d33999 813 LPUART_EnableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable);
<> 149:156823d33999 814
<> 149:156823d33999 815 status = kStatus_Success;
<> 149:156823d33999 816 }
<> 149:156823d33999 817
<> 149:156823d33999 818 return status;
<> 149:156823d33999 819 }
<> 149:156823d33999 820
<> 149:156823d33999 821 void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle)
<> 149:156823d33999 822 {
<> 149:156823d33999 823 assert(handle);
<> 149:156823d33999 824
<> 149:156823d33999 825 LPUART_DisableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_TransmissionCompleteInterruptEnable);
<> 149:156823d33999 826
<> 149:156823d33999 827 handle->txDataSize = 0;
<> 149:156823d33999 828 handle->txState = kLPUART_TxIdle;
<> 149:156823d33999 829 }
<> 149:156823d33999 830
<> 149:156823d33999 831 status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)
<> 149:156823d33999 832 {
<> 149:156823d33999 833 assert(handle);
<> 149:156823d33999 834 assert(count);
<> 149:156823d33999 835
<> 149:156823d33999 836 if (kLPUART_TxIdle == handle->txState)
<> 149:156823d33999 837 {
<> 149:156823d33999 838 return kStatus_NoTransferInProgress;
<> 149:156823d33999 839 }
<> 149:156823d33999 840
<> 149:156823d33999 841 *count = handle->txDataSizeAll - handle->txDataSize;
<> 149:156823d33999 842
<> 149:156823d33999 843 return kStatus_Success;
<> 149:156823d33999 844 }
<> 149:156823d33999 845
<> 149:156823d33999 846 status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
<> 149:156823d33999 847 lpuart_handle_t *handle,
<> 149:156823d33999 848 lpuart_transfer_t *xfer,
<> 149:156823d33999 849 size_t *receivedBytes)
<> 149:156823d33999 850 {
<> 149:156823d33999 851 assert(handle);
<> 149:156823d33999 852 assert(xfer);
<> 149:156823d33999 853 assert(xfer->data);
<> 149:156823d33999 854 assert(xfer->dataSize);
<> 149:156823d33999 855
<> 149:156823d33999 856 uint32_t i;
<> 149:156823d33999 857 status_t status;
<> 149:156823d33999 858 /* How many bytes to copy from ring buffer to user memory. */
<> 149:156823d33999 859 size_t bytesToCopy = 0U;
<> 149:156823d33999 860 /* How many bytes to receive. */
<> 149:156823d33999 861 size_t bytesToReceive;
<> 149:156823d33999 862 /* How many bytes currently have received. */
<> 149:156823d33999 863 size_t bytesCurrentReceived;
<> 149:156823d33999 864 uint32_t regPrimask = 0U;
<> 149:156823d33999 865
<> 149:156823d33999 866 /* How to get data:
<> 149:156823d33999 867 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
<> 149:156823d33999 868 to lpuart handle, enable interrupt to store received data to xfer->data. When
<> 149:156823d33999 869 all data received, trigger callback.
<> 149:156823d33999 870 2. If RX ring buffer is enabled and not empty, get data from ring buffer first.
<> 149:156823d33999 871 If there are enough data in ring buffer, copy them to xfer->data and return.
<> 149:156823d33999 872 If there are not enough data in ring buffer, copy all of them to xfer->data,
<> 149:156823d33999 873 save the xfer->data remained empty space to lpuart handle, receive data
<> 149:156823d33999 874 to this empty space and trigger callback when finished. */
<> 149:156823d33999 875
<> 149:156823d33999 876 if (kLPUART_RxBusy == handle->rxState)
<> 149:156823d33999 877 {
<> 149:156823d33999 878 status = kStatus_LPUART_RxBusy;
<> 149:156823d33999 879 }
<> 149:156823d33999 880 else
<> 149:156823d33999 881 {
<> 149:156823d33999 882 bytesToReceive = xfer->dataSize;
<> 149:156823d33999 883 bytesCurrentReceived = 0;
<> 149:156823d33999 884
<> 149:156823d33999 885 /* If RX ring buffer is used. */
<> 149:156823d33999 886 if (handle->rxRingBuffer)
<> 149:156823d33999 887 {
<> 149:156823d33999 888 /* Disable IRQ, protect ring buffer. */
<> 149:156823d33999 889 regPrimask = DisableGlobalIRQ();
<> 149:156823d33999 890
<> 149:156823d33999 891 /* How many bytes in RX ring buffer currently. */
<> 149:156823d33999 892 bytesToCopy = LPUART_TransferGetRxRingBufferLength(base, handle);
<> 149:156823d33999 893
<> 149:156823d33999 894 if (bytesToCopy)
<> 149:156823d33999 895 {
<> 149:156823d33999 896 bytesToCopy = MIN(bytesToReceive, bytesToCopy);
<> 149:156823d33999 897
<> 149:156823d33999 898 bytesToReceive -= bytesToCopy;
<> 149:156823d33999 899
<> 149:156823d33999 900 /* Copy data from ring buffer to user memory. */
<> 149:156823d33999 901 for (i = 0U; i < bytesToCopy; i++)
<> 149:156823d33999 902 {
<> 149:156823d33999 903 xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];
<> 149:156823d33999 904
<> 149:156823d33999 905 /* Wrap to 0. Not use modulo (%) because it might be large and slow. */
<> 149:156823d33999 906 if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
<> 149:156823d33999 907 {
<> 149:156823d33999 908 handle->rxRingBufferTail = 0U;
<> 149:156823d33999 909 }
<> 149:156823d33999 910 else
<> 149:156823d33999 911 {
<> 149:156823d33999 912 handle->rxRingBufferTail++;
<> 149:156823d33999 913 }
<> 149:156823d33999 914 }
<> 149:156823d33999 915 }
<> 149:156823d33999 916
<> 149:156823d33999 917 /* If ring buffer does not have enough data, still need to read more data. */
<> 149:156823d33999 918 if (bytesToReceive)
<> 149:156823d33999 919 {
<> 149:156823d33999 920 /* No data in ring buffer, save the request to LPUART handle. */
<> 149:156823d33999 921 handle->rxData = xfer->data + bytesCurrentReceived;
<> 149:156823d33999 922 handle->rxDataSize = bytesToReceive;
<> 149:156823d33999 923 handle->rxDataSizeAll = bytesToReceive;
<> 149:156823d33999 924 handle->rxState = kLPUART_RxBusy;
<> 149:156823d33999 925 }
<> 149:156823d33999 926 /* Enable IRQ if previously enabled. */
<> 149:156823d33999 927 EnableGlobalIRQ(regPrimask);
<> 149:156823d33999 928
<> 149:156823d33999 929 /* Call user callback since all data are received. */
<> 149:156823d33999 930 if (0 == bytesToReceive)
<> 149:156823d33999 931 {
<> 149:156823d33999 932 if (handle->callback)
<> 149:156823d33999 933 {
<> 149:156823d33999 934 handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData);
<> 149:156823d33999 935 }
<> 149:156823d33999 936 }
<> 149:156823d33999 937 }
<> 149:156823d33999 938 /* Ring buffer not used. */
<> 149:156823d33999 939 else
<> 149:156823d33999 940 {
<> 149:156823d33999 941 handle->rxData = xfer->data + bytesCurrentReceived;
<> 149:156823d33999 942 handle->rxDataSize = bytesToReceive;
<> 149:156823d33999 943 handle->rxDataSizeAll = bytesToReceive;
<> 149:156823d33999 944 handle->rxState = kLPUART_RxBusy;
<> 149:156823d33999 945
<> 149:156823d33999 946 /* Enable RX interrupt. */
<> 149:156823d33999 947 LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
<> 149:156823d33999 948 }
<> 149:156823d33999 949
<> 149:156823d33999 950 /* Return the how many bytes have read. */
<> 149:156823d33999 951 if (receivedBytes)
<> 149:156823d33999 952 {
<> 149:156823d33999 953 *receivedBytes = bytesCurrentReceived;
<> 149:156823d33999 954 }
<> 149:156823d33999 955
<> 149:156823d33999 956 status = kStatus_Success;
<> 149:156823d33999 957 }
<> 149:156823d33999 958
<> 149:156823d33999 959 return status;
<> 149:156823d33999 960 }
<> 149:156823d33999 961
<> 149:156823d33999 962 void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle)
<> 149:156823d33999 963 {
<> 149:156823d33999 964 assert(handle);
<> 149:156823d33999 965
<> 149:156823d33999 966 /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
<> 149:156823d33999 967 if (!handle->rxRingBuffer)
<> 149:156823d33999 968 {
<> 149:156823d33999 969 /* Disable RX interrupt. */
<> 149:156823d33999 970 LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
<> 149:156823d33999 971 }
<> 149:156823d33999 972
<> 149:156823d33999 973 handle->rxDataSize = 0U;
<> 149:156823d33999 974 handle->rxState = kLPUART_RxIdle;
<> 149:156823d33999 975 }
<> 149:156823d33999 976
<> 149:156823d33999 977 status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)
<> 149:156823d33999 978 {
<> 149:156823d33999 979 assert(handle);
<> 149:156823d33999 980 assert(count);
<> 149:156823d33999 981
<> 149:156823d33999 982 if (kLPUART_RxIdle == handle->rxState)
<> 149:156823d33999 983 {
<> 149:156823d33999 984 return kStatus_NoTransferInProgress;
<> 149:156823d33999 985 }
<> 149:156823d33999 986
<> 149:156823d33999 987 *count = handle->rxDataSizeAll - handle->rxDataSize;
<> 149:156823d33999 988
<> 149:156823d33999 989 return kStatus_Success;
<> 149:156823d33999 990 }
<> 149:156823d33999 991
<> 149:156823d33999 992 void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle)
<> 149:156823d33999 993 {
<> 149:156823d33999 994 assert(handle);
<> 149:156823d33999 995
<> 149:156823d33999 996 uint8_t count;
<> 149:156823d33999 997 uint8_t tempCount;
<> 149:156823d33999 998
<> 149:156823d33999 999 /* If RX overrun. */
<> 149:156823d33999 1000 if (LPUART_STAT_OR_MASK & base->STAT)
<> 149:156823d33999 1001 {
<> 149:156823d33999 1002 /* Clear overrun flag, otherwise the RX does not work. */
<> 149:156823d33999 1003 base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK);
<> 149:156823d33999 1004
<> 149:156823d33999 1005 /* Trigger callback. */
<> 149:156823d33999 1006 if (handle->callback)
<> 149:156823d33999 1007 {
<> 149:156823d33999 1008 handle->callback(base, handle, kStatus_LPUART_RxHardwareOverrun, handle->userData);
<> 149:156823d33999 1009 }
<> 149:156823d33999 1010 }
<> 149:156823d33999 1011
<> 149:156823d33999 1012 /* Receive data register full */
<> 149:156823d33999 1013 if ((LPUART_STAT_RDRF_MASK & base->STAT) && (LPUART_CTRL_RIE_MASK & base->CTRL))
<> 149:156823d33999 1014 {
<> 149:156823d33999 1015 /* Get the size that can be stored into buffer for this interrupt. */
<> 149:156823d33999 1016 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 149:156823d33999 1017 count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT));
<> 149:156823d33999 1018 #else
<> 149:156823d33999 1019 count = 1;
<> 149:156823d33999 1020 #endif
<> 149:156823d33999 1021
<> 149:156823d33999 1022 /* If handle->rxDataSize is not 0, first save data to handle->rxData. */
<> 149:156823d33999 1023 while ((count) && (handle->rxDataSize))
<> 149:156823d33999 1024 {
<> 149:156823d33999 1025 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 149:156823d33999 1026 tempCount = MIN(handle->rxDataSize, count);
<> 149:156823d33999 1027 #else
<> 149:156823d33999 1028 tempCount = 1;
<> 149:156823d33999 1029 #endif
<> 149:156823d33999 1030
<> 149:156823d33999 1031 /* Using non block API to read the data from the registers. */
<> 149:156823d33999 1032 LPUART_ReadNonBlocking(base, handle->rxData, tempCount);
<> 149:156823d33999 1033 handle->rxData += tempCount;
<> 149:156823d33999 1034 handle->rxDataSize -= tempCount;
<> 149:156823d33999 1035 count -= tempCount;
<> 149:156823d33999 1036
<> 149:156823d33999 1037 /* If all the data required for upper layer is ready, trigger callback. */
<> 149:156823d33999 1038 if (!handle->rxDataSize)
<> 149:156823d33999 1039 {
<> 149:156823d33999 1040 handle->rxState = kLPUART_RxIdle;
<> 149:156823d33999 1041
<> 149:156823d33999 1042 if (handle->callback)
<> 149:156823d33999 1043 {
<> 149:156823d33999 1044 handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData);
<> 149:156823d33999 1045 }
<> 149:156823d33999 1046 }
<> 149:156823d33999 1047 }
<> 149:156823d33999 1048
<> 149:156823d33999 1049 /* If use RX ring buffer, receive data to ring buffer. */
<> 149:156823d33999 1050 if (handle->rxRingBuffer)
<> 149:156823d33999 1051 {
<> 149:156823d33999 1052 while (count--)
<> 149:156823d33999 1053 {
<> 149:156823d33999 1054 /* If RX ring buffer is full, trigger callback to notify over run. */
<> 149:156823d33999 1055 if (LPUART_TransferIsRxRingBufferFull(base, handle))
<> 149:156823d33999 1056 {
<> 149:156823d33999 1057 if (handle->callback)
<> 149:156823d33999 1058 {
<> 149:156823d33999 1059 handle->callback(base, handle, kStatus_LPUART_RxRingBufferOverrun, handle->userData);
<> 149:156823d33999 1060 }
<> 149:156823d33999 1061 }
<> 149:156823d33999 1062
<> 149:156823d33999 1063 /* If ring buffer is still full after callback function, the oldest data is overrided. */
<> 149:156823d33999 1064 if (LPUART_TransferIsRxRingBufferFull(base, handle))
<> 149:156823d33999 1065 {
<> 149:156823d33999 1066 /* Increase handle->rxRingBufferTail to make room for new data. */
<> 149:156823d33999 1067 if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
<> 149:156823d33999 1068 {
<> 149:156823d33999 1069 handle->rxRingBufferTail = 0U;
<> 149:156823d33999 1070 }
<> 149:156823d33999 1071 else
<> 149:156823d33999 1072 {
<> 149:156823d33999 1073 handle->rxRingBufferTail++;
<> 149:156823d33999 1074 }
<> 149:156823d33999 1075 }
<> 149:156823d33999 1076
<> 149:156823d33999 1077 /* Read data. */
<> 149:156823d33999 1078 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
<> 149:156823d33999 1079 if (handle->isSevenDataBits)
<> 149:156823d33999 1080 {
<> 149:156823d33999 1081 handle->rxRingBuffer[handle->rxRingBufferHead] = (base->DATA & 0x7F);
<> 149:156823d33999 1082 }
<> 149:156823d33999 1083 else
<> 149:156823d33999 1084 {
<> 149:156823d33999 1085 handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA;
<> 149:156823d33999 1086 }
<> 149:156823d33999 1087 #else
<> 149:156823d33999 1088 handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA;
<> 149:156823d33999 1089 #endif
<> 149:156823d33999 1090
<> 149:156823d33999 1091 /* Increase handle->rxRingBufferHead. */
<> 149:156823d33999 1092 if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)
<> 149:156823d33999 1093 {
<> 149:156823d33999 1094 handle->rxRingBufferHead = 0U;
<> 149:156823d33999 1095 }
<> 149:156823d33999 1096 else
<> 149:156823d33999 1097 {
<> 149:156823d33999 1098 handle->rxRingBufferHead++;
<> 149:156823d33999 1099 }
<> 149:156823d33999 1100 }
<> 149:156823d33999 1101 }
<> 149:156823d33999 1102 /* If no receive requst pending, stop RX interrupt. */
<> 149:156823d33999 1103 else if (!handle->rxDataSize)
<> 149:156823d33999 1104 {
<> 149:156823d33999 1105 LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
<> 149:156823d33999 1106 }
<> 149:156823d33999 1107 else
<> 149:156823d33999 1108 {
<> 149:156823d33999 1109 }
<> 149:156823d33999 1110 }
<> 149:156823d33999 1111
<> 149:156823d33999 1112 /* Send data register empty and the interrupt is enabled. */
<> 149:156823d33999 1113 if ((base->STAT & LPUART_STAT_TDRE_MASK) && (base->CTRL & LPUART_CTRL_TIE_MASK))
<> 149:156823d33999 1114 {
<> 149:156823d33999 1115 /* Get the bytes that available at this moment. */
<> 149:156823d33999 1116 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 149:156823d33999 1117 count = FSL_FEATURE_LPUART_FIFO_SIZEn(base) -
<> 149:156823d33999 1118 ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT);
<> 149:156823d33999 1119 #else
<> 149:156823d33999 1120 count = 1;
<> 149:156823d33999 1121 #endif
<> 149:156823d33999 1122
<> 149:156823d33999 1123 while ((count) && (handle->txDataSize))
<> 149:156823d33999 1124 {
<> 149:156823d33999 1125 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 149:156823d33999 1126 tempCount = MIN(handle->txDataSize, count);
<> 149:156823d33999 1127 #else
<> 149:156823d33999 1128 tempCount = 1;
<> 149:156823d33999 1129 #endif
<> 149:156823d33999 1130
<> 149:156823d33999 1131 /* Using non block API to write the data to the registers. */
<> 149:156823d33999 1132 LPUART_WriteNonBlocking(base, handle->txData, tempCount);
<> 149:156823d33999 1133 handle->txData += tempCount;
<> 149:156823d33999 1134 handle->txDataSize -= tempCount;
<> 149:156823d33999 1135 count -= tempCount;
<> 149:156823d33999 1136
<> 149:156823d33999 1137 /* If all the data are written to data register, notify user with the callback, then TX finished. */
<> 149:156823d33999 1138 if (!handle->txDataSize)
<> 149:156823d33999 1139 {
<> 149:156823d33999 1140 handle->txState = kLPUART_TxIdle;
<> 149:156823d33999 1141
<> 149:156823d33999 1142 /* Disable TX register empty interrupt. */
<> 149:156823d33999 1143 base->CTRL = (base->CTRL & ~LPUART_CTRL_TIE_MASK);
<> 149:156823d33999 1144
<> 149:156823d33999 1145 /* Trigger callback. */
<> 149:156823d33999 1146 if (handle->callback)
<> 149:156823d33999 1147 {
<> 149:156823d33999 1148 handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData);
<> 149:156823d33999 1149 }
<> 149:156823d33999 1150 }
<> 149:156823d33999 1151 }
<> 149:156823d33999 1152 }
<> 149:156823d33999 1153 }
<> 149:156823d33999 1154
<> 149:156823d33999 1155 void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle)
<> 149:156823d33999 1156 {
<> 149:156823d33999 1157 /* To be implemented by User. */
<> 149:156823d33999 1158 }
<> 149:156823d33999 1159
<> 149:156823d33999 1160 #if defined(LPUART0)
<> 149:156823d33999 1161 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
<> 149:156823d33999 1162 void LPUART0_TX_DriverIRQHandler(void)
<> 149:156823d33999 1163 {
<> 149:156823d33999 1164 s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
<> 149:156823d33999 1165 }
<> 149:156823d33999 1166 void LPUART0_RX_DriverIRQHandler(void)
<> 149:156823d33999 1167 {
<> 149:156823d33999 1168 s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
<> 149:156823d33999 1169 }
<> 149:156823d33999 1170 #else
<> 149:156823d33999 1171 void LPUART0_DriverIRQHandler(void)
<> 149:156823d33999 1172 {
<> 149:156823d33999 1173 s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
<> 149:156823d33999 1174 }
<> 149:156823d33999 1175 #endif
<> 149:156823d33999 1176 #endif
<> 149:156823d33999 1177
<> 149:156823d33999 1178 #if defined(LPUART1)
<> 149:156823d33999 1179 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
<> 149:156823d33999 1180 void LPUART1_TX_DriverIRQHandler(void)
<> 149:156823d33999 1181 {
<> 149:156823d33999 1182 s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
<> 149:156823d33999 1183 }
<> 149:156823d33999 1184 void LPUART1_RX_DriverIRQHandler(void)
<> 149:156823d33999 1185 {
<> 149:156823d33999 1186 s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
<> 149:156823d33999 1187 }
<> 149:156823d33999 1188 #else
<> 149:156823d33999 1189 void LPUART1_DriverIRQHandler(void)
<> 149:156823d33999 1190 {
<> 149:156823d33999 1191 s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
<> 149:156823d33999 1192 }
<> 149:156823d33999 1193 #endif
<> 149:156823d33999 1194 #endif
<> 149:156823d33999 1195
<> 149:156823d33999 1196 #if defined(LPUART2)
<> 149:156823d33999 1197 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
<> 149:156823d33999 1198 void LPUART2_TX_DriverIRQHandler(void)
<> 149:156823d33999 1199 {
<> 149:156823d33999 1200 s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
<> 149:156823d33999 1201 }
<> 149:156823d33999 1202 void LPUART2_RX_DriverIRQHandler(void)
<> 149:156823d33999 1203 {
<> 149:156823d33999 1204 s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
<> 149:156823d33999 1205 }
<> 149:156823d33999 1206 #else
<> 149:156823d33999 1207 void LPUART2_DriverIRQHandler(void)
<> 149:156823d33999 1208 {
<> 149:156823d33999 1209 s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
<> 149:156823d33999 1210 }
<> 149:156823d33999 1211 #endif
<> 149:156823d33999 1212 #endif
<> 149:156823d33999 1213
<> 149:156823d33999 1214 #if defined(LPUART3)
<> 149:156823d33999 1215 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
<> 149:156823d33999 1216 void LPUART3_TX_DriverIRQHandler(void)
<> 149:156823d33999 1217 {
<> 149:156823d33999 1218 s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
<> 149:156823d33999 1219 }
<> 149:156823d33999 1220 void LPUART3_RX_DriverIRQHandler(void)
<> 149:156823d33999 1221 {
<> 149:156823d33999 1222 s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
<> 149:156823d33999 1223 }
<> 149:156823d33999 1224 #else
<> 149:156823d33999 1225 void LPUART3_DriverIRQHandler(void)
<> 149:156823d33999 1226 {
<> 149:156823d33999 1227 s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
<> 149:156823d33999 1228 }
<> 149:156823d33999 1229 #endif
<> 149:156823d33999 1230 #endif
<> 149:156823d33999 1231
<> 149:156823d33999 1232 #if defined(LPUART4)
<> 149:156823d33999 1233 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
<> 149:156823d33999 1234 void LPUART4_TX_DriverIRQHandler(void)
<> 149:156823d33999 1235 {
<> 149:156823d33999 1236 s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
<> 149:156823d33999 1237 }
<> 149:156823d33999 1238 void LPUART4_RX_DriverIRQHandler(void)
<> 149:156823d33999 1239 {
<> 149:156823d33999 1240 s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
<> 149:156823d33999 1241 }
<> 149:156823d33999 1242 #else
<> 149:156823d33999 1243 void LPUART4_DriverIRQHandler(void)
<> 149:156823d33999 1244 {
<> 149:156823d33999 1245 s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
<> 149:156823d33999 1246 }
<> 149:156823d33999 1247 #endif
<> 149:156823d33999 1248 #endif
<> 149:156823d33999 1249
<> 149:156823d33999 1250 #if defined(LPUART5)
<> 149:156823d33999 1251 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
<> 149:156823d33999 1252 void LPUART5_TX_DriverIRQHandler(void)
<> 149:156823d33999 1253 {
<> 149:156823d33999 1254 s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
<> 149:156823d33999 1255 }
<> 149:156823d33999 1256 void LPUART5_RX_DriverIRQHandler(void)
<> 149:156823d33999 1257 {
<> 149:156823d33999 1258 s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
<> 149:156823d33999 1259 }
<> 149:156823d33999 1260 #else
<> 149:156823d33999 1261 void LPUART5_DriverIRQHandler(void)
<> 149:156823d33999 1262 {
<> 149:156823d33999 1263 s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
<> 149:156823d33999 1264 }
<> 149:156823d33999 1265 #endif
<> 149:156823d33999 1266 #endif