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targets/TARGET_ARM_SSG/TARGET_BEETLE/device/fcache_api.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/fcache_api.h@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16
<> 144:ef7eb2e8f9f7 17 #ifndef _FCACHE_DRV_H
<> 144:ef7eb2e8f9f7 18 #define _FCACHE_DRV_H
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 extern "C" {
<> 144:ef7eb2e8f9f7 23 #else
<> 144:ef7eb2e8f9f7 24 #include <stdio.h>
<> 144:ef7eb2e8f9f7 25 #endif
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 /* Flash Cache Address Map */
<> 144:ef7eb2e8f9f7 28 #define SYS_FCACHE_BASE 0x40003000
<> 144:ef7eb2e8f9f7 29 /* Configuration and Control Register */
<> 144:ef7eb2e8f9f7 30 #define SYS_FCACHE_CCR (SYS_FCACHE_BASE)
<> 144:ef7eb2e8f9f7 31 /* Status Register */
<> 144:ef7eb2e8f9f7 32 #define SYS_FCACHE_SR (SYS_FCACHE_BASE + 0x4)
<> 144:ef7eb2e8f9f7 33 /* Interrupt Req Status Register */
<> 144:ef7eb2e8f9f7 34 #define SYS_FCACHE_IRQSTAT (SYS_FCACHE_BASE + 0x8)
<> 144:ef7eb2e8f9f7 35 /* Cache Statistic Hit Register */
<> 144:ef7eb2e8f9f7 36 #define SYS_FCACHE_CSHR (SYS_FCACHE_BASE + 0x14)
<> 144:ef7eb2e8f9f7 37 /* Cache Statistic Miss Register */
<> 144:ef7eb2e8f9f7 38 #define SYS_FCACHE_CSMR (SYS_FCACHE_BASE + 0x18)
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 /* SYS_FCACHE_CCR (RW): Configuration and Control Register */
<> 144:ef7eb2e8f9f7 41 #define FCACHE_EN 1 /* FCache Enable */
<> 144:ef7eb2e8f9f7 42 #define FCACHE_INV_REQ (1 << 1) /* Manual Invalidate Request */
<> 144:ef7eb2e8f9f7 43 #define FCACHE_POW_REQ (1 << 2) /* Manual SRAM Power Request */
<> 144:ef7eb2e8f9f7 44 #define FCACHE_SET_MAN_POW (1 << 3) /* Power Control Setting */
<> 144:ef7eb2e8f9f7 45 #define FCACHE_SET_MAN_INV (1 << 4) /* Invalidate Control Setting */
<> 144:ef7eb2e8f9f7 46 #define FCACHE_SET_PREFETCH (1 << 5) /* Cache Prefetch Setting */
<> 144:ef7eb2e8f9f7 47 #define FCACHE_STATISTIC_EN (1 << 6) /* Enable Statistics Logic */
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /* SYS_FCACHE_SR (RO): Status Register */
<> 144:ef7eb2e8f9f7 50 #define FCACHE_CS 0x3 /* Cache Status Mask */
<> 144:ef7eb2e8f9f7 51 #define FCACHE_CS_DISABLED 0x0
<> 144:ef7eb2e8f9f7 52 #define FCACHE_CS_ENABLING 0x1
<> 144:ef7eb2e8f9f7 53 #define FCACHE_CS_ENABLED 0x2
<> 144:ef7eb2e8f9f7 54 #define FCACHE_CS_DISABLING 0x3
<> 144:ef7eb2e8f9f7 55 #define FCACHE_INV_STAT 0x4 /* Invalidating Status */
<> 144:ef7eb2e8f9f7 56 #define FCACHE_POW_STAT 0x10 /* SRAM Power Ack */
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /* SYS_FCACHE_IRQSTAT (RW): Interrupt Req Status Register */
<> 144:ef7eb2e8f9f7 59 #define FCACHE_POW_ERR 1 /* SRAM Power Error */
<> 144:ef7eb2e8f9f7 60 #define FCACHE_MAN_INV_ERR (1 << 1) /* Manual Invalidation error status */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /* Macros */
<> 144:ef7eb2e8f9f7 63 #define FCache_Readl(reg) *(volatile unsigned int *)reg
<> 144:ef7eb2e8f9f7 64 #define FCache_Writel(reg, val) *(volatile unsigned int *)reg = val;
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 /* Functions */
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 /*
<> 144:ef7eb2e8f9f7 69 * FCache_DriverInitialize: flash cache driver initialize funtion
<> 144:ef7eb2e8f9f7 70 */
<> 144:ef7eb2e8f9f7 71 void FCache_DriverInitialize(void);
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 /*
<> 144:ef7eb2e8f9f7 74 * FCache_Enable: Enables the flash cache mode
<> 144:ef7eb2e8f9f7 75 * mode: supported modes:
<> 144:ef7eb2e8f9f7 76 * 0 - auto-power auto-invalidate
<> 144:ef7eb2e8f9f7 77 * 1 - manual-power, manual-invalidate
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79 void FCache_Enable(int mode);
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /*
<> 144:ef7eb2e8f9f7 82 * FCache_Disable: Disables the flash cache mode previously enabled
<> 144:ef7eb2e8f9f7 83 */
<> 144:ef7eb2e8f9f7 84 void FCache_Disable(void);
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /*
<> 144:ef7eb2e8f9f7 87 * FCache_Invalidate: to be invalidated the cache needs to be disabled.
<> 144:ef7eb2e8f9f7 88 * return -1: flash cannot be disabled
<> 144:ef7eb2e8f9f7 89 * -2: flash cannot be enabled
<> 144:ef7eb2e8f9f7 90 */
<> 144:ef7eb2e8f9f7 91 int FCache_Invalidate(void);
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /*
<> 144:ef7eb2e8f9f7 94 * FCache_GetStats: provides cache stats
<> 144:ef7eb2e8f9f7 95 */
<> 144:ef7eb2e8f9f7 96 unsigned int * FCache_GetStats(void);
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /*
<> 144:ef7eb2e8f9f7 99 * FCache_isEnabled: returns 1 if FCache is enabled
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101 unsigned int FCache_isEnabled(void);
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 104 }
<> 144:ef7eb2e8f9f7 105 #endif
<> 144:ef7eb2e8f9f7 106 #endif /* _FCACHE_DRV_H */