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SILICATUSA-ISO15693
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main.cpp
00001 #include "mbed.h" 00002 00003 SPI spi(p11, p12, p13); // mosi, miso, sclk 00004 DigitalOut cs(p28); // chip select 00005 DigitalOut ifsel1(p26); // interface select pin for CLRC6630 00006 DigitalOut pdres(p27); // CLRC6630 RESET pin - H = RESET 00007 DigitalOut led[] = {(LED1) , (LED2) , (LED3) , (LED4)}; // onboard LEDs 00008 Serial pc(USBTX, USBRX); // tx, rx 00009 00010 char r; 00011 int w = 0; 00012 char UID0 , UID1 , UID2 , UID3 , UID4, UID5 , UID6 , UID7 , UID8 , UID9, UID10; 00013 00014 00015 //write SPI registers 00016 void write_reg(char n, char o) 00017 { 00018 00019 cs=0; // device select 00020 00021 spi.write (n<<1); 00022 spi.write (o); 00023 00024 cs=1; // device deselect 00025 } 00026 00027 00028 // read SPI registers 00029 char read_reg(char n) 00030 { 00031 char t; 00032 cs=0; // device select 00033 00034 00035 spi.write ((n<<1)|0x01); 00036 t=spi.write (0); 00037 00038 cs=1; // device deselect 00039 00040 return t; 00041 } 00042 00043 00044 //> Terminate any running command. Flush_FiFo 00045 void terminate_and_flush_FiFo() 00046 { 00047 write_reg( 0x00, 0x00 ); 00048 write_reg( 0x02, 0xB0 ); 00049 } 00050 00051 00052 // Clear all IRQ 0,1 flags 00053 void clear_IRQ() 00054 { 00055 write_reg( 0x06, 0x7F ); 00056 write_reg( 0x07, 0x7F ); 00057 } 00058 00059 00060 // Disable Irq 0,1 sources 00061 void disable_IRQ() 00062 { 00063 write_reg( 0x08, 0x00 ); 00064 write_reg( 0x09, 0x00 ); 00065 } 00066 00067 00068 //> Wait until the command is finished. Enable IRQ sources. 00069 void wait_command_and_enable_IRQ() 00070 { 00071 write_reg( 0x08, 0x18 ); // Enable Irqs 0,1 00072 write_reg( 0x09, 0x42 ); // Enable the global IRQ to be propagated to the IRQ pin 00073 00074 while( (read_reg( 0x07 ) & 0x40)==0); 00075 } 00076 00077 00078 // Read IRQ 0,1 Status register 00079 void read_IRQ_status() 00080 { 00081 r = read_reg( 0x06 ); 00082 r = read_reg( 0x07 ); 00083 } 00084 00085 00086 // Start tranceive command 00087 void start_tranceive() 00088 { 00089 write_reg( 0x00, 0x07 ); 00090 wait(0.01); 00091 } 00092 00093 00094 int main() { 00095 00096 while (1) { 00097 00098 // start activity LED; 00099 led[3] = 0; 00100 led[2] = 0; 00101 led[1] = 0; 00102 led[0] = 1; 00103 00104 // set the comunication method 00105 //ifsel1 = 0; // usare questa istruzione per le schede revisione prototipo 00106 ifsel1 = 1; // usare questa istruzione per le schede revisione B 00107 wait(0.001); 00108 00109 // SPI comunication settings 00110 spi.format(8,0); 00111 spi.frequency(1000000); 00112 00113 do { 00114 00115 w = 0; 00116 00117 do { 00118 00119 //RESET the device 00120 pdres = 1; 00121 wait(0.001); 00122 pdres = 0; 00123 00124 wait(0.005); 00125 00126 00127 //> -------------------------------- 00128 //write_reg( 0x37, 0xFF ); 00129 00130 //> ============================================= 00131 //> Load Protocol (ISO15693) 00132 //> ============================================= 00133 00134 write_reg( 0x0F, 0x98 ); // Configure T0 00135 write_reg( 0x14, 0x92 ); // Configure T1 and cascade it with T0 00136 write_reg( 0x19, 0x20 ); // Configure T2 for LFO AutoTrimm 00137 write_reg( 0x1A, 0x03 ); // T2 reload value for LFO AutoTrimm 00138 write_reg( 0x1B, 0xFF ); 00139 write_reg( 0x1E, 0x00 ); // Configure T3 (for LPCD/ AutoTrimm) 00140 write_reg( 0x02, 0x90 ); // Set FiFo-Size and Waterlevel 00141 write_reg( 0x03, 0xFE ); 00142 write_reg( 0x0C, 0x80 ); // Init. RxBitCtrl register 00143 write_reg( 0x28, 0x80 ); 00144 write_reg( 0x29, 0x00 ); // Init. TxAmp register 00145 write_reg( 0x2A, 0x01 ); // Init. DrvCon register 00146 write_reg( 0x2B, 0x05 ); // Init. TxI register 00147 write_reg( 0x34, 0x00 ); // Init RxSOFD register 00148 write_reg( 0x38, 0x12 ); // Init. RCV register 00149 00150 //> Terminate any running command. Flush_FiFo 00151 terminate_and_flush_FiFo(); 00152 00153 // Clear all IRQ 0,1 flags 00154 clear_IRQ(); 00155 00156 // Write in FIFO "Load protocol" params(TxProtocol=Iso15693(0a), 0xRxProtocol=Iso15693(0a), 00157 write_reg( 0x05, 0x0A ); 00158 write_reg( 0x05, 0x0A ); 00159 00160 // Idle interrupt(Command terminated), RC663_BIT_IDLEIRQ=0x10 00161 r = read_reg( 0x08 ); 00162 write_reg( 0x08, 0x10 ); // Enable IRQ0, 0xIRQ1 interrupt sources 00163 00164 // Enable Global IRQ propagation. 00165 r = read_reg( 0x09 ); 00166 write_reg( 0x09, 0x40 ); 00167 wait(0.001); 00168 r = read_reg( 0x09 ); 00169 00170 //> Start RC663 command "Load Protocol"=0x0d 00171 write_reg( 0x00, 0x0D ); // Execute Rc663 command: "Load protocol" 00172 00173 //SLP 100 00174 wait(0.1); 00175 00176 // Disable Irq 0,1 sources 00177 disable_IRQ(); 00178 00179 write_reg( 0x02, 0xB0 ); // Flush FIFO 00180 00181 //> Apply RegisterSet 00182 write_reg( 0x2C, 0x7B ); 00183 write_reg( 0x2D, 0x7B ); 00184 write_reg( 0x2E, 0x08 ); 00185 write_reg( 0x2F, 0x00 ); 00186 write_reg( 0x30, 0x00 ); 00187 write_reg( 0x31, 0x00 ); 00188 write_reg( 0x33, 0x0F ); 00189 write_reg( 0x35, 0x02 ); 00190 write_reg( 0x37, 0x4E ); 00191 write_reg( 0x39, 0x04 ); 00192 write_reg( 0x36, 0x8C ); // Set the RxWait register 00193 write_reg( 0x31, 0xC0 ); 00194 write_reg( 0x32, 0x00 ); 00195 00196 // Write Timer-0, 0xTimer-1 reload values(high,low) 00197 write_reg( 0x10, 0x18 ); 00198 write_reg( 0x11, 0x86 ); 00199 write_reg( 0x15, 0x00 ); 00200 write_reg( 0x16, 0x00 ); 00201 write_reg( 0x29, 0x0A ); 00202 write_reg( 0x28, 0x81 ); 00203 write_reg( 0x0B, 0x00 ); // Disable MIFARE Crypto1 00204 00205 //> ============================================= 00206 //> FieldOn 00207 //> ============================================= 00208 write_reg( 0x28, 0x89 ); 00209 wait(0.1); 00210 00211 //> ============================================= 00212 //> ActivateCard 00213 //> ============================================= 00214 00215 // Set short timeout. Timer-0,Timer-1 reload values(hi,lo) 00216 write_reg( 0x10, 0x24 ); 00217 write_reg( 0x11, 0xEB ); 00218 write_reg( 0x15, 0x00 ); 00219 write_reg( 0x16, 0x00 ); 00220 00221 //> Terminate any running command. Flush_FiFo 00222 terminate_and_flush_FiFo(); 00223 00224 // Clear all IRQ 0,1 flags 00225 clear_IRQ(); 00226 00227 // Write: "Flags" and "Inventory" cmd in FIFO 00228 write_reg( 0x05, 0x36 ); 00229 write_reg( 0x05, 0x01 ); 00230 write_reg( 0x05, 0x00 ); 00231 write_reg( 0x05, 0x00 ); 00232 00233 // Start tranceive command 00234 start_tranceive(); 00235 00236 //> Wait until the command is finished. Enable IRQ sources. 00237 wait_command_and_enable_IRQ(); 00238 00239 while (w == 0){ 00240 pc.printf("\nNO CARD DETECTED...\n"); 00241 pc.printf("WAITING FOR A CARD...\n"); 00242 00243 led[3] = 0; 00244 led[2] = 0; 00245 led[0] = 0; 00246 led[1] = 1; 00247 00248 w++; 00249 } 00250 00251 } while ( read_reg( 0x40 == 0 ) ); 00252 00253 // Disable IRQ0,IRQ1 interrupt sources 00254 disable_IRQ(); 00255 00256 // Read IRQ 0,1 Status register 00257 read_IRQ_status(); 00258 00259 //> Read FIFO, 0xUID 00260 r = read_reg( 0x04 ); 00261 00262 pc.printf("\nUID = %02X ", UID1 = read_reg( 0x05 )); 00263 00264 pc.printf("%02X ", UID2 = read_reg( 0x05 )); 00265 00266 pc.printf("%02X ", UID3 = read_reg( 0x05 )); 00267 00268 pc.printf("%02X ", UID4 = read_reg( 0x05 )); 00269 00270 pc.printf("%02X ", UID5 = read_reg( 0x05 )); 00271 00272 pc.printf("%02X ", UID6 = read_reg( 0x05 )); 00273 00274 pc.printf("%02X ", UID7 = read_reg( 0x05 )); 00275 00276 pc.printf("%02X ", UID8 = read_reg( 0x05 )); 00277 00278 pc.printf("%02X ", UID9 = read_reg( 0x05 )); 00279 00280 pc.printf("%02X\n ", UID10 = read_reg( 0x05 )); 00281 00282 // Read IRQ 0,1 Status register 00283 read_IRQ_status(); 00284 00285 // Read Error status register 00286 r = read_reg( 0x0A ); // Response: 00 00287 00288 r = read_reg( 0x2E ); // Response: 08 00289 write_reg( 0x2E, 0x08 ); 00290 r = read_reg( 0x0C ); // Response: 80 00291 r = read_reg( 0x2E ); // Response: 08 00292 write_reg( 0x2E, 0x08 ); 00293 00294 led[3] = 0; 00295 led[1] = 0; 00296 led[0] = 0; 00297 led[2] = 1; 00298 00299 } while( (read_reg( 0x05 ) & 0x04) == 0 ); 00300 00301 00302 //> ============================================= 00303 //> Apply Waiting time 00304 //> ============================================= 00305 00306 write_reg( 0x10, 0x20 ); 00307 write_reg( 0x11, 0xFF ); 00308 write_reg( 0x15, 0x00 ); 00309 write_reg( 0x16, 0x00 ); 00310 00311 r = read_reg( 0x0E ); // Response: 00 00312 00313 // Clear all IRQ1 flags 00314 write_reg( 0x07, 0x7F ); 00315 00316 led[3] = 0; 00317 led[0] = 0; 00318 led[1] = 0; 00319 led[2] = 1; 00320 00321 } 00322 }
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