main.cpp

00001 #include "mbed.h"
00002 
00003 SPI spi(p11, p12, p13); // mosi, miso, sclk
00004 DigitalOut cs(p28); // chip select
00005 DigitalOut ifsel1(p26); // interface select pin for  CLRC6630
00006 DigitalOut pdres(p27); // CLRC6630 RESET pin - H = RESET
00007 DigitalOut led[] = {(LED1) , (LED2) , (LED3) , (LED4)}; // onboard LEDs
00008 Serial pc(USBTX, USBRX); // tx, rx
00009 
00010 char r;
00011 int w = 0;
00012 //char ATQB0 , ATQB1 , ATQB2 , ATQB3 , ATQB4, ATQB5 , ATQB6 , ATQB7 , ATQB8 , ATQB9, ATQB10 , ATQB11 , ATQB12 , ATQB13 , ATQB14, ATQB15 , ATQB16 , ATQB17 , ATQB18;
00013 
00014  
00015 //write SPI registers    
00016 void write_reg(char n, char o)
00017 {
00018  
00019     cs=0; // device select
00020     
00021     spi.write (n<<1);
00022     spi.write (o);
00023     
00024     cs=1; // device deselect
00025  }
00026  
00027 
00028 // read SPI registers
00029 char read_reg(char n)
00030 {
00031     char t;
00032     cs=0; // device select
00033     
00034     
00035     spi.write ((n<<1)|0x01);
00036     t=spi.write (0);
00037         
00038     cs=1; // device deselect
00039     
00040     return t;
00041  }
00042  
00043 
00044 //> Terminate any running command. Flush_FiFo
00045 void terminate_and_flush_FiFo()
00046 {
00047    write_reg( 0x00, 0x00 );
00048    write_reg( 0x02, 0xB0 );
00049 }
00050 
00051 
00052 // Clear all IRQ 0,1 flags
00053 void clear_IRQ()
00054 {
00055    write_reg( 0x06, 0x7F );
00056    write_reg( 0x07, 0x7F );
00057 } 
00058 
00059 
00060 // Disable Irq 0,1 sources
00061 void disable_IRQ()
00062 {
00063    write_reg( 0x08, 0x00 );       
00064    write_reg( 0x09, 0x00 );
00065 }
00066 
00067 
00068 //> Wait until the command is finished. Enable IRQ sources.
00069 void wait_command_and_enable_IRQ()
00070 {
00071    write_reg( 0x08, 0x18 );         // Enable Irqs 0,1
00072    write_reg( 0x09, 0x42 );         // Enable the global IRQ to be propagated to the IRQ pin
00073             
00074    while( (read_reg( 0x07 ) & 0x40)==0);
00075 }
00076 
00077 
00078 // Read IRQ 0,1 Status register
00079 void read_IRQ_status()
00080 {
00081    r = read_reg( 0x06 );
00082    r = read_reg( 0x07 );
00083 }
00084 
00085 
00086 // Start tranceive command
00087 void start_tranceive()
00088 {
00089     write_reg( 0x00, 0x07 );
00090     wait(0.001);
00091 }
00092 
00093  
00094  int main() {
00095     
00096         //  start activity LED;
00097         led[3] = 0;
00098         led[2] = 0;
00099         led[1] = 0;
00100         led[0] = 1;
00101                 
00102         // set the comunication method
00103         //ifsel1 = 0; // usare questa istruzione per le schede revisione prototipo
00104         ifsel1 = 1; // usare questa istruzione per le schede revisione B
00105         wait(0.001);
00106     
00107         // SPI comunication settings
00108         spi.format(8,0);
00109         spi.frequency(1000000);
00110 do {                          
00111         //RESET the device
00112         pdres = 1;
00113         wait(0.001);
00114         pdres = 0;
00115     
00116         wait(0.005);
00117                 
00118 //> Load Protocol
00119 write_reg( 0x0F, 0x98 ); //    Timer0 Timer starts at the end of transmission
00120 write_reg( 0x37, 0xFF );
00121 write_reg( 0x14, 0x92 ); //Timer1 Timer starts at the end of transmission
00122 write_reg( 0x19, 0x20 ); //Timer2
00123 write_reg( 0x1A, 0x03 ); //TReload Hi
00124 write_reg( 0x1B, 0xFF ); //TReload Lo
00125 write_reg( 0x1E, 0x00 ); //Timer3
00126 write_reg( 0x02, 0x90 ); //FIFO control register ->sets FIFO size to 255bytes
00127 write_reg( 0x03, 0xFE ); //Waterlevel settings
00128 write_reg( 0x0C, 0x80 ); //RXBitCtrl (Values AfterColl)
00129 write_reg( 0x28, 0x87 ); //DrvMode_Reg both driver pins enable, invert one driver
00130 write_reg( 0x29, 0xCC ); //00  TXAmp_Reg: set continous wave amplitude, set residual carrier
00131 write_reg( 0x2A, 0x01 ); //DrvCon_Reg: sets driver config to TXEnvelope
00132 write_reg( 0x2B, 0x05 ); //Txl_Reg: sets iiLoad, was auch immer das ist
00133 write_reg( 0x34, 0x00 ); //RxSofD_Reg: Subcarrier and SOF detection off
00134 write_reg( 0x38, 0x12 ); //Rcv_Reg: defines input for signal processing and defines collision level
00135 
00136 write_reg( 0x00, 0x00 ); //Idle commmand
00137 wait(0.02);
00138 
00139 write_reg( 0x02, 0xB0 ); //FIFO Control
00140 
00141 write_reg( 0x06, 0x7F ); //IRQ0_Reg:
00142 write_reg( 0x07, 0x7F ); //IRQ1_Reg:
00143 write_reg( 0x05, 0x04 ); // write Tx and RX protocol numbers (04 for ISO14443B)
00144 write_reg( 0x05, 0x04 ); // write Tx and RX protocol numbers (04 for ISO14443B)
00145 write_reg( 0x08, 0x10 ); //IRQ0En_Reg: IdleIrq is enable propagated to GlobalIRQ
00146 write_reg( 0x09, 0x40 ); //IRQ1En_Reg: GlobalIrq propagated to the interrupt pin
00147 write_reg( 0x00, 0x0D ); //LoadProtocol
00148 wait(0.02);
00149 
00150 write_reg( 0x08, 0x00 ); //Reset IRQ0
00151 write_reg( 0x09, 0x00 ); //Reset IRQ1
00152 write_reg( 0x02, 0xB0 ); //FIFO Control 
00153 
00154 // Init registers.
00155 write_reg( 0x2C, 0x7B ); 
00156 write_reg( 0x2D, 0x7B ); 
00157 write_reg( 0x2E, 0x08 );
00158 write_reg( 0x2F, 0x0A ); //00 
00159 write_reg( 0x30, 0x00 );
00160 write_reg( 0x31, 0x01 );
00161 write_reg( 0x33, 0x05 ); //05
00162 write_reg( 0x34, 0xB2 );
00163 write_reg( 0x35, 0x34 );
00164 write_reg( 0x37, 0x3F ); //3F
00165 write_reg( 0x38, 0x12 ); // 12
00166 write_reg( 0x39, 0x0A ); //0A 
00167 // End of load protocol
00168 
00169         //  start activity LED;
00170         led[3] = 0;
00171         led[2] = 0;
00172         led[1] = 1;
00173         led[0] = 0;
00174 
00175 //> ==============================================
00176 //> Field Reset
00177 //> ==============================================
00178 
00179 // Field off: Read out DrvMod register. Disable Drivers
00180 r = read_reg( 0x28 );   // Response:  87
00181   
00182 write_reg( 0x47, 0x04 );    // DEBUG
00183 //> phhalHw_FieldOn
00184 write_reg( 0x28, 0x8F );
00185 //SLP 100
00186 wait(0.02);
00187 
00188 //> Send REQB command
00189 write_reg( 0x31, 0xC1 );
00190 write_reg( 0x32, 0x0B );
00191 write_reg( 0x00, 0x00 );
00192 write_reg( 0x02, 0xB0 );
00193 write_reg( 0x06, 0x7F );
00194 write_reg( 0x07, 0x7F );
00195 
00196 write_reg( 0x05, 0x06 );  // SR176 
00197 write_reg( 0x05, 0x00 );
00198 
00199 /*write_reg( 0x05, 0x00 );  // GMTL
00200 write_reg( 0x05, 0x0B );
00201 write_reg( 0x05, 0x3F ); 
00202 write_reg( 0x05, 0x80 ); */
00203 
00204 /*write_reg( 0x05, 0x05 ); //ISO14443B
00205 write_reg( 0x05, 0x00 );
00206 write_reg( 0x05, 0x00 );*/
00207 
00208 write_reg( 0x00, 0x07 ); // Response:  00
00209 
00210 //SLP 100
00211 wait(0.02);
00212 
00213 //RE 04 0C    // Read FIFOLevel (12 bytes)
00214 r = read_reg( 0x04 );
00215 //if (r != 0x1B) return;
00216 
00217 if( r != 0 )
00218     {
00219     //  start activity LED;
00220     led[3] = 1;
00221     led[2] = 0;
00222     led[1] = 0;
00223     led[0] = 0;
00224     pc.printf("received = 0x%02X bytes: ",  r);
00225     while( read_reg( 0x04 ) )
00226         {
00227         pc.printf("%02X ", r = read_reg( 0x05 ));
00228         }
00229         pc.printf("\r\n",  r);
00230     }
00231     else
00232         pc.printf("NO CARD\r\n");
00233         
00234 } while( -1 );       
00235 }