main.cpp

00001 #include "mbed.h"
00002 
00003 SPI spi(p11, p12, p13); // mosi, miso, sclk
00004 DigitalOut cs(p28); // chip select
00005 DigitalOut ifsel1(p26); // interface select pin for  CLRC6630
00006 DigitalOut pdres(p27); // CLRC6630 RESET pin - H = RESET
00007 DigitalOut led[] = {(LED1) , (LED2) , (LED3) , (LED4)}; // onboard LEDs
00008 Serial pc(USBTX, USBRX); // tx, rx
00009 
00010 char r;
00011 int w = 0;
00012 char UID0 , UID1 , UID2 , UID3 , UID4;
00013 
00014  
00015 //write SPI registers    
00016 void write_reg(char n, char o)
00017 {
00018  
00019     cs=0; // device select
00020     
00021     spi.write (n<<1);
00022     spi.write (o);
00023     
00024     cs=1; // device deselect
00025  }
00026  
00027 
00028 // read SPI registers
00029 char read_reg(char n)
00030 {
00031     char t;
00032     cs=0; // device select
00033     
00034     
00035     spi.write ((n<<1)|0x01);
00036     t=spi.write (0);
00037         
00038     cs=1; // device deselect
00039     
00040     return t;
00041  }
00042  
00043 
00044 //> Terminate any running command. Flush_FiFo
00045 void terminate_and_flush_FiFo()
00046 {
00047    write_reg( 0x00, 0x00 );
00048    write_reg( 0x02, 0xb0 );
00049 }
00050 
00051 
00052 // Clear all IRQ 0,1 flags
00053 void clear_IRQ()
00054 {
00055    write_reg( 0x06, 0x7f );
00056    write_reg( 0x07, 0x7f );
00057 } 
00058 
00059 
00060 // Disable Irq 0,1 sources
00061 void disable_IRQ()
00062 {
00063    write_reg( 0x08, 0x00 );       
00064    write_reg( 0x09, 0x00 );
00065 }
00066 
00067 
00068 //> Wait until the command is finished. Enable IRQ sources.
00069 void wait_command_and_enable_IRQ()
00070 {
00071    write_reg( 0x08, 0x18 );         // Enable Irqs 0,1
00072    write_reg( 0x09, 0x42 );         // Enable the global IRQ to be propagated to the IRQ pin
00073             
00074    while( (read_reg( 0x07 ) & 0x40)==0);
00075 }
00076 
00077 
00078 // Read IRQ 0,1 Status register
00079 void read_IRQ_status()
00080 {
00081    r = read_reg( 0x06 );
00082    r = read_reg( 0x07 );
00083 }
00084 
00085 
00086 // Start tranceive command
00087 void start_tranceive()
00088 {
00089     write_reg( 0x00, 0x07 );
00090     wait(0.001);
00091 }
00092 
00093  
00094  int main() {
00095     
00096     while (1) {
00097     
00098         //  start activity LED;
00099         led[3] = 0;
00100         led[2] = 0;
00101         led[1] = 0;
00102         led[0] = 1;
00103                 
00104         // set the comunication method
00105         //ifsel1 = 0; // usare questa istruzione per le schede revisione prototipo
00106         ifsel1 = 1; // usare questa istruzione per le schede revisione B
00107         wait(0.001);
00108     
00109         // SPI comunication settings
00110         spi.format(8,0);
00111         spi.frequency(1000000);
00112     
00113             do {
00114                               
00115                 w = 0;
00116     
00117                     do {
00118                     
00119                     wait(0.1);
00120                     
00121                     //RESET the device
00122                     pdres = 1;
00123                     wait(0.001);
00124                     pdres = 0;
00125     
00126                     wait(0.005);
00127         
00128 //> =============================================
00129 //> RC663 Script for (Iso14443-3A protocol):
00130 //>   * ReqA
00131 //>   * Get UID (Select: Casade level 1)
00132 //>   * HaltA 
00133 //> 
00134 //> Note: Only one PICC shall be in HF
00135 //> =============================================
00136 
00137 //> =============================================
00138 //> RC663 ApplyProtocolSettings:  ISO14443A=01
00139 //> =============================================
00140 //
00141 //> Configure Timers 
00142 //
00143 // Set Timer-0, T0Control_Reg:
00144 // Starts at the end of Tx. Stops after Rx of first data. Auto-reloaded. 13.56 MHz input clock.
00145    write_reg( 0x0F, 0x98 );    
00146 
00147 // Set Timer-1, T1Control_Reg:
00148 // Starts at the end of Tx. Stops after Rx of first data. Input clock - cascaded with Timer-0.
00149    write_reg( 0x14, 0x92 );
00150    
00151 // Set Timer-2, T2Control_Reg:  Timer used for LFO trimming
00152    write_reg( 0x19, 0x20 );
00153                 
00154 // Set Timer-2 reload value (T2ReloadHi_Reg and T2ReloadLo_Reg)
00155    write_reg( 0x1A, 0x03 );
00156    write_reg( 0x1B, 0xFF );                            
00157     
00158 // Set Timer-3, T3Control_Reg:
00159 // Not started automatically. Not reloaded. Input clock 13.56 MHz                
00160    write_reg( 0x1E, 0x00 );
00161                             
00162 //> Configure FIFO Size=255 and Water-level
00163 // Set FifoControl_Reg, Fifo size=255 bytes. Flush FIFO
00164    write_reg( 0x02, 0x90 );            
00165     
00166 // Set WaterLevel =(FIFO length -1)
00167    write_reg( 0x03, 0xFE );
00168                         
00169 // RxBitCtrl_Reg(0x0c)    Received bit after collision are replaced with 1.
00170    write_reg( 0x0C, 0x80 );
00171     
00172 // DrvMod reg(0x28), Tx2Inv=1
00173    r = read_reg( 0x28  );    
00174    write_reg( 0x28, 0x80 );
00175                 
00176 // TxAmp_Reg(0x29)
00177    write_reg( 0x29, 0x00 );                
00178    
00179 // DrvCon_Reg(0x2A)
00180    write_reg( 0x2A, 0x01 );     
00181    
00182 // TxI_Reg(0x05),(0x05)
00183    write_reg( 0x2B, 0x05 );
00184                 
00185 // RxSOFD_Reg(0x34),(0x00), 
00186    write_reg( 0x34, 0x00 );
00187     
00188 // Rcv_Reg(0x38),(0x12) 
00189    write_reg( 0x38, 0x12 );
00190 //
00191 //> =============================================
00192 //> 2. LoadProtocol( bTxProtocol=0, bRxProtocol=0)
00193 //> =============================================
00194 
00195 //> Terminate any running command. Flush_FiFo
00196    terminate_and_flush_FiFo();
00197 
00198 // Clear all IRQ 0,1 flags
00199    clear_IRQ();
00200    
00201 //> Write in Fifo: Tx and Rx protocol numbers(0,0) 
00202    r = read_reg( 0x04 );
00203    write_reg( 0x05, 0x00 );    // Rx protocol=0
00204    write_reg( 0x05, 0x00 );    // Tx prot=0
00205 
00206 // Enable IRQ0 interrupt sources 
00207 // 
00208 // Idle interrupt(Command terminated), RC663_BIT_IDLEIRQ=0x10
00209    r = read_reg( 0x08 );
00210    write_reg( 0x08, 0x10 );
00211          
00212 // Enable Global IRQ propagation.
00213    r = read_reg( 0x09 );
00214    write_reg( 0x09, 0x40 );
00215    wait(0.001);
00216    r = read_reg( 0x09 );   
00217 
00218 //> Start RC663 command "Load Protocol"=0x0d
00219    write_reg( 0x00, 0x0D );
00220 
00221 //L_LoadProtocol
00222 
00223    while( (read_reg( 0x07 ) & 0x40)==0);
00224    
00225 // Disable Irq 0,1 sources
00226    disable_IRQ();
00227 
00228 //> Flush Fifo. Read Error Reg
00229    write_reg( 0x02, 0xB0 );
00230    r = read_reg( 0x0A );
00231 
00232 // Apply RegisterSet
00233 //
00234 //> Configure CRC-16 calculation, preset value(0x6363) for Tx&Rx
00235    write_reg( 0x2C, 0x18 );
00236    write_reg( 0x2D, 0x18 );
00237    write_reg( 0x2E, 0x08  );
00238 
00239 // Length of the pulse modulation in carrier clks+1  
00240    write_reg( 0x2F, 0x20 );
00241    
00242 // Symbol 1 and 0 burst lengths = 8 bits.
00243    write_reg( 0x30, 0x00 );
00244    
00245 // Start symbol=Symbol2, Stop symbol=Symbol3
00246    write_reg( 0x33, 0xCF );
00247  
00248 // Set Rx Baudrate 106 kBaud    
00249    write_reg( 0x35, 0x04 );
00250   
00251 // Set min-levels for Rx and phase shift   
00252    write_reg( 0x37, 0x32 );
00253    write_reg( 0x39, 0x00 );
00254                  
00255 // Set Rx waiting time  
00256    write_reg( 0x36, 0x90 );
00257    write_reg( 0x31, 0xC0 );
00258    write_reg( 0x32, 0x0B );
00259 
00260 // Set Timeout. Write T0,T1 reload values(hi,Low)
00261    write_reg( 0x10, 0x08 );
00262    write_reg( 0x11, 0xD8 );
00263    write_reg( 0x15, 0x00 );
00264    write_reg( 0x16, 0x00 );
00265    
00266 // Write DrvMod register   
00267    write_reg( 0x28, 0x81 );
00268    
00269 //> MIFARE Crypto1 state is further disabled.
00270    write_reg( 0x0B, 0x00 );
00271 
00272 //>  FieldOn
00273    write_reg( 0x28, 0x89 );
00274    
00275    wait(0.005);
00276    
00277 //> =============================================
00278 //>  I14443p3a_Sw_RequestA
00279 //> =============================================
00280    
00281 //  TxWaitStart at the end of Rx data
00282    write_reg( 0x31, 0xC0 );
00283    
00284 // Set min.time between Rx and Tx or between two Tx   
00285    write_reg( 0x32, 0x0B );
00286          
00287 //> Set timeout for this command cmd. Init reload values for timers-0,1 
00288    write_reg( 0x10, 0x08 );
00289    write_reg( 0x11, 0x94 );
00290    write_reg( 0x15, 0x00 );           
00291    write_reg( 0x16, 0x00 );
00292    write_reg( 0x06, 0x08 );
00293    write_reg( 0x36, 0x90 );
00294    write_reg( 0x2E, 0x0F );    
00295 
00296 //> ---------------------
00297 //> Send the ReqA command  
00298 //> ---------------------
00299 
00300 //> Terminate any running command. FlushFifo
00301    terminate_and_flush_FiFo();      
00302 
00303 // Clear all IRQ 0,1 flags 
00304    clear_IRQ();
00305 
00306 //> Write ReqA=26 into FIFO
00307    write_reg( 0x05, 0x26 );    
00308 
00309 //> Start RC663 command "Transcieve"=0x07. Activate Rx after Tx finishes.
00310    write_reg( 0x00, 0x07 );
00311    
00312 //> Wait until the command is finished. Enable IRQ sources.
00313    wait_command_and_enable_IRQ();
00314    
00315 // Disable Irq 0,1 sources
00316    disable_IRQ();       
00317    
00318 // Return Irq0 status    
00319    r = read_reg( 0x06 );   
00320 
00321 //> Wait until reception
00322    write_reg( 0x08, 0x54 );
00323    write_reg( 0x09, 0x42 );
00324    wait(0.001);
00325    
00326    while( (read_reg( 0x07 ) & 0x40)==0);
00327    
00328    while (w == 0){
00329    pc.printf("\nNO CARD DETECTED...\n");
00330    pc.printf("WAITING FOR A CARD...\n");
00331    w++;
00332    }
00333    
00334    } while ( read_reg( 0x40 == 0 ) );
00335    
00336    write_reg( 0x08, 0x00 );
00337    write_reg( 0x09, 0x00 );
00338       
00339    r = read_reg( 0x05 );     
00340    r = read_reg( 0x05 );    
00341                
00342 // Read the error register            
00343    r = read_reg( 0x0a );            
00344 
00345 // Reset TxLastBits_Reg
00346    write_reg( 0x2E, 0x08 );
00347 
00348 //> ------------------------------
00349 //> Get UID cascade level-1
00350 //> ------------------------------               
00351    write_reg( 0x2E, 0x08 );
00352    write_reg( 0x0C, 0x00 );
00353 
00354 // Terminate any running command, FlushFifo
00355    terminate_and_flush_FiFo();
00356 
00357 // Clear all IRQ 0,1 flags 
00358     clear_IRQ();
00359       
00360 //> Write "Antcollision CL 1" cmd into FIFO (SEL=93, NVB=20)
00361     write_reg( 0x05, 0x93 );
00362     write_reg( 0x05, 0x20 );
00363       
00364 // Start tranceive command
00365    start_tranceive();
00366     
00367 // Wait until the command is finished 
00368    wait_command_and_enable_IRQ();
00369     
00370 // Disable IRQ0 interrupt sources
00371    disable_IRQ();
00372           
00373 // Read IRQ 0,1 Status register        
00374    read_IRQ_status();    
00375   
00376 //> Read FIFO, Expected - Complete UID (one PICC in HF)
00377     r = read_reg( 0x04 );            // FIFO length
00378    
00379     // Cascade Tag (UID0)
00380     pc.printf("\nUID = 0x%02X",  UID0 = read_reg( 0x05 ));
00381         
00382     // UID1
00383     pc.printf("%02X",  UID1 = read_reg( 0x05 ));
00384         
00385     // UID2
00386     pc.printf("%02X",  UID2 =read_reg( 0x05 ));
00387         
00388     // UID3
00389     pc.printf("%02X\n",  UID3 =read_reg( 0x05 ));
00390        
00391     // BCC
00392     pc.printf("BCC = 0x%02X\n",  UID4 =read_reg( 0x05 ));
00393        
00394     led[1] = 1;
00395     
00396     w = 1;
00397 
00398 //> Read Error register       
00399     r = read_reg( 0x0A );
00400     
00401 //> ------------------------------
00402 //> Select cascade level-1
00403 //> ------------------------------               
00404 // Terminate any running command, FlushFifo
00405    terminate_and_flush_FiFo();
00406    
00407    write_reg( 0x2C, 0x19 );          // Enable RX and TX CRC
00408    write_reg( 0x2D, 0x19 ); 
00409    write_reg( 0x0C, 0x00 ); 
00410 
00411 
00412 // Clear all IRQ 0,1 flags 
00413    clear_IRQ();
00414       
00415 //> Write "Select CL 1" cmd into FIFO (SEL=93, NVB=70)
00416    write_reg( 0x05, 0x93 );
00417    write_reg( 0x05, 0x70 );
00418    write_reg( 0x05, UID0 );          // UID bytes ...
00419    write_reg( 0x05, UID1 );
00420    write_reg( 0x05, UID2 );
00421    write_reg( 0x05, UID3 );
00422    write_reg( 0x05, UID4 );
00423       
00424 // Start tranceive command 
00425    start_tranceive();
00426 
00427 // Wait until the command is finished 
00428    wait_command_and_enable_IRQ();
00429       
00430 // Disable IRQ0 interrupt sources
00431    disable_IRQ();
00432           
00433 // Read IRQ 0,1 Status register        
00434    read_IRQ_status();
00435       
00436 //> Read FIFO, Expected - Complete UID (one PICC in HF)
00437    r = read_reg( 0x04 );             // FIFO length
00438    
00439    } while( (read_reg( 0x05 ) & 0x04) == 0 );
00440 
00441    pc.printf("7 BYTE CARD DETECTED\n");
00442    
00443    led[2] = 1;
00444    
00445 //----------------------------------------------------------------------------------------
00446 //----------------------------------------------------------------------------------------
00447 //> ------------------------------
00448 //> Get UID cascade level-2
00449 //> ------------------------------               
00450    write_reg( 0x2E, 0x08 );
00451    write_reg( 0x0C, 0x00 );
00452    write_reg( 0x2C, 0x18 );       // TX, RX CRC off
00453    write_reg( 0x2D, 0x18 ); 
00454 
00455 // Terminate any running command, FlushFifo
00456    terminate_and_flush_FiFo();
00457 
00458 // Clear all IRQ 0,1 flags 
00459    clear_IRQ();
00460       
00461 //> Write "Antcollision CL 2" cmd into FIFO (SEL=95, NVB=20)
00462    write_reg( 0x05, 0x95 );
00463    write_reg( 0x05, 0x20 );
00464       
00465 // Start tranceive command 
00466    start_tranceive();   
00467 
00468 // Wait until the command is finished 
00469    wait_command_and_enable_IRQ();   
00470    
00471 // Disable IRQ0 interrupt sources
00472    disable_IRQ();
00473           
00474 // Read IRQ 0,1 Status register        
00475    read_IRQ_status();    
00476   
00477 //> Read FIFO
00478    r = read_reg( 0x04 );             // FIFO length
00479    
00480    // Cascade Tag (UID0)
00481     pc.printf("UID = 0x%02X",  UID0 = read_reg( 0x05 ));
00482         
00483     // UID1
00484     pc.printf("%02X",  UID1 = read_reg( 0x05 ));   
00485     
00486     // UID2
00487     pc.printf("%02X",  UID2 =read_reg( 0x05 ));   
00488     
00489     // UID
00490     pc.printf("%02X\n",  UID3 =read_reg( 0x05 ));   
00491     
00492     // BCC
00493     pc.printf("BCC = 0x%02X\n",  UID4 =read_reg( 0x05 ));
00494     
00495     led[3] = 1;
00496 
00497 //> Read Error register       
00498    r = read_reg( 0x0A );   
00499 
00500 //> ------------------------------
00501 //> Select cascade level-2
00502 //> ------------------------------               
00503 // Terminate any running command, FlushFifo
00504    terminate_and_flush_FiFo();
00505    
00506    write_reg( 0x2C, 0x19 );          // Enable RX and TX CRC
00507    write_reg( 0x2D, 0x19 ); 
00508    write_reg( 0x0C, 0x00 ); 
00509 
00510 // Clear all IRQ 0,1 flags 
00511    clear_IRQ();
00512       
00513 //> Write "Select CL 2" cmd into FIFO (SEL=95, NVB=70)
00514    write_reg( 0x05, 0x95 );
00515    write_reg( 0x05, 0x70 );
00516    write_reg( 0x05, UID0 );          // UID bytes ...
00517    write_reg( 0x05, UID1 );
00518    write_reg( 0x05, UID2 );
00519    write_reg( 0x05, UID3 );
00520    write_reg( 0x05, UID4 );
00521       
00522 // Start tranceive command 
00523    start_tranceive();
00524 
00525 // Wait until the command is finished 
00526    wait_command_and_enable_IRQ();
00527       
00528 // Disable IRQ0 interrupt sources
00529    disable_IRQ();
00530           
00531 // Read IRQ 0,1 Status register
00532    read_IRQ_status();
00533   
00534 //> Read FIFO
00535    r = read_reg( 0x04 );              // FIFO length
00536    
00537    r = read_reg( 0x05 );              // Response
00538   
00539    led[3] = 1 ;
00540 
00541     }
00542 }