Revision 1:f468352a5408, committed 2014-05-04

Comitter:

shinbo

Date:

Sun May 04 04:43:19 2014 +0000

Parent:

0:cb6ecbfcf585

Child:

2:849b0ab61874

Commit message:

-

Changed in this revision

--- a/main.cpp	Sun Mar 30 19:34:20 2014 +0000
+++ b/main.cpp	Sun May 04 04:43:19 2014 +0000
@@ -1,6 +1,6 @@
 #include "mbed.h"
 
-// this program control CS8416 in software mode(SPI) with LPC1114FN2.
+// this program control CS8416 in software mode(SPI) with LPC1114FN28.
 
 // CS8416 : 192 kHz Digital Audio Interface Receiver
 // http://www.cirrus.com/jp/pubs/proDatasheet/CS8416_F3.pdf
@@ -50,12 +50,32 @@
 
 
 const uint8_t DEF_REGVAL[10] = {
-    0x00,   // 0x00 : Control0
-    0x00,   // 0x01 : Control1
-    0x48,   // 0x02 : Control2                  // EMPH_CNTL[2:0]=deemphasis filter auto select, GPO0SEL[3:0]=(96KHZ)
-    0x00,   // 0x03 : Control3
-    0x80,   // 0x04 : Control4                  // RUN=normal part operation
-    0x85,   // 0x05 : Serial Audio Data Format  // SOMS=master mode, SODEL=second OSCLK period, SOLRPOL=right channel when OLRCK is high.
+    0x04,   // [0] Control0                  
+    // TRUNC=1 - Incoming data is truncated according to the length specified in the channel status data.
+    
+    0x80,   // [1] Control1                  
+    // SWCLK=1 - Enable automatic clock switching on PLL unlock. OMCK clock input is automatically output on RMCK on PLL Unlock.
+    // MUTESAO=0 - SDOUT not muted.
+    // HOLD[1:0]=00 - hold last audio sample.
+    
+    0x45,   // [2] Control2                  
+    // EMPH_CNTL[2:0]=100 - deemphasis filter auto select.
+    // GPO0SEL[3:0]=0101 - RERR/Receiver Error
+
+    0x00,   // [3] Control3
+
+    0x80,   // [4] Control4                  
+    // RUN=1 - normal part operation
+
+    0x85,   // [5] Serial Audio Data Format
+    // SOMS=1 - Serial audio output port is in master mode. OSCLK and OLRCK are outputs.
+    // SOSF=0 - OSCLK output frequency is 64*Fs.
+    // SORES[1:0]=00 - 24-bit resolution.
+    // SOJUST=0 - Left-Justified.
+    // SODEL=1 - second OSCLK period.
+    // SOSPOL=0 - SDOUT is sampled on rising edges of OSCLK.
+    // SOLRPOL=1 - right channel when OLRCK is high.
+    
     0x00,   // 0x06 : Receiver Error Mask
     0x00,   // 0x07 : Interrupt Mask
     0x00,   // 0x08 : Interrupt Mode MSB
@@ -107,6 +127,18 @@
             | (0 <<  3)     // ATC (default)
             | (0 <<  2)     // MUTE (OFF/default)
             | (0      ) );  // EMPH (OFF/default)
+
+    wait_us(10);                // us
+    fn1242_write(
+              (0 << 11)     // MODE0
+            | (0 << 10)     // LDL -> disable
+            |  1023);       // 10bit
+    wait_us(10);                // us
+    fn1242_write(
+              (1 << 11)     // MODE1
+            | (0 << 10)     // LDR -> disable
+            |  1023);       // 10bit
+
 }
 
 void cs8416_write(uint8_t u8_addr, uint8_t u8_data) {
@@ -221,7 +253,11 @@
         pin_led1 = 0;
         u8_data = 0x00;             // (01h)[1] RMCKF - Recovered Master Clock Frequency @ 0 : 256 Fs
     }
-    cs8416_write(0x01, DEF_REGVAL[1] + u8_data);    // (01h) : Control1
+    
+    if (g_freq == 0) {
+        u8_data |= 0x40;             // (01h)[6] MUTESAO - Mute control for the serial audio output port
+    }
+    cs8416_write(0x01, DEF_REGVAL[1] | u8_data);    // (01h) : Control1
 }
 
 
@@ -233,7 +269,7 @@
     } else {
         u8_data = 0x00;             // (04h)[5:3] RXSEL2:0
     }
-    cs8416_write(0x04, DEF_REGVAL[4] + u8_data);    // (04h) : Control4
+    cs8416_write(0x04, DEF_REGVAL[4] | u8_data);    // (04h) : Control4
 }
 
 
@@ -246,12 +282,14 @@
     fn1242_init();
     
     while (1) {
+        uint32_t u32_freq = g_freq;
+        
         uint8_t u8_addr18 = cs8416_read(0x18);  // (18h) : OMCK/RMCK Ratio
         decide_freq(u8_addr18);
         set_led();
         
         uint8_t u8_addr0B = cs8416_read(0x0b);  // (0Bh) : Format Detect Status
-        if (g_cur_frmt != u8_addr0B) {
+        if ((g_cur_frmt != u8_addr0B) || (g_freq != u32_freq)) {
             g_cur_frmt = u8_addr0B;
             set_rmckf();
         }
@@ -264,4 +302,5 @@
         
         wait_ms(200);               // ms
     }
+
 }