main.cpp

00001 #include "beacon.h"
00002 Serial pc(USBTX, USBRX);          // tx, rx
00003 SPI spi(D11, D12, D13);              // mosi, miso, sclk
00004 DigitalOut cs(D10);                //slave select or chip select
00005 
00006 void writereg(uint8_t reg,uint8_t val)
00007 {
00008     cs = 0;__disable_irq();spi.write(reg | 0x80);spi.write(val);__enable_irq();cs = 1;
00009 }
00010 uint8_t readreg(uint8_t reg)
00011 {
00012     int val;cs = 0;__disable_irq();spi.write(reg & ~0x80);val = spi.write(0);__enable_irq();cs = 1;return val;
00013 }
00014 void clearTxBuf()
00015 {
00016     writereg(RF22_REG_08_OPERATING_MODE2,0x01);
00017     writereg(RF22_REG_08_OPERATING_MODE2,0x00);
00018 } 
00019 void clearRxBuf()
00020 {
00021     writereg(RF22_REG_08_OPERATING_MODE2,0x02);
00022     writereg(RF22_REG_08_OPERATING_MODE2,0x00);
00023 }
00024 int setFrequency(float centre,float afcPullInRange)
00025 {
00026 //freq setting begins 
00027     uint8_t fbsel = 0x40;
00028     uint8_t afclimiter;
00029     if (centre >= 480.0) {
00030         centre /= 2;
00031         fbsel |= 0x20;
00032         afclimiter = afcPullInRange * 1000000.0 / 1250.0;
00033     } else {
00034         if (afcPullInRange < 0.0 || afcPullInRange > 0.159375)
00035             return false;
00036         afclimiter = afcPullInRange * 1000000.0 / 625.0;
00037     }
00038     centre /= 10.0;
00039     float integerPart = floor(centre);
00040     float fractionalPart = centre - integerPart;
00041  
00042     uint8_t fb = (uint8_t)integerPart - 24; // Range 0 to 23
00043     fbsel |= fb;
00044     uint16_t fc = fractionalPart * 64000;
00045     writereg(RF22_REG_73_FREQUENCY_OFFSET1, 0);  // REVISIT
00046     writereg(RF22_REG_74_FREQUENCY_OFFSET2, 0);
00047     writereg(RF22_REG_75_FREQUENCY_BAND_SELECT, fbsel);
00048     writereg(RF22_REG_76_NOMINAL_CARRIER_FREQUENCY1, fc >> 8);
00049     writereg(RF22_REG_77_NOMINAL_CARRIER_FREQUENCY0, fc & 0xff);
00050     writereg(RF22_REG_2A_AFC_LIMITER, afclimiter);
00051     return 0;
00052 }
00053 void init()
00054 {
00055     //reset()
00056     writereg(RF22_REG_07_OPERATING_MODE1,0x80);        //switch_reset
00057     wait(1);                    //takes time to reset                                  
00058 
00059     clearTxBuf();                                                             
00060     clearRxBuf();                                                             
00061     //txfifoalmostempty
00062     writereg(RF22_REG_7D_TX_FIFO_CONTROL2,10);
00063     //rxfifoalmostfull
00064     writereg(RF22_REG_7E_RX_FIFO_CONTROL,20);
00065     //Packet-engine registers
00066     writereg(RF22_REG_30_DATA_ACCESS_CONTROL,0x06);    //RF22_REG_30_DATA_ACCESS_CONTROL, RF22_ENPACRX | RF22_ENPACTX | RF22_ENCRC | RF22_CRC_CRC_16_IBM
00067     //&0x77 = diasable packet rx-tx handling
00068     
00069     //writereg(RF22_REG_32_HEADER_CONTROL1,0x88);    //RF22_REG_32_HEADER_CONTROL1, RF22_BCEN_HEADER3 | RF22_HDCH_HEADER3
00070     //writereg(RF22_REG_33_HEADER_CONTROL2,0x42);    //RF22_REG_33_HEADER_CONTROL2, RF22_HDLEN_4 | RF22_SYNCLEN_2
00071     writereg(RF22_REG_34_PREAMBLE_LENGTH,4);       //RF22_REG_34_PREAMBLE_LENGTH, nibbles); preamble length = 8;
00072     writereg(RF22_REG_36_SYNC_WORD3,0x2D);    //syncword3=2D
00073     writereg(RF22_REG_37_SYNC_WORD2,0xD4);    //syncword2=D4
00074     writereg(RF22_REG_3F_CHECK_HEADER3,0);    //RF22_REG_3F_CHECK_HEADER3, RF22_DEFAULT_NODE_ADDRESS
00075     writereg(RF22_REG_3A_TRANSMIT_HEADER3,0xab);    //header_to
00076     writereg(RF22_REG_3B_TRANSMIT_HEADER2,0xbc);    //header_from 
00077     writereg(RF22_REG_3C_TRANSMIT_HEADER1,0xcd);    //header_ids
00078     writereg(RF22_REG_3D_TRANSMIT_HEADER0,0xde);    //header_flags
00079     writereg(RF22_REG_3F_CHECK_HEADER3,0xab);   
00080     writereg(RF22_REG_40_CHECK_HEADER2,0xbc);   
00081     writereg(RF22_REG_41_CHECK_HEADER1,0xcd);   
00082     writereg(RF22_REG_42_CHECK_HEADER0,0xde);
00083     
00084     //RSSI threshold for clear channel indicator
00085     writereg(RF22_REG_27_RSSI_THRESHOLD,0xA5);         //55 for -80dBm, 2D for -100dBm, 7D for -60dBm, A5 for -40dBm, CD for -20 dBm
00086     
00087     writereg(RF22_REG_0B_GPIO_CONFIGURATION0,0x15); // TX state                        ??
00088     writereg(RF22_REG_0C_GPIO_CONFIGURATION1,0x12); // RX state                        ??
00089     
00090     //interrupts
00091     // spiWrite(RF22_REG_05_INTERRUPT_ENABLE1, RF22_ENTXFFAEM |RF22_ENRXFFAFULL | RF22_ENPKSENT |RF22_ENPKVALID| RF22_ENCRCERROR);
00092     // spiWrite(RF22_REG_06_INTERRUPT_ENABLE2, RF22_ENPREAVAL);
00093     
00094     setFrequency(435.0, 0.05);
00095     
00096     //return !(statusRead() & RF22_FREQERR);
00097     if((readreg(RF22_REG_02_DEVICE_STATUS)& 0x08)!= 0x00)
00098     pc.printf("frequency not set properly\n");
00099     //frequency set
00100 
00101     //setModemConfig(FSK_Rb2_4Fd36);       FSK_Rb2_4Fd36,       ///< FSK, No Manchester, Rb = 2.4kbs,  Fd = 36kHz
00102     //setmodemregisters
00103     //0x1b, 0x03, 0x41, 0x60, 0x27, 0x52, 0x00, 0x07, 0x40, 0x0a, 0x1e, 0x80, 0x60, 0x13, 0xa9, 0x2c, 0x22, 0x3a = FSK_RB2_4FD36
00104     //0xc8, 0x03, 0x39, 0x20, 0x68, 0xdc, 0x00, 0x6b, 0x2a, 0x08, 0x2a, 0x80, 0x60, 0x13, 0xa9, 0x2c, 0x21, 0x08 = OOK,2.4, 335
00105     writereg(RF22_REG_1C_IF_FILTER_BANDWIDTH,0xdf);
00106     writereg(RF22_REG_1F_CLOCK_RECOVERY_GEARSHIFT_OVERRIDE,0x03);
00107     writereg(RF22_REG_20_CLOCK_RECOVERY_OVERSAMPLING_RATE,0x39);
00108     writereg(RF22_REG_21_CLOCK_RECOVERY_OFFSET2,0x20);                     
00109     writereg(RF22_REG_22_CLOCK_RECOVERY_OFFSET1,0x68);           //updated 20 to 25 reg values from excel sheet for 1.2 Khz freq. deviation,fsk
00110     writereg(RF22_REG_23_CLOCK_RECOVERY_OFFSET0,0xdc);
00111     writereg(RF22_REG_24_CLOCK_RECOVERY_TIMING_LOOP_GAIN1,0x00);
00112     writereg(RF22_REG_25_CLOCK_RECOVERY_TIMING_LOOP_GAIN0,0x6B);
00113     writereg(RF22_REG_2C_OOK_COUNTER_VALUE_1,0x2C);
00114     writereg(RF22_REG_2D_OOK_COUNTER_VALUE_2,0x11);    //not required for fsk (OOK counter value)
00115     writereg(RF22_REG_2E_SLICER_PEAK_HOLD,0x2A);         //??
00116     writereg(RF22_REG_58,0x80);
00117     writereg(RF22_REG_69_AGC_OVERRIDE1,0x60);
00118     writereg(RF22_REG_6E_TX_DATA_RATE1,0x09);
00119     writereg(RF22_REG_6F_TX_DATA_RATE0,0xd5);
00120     writereg(RF22_REG_70_MODULATION_CONTROL1,0x2c);
00121     writereg(RF22_REG_71_MODULATION_CONTROL2,0x21);//ook = 0x21 //fsk = 0x22
00122     writereg(RF22_REG_72_FREQUENCY_DEVIATION,0x50);
00123     //set tx power
00124     writereg(RF22_REG_6D_TX_POWER,0x07);    //20dbm
00125 }
00126 int main()
00127 {
00128     wait(1);                     // wait for POR to complete   //change the timing later
00129     cs=1;                          // chip must be deselected
00130     wait(1);                    //change the time later
00131     spi.format(8,0);
00132     spi.frequency(10000000);       //10MHz SCLK    
00133     if (readreg(RF22_REG_00_DEVICE_TYPE) == 0x08) pc.printf("spi connection valid\n");
00134     else pc.printf("error in spi connection\n");
00135 
00136     init();
00137 
00138     
00139     //init complete
00140     pc.printf("init complete.....press t to send\n");
00141     
00142     
00143     //********
00144 
00145 while(1)//pc.getc()=='t')
00146 { 
00147    /*uint8_t data[] = "Hello World!";
00148     pc.printf("%d %d %d %d %d %d %d %d %d %d %d %d",data[0],data[1],data[2],data[3],data[4],data[5],data[6],data[7],data[8],data[9],data[10],data[11],data[12]);*/
00149     
00150     uint8_t data[500];              //starts from 0,1,2,3,4!!!;   
00151     int i = 0;                           //for loops
00152     int u = 0;                           //universal count for hk array
00153     int n=0,bar = 0; 
00154     //filling hk data
00155 /* 1   for(int n=0; n<4; n++)
00156         data[n] = 0x55;
00157         data[4] = 0x2D;   
00158         data[5] = 0xD4; 
00159         data[6] = 0xab;
00160         data[7] = 0xbc;                
00161         data[8] = 0xcd;        
00162         data[9] = 0xde;
00163         data[10]= 0xa9;        
00164     for(int n=11; n<50; n++) 
00165         data[n] = 0x5A; 
00166     for(int n=50; n<60; n++)
00167         data[n] = 0x5A;  
00168     for(int n=60; n<75; n++)
00169         data[n] = 0xCC;    
00170     for(int n=75; n<97; n++)
00171         data[n] = 0xBC;
00172     for(int n=97; n<110; n++)
00173         data[n] = 0xEC;
00174     for(int n=110; n<TX_DATA; n++)
00175         data[n] = n; */
00176     for(int i=0; i<7; i++){
00177         data[n++] = 0x49;
00178         data[n++] = 0x49;
00179         data[n++] = 0x54;
00180         data[n++] = 0x4D;
00181         data[n++] = 0x53;
00182         data[n++] = 0x41;
00183         data[n++] = 0x54;
00184         }
00185     /*for(int n=150; n<180; n++)
00186         data[n] = 0xBC; 
00187     for(int n=180; n<210; n++)
00188         data[n] = 0x6B;
00189     for(int n=210; n<330; n++)
00190         data[n] = 0x7D; 
00191     for(int n=330; n<TX_DATA; n++)
00192         data[n] = 0xFF;*/
00193 
00194     //tx settings begin
00195 
00196     //setModeIdle();
00197     writereg(RF22_REG_07_OPERATING_MODE1,0x01);        //ready mode
00198     //fillTxBuf(data, len);
00199     clearTxBuf();          
00200     //Filling Data into FIFO for the first time
00201     cs = 0;
00202         spi.write(0xFF);               //fifo write access
00203         for(i=0; i< 20; i++) {                                 //datalen; i++){
00204             spi.write(data[i]);
00205             //pc.printf("0x%X \n",data[u+i]);
00206             }
00207         u=i;//check its 64
00208         cs = 1; 
00209     //Set to Tx mode
00210     writereg(RF22_REG_07_OPERATING_MODE1,0x09);
00211     uint8_t reg=0x07;
00212     pc.printf("reg07 : 0x%X",readreg(reg));
00213     //Check for fifoempty Thresh
00214     while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x20) != 0x20) pc.printf("fifothresh1?\n");
00215 
00216     while(u!=TX_DATA) {
00217         if((TX_DATA - u) >= TIMES)
00218             bar = TIMES;
00219         else
00220             bar = (TX_DATA - u);
00221 
00222     //writing again
00223         cs = 0;
00224         spi.write(0xFF);                   //FIFO write access
00225         for(i=0; i<bar; i++){
00226             spi.write(data[u + i]);
00227             //pc.printf("0x%X \n",data[u+i]);
00228             }
00229         u = u + i;
00230         cs = 1;
00231         wait(0.01);
00232         //Check for fifoThresh
00233         while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x20) != 0x20) pc.printf("fifothresh2?\n");
00234     }    
00235     //rf22.waitPacketSent();
00236     while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x04) != 0x04)pc.printf(" chck pkt sent!\n");     
00237     pc.printf(" packet sent ");
00238     
00239 }
00240 }