pradeep shekhar
stdalone beacon without flowchart
Revision 0:6ee885353677, committed 2015-06-16
- Comitter:
- shekhar
- Date:
- Tue Jun 16 06:48:18 2015 +0000
- Commit message:
- Basic Standalone Beacon code: without flowchart implementation.
Changed in this revision
diff -r 000000000000 -r 6ee885353677 beacon.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/beacon.h Tue Jun 16 06:48:18 2015 +0000 @@ -0,0 +1,105 @@ +#include "mbed.h" + +#define TIMES 20 +#define RX_DATA 364 //in bytes +#define TX_DATA 49 //in bytes + +void writereg(uint8_t reg,uint8_t val); +uint8_t readreg(uint8_t reg); +void clearTxBuf(); +void clearRxBuf(); +int setFrequency(float,float); +void init(); + +#define RF22_MAX_MESSAGE_LEN 255 +// These values we set for FIFO thresholds +#define RF22_TXFFAEM_THRESHOLD 4 +#define RF22_RXFFAFULL_THRESHOLD 55 + +// Register names +#define RF22_REG_00_DEVICE_TYPE 0x00 +#define RF22_REG_02_DEVICE_STATUS 0x02 +#define RF22_REG_03_INTERRUPT_STATUS1 0x03 +#define RF22_REG_04_INTERRUPT_STATUS2 0x04 +#define RF22_REG_07_OPERATING_MODE1 0x07 +#define RF22_REG_08_OPERATING_MODE2 0x08 +#define RF22_REG_09_OSCILLATOR_LOAD_CAPACITANCE 0x09 +#define RF22_REG_0B_GPIO_CONFIGURATION0 0x0b +#define RF22_REG_0C_GPIO_CONFIGURATION1 0x0c +#define RF22_REG_0D_GPIO_CONFIGURATION2 0x0d +#define RF22_REG_1C_IF_FILTER_BANDWIDTH 0x1c +#define RF22_REG_1F_CLOCK_RECOVERY_GEARSHIFT_OVERRIDE 0x1f +#define RF22_REG_20_CLOCK_RECOVERY_OVERSAMPLING_RATE 0x20 +#define RF22_REG_21_CLOCK_RECOVERY_OFFSET2 0x21 +#define RF22_REG_22_CLOCK_RECOVERY_OFFSET1 0x22 +#define RF22_REG_23_CLOCK_RECOVERY_OFFSET0 0x23 +#define RF22_REG_24_CLOCK_RECOVERY_TIMING_LOOP_GAIN1 0x24 +#define RF22_REG_25_CLOCK_RECOVERY_TIMING_LOOP_GAIN0 0x25 +#define RF22_REG_26_RSSI 0x26 +#define RF22_REG_27_RSSI_THRESHOLD 0x27 +#define RF22_REG_28_ANTENNA_DIVERSITY1 0x28 +#define RF22_REG_29_ANTENNA_DIVERSITY2 0x29 +#define RF22_REG_2A_AFC_LIMITER 0x2a +#define RF22_REG_2B_AFC_CORRECTION_READ 0x2b +#define RF22_REG_2C_OOK_COUNTER_VALUE_1 0x2c +#define RF22_REG_2D_OOK_COUNTER_VALUE_2 0x2d +#define RF22_REG_2E_SLICER_PEAK_HOLD 0x2e +#define RF22_REG_30_DATA_ACCESS_CONTROL 0x30 +#define RF22_REG_31_EZMAC_STATUS 0x31 +#define RF22_REG_32_HEADER_CONTROL1 0x32 +#define RF22_REG_33_HEADER_CONTROL2 0x33 +#define RF22_REG_34_PREAMBLE_LENGTH 0x34 +#define RF22_REG_35_PREAMBLE_DETECTION_CONTROL1 0x35 +#define RF22_REG_36_SYNC_WORD3 0x36 +#define RF22_REG_37_SYNC_WORD2 0x37 +#define RF22_REG_38_SYNC_WORD1 0x38 +#define RF22_REG_39_SYNC_WORD0 0x39 +#define RF22_REG_3A_TRANSMIT_HEADER3 0x3a +#define RF22_REG_3B_TRANSMIT_HEADER2 0x3b +#define RF22_REG_3C_TRANSMIT_HEADER1 0x3c +#define RF22_REG_3D_TRANSMIT_HEADER0 0x3d +#define RF22_REG_3E_PACKET_LENGTH 0x3e +#define RF22_REG_3F_CHECK_HEADER3 0x3f +#define RF22_REG_40_CHECK_HEADER2 0x40 +#define RF22_REG_41_CHECK_HEADER1 0x41 +#define RF22_REG_42_CHECK_HEADER0 0x42 +#define RF22_REG_43_HEADER_ENABLE3 0x43 +#define RF22_REG_44_HEADER_ENABLE2 0x44 +#define RF22_REG_45_HEADER_ENABLE1 0x45 +#define RF22_REG_46_HEADER_ENABLE0 0x46 +#define RF22_REG_47_RECEIVED_HEADER3 0x47 +#define RF22_REG_48_RECEIVED_HEADER2 0x48 +#define RF22_REG_49_RECEIVED_HEADER1 0x49 +#define RF22_REG_4A_RECEIVED_HEADER0 0x4a +#define RF22_REG_4B_RECEIVED_PACKET_LENGTH 0x4b +#define RF22_REG_58 0x58 +#define RF22_REG_60_CHANNEL_FILTER_COEFFICIENT_ADDRESS 0x60 +#define RF22_REG_61_CHANNEL_FILTER_COEFFICIENT_VALUE 0x61 +#define RF22_REG_62_CRYSTAL_OSCILLATOR_POR_CONTROL 0x62 +#define RF22_REG_63_RC_OSCILLATOR_COARSE_CALIBRATION 0x63 +#define RF22_REG_64_RC_OSCILLATOR_FINE_CALIBRATION 0x64 +#define RF22_REG_65_LDO_CONTROL_OVERRIDE 0x65 +#define RF22_REG_66_LDO_LEVEL_SETTINGS 0x66 +#define RF22_REG_67_DELTA_SIGMA_ADC_TUNING1 0x67 +#define RF22_REG_68_DELTA_SIGMA_ADC_TUNING2 0x68 +#define RF22_REG_69_AGC_OVERRIDE1 0x69 +#define RF22_REG_6A_AGC_OVERRIDE2 0x6a +#define RF22_REG_6B_GFSK_FIR_FILTER_COEFFICIENT_ADDRESS 0x6b +#define RF22_REG_6C_GFSK_FIR_FILTER_COEFFICIENT_VALUE 0x6c +#define RF22_REG_6D_TX_POWER 0x6d +#define RF22_REG_6E_TX_DATA_RATE1 0x6e +#define RF22_REG_6F_TX_DATA_RATE0 0x6f +#define RF22_REG_70_MODULATION_CONTROL1 0x70 +#define RF22_REG_71_MODULATION_CONTROL2 0x71 +#define RF22_REG_72_FREQUENCY_DEVIATION 0x72 +#define RF22_REG_73_FREQUENCY_OFFSET1 0x73 +#define RF22_REG_74_FREQUENCY_OFFSET2 0x74 +#define RF22_REG_75_FREQUENCY_BAND_SELECT 0x75 +#define RF22_REG_76_NOMINAL_CARRIER_FREQUENCY1 0x76 +#define RF22_REG_77_NOMINAL_CARRIER_FREQUENCY0 0x77 +#define RF22_REG_79_FREQUENCY_HOPPING_CHANNEL_SELECT 0x79 +#define RF22_REG_7A_FREQUENCY_HOPPING_STEP_SIZE 0x7a +#define RF22_REG_7C_TX_FIFO_CONTROL1 0x7c +#define RF22_REG_7D_TX_FIFO_CONTROL2 0x7d +#define RF22_REG_7E_RX_FIFO_CONTROL 0x7e +#define RF22_REG_7F_FIFO_ACCESS 0x7f \ No newline at end of file
diff -r 000000000000 -r 6ee885353677 main.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/main.cpp Tue Jun 16 06:48:18 2015 +0000
@@ -0,0 +1,240 @@
+#include "beacon.h"
+Serial pc(USBTX, USBRX); // tx, rx
+SPI spi(D11, D12, D13); // mosi, miso, sclk
+DigitalOut cs(D10); //slave select or chip select
+
+void writereg(uint8_t reg,uint8_t val)
+{
+ cs = 0;__disable_irq();spi.write(reg | 0x80);spi.write(val);__enable_irq();cs = 1;
+}
+uint8_t readreg(uint8_t reg)
+{
+ int val;cs = 0;__disable_irq();spi.write(reg & ~0x80);val = spi.write(0);__enable_irq();cs = 1;return val;
+}
+void clearTxBuf()
+{
+ writereg(RF22_REG_08_OPERATING_MODE2,0x01);
+ writereg(RF22_REG_08_OPERATING_MODE2,0x00);
+}
+void clearRxBuf()
+{
+ writereg(RF22_REG_08_OPERATING_MODE2,0x02);
+ writereg(RF22_REG_08_OPERATING_MODE2,0x00);
+}
+int setFrequency(float centre,float afcPullInRange)
+{
+//freq setting begins
+ uint8_t fbsel = 0x40;
+ uint8_t afclimiter;
+ if (centre >= 480.0) {
+ centre /= 2;
+ fbsel |= 0x20;
+ afclimiter = afcPullInRange * 1000000.0 / 1250.0;
+ } else {
+ if (afcPullInRange < 0.0 || afcPullInRange > 0.159375)
+ return false;
+ afclimiter = afcPullInRange * 1000000.0 / 625.0;
+ }
+ centre /= 10.0;
+ float integerPart = floor(centre);
+ float fractionalPart = centre - integerPart;
+
+ uint8_t fb = (uint8_t)integerPart - 24; // Range 0 to 23
+ fbsel |= fb;
+ uint16_t fc = fractionalPart * 64000;
+ writereg(RF22_REG_73_FREQUENCY_OFFSET1, 0); // REVISIT
+ writereg(RF22_REG_74_FREQUENCY_OFFSET2, 0);
+ writereg(RF22_REG_75_FREQUENCY_BAND_SELECT, fbsel);
+ writereg(RF22_REG_76_NOMINAL_CARRIER_FREQUENCY1, fc >> 8);
+ writereg(RF22_REG_77_NOMINAL_CARRIER_FREQUENCY0, fc & 0xff);
+ writereg(RF22_REG_2A_AFC_LIMITER, afclimiter);
+ return 0;
+}
+void init()
+{
+ //reset()
+ writereg(RF22_REG_07_OPERATING_MODE1,0x80); //switch_reset
+ wait(1); //takes time to reset
+
+ clearTxBuf();
+ clearRxBuf();
+ //txfifoalmostempty
+ writereg(RF22_REG_7D_TX_FIFO_CONTROL2,10);
+ //rxfifoalmostfull
+ writereg(RF22_REG_7E_RX_FIFO_CONTROL,20);
+ //Packet-engine registers
+ writereg(RF22_REG_30_DATA_ACCESS_CONTROL,0x06); //RF22_REG_30_DATA_ACCESS_CONTROL, RF22_ENPACRX | RF22_ENPACTX | RF22_ENCRC | RF22_CRC_CRC_16_IBM
+ //&0x77 = diasable packet rx-tx handling
+
+ //writereg(RF22_REG_32_HEADER_CONTROL1,0x88); //RF22_REG_32_HEADER_CONTROL1, RF22_BCEN_HEADER3 | RF22_HDCH_HEADER3
+ //writereg(RF22_REG_33_HEADER_CONTROL2,0x42); //RF22_REG_33_HEADER_CONTROL2, RF22_HDLEN_4 | RF22_SYNCLEN_2
+ writereg(RF22_REG_34_PREAMBLE_LENGTH,4); //RF22_REG_34_PREAMBLE_LENGTH, nibbles); preamble length = 8;
+ writereg(RF22_REG_36_SYNC_WORD3,0x2D); //syncword3=2D
+ writereg(RF22_REG_37_SYNC_WORD2,0xD4); //syncword2=D4
+ writereg(RF22_REG_3F_CHECK_HEADER3,0); //RF22_REG_3F_CHECK_HEADER3, RF22_DEFAULT_NODE_ADDRESS
+ writereg(RF22_REG_3A_TRANSMIT_HEADER3,0xab); //header_to
+ writereg(RF22_REG_3B_TRANSMIT_HEADER2,0xbc); //header_from
+ writereg(RF22_REG_3C_TRANSMIT_HEADER1,0xcd); //header_ids
+ writereg(RF22_REG_3D_TRANSMIT_HEADER0,0xde); //header_flags
+ writereg(RF22_REG_3F_CHECK_HEADER3,0xab);
+ writereg(RF22_REG_40_CHECK_HEADER2,0xbc);
+ writereg(RF22_REG_41_CHECK_HEADER1,0xcd);
+ writereg(RF22_REG_42_CHECK_HEADER0,0xde);
+
+ //RSSI threshold for clear channel indicator
+ writereg(RF22_REG_27_RSSI_THRESHOLD,0xA5); //55 for -80dBm, 2D for -100dBm, 7D for -60dBm, A5 for -40dBm, CD for -20 dBm
+
+ writereg(RF22_REG_0B_GPIO_CONFIGURATION0,0x15); // TX state ??
+ writereg(RF22_REG_0C_GPIO_CONFIGURATION1,0x12); // RX state ??
+
+ //interrupts
+ // spiWrite(RF22_REG_05_INTERRUPT_ENABLE1, RF22_ENTXFFAEM |RF22_ENRXFFAFULL | RF22_ENPKSENT |RF22_ENPKVALID| RF22_ENCRCERROR);
+ // spiWrite(RF22_REG_06_INTERRUPT_ENABLE2, RF22_ENPREAVAL);
+
+ setFrequency(435.0, 0.05);
+
+ //return !(statusRead() & RF22_FREQERR);
+ if((readreg(RF22_REG_02_DEVICE_STATUS)& 0x08)!= 0x00)
+ pc.printf("frequency not set properly\n");
+ //frequency set
+
+ //setModemConfig(FSK_Rb2_4Fd36); FSK_Rb2_4Fd36, ///< FSK, No Manchester, Rb = 2.4kbs, Fd = 36kHz
+ //setmodemregisters
+ //0x1b, 0x03, 0x41, 0x60, 0x27, 0x52, 0x00, 0x07, 0x40, 0x0a, 0x1e, 0x80, 0x60, 0x13, 0xa9, 0x2c, 0x22, 0x3a = FSK_RB2_4FD36
+ //0xc8, 0x03, 0x39, 0x20, 0x68, 0xdc, 0x00, 0x6b, 0x2a, 0x08, 0x2a, 0x80, 0x60, 0x13, 0xa9, 0x2c, 0x21, 0x08 = OOK,2.4, 335
+ writereg(RF22_REG_1C_IF_FILTER_BANDWIDTH,0xdf);
+ writereg(RF22_REG_1F_CLOCK_RECOVERY_GEARSHIFT_OVERRIDE,0x03);
+ writereg(RF22_REG_20_CLOCK_RECOVERY_OVERSAMPLING_RATE,0x39);
+ writereg(RF22_REG_21_CLOCK_RECOVERY_OFFSET2,0x20);
+ writereg(RF22_REG_22_CLOCK_RECOVERY_OFFSET1,0x68); //updated 20 to 25 reg values from excel sheet for 1.2 Khz freq. deviation,fsk
+ writereg(RF22_REG_23_CLOCK_RECOVERY_OFFSET0,0xdc);
+ writereg(RF22_REG_24_CLOCK_RECOVERY_TIMING_LOOP_GAIN1,0x00);
+ writereg(RF22_REG_25_CLOCK_RECOVERY_TIMING_LOOP_GAIN0,0x6B);
+ writereg(RF22_REG_2C_OOK_COUNTER_VALUE_1,0x2C);
+ writereg(RF22_REG_2D_OOK_COUNTER_VALUE_2,0x11); //not required for fsk (OOK counter value)
+ writereg(RF22_REG_2E_SLICER_PEAK_HOLD,0x2A); //??
+ writereg(RF22_REG_58,0x80);
+ writereg(RF22_REG_69_AGC_OVERRIDE1,0x60);
+ writereg(RF22_REG_6E_TX_DATA_RATE1,0x09);
+ writereg(RF22_REG_6F_TX_DATA_RATE0,0xd5);
+ writereg(RF22_REG_70_MODULATION_CONTROL1,0x2c);
+ writereg(RF22_REG_71_MODULATION_CONTROL2,0x21);//ook = 0x21 //fsk = 0x22
+ writereg(RF22_REG_72_FREQUENCY_DEVIATION,0x50);
+ //set tx power
+ writereg(RF22_REG_6D_TX_POWER,0x07); //20dbm
+}
+int main()
+{
+ wait(1); // wait for POR to complete //change the timing later
+ cs=1; // chip must be deselected
+ wait(1); //change the time later
+ spi.format(8,0);
+ spi.frequency(10000000); //10MHz SCLK
+ if (readreg(RF22_REG_00_DEVICE_TYPE) == 0x08) pc.printf("spi connection valid\n");
+ else pc.printf("error in spi connection\n");
+
+ init();
+
+
+ //init complete
+ pc.printf("init complete.....press t to send\n");
+
+
+ //********
+
+while(1)//pc.getc()=='t')
+{
+ /*uint8_t data[] = "Hello World!";
+ pc.printf("%d %d %d %d %d %d %d %d %d %d %d %d",data[0],data[1],data[2],data[3],data[4],data[5],data[6],data[7],data[8],data[9],data[10],data[11],data[12]);*/
+
+ uint8_t data[500]; //starts from 0,1,2,3,4!!!;
+ int i = 0; //for loops
+ int u = 0; //universal count for hk array
+ int n=0,bar = 0;
+ //filling hk data
+/* 1 for(int n=0; n<4; n++)
+ data[n] = 0x55;
+ data[4] = 0x2D;
+ data[5] = 0xD4;
+ data[6] = 0xab;
+ data[7] = 0xbc;
+ data[8] = 0xcd;
+ data[9] = 0xde;
+ data[10]= 0xa9;
+ for(int n=11; n<50; n++)
+ data[n] = 0x5A;
+ for(int n=50; n<60; n++)
+ data[n] = 0x5A;
+ for(int n=60; n<75; n++)
+ data[n] = 0xCC;
+ for(int n=75; n<97; n++)
+ data[n] = 0xBC;
+ for(int n=97; n<110; n++)
+ data[n] = 0xEC;
+ for(int n=110; n<TX_DATA; n++)
+ data[n] = n; */
+ for(int i=0; i<7; i++){
+ data[n++] = 0x49;
+ data[n++] = 0x49;
+ data[n++] = 0x54;
+ data[n++] = 0x4D;
+ data[n++] = 0x53;
+ data[n++] = 0x41;
+ data[n++] = 0x54;
+ }
+ /*for(int n=150; n<180; n++)
+ data[n] = 0xBC;
+ for(int n=180; n<210; n++)
+ data[n] = 0x6B;
+ for(int n=210; n<330; n++)
+ data[n] = 0x7D;
+ for(int n=330; n<TX_DATA; n++)
+ data[n] = 0xFF;*/
+
+ //tx settings begin
+
+ //setModeIdle();
+ writereg(RF22_REG_07_OPERATING_MODE1,0x01); //ready mode
+ //fillTxBuf(data, len);
+ clearTxBuf();
+ //Filling Data into FIFO for the first time
+ cs = 0;
+ spi.write(0xFF); //fifo write access
+ for(i=0; i< 20; i++) { //datalen; i++){
+ spi.write(data[i]);
+ //pc.printf("0x%X \n",data[u+i]);
+ }
+ u=i;//check its 64
+ cs = 1;
+ //Set to Tx mode
+ writereg(RF22_REG_07_OPERATING_MODE1,0x09);
+ uint8_t reg=0x07;
+ pc.printf("reg07 : 0x%X",readreg(reg));
+ //Check for fifoempty Thresh
+ while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x20) != 0x20) pc.printf("fifothresh1?\n");
+
+ while(u!=TX_DATA) {
+ if((TX_DATA - u) >= TIMES)
+ bar = TIMES;
+ else
+ bar = (TX_DATA - u);
+
+ //writing again
+ cs = 0;
+ spi.write(0xFF); //FIFO write access
+ for(i=0; i<bar; i++){
+ spi.write(data[u + i]);
+ //pc.printf("0x%X \n",data[u+i]);
+ }
+ u = u + i;
+ cs = 1;
+ wait(0.01);
+ //Check for fifoThresh
+ while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x20) != 0x20) pc.printf("fifothresh2?\n");
+ }
+ //rf22.waitPacketSent();
+ while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x04) != 0x04)pc.printf(" chck pkt sent!\n");
+ pc.printf(" packet sent ");
+
+}
+}
\ No newline at end of file
diff -r 000000000000 -r 6ee885353677 mbed.bld --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed.bld Tue Jun 16 06:48:18 2015 +0000 @@ -0,0 +1,1 @@ +http://mbed.org/users/mbed_official/code/mbed/builds/4fc01daae5a5 \ No newline at end of file