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targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/system_stm32f3xx.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file system_stm32f3xx.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V2.3.0
<> 144:ef7eb2e8f9f7 6 * @date 29-April-2015
<> 144:ef7eb2e8f9f7 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * 1. This file provides two functions and one global variable to be called from
<> 144:ef7eb2e8f9f7 10 * user application:
<> 144:ef7eb2e8f9f7 11 * - SystemInit(): This function is called at startup just after reset and
<> 144:ef7eb2e8f9f7 12 * before branch to main program. This call is made inside
<> 144:ef7eb2e8f9f7 13 * the "startup_stm32f3xx.s" file.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
<> 144:ef7eb2e8f9f7 16 * by the user application to setup the SysTick
<> 144:ef7eb2e8f9f7 17 * timer or configure other parameters.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
<> 144:ef7eb2e8f9f7 20 * be called whenever the core clock is changed
<> 144:ef7eb2e8f9f7 21 * during program execution.
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
<> 144:ef7eb2e8f9f7 24 * Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
<> 144:ef7eb2e8f9f7 25 * configure the system clock before to branch to main program.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * 3. This file configures the system clock as follows:
<> 144:ef7eb2e8f9f7 28 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
<> 144:ef7eb2e8f9f7 30 * | (external 8 MHz clock) | (internal 8 MHz)
<> 144:ef7eb2e8f9f7 31 * | 2- PLL_HSE_XTAL |
<> 144:ef7eb2e8f9f7 32 * | (external 8 MHz xtal) |
<> 144:ef7eb2e8f9f7 33 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 34 * SYSCLK(MHz) | 72 | 64
<> 144:ef7eb2e8f9f7 35 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 36 * AHBCLK (MHz) | 72 | 64
<> 144:ef7eb2e8f9f7 37 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 38 * APB1CLK (MHz) | 36 | 32
<> 144:ef7eb2e8f9f7 39 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 40 * APB2CLK (MHz) | 72 | 64
<> 144:ef7eb2e8f9f7 41 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 42 * USB capable (48 MHz precise clock) | NO | NO
<> 144:ef7eb2e8f9f7 43 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 44 ******************************************************************************
<> 144:ef7eb2e8f9f7 45 * @attention
<> 144:ef7eb2e8f9f7 46 *
<> 144:ef7eb2e8f9f7 47 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 48 *
<> 144:ef7eb2e8f9f7 49 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 50 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 51 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 52 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 53 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 54 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 55 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 56 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 57 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 58 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 59 *
<> 144:ef7eb2e8f9f7 60 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 61 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 63 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 66 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 67 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 68 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 69 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 70 *
<> 144:ef7eb2e8f9f7 71 ******************************************************************************
<> 144:ef7eb2e8f9f7 72 */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /** @addtogroup CMSIS
<> 144:ef7eb2e8f9f7 75 * @{
<> 144:ef7eb2e8f9f7 76 */
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 /** @addtogroup stm32f3xx_system
<> 144:ef7eb2e8f9f7 79 * @{
<> 144:ef7eb2e8f9f7 80 */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 /** @addtogroup STM32F3xx_System_Private_Includes
<> 144:ef7eb2e8f9f7 83 * @{
<> 144:ef7eb2e8f9f7 84 */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 #include "stm32f3xx.h"
<> 144:ef7eb2e8f9f7 87 #include "hal_tick.h"
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 #include "stm32f3xx_hal.h"
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /**
<> 144:ef7eb2e8f9f7 92 * @}
<> 144:ef7eb2e8f9f7 93 */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /** @addtogroup STM32F3xx_System_Private_TypesDefinitions
<> 144:ef7eb2e8f9f7 96 * @{
<> 144:ef7eb2e8f9f7 97 */
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /**
<> 144:ef7eb2e8f9f7 100 * @}
<> 144:ef7eb2e8f9f7 101 */
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /** @addtogroup STM32F3xx_System_Private_Defines
<> 144:ef7eb2e8f9f7 104 * @{
<> 144:ef7eb2e8f9f7 105 */
<> 144:ef7eb2e8f9f7 106 #if !defined (HSE_VALUE)
<> 144:ef7eb2e8f9f7 107 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
<> 144:ef7eb2e8f9f7 108 This value can be provided and adapted by the user application. */
<> 144:ef7eb2e8f9f7 109 #endif /* HSE_VALUE */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 #if !defined (HSI_VALUE)
<> 144:ef7eb2e8f9f7 112 #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
<> 144:ef7eb2e8f9f7 113 This value can be provided and adapted by the user application. */
<> 144:ef7eb2e8f9f7 114 #endif /* HSI_VALUE */
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /*!< Uncomment the following line if you need to relocate your vector Table in
<> 144:ef7eb2e8f9f7 117 Internal SRAM. */
<> 144:ef7eb2e8f9f7 118 /* #define VECT_TAB_SRAM */
<> 144:ef7eb2e8f9f7 119 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
<> 144:ef7eb2e8f9f7 120 This value must be a multiple of 0x200. */
<> 144:ef7eb2e8f9f7 121 /**
<> 144:ef7eb2e8f9f7 122 * @}
<> 144:ef7eb2e8f9f7 123 */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /** @addtogroup STM32F3xx_System_Private_Macros
<> 144:ef7eb2e8f9f7 126 * @{
<> 144:ef7eb2e8f9f7 127 */
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
<> 144:ef7eb2e8f9f7 130 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
<> 144:ef7eb2e8f9f7 131 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /**
<> 144:ef7eb2e8f9f7 134 * @}
<> 144:ef7eb2e8f9f7 135 */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /** @addtogroup STM32F3xx_System_Private_Variables
<> 144:ef7eb2e8f9f7 138 * @{
<> 144:ef7eb2e8f9f7 139 */
<> 144:ef7eb2e8f9f7 140 /* This variable is updated in three ways:
<> 144:ef7eb2e8f9f7 141 1) by calling CMSIS function SystemCoreClockUpdate()
<> 144:ef7eb2e8f9f7 142 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
<> 144:ef7eb2e8f9f7 143 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
<> 144:ef7eb2e8f9f7 144 Note: If you use this function to configure the system clock there is no need to
<> 144:ef7eb2e8f9f7 145 call the 2 first functions listed above, since SystemCoreClock variable is
<> 144:ef7eb2e8f9f7 146 updated automatically.
<> 144:ef7eb2e8f9f7 147 */
<> 144:ef7eb2e8f9f7 148 uint32_t SystemCoreClock = 72000000;
<> 144:ef7eb2e8f9f7 149 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
<> 144:ef7eb2e8f9f7 150 const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 /**
<> 144:ef7eb2e8f9f7 153 * @}
<> 144:ef7eb2e8f9f7 154 */
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
<> 144:ef7eb2e8f9f7 157 * @{
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
<> 144:ef7eb2e8f9f7 161 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
<> 144:ef7eb2e8f9f7 162 #endif
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 uint8_t SetSysClock_PLL_HSI(void);
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /**
<> 144:ef7eb2e8f9f7 167 * @}
<> 144:ef7eb2e8f9f7 168 */
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 /** @addtogroup STM32F3xx_System_Private_Functions
<> 144:ef7eb2e8f9f7 171 * @{
<> 144:ef7eb2e8f9f7 172 */
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /**
<> 144:ef7eb2e8f9f7 175 * @brief Setup the microcontroller system
<> 144:ef7eb2e8f9f7 176 * Initialize the FPU setting, vector table location and the PLL configuration is reset.
<> 144:ef7eb2e8f9f7 177 * @param None
<> 144:ef7eb2e8f9f7 178 * @retval None
<> 144:ef7eb2e8f9f7 179 */
<> 144:ef7eb2e8f9f7 180 void SystemInit(void)
<> 144:ef7eb2e8f9f7 181 {
<> 144:ef7eb2e8f9f7 182 /* FPU settings ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 183 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 144:ef7eb2e8f9f7 184 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
<> 144:ef7eb2e8f9f7 185 #endif
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /* Reset the RCC clock configuration to the default reset state ------------*/
<> 144:ef7eb2e8f9f7 188 /* Set HSION bit */
<> 144:ef7eb2e8f9f7 189 RCC->CR |= 0x00000001U;
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /* Reset CFGR register */
<> 144:ef7eb2e8f9f7 192 RCC->CFGR &= 0xF87FC00CU;
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /* Reset HSEON, CSSON and PLLON bits */
<> 144:ef7eb2e8f9f7 195 RCC->CR &= 0xFEF6FFFFU;
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /* Reset HSEBYP bit */
<> 144:ef7eb2e8f9f7 198 RCC->CR &= 0xFFFBFFFFU;
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
<> 144:ef7eb2e8f9f7 201 RCC->CFGR &= 0xFF80FFFFU;
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /* Reset PREDIV1[3:0] bits */
<> 144:ef7eb2e8f9f7 204 RCC->CFGR2 &= 0xFFFFFFF0U;
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /* Reset USARTSW[1:0], I2CSW and TIMs bits */
<> 144:ef7eb2e8f9f7 207 RCC->CFGR3 &= 0xFF00FCCCU;
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /* Disable all interrupts */
<> 144:ef7eb2e8f9f7 210 RCC->CIR = 0x00000000U;
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 #ifdef VECT_TAB_SRAM
<> 144:ef7eb2e8f9f7 213 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
<> 144:ef7eb2e8f9f7 214 #else
<> 144:ef7eb2e8f9f7 215 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
<> 144:ef7eb2e8f9f7 216 #endif
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /* Configure the Cube driver */
<> 144:ef7eb2e8f9f7 219 SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
<> 144:ef7eb2e8f9f7 220 HAL_Init();
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 /* Configure the System clock source, PLL Multiplier and Divider factors,
<> 144:ef7eb2e8f9f7 223 AHB/APBx prescalers and Flash settings */
<> 144:ef7eb2e8f9f7 224 SetSysClock();
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /* Reset the timer to avoid issues after the RAM initialization */
<> 144:ef7eb2e8f9f7 227 TIM_MST_RESET_ON;
<> 144:ef7eb2e8f9f7 228 TIM_MST_RESET_OFF;
<> 144:ef7eb2e8f9f7 229 }
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /**
<> 144:ef7eb2e8f9f7 232 * @brief Update SystemCoreClock variable according to Clock Register Values.
<> 144:ef7eb2e8f9f7 233 * The SystemCoreClock variable contains the core clock (HCLK), it can
<> 144:ef7eb2e8f9f7 234 * be used by the user application to setup the SysTick timer or configure
<> 144:ef7eb2e8f9f7 235 * other parameters.
<> 144:ef7eb2e8f9f7 236 *
<> 144:ef7eb2e8f9f7 237 * @note Each time the core clock (HCLK) changes, this function must be called
<> 144:ef7eb2e8f9f7 238 * to update SystemCoreClock variable value. Otherwise, any configuration
<> 144:ef7eb2e8f9f7 239 * based on this variable will be incorrect.
<> 144:ef7eb2e8f9f7 240 *
<> 144:ef7eb2e8f9f7 241 * @note - The system frequency computed by this function is not the real
<> 144:ef7eb2e8f9f7 242 * frequency in the chip. It is calculated based on the predefined
<> 144:ef7eb2e8f9f7 243 * constant and the selected clock source:
<> 144:ef7eb2e8f9f7 244 *
<> 144:ef7eb2e8f9f7 245 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
<> 144:ef7eb2e8f9f7 246 *
<> 144:ef7eb2e8f9f7 247 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
<> 144:ef7eb2e8f9f7 248 *
<> 144:ef7eb2e8f9f7 249 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
<> 144:ef7eb2e8f9f7 250 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
<> 144:ef7eb2e8f9f7 251 *
<> 144:ef7eb2e8f9f7 252 * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
<> 144:ef7eb2e8f9f7 253 * 8 MHz) but the real value may vary depending on the variations
<> 144:ef7eb2e8f9f7 254 * in voltage and temperature.
<> 144:ef7eb2e8f9f7 255 *
<> 144:ef7eb2e8f9f7 256 * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
<> 144:ef7eb2e8f9f7 257 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
<> 144:ef7eb2e8f9f7 258 * frequency of the crystal used. Otherwise, this function may
<> 144:ef7eb2e8f9f7 259 * have wrong result.
<> 144:ef7eb2e8f9f7 260 *
<> 144:ef7eb2e8f9f7 261 * - The result of this function could be not correct when using fractional
<> 144:ef7eb2e8f9f7 262 * value for HSE crystal.
<> 144:ef7eb2e8f9f7 263 *
<> 144:ef7eb2e8f9f7 264 * @param None
<> 144:ef7eb2e8f9f7 265 * @retval None
<> 144:ef7eb2e8f9f7 266 */
<> 144:ef7eb2e8f9f7 267 void SystemCoreClockUpdate (void)
<> 144:ef7eb2e8f9f7 268 {
<> 144:ef7eb2e8f9f7 269 uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /* Get SYSCLK source -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 272 tmp = RCC->CFGR & RCC_CFGR_SWS;
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 switch (tmp)
<> 144:ef7eb2e8f9f7 275 {
<> 144:ef7eb2e8f9f7 276 case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
<> 144:ef7eb2e8f9f7 277 SystemCoreClock = HSI_VALUE;
<> 144:ef7eb2e8f9f7 278 break;
<> 144:ef7eb2e8f9f7 279 case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
<> 144:ef7eb2e8f9f7 280 SystemCoreClock = HSE_VALUE;
<> 144:ef7eb2e8f9f7 281 break;
<> 144:ef7eb2e8f9f7 282 case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
<> 144:ef7eb2e8f9f7 283 /* Get PLL clock source and multiplication factor ----------------------*/
<> 144:ef7eb2e8f9f7 284 pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
<> 144:ef7eb2e8f9f7 285 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
<> 144:ef7eb2e8f9f7 286 pllmull = ( pllmull >> 18) + 2;
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
<> 144:ef7eb2e8f9f7 289 predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
<> 144:ef7eb2e8f9f7 290 if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
<> 144:ef7eb2e8f9f7 291 {
<> 144:ef7eb2e8f9f7 292 /* HSE oscillator clock selected as PREDIV1 clock entry */
<> 144:ef7eb2e8f9f7 293 SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
<> 144:ef7eb2e8f9f7 294 }
<> 144:ef7eb2e8f9f7 295 else
<> 144:ef7eb2e8f9f7 296 {
<> 144:ef7eb2e8f9f7 297 /* HSI oscillator clock selected as PREDIV1 clock entry */
<> 144:ef7eb2e8f9f7 298 SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
<> 144:ef7eb2e8f9f7 299 }
<> 144:ef7eb2e8f9f7 300 #else
<> 144:ef7eb2e8f9f7 301 if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
<> 144:ef7eb2e8f9f7 302 {
<> 144:ef7eb2e8f9f7 303 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
<> 144:ef7eb2e8f9f7 304 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
<> 144:ef7eb2e8f9f7 305 }
<> 144:ef7eb2e8f9f7 306 else
<> 144:ef7eb2e8f9f7 307 {
<> 144:ef7eb2e8f9f7 308 predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
<> 144:ef7eb2e8f9f7 309 /* HSE oscillator clock selected as PREDIV1 clock entry */
<> 144:ef7eb2e8f9f7 310 SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
<> 144:ef7eb2e8f9f7 311 }
<> 144:ef7eb2e8f9f7 312 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
<> 144:ef7eb2e8f9f7 313 break;
<> 144:ef7eb2e8f9f7 314 default: /* HSI used as system clock */
<> 144:ef7eb2e8f9f7 315 SystemCoreClock = HSI_VALUE;
<> 144:ef7eb2e8f9f7 316 break;
<> 144:ef7eb2e8f9f7 317 }
<> 144:ef7eb2e8f9f7 318 /* Compute HCLK clock frequency ----------------*/
<> 144:ef7eb2e8f9f7 319 /* Get HCLK prescaler */
<> 144:ef7eb2e8f9f7 320 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
<> 144:ef7eb2e8f9f7 321 /* HCLK clock frequency */
<> 144:ef7eb2e8f9f7 322 SystemCoreClock >>= tmp;
<> 144:ef7eb2e8f9f7 323 }
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /**
<> 144:ef7eb2e8f9f7 326 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
<> 144:ef7eb2e8f9f7 327 * AHB/APBx prescalers and Flash settings
<> 144:ef7eb2e8f9f7 328 * @note This function should be called only once the RCC clock configuration
<> 144:ef7eb2e8f9f7 329 * is reset to the default reset state (done in SystemInit() function).
<> 144:ef7eb2e8f9f7 330 * @param None
<> 144:ef7eb2e8f9f7 331 * @retval None
<> 144:ef7eb2e8f9f7 332 */
<> 144:ef7eb2e8f9f7 333 void SetSysClock(void)
<> 144:ef7eb2e8f9f7 334 {
<> 144:ef7eb2e8f9f7 335 /* 1- Try to start with HSE and external clock */
<> 144:ef7eb2e8f9f7 336 #if USE_PLL_HSE_EXTC != 0
<> 144:ef7eb2e8f9f7 337 if (SetSysClock_PLL_HSE(1) == 0)
<> 144:ef7eb2e8f9f7 338 #endif
<> 144:ef7eb2e8f9f7 339 {
<> 144:ef7eb2e8f9f7 340 /* 2- If fail try to start with HSE and external xtal */
<> 144:ef7eb2e8f9f7 341 #if USE_PLL_HSE_XTAL != 0
<> 144:ef7eb2e8f9f7 342 if (SetSysClock_PLL_HSE(0) == 0)
<> 144:ef7eb2e8f9f7 343 #endif
<> 144:ef7eb2e8f9f7 344 {
<> 144:ef7eb2e8f9f7 345 /* 3- If fail start with HSI clock */
<> 144:ef7eb2e8f9f7 346 if (SetSysClock_PLL_HSI() == 0)
<> 144:ef7eb2e8f9f7 347 {
<> 144:ef7eb2e8f9f7 348 while(1)
<> 144:ef7eb2e8f9f7 349 {
<> 144:ef7eb2e8f9f7 350 // [TODO] Put something here to tell the user that a problem occured...
<> 144:ef7eb2e8f9f7 351 }
<> 144:ef7eb2e8f9f7 352 }
<> 144:ef7eb2e8f9f7 353 }
<> 144:ef7eb2e8f9f7 354 }
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /* Output clock on MCO1 pin(PA8) for debugging purpose */
<> 144:ef7eb2e8f9f7 357 //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 72 MHz or 64 MHz
<> 144:ef7eb2e8f9f7 358 }
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
<> 144:ef7eb2e8f9f7 361 /******************************************************************************/
<> 144:ef7eb2e8f9f7 362 /* PLL (clocked by HSE) used as System clock source */
<> 144:ef7eb2e8f9f7 363 /******************************************************************************/
<> 144:ef7eb2e8f9f7 364 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
<> 144:ef7eb2e8f9f7 365 {
<> 144:ef7eb2e8f9f7 366 RCC_ClkInitTypeDef RCC_ClkInitStruct;
<> 144:ef7eb2e8f9f7 367 RCC_OscInitTypeDef RCC_OscInitStruct;
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /* Enable HSE oscillator and activate PLL with HSE as source */
<> 144:ef7eb2e8f9f7 370 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
<> 144:ef7eb2e8f9f7 371 if (bypass == 0)
<> 144:ef7eb2e8f9f7 372 {
<> 144:ef7eb2e8f9f7 373 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
<> 144:ef7eb2e8f9f7 374 }
<> 144:ef7eb2e8f9f7 375 else
<> 144:ef7eb2e8f9f7 376 {
<> 144:ef7eb2e8f9f7 377 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
<> 144:ef7eb2e8f9f7 378 }
<> 144:ef7eb2e8f9f7 379 RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
<> 144:ef7eb2e8f9f7 380 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
<> 144:ef7eb2e8f9f7 381 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
<> 144:ef7eb2e8f9f7 382 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
<> 144:ef7eb2e8f9f7 383 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
<> 144:ef7eb2e8f9f7 384 {
<> 144:ef7eb2e8f9f7 385 return 0; // FAIL
<> 144:ef7eb2e8f9f7 386 }
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
<> 144:ef7eb2e8f9f7 389 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
<> 144:ef7eb2e8f9f7 390 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
<> 144:ef7eb2e8f9f7 391 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz
<> 144:ef7eb2e8f9f7 392 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz
<> 144:ef7eb2e8f9f7 393 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz
<> 144:ef7eb2e8f9f7 394 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
<> 144:ef7eb2e8f9f7 395 {
<> 144:ef7eb2e8f9f7 396 return 0; // FAIL
<> 144:ef7eb2e8f9f7 397 }
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 /* Output clock on MCO1 pin(PA8) for debugging purpose */
<> 144:ef7eb2e8f9f7 400 //if (bypass == 0)
<> 144:ef7eb2e8f9f7 401 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
<> 144:ef7eb2e8f9f7 402 //else
<> 144:ef7eb2e8f9f7 403 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 return 1; // OK
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407 #endif
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 /******************************************************************************/
<> 144:ef7eb2e8f9f7 410 /* PLL (clocked by HSI) used as System clock source */
<> 144:ef7eb2e8f9f7 411 /******************************************************************************/
<> 144:ef7eb2e8f9f7 412 uint8_t SetSysClock_PLL_HSI(void)
<> 144:ef7eb2e8f9f7 413 {
<> 144:ef7eb2e8f9f7 414 RCC_ClkInitTypeDef RCC_ClkInitStruct;
<> 144:ef7eb2e8f9f7 415 RCC_OscInitTypeDef RCC_OscInitStruct;
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 /* Enable HSI oscillator and activate PLL with HSI as source */
<> 144:ef7eb2e8f9f7 418 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
<> 144:ef7eb2e8f9f7 419 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
<> 144:ef7eb2e8f9f7 420 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
<> 144:ef7eb2e8f9f7 421 RCC_OscInitStruct.HSICalibrationValue = 16;
<> 144:ef7eb2e8f9f7 422 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
<> 144:ef7eb2e8f9f7 423 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
<> 144:ef7eb2e8f9f7 424 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
<> 144:ef7eb2e8f9f7 425 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
<> 144:ef7eb2e8f9f7 426 {
<> 144:ef7eb2e8f9f7 427 return 0; // FAIL
<> 144:ef7eb2e8f9f7 428 }
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
<> 144:ef7eb2e8f9f7 431 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
<> 144:ef7eb2e8f9f7 432 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
<> 144:ef7eb2e8f9f7 433 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 64 MHz
<> 144:ef7eb2e8f9f7 434 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 32 MHz
<> 144:ef7eb2e8f9f7 435 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 MHz
<> 144:ef7eb2e8f9f7 436 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
<> 144:ef7eb2e8f9f7 437 {
<> 144:ef7eb2e8f9f7 438 return 0; // FAIL
<> 144:ef7eb2e8f9f7 439 }
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /* Output clock on MCO1 pin(PA8) for debugging purpose */
<> 144:ef7eb2e8f9f7 442 //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 return 1; // OK
<> 144:ef7eb2e8f9f7 445 }
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /**
<> 144:ef7eb2e8f9f7 448 * @}
<> 144:ef7eb2e8f9f7 449 */
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /**
<> 144:ef7eb2e8f9f7 452 * @}
<> 144:ef7eb2e8f9f7 453 */
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /**
<> 144:ef7eb2e8f9f7 456 * @}
<> 144:ef7eb2e8f9f7 457 */
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 460