shao ziyang
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mbed-dev
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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h@154:1375a99fb16d, 2017-01-02 (annotated)
- Committer:
- shaoziyang
- Date:
- Mon Jan 02 15:52:04 2017 +0000
- Revision:
- 154:1375a99fb16d
- Parent:
- 149:156823d33999
Mbed for ST SensorTile kit, fixed GPIOG bug, add PORTG support.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| <> | 144:ef7eb2e8f9f7 | 1 | /** |
| <> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
| <> | 144:ef7eb2e8f9f7 | 3 | * @file stm32l4xx_hal.h |
| <> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
| <> | 144:ef7eb2e8f9f7 | 5 | * @version V1.5.1 |
| <> | 144:ef7eb2e8f9f7 | 6 | * @date 31-May-2016 |
| <> | 144:ef7eb2e8f9f7 | 7 | * @brief This file contains all the functions prototypes for the HAL |
| <> | 144:ef7eb2e8f9f7 | 8 | * module driver. |
| <> | 144:ef7eb2e8f9f7 | 9 | ****************************************************************************** |
| <> | 144:ef7eb2e8f9f7 | 10 | * @attention |
| <> | 144:ef7eb2e8f9f7 | 11 | * |
| <> | 144:ef7eb2e8f9f7 | 12 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| <> | 144:ef7eb2e8f9f7 | 13 | * |
| <> | 144:ef7eb2e8f9f7 | 14 | * Redistribution and use in source and binary forms, with or without modification, |
| <> | 144:ef7eb2e8f9f7 | 15 | * are permitted provided that the following conditions are met: |
| <> | 144:ef7eb2e8f9f7 | 16 | * 1. Redistributions of source code must retain the above copyright notice, |
| <> | 144:ef7eb2e8f9f7 | 17 | * this list of conditions and the following disclaimer. |
| <> | 144:ef7eb2e8f9f7 | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| <> | 144:ef7eb2e8f9f7 | 19 | * this list of conditions and the following disclaimer in the documentation |
| <> | 144:ef7eb2e8f9f7 | 20 | * and/or other materials provided with the distribution. |
| <> | 144:ef7eb2e8f9f7 | 21 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| <> | 144:ef7eb2e8f9f7 | 22 | * may be used to endorse or promote products derived from this software |
| <> | 144:ef7eb2e8f9f7 | 23 | * without specific prior written permission. |
| <> | 144:ef7eb2e8f9f7 | 24 | * |
| <> | 144:ef7eb2e8f9f7 | 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| <> | 144:ef7eb2e8f9f7 | 26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| <> | 144:ef7eb2e8f9f7 | 27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| <> | 144:ef7eb2e8f9f7 | 28 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| <> | 144:ef7eb2e8f9f7 | 29 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| <> | 144:ef7eb2e8f9f7 | 30 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| <> | 144:ef7eb2e8f9f7 | 31 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| <> | 144:ef7eb2e8f9f7 | 32 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| <> | 144:ef7eb2e8f9f7 | 33 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| <> | 144:ef7eb2e8f9f7 | 34 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| <> | 144:ef7eb2e8f9f7 | 35 | * |
| <> | 144:ef7eb2e8f9f7 | 36 | ****************************************************************************** |
| <> | 144:ef7eb2e8f9f7 | 37 | */ |
| <> | 144:ef7eb2e8f9f7 | 38 | |
| <> | 144:ef7eb2e8f9f7 | 39 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| <> | 144:ef7eb2e8f9f7 | 40 | #ifndef __STM32L4xx_HAL_H |
| <> | 144:ef7eb2e8f9f7 | 41 | #define __STM32L4xx_HAL_H |
| <> | 144:ef7eb2e8f9f7 | 42 | |
| <> | 144:ef7eb2e8f9f7 | 43 | #ifdef __cplusplus |
| <> | 144:ef7eb2e8f9f7 | 44 | extern "C" { |
| <> | 144:ef7eb2e8f9f7 | 45 | #endif |
| <> | 144:ef7eb2e8f9f7 | 46 | |
| <> | 144:ef7eb2e8f9f7 | 47 | /* Includes ------------------------------------------------------------------*/ |
| <> | 144:ef7eb2e8f9f7 | 48 | #include "stm32l4xx_hal_conf.h" |
| <> | 144:ef7eb2e8f9f7 | 49 | |
| <> | 144:ef7eb2e8f9f7 | 50 | /** @addtogroup STM32L4xx_HAL_Driver |
| <> | 144:ef7eb2e8f9f7 | 51 | * @{ |
| <> | 144:ef7eb2e8f9f7 | 52 | */ |
| <> | 144:ef7eb2e8f9f7 | 53 | |
| <> | 144:ef7eb2e8f9f7 | 54 | /** @addtogroup HAL |
| <> | 144:ef7eb2e8f9f7 | 55 | * @{ |
| <> | 144:ef7eb2e8f9f7 | 56 | */ |
| <> | 144:ef7eb2e8f9f7 | 57 | |
| <> | 144:ef7eb2e8f9f7 | 58 | /* Exported types ------------------------------------------------------------*/ |
| <> | 144:ef7eb2e8f9f7 | 59 | /* Exported constants --------------------------------------------------------*/ |
| <> | 144:ef7eb2e8f9f7 | 60 | /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants |
| <> | 144:ef7eb2e8f9f7 | 61 | * @{ |
| <> | 144:ef7eb2e8f9f7 | 62 | */ |
| <> | 144:ef7eb2e8f9f7 | 63 | |
| <> | 144:ef7eb2e8f9f7 | 64 | /** @defgroup SYSCFG_BootMode Boot Mode |
| <> | 144:ef7eb2e8f9f7 | 65 | * @{ |
| <> | 144:ef7eb2e8f9f7 | 66 | */ |
| <> | 144:ef7eb2e8f9f7 | 67 | #define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000) |
| <> | 144:ef7eb2e8f9f7 | 68 | #define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 |
| <> | 144:ef7eb2e8f9f7 | 69 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| <> | 144:ef7eb2e8f9f7 | 70 | #define SYSCFG_BOOT_FMC SYSCFG_MEMRMP_MEM_MODE_1 |
| <> | 144:ef7eb2e8f9f7 | 71 | #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
| <> | 144:ef7eb2e8f9f7 | 72 | #define SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) |
| <> | 144:ef7eb2e8f9f7 | 73 | #define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) |
| <> | 144:ef7eb2e8f9f7 | 74 | |
| <> | 144:ef7eb2e8f9f7 | 75 | /** |
| <> | 144:ef7eb2e8f9f7 | 76 | * @} |
| <> | 144:ef7eb2e8f9f7 | 77 | */ |
| <> | 144:ef7eb2e8f9f7 | 78 | |
| <> | 144:ef7eb2e8f9f7 | 79 | /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts |
| <> | 144:ef7eb2e8f9f7 | 80 | * @{ |
| <> | 144:ef7eb2e8f9f7 | 81 | */ |
| <> | 144:ef7eb2e8f9f7 | 82 | #define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ |
| <> | 144:ef7eb2e8f9f7 | 83 | #define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ |
| <> | 144:ef7eb2e8f9f7 | 84 | #define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ |
| <> | 144:ef7eb2e8f9f7 | 85 | #define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ |
| <> | 144:ef7eb2e8f9f7 | 86 | #define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ |
| <> | 144:ef7eb2e8f9f7 | 87 | #define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ |
| <> | 144:ef7eb2e8f9f7 | 88 | |
| <> | 144:ef7eb2e8f9f7 | 89 | /** |
| <> | 144:ef7eb2e8f9f7 | 90 | * @} |
| <> | 144:ef7eb2e8f9f7 | 91 | */ |
| <> | 144:ef7eb2e8f9f7 | 92 | |
| <> | 144:ef7eb2e8f9f7 | 93 | /** @defgroup SYSCFG_SRAM2WRP SRAM2 Write protection |
| <> | 144:ef7eb2e8f9f7 | 94 | * @{ |
| <> | 144:ef7eb2e8f9f7 | 95 | */ |
| <> | 144:ef7eb2e8f9f7 | 96 | #define SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */ |
| <> | 144:ef7eb2e8f9f7 | 97 | #define SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */ |
| <> | 144:ef7eb2e8f9f7 | 98 | #define SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */ |
| <> | 144:ef7eb2e8f9f7 | 99 | #define SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */ |
| <> | 144:ef7eb2e8f9f7 | 100 | #define SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */ |
| <> | 144:ef7eb2e8f9f7 | 101 | #define SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */ |
| <> | 144:ef7eb2e8f9f7 | 102 | #define SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */ |
| <> | 144:ef7eb2e8f9f7 | 103 | #define SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */ |
| <> | 144:ef7eb2e8f9f7 | 104 | #define SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */ |
| <> | 144:ef7eb2e8f9f7 | 105 | #define SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */ |
| <> | 144:ef7eb2e8f9f7 | 106 | #define SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */ |
| <> | 144:ef7eb2e8f9f7 | 107 | #define SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */ |
| <> | 144:ef7eb2e8f9f7 | 108 | #define SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */ |
| <> | 144:ef7eb2e8f9f7 | 109 | #define SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */ |
| <> | 144:ef7eb2e8f9f7 | 110 | #define SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */ |
| <> | 144:ef7eb2e8f9f7 | 111 | #define SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */ |
| <> | 144:ef7eb2e8f9f7 | 112 | #define SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */ |
| <> | 144:ef7eb2e8f9f7 | 113 | #define SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */ |
| <> | 144:ef7eb2e8f9f7 | 114 | #define SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */ |
| <> | 144:ef7eb2e8f9f7 | 115 | #define SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */ |
| <> | 144:ef7eb2e8f9f7 | 116 | #define SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */ |
| <> | 144:ef7eb2e8f9f7 | 117 | #define SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */ |
| <> | 144:ef7eb2e8f9f7 | 118 | #define SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */ |
| <> | 144:ef7eb2e8f9f7 | 119 | #define SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */ |
| <> | 144:ef7eb2e8f9f7 | 120 | #define SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */ |
| <> | 144:ef7eb2e8f9f7 | 121 | #define SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */ |
| <> | 144:ef7eb2e8f9f7 | 122 | #define SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */ |
| <> | 144:ef7eb2e8f9f7 | 123 | #define SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */ |
| <> | 144:ef7eb2e8f9f7 | 124 | #define SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */ |
| <> | 144:ef7eb2e8f9f7 | 125 | #define SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */ |
| <> | 144:ef7eb2e8f9f7 | 126 | #define SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */ |
| <> | 144:ef7eb2e8f9f7 | 127 | #define SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */ |
| <> | 144:ef7eb2e8f9f7 | 128 | |
| <> | 144:ef7eb2e8f9f7 | 129 | /** |
| <> | 144:ef7eb2e8f9f7 | 130 | * @} |
| <> | 144:ef7eb2e8f9f7 | 131 | */ |
| <> | 144:ef7eb2e8f9f7 | 132 | |
| <> | 144:ef7eb2e8f9f7 | 133 | #if defined(VREFBUF) |
| <> | 144:ef7eb2e8f9f7 | 134 | /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale |
| <> | 144:ef7eb2e8f9f7 | 135 | * @{ |
| <> | 144:ef7eb2e8f9f7 | 136 | */ |
| <> | 144:ef7eb2e8f9f7 | 137 | #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ |
| <> | 144:ef7eb2e8f9f7 | 138 | #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */ |
| <> | 144:ef7eb2e8f9f7 | 139 | |
| <> | 144:ef7eb2e8f9f7 | 140 | /** |
| <> | 144:ef7eb2e8f9f7 | 141 | * @} |
| <> | 144:ef7eb2e8f9f7 | 142 | */ |
| <> | 144:ef7eb2e8f9f7 | 143 | |
| <> | 144:ef7eb2e8f9f7 | 144 | /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance |
| <> | 144:ef7eb2e8f9f7 | 145 | * @{ |
| <> | 144:ef7eb2e8f9f7 | 146 | */ |
| <> | 144:ef7eb2e8f9f7 | 147 | #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ |
| <> | 144:ef7eb2e8f9f7 | 148 | #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ |
| <> | 144:ef7eb2e8f9f7 | 149 | |
| <> | 144:ef7eb2e8f9f7 | 150 | /** |
| <> | 144:ef7eb2e8f9f7 | 151 | * @} |
| <> | 144:ef7eb2e8f9f7 | 152 | */ |
| <> | 144:ef7eb2e8f9f7 | 153 | #endif /* VREFBUF */ |
| <> | 144:ef7eb2e8f9f7 | 154 | |
| <> | 144:ef7eb2e8f9f7 | 155 | /** @defgroup SYSCFG_flags_definition Flags |
| <> | 144:ef7eb2e8f9f7 | 156 | * @{ |
| <> | 144:ef7eb2e8f9f7 | 157 | */ |
| <> | 144:ef7eb2e8f9f7 | 158 | |
| <> | 144:ef7eb2e8f9f7 | 159 | #define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */ |
| <> | 144:ef7eb2e8f9f7 | 160 | #define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */ |
| <> | 144:ef7eb2e8f9f7 | 161 | |
| <> | 144:ef7eb2e8f9f7 | 162 | /** |
| <> | 144:ef7eb2e8f9f7 | 163 | * @} |
| <> | 144:ef7eb2e8f9f7 | 164 | */ |
| <> | 144:ef7eb2e8f9f7 | 165 | |
| <> | 144:ef7eb2e8f9f7 | 166 | /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO |
| <> | 144:ef7eb2e8f9f7 | 167 | * @{ |
| <> | 144:ef7eb2e8f9f7 | 168 | */ |
| <> | 144:ef7eb2e8f9f7 | 169 | |
| <> | 144:ef7eb2e8f9f7 | 170 | /** @brief Fast-mode Plus driving capability on a specific GPIO |
| <> | 144:ef7eb2e8f9f7 | 171 | */ |
| <> | 144:ef7eb2e8f9f7 | 172 | #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ |
| <> | 144:ef7eb2e8f9f7 | 173 | #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ |
| <> | 144:ef7eb2e8f9f7 | 174 | #if defined(SYSCFG_CFGR1_I2C_PB8_FMP) |
| <> | 144:ef7eb2e8f9f7 | 175 | #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ |
| <> | 144:ef7eb2e8f9f7 | 176 | #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */ |
| <> | 144:ef7eb2e8f9f7 | 177 | #if defined(SYSCFG_CFGR1_I2C_PB9_FMP) |
| <> | 144:ef7eb2e8f9f7 | 178 | #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ |
| <> | 144:ef7eb2e8f9f7 | 179 | #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */ |
| <> | 144:ef7eb2e8f9f7 | 180 | |
| <> | 144:ef7eb2e8f9f7 | 181 | /** |
| <> | 144:ef7eb2e8f9f7 | 182 | * @} |
| <> | 144:ef7eb2e8f9f7 | 183 | */ |
| <> | 144:ef7eb2e8f9f7 | 184 | |
| <> | 144:ef7eb2e8f9f7 | 185 | /** |
| <> | 144:ef7eb2e8f9f7 | 186 | * @} |
| <> | 144:ef7eb2e8f9f7 | 187 | */ |
| <> | 144:ef7eb2e8f9f7 | 188 | |
| <> | 144:ef7eb2e8f9f7 | 189 | /* Exported macros -----------------------------------------------------------*/ |
| <> | 144:ef7eb2e8f9f7 | 190 | |
| <> | 144:ef7eb2e8f9f7 | 191 | /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros |
| <> | 144:ef7eb2e8f9f7 | 192 | * @{ |
| <> | 144:ef7eb2e8f9f7 | 193 | */ |
| <> | 144:ef7eb2e8f9f7 | 194 | |
| <> | 144:ef7eb2e8f9f7 | 195 | /** @brief Freeze/Unfreeze Peripherals in Debug mode |
| <> | 144:ef7eb2e8f9f7 | 196 | */ |
| <> | 144:ef7eb2e8f9f7 | 197 | #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP) |
| <> | 144:ef7eb2e8f9f7 | 198 | #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) |
| <> | 144:ef7eb2e8f9f7 | 199 | #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) |
| <> | 144:ef7eb2e8f9f7 | 200 | #endif |
| <> | 144:ef7eb2e8f9f7 | 201 | |
| <> | 144:ef7eb2e8f9f7 | 202 | #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP) |
| <> | 144:ef7eb2e8f9f7 | 203 | #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) |
| <> | 144:ef7eb2e8f9f7 | 204 | #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) |
| <> | 144:ef7eb2e8f9f7 | 205 | #endif |
| <> | 144:ef7eb2e8f9f7 | 206 | |
| <> | 144:ef7eb2e8f9f7 | 207 | #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) |
| <> | 144:ef7eb2e8f9f7 | 208 | #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) |
| <> | 144:ef7eb2e8f9f7 | 209 | #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) |
| <> | 144:ef7eb2e8f9f7 | 210 | #endif |
| <> | 144:ef7eb2e8f9f7 | 211 | |
| <> | 144:ef7eb2e8f9f7 | 212 | #if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP) |
| <> | 144:ef7eb2e8f9f7 | 213 | #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) |
| <> | 144:ef7eb2e8f9f7 | 214 | #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) |
| <> | 144:ef7eb2e8f9f7 | 215 | #endif |
| <> | 144:ef7eb2e8f9f7 | 216 | |
| <> | 144:ef7eb2e8f9f7 | 217 | #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) |
| <> | 144:ef7eb2e8f9f7 | 218 | #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) |
| <> | 144:ef7eb2e8f9f7 | 219 | #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) |
| <> | 144:ef7eb2e8f9f7 | 220 | #endif |
| <> | 144:ef7eb2e8f9f7 | 221 | |
| <> | 144:ef7eb2e8f9f7 | 222 | #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP) |
| <> | 144:ef7eb2e8f9f7 | 223 | #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) |
| <> | 144:ef7eb2e8f9f7 | 224 | #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) |
| <> | 144:ef7eb2e8f9f7 | 225 | #endif |
| <> | 144:ef7eb2e8f9f7 | 226 | |
| <> | 144:ef7eb2e8f9f7 | 227 | #if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP) |
| <> | 144:ef7eb2e8f9f7 | 228 | #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) |
| <> | 144:ef7eb2e8f9f7 | 229 | #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) |
| <> | 144:ef7eb2e8f9f7 | 230 | #endif |
| <> | 144:ef7eb2e8f9f7 | 231 | |
| <> | 144:ef7eb2e8f9f7 | 232 | #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP) |
| <> | 144:ef7eb2e8f9f7 | 233 | #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) |
| <> | 144:ef7eb2e8f9f7 | 234 | #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) |
| <> | 144:ef7eb2e8f9f7 | 235 | #endif |
| <> | 144:ef7eb2e8f9f7 | 236 | |
| <> | 144:ef7eb2e8f9f7 | 237 | #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP) |
| <> | 144:ef7eb2e8f9f7 | 238 | #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) |
| <> | 144:ef7eb2e8f9f7 | 239 | #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) |
| <> | 144:ef7eb2e8f9f7 | 240 | #endif |
| <> | 144:ef7eb2e8f9f7 | 241 | |
| <> | 144:ef7eb2e8f9f7 | 242 | #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP) |
| <> | 144:ef7eb2e8f9f7 | 243 | #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) |
| <> | 144:ef7eb2e8f9f7 | 244 | #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) |
| <> | 144:ef7eb2e8f9f7 | 245 | #endif |
| <> | 144:ef7eb2e8f9f7 | 246 | |
| <> | 144:ef7eb2e8f9f7 | 247 | #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP) |
| <> | 144:ef7eb2e8f9f7 | 248 | #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) |
| <> | 144:ef7eb2e8f9f7 | 249 | #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) |
| <> | 144:ef7eb2e8f9f7 | 250 | #endif |
| <> | 144:ef7eb2e8f9f7 | 251 | |
| <> | 144:ef7eb2e8f9f7 | 252 | #if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP) |
| <> | 144:ef7eb2e8f9f7 | 253 | #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) |
| <> | 144:ef7eb2e8f9f7 | 254 | #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) |
| <> | 144:ef7eb2e8f9f7 | 255 | #endif |
| <> | 144:ef7eb2e8f9f7 | 256 | |
| <> | 144:ef7eb2e8f9f7 | 257 | #if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP) |
| <> | 144:ef7eb2e8f9f7 | 258 | #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP) |
| <> | 144:ef7eb2e8f9f7 | 259 | #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP) |
| <> | 144:ef7eb2e8f9f7 | 260 | #endif |
| <> | 144:ef7eb2e8f9f7 | 261 | |
| <> | 144:ef7eb2e8f9f7 | 262 | #if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) |
| <> | 144:ef7eb2e8f9f7 | 263 | #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) |
| <> | 144:ef7eb2e8f9f7 | 264 | #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) |
| <> | 144:ef7eb2e8f9f7 | 265 | #endif |
| <> | 144:ef7eb2e8f9f7 | 266 | |
| <> | 144:ef7eb2e8f9f7 | 267 | #if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) |
| <> | 144:ef7eb2e8f9f7 | 268 | #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) |
| <> | 144:ef7eb2e8f9f7 | 269 | #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) |
| <> | 144:ef7eb2e8f9f7 | 270 | #endif |
| <> | 144:ef7eb2e8f9f7 | 271 | |
| <> | 144:ef7eb2e8f9f7 | 272 | #if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP) |
| <> | 144:ef7eb2e8f9f7 | 273 | #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) |
| <> | 144:ef7eb2e8f9f7 | 274 | #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) |
| <> | 144:ef7eb2e8f9f7 | 275 | #endif |
| <> | 144:ef7eb2e8f9f7 | 276 | |
| <> | 144:ef7eb2e8f9f7 | 277 | #if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP) |
| <> | 144:ef7eb2e8f9f7 | 278 | #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) |
| <> | 144:ef7eb2e8f9f7 | 279 | #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) |
| <> | 144:ef7eb2e8f9f7 | 280 | #endif |
| <> | 144:ef7eb2e8f9f7 | 281 | |
| <> | 144:ef7eb2e8f9f7 | 282 | #if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP) |
| <> | 144:ef7eb2e8f9f7 | 283 | #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) |
| <> | 144:ef7eb2e8f9f7 | 284 | #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) |
| <> | 144:ef7eb2e8f9f7 | 285 | #endif |
| <> | 144:ef7eb2e8f9f7 | 286 | |
| <> | 144:ef7eb2e8f9f7 | 287 | #if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP) |
| <> | 144:ef7eb2e8f9f7 | 288 | #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) |
| <> | 144:ef7eb2e8f9f7 | 289 | #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) |
| <> | 144:ef7eb2e8f9f7 | 290 | #endif |
| <> | 144:ef7eb2e8f9f7 | 291 | |
| <> | 144:ef7eb2e8f9f7 | 292 | #if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP) |
| <> | 144:ef7eb2e8f9f7 | 293 | #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) |
| <> | 144:ef7eb2e8f9f7 | 294 | #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) |
| <> | 144:ef7eb2e8f9f7 | 295 | #endif |
| <> | 144:ef7eb2e8f9f7 | 296 | |
| <> | 144:ef7eb2e8f9f7 | 297 | /** |
| <> | 144:ef7eb2e8f9f7 | 298 | * @} |
| <> | 144:ef7eb2e8f9f7 | 299 | */ |
| <> | 144:ef7eb2e8f9f7 | 300 | |
| <> | 144:ef7eb2e8f9f7 | 301 | /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros |
| <> | 144:ef7eb2e8f9f7 | 302 | * @{ |
| <> | 144:ef7eb2e8f9f7 | 303 | */ |
| <> | 144:ef7eb2e8f9f7 | 304 | |
| <> | 144:ef7eb2e8f9f7 | 305 | /** @brief Main Flash memory mapped at 0x00000000. |
| <> | 144:ef7eb2e8f9f7 | 306 | */ |
| <> | 144:ef7eb2e8f9f7 | 307 | #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) |
| <> | 144:ef7eb2e8f9f7 | 308 | |
| <> | 144:ef7eb2e8f9f7 | 309 | /** @brief System Flash memory mapped at 0x00000000. |
| <> | 144:ef7eb2e8f9f7 | 310 | */ |
| <> | 144:ef7eb2e8f9f7 | 311 | #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0) |
| <> | 144:ef7eb2e8f9f7 | 312 | |
| <> | 144:ef7eb2e8f9f7 | 313 | /** @brief Embedded SRAM mapped at 0x00000000. |
| <> | 144:ef7eb2e8f9f7 | 314 | */ |
| <> | 144:ef7eb2e8f9f7 | 315 | #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0)) |
| <> | 144:ef7eb2e8f9f7 | 316 | |
| <> | 144:ef7eb2e8f9f7 | 317 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| <> | 144:ef7eb2e8f9f7 | 318 | /** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000. |
| <> | 144:ef7eb2e8f9f7 | 319 | */ |
| <> | 144:ef7eb2e8f9f7 | 320 | #define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1) |
| <> | 144:ef7eb2e8f9f7 | 321 | #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
| <> | 144:ef7eb2e8f9f7 | 322 | |
| <> | 144:ef7eb2e8f9f7 | 323 | /** @brief QUADSPI mapped at 0x00000000. |
| <> | 144:ef7eb2e8f9f7 | 324 | */ |
| <> | 144:ef7eb2e8f9f7 | 325 | #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1)) |
| <> | 144:ef7eb2e8f9f7 | 326 | |
| <> | 144:ef7eb2e8f9f7 | 327 | /** |
| <> | 144:ef7eb2e8f9f7 | 328 | * @brief Return the boot mode as configured by user. |
| <> | 144:ef7eb2e8f9f7 | 329 | * @retval The boot mode as configured by user. The returned value can be one |
| <> | 144:ef7eb2e8f9f7 | 330 | * of the following values: |
| <> | 144:ef7eb2e8f9f7 | 331 | * @arg @ref SYSCFG_BOOT_MAINFLASH |
| <> | 144:ef7eb2e8f9f7 | 332 | * @arg @ref SYSCFG_BOOT_SYSTEMFLASH |
| <> | 144:ef7eb2e8f9f7 | 333 | @if STM32L486xx |
| <> | 144:ef7eb2e8f9f7 | 334 | * @arg @ref SYSCFG_BOOT_FMC |
| <> | 144:ef7eb2e8f9f7 | 335 | @endif |
| <> | 144:ef7eb2e8f9f7 | 336 | * @arg @ref SYSCFG_BOOT_SRAM |
| <> | 144:ef7eb2e8f9f7 | 337 | * @arg @ref SYSCFG_BOOT_QUADSPI |
| <> | 144:ef7eb2e8f9f7 | 338 | */ |
| <> | 144:ef7eb2e8f9f7 | 339 | #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) |
| <> | 144:ef7eb2e8f9f7 | 340 | |
| <> | 144:ef7eb2e8f9f7 | 341 | /** @brief SRAM2 page write protection enable macro |
| <> | 144:ef7eb2e8f9f7 | 342 | * @param __SRAM2WRP__: This parameter can be a value of @ref SYSCFG_SRAM2WRP |
| <> | 144:ef7eb2e8f9f7 | 343 | * @note write protection can only be disabled by a system reset |
| <> | 144:ef7eb2e8f9f7 | 344 | */ |
| <> | 144:ef7eb2e8f9f7 | 345 | #define __HAL_SYSCFG_SRAM2_WRP_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ |
| <> | 144:ef7eb2e8f9f7 | 346 | SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\ |
| <> | 144:ef7eb2e8f9f7 | 347 | }while(0) |
| <> | 144:ef7eb2e8f9f7 | 348 | |
| <> | 144:ef7eb2e8f9f7 | 349 | /** @brief SRAM2 page write protection unlock prior to erase |
| <> | 144:ef7eb2e8f9f7 | 350 | * @note Writing a wrong key reactivates the write protection |
| <> | 144:ef7eb2e8f9f7 | 351 | */ |
| <> | 144:ef7eb2e8f9f7 | 352 | #define __HAL_SYSCFG_SRAM2_WRP_UNLOCK() do {SYSCFG->SKR = 0xCA;\ |
| <> | 144:ef7eb2e8f9f7 | 353 | SYSCFG->SKR = 0x53;\ |
| <> | 144:ef7eb2e8f9f7 | 354 | }while(0) |
| <> | 144:ef7eb2e8f9f7 | 355 | |
| <> | 144:ef7eb2e8f9f7 | 356 | /** @brief SRAM2 erase |
| <> | 144:ef7eb2e8f9f7 | 357 | * @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase |
| <> | 144:ef7eb2e8f9f7 | 358 | */ |
| <> | 144:ef7eb2e8f9f7 | 359 | #define __HAL_SYSCFG_SRAM2_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER) |
| <> | 144:ef7eb2e8f9f7 | 360 | |
| <> | 144:ef7eb2e8f9f7 | 361 | /** @brief Floating Point Unit interrupt enable/disable macros |
| <> | 144:ef7eb2e8f9f7 | 362 | * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts |
| <> | 144:ef7eb2e8f9f7 | 363 | */ |
| <> | 144:ef7eb2e8f9f7 | 364 | #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ |
| <> | 144:ef7eb2e8f9f7 | 365 | SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ |
| <> | 144:ef7eb2e8f9f7 | 366 | }while(0) |
| <> | 144:ef7eb2e8f9f7 | 367 | |
| <> | 144:ef7eb2e8f9f7 | 368 | #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ |
| <> | 144:ef7eb2e8f9f7 | 369 | CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ |
| <> | 144:ef7eb2e8f9f7 | 370 | }while(0) |
| <> | 144:ef7eb2e8f9f7 | 371 | |
| <> | 144:ef7eb2e8f9f7 | 372 | /** @brief SYSCFG Break ECC lock. |
| <> | 144:ef7eb2e8f9f7 | 373 | * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. |
| <> | 144:ef7eb2e8f9f7 | 374 | * @note The selected configuration is locked and can be unlocked only by system reset. |
| <> | 144:ef7eb2e8f9f7 | 375 | */ |
| <> | 144:ef7eb2e8f9f7 | 376 | #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) |
| <> | 144:ef7eb2e8f9f7 | 377 | |
| <> | 144:ef7eb2e8f9f7 | 378 | /** @brief SYSCFG Break Cortex-M4 Lockup lock. |
| <> | 144:ef7eb2e8f9f7 | 379 | * Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. |
| <> | 144:ef7eb2e8f9f7 | 380 | * @note The selected configuration is locked and can be unlocked only by system reset. |
| <> | 144:ef7eb2e8f9f7 | 381 | */ |
| <> | 144:ef7eb2e8f9f7 | 382 | #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) |
| <> | 144:ef7eb2e8f9f7 | 383 | |
| <> | 144:ef7eb2e8f9f7 | 384 | /** @brief SYSCFG Break PVD lock. |
| <> | 144:ef7eb2e8f9f7 | 385 | * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register. |
| <> | 144:ef7eb2e8f9f7 | 386 | * @note The selected configuration is locked and can be unlocked only by system reset. |
| <> | 144:ef7eb2e8f9f7 | 387 | */ |
| <> | 144:ef7eb2e8f9f7 | 388 | #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) |
| <> | 144:ef7eb2e8f9f7 | 389 | |
| <> | 144:ef7eb2e8f9f7 | 390 | /** @brief SYSCFG Break SRAM2 parity lock. |
| <> | 144:ef7eb2e8f9f7 | 391 | * Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input. |
| <> | 144:ef7eb2e8f9f7 | 392 | * @note The selected configuration is locked and can be unlocked by system reset. |
| <> | 144:ef7eb2e8f9f7 | 393 | */ |
| <> | 144:ef7eb2e8f9f7 | 394 | #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) |
| <> | 144:ef7eb2e8f9f7 | 395 | |
| <> | 144:ef7eb2e8f9f7 | 396 | /** @brief Check SYSCFG flag is set or not. |
| <> | 144:ef7eb2e8f9f7 | 397 | * @param __FLAG__: specifies the flag to check. |
| <> | 144:ef7eb2e8f9f7 | 398 | * This parameter can be one of the following values: |
| <> | 144:ef7eb2e8f9f7 | 399 | * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag |
| <> | 144:ef7eb2e8f9f7 | 400 | * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing |
| <> | 144:ef7eb2e8f9f7 | 401 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| <> | 144:ef7eb2e8f9f7 | 402 | */ |
| <> | 144:ef7eb2e8f9f7 | 403 | #define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0) ? 1 : 0) |
| <> | 144:ef7eb2e8f9f7 | 404 | |
| <> | 144:ef7eb2e8f9f7 | 405 | /** @brief Set the SPF bit to clear the SRAM Parity Error Flag. |
| <> | 144:ef7eb2e8f9f7 | 406 | */ |
| <> | 144:ef7eb2e8f9f7 | 407 | #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) |
| <> | 144:ef7eb2e8f9f7 | 408 | |
| <> | 144:ef7eb2e8f9f7 | 409 | /** @brief Fast-mode Plus driving capability enable/disable macros |
| <> | 144:ef7eb2e8f9f7 | 410 | * @param __FASTMODEPLUS__: This parameter can be a value of : |
| <> | 144:ef7eb2e8f9f7 | 411 | * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 |
| <> | 144:ef7eb2e8f9f7 | 412 | * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 |
| <> | 144:ef7eb2e8f9f7 | 413 | * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 |
| <> | 144:ef7eb2e8f9f7 | 414 | * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 |
| <> | 144:ef7eb2e8f9f7 | 415 | */ |
| <> | 144:ef7eb2e8f9f7 | 416 | #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ |
| <> | 144:ef7eb2e8f9f7 | 417 | SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ |
| <> | 144:ef7eb2e8f9f7 | 418 | }while(0) |
| <> | 144:ef7eb2e8f9f7 | 419 | |
| <> | 144:ef7eb2e8f9f7 | 420 | #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ |
| <> | 144:ef7eb2e8f9f7 | 421 | CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ |
| <> | 144:ef7eb2e8f9f7 | 422 | }while(0) |
| <> | 144:ef7eb2e8f9f7 | 423 | |
| <> | 144:ef7eb2e8f9f7 | 424 | /** |
| <> | 144:ef7eb2e8f9f7 | 425 | * @} |
| <> | 144:ef7eb2e8f9f7 | 426 | */ |
| <> | 144:ef7eb2e8f9f7 | 427 | |
| <> | 144:ef7eb2e8f9f7 | 428 | /* Private macros ------------------------------------------------------------*/ |
| <> | 144:ef7eb2e8f9f7 | 429 | /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros |
| <> | 144:ef7eb2e8f9f7 | 430 | * @{ |
| <> | 144:ef7eb2e8f9f7 | 431 | */ |
| <> | 144:ef7eb2e8f9f7 | 432 | |
| <> | 144:ef7eb2e8f9f7 | 433 | #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ |
| <> | 144:ef7eb2e8f9f7 | 434 | (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ |
| <> | 144:ef7eb2e8f9f7 | 435 | (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ |
| <> | 144:ef7eb2e8f9f7 | 436 | (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ |
| <> | 144:ef7eb2e8f9f7 | 437 | (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ |
| <> | 144:ef7eb2e8f9f7 | 438 | (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) |
| <> | 144:ef7eb2e8f9f7 | 439 | |
| <> | 144:ef7eb2e8f9f7 | 440 | #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ |
| <> | 144:ef7eb2e8f9f7 | 441 | ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ |
| <> | 144:ef7eb2e8f9f7 | 442 | ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ |
| <> | 144:ef7eb2e8f9f7 | 443 | ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) |
| <> | 144:ef7eb2e8f9f7 | 444 | |
| <> | 144:ef7eb2e8f9f7 | 445 | #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= 0xFFFFFFFF)) |
| <> | 144:ef7eb2e8f9f7 | 446 | |
| <> | 144:ef7eb2e8f9f7 | 447 | #if defined(VREFBUF) |
| <> | 144:ef7eb2e8f9f7 | 448 | #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ |
| <> | 144:ef7eb2e8f9f7 | 449 | ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1)) |
| <> | 144:ef7eb2e8f9f7 | 450 | |
| <> | 144:ef7eb2e8f9f7 | 451 | #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ |
| <> | 144:ef7eb2e8f9f7 | 452 | ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) |
| <> | 144:ef7eb2e8f9f7 | 453 | |
| <> | 144:ef7eb2e8f9f7 | 454 | #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) |
| <> | 144:ef7eb2e8f9f7 | 455 | #endif /* VREFBUF */ |
| <> | 144:ef7eb2e8f9f7 | 456 | |
| <> | 144:ef7eb2e8f9f7 | 457 | #if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9) |
| <> | 144:ef7eb2e8f9f7 | 458 | #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ |
| <> | 144:ef7eb2e8f9f7 | 459 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ |
| <> | 144:ef7eb2e8f9f7 | 460 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ |
| <> | 144:ef7eb2e8f9f7 | 461 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) |
| <> | 144:ef7eb2e8f9f7 | 462 | #elif defined(SYSCFG_FASTMODEPLUS_PB8) |
| <> | 144:ef7eb2e8f9f7 | 463 | #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ |
| <> | 144:ef7eb2e8f9f7 | 464 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ |
| <> | 144:ef7eb2e8f9f7 | 465 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8)) |
| <> | 144:ef7eb2e8f9f7 | 466 | #elif defined(SYSCFG_FASTMODEPLUS_PB9) |
| <> | 144:ef7eb2e8f9f7 | 467 | #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ |
| <> | 144:ef7eb2e8f9f7 | 468 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ |
| <> | 144:ef7eb2e8f9f7 | 469 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) |
| <> | 144:ef7eb2e8f9f7 | 470 | #else |
| <> | 144:ef7eb2e8f9f7 | 471 | #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ |
| <> | 144:ef7eb2e8f9f7 | 472 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7)) |
| <> | 144:ef7eb2e8f9f7 | 473 | #endif |
| <> | 144:ef7eb2e8f9f7 | 474 | /** |
| <> | 144:ef7eb2e8f9f7 | 475 | * @} |
| <> | 144:ef7eb2e8f9f7 | 476 | */ |
| <> | 144:ef7eb2e8f9f7 | 477 | |
| <> | 144:ef7eb2e8f9f7 | 478 | /* Exported functions --------------------------------------------------------*/ |
| <> | 144:ef7eb2e8f9f7 | 479 | |
| <> | 144:ef7eb2e8f9f7 | 480 | /** @addtogroup HAL_Exported_Functions |
| <> | 144:ef7eb2e8f9f7 | 481 | * @{ |
| <> | 144:ef7eb2e8f9f7 | 482 | */ |
| <> | 144:ef7eb2e8f9f7 | 483 | |
| <> | 144:ef7eb2e8f9f7 | 484 | /** @addtogroup HAL_Exported_Functions_Group1 |
| <> | 144:ef7eb2e8f9f7 | 485 | * @{ |
| <> | 144:ef7eb2e8f9f7 | 486 | */ |
| <> | 144:ef7eb2e8f9f7 | 487 | |
| <> | 144:ef7eb2e8f9f7 | 488 | /* Initialization and de-initialization functions ******************************/ |
| <> | 144:ef7eb2e8f9f7 | 489 | HAL_StatusTypeDef HAL_Init(void); |
| <> | 144:ef7eb2e8f9f7 | 490 | HAL_StatusTypeDef HAL_DeInit(void); |
| <> | 144:ef7eb2e8f9f7 | 491 | void HAL_MspInit(void); |
| <> | 144:ef7eb2e8f9f7 | 492 | void HAL_MspDeInit(void); |
| <> | 144:ef7eb2e8f9f7 | 493 | HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); |
| <> | 144:ef7eb2e8f9f7 | 494 | |
| <> | 144:ef7eb2e8f9f7 | 495 | /** |
| <> | 144:ef7eb2e8f9f7 | 496 | * @} |
| <> | 144:ef7eb2e8f9f7 | 497 | */ |
| <> | 144:ef7eb2e8f9f7 | 498 | |
| <> | 144:ef7eb2e8f9f7 | 499 | /** @addtogroup HAL_Exported_Functions_Group2 |
| <> | 144:ef7eb2e8f9f7 | 500 | * @{ |
| <> | 144:ef7eb2e8f9f7 | 501 | */ |
| <> | 144:ef7eb2e8f9f7 | 502 | |
| <> | 144:ef7eb2e8f9f7 | 503 | /* Peripheral Control functions ************************************************/ |
| <> | 144:ef7eb2e8f9f7 | 504 | void HAL_IncTick(void); |
| <> | 144:ef7eb2e8f9f7 | 505 | void HAL_Delay(uint32_t Delay); |
| <> | 144:ef7eb2e8f9f7 | 506 | uint32_t HAL_GetTick(void); |
| <> | 144:ef7eb2e8f9f7 | 507 | void HAL_SuspendTick(void); |
| <> | 144:ef7eb2e8f9f7 | 508 | void HAL_ResumeTick(void); |
| <> | 144:ef7eb2e8f9f7 | 509 | uint32_t HAL_GetHalVersion(void); |
| <> | 144:ef7eb2e8f9f7 | 510 | uint32_t HAL_GetREVID(void); |
| <> | 144:ef7eb2e8f9f7 | 511 | uint32_t HAL_GetDEVID(void); |
| <> | 144:ef7eb2e8f9f7 | 512 | |
| <> | 144:ef7eb2e8f9f7 | 513 | /** |
| <> | 144:ef7eb2e8f9f7 | 514 | * @} |
| <> | 144:ef7eb2e8f9f7 | 515 | */ |
| <> | 144:ef7eb2e8f9f7 | 516 | |
| <> | 144:ef7eb2e8f9f7 | 517 | /** @addtogroup HAL_Exported_Functions_Group3 |
| <> | 144:ef7eb2e8f9f7 | 518 | * @{ |
| <> | 144:ef7eb2e8f9f7 | 519 | */ |
| <> | 144:ef7eb2e8f9f7 | 520 | |
| <> | 144:ef7eb2e8f9f7 | 521 | /* DBGMCU Peripheral Control functions *****************************************/ |
| <> | 144:ef7eb2e8f9f7 | 522 | void HAL_DBGMCU_EnableDBGSleepMode(void); |
| <> | 144:ef7eb2e8f9f7 | 523 | void HAL_DBGMCU_DisableDBGSleepMode(void); |
| <> | 144:ef7eb2e8f9f7 | 524 | void HAL_DBGMCU_EnableDBGStopMode(void); |
| <> | 144:ef7eb2e8f9f7 | 525 | void HAL_DBGMCU_DisableDBGStopMode(void); |
| <> | 144:ef7eb2e8f9f7 | 526 | void HAL_DBGMCU_EnableDBGStandbyMode(void); |
| <> | 144:ef7eb2e8f9f7 | 527 | void HAL_DBGMCU_DisableDBGStandbyMode(void); |
| <> | 144:ef7eb2e8f9f7 | 528 | |
| <> | 144:ef7eb2e8f9f7 | 529 | /** |
| <> | 144:ef7eb2e8f9f7 | 530 | * @} |
| <> | 144:ef7eb2e8f9f7 | 531 | */ |
| <> | 144:ef7eb2e8f9f7 | 532 | |
| <> | 144:ef7eb2e8f9f7 | 533 | /** @addtogroup HAL_Exported_Functions_Group4 |
| <> | 144:ef7eb2e8f9f7 | 534 | * @{ |
| <> | 144:ef7eb2e8f9f7 | 535 | */ |
| <> | 144:ef7eb2e8f9f7 | 536 | |
| <> | 144:ef7eb2e8f9f7 | 537 | /* SYSCFG Control functions ****************************************************/ |
| <> | 144:ef7eb2e8f9f7 | 538 | void HAL_SYSCFG_SRAM2Erase(void); |
| <> | 144:ef7eb2e8f9f7 | 539 | void HAL_SYSCFG_EnableMemorySwappingBank(void); |
| <> | 144:ef7eb2e8f9f7 | 540 | void HAL_SYSCFG_DisableMemorySwappingBank(void); |
| <> | 144:ef7eb2e8f9f7 | 541 | |
| <> | 144:ef7eb2e8f9f7 | 542 | #if defined(VREFBUF) |
| <> | 144:ef7eb2e8f9f7 | 543 | void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); |
| <> | 144:ef7eb2e8f9f7 | 544 | void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); |
| <> | 144:ef7eb2e8f9f7 | 545 | void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); |
| <> | 144:ef7eb2e8f9f7 | 546 | HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); |
| <> | 144:ef7eb2e8f9f7 | 547 | void HAL_SYSCFG_DisableVREFBUF(void); |
| <> | 144:ef7eb2e8f9f7 | 548 | #endif /* VREFBUF */ |
| <> | 144:ef7eb2e8f9f7 | 549 | |
| <> | 144:ef7eb2e8f9f7 | 550 | void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); |
| <> | 144:ef7eb2e8f9f7 | 551 | void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); |
| <> | 144:ef7eb2e8f9f7 | 552 | |
| <> | 144:ef7eb2e8f9f7 | 553 | /** |
| <> | 144:ef7eb2e8f9f7 | 554 | * @} |
| <> | 144:ef7eb2e8f9f7 | 555 | */ |
| <> | 144:ef7eb2e8f9f7 | 556 | |
| <> | 144:ef7eb2e8f9f7 | 557 | /** |
| <> | 144:ef7eb2e8f9f7 | 558 | * @} |
| <> | 144:ef7eb2e8f9f7 | 559 | */ |
| <> | 144:ef7eb2e8f9f7 | 560 | |
| <> | 144:ef7eb2e8f9f7 | 561 | /** |
| <> | 144:ef7eb2e8f9f7 | 562 | * @} |
| <> | 144:ef7eb2e8f9f7 | 563 | */ |
| <> | 144:ef7eb2e8f9f7 | 564 | |
| <> | 144:ef7eb2e8f9f7 | 565 | /** |
| <> | 144:ef7eb2e8f9f7 | 566 | * @} |
| <> | 144:ef7eb2e8f9f7 | 567 | */ |
| <> | 144:ef7eb2e8f9f7 | 568 | |
| <> | 144:ef7eb2e8f9f7 | 569 | #ifdef __cplusplus |
| <> | 144:ef7eb2e8f9f7 | 570 | } |
| <> | 144:ef7eb2e8f9f7 | 571 | #endif |
| <> | 144:ef7eb2e8f9f7 | 572 | |
| <> | 144:ef7eb2e8f9f7 | 573 | #endif /* __STM32L4xx_HAL_H */ |
| <> | 144:ef7eb2e8f9f7 | 574 | |
| <> | 144:ef7eb2e8f9f7 | 575 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |