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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.c@149:156823d33999, 2016-10-28 (annotated)

Committer:: <>
Date:: Fri Oct 28 11:17:30 2016 +0100
Revision:: 149:156823d33999
Parent:: targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_adc.c@144:ef7eb2e8f9f7

This updates the lib to the mbed lib v128

NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32l4xx_hal_adc.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application conversion
<>	144:ef7eb2e8f9f7	5	* @version V1.5.1
<>	144:ef7eb2e8f9f7	6	* @date 31-May-2016
<>	144:ef7eb2e8f9f7	7	* @brief This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	8	* functionalities of the Analog to Digital Convertor (ADC)
<>	144:ef7eb2e8f9f7	9	* peripheral:
<>	144:ef7eb2e8f9f7	10	* + Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	11	* ++ Configuration of ADC
<>	144:ef7eb2e8f9f7	12	* + Operation functions
<>	144:ef7eb2e8f9f7	13	* ++ Start, stop, get result of regular conversions of regular
<>	144:ef7eb2e8f9f7	14	* using 3 possible modes: polling, interruption or DMA.
<>	144:ef7eb2e8f9f7	15	* + Control functions
<>	144:ef7eb2e8f9f7	16	* ++ Analog Watchdog configuration
<>	144:ef7eb2e8f9f7	17	* ++ Channels configuration on regular group
<>	144:ef7eb2e8f9f7	18	* + State functions
<>	144:ef7eb2e8f9f7	19	* ++ ADC state machine management
<>	144:ef7eb2e8f9f7	20	* ++ Interrupts and flags management
<>	144:ef7eb2e8f9f7	21	*
<>	144:ef7eb2e8f9f7	22	@verbatim
<>	144:ef7eb2e8f9f7	23	==============================================================================
<>	144:ef7eb2e8f9f7	24	##### ADC specific features #####
<>	144:ef7eb2e8f9f7	25	==============================================================================
<>	144:ef7eb2e8f9f7	26	[..]
<>	144:ef7eb2e8f9f7	27	(#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
<>	144:ef7eb2e8f9f7	28
<>	144:ef7eb2e8f9f7	29	(#) Interrupt generation at the end of regular conversion and in case of
<>	144:ef7eb2e8f9f7	30	analog watchdog and overrun events.
<>	144:ef7eb2e8f9f7	31
<>	144:ef7eb2e8f9f7	32	(#) Single and continuous conversion modes.
<>	144:ef7eb2e8f9f7	33
<>	144:ef7eb2e8f9f7	34	(#) Scan mode for automatic conversion of channel 0 to channel 'n'.
<>	144:ef7eb2e8f9f7	35
<>	144:ef7eb2e8f9f7	36	(#) Data alignment with in-built data coherency.
<>	144:ef7eb2e8f9f7	37
<>	144:ef7eb2e8f9f7	38	(#) Channel-wise programmable sampling time.
<>	144:ef7eb2e8f9f7	39
<>	144:ef7eb2e8f9f7	40	(#) External trigger (timer or EXTI) with configurable polarity for
<>	144:ef7eb2e8f9f7	41	regular groups.
<>	144:ef7eb2e8f9f7	42
<>	144:ef7eb2e8f9f7	43	(#) DMA request generation for transfer of regular group converted data.
<>	144:ef7eb2e8f9f7	44
<>	144:ef7eb2e8f9f7	45	(#) Configurable delay between conversions in Dual interleaved mode.
<>	144:ef7eb2e8f9f7	46
<>	144:ef7eb2e8f9f7	47	(#) ADC channels selectable single/differential input.
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	(#) ADC offset on regular groups.
<>	144:ef7eb2e8f9f7	50
<>	144:ef7eb2e8f9f7	51	(#) ADC supply requirements: 1.62 V to 3.6 V.
<>	144:ef7eb2e8f9f7	52
<>	144:ef7eb2e8f9f7	53	(#) ADC input range: from Vref_ (connected to Vssa) to Vref+ (connected to
<>	144:ef7eb2e8f9f7	54	Vdda or to an external voltage reference).
<>	144:ef7eb2e8f9f7	55
<>	144:ef7eb2e8f9f7	56
<>	144:ef7eb2e8f9f7	57
<>	144:ef7eb2e8f9f7	58	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	59	==============================================================================
<>	144:ef7eb2e8f9f7	60	[..]
<>	144:ef7eb2e8f9f7	61
<>	144:ef7eb2e8f9f7	62	(#) Enable the ADC interface
<>	144:ef7eb2e8f9f7	63	As prerequisite, in HAL_ADC_MspInit(), ADC clock source must be
<>	144:ef7eb2e8f9f7	64	configured at RCC top level.
<>	144:ef7eb2e8f9f7	65
<>	144:ef7eb2e8f9f7	66	Two different clock sources are available:
<>	144:ef7eb2e8f9f7	67	(++) - the ADC clock can be a specific clock source, coming from the system
<>	144:ef7eb2e8f9f7	68	clock, the PLLSAI1 or the PLLSAI2 running up to 80MHz.
<>	144:ef7eb2e8f9f7	69	(++) - or the ADC clock can be derived from the AHB clock of the ADC bus
<>	144:ef7eb2e8f9f7	70	interface, divided by a programmable factor
<>	144:ef7eb2e8f9f7	71
<>	144:ef7eb2e8f9f7	72
<>	144:ef7eb2e8f9f7	73	(++) For example, in case of PLLSAI2:
<>	144:ef7eb2e8f9f7	74	(+++) __HAL_RCC_ADC_CLK_ENABLE();
<>	144:ef7eb2e8f9f7	75	(+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
<>	144:ef7eb2e8f9f7	76	(+++) where
<>	144:ef7eb2e8f9f7	77	(+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
<>	144:ef7eb2e8f9f7	78	(+++) PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI2
<>	144:ef7eb2e8f9f7	79
<>	144:ef7eb2e8f9f7	80
<>	144:ef7eb2e8f9f7	81	(#) ADC pins configuration
<>	144:ef7eb2e8f9f7	82	(++) Enable the clock for the ADC GPIOs using the following function:
<>	144:ef7eb2e8f9f7	83	__HAL_RCC_GPIOx_CLK_ENABLE();
<>	144:ef7eb2e8f9f7	84	(++) Configure these ADC pins in analog mode using HAL_GPIO_Init();
<>	144:ef7eb2e8f9f7	85
<>	144:ef7eb2e8f9f7	86	(#) Configure the ADC parameters (conversion resolution, data alignment,
<>	144:ef7eb2e8f9f7	87	continuous mode, ...) using the HAL_ADC_Init() function.
<>	144:ef7eb2e8f9f7	88
<>	144:ef7eb2e8f9f7	89	(#) Optionally, perform an automatic ADC calibration to improve the
<>	144:ef7eb2e8f9f7	90	conversion accuracy using function HAL_ADCEx_Calibration_Start().
<>	144:ef7eb2e8f9f7	91
<>	144:ef7eb2e8f9f7	92	(#) Activate the ADC peripheral using one of the start functions:
<>	144:ef7eb2e8f9f7	93	HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADC_Start_DMA(),
<>	144:ef7eb2e8f9f7	94	HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT() or
<>	144:ef7eb2e8f9f7	95	HAL_ADCEx_MultiModeStart_DMA() when multimode feature is available.
<>	144:ef7eb2e8f9f7	96
<>	144:ef7eb2e8f9f7	97	* Channels to regular group configuration *
<>	144:ef7eb2e8f9f7	98	============================================
<>	144:ef7eb2e8f9f7	99	[..]
<>	144:ef7eb2e8f9f7	100	(+) To configure the ADC regular group features, use
<>	144:ef7eb2e8f9f7	101	HAL_ADC_Init() and HAL_ADC_ConfigChannel() functions.
<>	144:ef7eb2e8f9f7	102	(+) To activate the continuous mode, use the HAL_ADC_Init() function.
<>	144:ef7eb2e8f9f7	103	(+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
<>	144:ef7eb2e8f9f7	104
<>	144:ef7eb2e8f9f7	105	* DMA for regular configuration *
<>	144:ef7eb2e8f9f7	106	=============================================================
<>	144:ef7eb2e8f9f7	107	[..]
<>	144:ef7eb2e8f9f7	108	(+) To enable the DMA mode for regular group, use the
<>	144:ef7eb2e8f9f7	109	HAL_ADC_Start_DMA() function.
<>	144:ef7eb2e8f9f7	110	(+) To enable the generation of DMA requests continuously at the end of
<>	144:ef7eb2e8f9f7	111	the last DMA transfer, resort to DMAContinuousRequests parameter of
<>	144:ef7eb2e8f9f7	112	ADC handle initialization structure.
<>	144:ef7eb2e8f9f7	113
<>	144:ef7eb2e8f9f7	114
<>	144:ef7eb2e8f9f7	115
<>	144:ef7eb2e8f9f7	116	@endverbatim
<>	144:ef7eb2e8f9f7	117	******************************************************************************
<>	144:ef7eb2e8f9f7	118	* @attention
<>	144:ef7eb2e8f9f7	119	*
<>	144:ef7eb2e8f9f7	120	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	121	*
<>	144:ef7eb2e8f9f7	122	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	123	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	124	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	125	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	126	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	127	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	128	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	129	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	130	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	131	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	132	*
<>	144:ef7eb2e8f9f7	133	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	134	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	135	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	136	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	137	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	138	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	139	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	140	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	141	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	142	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	143	*
<>	144:ef7eb2e8f9f7	144	******************************************************************************
<>	144:ef7eb2e8f9f7	145	*/
<>	144:ef7eb2e8f9f7	146
<>	144:ef7eb2e8f9f7	147	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	148	#include "stm32l4xx_hal.h"
<>	144:ef7eb2e8f9f7	149
<>	144:ef7eb2e8f9f7	150	/** @addtogroup STM32L4xx_HAL_Driver
<>	144:ef7eb2e8f9f7	151	* @{
<>	144:ef7eb2e8f9f7	152	*/
<>	144:ef7eb2e8f9f7	153
<>	144:ef7eb2e8f9f7	154	/** @defgroup ADC ADC
<>	144:ef7eb2e8f9f7	155	* @brief ADC HAL module driver
<>	144:ef7eb2e8f9f7	156	* @{
<>	144:ef7eb2e8f9f7	157	*/
<>	144:ef7eb2e8f9f7	158
<>	144:ef7eb2e8f9f7	159	#ifdef HAL_ADC_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	160
<>	144:ef7eb2e8f9f7	161	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	162	/* Private define ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	163
<>	144:ef7eb2e8f9f7	164	/** @defgroup ADC_Private_Constants ADC Private Constants
<>	144:ef7eb2e8f9f7	165	* @{
<>	144:ef7eb2e8f9f7	166	*/
<>	144:ef7eb2e8f9f7	167
<>	144:ef7eb2e8f9f7	168	#define ADC_CFGR_FIELDS_1 ((uint32_t)(ADC_CFGR_RES \| ADC_CFGR_ALIGN \|\
<>	144:ef7eb2e8f9f7	169	ADC_CFGR_CONT \| ADC_CFGR_OVRMOD \|\
<>	144:ef7eb2e8f9f7	170	ADC_CFGR_DISCEN \| ADC_CFGR_DISCNUM \|\
<>	144:ef7eb2e8f9f7	171	ADC_CFGR_EXTEN \| ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated
<>	144:ef7eb2e8f9f7	172	when no regular conversion is on-going */
<>	144:ef7eb2e8f9f7	173
<>	144:ef7eb2e8f9f7	174	#define ADC_CFGR2_FIELDS ((uint32_t)(ADC_CFGR2_ROVSE \| ADC_CFGR2_OVSR \|\
<>	144:ef7eb2e8f9f7	175	ADC_CFGR2_OVSS \| ADC_CFGR2_TROVS \|\
<>	144:ef7eb2e8f9f7	176	ADC_CFGR2_ROVSM)) /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion
<>	144:ef7eb2e8f9f7	177	(neither regular nor injected) is on-going */
<>	144:ef7eb2e8f9f7	178
<>	144:ef7eb2e8f9f7	179	#define ADC_CFGR_WD_FIELDS ((uint32_t)(ADC_CFGR_AWD1SGL \| ADC_CFGR_JAWD1EN \| \
<>	144:ef7eb2e8f9f7	180	ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1CH)) /*!< ADC_CFGR fields of Analog Watchdog parameters that can be updated when no
<>	144:ef7eb2e8f9f7	181	conversion (neither regular nor injected) is on-going */
<>	144:ef7eb2e8f9f7	182
<>	144:ef7eb2e8f9f7	183	#define ADC_OFR_FIELDS ((uint32_t)(ADC_OFR1_OFFSET1 \| ADC_OFR1_OFFSET1_CH \| ADC_OFR1_OFFSET1_EN)) /*!< ADC_OFR fields of parameters that can be updated when no conversion
<>	144:ef7eb2e8f9f7	184	(neither regular nor injected) is on-going */
<>	144:ef7eb2e8f9f7	185
<>	144:ef7eb2e8f9f7	186
<>	144:ef7eb2e8f9f7	187
<>	144:ef7eb2e8f9f7	188	/* Delay to wait before setting ADEN once ADCAL has been reset
<>	144:ef7eb2e8f9f7	189	must be at least 4 ADC clock cycles.
<>	144:ef7eb2e8f9f7	190	Assuming lowest ADC clock (140 KHz according to DS), this
<>	144:ef7eb2e8f9f7	191	4 ADC clock cycles duration is equal to
<>	144:ef7eb2e8f9f7	192	4 / 140,000 = 0.028 ms.
<>	144:ef7eb2e8f9f7	193	ADC_ENABLE_TIMEOUT set to 2 is a margin large enough to ensure
<>	144:ef7eb2e8f9f7	194	the 4 ADC clock cycles have elapsed while waiting for ADRDY
<>	144:ef7eb2e8f9f7	195	to become 1 */
<>	144:ef7eb2e8f9f7	196	#define ADC_ENABLE_TIMEOUT ((uint32_t) 2) /!< ADC enable time-out value /
<>	144:ef7eb2e8f9f7	197	#define ADC_DISABLE_TIMEOUT ((uint32_t) 2) /!< ADC disable time-out value /
<>	144:ef7eb2e8f9f7	198
<>	144:ef7eb2e8f9f7	199
<>	144:ef7eb2e8f9f7	200
<>	144:ef7eb2e8f9f7	201	/* Delay for ADC voltage regulator startup time */
<>	144:ef7eb2e8f9f7	202	/* Maximum delay is 10 microseconds */
<>	144:ef7eb2e8f9f7	203	/* (refer device RM, parameter Tadcvreg_stup). */
<>	144:ef7eb2e8f9f7	204	#define ADC_STAB_DELAY_US ((uint32_t) 10) /!< ADC voltage regulator startup time /
<>	144:ef7eb2e8f9f7	205
<>	144:ef7eb2e8f9f7	206
<>	144:ef7eb2e8f9f7	207	/* Timeout to wait for current conversion on going to be completed. */
<>	144:ef7eb2e8f9f7	208	/* Timeout fixed to worst case, for 1 channel. */
<>	144:ef7eb2e8f9f7	209	/* - maximum sampling time (640.5 adc_clk) */
<>	144:ef7eb2e8f9f7	210	/* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */
<>	144:ef7eb2e8f9f7	211	/* - ADC clock with prescaler 256 */
<>	144:ef7eb2e8f9f7	212	/* 653 * 256 = 167168 clock cycles max */
<>	144:ef7eb2e8f9f7	213	/* Unit: cycles of CPU clock. */
<>	144:ef7eb2e8f9f7	214	#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 167168) /!< ADC conversion completion time-out value /
<>	144:ef7eb2e8f9f7	215
<>	144:ef7eb2e8f9f7	216
<>	144:ef7eb2e8f9f7	217
<>	144:ef7eb2e8f9f7	218
<>	144:ef7eb2e8f9f7	219	/**
<>	144:ef7eb2e8f9f7	220	* @}
<>	144:ef7eb2e8f9f7	221	*/
<>	144:ef7eb2e8f9f7	222
<>	144:ef7eb2e8f9f7	223	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	224	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	225	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	226	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	227
<>	144:ef7eb2e8f9f7	228	/** @defgroup ADC_Exported_Functions ADC Exported Functions
<>	144:ef7eb2e8f9f7	229	* @{
<>	144:ef7eb2e8f9f7	230	*/
<>	144:ef7eb2e8f9f7	231
<>	144:ef7eb2e8f9f7	232	/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	233	* @brief Initialization and Configuration functions
<>	144:ef7eb2e8f9f7	234	*
<>	144:ef7eb2e8f9f7	235	@verbatim
<>	144:ef7eb2e8f9f7	236	===============================================================================
<>	144:ef7eb2e8f9f7	237	##### Initialization and de-initialization functions #####
<>	144:ef7eb2e8f9f7	238	===============================================================================
<>	144:ef7eb2e8f9f7	239	[..] This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	240	(+) Initialize and configure the ADC.
<>	144:ef7eb2e8f9f7	241	(+) De-initialize the ADC.
<>	144:ef7eb2e8f9f7	242
<>	144:ef7eb2e8f9f7	243	@endverbatim
<>	144:ef7eb2e8f9f7	244	* @{
<>	144:ef7eb2e8f9f7	245	*/
<>	144:ef7eb2e8f9f7	246
<>	144:ef7eb2e8f9f7	247	/**
<>	144:ef7eb2e8f9f7	248	* @brief Initialize the ADC peripheral and regular group according to
<>	144:ef7eb2e8f9f7	249	* parameters specified in structure "ADC_InitTypeDef".
<>	144:ef7eb2e8f9f7	250	* @note As prerequisite, ADC clock must be configured at RCC top level
<>	144:ef7eb2e8f9f7	251	* depending on possible clock sources: System/PLLSAI1/PLLSAI2 clocks
<>	144:ef7eb2e8f9f7	252	* or AHB clock.
<>	144:ef7eb2e8f9f7	253	* @note Possibility to update parameters on the fly:
<>	144:ef7eb2e8f9f7	254	* this function initializes the ADC MSP (HAL_ADC_MspInit()) only when
<>	144:ef7eb2e8f9f7	255	* coming from ADC state reset. Following calls to this function can
<>	144:ef7eb2e8f9f7	256	* be used to reconfigure some parameters of ADC_InitTypeDef
<>	144:ef7eb2e8f9f7	257	* structure on the fly, without modifying MSP configuration. If ADC
<>	144:ef7eb2e8f9f7	258	* MSP has to be modified again, HAL_ADC_DeInit() must be called
<>	144:ef7eb2e8f9f7	259	* before HAL_ADC_Init().
<>	144:ef7eb2e8f9f7	260	* The setting of these parameters is conditioned by ADC state.
<>	144:ef7eb2e8f9f7	261	* For parameters constraints, see comments of structure
<>	144:ef7eb2e8f9f7	262	* "ADC_InitTypeDef".
<>	144:ef7eb2e8f9f7	263	* @note This function configures the ADC within 2 scopes: scope of entire
<>	144:ef7eb2e8f9f7	264	* ADC and scope of regular group. For parameters details, see comments
<>	144:ef7eb2e8f9f7	265	* of structure "ADC_InitTypeDef".
<>	144:ef7eb2e8f9f7	266	* @note Parameters related to common ADC registers (ADC clock mode) are set
<>	144:ef7eb2e8f9f7	267	* only if all ADCs are disabled.
<>	144:ef7eb2e8f9f7	268	* If this is not the case, these common parameters setting are
<>	144:ef7eb2e8f9f7	269	* bypassed without error reporting: it can be the intended behaviour in
<>	144:ef7eb2e8f9f7	270	* case of update of a parameter of ADC_InitTypeDef on the fly,
<>	144:ef7eb2e8f9f7	271	* without disabling the other ADCs.
<>	144:ef7eb2e8f9f7	272	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	273	* @retval HAL status
<>	144:ef7eb2e8f9f7	274	*/
<>	144:ef7eb2e8f9f7	275	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	276	{
<>	144:ef7eb2e8f9f7	277	HAL_StatusTypeDef tmp_status = HAL_OK;
<>	144:ef7eb2e8f9f7	278
<>	144:ef7eb2e8f9f7	279	ADC_Common_TypeDef *tmpADC_Common;
<>	144:ef7eb2e8f9f7	280	uint32_t tmpCFGR = 0;
<>	144:ef7eb2e8f9f7	281	__IO uint32_t wait_loop_index = 0;
<>	144:ef7eb2e8f9f7	282
<>	144:ef7eb2e8f9f7	283	/* Check ADC handle */
<>	144:ef7eb2e8f9f7	284	if(hadc == NULL)
<>	144:ef7eb2e8f9f7	285	{
<>	144:ef7eb2e8f9f7	286	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	287	}
<>	144:ef7eb2e8f9f7	288
<>	144:ef7eb2e8f9f7	289	/* Check the parameters */
<>	144:ef7eb2e8f9f7	290	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	291	assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
<>	144:ef7eb2e8f9f7	292	assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
<>	144:ef7eb2e8f9f7	293	assert_param(IS_ADC_DFSDMCFG_MODE(hadc));
<>	144:ef7eb2e8f9f7	294	assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
<>	144:ef7eb2e8f9f7	295	assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
<>	144:ef7eb2e8f9f7	296	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
<>	144:ef7eb2e8f9f7	297	assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
<>	144:ef7eb2e8f9f7	298	assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
<>	144:ef7eb2e8f9f7	299	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
<>	144:ef7eb2e8f9f7	300	assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
<>	144:ef7eb2e8f9f7	301	assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
<>	144:ef7eb2e8f9f7	302	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
<>	144:ef7eb2e8f9f7	303	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
<>	144:ef7eb2e8f9f7	304
<>	144:ef7eb2e8f9f7	305	if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
<>	144:ef7eb2e8f9f7	306	{
<>	144:ef7eb2e8f9f7	307	assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
<>	144:ef7eb2e8f9f7	308	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
<>	144:ef7eb2e8f9f7	309
<>	144:ef7eb2e8f9f7	310	if (hadc->Init.DiscontinuousConvMode == ENABLE)
<>	144:ef7eb2e8f9f7	311	{
<>	144:ef7eb2e8f9f7	312	assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
<>	144:ef7eb2e8f9f7	313	}
<>	144:ef7eb2e8f9f7	314	}
<>	144:ef7eb2e8f9f7	315
<>	144:ef7eb2e8f9f7	316
<>	144:ef7eb2e8f9f7	317	/* DISCEN and CONT bits can't be set at the same time */
<>	144:ef7eb2e8f9f7	318	assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
<>	144:ef7eb2e8f9f7	319
<>	144:ef7eb2e8f9f7	320
<>	144:ef7eb2e8f9f7	321	/* Actions performed only if ADC is coming from state reset: */
<>	144:ef7eb2e8f9f7	322	/* - Initialization of ADC MSP */
<>	144:ef7eb2e8f9f7	323	if (hadc->State == HAL_ADC_STATE_RESET)
<>	144:ef7eb2e8f9f7	324	{
<>	144:ef7eb2e8f9f7	325	/* Init the low level hardware */
<>	144:ef7eb2e8f9f7	326	HAL_ADC_MspInit(hadc);
<>	144:ef7eb2e8f9f7	327
<>	144:ef7eb2e8f9f7	328	/* Set ADC error code to none */
<>	144:ef7eb2e8f9f7	329	ADC_CLEAR_ERRORCODE(hadc);
<>	144:ef7eb2e8f9f7	330
<>	144:ef7eb2e8f9f7	331	/* Initialize Lock */
<>	144:ef7eb2e8f9f7	332	hadc->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	333	}
<>	144:ef7eb2e8f9f7	334
<>	144:ef7eb2e8f9f7	335
<>	144:ef7eb2e8f9f7	336	/* - Exit from deep-power-down mode and ADC voltage regulator enable */
<>	144:ef7eb2e8f9f7	337	/* Exit deep power down mode if still in that state */
<>	144:ef7eb2e8f9f7	338	if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_DEEPPWD))
<>	144:ef7eb2e8f9f7	339	{
<>	144:ef7eb2e8f9f7	340	/* Exit deep power down mode */
<>	144:ef7eb2e8f9f7	341	CLEAR_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
<>	144:ef7eb2e8f9f7	342
<>	144:ef7eb2e8f9f7	343	/* System was in deep power down mode, calibration must
<>	144:ef7eb2e8f9f7	344	be relaunched or a previously saved calibration factor
<>	144:ef7eb2e8f9f7	345	re-applied once the ADC voltage regulator is enabled */
<>	144:ef7eb2e8f9f7	346	}
<>	144:ef7eb2e8f9f7	347
<>	144:ef7eb2e8f9f7	348
<>	144:ef7eb2e8f9f7	349	if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
<>	144:ef7eb2e8f9f7	350	{
<>	144:ef7eb2e8f9f7	351	/* Enable ADC internal voltage regulator */
<>	144:ef7eb2e8f9f7	352	SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
<>	144:ef7eb2e8f9f7	353
<>	144:ef7eb2e8f9f7	354	/* Delay for ADC stabilization time */
<>	144:ef7eb2e8f9f7	355	/* Wait loop initialization and execution */
<>	144:ef7eb2e8f9f7	356	/* Note: Variable divided by 2 to compensate partially */
<>	144:ef7eb2e8f9f7	357	/* CPU processing cycles. */
<>	144:ef7eb2e8f9f7	358	wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / (1000000 * 2)));
<>	144:ef7eb2e8f9f7	359	while(wait_loop_index != 0)
<>	144:ef7eb2e8f9f7	360	{
<>	144:ef7eb2e8f9f7	361	wait_loop_index--;
<>	144:ef7eb2e8f9f7	362	}
<>	144:ef7eb2e8f9f7	363	}
<>	144:ef7eb2e8f9f7	364
<>	144:ef7eb2e8f9f7	365
<>	144:ef7eb2e8f9f7	366
<>	144:ef7eb2e8f9f7	367
<>	144:ef7eb2e8f9f7	368	/* Verification that ADC voltage regulator is correctly enabled, whether */
<>	144:ef7eb2e8f9f7	369	/* or not ADC is coming from state reset (if any potential problem of */
<>	144:ef7eb2e8f9f7	370	/* clocking, voltage regulator would not be enabled). */
<>	144:ef7eb2e8f9f7	371	if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
<>	144:ef7eb2e8f9f7	372	{
<>	144:ef7eb2e8f9f7	373	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	374	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	375
<>	144:ef7eb2e8f9f7	376	/* Set ADC error code to ADC IP internal error */
<>	144:ef7eb2e8f9f7	377	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	378
<>	144:ef7eb2e8f9f7	379	tmp_status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	380	}
<>	144:ef7eb2e8f9f7	381
<>	144:ef7eb2e8f9f7	382
<>	144:ef7eb2e8f9f7	383	/* Configuration of ADC parameters if previous preliminary actions are */
<>	144:ef7eb2e8f9f7	384	/* correctly completed and if there is no conversion on going on regular */
<>	144:ef7eb2e8f9f7	385	/* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
<>	144:ef7eb2e8f9f7	386	/* called to update a parameter on the fly). */
<>	144:ef7eb2e8f9f7	387	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
<>	144:ef7eb2e8f9f7	388	(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) )
<>	144:ef7eb2e8f9f7	389	{
<>	144:ef7eb2e8f9f7	390
<>	144:ef7eb2e8f9f7	391	/* Initialize the ADC state */
<>	144:ef7eb2e8f9f7	392	SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
<>	144:ef7eb2e8f9f7	393
<>	144:ef7eb2e8f9f7	394	/* Configuration of common ADC parameters */
<>	144:ef7eb2e8f9f7	395
<>	144:ef7eb2e8f9f7	396	/* Pointer to the common control register */
<>	144:ef7eb2e8f9f7	397	tmpADC_Common = ADC_COMMON_REGISTER(hadc);
<>	144:ef7eb2e8f9f7	398
<>	144:ef7eb2e8f9f7	399
<>	144:ef7eb2e8f9f7	400	/* Parameters update conditioned to ADC state: */
<>	144:ef7eb2e8f9f7	401	/* Parameters that can be updated only when ADC is disabled: */
<>	144:ef7eb2e8f9f7	402	/* - clock configuration */
<>	144:ef7eb2e8f9f7	403	if ((ADC_IS_ENABLE(hadc) == RESET) &&
<>	144:ef7eb2e8f9f7	404	(ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
<>	144:ef7eb2e8f9f7	405	{
<>	144:ef7eb2e8f9f7	406	/* Reset configuration of ADC common register CCR: */
<>	144:ef7eb2e8f9f7	407	/* */
<>	144:ef7eb2e8f9f7	408	/* - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set */
<>	144:ef7eb2e8f9f7	409	/* according to adc->Init.ClockPrescaler. It selects the clock */
<>	144:ef7eb2e8f9f7	410	/* source and sets the clock division factor. */
<>	144:ef7eb2e8f9f7	411	/* */
<>	144:ef7eb2e8f9f7	412	/* Some parameters of this register are not reset, since they are set */
<>	144:ef7eb2e8f9f7	413	/* by other functions and must be kept in case of usage of this */
<>	144:ef7eb2e8f9f7	414	/* function on the fly (update of a parameter of ADC_InitTypeDef */
<>	144:ef7eb2e8f9f7	415	/* without needing to reconfigure all other ADC groups/channels */
<>	144:ef7eb2e8f9f7	416	/* parameters): */
<>	144:ef7eb2e8f9f7	417	/* - when multimode feature is available, multimode-related */
<>	144:ef7eb2e8f9f7	418	/* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */
<>	144:ef7eb2e8f9f7	419	/* HAL_ADCEx_MultiModeConfigChannel() ) */
<>	144:ef7eb2e8f9f7	420	/* - internal measurement paths: Vbat, temperature sensor, Vref */
<>	144:ef7eb2e8f9f7	421	/* (set into HAL_ADC_ConfigChannel() or */
<>	144:ef7eb2e8f9f7	422	/* HAL_ADCEx_InjectedConfigChannel() ) */
<>	144:ef7eb2e8f9f7	423
<>	144:ef7eb2e8f9f7	424	MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_PRESC\|ADC_CCR_CKMODE, hadc->Init.ClockPrescaler);
<>	144:ef7eb2e8f9f7	425	}
<>	144:ef7eb2e8f9f7	426
<>	144:ef7eb2e8f9f7	427
<>	144:ef7eb2e8f9f7	428	/* Configuration of ADC: */
<>	144:ef7eb2e8f9f7	429	/* - resolution Init.Resolution */
<>	144:ef7eb2e8f9f7	430	/* - data alignment Init.DataAlign */
<>	144:ef7eb2e8f9f7	431	/* - external trigger to start conversion Init.ExternalTrigConv */
<>	144:ef7eb2e8f9f7	432	/* - external trigger polarity Init.ExternalTrigConvEdge */
<>	144:ef7eb2e8f9f7	433	/* - continuous conversion mode Init.ContinuousConvMode */
<>	144:ef7eb2e8f9f7	434	/* - overrun Init.Overrun */
<>	144:ef7eb2e8f9f7	435	/* - discontinuous mode Init.DiscontinuousConvMode */
<>	144:ef7eb2e8f9f7	436	/* - discontinuous mode channel count Init.NbrOfDiscConversion */
<>	144:ef7eb2e8f9f7	437	tmpCFGR = ( ADC_CFGR_CONTINUOUS(hadc->Init.ContinuousConvMode) \|
<>	144:ef7eb2e8f9f7	438	hadc->Init.Overrun \|
<>	144:ef7eb2e8f9f7	439	hadc->Init.DataAlign \|
<>	144:ef7eb2e8f9f7	440	hadc->Init.Resolution \|
<>	144:ef7eb2e8f9f7	441	ADC_CFGR_REG_DISCONTINUOUS(hadc->Init.DiscontinuousConvMode) \|
<>	144:ef7eb2e8f9f7	442	ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) );
<>	144:ef7eb2e8f9f7	443
<>	144:ef7eb2e8f9f7	444	/* Enable external trigger if trigger selection is different of software */
<>	144:ef7eb2e8f9f7	445	/* start. */
<>	144:ef7eb2e8f9f7	446	/* - external trigger to start conversion Init.ExternalTrigConv */
<>	144:ef7eb2e8f9f7	447	/* - external trigger polarity Init.ExternalTrigConvEdge */
<>	144:ef7eb2e8f9f7	448	/* Note: parameter ExternalTrigConvEdge set to "trigger edge none" is */
<>	144:ef7eb2e8f9f7	449	/* equivalent to software start. */
<>	144:ef7eb2e8f9f7	450	if ((hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
<>	144:ef7eb2e8f9f7	451	&& (hadc->Init.ExternalTrigConvEdge != ADC_EXTERNALTRIGCONVEDGE_NONE))
<>	144:ef7eb2e8f9f7	452	{
<>	144:ef7eb2e8f9f7	453	tmpCFGR \|= ( hadc->Init.ExternalTrigConv \| hadc->Init.ExternalTrigConvEdge);
<>	144:ef7eb2e8f9f7	454	}
<>	144:ef7eb2e8f9f7	455
<>	144:ef7eb2e8f9f7	456	/* Update Configuration Register CFGR */
<>	144:ef7eb2e8f9f7	457	MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
<>	144:ef7eb2e8f9f7	458
<>	144:ef7eb2e8f9f7	459
<>	144:ef7eb2e8f9f7	460	/* Parameters update conditioned to ADC state: */
<>	144:ef7eb2e8f9f7	461	/* Parameters that can be updated when ADC is disabled or enabled without */
<>	144:ef7eb2e8f9f7	462	/* conversion on going on regular and injected groups: */
<>	144:ef7eb2e8f9f7	463	/* - DMA continuous request Init.DMAContinuousRequests */
<>	144:ef7eb2e8f9f7	464	/* - LowPowerAutoWait feature Init.LowPowerAutoWait */
<>	144:ef7eb2e8f9f7	465	/* - Oversampling parameters Init.Oversampling */
<>	144:ef7eb2e8f9f7	466	if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
<>	144:ef7eb2e8f9f7	467	{
<>	144:ef7eb2e8f9f7	468	tmpCFGR = ( ADC_CFGR_DFSDM(hadc) \|
<>	144:ef7eb2e8f9f7	469	ADC_CFGR_AUTOWAIT(hadc->Init.LowPowerAutoWait) \|
<>	144:ef7eb2e8f9f7	470	ADC_CFGR_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
<>	144:ef7eb2e8f9f7	471
<>	144:ef7eb2e8f9f7	472	MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
<>	144:ef7eb2e8f9f7	473
<>	144:ef7eb2e8f9f7	474
<>	144:ef7eb2e8f9f7	475	if (hadc->Init.OversamplingMode == ENABLE)
<>	144:ef7eb2e8f9f7	476	{
<>	144:ef7eb2e8f9f7	477	assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
<>	144:ef7eb2e8f9f7	478	assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
<>	144:ef7eb2e8f9f7	479	assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
<>	144:ef7eb2e8f9f7	480	assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
<>	144:ef7eb2e8f9f7	481
<>	144:ef7eb2e8f9f7	482	if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START)
<>	144:ef7eb2e8f9f7	483	\|\| (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
<>	144:ef7eb2e8f9f7	484	{
<>	144:ef7eb2e8f9f7	485	/* Multi trigger is not applicable to software-triggered conversions */
<>	144:ef7eb2e8f9f7	486	assert_param((hadc->Init.Oversampling.TriggeredMode == ADC_TRIGGEREDMODE_SINGLE_TRIGGER));
<>	144:ef7eb2e8f9f7	487	}
<>	144:ef7eb2e8f9f7	488
<>	144:ef7eb2e8f9f7	489
<>	144:ef7eb2e8f9f7	490	/* Configuration of Oversampler: */
<>	144:ef7eb2e8f9f7	491	/* - Oversampling Ratio */
<>	144:ef7eb2e8f9f7	492	/* - Right bit shift */
<>	144:ef7eb2e8f9f7	493	/* - Triggered mode */
<>	144:ef7eb2e8f9f7	494	/* - Oversampling mode (continued/resumed) */
<>	144:ef7eb2e8f9f7	495	MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
<>	144:ef7eb2e8f9f7	496	ADC_CFGR2_ROVSE \|
<>	144:ef7eb2e8f9f7	497	hadc->Init.Oversampling.Ratio \|
<>	144:ef7eb2e8f9f7	498	hadc->Init.Oversampling.RightBitShift \|
<>	144:ef7eb2e8f9f7	499	hadc->Init.Oversampling.TriggeredMode \|
<>	144:ef7eb2e8f9f7	500	hadc->Init.Oversampling.OversamplingStopReset);
<>	144:ef7eb2e8f9f7	501	}
<>	144:ef7eb2e8f9f7	502	else
<>	144:ef7eb2e8f9f7	503	{
<>	144:ef7eb2e8f9f7	504	/* Disable Regular OverSampling */
<>	144:ef7eb2e8f9f7	505	CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
<>	144:ef7eb2e8f9f7	506	}
<>	144:ef7eb2e8f9f7	507
<>	144:ef7eb2e8f9f7	508
<>	144:ef7eb2e8f9f7	509	} /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
<>	144:ef7eb2e8f9f7	510
<>	144:ef7eb2e8f9f7	511
<>	144:ef7eb2e8f9f7	512
<>	144:ef7eb2e8f9f7	513
<>	144:ef7eb2e8f9f7	514	/* Configuration of regular group sequencer: */
<>	144:ef7eb2e8f9f7	515	/* - if scan mode is disabled, regular channels sequence length is set to */
<>	144:ef7eb2e8f9f7	516	/* 0x00: 1 channel converted (channel on regular rank 1) */
<>	144:ef7eb2e8f9f7	517	/* Parameter "NbrOfConversion" is discarded. */
<>	144:ef7eb2e8f9f7	518	/* Note: Scan mode is not present by hardware on this device, but */
<>	144:ef7eb2e8f9f7	519	/* emulated by software for alignment over all STM32 devices. */
<>	144:ef7eb2e8f9f7	520	/* - if scan mode is enabled, regular channels sequence length is set to */
<>	144:ef7eb2e8f9f7	521	/* parameter "NbrOfConversion" */
<>	144:ef7eb2e8f9f7	522
<>	144:ef7eb2e8f9f7	523	if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
<>	144:ef7eb2e8f9f7	524	{
<>	144:ef7eb2e8f9f7	525	/* Set number of ranks in regular group sequencer */
<>	144:ef7eb2e8f9f7	526	MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
<>	144:ef7eb2e8f9f7	527	}
<>	144:ef7eb2e8f9f7	528	else
<>	144:ef7eb2e8f9f7	529	{
<>	144:ef7eb2e8f9f7	530	CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
<>	144:ef7eb2e8f9f7	531	}
<>	144:ef7eb2e8f9f7	532
<>	144:ef7eb2e8f9f7	533
<>	144:ef7eb2e8f9f7	534	/* Initialize the ADC state */
<>	144:ef7eb2e8f9f7	535	/* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
<>	144:ef7eb2e8f9f7	536	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
<>	144:ef7eb2e8f9f7	537	}
<>	144:ef7eb2e8f9f7	538	else
<>	144:ef7eb2e8f9f7	539	{
<>	144:ef7eb2e8f9f7	540	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	541	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	542
<>	144:ef7eb2e8f9f7	543	tmp_status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	544	} /* if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) */
<>	144:ef7eb2e8f9f7	545
<>	144:ef7eb2e8f9f7	546
<>	144:ef7eb2e8f9f7	547	/* Return function status */
<>	144:ef7eb2e8f9f7	548	return tmp_status;
<>	144:ef7eb2e8f9f7	549
<>	144:ef7eb2e8f9f7	550	}
<>	144:ef7eb2e8f9f7	551
<>	144:ef7eb2e8f9f7	552	/**
<>	144:ef7eb2e8f9f7	553	* @brief Deinitialize the ADC peripheral registers to their default reset
<>	144:ef7eb2e8f9f7	554	* values, with deinitialization of the ADC MSP.
<>	144:ef7eb2e8f9f7	555	* @note Keep in mind that all ADCs use the same clock: disabling
<>	144:ef7eb2e8f9f7	556	* the clock will reset all ADCs.
<>	144:ef7eb2e8f9f7	557	* @note By default, HAL_ADC_DeInit() sets DEEPPWD: this saves more power by
<>	144:ef7eb2e8f9f7	558	* reducing the leakage currents and is particularly interesting before
<>	144:ef7eb2e8f9f7	559	* entering STOP 1 or STOP 2 modes.
<>	144:ef7eb2e8f9f7	560	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	561	* @retval HAL status
<>	144:ef7eb2e8f9f7	562	*/
<>	144:ef7eb2e8f9f7	563	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	564	{
<>	144:ef7eb2e8f9f7	565	/* Check ADC handle */
<>	144:ef7eb2e8f9f7	566	if(hadc == NULL)
<>	144:ef7eb2e8f9f7	567	{
<>	144:ef7eb2e8f9f7	568	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	569	}
<>	144:ef7eb2e8f9f7	570
<>	144:ef7eb2e8f9f7	571	/* Check the parameters */
<>	144:ef7eb2e8f9f7	572	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	573
<>	144:ef7eb2e8f9f7	574	/* Change ADC state */
<>	144:ef7eb2e8f9f7	575	SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
<>	144:ef7eb2e8f9f7	576
<>	144:ef7eb2e8f9f7	577	/* Stop potential conversion on going, on regular and injected groups */
<>	144:ef7eb2e8f9f7	578	/* No check on ADC_ConversionStop() return status, if the conversion
<>	144:ef7eb2e8f9f7	579	stop failed, it is up to HAL_ADC_MspDeInit() to reset the ADC IP */
<>	144:ef7eb2e8f9f7	580	ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
<>	144:ef7eb2e8f9f7	581
<>	144:ef7eb2e8f9f7	582
<>	144:ef7eb2e8f9f7	583	/* Disable ADC peripheral if conversions are effectively stopped */
<>	144:ef7eb2e8f9f7	584	/* Flush register JSQR: reset the queue sequencer when injected */
<>	144:ef7eb2e8f9f7	585	/* queue sequencer is enabled and ADC disabled. */
<>	144:ef7eb2e8f9f7	586	/* The software and hardware triggers of the injected sequence are both */
<>	144:ef7eb2e8f9f7	587	/* internally disabled just after the completion of the last valid */
<>	144:ef7eb2e8f9f7	588	/* injected sequence. */
<>	144:ef7eb2e8f9f7	589	SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
<>	144:ef7eb2e8f9f7	590
<>	144:ef7eb2e8f9f7	591	/* Disable the ADC peripheral */
<>	144:ef7eb2e8f9f7	592	/* No check on ADC_Disable() return status, if the ADC disabling process
<>	144:ef7eb2e8f9f7	593	failed, it is up to HAL_ADC_MspDeInit() to reset the ADC IP */
<>	144:ef7eb2e8f9f7	594	ADC_Disable(hadc);
<>	144:ef7eb2e8f9f7	595
<>	144:ef7eb2e8f9f7	596
<>	144:ef7eb2e8f9f7	597	/* ========== Reset ADC registers ========== */
<>	144:ef7eb2e8f9f7	598	/* Reset register IER */
<>	144:ef7eb2e8f9f7	599	__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 \| ADC_IT_AWD2 \| ADC_IT_AWD1 \|
<>	144:ef7eb2e8f9f7	600	ADC_IT_JQOVF \| ADC_IT_OVR \|
<>	144:ef7eb2e8f9f7	601	ADC_IT_JEOS \| ADC_IT_JEOC \|
<>	144:ef7eb2e8f9f7	602	ADC_IT_EOS \| ADC_IT_EOC \|
<>	144:ef7eb2e8f9f7	603	ADC_IT_EOSMP \| ADC_IT_RDY ) );
<>	144:ef7eb2e8f9f7	604
<>	144:ef7eb2e8f9f7	605	/* Reset register ISR */
<>	144:ef7eb2e8f9f7	606	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 \| ADC_FLAG_AWD2 \| ADC_FLAG_AWD1 \|
<>	144:ef7eb2e8f9f7	607	ADC_FLAG_JQOVF \| ADC_FLAG_OVR \|
<>	144:ef7eb2e8f9f7	608	ADC_FLAG_JEOS \| ADC_FLAG_JEOC \|
<>	144:ef7eb2e8f9f7	609	ADC_FLAG_EOS \| ADC_FLAG_EOC \|
<>	144:ef7eb2e8f9f7	610	ADC_FLAG_EOSMP \| ADC_FLAG_RDY ) );
<>	144:ef7eb2e8f9f7	611
<>	144:ef7eb2e8f9f7	612	/* Reset register CR */
<>	144:ef7eb2e8f9f7	613	/* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,
<>	144:ef7eb2e8f9f7	614	ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set":
<>	144:ef7eb2e8f9f7	615	no direct reset applicable.
<>	144:ef7eb2e8f9f7	616	Update CR register to reset value where doable by software */
<>	144:ef7eb2e8f9f7	617	CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN \| ADC_CR_ADCALDIF);
<>	144:ef7eb2e8f9f7	618	SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
<>	144:ef7eb2e8f9f7	619
<>	144:ef7eb2e8f9f7	620	/* Reset register CFGR */
<>	144:ef7eb2e8f9f7	621	CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_FIELDS);
<>	144:ef7eb2e8f9f7	622	SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
<>	144:ef7eb2e8f9f7	623
<>	144:ef7eb2e8f9f7	624	/* Reset register CFGR2 */
<>	144:ef7eb2e8f9f7	625	CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM \| ADC_CFGR2_TROVS \| ADC_CFGR2_OVSS \|
<>	144:ef7eb2e8f9f7	626	ADC_CFGR2_OVSR \| ADC_CFGR2_JOVSE \| ADC_CFGR2_ROVSE );
<>	144:ef7eb2e8f9f7	627
<>	144:ef7eb2e8f9f7	628	/* Reset register SMPR1 */
<>	144:ef7eb2e8f9f7	629	CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS);
<>	144:ef7eb2e8f9f7	630
<>	144:ef7eb2e8f9f7	631	/* Reset register SMPR2 */
<>	144:ef7eb2e8f9f7	632	CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 \| ADC_SMPR2_SMP17 \| ADC_SMPR2_SMP16 \|
<>	144:ef7eb2e8f9f7	633	ADC_SMPR2_SMP15 \| ADC_SMPR2_SMP14 \| ADC_SMPR2_SMP13 \|
<>	144:ef7eb2e8f9f7	634	ADC_SMPR2_SMP12 \| ADC_SMPR2_SMP11 \| ADC_SMPR2_SMP10 );
<>	144:ef7eb2e8f9f7	635
<>	144:ef7eb2e8f9f7	636	/* Reset register TR1 */
<>	144:ef7eb2e8f9f7	637	CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 \| ADC_TR1_LT1);
<>	144:ef7eb2e8f9f7	638
<>	144:ef7eb2e8f9f7	639	/* Reset register TR2 */
<>	144:ef7eb2e8f9f7	640	CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 \| ADC_TR2_LT2);
<>	144:ef7eb2e8f9f7	641
<>	144:ef7eb2e8f9f7	642	/* Reset register TR3 */
<>	144:ef7eb2e8f9f7	643	CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 \| ADC_TR3_LT3);
<>	144:ef7eb2e8f9f7	644
<>	144:ef7eb2e8f9f7	645	/* Reset register SQR1 */
<>	144:ef7eb2e8f9f7	646	CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 \| ADC_SQR1_SQ3 \| ADC_SQR1_SQ2 \|
<>	144:ef7eb2e8f9f7	647	ADC_SQR1_SQ1 \| ADC_SQR1_L);
<>	144:ef7eb2e8f9f7	648
<>	144:ef7eb2e8f9f7	649	/* Reset register SQR2 */
<>	144:ef7eb2e8f9f7	650	CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 \| ADC_SQR2_SQ8 \| ADC_SQR2_SQ7 \|
<>	144:ef7eb2e8f9f7	651	ADC_SQR2_SQ6 \| ADC_SQR2_SQ5);
<>	144:ef7eb2e8f9f7	652
<>	144:ef7eb2e8f9f7	653	/* Reset register SQR3 */
<>	144:ef7eb2e8f9f7	654	CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 \| ADC_SQR3_SQ13 \| ADC_SQR3_SQ12 \|
<>	144:ef7eb2e8f9f7	655	ADC_SQR3_SQ11 \| ADC_SQR3_SQ10);
<>	144:ef7eb2e8f9f7	656
<>	144:ef7eb2e8f9f7	657	/* Reset register SQR4 */
<>	144:ef7eb2e8f9f7	658	CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 \| ADC_SQR4_SQ15);
<>	144:ef7eb2e8f9f7	659
<>	144:ef7eb2e8f9f7	660	/* Register JSQR was reset when the ADC was disabled */
<>	144:ef7eb2e8f9f7	661
<>	144:ef7eb2e8f9f7	662	/* Reset register DR */
<>	144:ef7eb2e8f9f7	663	/* bits in access mode read only, no direct reset applicable*/
<>	144:ef7eb2e8f9f7	664
<>	144:ef7eb2e8f9f7	665	/* Reset register OFR1 */
<>	144:ef7eb2e8f9f7	666	CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN \| ADC_OFR1_OFFSET1_CH \| ADC_OFR1_OFFSET1);
<>	144:ef7eb2e8f9f7	667	/* Reset register OFR2 */
<>	144:ef7eb2e8f9f7	668	CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN \| ADC_OFR2_OFFSET2_CH \| ADC_OFR2_OFFSET2);
<>	144:ef7eb2e8f9f7	669	/* Reset register OFR3 */
<>	144:ef7eb2e8f9f7	670	CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN \| ADC_OFR3_OFFSET3_CH \| ADC_OFR3_OFFSET3);
<>	144:ef7eb2e8f9f7	671	/* Reset register OFR4 */
<>	144:ef7eb2e8f9f7	672	CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN \| ADC_OFR4_OFFSET4_CH \| ADC_OFR4_OFFSET4);
<>	144:ef7eb2e8f9f7	673
<>	144:ef7eb2e8f9f7	674	/* Reset registers JDR1, JDR2, JDR3, JDR4 */
<>	144:ef7eb2e8f9f7	675	/* bits in access mode read only, no direct reset applicable*/
<>	144:ef7eb2e8f9f7	676
<>	144:ef7eb2e8f9f7	677	/* Reset register AWD2CR */
<>	144:ef7eb2e8f9f7	678	CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
<>	144:ef7eb2e8f9f7	679
<>	144:ef7eb2e8f9f7	680	/* Reset register AWD3CR */
<>	144:ef7eb2e8f9f7	681	CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
<>	144:ef7eb2e8f9f7	682
<>	144:ef7eb2e8f9f7	683	/* Reset register DIFSEL */
<>	144:ef7eb2e8f9f7	684	CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
<>	144:ef7eb2e8f9f7	685
<>	144:ef7eb2e8f9f7	686	/* Reset register CALFACT */
<>	144:ef7eb2e8f9f7	687	CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D \| ADC_CALFACT_CALFACT_S);
<>	144:ef7eb2e8f9f7	688
<>	144:ef7eb2e8f9f7	689
<>	144:ef7eb2e8f9f7	690
<>	144:ef7eb2e8f9f7	691
<>	144:ef7eb2e8f9f7	692
<>	144:ef7eb2e8f9f7	693
<>	144:ef7eb2e8f9f7	694	/* ========== Reset common ADC registers ========== */
<>	144:ef7eb2e8f9f7	695
<>	144:ef7eb2e8f9f7	696	/* Software is allowed to change common parameters only when all the other
<>	144:ef7eb2e8f9f7	697	ADCs are disabled. */
<>	144:ef7eb2e8f9f7	698	if ((ADC_IS_ENABLE(hadc) == RESET) &&
<>	144:ef7eb2e8f9f7	699	(ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
<>	144:ef7eb2e8f9f7	700	{
<>	144:ef7eb2e8f9f7	701	/* Reset configuration of ADC common register CCR:
<>	144:ef7eb2e8f9f7	702	- clock mode: CKMODE, PRESCEN
<>	144:ef7eb2e8f9f7	703	- multimode related parameters (when this feature is available): MDMA,
<>	144:ef7eb2e8f9f7	704	DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API)
<>	144:ef7eb2e8f9f7	705	- internal measurement paths: Vbat, temperature sensor, Vref (set into
<>	144:ef7eb2e8f9f7	706	HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
<>	144:ef7eb2e8f9f7	707	*/
<>	144:ef7eb2e8f9f7	708	ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
<>	144:ef7eb2e8f9f7	709	}
<>	144:ef7eb2e8f9f7	710
<>	144:ef7eb2e8f9f7	711	/* DeInit the low level hardware.
<>	144:ef7eb2e8f9f7	712
<>	144:ef7eb2e8f9f7	713	For example:
<>	144:ef7eb2e8f9f7	714	__HAL_RCC_ADC_FORCE_RESET();
<>	144:ef7eb2e8f9f7	715	__HAL_RCC_ADC_RELEASE_RESET();
<>	144:ef7eb2e8f9f7	716	__HAL_RCC_ADC_CLK_DISABLE();
<>	144:ef7eb2e8f9f7	717
<>	144:ef7eb2e8f9f7	718	Keep in mind that all ADCs use the same clock: disabling
<>	144:ef7eb2e8f9f7	719	the clock will reset all ADCs.
<>	144:ef7eb2e8f9f7	720
<>	144:ef7eb2e8f9f7	721	*/
<>	144:ef7eb2e8f9f7	722	HAL_ADC_MspDeInit(hadc);
<>	144:ef7eb2e8f9f7	723
<>	144:ef7eb2e8f9f7	724	/* Set ADC error code to none */
<>	144:ef7eb2e8f9f7	725	ADC_CLEAR_ERRORCODE(hadc);
<>	144:ef7eb2e8f9f7	726
<>	144:ef7eb2e8f9f7	727	/* Reset injected channel configuration parameters */
<>	144:ef7eb2e8f9f7	728	hadc->InjectionConfig.ContextQueue = 0;
<>	144:ef7eb2e8f9f7	729	hadc->InjectionConfig.ChannelCount = 0;
<>	144:ef7eb2e8f9f7	730
<>	144:ef7eb2e8f9f7	731	/* Change ADC state */
<>	144:ef7eb2e8f9f7	732	hadc->State = HAL_ADC_STATE_RESET;
<>	144:ef7eb2e8f9f7	733
<>	144:ef7eb2e8f9f7	734	/* Process unlocked */
<>	144:ef7eb2e8f9f7	735	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	736
<>	144:ef7eb2e8f9f7	737
<>	144:ef7eb2e8f9f7	738	/* Return function status */
<>	144:ef7eb2e8f9f7	739	return HAL_OK;
<>	144:ef7eb2e8f9f7	740
<>	144:ef7eb2e8f9f7	741	}
<>	144:ef7eb2e8f9f7	742
<>	144:ef7eb2e8f9f7	743	/**
<>	144:ef7eb2e8f9f7	744	* @brief Initialize the ADC MSP.
<>	144:ef7eb2e8f9f7	745	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	746	* @retval None
<>	144:ef7eb2e8f9f7	747	*/
<>	144:ef7eb2e8f9f7	748	__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	749	{
<>	144:ef7eb2e8f9f7	750	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	751	UNUSED(hadc);
<>	144:ef7eb2e8f9f7	752
<>	144:ef7eb2e8f9f7	753	/* NOTE : This function should not be modified. When the callback is needed,
<>	144:ef7eb2e8f9f7	754	function HAL_ADC_MspInit must be implemented in the user file.
<>	144:ef7eb2e8f9f7	755	*/
<>	144:ef7eb2e8f9f7	756	}
<>	144:ef7eb2e8f9f7	757
<>	144:ef7eb2e8f9f7	758	/**
<>	144:ef7eb2e8f9f7	759	* @brief DeInitialize the ADC MSP.
<>	144:ef7eb2e8f9f7	760	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	761	* @note All ADCs use the same clock: disabling the clock will reset all ADCs.
<>	144:ef7eb2e8f9f7	762	* @retval None
<>	144:ef7eb2e8f9f7	763	*/
<>	144:ef7eb2e8f9f7	764	__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	765	{
<>	144:ef7eb2e8f9f7	766	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	767	UNUSED(hadc);
<>	144:ef7eb2e8f9f7	768
<>	144:ef7eb2e8f9f7	769	/* NOTE : This function should not be modified. When the callback is needed,
<>	144:ef7eb2e8f9f7	770	function HAL_ADC_MspDeInit must be implemented in the user file.
<>	144:ef7eb2e8f9f7	771	*/
<>	144:ef7eb2e8f9f7	772	}
<>	144:ef7eb2e8f9f7	773
<>	144:ef7eb2e8f9f7	774	/**
<>	144:ef7eb2e8f9f7	775	* @}
<>	144:ef7eb2e8f9f7	776	*/
<>	144:ef7eb2e8f9f7	777
<>	144:ef7eb2e8f9f7	778	/** @defgroup ADC_Exported_Functions_Group2 Input and Output operation functions
<>	144:ef7eb2e8f9f7	779	* @brief IO operation functions
<>	144:ef7eb2e8f9f7	780	*
<>	144:ef7eb2e8f9f7	781	@verbatim
<>	144:ef7eb2e8f9f7	782	===============================================================================
<>	144:ef7eb2e8f9f7	783	##### IO operation functions #####
<>	144:ef7eb2e8f9f7	784	===============================================================================
<>	144:ef7eb2e8f9f7	785	[..] This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	786	(+) Start conversion of regular group.
<>	144:ef7eb2e8f9f7	787	(+) Stop conversion of regular group.
<>	144:ef7eb2e8f9f7	788	(+) Poll for conversion complete on regular group.
<>	144:ef7eb2e8f9f7	789	(+) Poll for conversion event.
<>	144:ef7eb2e8f9f7	790	(+) Get result of regular channel conversion.
<>	144:ef7eb2e8f9f7	791	(+) Start conversion of regular group and enable interruptions.
<>	144:ef7eb2e8f9f7	792	(+) Stop conversion of regular group and disable interruptions.
<>	144:ef7eb2e8f9f7	793	(+) Handle ADC interrupt request
<>	144:ef7eb2e8f9f7	794	(+) Start conversion of regular group and enable DMA transfer.
<>	144:ef7eb2e8f9f7	795	(+) Stop conversion of regular group and disable ADC DMA transfer.
<>	144:ef7eb2e8f9f7	796
<>	144:ef7eb2e8f9f7	797	@endverbatim
<>	144:ef7eb2e8f9f7	798	* @{
<>	144:ef7eb2e8f9f7	799	*/
<>	144:ef7eb2e8f9f7	800
<>	144:ef7eb2e8f9f7	801	/**
<>	144:ef7eb2e8f9f7	802	* @brief Enable ADC, start conversion of regular group.
<>	144:ef7eb2e8f9f7	803	* @note Interruptions enabled in this function: None.
<>	144:ef7eb2e8f9f7	804	* @note Case of multimode enabled (when multimode feature is available):
<>	144:ef7eb2e8f9f7	805	* if ADC is Slave, ADC is enabled but conversion is not started,
<>	144:ef7eb2e8f9f7	806	* if ADC is master, ADC is enabled and multimode conversion is started.
<>	144:ef7eb2e8f9f7	807	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	808	* @retval HAL status
<>	144:ef7eb2e8f9f7	809	*/
<>	144:ef7eb2e8f9f7	810	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	811	{
<>	144:ef7eb2e8f9f7	812	ADC_TypeDef *tmpADC_Master;
<>	144:ef7eb2e8f9f7	813	HAL_StatusTypeDef tmp_status = HAL_OK;
<>	144:ef7eb2e8f9f7	814
<>	144:ef7eb2e8f9f7	815	/* Check the parameters */
<>	144:ef7eb2e8f9f7	816	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	817
<>	144:ef7eb2e8f9f7	818
<>	144:ef7eb2e8f9f7	819	/* if a regular conversion is already on-going (i.e. ADSTART is set),
<>	144:ef7eb2e8f9f7	820	don't restart the conversion. */
<>	144:ef7eb2e8f9f7	821	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
<>	144:ef7eb2e8f9f7	822	{
<>	144:ef7eb2e8f9f7	823	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	824	}
<>	144:ef7eb2e8f9f7	825	else
<>	144:ef7eb2e8f9f7	826	{
<>	144:ef7eb2e8f9f7	827	/* Process locked */
<>	144:ef7eb2e8f9f7	828	__HAL_LOCK(hadc);
<>	144:ef7eb2e8f9f7	829
<>	144:ef7eb2e8f9f7	830	/* Enable the ADC peripheral */
<>	144:ef7eb2e8f9f7	831	tmp_status = ADC_Enable(hadc);
<>	144:ef7eb2e8f9f7	832
<>	144:ef7eb2e8f9f7	833	/* Start conversion if ADC is effectively enabled */
<>	144:ef7eb2e8f9f7	834	if (tmp_status == HAL_OK)
<>	144:ef7eb2e8f9f7	835	{
<>	144:ef7eb2e8f9f7	836	/* State machine update: Check if an injected conversion is ongoing */
<>	144:ef7eb2e8f9f7	837	if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<>	144:ef7eb2e8f9f7	838	{
<>	144:ef7eb2e8f9f7	839	/* Reset ADC error code fields related to regular conversions only */
<>	144:ef7eb2e8f9f7	840	CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR\|HAL_ADC_ERROR_DMA));
<>	144:ef7eb2e8f9f7	841	}
<>	144:ef7eb2e8f9f7	842	else
<>	144:ef7eb2e8f9f7	843	{
<>	144:ef7eb2e8f9f7	844	/* Set ADC error code to none */
<>	144:ef7eb2e8f9f7	845	ADC_CLEAR_ERRORCODE(hadc);
<>	144:ef7eb2e8f9f7	846	}
<>	144:ef7eb2e8f9f7	847	/* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
<>	144:ef7eb2e8f9f7	848	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY\|HAL_ADC_STATE_REG_EOC\|HAL_ADC_STATE_REG_OVR\|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
<>	144:ef7eb2e8f9f7	849
<>	144:ef7eb2e8f9f7	850	/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
<>	144:ef7eb2e8f9f7	851	- by default if ADC is Master or Independent or if multimode feature is not available
<>	144:ef7eb2e8f9f7	852	- if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
<>	144:ef7eb2e8f9f7	853	if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
<>	144:ef7eb2e8f9f7	854	{
<>	144:ef7eb2e8f9f7	855	CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<>	144:ef7eb2e8f9f7	856	}
<>	144:ef7eb2e8f9f7	857
<>	144:ef7eb2e8f9f7	858	/* Clear regular group conversion flag and overrun flag */
<>	144:ef7eb2e8f9f7	859	/* (To ensure of no unknown state from potential previous ADC operations) */
<>	144:ef7eb2e8f9f7	860	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC \| ADC_FLAG_EOS \| ADC_FLAG_OVR));
<>	144:ef7eb2e8f9f7	861
<>	144:ef7eb2e8f9f7	862	/* Enable conversion of regular group. */
<>	144:ef7eb2e8f9f7	863	/* If software start has been selected, conversion starts immediately. */
<>	144:ef7eb2e8f9f7	864	/* If external trigger has been selected, conversion starts at next */
<>	144:ef7eb2e8f9f7	865	/* trigger event. */
<>	144:ef7eb2e8f9f7	866	/* Case of multimode enabled (when multimode feature is available): */
<>	144:ef7eb2e8f9f7	867	/* - if ADC is slave and dual regular conversions are enabled, ADC is */
<>	144:ef7eb2e8f9f7	868	/* enabled only (conversion is not started), */
<>	144:ef7eb2e8f9f7	869	/* - if ADC is master, ADC is enabled and conversion is started. */
<>	144:ef7eb2e8f9f7	870	if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
<>	144:ef7eb2e8f9f7	871	{
<>	144:ef7eb2e8f9f7	872	/* Multimode feature is not available or ADC Instance is Independent or Master,
<>	144:ef7eb2e8f9f7	873	or is not Slave ADC with dual regular conversions enabled.
<>	144:ef7eb2e8f9f7	874	Then, set HAL_ADC_STATE_INJ_BUSY bit and reset HAL_ADC_STATE_INJ_EOC bit if JAUTO is set. */
<>	144:ef7eb2e8f9f7	875	if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
<>	144:ef7eb2e8f9f7	876	{
<>	144:ef7eb2e8f9f7	877	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<>	144:ef7eb2e8f9f7	878	}
<>	144:ef7eb2e8f9f7	879	/* Process unlocked */
<>	144:ef7eb2e8f9f7	880	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	881	/* Start ADC */
<>	144:ef7eb2e8f9f7	882	SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
<>	144:ef7eb2e8f9f7	883	}
<>	144:ef7eb2e8f9f7	884	else
<>	144:ef7eb2e8f9f7	885	{
<>	144:ef7eb2e8f9f7	886	SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<>	144:ef7eb2e8f9f7	887	/* if Master ADC JAUTO bit is set, update Slave State in setting
<>	144:ef7eb2e8f9f7	888	HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
<>	144:ef7eb2e8f9f7	889	tmpADC_Master = ADC_MASTER_REGISTER(hadc);
<>	144:ef7eb2e8f9f7	890	if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET)
<>	144:ef7eb2e8f9f7	891	{
<>	144:ef7eb2e8f9f7	892	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<>	144:ef7eb2e8f9f7	893
<>	144:ef7eb2e8f9f7	894	} /* if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) */
<>	144:ef7eb2e8f9f7	895	/* Process unlocked */
<>	144:ef7eb2e8f9f7	896	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	897	} /* if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) */
<>	144:ef7eb2e8f9f7	898	}
<>	144:ef7eb2e8f9f7	899	else
<>	144:ef7eb2e8f9f7	900	{
<>	144:ef7eb2e8f9f7	901	/* Process unlocked */
<>	144:ef7eb2e8f9f7	902	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	903	}
<>	144:ef7eb2e8f9f7	904
<>	144:ef7eb2e8f9f7	905	/* Return function status */
<>	144:ef7eb2e8f9f7	906	return tmp_status;
<>	144:ef7eb2e8f9f7	907	}
<>	144:ef7eb2e8f9f7	908	}
<>	144:ef7eb2e8f9f7	909
<>	144:ef7eb2e8f9f7	910	/**
<>	144:ef7eb2e8f9f7	911	* @brief Stop ADC conversion of regular and injected groups, disable ADC peripheral.
<>	144:ef7eb2e8f9f7	912	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	913	* @retval HAL status.
<>	144:ef7eb2e8f9f7	914	*/
<>	144:ef7eb2e8f9f7	915	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	916	{
<>	144:ef7eb2e8f9f7	917	HAL_StatusTypeDef tmp_status = HAL_OK;
<>	144:ef7eb2e8f9f7	918
<>	144:ef7eb2e8f9f7	919	/* Check the parameters */
<>	144:ef7eb2e8f9f7	920	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	921
<>	144:ef7eb2e8f9f7	922	/* Process locked */
<>	144:ef7eb2e8f9f7	923	__HAL_LOCK(hadc);
<>	144:ef7eb2e8f9f7	924
<>	144:ef7eb2e8f9f7	925	/* 1. Stop potential regular and injected on-going conversions */
<>	144:ef7eb2e8f9f7	926	tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
<>	144:ef7eb2e8f9f7	927
<>	144:ef7eb2e8f9f7	928	/* Disable ADC peripheral if conversions are effectively stopped */
<>	144:ef7eb2e8f9f7	929	if (tmp_status == HAL_OK)
<>	144:ef7eb2e8f9f7	930	{
<>	144:ef7eb2e8f9f7	931	/* 2. Disable the ADC peripheral */
<>	144:ef7eb2e8f9f7	932	tmp_status = ADC_Disable(hadc);
<>	144:ef7eb2e8f9f7	933
<>	144:ef7eb2e8f9f7	934	/* Check if ADC is effectively disabled */
<>	144:ef7eb2e8f9f7	935	if (tmp_status == HAL_OK)
<>	144:ef7eb2e8f9f7	936	{
<>	144:ef7eb2e8f9f7	937	/* Change ADC state */
<>	144:ef7eb2e8f9f7	938	/* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
<>	144:ef7eb2e8f9f7	939	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY\|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
<>	144:ef7eb2e8f9f7	940	}
<>	144:ef7eb2e8f9f7	941	}
<>	144:ef7eb2e8f9f7	942
<>	144:ef7eb2e8f9f7	943	/* Process unlocked */
<>	144:ef7eb2e8f9f7	944	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	945
<>	144:ef7eb2e8f9f7	946	/* Return function status */
<>	144:ef7eb2e8f9f7	947	return tmp_status;
<>	144:ef7eb2e8f9f7	948	}
<>	144:ef7eb2e8f9f7	949
<>	144:ef7eb2e8f9f7	950
<>	144:ef7eb2e8f9f7	951
<>	144:ef7eb2e8f9f7	952	/**
<>	144:ef7eb2e8f9f7	953	* @brief Wait for regular group conversion to be completed.
<>	144:ef7eb2e8f9f7	954	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	955	* @param Timeout: Timeout value in millisecond.
<>	144:ef7eb2e8f9f7	956	* @note Depending on hadc->Init.EOCSelection, EOS or EOC is
<>	144:ef7eb2e8f9f7	957	* checked and cleared depending on AUTDLY bit status.
<>	144:ef7eb2e8f9f7	958	* @note HAL_ADC_PollForConversion() returns HAL_ERROR if EOC is polled in a
<>	144:ef7eb2e8f9f7	959	* DMA-managed conversions configuration: indeed, EOC is immediately
<>	144:ef7eb2e8f9f7	960	* reset by the DMA reading the DR register when the converted data is
<>	144:ef7eb2e8f9f7	961	* available. Therefore, EOC is set for a too short period to be
<>	144:ef7eb2e8f9f7	962	* reliably polled.
<>	144:ef7eb2e8f9f7	963	* @retval HAL status
<>	144:ef7eb2e8f9f7	964	*/
<>	144:ef7eb2e8f9f7	965	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	966	{
<>	144:ef7eb2e8f9f7	967	uint32_t tickstart;
<>	144:ef7eb2e8f9f7	968	uint32_t tmp_Flag_End = 0x00;
<>	144:ef7eb2e8f9f7	969	ADC_TypeDef *tmpADC_Master;
<>	144:ef7eb2e8f9f7	970	uint32_t tmp_cfgr = 0x00;
<>	144:ef7eb2e8f9f7	971	uint32_t tmp_eos_raised = 0x01; /* by default, assume that EOS is set,
<>	144:ef7eb2e8f9f7	972	tmp_eos_raised will be corrected
<>	144:ef7eb2e8f9f7	973	accordingly during API execution */
<>	144:ef7eb2e8f9f7	974
<>	144:ef7eb2e8f9f7	975	/* Check the parameters */
<>	144:ef7eb2e8f9f7	976	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	977
<>	144:ef7eb2e8f9f7	978	/* If end of sequence selected */
<>	144:ef7eb2e8f9f7	979	if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
<>	144:ef7eb2e8f9f7	980	{
<>	144:ef7eb2e8f9f7	981	tmp_Flag_End = ADC_FLAG_EOS;
<>	144:ef7eb2e8f9f7	982	}
<>	144:ef7eb2e8f9f7	983	else /* end of conversion selected */
<>	144:ef7eb2e8f9f7	984	{
<>	144:ef7eb2e8f9f7	985	/* Check that the ADC is not in a DMA-based configuration. Otherwise,
<>	144:ef7eb2e8f9f7	986	returns an error. */
<>	144:ef7eb2e8f9f7	987
<>	144:ef7eb2e8f9f7	988	/* Check whether dual regular conversions are disabled or unavailable. */
<>	144:ef7eb2e8f9f7	989	if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET)
<>	144:ef7eb2e8f9f7	990	{
<>	144:ef7eb2e8f9f7	991	/* Check DMAEN bit in handle ADC CFGR register */
<>	144:ef7eb2e8f9f7	992	if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != RESET)
<>	144:ef7eb2e8f9f7	993	{
<>	144:ef7eb2e8f9f7	994	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<>	144:ef7eb2e8f9f7	995	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	996	}
<>	144:ef7eb2e8f9f7	997	}
<>	144:ef7eb2e8f9f7	998	else
<>	144:ef7eb2e8f9f7	999	{
<>	144:ef7eb2e8f9f7	1000	/* Else need to check Common register CCR MDMA bit field. */
<>	144:ef7eb2e8f9f7	1001	if (ADC_MULTIMODE_DMA_ENABLED())
<>	144:ef7eb2e8f9f7	1002	{
<>	144:ef7eb2e8f9f7	1003	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<>	144:ef7eb2e8f9f7	1004	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1005	}
<>	144:ef7eb2e8f9f7	1006	}
<>	144:ef7eb2e8f9f7	1007
<>	144:ef7eb2e8f9f7	1008	/* no DMA transfer detected, polling ADC_FLAG_EOC is possible */
<>	144:ef7eb2e8f9f7	1009	tmp_Flag_End = ADC_FLAG_EOC;
<>	144:ef7eb2e8f9f7	1010	}
<>	144:ef7eb2e8f9f7	1011
<>	144:ef7eb2e8f9f7	1012	/* Get timeout */
<>	144:ef7eb2e8f9f7	1013	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1014
<>	144:ef7eb2e8f9f7	1015	/* Wait until End of Conversion or Sequence flag is raised */
<>	144:ef7eb2e8f9f7	1016	while (HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_End))
<>	144:ef7eb2e8f9f7	1017	{
<>	144:ef7eb2e8f9f7	1018	/* Check if timeout is disabled (set to infinite wait) */
<>	144:ef7eb2e8f9f7	1019	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	1020	{
<>	144:ef7eb2e8f9f7	1021	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	1022	{
<>	144:ef7eb2e8f9f7	1023	SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
<>	144:ef7eb2e8f9f7	1024	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1025	}
<>	144:ef7eb2e8f9f7	1026	}
<>	144:ef7eb2e8f9f7	1027	}
<>	144:ef7eb2e8f9f7	1028
<>	144:ef7eb2e8f9f7	1029	/* Next, to clear the polled flag as well as to update the handle State,
<>	144:ef7eb2e8f9f7	1030	EOS is checked and the relevant configuration register is retrieved. */
<>	144:ef7eb2e8f9f7	1031	/* 1. Check whether or not EOS is set */
<>	144:ef7eb2e8f9f7	1032	if (HAL_IS_BIT_CLR(hadc->Instance->ISR, ADC_FLAG_EOS))
<>	144:ef7eb2e8f9f7	1033	{
<>	144:ef7eb2e8f9f7	1034	tmp_eos_raised = 0;
<>	144:ef7eb2e8f9f7	1035	}
<>	144:ef7eb2e8f9f7	1036	/* 2. Check whether or not hadc is the handle of a Slave ADC with dual
<>	144:ef7eb2e8f9f7	1037	regular conversions enabled. */
<>	144:ef7eb2e8f9f7	1038	if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
<>	144:ef7eb2e8f9f7	1039	{
<>	144:ef7eb2e8f9f7	1040	/* Retrieve handle ADC CFGR register */
<>	144:ef7eb2e8f9f7	1041	tmp_cfgr = READ_REG(hadc->Instance->CFGR);
<>	144:ef7eb2e8f9f7	1042	}
<>	144:ef7eb2e8f9f7	1043	else
<>	144:ef7eb2e8f9f7	1044	{
<>	144:ef7eb2e8f9f7	1045	/* Retrieve Master ADC CFGR register */
<>	144:ef7eb2e8f9f7	1046	tmpADC_Master = ADC_MASTER_REGISTER(hadc);
<>	144:ef7eb2e8f9f7	1047	tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
<>	144:ef7eb2e8f9f7	1048	}
<>	144:ef7eb2e8f9f7	1049
<>	144:ef7eb2e8f9f7	1050	/* Clear polled flag */
<>	144:ef7eb2e8f9f7	1051	if (tmp_Flag_End == ADC_FLAG_EOS)
<>	144:ef7eb2e8f9f7	1052	{
<>	144:ef7eb2e8f9f7	1053	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
<>	144:ef7eb2e8f9f7	1054	}
<>	144:ef7eb2e8f9f7	1055	else
<>	144:ef7eb2e8f9f7	1056	{
<>	144:ef7eb2e8f9f7	1057
<>	144:ef7eb2e8f9f7	1058	/* Clear end of conversion EOC flag of regular group if low power feature */
<>	144:ef7eb2e8f9f7	1059	/* "LowPowerAutoWait " is disabled, to not interfere with this feature */
<>	144:ef7eb2e8f9f7	1060	/* until data register is read using function HAL_ADC_GetValue(). */
<>	144:ef7eb2e8f9f7	1061	/* For regular groups, no new conversion will start before EOC is cleared.*/
<>	144:ef7eb2e8f9f7	1062	/* Note that 1. reading DR clears EOC. */
<>	144:ef7eb2e8f9f7	1063	/* 2. in multimode with dual regular conversions enabled (when */
<>	144:ef7eb2e8f9f7	1064	/* multimode feature is available), Master AUTDLY bit is */
<>	144:ef7eb2e8f9f7	1065	/* checked. */
<>	144:ef7eb2e8f9f7	1066	if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET)
<>	144:ef7eb2e8f9f7	1067	{
<>	144:ef7eb2e8f9f7	1068	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
<>	144:ef7eb2e8f9f7	1069	}
<>	144:ef7eb2e8f9f7	1070	}
<>	144:ef7eb2e8f9f7	1071
<>	144:ef7eb2e8f9f7	1072
<>	144:ef7eb2e8f9f7	1073	/* Update ADC state machine */
<>	144:ef7eb2e8f9f7	1074	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
<>	144:ef7eb2e8f9f7	1075	/* If 1. EOS is set
<>	144:ef7eb2e8f9f7	1076	2. conversions are software-triggered
<>	144:ef7eb2e8f9f7	1077	3. CONT bit is reset (that of handle ADC or Master ADC if applicable)
<>	144:ef7eb2e8f9f7	1078	Then regular conversions are over and HAL_ADC_STATE_REG_BUSY can be reset.
<>	144:ef7eb2e8f9f7	1079	4. additionally, if no injected conversions are on-going, HAL_ADC_STATE_READY
<>	144:ef7eb2e8f9f7	1080	can be set */
<>	144:ef7eb2e8f9f7	1081	if ((tmp_eos_raised)
<>	144:ef7eb2e8f9f7	1082	&& (ADC_IS_SOFTWARE_START_REGULAR(hadc))
<>	144:ef7eb2e8f9f7	1083	&& (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET))
<>	144:ef7eb2e8f9f7	1084	{
<>	144:ef7eb2e8f9f7	1085	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<>	144:ef7eb2e8f9f7	1086	/* If no injected conversion on-going, set HAL_ADC_STATE_READY bit */
<>	144:ef7eb2e8f9f7	1087	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<>	144:ef7eb2e8f9f7	1088	{
<>	144:ef7eb2e8f9f7	1089	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<>	144:ef7eb2e8f9f7	1090	}
<>	144:ef7eb2e8f9f7	1091	}
<>	144:ef7eb2e8f9f7	1092
<>	144:ef7eb2e8f9f7	1093
<>	144:ef7eb2e8f9f7	1094	/* Return API HAL status */
<>	144:ef7eb2e8f9f7	1095	return HAL_OK;
<>	144:ef7eb2e8f9f7	1096	}
<>	144:ef7eb2e8f9f7	1097
<>	144:ef7eb2e8f9f7	1098	/**
<>	144:ef7eb2e8f9f7	1099	* @brief Poll for ADC event.
<>	144:ef7eb2e8f9f7	1100	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1101	* @param EventType: the ADC event type.
<>	144:ef7eb2e8f9f7	1102	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1103	* @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event
<>	144:ef7eb2e8f9f7	1104	* @arg @ref ADC_AWD_EVENT ADC Analog watchdog 1 event
<>	144:ef7eb2e8f9f7	1105	* @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event
<>	144:ef7eb2e8f9f7	1106	* @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event
<>	144:ef7eb2e8f9f7	1107	* @arg @ref ADC_OVR_EVENT ADC Overrun event
<>	144:ef7eb2e8f9f7	1108	* @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event
<>	144:ef7eb2e8f9f7	1109	* @param Timeout: Timeout value in millisecond.
<>	144:ef7eb2e8f9f7	1110	* @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
<>	144:ef7eb2e8f9f7	1111	* Indeed, the latter is reset only if hadc->Init.Overrun field is set
<>	144:ef7eb2e8f9f7	1112	* to ADC_OVR_DATA_OVERWRITTEN. Otherwise, DR may be potentially overwritten
<>	144:ef7eb2e8f9f7	1113	* by a new converted data as soon as OVR is cleared.
<>	144:ef7eb2e8f9f7	1114	* To reset OVR flag once the preserved data is retrieved, the user can resort
<>	144:ef7eb2e8f9f7	1115	* to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
<>	144:ef7eb2e8f9f7	1116	* @retval HAL status
<>	144:ef7eb2e8f9f7	1117	*/
<>	144:ef7eb2e8f9f7	1118	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	1119	{
<>	144:ef7eb2e8f9f7	1120	uint32_t tickstart;
<>	144:ef7eb2e8f9f7	1121
<>	144:ef7eb2e8f9f7	1122	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1123	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	1124	assert_param(IS_ADC_EVENT_TYPE(EventType));
<>	144:ef7eb2e8f9f7	1125
<>	144:ef7eb2e8f9f7	1126	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1127
<>	144:ef7eb2e8f9f7	1128	/* Check selected event flag */
<>	144:ef7eb2e8f9f7	1129	while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
<>	144:ef7eb2e8f9f7	1130	{
<>	144:ef7eb2e8f9f7	1131	/* Check if timeout is disabled (set to infinite wait) */
<>	144:ef7eb2e8f9f7	1132	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	1133	{
<>	144:ef7eb2e8f9f7	1134	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	1135	{
<>	144:ef7eb2e8f9f7	1136	/* Update ADC state machine to timeout */
<>	144:ef7eb2e8f9f7	1137	SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
<>	144:ef7eb2e8f9f7	1138
<>	144:ef7eb2e8f9f7	1139	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1140	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	1141
<>	144:ef7eb2e8f9f7	1142	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1143	}
<>	144:ef7eb2e8f9f7	1144	}
<>	144:ef7eb2e8f9f7	1145	}
<>	144:ef7eb2e8f9f7	1146
<>	144:ef7eb2e8f9f7	1147
<>	144:ef7eb2e8f9f7	1148	switch(EventType)
<>	144:ef7eb2e8f9f7	1149	{
<>	144:ef7eb2e8f9f7	1150	/* End Of Sampling event */
<>	144:ef7eb2e8f9f7	1151	case ADC_EOSMP_EVENT:
<>	144:ef7eb2e8f9f7	1152	/* Change ADC state */
<>	144:ef7eb2e8f9f7	1153	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
<>	144:ef7eb2e8f9f7	1154
<>	144:ef7eb2e8f9f7	1155	/* Clear the End Of Sampling flag */
<>	144:ef7eb2e8f9f7	1156	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
<>	144:ef7eb2e8f9f7	1157
<>	144:ef7eb2e8f9f7	1158	break;
<>	144:ef7eb2e8f9f7	1159
<>	144:ef7eb2e8f9f7	1160	/* Analog watchdog (level out of window) event */
<>	144:ef7eb2e8f9f7	1161	/* Note: In case of several analog watchdog enabled, if needed to know */
<>	144:ef7eb2e8f9f7	1162	/* which one triggered and on which ADCx, test ADC state of Analog Watchdog */
<>	144:ef7eb2e8f9f7	1163	/* flags HAL_ADC_STATE_AWD/2/3 function. */
<>	144:ef7eb2e8f9f7	1164	/* For example: "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD) " */
<>	144:ef7eb2e8f9f7	1165	/* "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD2)" */
<>	144:ef7eb2e8f9f7	1166	/* "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD3)" */
<>	144:ef7eb2e8f9f7	1167	case ADC_AWD_EVENT:
<>	144:ef7eb2e8f9f7	1168	/* Change ADC state */
<>	144:ef7eb2e8f9f7	1169	SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
<>	144:ef7eb2e8f9f7	1170
<>	144:ef7eb2e8f9f7	1171	/* Clear ADC analog watchdog flag */
<>	144:ef7eb2e8f9f7	1172	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
<>	144:ef7eb2e8f9f7	1173
<>	144:ef7eb2e8f9f7	1174	break;
<>	144:ef7eb2e8f9f7	1175
<>	144:ef7eb2e8f9f7	1176	/* Check analog watchdog 2 flag */
<>	144:ef7eb2e8f9f7	1177	case ADC_AWD2_EVENT:
<>	144:ef7eb2e8f9f7	1178	/* Change ADC state */
<>	144:ef7eb2e8f9f7	1179	SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
<>	144:ef7eb2e8f9f7	1180
<>	144:ef7eb2e8f9f7	1181	/* Clear ADC analog watchdog flag */
<>	144:ef7eb2e8f9f7	1182	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
<>	144:ef7eb2e8f9f7	1183
<>	144:ef7eb2e8f9f7	1184	break;
<>	144:ef7eb2e8f9f7	1185
<>	144:ef7eb2e8f9f7	1186	/* Check analog watchdog 3 flag */
<>	144:ef7eb2e8f9f7	1187	case ADC_AWD3_EVENT:
<>	144:ef7eb2e8f9f7	1188	/* Change ADC state */
<>	144:ef7eb2e8f9f7	1189	SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
<>	144:ef7eb2e8f9f7	1190
<>	144:ef7eb2e8f9f7	1191	/* Clear ADC analog watchdog flag */
<>	144:ef7eb2e8f9f7	1192	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
<>	144:ef7eb2e8f9f7	1193
<>	144:ef7eb2e8f9f7	1194	break;
<>	144:ef7eb2e8f9f7	1195
<>	144:ef7eb2e8f9f7	1196	/* Injected context queue overflow event */
<>	144:ef7eb2e8f9f7	1197	case ADC_JQOVF_EVENT:
<>	144:ef7eb2e8f9f7	1198	/* Change ADC state */
<>	144:ef7eb2e8f9f7	1199	SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
<>	144:ef7eb2e8f9f7	1200
<>	144:ef7eb2e8f9f7	1201	/* Set ADC error code to Injected context queue overflow */
<>	144:ef7eb2e8f9f7	1202	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
<>	144:ef7eb2e8f9f7	1203
<>	144:ef7eb2e8f9f7	1204	/* Clear ADC Injected context queue overflow flag */
<>	144:ef7eb2e8f9f7	1205	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
<>	144:ef7eb2e8f9f7	1206
<>	144:ef7eb2e8f9f7	1207	break;
<>	144:ef7eb2e8f9f7	1208
<>	144:ef7eb2e8f9f7	1209	/* Overrun event */
<>	144:ef7eb2e8f9f7	1210	default: /* Case ADC_OVR_EVENT */
<>	144:ef7eb2e8f9f7	1211	/* If overrun is set to overwrite previous data, overrun event is not */
<>	144:ef7eb2e8f9f7	1212	/* considered as an error. */
<>	144:ef7eb2e8f9f7	1213	/* (cf ref manual "Managing conversions without using the DMA and without */
<>	144:ef7eb2e8f9f7	1214	/* overrun ") */
<>	144:ef7eb2e8f9f7	1215	if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
<>	144:ef7eb2e8f9f7	1216	{
<>	144:ef7eb2e8f9f7	1217	/* Change ADC state */
<>	144:ef7eb2e8f9f7	1218	SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
<>	144:ef7eb2e8f9f7	1219
<>	144:ef7eb2e8f9f7	1220	/* Set ADC error code to overrun */
<>	144:ef7eb2e8f9f7	1221	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
<>	144:ef7eb2e8f9f7	1222	}
<>	144:ef7eb2e8f9f7	1223	else
<>	144:ef7eb2e8f9f7	1224	{
<>	144:ef7eb2e8f9f7	1225	/* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
<>	144:ef7eb2e8f9f7	1226	otherwise, DR is potentially overwritten by new converted data as soon
<>	144:ef7eb2e8f9f7	1227	as OVR is cleared. */
<>	144:ef7eb2e8f9f7	1228	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
<>	144:ef7eb2e8f9f7	1229	}
<>	144:ef7eb2e8f9f7	1230	break;
<>	144:ef7eb2e8f9f7	1231	}
<>	144:ef7eb2e8f9f7	1232
<>	144:ef7eb2e8f9f7	1233	/* Return API HAL status */
<>	144:ef7eb2e8f9f7	1234	return HAL_OK;
<>	144:ef7eb2e8f9f7	1235	}
<>	144:ef7eb2e8f9f7	1236
<>	144:ef7eb2e8f9f7	1237
<>	144:ef7eb2e8f9f7	1238	/**
<>	144:ef7eb2e8f9f7	1239	* @brief Enable ADC, start conversion of regular group with interruption.
<>	144:ef7eb2e8f9f7	1240	* @note Interruptions enabled in this function according to initialization
<>	144:ef7eb2e8f9f7	1241	* setting : EOC (end of conversion), EOS (end of sequence),
<>	144:ef7eb2e8f9f7	1242	* OVR overrun.
<>	144:ef7eb2e8f9f7	1243	* Each of these interruptions has its dedicated callback function.
<>	144:ef7eb2e8f9f7	1244	* @note Case of multimode enabled (when multimode feature is available):
<>	144:ef7eb2e8f9f7	1245	* HAL_ADC_Start_IT() must be called for ADC Slave first, then for
<>	144:ef7eb2e8f9f7	1246	* ADC Master.
<>	144:ef7eb2e8f9f7	1247	* For ADC Slave, ADC is enabled only (conversion is not started).
<>	144:ef7eb2e8f9f7	1248	* For ADC Master, ADC is enabled and multimode conversion is started.
<>	144:ef7eb2e8f9f7	1249	* @note To guarantee a proper reset of all interruptions once all the needed
<>	144:ef7eb2e8f9f7	1250	* conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
<>	144:ef7eb2e8f9f7	1251	* a correct stop of the IT-based conversions.
<>	144:ef7eb2e8f9f7	1252	* @note By default, HAL_ADC_Start_IT() doesn't enable the End Of Sampling
<>	144:ef7eb2e8f9f7	1253	* interruption. If required (e.g. in case of oversampling with trigger
<>	144:ef7eb2e8f9f7	1254	* mode), the user must
<>	144:ef7eb2e8f9f7	1255	* 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
<>	144:ef7eb2e8f9f7	1256	* 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
<>	144:ef7eb2e8f9f7	1257	* before calling HAL_ADC_Start_IT().
<>	144:ef7eb2e8f9f7	1258	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1259	* @retval HAL status
<>	144:ef7eb2e8f9f7	1260	*/
<>	144:ef7eb2e8f9f7	1261	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	1262	{
<>	144:ef7eb2e8f9f7	1263	HAL_StatusTypeDef tmp_status = HAL_OK;
<>	144:ef7eb2e8f9f7	1264	ADC_TypeDef *tmpADC_Master;
<>	144:ef7eb2e8f9f7	1265
<>	144:ef7eb2e8f9f7	1266	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1267	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	1268
<>	144:ef7eb2e8f9f7	1269	/* if a regular conversion is already on-going (i.e. ADSTART is set),
<>	144:ef7eb2e8f9f7	1270	don't restart the conversion. */
<>	144:ef7eb2e8f9f7	1271	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
<>	144:ef7eb2e8f9f7	1272	{
<>	144:ef7eb2e8f9f7	1273	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1274	}
<>	144:ef7eb2e8f9f7	1275	else
<>	144:ef7eb2e8f9f7	1276	{
<>	144:ef7eb2e8f9f7	1277	/* Process locked */
<>	144:ef7eb2e8f9f7	1278	__HAL_LOCK(hadc);
<>	144:ef7eb2e8f9f7	1279
<>	144:ef7eb2e8f9f7	1280	/* Enable the ADC peripheral */
<>	144:ef7eb2e8f9f7	1281	tmp_status = ADC_Enable(hadc);
<>	144:ef7eb2e8f9f7	1282
<>	144:ef7eb2e8f9f7	1283	/* Start conversion if ADC is effectively enabled */
<>	144:ef7eb2e8f9f7	1284	if (tmp_status == HAL_OK)
<>	144:ef7eb2e8f9f7	1285	{
<>	144:ef7eb2e8f9f7	1286	/* State machine update: Check if an injected conversion is ongoing */
<>	144:ef7eb2e8f9f7	1287	if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<>	144:ef7eb2e8f9f7	1288	{
<>	144:ef7eb2e8f9f7	1289	/* Reset ADC error code fields related to regular conversions only */
<>	144:ef7eb2e8f9f7	1290	CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR\|HAL_ADC_ERROR_DMA));
<>	144:ef7eb2e8f9f7	1291	}
<>	144:ef7eb2e8f9f7	1292	else
<>	144:ef7eb2e8f9f7	1293	{
<>	144:ef7eb2e8f9f7	1294	/* Set ADC error code to none */
<>	144:ef7eb2e8f9f7	1295	ADC_CLEAR_ERRORCODE(hadc);
<>	144:ef7eb2e8f9f7	1296	}
<>	144:ef7eb2e8f9f7	1297	/* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
<>	144:ef7eb2e8f9f7	1298	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY\|HAL_ADC_STATE_REG_EOC\|HAL_ADC_STATE_REG_OVR\|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
<>	144:ef7eb2e8f9f7	1299
<>	144:ef7eb2e8f9f7	1300	/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
<>	144:ef7eb2e8f9f7	1301	- by default if ADC is Master or Independent or if multimode feature is not available
<>	144:ef7eb2e8f9f7	1302	- if MultiMode setting is set to independent mode (no dual regular or injected conversions are configured) */
<>	144:ef7eb2e8f9f7	1303	if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
<>	144:ef7eb2e8f9f7	1304	{
<>	144:ef7eb2e8f9f7	1305	CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<>	144:ef7eb2e8f9f7	1306	}
<>	144:ef7eb2e8f9f7	1307
<>	144:ef7eb2e8f9f7	1308	/* Clear regular group conversion flag and overrun flag */
<>	144:ef7eb2e8f9f7	1309	/* (To ensure of no unknown state from potential previous ADC operations) */
<>	144:ef7eb2e8f9f7	1310	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC \| ADC_FLAG_EOS \| ADC_FLAG_OVR));
<>	144:ef7eb2e8f9f7	1311
<>	144:ef7eb2e8f9f7	1312	/* By default, disable all interruptions before enabling the desired ones */
<>	144:ef7eb2e8f9f7	1313	__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC \| ADC_IT_EOS \| ADC_IT_OVR));
<>	144:ef7eb2e8f9f7	1314
<>	144:ef7eb2e8f9f7	1315	/* Enable required interruptions */
<>	144:ef7eb2e8f9f7	1316	switch(hadc->Init.EOCSelection)
<>	144:ef7eb2e8f9f7	1317	{
<>	144:ef7eb2e8f9f7	1318	case ADC_EOC_SEQ_CONV:
<>	144:ef7eb2e8f9f7	1319	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
<>	144:ef7eb2e8f9f7	1320	break;
<>	144:ef7eb2e8f9f7	1321	/* case ADC_EOC_SINGLE_CONV */
<>	144:ef7eb2e8f9f7	1322	default:
<>	144:ef7eb2e8f9f7	1323	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
<>	144:ef7eb2e8f9f7	1324	break;
<>	144:ef7eb2e8f9f7	1325	}
<>	144:ef7eb2e8f9f7	1326
<>	144:ef7eb2e8f9f7	1327	/* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
<>	144:ef7eb2e8f9f7	1328	ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
<>	144:ef7eb2e8f9f7	1329	behavior and no CPU time is lost for a non-processed interruption */
<>	144:ef7eb2e8f9f7	1330	if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
<>	144:ef7eb2e8f9f7	1331	{
<>	144:ef7eb2e8f9f7	1332	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
<>	144:ef7eb2e8f9f7	1333	}
<>	144:ef7eb2e8f9f7	1334
<>	144:ef7eb2e8f9f7	1335	/* Enable conversion of regular group. */
<>	144:ef7eb2e8f9f7	1336	/* If software start has been selected, conversion starts immediately. */
<>	144:ef7eb2e8f9f7	1337	/* If external trigger has been selected, conversion starts at next */
<>	144:ef7eb2e8f9f7	1338	/* trigger event. */
<>	144:ef7eb2e8f9f7	1339	/* Case of multimode enabled (when multimode feature is available): */
<>	144:ef7eb2e8f9f7	1340	/* - if ADC is slave and dual regular conversions are enabled, ADC is */
<>	144:ef7eb2e8f9f7	1341	/* enabled only (conversion is not started), */
<>	144:ef7eb2e8f9f7	1342	/* - if ADC is master, ADC is enabled and conversion is started. */
<>	144:ef7eb2e8f9f7	1343	if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc) )
<>	144:ef7eb2e8f9f7	1344	{
<>	144:ef7eb2e8f9f7	1345	/* Multimode feature is not available or ADC Instance is Independent or Master,
<>	144:ef7eb2e8f9f7	1346	or is not Slave ADC with dual regular conversions enabled.
<>	144:ef7eb2e8f9f7	1347	Then set HAL_ADC_STATE_INJ_BUSY and reset HAL_ADC_STATE_INJ_EOC if JAUTO is set. */
<>	144:ef7eb2e8f9f7	1348	if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
<>	144:ef7eb2e8f9f7	1349	{
<>	144:ef7eb2e8f9f7	1350	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<>	144:ef7eb2e8f9f7	1351
<>	144:ef7eb2e8f9f7	1352	/* Enable as well injected interruptions in case
<>	144:ef7eb2e8f9f7	1353	HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
<>	144:ef7eb2e8f9f7	1354	allows to start regular and injected conversions when JAUTO is
<>	144:ef7eb2e8f9f7	1355	set with a single call to HAL_ADC_Start_IT() */
<>	144:ef7eb2e8f9f7	1356	switch(hadc->Init.EOCSelection)
<>	144:ef7eb2e8f9f7	1357	{
<>	144:ef7eb2e8f9f7	1358	case ADC_EOC_SEQ_CONV:
<>	144:ef7eb2e8f9f7	1359	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
<>	144:ef7eb2e8f9f7	1360	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
<>	144:ef7eb2e8f9f7	1361	break;
<>	144:ef7eb2e8f9f7	1362	/* case ADC_EOC_SINGLE_CONV */
<>	144:ef7eb2e8f9f7	1363	default:
<>	144:ef7eb2e8f9f7	1364	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
<>	144:ef7eb2e8f9f7	1365	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
<>	144:ef7eb2e8f9f7	1366	break;
<>	144:ef7eb2e8f9f7	1367	}
<>	144:ef7eb2e8f9f7	1368	} /* if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET) */
<>	144:ef7eb2e8f9f7	1369	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1370	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	1371	/* Start ADC */
<>	144:ef7eb2e8f9f7	1372	SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
<>	144:ef7eb2e8f9f7	1373	}
<>	144:ef7eb2e8f9f7	1374	else
<>	144:ef7eb2e8f9f7	1375	{
<>	144:ef7eb2e8f9f7	1376	/* hadc is the handle of a Slave ADC with dual regular conversions
<>	144:ef7eb2e8f9f7	1377	enabled. Therefore, ADC_CR_ADSTART is NOT set */
<>	144:ef7eb2e8f9f7	1378	SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<>	144:ef7eb2e8f9f7	1379	/* if Master ADC JAUTO bit is set, Slave injected interruptions
<>	144:ef7eb2e8f9f7	1380	are enabled nevertheless (for same reason as above) */
<>	144:ef7eb2e8f9f7	1381	tmpADC_Master = ADC_MASTER_REGISTER(hadc);
<>	144:ef7eb2e8f9f7	1382	if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET)
<>	144:ef7eb2e8f9f7	1383	{
<>	144:ef7eb2e8f9f7	1384	/* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit
<>	144:ef7eb2e8f9f7	1385	and in resetting HAL_ADC_STATE_INJ_EOC bit */
<>	144:ef7eb2e8f9f7	1386	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<>	144:ef7eb2e8f9f7	1387	/* Next, set Slave injected interruptions */
<>	144:ef7eb2e8f9f7	1388	switch(hadc->Init.EOCSelection)
<>	144:ef7eb2e8f9f7	1389	{
<>	144:ef7eb2e8f9f7	1390	case ADC_EOC_SEQ_CONV:
<>	144:ef7eb2e8f9f7	1391	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
<>	144:ef7eb2e8f9f7	1392	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
<>	144:ef7eb2e8f9f7	1393	break;
<>	144:ef7eb2e8f9f7	1394	/* case ADC_EOC_SINGLE_CONV */
<>	144:ef7eb2e8f9f7	1395	default:
<>	144:ef7eb2e8f9f7	1396	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
<>	144:ef7eb2e8f9f7	1397	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
<>	144:ef7eb2e8f9f7	1398	break;
<>	144:ef7eb2e8f9f7	1399	}
<>	144:ef7eb2e8f9f7	1400	} /* if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) */
<>	144:ef7eb2e8f9f7	1401	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1402	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	1403	} /* if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc) ) */
<>	144:ef7eb2e8f9f7	1404	} /* if (tmp_status == HAL_OK) */
<>	144:ef7eb2e8f9f7	1405	else
<>	144:ef7eb2e8f9f7	1406	{
<>	144:ef7eb2e8f9f7	1407	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1408	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	1409	}
<>	144:ef7eb2e8f9f7	1410
<>	144:ef7eb2e8f9f7	1411	/* Return function status */
<>	144:ef7eb2e8f9f7	1412	return tmp_status;
<>	144:ef7eb2e8f9f7	1413
<>	144:ef7eb2e8f9f7	1414	}
<>	144:ef7eb2e8f9f7	1415	}
<>	144:ef7eb2e8f9f7	1416
<>	144:ef7eb2e8f9f7	1417
<>	144:ef7eb2e8f9f7	1418
<>	144:ef7eb2e8f9f7	1419	/**
<>	144:ef7eb2e8f9f7	1420	* @brief Stop ADC conversion of regular groups when interruptions are enabled.
<>	144:ef7eb2e8f9f7	1421	* @note Stop as well injected conversions and disable ADC peripheral.
<>	144:ef7eb2e8f9f7	1422	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1423	* @retval HAL status.
<>	144:ef7eb2e8f9f7	1424	*/
<>	144:ef7eb2e8f9f7	1425	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	1426	{
<>	144:ef7eb2e8f9f7	1427	HAL_StatusTypeDef tmp_status = HAL_OK;
<>	144:ef7eb2e8f9f7	1428
<>	144:ef7eb2e8f9f7	1429	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1430	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	1431
<>	144:ef7eb2e8f9f7	1432	/* Process locked */
<>	144:ef7eb2e8f9f7	1433	__HAL_LOCK(hadc);
<>	144:ef7eb2e8f9f7	1434
<>	144:ef7eb2e8f9f7	1435	/* 1. Stop potential regular and injected on-going conversions */
<>	144:ef7eb2e8f9f7	1436	tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
<>	144:ef7eb2e8f9f7	1437
<>	144:ef7eb2e8f9f7	1438	/* Disable ADC peripheral if conversions are effectively stopped */
<>	144:ef7eb2e8f9f7	1439	if (tmp_status == HAL_OK)
<>	144:ef7eb2e8f9f7	1440	{
<>	144:ef7eb2e8f9f7	1441	/* Disable all interrupts */
<>	144:ef7eb2e8f9f7	1442	__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC \| ADC_IT_EOS \| ADC_IT_OVR));
<>	144:ef7eb2e8f9f7	1443
<>	144:ef7eb2e8f9f7	1444	/* 2. Disable the ADC peripheral */
<>	144:ef7eb2e8f9f7	1445	tmp_status = ADC_Disable(hadc);
<>	144:ef7eb2e8f9f7	1446
<>	144:ef7eb2e8f9f7	1447	/* Check if ADC is effectively disabled */
<>	144:ef7eb2e8f9f7	1448	if (tmp_status == HAL_OK)
<>	144:ef7eb2e8f9f7	1449	{
<>	144:ef7eb2e8f9f7	1450	/* Change ADC state */
<>	144:ef7eb2e8f9f7	1451	/* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
<>	144:ef7eb2e8f9f7	1452	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY\|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
<>	144:ef7eb2e8f9f7	1453	}
<>	144:ef7eb2e8f9f7	1454	}
<>	144:ef7eb2e8f9f7	1455
<>	144:ef7eb2e8f9f7	1456	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1457	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	1458
<>	144:ef7eb2e8f9f7	1459	/* Return function status */
<>	144:ef7eb2e8f9f7	1460	return tmp_status;
<>	144:ef7eb2e8f9f7	1461	}
<>	144:ef7eb2e8f9f7	1462
<>	144:ef7eb2e8f9f7	1463
<>	144:ef7eb2e8f9f7	1464	/**
<>	144:ef7eb2e8f9f7	1465	* @brief Enable ADC, start conversion of regular group and transfer result through DMA.
<>	144:ef7eb2e8f9f7	1466	* @note Interruptions enabled in this function:
<>	144:ef7eb2e8f9f7	1467	* overrun (if applicable), DMA half transfer, DMA transfer complete.
<>	144:ef7eb2e8f9f7	1468	* Each of these interruptions has its dedicated callback function.
<>	144:ef7eb2e8f9f7	1469	* @note Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA()
<>	144:ef7eb2e8f9f7	1470	* is designed for single-ADC mode only. For multimode, the dedicated
<>	144:ef7eb2e8f9f7	1471	* HAL_ADCEx_MultiModeStart_DMA() function must be used.
<>	144:ef7eb2e8f9f7	1472	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1473	* @param pData: Destination Buffer address.
<>	144:ef7eb2e8f9f7	1474	* @param Length: Length of data to be transferred from ADC peripheral to memory (in bytes)
<>	144:ef7eb2e8f9f7	1475	* @retval None
<>	144:ef7eb2e8f9f7	1476	*/
<>	144:ef7eb2e8f9f7	1477	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
<>	144:ef7eb2e8f9f7	1478	{
<>	144:ef7eb2e8f9f7	1479	HAL_StatusTypeDef tmp_status = HAL_OK;
<>	144:ef7eb2e8f9f7	1480
<>	144:ef7eb2e8f9f7	1481	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1482	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	1483
<>	144:ef7eb2e8f9f7	1484	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
<>	144:ef7eb2e8f9f7	1485	{
<>	144:ef7eb2e8f9f7	1486	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1487	}
<>	144:ef7eb2e8f9f7	1488	else
<>	144:ef7eb2e8f9f7	1489	{
<>	144:ef7eb2e8f9f7	1490
<>	144:ef7eb2e8f9f7	1491	/* Process locked */
<>	144:ef7eb2e8f9f7	1492	__HAL_LOCK(hadc);
<>	144:ef7eb2e8f9f7	1493
<>	144:ef7eb2e8f9f7	1494	/* Ensure that dual regular conversions are not enabled or unavailable. */
<>	144:ef7eb2e8f9f7	1495	/* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */
<>	144:ef7eb2e8f9f7	1496	if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET)
<>	144:ef7eb2e8f9f7	1497	{
<>	144:ef7eb2e8f9f7	1498	/* Enable the ADC peripheral */
<>	144:ef7eb2e8f9f7	1499	tmp_status = ADC_Enable(hadc);
<>	144:ef7eb2e8f9f7	1500
<>	144:ef7eb2e8f9f7	1501	/* Start conversion if ADC is effectively enabled */
<>	144:ef7eb2e8f9f7	1502	if (tmp_status == HAL_OK)
<>	144:ef7eb2e8f9f7	1503	{
<>	144:ef7eb2e8f9f7	1504	/* State machine update: Check if an injected conversion is ongoing */
<>	144:ef7eb2e8f9f7	1505	if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<>	144:ef7eb2e8f9f7	1506	{
<>	144:ef7eb2e8f9f7	1507	/* Reset ADC error code fields related to regular conversions only */
<>	144:ef7eb2e8f9f7	1508	CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR\|HAL_ADC_ERROR_DMA));
<>	144:ef7eb2e8f9f7	1509	}
<>	144:ef7eb2e8f9f7	1510	else
<>	144:ef7eb2e8f9f7	1511	{
<>	144:ef7eb2e8f9f7	1512	/* Set ADC error code to none */
<>	144:ef7eb2e8f9f7	1513	ADC_CLEAR_ERRORCODE(hadc);
<>	144:ef7eb2e8f9f7	1514	}
<>	144:ef7eb2e8f9f7	1515	/* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
<>	144:ef7eb2e8f9f7	1516	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY\|HAL_ADC_STATE_REG_EOC\|HAL_ADC_STATE_REG_OVR\|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
<>	144:ef7eb2e8f9f7	1517
<>	144:ef7eb2e8f9f7	1518	/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
<>	144:ef7eb2e8f9f7	1519	- by default if ADC is Master or Independent or if multimode feature is not available
<>	144:ef7eb2e8f9f7	1520	- if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
<>	144:ef7eb2e8f9f7	1521	if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
<>	144:ef7eb2e8f9f7	1522	{
<>	144:ef7eb2e8f9f7	1523	CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<>	144:ef7eb2e8f9f7	1524	}
<>	144:ef7eb2e8f9f7	1525
<>	144:ef7eb2e8f9f7	1526	/* Set the DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1527	hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
<>	144:ef7eb2e8f9f7	1528
<>	144:ef7eb2e8f9f7	1529	/* Set the DMA half transfer complete callback */
<>	144:ef7eb2e8f9f7	1530	hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
<>	144:ef7eb2e8f9f7	1531
<>	144:ef7eb2e8f9f7	1532	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1533	hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
<>	144:ef7eb2e8f9f7	1534
<>	144:ef7eb2e8f9f7	1535
<>	144:ef7eb2e8f9f7	1536	/* Manage ADC and DMA start: ADC overrun interruption, DMA start, */
<>	144:ef7eb2e8f9f7	1537	/* ADC start (in case of SW start): */
<>	144:ef7eb2e8f9f7	1538
<>	144:ef7eb2e8f9f7	1539	/* Clear regular group conversion flag and overrun flag */
<>	144:ef7eb2e8f9f7	1540	/* (To ensure of no unknown state from potential previous ADC */
<>	144:ef7eb2e8f9f7	1541	/* operations) */
<>	144:ef7eb2e8f9f7	1542	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC \| ADC_FLAG_EOS \| ADC_FLAG_OVR));
<>	144:ef7eb2e8f9f7	1543
<>	144:ef7eb2e8f9f7	1544	/* With DMA, overrun event is always considered as an error even if
<>	144:ef7eb2e8f9f7	1545	hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
<>	144:ef7eb2e8f9f7	1546	ADC_IT_OVR is enabled. */
<>	144:ef7eb2e8f9f7	1547	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
<>	144:ef7eb2e8f9f7	1548
<>	144:ef7eb2e8f9f7	1549
<>	144:ef7eb2e8f9f7	1550	/* Enable ADC DMA mode */
<>	144:ef7eb2e8f9f7	1551	SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
<>	144:ef7eb2e8f9f7	1552
<>	144:ef7eb2e8f9f7	1553	/* Start the DMA channel */
<>	144:ef7eb2e8f9f7	1554	HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
<>	144:ef7eb2e8f9f7	1555
<>	144:ef7eb2e8f9f7	1556	/* Enable conversion of regular group. */
<>	144:ef7eb2e8f9f7	1557	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1558	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	1559	/* If software start has been selected, conversion starts immediately. */
<>	144:ef7eb2e8f9f7	1560	/* If external trigger has been selected, conversion will start at next */
<>	144:ef7eb2e8f9f7	1561	/* trigger event. */
<>	144:ef7eb2e8f9f7	1562	SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
<>	144:ef7eb2e8f9f7	1563
<>	144:ef7eb2e8f9f7	1564	}
<>	144:ef7eb2e8f9f7	1565	else
<>	144:ef7eb2e8f9f7	1566	{
<>	144:ef7eb2e8f9f7	1567	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1568	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	1569	} /* if (tmp_status == HAL_OK) */
<>	144:ef7eb2e8f9f7	1570	}
<>	144:ef7eb2e8f9f7	1571	else
<>	144:ef7eb2e8f9f7	1572	{
<>	144:ef7eb2e8f9f7	1573	tmp_status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1574	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1575	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	1576	} /* if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET) */
<>	144:ef7eb2e8f9f7	1577
<>	144:ef7eb2e8f9f7	1578
<>	144:ef7eb2e8f9f7	1579
<>	144:ef7eb2e8f9f7	1580	/* Return function status */
<>	144:ef7eb2e8f9f7	1581	return tmp_status;
<>	144:ef7eb2e8f9f7	1582	} /* if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)) */
<>	144:ef7eb2e8f9f7	1583	}
<>	144:ef7eb2e8f9f7	1584
<>	144:ef7eb2e8f9f7	1585
<>	144:ef7eb2e8f9f7	1586	/**
<>	144:ef7eb2e8f9f7	1587	* @brief Stop ADC conversion of regular groups and disable ADC DMA transfer.
<>	144:ef7eb2e8f9f7	1588	* @note Stop as well injected conversions and disable ADC peripheral.
<>	144:ef7eb2e8f9f7	1589	* @note Case of multimode enabled (when multimode feature is available):
<>	144:ef7eb2e8f9f7	1590	* HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only.
<>	144:ef7eb2e8f9f7	1591	* For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
<>	144:ef7eb2e8f9f7	1592	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1593	* @retval HAL status.
<>	144:ef7eb2e8f9f7	1594	*/
<>	144:ef7eb2e8f9f7	1595	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	1596	{
<>	144:ef7eb2e8f9f7	1597	HAL_StatusTypeDef tmp_status = HAL_OK;
<>	144:ef7eb2e8f9f7	1598
<>	144:ef7eb2e8f9f7	1599	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1600	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	1601
<>	144:ef7eb2e8f9f7	1602	/* Process locked */
<>	144:ef7eb2e8f9f7	1603	__HAL_LOCK(hadc);
<>	144:ef7eb2e8f9f7	1604
<>	144:ef7eb2e8f9f7	1605	/* 1. Stop potential regular conversion on going */
<>	144:ef7eb2e8f9f7	1606	tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
<>	144:ef7eb2e8f9f7	1607
<>	144:ef7eb2e8f9f7	1608	/* Disable ADC peripheral if conversions are effectively stopped */
<>	144:ef7eb2e8f9f7	1609	if (tmp_status == HAL_OK)
<>	144:ef7eb2e8f9f7	1610	{
<>	144:ef7eb2e8f9f7	1611	/* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
<>	144:ef7eb2e8f9f7	1612	CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
<>	144:ef7eb2e8f9f7	1613
<>	144:ef7eb2e8f9f7	1614	/* Disable the DMA channel (in case of DMA in circular mode or stop while */
<>	144:ef7eb2e8f9f7	1615	/* while DMA transfer is on going) */
<>	144:ef7eb2e8f9f7	1616	tmp_status = HAL_DMA_Abort(hadc->DMA_Handle);
<>	144:ef7eb2e8f9f7	1617
<>	144:ef7eb2e8f9f7	1618	/* Check if DMA channel effectively disabled */
<>	144:ef7eb2e8f9f7	1619	if (tmp_status != HAL_OK)
<>	144:ef7eb2e8f9f7	1620	{
<>	144:ef7eb2e8f9f7	1621	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	1622	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	1623	}
<>	144:ef7eb2e8f9f7	1624
<>	144:ef7eb2e8f9f7	1625	/* Disable ADC overrun interrupt */
<>	144:ef7eb2e8f9f7	1626	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
<>	144:ef7eb2e8f9f7	1627
<>	144:ef7eb2e8f9f7	1628	/* 2. Disable the ADC peripheral */
<>	144:ef7eb2e8f9f7	1629	/* Update "tmp_status" only if DMA channel disabling passed, to keep in */
<>	144:ef7eb2e8f9f7	1630	/* memory a potential failing status. */
<>	144:ef7eb2e8f9f7	1631	if (tmp_status == HAL_OK)
<>	144:ef7eb2e8f9f7	1632	{
<>	144:ef7eb2e8f9f7	1633	tmp_status = ADC_Disable(hadc);
<>	144:ef7eb2e8f9f7	1634	}
<>	144:ef7eb2e8f9f7	1635	else
<>	144:ef7eb2e8f9f7	1636	{
<>	144:ef7eb2e8f9f7	1637	ADC_Disable(hadc);
<>	144:ef7eb2e8f9f7	1638	}
<>	144:ef7eb2e8f9f7	1639
<>	144:ef7eb2e8f9f7	1640	/* Check if ADC is effectively disabled */
<>	144:ef7eb2e8f9f7	1641	if (tmp_status == HAL_OK)
<>	144:ef7eb2e8f9f7	1642	{
<>	144:ef7eb2e8f9f7	1643	/* Change ADC state */
<>	144:ef7eb2e8f9f7	1644	/* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
<>	144:ef7eb2e8f9f7	1645	ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY\|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
<>	144:ef7eb2e8f9f7	1646	}
<>	144:ef7eb2e8f9f7	1647
<>	144:ef7eb2e8f9f7	1648	}
<>	144:ef7eb2e8f9f7	1649
<>	144:ef7eb2e8f9f7	1650	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1651	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	1652
<>	144:ef7eb2e8f9f7	1653	/* Return function status */
<>	144:ef7eb2e8f9f7	1654	return tmp_status;
<>	144:ef7eb2e8f9f7	1655	}
<>	144:ef7eb2e8f9f7	1656
<>	144:ef7eb2e8f9f7	1657
<>	144:ef7eb2e8f9f7	1658	/**
<>	144:ef7eb2e8f9f7	1659	* @brief Get ADC regular group conversion result.
<>	144:ef7eb2e8f9f7	1660	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1661	* @note Reading DR register automatically clears EOC flag. To reset EOS flag,
<>	144:ef7eb2e8f9f7	1662	* the user must resort to the macro
<>	144:ef7eb2e8f9f7	1663	* __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS)
<>	144:ef7eb2e8f9f7	1664	* @retval Converted value
<>	144:ef7eb2e8f9f7	1665	*/
<>	144:ef7eb2e8f9f7	1666	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	1667	{
<>	144:ef7eb2e8f9f7	1668	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1669	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	1670
<>	144:ef7eb2e8f9f7	1671	/* Return ADC converted value */
<>	144:ef7eb2e8f9f7	1672	return hadc->Instance->DR;
<>	144:ef7eb2e8f9f7	1673	}
<>	144:ef7eb2e8f9f7	1674
<>	144:ef7eb2e8f9f7	1675
<>	144:ef7eb2e8f9f7	1676	/**
<>	144:ef7eb2e8f9f7	1677	* @brief Handle ADC interrupt request.
<>	144:ef7eb2e8f9f7	1678	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1679	* @retval None
<>	144:ef7eb2e8f9f7	1680	*/
<>	144:ef7eb2e8f9f7	1681	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	1682	{
<>	144:ef7eb2e8f9f7	1683	uint32_t overrun_error = 0; /* flag set if overrun occurrence has to be considered as an error */
<>	144:ef7eb2e8f9f7	1684	ADC_TypeDef *tmpADC_Master;
<>	144:ef7eb2e8f9f7	1685	uint32_t tmp_isr = hadc->Instance->ISR;
<>	144:ef7eb2e8f9f7	1686	uint32_t tmp_ier = hadc->Instance->IER;
<>	144:ef7eb2e8f9f7	1687	uint32_t tmp_cfgr = 0x0;
<>	144:ef7eb2e8f9f7	1688	uint32_t tmp_cfgr_jqm = 0x0;
<>	144:ef7eb2e8f9f7	1689
<>	144:ef7eb2e8f9f7	1690
<>	144:ef7eb2e8f9f7	1691	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1692	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	1693	assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
<>	144:ef7eb2e8f9f7	1694
<>	144:ef7eb2e8f9f7	1695
<>	144:ef7eb2e8f9f7	1696	/* ====== Check End of Sampling flag for regular group ===== */
<>	144:ef7eb2e8f9f7	1697	if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
<>	144:ef7eb2e8f9f7	1698	{
<>	144:ef7eb2e8f9f7	1699	/* Update state machine on end of sampling status if not in error state */
<>	144:ef7eb2e8f9f7	1700	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
<>	144:ef7eb2e8f9f7	1701	{
<>	144:ef7eb2e8f9f7	1702	/* Change ADC state */
<>	144:ef7eb2e8f9f7	1703	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
<>	144:ef7eb2e8f9f7	1704	}
<>	144:ef7eb2e8f9f7	1705
<>	144:ef7eb2e8f9f7	1706	/* End Of Sampling callback */
<>	144:ef7eb2e8f9f7	1707	HAL_ADCEx_EndOfSamplingCallback(hadc);
<>	144:ef7eb2e8f9f7	1708
<>	144:ef7eb2e8f9f7	1709	/* Clear regular group conversion flag */
<>	144:ef7eb2e8f9f7	1710	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP );
<>	144:ef7eb2e8f9f7	1711	}
<>	144:ef7eb2e8f9f7	1712
<>	144:ef7eb2e8f9f7	1713	/* ====== Check End of Conversion or Sequence flags for regular group ===== */
<>	144:ef7eb2e8f9f7	1714	if( (((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) \|\|
<>	144:ef7eb2e8f9f7	1715	(((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)) )
<>	144:ef7eb2e8f9f7	1716	{
<>	144:ef7eb2e8f9f7	1717	/* Update state machine on conversion status if not in error state */
<>	144:ef7eb2e8f9f7	1718	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
<>	144:ef7eb2e8f9f7	1719	{
<>	144:ef7eb2e8f9f7	1720	/* Change ADC state */
<>	144:ef7eb2e8f9f7	1721	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
<>	144:ef7eb2e8f9f7	1722	}
<>	144:ef7eb2e8f9f7	1723
<>	144:ef7eb2e8f9f7	1724	/* Disable interruption if no further conversion upcoming by regular */
<>	144:ef7eb2e8f9f7	1725	/* external trigger or by continuous mode, */
<>	144:ef7eb2e8f9f7	1726	/* and if scan sequence if completed. */
<>	144:ef7eb2e8f9f7	1727	if(ADC_IS_SOFTWARE_START_REGULAR(hadc))
<>	144:ef7eb2e8f9f7	1728	{
<>	144:ef7eb2e8f9f7	1729	if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
<>	144:ef7eb2e8f9f7	1730	{
<>	144:ef7eb2e8f9f7	1731	/* check CONT bit directly in handle ADC CFGR register */
<>	144:ef7eb2e8f9f7	1732	tmp_cfgr = READ_REG(hadc->Instance->CFGR);
<>	144:ef7eb2e8f9f7	1733	}
<>	144:ef7eb2e8f9f7	1734	else
<>	144:ef7eb2e8f9f7	1735	{
<>	144:ef7eb2e8f9f7	1736	/* else need to check Master ADC CONT bit */
<>	144:ef7eb2e8f9f7	1737	tmpADC_Master = ADC_MASTER_REGISTER(hadc);
<>	144:ef7eb2e8f9f7	1738	tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
<>	144:ef7eb2e8f9f7	1739	}
<>	144:ef7eb2e8f9f7	1740
<>	144:ef7eb2e8f9f7	1741	/* Carry on if continuous mode is disabled */
<>	144:ef7eb2e8f9f7	1742	if (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT)
<>	144:ef7eb2e8f9f7	1743	{
<>	144:ef7eb2e8f9f7	1744	/* If End of Sequence is reached, disable interrupts */
<>	144:ef7eb2e8f9f7	1745	if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
<>	144:ef7eb2e8f9f7	1746	{
<>	144:ef7eb2e8f9f7	1747	/* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
<>	144:ef7eb2e8f9f7	1748	/* ADSTART==0 (no conversion on going) */
<>	144:ef7eb2e8f9f7	1749	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<>	144:ef7eb2e8f9f7	1750	{
<>	144:ef7eb2e8f9f7	1751	/* Disable ADC end of sequence conversion interrupt */
<>	144:ef7eb2e8f9f7	1752	/* Note: if Overrun interrupt was enabled with EOC or EOS interrupt */
<>	144:ef7eb2e8f9f7	1753	/* in HAL_Start_IT(), it isn't disabled here because it can be used */
<>	144:ef7eb2e8f9f7	1754	/* by overrun IRQ process below. */
<>	144:ef7eb2e8f9f7	1755	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC \| ADC_IT_EOS);
<>	144:ef7eb2e8f9f7	1756	/* Clear HAL_ADC_STATE_REG_BUSY bit */
<>	144:ef7eb2e8f9f7	1757	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<>	144:ef7eb2e8f9f7	1758	/* If no injected conversion on-going, set HAL_ADC_STATE_READY bit */
<>	144:ef7eb2e8f9f7	1759	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<>	144:ef7eb2e8f9f7	1760	{
<>	144:ef7eb2e8f9f7	1761	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<>	144:ef7eb2e8f9f7	1762	}
<>	144:ef7eb2e8f9f7	1763	}
<>	144:ef7eb2e8f9f7	1764	else
<>	144:ef7eb2e8f9f7	1765	{
<>	144:ef7eb2e8f9f7	1766	/* Change ADC state to error state */
<>	144:ef7eb2e8f9f7	1767	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	1768
<>	144:ef7eb2e8f9f7	1769	/* Set ADC error code to ADC IP internal error */
<>	144:ef7eb2e8f9f7	1770	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	1771	}
<>	144:ef7eb2e8f9f7	1772	}
<>	144:ef7eb2e8f9f7	1773	} /* if (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT) */
<>	144:ef7eb2e8f9f7	1774	} /* if(ADC_IS_SOFTWARE_START_REGULAR(hadc) */
<>	144:ef7eb2e8f9f7	1775
<>	144:ef7eb2e8f9f7	1776	/* Conversion complete callback */
<>	144:ef7eb2e8f9f7	1777	/* Note: HAL_ADC_ConvCpltCallback can resort to
<>	144:ef7eb2e8f9f7	1778	if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) or
<>	144:ef7eb2e8f9f7	1779	if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOC)) to determine whether
<>	144:ef7eb2e8f9f7	1780	interruption has been triggered by end of conversion or end of
<>	144:ef7eb2e8f9f7	1781	sequence. */
<>	144:ef7eb2e8f9f7	1782	HAL_ADC_ConvCpltCallback(hadc);
<>	144:ef7eb2e8f9f7	1783
<>	144:ef7eb2e8f9f7	1784
<>	144:ef7eb2e8f9f7	1785	/* Clear regular group conversion flag */
<>	144:ef7eb2e8f9f7	1786	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC \| ADC_FLAG_EOS) );
<>	144:ef7eb2e8f9f7	1787	}
<>	144:ef7eb2e8f9f7	1788
<>	144:ef7eb2e8f9f7	1789
<>	144:ef7eb2e8f9f7	1790	/* ========== Check End of Conversion flag for injected group ========== */
<>	144:ef7eb2e8f9f7	1791	if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) \|\|
<>	144:ef7eb2e8f9f7	1792	(((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)) )
<>	144:ef7eb2e8f9f7	1793	{
<>	144:ef7eb2e8f9f7	1794	/* Update state machine on conversion status if not in error state */
<>	144:ef7eb2e8f9f7	1795	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
<>	144:ef7eb2e8f9f7	1796	{
<>	144:ef7eb2e8f9f7	1797	/* Change ADC state */
<>	144:ef7eb2e8f9f7	1798	SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
<>	144:ef7eb2e8f9f7	1799	}
<>	144:ef7eb2e8f9f7	1800
<>	144:ef7eb2e8f9f7	1801
<>	144:ef7eb2e8f9f7	1802	/* Check whether interruptions can be disabled only if
<>	144:ef7eb2e8f9f7	1803	- injected conversions are software-triggered when injected queue management is disabled
<>	144:ef7eb2e8f9f7	1804	OR
<>	144:ef7eb2e8f9f7	1805	- auto-injection is enabled, continuous mode is disabled (CONT = 0)
<>	144:ef7eb2e8f9f7	1806	and regular conversions are software-triggered */
<>	144:ef7eb2e8f9f7	1807	/* If End of Sequence is reached, disable interrupts */
<>	144:ef7eb2e8f9f7	1808	if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
<>	144:ef7eb2e8f9f7	1809	{
<>	144:ef7eb2e8f9f7	1810
<>	144:ef7eb2e8f9f7	1811	/* First, retrieve proper registers to check */
<>	144:ef7eb2e8f9f7	1812	/* 1a. Are injected conversions that of a dual Slave ? */
<>	144:ef7eb2e8f9f7	1813	if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc))
<>	144:ef7eb2e8f9f7	1814	{
<>	144:ef7eb2e8f9f7	1815	/* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
<>	144:ef7eb2e8f9f7	1816	check JQM bit directly in ADC CFGR register */
<>	144:ef7eb2e8f9f7	1817	tmp_cfgr_jqm = READ_REG(hadc->Instance->CFGR);
<>	144:ef7eb2e8f9f7	1818	}
<>	144:ef7eb2e8f9f7	1819	else
<>	144:ef7eb2e8f9f7	1820	{
<>	144:ef7eb2e8f9f7	1821	/* hadc is the handle of a Slave ADC with dual injected conversions enabled:
<>	144:ef7eb2e8f9f7	1822	need to check JQM bit of Master ADC CFGR register */
<>	144:ef7eb2e8f9f7	1823	tmpADC_Master = ADC_MASTER_REGISTER(hadc);
<>	144:ef7eb2e8f9f7	1824	tmp_cfgr_jqm = READ_REG(tmpADC_Master->CFGR);
<>	144:ef7eb2e8f9f7	1825	}
<>	144:ef7eb2e8f9f7	1826	/* 1b. Is hadc the handle of a Slave ADC with regular conversions enabled? */
<>	144:ef7eb2e8f9f7	1827	if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
<>	144:ef7eb2e8f9f7	1828	{
<>	144:ef7eb2e8f9f7	1829	/* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
<>	144:ef7eb2e8f9f7	1830	check JAUTO and CONT bits directly in ADC CFGR register */
<>	144:ef7eb2e8f9f7	1831	tmp_cfgr = READ_REG(hadc->Instance->CFGR);
<>	144:ef7eb2e8f9f7	1832	}
<>	144:ef7eb2e8f9f7	1833	else
<>	144:ef7eb2e8f9f7	1834	{
<>	144:ef7eb2e8f9f7	1835	/* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
<>	144:ef7eb2e8f9f7	1836	check JAUTO and CONT bits of Master ADC CFGR register */
<>	144:ef7eb2e8f9f7	1837	tmpADC_Master = ADC_MASTER_REGISTER(hadc);
<>	144:ef7eb2e8f9f7	1838	tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
<>	144:ef7eb2e8f9f7	1839	}
<>	144:ef7eb2e8f9f7	1840
<>	144:ef7eb2e8f9f7	1841	/* Secondly, check whether JEOC and JEOS interruptions can be disabled */
<>	144:ef7eb2e8f9f7	1842	if ((ADC_IS_SOFTWARE_START_INJECTED(hadc) && (READ_BIT(tmp_cfgr_jqm, ADC_CFGR_JQM) != ADC_CFGR_JQM))
<>	144:ef7eb2e8f9f7	1843	&& (!((READ_BIT(tmp_cfgr, (ADC_CFGR_JAUTO\|ADC_CFGR_CONT)) == (ADC_CFGR_JAUTO\|ADC_CFGR_CONT)) &&
<>	144:ef7eb2e8f9f7	1844	(ADC_IS_SOFTWARE_START_REGULAR(hadc)))) )
<>	144:ef7eb2e8f9f7	1845	{
<>	144:ef7eb2e8f9f7	1846	/* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
<>	144:ef7eb2e8f9f7	1847	/* JADSTART==0 (no conversion on going) */
<>	144:ef7eb2e8f9f7	1848	if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
<>	144:ef7eb2e8f9f7	1849	{
<>	144:ef7eb2e8f9f7	1850	/* Disable ADC end of sequence conversion interrupt */
<>	144:ef7eb2e8f9f7	1851	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC \| ADC_IT_JEOS);
<>	144:ef7eb2e8f9f7	1852	/* Clear HAL_ADC_STATE_INJ_BUSY bit */
<>	144:ef7eb2e8f9f7	1853	CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
<>	144:ef7eb2e8f9f7	1854	/* If no regular conversion on-going, set HAL_ADC_STATE_READY bit */
<>	144:ef7eb2e8f9f7	1855	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
<>	144:ef7eb2e8f9f7	1856	{
<>	144:ef7eb2e8f9f7	1857	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<>	144:ef7eb2e8f9f7	1858	}
<>	144:ef7eb2e8f9f7	1859	}
<>	144:ef7eb2e8f9f7	1860	else
<>	144:ef7eb2e8f9f7	1861	{
<>	144:ef7eb2e8f9f7	1862	/* Change ADC state to error state */
<>	144:ef7eb2e8f9f7	1863	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	1864
<>	144:ef7eb2e8f9f7	1865	/* Set ADC error code to ADC IP internal error */
<>	144:ef7eb2e8f9f7	1866	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	1867	}
<>	144:ef7eb2e8f9f7	1868	}
<>	144:ef7eb2e8f9f7	1869	} /* if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) */
<>	144:ef7eb2e8f9f7	1870
<>	144:ef7eb2e8f9f7	1871	/* Injected Conversion complete callback */
<>	144:ef7eb2e8f9f7	1872	/* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to
<>	144:ef7eb2e8f9f7	1873	if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
<>	144:ef7eb2e8f9f7	1874	if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
<>	144:ef7eb2e8f9f7	1875	interruption has been triggered by end of conversion or end of
<>	144:ef7eb2e8f9f7	1876	sequence. */
<>	144:ef7eb2e8f9f7	1877	HAL_ADCEx_InjectedConvCpltCallback(hadc);
<>	144:ef7eb2e8f9f7	1878
<>	144:ef7eb2e8f9f7	1879	/* Clear injected group conversion flag */
<>	144:ef7eb2e8f9f7	1880	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC \| ADC_FLAG_JEOS);
<>	144:ef7eb2e8f9f7	1881	}
<>	144:ef7eb2e8f9f7	1882
<>	144:ef7eb2e8f9f7	1883
<>	144:ef7eb2e8f9f7	1884	/* ========== Check Analog watchdog flags =================================================== */
<>	144:ef7eb2e8f9f7	1885
<>	144:ef7eb2e8f9f7	1886	/* ========== Check Analog watchdog 1 flags ========== */
<>	144:ef7eb2e8f9f7	1887	if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
<>	144:ef7eb2e8f9f7	1888	{
<>	144:ef7eb2e8f9f7	1889	/* Change ADC state */
<>	144:ef7eb2e8f9f7	1890	SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
<>	144:ef7eb2e8f9f7	1891
<>	144:ef7eb2e8f9f7	1892	/* Level out of window 1 callback */
<>	144:ef7eb2e8f9f7	1893	HAL_ADC_LevelOutOfWindowCallback(hadc);
<>	144:ef7eb2e8f9f7	1894	/* Clear ADC Analog watchdog flag */
<>	144:ef7eb2e8f9f7	1895	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
<>	144:ef7eb2e8f9f7	1896	}
<>	144:ef7eb2e8f9f7	1897
<>	144:ef7eb2e8f9f7	1898	/* ========== Check Analog watchdog 2 flags ========== */
<>	144:ef7eb2e8f9f7	1899	if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
<>	144:ef7eb2e8f9f7	1900	{
<>	144:ef7eb2e8f9f7	1901	/* Change ADC state */
<>	144:ef7eb2e8f9f7	1902	SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
<>	144:ef7eb2e8f9f7	1903
<>	144:ef7eb2e8f9f7	1904	/* Level out of window 2 callback */
<>	144:ef7eb2e8f9f7	1905	HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
<>	144:ef7eb2e8f9f7	1906	/* Clear ADC Analog watchdog flag */
<>	144:ef7eb2e8f9f7	1907	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
<>	144:ef7eb2e8f9f7	1908	}
<>	144:ef7eb2e8f9f7	1909
<>	144:ef7eb2e8f9f7	1910	/* ========== Check Analog watchdog 3 flags ========== */
<>	144:ef7eb2e8f9f7	1911	if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
<>	144:ef7eb2e8f9f7	1912	{
<>	144:ef7eb2e8f9f7	1913	/* Change ADC state */
<>	144:ef7eb2e8f9f7	1914	SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
<>	144:ef7eb2e8f9f7	1915
<>	144:ef7eb2e8f9f7	1916	/* Level out of window 3 callback */
<>	144:ef7eb2e8f9f7	1917	HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
<>	144:ef7eb2e8f9f7	1918	/* Clear ADC Analog watchdog flag */
<>	144:ef7eb2e8f9f7	1919	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
<>	144:ef7eb2e8f9f7	1920	}
<>	144:ef7eb2e8f9f7	1921
<>	144:ef7eb2e8f9f7	1922
<>	144:ef7eb2e8f9f7	1923	/* ========== Check Overrun flag ========== */
<>	144:ef7eb2e8f9f7	1924	if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
<>	144:ef7eb2e8f9f7	1925	{
<>	144:ef7eb2e8f9f7	1926	/* If overrun is set to overwrite previous data (default setting), */
<>	144:ef7eb2e8f9f7	1927	/* overrun event is not considered as an error. */
<>	144:ef7eb2e8f9f7	1928	/* (cf ref manual "Managing conversions without using the DMA and without */
<>	144:ef7eb2e8f9f7	1929	/* overrun ") */
<>	144:ef7eb2e8f9f7	1930	/* Exception for usage with DMA overrun event always considered as an */
<>	144:ef7eb2e8f9f7	1931	/* error. */
<>	144:ef7eb2e8f9f7	1932
<>	144:ef7eb2e8f9f7	1933	if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
<>	144:ef7eb2e8f9f7	1934	{
<>	144:ef7eb2e8f9f7	1935	overrun_error = 1;
<>	144:ef7eb2e8f9f7	1936	}
<>	144:ef7eb2e8f9f7	1937	else
<>	144:ef7eb2e8f9f7	1938	{
<>	144:ef7eb2e8f9f7	1939	/* check DMA configuration, depending on multimode set or not,
<>	144:ef7eb2e8f9f7	1940	or whether or not multimode feature is available */
<>	144:ef7eb2e8f9f7	1941	if (ADC_IS_DUAL_CONVERSION_ENABLE(hadc) == RESET)
<>	144:ef7eb2e8f9f7	1942	{
<>	144:ef7eb2e8f9f7	1943	/* Multimode not set or feature not available or ADC independent */
<>	144:ef7eb2e8f9f7	1944	if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN))
<>	144:ef7eb2e8f9f7	1945	{
<>	144:ef7eb2e8f9f7	1946	overrun_error = 1;
<>	144:ef7eb2e8f9f7	1947	}
<>	144:ef7eb2e8f9f7	1948	}
<>	144:ef7eb2e8f9f7	1949	else
<>	144:ef7eb2e8f9f7	1950	{
<>	144:ef7eb2e8f9f7	1951	/* Multimode (when feature is available) is enabled,
<>	144:ef7eb2e8f9f7	1952	Common Control Register MDMA bits must be checked. */
<>	144:ef7eb2e8f9f7	1953	if (ADC_MULTIMODE_DMA_ENABLED())
<>	144:ef7eb2e8f9f7	1954	{
<>	144:ef7eb2e8f9f7	1955	overrun_error = 1;
<>	144:ef7eb2e8f9f7	1956	}
<>	144:ef7eb2e8f9f7	1957	}
<>	144:ef7eb2e8f9f7	1958	}
<>	144:ef7eb2e8f9f7	1959
<>	144:ef7eb2e8f9f7	1960	if (overrun_error == 1)
<>	144:ef7eb2e8f9f7	1961	{
<>	144:ef7eb2e8f9f7	1962	/* Change ADC state to error state */
<>	144:ef7eb2e8f9f7	1963	SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
<>	144:ef7eb2e8f9f7	1964
<>	144:ef7eb2e8f9f7	1965	/* Set ADC error code to overrun */
<>	144:ef7eb2e8f9f7	1966	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
<>	144:ef7eb2e8f9f7	1967
<>	144:ef7eb2e8f9f7	1968	/* Error callback */
<>	144:ef7eb2e8f9f7	1969	HAL_ADC_ErrorCallback(hadc);
<>	144:ef7eb2e8f9f7	1970	}
<>	144:ef7eb2e8f9f7	1971
<>	144:ef7eb2e8f9f7	1972	/* Clear the Overrun flag, to be done AFTER HAL_ADC_ErrorCallback() since
<>	144:ef7eb2e8f9f7	1973	old data is preserved until OVR is reset */
<>	144:ef7eb2e8f9f7	1974	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
<>	144:ef7eb2e8f9f7	1975
<>	144:ef7eb2e8f9f7	1976	}
<>	144:ef7eb2e8f9f7	1977
<>	144:ef7eb2e8f9f7	1978
<>	144:ef7eb2e8f9f7	1979	/* ========== Check Injected context queue overflow flag ========== */
<>	144:ef7eb2e8f9f7	1980	if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
<>	144:ef7eb2e8f9f7	1981	{
<>	144:ef7eb2e8f9f7	1982	/* Change ADC state to overrun state */
<>	144:ef7eb2e8f9f7	1983	SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
<>	144:ef7eb2e8f9f7	1984
<>	144:ef7eb2e8f9f7	1985	/* Set ADC error code to Injected context queue overflow */
<>	144:ef7eb2e8f9f7	1986	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
<>	144:ef7eb2e8f9f7	1987
<>	144:ef7eb2e8f9f7	1988	/* Clear the Injected context queue overflow flag */
<>	144:ef7eb2e8f9f7	1989	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
<>	144:ef7eb2e8f9f7	1990
<>	144:ef7eb2e8f9f7	1991	/* Error callback */
<>	144:ef7eb2e8f9f7	1992	HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
<>	144:ef7eb2e8f9f7	1993	}
<>	144:ef7eb2e8f9f7	1994
<>	144:ef7eb2e8f9f7	1995	}
<>	144:ef7eb2e8f9f7	1996
<>	144:ef7eb2e8f9f7	1997	/**
<>	144:ef7eb2e8f9f7	1998	* @brief Conversion complete callback in non-blocking mode.
<>	144:ef7eb2e8f9f7	1999	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	2000	* @retval None
<>	144:ef7eb2e8f9f7	2001	*/
<>	144:ef7eb2e8f9f7	2002	__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	2003	{
<>	144:ef7eb2e8f9f7	2004	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2005	UNUSED(hadc);
<>	144:ef7eb2e8f9f7	2006
<>	144:ef7eb2e8f9f7	2007	/* NOTE : This function should not be modified. When the callback is needed,
<>	144:ef7eb2e8f9f7	2008	function HAL_ADC_ConvCpltCallback must be implemented in the user file.
<>	144:ef7eb2e8f9f7	2009	*/
<>	144:ef7eb2e8f9f7	2010	}
<>	144:ef7eb2e8f9f7	2011
<>	144:ef7eb2e8f9f7	2012	/**
<>	144:ef7eb2e8f9f7	2013	* @brief Conversion DMA half-transfer callback in non-blocking mode.
<>	144:ef7eb2e8f9f7	2014	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	2015	* @retval None
<>	144:ef7eb2e8f9f7	2016	*/
<>	144:ef7eb2e8f9f7	2017	__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	2018	{
<>	144:ef7eb2e8f9f7	2019	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2020	UNUSED(hadc);
<>	144:ef7eb2e8f9f7	2021
<>	144:ef7eb2e8f9f7	2022	/* NOTE : This function should not be modified. When the callback is needed,
<>	144:ef7eb2e8f9f7	2023	function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
<>	144:ef7eb2e8f9f7	2024	*/
<>	144:ef7eb2e8f9f7	2025	}
<>	144:ef7eb2e8f9f7	2026
<>	144:ef7eb2e8f9f7	2027	/**
<>	144:ef7eb2e8f9f7	2028	* @brief Analog watchdog 1 callback in non-blocking mode.
<>	144:ef7eb2e8f9f7	2029	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	2030	* @retval None
<>	144:ef7eb2e8f9f7	2031	*/
<>	144:ef7eb2e8f9f7	2032	__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	2033	{
<>	144:ef7eb2e8f9f7	2034	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2035	UNUSED(hadc);
<>	144:ef7eb2e8f9f7	2036
<>	144:ef7eb2e8f9f7	2037	/* NOTE : This function should not be modified. When the callback is needed,
<>	144:ef7eb2e8f9f7	2038	function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
<>	144:ef7eb2e8f9f7	2039	*/
<>	144:ef7eb2e8f9f7	2040	}
<>	144:ef7eb2e8f9f7	2041
<>	144:ef7eb2e8f9f7	2042	/**
<>	144:ef7eb2e8f9f7	2043	* @brief ADC error callback in non-blocking mode
<>	144:ef7eb2e8f9f7	2044	* (ADC conversion with interruption or transfer by DMA).
<>	144:ef7eb2e8f9f7	2045	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	2046	* @retval None
<>	144:ef7eb2e8f9f7	2047	*/
<>	144:ef7eb2e8f9f7	2048	__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
<>	144:ef7eb2e8f9f7	2049	{
<>	144:ef7eb2e8f9f7	2050	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2051	UNUSED(hadc);
<>	144:ef7eb2e8f9f7	2052
<>	144:ef7eb2e8f9f7	2053	/* NOTE : This function should not be modified. When the callback is needed,
<>	144:ef7eb2e8f9f7	2054	function HAL_ADC_ErrorCallback must be implemented in the user file.
<>	144:ef7eb2e8f9f7	2055	*/
<>	144:ef7eb2e8f9f7	2056	}
<>	144:ef7eb2e8f9f7	2057
<>	144:ef7eb2e8f9f7	2058	/**
<>	144:ef7eb2e8f9f7	2059	* @}
<>	144:ef7eb2e8f9f7	2060	*/
<>	144:ef7eb2e8f9f7	2061
<>	144:ef7eb2e8f9f7	2062	/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
<>	144:ef7eb2e8f9f7	2063	* @brief Peripheral Control functions
<>	144:ef7eb2e8f9f7	2064	*
<>	144:ef7eb2e8f9f7	2065	@verbatim
<>	144:ef7eb2e8f9f7	2066	===============================================================================
<>	144:ef7eb2e8f9f7	2067	##### Peripheral Control functions #####
<>	144:ef7eb2e8f9f7	2068	===============================================================================
<>	144:ef7eb2e8f9f7	2069	[..] This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	2070	(+) Configure channels on regular group
<>	144:ef7eb2e8f9f7	2071	(+) Configure the analog watchdog
<>	144:ef7eb2e8f9f7	2072
<>	144:ef7eb2e8f9f7	2073	@endverbatim
<>	144:ef7eb2e8f9f7	2074	* @{
<>	144:ef7eb2e8f9f7	2075	*/
<>	144:ef7eb2e8f9f7	2076
<>	144:ef7eb2e8f9f7	2077
<>	144:ef7eb2e8f9f7	2078	/**
<>	144:ef7eb2e8f9f7	2079	* @brief Configure the selected channel to be linked to the regular group.
<>	144:ef7eb2e8f9f7	2080	* @note In case of usage of internal measurement channels (Vbat / VrefInt /
<>	144:ef7eb2e8f9f7	2081	* TempSensor), the recommended sampling time is provided by the
<>	144:ef7eb2e8f9f7	2082	* datasheet.
<>	144:ef7eb2e8f9f7	2083	* These internal paths can be disabled using function
<>	144:ef7eb2e8f9f7	2084	* HAL_ADC_DeInit().
<>	144:ef7eb2e8f9f7	2085	* @note Possibility to update parameters on the fly:
<>	144:ef7eb2e8f9f7	2086	* HAL_ADC_ConfigChannel() initializes channel into regular group,
<>	144:ef7eb2e8f9f7	2087	* consecutive calls to this function can be used to reconfigure some
<>	144:ef7eb2e8f9f7	2088	* parameters of structure "ADC_ChannelConfTypeDef" on the fly, without
<>	144:ef7eb2e8f9f7	2089	* resetting the ADC.
<>	144:ef7eb2e8f9f7	2090	* The setting of these parameters is conditioned to ADC state.
<>	144:ef7eb2e8f9f7	2091	* For parameters constraints, see comments of structure
<>	144:ef7eb2e8f9f7	2092	* "ADC_ChannelConfTypeDef".
<>	144:ef7eb2e8f9f7	2093	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	2094	* @param sConfig: Structure ADC channel for regular group.
<>	144:ef7eb2e8f9f7	2095	* @retval HAL status
<>	144:ef7eb2e8f9f7	2096	*/
<>	144:ef7eb2e8f9f7	2097	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
<>	144:ef7eb2e8f9f7	2098	{
<>	144:ef7eb2e8f9f7	2099	HAL_StatusTypeDef tmp_status = HAL_OK;
<>	144:ef7eb2e8f9f7	2100
<>	144:ef7eb2e8f9f7	2101	ADC_Common_TypeDef *tmpADC_Common;
<>	144:ef7eb2e8f9f7	2102	uint32_t tmpOffsetShifted;
<>	144:ef7eb2e8f9f7	2103	__IO uint32_t wait_loop_index = 0;
<>	144:ef7eb2e8f9f7	2104
<>	144:ef7eb2e8f9f7	2105	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2106	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	2107	assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
<>	144:ef7eb2e8f9f7	2108	assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
<>	144:ef7eb2e8f9f7	2109	assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
<>	144:ef7eb2e8f9f7	2110	assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
<>	144:ef7eb2e8f9f7	2111	assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
<>	144:ef7eb2e8f9f7	2112
<>	144:ef7eb2e8f9f7	2113	/* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
<>	144:ef7eb2e8f9f7	2114	ignored (considered as reset) */
<>	144:ef7eb2e8f9f7	2115	assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
<>	144:ef7eb2e8f9f7	2116
<>	144:ef7eb2e8f9f7	2117	/* Verification of channel number */
<>	144:ef7eb2e8f9f7	2118	if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
<>	144:ef7eb2e8f9f7	2119	{
<>	144:ef7eb2e8f9f7	2120	assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel));
<>	144:ef7eb2e8f9f7	2121	}
<>	144:ef7eb2e8f9f7	2122	else
<>	144:ef7eb2e8f9f7	2123	{
<>	144:ef7eb2e8f9f7	2124	assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfig->Channel));
<>	144:ef7eb2e8f9f7	2125	}
<>	144:ef7eb2e8f9f7	2126
<>	144:ef7eb2e8f9f7	2127	/* Process locked */
<>	144:ef7eb2e8f9f7	2128	__HAL_LOCK(hadc);
<>	144:ef7eb2e8f9f7	2129
<>	144:ef7eb2e8f9f7	2130
<>	144:ef7eb2e8f9f7	2131	/* Parameters update conditioned to ADC state: */
<>	144:ef7eb2e8f9f7	2132	/* Parameters that can be updated when ADC is disabled or enabled without */
<>	144:ef7eb2e8f9f7	2133	/* conversion on going on regular group: */
<>	144:ef7eb2e8f9f7	2134	/* - Channel number */
<>	144:ef7eb2e8f9f7	2135	/* - Channel rank */
<>	144:ef7eb2e8f9f7	2136	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<>	144:ef7eb2e8f9f7	2137	{
<>	144:ef7eb2e8f9f7	2138
<>	144:ef7eb2e8f9f7	2139	/* Regular sequence configuration */
<>	144:ef7eb2e8f9f7	2140	/* Clear the old SQx bits then set the new ones for the selected rank */
<>	144:ef7eb2e8f9f7	2141	/* For Rank 1 to 4 */
<>	144:ef7eb2e8f9f7	2142	if (sConfig->Rank < 5)
<>	144:ef7eb2e8f9f7	2143	{
<>	144:ef7eb2e8f9f7	2144	MODIFY_REG(hadc->Instance->SQR1,
<>	144:ef7eb2e8f9f7	2145	ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank),
<>	144:ef7eb2e8f9f7	2146	ADC_SQR1_RK(sConfig->Channel, sConfig->Rank));
<>	144:ef7eb2e8f9f7	2147	}
<>	144:ef7eb2e8f9f7	2148	/* For Rank 5 to 9 */
<>	144:ef7eb2e8f9f7	2149	else if (sConfig->Rank < 10)
<>	144:ef7eb2e8f9f7	2150	{
<>	144:ef7eb2e8f9f7	2151	MODIFY_REG(hadc->Instance->SQR2,
<>	144:ef7eb2e8f9f7	2152	ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank),
<>	144:ef7eb2e8f9f7	2153	ADC_SQR2_RK(sConfig->Channel, sConfig->Rank));
<>	144:ef7eb2e8f9f7	2154	}
<>	144:ef7eb2e8f9f7	2155	/* For Rank 10 to 14 */
<>	144:ef7eb2e8f9f7	2156	else if (sConfig->Rank < 15)
<>	144:ef7eb2e8f9f7	2157	{
<>	144:ef7eb2e8f9f7	2158	MODIFY_REG(hadc->Instance->SQR3,
<>	144:ef7eb2e8f9f7	2159	ADC_SQR3_RK(ADC_SQR3_SQ10, sConfig->Rank),
<>	144:ef7eb2e8f9f7	2160	ADC_SQR3_RK(sConfig->Channel, sConfig->Rank));
<>	144:ef7eb2e8f9f7	2161	}
<>	144:ef7eb2e8f9f7	2162	/* For Rank 15 to 16 */
<>	144:ef7eb2e8f9f7	2163	else
<>	144:ef7eb2e8f9f7	2164	{
<>	144:ef7eb2e8f9f7	2165	MODIFY_REG(hadc->Instance->SQR4,
<>	144:ef7eb2e8f9f7	2166	ADC_SQR4_RK(ADC_SQR4_SQ15, sConfig->Rank),
<>	144:ef7eb2e8f9f7	2167	ADC_SQR4_RK(sConfig->Channel, sConfig->Rank));
<>	144:ef7eb2e8f9f7	2168	}
<>	144:ef7eb2e8f9f7	2169
<>	144:ef7eb2e8f9f7	2170
<>	144:ef7eb2e8f9f7	2171	/* Parameters update conditioned to ADC state: */
<>	144:ef7eb2e8f9f7	2172	/* Parameters that can be updated when ADC is disabled or enabled without */
<>	144:ef7eb2e8f9f7	2173	/* conversion on going on regular group: */
<>	144:ef7eb2e8f9f7	2174	/* - Channel sampling time */
<>	144:ef7eb2e8f9f7	2175	/* - Channel offset */
<>	144:ef7eb2e8f9f7	2176	if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
<>	144:ef7eb2e8f9f7	2177	{
<>	144:ef7eb2e8f9f7	2178
<>	144:ef7eb2e8f9f7	2179	/* Channel sampling time configuration */
<>	144:ef7eb2e8f9f7	2180	/* Clear the old sample time then set the new one for the selected channel */
<>	144:ef7eb2e8f9f7	2181	/* For channels 10 to 18 */
<>	144:ef7eb2e8f9f7	2182	if (sConfig->Channel >= ADC_CHANNEL_10)
<>	144:ef7eb2e8f9f7	2183	{
<>	144:ef7eb2e8f9f7	2184	ADC_SMPR2_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel);
<>	144:ef7eb2e8f9f7	2185	}
<>	144:ef7eb2e8f9f7	2186	else /* For channels 0 to 9 */
<>	144:ef7eb2e8f9f7	2187	{
<>	144:ef7eb2e8f9f7	2188	ADC_SMPR1_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel);
<>	144:ef7eb2e8f9f7	2189	}
<>	144:ef7eb2e8f9f7	2190
<>	144:ef7eb2e8f9f7	2191
<>	144:ef7eb2e8f9f7	2192	/* Configure the offset: offset enable/disable, channel, offset value */
<>	144:ef7eb2e8f9f7	2193
<>	144:ef7eb2e8f9f7	2194	/* Shift the offset with respect to the selected ADC resolution. */
<>	144:ef7eb2e8f9f7	2195	/* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
<>	144:ef7eb2e8f9f7	2196	tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset);
<>	144:ef7eb2e8f9f7	2197
<>	144:ef7eb2e8f9f7	2198	switch (sConfig->OffsetNumber)
<>	144:ef7eb2e8f9f7	2199	{
<>	144:ef7eb2e8f9f7	2200	/* Configure offset register i when applicable: */
<>	144:ef7eb2e8f9f7	2201	/* - Enable offset */
<>	144:ef7eb2e8f9f7	2202	/* - Set channel number */
<>	144:ef7eb2e8f9f7	2203	/* - Set offset value */
<>	144:ef7eb2e8f9f7	2204	case ADC_OFFSET_1:
<>	144:ef7eb2e8f9f7	2205	MODIFY_REG(hadc->Instance->OFR1,
<>	144:ef7eb2e8f9f7	2206	ADC_OFR_FIELDS,
<>	144:ef7eb2e8f9f7	2207	ADC_OFR1_OFFSET1_EN \| ADC_OFR_CHANNEL(sConfig->Channel) \| tmpOffsetShifted);
<>	144:ef7eb2e8f9f7	2208	break;
<>	144:ef7eb2e8f9f7	2209
<>	144:ef7eb2e8f9f7	2210	case ADC_OFFSET_2:
<>	144:ef7eb2e8f9f7	2211	MODIFY_REG(hadc->Instance->OFR2,
<>	144:ef7eb2e8f9f7	2212	ADC_OFR_FIELDS,
<>	144:ef7eb2e8f9f7	2213	ADC_OFR2_OFFSET2_EN \| ADC_OFR_CHANNEL(sConfig->Channel) \| tmpOffsetShifted);
<>	144:ef7eb2e8f9f7	2214	break;
<>	144:ef7eb2e8f9f7	2215
<>	144:ef7eb2e8f9f7	2216	case ADC_OFFSET_3:
<>	144:ef7eb2e8f9f7	2217	MODIFY_REG(hadc->Instance->OFR3,
<>	144:ef7eb2e8f9f7	2218	ADC_OFR_FIELDS,
<>	144:ef7eb2e8f9f7	2219	ADC_OFR3_OFFSET3_EN \| ADC_OFR_CHANNEL(sConfig->Channel) \| tmpOffsetShifted);
<>	144:ef7eb2e8f9f7	2220	break;
<>	144:ef7eb2e8f9f7	2221
<>	144:ef7eb2e8f9f7	2222	case ADC_OFFSET_4:
<>	144:ef7eb2e8f9f7	2223	MODIFY_REG(hadc->Instance->OFR4,
<>	144:ef7eb2e8f9f7	2224	ADC_OFR_FIELDS,
<>	144:ef7eb2e8f9f7	2225	ADC_OFR4_OFFSET4_EN \| ADC_OFR_CHANNEL(sConfig->Channel) \| tmpOffsetShifted);
<>	144:ef7eb2e8f9f7	2226	break;
<>	144:ef7eb2e8f9f7	2227
<>	144:ef7eb2e8f9f7	2228	/* Case ADC_OFFSET_NONE */
<>	144:ef7eb2e8f9f7	2229	default :
<>	144:ef7eb2e8f9f7	2230	/* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled.
<>	144:ef7eb2e8f9f7	2231	If this is the case, offset OFRx is disabled since
<>	144:ef7eb2e8f9f7	2232	sConfig->OffsetNumber = ADC_OFFSET_NONE. */
<>	144:ef7eb2e8f9f7	2233	if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
<>	144:ef7eb2e8f9f7	2234	{
<>	144:ef7eb2e8f9f7	2235	CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
<>	144:ef7eb2e8f9f7	2236	}
<>	144:ef7eb2e8f9f7	2237	if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
<>	144:ef7eb2e8f9f7	2238	{
<>	144:ef7eb2e8f9f7	2239	CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN);
<>	144:ef7eb2e8f9f7	2240	}
<>	144:ef7eb2e8f9f7	2241	if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
<>	144:ef7eb2e8f9f7	2242	{
<>	144:ef7eb2e8f9f7	2243	CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN);
<>	144:ef7eb2e8f9f7	2244	}
<>	144:ef7eb2e8f9f7	2245	if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
<>	144:ef7eb2e8f9f7	2246	{
<>	144:ef7eb2e8f9f7	2247	CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN);
<>	144:ef7eb2e8f9f7	2248	}
<>	144:ef7eb2e8f9f7	2249	break;
<>	144:ef7eb2e8f9f7	2250	} /* switch (sConfig->OffsetNumber) */
<>	144:ef7eb2e8f9f7	2251
<>	144:ef7eb2e8f9f7	2252	} /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
<>	144:ef7eb2e8f9f7	2253
<>	144:ef7eb2e8f9f7	2254
<>	144:ef7eb2e8f9f7	2255
<>	144:ef7eb2e8f9f7	2256	/* Parameters update conditioned to ADC state: */
<>	144:ef7eb2e8f9f7	2257	/* Parameters that can be updated only when ADC is disabled: */
<>	144:ef7eb2e8f9f7	2258	/* - Single or differential mode */
<>	144:ef7eb2e8f9f7	2259	/* - Internal measurement channels: Vbat/VrefInt/TempSensor */
<>	144:ef7eb2e8f9f7	2260	if (ADC_IS_ENABLE(hadc) == RESET)
<>	144:ef7eb2e8f9f7	2261	{
<>	144:ef7eb2e8f9f7	2262	/* Configuration of differential mode */
<>	144:ef7eb2e8f9f7	2263	if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
<>	144:ef7eb2e8f9f7	2264	{
<>	144:ef7eb2e8f9f7	2265	/* Disable differential mode (default mode: single-ended) */
<>	144:ef7eb2e8f9f7	2266	CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
<>	144:ef7eb2e8f9f7	2267	}
<>	144:ef7eb2e8f9f7	2268	else
<>	144:ef7eb2e8f9f7	2269	{
<>	144:ef7eb2e8f9f7	2270	/* Enable differential mode */
<>	144:ef7eb2e8f9f7	2271	SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
<>	144:ef7eb2e8f9f7	2272
<>	144:ef7eb2e8f9f7	2273	/* Sampling time configuration of channel ADC_IN+1 (negative input) */
<>	144:ef7eb2e8f9f7	2274	/* Clear the old sample time then set the new one for the selected */
<>	144:ef7eb2e8f9f7	2275	/* channel. */
<>	144:ef7eb2e8f9f7	2276	/* Starting from channel 9, SMPR2 register must be configured */
<>	144:ef7eb2e8f9f7	2277	if (sConfig->Channel >= ADC_CHANNEL_9)
<>	144:ef7eb2e8f9f7	2278	{
<>	144:ef7eb2e8f9f7	2279	ADC_SMPR2_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel+1);
<>	144:ef7eb2e8f9f7	2280	}
<>	144:ef7eb2e8f9f7	2281	else /* For channels 0 to 8, SMPR1 must be configured */
<>	144:ef7eb2e8f9f7	2282	{
<>	144:ef7eb2e8f9f7	2283	ADC_SMPR1_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel+1);
<>	144:ef7eb2e8f9f7	2284	}
<>	144:ef7eb2e8f9f7	2285	}
<>	144:ef7eb2e8f9f7	2286
<>	144:ef7eb2e8f9f7	2287
<>	144:ef7eb2e8f9f7	2288
<>	144:ef7eb2e8f9f7	2289	/* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */
<>	144:ef7eb2e8f9f7	2290	/* If internal channel selected, enable dedicated internal buffers and */
<>	144:ef7eb2e8f9f7	2291	/* paths. */
<>	144:ef7eb2e8f9f7	2292	/* Note: these internal measurement paths can be disabled using */
<>	144:ef7eb2e8f9f7	2293	/* HAL_ADC_DeInit(). */
<>	144:ef7eb2e8f9f7	2294
<>	144:ef7eb2e8f9f7	2295	/* Configuration of common ADC parameters */
<>	144:ef7eb2e8f9f7	2296	tmpADC_Common = ADC_COMMON_REGISTER(hadc);
<>	144:ef7eb2e8f9f7	2297
<>	144:ef7eb2e8f9f7	2298
<>	144:ef7eb2e8f9f7	2299	/* If the requested internal measurement path has already been enabled, */
<>	144:ef7eb2e8f9f7	2300	/* bypass the configuration processing. */
<>	144:ef7eb2e8f9f7	2301	if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
<>	144:ef7eb2e8f9f7	2302	(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) \|\|
<>	144:ef7eb2e8f9f7	2303	( (sConfig->Channel == ADC_CHANNEL_VBAT) &&
<>	144:ef7eb2e8f9f7	2304	(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) \|\|
<>	144:ef7eb2e8f9f7	2305	( (sConfig->Channel == ADC_CHANNEL_VREFINT) &&
<>	144:ef7eb2e8f9f7	2306	(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
<>	144:ef7eb2e8f9f7	2307	)
<>	144:ef7eb2e8f9f7	2308	{
<>	144:ef7eb2e8f9f7	2309	/* Configuration of common ADC parameters (continuation) */
<>	144:ef7eb2e8f9f7	2310
<>	144:ef7eb2e8f9f7	2311	/* Software is allowed to change common parameters only when all ADCs */
<>	144:ef7eb2e8f9f7	2312	/* of the common group are disabled. */
<>	144:ef7eb2e8f9f7	2313	if ((ADC_IS_ENABLE(hadc) == RESET) &&
<>	144:ef7eb2e8f9f7	2314	(ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
<>	144:ef7eb2e8f9f7	2315	{
<>	144:ef7eb2e8f9f7	2316	if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
<>	144:ef7eb2e8f9f7	2317	{
<>	144:ef7eb2e8f9f7	2318	if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
<>	144:ef7eb2e8f9f7	2319	{
<>	144:ef7eb2e8f9f7	2320	SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
<>	144:ef7eb2e8f9f7	2321
<>	144:ef7eb2e8f9f7	2322	/* Delay for temperature sensor stabilization time */
<>	144:ef7eb2e8f9f7	2323	/* Wait loop initialization and execution */
<>	144:ef7eb2e8f9f7	2324	/* Note: Variable divided by 2 to compensate partially */
<>	144:ef7eb2e8f9f7	2325	/* CPU processing cycles. */
<>	144:ef7eb2e8f9f7	2326	wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / (1000000 * 2)));
<>	144:ef7eb2e8f9f7	2327	while(wait_loop_index != 0)
<>	144:ef7eb2e8f9f7	2328	{
<>	144:ef7eb2e8f9f7	2329	wait_loop_index--;
<>	144:ef7eb2e8f9f7	2330	}
<>	144:ef7eb2e8f9f7	2331	}
<>	144:ef7eb2e8f9f7	2332	}
<>	144:ef7eb2e8f9f7	2333	else if (sConfig->Channel == ADC_CHANNEL_VBAT)
<>	144:ef7eb2e8f9f7	2334	{
<>	144:ef7eb2e8f9f7	2335	if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
<>	144:ef7eb2e8f9f7	2336	{
<>	144:ef7eb2e8f9f7	2337	SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
<>	144:ef7eb2e8f9f7	2338	}
<>	144:ef7eb2e8f9f7	2339	}
<>	144:ef7eb2e8f9f7	2340	else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
<>	144:ef7eb2e8f9f7	2341	{
<>	144:ef7eb2e8f9f7	2342	if (ADC_VREFINT_INSTANCE(hadc))
<>	144:ef7eb2e8f9f7	2343	{
<>	144:ef7eb2e8f9f7	2344	SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
<>	144:ef7eb2e8f9f7	2345	}
<>	144:ef7eb2e8f9f7	2346	}
<>	144:ef7eb2e8f9f7	2347	}
<>	144:ef7eb2e8f9f7	2348	/* If the requested internal measurement path has already been */
<>	144:ef7eb2e8f9f7	2349	/* enabled and other ADC of the common group are enabled, internal */
<>	144:ef7eb2e8f9f7	2350	/* measurement paths cannot be enabled. */
<>	144:ef7eb2e8f9f7	2351	else
<>	144:ef7eb2e8f9f7	2352	{
<>	144:ef7eb2e8f9f7	2353	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	2354	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<>	144:ef7eb2e8f9f7	2355
<>	144:ef7eb2e8f9f7	2356	tmp_status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	2357	}
<>	144:ef7eb2e8f9f7	2358	}
<>	144:ef7eb2e8f9f7	2359
<>	144:ef7eb2e8f9f7	2360	} /* if (ADC_IS_ENABLE(hadc) == RESET) */
<>	144:ef7eb2e8f9f7	2361
<>	144:ef7eb2e8f9f7	2362	} /* if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) */
<>	144:ef7eb2e8f9f7	2363
<>	144:ef7eb2e8f9f7	2364	/* If a conversion is on going on regular group, no update on regular */
<>	144:ef7eb2e8f9f7	2365	/* channel could be done on neither of the channel configuration structure */
<>	144:ef7eb2e8f9f7	2366	/* parameters. */
<>	144:ef7eb2e8f9f7	2367	else
<>	144:ef7eb2e8f9f7	2368	{
<>	144:ef7eb2e8f9f7	2369	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	2370	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<>	144:ef7eb2e8f9f7	2371
<>	144:ef7eb2e8f9f7	2372	tmp_status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	2373	}
<>	144:ef7eb2e8f9f7	2374
<>	144:ef7eb2e8f9f7	2375	/* Process unlocked */
<>	144:ef7eb2e8f9f7	2376	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	2377
<>	144:ef7eb2e8f9f7	2378	/* Return function status */
<>	144:ef7eb2e8f9f7	2379	return tmp_status;
<>	144:ef7eb2e8f9f7	2380	}
<>	144:ef7eb2e8f9f7	2381
<>	144:ef7eb2e8f9f7	2382
<>	144:ef7eb2e8f9f7	2383
<>	144:ef7eb2e8f9f7	2384	/**
<>	144:ef7eb2e8f9f7	2385	* @brief Configure the analog watchdog.
<>	144:ef7eb2e8f9f7	2386	* @note Possibility to update parameters on the fly:
<>	144:ef7eb2e8f9f7	2387	* This function initializes the selected analog watchdog, successive
<>	144:ef7eb2e8f9f7	2388	* calls to this function can be used to reconfigure some parameters
<>	144:ef7eb2e8f9f7	2389	* of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
<>	144:ef7eb2e8f9f7	2390	* the ADC, e.g. to set several channels to monitor simultaneously.
<>	144:ef7eb2e8f9f7	2391	* The setting of these parameters is conditioned to ADC state.
<>	144:ef7eb2e8f9f7	2392	* For parameters constraints, see comments of structure
<>	144:ef7eb2e8f9f7	2393	* "ADC_AnalogWDGConfTypeDef".
<>	144:ef7eb2e8f9f7	2394	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	2395	* @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
<>	144:ef7eb2e8f9f7	2396	* @retval HAL status
<>	144:ef7eb2e8f9f7	2397	*/
<>	144:ef7eb2e8f9f7	2398	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
<>	144:ef7eb2e8f9f7	2399	{
<>	144:ef7eb2e8f9f7	2400	HAL_StatusTypeDef tmp_status = HAL_OK;
<>	144:ef7eb2e8f9f7	2401
<>	144:ef7eb2e8f9f7	2402
<>	144:ef7eb2e8f9f7	2403	uint32_t tmpAWDHighThresholdShifted;
<>	144:ef7eb2e8f9f7	2404	uint32_t tmpAWDLowThresholdShifted;
<>	144:ef7eb2e8f9f7	2405
<>	144:ef7eb2e8f9f7	2406	uint32_t tmpADCFlagAWD2orAWD3;
<>	144:ef7eb2e8f9f7	2407	uint32_t tmpADCITAWD2orAWD3;
<>	144:ef7eb2e8f9f7	2408
<>	144:ef7eb2e8f9f7	2409	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2410	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	2411	assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
<>	144:ef7eb2e8f9f7	2412	assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
<>	144:ef7eb2e8f9f7	2413	assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
<>	144:ef7eb2e8f9f7	2414
<>	144:ef7eb2e8f9f7	2415	if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\|
<>	144:ef7eb2e8f9f7	2416	(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) \|\|
<>	144:ef7eb2e8f9f7	2417	(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) )
<>	144:ef7eb2e8f9f7	2418	{
<>	144:ef7eb2e8f9f7	2419	assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel));
<>	144:ef7eb2e8f9f7	2420	}
<>	144:ef7eb2e8f9f7	2421
<>	144:ef7eb2e8f9f7	2422
<>	144:ef7eb2e8f9f7	2423	/* Verify if threshold is within the selected ADC resolution */
<>	144:ef7eb2e8f9f7	2424	assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
<>	144:ef7eb2e8f9f7	2425	assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
<>	144:ef7eb2e8f9f7	2426
<>	144:ef7eb2e8f9f7	2427	/* Process locked */
<>	144:ef7eb2e8f9f7	2428	__HAL_LOCK(hadc);
<>	144:ef7eb2e8f9f7	2429
<>	144:ef7eb2e8f9f7	2430	/* Parameters update conditioned to ADC state: */
<>	144:ef7eb2e8f9f7	2431	/* Parameters that can be updated when ADC is disabled or enabled without */
<>	144:ef7eb2e8f9f7	2432	/* conversion on going on regular and injected groups: */
<>	144:ef7eb2e8f9f7	2433	/* - Analog watchdog channels */
<>	144:ef7eb2e8f9f7	2434	/* - Analog watchdog thresholds */
<>	144:ef7eb2e8f9f7	2435	if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
<>	144:ef7eb2e8f9f7	2436	{
<>	144:ef7eb2e8f9f7	2437
<>	144:ef7eb2e8f9f7	2438	/* Analog watchdogs configuration */
<>	144:ef7eb2e8f9f7	2439	if(AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
<>	144:ef7eb2e8f9f7	2440	{
<>	144:ef7eb2e8f9f7	2441	/* Configuration of analog watchdog: */
<>	144:ef7eb2e8f9f7	2442	/* - Set the analog watchdog enable mode: regular and/or injected */
<>	144:ef7eb2e8f9f7	2443	/* groups, one or overall group of channels. */
<>	144:ef7eb2e8f9f7	2444	/* - Set the Analog watchdog channel (is not used if watchdog */
<>	144:ef7eb2e8f9f7	2445	/* mode "all channels": ADC_CFGR_AWD1SGL=0). */
<>	144:ef7eb2e8f9f7	2446
<>	144:ef7eb2e8f9f7	2447	MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_WD_FIELDS,
<>	144:ef7eb2e8f9f7	2448	AnalogWDGConfig->WatchdogMode \| ADC_CFGR_SET_AWD1CH(AnalogWDGConfig->Channel) );
<>	144:ef7eb2e8f9f7	2449
<>	144:ef7eb2e8f9f7	2450	/* Shift the offset with respect to the selected ADC resolution: */
<>	144:ef7eb2e8f9f7	2451	/* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
<>	144:ef7eb2e8f9f7	2452	/* are set to 0 */
<>	144:ef7eb2e8f9f7	2453	tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
<>	144:ef7eb2e8f9f7	2454	tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
<>	144:ef7eb2e8f9f7	2455
<>	144:ef7eb2e8f9f7	2456	/* Set the high and low thresholds */
<>	144:ef7eb2e8f9f7	2457	MODIFY_REG(hadc->Instance->TR1, ADC_TR1_HT1 \| ADC_TR1_LT1,
<>	144:ef7eb2e8f9f7	2458	ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) \| tmpAWDLowThresholdShifted );
<>	144:ef7eb2e8f9f7	2459
<>	144:ef7eb2e8f9f7	2460	/* Clear the ADC Analog watchdog flag (in case left enabled by */
<>	144:ef7eb2e8f9f7	2461	/* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
<>	144:ef7eb2e8f9f7	2462	/* or HAL_ADC_PollForEvent(). */
<>	144:ef7eb2e8f9f7	2463	__HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD1);
<>	144:ef7eb2e8f9f7	2464
<>	144:ef7eb2e8f9f7	2465	/* Configure ADC Analog watchdog interrupt */
<>	144:ef7eb2e8f9f7	2466	if(AnalogWDGConfig->ITMode == ENABLE)
<>	144:ef7eb2e8f9f7	2467	{
<>	144:ef7eb2e8f9f7	2468	/* Enable the ADC Analog watchdog interrupt */
<>	144:ef7eb2e8f9f7	2469	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD1);
<>	144:ef7eb2e8f9f7	2470	}
<>	144:ef7eb2e8f9f7	2471	else
<>	144:ef7eb2e8f9f7	2472	{
<>	144:ef7eb2e8f9f7	2473	/* Disable the ADC Analog watchdog interrupt */
<>	144:ef7eb2e8f9f7	2474	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD1);
<>	144:ef7eb2e8f9f7	2475	}
<>	144:ef7eb2e8f9f7	2476
<>	144:ef7eb2e8f9f7	2477	/* Update state, clear previous result related to AWD1 */
<>	144:ef7eb2e8f9f7	2478	CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
<>	144:ef7eb2e8f9f7	2479	}
<>	144:ef7eb2e8f9f7	2480	/* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
<>	144:ef7eb2e8f9f7	2481	else
<>	144:ef7eb2e8f9f7	2482	{
<>	144:ef7eb2e8f9f7	2483	/* Shift the threshold with respect to the selected ADC resolution */
<>	144:ef7eb2e8f9f7	2484	/* have to be left-aligned on bit 7, the LSB (right bits) are set to 0 */
<>	144:ef7eb2e8f9f7	2485	tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
<>	144:ef7eb2e8f9f7	2486	tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
<>	144:ef7eb2e8f9f7	2487
<>	144:ef7eb2e8f9f7	2488	if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
<>	144:ef7eb2e8f9f7	2489	{
<>	144:ef7eb2e8f9f7	2490	/* Set the Analog watchdog channel or group of channels. This also */
<>	144:ef7eb2e8f9f7	2491	/* enables the watchdog. */
<>	144:ef7eb2e8f9f7	2492	/* Note: Conditional register reset, because several channels can be */
<>	144:ef7eb2e8f9f7	2493	/* set by successive calls of this function. */
<>	144:ef7eb2e8f9f7	2494	if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
<>	144:ef7eb2e8f9f7	2495	{
<>	144:ef7eb2e8f9f7	2496	SET_BIT(hadc->Instance->AWD2CR, ADC_CFGR_SET_AWD23CR(AnalogWDGConfig->Channel));
<>	144:ef7eb2e8f9f7	2497	}
<>	144:ef7eb2e8f9f7	2498	else
<>	144:ef7eb2e8f9f7	2499	{
<>	144:ef7eb2e8f9f7	2500	CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
<>	144:ef7eb2e8f9f7	2501	}
<>	144:ef7eb2e8f9f7	2502
<>	144:ef7eb2e8f9f7	2503	/* Set the high and low thresholds */
<>	144:ef7eb2e8f9f7	2504	MODIFY_REG(hadc->Instance->TR2, ADC_TR2_HT2 \| ADC_TR2_LT2,
<>	144:ef7eb2e8f9f7	2505	ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) \| tmpAWDLowThresholdShifted );
<>	144:ef7eb2e8f9f7	2506
<>	144:ef7eb2e8f9f7	2507	/* Set temporary variable to flag and IT of AWD2 or AWD3 for further */
<>	144:ef7eb2e8f9f7	2508	/* settings. */
<>	144:ef7eb2e8f9f7	2509	tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD2;
<>	144:ef7eb2e8f9f7	2510	tmpADCITAWD2orAWD3 = ADC_IT_AWD2;
<>	144:ef7eb2e8f9f7	2511
<>	144:ef7eb2e8f9f7	2512	/* Update state, clear previous result related to AWD2 */
<>	144:ef7eb2e8f9f7	2513	CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
<>	144:ef7eb2e8f9f7	2514	}
<>	144:ef7eb2e8f9f7	2515	/* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
<>	144:ef7eb2e8f9f7	2516	else
<>	144:ef7eb2e8f9f7	2517	{
<>	144:ef7eb2e8f9f7	2518	/* Set the Analog watchdog channel or group of channels. This also */
<>	144:ef7eb2e8f9f7	2519	/* enables the watchdog. */
<>	144:ef7eb2e8f9f7	2520	/* Note: Conditional register reset, because several channels can be */
<>	144:ef7eb2e8f9f7	2521	/* set by successive calls of this function. */
<>	144:ef7eb2e8f9f7	2522	if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
<>	144:ef7eb2e8f9f7	2523	{
<>	144:ef7eb2e8f9f7	2524	SET_BIT(hadc->Instance->AWD3CR, ADC_CFGR_SET_AWD23CR(AnalogWDGConfig->Channel));
<>	144:ef7eb2e8f9f7	2525	}
<>	144:ef7eb2e8f9f7	2526	else
<>	144:ef7eb2e8f9f7	2527	{
<>	144:ef7eb2e8f9f7	2528	CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
<>	144:ef7eb2e8f9f7	2529	}
<>	144:ef7eb2e8f9f7	2530
<>	144:ef7eb2e8f9f7	2531	/* Set the high and low thresholds */
<>	144:ef7eb2e8f9f7	2532	MODIFY_REG(hadc->Instance->TR3, ADC_TR3_HT3 \| ADC_TR3_LT3,
<>	144:ef7eb2e8f9f7	2533	ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) \| tmpAWDLowThresholdShifted );
<>	144:ef7eb2e8f9f7	2534
<>	144:ef7eb2e8f9f7	2535	/* Set temporary variable to flag and IT of AWD2 or AWD3 for further */
<>	144:ef7eb2e8f9f7	2536	/* settings. */
<>	144:ef7eb2e8f9f7	2537	tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD3;
<>	144:ef7eb2e8f9f7	2538	tmpADCITAWD2orAWD3 = ADC_IT_AWD3;
<>	144:ef7eb2e8f9f7	2539
<>	144:ef7eb2e8f9f7	2540	/* Update state, clear previous result related to AWD3 */
<>	144:ef7eb2e8f9f7	2541	CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
<>	144:ef7eb2e8f9f7	2542	}
<>	144:ef7eb2e8f9f7	2543
<>	144:ef7eb2e8f9f7	2544	/* Clear the ADC Analog watchdog flag (in case left enabled by */
<>	144:ef7eb2e8f9f7	2545	/* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
<>	144:ef7eb2e8f9f7	2546	/* or HAL_ADC_PollForEvent(). */
<>	144:ef7eb2e8f9f7	2547	__HAL_ADC_CLEAR_FLAG(hadc, tmpADCFlagAWD2orAWD3);
<>	144:ef7eb2e8f9f7	2548
<>	144:ef7eb2e8f9f7	2549	/* Configure ADC Analog watchdog interrupt */
<>	144:ef7eb2e8f9f7	2550	if(AnalogWDGConfig->ITMode == ENABLE)
<>	144:ef7eb2e8f9f7	2551	{
<>	144:ef7eb2e8f9f7	2552	__HAL_ADC_ENABLE_IT(hadc, tmpADCITAWD2orAWD3);
<>	144:ef7eb2e8f9f7	2553	}
<>	144:ef7eb2e8f9f7	2554	else
<>	144:ef7eb2e8f9f7	2555	{
<>	144:ef7eb2e8f9f7	2556	__HAL_ADC_DISABLE_IT(hadc, tmpADCITAWD2orAWD3);
<>	144:ef7eb2e8f9f7	2557	}
<>	144:ef7eb2e8f9f7	2558	}
<>	144:ef7eb2e8f9f7	2559
<>	144:ef7eb2e8f9f7	2560	}
<>	144:ef7eb2e8f9f7	2561	/* If a conversion is on going on regular or injected groups, no update */
<>	144:ef7eb2e8f9f7	2562	/* could be done on neither of the AWD configuration structure parameters. */
<>	144:ef7eb2e8f9f7	2563	else
<>	144:ef7eb2e8f9f7	2564	{
<>	144:ef7eb2e8f9f7	2565	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	2566	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<>	144:ef7eb2e8f9f7	2567
<>	144:ef7eb2e8f9f7	2568	tmp_status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	2569	}
<>	144:ef7eb2e8f9f7	2570
<>	144:ef7eb2e8f9f7	2571
<>	144:ef7eb2e8f9f7	2572	/* Process unlocked */
<>	144:ef7eb2e8f9f7	2573	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	2574
<>	144:ef7eb2e8f9f7	2575
<>	144:ef7eb2e8f9f7	2576	/* Return function status */
<>	144:ef7eb2e8f9f7	2577	return tmp_status;
<>	144:ef7eb2e8f9f7	2578	}
<>	144:ef7eb2e8f9f7	2579
<>	144:ef7eb2e8f9f7	2580
<>	144:ef7eb2e8f9f7	2581	/**
<>	144:ef7eb2e8f9f7	2582	* @}
<>	144:ef7eb2e8f9f7	2583	*/
<>	144:ef7eb2e8f9f7	2584
<>	144:ef7eb2e8f9f7	2585	/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
<>	144:ef7eb2e8f9f7	2586	* @brief ADC Peripheral State functions
<>	144:ef7eb2e8f9f7	2587	*
<>	144:ef7eb2e8f9f7	2588	@verbatim
<>	144:ef7eb2e8f9f7	2589	===============================================================================
<>	144:ef7eb2e8f9f7	2590	##### Peripheral state and errors functions #####
<>	144:ef7eb2e8f9f7	2591	===============================================================================
<>	144:ef7eb2e8f9f7	2592	[..]
<>	144:ef7eb2e8f9f7	2593	This subsection provides functions to get in run-time the status of the
<>	144:ef7eb2e8f9f7	2594	peripheral.
<>	144:ef7eb2e8f9f7	2595	(+) Check the ADC state
<>	144:ef7eb2e8f9f7	2596	(+) Check the ADC error code
<>	144:ef7eb2e8f9f7	2597
<>	144:ef7eb2e8f9f7	2598	@endverbatim
<>	144:ef7eb2e8f9f7	2599	* @{
<>	144:ef7eb2e8f9f7	2600	*/
<>	144:ef7eb2e8f9f7	2601
<>	144:ef7eb2e8f9f7	2602	/**
<>	144:ef7eb2e8f9f7	2603	* @brief Return the ADC handle state.
<>	144:ef7eb2e8f9f7	2604	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	2605	* @retval HAL state (uint32_t bit-map)
<>	144:ef7eb2e8f9f7	2606	*/
<>	144:ef7eb2e8f9f7	2607	uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	2608	{
<>	144:ef7eb2e8f9f7	2609	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2610	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	2611
<>	144:ef7eb2e8f9f7	2612	/* Return ADC handle state */
<>	144:ef7eb2e8f9f7	2613	return hadc->State;
<>	144:ef7eb2e8f9f7	2614	}
<>	144:ef7eb2e8f9f7	2615
<>	144:ef7eb2e8f9f7	2616
<>	144:ef7eb2e8f9f7	2617	/**
<>	144:ef7eb2e8f9f7	2618	* @brief Return the ADC error code.
<>	144:ef7eb2e8f9f7	2619	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	2620	* @retval ADC Error Code (uint32_t bit-map)
<>	144:ef7eb2e8f9f7	2621	*/
<>	144:ef7eb2e8f9f7	2622	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
<>	144:ef7eb2e8f9f7	2623	{
<>	144:ef7eb2e8f9f7	2624	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2625	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	2626
<>	144:ef7eb2e8f9f7	2627	return hadc->ErrorCode;
<>	144:ef7eb2e8f9f7	2628	}
<>	144:ef7eb2e8f9f7	2629
<>	144:ef7eb2e8f9f7	2630	/**
<>	144:ef7eb2e8f9f7	2631	* @}
<>	144:ef7eb2e8f9f7	2632	*/
<>	144:ef7eb2e8f9f7	2633
<>	144:ef7eb2e8f9f7	2634	/**
<>	144:ef7eb2e8f9f7	2635	* @}
<>	144:ef7eb2e8f9f7	2636	*/
<>	144:ef7eb2e8f9f7	2637
<>	144:ef7eb2e8f9f7	2638
<>	144:ef7eb2e8f9f7	2639
<>	144:ef7eb2e8f9f7	2640	/** @defgroup ADC_Private_Functions ADC Private Functions
<>	144:ef7eb2e8f9f7	2641	* @{
<>	144:ef7eb2e8f9f7	2642	*/
<>	144:ef7eb2e8f9f7	2643
<>	144:ef7eb2e8f9f7	2644	/**
<>	144:ef7eb2e8f9f7	2645	* @brief Stop ADC conversion.
<>	144:ef7eb2e8f9f7	2646	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	2647	* @param ConversionGroup: ADC group regular and/or injected.
<>	144:ef7eb2e8f9f7	2648	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2649	* @arg @ref ADC_REGULAR_GROUP ADC regular conversion type.
<>	144:ef7eb2e8f9f7	2650	* @arg @ref ADC_INJECTED_GROUP ADC injected conversion type.
<>	144:ef7eb2e8f9f7	2651	* @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type.
<>	144:ef7eb2e8f9f7	2652	* @retval HAL status.
<>	144:ef7eb2e8f9f7	2653	*/
<>	144:ef7eb2e8f9f7	2654	HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup)
<>	144:ef7eb2e8f9f7	2655	{
<>	144:ef7eb2e8f9f7	2656	uint32_t tmp_ADC_CR_ADSTART_JADSTART = 0;
<>	144:ef7eb2e8f9f7	2657	uint32_t tickstart = 0;
<>	144:ef7eb2e8f9f7	2658	uint32_t Conversion_Timeout_CPU_cycles = 0;
<>	144:ef7eb2e8f9f7	2659
<>	144:ef7eb2e8f9f7	2660	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2661	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	2662	assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
<>	144:ef7eb2e8f9f7	2663
<>	144:ef7eb2e8f9f7	2664	/* Verification if ADC is not already stopped (on regular and injected */
<>	144:ef7eb2e8f9f7	2665	/* groups) to bypass this function if not needed. */
<>	144:ef7eb2e8f9f7	2666	if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc))
<>	144:ef7eb2e8f9f7	2667	{
<>	144:ef7eb2e8f9f7	2668	/* Particular case of continuous auto-injection mode combined with */
<>	144:ef7eb2e8f9f7	2669	/* auto-delay mode. */
<>	144:ef7eb2e8f9f7	2670	/* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
<>	144:ef7eb2e8f9f7	2671	/* injected group stop ADC_CR_JADSTP). */
<>	144:ef7eb2e8f9f7	2672	/* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */
<>	144:ef7eb2e8f9f7	2673	/* (see reference manual). */
<>	144:ef7eb2e8f9f7	2674	if ((HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
<>	144:ef7eb2e8f9f7	2675	&& (hadc->Init.ContinuousConvMode==ENABLE)
<>	144:ef7eb2e8f9f7	2676	&& (hadc->Init.LowPowerAutoWait==ENABLE))
<>	144:ef7eb2e8f9f7	2677	{
<>	144:ef7eb2e8f9f7	2678	/* Use stop of regular group */
<>	144:ef7eb2e8f9f7	2679	ConversionGroup = ADC_REGULAR_GROUP;
<>	144:ef7eb2e8f9f7	2680
<>	144:ef7eb2e8f9f7	2681	/* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
<>	144:ef7eb2e8f9f7	2682	while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == RESET)
<>	144:ef7eb2e8f9f7	2683	{
<>	144:ef7eb2e8f9f7	2684	if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES *4))
<>	144:ef7eb2e8f9f7	2685	{
<>	144:ef7eb2e8f9f7	2686	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	2687	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2688
<>	144:ef7eb2e8f9f7	2689	/* Set ADC error code to ADC IP internal error */
<>	144:ef7eb2e8f9f7	2690	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2691
<>	144:ef7eb2e8f9f7	2692	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2693	}
<>	144:ef7eb2e8f9f7	2694	Conversion_Timeout_CPU_cycles ++;
<>	144:ef7eb2e8f9f7	2695	}
<>	144:ef7eb2e8f9f7	2696
<>	144:ef7eb2e8f9f7	2697	/* Clear JEOS */
<>	144:ef7eb2e8f9f7	2698	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
<>	144:ef7eb2e8f9f7	2699	}
<>	144:ef7eb2e8f9f7	2700
<>	144:ef7eb2e8f9f7	2701	/* Stop potential conversion on going on regular group */
<>	144:ef7eb2e8f9f7	2702	if (ConversionGroup != ADC_INJECTED_GROUP)
<>	144:ef7eb2e8f9f7	2703	{
<>	144:ef7eb2e8f9f7	2704	/* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
<>	144:ef7eb2e8f9f7	2705	if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) &&
<>	144:ef7eb2e8f9f7	2706	HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
<>	144:ef7eb2e8f9f7	2707	{
<>	144:ef7eb2e8f9f7	2708	/* Stop conversions on regular group */
<>	144:ef7eb2e8f9f7	2709	SET_BIT(hadc->Instance->CR, ADC_CR_ADSTP);
<>	144:ef7eb2e8f9f7	2710	}
<>	144:ef7eb2e8f9f7	2711	}
<>	144:ef7eb2e8f9f7	2712
<>	144:ef7eb2e8f9f7	2713	/* Stop potential conversion on going on injected group */
<>	144:ef7eb2e8f9f7	2714	if (ConversionGroup != ADC_REGULAR_GROUP)
<>	144:ef7eb2e8f9f7	2715	{
<>	144:ef7eb2e8f9f7	2716	/* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
<>	144:ef7eb2e8f9f7	2717	if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_JADSTART) &&
<>	144:ef7eb2e8f9f7	2718	HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
<>	144:ef7eb2e8f9f7	2719	{
<>	144:ef7eb2e8f9f7	2720	/* Stop conversions on injected group */
<>	144:ef7eb2e8f9f7	2721	SET_BIT(hadc->Instance->CR, ADC_CR_JADSTP);
<>	144:ef7eb2e8f9f7	2722	}
<>	144:ef7eb2e8f9f7	2723	}
<>	144:ef7eb2e8f9f7	2724
<>	144:ef7eb2e8f9f7	2725	/* Selection of start and stop bits with respect to the regular or injected group */
<>	144:ef7eb2e8f9f7	2726	switch(ConversionGroup)
<>	144:ef7eb2e8f9f7	2727	{
<>	144:ef7eb2e8f9f7	2728	case ADC_REGULAR_INJECTED_GROUP:
<>	144:ef7eb2e8f9f7	2729	tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART \| ADC_CR_JADSTART);
<>	144:ef7eb2e8f9f7	2730	break;
<>	144:ef7eb2e8f9f7	2731	case ADC_INJECTED_GROUP:
<>	144:ef7eb2e8f9f7	2732	tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
<>	144:ef7eb2e8f9f7	2733	break;
<>	144:ef7eb2e8f9f7	2734	/* Case ADC_REGULAR_GROUP only*/
<>	144:ef7eb2e8f9f7	2735	default:
<>	144:ef7eb2e8f9f7	2736	tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
<>	144:ef7eb2e8f9f7	2737	break;
<>	144:ef7eb2e8f9f7	2738	}
<>	144:ef7eb2e8f9f7	2739
<>	144:ef7eb2e8f9f7	2740	/* Wait for conversion effectively stopped */
<>	144:ef7eb2e8f9f7	2741
<>	144:ef7eb2e8f9f7	2742
<>	144:ef7eb2e8f9f7	2743	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2744
<>	144:ef7eb2e8f9f7	2745	while((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != RESET)
<>	144:ef7eb2e8f9f7	2746	{
<>	144:ef7eb2e8f9f7	2747	if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
<>	144:ef7eb2e8f9f7	2748	{
<>	144:ef7eb2e8f9f7	2749	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	2750	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2751
<>	144:ef7eb2e8f9f7	2752	/* Set ADC error code to ADC IP internal error */
<>	144:ef7eb2e8f9f7	2753	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2754
<>	144:ef7eb2e8f9f7	2755	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2756	}
<>	144:ef7eb2e8f9f7	2757	}
<>	144:ef7eb2e8f9f7	2758
<>	144:ef7eb2e8f9f7	2759	} /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc)) */
<>	144:ef7eb2e8f9f7	2760
<>	144:ef7eb2e8f9f7	2761	/* Return HAL status */
<>	144:ef7eb2e8f9f7	2762	return HAL_OK;
<>	144:ef7eb2e8f9f7	2763	}
<>	144:ef7eb2e8f9f7	2764
<>	144:ef7eb2e8f9f7	2765
<>	144:ef7eb2e8f9f7	2766
<>	144:ef7eb2e8f9f7	2767	/**
<>	144:ef7eb2e8f9f7	2768	* @brief Enable the selected ADC.
<>	144:ef7eb2e8f9f7	2769	* @note Prerequisite condition to use this function: ADC must be disabled
<>	144:ef7eb2e8f9f7	2770	* and voltage regulator must be enabled (done into HAL_ADC_Init()).
<>	144:ef7eb2e8f9f7	2771	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	2772	* @retval HAL status.
<>	144:ef7eb2e8f9f7	2773	*/
<>	144:ef7eb2e8f9f7	2774	HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	2775	{
<>	144:ef7eb2e8f9f7	2776	uint32_t tickstart = 0;
<>	144:ef7eb2e8f9f7	2777
<>	144:ef7eb2e8f9f7	2778	/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
<>	144:ef7eb2e8f9f7	2779	/* enabling phase not yet completed: flag ADC ready not set yet). */
<>	144:ef7eb2e8f9f7	2780	/* Timeout implemented not to be stuck if ADC cannot be enabled (possible */
<>	144:ef7eb2e8f9f7	2781	/* causes: ADC clock not running, ...). */
<>	144:ef7eb2e8f9f7	2782	if (ADC_IS_ENABLE(hadc) == RESET)
<>	144:ef7eb2e8f9f7	2783	{
<>	144:ef7eb2e8f9f7	2784	/* Check if conditions to enable the ADC are fulfilled */
<>	144:ef7eb2e8f9f7	2785	if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
<>	144:ef7eb2e8f9f7	2786	{
<>	144:ef7eb2e8f9f7	2787	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	2788	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2789
<>	144:ef7eb2e8f9f7	2790	/* Set ADC error code to ADC IP internal error */
<>	144:ef7eb2e8f9f7	2791	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2792
<>	144:ef7eb2e8f9f7	2793	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2794	}
<>	144:ef7eb2e8f9f7	2795
<>	144:ef7eb2e8f9f7	2796	/* Enable the ADC peripheral */
<>	144:ef7eb2e8f9f7	2797	ADC_ENABLE(hadc);
<>	144:ef7eb2e8f9f7	2798
<>	144:ef7eb2e8f9f7	2799
<>	144:ef7eb2e8f9f7	2800	/* Wait for ADC effectively enabled */
<>	144:ef7eb2e8f9f7	2801	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2802
<>	144:ef7eb2e8f9f7	2803	while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
<>	144:ef7eb2e8f9f7	2804	{
<>	144:ef7eb2e8f9f7	2805	/* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
<>	144:ef7eb2e8f9f7	2806	has been cleared (after a calibration), ADEN bit is reset by the
<>	144:ef7eb2e8f9f7	2807	calibration logic.
<>	144:ef7eb2e8f9f7	2808	The workaround is to continue setting ADEN until ADRDY is becomes 1.
<>	144:ef7eb2e8f9f7	2809	Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
<>	144:ef7eb2e8f9f7	2810	4 ADC clock cycle duration */
<>	144:ef7eb2e8f9f7	2811	ADC_ENABLE(hadc);
<>	144:ef7eb2e8f9f7	2812
<>	144:ef7eb2e8f9f7	2813	if((HAL_GetTick()-tickstart) > ADC_ENABLE_TIMEOUT)
<>	144:ef7eb2e8f9f7	2814	{
<>	144:ef7eb2e8f9f7	2815	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	2816	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2817
<>	144:ef7eb2e8f9f7	2818	/* Set ADC error code to ADC IP internal error */
<>	144:ef7eb2e8f9f7	2819	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2820
<>	144:ef7eb2e8f9f7	2821	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2822	}
<>	144:ef7eb2e8f9f7	2823	}
<>	144:ef7eb2e8f9f7	2824	}
<>	144:ef7eb2e8f9f7	2825
<>	144:ef7eb2e8f9f7	2826	/* Return HAL status */
<>	144:ef7eb2e8f9f7	2827	return HAL_OK;
<>	144:ef7eb2e8f9f7	2828	}
<>	144:ef7eb2e8f9f7	2829
<>	144:ef7eb2e8f9f7	2830	/**
<>	144:ef7eb2e8f9f7	2831	* @brief Disable the selected ADC.
<>	144:ef7eb2e8f9f7	2832	* @note Prerequisite condition to use this function: ADC conversions must be
<>	144:ef7eb2e8f9f7	2833	* stopped.
<>	144:ef7eb2e8f9f7	2834	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	2835	* @retval HAL status.
<>	144:ef7eb2e8f9f7	2836	*/
<>	144:ef7eb2e8f9f7	2837	HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	2838	{
<>	144:ef7eb2e8f9f7	2839	uint32_t tickstart = 0;
<>	144:ef7eb2e8f9f7	2840
<>	144:ef7eb2e8f9f7	2841	/* Verification if ADC is not already disabled: */
<>	144:ef7eb2e8f9f7	2842	/* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
<>	144:ef7eb2e8f9f7	2843	/* disabled. */
<>	144:ef7eb2e8f9f7	2844	if (ADC_IS_ENABLE(hadc) != RESET )
<>	144:ef7eb2e8f9f7	2845	{
<>	144:ef7eb2e8f9f7	2846	/* Check if conditions to disable the ADC are fulfilled */
<>	144:ef7eb2e8f9f7	2847	if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
<>	144:ef7eb2e8f9f7	2848	{
<>	144:ef7eb2e8f9f7	2849	/* Disable the ADC peripheral */
<>	144:ef7eb2e8f9f7	2850	ADC_DISABLE(hadc);
<>	144:ef7eb2e8f9f7	2851	}
<>	144:ef7eb2e8f9f7	2852	else
<>	144:ef7eb2e8f9f7	2853	{
<>	144:ef7eb2e8f9f7	2854	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	2855	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2856
<>	144:ef7eb2e8f9f7	2857	/* Set ADC error code to ADC IP internal error */
<>	144:ef7eb2e8f9f7	2858	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2859
<>	144:ef7eb2e8f9f7	2860	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2861	}
<>	144:ef7eb2e8f9f7	2862
<>	144:ef7eb2e8f9f7	2863	/* Wait for ADC effectively disabled */
<>	144:ef7eb2e8f9f7	2864	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2865
<>	144:ef7eb2e8f9f7	2866	while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
<>	144:ef7eb2e8f9f7	2867	{
<>	144:ef7eb2e8f9f7	2868	if((HAL_GetTick()-tickstart) > ADC_DISABLE_TIMEOUT)
<>	144:ef7eb2e8f9f7	2869	{
<>	144:ef7eb2e8f9f7	2870	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	2871	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2872
<>	144:ef7eb2e8f9f7	2873	/* Set ADC error code to ADC IP internal error */
<>	144:ef7eb2e8f9f7	2874	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2875
<>	144:ef7eb2e8f9f7	2876	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2877	}
<>	144:ef7eb2e8f9f7	2878	}
<>	144:ef7eb2e8f9f7	2879	}
<>	144:ef7eb2e8f9f7	2880
<>	144:ef7eb2e8f9f7	2881	/* Return HAL status */
<>	144:ef7eb2e8f9f7	2882	return HAL_OK;
<>	144:ef7eb2e8f9f7	2883	}
<>	144:ef7eb2e8f9f7	2884
<>	144:ef7eb2e8f9f7	2885
<>	144:ef7eb2e8f9f7	2886	/**
<>	144:ef7eb2e8f9f7	2887	* @brief DMA transfer complete callback.
<>	144:ef7eb2e8f9f7	2888	* @param hdma: pointer to DMA handle.
<>	144:ef7eb2e8f9f7	2889	* @retval None
<>	144:ef7eb2e8f9f7	2890	*/
<>	144:ef7eb2e8f9f7	2891	void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2892	{
<>	144:ef7eb2e8f9f7	2893	/* Retrieve ADC handle corresponding to current DMA handle */
<>	144:ef7eb2e8f9f7	2894	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	2895
<>	144:ef7eb2e8f9f7	2896	/* Update state machine on conversion status if not in error state */
<>	144:ef7eb2e8f9f7	2897	if (HAL_IS_BIT_CLR(hadc->State, (HAL_ADC_STATE_ERROR_INTERNAL\|HAL_ADC_STATE_ERROR_DMA)))
<>	144:ef7eb2e8f9f7	2898	{
<>	144:ef7eb2e8f9f7	2899	/* Update ADC state machine */
<>	144:ef7eb2e8f9f7	2900	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
<>	144:ef7eb2e8f9f7	2901	/* Is it the end of the regular sequence ? */
<>	144:ef7eb2e8f9f7	2902	if (HAL_IS_BIT_SET(hadc->Instance->ISR, ADC_FLAG_EOS))
<>	144:ef7eb2e8f9f7	2903	{
<>	144:ef7eb2e8f9f7	2904	/* Are conversions software-triggered ? */
<>	144:ef7eb2e8f9f7	2905	if(ADC_IS_SOFTWARE_START_REGULAR(hadc))
<>	144:ef7eb2e8f9f7	2906	{
<>	144:ef7eb2e8f9f7	2907	/* Is CONT bit set ? */
<>	144:ef7eb2e8f9f7	2908	if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == RESET)
<>	144:ef7eb2e8f9f7	2909	{
<>	144:ef7eb2e8f9f7	2910	/* CONT bit is not set, no more conversions expected */
<>	144:ef7eb2e8f9f7	2911	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<>	144:ef7eb2e8f9f7	2912	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<>	144:ef7eb2e8f9f7	2913	{
<>	144:ef7eb2e8f9f7	2914	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<>	144:ef7eb2e8f9f7	2915	}
<>	144:ef7eb2e8f9f7	2916	}
<>	144:ef7eb2e8f9f7	2917	}
<>	144:ef7eb2e8f9f7	2918	}
<>	144:ef7eb2e8f9f7	2919	else
<>	144:ef7eb2e8f9f7	2920	{
<>	144:ef7eb2e8f9f7	2921	/* DMA End of Transfer interrupt was triggered but conversions sequence
<>	144:ef7eb2e8f9f7	2922	is not over. If DMACFG is set to 0, conversions are stopped. */
<>	144:ef7eb2e8f9f7	2923	if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == RESET)
<>	144:ef7eb2e8f9f7	2924	{
<>	144:ef7eb2e8f9f7	2925	/* DMACFG bit is not set, conversions are stopped. */
<>	144:ef7eb2e8f9f7	2926	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<>	144:ef7eb2e8f9f7	2927	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<>	144:ef7eb2e8f9f7	2928	{
<>	144:ef7eb2e8f9f7	2929	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<>	144:ef7eb2e8f9f7	2930	}
<>	144:ef7eb2e8f9f7	2931	}
<>	144:ef7eb2e8f9f7	2932	}
<>	144:ef7eb2e8f9f7	2933
<>	144:ef7eb2e8f9f7	2934	/* Conversion complete callback */
<>	144:ef7eb2e8f9f7	2935	HAL_ADC_ConvCpltCallback(hadc);
<>	144:ef7eb2e8f9f7	2936	}
<>	144:ef7eb2e8f9f7	2937	else /* DMA or internal error occurred (or both) */
<>	144:ef7eb2e8f9f7	2938	{
<>	144:ef7eb2e8f9f7	2939	/* In case of internal error, */
<>	144:ef7eb2e8f9f7	2940	if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
<>	144:ef7eb2e8f9f7	2941	{
<>	144:ef7eb2e8f9f7	2942	/* call Error Callback function */
<>	144:ef7eb2e8f9f7	2943	HAL_ADC_ErrorCallback(hadc);
<>	144:ef7eb2e8f9f7	2944	}
<>	144:ef7eb2e8f9f7	2945
<>	144:ef7eb2e8f9f7	2946	}
<>	144:ef7eb2e8f9f7	2947
<>	144:ef7eb2e8f9f7	2948
<>	144:ef7eb2e8f9f7	2949	}
<>	144:ef7eb2e8f9f7	2950
<>	144:ef7eb2e8f9f7	2951	/**
<>	144:ef7eb2e8f9f7	2952	* @brief DMA half transfer complete callback.
<>	144:ef7eb2e8f9f7	2953	* @param hdma: pointer to DMA handle.
<>	144:ef7eb2e8f9f7	2954	* @retval None
<>	144:ef7eb2e8f9f7	2955	*/
<>	144:ef7eb2e8f9f7	2956	void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2957	{
<>	144:ef7eb2e8f9f7	2958	/* Retrieve ADC handle corresponding to current DMA handle */
<>	144:ef7eb2e8f9f7	2959	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	2960
<>	144:ef7eb2e8f9f7	2961	/* Half conversion callback */
<>	144:ef7eb2e8f9f7	2962	HAL_ADC_ConvHalfCpltCallback(hadc);
<>	144:ef7eb2e8f9f7	2963	}
<>	144:ef7eb2e8f9f7	2964
<>	144:ef7eb2e8f9f7	2965	/**
<>	144:ef7eb2e8f9f7	2966	* @brief DMA error callback.
<>	144:ef7eb2e8f9f7	2967	* @param hdma: pointer to DMA handle.
<>	144:ef7eb2e8f9f7	2968	* @retval None
<>	144:ef7eb2e8f9f7	2969	*/
<>	144:ef7eb2e8f9f7	2970	void ADC_DMAError(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2971	{
<>	144:ef7eb2e8f9f7	2972	/* Retrieve ADC handle corresponding to current DMA handle */
<>	144:ef7eb2e8f9f7	2973	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	2974
<>	144:ef7eb2e8f9f7	2975	/* Change ADC state */
<>	144:ef7eb2e8f9f7	2976	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
<>	144:ef7eb2e8f9f7	2977
<>	144:ef7eb2e8f9f7	2978	/* Set ADC error code to DMA error */
<>	144:ef7eb2e8f9f7	2979	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
<>	144:ef7eb2e8f9f7	2980
<>	144:ef7eb2e8f9f7	2981	/* Error callback */
<>	144:ef7eb2e8f9f7	2982	HAL_ADC_ErrorCallback(hadc);
<>	144:ef7eb2e8f9f7	2983	}
<>	144:ef7eb2e8f9f7	2984
<>	144:ef7eb2e8f9f7	2985
<>	144:ef7eb2e8f9f7	2986	/**
<>	144:ef7eb2e8f9f7	2987	* @}
<>	144:ef7eb2e8f9f7	2988	*/
<>	144:ef7eb2e8f9f7	2989
<>	144:ef7eb2e8f9f7	2990
<>	144:ef7eb2e8f9f7	2991	#endif /* HAL_ADC_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	2992	/**
<>	144:ef7eb2e8f9f7	2993	* @}
<>	144:ef7eb2e8f9f7	2994	*/
<>	144:ef7eb2e8f9f7	2995
<>	144:ef7eb2e8f9f7	2996	/**
<>	144:ef7eb2e8f9f7	2997	* @}
<>	144:ef7eb2e8f9f7	2998	*/
<>	144:ef7eb2e8f9f7	2999
<>	144:ef7eb2e8f9f7	3000	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	02 Jan 2017
Imports:	3
Forks:	0
Commits:	155
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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.c@149:156823d33999, 2016-10-28 (annotated)

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