shao ziyang / mbed-dev

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Dependents:   SensorTileTest

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targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_adc_ex.c@154:1375a99fb16d, 2017-01-02 (annotated)

Committer:
shaoziyang
Date:
Mon Jan 02 15:52:04 2017 +0000
Revision:
154:1375a99fb16d
Parent:
149:156823d33999 
Mbed for ST SensorTile kit, fixed GPIOG bug, add PORTG support.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f3xx_hal_adc_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.3.0
<> 144:ef7eb2e8f9f7 6 * @date 01-July-2016
<> 144:ef7eb2e8f9f7 7 * @brief This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 8 * functionalities of the Analog to Digital Convertor (ADC)
<> 144:ef7eb2e8f9f7 9 * peripheral:
<> 144:ef7eb2e8f9f7 10 * + Operation functions
<> 144:ef7eb2e8f9f7 11 * ++ Start, stop, get result of conversions of injected
<> 144:ef7eb2e8f9f7 12 * group, using 2 possible modes: polling, interruption.
<> 144:ef7eb2e8f9f7 13 * ++ Multimode feature (available on devices with 2 ADCs or more)
<> 144:ef7eb2e8f9f7 14 * ++ Calibration (ADC automatic self-calibration)
<> 144:ef7eb2e8f9f7 15 * + Control functions
<> 144:ef7eb2e8f9f7 16 * ++ Channels configuration on injected group
<> 144:ef7eb2e8f9f7 17 * Other functions (generic functions) are available in file
<> 144:ef7eb2e8f9f7 18 * "stm32f3xx_hal_adc.c".
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 @verbatim
<> 144:ef7eb2e8f9f7 21 [..]
<> 144:ef7eb2e8f9f7 22 (@) Sections "ADC peripheral features" and "How to use this driver" are
<> 144:ef7eb2e8f9f7 23 available in file of generic functions "stm32f3xx_hal_adc.c".
<> 144:ef7eb2e8f9f7 24 [..]
<> 144:ef7eb2e8f9f7 25 @endverbatim
<> 144:ef7eb2e8f9f7 26 ******************************************************************************
<> 144:ef7eb2e8f9f7 27 * @attention
<> 144:ef7eb2e8f9f7 28 *
<> 144:ef7eb2e8f9f7 29 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 30 *
<> 144:ef7eb2e8f9f7 31 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 32 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 33 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 34 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 35 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 36 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 37 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 38 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 39 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 40 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 41 *
<> 144:ef7eb2e8f9f7 42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 43 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 45 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 46 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 47 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 48 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 49 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 50 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 51 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 52 *
<> 144:ef7eb2e8f9f7 53 ******************************************************************************
<> 144:ef7eb2e8f9f7 54 */
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 57 #include "stm32f3xx_hal.h"
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /** @addtogroup STM32F3xx_HAL_Driver
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /** @defgroup ADCEx ADCEx
<> 144:ef7eb2e8f9f7 64 * @brief ADC Extended HAL module driver
<> 144:ef7eb2e8f9f7 65 * @{
<> 144:ef7eb2e8f9f7 66 */
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 #ifdef HAL_ADC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 71 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 72 /** @defgroup ADCEx_Private_Constants ADCEx Private Constants
<> 144:ef7eb2e8f9f7 73 * @{
<> 144:ef7eb2e8f9f7 74 */
<> 144:ef7eb2e8f9f7 75 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 76 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 77 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 78 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 79 /* Fixed timeout values for ADC calibration, enable settling time, disable */
<> 144:ef7eb2e8f9f7 80 /* settling time. */
<> 144:ef7eb2e8f9f7 81 /* Values defined to be higher than worst cases: low clock frequency, */
<> 144:ef7eb2e8f9f7 82 /* maximum prescalers. */
<> 144:ef7eb2e8f9f7 83 /* Ex of profile low frequency : Clock source at 0.5 MHz, ADC clock */
<> 144:ef7eb2e8f9f7 84 /* prescaler 256 (devices STM32F30xx), sampling time 7.5 ADC clock cycles, */
<> 144:ef7eb2e8f9f7 85 /* resolution 12 bits. */
<> 144:ef7eb2e8f9f7 86 /* Unit: ms */
<> 144:ef7eb2e8f9f7 87 #define ADC_CALIBRATION_TIMEOUT ((uint32_t) 10)
<> 144:ef7eb2e8f9f7 88 #define ADC_ENABLE_TIMEOUT ((uint32_t) 2)
<> 144:ef7eb2e8f9f7 89 #define ADC_DISABLE_TIMEOUT ((uint32_t) 2)
<> 144:ef7eb2e8f9f7 90 #define ADC_STOP_CONVERSION_TIMEOUT ((uint32_t) 11)
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /* Timeout to wait for current conversion on going to be completed. */
<> 144:ef7eb2e8f9f7 93 /* Timeout fixed to worst case, for 1 channel. */
<> 144:ef7eb2e8f9f7 94 /* - maximum sampling time (601.5 adc_clk) */
<> 144:ef7eb2e8f9f7 95 /* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */
<> 144:ef7eb2e8f9f7 96 /* - ADC clock (from PLL with prescaler 256 (devices STM32F30xx)) */
<> 144:ef7eb2e8f9f7 97 /* Unit: cycles of CPU clock. */
<> 144:ef7eb2e8f9f7 98 #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 156928)
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
<> 144:ef7eb2e8f9f7 101 /* Maximum delay is 10us (refer to device datasheet, param. TADCVREG_STUP). */
<> 144:ef7eb2e8f9f7 102 /* Unit: us */
<> 144:ef7eb2e8f9f7 103 #define ADC_STAB_DELAY_US ((uint32_t) 10)
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /* Delay for temperature sensor stabilization time. */
<> 144:ef7eb2e8f9f7 106 /* Maximum delay is 10us (refer device datasheet, parameter tSTART). */
<> 144:ef7eb2e8f9f7 107 /* Unit: us */
<> 144:ef7eb2e8f9f7 108 #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 111 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 112 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 113 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 116 /* Timeout values for ADC enable and disable settling time. */
<> 144:ef7eb2e8f9f7 117 /* Values defined to be higher than worst cases: low clocks freq, */
<> 144:ef7eb2e8f9f7 118 /* maximum prescaler. */
<> 144:ef7eb2e8f9f7 119 /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
<> 144:ef7eb2e8f9f7 120 /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
<> 144:ef7eb2e8f9f7 121 /* Unit: ms */
<> 144:ef7eb2e8f9f7 122 #define ADC_ENABLE_TIMEOUT ((uint32_t) 2)
<> 144:ef7eb2e8f9f7 123 #define ADC_DISABLE_TIMEOUT ((uint32_t) 2)
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /* Delay for ADC calibration: */
<> 144:ef7eb2e8f9f7 126 /* Hardware prerequisite before starting a calibration: the ADC must have */
<> 144:ef7eb2e8f9f7 127 /* been in power-on state for at least two ADC clock cycles. */
<> 144:ef7eb2e8f9f7 128 /* Unit: ADC clock cycles */
<> 144:ef7eb2e8f9f7 129 #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ((uint32_t) 2)
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /* Timeout value for ADC calibration */
<> 144:ef7eb2e8f9f7 132 /* Value defined to be higher than worst cases: low clocks freq, */
<> 144:ef7eb2e8f9f7 133 /* maximum prescaler. */
<> 144:ef7eb2e8f9f7 134 /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
<> 144:ef7eb2e8f9f7 135 /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
<> 144:ef7eb2e8f9f7 136 /* Unit: ms */
<> 144:ef7eb2e8f9f7 137 #define ADC_CALIBRATION_TIMEOUT ((uint32_t) 10)
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /* Delay for ADC stabilization time. */
<> 144:ef7eb2e8f9f7 140 /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
<> 144:ef7eb2e8f9f7 141 /* Unit: us */
<> 144:ef7eb2e8f9f7 142 #define ADC_STAB_DELAY_US ((uint32_t) 1)
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /* Delay for temperature sensor stabilization time. */
<> 144:ef7eb2e8f9f7 145 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
<> 144:ef7eb2e8f9f7 146 /* Unit: us */
<> 144:ef7eb2e8f9f7 147 #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /* Maximum number of CPU cycles corresponding to 1 ADC cycle */
<> 144:ef7eb2e8f9f7 150 /* Value fixed to worst case: clock prescalers slowing down ADC clock to */
<> 144:ef7eb2e8f9f7 151 /* minimum frequency */
<> 144:ef7eb2e8f9f7 152 /* - AHB prescaler: 16 */
<> 144:ef7eb2e8f9f7 153 /* - ADC prescaler: 8 */
<> 144:ef7eb2e8f9f7 154 /* Unit: cycles of CPU clock. */
<> 144:ef7eb2e8f9f7 155 #define ADC_CYCLE_WORST_CASE_CPU_CYCLES ((uint32_t) 128)
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /* ADC conversion cycles (unit: ADC clock cycles) */
<> 144:ef7eb2e8f9f7 158 /* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */
<> 144:ef7eb2e8f9f7 159 /* resolution 12 bits) */
<> 144:ef7eb2e8f9f7 160 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 ((uint32_t) 14)
<> 144:ef7eb2e8f9f7 161 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 ((uint32_t) 20)
<> 144:ef7eb2e8f9f7 162 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 ((uint32_t) 26)
<> 144:ef7eb2e8f9f7 163 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 ((uint32_t) 41)
<> 144:ef7eb2e8f9f7 164 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 ((uint32_t) 54)
<> 144:ef7eb2e8f9f7 165 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 ((uint32_t) 68)
<> 144:ef7eb2e8f9f7 166 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 ((uint32_t) 84)
<> 144:ef7eb2e8f9f7 167 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 ((uint32_t)252)
<> 144:ef7eb2e8f9f7 168 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 169 /**
<> 144:ef7eb2e8f9f7 170 * @}
<> 144:ef7eb2e8f9f7 171 */
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 174 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 175 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 176 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 177 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 178 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 179 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 180 static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 181 static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 182 static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup);
<> 144:ef7eb2e8f9f7 183 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 184 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 185 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 186 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 189 static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 190 static HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 191 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 194 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 195 static void ADC_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions
<> 144:ef7eb2e8f9f7 200 * @{
<> 144:ef7eb2e8f9f7 201 */
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /** @defgroup ADCEx_Exported_Functions_Group1 ADCEx Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 204 * @brief ADC Extended Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 205 *
<> 144:ef7eb2e8f9f7 206 @verbatim
<> 144:ef7eb2e8f9f7 207 ===============================================================================
<> 144:ef7eb2e8f9f7 208 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 209 ===============================================================================
<> 144:ef7eb2e8f9f7 210 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 211 (+) Initialize and configure the ADC.
<> 144:ef7eb2e8f9f7 212 (+) De-initialize the ADC.
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 @endverbatim
<> 144:ef7eb2e8f9f7 215 * @{
<> 144:ef7eb2e8f9f7 216 */
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 219 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 220 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 221 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 222 /**
<> 144:ef7eb2e8f9f7 223 * @brief Initializes the ADC peripheral and regular group according to
<> 144:ef7eb2e8f9f7 224 * parameters specified in structure "ADC_InitTypeDef".
<> 144:ef7eb2e8f9f7 225 * @note As prerequisite, ADC clock must be configured at RCC top level
<> 144:ef7eb2e8f9f7 226 * depending on possible clock sources: AHB clock or PLL clock.
<> 144:ef7eb2e8f9f7 227 * See commented example code below that can be copied and uncommented
<> 144:ef7eb2e8f9f7 228 * into HAL_ADC_MspInit().
<> 144:ef7eb2e8f9f7 229 * @note Possibility to update parameters on the fly:
<> 144:ef7eb2e8f9f7 230 * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
<> 144:ef7eb2e8f9f7 231 * coming from ADC state reset. Following calls to this function can
<> 144:ef7eb2e8f9f7 232 * be used to reconfigure some parameters of ADC_InitTypeDef
<> 144:ef7eb2e8f9f7 233 * structure on the fly, without modifying MSP configuration. If ADC
<> 144:ef7eb2e8f9f7 234 * MSP has to be modified again, HAL_ADC_DeInit() must be called
<> 144:ef7eb2e8f9f7 235 * before HAL_ADC_Init().
<> 144:ef7eb2e8f9f7 236 * The setting of these parameters is conditioned by ADC state.
<> 144:ef7eb2e8f9f7 237 * For parameters constraints, see comments of structure
<> 144:ef7eb2e8f9f7 238 * "ADC_InitTypeDef".
<> 144:ef7eb2e8f9f7 239 * @note This function configures the ADC within 2 scopes: scope of entire
<> 144:ef7eb2e8f9f7 240 * ADC and scope of regular group. For parameters details, see comments
<> 144:ef7eb2e8f9f7 241 * of structure "ADC_InitTypeDef".
<> 144:ef7eb2e8f9f7 242 * @note For devices with several ADCs: parameters related to common ADC
<> 144:ef7eb2e8f9f7 243 * registers (ADC clock mode) are set only if all ADCs sharing the
<> 144:ef7eb2e8f9f7 244 * same common group are disabled.
<> 144:ef7eb2e8f9f7 245 * If this is not the case, these common parameters setting are
<> 144:ef7eb2e8f9f7 246 * bypassed without error reporting: it can be the intended behaviour in
<> 144:ef7eb2e8f9f7 247 * case of update of a parameter of ADC_InitTypeDef on the fly,
<> 144:ef7eb2e8f9f7 248 * without disabling the other ADCs sharing the same common group.
<> 144:ef7eb2e8f9f7 249 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 250 * @retval HAL status
<> 144:ef7eb2e8f9f7 251 */
<> 144:ef7eb2e8f9f7 252 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 253 {
<> 144:ef7eb2e8f9f7 254 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 255 ADC_Common_TypeDef *tmpADC_Common;
<> 144:ef7eb2e8f9f7 256 ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
<> 144:ef7eb2e8f9f7 257 uint32_t tmpCFGR = 0;
<> 144:ef7eb2e8f9f7 258 __IO uint32_t wait_loop_index = 0;
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /* Check ADC handle */
<> 144:ef7eb2e8f9f7 261 if(hadc == NULL)
<> 144:ef7eb2e8f9f7 262 {
<> 144:ef7eb2e8f9f7 263 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 264 }
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /* Check the parameters */
<> 144:ef7eb2e8f9f7 267 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 268 assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
<> 144:ef7eb2e8f9f7 269 assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
<> 144:ef7eb2e8f9f7 270 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
<> 144:ef7eb2e8f9f7 271 assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
<> 144:ef7eb2e8f9f7 272 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
<> 144:ef7eb2e8f9f7 273 assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
<> 144:ef7eb2e8f9f7 274 assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
<> 144:ef7eb2e8f9f7 275 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
<> 144:ef7eb2e8f9f7 276 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
<> 144:ef7eb2e8f9f7 277 assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
<> 144:ef7eb2e8f9f7 278 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
<> 144:ef7eb2e8f9f7 281 {
<> 144:ef7eb2e8f9f7 282 assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
<> 144:ef7eb2e8f9f7 283 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
<> 144:ef7eb2e8f9f7 284 if(hadc->Init.DiscontinuousConvMode != DISABLE)
<> 144:ef7eb2e8f9f7 285 {
<> 144:ef7eb2e8f9f7 286 assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
<> 144:ef7eb2e8f9f7 287 }
<> 144:ef7eb2e8f9f7 288 }
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /* Configuration of ADC core parameters and ADC MSP related parameters */
<> 144:ef7eb2e8f9f7 291 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
<> 144:ef7eb2e8f9f7 292 {
<> 144:ef7eb2e8f9f7 293 /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
<> 144:ef7eb2e8f9f7 294 /* at RCC top level. */
<> 144:ef7eb2e8f9f7 295 /* Refer to header of this file for more details on clock enabling */
<> 144:ef7eb2e8f9f7 296 /* procedure. */
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /* Actions performed only if ADC is coming from state reset: */
<> 144:ef7eb2e8f9f7 299 /* - Initialization of ADC MSP */
<> 144:ef7eb2e8f9f7 300 /* - ADC voltage regulator enable */
<> 144:ef7eb2e8f9f7 301 if (hadc->State == HAL_ADC_STATE_RESET)
<> 144:ef7eb2e8f9f7 302 {
<> 144:ef7eb2e8f9f7 303 /* Initialize ADC error code */
<> 144:ef7eb2e8f9f7 304 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /* Initialize HAL ADC API internal variables */
<> 144:ef7eb2e8f9f7 307 hadc->InjectionConfig.ChannelCount = 0;
<> 144:ef7eb2e8f9f7 308 hadc->InjectionConfig.ContextQueue = 0;
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 311 hadc->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /* Init the low level hardware */
<> 144:ef7eb2e8f9f7 314 HAL_ADC_MspInit(hadc);
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /* Enable voltage regulator (if disabled at this step) */
<> 144:ef7eb2e8f9f7 317 if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0))
<> 144:ef7eb2e8f9f7 318 {
<> 144:ef7eb2e8f9f7 319 /* Note: The software must wait for the startup time of the ADC */
<> 144:ef7eb2e8f9f7 320 /* voltage regulator before launching a calibration or */
<> 144:ef7eb2e8f9f7 321 /* enabling the ADC. This temporization must be implemented by */
<> 144:ef7eb2e8f9f7 322 /* software and is equal to 10 us in the worst case */
<> 144:ef7eb2e8f9f7 323 /* process/temperature/power supply. */
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /* Disable the ADC (if not already disabled) */
<> 144:ef7eb2e8f9f7 326 tmp_hal_status = ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 329 /* Configuration of ADC parameters if previous preliminary actions */
<> 144:ef7eb2e8f9f7 330 /* are correctly completed. */
<> 144:ef7eb2e8f9f7 331 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
<> 144:ef7eb2e8f9f7 332 (tmp_hal_status == HAL_OK) )
<> 144:ef7eb2e8f9f7 333 {
<> 144:ef7eb2e8f9f7 334 /* Set ADC state */
<> 144:ef7eb2e8f9f7 335 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 336 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 144:ef7eb2e8f9f7 337 HAL_ADC_STATE_BUSY_INTERNAL);
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /* Set the intermediate state before moving the ADC voltage */
<> 144:ef7eb2e8f9f7 340 /* regulator to state enable. */
<> 144:ef7eb2e8f9f7 341 CLEAR_BIT(hadc->Instance->CR, (ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0));
<> 144:ef7eb2e8f9f7 342 /* Set ADVREGEN bits to 0x01 */
<> 144:ef7eb2e8f9f7 343 SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_0);
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /* Delay for ADC stabilization time. */
<> 144:ef7eb2e8f9f7 346 /* Compute number of CPU cycles to wait for */
<> 144:ef7eb2e8f9f7 347 wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
<> 144:ef7eb2e8f9f7 348 while(wait_loop_index != 0)
<> 144:ef7eb2e8f9f7 349 {
<> 144:ef7eb2e8f9f7 350 wait_loop_index--;
<> 144:ef7eb2e8f9f7 351 }
<> 144:ef7eb2e8f9f7 352 }
<> 144:ef7eb2e8f9f7 353 }
<> 144:ef7eb2e8f9f7 354 }
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /* Verification that ADC voltage regulator is correctly enabled, whether */
<> 144:ef7eb2e8f9f7 357 /* or not ADC is coming from state reset (if any potential problem of */
<> 144:ef7eb2e8f9f7 358 /* clocking, voltage regulator would not be enabled). */
<> 144:ef7eb2e8f9f7 359 if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0) ||
<> 144:ef7eb2e8f9f7 360 HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADVREGEN_1) )
<> 144:ef7eb2e8f9f7 361 {
<> 144:ef7eb2e8f9f7 362 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 363 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 364 HAL_ADC_STATE_BUSY_INTERNAL,
<> 144:ef7eb2e8f9f7 365 HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 368 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 371 }
<> 144:ef7eb2e8f9f7 372 }
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /* Configuration of ADC parameters if previous preliminary actions are */
<> 144:ef7eb2e8f9f7 376 /* correctly completed and if there is no conversion on going on regular */
<> 144:ef7eb2e8f9f7 377 /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
<> 144:ef7eb2e8f9f7 378 /* called to update a parameter on the fly). */
<> 144:ef7eb2e8f9f7 379 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
<> 144:ef7eb2e8f9f7 380 (tmp_hal_status == HAL_OK) &&
<> 144:ef7eb2e8f9f7 381 (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) )
<> 144:ef7eb2e8f9f7 382 {
<> 144:ef7eb2e8f9f7 383 /* Set ADC state */
<> 144:ef7eb2e8f9f7 384 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 385 HAL_ADC_STATE_REG_BUSY,
<> 144:ef7eb2e8f9f7 386 HAL_ADC_STATE_BUSY_INTERNAL);
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /* Configuration of common ADC parameters */
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 /* Pointer to the common control register to which is belonging hadc */
<> 144:ef7eb2e8f9f7 391 /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
<> 144:ef7eb2e8f9f7 392 /* control registers) */
<> 144:ef7eb2e8f9f7 393 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /* Set handle of the other ADC sharing the same common register */
<> 144:ef7eb2e8f9f7 396 ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 /* Parameters update conditioned to ADC state: */
<> 144:ef7eb2e8f9f7 400 /* Parameters that can be updated only when ADC is disabled: */
<> 144:ef7eb2e8f9f7 401 /* - Multimode clock configuration */
<> 144:ef7eb2e8f9f7 402 if ((ADC_IS_ENABLE(hadc) == RESET) &&
<> 144:ef7eb2e8f9f7 403 ((tmphadcSharingSameCommonRegister.Instance == NULL) ||
<> 144:ef7eb2e8f9f7 404 (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) )
<> 144:ef7eb2e8f9f7 405 {
<> 144:ef7eb2e8f9f7 406 /* Reset configuration of ADC common register CCR: */
<> 144:ef7eb2e8f9f7 407 /* - ADC clock mode: CKMODE */
<> 144:ef7eb2e8f9f7 408 /* Some parameters of this register are not reset, since they are set */
<> 144:ef7eb2e8f9f7 409 /* by other functions and must be kept in case of usage of this */
<> 144:ef7eb2e8f9f7 410 /* function on the fly (update of a parameter of ADC_InitTypeDef */
<> 144:ef7eb2e8f9f7 411 /* without needing to reconfigure all other ADC groups/channels */
<> 144:ef7eb2e8f9f7 412 /* parameters): */
<> 144:ef7eb2e8f9f7 413 /* - multimode related parameters: MDMA, DMACFG, DELAY, MULTI (set */
<> 144:ef7eb2e8f9f7 414 /* into HAL_ADCEx_MultiModeConfigChannel() ) */
<> 144:ef7eb2e8f9f7 415 /* - internal measurement paths: Vbat, temperature sensor, Vref */
<> 144:ef7eb2e8f9f7 416 /* (set into HAL_ADC_ConfigChannel() or */
<> 144:ef7eb2e8f9f7 417 /* HAL_ADCEx_InjectedConfigChannel() ) */
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 MODIFY_REG(tmpADC_Common->CCR ,
<> 144:ef7eb2e8f9f7 420 ADC_CCR_CKMODE ,
<> 144:ef7eb2e8f9f7 421 hadc->Init.ClockPrescaler );
<> 144:ef7eb2e8f9f7 422 }
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /* Configuration of ADC: */
<> 144:ef7eb2e8f9f7 426 /* - resolution */
<> 144:ef7eb2e8f9f7 427 /* - data alignment */
<> 144:ef7eb2e8f9f7 428 /* - external trigger to start conversion */
<> 144:ef7eb2e8f9f7 429 /* - external trigger polarity */
<> 144:ef7eb2e8f9f7 430 /* - continuous conversion mode */
<> 144:ef7eb2e8f9f7 431 /* - overrun */
<> 144:ef7eb2e8f9f7 432 /* - discontinuous mode */
<> 144:ef7eb2e8f9f7 433 SET_BIT(tmpCFGR, ADC_CFGR_CONTINUOUS(hadc->Init.ContinuousConvMode) |
<> 144:ef7eb2e8f9f7 434 ADC_CFGR_OVERRUN(hadc->Init.Overrun) |
<> 144:ef7eb2e8f9f7 435 hadc->Init.DataAlign |
<> 144:ef7eb2e8f9f7 436 hadc->Init.Resolution );
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 /* Enable discontinuous mode only if continuous mode is disabled */
<> 144:ef7eb2e8f9f7 439 if (hadc->Init.DiscontinuousConvMode == ENABLE)
<> 144:ef7eb2e8f9f7 440 {
<> 144:ef7eb2e8f9f7 441 if (hadc->Init.ContinuousConvMode == DISABLE)
<> 144:ef7eb2e8f9f7 442 {
<> 144:ef7eb2e8f9f7 443 /* Enable the selected ADC regular discontinuous mode */
<> 144:ef7eb2e8f9f7 444 /* Set the number of channels to be converted in discontinuous mode */
<> 144:ef7eb2e8f9f7 445 SET_BIT(tmpCFGR, ADC_CFGR_DISCEN |
<> 144:ef7eb2e8f9f7 446 ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) );
<> 144:ef7eb2e8f9f7 447 }
<> 144:ef7eb2e8f9f7 448 else
<> 144:ef7eb2e8f9f7 449 {
<> 144:ef7eb2e8f9f7 450 /* ADC regular group discontinuous was intended to be enabled, */
<> 144:ef7eb2e8f9f7 451 /* but ADC regular group modes continuous and sequencer discontinuous */
<> 144:ef7eb2e8f9f7 452 /* cannot be enabled simultaneously. */
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 455 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 456 HAL_ADC_STATE_BUSY_INTERNAL,
<> 144:ef7eb2e8f9f7 457 HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 460 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 461 }
<> 144:ef7eb2e8f9f7 462 }
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 /* Enable external trigger if trigger selection is different of software */
<> 144:ef7eb2e8f9f7 465 /* start. */
<> 144:ef7eb2e8f9f7 466 /* Note: This configuration keeps the hardware feature of parameter */
<> 144:ef7eb2e8f9f7 467 /* ExternalTrigConvEdge "trigger edge none" equivalent to */
<> 144:ef7eb2e8f9f7 468 /* software start. */
<> 144:ef7eb2e8f9f7 469 if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
<> 144:ef7eb2e8f9f7 470 {
<> 144:ef7eb2e8f9f7 471 SET_BIT(tmpCFGR, ADC_CFGR_EXTSEL_SET(hadc, hadc->Init.ExternalTrigConv) |
<> 144:ef7eb2e8f9f7 472 hadc->Init.ExternalTrigConvEdge );
<> 144:ef7eb2e8f9f7 473 }
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 /* Parameters update conditioned to ADC state: */
<> 144:ef7eb2e8f9f7 476 /* Parameters that can be updated when ADC is disabled or enabled without */
<> 144:ef7eb2e8f9f7 477 /* conversion on going on regular and injected groups: */
<> 144:ef7eb2e8f9f7 478 /* - DMA continuous request */
<> 144:ef7eb2e8f9f7 479 /* - LowPowerAutoWait feature */
<> 144:ef7eb2e8f9f7 480 if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
<> 144:ef7eb2e8f9f7 481 {
<> 144:ef7eb2e8f9f7 482 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AUTDLY |
<> 144:ef7eb2e8f9f7 483 ADC_CFGR_DMACFG );
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 SET_BIT(tmpCFGR, ADC_CFGR_AUTOWAIT(hadc->Init.LowPowerAutoWait) |
<> 144:ef7eb2e8f9f7 486 ADC_CFGR_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
<> 144:ef7eb2e8f9f7 487 }
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 /* Update ADC configuration register with previous settings */
<> 144:ef7eb2e8f9f7 490 MODIFY_REG(hadc->Instance->CFGR,
<> 144:ef7eb2e8f9f7 491 ADC_CFGR_DISCNUM |
<> 144:ef7eb2e8f9f7 492 ADC_CFGR_DISCEN |
<> 144:ef7eb2e8f9f7 493 ADC_CFGR_CONT |
<> 144:ef7eb2e8f9f7 494 ADC_CFGR_OVRMOD |
<> 144:ef7eb2e8f9f7 495 ADC_CFGR_EXTSEL |
<> 144:ef7eb2e8f9f7 496 ADC_CFGR_EXTEN |
<> 144:ef7eb2e8f9f7 497 ADC_CFGR_ALIGN |
<> 144:ef7eb2e8f9f7 498 ADC_CFGR_RES ,
<> 144:ef7eb2e8f9f7 499 tmpCFGR );
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 /* Configuration of regular group sequencer: */
<> 144:ef7eb2e8f9f7 503 /* - if scan mode is disabled, regular channels sequence length is set to */
<> 144:ef7eb2e8f9f7 504 /* 0x00: 1 channel converted (channel on regular rank 1) */
<> 144:ef7eb2e8f9f7 505 /* Parameter "NbrOfConversion" is discarded. */
<> 144:ef7eb2e8f9f7 506 /* Note: Scan mode is not present by hardware on this device, but */
<> 144:ef7eb2e8f9f7 507 /* emulated by software for alignment over all STM32 devices. */
<> 144:ef7eb2e8f9f7 508 /* - if scan mode is enabled, regular channels sequence length is set to */
<> 144:ef7eb2e8f9f7 509 /* parameter "NbrOfConversion" */
<> 144:ef7eb2e8f9f7 510 if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
<> 144:ef7eb2e8f9f7 511 {
<> 144:ef7eb2e8f9f7 512 /* Set number of ranks in regular group sequencer */
<> 144:ef7eb2e8f9f7 513 MODIFY_REG(hadc->Instance->SQR1 ,
<> 144:ef7eb2e8f9f7 514 ADC_SQR1_L ,
<> 144:ef7eb2e8f9f7 515 (hadc->Init.NbrOfConversion - (uint8_t)1) );
<> 144:ef7eb2e8f9f7 516 }
<> 144:ef7eb2e8f9f7 517 else
<> 144:ef7eb2e8f9f7 518 {
<> 144:ef7eb2e8f9f7 519 CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
<> 144:ef7eb2e8f9f7 520 }
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 /* Set ADC error code to none */
<> 144:ef7eb2e8f9f7 523 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 524
<> 144:ef7eb2e8f9f7 525 /* Set the ADC state */
<> 144:ef7eb2e8f9f7 526 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 527 HAL_ADC_STATE_BUSY_INTERNAL,
<> 144:ef7eb2e8f9f7 528 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 529 }
<> 144:ef7eb2e8f9f7 530 else
<> 144:ef7eb2e8f9f7 531 {
<> 144:ef7eb2e8f9f7 532 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 533 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 534 HAL_ADC_STATE_BUSY_INTERNAL,
<> 144:ef7eb2e8f9f7 535 HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 538 }
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 /* Return function status */
<> 144:ef7eb2e8f9f7 542 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 543 }
<> 144:ef7eb2e8f9f7 544 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 545 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 546 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 547 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 550 /**
<> 144:ef7eb2e8f9f7 551 * @brief Initializes the ADC peripheral and regular group according to
<> 144:ef7eb2e8f9f7 552 * parameters specified in structure "ADC_InitTypeDef".
<> 144:ef7eb2e8f9f7 553 * @note As prerequisite, ADC clock must be configured at RCC top level
<> 144:ef7eb2e8f9f7 554 * (clock source APB2).
<> 144:ef7eb2e8f9f7 555 * See commented example code below that can be copied and uncommented
<> 144:ef7eb2e8f9f7 556 * into HAL_ADC_MspInit().
<> 144:ef7eb2e8f9f7 557 * @note Possibility to update parameters on the fly:
<> 144:ef7eb2e8f9f7 558 * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
<> 144:ef7eb2e8f9f7 559 * coming from ADC state reset. Following calls to this function can
<> 144:ef7eb2e8f9f7 560 * be used to reconfigure some parameters of ADC_InitTypeDef
<> 144:ef7eb2e8f9f7 561 * structure on the fly, without modifying MSP configuration. If ADC
<> 144:ef7eb2e8f9f7 562 * MSP has to be modified again, HAL_ADC_DeInit() must be called
<> 144:ef7eb2e8f9f7 563 * before HAL_ADC_Init().
<> 144:ef7eb2e8f9f7 564 * The setting of these parameters is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 565 * For parameters constraints, see comments of structure
<> 144:ef7eb2e8f9f7 566 * "ADC_InitTypeDef".
<> 144:ef7eb2e8f9f7 567 * @note This function configures the ADC within 2 scopes: scope of entire
<> 144:ef7eb2e8f9f7 568 * ADC and scope of regular group. For parameters details, see comments
<> 144:ef7eb2e8f9f7 569 * of structure "ADC_InitTypeDef".
<> 144:ef7eb2e8f9f7 570 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 571 * @retval HAL status
<> 144:ef7eb2e8f9f7 572 */
<> 144:ef7eb2e8f9f7 573 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 574 {
<> 144:ef7eb2e8f9f7 575 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 576 uint32_t tmp_cr1 = 0;
<> 144:ef7eb2e8f9f7 577 uint32_t tmp_cr2 = 0;
<> 144:ef7eb2e8f9f7 578 uint32_t tmp_sqr1 = 0;
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 /* Check ADC handle */
<> 144:ef7eb2e8f9f7 581 if(hadc == NULL)
<> 144:ef7eb2e8f9f7 582 {
<> 144:ef7eb2e8f9f7 583 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 584 }
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 /* Check the parameters */
<> 144:ef7eb2e8f9f7 587 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 588 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
<> 144:ef7eb2e8f9f7 589 assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
<> 144:ef7eb2e8f9f7 590 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
<> 144:ef7eb2e8f9f7 591 assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593 if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
<> 144:ef7eb2e8f9f7 594 {
<> 144:ef7eb2e8f9f7 595 assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
<> 144:ef7eb2e8f9f7 596 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
<> 144:ef7eb2e8f9f7 597 if(hadc->Init.DiscontinuousConvMode != DISABLE)
<> 144:ef7eb2e8f9f7 598 {
<> 144:ef7eb2e8f9f7 599 assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
<> 144:ef7eb2e8f9f7 600 }
<> 144:ef7eb2e8f9f7 601 }
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
<> 144:ef7eb2e8f9f7 604 /* at RCC top level. */
<> 144:ef7eb2e8f9f7 605 /* Refer to header of this file for more details on clock enabling */
<> 144:ef7eb2e8f9f7 606 /* procedure. */
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 /* Actions performed only if ADC is coming from state reset: */
<> 144:ef7eb2e8f9f7 609 /* - Initialization of ADC MSP */
<> 144:ef7eb2e8f9f7 610 if (hadc->State == HAL_ADC_STATE_RESET)
<> 144:ef7eb2e8f9f7 611 {
<> 144:ef7eb2e8f9f7 612 /* Initialize ADC error code */
<> 144:ef7eb2e8f9f7 613 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 616 hadc->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /* Init the low level hardware */
<> 144:ef7eb2e8f9f7 619 HAL_ADC_MspInit(hadc);
<> 144:ef7eb2e8f9f7 620 }
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 /* Stop potential conversion on going, on regular and injected groups */
<> 144:ef7eb2e8f9f7 623 /* Disable ADC peripheral */
<> 144:ef7eb2e8f9f7 624 /* Note: In case of ADC already enabled, precaution to not launch an */
<> 144:ef7eb2e8f9f7 625 /* unwanted conversion while modifying register CR2 by writing 1 to */
<> 144:ef7eb2e8f9f7 626 /* bit ADON. */
<> 144:ef7eb2e8f9f7 627 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 /* Configuration of ADC parameters if previous preliminary actions are */
<> 144:ef7eb2e8f9f7 631 /* correctly completed. */
<> 144:ef7eb2e8f9f7 632 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
<> 144:ef7eb2e8f9f7 633 (tmp_hal_status == HAL_OK) )
<> 144:ef7eb2e8f9f7 634 {
<> 144:ef7eb2e8f9f7 635 /* Set ADC state */
<> 144:ef7eb2e8f9f7 636 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 637 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 144:ef7eb2e8f9f7 638 HAL_ADC_STATE_BUSY_INTERNAL);
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 /* Set ADC parameters */
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 /* Configuration of ADC: */
<> 144:ef7eb2e8f9f7 643 /* - data alignment */
<> 144:ef7eb2e8f9f7 644 /* - external trigger to start conversion */
<> 144:ef7eb2e8f9f7 645 /* - external trigger polarity (always set to 1, because needed for all */
<> 144:ef7eb2e8f9f7 646 /* triggers: external trigger of SW start) */
<> 144:ef7eb2e8f9f7 647 /* - continuous conversion mode */
<> 144:ef7eb2e8f9f7 648 /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */
<> 144:ef7eb2e8f9f7 649 /* HAL_ADC_Start_xxx functions because if set in this function, */
<> 144:ef7eb2e8f9f7 650 /* a conversion on injected group would start a conversion also on */
<> 144:ef7eb2e8f9f7 651 /* regular group after ADC enabling. */
<> 144:ef7eb2e8f9f7 652 tmp_cr2 |= (hadc->Init.DataAlign |
<> 144:ef7eb2e8f9f7 653 hadc->Init.ExternalTrigConv |
<> 144:ef7eb2e8f9f7 654 ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode) );
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 /* Configuration of ADC: */
<> 144:ef7eb2e8f9f7 657 /* - scan mode */
<> 144:ef7eb2e8f9f7 658 /* - discontinuous mode disable/enable */
<> 144:ef7eb2e8f9f7 659 /* - discontinuous mode number of conversions */
<> 144:ef7eb2e8f9f7 660 tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 /* Enable discontinuous mode only if continuous mode is disabled */
<> 144:ef7eb2e8f9f7 663 /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */
<> 144:ef7eb2e8f9f7 664 /* discontinuous is set anyway, but will have no effect on ADC HW. */
<> 144:ef7eb2e8f9f7 665 if (hadc->Init.DiscontinuousConvMode == ENABLE)
<> 144:ef7eb2e8f9f7 666 {
<> 144:ef7eb2e8f9f7 667 if (hadc->Init.ContinuousConvMode == DISABLE)
<> 144:ef7eb2e8f9f7 668 {
<> 144:ef7eb2e8f9f7 669 /* Enable the selected ADC regular discontinuous mode */
<> 144:ef7eb2e8f9f7 670 /* Set the number of channels to be converted in discontinuous mode */
<> 144:ef7eb2e8f9f7 671 tmp_cr1 |= (ADC_CR1_DISCEN |
<> 144:ef7eb2e8f9f7 672 ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) );
<> 144:ef7eb2e8f9f7 673 }
<> 144:ef7eb2e8f9f7 674 else
<> 144:ef7eb2e8f9f7 675 {
<> 144:ef7eb2e8f9f7 676 /* ADC regular group discontinuous was intended to be enabled, */
<> 144:ef7eb2e8f9f7 677 /* but ADC regular group modes continuous and sequencer discontinuous */
<> 144:ef7eb2e8f9f7 678 /* cannot be enabled simultaneously. */
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 681 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 684 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 685 }
<> 144:ef7eb2e8f9f7 686 }
<> 144:ef7eb2e8f9f7 687
<> 144:ef7eb2e8f9f7 688 /* Update ADC configuration register CR1 with previous settings */
<> 144:ef7eb2e8f9f7 689 MODIFY_REG(hadc->Instance->CR1,
<> 144:ef7eb2e8f9f7 690 ADC_CR1_SCAN |
<> 144:ef7eb2e8f9f7 691 ADC_CR1_DISCEN |
<> 144:ef7eb2e8f9f7 692 ADC_CR1_DISCNUM ,
<> 144:ef7eb2e8f9f7 693 tmp_cr1 );
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 /* Update ADC configuration register CR2 with previous settings */
<> 144:ef7eb2e8f9f7 696 MODIFY_REG(hadc->Instance->CR2,
<> 144:ef7eb2e8f9f7 697 ADC_CR2_ALIGN |
<> 144:ef7eb2e8f9f7 698 ADC_CR2_EXTSEL |
<> 144:ef7eb2e8f9f7 699 ADC_CR2_EXTTRIG |
<> 144:ef7eb2e8f9f7 700 ADC_CR2_CONT ,
<> 144:ef7eb2e8f9f7 701 tmp_cr2 );
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 /* Configuration of regular group sequencer: */
<> 144:ef7eb2e8f9f7 704 /* - if scan mode is disabled, regular channels sequence length is set to */
<> 144:ef7eb2e8f9f7 705 /* 0x00: 1 channel converted (channel on regular rank 1) */
<> 144:ef7eb2e8f9f7 706 /* Parameter "NbrOfConversion" is discarded. */
<> 144:ef7eb2e8f9f7 707 /* Note: Scan mode is present by hardware on this device and, if */
<> 144:ef7eb2e8f9f7 708 /* disabled, discards automatically nb of conversions. Anyway, nb of */
<> 144:ef7eb2e8f9f7 709 /* conversions is forced to 0x00 for alignment over all STM32 devices. */
<> 144:ef7eb2e8f9f7 710 /* - if scan mode is enabled, regular channels sequence length is set to */
<> 144:ef7eb2e8f9f7 711 /* parameter "NbrOfConversion" */
<> 144:ef7eb2e8f9f7 712 if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
<> 144:ef7eb2e8f9f7 713 {
<> 144:ef7eb2e8f9f7 714 tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
<> 144:ef7eb2e8f9f7 715 }
<> 144:ef7eb2e8f9f7 716
<> 144:ef7eb2e8f9f7 717 MODIFY_REG(hadc->Instance->SQR1,
<> 144:ef7eb2e8f9f7 718 ADC_SQR1_L ,
<> 144:ef7eb2e8f9f7 719 tmp_sqr1 );
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 /* Check back that ADC registers have effectively been configured to */
<> 144:ef7eb2e8f9f7 722 /* ensure of no potential problem of ADC core IP clocking. */
<> 144:ef7eb2e8f9f7 723 /* Check through register CR2 (excluding bits set in other functions: */
<> 144:ef7eb2e8f9f7 724 /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */
<> 144:ef7eb2e8f9f7 725 /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */
<> 144:ef7eb2e8f9f7 726 /* measurement path bit (TSVREFE). */
<> 144:ef7eb2e8f9f7 727 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
<> 144:ef7eb2e8f9f7 728 ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
<> 144:ef7eb2e8f9f7 729 ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL |
<> 144:ef7eb2e8f9f7 730 ADC_CR2_TSVREFE ))
<> 144:ef7eb2e8f9f7 731 == tmp_cr2)
<> 144:ef7eb2e8f9f7 732 {
<> 144:ef7eb2e8f9f7 733 /* Set ADC error code to none */
<> 144:ef7eb2e8f9f7 734 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 /* Set the ADC state */
<> 144:ef7eb2e8f9f7 737 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 738 HAL_ADC_STATE_BUSY_INTERNAL,
<> 144:ef7eb2e8f9f7 739 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 740 }
<> 144:ef7eb2e8f9f7 741 else
<> 144:ef7eb2e8f9f7 742 {
<> 144:ef7eb2e8f9f7 743 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 744 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 745 HAL_ADC_STATE_BUSY_INTERNAL,
<> 144:ef7eb2e8f9f7 746 HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 749 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 752 }
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 }
<> 144:ef7eb2e8f9f7 755 else
<> 144:ef7eb2e8f9f7 756 {
<> 144:ef7eb2e8f9f7 757 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 758 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 761 }
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763 /* Return function status */
<> 144:ef7eb2e8f9f7 764 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 765 }
<> 144:ef7eb2e8f9f7 766 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 767
<> 144:ef7eb2e8f9f7 768 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 769 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 770 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 771 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 772 /**
<> 144:ef7eb2e8f9f7 773 * @brief Deinitialize the ADC peripheral registers to their default reset
<> 144:ef7eb2e8f9f7 774 * values, with deinitialization of the ADC MSP.
<> 144:ef7eb2e8f9f7 775 * @note For devices with several ADCs: reset of ADC common registers is done
<> 144:ef7eb2e8f9f7 776 * only if all ADCs sharing the same common group are disabled.
<> 144:ef7eb2e8f9f7 777 * If this is not the case, reset of these common parameters reset is
<> 144:ef7eb2e8f9f7 778 * bypassed without error reporting: it can be the intended behaviour in
<> 144:ef7eb2e8f9f7 779 * case of reset of a single ADC while the other ADCs sharing the same
<> 144:ef7eb2e8f9f7 780 * common group is still running.
<> 144:ef7eb2e8f9f7 781 * @note For devices with several ADCs: Global reset of all ADCs sharing a
<> 144:ef7eb2e8f9f7 782 * common group is possible.
<> 144:ef7eb2e8f9f7 783 * As this function is intended to reset a single ADC, to not impact
<> 144:ef7eb2e8f9f7 784 * other ADCs, instructions for global reset of multiple ADCs have been
<> 144:ef7eb2e8f9f7 785 * let commented below.
<> 144:ef7eb2e8f9f7 786 * If needed, the example code can be copied and uncommented into
<> 144:ef7eb2e8f9f7 787 * function HAL_ADC_MspDeInit().
<> 144:ef7eb2e8f9f7 788 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 789 * @retval HAL status
<> 144:ef7eb2e8f9f7 790 */
<> 144:ef7eb2e8f9f7 791 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 792 {
<> 144:ef7eb2e8f9f7 793 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 794 ADC_Common_TypeDef *tmpADC_Common;
<> 144:ef7eb2e8f9f7 795 ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 /* Check ADC handle */
<> 144:ef7eb2e8f9f7 798 if(hadc == NULL)
<> 144:ef7eb2e8f9f7 799 {
<> 144:ef7eb2e8f9f7 800 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 801 }
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 /* Check the parameters */
<> 144:ef7eb2e8f9f7 804 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 805
<> 144:ef7eb2e8f9f7 806 /* Set ADC state */
<> 144:ef7eb2e8f9f7 807 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 /* Stop potential conversion on going, on regular and injected groups */
<> 144:ef7eb2e8f9f7 810 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
<> 144:ef7eb2e8f9f7 811
<> 144:ef7eb2e8f9f7 812 /* Disable ADC peripheral if conversions are effectively stopped */
<> 144:ef7eb2e8f9f7 813 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 814 {
<> 144:ef7eb2e8f9f7 815 /* Flush register JSQR: queue sequencer reset when injected queue */
<> 144:ef7eb2e8f9f7 816 /* sequencer is enabled and ADC disabled. */
<> 144:ef7eb2e8f9f7 817 /* Enable injected queue sequencer after injected conversion stop */
<> 144:ef7eb2e8f9f7 818 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
<> 144:ef7eb2e8f9f7 819
<> 144:ef7eb2e8f9f7 820 /* Disable the ADC peripheral */
<> 144:ef7eb2e8f9f7 821 tmp_hal_status = ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 822
<> 144:ef7eb2e8f9f7 823 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 824 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 825 {
<> 144:ef7eb2e8f9f7 826 /* Change ADC state */
<> 144:ef7eb2e8f9f7 827 hadc->State = HAL_ADC_STATE_READY;
<> 144:ef7eb2e8f9f7 828 }
<> 144:ef7eb2e8f9f7 829 else
<> 144:ef7eb2e8f9f7 830 {
<> 144:ef7eb2e8f9f7 831 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 832 }
<> 144:ef7eb2e8f9f7 833 }
<> 144:ef7eb2e8f9f7 834
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 /* Configuration of ADC parameters if previous preliminary actions are */
<> 144:ef7eb2e8f9f7 837 /* correctly completed. */
<> 144:ef7eb2e8f9f7 838 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 839 {
<> 144:ef7eb2e8f9f7 840 /* ========== Reset ADC registers ========== */
<> 144:ef7eb2e8f9f7 841 /* Reset register IER */
<> 144:ef7eb2e8f9f7 842 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
<> 144:ef7eb2e8f9f7 843 ADC_IT_JQOVF | ADC_IT_OVR |
<> 144:ef7eb2e8f9f7 844 ADC_IT_JEOS | ADC_IT_JEOC |
<> 144:ef7eb2e8f9f7 845 ADC_IT_EOS | ADC_IT_EOC |
<> 144:ef7eb2e8f9f7 846 ADC_IT_EOSMP | ADC_IT_RDY ) );
<> 144:ef7eb2e8f9f7 847
<> 144:ef7eb2e8f9f7 848 /* Reset register ISR */
<> 144:ef7eb2e8f9f7 849 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
<> 144:ef7eb2e8f9f7 850 ADC_FLAG_JQOVF | ADC_FLAG_OVR |
<> 144:ef7eb2e8f9f7 851 ADC_FLAG_JEOS | ADC_FLAG_JEOC |
<> 144:ef7eb2e8f9f7 852 ADC_FLAG_EOS | ADC_FLAG_EOC |
<> 144:ef7eb2e8f9f7 853 ADC_FLAG_EOSMP | ADC_FLAG_RDY ) );
<> 144:ef7eb2e8f9f7 854
<> 144:ef7eb2e8f9f7 855 /* Reset register CR */
<> 144:ef7eb2e8f9f7 856 /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART are */
<> 144:ef7eb2e8f9f7 857 /* in access mode "read-set": no direct reset applicable. */
<> 144:ef7eb2e8f9f7 858 /* Reset Calibration mode to default setting (single ended): */
<> 144:ef7eb2e8f9f7 859 /* Disable voltage regulator: */
<> 144:ef7eb2e8f9f7 860 /* Note: Voltage regulator disable is conditioned to ADC state disabled: */
<> 144:ef7eb2e8f9f7 861 /* already done above. */
<> 144:ef7eb2e8f9f7 862 /* Note: Voltage regulator disable is intended for power saving. */
<> 144:ef7eb2e8f9f7 863 /* Sequence to disable voltage regulator: */
<> 144:ef7eb2e8f9f7 864 /* 1. Set the intermediate state before moving the ADC voltage regulator */
<> 144:ef7eb2e8f9f7 865 /* to disable state. */
<> 144:ef7eb2e8f9f7 866 CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0 | ADC_CR_ADCALDIF);
<> 144:ef7eb2e8f9f7 867 /* 2. Set ADVREGEN bits to 0x10 */
<> 144:ef7eb2e8f9f7 868 SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_1);
<> 144:ef7eb2e8f9f7 869
<> 144:ef7eb2e8f9f7 870 /* Reset register CFGR */
<> 144:ef7eb2e8f9f7 871 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |
<> 144:ef7eb2e8f9f7 872 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |
<> 144:ef7eb2e8f9f7 873 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |
<> 144:ef7eb2e8f9f7 874 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |
<> 144:ef7eb2e8f9f7 875 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |
<> 144:ef7eb2e8f9f7 876 ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN );
<> 144:ef7eb2e8f9f7 877
<> 144:ef7eb2e8f9f7 878 /* Reset register SMPR1 */
<> 144:ef7eb2e8f9f7 879 CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |
<> 144:ef7eb2e8f9f7 880 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |
<> 144:ef7eb2e8f9f7 881 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 );
<> 144:ef7eb2e8f9f7 882
<> 144:ef7eb2e8f9f7 883 /* Reset register SMPR2 */
<> 144:ef7eb2e8f9f7 884 CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
<> 144:ef7eb2e8f9f7 885 ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
<> 144:ef7eb2e8f9f7 886 ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10 );
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 /* Reset register TR1 */
<> 144:ef7eb2e8f9f7 889 CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1);
<> 144:ef7eb2e8f9f7 890
<> 144:ef7eb2e8f9f7 891 /* Reset register TR2 */
<> 144:ef7eb2e8f9f7 892 CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2);
<> 144:ef7eb2e8f9f7 893
<> 144:ef7eb2e8f9f7 894 /* Reset register TR3 */
<> 144:ef7eb2e8f9f7 895 CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3);
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 /* Reset register SQR1 */
<> 144:ef7eb2e8f9f7 898 CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
<> 144:ef7eb2e8f9f7 899 ADC_SQR1_SQ1 | ADC_SQR1_L);
<> 144:ef7eb2e8f9f7 900
<> 144:ef7eb2e8f9f7 901 /* Reset register SQR2 */
<> 144:ef7eb2e8f9f7 902 CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
<> 144:ef7eb2e8f9f7 903 ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905 /* Reset register SQR3 */
<> 144:ef7eb2e8f9f7 906 CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
<> 144:ef7eb2e8f9f7 907 ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
<> 144:ef7eb2e8f9f7 908
<> 144:ef7eb2e8f9f7 909 /* Reset register SQR4 */
<> 144:ef7eb2e8f9f7 910 CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
<> 144:ef7eb2e8f9f7 911
<> 144:ef7eb2e8f9f7 912 /* Reset register DR */
<> 144:ef7eb2e8f9f7 913 /* bits in access mode read only, no direct reset applicable*/
<> 144:ef7eb2e8f9f7 914
<> 144:ef7eb2e8f9f7 915 /* Reset register OFR1 */
<> 144:ef7eb2e8f9f7 916 CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
<> 144:ef7eb2e8f9f7 917 /* Reset register OFR2 */
<> 144:ef7eb2e8f9f7 918 CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
<> 144:ef7eb2e8f9f7 919 /* Reset register OFR3 */
<> 144:ef7eb2e8f9f7 920 CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
<> 144:ef7eb2e8f9f7 921 /* Reset register OFR4 */
<> 144:ef7eb2e8f9f7 922 CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
<> 144:ef7eb2e8f9f7 925 /* bits in access mode read only, no direct reset applicable*/
<> 144:ef7eb2e8f9f7 926
<> 144:ef7eb2e8f9f7 927 /* Reset register AWD2CR */
<> 144:ef7eb2e8f9f7 928 CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
<> 144:ef7eb2e8f9f7 929
<> 144:ef7eb2e8f9f7 930 /* Reset register AWD3CR */
<> 144:ef7eb2e8f9f7 931 CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
<> 144:ef7eb2e8f9f7 932
<> 144:ef7eb2e8f9f7 933 /* Reset register DIFSEL */
<> 144:ef7eb2e8f9f7 934 CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
<> 144:ef7eb2e8f9f7 935
<> 144:ef7eb2e8f9f7 936 /* Reset register CALFACT */
<> 144:ef7eb2e8f9f7 937 CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
<> 144:ef7eb2e8f9f7 938
<> 144:ef7eb2e8f9f7 939
<> 144:ef7eb2e8f9f7 940
<> 144:ef7eb2e8f9f7 941
<> 144:ef7eb2e8f9f7 942
<> 144:ef7eb2e8f9f7 943
<> 144:ef7eb2e8f9f7 944 /* ========== Reset common ADC registers ========== */
<> 144:ef7eb2e8f9f7 945
<> 144:ef7eb2e8f9f7 946 /* Pointer to the common control register to which is belonging hadc */
<> 144:ef7eb2e8f9f7 947 /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
<> 144:ef7eb2e8f9f7 948 /* control registers) */
<> 144:ef7eb2e8f9f7 949 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
<> 144:ef7eb2e8f9f7 950
<> 144:ef7eb2e8f9f7 951 /* Set handle of the other ADC sharing the same common register */
<> 144:ef7eb2e8f9f7 952 ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
<> 144:ef7eb2e8f9f7 953
<> 144:ef7eb2e8f9f7 954 /* Software is allowed to change common parameters only when all ADCs of */
<> 144:ef7eb2e8f9f7 955 /* the common group are disabled. */
<> 144:ef7eb2e8f9f7 956 if ((ADC_IS_ENABLE(hadc) == RESET) &&
<> 144:ef7eb2e8f9f7 957 ( (tmphadcSharingSameCommonRegister.Instance == NULL) ||
<> 144:ef7eb2e8f9f7 958 (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) )
<> 144:ef7eb2e8f9f7 959 {
<> 144:ef7eb2e8f9f7 960 /* Reset configuration of ADC common register CCR:
<> 144:ef7eb2e8f9f7 961 - clock mode: CKMODE
<> 144:ef7eb2e8f9f7 962 - multimode related parameters: MDMA, DMACFG, DELAY, MULTI (set into
<> 144:ef7eb2e8f9f7 963 HAL_ADCEx_MultiModeConfigChannel() )
<> 144:ef7eb2e8f9f7 964 - internal measurement paths: Vbat, temperature sensor, Vref (set into
<> 144:ef7eb2e8f9f7 965 HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
<> 144:ef7eb2e8f9f7 966 */
<> 144:ef7eb2e8f9f7 967 CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_CKMODE |
<> 144:ef7eb2e8f9f7 968 ADC_CCR_VBATEN |
<> 144:ef7eb2e8f9f7 969 ADC_CCR_TSEN |
<> 144:ef7eb2e8f9f7 970 ADC_CCR_VREFEN |
<> 144:ef7eb2e8f9f7 971 ADC_CCR_MDMA |
<> 144:ef7eb2e8f9f7 972 ADC_CCR_DMACFG |
<> 144:ef7eb2e8f9f7 973 ADC_CCR_DELAY |
<> 144:ef7eb2e8f9f7 974 ADC_CCR_MULTI );
<> 144:ef7eb2e8f9f7 975
<> 144:ef7eb2e8f9f7 976 /* Other ADC common registers (CSR, CDR) are in access mode read only,
<> 144:ef7eb2e8f9f7 977 no direct reset applicable */
<> 144:ef7eb2e8f9f7 978 }
<> 144:ef7eb2e8f9f7 979
<> 144:ef7eb2e8f9f7 980
<> 144:ef7eb2e8f9f7 981 /* ========== Hard reset and clock disable of ADC peripheral ========== */
<> 144:ef7eb2e8f9f7 982 /* Into HAL_ADC_MspDeInit(), ADC clock can be hard reset and disabled */
<> 144:ef7eb2e8f9f7 983 /* at RCC top level. */
<> 144:ef7eb2e8f9f7 984 /* Refer to header of this file for more details on clock disabling */
<> 144:ef7eb2e8f9f7 985 /* procedure. */
<> 144:ef7eb2e8f9f7 986
<> 144:ef7eb2e8f9f7 987
<> 144:ef7eb2e8f9f7 988 /* DeInit the low level hardware */
<> 144:ef7eb2e8f9f7 989 HAL_ADC_MspDeInit(hadc);
<> 144:ef7eb2e8f9f7 990
<> 144:ef7eb2e8f9f7 991 /* Set ADC error code to none */
<> 144:ef7eb2e8f9f7 992 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 993
<> 144:ef7eb2e8f9f7 994 /* Set ADC state */
<> 144:ef7eb2e8f9f7 995 hadc->State = HAL_ADC_STATE_RESET;
<> 144:ef7eb2e8f9f7 996 }
<> 144:ef7eb2e8f9f7 997
<> 144:ef7eb2e8f9f7 998 /* Process unlocked */
<> 144:ef7eb2e8f9f7 999 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1000
<> 144:ef7eb2e8f9f7 1001
<> 144:ef7eb2e8f9f7 1002 /* Return function status */
<> 144:ef7eb2e8f9f7 1003 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 1004 }
<> 144:ef7eb2e8f9f7 1005 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 1006 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 1007 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 1008 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 1011 /**
<> 144:ef7eb2e8f9f7 1012 * @brief Deinitialize the ADC peripheral registers to its default reset values.
<> 144:ef7eb2e8f9f7 1013 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1014 * @retval HAL status
<> 144:ef7eb2e8f9f7 1015 */
<> 144:ef7eb2e8f9f7 1016 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1017 {
<> 144:ef7eb2e8f9f7 1018 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 1019
<> 144:ef7eb2e8f9f7 1020 /* Check ADC handle */
<> 144:ef7eb2e8f9f7 1021 if(hadc == NULL)
<> 144:ef7eb2e8f9f7 1022 {
<> 144:ef7eb2e8f9f7 1023 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1024 }
<> 144:ef7eb2e8f9f7 1025
<> 144:ef7eb2e8f9f7 1026 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1027 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1028
<> 144:ef7eb2e8f9f7 1029 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1030 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
<> 144:ef7eb2e8f9f7 1031
<> 144:ef7eb2e8f9f7 1032 /* Stop potential conversion on going, on regular and injected groups */
<> 144:ef7eb2e8f9f7 1033 /* Disable ADC peripheral */
<> 144:ef7eb2e8f9f7 1034 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
<> 144:ef7eb2e8f9f7 1035
<> 144:ef7eb2e8f9f7 1036
<> 144:ef7eb2e8f9f7 1037 /* Configuration of ADC parameters if previous preliminary actions are */
<> 144:ef7eb2e8f9f7 1038 /* correctly completed. */
<> 144:ef7eb2e8f9f7 1039 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1040 {
<> 144:ef7eb2e8f9f7 1041 /* ========== Reset ADC registers ========== */
<> 144:ef7eb2e8f9f7 1042 /* Reset register SR */
<> 144:ef7eb2e8f9f7 1043 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC |
<> 144:ef7eb2e8f9f7 1044 ADC_FLAG_JSTRT | ADC_FLAG_STRT));
<> 144:ef7eb2e8f9f7 1045
<> 144:ef7eb2e8f9f7 1046 /* Reset register CR1 */
<> 144:ef7eb2e8f9f7 1047 CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM |
<> 144:ef7eb2e8f9f7 1048 ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO |
<> 144:ef7eb2e8f9f7 1049 ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE |
<> 144:ef7eb2e8f9f7 1050 ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH ));
<> 144:ef7eb2e8f9f7 1051
<> 144:ef7eb2e8f9f7 1052 /* Reset register CR2 */
<> 144:ef7eb2e8f9f7 1053 CLEAR_BIT(hadc->Instance->CR2, (ADC_CR2_TSVREFE | ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
<> 144:ef7eb2e8f9f7 1054 ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL | ADC_CR2_JEXTTRIG |
<> 144:ef7eb2e8f9f7 1055 ADC_CR2_JEXTSEL | ADC_CR2_ALIGN | ADC_CR2_DMA |
<> 144:ef7eb2e8f9f7 1056 ADC_CR2_RSTCAL | ADC_CR2_CAL | ADC_CR2_CONT |
<> 144:ef7eb2e8f9f7 1057 ADC_CR2_ADON ));
<> 144:ef7eb2e8f9f7 1058
<> 144:ef7eb2e8f9f7 1059 /* Reset register SMPR1 */
<> 144:ef7eb2e8f9f7 1060 CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP15 |
<> 144:ef7eb2e8f9f7 1061 ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 |
<> 144:ef7eb2e8f9f7 1062 ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10 ));
<> 144:ef7eb2e8f9f7 1063
<> 144:ef7eb2e8f9f7 1064 /* Reset register SMPR2 */
<> 144:ef7eb2e8f9f7 1065 CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP9 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 |
<> 144:ef7eb2e8f9f7 1066 ADC_SMPR2_SMP6 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 |
<> 144:ef7eb2e8f9f7 1067 ADC_SMPR2_SMP3 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 |
<> 144:ef7eb2e8f9f7 1068 ADC_SMPR2_SMP0 ));
<> 144:ef7eb2e8f9f7 1069
<> 144:ef7eb2e8f9f7 1070 /* Reset register JOFR1 */
<> 144:ef7eb2e8f9f7 1071 CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1);
<> 144:ef7eb2e8f9f7 1072 /* Reset register JOFR2 */
<> 144:ef7eb2e8f9f7 1073 CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2);
<> 144:ef7eb2e8f9f7 1074 /* Reset register JOFR3 */
<> 144:ef7eb2e8f9f7 1075 CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3);
<> 144:ef7eb2e8f9f7 1076 /* Reset register JOFR4 */
<> 144:ef7eb2e8f9f7 1077 CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4);
<> 144:ef7eb2e8f9f7 1078
<> 144:ef7eb2e8f9f7 1079 /* Reset register HTR */
<> 144:ef7eb2e8f9f7 1080 CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT);
<> 144:ef7eb2e8f9f7 1081 /* Reset register LTR */
<> 144:ef7eb2e8f9f7 1082 CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT);
<> 144:ef7eb2e8f9f7 1083
<> 144:ef7eb2e8f9f7 1084 /* Reset register SQR1 */
<> 144:ef7eb2e8f9f7 1085 CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L |
<> 144:ef7eb2e8f9f7 1086 ADC_SQR1_SQ16 | ADC_SQR1_SQ15 |
<> 144:ef7eb2e8f9f7 1087 ADC_SQR1_SQ14 | ADC_SQR1_SQ13 );
<> 144:ef7eb2e8f9f7 1088
<> 144:ef7eb2e8f9f7 1089 /* Reset register SQR1 */
<> 144:ef7eb2e8f9f7 1090 CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L |
<> 144:ef7eb2e8f9f7 1091 ADC_SQR1_SQ16 | ADC_SQR1_SQ15 |
<> 144:ef7eb2e8f9f7 1092 ADC_SQR1_SQ14 | ADC_SQR1_SQ13 );
<> 144:ef7eb2e8f9f7 1093
<> 144:ef7eb2e8f9f7 1094 /* Reset register SQR2 */
<> 144:ef7eb2e8f9f7 1095 CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 |
<> 144:ef7eb2e8f9f7 1096 ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 );
<> 144:ef7eb2e8f9f7 1097
<> 144:ef7eb2e8f9f7 1098 /* Reset register SQR3 */
<> 144:ef7eb2e8f9f7 1099 CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 |
<> 144:ef7eb2e8f9f7 1100 ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1 );
<> 144:ef7eb2e8f9f7 1101
<> 144:ef7eb2e8f9f7 1102 /* Reset register JSQR */
<> 144:ef7eb2e8f9f7 1103 CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL |
<> 144:ef7eb2e8f9f7 1104 ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
<> 144:ef7eb2e8f9f7 1105 ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 );
<> 144:ef7eb2e8f9f7 1106
<> 144:ef7eb2e8f9f7 1107 /* Reset register JSQR */
<> 144:ef7eb2e8f9f7 1108 CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL |
<> 144:ef7eb2e8f9f7 1109 ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
<> 144:ef7eb2e8f9f7 1110 ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 );
<> 144:ef7eb2e8f9f7 1111
<> 144:ef7eb2e8f9f7 1112 /* Reset register DR */
<> 144:ef7eb2e8f9f7 1113 /* bits in access mode read only, no direct reset applicable*/
<> 144:ef7eb2e8f9f7 1114
<> 144:ef7eb2e8f9f7 1115 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
<> 144:ef7eb2e8f9f7 1116 /* bits in access mode read only, no direct reset applicable*/
<> 144:ef7eb2e8f9f7 1117
<> 144:ef7eb2e8f9f7 1118 /* Reset VBAT measurement path, in case of enabled before by selecting */
<> 144:ef7eb2e8f9f7 1119 /* channel ADC_CHANNEL_VBAT. */
<> 144:ef7eb2e8f9f7 1120 SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT);
<> 144:ef7eb2e8f9f7 1121
<> 144:ef7eb2e8f9f7 1122
<> 144:ef7eb2e8f9f7 1123 /* ========== Hard reset ADC peripheral ========== */
<> 144:ef7eb2e8f9f7 1124 /* Performs a global reset of the entire ADC peripheral: ADC state is */
<> 144:ef7eb2e8f9f7 1125 /* forced to a similar state after device power-on. */
<> 144:ef7eb2e8f9f7 1126 /* If needed, copy-paste and uncomment the following reset code into */
<> 144:ef7eb2e8f9f7 1127 /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */
<> 144:ef7eb2e8f9f7 1128 /* */
<> 144:ef7eb2e8f9f7 1129 /* __HAL_RCC_ADC1_FORCE_RESET() */
<> 144:ef7eb2e8f9f7 1130 /* __HAL_RCC_ADC1_RELEASE_RESET() */
<> 144:ef7eb2e8f9f7 1131
<> 144:ef7eb2e8f9f7 1132 /* DeInit the low level hardware */
<> 144:ef7eb2e8f9f7 1133 HAL_ADC_MspDeInit(hadc);
<> 144:ef7eb2e8f9f7 1134
<> 144:ef7eb2e8f9f7 1135 /* Set ADC error code to none */
<> 144:ef7eb2e8f9f7 1136 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 1137
<> 144:ef7eb2e8f9f7 1138 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1139 hadc->State = HAL_ADC_STATE_RESET;
<> 144:ef7eb2e8f9f7 1140
<> 144:ef7eb2e8f9f7 1141 }
<> 144:ef7eb2e8f9f7 1142
<> 144:ef7eb2e8f9f7 1143 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1144 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1145
<> 144:ef7eb2e8f9f7 1146 /* Return function status */
<> 144:ef7eb2e8f9f7 1147 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 1148 }
<> 144:ef7eb2e8f9f7 1149 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 1150
<> 144:ef7eb2e8f9f7 1151 /**
<> 144:ef7eb2e8f9f7 1152 * @}
<> 144:ef7eb2e8f9f7 1153 */
<> 144:ef7eb2e8f9f7 1154
<> 144:ef7eb2e8f9f7 1155 /** @defgroup ADCEx_Exported_Functions_Group2 ADCEx Input and Output operation functions
<> 144:ef7eb2e8f9f7 1156 * @brief ADC Extended IO operation functions
<> 144:ef7eb2e8f9f7 1157 *
<> 144:ef7eb2e8f9f7 1158 @verbatim
<> 144:ef7eb2e8f9f7 1159 ===============================================================================
<> 144:ef7eb2e8f9f7 1160 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 1161 ===============================================================================
<> 144:ef7eb2e8f9f7 1162 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1163 (+) Start conversion of regular group.
<> 144:ef7eb2e8f9f7 1164 (+) Stop conversion of regular group.
<> 144:ef7eb2e8f9f7 1165 (+) Poll for conversion complete on regular group.
<> 144:ef7eb2e8f9f7 1166 (+) Poll for conversion event.
<> 144:ef7eb2e8f9f7 1167 (+) Get result of regular channel conversion.
<> 144:ef7eb2e8f9f7 1168 (+) Start conversion of regular group and enable interruptions.
<> 144:ef7eb2e8f9f7 1169 (+) Stop conversion of regular group and disable interruptions.
<> 144:ef7eb2e8f9f7 1170 (+) Handle ADC interrupt request
<> 144:ef7eb2e8f9f7 1171 (+) Start conversion of regular group and enable DMA transfer.
<> 144:ef7eb2e8f9f7 1172 (+) Stop conversion of regular group and disable ADC DMA transfer.
<> 144:ef7eb2e8f9f7 1173
<> 144:ef7eb2e8f9f7 1174 (+) Start conversion of injected group.
<> 144:ef7eb2e8f9f7 1175 (+) Stop conversion of injected group.
<> 144:ef7eb2e8f9f7 1176 (+) Poll for conversion complete on injected group.
<> 144:ef7eb2e8f9f7 1177 (+) Get result of injected channel conversion.
<> 144:ef7eb2e8f9f7 1178 (+) Start conversion of injected group and enable interruptions.
<> 144:ef7eb2e8f9f7 1179 (+) Stop conversion of injected group and disable interruptions.
<> 144:ef7eb2e8f9f7 1180
<> 144:ef7eb2e8f9f7 1181 (+) Start multimode and enable DMA transfer.
<> 144:ef7eb2e8f9f7 1182 (+) Stop multimode and disable ADC DMA transfer.
<> 144:ef7eb2e8f9f7 1183 (+) Get result of multimode conversion.
<> 144:ef7eb2e8f9f7 1184
<> 144:ef7eb2e8f9f7 1185 (+) Perform the ADC self-calibration for single or differential ending.
<> 144:ef7eb2e8f9f7 1186 (+) Get calibration factors for single or differential ending.
<> 144:ef7eb2e8f9f7 1187 (+) Set calibration factors for single or differential ending.
<> 144:ef7eb2e8f9f7 1188
<> 144:ef7eb2e8f9f7 1189 @endverbatim
<> 144:ef7eb2e8f9f7 1190 * @{
<> 144:ef7eb2e8f9f7 1191 */
<> 144:ef7eb2e8f9f7 1192
<> 144:ef7eb2e8f9f7 1193 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 1194 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 1195 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 1196 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 1197 /**
<> 144:ef7eb2e8f9f7 1198 * @brief Enables ADC, starts conversion of regular group.
<> 144:ef7eb2e8f9f7 1199 * Interruptions enabled in this function: None.
<> 144:ef7eb2e8f9f7 1200 * @note Case of multimode enabled (for devices with several ADCs):
<> 144:ef7eb2e8f9f7 1201 * if ADC is slave, ADC is enabled only (conversion is not started).
<> 144:ef7eb2e8f9f7 1202 * if ADC is master, ADC is enabled and multimode conversion is started.
<> 144:ef7eb2e8f9f7 1203 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1204 * @retval HAL status
<> 144:ef7eb2e8f9f7 1205 */
<> 144:ef7eb2e8f9f7 1206 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1207 {
<> 144:ef7eb2e8f9f7 1208 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 1209
<> 144:ef7eb2e8f9f7 1210 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1211 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1212
<> 144:ef7eb2e8f9f7 1213 /* Perform ADC enable and conversion start if no conversion is on going */
<> 144:ef7eb2e8f9f7 1214 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<> 144:ef7eb2e8f9f7 1215 {
<> 144:ef7eb2e8f9f7 1216 /* Process locked */
<> 144:ef7eb2e8f9f7 1217 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 1218
<> 144:ef7eb2e8f9f7 1219 /* Enable the ADC peripheral */
<> 144:ef7eb2e8f9f7 1220 tmp_hal_status = ADC_Enable(hadc);
<> 144:ef7eb2e8f9f7 1221
<> 144:ef7eb2e8f9f7 1222 /* Start conversion if ADC is effectively enabled */
<> 144:ef7eb2e8f9f7 1223 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1224 {
<> 144:ef7eb2e8f9f7 1225 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1226 /* - Clear state bitfield related to regular group conversion results */
<> 144:ef7eb2e8f9f7 1227 /* - Set state bitfield related to regular operation */
<> 144:ef7eb2e8f9f7 1228 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 1229 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
<> 144:ef7eb2e8f9f7 1230 HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 1231
<> 144:ef7eb2e8f9f7 1232 /* Set group injected state (from auto-injection) and multimode state */
<> 144:ef7eb2e8f9f7 1233 /* for all cases of multimode: independent mode, multimode ADC master */
<> 144:ef7eb2e8f9f7 1234 /* or multimode ADC slave (for devices with several ADCs): */
<> 144:ef7eb2e8f9f7 1235 if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
<> 144:ef7eb2e8f9f7 1236 {
<> 144:ef7eb2e8f9f7 1237 /* Set ADC state (ADC independent or master) */
<> 144:ef7eb2e8f9f7 1238 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<> 144:ef7eb2e8f9f7 1239
<> 144:ef7eb2e8f9f7 1240 /* If conversions on group regular are also triggering group injected,*/
<> 144:ef7eb2e8f9f7 1241 /* update ADC state. */
<> 144:ef7eb2e8f9f7 1242 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
<> 144:ef7eb2e8f9f7 1243 {
<> 144:ef7eb2e8f9f7 1244 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 1245 }
<> 144:ef7eb2e8f9f7 1246 }
<> 144:ef7eb2e8f9f7 1247 else
<> 144:ef7eb2e8f9f7 1248 {
<> 144:ef7eb2e8f9f7 1249 /* Set ADC state (ADC slave) */
<> 144:ef7eb2e8f9f7 1250 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<> 144:ef7eb2e8f9f7 1251
<> 144:ef7eb2e8f9f7 1252 /* If conversions on group regular are also triggering group injected,*/
<> 144:ef7eb2e8f9f7 1253 /* update ADC state. */
<> 144:ef7eb2e8f9f7 1254 if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
<> 144:ef7eb2e8f9f7 1255 {
<> 144:ef7eb2e8f9f7 1256 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 1257 }
<> 144:ef7eb2e8f9f7 1258 }
<> 144:ef7eb2e8f9f7 1259
<> 144:ef7eb2e8f9f7 1260 /* State machine update: Check if an injected conversion is ongoing */
<> 144:ef7eb2e8f9f7 1261 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<> 144:ef7eb2e8f9f7 1262 {
<> 144:ef7eb2e8f9f7 1263 /* Reset ADC error code fields related to conversions on group regular*/
<> 144:ef7eb2e8f9f7 1264 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
<> 144:ef7eb2e8f9f7 1265 }
<> 144:ef7eb2e8f9f7 1266 else
<> 144:ef7eb2e8f9f7 1267 {
<> 144:ef7eb2e8f9f7 1268 /* Reset ADC all error code fields */
<> 144:ef7eb2e8f9f7 1269 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 1270 }
<> 144:ef7eb2e8f9f7 1271
<> 144:ef7eb2e8f9f7 1272 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1273 /* Unlock before starting ADC conversions: in case of potential */
<> 144:ef7eb2e8f9f7 1274 /* interruption, to let the process to ADC IRQ Handler. */
<> 144:ef7eb2e8f9f7 1275 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1276
<> 144:ef7eb2e8f9f7 1277 /* Clear regular group conversion flag and overrun flag */
<> 144:ef7eb2e8f9f7 1278 /* (To ensure of no unknown state from potential previous ADC */
<> 144:ef7eb2e8f9f7 1279 /* operations) */
<> 144:ef7eb2e8f9f7 1280 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
<> 144:ef7eb2e8f9f7 1281
<> 144:ef7eb2e8f9f7 1282 /* Enable conversion of regular group. */
<> 144:ef7eb2e8f9f7 1283 /* If software start has been selected, conversion starts immediately. */
<> 144:ef7eb2e8f9f7 1284 /* If external trigger has been selected, conversion will start at next */
<> 144:ef7eb2e8f9f7 1285 /* trigger event. */
<> 144:ef7eb2e8f9f7 1286 /* Case of multimode enabled (for devices with several ADCs): */
<> 144:ef7eb2e8f9f7 1287 /* - if ADC is slave, ADC is enabled only (conversion is not started). */
<> 144:ef7eb2e8f9f7 1288 /* - if ADC is master, ADC is enabled and conversion is started. */
<> 144:ef7eb2e8f9f7 1289 if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
<> 144:ef7eb2e8f9f7 1290 {
<> 144:ef7eb2e8f9f7 1291 SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
<> 144:ef7eb2e8f9f7 1292 }
<> 144:ef7eb2e8f9f7 1293 }
<> 144:ef7eb2e8f9f7 1294 else
<> 144:ef7eb2e8f9f7 1295 {
<> 144:ef7eb2e8f9f7 1296 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1297 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1298 }
<> 144:ef7eb2e8f9f7 1299 }
<> 144:ef7eb2e8f9f7 1300 else
<> 144:ef7eb2e8f9f7 1301 {
<> 144:ef7eb2e8f9f7 1302 tmp_hal_status = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1303 }
<> 144:ef7eb2e8f9f7 1304
<> 144:ef7eb2e8f9f7 1305 /* Return function status */
<> 144:ef7eb2e8f9f7 1306 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 1307 }
<> 144:ef7eb2e8f9f7 1308 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 1309 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 1310 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 1311 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 1312
<> 144:ef7eb2e8f9f7 1313 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 1314 /**
<> 144:ef7eb2e8f9f7 1315 * @brief Enables ADC, starts conversion of regular group.
<> 144:ef7eb2e8f9f7 1316 * Interruptions enabled in this function: None.
<> 144:ef7eb2e8f9f7 1317 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1318 * @retval HAL status
<> 144:ef7eb2e8f9f7 1319 */
<> 144:ef7eb2e8f9f7 1320 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1321 {
<> 144:ef7eb2e8f9f7 1322 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 1323
<> 144:ef7eb2e8f9f7 1324 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1325 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1326
<> 144:ef7eb2e8f9f7 1327 /* Process locked */
<> 144:ef7eb2e8f9f7 1328 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 1329
<> 144:ef7eb2e8f9f7 1330 /* Enable the ADC peripheral */
<> 144:ef7eb2e8f9f7 1331 tmp_hal_status = ADC_Enable(hadc);
<> 144:ef7eb2e8f9f7 1332
<> 144:ef7eb2e8f9f7 1333 /* Start conversion if ADC is effectively enabled */
<> 144:ef7eb2e8f9f7 1334 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1335 {
<> 144:ef7eb2e8f9f7 1336 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1337 /* - Clear state bitfield related to regular group conversion results */
<> 144:ef7eb2e8f9f7 1338 /* - Set state bitfield related to regular operation */
<> 144:ef7eb2e8f9f7 1339 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 1340 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC,
<> 144:ef7eb2e8f9f7 1341 HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 1342
<> 144:ef7eb2e8f9f7 1343 /* Set group injected state (from auto-injection) */
<> 144:ef7eb2e8f9f7 1344 /* If conversions on group regular are also triggering group injected, */
<> 144:ef7eb2e8f9f7 1345 /* update ADC state. */
<> 144:ef7eb2e8f9f7 1346 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
<> 144:ef7eb2e8f9f7 1347 {
<> 144:ef7eb2e8f9f7 1348 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 1349 }
<> 144:ef7eb2e8f9f7 1350
<> 144:ef7eb2e8f9f7 1351 /* State machine update: Check if an injected conversion is ongoing */
<> 144:ef7eb2e8f9f7 1352 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<> 144:ef7eb2e8f9f7 1353 {
<> 144:ef7eb2e8f9f7 1354 /* Reset ADC error code fields related to conversions on group regular */
<> 144:ef7eb2e8f9f7 1355 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
<> 144:ef7eb2e8f9f7 1356 }
<> 144:ef7eb2e8f9f7 1357 else
<> 144:ef7eb2e8f9f7 1358 {
<> 144:ef7eb2e8f9f7 1359 /* Reset ADC all error code fields */
<> 144:ef7eb2e8f9f7 1360 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 1361 }
<> 144:ef7eb2e8f9f7 1362
<> 144:ef7eb2e8f9f7 1363 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1364 /* Unlock before starting ADC conversions: in case of potential */
<> 144:ef7eb2e8f9f7 1365 /* interruption, to let the process to ADC IRQ Handler. */
<> 144:ef7eb2e8f9f7 1366 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1367
<> 144:ef7eb2e8f9f7 1368 /* Clear regular group conversion flag and overrun flag */
<> 144:ef7eb2e8f9f7 1369 /* (To ensure of no unknown state from potential previous ADC operations) */
<> 144:ef7eb2e8f9f7 1370 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
<> 144:ef7eb2e8f9f7 1371
<> 144:ef7eb2e8f9f7 1372 /* Enable conversion of regular group. */
<> 144:ef7eb2e8f9f7 1373 /* If software start has been selected, conversion starts immediately. */
<> 144:ef7eb2e8f9f7 1374 /* If external trigger has been selected, conversion will start at next */
<> 144:ef7eb2e8f9f7 1375 /* trigger event. */
<> 144:ef7eb2e8f9f7 1376 /* Note: Alternate trigger for single conversion could be to force an */
<> 144:ef7eb2e8f9f7 1377 /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
<> 144:ef7eb2e8f9f7 1378 if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
<> 144:ef7eb2e8f9f7 1379 {
<> 144:ef7eb2e8f9f7 1380 /* Start ADC conversion on regular group with SW start */
<> 144:ef7eb2e8f9f7 1381 SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
<> 144:ef7eb2e8f9f7 1382 }
<> 144:ef7eb2e8f9f7 1383 else
<> 144:ef7eb2e8f9f7 1384 {
<> 144:ef7eb2e8f9f7 1385 /* Start ADC conversion on regular group with external trigger */
<> 144:ef7eb2e8f9f7 1386 SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
<> 144:ef7eb2e8f9f7 1387 }
<> 144:ef7eb2e8f9f7 1388 }
<> 144:ef7eb2e8f9f7 1389
<> 144:ef7eb2e8f9f7 1390 /* Return function status */
<> 144:ef7eb2e8f9f7 1391 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 1392 }
<> 144:ef7eb2e8f9f7 1393 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 1394
<> 144:ef7eb2e8f9f7 1395 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 1396 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 1397 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 1398 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 1399 /**
<> 144:ef7eb2e8f9f7 1400 * @brief Stop ADC conversion of both groups regular and injected,
<> 144:ef7eb2e8f9f7 1401 * disable ADC peripheral.
<> 144:ef7eb2e8f9f7 1402 * @note ADC peripheral disable is forcing interruption of potential
<> 144:ef7eb2e8f9f7 1403 * conversion on injected group. If injected group is under use,
<> 144:ef7eb2e8f9f7 1404 * it should be preliminarily stopped using function
<> 144:ef7eb2e8f9f7 1405 * @ref HAL_ADCEx_InjectedStop().
<> 144:ef7eb2e8f9f7 1406 * To stop ADC conversion only on ADC group regular
<> 144:ef7eb2e8f9f7 1407 * while letting ADC group injected conversions running,
<> 144:ef7eb2e8f9f7 1408 * use function @ref HAL_ADCEx_RegularStop().
<> 144:ef7eb2e8f9f7 1409 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1410 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1411 */
<> 144:ef7eb2e8f9f7 1412 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1413 {
<> 144:ef7eb2e8f9f7 1414 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 1415
<> 144:ef7eb2e8f9f7 1416 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1417 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1418
<> 144:ef7eb2e8f9f7 1419 /* Process locked */
<> 144:ef7eb2e8f9f7 1420 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 1421
<> 144:ef7eb2e8f9f7 1422 /* 1. Stop potential conversion on going, on regular and injected groups */
<> 144:ef7eb2e8f9f7 1423 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
<> 144:ef7eb2e8f9f7 1424
<> 144:ef7eb2e8f9f7 1425 /* Disable ADC peripheral if conversions are effectively stopped */
<> 144:ef7eb2e8f9f7 1426 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1427 {
<> 144:ef7eb2e8f9f7 1428 /* 2. Disable the ADC peripheral */
<> 144:ef7eb2e8f9f7 1429 tmp_hal_status = ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 1430
<> 144:ef7eb2e8f9f7 1431 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 1432 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1433 {
<> 144:ef7eb2e8f9f7 1434 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1435 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 1436 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 144:ef7eb2e8f9f7 1437 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 1438 }
<> 144:ef7eb2e8f9f7 1439 }
<> 144:ef7eb2e8f9f7 1440
<> 144:ef7eb2e8f9f7 1441 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1442 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1443
<> 144:ef7eb2e8f9f7 1444 /* Return function status */
<> 144:ef7eb2e8f9f7 1445 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 1446 }
<> 144:ef7eb2e8f9f7 1447 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 1448 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 1449 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 1450 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 1451
<> 144:ef7eb2e8f9f7 1452 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 1453 /**
<> 144:ef7eb2e8f9f7 1454 * @brief Stop ADC conversion of regular group (and injected channels in
<> 144:ef7eb2e8f9f7 1455 * case of auto_injection mode), disable ADC peripheral.
<> 144:ef7eb2e8f9f7 1456 * @note ADC peripheral disable is forcing interruption of potential
<> 144:ef7eb2e8f9f7 1457 * conversion on injected group. If injected group is under use, it
<> 144:ef7eb2e8f9f7 1458 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
<> 144:ef7eb2e8f9f7 1459 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1460 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1461 */
<> 144:ef7eb2e8f9f7 1462 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1463 {
<> 144:ef7eb2e8f9f7 1464 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 1465
<> 144:ef7eb2e8f9f7 1466 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1467 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1468
<> 144:ef7eb2e8f9f7 1469 /* Process locked */
<> 144:ef7eb2e8f9f7 1470 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 1471
<> 144:ef7eb2e8f9f7 1472 /* Stop potential conversion on going, on regular and injected groups */
<> 144:ef7eb2e8f9f7 1473 /* Disable ADC peripheral */
<> 144:ef7eb2e8f9f7 1474 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
<> 144:ef7eb2e8f9f7 1475
<> 144:ef7eb2e8f9f7 1476 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 1477 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1478 {
<> 144:ef7eb2e8f9f7 1479 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1480 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 1481 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 144:ef7eb2e8f9f7 1482 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 1483 }
<> 144:ef7eb2e8f9f7 1484
<> 144:ef7eb2e8f9f7 1485 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1486 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1487
<> 144:ef7eb2e8f9f7 1488 /* Return function status */
<> 144:ef7eb2e8f9f7 1489 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 1490 }
<> 144:ef7eb2e8f9f7 1491 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 1492
<> 144:ef7eb2e8f9f7 1493 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 1494 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 1495 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 1496 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 1497 /**
<> 144:ef7eb2e8f9f7 1498 * @brief Wait for regular group conversion to be completed.
<> 144:ef7eb2e8f9f7 1499 * @note ADC conversion flags EOS (end of sequence) and EOC (end of
<> 144:ef7eb2e8f9f7 1500 * conversion) are cleared by this function, with an exception:
<> 144:ef7eb2e8f9f7 1501 * if low power feature "LowPowerAutoWait" is enabled, flags are
<> 144:ef7eb2e8f9f7 1502 * not cleared to not interfere with this feature until data register
<> 144:ef7eb2e8f9f7 1503 * is read using function HAL_ADC_GetValue().
<> 144:ef7eb2e8f9f7 1504 * @note This function cannot be used in a particular setup: ADC configured
<> 144:ef7eb2e8f9f7 1505 * in DMA mode and polling for end of each conversion (ADC init
<> 144:ef7eb2e8f9f7 1506 * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
<> 144:ef7eb2e8f9f7 1507 * In this case, DMA resets the flag EOC and polling cannot be
<> 144:ef7eb2e8f9f7 1508 * performed on each conversion. Nevertheless, polling can still
<> 144:ef7eb2e8f9f7 1509 * be performed on the complete sequence (ADC init
<> 144:ef7eb2e8f9f7 1510 * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
<> 144:ef7eb2e8f9f7 1511 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1512 * @param Timeout: Timeout value in millisecond.
<> 144:ef7eb2e8f9f7 1513 * @note Depending on init parameter "EOCSelection", flags EOS or EOC is
<> 144:ef7eb2e8f9f7 1514 * checked and cleared depending on autodelay status (bit AUTDLY).
<> 144:ef7eb2e8f9f7 1515 * @retval HAL status
<> 144:ef7eb2e8f9f7 1516 */
<> 144:ef7eb2e8f9f7 1517 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1518 {
<> 144:ef7eb2e8f9f7 1519 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 1520 uint32_t tmp_Flag_EOC;
<> 144:ef7eb2e8f9f7 1521 ADC_Common_TypeDef *tmpADC_Common;
<> 144:ef7eb2e8f9f7 1522 uint32_t tmp_cfgr = 0x0;
<> 144:ef7eb2e8f9f7 1523
<> 144:ef7eb2e8f9f7 1524 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1525 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1526
<> 144:ef7eb2e8f9f7 1527 /* If end of conversion selected to end of sequence */
<> 144:ef7eb2e8f9f7 1528 if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
<> 144:ef7eb2e8f9f7 1529 {
<> 144:ef7eb2e8f9f7 1530 tmp_Flag_EOC = ADC_FLAG_EOS;
<> 144:ef7eb2e8f9f7 1531 }
<> 144:ef7eb2e8f9f7 1532 /* If end of conversion selected to end of each conversion */
<> 144:ef7eb2e8f9f7 1533 else /* ADC_EOC_SINGLE_CONV */
<> 144:ef7eb2e8f9f7 1534 {
<> 144:ef7eb2e8f9f7 1535 /* Verification that ADC configuration is compliant with polling for */
<> 144:ef7eb2e8f9f7 1536 /* each conversion: */
<> 144:ef7eb2e8f9f7 1537 /* Particular case is ADC configured in DMA mode and ADC sequencer with */
<> 144:ef7eb2e8f9f7 1538 /* several ranks and polling for end of each conversion. */
<> 144:ef7eb2e8f9f7 1539 /* For code simplicity sake, this particular case is generalized to */
<> 144:ef7eb2e8f9f7 1540 /* ADC configured in DMA mode and and polling for end of each conversion. */
<> 144:ef7eb2e8f9f7 1541
<> 144:ef7eb2e8f9f7 1542 /* Pointer to the common control register to which is belonging hadc */
<> 144:ef7eb2e8f9f7 1543 /* (Depending on STM32F3 product, there may have up to 4 ADC and 2 common */
<> 144:ef7eb2e8f9f7 1544 /* control registers) */
<> 144:ef7eb2e8f9f7 1545 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
<> 144:ef7eb2e8f9f7 1546
<> 144:ef7eb2e8f9f7 1547 /* Check DMA configuration, depending on MultiMode set or not */
<> 144:ef7eb2e8f9f7 1548 if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI) == ADC_MODE_INDEPENDENT)
<> 144:ef7eb2e8f9f7 1549 {
<> 144:ef7eb2e8f9f7 1550 if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN))
<> 144:ef7eb2e8f9f7 1551 {
<> 144:ef7eb2e8f9f7 1552 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 1553 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 1554
<> 144:ef7eb2e8f9f7 1555 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1556 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1557
<> 144:ef7eb2e8f9f7 1558 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1559 }
<> 144:ef7eb2e8f9f7 1560 }
<> 144:ef7eb2e8f9f7 1561 else
<> 144:ef7eb2e8f9f7 1562 {
<> 144:ef7eb2e8f9f7 1563 /* MultiMode is enabled, Common Control Register MDMA bits must be checked */
<> 144:ef7eb2e8f9f7 1564 if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA) != RESET)
<> 144:ef7eb2e8f9f7 1565 {
<> 144:ef7eb2e8f9f7 1566 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 1567 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 1568
<> 144:ef7eb2e8f9f7 1569 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1570 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1571
<> 144:ef7eb2e8f9f7 1572 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1573 }
<> 144:ef7eb2e8f9f7 1574 }
<> 144:ef7eb2e8f9f7 1575
<> 144:ef7eb2e8f9f7 1576 tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS);
<> 144:ef7eb2e8f9f7 1577
<> 144:ef7eb2e8f9f7 1578 }
<> 144:ef7eb2e8f9f7 1579
<> 144:ef7eb2e8f9f7 1580 /* Get relevant register CFGR in ADC instance of ADC master or slave */
<> 144:ef7eb2e8f9f7 1581 /* in function of multimode state (for devices with multimode */
<> 144:ef7eb2e8f9f7 1582 /* available). */
<> 144:ef7eb2e8f9f7 1583 if(ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
<> 144:ef7eb2e8f9f7 1584 {
<> 144:ef7eb2e8f9f7 1585 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
<> 144:ef7eb2e8f9f7 1586 }
<> 144:ef7eb2e8f9f7 1587 else
<> 144:ef7eb2e8f9f7 1588 {
<> 144:ef7eb2e8f9f7 1589 tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
<> 144:ef7eb2e8f9f7 1590 }
<> 144:ef7eb2e8f9f7 1591
<> 144:ef7eb2e8f9f7 1592 /* Get tick count */
<> 144:ef7eb2e8f9f7 1593 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1594
<> 144:ef7eb2e8f9f7 1595 /* Wait until End of Conversion or End of Sequence flag is raised */
<> 144:ef7eb2e8f9f7 1596 while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
<> 144:ef7eb2e8f9f7 1597 {
<> 144:ef7eb2e8f9f7 1598 /* Check if timeout is disabled (set to infinite wait) */
<> 144:ef7eb2e8f9f7 1599 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1600 {
<> 144:ef7eb2e8f9f7 1601 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 1602 {
<> 144:ef7eb2e8f9f7 1603 /* Update ADC state machine to timeout */
<> 144:ef7eb2e8f9f7 1604 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
<> 144:ef7eb2e8f9f7 1605
<> 144:ef7eb2e8f9f7 1606 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1607 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1608
<> 144:ef7eb2e8f9f7 1609 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1610 }
<> 144:ef7eb2e8f9f7 1611 }
<> 144:ef7eb2e8f9f7 1612 }
<> 144:ef7eb2e8f9f7 1613
<> 144:ef7eb2e8f9f7 1614 /* Update ADC state machine */
<> 144:ef7eb2e8f9f7 1615 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
<> 144:ef7eb2e8f9f7 1616
<> 144:ef7eb2e8f9f7 1617 /* Determine whether any further conversion upcoming on group regular */
<> 144:ef7eb2e8f9f7 1618 /* by external trigger, continuous mode or scan sequence on going. */
<> 144:ef7eb2e8f9f7 1619 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 144:ef7eb2e8f9f7 1620 (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) )
<> 144:ef7eb2e8f9f7 1621 {
<> 144:ef7eb2e8f9f7 1622 /* If End of Sequence is reached, disable interrupts */
<> 144:ef7eb2e8f9f7 1623 if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
<> 144:ef7eb2e8f9f7 1624 {
<> 144:ef7eb2e8f9f7 1625 /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
<> 144:ef7eb2e8f9f7 1626 /* ADSTART==0 (no conversion on going) */
<> 144:ef7eb2e8f9f7 1627 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<> 144:ef7eb2e8f9f7 1628 {
<> 144:ef7eb2e8f9f7 1629 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1630 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 1631
<> 144:ef7eb2e8f9f7 1632 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<> 144:ef7eb2e8f9f7 1633 {
<> 144:ef7eb2e8f9f7 1634 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 1635 }
<> 144:ef7eb2e8f9f7 1636 }
<> 144:ef7eb2e8f9f7 1637 else
<> 144:ef7eb2e8f9f7 1638 {
<> 144:ef7eb2e8f9f7 1639 /* Change ADC state to error state */
<> 144:ef7eb2e8f9f7 1640 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 1641
<> 144:ef7eb2e8f9f7 1642 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 1643 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 1644 }
<> 144:ef7eb2e8f9f7 1645 }
<> 144:ef7eb2e8f9f7 1646 }
<> 144:ef7eb2e8f9f7 1647
<> 144:ef7eb2e8f9f7 1648 /* Clear end of conversion flag of regular group if low power feature */
<> 144:ef7eb2e8f9f7 1649 /* "LowPowerAutoWait " is disabled, to not interfere with this feature */
<> 144:ef7eb2e8f9f7 1650 /* until data register is read using function HAL_ADC_GetValue(). */
<> 144:ef7eb2e8f9f7 1651 if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET)
<> 144:ef7eb2e8f9f7 1652 {
<> 144:ef7eb2e8f9f7 1653 /* Clear regular group conversion flag */
<> 144:ef7eb2e8f9f7 1654 /* (EOC or EOS depending on HAL ADC initialization parameter) */
<> 144:ef7eb2e8f9f7 1655 __HAL_ADC_CLEAR_FLAG(hadc, tmp_Flag_EOC);
<> 144:ef7eb2e8f9f7 1656 }
<> 144:ef7eb2e8f9f7 1657
<> 144:ef7eb2e8f9f7 1658 /* Return ADC state */
<> 144:ef7eb2e8f9f7 1659 return HAL_OK;
<> 144:ef7eb2e8f9f7 1660 }
<> 144:ef7eb2e8f9f7 1661 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 1662 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 1663 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 1664 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 1665
<> 144:ef7eb2e8f9f7 1666 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 1667 /**
<> 144:ef7eb2e8f9f7 1668 * @brief Wait for regular group conversion to be completed.
<> 144:ef7eb2e8f9f7 1669 * @note This function cannot be used in a particular setup: ADC configured
<> 144:ef7eb2e8f9f7 1670 * in DMA mode.
<> 144:ef7eb2e8f9f7 1671 * In this case, DMA resets the flag EOC and polling cannot be
<> 144:ef7eb2e8f9f7 1672 * performed on each conversion.
<> 144:ef7eb2e8f9f7 1673 * @note On STM32F37x devices, limitation in case of sequencer enabled
<> 144:ef7eb2e8f9f7 1674 * (several ranks selected): polling cannot be done on each
<> 144:ef7eb2e8f9f7 1675 * conversion inside the sequence. In this case, polling is replaced by
<> 144:ef7eb2e8f9f7 1676 * wait for maximum conversion time.
<> 144:ef7eb2e8f9f7 1677 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1678 * @param Timeout: Timeout value in millisecond.
<> 144:ef7eb2e8f9f7 1679 * @retval HAL status
<> 144:ef7eb2e8f9f7 1680 */
<> 144:ef7eb2e8f9f7 1681 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1682 {
<> 144:ef7eb2e8f9f7 1683 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 1684
<> 144:ef7eb2e8f9f7 1685 /* Variables for polling in case of scan mode enabled */
<> 144:ef7eb2e8f9f7 1686 uint32_t Conversion_Timeout_CPU_cycles_max = 0;
<> 144:ef7eb2e8f9f7 1687 uint32_t Conversion_Timeout_CPU_cycles = 0;
<> 144:ef7eb2e8f9f7 1688
<> 144:ef7eb2e8f9f7 1689 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1690 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1691
<> 144:ef7eb2e8f9f7 1692 /* Verification that ADC configuration is compliant with polling for */
<> 144:ef7eb2e8f9f7 1693 /* each conversion: */
<> 144:ef7eb2e8f9f7 1694 /* Particular case is ADC configured in DMA mode */
<> 144:ef7eb2e8f9f7 1695 if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA))
<> 144:ef7eb2e8f9f7 1696 {
<> 144:ef7eb2e8f9f7 1697 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 1698 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 1699
<> 144:ef7eb2e8f9f7 1700 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1701 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1702
<> 144:ef7eb2e8f9f7 1703 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1704 }
<> 144:ef7eb2e8f9f7 1705
<> 144:ef7eb2e8f9f7 1706 /* Get tick count */
<> 144:ef7eb2e8f9f7 1707 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1708
<> 144:ef7eb2e8f9f7 1709 /* Polling for end of conversion: differentiation if single/sequence */
<> 144:ef7eb2e8f9f7 1710 /* conversion. */
<> 144:ef7eb2e8f9f7 1711 /* - If single conversion for regular group (Scan mode disabled or enabled */
<> 144:ef7eb2e8f9f7 1712 /* with NbrOfConversion =1), flag EOC is used to determine the */
<> 144:ef7eb2e8f9f7 1713 /* conversion completion. */
<> 144:ef7eb2e8f9f7 1714 /* - If sequence conversion for regular group (scan mode enabled and */
<> 144:ef7eb2e8f9f7 1715 /* NbrOfConversion >=2), flag EOC is set only at the end of the */
<> 144:ef7eb2e8f9f7 1716 /* sequence. */
<> 144:ef7eb2e8f9f7 1717 /* To poll for each conversion, the maximum conversion time is computed */
<> 144:ef7eb2e8f9f7 1718 /* from ADC conversion time (selected sampling time + conversion time of */
<> 144:ef7eb2e8f9f7 1719 /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */
<> 144:ef7eb2e8f9f7 1720 /* settings, conversion time range can be from 28 to 32256 CPU cycles). */
<> 144:ef7eb2e8f9f7 1721 /* As flag EOC is not set after each conversion, no timeout status can */
<> 144:ef7eb2e8f9f7 1722 /* be set. */
<> 144:ef7eb2e8f9f7 1723 if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) &&
<> 144:ef7eb2e8f9f7 1724 HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) )
<> 144:ef7eb2e8f9f7 1725 {
<> 144:ef7eb2e8f9f7 1726 /* Wait until End of Conversion flag is raised */
<> 144:ef7eb2e8f9f7 1727 while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
<> 144:ef7eb2e8f9f7 1728 {
<> 144:ef7eb2e8f9f7 1729 /* Check if timeout is disabled (set to infinite wait) */
<> 144:ef7eb2e8f9f7 1730 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1731 {
<> 144:ef7eb2e8f9f7 1732 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 1733 {
<> 144:ef7eb2e8f9f7 1734 /* Update ADC state machine to timeout */
<> 144:ef7eb2e8f9f7 1735 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
<> 144:ef7eb2e8f9f7 1736
<> 144:ef7eb2e8f9f7 1737 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1738 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1739
<> 144:ef7eb2e8f9f7 1740 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1741 }
<> 144:ef7eb2e8f9f7 1742 }
<> 144:ef7eb2e8f9f7 1743 }
<> 144:ef7eb2e8f9f7 1744 }
<> 144:ef7eb2e8f9f7 1745 else
<> 144:ef7eb2e8f9f7 1746 {
<> 144:ef7eb2e8f9f7 1747 /* Replace polling by wait for maximum conversion time */
<> 144:ef7eb2e8f9f7 1748 /* Calculation of CPU cycles corresponding to ADC conversion cycles. */
<> 144:ef7eb2e8f9f7 1749 /* Retrieve ADC clock prescaler and ADC maximum conversion cycles on all */
<> 144:ef7eb2e8f9f7 1750 /* channels. */
<> 144:ef7eb2e8f9f7 1751 Conversion_Timeout_CPU_cycles_max = ADC_CLOCK_PRESCALER_RANGE() ;
<> 144:ef7eb2e8f9f7 1752 Conversion_Timeout_CPU_cycles_max *= ADC_CONVCYCLES_MAX_RANGE(hadc);
<> 144:ef7eb2e8f9f7 1753
<> 144:ef7eb2e8f9f7 1754 /* Poll with maximum conversion time */
<> 144:ef7eb2e8f9f7 1755 while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
<> 144:ef7eb2e8f9f7 1756 {
<> 144:ef7eb2e8f9f7 1757 /* Check if timeout is disabled (set to infinite wait) */
<> 144:ef7eb2e8f9f7 1758 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1759 {
<> 144:ef7eb2e8f9f7 1760 if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1761 {
<> 144:ef7eb2e8f9f7 1762 /* Update ADC state machine to timeout */
<> 144:ef7eb2e8f9f7 1763 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
<> 144:ef7eb2e8f9f7 1764
<> 144:ef7eb2e8f9f7 1765 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1766 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1767
<> 144:ef7eb2e8f9f7 1768 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1769 }
<> 144:ef7eb2e8f9f7 1770 }
<> 144:ef7eb2e8f9f7 1771 Conversion_Timeout_CPU_cycles ++;
<> 144:ef7eb2e8f9f7 1772 }
<> 144:ef7eb2e8f9f7 1773 }
<> 144:ef7eb2e8f9f7 1774
<> 144:ef7eb2e8f9f7 1775 /* Clear regular group conversion flag */
<> 144:ef7eb2e8f9f7 1776 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
<> 144:ef7eb2e8f9f7 1777
<> 144:ef7eb2e8f9f7 1778 /* Update ADC state machine */
<> 144:ef7eb2e8f9f7 1779 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
<> 144:ef7eb2e8f9f7 1780
<> 144:ef7eb2e8f9f7 1781 /* Determine whether any further conversion upcoming on group regular */
<> 144:ef7eb2e8f9f7 1782 /* by external trigger, continuous mode or scan sequence on going. */
<> 144:ef7eb2e8f9f7 1783 /* Note: On STM32F37x devices, in case of sequencer enabled */
<> 144:ef7eb2e8f9f7 1784 /* (several ranks selected), end of conversion flag is raised */
<> 144:ef7eb2e8f9f7 1785 /* at the end of the sequence. */
<> 144:ef7eb2e8f9f7 1786 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 144:ef7eb2e8f9f7 1787 (hadc->Init.ContinuousConvMode == DISABLE) )
<> 144:ef7eb2e8f9f7 1788 {
<> 144:ef7eb2e8f9f7 1789 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1790 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 1791
<> 144:ef7eb2e8f9f7 1792 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<> 144:ef7eb2e8f9f7 1793 {
<> 144:ef7eb2e8f9f7 1794 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 1795 }
<> 144:ef7eb2e8f9f7 1796 }
<> 144:ef7eb2e8f9f7 1797
<> 144:ef7eb2e8f9f7 1798 /* Return ADC state */
<> 144:ef7eb2e8f9f7 1799 return HAL_OK;
<> 144:ef7eb2e8f9f7 1800 }
<> 144:ef7eb2e8f9f7 1801 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 1802
<> 144:ef7eb2e8f9f7 1803 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 1804 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 1805 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 1806 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 1807 /**
<> 144:ef7eb2e8f9f7 1808 * @brief Poll for conversion event.
<> 144:ef7eb2e8f9f7 1809 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1810 * @param EventType: the ADC event type.
<> 144:ef7eb2e8f9f7 1811 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1812 * @arg ADC_AWD1_EVENT: ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
<> 144:ef7eb2e8f9f7 1813 * @arg ADC_AWD2_EVENT: ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
<> 144:ef7eb2e8f9f7 1814 * @arg ADC_AWD3_EVENT: ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
<> 144:ef7eb2e8f9f7 1815 * @arg ADC_OVR_EVENT: ADC Overrun event
<> 144:ef7eb2e8f9f7 1816 * @arg ADC_JQOVF_EVENT: ADC Injected context queue overflow event
<> 144:ef7eb2e8f9f7 1817 * @param Timeout: Timeout value in millisecond.
<> 144:ef7eb2e8f9f7 1818 * @retval HAL status
<> 144:ef7eb2e8f9f7 1819 */
<> 144:ef7eb2e8f9f7 1820 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1821 {
<> 144:ef7eb2e8f9f7 1822 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 1823
<> 144:ef7eb2e8f9f7 1824 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1825 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1826 assert_param(IS_ADC_EVENT_TYPE(EventType));
<> 144:ef7eb2e8f9f7 1827
<> 144:ef7eb2e8f9f7 1828 /* Get start tick count */
<> 144:ef7eb2e8f9f7 1829 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1830
<> 144:ef7eb2e8f9f7 1831 /* Check selected event flag */
<> 144:ef7eb2e8f9f7 1832 while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
<> 144:ef7eb2e8f9f7 1833 {
<> 144:ef7eb2e8f9f7 1834 /* Check if timeout is disabled (set to infinite wait) */
<> 144:ef7eb2e8f9f7 1835 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1836 {
<> 144:ef7eb2e8f9f7 1837 if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1838 {
<> 144:ef7eb2e8f9f7 1839 /* Update ADC state machine to timeout */
<> 144:ef7eb2e8f9f7 1840 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
<> 144:ef7eb2e8f9f7 1841
<> 144:ef7eb2e8f9f7 1842 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1843 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1844
<> 144:ef7eb2e8f9f7 1845 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1846 }
<> 144:ef7eb2e8f9f7 1847 }
<> 144:ef7eb2e8f9f7 1848 }
<> 144:ef7eb2e8f9f7 1849
<> 144:ef7eb2e8f9f7 1850
<> 144:ef7eb2e8f9f7 1851 switch(EventType)
<> 144:ef7eb2e8f9f7 1852 {
<> 144:ef7eb2e8f9f7 1853 /* Analog watchdog (level out of window) event */
<> 144:ef7eb2e8f9f7 1854 /* Note: In case of several analog watchdog enabled, if needed to know */
<> 144:ef7eb2e8f9f7 1855 /* which one triggered and on which ADCx, test ADC state of analog watchdog */
<> 144:ef7eb2e8f9f7 1856 /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */
<> 144:ef7eb2e8f9f7 1857 /* For example: */
<> 144:ef7eb2e8f9f7 1858 /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)) " */
<> 144:ef7eb2e8f9f7 1859 /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD2)) " */
<> 144:ef7eb2e8f9f7 1860 /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD3)) " */
<> 144:ef7eb2e8f9f7 1861 /* Check analog watchdog 1 flag */
<> 144:ef7eb2e8f9f7 1862 case ADC_AWD_EVENT:
<> 144:ef7eb2e8f9f7 1863 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1864 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
<> 144:ef7eb2e8f9f7 1865
<> 144:ef7eb2e8f9f7 1866 /* Clear ADC analog watchdog flag */
<> 144:ef7eb2e8f9f7 1867 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
<> 144:ef7eb2e8f9f7 1868 break;
<> 144:ef7eb2e8f9f7 1869
<> 144:ef7eb2e8f9f7 1870 /* Check analog watchdog 2 flag */
<> 144:ef7eb2e8f9f7 1871 case ADC_AWD2_EVENT:
<> 144:ef7eb2e8f9f7 1872 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1873 SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
<> 144:ef7eb2e8f9f7 1874
<> 144:ef7eb2e8f9f7 1875 /* Clear ADC analog watchdog flag */
<> 144:ef7eb2e8f9f7 1876 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
<> 144:ef7eb2e8f9f7 1877 break;
<> 144:ef7eb2e8f9f7 1878
<> 144:ef7eb2e8f9f7 1879 /* Check analog watchdog 3 flag */
<> 144:ef7eb2e8f9f7 1880 case ADC_AWD3_EVENT:
<> 144:ef7eb2e8f9f7 1881 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1882 SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
<> 144:ef7eb2e8f9f7 1883
<> 144:ef7eb2e8f9f7 1884 /* Clear ADC analog watchdog flag */
<> 144:ef7eb2e8f9f7 1885 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
<> 144:ef7eb2e8f9f7 1886 break;
<> 144:ef7eb2e8f9f7 1887
<> 144:ef7eb2e8f9f7 1888 /* Injected context queue overflow event */
<> 144:ef7eb2e8f9f7 1889 case ADC_JQOVF_EVENT:
<> 144:ef7eb2e8f9f7 1890 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1891 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
<> 144:ef7eb2e8f9f7 1892
<> 144:ef7eb2e8f9f7 1893 /* Set ADC error code to Injected context queue overflow */
<> 144:ef7eb2e8f9f7 1894 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
<> 144:ef7eb2e8f9f7 1895
<> 144:ef7eb2e8f9f7 1896 /* Clear ADC Injected context queue overflow flag */
<> 144:ef7eb2e8f9f7 1897 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
<> 144:ef7eb2e8f9f7 1898 break;
<> 144:ef7eb2e8f9f7 1899
<> 144:ef7eb2e8f9f7 1900 /* Overrun event */
<> 144:ef7eb2e8f9f7 1901 default: /* Case ADC_OVR_EVENT */
<> 144:ef7eb2e8f9f7 1902 /* If overrun is set to overwrite previous data, overrun event is not */
<> 144:ef7eb2e8f9f7 1903 /* considered as an error. */
<> 144:ef7eb2e8f9f7 1904 /* (cf ref manual "Managing conversions without using the DMA and without */
<> 144:ef7eb2e8f9f7 1905 /* overrun ") */
<> 144:ef7eb2e8f9f7 1906 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
<> 144:ef7eb2e8f9f7 1907 {
<> 144:ef7eb2e8f9f7 1908 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1909 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
<> 144:ef7eb2e8f9f7 1910
<> 144:ef7eb2e8f9f7 1911 /* Set ADC error code to overrun */
<> 144:ef7eb2e8f9f7 1912 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
<> 144:ef7eb2e8f9f7 1913 }
<> 144:ef7eb2e8f9f7 1914
<> 144:ef7eb2e8f9f7 1915 /* Clear ADC Overrun flag */
<> 144:ef7eb2e8f9f7 1916 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
<> 144:ef7eb2e8f9f7 1917 break;
<> 144:ef7eb2e8f9f7 1918 }
<> 144:ef7eb2e8f9f7 1919
<> 144:ef7eb2e8f9f7 1920 /* Return ADC state */
<> 144:ef7eb2e8f9f7 1921 return HAL_OK;
<> 144:ef7eb2e8f9f7 1922 }
<> 144:ef7eb2e8f9f7 1923 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 1924 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 1925 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 1926 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 1927
<> 144:ef7eb2e8f9f7 1928 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 1929 /**
<> 144:ef7eb2e8f9f7 1930 * @brief Poll for conversion event.
<> 144:ef7eb2e8f9f7 1931 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1932 * @param EventType: the ADC event type.
<> 144:ef7eb2e8f9f7 1933 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1934 * @arg ADC_AWD_EVENT: ADC Analog watchdog event.
<> 144:ef7eb2e8f9f7 1935 * @param Timeout: Timeout value in millisecond.
<> 144:ef7eb2e8f9f7 1936 * @retval HAL status
<> 144:ef7eb2e8f9f7 1937 */
<> 144:ef7eb2e8f9f7 1938 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1939 {
<> 144:ef7eb2e8f9f7 1940 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 1941
<> 144:ef7eb2e8f9f7 1942 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1943 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1944 assert_param(IS_ADC_EVENT_TYPE(EventType));
<> 144:ef7eb2e8f9f7 1945
<> 144:ef7eb2e8f9f7 1946 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1947
<> 144:ef7eb2e8f9f7 1948 /* Check selected event flag */
<> 144:ef7eb2e8f9f7 1949 while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
<> 144:ef7eb2e8f9f7 1950 {
<> 144:ef7eb2e8f9f7 1951 /* Check if timeout is disabled (set to infinite wait) */
<> 144:ef7eb2e8f9f7 1952 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1953 {
<> 144:ef7eb2e8f9f7 1954 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 1955 {
<> 144:ef7eb2e8f9f7 1956 /* Update ADC state machine to timeout */
<> 144:ef7eb2e8f9f7 1957 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
<> 144:ef7eb2e8f9f7 1958
<> 144:ef7eb2e8f9f7 1959 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1960 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1961
<> 144:ef7eb2e8f9f7 1962 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1963 }
<> 144:ef7eb2e8f9f7 1964 }
<> 144:ef7eb2e8f9f7 1965 }
<> 144:ef7eb2e8f9f7 1966
<> 144:ef7eb2e8f9f7 1967 /* Analog watchdog (level out of window) event */
<> 144:ef7eb2e8f9f7 1968 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1969 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
<> 144:ef7eb2e8f9f7 1970
<> 144:ef7eb2e8f9f7 1971 /* Clear ADC analog watchdog flag */
<> 144:ef7eb2e8f9f7 1972 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
<> 144:ef7eb2e8f9f7 1973
<> 144:ef7eb2e8f9f7 1974 /* Return ADC state */
<> 144:ef7eb2e8f9f7 1975 return HAL_OK;
<> 144:ef7eb2e8f9f7 1976 }
<> 144:ef7eb2e8f9f7 1977 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 1978
<> 144:ef7eb2e8f9f7 1979 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 1980 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 1981 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 1982 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 1983 /**
<> 144:ef7eb2e8f9f7 1984 * @brief Enables ADC, starts conversion of regular group with interruption.
<> 144:ef7eb2e8f9f7 1985 * Interruptions enabled in this function:
<> 144:ef7eb2e8f9f7 1986 * - EOC (end of conversion of regular group) or EOS (end of
<> 144:ef7eb2e8f9f7 1987 * sequence of regular group) depending on ADC initialization
<> 144:ef7eb2e8f9f7 1988 * parameter "EOCSelection"
<> 144:ef7eb2e8f9f7 1989 * - overrun, depending on ADC initialization parameter "Overrun"
<> 144:ef7eb2e8f9f7 1990 * Each of these interruptions has its dedicated callback function.
<> 144:ef7eb2e8f9f7 1991 * @note Case of multimode enabled (for devices with several ADCs): This
<> 144:ef7eb2e8f9f7 1992 * function must be called for ADC slave first, then ADC master.
<> 144:ef7eb2e8f9f7 1993 * For ADC slave, ADC is enabled only (conversion is not started).
<> 144:ef7eb2e8f9f7 1994 * For ADC master, ADC is enabled and multimode conversion is started.
<> 144:ef7eb2e8f9f7 1995 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1996 * @retval HAL status
<> 144:ef7eb2e8f9f7 1997 */
<> 144:ef7eb2e8f9f7 1998 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1999 {
<> 144:ef7eb2e8f9f7 2000 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 2001
<> 144:ef7eb2e8f9f7 2002 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2003 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 2004
<> 144:ef7eb2e8f9f7 2005 /* Perform ADC enable and conversion start if no conversion is on going */
<> 144:ef7eb2e8f9f7 2006 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<> 144:ef7eb2e8f9f7 2007 {
<> 144:ef7eb2e8f9f7 2008 /* Process locked */
<> 144:ef7eb2e8f9f7 2009 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 2010
<> 144:ef7eb2e8f9f7 2011 /* Enable the ADC peripheral */
<> 144:ef7eb2e8f9f7 2012 tmp_hal_status = ADC_Enable(hadc);
<> 144:ef7eb2e8f9f7 2013
<> 144:ef7eb2e8f9f7 2014 /* Start conversion if ADC is effectively enabled */
<> 144:ef7eb2e8f9f7 2015 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 2016 {
<> 144:ef7eb2e8f9f7 2017 /* Set ADC state */
<> 144:ef7eb2e8f9f7 2018 /* - Clear state bitfield related to regular group conversion results */
<> 144:ef7eb2e8f9f7 2019 /* - Set state bitfield related to regular operation */
<> 144:ef7eb2e8f9f7 2020 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 2021 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
<> 144:ef7eb2e8f9f7 2022 HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 2023
<> 144:ef7eb2e8f9f7 2024 /* Set group injected state (from auto-injection) and multimode state */
<> 144:ef7eb2e8f9f7 2025 /* for all cases of multimode: independent mode, multimode ADC master */
<> 144:ef7eb2e8f9f7 2026 /* or multimode ADC slave (for devices with several ADCs): */
<> 144:ef7eb2e8f9f7 2027 if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
<> 144:ef7eb2e8f9f7 2028 {
<> 144:ef7eb2e8f9f7 2029 /* Set ADC state (ADC independent or master) */
<> 144:ef7eb2e8f9f7 2030 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<> 144:ef7eb2e8f9f7 2031
<> 144:ef7eb2e8f9f7 2032 /* If conversions on group regular are also triggering group injected,*/
<> 144:ef7eb2e8f9f7 2033 /* update ADC state. */
<> 144:ef7eb2e8f9f7 2034 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
<> 144:ef7eb2e8f9f7 2035 {
<> 144:ef7eb2e8f9f7 2036 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 2037 }
<> 144:ef7eb2e8f9f7 2038 }
<> 144:ef7eb2e8f9f7 2039 else
<> 144:ef7eb2e8f9f7 2040 {
<> 144:ef7eb2e8f9f7 2041 /* Set ADC state (ADC slave) */
<> 144:ef7eb2e8f9f7 2042 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<> 144:ef7eb2e8f9f7 2043
<> 144:ef7eb2e8f9f7 2044 /* If conversions on group regular are also triggering group injected,*/
<> 144:ef7eb2e8f9f7 2045 /* update ADC state. */
<> 144:ef7eb2e8f9f7 2046 if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
<> 144:ef7eb2e8f9f7 2047 {
<> 144:ef7eb2e8f9f7 2048 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 2049 }
<> 144:ef7eb2e8f9f7 2050 }
<> 144:ef7eb2e8f9f7 2051
<> 144:ef7eb2e8f9f7 2052 /* State machine update: Check if an injected conversion is ongoing */
<> 144:ef7eb2e8f9f7 2053 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<> 144:ef7eb2e8f9f7 2054 {
<> 144:ef7eb2e8f9f7 2055 /* Reset ADC error code fields related to conversions on group regular*/
<> 144:ef7eb2e8f9f7 2056 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
<> 144:ef7eb2e8f9f7 2057 }
<> 144:ef7eb2e8f9f7 2058 else
<> 144:ef7eb2e8f9f7 2059 {
<> 144:ef7eb2e8f9f7 2060 /* Reset ADC all error code fields */
<> 144:ef7eb2e8f9f7 2061 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 2062 }
<> 144:ef7eb2e8f9f7 2063
<> 144:ef7eb2e8f9f7 2064 /* Process unlocked */
<> 144:ef7eb2e8f9f7 2065 /* Unlock before starting ADC conversions: in case of potential */
<> 144:ef7eb2e8f9f7 2066 /* interruption, to let the process to ADC IRQ Handler. */
<> 144:ef7eb2e8f9f7 2067 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 2068
<> 144:ef7eb2e8f9f7 2069 /* Clear regular group conversion flag and overrun flag */
<> 144:ef7eb2e8f9f7 2070 /* (To ensure of no unknown state from potential previous ADC */
<> 144:ef7eb2e8f9f7 2071 /* operations) */
<> 144:ef7eb2e8f9f7 2072 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
<> 144:ef7eb2e8f9f7 2073
<> 144:ef7eb2e8f9f7 2074 /* Enable ADC end of conversion interrupt */
<> 144:ef7eb2e8f9f7 2075 /* Enable ADC overrun interrupt */
<> 144:ef7eb2e8f9f7 2076 switch(hadc->Init.EOCSelection)
<> 144:ef7eb2e8f9f7 2077 {
<> 144:ef7eb2e8f9f7 2078 case ADC_EOC_SEQ_CONV:
<> 144:ef7eb2e8f9f7 2079 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
<> 144:ef7eb2e8f9f7 2080 __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS));
<> 144:ef7eb2e8f9f7 2081 break;
<> 144:ef7eb2e8f9f7 2082 /* case ADC_EOC_SINGLE_CONV */
<> 144:ef7eb2e8f9f7 2083 default:
<> 144:ef7eb2e8f9f7 2084 __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS));
<> 144:ef7eb2e8f9f7 2085 break;
<> 144:ef7eb2e8f9f7 2086 }
<> 144:ef7eb2e8f9f7 2087
<> 144:ef7eb2e8f9f7 2088 /* If overrun is set to overwrite previous data (default setting), */
<> 144:ef7eb2e8f9f7 2089 /* overrun interrupt is not activated (overrun event is not considered */
<> 144:ef7eb2e8f9f7 2090 /* as an error). */
<> 144:ef7eb2e8f9f7 2091 /* (cf ref manual "Managing conversions without using the DMA and */
<> 144:ef7eb2e8f9f7 2092 /* without overrun ") */
<> 144:ef7eb2e8f9f7 2093 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
<> 144:ef7eb2e8f9f7 2094 {
<> 144:ef7eb2e8f9f7 2095 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
<> 144:ef7eb2e8f9f7 2096 }
<> 144:ef7eb2e8f9f7 2097
<> 144:ef7eb2e8f9f7 2098 /* Enable conversion of regular group. */
<> 144:ef7eb2e8f9f7 2099 /* If software start has been selected, conversion starts immediately. */
<> 144:ef7eb2e8f9f7 2100 /* If external trigger has been selected, conversion will start at next */
<> 144:ef7eb2e8f9f7 2101 /* trigger event. */
<> 144:ef7eb2e8f9f7 2102 /* Case of multimode enabled (for devices with several ADCs): */
<> 144:ef7eb2e8f9f7 2103 /* - if ADC is slave, ADC is enabled only (conversion is not started). */
<> 144:ef7eb2e8f9f7 2104 /* - if ADC is master, ADC is enabled and conversion is started. */
<> 144:ef7eb2e8f9f7 2105 if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
<> 144:ef7eb2e8f9f7 2106 {
<> 144:ef7eb2e8f9f7 2107 SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
<> 144:ef7eb2e8f9f7 2108 }
<> 144:ef7eb2e8f9f7 2109 }
<> 144:ef7eb2e8f9f7 2110 else
<> 144:ef7eb2e8f9f7 2111 {
<> 144:ef7eb2e8f9f7 2112 /* Process unlocked */
<> 144:ef7eb2e8f9f7 2113 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 2114 }
<> 144:ef7eb2e8f9f7 2115 }
<> 144:ef7eb2e8f9f7 2116 else
<> 144:ef7eb2e8f9f7 2117 {
<> 144:ef7eb2e8f9f7 2118 tmp_hal_status = HAL_BUSY;
<> 144:ef7eb2e8f9f7 2119 }
<> 144:ef7eb2e8f9f7 2120
<> 144:ef7eb2e8f9f7 2121 /* Return function status */
<> 144:ef7eb2e8f9f7 2122 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 2123 }
<> 144:ef7eb2e8f9f7 2124 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 2125 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 2126 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 2127 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 2128
<> 144:ef7eb2e8f9f7 2129 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 2130 /**
<> 144:ef7eb2e8f9f7 2131 * @brief Enables ADC, starts conversion of regular group with interruption.
<> 144:ef7eb2e8f9f7 2132 * Interruptions enabled in this function:
<> 144:ef7eb2e8f9f7 2133 * - EOC (end of conversion of regular group)
<> 144:ef7eb2e8f9f7 2134 * Each of these interruptions has its dedicated callback function.
<> 144:ef7eb2e8f9f7 2135 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 2136 * @retval HAL status
<> 144:ef7eb2e8f9f7 2137 */
<> 144:ef7eb2e8f9f7 2138 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 2139 {
<> 144:ef7eb2e8f9f7 2140 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 2141
<> 144:ef7eb2e8f9f7 2142 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2143 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 2144
<> 144:ef7eb2e8f9f7 2145 /* Process locked */
<> 144:ef7eb2e8f9f7 2146 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 2147
<> 144:ef7eb2e8f9f7 2148 /* Enable the ADC peripheral */
<> 144:ef7eb2e8f9f7 2149 tmp_hal_status = ADC_Enable(hadc);
<> 144:ef7eb2e8f9f7 2150
<> 144:ef7eb2e8f9f7 2151 /* Start conversion if ADC is effectively enabled */
<> 144:ef7eb2e8f9f7 2152 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 2153 {
<> 144:ef7eb2e8f9f7 2154 /* Set ADC state */
<> 144:ef7eb2e8f9f7 2155 /* - Clear state bitfield related to regular group conversion results */
<> 144:ef7eb2e8f9f7 2156 /* - Set state bitfield related to regular operation */
<> 144:ef7eb2e8f9f7 2157 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 2158 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC,
<> 144:ef7eb2e8f9f7 2159 HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 2160
<> 144:ef7eb2e8f9f7 2161 /* Set group injected state (from auto-injection) */
<> 144:ef7eb2e8f9f7 2162 /* If conversions on group regular are also triggering group injected, */
<> 144:ef7eb2e8f9f7 2163 /* update ADC state. */
<> 144:ef7eb2e8f9f7 2164 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
<> 144:ef7eb2e8f9f7 2165 {
<> 144:ef7eb2e8f9f7 2166 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 2167 }
<> 144:ef7eb2e8f9f7 2168
<> 144:ef7eb2e8f9f7 2169 /* State machine update: Check if an injected conversion is ongoing */
<> 144:ef7eb2e8f9f7 2170 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<> 144:ef7eb2e8f9f7 2171 {
<> 144:ef7eb2e8f9f7 2172 /* Reset ADC error code fields related to conversions on group regular */
<> 144:ef7eb2e8f9f7 2173 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
<> 144:ef7eb2e8f9f7 2174 }
<> 144:ef7eb2e8f9f7 2175 else
<> 144:ef7eb2e8f9f7 2176 {
<> 144:ef7eb2e8f9f7 2177 /* Reset ADC all error code fields */
<> 144:ef7eb2e8f9f7 2178 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 2179 }
<> 144:ef7eb2e8f9f7 2180
<> 144:ef7eb2e8f9f7 2181 /* Process unlocked */
<> 144:ef7eb2e8f9f7 2182 /* Unlock before starting ADC conversions: in case of potential */
<> 144:ef7eb2e8f9f7 2183 /* interruption, to let the process to ADC IRQ Handler. */
<> 144:ef7eb2e8f9f7 2184 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 2185
<> 144:ef7eb2e8f9f7 2186 /* Clear regular group conversion flag and overrun flag */
<> 144:ef7eb2e8f9f7 2187 /* (To ensure of no unknown state from potential previous ADC operations) */
<> 144:ef7eb2e8f9f7 2188 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
<> 144:ef7eb2e8f9f7 2189
<> 144:ef7eb2e8f9f7 2190 /* Enable end of conversion interrupt for regular group */
<> 144:ef7eb2e8f9f7 2191 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
<> 144:ef7eb2e8f9f7 2192
<> 144:ef7eb2e8f9f7 2193 /* Enable conversion of regular group. */
<> 144:ef7eb2e8f9f7 2194 /* If software start has been selected, conversion starts immediately. */
<> 144:ef7eb2e8f9f7 2195 /* If external trigger has been selected, conversion will start at next */
<> 144:ef7eb2e8f9f7 2196 /* trigger event. */
<> 144:ef7eb2e8f9f7 2197 if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
<> 144:ef7eb2e8f9f7 2198 {
<> 144:ef7eb2e8f9f7 2199 /* Start ADC conversion on regular group with SW start */
<> 144:ef7eb2e8f9f7 2200 SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
<> 144:ef7eb2e8f9f7 2201 }
<> 144:ef7eb2e8f9f7 2202 else
<> 144:ef7eb2e8f9f7 2203 {
<> 144:ef7eb2e8f9f7 2204 /* Start ADC conversion on regular group with external trigger */
<> 144:ef7eb2e8f9f7 2205 SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
<> 144:ef7eb2e8f9f7 2206 }
<> 144:ef7eb2e8f9f7 2207 }
<> 144:ef7eb2e8f9f7 2208
<> 144:ef7eb2e8f9f7 2209 /* Return function status */
<> 144:ef7eb2e8f9f7 2210 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 2211 }
<> 144:ef7eb2e8f9f7 2212 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 2213
<> 144:ef7eb2e8f9f7 2214 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 2215 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 2216 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 2217 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 2218 /**
<> 144:ef7eb2e8f9f7 2219 * @brief Stop ADC conversion of both groups regular and injected,
<> 144:ef7eb2e8f9f7 2220 * disable ADC peripheral.
<> 144:ef7eb2e8f9f7 2221 * Interruptions disabled in this function:
<> 144:ef7eb2e8f9f7 2222 * - EOC (end of conversion of regular group) and EOS (end of
<> 144:ef7eb2e8f9f7 2223 * sequence of regular group)
<> 144:ef7eb2e8f9f7 2224 * - overrun
<> 144:ef7eb2e8f9f7 2225 * @note ADC peripheral disable is forcing interruption of potential
<> 144:ef7eb2e8f9f7 2226 * conversion on injected group. If injected group is under use,
<> 144:ef7eb2e8f9f7 2227 * it should be preliminarily stopped using function
<> 144:ef7eb2e8f9f7 2228 * @ref HAL_ADCEx_InjectedStop().
<> 144:ef7eb2e8f9f7 2229 * To stop ADC conversion only on ADC group regular
<> 144:ef7eb2e8f9f7 2230 * while letting ADC group injected conversions running,
<> 144:ef7eb2e8f9f7 2231 * use function @ref HAL_ADCEx_RegularStop_IT().
<> 144:ef7eb2e8f9f7 2232 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 2233 * @retval HAL status.
<> 144:ef7eb2e8f9f7 2234 */
<> 144:ef7eb2e8f9f7 2235 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 2236 {
<> 144:ef7eb2e8f9f7 2237 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 2238
<> 144:ef7eb2e8f9f7 2239 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2240 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 2241
<> 144:ef7eb2e8f9f7 2242 /* Process locked */
<> 144:ef7eb2e8f9f7 2243 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 2244
<> 144:ef7eb2e8f9f7 2245 /* 1. Stop potential conversion on going, on regular and injected groups */
<> 144:ef7eb2e8f9f7 2246 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
<> 144:ef7eb2e8f9f7 2247
<> 144:ef7eb2e8f9f7 2248 /* Disable ADC peripheral if conversions are effectively stopped */
<> 144:ef7eb2e8f9f7 2249 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 2250 {
<> 144:ef7eb2e8f9f7 2251 /* Disable ADC end of conversion interrupt for regular group */
<> 144:ef7eb2e8f9f7 2252 /* Disable ADC overrun interrupt */
<> 144:ef7eb2e8f9f7 2253 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
<> 144:ef7eb2e8f9f7 2254
<> 144:ef7eb2e8f9f7 2255 /* 2. Disable the ADC peripheral */
<> 144:ef7eb2e8f9f7 2256 tmp_hal_status = ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 2257
<> 144:ef7eb2e8f9f7 2258 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 2259 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 2260 {
<> 144:ef7eb2e8f9f7 2261 /* Set ADC state */
<> 144:ef7eb2e8f9f7 2262 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 2263 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 144:ef7eb2e8f9f7 2264 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 2265 }
<> 144:ef7eb2e8f9f7 2266 }
<> 144:ef7eb2e8f9f7 2267
<> 144:ef7eb2e8f9f7 2268 /* Process unlocked */
<> 144:ef7eb2e8f9f7 2269 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 2270
<> 144:ef7eb2e8f9f7 2271 /* Return function status */
<> 144:ef7eb2e8f9f7 2272 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 2273 }
<> 144:ef7eb2e8f9f7 2274 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 2275 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 2276 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 2277 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 2278
<> 144:ef7eb2e8f9f7 2279 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 2280 /**
<> 144:ef7eb2e8f9f7 2281 * @brief Stop ADC conversion of regular group (and injected group in
<> 144:ef7eb2e8f9f7 2282 * case of auto_injection mode), disable interrution of
<> 144:ef7eb2e8f9f7 2283 * end-of-conversion, disable ADC peripheral.
<> 144:ef7eb2e8f9f7 2284 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 2285 * @retval None
<> 144:ef7eb2e8f9f7 2286 */
<> 144:ef7eb2e8f9f7 2287 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 2288 {
<> 144:ef7eb2e8f9f7 2289 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 2290
<> 144:ef7eb2e8f9f7 2291 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2292 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 2293
<> 144:ef7eb2e8f9f7 2294 /* Process locked */
<> 144:ef7eb2e8f9f7 2295 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 2296
<> 144:ef7eb2e8f9f7 2297 /* Stop potential conversion on going, on regular and injected groups */
<> 144:ef7eb2e8f9f7 2298 /* Disable ADC peripheral */
<> 144:ef7eb2e8f9f7 2299 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
<> 144:ef7eb2e8f9f7 2300
<> 144:ef7eb2e8f9f7 2301 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 2302 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 2303 {
<> 144:ef7eb2e8f9f7 2304 /* Disable ADC end of conversion interrupt for regular group */
<> 144:ef7eb2e8f9f7 2305 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
<> 144:ef7eb2e8f9f7 2306
<> 144:ef7eb2e8f9f7 2307 /* Set ADC state */
<> 144:ef7eb2e8f9f7 2308 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 2309 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 144:ef7eb2e8f9f7 2310 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 2311 }
<> 144:ef7eb2e8f9f7 2312
<> 144:ef7eb2e8f9f7 2313 /* Process unlocked */
<> 144:ef7eb2e8f9f7 2314 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 2315
<> 144:ef7eb2e8f9f7 2316 /* Return function status */
<> 144:ef7eb2e8f9f7 2317 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 2318 }
<> 144:ef7eb2e8f9f7 2319 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 2320
<> 144:ef7eb2e8f9f7 2321 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 2322 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 2323 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 2324 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 2325 /**
<> 144:ef7eb2e8f9f7 2326 * @brief Enables ADC, starts conversion of regular group and transfers result
<> 144:ef7eb2e8f9f7 2327 * through DMA.
<> 144:ef7eb2e8f9f7 2328 * Interruptions enabled in this function:
<> 144:ef7eb2e8f9f7 2329 * - DMA transfer complete
<> 144:ef7eb2e8f9f7 2330 * - DMA half transfer
<> 144:ef7eb2e8f9f7 2331 * - overrun
<> 144:ef7eb2e8f9f7 2332 * Each of these interruptions has its dedicated callback function.
<> 144:ef7eb2e8f9f7 2333 * @note Case of multimode enabled (for devices with several ADCs): This
<> 144:ef7eb2e8f9f7 2334 * function is for single-ADC mode only. For multimode, use the
<> 144:ef7eb2e8f9f7 2335 * dedicated MultimodeStart function.
<> 144:ef7eb2e8f9f7 2336 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 2337 * @param pData: The destination Buffer address.
<> 144:ef7eb2e8f9f7 2338 * @param Length: The length of data to be transferred from ADC peripheral to memory.
<> 144:ef7eb2e8f9f7 2339 * @retval None
<> 144:ef7eb2e8f9f7 2340 */
<> 144:ef7eb2e8f9f7 2341 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
<> 144:ef7eb2e8f9f7 2342 {
<> 144:ef7eb2e8f9f7 2343 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 2344
<> 144:ef7eb2e8f9f7 2345 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2346 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 2347
<> 144:ef7eb2e8f9f7 2348 /* Perform ADC enable and conversion start if no conversion is on going */
<> 144:ef7eb2e8f9f7 2349 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<> 144:ef7eb2e8f9f7 2350 {
<> 144:ef7eb2e8f9f7 2351 /* Process locked */
<> 144:ef7eb2e8f9f7 2352 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 2353
<> 144:ef7eb2e8f9f7 2354 /* Verification if multimode is disabled (for devices with several ADC) */
<> 144:ef7eb2e8f9f7 2355 /* If multimode is enabled, dedicated function multimode conversion */
<> 144:ef7eb2e8f9f7 2356 /* start DMA must be used. */
<> 144:ef7eb2e8f9f7 2357 if(ADC_COMMON_CCR_MULTI(hadc) == RESET)
<> 144:ef7eb2e8f9f7 2358 {
<> 144:ef7eb2e8f9f7 2359 /* Enable the ADC peripheral */
<> 144:ef7eb2e8f9f7 2360 tmp_hal_status = ADC_Enable(hadc);
<> 144:ef7eb2e8f9f7 2361
<> 144:ef7eb2e8f9f7 2362 /* Start conversion if ADC is effectively enabled */
<> 144:ef7eb2e8f9f7 2363 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 2364 {
<> 144:ef7eb2e8f9f7 2365 /* Set ADC state */
<> 144:ef7eb2e8f9f7 2366 /* - Clear state bitfield related to regular group conversion results */
<> 144:ef7eb2e8f9f7 2367 /* - Set state bitfield related to regular operation */
<> 144:ef7eb2e8f9f7 2368 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 2369 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
<> 144:ef7eb2e8f9f7 2370 HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 2371
<> 144:ef7eb2e8f9f7 2372 /* Set group injected state (from auto-injection) and multimode state */
<> 144:ef7eb2e8f9f7 2373 /* for all cases of multimode: independent mode, multimode ADC master */
<> 144:ef7eb2e8f9f7 2374 /* or multimode ADC slave (for devices with several ADCs): */
<> 144:ef7eb2e8f9f7 2375 if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
<> 144:ef7eb2e8f9f7 2376 {
<> 144:ef7eb2e8f9f7 2377 /* Set ADC state (ADC independent or master) */
<> 144:ef7eb2e8f9f7 2378 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<> 144:ef7eb2e8f9f7 2379
<> 144:ef7eb2e8f9f7 2380 /* If conversions on group regular are also triggering group injected,*/
<> 144:ef7eb2e8f9f7 2381 /* update ADC state. */
<> 144:ef7eb2e8f9f7 2382 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
<> 144:ef7eb2e8f9f7 2383 {
<> 144:ef7eb2e8f9f7 2384 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 2385 }
<> 144:ef7eb2e8f9f7 2386 }
<> 144:ef7eb2e8f9f7 2387 else
<> 144:ef7eb2e8f9f7 2388 {
<> 144:ef7eb2e8f9f7 2389 /* Set ADC state (ADC slave) */
<> 144:ef7eb2e8f9f7 2390 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<> 144:ef7eb2e8f9f7 2391
<> 144:ef7eb2e8f9f7 2392 /* If conversions on group regular are also triggering group injected,*/
<> 144:ef7eb2e8f9f7 2393 /* update ADC state. */
<> 144:ef7eb2e8f9f7 2394 if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
<> 144:ef7eb2e8f9f7 2395 {
<> 144:ef7eb2e8f9f7 2396 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 2397 }
<> 144:ef7eb2e8f9f7 2398 }
<> 144:ef7eb2e8f9f7 2399
<> 144:ef7eb2e8f9f7 2400 /* State machine update: Check if an injected conversion is ongoing */
<> 144:ef7eb2e8f9f7 2401 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<> 144:ef7eb2e8f9f7 2402 {
<> 144:ef7eb2e8f9f7 2403 /* Reset ADC error code fields related to conversions on group regular*/
<> 144:ef7eb2e8f9f7 2404 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
<> 144:ef7eb2e8f9f7 2405 }
<> 144:ef7eb2e8f9f7 2406 else
<> 144:ef7eb2e8f9f7 2407 {
<> 144:ef7eb2e8f9f7 2408 /* Reset ADC all error code fields */
<> 144:ef7eb2e8f9f7 2409 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 2410 }
<> 144:ef7eb2e8f9f7 2411
<> 144:ef7eb2e8f9f7 2412 /* Process unlocked */
<> 144:ef7eb2e8f9f7 2413 /* Unlock before starting ADC conversions: in case of potential */
<> 144:ef7eb2e8f9f7 2414 /* interruption, to let the process to ADC IRQ Handler. */
<> 144:ef7eb2e8f9f7 2415 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 2416
<> 144:ef7eb2e8f9f7 2417
<> 144:ef7eb2e8f9f7 2418 /* Set the DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 2419 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
<> 144:ef7eb2e8f9f7 2420
<> 144:ef7eb2e8f9f7 2421 /* Set the DMA half transfer complete callback */
<> 144:ef7eb2e8f9f7 2422 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
<> 144:ef7eb2e8f9f7 2423
<> 144:ef7eb2e8f9f7 2424 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2425 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
<> 144:ef7eb2e8f9f7 2426
<> 144:ef7eb2e8f9f7 2427
<> 144:ef7eb2e8f9f7 2428 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
<> 144:ef7eb2e8f9f7 2429 /* start (in case of SW start): */
<> 144:ef7eb2e8f9f7 2430
<> 144:ef7eb2e8f9f7 2431 /* Clear regular group conversion flag and overrun flag */
<> 144:ef7eb2e8f9f7 2432 /* (To ensure of no unknown state from potential previous ADC */
<> 144:ef7eb2e8f9f7 2433 /* operations) */
<> 144:ef7eb2e8f9f7 2434 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
<> 144:ef7eb2e8f9f7 2435
<> 144:ef7eb2e8f9f7 2436 /* Enable ADC overrun interrupt */
<> 144:ef7eb2e8f9f7 2437 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
<> 144:ef7eb2e8f9f7 2438
<> 144:ef7eb2e8f9f7 2439 /* Enable ADC DMA mode */
<> 144:ef7eb2e8f9f7 2440 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
<> 144:ef7eb2e8f9f7 2441
<> 144:ef7eb2e8f9f7 2442 /* Start the DMA channel */
<> 144:ef7eb2e8f9f7 2443 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 2444
<> 144:ef7eb2e8f9f7 2445 /* Enable conversion of regular group. */
<> 144:ef7eb2e8f9f7 2446 /* If software start has been selected, conversion starts immediately.*/
<> 144:ef7eb2e8f9f7 2447 /* If external trigger has been selected, conversion will start at */
<> 144:ef7eb2e8f9f7 2448 /* next trigger event. */
<> 144:ef7eb2e8f9f7 2449 SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
<> 144:ef7eb2e8f9f7 2450
<> 144:ef7eb2e8f9f7 2451 }
<> 144:ef7eb2e8f9f7 2452 else
<> 144:ef7eb2e8f9f7 2453 {
<> 144:ef7eb2e8f9f7 2454 /* Process unlocked */
<> 144:ef7eb2e8f9f7 2455 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 2456 }
<> 144:ef7eb2e8f9f7 2457 }
<> 144:ef7eb2e8f9f7 2458 else
<> 144:ef7eb2e8f9f7 2459 {
<> 144:ef7eb2e8f9f7 2460 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2461
<> 144:ef7eb2e8f9f7 2462 /* Process unlocked */
<> 144:ef7eb2e8f9f7 2463 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 2464 }
<> 144:ef7eb2e8f9f7 2465 }
<> 144:ef7eb2e8f9f7 2466 else
<> 144:ef7eb2e8f9f7 2467 {
<> 144:ef7eb2e8f9f7 2468 tmp_hal_status = HAL_BUSY;
<> 144:ef7eb2e8f9f7 2469 }
<> 144:ef7eb2e8f9f7 2470
<> 144:ef7eb2e8f9f7 2471 /* Return function status */
<> 144:ef7eb2e8f9f7 2472 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 2473 }
<> 144:ef7eb2e8f9f7 2474 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 2475 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 2476 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 2477 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 2478
<> 144:ef7eb2e8f9f7 2479 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 2480 /**
<> 144:ef7eb2e8f9f7 2481 * @brief Enables ADC, starts conversion of regular group and transfers result
<> 144:ef7eb2e8f9f7 2482 * through DMA.
<> 144:ef7eb2e8f9f7 2483 * Interruptions enabled in this function:
<> 144:ef7eb2e8f9f7 2484 * - DMA transfer complete
<> 144:ef7eb2e8f9f7 2485 * - DMA half transfer
<> 144:ef7eb2e8f9f7 2486 * Each of these interruptions has its dedicated callback function.
<> 144:ef7eb2e8f9f7 2487 * @note For devices with several ADCs: This function is for single-ADC mode
<> 144:ef7eb2e8f9f7 2488 * only. For multimode, use the dedicated MultimodeStart function.
<> 144:ef7eb2e8f9f7 2489 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 2490 * @param pData: The destination Buffer address.
<> 144:ef7eb2e8f9f7 2491 * @param Length: The length of data to be transferred from ADC peripheral to memory.
<> 144:ef7eb2e8f9f7 2492 * @retval None
<> 144:ef7eb2e8f9f7 2493 */
<> 144:ef7eb2e8f9f7 2494 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
<> 144:ef7eb2e8f9f7 2495 {
<> 144:ef7eb2e8f9f7 2496 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 2497
<> 144:ef7eb2e8f9f7 2498 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2499 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 2500
<> 144:ef7eb2e8f9f7 2501 /* Process locked */
<> 144:ef7eb2e8f9f7 2502 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 2503
<> 144:ef7eb2e8f9f7 2504 /* Enable the ADC peripheral */
<> 144:ef7eb2e8f9f7 2505 tmp_hal_status = ADC_Enable(hadc);
<> 144:ef7eb2e8f9f7 2506
<> 144:ef7eb2e8f9f7 2507 /* Start conversion if ADC is effectively enabled */
<> 144:ef7eb2e8f9f7 2508 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 2509 {
<> 144:ef7eb2e8f9f7 2510 /* Set ADC state */
<> 144:ef7eb2e8f9f7 2511 /* - Clear state bitfield related to regular group conversion results */
<> 144:ef7eb2e8f9f7 2512 /* - Set state bitfield related to regular operation */
<> 144:ef7eb2e8f9f7 2513 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 2514 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC,
<> 144:ef7eb2e8f9f7 2515 HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 2516
<> 144:ef7eb2e8f9f7 2517 /* Set group injected state (from auto-injection) */
<> 144:ef7eb2e8f9f7 2518 /* If conversions on group regular are also triggering group injected, */
<> 144:ef7eb2e8f9f7 2519 /* update ADC state. */
<> 144:ef7eb2e8f9f7 2520 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
<> 144:ef7eb2e8f9f7 2521 {
<> 144:ef7eb2e8f9f7 2522 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 2523 }
<> 144:ef7eb2e8f9f7 2524
<> 144:ef7eb2e8f9f7 2525 /* State machine update: Check if an injected conversion is ongoing */
<> 144:ef7eb2e8f9f7 2526 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<> 144:ef7eb2e8f9f7 2527 {
<> 144:ef7eb2e8f9f7 2528 /* Reset ADC error code fields related to conversions on group regular */
<> 144:ef7eb2e8f9f7 2529 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
<> 144:ef7eb2e8f9f7 2530 }
<> 144:ef7eb2e8f9f7 2531 else
<> 144:ef7eb2e8f9f7 2532 {
<> 144:ef7eb2e8f9f7 2533 /* Reset ADC all error code fields */
<> 144:ef7eb2e8f9f7 2534 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 2535 }
<> 144:ef7eb2e8f9f7 2536
<> 144:ef7eb2e8f9f7 2537 /* Process unlocked */
<> 144:ef7eb2e8f9f7 2538 /* Unlock before starting ADC conversions: in case of potential */
<> 144:ef7eb2e8f9f7 2539 /* interruption, to let the process to ADC IRQ Handler. */
<> 144:ef7eb2e8f9f7 2540 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 2541
<> 144:ef7eb2e8f9f7 2542 /* Set the DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 2543 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
<> 144:ef7eb2e8f9f7 2544
<> 144:ef7eb2e8f9f7 2545 /* Set the DMA half transfer complete callback */
<> 144:ef7eb2e8f9f7 2546 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
<> 144:ef7eb2e8f9f7 2547
<> 144:ef7eb2e8f9f7 2548 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2549 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
<> 144:ef7eb2e8f9f7 2550
<> 144:ef7eb2e8f9f7 2551
<> 144:ef7eb2e8f9f7 2552 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
<> 144:ef7eb2e8f9f7 2553 /* start (in case of SW start): */
<> 144:ef7eb2e8f9f7 2554
<> 144:ef7eb2e8f9f7 2555 /* Clear regular group conversion flag and overrun flag */
<> 144:ef7eb2e8f9f7 2556 /* (To ensure of no unknown state from potential previous ADC operations) */
<> 144:ef7eb2e8f9f7 2557 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
<> 144:ef7eb2e8f9f7 2558
<> 144:ef7eb2e8f9f7 2559 /* Enable ADC DMA mode */
<> 144:ef7eb2e8f9f7 2560 hadc->Instance->CR2 |= ADC_CR2_DMA;
<> 144:ef7eb2e8f9f7 2561
<> 144:ef7eb2e8f9f7 2562 /* Start the DMA channel */
<> 144:ef7eb2e8f9f7 2563 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 2564
<> 144:ef7eb2e8f9f7 2565 /* Enable conversion of regular group. */
<> 144:ef7eb2e8f9f7 2566 /* If software start has been selected, conversion starts immediately. */
<> 144:ef7eb2e8f9f7 2567 /* If external trigger has been selected, conversion will start at next */
<> 144:ef7eb2e8f9f7 2568 /* trigger event. */
<> 144:ef7eb2e8f9f7 2569 /* Note: Alternate trigger for single conversion could be to force an */
<> 144:ef7eb2e8f9f7 2570 /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
<> 144:ef7eb2e8f9f7 2571 if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
<> 144:ef7eb2e8f9f7 2572 {
<> 144:ef7eb2e8f9f7 2573 /* Start ADC conversion on regular group with SW start */
<> 144:ef7eb2e8f9f7 2574 SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
<> 144:ef7eb2e8f9f7 2575 }
<> 144:ef7eb2e8f9f7 2576 else
<> 144:ef7eb2e8f9f7 2577 {
<> 144:ef7eb2e8f9f7 2578 /* Start ADC conversion on regular group with external trigger */
<> 144:ef7eb2e8f9f7 2579 SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
<> 144:ef7eb2e8f9f7 2580 }
<> 144:ef7eb2e8f9f7 2581 }
<> 144:ef7eb2e8f9f7 2582
<> 144:ef7eb2e8f9f7 2583 /* Return function status */
<> 144:ef7eb2e8f9f7 2584 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 2585 }
<> 144:ef7eb2e8f9f7 2586 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 2587
<> 144:ef7eb2e8f9f7 2588 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 2589 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 2590 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 2591 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 2592 /**
<> 144:ef7eb2e8f9f7 2593 * @brief Stop ADC conversion of both groups regular and injected,
<> 144:ef7eb2e8f9f7 2594 * disable ADC DMA transfer, disable ADC peripheral.
<> 144:ef7eb2e8f9f7 2595 * Interruptions disabled in this function:
<> 144:ef7eb2e8f9f7 2596 * - DMA transfer complete
<> 144:ef7eb2e8f9f7 2597 * - DMA half transfer
<> 144:ef7eb2e8f9f7 2598 * - overrun
<> 144:ef7eb2e8f9f7 2599 * @note ADC peripheral disable is forcing interruption of potential
<> 144:ef7eb2e8f9f7 2600 * conversion on injected group. If injected group is under use,
<> 144:ef7eb2e8f9f7 2601 * it should be preliminarily stopped using function
<> 144:ef7eb2e8f9f7 2602 * @ref HAL_ADCEx_InjectedStop().
<> 144:ef7eb2e8f9f7 2603 * To stop ADC conversion only on ADC group regular
<> 144:ef7eb2e8f9f7 2604 * while letting ADC group injected conversions running,
<> 144:ef7eb2e8f9f7 2605 * use function @ref HAL_ADCEx_RegularStop_DMA().
<> 144:ef7eb2e8f9f7 2606 * @note Case of multimode enabled (for devices with several ADCs): This
<> 144:ef7eb2e8f9f7 2607 * function is for single-ADC mode only. For multimode, use the
<> 144:ef7eb2e8f9f7 2608 * dedicated MultimodeStop function.
<> 144:ef7eb2e8f9f7 2609 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 2610 * @retval HAL status.
<> 144:ef7eb2e8f9f7 2611 */
<> 144:ef7eb2e8f9f7 2612 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 2613 {
<> 144:ef7eb2e8f9f7 2614 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 2615
<> 144:ef7eb2e8f9f7 2616 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2617 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 2618
<> 144:ef7eb2e8f9f7 2619 /* Process locked */
<> 144:ef7eb2e8f9f7 2620 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 2621
<> 144:ef7eb2e8f9f7 2622 /* 1. Stop potential conversion on going, on regular and injected groups */
<> 144:ef7eb2e8f9f7 2623 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
<> 144:ef7eb2e8f9f7 2624
<> 144:ef7eb2e8f9f7 2625 /* Disable ADC peripheral if conversions are effectively stopped */
<> 144:ef7eb2e8f9f7 2626 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 2627 {
<> 144:ef7eb2e8f9f7 2628 /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
<> 144:ef7eb2e8f9f7 2629 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
<> 144:ef7eb2e8f9f7 2630
<> 144:ef7eb2e8f9f7 2631 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
<> 144:ef7eb2e8f9f7 2632 /* while DMA transfer is on going) */
<> 144:ef7eb2e8f9f7 2633 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
<> 144:ef7eb2e8f9f7 2634
<> 144:ef7eb2e8f9f7 2635 /* Check if DMA channel effectively disabled */
<> 144:ef7eb2e8f9f7 2636 if (tmp_hal_status != HAL_OK)
<> 144:ef7eb2e8f9f7 2637 {
<> 144:ef7eb2e8f9f7 2638 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 2639 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
<> 144:ef7eb2e8f9f7 2640 }
<> 144:ef7eb2e8f9f7 2641
<> 144:ef7eb2e8f9f7 2642 /* Disable ADC overrun interrupt */
<> 144:ef7eb2e8f9f7 2643 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
<> 144:ef7eb2e8f9f7 2644
<> 144:ef7eb2e8f9f7 2645 /* 2. Disable the ADC peripheral */
<> 144:ef7eb2e8f9f7 2646 /* Update "tmp_hal_status" only if DMA channel disabling passed, */
<> 144:ef7eb2e8f9f7 2647 /* to retain a potential failing status. */
<> 144:ef7eb2e8f9f7 2648 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 2649 {
<> 144:ef7eb2e8f9f7 2650 tmp_hal_status = ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 2651 }
<> 144:ef7eb2e8f9f7 2652 else
<> 144:ef7eb2e8f9f7 2653 {
<> 144:ef7eb2e8f9f7 2654 ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 2655 }
<> 144:ef7eb2e8f9f7 2656
<> 144:ef7eb2e8f9f7 2657 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 2658 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 2659 {
<> 144:ef7eb2e8f9f7 2660 /* Set ADC state */
<> 144:ef7eb2e8f9f7 2661 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 2662 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 144:ef7eb2e8f9f7 2663 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 2664 }
<> 144:ef7eb2e8f9f7 2665
<> 144:ef7eb2e8f9f7 2666 }
<> 144:ef7eb2e8f9f7 2667
<> 144:ef7eb2e8f9f7 2668 /* Process unlocked */
<> 144:ef7eb2e8f9f7 2669 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 2670
<> 144:ef7eb2e8f9f7 2671 /* Return function status */
<> 144:ef7eb2e8f9f7 2672 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 2673 }
<> 144:ef7eb2e8f9f7 2674 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 2675 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 2676 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 2677 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 2678
<> 144:ef7eb2e8f9f7 2679 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 2680 /**
<> 144:ef7eb2e8f9f7 2681 * @brief Stop ADC conversion of regular group (and injected group in
<> 144:ef7eb2e8f9f7 2682 * case of auto_injection mode), disable ADC DMA transfer, disable
<> 144:ef7eb2e8f9f7 2683 * ADC peripheral.
<> 144:ef7eb2e8f9f7 2684 * @note ADC peripheral disable is forcing interruption of potential
<> 144:ef7eb2e8f9f7 2685 * conversion on injected group. If injected group is under use, it
<> 144:ef7eb2e8f9f7 2686 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
<> 144:ef7eb2e8f9f7 2687 * @note For devices with several ADCs: This function is for single-ADC mode
<> 144:ef7eb2e8f9f7 2688 * only. For multimode, use the dedicated MultimodeStop function.
<> 144:ef7eb2e8f9f7 2689 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 2690 * @retval HAL status.
<> 144:ef7eb2e8f9f7 2691 */
<> 144:ef7eb2e8f9f7 2692 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 2693 {
<> 144:ef7eb2e8f9f7 2694 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 2695
<> 144:ef7eb2e8f9f7 2696 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2697 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 2698
<> 144:ef7eb2e8f9f7 2699 /* Process locked */
<> 144:ef7eb2e8f9f7 2700 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 2701
<> 144:ef7eb2e8f9f7 2702 /* Stop potential conversion on going, on regular and injected groups */
<> 144:ef7eb2e8f9f7 2703 /* Disable ADC peripheral */
<> 144:ef7eb2e8f9f7 2704 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
<> 144:ef7eb2e8f9f7 2705
<> 144:ef7eb2e8f9f7 2706 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 2707 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 2708 {
<> 144:ef7eb2e8f9f7 2709 /* Disable ADC DMA mode */
<> 144:ef7eb2e8f9f7 2710 hadc->Instance->CR2 &= ~ADC_CR2_DMA;
<> 144:ef7eb2e8f9f7 2711
<> 144:ef7eb2e8f9f7 2712 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
<> 144:ef7eb2e8f9f7 2713 /* while DMA transfer is on going) */
<> 144:ef7eb2e8f9f7 2714 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
<> 144:ef7eb2e8f9f7 2715
<> 144:ef7eb2e8f9f7 2716 /* Check if DMA channel effectively disabled */
<> 144:ef7eb2e8f9f7 2717 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 2718 {
<> 144:ef7eb2e8f9f7 2719 /* Set ADC state */
<> 144:ef7eb2e8f9f7 2720 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 2721 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 144:ef7eb2e8f9f7 2722 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 2723 }
<> 144:ef7eb2e8f9f7 2724 else
<> 144:ef7eb2e8f9f7 2725 {
<> 144:ef7eb2e8f9f7 2726 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 2727 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
<> 144:ef7eb2e8f9f7 2728 }
<> 144:ef7eb2e8f9f7 2729 }
<> 144:ef7eb2e8f9f7 2730
<> 144:ef7eb2e8f9f7 2731 /* Process unlocked */
<> 144:ef7eb2e8f9f7 2732 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 2733
<> 144:ef7eb2e8f9f7 2734 /* Return function status */
<> 144:ef7eb2e8f9f7 2735 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 2736 }
<> 144:ef7eb2e8f9f7 2737 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 2738
<> 144:ef7eb2e8f9f7 2739 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 2740 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 2741 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 2742 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 2743 /**
<> 144:ef7eb2e8f9f7 2744 * @brief Get ADC regular group conversion result.
<> 144:ef7eb2e8f9f7 2745 * @note Reading register DR automatically clears ADC flag EOC
<> 144:ef7eb2e8f9f7 2746 * (ADC group regular end of unitary conversion).
<> 144:ef7eb2e8f9f7 2747 * @note This function does not clear ADC flag EOS
<> 144:ef7eb2e8f9f7 2748 * (ADC group regular end of sequence conversion).
<> 144:ef7eb2e8f9f7 2749 * Occurrence of flag EOS rising:
<> 144:ef7eb2e8f9f7 2750 * - If sequencer is composed of 1 rank, flag EOS is equivalent
<> 144:ef7eb2e8f9f7 2751 * to flag EOC.
<> 144:ef7eb2e8f9f7 2752 * - If sequencer is composed of several ranks, during the scan
<> 144:ef7eb2e8f9f7 2753 * sequence flag EOC only is raised, at the end of the scan sequence
<> 144:ef7eb2e8f9f7 2754 * both flags EOC and EOS are raised.
<> 144:ef7eb2e8f9f7 2755 * To clear this flag, either use function:
<> 144:ef7eb2e8f9f7 2756 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
<> 144:ef7eb2e8f9f7 2757 * model polling: @ref HAL_ADC_PollForConversion()
<> 144:ef7eb2e8f9f7 2758 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
<> 144:ef7eb2e8f9f7 2759 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 2760 * @retval ADC group regular conversion data
<> 144:ef7eb2e8f9f7 2761 */
<> 144:ef7eb2e8f9f7 2762 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 2763 {
<> 144:ef7eb2e8f9f7 2764 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2765 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 2766
<> 144:ef7eb2e8f9f7 2767 /* Note: ADC flag EOC is not cleared here by software because */
<> 144:ef7eb2e8f9f7 2768 /* automatically cleared by hardware when reading register DR. */
<> 144:ef7eb2e8f9f7 2769
<> 144:ef7eb2e8f9f7 2770 /* Return ADC converted value */
<> 144:ef7eb2e8f9f7 2771 return hadc->Instance->DR;
<> 144:ef7eb2e8f9f7 2772 }
<> 144:ef7eb2e8f9f7 2773 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 2774 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 2775 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 2776 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 2777
<> 144:ef7eb2e8f9f7 2778 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 2779 /**
<> 144:ef7eb2e8f9f7 2780 * @brief Get ADC regular group conversion result.
<> 144:ef7eb2e8f9f7 2781 * @note Reading register DR automatically clears ADC flag EOC
<> 144:ef7eb2e8f9f7 2782 * (ADC group regular end of unitary conversion).
<> 144:ef7eb2e8f9f7 2783 * @note This function does not clear ADC flag EOS
<> 144:ef7eb2e8f9f7 2784 * (ADC group regular end of sequence conversion).
<> 144:ef7eb2e8f9f7 2785 * Occurrence of flag EOS rising:
<> 144:ef7eb2e8f9f7 2786 * - If sequencer is composed of 1 rank, flag EOS is equivalent
<> 144:ef7eb2e8f9f7 2787 * to flag EOC.
<> 144:ef7eb2e8f9f7 2788 * - If sequencer is composed of several ranks, during the scan
<> 144:ef7eb2e8f9f7 2789 * sequence flag EOC only is raised, at the end of the scan sequence
<> 144:ef7eb2e8f9f7 2790 * both flags EOC and EOS are raised.
<> 144:ef7eb2e8f9f7 2791 * To clear this flag, either use function:
<> 144:ef7eb2e8f9f7 2792 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
<> 144:ef7eb2e8f9f7 2793 * model polling: @ref HAL_ADC_PollForConversion()
<> 144:ef7eb2e8f9f7 2794 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
<> 144:ef7eb2e8f9f7 2795 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 2796 * @retval ADC group regular conversion data
<> 144:ef7eb2e8f9f7 2797 */
<> 144:ef7eb2e8f9f7 2798 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 2799 {
<> 144:ef7eb2e8f9f7 2800 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2801 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 2802
<> 144:ef7eb2e8f9f7 2803 /* Note: EOC flag is not cleared here by software because automatically */
<> 144:ef7eb2e8f9f7 2804 /* cleared by hardware when reading register DR. */
<> 144:ef7eb2e8f9f7 2805
<> 144:ef7eb2e8f9f7 2806 /* Return ADC converted value */
<> 144:ef7eb2e8f9f7 2807 return hadc->Instance->DR;
<> 144:ef7eb2e8f9f7 2808 }
<> 144:ef7eb2e8f9f7 2809 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 2810
<> 144:ef7eb2e8f9f7 2811 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 2812 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 2813 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 2814 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 2815 /**
<> 144:ef7eb2e8f9f7 2816 * @brief Handles ADC interrupt request.
<> 144:ef7eb2e8f9f7 2817 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 2818 * @retval None
<> 144:ef7eb2e8f9f7 2819 */
<> 144:ef7eb2e8f9f7 2820 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 2821 {
<> 144:ef7eb2e8f9f7 2822 uint32_t overrun_error = 0; /* flag set if overrun occurrence has to be considered as an error */
<> 144:ef7eb2e8f9f7 2823 ADC_Common_TypeDef *tmpADC_Common;
<> 144:ef7eb2e8f9f7 2824 uint32_t tmp_cfgr = 0x0;
<> 144:ef7eb2e8f9f7 2825 uint32_t tmp_cfgr_jqm = 0x0;
<> 144:ef7eb2e8f9f7 2826
<> 144:ef7eb2e8f9f7 2827 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2828 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 2829 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
<> 144:ef7eb2e8f9f7 2830 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
<> 144:ef7eb2e8f9f7 2831
<> 144:ef7eb2e8f9f7 2832 /* ========== Check End of Conversion flag for regular group ========== */
<> 144:ef7eb2e8f9f7 2833 if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) ||
<> 144:ef7eb2e8f9f7 2834 (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) )
<> 144:ef7eb2e8f9f7 2835 {
<> 144:ef7eb2e8f9f7 2836 /* Update state machine on conversion status if not in error state */
<> 144:ef7eb2e8f9f7 2837 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
<> 144:ef7eb2e8f9f7 2838 {
<> 144:ef7eb2e8f9f7 2839 /* Set ADC state */
<> 144:ef7eb2e8f9f7 2840 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
<> 144:ef7eb2e8f9f7 2841 }
<> 144:ef7eb2e8f9f7 2842
<> 144:ef7eb2e8f9f7 2843 /* Get relevant register CFGR in ADC instance of ADC master or slave */
<> 144:ef7eb2e8f9f7 2844 /* in function of multimode state (for devices with multimode */
<> 144:ef7eb2e8f9f7 2845 /* available). */
<> 144:ef7eb2e8f9f7 2846 if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
<> 144:ef7eb2e8f9f7 2847 {
<> 144:ef7eb2e8f9f7 2848 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
<> 144:ef7eb2e8f9f7 2849 }
<> 144:ef7eb2e8f9f7 2850 else
<> 144:ef7eb2e8f9f7 2851 {
<> 144:ef7eb2e8f9f7 2852 tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
<> 144:ef7eb2e8f9f7 2853 }
<> 144:ef7eb2e8f9f7 2854
<> 144:ef7eb2e8f9f7 2855 /* Disable interruption if no further conversion upcoming by regular */
<> 144:ef7eb2e8f9f7 2856 /* external trigger or by continuous mode, */
<> 144:ef7eb2e8f9f7 2857 /* and if scan sequence if completed. */
<> 144:ef7eb2e8f9f7 2858 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 144:ef7eb2e8f9f7 2859 (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == RESET) )
<> 144:ef7eb2e8f9f7 2860 {
<> 144:ef7eb2e8f9f7 2861 /* If End of Sequence is reached, disable interrupts */
<> 144:ef7eb2e8f9f7 2862 if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
<> 144:ef7eb2e8f9f7 2863 {
<> 144:ef7eb2e8f9f7 2864 /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
<> 144:ef7eb2e8f9f7 2865 /* ADSTART==0 (no conversion on going) */
<> 144:ef7eb2e8f9f7 2866 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<> 144:ef7eb2e8f9f7 2867 {
<> 144:ef7eb2e8f9f7 2868 /* Disable ADC end of sequence conversion interrupt */
<> 144:ef7eb2e8f9f7 2869 /* Note: Overrun interrupt was enabled with EOC interrupt in */
<> 144:ef7eb2e8f9f7 2870 /* HAL_Start_IT(), but is not disabled here because can be used */
<> 144:ef7eb2e8f9f7 2871 /* by overrun IRQ process below. */
<> 144:ef7eb2e8f9f7 2872 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
<> 144:ef7eb2e8f9f7 2873
<> 144:ef7eb2e8f9f7 2874 /* Set ADC state */
<> 144:ef7eb2e8f9f7 2875 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 2876
<> 144:ef7eb2e8f9f7 2877 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<> 144:ef7eb2e8f9f7 2878 {
<> 144:ef7eb2e8f9f7 2879 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 2880 }
<> 144:ef7eb2e8f9f7 2881 }
<> 144:ef7eb2e8f9f7 2882 else
<> 144:ef7eb2e8f9f7 2883 {
<> 144:ef7eb2e8f9f7 2884 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 2885 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 2886
<> 144:ef7eb2e8f9f7 2887 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 2888 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 2889 }
<> 144:ef7eb2e8f9f7 2890 }
<> 144:ef7eb2e8f9f7 2891 }
<> 144:ef7eb2e8f9f7 2892
<> 144:ef7eb2e8f9f7 2893 /* Conversion complete callback */
<> 144:ef7eb2e8f9f7 2894 /* Note: into callback, to determine if conversion has been triggered */
<> 144:ef7eb2e8f9f7 2895 /* from EOC or EOS, possibility to use: */
<> 144:ef7eb2e8f9f7 2896 /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
<> 144:ef7eb2e8f9f7 2897 HAL_ADC_ConvCpltCallback(hadc);
<> 144:ef7eb2e8f9f7 2898
<> 144:ef7eb2e8f9f7 2899
<> 144:ef7eb2e8f9f7 2900 /* Clear regular group conversion flag */
<> 144:ef7eb2e8f9f7 2901 /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
<> 144:ef7eb2e8f9f7 2902 /* conversion flags clear induces the release of the preserved */
<> 144:ef7eb2e8f9f7 2903 /* data. */
<> 144:ef7eb2e8f9f7 2904 /* Therefore, if the preserved data value is needed, it must be */
<> 144:ef7eb2e8f9f7 2905 /* read preliminarily into HAL_ADC_ConvCpltCallback(). */
<> 144:ef7eb2e8f9f7 2906 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) );
<> 144:ef7eb2e8f9f7 2907 }
<> 144:ef7eb2e8f9f7 2908
<> 144:ef7eb2e8f9f7 2909
<> 144:ef7eb2e8f9f7 2910 /* ========== Check End of Conversion flag for injected group ========== */
<> 144:ef7eb2e8f9f7 2911 if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC)) ||
<> 144:ef7eb2e8f9f7 2912 (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOS)) )
<> 144:ef7eb2e8f9f7 2913 {
<> 144:ef7eb2e8f9f7 2914 /* Set ADC state */
<> 144:ef7eb2e8f9f7 2915 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
<> 144:ef7eb2e8f9f7 2916
<> 144:ef7eb2e8f9f7 2917 /* Get relevant register CFGR in ADC instance of ADC master or slave */
<> 144:ef7eb2e8f9f7 2918 /* in function of multimode state (for devices with multimode */
<> 144:ef7eb2e8f9f7 2919 /* available). */
<> 144:ef7eb2e8f9f7 2920 if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
<> 144:ef7eb2e8f9f7 2921 {
<> 144:ef7eb2e8f9f7 2922 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
<> 144:ef7eb2e8f9f7 2923 }
<> 144:ef7eb2e8f9f7 2924 else
<> 144:ef7eb2e8f9f7 2925 {
<> 144:ef7eb2e8f9f7 2926 tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
<> 144:ef7eb2e8f9f7 2927 }
<> 144:ef7eb2e8f9f7 2928
<> 144:ef7eb2e8f9f7 2929 /* Disable interruption if no further conversion upcoming by injected */
<> 144:ef7eb2e8f9f7 2930 /* external trigger or by automatic injected conversion with regular */
<> 144:ef7eb2e8f9f7 2931 /* group having no further conversion upcoming (same conditions as */
<> 144:ef7eb2e8f9f7 2932 /* regular group interruption disabling above), */
<> 144:ef7eb2e8f9f7 2933 /* and if injected scan sequence is completed. */
<> 144:ef7eb2e8f9f7 2934 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
<> 144:ef7eb2e8f9f7 2935 ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) &&
<> 144:ef7eb2e8f9f7 2936 (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 144:ef7eb2e8f9f7 2937 (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) ) )
<> 144:ef7eb2e8f9f7 2938 {
<> 144:ef7eb2e8f9f7 2939 /* If End of Sequence is reached, disable interrupts */
<> 144:ef7eb2e8f9f7 2940 if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
<> 144:ef7eb2e8f9f7 2941 {
<> 144:ef7eb2e8f9f7 2942
<> 144:ef7eb2e8f9f7 2943 /* Get relevant register CFGR in ADC instance of ADC master or slave */
<> 144:ef7eb2e8f9f7 2944 /* in function of multimode state (for devices with multimode */
<> 144:ef7eb2e8f9f7 2945 /* available). */
<> 144:ef7eb2e8f9f7 2946 if (ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc))
<> 144:ef7eb2e8f9f7 2947 {
<> 144:ef7eb2e8f9f7 2948 tmp_cfgr_jqm = READ_REG(hadc->Instance->CFGR);
<> 144:ef7eb2e8f9f7 2949 }
<> 144:ef7eb2e8f9f7 2950 else
<> 144:ef7eb2e8f9f7 2951 {
<> 144:ef7eb2e8f9f7 2952 tmp_cfgr_jqm = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
<> 144:ef7eb2e8f9f7 2953 }
<> 144:ef7eb2e8f9f7 2954
<> 144:ef7eb2e8f9f7 2955 /* Particular case if injected contexts queue is enabled: */
<> 144:ef7eb2e8f9f7 2956 /* when the last context has been fully processed, JSQR is reset */
<> 144:ef7eb2e8f9f7 2957 /* by the hardware. Even if no injected conversion is planned to come */
<> 144:ef7eb2e8f9f7 2958 /* (queue empty, triggers are ignored), it can start again */
<> 144:ef7eb2e8f9f7 2959 /* immediately after setting a new context (JADSTART is still set). */
<> 144:ef7eb2e8f9f7 2960 /* Therefore, state of HAL ADC injected group is kept to busy. */
<> 144:ef7eb2e8f9f7 2961 if(READ_BIT(tmp_cfgr_jqm, ADC_CFGR_JQM) == RESET)
<> 144:ef7eb2e8f9f7 2962 {
<> 144:ef7eb2e8f9f7 2963 /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
<> 144:ef7eb2e8f9f7 2964 /* JADSTART==0 (no conversion on going) */
<> 144:ef7eb2e8f9f7 2965 if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
<> 144:ef7eb2e8f9f7 2966 {
<> 144:ef7eb2e8f9f7 2967 /* Disable ADC end of sequence conversion interrupt */
<> 144:ef7eb2e8f9f7 2968 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
<> 144:ef7eb2e8f9f7 2969
<> 144:ef7eb2e8f9f7 2970 /* Set ADC state */
<> 144:ef7eb2e8f9f7 2971 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 2972
<> 144:ef7eb2e8f9f7 2973 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
<> 144:ef7eb2e8f9f7 2974 {
<> 144:ef7eb2e8f9f7 2975 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 2976 }
<> 144:ef7eb2e8f9f7 2977 }
<> 144:ef7eb2e8f9f7 2978 else
<> 144:ef7eb2e8f9f7 2979 {
<> 144:ef7eb2e8f9f7 2980 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 2981 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 2982
<> 144:ef7eb2e8f9f7 2983 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 2984 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 2985 }
<> 144:ef7eb2e8f9f7 2986 }
<> 144:ef7eb2e8f9f7 2987 }
<> 144:ef7eb2e8f9f7 2988 }
<> 144:ef7eb2e8f9f7 2989
<> 144:ef7eb2e8f9f7 2990 /* Conversion complete callback */
<> 144:ef7eb2e8f9f7 2991 /* Note: into callback, to determine if conversion has been triggered */
<> 144:ef7eb2e8f9f7 2992 /* from JEOC or JEOS, possibility to use: */
<> 144:ef7eb2e8f9f7 2993 /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) " */
<> 144:ef7eb2e8f9f7 2994 HAL_ADCEx_InjectedConvCpltCallback(hadc);
<> 144:ef7eb2e8f9f7 2995
<> 144:ef7eb2e8f9f7 2996 /* Clear injected group conversion flag */
<> 144:ef7eb2e8f9f7 2997 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
<> 144:ef7eb2e8f9f7 2998 }
<> 144:ef7eb2e8f9f7 2999
<> 144:ef7eb2e8f9f7 3000 /* ========== Check analog watchdog 1 flag ========== */
<> 144:ef7eb2e8f9f7 3001 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD1) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD1))
<> 144:ef7eb2e8f9f7 3002 {
<> 144:ef7eb2e8f9f7 3003 /* Set ADC state */
<> 144:ef7eb2e8f9f7 3004 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
<> 144:ef7eb2e8f9f7 3005
<> 144:ef7eb2e8f9f7 3006 /* Level out of window 1 callback */
<> 144:ef7eb2e8f9f7 3007 HAL_ADC_LevelOutOfWindowCallback(hadc);
<> 144:ef7eb2e8f9f7 3008 /* Clear ADC analog watchdog flag */
<> 144:ef7eb2e8f9f7 3009 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
<> 144:ef7eb2e8f9f7 3010 }
<> 144:ef7eb2e8f9f7 3011
<> 144:ef7eb2e8f9f7 3012 /* ========== Check analog watchdog 2 flag ========== */
<> 144:ef7eb2e8f9f7 3013 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD2) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD2))
<> 144:ef7eb2e8f9f7 3014 {
<> 144:ef7eb2e8f9f7 3015 /* Set ADC state */
<> 144:ef7eb2e8f9f7 3016 SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
<> 144:ef7eb2e8f9f7 3017
<> 144:ef7eb2e8f9f7 3018 /* Level out of window 2 callback */
<> 144:ef7eb2e8f9f7 3019 HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
<> 144:ef7eb2e8f9f7 3020 /* Clear ADC analog watchdog flag */
<> 144:ef7eb2e8f9f7 3021 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
<> 144:ef7eb2e8f9f7 3022 }
<> 144:ef7eb2e8f9f7 3023
<> 144:ef7eb2e8f9f7 3024 /* ========== Check analog watchdog 3 flag ========== */
<> 144:ef7eb2e8f9f7 3025 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD3) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD3))
<> 144:ef7eb2e8f9f7 3026 {
<> 144:ef7eb2e8f9f7 3027 /* Set ADC state */
<> 144:ef7eb2e8f9f7 3028 SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
<> 144:ef7eb2e8f9f7 3029
<> 144:ef7eb2e8f9f7 3030 /* Level out of window 3 callback */
<> 144:ef7eb2e8f9f7 3031 HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
<> 144:ef7eb2e8f9f7 3032 /* Clear ADC analog watchdog flag */
<> 144:ef7eb2e8f9f7 3033 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
<> 144:ef7eb2e8f9f7 3034 }
<> 144:ef7eb2e8f9f7 3035
<> 144:ef7eb2e8f9f7 3036 /* ========== Check Overrun flag ========== */
<> 144:ef7eb2e8f9f7 3037 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR))
<> 144:ef7eb2e8f9f7 3038 {
<> 144:ef7eb2e8f9f7 3039 /* If overrun is set to overwrite previous data (default setting), */
<> 144:ef7eb2e8f9f7 3040 /* overrun event is not considered as an error. */
<> 144:ef7eb2e8f9f7 3041 /* (cf ref manual "Managing conversions without using the DMA and */
<> 144:ef7eb2e8f9f7 3042 /* without overrun ") */
<> 144:ef7eb2e8f9f7 3043 /* Exception for usage with DMA overrun event always considered as an */
<> 144:ef7eb2e8f9f7 3044 /* error. */
<> 144:ef7eb2e8f9f7 3045 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
<> 144:ef7eb2e8f9f7 3046 {
<> 144:ef7eb2e8f9f7 3047 overrun_error = 1;
<> 144:ef7eb2e8f9f7 3048 }
<> 144:ef7eb2e8f9f7 3049 else
<> 144:ef7eb2e8f9f7 3050 {
<> 144:ef7eb2e8f9f7 3051 /* Pointer to the common control register to which is belonging hadc */
<> 144:ef7eb2e8f9f7 3052 /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
<> 144:ef7eb2e8f9f7 3053 /* control registers) */
<> 144:ef7eb2e8f9f7 3054 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
<> 144:ef7eb2e8f9f7 3055
<> 144:ef7eb2e8f9f7 3056 /* Check DMA configuration, depending on MultiMode set or not */
<> 144:ef7eb2e8f9f7 3057 if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI) == ADC_MODE_INDEPENDENT)
<> 144:ef7eb2e8f9f7 3058 {
<> 144:ef7eb2e8f9f7 3059 if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN))
<> 144:ef7eb2e8f9f7 3060 {
<> 144:ef7eb2e8f9f7 3061 overrun_error = 1;
<> 144:ef7eb2e8f9f7 3062 }
<> 144:ef7eb2e8f9f7 3063 }
<> 144:ef7eb2e8f9f7 3064 else
<> 144:ef7eb2e8f9f7 3065 {
<> 144:ef7eb2e8f9f7 3066 /* MultiMode is enabled, Common Control Register MDMA bits must be checked */
<> 144:ef7eb2e8f9f7 3067 if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA) != RESET)
<> 144:ef7eb2e8f9f7 3068 {
<> 144:ef7eb2e8f9f7 3069 overrun_error = 1;
<> 144:ef7eb2e8f9f7 3070 }
<> 144:ef7eb2e8f9f7 3071 }
<> 144:ef7eb2e8f9f7 3072 }
<> 144:ef7eb2e8f9f7 3073
<> 144:ef7eb2e8f9f7 3074 if (overrun_error == 1)
<> 144:ef7eb2e8f9f7 3075 {
<> 144:ef7eb2e8f9f7 3076 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 3077 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
<> 144:ef7eb2e8f9f7 3078
<> 144:ef7eb2e8f9f7 3079 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 3080 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
<> 144:ef7eb2e8f9f7 3081
<> 144:ef7eb2e8f9f7 3082 /* Error callback */
<> 144:ef7eb2e8f9f7 3083 HAL_ADC_ErrorCallback(hadc);
<> 144:ef7eb2e8f9f7 3084 }
<> 144:ef7eb2e8f9f7 3085
<> 144:ef7eb2e8f9f7 3086 /* Clear the Overrun flag */
<> 144:ef7eb2e8f9f7 3087 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
<> 144:ef7eb2e8f9f7 3088
<> 144:ef7eb2e8f9f7 3089 }
<> 144:ef7eb2e8f9f7 3090
<> 144:ef7eb2e8f9f7 3091
<> 144:ef7eb2e8f9f7 3092 /* ========== Check Injected context queue overflow flag ========== */
<> 144:ef7eb2e8f9f7 3093 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JQOVF) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JQOVF))
<> 144:ef7eb2e8f9f7 3094 {
<> 144:ef7eb2e8f9f7 3095 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 3096 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
<> 144:ef7eb2e8f9f7 3097
<> 144:ef7eb2e8f9f7 3098 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 3099 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
<> 144:ef7eb2e8f9f7 3100
<> 144:ef7eb2e8f9f7 3101 /* Clear the Injected context queue overflow flag */
<> 144:ef7eb2e8f9f7 3102 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
<> 144:ef7eb2e8f9f7 3103
<> 144:ef7eb2e8f9f7 3104 /* Error callback */
<> 144:ef7eb2e8f9f7 3105 HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
<> 144:ef7eb2e8f9f7 3106 }
<> 144:ef7eb2e8f9f7 3107
<> 144:ef7eb2e8f9f7 3108 }
<> 144:ef7eb2e8f9f7 3109 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 3110 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 3111 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 3112 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 3113
<> 144:ef7eb2e8f9f7 3114 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 3115 /**
<> 144:ef7eb2e8f9f7 3116 * @brief Handles ADC interrupt request
<> 144:ef7eb2e8f9f7 3117 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 3118 * @retval None
<> 144:ef7eb2e8f9f7 3119 */
<> 144:ef7eb2e8f9f7 3120 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 3121 {
<> 144:ef7eb2e8f9f7 3122 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3123 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 3124 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
<> 144:ef7eb2e8f9f7 3125 assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
<> 144:ef7eb2e8f9f7 3126
<> 144:ef7eb2e8f9f7 3127
<> 144:ef7eb2e8f9f7 3128 /* ========== Check End of Conversion flag for regular group ========== */
<> 144:ef7eb2e8f9f7 3129 if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC))
<> 144:ef7eb2e8f9f7 3130 {
<> 144:ef7eb2e8f9f7 3131 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) )
<> 144:ef7eb2e8f9f7 3132 {
<> 144:ef7eb2e8f9f7 3133 /* Update state machine on conversion status if not in error state */
<> 144:ef7eb2e8f9f7 3134 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
<> 144:ef7eb2e8f9f7 3135 {
<> 144:ef7eb2e8f9f7 3136 /* Set ADC state */
<> 144:ef7eb2e8f9f7 3137 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
<> 144:ef7eb2e8f9f7 3138 }
<> 144:ef7eb2e8f9f7 3139
<> 144:ef7eb2e8f9f7 3140 /* Determine whether any further conversion upcoming on group regular */
<> 144:ef7eb2e8f9f7 3141 /* by external trigger, continuous mode or scan sequence on going. */
<> 144:ef7eb2e8f9f7 3142 /* Note: On STM32F37x devices, in case of sequencer enabled */
<> 144:ef7eb2e8f9f7 3143 /* (several ranks selected), end of conversion flag is raised */
<> 144:ef7eb2e8f9f7 3144 /* at the end of the sequence. */
<> 144:ef7eb2e8f9f7 3145 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 144:ef7eb2e8f9f7 3146 (hadc->Init.ContinuousConvMode == DISABLE) )
<> 144:ef7eb2e8f9f7 3147 {
<> 144:ef7eb2e8f9f7 3148 /* Disable ADC end of single conversion interrupt */
<> 144:ef7eb2e8f9f7 3149 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
<> 144:ef7eb2e8f9f7 3150
<> 144:ef7eb2e8f9f7 3151 /* Set ADC state */
<> 144:ef7eb2e8f9f7 3152 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 3153
<> 144:ef7eb2e8f9f7 3154 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<> 144:ef7eb2e8f9f7 3155 {
<> 144:ef7eb2e8f9f7 3156 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 3157 }
<> 144:ef7eb2e8f9f7 3158 }
<> 144:ef7eb2e8f9f7 3159
<> 144:ef7eb2e8f9f7 3160 /* Conversion complete callback */
<> 144:ef7eb2e8f9f7 3161 HAL_ADC_ConvCpltCallback(hadc);
<> 144:ef7eb2e8f9f7 3162
<> 144:ef7eb2e8f9f7 3163 /* Clear regular group conversion flag */
<> 144:ef7eb2e8f9f7 3164 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
<> 144:ef7eb2e8f9f7 3165 }
<> 144:ef7eb2e8f9f7 3166 }
<> 144:ef7eb2e8f9f7 3167
<> 144:ef7eb2e8f9f7 3168 /* ========== Check End of Conversion flag for injected group ========== */
<> 144:ef7eb2e8f9f7 3169 if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC))
<> 144:ef7eb2e8f9f7 3170 {
<> 144:ef7eb2e8f9f7 3171 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))
<> 144:ef7eb2e8f9f7 3172 {
<> 144:ef7eb2e8f9f7 3173 /* Update state machine on conversion status if not in error state */
<> 144:ef7eb2e8f9f7 3174 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
<> 144:ef7eb2e8f9f7 3175 {
<> 144:ef7eb2e8f9f7 3176 /* Set ADC state */
<> 144:ef7eb2e8f9f7 3177 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
<> 144:ef7eb2e8f9f7 3178 }
<> 144:ef7eb2e8f9f7 3179
<> 144:ef7eb2e8f9f7 3180 /* Determine whether any further conversion upcoming on group injected */
<> 144:ef7eb2e8f9f7 3181 /* by external trigger, scan sequence on going or by automatic injected */
<> 144:ef7eb2e8f9f7 3182 /* conversion from group regular (same conditions as group regular */
<> 144:ef7eb2e8f9f7 3183 /* interruption disabling above). */
<> 144:ef7eb2e8f9f7 3184 /* Note: On STM32F37x devices, in case of sequencer enabled */
<> 144:ef7eb2e8f9f7 3185 /* (several ranks selected), end of conversion flag is raised */
<> 144:ef7eb2e8f9f7 3186 /* at the end of the sequence. */
<> 144:ef7eb2e8f9f7 3187 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
<> 144:ef7eb2e8f9f7 3188 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
<> 144:ef7eb2e8f9f7 3189 (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 144:ef7eb2e8f9f7 3190 (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
<> 144:ef7eb2e8f9f7 3191 {
<> 144:ef7eb2e8f9f7 3192 /* Disable ADC end of single conversion interrupt */
<> 144:ef7eb2e8f9f7 3193 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
<> 144:ef7eb2e8f9f7 3194
<> 144:ef7eb2e8f9f7 3195 /* Set ADC state */
<> 144:ef7eb2e8f9f7 3196 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 3197
<> 144:ef7eb2e8f9f7 3198 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
<> 144:ef7eb2e8f9f7 3199 {
<> 144:ef7eb2e8f9f7 3200 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 3201 }
<> 144:ef7eb2e8f9f7 3202 }
<> 144:ef7eb2e8f9f7 3203
<> 144:ef7eb2e8f9f7 3204 /* Conversion complete callback */
<> 144:ef7eb2e8f9f7 3205 HAL_ADCEx_InjectedConvCpltCallback(hadc);
<> 144:ef7eb2e8f9f7 3206
<> 144:ef7eb2e8f9f7 3207 /* Clear injected group conversion flag */
<> 144:ef7eb2e8f9f7 3208 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
<> 144:ef7eb2e8f9f7 3209 }
<> 144:ef7eb2e8f9f7 3210 }
<> 144:ef7eb2e8f9f7 3211
<> 144:ef7eb2e8f9f7 3212 /* ========== Check Analog watchdog flags ========== */
<> 144:ef7eb2e8f9f7 3213 if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
<> 144:ef7eb2e8f9f7 3214 {
<> 144:ef7eb2e8f9f7 3215 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
<> 144:ef7eb2e8f9f7 3216 {
<> 144:ef7eb2e8f9f7 3217 /* Set ADC state */
<> 144:ef7eb2e8f9f7 3218 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
<> 144:ef7eb2e8f9f7 3219
<> 144:ef7eb2e8f9f7 3220 /* Level out of window callback */
<> 144:ef7eb2e8f9f7 3221 HAL_ADC_LevelOutOfWindowCallback(hadc);
<> 144:ef7eb2e8f9f7 3222
<> 144:ef7eb2e8f9f7 3223 /* Clear the ADC analog watchdog flag */
<> 144:ef7eb2e8f9f7 3224 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
<> 144:ef7eb2e8f9f7 3225 }
<> 144:ef7eb2e8f9f7 3226 }
<> 144:ef7eb2e8f9f7 3227
<> 144:ef7eb2e8f9f7 3228 }
<> 144:ef7eb2e8f9f7 3229 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 3230
<> 144:ef7eb2e8f9f7 3231
<> 144:ef7eb2e8f9f7 3232 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 3233 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 3234 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 3235 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 3236 /**
<> 144:ef7eb2e8f9f7 3237 * @brief Perform an ADC automatic self-calibration
<> 144:ef7eb2e8f9f7 3238 * Calibration prerequisite: ADC must be disabled (execute this
<> 144:ef7eb2e8f9f7 3239 * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
<> 144:ef7eb2e8f9f7 3240 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 3241 * @param SingleDiff: Selection of single-ended or differential input
<> 144:ef7eb2e8f9f7 3242 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3243 * @arg ADC_SINGLE_ENDED: Channel in mode input single ended
<> 144:ef7eb2e8f9f7 3244 * @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
<> 144:ef7eb2e8f9f7 3245 * @retval HAL status
<> 144:ef7eb2e8f9f7 3246 */
<> 144:ef7eb2e8f9f7 3247 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
<> 144:ef7eb2e8f9f7 3248 {
<> 144:ef7eb2e8f9f7 3249 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 3250 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 3251
<> 144:ef7eb2e8f9f7 3252 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3253 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 3254 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
<> 144:ef7eb2e8f9f7 3255
<> 144:ef7eb2e8f9f7 3256 /* Process locked */
<> 144:ef7eb2e8f9f7 3257 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 3258
<> 144:ef7eb2e8f9f7 3259 /* Calibration prerequisite: ADC must be disabled. */
<> 144:ef7eb2e8f9f7 3260
<> 144:ef7eb2e8f9f7 3261 /* Disable the ADC (if not already disabled) */
<> 144:ef7eb2e8f9f7 3262 tmp_hal_status = ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 3263
<> 144:ef7eb2e8f9f7 3264 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 3265 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 3266 {
<> 144:ef7eb2e8f9f7 3267 /* Change ADC state */
<> 144:ef7eb2e8f9f7 3268 hadc->State = HAL_ADC_STATE_READY;
<> 144:ef7eb2e8f9f7 3269
<> 144:ef7eb2e8f9f7 3270 /* Select calibration mode single ended or differential ended */
<> 144:ef7eb2e8f9f7 3271 hadc->Instance->CR &= (~ADC_CR_ADCALDIF);
<> 144:ef7eb2e8f9f7 3272 if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
<> 144:ef7eb2e8f9f7 3273 {
<> 144:ef7eb2e8f9f7 3274 hadc->Instance->CR |= ADC_CR_ADCALDIF;
<> 144:ef7eb2e8f9f7 3275 }
<> 144:ef7eb2e8f9f7 3276
<> 144:ef7eb2e8f9f7 3277 /* Start ADC calibration */
<> 144:ef7eb2e8f9f7 3278 hadc->Instance->CR |= ADC_CR_ADCAL;
<> 144:ef7eb2e8f9f7 3279
<> 144:ef7eb2e8f9f7 3280 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 3281
<> 144:ef7eb2e8f9f7 3282 /* Wait for calibration completion */
<> 144:ef7eb2e8f9f7 3283 while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
<> 144:ef7eb2e8f9f7 3284 {
<> 144:ef7eb2e8f9f7 3285 if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
<> 144:ef7eb2e8f9f7 3286 {
<> 144:ef7eb2e8f9f7 3287 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 3288 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 3289 HAL_ADC_STATE_BUSY_INTERNAL,
<> 144:ef7eb2e8f9f7 3290 HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 3291
<> 144:ef7eb2e8f9f7 3292 /* Process unlocked */
<> 144:ef7eb2e8f9f7 3293 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 3294
<> 144:ef7eb2e8f9f7 3295 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 3296 }
<> 144:ef7eb2e8f9f7 3297 }
<> 144:ef7eb2e8f9f7 3298
<> 144:ef7eb2e8f9f7 3299 /* Set ADC state */
<> 144:ef7eb2e8f9f7 3300 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 3301 HAL_ADC_STATE_BUSY_INTERNAL,
<> 144:ef7eb2e8f9f7 3302 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 3303 }
<> 144:ef7eb2e8f9f7 3304 else
<> 144:ef7eb2e8f9f7 3305 {
<> 144:ef7eb2e8f9f7 3306 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 3307 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 3308 }
<> 144:ef7eb2e8f9f7 3309
<> 144:ef7eb2e8f9f7 3310 /* Process unlocked */
<> 144:ef7eb2e8f9f7 3311 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 3312
<> 144:ef7eb2e8f9f7 3313 /* Return function status */
<> 144:ef7eb2e8f9f7 3314 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 3315 }
<> 144:ef7eb2e8f9f7 3316 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 3317 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 3318 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 3319 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 3320
<> 144:ef7eb2e8f9f7 3321 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 3322 /**
<> 144:ef7eb2e8f9f7 3323 * @brief Perform an ADC automatic self-calibration
<> 144:ef7eb2e8f9f7 3324 * Calibration prerequisite: ADC must be disabled (execute this
<> 144:ef7eb2e8f9f7 3325 * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
<> 144:ef7eb2e8f9f7 3326 * During calibration process, ADC is enabled. ADC is let enabled at
<> 144:ef7eb2e8f9f7 3327 * the completion of this function.
<> 144:ef7eb2e8f9f7 3328 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 3329 * @retval HAL status
<> 144:ef7eb2e8f9f7 3330 */
<> 144:ef7eb2e8f9f7 3331 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 3332 {
<> 144:ef7eb2e8f9f7 3333 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 3334 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 3335 __IO uint32_t wait_loop_index = 0;
<> 144:ef7eb2e8f9f7 3336
<> 144:ef7eb2e8f9f7 3337 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3338 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 3339
<> 144:ef7eb2e8f9f7 3340 /* Process locked */
<> 144:ef7eb2e8f9f7 3341 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 3342
<> 144:ef7eb2e8f9f7 3343 /* 1. Calibration prerequisite: */
<> 144:ef7eb2e8f9f7 3344 /* - ADC must be disabled for at least two ADC clock cycles in disable */
<> 144:ef7eb2e8f9f7 3345 /* mode before ADC enable */
<> 144:ef7eb2e8f9f7 3346 /* Stop potential conversion on going, on regular and injected groups */
<> 144:ef7eb2e8f9f7 3347 /* Disable ADC peripheral */
<> 144:ef7eb2e8f9f7 3348 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
<> 144:ef7eb2e8f9f7 3349
<> 144:ef7eb2e8f9f7 3350 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 3351 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 3352 {
<> 144:ef7eb2e8f9f7 3353 /* Set ADC state */
<> 144:ef7eb2e8f9f7 3354 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 3355 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 144:ef7eb2e8f9f7 3356 HAL_ADC_STATE_BUSY_INTERNAL);
<> 144:ef7eb2e8f9f7 3357
<> 144:ef7eb2e8f9f7 3358 /* Wait two ADC clock cycles */
<> 144:ef7eb2e8f9f7 3359 while(wait_loop_index < ADC_CYCLE_WORST_CASE_CPU_CYCLES *2)
<> 144:ef7eb2e8f9f7 3360 {
<> 144:ef7eb2e8f9f7 3361 wait_loop_index++;
<> 144:ef7eb2e8f9f7 3362 }
<> 144:ef7eb2e8f9f7 3363
<> 144:ef7eb2e8f9f7 3364 /* 2. Enable the ADC peripheral */
<> 144:ef7eb2e8f9f7 3365 ADC_Enable(hadc);
<> 144:ef7eb2e8f9f7 3366
<> 144:ef7eb2e8f9f7 3367
<> 144:ef7eb2e8f9f7 3368 /* 3. Resets ADC calibration registers */
<> 144:ef7eb2e8f9f7 3369 SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL);
<> 144:ef7eb2e8f9f7 3370
<> 144:ef7eb2e8f9f7 3371 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 3372
<> 144:ef7eb2e8f9f7 3373 /* Wait for calibration reset completion */
<> 144:ef7eb2e8f9f7 3374 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL))
<> 144:ef7eb2e8f9f7 3375 {
<> 144:ef7eb2e8f9f7 3376 if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
<> 144:ef7eb2e8f9f7 3377 {
<> 144:ef7eb2e8f9f7 3378 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 3379 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 3380 HAL_ADC_STATE_BUSY_INTERNAL,
<> 144:ef7eb2e8f9f7 3381 HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 3382
<> 144:ef7eb2e8f9f7 3383 /* Process unlocked */
<> 144:ef7eb2e8f9f7 3384 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 3385
<> 144:ef7eb2e8f9f7 3386 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 3387 }
<> 144:ef7eb2e8f9f7 3388 }
<> 144:ef7eb2e8f9f7 3389
<> 144:ef7eb2e8f9f7 3390
<> 144:ef7eb2e8f9f7 3391 /* 4. Start ADC calibration */
<> 144:ef7eb2e8f9f7 3392 SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL);
<> 144:ef7eb2e8f9f7 3393
<> 144:ef7eb2e8f9f7 3394 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 3395
<> 144:ef7eb2e8f9f7 3396 /* Wait for calibration completion */
<> 144:ef7eb2e8f9f7 3397 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL))
<> 144:ef7eb2e8f9f7 3398 {
<> 144:ef7eb2e8f9f7 3399 if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
<> 144:ef7eb2e8f9f7 3400 {
<> 144:ef7eb2e8f9f7 3401 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 3402 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 3403 HAL_ADC_STATE_BUSY_INTERNAL,
<> 144:ef7eb2e8f9f7 3404 HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 3405
<> 144:ef7eb2e8f9f7 3406 /* Process unlocked */
<> 144:ef7eb2e8f9f7 3407 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 3408
<> 144:ef7eb2e8f9f7 3409 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 3410 }
<> 144:ef7eb2e8f9f7 3411 }
<> 144:ef7eb2e8f9f7 3412
<> 144:ef7eb2e8f9f7 3413 /* Set ADC state */
<> 144:ef7eb2e8f9f7 3414 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 3415 HAL_ADC_STATE_BUSY_INTERNAL,
<> 144:ef7eb2e8f9f7 3416 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 3417 }
<> 144:ef7eb2e8f9f7 3418
<> 144:ef7eb2e8f9f7 3419 /* Process unlocked */
<> 144:ef7eb2e8f9f7 3420 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 3421
<> 144:ef7eb2e8f9f7 3422 /* Return function status */
<> 144:ef7eb2e8f9f7 3423 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 3424 }
<> 144:ef7eb2e8f9f7 3425
<> 144:ef7eb2e8f9f7 3426 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 3427
<> 144:ef7eb2e8f9f7 3428 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 3429 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 3430 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 3431 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 3432 /**
<> 144:ef7eb2e8f9f7 3433 * @brief Get the calibration factor from automatic conversion result
<> 144:ef7eb2e8f9f7 3434 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 3435 * @param SingleDiff: Selection of single-ended or differential input
<> 144:ef7eb2e8f9f7 3436 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3437 * @arg ADC_SINGLE_ENDED: Channel in mode input single ended
<> 144:ef7eb2e8f9f7 3438 * @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
<> 144:ef7eb2e8f9f7 3439 * @retval Converted value
<> 144:ef7eb2e8f9f7 3440 */
<> 144:ef7eb2e8f9f7 3441 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
<> 144:ef7eb2e8f9f7 3442 {
<> 144:ef7eb2e8f9f7 3443 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3444 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 3445 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
<> 144:ef7eb2e8f9f7 3446
<> 144:ef7eb2e8f9f7 3447 /* Return the selected ADC calibration value */
<> 144:ef7eb2e8f9f7 3448 if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
<> 144:ef7eb2e8f9f7 3449 {
<> 144:ef7eb2e8f9f7 3450 return ADC_CALFACT_DIFF_GET(hadc->Instance->CALFACT);
<> 144:ef7eb2e8f9f7 3451 }
<> 144:ef7eb2e8f9f7 3452 else
<> 144:ef7eb2e8f9f7 3453 {
<> 144:ef7eb2e8f9f7 3454 return ((hadc->Instance->CALFACT) & ADC_CALFACT_CALFACT_S);
<> 144:ef7eb2e8f9f7 3455 }
<> 144:ef7eb2e8f9f7 3456 }
<> 144:ef7eb2e8f9f7 3457 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 3458 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 3459 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 3460 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 3461
<> 144:ef7eb2e8f9f7 3462 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 3463 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 3464 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 3465 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 3466 /**
<> 144:ef7eb2e8f9f7 3467 * @brief Set the calibration factor to overwrite automatic conversion result. ADC must be enabled and no conversion on going.
<> 144:ef7eb2e8f9f7 3468 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 3469 * @param SingleDiff: Selection of single-ended or differential input
<> 144:ef7eb2e8f9f7 3470 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3471 * @arg ADC_SINGLE_ENDED: Channel in mode input single ended
<> 144:ef7eb2e8f9f7 3472 * @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
<> 144:ef7eb2e8f9f7 3473 * @param CalibrationFactor: Calibration factor (coded on 7 bits maximum)
<> 144:ef7eb2e8f9f7 3474 * @retval HAL state
<> 144:ef7eb2e8f9f7 3475 */
<> 144:ef7eb2e8f9f7 3476 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
<> 144:ef7eb2e8f9f7 3477 {
<> 144:ef7eb2e8f9f7 3478 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 3479
<> 144:ef7eb2e8f9f7 3480 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3481 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 3482 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
<> 144:ef7eb2e8f9f7 3483 assert_param(IS_ADC_CALFACT(CalibrationFactor));
<> 144:ef7eb2e8f9f7 3484
<> 144:ef7eb2e8f9f7 3485 /* Process locked */
<> 144:ef7eb2e8f9f7 3486 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 3487
<> 144:ef7eb2e8f9f7 3488 /* Verification of hardware constraints before modifying the calibration */
<> 144:ef7eb2e8f9f7 3489 /* factors register: ADC must be enabled, no conversion on going. */
<> 144:ef7eb2e8f9f7 3490 if ( (ADC_IS_ENABLE(hadc) != RESET) &&
<> 144:ef7eb2e8f9f7 3491 (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) )
<> 144:ef7eb2e8f9f7 3492 {
<> 144:ef7eb2e8f9f7 3493 /* Set the selected ADC calibration value */
<> 144:ef7eb2e8f9f7 3494 if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
<> 144:ef7eb2e8f9f7 3495 {
<> 144:ef7eb2e8f9f7 3496 MODIFY_REG(hadc->Instance->CALFACT ,
<> 144:ef7eb2e8f9f7 3497 ADC_CALFACT_CALFACT_D ,
<> 144:ef7eb2e8f9f7 3498 ADC_CALFACT_DIFF_SET(CalibrationFactor) );
<> 144:ef7eb2e8f9f7 3499 }
<> 144:ef7eb2e8f9f7 3500 else
<> 144:ef7eb2e8f9f7 3501 {
<> 144:ef7eb2e8f9f7 3502 MODIFY_REG(hadc->Instance->CALFACT,
<> 144:ef7eb2e8f9f7 3503 ADC_CALFACT_CALFACT_S ,
<> 144:ef7eb2e8f9f7 3504 CalibrationFactor );
<> 144:ef7eb2e8f9f7 3505 }
<> 144:ef7eb2e8f9f7 3506 }
<> 144:ef7eb2e8f9f7 3507 else
<> 144:ef7eb2e8f9f7 3508 {
<> 144:ef7eb2e8f9f7 3509 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 3510 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 3511
<> 144:ef7eb2e8f9f7 3512 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 3513 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 3514 }
<> 144:ef7eb2e8f9f7 3515
<> 144:ef7eb2e8f9f7 3516 /* Process unlocked */
<> 144:ef7eb2e8f9f7 3517 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 3518
<> 144:ef7eb2e8f9f7 3519 /* Return function status */
<> 144:ef7eb2e8f9f7 3520 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 3521 }
<> 144:ef7eb2e8f9f7 3522 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 3523 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 3524 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 3525 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 3526
<> 144:ef7eb2e8f9f7 3527 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 3528 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 3529 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 3530 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 3531 /**
<> 144:ef7eb2e8f9f7 3532 * @brief Enables ADC, starts conversion of injected group.
<> 144:ef7eb2e8f9f7 3533 * Interruptions enabled in this function: None.
<> 144:ef7eb2e8f9f7 3534 * @note Case of multimode enabled (for devices with several ADCs): This
<> 144:ef7eb2e8f9f7 3535 * function must be called for ADC slave first, then ADC master.
<> 144:ef7eb2e8f9f7 3536 * For ADC slave, ADC is enabled only (conversion is not started).
<> 144:ef7eb2e8f9f7 3537 * For ADC master, ADC is enabled and multimode conversion is started.
<> 144:ef7eb2e8f9f7 3538 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 3539 * @retval HAL status
<> 144:ef7eb2e8f9f7 3540 */
<> 144:ef7eb2e8f9f7 3541 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 3542 {
<> 144:ef7eb2e8f9f7 3543 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 3544
<> 144:ef7eb2e8f9f7 3545 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3546 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 3547
<> 144:ef7eb2e8f9f7 3548 /* Perform ADC enable and conversion start if no conversion is on going */
<> 144:ef7eb2e8f9f7 3549 if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
<> 144:ef7eb2e8f9f7 3550 {
<> 144:ef7eb2e8f9f7 3551 /* Process locked */
<> 144:ef7eb2e8f9f7 3552 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 3553
<> 144:ef7eb2e8f9f7 3554 /* Enable the ADC peripheral */
<> 144:ef7eb2e8f9f7 3555 tmp_hal_status = ADC_Enable(hadc);
<> 144:ef7eb2e8f9f7 3556
<> 144:ef7eb2e8f9f7 3557 /* Start conversion if ADC is effectively enabled */
<> 144:ef7eb2e8f9f7 3558 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 3559 {
<> 144:ef7eb2e8f9f7 3560 /* Set ADC state */
<> 144:ef7eb2e8f9f7 3561 /* - Clear state bitfield related to injected group conversion results */
<> 144:ef7eb2e8f9f7 3562 /* - Set state bitfield related to injected operation */
<> 144:ef7eb2e8f9f7 3563 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 3564 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
<> 144:ef7eb2e8f9f7 3565 HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 3566
<> 144:ef7eb2e8f9f7 3567 /* Case of independent mode or multimode(for devices with several ADCs):*/
<> 144:ef7eb2e8f9f7 3568 /* Set multimode state. */
<> 144:ef7eb2e8f9f7 3569 if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
<> 144:ef7eb2e8f9f7 3570 {
<> 144:ef7eb2e8f9f7 3571 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<> 144:ef7eb2e8f9f7 3572 }
<> 144:ef7eb2e8f9f7 3573 else
<> 144:ef7eb2e8f9f7 3574 {
<> 144:ef7eb2e8f9f7 3575 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<> 144:ef7eb2e8f9f7 3576 }
<> 144:ef7eb2e8f9f7 3577
<> 144:ef7eb2e8f9f7 3578 /* Check if a regular conversion is ongoing */
<> 144:ef7eb2e8f9f7 3579 /* Note: On this device, there is no ADC error code fields related to */
<> 144:ef7eb2e8f9f7 3580 /* conversions on group injected only. In case of conversion on */
<> 144:ef7eb2e8f9f7 3581 /* going on group regular, no error code is reset. */
<> 144:ef7eb2e8f9f7 3582 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
<> 144:ef7eb2e8f9f7 3583 {
<> 144:ef7eb2e8f9f7 3584 /* Reset ADC all error code fields */
<> 144:ef7eb2e8f9f7 3585 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 3586 }
<> 144:ef7eb2e8f9f7 3587
<> 144:ef7eb2e8f9f7 3588 /* Process unlocked */
<> 144:ef7eb2e8f9f7 3589 /* Unlock before starting ADC conversions: in case of potential */
<> 144:ef7eb2e8f9f7 3590 /* interruption, to let the process to ADC IRQ Handler. */
<> 144:ef7eb2e8f9f7 3591 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 3592
<> 144:ef7eb2e8f9f7 3593 /* Clear injected group conversion flag */
<> 144:ef7eb2e8f9f7 3594 /* (To ensure of no unknown state from potential previous ADC */
<> 144:ef7eb2e8f9f7 3595 /* operations) */
<> 144:ef7eb2e8f9f7 3596 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
<> 144:ef7eb2e8f9f7 3597
<> 144:ef7eb2e8f9f7 3598 /* Enable conversion of injected group, if automatic injected */
<> 144:ef7eb2e8f9f7 3599 /* conversion is disabled. */
<> 144:ef7eb2e8f9f7 3600 /* If software start has been selected, conversion starts immediately. */
<> 144:ef7eb2e8f9f7 3601 /* If external trigger has been selected, conversion will start at next */
<> 144:ef7eb2e8f9f7 3602 /* trigger event. */
<> 144:ef7eb2e8f9f7 3603 /* Case of multimode enabled (for devices with several ADCs): */
<> 144:ef7eb2e8f9f7 3604 /* - if ADC is slave, ADC is enabled only (conversion is not started). */
<> 144:ef7eb2e8f9f7 3605 /* - if ADC is master, ADC is enabled and conversion is started. */
<> 144:ef7eb2e8f9f7 3606 if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO) &&
<> 144:ef7eb2e8f9f7 3607 ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc) )
<> 144:ef7eb2e8f9f7 3608 {
<> 144:ef7eb2e8f9f7 3609 SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART);
<> 144:ef7eb2e8f9f7 3610 }
<> 144:ef7eb2e8f9f7 3611 }
<> 144:ef7eb2e8f9f7 3612 else
<> 144:ef7eb2e8f9f7 3613 {
<> 144:ef7eb2e8f9f7 3614 /* Process unlocked */
<> 144:ef7eb2e8f9f7 3615 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 3616 }
<> 144:ef7eb2e8f9f7 3617 }
<> 144:ef7eb2e8f9f7 3618 else
<> 144:ef7eb2e8f9f7 3619 {
<> 144:ef7eb2e8f9f7 3620 tmp_hal_status = HAL_BUSY;
<> 144:ef7eb2e8f9f7 3621 }
<> 144:ef7eb2e8f9f7 3622
<> 144:ef7eb2e8f9f7 3623 /* Return function status */
<> 144:ef7eb2e8f9f7 3624 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 3625 }
<> 144:ef7eb2e8f9f7 3626 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 3627 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 3628 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 3629 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 3630
<> 144:ef7eb2e8f9f7 3631 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 3632 /**
<> 144:ef7eb2e8f9f7 3633 * @brief Enables ADC, starts conversion of injected group.
<> 144:ef7eb2e8f9f7 3634 * Interruptions enabled in this function: None.
<> 144:ef7eb2e8f9f7 3635 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 3636 * @retval HAL status
<> 144:ef7eb2e8f9f7 3637 */
<> 144:ef7eb2e8f9f7 3638 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 3639 {
<> 144:ef7eb2e8f9f7 3640 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 3641
<> 144:ef7eb2e8f9f7 3642 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3643 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 3644
<> 144:ef7eb2e8f9f7 3645 /* Process locked */
<> 144:ef7eb2e8f9f7 3646 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 3647
<> 144:ef7eb2e8f9f7 3648 /* Enable the ADC peripheral */
<> 144:ef7eb2e8f9f7 3649 tmp_hal_status = ADC_Enable(hadc);
<> 144:ef7eb2e8f9f7 3650
<> 144:ef7eb2e8f9f7 3651 /* Start conversion if ADC is effectively enabled */
<> 144:ef7eb2e8f9f7 3652 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 3653 {
<> 144:ef7eb2e8f9f7 3654 /* Set ADC state */
<> 144:ef7eb2e8f9f7 3655 /* - Clear state bitfield related to injected group conversion results */
<> 144:ef7eb2e8f9f7 3656 /* - Set state bitfield related to injected operation */
<> 144:ef7eb2e8f9f7 3657 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 3658 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
<> 144:ef7eb2e8f9f7 3659 HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 3660
<> 144:ef7eb2e8f9f7 3661 /* Check if a regular conversion is ongoing */
<> 144:ef7eb2e8f9f7 3662 /* Note: On this device, there is no ADC error code fields related to */
<> 144:ef7eb2e8f9f7 3663 /* conversions on group injected only. In case of conversion on */
<> 144:ef7eb2e8f9f7 3664 /* going on group regular, no error code is reset. */
<> 144:ef7eb2e8f9f7 3665 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
<> 144:ef7eb2e8f9f7 3666 {
<> 144:ef7eb2e8f9f7 3667 /* Reset ADC all error code fields */
<> 144:ef7eb2e8f9f7 3668 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 3669 }
<> 144:ef7eb2e8f9f7 3670
<> 144:ef7eb2e8f9f7 3671 /* Process unlocked */
<> 144:ef7eb2e8f9f7 3672 /* Unlock before starting ADC conversions: in case of potential */
<> 144:ef7eb2e8f9f7 3673 /* interruption, to let the process to ADC IRQ Handler. */
<> 144:ef7eb2e8f9f7 3674 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 3675
<> 144:ef7eb2e8f9f7 3676 /* Clear injected group conversion flag */
<> 144:ef7eb2e8f9f7 3677 /* (To ensure of no unknown state from potential previous ADC operations) */
<> 144:ef7eb2e8f9f7 3678 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
<> 144:ef7eb2e8f9f7 3679
<> 144:ef7eb2e8f9f7 3680 /* Enable conversion of injected group. */
<> 144:ef7eb2e8f9f7 3681 /* If software start has been selected, conversion starts immediately. */
<> 144:ef7eb2e8f9f7 3682 /* If external trigger has been selected, conversion will start at next */
<> 144:ef7eb2e8f9f7 3683 /* trigger event. */
<> 144:ef7eb2e8f9f7 3684 /* If external trigger has been selected, conversion will start at next */
<> 144:ef7eb2e8f9f7 3685 /* trigger event. */
<> 144:ef7eb2e8f9f7 3686 /* If automatic injected conversion is enabled, conversion will start */
<> 144:ef7eb2e8f9f7 3687 /* after next regular group conversion. */
<> 144:ef7eb2e8f9f7 3688 if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
<> 144:ef7eb2e8f9f7 3689 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
<> 144:ef7eb2e8f9f7 3690 {
<> 144:ef7eb2e8f9f7 3691 /* Start ADC conversion on injected group with SW start */
<> 144:ef7eb2e8f9f7 3692 SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
<> 144:ef7eb2e8f9f7 3693 }
<> 144:ef7eb2e8f9f7 3694 else
<> 144:ef7eb2e8f9f7 3695 {
<> 144:ef7eb2e8f9f7 3696 /* Start ADC conversion on injected group with external trigger */
<> 144:ef7eb2e8f9f7 3697 SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
<> 144:ef7eb2e8f9f7 3698 }
<> 144:ef7eb2e8f9f7 3699 }
<> 144:ef7eb2e8f9f7 3700
<> 144:ef7eb2e8f9f7 3701 /* Return function status */
<> 144:ef7eb2e8f9f7 3702 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 3703 }
<> 144:ef7eb2e8f9f7 3704 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 3705
<> 144:ef7eb2e8f9f7 3706 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 3707 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 3708 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 3709 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 3710 /**
<> 144:ef7eb2e8f9f7 3711 * @brief Stop ADC group injected conversion (potential conversion on going
<> 144:ef7eb2e8f9f7 3712 * on ADC group regular is not impacted), disable ADC peripheral
<> 144:ef7eb2e8f9f7 3713 * if no conversion is on going on group regular.
<> 144:ef7eb2e8f9f7 3714 * @note To stop ADC conversion of both groups regular and injected and to
<> 144:ef7eb2e8f9f7 3715 * to disable ADC peripheral, instead of using 2 functions
<> 144:ef7eb2e8f9f7 3716 * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
<> 144:ef7eb2e8f9f7 3717 * use function @ref HAL_ADC_Stop().
<> 144:ef7eb2e8f9f7 3718 * @note If injected group mode auto-injection is enabled,
<> 144:ef7eb2e8f9f7 3719 * function HAL_ADC_Stop must be used.
<> 144:ef7eb2e8f9f7 3720 * @note Case of multimode enabled (for devices with several ADCs): This
<> 144:ef7eb2e8f9f7 3721 * function must be called for ADC master first, then ADC slave.
<> 144:ef7eb2e8f9f7 3722 * For ADC master, conversion is stopped and ADC is disabled.
<> 144:ef7eb2e8f9f7 3723 * For ADC slave, ADC is disabled only (conversion stop of ADC master
<> 144:ef7eb2e8f9f7 3724 * has already stopped conversion of ADC slave).
<> 144:ef7eb2e8f9f7 3725 * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
<> 144:ef7eb2e8f9f7 3726 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 3727 * @retval None
<> 144:ef7eb2e8f9f7 3728 */
<> 144:ef7eb2e8f9f7 3729 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 3730 {
<> 144:ef7eb2e8f9f7 3731 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 3732
<> 144:ef7eb2e8f9f7 3733 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3734 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 3735
<> 144:ef7eb2e8f9f7 3736 /* Process locked */
<> 144:ef7eb2e8f9f7 3737 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 3738
<> 144:ef7eb2e8f9f7 3739 /* Stop potential ADC conversion on going and disable ADC peripheral */
<> 144:ef7eb2e8f9f7 3740 /* conditioned to: */
<> 144:ef7eb2e8f9f7 3741 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
<> 144:ef7eb2e8f9f7 3742 /* - For ADC injected group conversion stop: */
<> 144:ef7eb2e8f9f7 3743 /* On this STM32 family, conversion on the other group */
<> 144:ef7eb2e8f9f7 3744 /* (group regular) can continue (groups regular and injected */
<> 144:ef7eb2e8f9f7 3745 /* conversion stop commands are independent) */
<> 144:ef7eb2e8f9f7 3746 /* - For ADC disable: */
<> 144:ef7eb2e8f9f7 3747 /* No conversion on the other group (group regular) must be intended to */
<> 144:ef7eb2e8f9f7 3748 /* continue (groups regular and injected are both impacted by */
<> 144:ef7eb2e8f9f7 3749 /* ADC disable) */
<> 144:ef7eb2e8f9f7 3750 if(HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
<> 144:ef7eb2e8f9f7 3751 {
<> 144:ef7eb2e8f9f7 3752 /* 1. Stop potential conversion on going on injected group only. */
<> 144:ef7eb2e8f9f7 3753 tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
<> 144:ef7eb2e8f9f7 3754
<> 144:ef7eb2e8f9f7 3755 /* Disable ADC peripheral if conversion on ADC group injected is */
<> 144:ef7eb2e8f9f7 3756 /* effectively stopped and if no conversion on the other group */
<> 144:ef7eb2e8f9f7 3757 /* (ADC group regular) is intended to continue. */
<> 144:ef7eb2e8f9f7 3758 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 3759 {
<> 144:ef7eb2e8f9f7 3760 if((ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) &&
<> 144:ef7eb2e8f9f7 3761 ((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) )
<> 144:ef7eb2e8f9f7 3762 {
<> 144:ef7eb2e8f9f7 3763 /* 2. Disable the ADC peripheral */
<> 144:ef7eb2e8f9f7 3764 tmp_hal_status = ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 3765
<> 144:ef7eb2e8f9f7 3766 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 3767 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 3768 {
<> 144:ef7eb2e8f9f7 3769 /* Set ADC state */
<> 144:ef7eb2e8f9f7 3770 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 3771 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 144:ef7eb2e8f9f7 3772 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 3773 }
<> 144:ef7eb2e8f9f7 3774 }
<> 144:ef7eb2e8f9f7 3775 /* Conversion on ADC group injected group is stopped, but ADC is not */
<> 144:ef7eb2e8f9f7 3776 /* disabled since conversion on ADC group regular is still on going. */
<> 144:ef7eb2e8f9f7 3777 else
<> 144:ef7eb2e8f9f7 3778 {
<> 144:ef7eb2e8f9f7 3779 /* Set ADC state */
<> 144:ef7eb2e8f9f7 3780 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 3781 }
<> 144:ef7eb2e8f9f7 3782 }
<> 144:ef7eb2e8f9f7 3783 }
<> 144:ef7eb2e8f9f7 3784 else
<> 144:ef7eb2e8f9f7 3785 {
<> 144:ef7eb2e8f9f7 3786 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 3787 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 3788
<> 144:ef7eb2e8f9f7 3789 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 3790 }
<> 144:ef7eb2e8f9f7 3791
<> 144:ef7eb2e8f9f7 3792 /* Process unlocked */
<> 144:ef7eb2e8f9f7 3793 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 3794
<> 144:ef7eb2e8f9f7 3795 /* Return function status */
<> 144:ef7eb2e8f9f7 3796 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 3797 }
<> 144:ef7eb2e8f9f7 3798 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 3799 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 3800 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 3801 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 3802
<> 144:ef7eb2e8f9f7 3803 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 3804 /**
<> 144:ef7eb2e8f9f7 3805 * @brief Stop conversion of injected channels. Disable ADC peripheral if
<> 144:ef7eb2e8f9f7 3806 * no regular conversion is on going.
<> 144:ef7eb2e8f9f7 3807 * @note If ADC must be disabled and if conversion is on going on
<> 144:ef7eb2e8f9f7 3808 * regular group, function HAL_ADC_Stop must be used to stop both
<> 144:ef7eb2e8f9f7 3809 * injected and regular groups, and disable the ADC.
<> 144:ef7eb2e8f9f7 3810 * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
<> 144:ef7eb2e8f9f7 3811 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 3812 * @retval None
<> 144:ef7eb2e8f9f7 3813 */
<> 144:ef7eb2e8f9f7 3814 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 3815 {
<> 144:ef7eb2e8f9f7 3816 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 3817
<> 144:ef7eb2e8f9f7 3818 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3819 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 3820
<> 144:ef7eb2e8f9f7 3821 /* Process locked */
<> 144:ef7eb2e8f9f7 3822 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 3823
<> 144:ef7eb2e8f9f7 3824 /* Stop potential conversion and disable ADC peripheral */
<> 144:ef7eb2e8f9f7 3825 /* Conditioned to: */
<> 144:ef7eb2e8f9f7 3826 /* - No conversion on the other group (regular group) is intended to */
<> 144:ef7eb2e8f9f7 3827 /* continue (injected and regular groups stop conversion and ADC disable */
<> 144:ef7eb2e8f9f7 3828 /* are common) */
<> 144:ef7eb2e8f9f7 3829 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
<> 144:ef7eb2e8f9f7 3830 if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
<> 144:ef7eb2e8f9f7 3831 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
<> 144:ef7eb2e8f9f7 3832 {
<> 144:ef7eb2e8f9f7 3833 /* Stop potential conversion on going, on regular and injected groups */
<> 144:ef7eb2e8f9f7 3834 /* Disable ADC peripheral */
<> 144:ef7eb2e8f9f7 3835 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
<> 144:ef7eb2e8f9f7 3836
<> 144:ef7eb2e8f9f7 3837 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 3838 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 3839 {
<> 144:ef7eb2e8f9f7 3840 /* Set ADC state */
<> 144:ef7eb2e8f9f7 3841 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 3842 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 144:ef7eb2e8f9f7 3843 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 3844 }
<> 144:ef7eb2e8f9f7 3845 }
<> 144:ef7eb2e8f9f7 3846 else
<> 144:ef7eb2e8f9f7 3847 {
<> 144:ef7eb2e8f9f7 3848 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 3849 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 3850
<> 144:ef7eb2e8f9f7 3851 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 3852 }
<> 144:ef7eb2e8f9f7 3853
<> 144:ef7eb2e8f9f7 3854 /* Process unlocked */
<> 144:ef7eb2e8f9f7 3855 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 3856
<> 144:ef7eb2e8f9f7 3857 /* Return function status */
<> 144:ef7eb2e8f9f7 3858 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 3859 }
<> 144:ef7eb2e8f9f7 3860 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 3861
<> 144:ef7eb2e8f9f7 3862 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 3863 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 3864 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 3865 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 3866 /**
<> 144:ef7eb2e8f9f7 3867 * @brief Wait for injected group conversion to be completed.
<> 144:ef7eb2e8f9f7 3868 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 3869 * @param Timeout: Timeout value in millisecond.
<> 144:ef7eb2e8f9f7 3870 * @retval HAL status
<> 144:ef7eb2e8f9f7 3871 */
<> 144:ef7eb2e8f9f7 3872 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 3873 {
<> 144:ef7eb2e8f9f7 3874 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 3875 uint32_t tmp_Flag_EOC;
<> 144:ef7eb2e8f9f7 3876 uint32_t tmp_cfgr = 0x00000000;
<> 144:ef7eb2e8f9f7 3877
<> 144:ef7eb2e8f9f7 3878 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3879 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 3880
<> 144:ef7eb2e8f9f7 3881 /* If end of conversion selected to end of sequence */
<> 144:ef7eb2e8f9f7 3882 if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
<> 144:ef7eb2e8f9f7 3883 {
<> 144:ef7eb2e8f9f7 3884 tmp_Flag_EOC = ADC_FLAG_JEOS;
<> 144:ef7eb2e8f9f7 3885 }
<> 144:ef7eb2e8f9f7 3886 /* If end of conversion selected to end of each conversion */
<> 144:ef7eb2e8f9f7 3887 else /* ADC_EOC_SINGLE_CONV */
<> 144:ef7eb2e8f9f7 3888 {
<> 144:ef7eb2e8f9f7 3889 tmp_Flag_EOC = (ADC_FLAG_JEOC | ADC_FLAG_JEOS);
<> 144:ef7eb2e8f9f7 3890 }
<> 144:ef7eb2e8f9f7 3891
<> 144:ef7eb2e8f9f7 3892 /* Get relevant register CFGR in ADC instance of ADC master or slave */
<> 144:ef7eb2e8f9f7 3893 /* in function of multimode state (for devices with multimode */
<> 144:ef7eb2e8f9f7 3894 /* available). */
<> 144:ef7eb2e8f9f7 3895 if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
<> 144:ef7eb2e8f9f7 3896 {
<> 144:ef7eb2e8f9f7 3897 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
<> 144:ef7eb2e8f9f7 3898 }
<> 144:ef7eb2e8f9f7 3899 else
<> 144:ef7eb2e8f9f7 3900 {
<> 144:ef7eb2e8f9f7 3901 tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
<> 144:ef7eb2e8f9f7 3902 }
<> 144:ef7eb2e8f9f7 3903
<> 144:ef7eb2e8f9f7 3904 /* Get tick count */
<> 144:ef7eb2e8f9f7 3905 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 3906
<> 144:ef7eb2e8f9f7 3907 /* Wait until End of Conversion flag is raised */
<> 144:ef7eb2e8f9f7 3908 while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
<> 144:ef7eb2e8f9f7 3909 {
<> 144:ef7eb2e8f9f7 3910 /* Check if timeout is disabled (set to infinite wait) */
<> 144:ef7eb2e8f9f7 3911 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 3912 {
<> 144:ef7eb2e8f9f7 3913 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 3914 {
<> 144:ef7eb2e8f9f7 3915 /* Update ADC state machine to timeout */
<> 144:ef7eb2e8f9f7 3916 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
<> 144:ef7eb2e8f9f7 3917
<> 144:ef7eb2e8f9f7 3918 /* Process unlocked */
<> 144:ef7eb2e8f9f7 3919 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 3920
<> 144:ef7eb2e8f9f7 3921 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3922 }
<> 144:ef7eb2e8f9f7 3923 }
<> 144:ef7eb2e8f9f7 3924 }
<> 144:ef7eb2e8f9f7 3925
<> 144:ef7eb2e8f9f7 3926 /* Update ADC state machine */
<> 144:ef7eb2e8f9f7 3927 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
<> 144:ef7eb2e8f9f7 3928
<> 144:ef7eb2e8f9f7 3929 /* Determine whether any further conversion upcoming on group injected */
<> 144:ef7eb2e8f9f7 3930 /* by external trigger or by automatic injected conversion */
<> 144:ef7eb2e8f9f7 3931 /* from group regular. */
<> 144:ef7eb2e8f9f7 3932 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
<> 144:ef7eb2e8f9f7 3933 ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) &&
<> 144:ef7eb2e8f9f7 3934 (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 144:ef7eb2e8f9f7 3935 (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) ) )
<> 144:ef7eb2e8f9f7 3936 {
<> 144:ef7eb2e8f9f7 3937 /* Set ADC state */
<> 144:ef7eb2e8f9f7 3938 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 3939
<> 144:ef7eb2e8f9f7 3940 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
<> 144:ef7eb2e8f9f7 3941 {
<> 144:ef7eb2e8f9f7 3942 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 3943 }
<> 144:ef7eb2e8f9f7 3944 }
<> 144:ef7eb2e8f9f7 3945
<> 144:ef7eb2e8f9f7 3946 /* Clear end of conversion flag of injected group if low power feature */
<> 144:ef7eb2e8f9f7 3947 /* "Auto Wait" is disabled, to not interfere with this feature until data */
<> 144:ef7eb2e8f9f7 3948 /* register is read using function HAL_ADC_GetValue(). */
<> 144:ef7eb2e8f9f7 3949 if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET)
<> 144:ef7eb2e8f9f7 3950 {
<> 144:ef7eb2e8f9f7 3951 /* Clear injected group conversion flag */
<> 144:ef7eb2e8f9f7 3952 /* (JEOC or JEOS depending on HAL ADC initialization parameter) */
<> 144:ef7eb2e8f9f7 3953 __HAL_ADC_CLEAR_FLAG(hadc, tmp_Flag_EOC);
<> 144:ef7eb2e8f9f7 3954 }
<> 144:ef7eb2e8f9f7 3955
<> 144:ef7eb2e8f9f7 3956 /* Return ADC state */
<> 144:ef7eb2e8f9f7 3957 return HAL_OK;
<> 144:ef7eb2e8f9f7 3958 }
<> 144:ef7eb2e8f9f7 3959 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 3960 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 3961 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 3962 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 3963
<> 144:ef7eb2e8f9f7 3964 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 3965 /**
<> 144:ef7eb2e8f9f7 3966 * @brief Wait for injected group conversion to be completed.
<> 144:ef7eb2e8f9f7 3967 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 3968 * @param Timeout: Timeout value in millisecond.
<> 144:ef7eb2e8f9f7 3969 * @retval HAL status
<> 144:ef7eb2e8f9f7 3970 */
<> 144:ef7eb2e8f9f7 3971 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 3972 {
<> 144:ef7eb2e8f9f7 3973 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 3974
<> 144:ef7eb2e8f9f7 3975 /* Variables for polling in case of scan mode enabled */
<> 144:ef7eb2e8f9f7 3976 uint32_t Conversion_Timeout_CPU_cycles_max =0;
<> 144:ef7eb2e8f9f7 3977 uint32_t Conversion_Timeout_CPU_cycles =0;
<> 144:ef7eb2e8f9f7 3978
<> 144:ef7eb2e8f9f7 3979 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3980 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 3981
<> 144:ef7eb2e8f9f7 3982 /* Get tick count */
<> 144:ef7eb2e8f9f7 3983 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 3984
<> 144:ef7eb2e8f9f7 3985 /* Polling for end of conversion: differentiation if single/sequence */
<> 144:ef7eb2e8f9f7 3986 /* conversion. */
<> 144:ef7eb2e8f9f7 3987 /* For injected group, flag JEOC is set only at the end of the sequence, */
<> 144:ef7eb2e8f9f7 3988 /* not for each conversion within the sequence. */
<> 144:ef7eb2e8f9f7 3989 /* - If single conversion for injected group (scan mode disabled or */
<> 144:ef7eb2e8f9f7 3990 /* InjectedNbrOfConversion ==1), flag JEOC is used to determine the */
<> 144:ef7eb2e8f9f7 3991 /* conversion completion. */
<> 144:ef7eb2e8f9f7 3992 /* - If sequence conversion for injected group (scan mode enabled and */
<> 144:ef7eb2e8f9f7 3993 /* InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */
<> 144:ef7eb2e8f9f7 3994 /* sequence. */
<> 144:ef7eb2e8f9f7 3995 /* To poll for each conversion, the maximum conversion time is computed */
<> 144:ef7eb2e8f9f7 3996 /* from ADC conversion time (selected sampling time + conversion time of */
<> 144:ef7eb2e8f9f7 3997 /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */
<> 144:ef7eb2e8f9f7 3998 /* settings, conversion time range can be from 28 to 32256 CPU cycles). */
<> 144:ef7eb2e8f9f7 3999 /* As flag JEOC is not set after each conversion, no timeout status can */
<> 144:ef7eb2e8f9f7 4000 /* be set. */
<> 144:ef7eb2e8f9f7 4001 if ((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET)
<> 144:ef7eb2e8f9f7 4002 {
<> 144:ef7eb2e8f9f7 4003 /* Wait until End of Conversion flag is raised */
<> 144:ef7eb2e8f9f7 4004 while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC))
<> 144:ef7eb2e8f9f7 4005 {
<> 144:ef7eb2e8f9f7 4006 /* Check if timeout is disabled (set to infinite wait) */
<> 144:ef7eb2e8f9f7 4007 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 4008 {
<> 144:ef7eb2e8f9f7 4009 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 4010 {
<> 144:ef7eb2e8f9f7 4011 /* Update ADC state machine to timeout */
<> 144:ef7eb2e8f9f7 4012 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
<> 144:ef7eb2e8f9f7 4013
<> 144:ef7eb2e8f9f7 4014 /* Process unlocked */
<> 144:ef7eb2e8f9f7 4015 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 4016
<> 144:ef7eb2e8f9f7 4017 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 4018 }
<> 144:ef7eb2e8f9f7 4019 }
<> 144:ef7eb2e8f9f7 4020 }
<> 144:ef7eb2e8f9f7 4021 }
<> 144:ef7eb2e8f9f7 4022 else
<> 144:ef7eb2e8f9f7 4023 {
<> 144:ef7eb2e8f9f7 4024 /* Replace polling by wait for maximum conversion time */
<> 144:ef7eb2e8f9f7 4025 /* Calculation of CPU cycles corresponding to ADC conversion cycles. */
<> 144:ef7eb2e8f9f7 4026 /* Retrieve ADC clock prescaler and ADC maximum conversion cycles on all */
<> 144:ef7eb2e8f9f7 4027 /* channels. */
<> 144:ef7eb2e8f9f7 4028 Conversion_Timeout_CPU_cycles_max = ADC_CLOCK_PRESCALER_RANGE();
<> 144:ef7eb2e8f9f7 4029 Conversion_Timeout_CPU_cycles_max *= ADC_CONVCYCLES_MAX_RANGE(hadc);
<> 144:ef7eb2e8f9f7 4030
<> 144:ef7eb2e8f9f7 4031 /* Poll with maximum conversion time */
<> 144:ef7eb2e8f9f7 4032 while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
<> 144:ef7eb2e8f9f7 4033 {
<> 144:ef7eb2e8f9f7 4034 /* Check if timeout is disabled (set to infinite wait) */
<> 144:ef7eb2e8f9f7 4035 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 4036 {
<> 144:ef7eb2e8f9f7 4037 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 4038 {
<> 144:ef7eb2e8f9f7 4039 /* Update ADC state machine to timeout */
<> 144:ef7eb2e8f9f7 4040 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
<> 144:ef7eb2e8f9f7 4041
<> 144:ef7eb2e8f9f7 4042 /* Process unlocked */
<> 144:ef7eb2e8f9f7 4043 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 4044
<> 144:ef7eb2e8f9f7 4045 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 4046 }
<> 144:ef7eb2e8f9f7 4047 }
<> 144:ef7eb2e8f9f7 4048 Conversion_Timeout_CPU_cycles ++;
<> 144:ef7eb2e8f9f7 4049 }
<> 144:ef7eb2e8f9f7 4050 }
<> 144:ef7eb2e8f9f7 4051
<> 144:ef7eb2e8f9f7 4052
<> 144:ef7eb2e8f9f7 4053 /* Clear injected group conversion flag (and regular conversion flag raised simultaneously) */
<> 144:ef7eb2e8f9f7 4054 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC | ADC_FLAG_EOC);
<> 144:ef7eb2e8f9f7 4055
<> 144:ef7eb2e8f9f7 4056 /* Update ADC state machine */
<> 144:ef7eb2e8f9f7 4057 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
<> 144:ef7eb2e8f9f7 4058
<> 144:ef7eb2e8f9f7 4059 /* Determine whether any further conversion upcoming on group injected */
<> 144:ef7eb2e8f9f7 4060 /* by external trigger or by automatic injected conversion */
<> 144:ef7eb2e8f9f7 4061 /* from group regular. */
<> 144:ef7eb2e8f9f7 4062 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
<> 144:ef7eb2e8f9f7 4063 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
<> 144:ef7eb2e8f9f7 4064 (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 144:ef7eb2e8f9f7 4065 (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
<> 144:ef7eb2e8f9f7 4066 {
<> 144:ef7eb2e8f9f7 4067 /* Set ADC state */
<> 144:ef7eb2e8f9f7 4068 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 4069
<> 144:ef7eb2e8f9f7 4070 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
<> 144:ef7eb2e8f9f7 4071 {
<> 144:ef7eb2e8f9f7 4072 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 4073 }
<> 144:ef7eb2e8f9f7 4074 }
<> 144:ef7eb2e8f9f7 4075
<> 144:ef7eb2e8f9f7 4076 /* Return ADC state */
<> 144:ef7eb2e8f9f7 4077 return HAL_OK;
<> 144:ef7eb2e8f9f7 4078 }
<> 144:ef7eb2e8f9f7 4079 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 4080
<> 144:ef7eb2e8f9f7 4081 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 4082 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 4083 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 4084 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 4085 /**
<> 144:ef7eb2e8f9f7 4086 * @brief Enables ADC, starts conversion of injected group with interruption.
<> 144:ef7eb2e8f9f7 4087 * Interruptions enabled in this function:
<> 144:ef7eb2e8f9f7 4088 * - JEOC (end of conversion of injected group) or JEOS (end of
<> 144:ef7eb2e8f9f7 4089 * sequence of injected group) depending on ADC initialization
<> 144:ef7eb2e8f9f7 4090 * parameter "EOCSelection"
<> 144:ef7eb2e8f9f7 4091 * Each of these interruptions has its dedicated callback function.
<> 144:ef7eb2e8f9f7 4092 * @note Case of multimode enabled (for devices with several ADCs): This
<> 144:ef7eb2e8f9f7 4093 * function must be called for ADC slave first, then ADC master.
<> 144:ef7eb2e8f9f7 4094 * For ADC slave, ADC is enabled only (conversion is not started).
<> 144:ef7eb2e8f9f7 4095 * For ADC master, ADC is enabled and multimode conversion is started.
<> 144:ef7eb2e8f9f7 4096 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 4097 * @retval HAL status.
<> 144:ef7eb2e8f9f7 4098 */
<> 144:ef7eb2e8f9f7 4099 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 4100 {
<> 144:ef7eb2e8f9f7 4101 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 4102
<> 144:ef7eb2e8f9f7 4103 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4104 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 4105
<> 144:ef7eb2e8f9f7 4106 /* Perform ADC enable and conversion start if no conversion is on going */
<> 144:ef7eb2e8f9f7 4107 if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
<> 144:ef7eb2e8f9f7 4108 {
<> 144:ef7eb2e8f9f7 4109 /* Process locked */
<> 144:ef7eb2e8f9f7 4110 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 4111
<> 144:ef7eb2e8f9f7 4112 /* Enable the ADC peripheral */
<> 144:ef7eb2e8f9f7 4113 tmp_hal_status = ADC_Enable(hadc);
<> 144:ef7eb2e8f9f7 4114
<> 144:ef7eb2e8f9f7 4115 /* Start conversion if ADC is effectively enabled */
<> 144:ef7eb2e8f9f7 4116 /* Start conversion if ADC is effectively enabled */
<> 144:ef7eb2e8f9f7 4117 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 4118 {
<> 144:ef7eb2e8f9f7 4119 /* Set ADC state */
<> 144:ef7eb2e8f9f7 4120 /* - Clear state bitfield related to injected group conversion results */
<> 144:ef7eb2e8f9f7 4121 /* - Set state bitfield related to injected operation */
<> 144:ef7eb2e8f9f7 4122 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 4123 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
<> 144:ef7eb2e8f9f7 4124 HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 4125
<> 144:ef7eb2e8f9f7 4126 /* Case of independent mode or multimode(for devices with several ADCs):*/
<> 144:ef7eb2e8f9f7 4127 /* Set multimode state. */
<> 144:ef7eb2e8f9f7 4128 if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
<> 144:ef7eb2e8f9f7 4129 {
<> 144:ef7eb2e8f9f7 4130 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<> 144:ef7eb2e8f9f7 4131 }
<> 144:ef7eb2e8f9f7 4132 else
<> 144:ef7eb2e8f9f7 4133 {
<> 144:ef7eb2e8f9f7 4134 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<> 144:ef7eb2e8f9f7 4135 }
<> 144:ef7eb2e8f9f7 4136
<> 144:ef7eb2e8f9f7 4137 /* Check if a regular conversion is ongoing */
<> 144:ef7eb2e8f9f7 4138 /* Note: On this device, there is no ADC error code fields related to */
<> 144:ef7eb2e8f9f7 4139 /* conversions on group injected only. In case of conversion on */
<> 144:ef7eb2e8f9f7 4140 /* going on group regular, no error code is reset. */
<> 144:ef7eb2e8f9f7 4141 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
<> 144:ef7eb2e8f9f7 4142 {
<> 144:ef7eb2e8f9f7 4143 /* Reset ADC all error code fields */
<> 144:ef7eb2e8f9f7 4144 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 4145 }
<> 144:ef7eb2e8f9f7 4146
<> 144:ef7eb2e8f9f7 4147 /* Process unlocked */
<> 144:ef7eb2e8f9f7 4148 /* Unlock before starting ADC conversions: in case of potential */
<> 144:ef7eb2e8f9f7 4149 /* interruption, to let the process to ADC IRQ Handler. */
<> 144:ef7eb2e8f9f7 4150 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 4151
<> 144:ef7eb2e8f9f7 4152 /* Clear injected group conversion flag */
<> 144:ef7eb2e8f9f7 4153 /* (To ensure of no unknown state from potential previous ADC */
<> 144:ef7eb2e8f9f7 4154 /* operations) */
<> 144:ef7eb2e8f9f7 4155 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
<> 144:ef7eb2e8f9f7 4156
<> 144:ef7eb2e8f9f7 4157 /* Enable ADC Injected context queue overflow interrupt if this feature */
<> 144:ef7eb2e8f9f7 4158 /* is enabled. */
<> 144:ef7eb2e8f9f7 4159 if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != RESET)
<> 144:ef7eb2e8f9f7 4160 {
<> 144:ef7eb2e8f9f7 4161 __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
<> 144:ef7eb2e8f9f7 4162 }
<> 144:ef7eb2e8f9f7 4163
<> 144:ef7eb2e8f9f7 4164 /* Enable ADC end of conversion interrupt */
<> 144:ef7eb2e8f9f7 4165 switch(hadc->Init.EOCSelection)
<> 144:ef7eb2e8f9f7 4166 {
<> 144:ef7eb2e8f9f7 4167 case ADC_EOC_SEQ_CONV:
<> 144:ef7eb2e8f9f7 4168 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
<> 144:ef7eb2e8f9f7 4169 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
<> 144:ef7eb2e8f9f7 4170 break;
<> 144:ef7eb2e8f9f7 4171 /* case ADC_EOC_SINGLE_CONV */
<> 144:ef7eb2e8f9f7 4172 default:
<> 144:ef7eb2e8f9f7 4173 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
<> 144:ef7eb2e8f9f7 4174 break;
<> 144:ef7eb2e8f9f7 4175 }
<> 144:ef7eb2e8f9f7 4176
<> 144:ef7eb2e8f9f7 4177 /* Enable conversion of injected group, if automatic injected */
<> 144:ef7eb2e8f9f7 4178 /* conversion is disabled. */
<> 144:ef7eb2e8f9f7 4179 /* If software start has been selected, conversion starts immediately. */
<> 144:ef7eb2e8f9f7 4180 /* If external trigger has been selected, conversion will start at next */
<> 144:ef7eb2e8f9f7 4181 /* trigger event. */
<> 144:ef7eb2e8f9f7 4182 /* Case of multimode enabled (for devices with several ADCs): */
<> 144:ef7eb2e8f9f7 4183 /* - if ADC is slave, ADC is enabled only (conversion is not started). */
<> 144:ef7eb2e8f9f7 4184 /* - if ADC is master, ADC is enabled and conversion is started. */
<> 144:ef7eb2e8f9f7 4185 if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO) &&
<> 144:ef7eb2e8f9f7 4186 ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc) )
<> 144:ef7eb2e8f9f7 4187 {
<> 144:ef7eb2e8f9f7 4188 SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART);
<> 144:ef7eb2e8f9f7 4189 }
<> 144:ef7eb2e8f9f7 4190 }
<> 144:ef7eb2e8f9f7 4191 else
<> 144:ef7eb2e8f9f7 4192 {
<> 144:ef7eb2e8f9f7 4193 /* Process unlocked */
<> 144:ef7eb2e8f9f7 4194 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 4195 }
<> 144:ef7eb2e8f9f7 4196 }
<> 144:ef7eb2e8f9f7 4197 else
<> 144:ef7eb2e8f9f7 4198 {
<> 144:ef7eb2e8f9f7 4199 tmp_hal_status = HAL_BUSY;
<> 144:ef7eb2e8f9f7 4200 }
<> 144:ef7eb2e8f9f7 4201
<> 144:ef7eb2e8f9f7 4202 /* Return function status */
<> 144:ef7eb2e8f9f7 4203 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 4204 }
<> 144:ef7eb2e8f9f7 4205 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 4206 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 4207 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 4208 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 4209
<> 144:ef7eb2e8f9f7 4210 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 4211 /**
<> 144:ef7eb2e8f9f7 4212 * @brief Enables ADC, starts conversion of injected group with interruption.
<> 144:ef7eb2e8f9f7 4213 * Interruptions enabled in this function:
<> 144:ef7eb2e8f9f7 4214 * - JEOC (end of conversion of injected group)
<> 144:ef7eb2e8f9f7 4215 * Each of these interruptions has its dedicated callback function.
<> 144:ef7eb2e8f9f7 4216 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 4217 * @retval HAL status.
<> 144:ef7eb2e8f9f7 4218 */
<> 144:ef7eb2e8f9f7 4219 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 4220 {
<> 144:ef7eb2e8f9f7 4221 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 4222
<> 144:ef7eb2e8f9f7 4223 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4224 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 4225
<> 144:ef7eb2e8f9f7 4226 /* Process locked */
<> 144:ef7eb2e8f9f7 4227 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 4228
<> 144:ef7eb2e8f9f7 4229 /* Enable the ADC peripheral */
<> 144:ef7eb2e8f9f7 4230 tmp_hal_status = ADC_Enable(hadc);
<> 144:ef7eb2e8f9f7 4231
<> 144:ef7eb2e8f9f7 4232 /* Start conversion if ADC is effectively enabled */
<> 144:ef7eb2e8f9f7 4233 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 4234 {
<> 144:ef7eb2e8f9f7 4235 /* Set ADC state */
<> 144:ef7eb2e8f9f7 4236 /* - Clear state bitfield related to injected group conversion results */
<> 144:ef7eb2e8f9f7 4237 /* - Set state bitfield related to injected operation */
<> 144:ef7eb2e8f9f7 4238 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 4239 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
<> 144:ef7eb2e8f9f7 4240 HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 4241
<> 144:ef7eb2e8f9f7 4242 /* Check if a regular conversion is ongoing */
<> 144:ef7eb2e8f9f7 4243 /* Note: On this device, there is no ADC error code fields related to */
<> 144:ef7eb2e8f9f7 4244 /* conversions on group injected only. In case of conversion on */
<> 144:ef7eb2e8f9f7 4245 /* going on group regular, no error code is reset. */
<> 144:ef7eb2e8f9f7 4246 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
<> 144:ef7eb2e8f9f7 4247 {
<> 144:ef7eb2e8f9f7 4248 /* Reset ADC all error code fields */
<> 144:ef7eb2e8f9f7 4249 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 4250 }
<> 144:ef7eb2e8f9f7 4251
<> 144:ef7eb2e8f9f7 4252 /* Process unlocked */
<> 144:ef7eb2e8f9f7 4253 /* Unlock before starting ADC conversions: in case of potential */
<> 144:ef7eb2e8f9f7 4254 /* interruption, to let the process to ADC IRQ Handler. */
<> 144:ef7eb2e8f9f7 4255 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 4256
<> 144:ef7eb2e8f9f7 4257 /* Set ADC error code to none */
<> 144:ef7eb2e8f9f7 4258 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 4259
<> 144:ef7eb2e8f9f7 4260 /* Clear injected group conversion flag */
<> 144:ef7eb2e8f9f7 4261 /* (To ensure of no unknown state from potential previous ADC operations) */
<> 144:ef7eb2e8f9f7 4262 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
<> 144:ef7eb2e8f9f7 4263
<> 144:ef7eb2e8f9f7 4264 /* Enable end of conversion interrupt for injected channels */
<> 144:ef7eb2e8f9f7 4265 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
<> 144:ef7eb2e8f9f7 4266
<> 144:ef7eb2e8f9f7 4267 /* Enable conversion of injected group. */
<> 144:ef7eb2e8f9f7 4268 /* If software start has been selected, conversion starts immediately. */
<> 144:ef7eb2e8f9f7 4269 /* If external trigger has been selected, conversion will start at next */
<> 144:ef7eb2e8f9f7 4270 /* trigger event. */
<> 144:ef7eb2e8f9f7 4271 /* If external trigger has been selected, conversion will start at next */
<> 144:ef7eb2e8f9f7 4272 /* trigger event. */
<> 144:ef7eb2e8f9f7 4273 /* If automatic injected conversion is enabled, conversion will start */
<> 144:ef7eb2e8f9f7 4274 /* after next regular group conversion. */
<> 144:ef7eb2e8f9f7 4275 if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
<> 144:ef7eb2e8f9f7 4276 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
<> 144:ef7eb2e8f9f7 4277 {
<> 144:ef7eb2e8f9f7 4278 /* Start ADC conversion on injected group with SW start */
<> 144:ef7eb2e8f9f7 4279 SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
<> 144:ef7eb2e8f9f7 4280 }
<> 144:ef7eb2e8f9f7 4281 else
<> 144:ef7eb2e8f9f7 4282 {
<> 144:ef7eb2e8f9f7 4283 /* Start ADC conversion on injected group with external trigger */
<> 144:ef7eb2e8f9f7 4284 SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
<> 144:ef7eb2e8f9f7 4285 }
<> 144:ef7eb2e8f9f7 4286 }
<> 144:ef7eb2e8f9f7 4287
<> 144:ef7eb2e8f9f7 4288 /* Return function status */
<> 144:ef7eb2e8f9f7 4289 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 4290 }
<> 144:ef7eb2e8f9f7 4291 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 4292
<> 144:ef7eb2e8f9f7 4293 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 4294 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 4295 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 4296 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 4297 /**
<> 144:ef7eb2e8f9f7 4298 * @brief Stop ADC group injected conversion (potential conversion on going
<> 144:ef7eb2e8f9f7 4299 * on ADC group regular is not impacted), disable ADC peripheral
<> 144:ef7eb2e8f9f7 4300 * if no conversion is on going on group regular.
<> 144:ef7eb2e8f9f7 4301 * Interruptions disabled in this function:
<> 144:ef7eb2e8f9f7 4302 * - JEOC (end of conversion of injected group) and JEOS (end of
<> 144:ef7eb2e8f9f7 4303 * sequence of injected group)
<> 144:ef7eb2e8f9f7 4304 * @note To stop ADC conversion of both groups regular and injected and to
<> 144:ef7eb2e8f9f7 4305 * to disable ADC peripheral, instead of using 2 functions
<> 144:ef7eb2e8f9f7 4306 * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
<> 144:ef7eb2e8f9f7 4307 * use function @ref HAL_ADC_Stop().
<> 144:ef7eb2e8f9f7 4308 * @note If injected group mode auto-injection is enabled,
<> 144:ef7eb2e8f9f7 4309 * function HAL_ADC_Stop must be used.
<> 144:ef7eb2e8f9f7 4310 * @note Case of multimode enabled (for devices with several ADCs): This
<> 144:ef7eb2e8f9f7 4311 * function must be called for ADC master first, then ADC slave.
<> 144:ef7eb2e8f9f7 4312 * For ADC master, conversion is stopped and ADC is disabled.
<> 144:ef7eb2e8f9f7 4313 * For ADC slave, ADC is disabled only (conversion stop of ADC master
<> 144:ef7eb2e8f9f7 4314 * has already stopped conversion of ADC slave).
<> 144:ef7eb2e8f9f7 4315 * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
<> 144:ef7eb2e8f9f7 4316 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 4317 * @retval None
<> 144:ef7eb2e8f9f7 4318 */
<> 144:ef7eb2e8f9f7 4319 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 4320 {
<> 144:ef7eb2e8f9f7 4321 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 4322
<> 144:ef7eb2e8f9f7 4323 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4324 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 4325
<> 144:ef7eb2e8f9f7 4326 /* Process locked */
<> 144:ef7eb2e8f9f7 4327 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 4328
<> 144:ef7eb2e8f9f7 4329 /* Stop potential ADC conversion on going and disable ADC peripheral */
<> 144:ef7eb2e8f9f7 4330 /* conditioned to: */
<> 144:ef7eb2e8f9f7 4331 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
<> 144:ef7eb2e8f9f7 4332 /* - For ADC injected group conversion stop: */
<> 144:ef7eb2e8f9f7 4333 /* On this STM32 family, conversion on the other group */
<> 144:ef7eb2e8f9f7 4334 /* (group regular) can continue (groups regular and injected */
<> 144:ef7eb2e8f9f7 4335 /* conversion stop commands are independent) */
<> 144:ef7eb2e8f9f7 4336 /* - For ADC disable: */
<> 144:ef7eb2e8f9f7 4337 /* No conversion on the other group (group regular) must be intended to */
<> 144:ef7eb2e8f9f7 4338 /* continue (groups regular and injected are both impacted by */
<> 144:ef7eb2e8f9f7 4339 /* ADC disable) */
<> 144:ef7eb2e8f9f7 4340 if(HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
<> 144:ef7eb2e8f9f7 4341 {
<> 144:ef7eb2e8f9f7 4342 /* 1. Stop potential conversion on going on injected group only. */
<> 144:ef7eb2e8f9f7 4343 tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
<> 144:ef7eb2e8f9f7 4344
<> 144:ef7eb2e8f9f7 4345 /* Disable ADC peripheral if conversion on ADC group injected is */
<> 144:ef7eb2e8f9f7 4346 /* effectively stopped and if no conversion on the other group */
<> 144:ef7eb2e8f9f7 4347 /* (ADC group regular) is intended to continue. */
<> 144:ef7eb2e8f9f7 4348 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 4349 {
<> 144:ef7eb2e8f9f7 4350 /* Disable ADC end of conversion interrupt for injected channels */
<> 144:ef7eb2e8f9f7 4351 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_IT_JQOVF));
<> 144:ef7eb2e8f9f7 4352
<> 144:ef7eb2e8f9f7 4353 if((ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) &&
<> 144:ef7eb2e8f9f7 4354 ((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) )
<> 144:ef7eb2e8f9f7 4355 {
<> 144:ef7eb2e8f9f7 4356 /* 2. Disable the ADC peripheral */
<> 144:ef7eb2e8f9f7 4357 tmp_hal_status = ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 4358
<> 144:ef7eb2e8f9f7 4359 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 4360 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 4361 {
<> 144:ef7eb2e8f9f7 4362 /* Set ADC state */
<> 144:ef7eb2e8f9f7 4363 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 4364 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 144:ef7eb2e8f9f7 4365 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 4366 }
<> 144:ef7eb2e8f9f7 4367 }
<> 144:ef7eb2e8f9f7 4368 /* Conversion on ADC group injected group is stopped, but ADC is not */
<> 144:ef7eb2e8f9f7 4369 /* disabled since conversion on ADC group regular is still on going. */
<> 144:ef7eb2e8f9f7 4370 else
<> 144:ef7eb2e8f9f7 4371 {
<> 144:ef7eb2e8f9f7 4372 /* Set ADC state */
<> 144:ef7eb2e8f9f7 4373 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 4374 }
<> 144:ef7eb2e8f9f7 4375 }
<> 144:ef7eb2e8f9f7 4376 }
<> 144:ef7eb2e8f9f7 4377 else
<> 144:ef7eb2e8f9f7 4378 {
<> 144:ef7eb2e8f9f7 4379 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 4380 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 4381
<> 144:ef7eb2e8f9f7 4382 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 4383 }
<> 144:ef7eb2e8f9f7 4384
<> 144:ef7eb2e8f9f7 4385 /* Process unlocked */
<> 144:ef7eb2e8f9f7 4386 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 4387
<> 144:ef7eb2e8f9f7 4388 /* Return function status */
<> 144:ef7eb2e8f9f7 4389 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 4390 }
<> 144:ef7eb2e8f9f7 4391 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 4392 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 4393 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 4394 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 4395
<> 144:ef7eb2e8f9f7 4396 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 4397 /**
<> 144:ef7eb2e8f9f7 4398 * @brief Stop conversion of injected channels, disable interruption of
<> 144:ef7eb2e8f9f7 4399 * end-of-conversion. Disable ADC peripheral if no regular conversion
<> 144:ef7eb2e8f9f7 4400 * is on going.
<> 144:ef7eb2e8f9f7 4401 * @note If ADC must be disabled and if conversion is on going on
<> 144:ef7eb2e8f9f7 4402 * regular group, function HAL_ADC_Stop must be used to stop both
<> 144:ef7eb2e8f9f7 4403 * injected and regular groups, and disable the ADC.
<> 144:ef7eb2e8f9f7 4404 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 4405 * @retval None
<> 144:ef7eb2e8f9f7 4406 */
<> 144:ef7eb2e8f9f7 4407 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 4408 {
<> 144:ef7eb2e8f9f7 4409 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 4410
<> 144:ef7eb2e8f9f7 4411 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4412 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 4413
<> 144:ef7eb2e8f9f7 4414 /* Process locked */
<> 144:ef7eb2e8f9f7 4415 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 4416
<> 144:ef7eb2e8f9f7 4417 /* Stop potential conversion and disable ADC peripheral */
<> 144:ef7eb2e8f9f7 4418 /* Conditioned to: */
<> 144:ef7eb2e8f9f7 4419 /* - No conversion on the other group (regular group) is intended to */
<> 144:ef7eb2e8f9f7 4420 /* continue (injected and regular groups stop conversion and ADC disable */
<> 144:ef7eb2e8f9f7 4421 /* are common) */
<> 144:ef7eb2e8f9f7 4422 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
<> 144:ef7eb2e8f9f7 4423 if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
<> 144:ef7eb2e8f9f7 4424 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
<> 144:ef7eb2e8f9f7 4425 {
<> 144:ef7eb2e8f9f7 4426 /* Stop potential conversion on going, on regular and injected groups */
<> 144:ef7eb2e8f9f7 4427 /* Disable ADC peripheral */
<> 144:ef7eb2e8f9f7 4428 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
<> 144:ef7eb2e8f9f7 4429
<> 144:ef7eb2e8f9f7 4430 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 4431 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 4432 {
<> 144:ef7eb2e8f9f7 4433 /* Disable ADC end of conversion interrupt for injected channels */
<> 144:ef7eb2e8f9f7 4434 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
<> 144:ef7eb2e8f9f7 4435
<> 144:ef7eb2e8f9f7 4436 /* Set ADC state */
<> 144:ef7eb2e8f9f7 4437 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 4438 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 144:ef7eb2e8f9f7 4439 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 4440 }
<> 144:ef7eb2e8f9f7 4441 }
<> 144:ef7eb2e8f9f7 4442 else
<> 144:ef7eb2e8f9f7 4443 {
<> 144:ef7eb2e8f9f7 4444 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 4445 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 4446
<> 144:ef7eb2e8f9f7 4447 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 4448 }
<> 144:ef7eb2e8f9f7 4449
<> 144:ef7eb2e8f9f7 4450 /* Process unlocked */
<> 144:ef7eb2e8f9f7 4451 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 4452
<> 144:ef7eb2e8f9f7 4453 /* Return function status */
<> 144:ef7eb2e8f9f7 4454 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 4455 }
<> 144:ef7eb2e8f9f7 4456 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 4457
<> 144:ef7eb2e8f9f7 4458 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 4459 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 4460 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
<> 144:ef7eb2e8f9f7 4461 /**
<> 144:ef7eb2e8f9f7 4462 * @brief With ADC configured in multimode, for ADC master:
<> 144:ef7eb2e8f9f7 4463 * Enables ADC, starts conversion of regular group and transfers result
<> 144:ef7eb2e8f9f7 4464 * through DMA.
<> 144:ef7eb2e8f9f7 4465 * Multimode must have been previously configured using
<> 144:ef7eb2e8f9f7 4466 * HAL_ADCEx_MultiModeConfigChannel() function.
<> 144:ef7eb2e8f9f7 4467 * Interruptions enabled in this function:
<> 144:ef7eb2e8f9f7 4468 * - DMA transfer complete
<> 144:ef7eb2e8f9f7 4469 * - DMA half transfer
<> 144:ef7eb2e8f9f7 4470 * - overrun
<> 144:ef7eb2e8f9f7 4471 * Each of these interruptions has its dedicated callback function.
<> 144:ef7eb2e8f9f7 4472 * @note ADC slave must be preliminarily enabled using single-mode
<> 144:ef7eb2e8f9f7 4473 * HAL_ADC_Start() function.
<> 144:ef7eb2e8f9f7 4474 * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
<> 144:ef7eb2e8f9f7 4475 * @param pData: The destination Buffer address.
<> 144:ef7eb2e8f9f7 4476 * @param Length: The length of data to be transferred from ADC peripheral to memory.
<> 144:ef7eb2e8f9f7 4477 * @retval None
<> 144:ef7eb2e8f9f7 4478 */
<> 144:ef7eb2e8f9f7 4479 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
<> 144:ef7eb2e8f9f7 4480 {
<> 144:ef7eb2e8f9f7 4481 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 4482 ADC_HandleTypeDef tmphadcSlave;
<> 144:ef7eb2e8f9f7 4483 ADC_Common_TypeDef *tmpADC_Common;
<> 144:ef7eb2e8f9f7 4484
<> 144:ef7eb2e8f9f7 4485 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4486 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 4487 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
<> 144:ef7eb2e8f9f7 4488 assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
<> 144:ef7eb2e8f9f7 4489 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
<> 144:ef7eb2e8f9f7 4490
<> 144:ef7eb2e8f9f7 4491 /* Process locked */
<> 144:ef7eb2e8f9f7 4492 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 4493
<> 144:ef7eb2e8f9f7 4494 /* Perform ADC enable and conversion start if no conversion is on going */
<> 144:ef7eb2e8f9f7 4495 /* (check on ADC master only) */
<> 144:ef7eb2e8f9f7 4496 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<> 144:ef7eb2e8f9f7 4497 {
<> 144:ef7eb2e8f9f7 4498 /* Set a temporary handle of the ADC slave associated to the ADC master */
<> 144:ef7eb2e8f9f7 4499 /* (Depending on STM32F3 product, there may be up to 2 ADC slaves) */
<> 144:ef7eb2e8f9f7 4500 ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
<> 144:ef7eb2e8f9f7 4501
<> 144:ef7eb2e8f9f7 4502 if (tmphadcSlave.Instance == NULL)
<> 144:ef7eb2e8f9f7 4503 {
<> 144:ef7eb2e8f9f7 4504 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 4505 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 4506
<> 144:ef7eb2e8f9f7 4507 /* Process unlocked */
<> 144:ef7eb2e8f9f7 4508 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 4509
<> 144:ef7eb2e8f9f7 4510 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 4511 }
<> 144:ef7eb2e8f9f7 4512
<> 144:ef7eb2e8f9f7 4513
<> 144:ef7eb2e8f9f7 4514 /* Enable the ADC peripherals: master and slave (in case if not already */
<> 144:ef7eb2e8f9f7 4515 /* enabled previously) */
<> 144:ef7eb2e8f9f7 4516 tmp_hal_status = ADC_Enable(hadc);
<> 144:ef7eb2e8f9f7 4517 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 4518 {
<> 144:ef7eb2e8f9f7 4519 tmp_hal_status = ADC_Enable(&tmphadcSlave);
<> 144:ef7eb2e8f9f7 4520 }
<> 144:ef7eb2e8f9f7 4521
<> 144:ef7eb2e8f9f7 4522 /* Start conversion all ADCs of multimode are effectively enabled */
<> 144:ef7eb2e8f9f7 4523 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 4524 {
<> 144:ef7eb2e8f9f7 4525 /* Set ADC state (ADC master) */
<> 144:ef7eb2e8f9f7 4526 /* - Clear state bitfield related to regular group conversion results */
<> 144:ef7eb2e8f9f7 4527 /* - Set state bitfield related to regular operation */
<> 144:ef7eb2e8f9f7 4528 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 4529 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP | HAL_ADC_STATE_MULTIMODE_SLAVE,
<> 144:ef7eb2e8f9f7 4530 HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 4531
<> 144:ef7eb2e8f9f7 4532 /* If conversions on group regular are also triggering group injected, */
<> 144:ef7eb2e8f9f7 4533 /* update ADC state. */
<> 144:ef7eb2e8f9f7 4534 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
<> 144:ef7eb2e8f9f7 4535 {
<> 144:ef7eb2e8f9f7 4536 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 4537 }
<> 144:ef7eb2e8f9f7 4538
<> 144:ef7eb2e8f9f7 4539 /* Process unlocked */
<> 144:ef7eb2e8f9f7 4540 /* Unlock before starting ADC conversions: in case of potential */
<> 144:ef7eb2e8f9f7 4541 /* interruption, to let the process to ADC IRQ Handler. */
<> 144:ef7eb2e8f9f7 4542 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 4543
<> 144:ef7eb2e8f9f7 4544 /* Set ADC error code to none */
<> 144:ef7eb2e8f9f7 4545 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 4546
<> 144:ef7eb2e8f9f7 4547
<> 144:ef7eb2e8f9f7 4548 /* Set the DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 4549 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
<> 144:ef7eb2e8f9f7 4550
<> 144:ef7eb2e8f9f7 4551 /* Set the DMA half transfer complete callback */
<> 144:ef7eb2e8f9f7 4552 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
<> 144:ef7eb2e8f9f7 4553
<> 144:ef7eb2e8f9f7 4554 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 4555 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
<> 144:ef7eb2e8f9f7 4556
<> 144:ef7eb2e8f9f7 4557 /* Pointer to the common control register to which is belonging hadc */
<> 144:ef7eb2e8f9f7 4558 /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
<> 144:ef7eb2e8f9f7 4559 /* control registers) */
<> 144:ef7eb2e8f9f7 4560 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
<> 144:ef7eb2e8f9f7 4561
<> 144:ef7eb2e8f9f7 4562
<> 144:ef7eb2e8f9f7 4563 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
<> 144:ef7eb2e8f9f7 4564 /* start (in case of SW start): */
<> 144:ef7eb2e8f9f7 4565
<> 144:ef7eb2e8f9f7 4566 /* Clear regular group conversion flag and overrun flag */
<> 144:ef7eb2e8f9f7 4567 /* (To ensure of no unknown state from potential previous ADC operations) */
<> 144:ef7eb2e8f9f7 4568 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
<> 144:ef7eb2e8f9f7 4569
<> 144:ef7eb2e8f9f7 4570 /* Enable ADC overrun interrupt */
<> 144:ef7eb2e8f9f7 4571 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
<> 144:ef7eb2e8f9f7 4572
<> 144:ef7eb2e8f9f7 4573 /* Start the DMA channel */
<> 144:ef7eb2e8f9f7 4574 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 4575
<> 144:ef7eb2e8f9f7 4576 /* Enable conversion of regular group. */
<> 144:ef7eb2e8f9f7 4577 /* If software start has been selected, conversion starts immediately. */
<> 144:ef7eb2e8f9f7 4578 /* If external trigger has been selected, conversion will start at next */
<> 144:ef7eb2e8f9f7 4579 /* trigger event. */
<> 144:ef7eb2e8f9f7 4580 SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
<> 144:ef7eb2e8f9f7 4581
<> 144:ef7eb2e8f9f7 4582 }
<> 144:ef7eb2e8f9f7 4583 else
<> 144:ef7eb2e8f9f7 4584 {
<> 144:ef7eb2e8f9f7 4585 /* Process unlocked */
<> 144:ef7eb2e8f9f7 4586 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 4587 }
<> 144:ef7eb2e8f9f7 4588 }
<> 144:ef7eb2e8f9f7 4589 else
<> 144:ef7eb2e8f9f7 4590 {
<> 144:ef7eb2e8f9f7 4591 tmp_hal_status = HAL_BUSY;
<> 144:ef7eb2e8f9f7 4592 }
<> 144:ef7eb2e8f9f7 4593
<> 144:ef7eb2e8f9f7 4594 /* Return function status */
<> 144:ef7eb2e8f9f7 4595 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 4596 }
<> 144:ef7eb2e8f9f7 4597
<> 144:ef7eb2e8f9f7 4598 /**
<> 144:ef7eb2e8f9f7 4599 * @brief With ADC configured in multimode, for ADC master:
<> 144:ef7eb2e8f9f7 4600 * Stop ADC group regular conversion (potential conversion on going
<> 144:ef7eb2e8f9f7 4601 * on ADC group injected is not impacted),
<> 144:ef7eb2e8f9f7 4602 * disable ADC DMA transfer, disable ADC peripheral
<> 144:ef7eb2e8f9f7 4603 * if no conversion is on going on group injected.
<> 144:ef7eb2e8f9f7 4604 * Interruptions disabled in this function:
<> 144:ef7eb2e8f9f7 4605 * - DMA transfer complete
<> 144:ef7eb2e8f9f7 4606 * - DMA half transfer
<> 144:ef7eb2e8f9f7 4607 * - overrun
<> 144:ef7eb2e8f9f7 4608 * @note In case of auto-injection mode, this function also stop conversion
<> 144:ef7eb2e8f9f7 4609 * on ADC group injected.
<> 144:ef7eb2e8f9f7 4610 * @note Multimode is kept enabled after this function. To disable multimode
<> 144:ef7eb2e8f9f7 4611 * (set with HAL_ADCEx_MultiModeConfigChannel() ), ADC must be
<> 144:ef7eb2e8f9f7 4612 * reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit().
<> 144:ef7eb2e8f9f7 4613 * @note In case of DMA configured in circular mode, function
<> 144:ef7eb2e8f9f7 4614 * HAL_ADC_Stop_DMA must be called after this function with handle of
<> 144:ef7eb2e8f9f7 4615 * ADC slave, to properly disable the DMA channel of ADC slave.
<> 144:ef7eb2e8f9f7 4616 * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
<> 144:ef7eb2e8f9f7 4617 * @retval None
<> 144:ef7eb2e8f9f7 4618 */
<> 144:ef7eb2e8f9f7 4619 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 4620 {
<> 144:ef7eb2e8f9f7 4621 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 4622 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 4623 ADC_HandleTypeDef tmphadcSlave;
<> 144:ef7eb2e8f9f7 4624
<> 144:ef7eb2e8f9f7 4625 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4626 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 4627
<> 144:ef7eb2e8f9f7 4628 /* Process locked */
<> 144:ef7eb2e8f9f7 4629 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 4630
<> 144:ef7eb2e8f9f7 4631 /* 1. Stop potential multimode conversion on going, on regular and */
<> 144:ef7eb2e8f9f7 4632 /* injected groups. */
<> 144:ef7eb2e8f9f7 4633 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
<> 144:ef7eb2e8f9f7 4634
<> 144:ef7eb2e8f9f7 4635 /* Disable ADC peripheral if conversions are effectively stopped */
<> 144:ef7eb2e8f9f7 4636 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 4637 {
<> 144:ef7eb2e8f9f7 4638 /* Set a temporary handle of the ADC slave associated to the ADC master */
<> 144:ef7eb2e8f9f7 4639 /* (Depending on STM32F3 product, there may be up to 2 ADC slaves) */
<> 144:ef7eb2e8f9f7 4640 ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
<> 144:ef7eb2e8f9f7 4641
<> 144:ef7eb2e8f9f7 4642 if (tmphadcSlave.Instance == NULL)
<> 144:ef7eb2e8f9f7 4643 {
<> 144:ef7eb2e8f9f7 4644 /* Update ADC state machine (ADC master) to error */
<> 144:ef7eb2e8f9f7 4645 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
<> 144:ef7eb2e8f9f7 4646
<> 144:ef7eb2e8f9f7 4647 /* Process unlocked */
<> 144:ef7eb2e8f9f7 4648 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 4649
<> 144:ef7eb2e8f9f7 4650 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 4651 }
<> 144:ef7eb2e8f9f7 4652
<> 144:ef7eb2e8f9f7 4653 /* Procedure to disable the ADC peripheral: wait for conversions */
<> 144:ef7eb2e8f9f7 4654 /* effectively stopped (ADC master and ADC slave), then disable ADC */
<> 144:ef7eb2e8f9f7 4655
<> 144:ef7eb2e8f9f7 4656 /* 1. Wait until ADSTP=0 for ADC master and ADC slave */
<> 144:ef7eb2e8f9f7 4657 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 4658
<> 144:ef7eb2e8f9f7 4659 while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) ||
<> 144:ef7eb2e8f9f7 4660 ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) )
<> 144:ef7eb2e8f9f7 4661 {
<> 144:ef7eb2e8f9f7 4662 if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
<> 144:ef7eb2e8f9f7 4663 {
<> 144:ef7eb2e8f9f7 4664 /* Update ADC state machine (ADC master) to error */
<> 144:ef7eb2e8f9f7 4665 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 4666
<> 144:ef7eb2e8f9f7 4667 /* Process unlocked */
<> 144:ef7eb2e8f9f7 4668 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 4669
<> 144:ef7eb2e8f9f7 4670 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 4671 }
<> 144:ef7eb2e8f9f7 4672 }
<> 144:ef7eb2e8f9f7 4673
<> 144:ef7eb2e8f9f7 4674 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
<> 144:ef7eb2e8f9f7 4675 /* while DMA transfer is on going) */
<> 144:ef7eb2e8f9f7 4676 /* Note: In case of ADC slave using its own DMA channel (multimode */
<> 144:ef7eb2e8f9f7 4677 /* parameter "DMAAccessMode" set to disabled): */
<> 144:ef7eb2e8f9f7 4678 /* DMA channel of ADC slave should stopped after this function with */
<> 144:ef7eb2e8f9f7 4679 /* function HAL_ADC_Stop_DMA. */
<> 144:ef7eb2e8f9f7 4680 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
<> 144:ef7eb2e8f9f7 4681
<> 144:ef7eb2e8f9f7 4682 /* Check if DMA channel effectively disabled */
<> 144:ef7eb2e8f9f7 4683 if (tmp_hal_status != HAL_OK)
<> 144:ef7eb2e8f9f7 4684 {
<> 144:ef7eb2e8f9f7 4685 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 4686 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
<> 144:ef7eb2e8f9f7 4687 }
<> 144:ef7eb2e8f9f7 4688
<> 144:ef7eb2e8f9f7 4689 /* Disable ADC overrun interrupt */
<> 144:ef7eb2e8f9f7 4690 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
<> 144:ef7eb2e8f9f7 4691
<> 144:ef7eb2e8f9f7 4692
<> 144:ef7eb2e8f9f7 4693
<> 144:ef7eb2e8f9f7 4694 /* 2. Disable the ADC peripherals: master and slave */
<> 144:ef7eb2e8f9f7 4695 /* Update "tmp_hal_status" only if DMA channel disabling passed, */
<> 144:ef7eb2e8f9f7 4696 /* to retain a potential failing status. */
<> 144:ef7eb2e8f9f7 4697 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 4698 {
<> 144:ef7eb2e8f9f7 4699 /* Check if ADC are effectively disabled */
<> 144:ef7eb2e8f9f7 4700 if ((ADC_Disable(hadc) != HAL_ERROR) &&
<> 144:ef7eb2e8f9f7 4701 (ADC_Disable(&tmphadcSlave) != HAL_ERROR) )
<> 144:ef7eb2e8f9f7 4702 {
<> 144:ef7eb2e8f9f7 4703 tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 4704
<> 144:ef7eb2e8f9f7 4705 /* Change ADC state (ADC master) */
<> 144:ef7eb2e8f9f7 4706 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 4707 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 144:ef7eb2e8f9f7 4708 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 4709 }
<> 144:ef7eb2e8f9f7 4710 }
<> 144:ef7eb2e8f9f7 4711 else
<> 144:ef7eb2e8f9f7 4712 {
<> 144:ef7eb2e8f9f7 4713 /* In case of error, attempt to disable ADC instances anyway */
<> 144:ef7eb2e8f9f7 4714 ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 4715 ADC_Disable(&tmphadcSlave);
<> 144:ef7eb2e8f9f7 4716
<> 144:ef7eb2e8f9f7 4717 /* Update ADC state machine (ADC master) to error */
<> 144:ef7eb2e8f9f7 4718 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 4719 }
<> 144:ef7eb2e8f9f7 4720
<> 144:ef7eb2e8f9f7 4721 }
<> 144:ef7eb2e8f9f7 4722
<> 144:ef7eb2e8f9f7 4723 /* Process unlocked */
<> 144:ef7eb2e8f9f7 4724 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 4725
<> 144:ef7eb2e8f9f7 4726 /* Return function status */
<> 144:ef7eb2e8f9f7 4727 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 4728 }
<> 144:ef7eb2e8f9f7 4729
<> 144:ef7eb2e8f9f7 4730 /**
<> 144:ef7eb2e8f9f7 4731 * @brief Returns the last ADC Master&Slave regular conversions results data
<> 144:ef7eb2e8f9f7 4732 * in the selected multi mode.
<> 144:ef7eb2e8f9f7 4733 * @note Reading register CDR does not clear flag ADC flag EOC
<> 144:ef7eb2e8f9f7 4734 * (ADC group regular end of unitary conversion),
<> 144:ef7eb2e8f9f7 4735 * as it is the case for independent mode data register.
<> 144:ef7eb2e8f9f7 4736 * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
<> 144:ef7eb2e8f9f7 4737 * @retval The converted data value.
<> 144:ef7eb2e8f9f7 4738 */
<> 144:ef7eb2e8f9f7 4739 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 4740 {
<> 144:ef7eb2e8f9f7 4741 ADC_Common_TypeDef *tmpADC_Common;
<> 144:ef7eb2e8f9f7 4742
<> 144:ef7eb2e8f9f7 4743 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4744 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 4745
<> 144:ef7eb2e8f9f7 4746 /* Pointer to the common control register to which is belonging hadc */
<> 144:ef7eb2e8f9f7 4747 /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
<> 144:ef7eb2e8f9f7 4748 /* control registers) */
<> 144:ef7eb2e8f9f7 4749 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
<> 144:ef7eb2e8f9f7 4750
<> 144:ef7eb2e8f9f7 4751 /* Return the multi mode conversion value */
<> 144:ef7eb2e8f9f7 4752 return tmpADC_Common->CDR;
<> 144:ef7eb2e8f9f7 4753 }
<> 144:ef7eb2e8f9f7 4754 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 4755 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 4756 /* STM32F303x8 || STM32F334x8 || STM32F328xx */
<> 144:ef7eb2e8f9f7 4757
<> 144:ef7eb2e8f9f7 4758 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 4759 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 4760 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 4761 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 4762 /**
<> 144:ef7eb2e8f9f7 4763 * @brief Get ADC injected group conversion result.
<> 144:ef7eb2e8f9f7 4764 * @note Reading register JDRx automatically clears ADC flag JEOC
<> 144:ef7eb2e8f9f7 4765 * (ADC group injected end of unitary conversion).
<> 144:ef7eb2e8f9f7 4766 * @note This function does not clear ADC flag JEOS
<> 144:ef7eb2e8f9f7 4767 * (ADC group injected end of sequence conversion)
<> 144:ef7eb2e8f9f7 4768 * Occurrence of flag JEOS rising:
<> 144:ef7eb2e8f9f7 4769 * - If sequencer is composed of 1 rank, flag JEOS is equivalent
<> 144:ef7eb2e8f9f7 4770 * to flag JEOC.
<> 144:ef7eb2e8f9f7 4771 * - If sequencer is composed of several ranks, during the scan
<> 144:ef7eb2e8f9f7 4772 * sequence flag JEOC only is raised, at the end of the scan sequence
<> 144:ef7eb2e8f9f7 4773 * both flags JEOC and EOS are raised.
<> 144:ef7eb2e8f9f7 4774 * Flag JEOS must not be cleared by this function because
<> 144:ef7eb2e8f9f7 4775 * it would not be compliant with low power features
<> 144:ef7eb2e8f9f7 4776 * (feature low power auto-wait, not available on all STM32 families).
<> 144:ef7eb2e8f9f7 4777 * To clear this flag, either use function:
<> 144:ef7eb2e8f9f7 4778 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
<> 144:ef7eb2e8f9f7 4779 * model polling: @ref HAL_ADCEx_InjectedPollForConversion()
<> 144:ef7eb2e8f9f7 4780 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
<> 144:ef7eb2e8f9f7 4781 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 4782 * @param InjectedRank: the converted ADC injected rank.
<> 144:ef7eb2e8f9f7 4783 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4784 * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
<> 144:ef7eb2e8f9f7 4785 * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
<> 144:ef7eb2e8f9f7 4786 * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
<> 144:ef7eb2e8f9f7 4787 * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
<> 144:ef7eb2e8f9f7 4788 * @retval ADC group injected conversion data
<> 144:ef7eb2e8f9f7 4789 */
<> 144:ef7eb2e8f9f7 4790 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
<> 144:ef7eb2e8f9f7 4791 {
<> 144:ef7eb2e8f9f7 4792 uint32_t tmp_jdr = 0;
<> 144:ef7eb2e8f9f7 4793
<> 144:ef7eb2e8f9f7 4794 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4795 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 4796 assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
<> 144:ef7eb2e8f9f7 4797
<> 144:ef7eb2e8f9f7 4798 /* Note: ADC flag JEOC is not cleared here by software because */
<> 144:ef7eb2e8f9f7 4799 /* automatically cleared by hardware when reading register JDRx. */
<> 144:ef7eb2e8f9f7 4800
<> 144:ef7eb2e8f9f7 4801 /* Get ADC converted value */
<> 144:ef7eb2e8f9f7 4802 switch(InjectedRank)
<> 144:ef7eb2e8f9f7 4803 {
<> 144:ef7eb2e8f9f7 4804 case ADC_INJECTED_RANK_4:
<> 144:ef7eb2e8f9f7 4805 tmp_jdr = hadc->Instance->JDR4;
<> 144:ef7eb2e8f9f7 4806 break;
<> 144:ef7eb2e8f9f7 4807 case ADC_INJECTED_RANK_3:
<> 144:ef7eb2e8f9f7 4808 tmp_jdr = hadc->Instance->JDR3;
<> 144:ef7eb2e8f9f7 4809 break;
<> 144:ef7eb2e8f9f7 4810 case ADC_INJECTED_RANK_2:
<> 144:ef7eb2e8f9f7 4811 tmp_jdr = hadc->Instance->JDR2;
<> 144:ef7eb2e8f9f7 4812 break;
<> 144:ef7eb2e8f9f7 4813 case ADC_INJECTED_RANK_1:
<> 144:ef7eb2e8f9f7 4814 default:
<> 144:ef7eb2e8f9f7 4815 tmp_jdr = hadc->Instance->JDR1;
<> 144:ef7eb2e8f9f7 4816 break;
<> 144:ef7eb2e8f9f7 4817 }
<> 144:ef7eb2e8f9f7 4818
<> 144:ef7eb2e8f9f7 4819 /* Return ADC converted value */
<> 144:ef7eb2e8f9f7 4820 return tmp_jdr;
<> 144:ef7eb2e8f9f7 4821 }
<> 144:ef7eb2e8f9f7 4822 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 4823 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 4824 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 4825 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 4826
<> 144:ef7eb2e8f9f7 4827 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 4828 /**
<> 144:ef7eb2e8f9f7 4829 * @brief Get ADC injected group conversion result.
<> 144:ef7eb2e8f9f7 4830 * @note Reading register JDRx automatically clears ADC flag JEOC
<> 144:ef7eb2e8f9f7 4831 * (ADC group injected end of unitary conversion).
<> 144:ef7eb2e8f9f7 4832 * @note This function does not clear ADC flag JEOS
<> 144:ef7eb2e8f9f7 4833 * (ADC group injected end of sequence conversion)
<> 144:ef7eb2e8f9f7 4834 * Occurrence of flag JEOS rising:
<> 144:ef7eb2e8f9f7 4835 * - If sequencer is composed of 1 rank, flag JEOS is equivalent
<> 144:ef7eb2e8f9f7 4836 * to flag JEOC.
<> 144:ef7eb2e8f9f7 4837 * - If sequencer is composed of several ranks, during the scan
<> 144:ef7eb2e8f9f7 4838 * sequence flag JEOC only is raised, at the end of the scan sequence
<> 144:ef7eb2e8f9f7 4839 * both flags JEOC and EOS are raised.
<> 144:ef7eb2e8f9f7 4840 * Flag JEOS must not be cleared by this function because
<> 144:ef7eb2e8f9f7 4841 * it would not be compliant with low power features
<> 144:ef7eb2e8f9f7 4842 * (feature low power auto-wait, not available on all STM32 families).
<> 144:ef7eb2e8f9f7 4843 * To clear this flag, either use function:
<> 144:ef7eb2e8f9f7 4844 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
<> 144:ef7eb2e8f9f7 4845 * model polling: @ref HAL_ADCEx_InjectedPollForConversion()
<> 144:ef7eb2e8f9f7 4846 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
<> 144:ef7eb2e8f9f7 4847 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 4848 * @param InjectedRank: the converted ADC injected rank.
<> 144:ef7eb2e8f9f7 4849 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4850 * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
<> 144:ef7eb2e8f9f7 4851 * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
<> 144:ef7eb2e8f9f7 4852 * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
<> 144:ef7eb2e8f9f7 4853 * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
<> 144:ef7eb2e8f9f7 4854 * @retval ADC group injected conversion data
<> 144:ef7eb2e8f9f7 4855 */
<> 144:ef7eb2e8f9f7 4856 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
<> 144:ef7eb2e8f9f7 4857 {
<> 144:ef7eb2e8f9f7 4858 uint32_t tmp_jdr = 0;
<> 144:ef7eb2e8f9f7 4859
<> 144:ef7eb2e8f9f7 4860 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4861 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 4862 assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
<> 144:ef7eb2e8f9f7 4863
<> 144:ef7eb2e8f9f7 4864 /* Get ADC converted value */
<> 144:ef7eb2e8f9f7 4865 switch(InjectedRank)
<> 144:ef7eb2e8f9f7 4866 {
<> 144:ef7eb2e8f9f7 4867 case ADC_INJECTED_RANK_4:
<> 144:ef7eb2e8f9f7 4868 tmp_jdr = hadc->Instance->JDR4;
<> 144:ef7eb2e8f9f7 4869 break;
<> 144:ef7eb2e8f9f7 4870 case ADC_INJECTED_RANK_3:
<> 144:ef7eb2e8f9f7 4871 tmp_jdr = hadc->Instance->JDR3;
<> 144:ef7eb2e8f9f7 4872 break;
<> 144:ef7eb2e8f9f7 4873 case ADC_INJECTED_RANK_2:
<> 144:ef7eb2e8f9f7 4874 tmp_jdr = hadc->Instance->JDR2;
<> 144:ef7eb2e8f9f7 4875 break;
<> 144:ef7eb2e8f9f7 4876 case ADC_INJECTED_RANK_1:
<> 144:ef7eb2e8f9f7 4877 default:
<> 144:ef7eb2e8f9f7 4878 tmp_jdr = hadc->Instance->JDR1;
<> 144:ef7eb2e8f9f7 4879 break;
<> 144:ef7eb2e8f9f7 4880 }
<> 144:ef7eb2e8f9f7 4881
<> 144:ef7eb2e8f9f7 4882 /* Return ADC converted value */
<> 144:ef7eb2e8f9f7 4883 return tmp_jdr;
<> 144:ef7eb2e8f9f7 4884 }
<> 144:ef7eb2e8f9f7 4885 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 4886
<> 144:ef7eb2e8f9f7 4887 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 4888 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 4889 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 4890 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 4891 /**
<> 144:ef7eb2e8f9f7 4892 * @brief Stop ADC group regular conversion (potential conversion on going
<> 144:ef7eb2e8f9f7 4893 * on ADC group injected is not impacted), disable ADC peripheral
<> 144:ef7eb2e8f9f7 4894 * if no conversion is on going on group injected.
<> 144:ef7eb2e8f9f7 4895 * @note To stop ADC conversion of both groups regular and injected and to
<> 144:ef7eb2e8f9f7 4896 * to disable ADC peripheral, instead of using 2 functions
<> 144:ef7eb2e8f9f7 4897 * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
<> 144:ef7eb2e8f9f7 4898 * use function @ref HAL_ADC_Stop().
<> 144:ef7eb2e8f9f7 4899 * @note In case of auto-injection mode, this function also stop conversion
<> 144:ef7eb2e8f9f7 4900 * on ADC group injected.
<> 144:ef7eb2e8f9f7 4901 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 4902 * @retval HAL status.
<> 144:ef7eb2e8f9f7 4903 */
<> 144:ef7eb2e8f9f7 4904 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 4905 {
<> 144:ef7eb2e8f9f7 4906 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 4907
<> 144:ef7eb2e8f9f7 4908 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4909 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 4910
<> 144:ef7eb2e8f9f7 4911 /* Process locked */
<> 144:ef7eb2e8f9f7 4912 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 4913
<> 144:ef7eb2e8f9f7 4914 /* Stop potential ADC conversion on going and disable ADC peripheral */
<> 144:ef7eb2e8f9f7 4915 /* conditioned to: */
<> 144:ef7eb2e8f9f7 4916 /* - For ADC regular group conversion stop: */
<> 144:ef7eb2e8f9f7 4917 /* On this STM32 family, conversion on the other group */
<> 144:ef7eb2e8f9f7 4918 /* (group injected) can continue (groups regular and injected */
<> 144:ef7eb2e8f9f7 4919 /* conversion stop commands are independent) */
<> 144:ef7eb2e8f9f7 4920 /* - For ADC disable: */
<> 144:ef7eb2e8f9f7 4921 /* No conversion on the other group (group injected) must be intended to */
<> 144:ef7eb2e8f9f7 4922 /* continue (groups regular and injected are both impacted by */
<> 144:ef7eb2e8f9f7 4923 /* ADC disable) */
<> 144:ef7eb2e8f9f7 4924
<> 144:ef7eb2e8f9f7 4925 /* 1. Stop potential conversion on going, on regular group only */
<> 144:ef7eb2e8f9f7 4926 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
<> 144:ef7eb2e8f9f7 4927
<> 144:ef7eb2e8f9f7 4928 /* Disable ADC peripheral if conversion on ADC group regular is */
<> 144:ef7eb2e8f9f7 4929 /* effectively stopped and if no conversion on the other group */
<> 144:ef7eb2e8f9f7 4930 /* (ADC group injected) is intended to continue. */
<> 144:ef7eb2e8f9f7 4931 if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) &&
<> 144:ef7eb2e8f9f7 4932 ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET) )
<> 144:ef7eb2e8f9f7 4933 {
<> 144:ef7eb2e8f9f7 4934 /* 2. Disable the ADC peripheral */
<> 144:ef7eb2e8f9f7 4935 tmp_hal_status = ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 4936
<> 144:ef7eb2e8f9f7 4937 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 4938 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 4939 {
<> 144:ef7eb2e8f9f7 4940 /* Set ADC state */
<> 144:ef7eb2e8f9f7 4941 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 4942 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 144:ef7eb2e8f9f7 4943 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 4944 }
<> 144:ef7eb2e8f9f7 4945 }
<> 144:ef7eb2e8f9f7 4946 /* Conversion on ADC group regular group is stopped, but ADC is not */
<> 144:ef7eb2e8f9f7 4947 /* disabled since conversion on ADC group injected is still on going. */
<> 144:ef7eb2e8f9f7 4948 else
<> 144:ef7eb2e8f9f7 4949 {
<> 144:ef7eb2e8f9f7 4950 /* Set ADC state */
<> 144:ef7eb2e8f9f7 4951 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 4952 }
<> 144:ef7eb2e8f9f7 4953
<> 144:ef7eb2e8f9f7 4954 /* Process unlocked */
<> 144:ef7eb2e8f9f7 4955 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 4956
<> 144:ef7eb2e8f9f7 4957 /* Return function status */
<> 144:ef7eb2e8f9f7 4958 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 4959 }
<> 144:ef7eb2e8f9f7 4960
<> 144:ef7eb2e8f9f7 4961 /**
<> 144:ef7eb2e8f9f7 4962 * @brief Stop ADC group regular conversion (potential conversion on going
<> 144:ef7eb2e8f9f7 4963 * on ADC group injected is not impacted), disable ADC peripheral
<> 144:ef7eb2e8f9f7 4964 * if no conversion is on going on group injected.
<> 144:ef7eb2e8f9f7 4965 * Interruptions disabled in this function:
<> 144:ef7eb2e8f9f7 4966 * - EOC (end of conversion of regular group) and EOS (end of
<> 144:ef7eb2e8f9f7 4967 * sequence of regular group)
<> 144:ef7eb2e8f9f7 4968 * - overrun
<> 144:ef7eb2e8f9f7 4969 * @note To stop ADC conversion of both groups regular and injected and to
<> 144:ef7eb2e8f9f7 4970 * to disable ADC peripheral, instead of using 2 functions
<> 144:ef7eb2e8f9f7 4971 * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
<> 144:ef7eb2e8f9f7 4972 * use function @ref HAL_ADC_Stop().
<> 144:ef7eb2e8f9f7 4973 * @note In case of auto-injection mode, this function also stop conversion
<> 144:ef7eb2e8f9f7 4974 * on ADC group injected.
<> 144:ef7eb2e8f9f7 4975 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 4976 * @retval HAL status.
<> 144:ef7eb2e8f9f7 4977 */
<> 144:ef7eb2e8f9f7 4978 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 4979 {
<> 144:ef7eb2e8f9f7 4980 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 4981
<> 144:ef7eb2e8f9f7 4982 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4983 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 4984
<> 144:ef7eb2e8f9f7 4985 /* Process locked */
<> 144:ef7eb2e8f9f7 4986 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 4987
<> 144:ef7eb2e8f9f7 4988 /* Stop potential ADC conversion on going and disable ADC peripheral */
<> 144:ef7eb2e8f9f7 4989 /* conditioned to: */
<> 144:ef7eb2e8f9f7 4990 /* - For ADC regular group conversion stop: */
<> 144:ef7eb2e8f9f7 4991 /* On this STM32 family, conversion on the other group */
<> 144:ef7eb2e8f9f7 4992 /* (group injected) can continue (groups regular and injected */
<> 144:ef7eb2e8f9f7 4993 /* conversion stop commands are independent) */
<> 144:ef7eb2e8f9f7 4994 /* - For ADC disable: */
<> 144:ef7eb2e8f9f7 4995 /* No conversion on the other group (group injected) must be intended to */
<> 144:ef7eb2e8f9f7 4996 /* continue (groups regular and injected are both impacted by */
<> 144:ef7eb2e8f9f7 4997 /* ADC disable) */
<> 144:ef7eb2e8f9f7 4998
<> 144:ef7eb2e8f9f7 4999 /* 1. Stop potential conversion on going, on regular group only */
<> 144:ef7eb2e8f9f7 5000 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
<> 144:ef7eb2e8f9f7 5001
<> 144:ef7eb2e8f9f7 5002 /* Disable ADC peripheral if conversion on ADC group regular is */
<> 144:ef7eb2e8f9f7 5003 /* effectively stopped and if no conversion on the other group */
<> 144:ef7eb2e8f9f7 5004 /* (ADC group injected) is intended to continue. */
<> 144:ef7eb2e8f9f7 5005 if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) &&
<> 144:ef7eb2e8f9f7 5006 ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET) )
<> 144:ef7eb2e8f9f7 5007 {
<> 144:ef7eb2e8f9f7 5008 /* Disable ADC end of conversion interrupt for regular group */
<> 144:ef7eb2e8f9f7 5009 /* Disable ADC overrun interrupt */
<> 144:ef7eb2e8f9f7 5010 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
<> 144:ef7eb2e8f9f7 5011
<> 144:ef7eb2e8f9f7 5012 /* 2. Disable the ADC peripheral */
<> 144:ef7eb2e8f9f7 5013 tmp_hal_status = ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 5014
<> 144:ef7eb2e8f9f7 5015 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 5016 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 5017 {
<> 144:ef7eb2e8f9f7 5018 /* Set ADC state */
<> 144:ef7eb2e8f9f7 5019 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 5020 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 144:ef7eb2e8f9f7 5021 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 5022 }
<> 144:ef7eb2e8f9f7 5023 }
<> 144:ef7eb2e8f9f7 5024 /* Conversion on ADC group regular group is stopped, but ADC is not */
<> 144:ef7eb2e8f9f7 5025 /* disabled since conversion on ADC group injected is still on going. */
<> 144:ef7eb2e8f9f7 5026 else
<> 144:ef7eb2e8f9f7 5027 {
<> 144:ef7eb2e8f9f7 5028 /* Set ADC state */
<> 144:ef7eb2e8f9f7 5029 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 5030 }
<> 144:ef7eb2e8f9f7 5031
<> 144:ef7eb2e8f9f7 5032 /* Process unlocked */
<> 144:ef7eb2e8f9f7 5033 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 5034
<> 144:ef7eb2e8f9f7 5035 /* Return function status */
<> 144:ef7eb2e8f9f7 5036 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 5037 }
<> 144:ef7eb2e8f9f7 5038
<> 144:ef7eb2e8f9f7 5039 /**
<> 144:ef7eb2e8f9f7 5040 * @brief Stop ADC group regular conversion (potential conversion on going
<> 144:ef7eb2e8f9f7 5041 * on ADC group injected is not impacted),
<> 144:ef7eb2e8f9f7 5042 * disable ADC DMA transfer, disable ADC peripheral
<> 144:ef7eb2e8f9f7 5043 * if no conversion is on going on group injected.
<> 144:ef7eb2e8f9f7 5044 * Interruptions disabled in this function:
<> 144:ef7eb2e8f9f7 5045 * - DMA transfer complete
<> 144:ef7eb2e8f9f7 5046 * - DMA half transfer
<> 144:ef7eb2e8f9f7 5047 * - overrun
<> 144:ef7eb2e8f9f7 5048 * @note To stop ADC conversion of both groups regular and injected and to
<> 144:ef7eb2e8f9f7 5049 * to disable ADC peripheral, instead of using 2 functions
<> 144:ef7eb2e8f9f7 5050 * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
<> 144:ef7eb2e8f9f7 5051 * use function @ref HAL_ADC_Stop().
<> 144:ef7eb2e8f9f7 5052 * @note Case of multimode enabled (for devices with several ADCs): This
<> 144:ef7eb2e8f9f7 5053 * function is for single-ADC mode only. For multimode, use the
<> 144:ef7eb2e8f9f7 5054 * dedicated MultimodeStop function.
<> 144:ef7eb2e8f9f7 5055 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 5056 * @retval HAL status.
<> 144:ef7eb2e8f9f7 5057 */
<> 144:ef7eb2e8f9f7 5058 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 5059 {
<> 144:ef7eb2e8f9f7 5060 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 5061
<> 144:ef7eb2e8f9f7 5062 /* Check the parameters */
<> 144:ef7eb2e8f9f7 5063 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 5064
<> 144:ef7eb2e8f9f7 5065 /* Process locked */
<> 144:ef7eb2e8f9f7 5066 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 5067
<> 144:ef7eb2e8f9f7 5068 /* Stop potential ADC conversion on going and disable ADC peripheral */
<> 144:ef7eb2e8f9f7 5069 /* conditioned to: */
<> 144:ef7eb2e8f9f7 5070 /* - For ADC regular group conversion stop: */
<> 144:ef7eb2e8f9f7 5071 /* On this STM32 family, conversion on the other group */
<> 144:ef7eb2e8f9f7 5072 /* (group injected) can continue (groups regular and injected */
<> 144:ef7eb2e8f9f7 5073 /* conversion stop commands are independent) */
<> 144:ef7eb2e8f9f7 5074 /* - For ADC disable: */
<> 144:ef7eb2e8f9f7 5075 /* No conversion on the other group (group injected) must be intended to */
<> 144:ef7eb2e8f9f7 5076 /* continue (groups regular and injected are both impacted by */
<> 144:ef7eb2e8f9f7 5077 /* ADC disable) */
<> 144:ef7eb2e8f9f7 5078
<> 144:ef7eb2e8f9f7 5079 /* 1. Stop potential conversion on going, on regular group only */
<> 144:ef7eb2e8f9f7 5080 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
<> 144:ef7eb2e8f9f7 5081
<> 144:ef7eb2e8f9f7 5082 /* Disable ADC peripheral if conversion on ADC group regular is */
<> 144:ef7eb2e8f9f7 5083 /* effectively stopped and if no conversion on the other group */
<> 144:ef7eb2e8f9f7 5084 /* (ADC group injected) is intended to continue. */
<> 144:ef7eb2e8f9f7 5085 if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) &&
<> 144:ef7eb2e8f9f7 5086 ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET) )
<> 144:ef7eb2e8f9f7 5087 {
<> 144:ef7eb2e8f9f7 5088 /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
<> 144:ef7eb2e8f9f7 5089 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
<> 144:ef7eb2e8f9f7 5090
<> 144:ef7eb2e8f9f7 5091 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
<> 144:ef7eb2e8f9f7 5092 /* while DMA transfer is on going) */
<> 144:ef7eb2e8f9f7 5093 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
<> 144:ef7eb2e8f9f7 5094
<> 144:ef7eb2e8f9f7 5095 /* Check if DMA channel effectively disabled */
<> 144:ef7eb2e8f9f7 5096 if (tmp_hal_status != HAL_OK)
<> 144:ef7eb2e8f9f7 5097 {
<> 144:ef7eb2e8f9f7 5098 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 5099 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
<> 144:ef7eb2e8f9f7 5100 }
<> 144:ef7eb2e8f9f7 5101
<> 144:ef7eb2e8f9f7 5102 /* Disable ADC overrun interrupt */
<> 144:ef7eb2e8f9f7 5103 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
<> 144:ef7eb2e8f9f7 5104
<> 144:ef7eb2e8f9f7 5105 /* 2. Disable the ADC peripheral */
<> 144:ef7eb2e8f9f7 5106 /* Update "tmp_hal_status" only if DMA channel disabling passed, */
<> 144:ef7eb2e8f9f7 5107 /* to retain a potential failing status. */
<> 144:ef7eb2e8f9f7 5108 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 5109 {
<> 144:ef7eb2e8f9f7 5110 tmp_hal_status = ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 5111 }
<> 144:ef7eb2e8f9f7 5112 else
<> 144:ef7eb2e8f9f7 5113 {
<> 144:ef7eb2e8f9f7 5114 ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 5115 }
<> 144:ef7eb2e8f9f7 5116
<> 144:ef7eb2e8f9f7 5117 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 5118 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 5119 {
<> 144:ef7eb2e8f9f7 5120 /* Set ADC state */
<> 144:ef7eb2e8f9f7 5121 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 5122 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 144:ef7eb2e8f9f7 5123 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 5124 }
<> 144:ef7eb2e8f9f7 5125 }
<> 144:ef7eb2e8f9f7 5126 /* Conversion on ADC group regular group is stopped, but ADC is not */
<> 144:ef7eb2e8f9f7 5127 /* disabled since conversion on ADC group injected is still on going. */
<> 144:ef7eb2e8f9f7 5128 else
<> 144:ef7eb2e8f9f7 5129 {
<> 144:ef7eb2e8f9f7 5130 /* Set ADC state */
<> 144:ef7eb2e8f9f7 5131 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 5132 }
<> 144:ef7eb2e8f9f7 5133
<> 144:ef7eb2e8f9f7 5134 /* Process unlocked */
<> 144:ef7eb2e8f9f7 5135 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 5136
<> 144:ef7eb2e8f9f7 5137 /* Return function status */
<> 144:ef7eb2e8f9f7 5138 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 5139 }
<> 144:ef7eb2e8f9f7 5140
<> 144:ef7eb2e8f9f7 5141 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 5142 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 5143 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
<> 144:ef7eb2e8f9f7 5144 /**
<> 144:ef7eb2e8f9f7 5145 * @brief With ADC configured in multimode, for ADC master:
<> 144:ef7eb2e8f9f7 5146 * Stop ADC group regular conversion (potential conversion on going
<> 144:ef7eb2e8f9f7 5147 * on ADC group injected is not impacted),
<> 144:ef7eb2e8f9f7 5148 * disable ADC DMA transfer, disable ADC peripheral
<> 144:ef7eb2e8f9f7 5149 * if no conversion is on going on group injected.
<> 144:ef7eb2e8f9f7 5150 * Interruptions disabled in this function:
<> 144:ef7eb2e8f9f7 5151 * - DMA transfer complete
<> 144:ef7eb2e8f9f7 5152 * - DMA half transfer
<> 144:ef7eb2e8f9f7 5153 * - overrun
<> 144:ef7eb2e8f9f7 5154 * @note To stop ADC conversion of both groups regular and injected and to
<> 144:ef7eb2e8f9f7 5155 * to disable ADC peripheral, instead of using 2 functions
<> 144:ef7eb2e8f9f7 5156 * @ref HAL_ADCEx_RegularMultiModeStop_DMA() and
<> 144:ef7eb2e8f9f7 5157 * @ref HAL_ADCEx_InjectedStop(), use function
<> 144:ef7eb2e8f9f7 5158 * @ref HAL_ADCEx_MultiModeStop_DMA.
<> 144:ef7eb2e8f9f7 5159 * @note In case of auto-injection mode, this function also stop conversion
<> 144:ef7eb2e8f9f7 5160 * on ADC group injected.
<> 144:ef7eb2e8f9f7 5161 * @note Multimode is kept enabled after this function. To disable multimode
<> 144:ef7eb2e8f9f7 5162 * (set with HAL_ADCEx_MultiModeConfigChannel() ), ADC must be
<> 144:ef7eb2e8f9f7 5163 * reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit().
<> 144:ef7eb2e8f9f7 5164 * @note In case of DMA configured in circular mode, function
<> 144:ef7eb2e8f9f7 5165 * HAL_ADC_Stop_DMA must be called after this function with handle of
<> 144:ef7eb2e8f9f7 5166 * ADC slave, to properly disable the DMA channel of ADC slave.
<> 144:ef7eb2e8f9f7 5167 * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
<> 144:ef7eb2e8f9f7 5168 * @retval None
<> 144:ef7eb2e8f9f7 5169 */
<> 144:ef7eb2e8f9f7 5170 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 5171 {
<> 144:ef7eb2e8f9f7 5172 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 5173 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 5174 ADC_HandleTypeDef tmphadcSlave;
<> 144:ef7eb2e8f9f7 5175
<> 144:ef7eb2e8f9f7 5176 /* Check the parameters */
<> 144:ef7eb2e8f9f7 5177 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 5178
<> 144:ef7eb2e8f9f7 5179 /* Process locked */
<> 144:ef7eb2e8f9f7 5180 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 5181
<> 144:ef7eb2e8f9f7 5182 /* Stop potential ADC conversion on going and disable ADC peripheral */
<> 144:ef7eb2e8f9f7 5183 /* conditioned to: */
<> 144:ef7eb2e8f9f7 5184 /* - For ADC regular group conversion stop: */
<> 144:ef7eb2e8f9f7 5185 /* On this STM32 family, conversion on the other group */
<> 144:ef7eb2e8f9f7 5186 /* (group injected) can continue (groups regular and injected */
<> 144:ef7eb2e8f9f7 5187 /* conversion stop commands are independent) */
<> 144:ef7eb2e8f9f7 5188 /* - For ADC disable: */
<> 144:ef7eb2e8f9f7 5189 /* No conversion on the other group (group injected) must be intended to */
<> 144:ef7eb2e8f9f7 5190 /* continue (groups regular and injected are both impacted by */
<> 144:ef7eb2e8f9f7 5191 /* ADC disable) */
<> 144:ef7eb2e8f9f7 5192
<> 144:ef7eb2e8f9f7 5193 /* 1. Stop potential conversion on going, on regular group only */
<> 144:ef7eb2e8f9f7 5194 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
<> 144:ef7eb2e8f9f7 5195
<> 144:ef7eb2e8f9f7 5196 /* Disable ADC peripheral if conversion on ADC group regular is */
<> 144:ef7eb2e8f9f7 5197 /* effectively stopped and if no conversion on the other group */
<> 144:ef7eb2e8f9f7 5198 /* (ADC group injected) is intended to continue. */
<> 144:ef7eb2e8f9f7 5199 if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) &&
<> 144:ef7eb2e8f9f7 5200 ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET) )
<> 144:ef7eb2e8f9f7 5201 {
<> 144:ef7eb2e8f9f7 5202 /* Set a temporary handle of the ADC slave associated to the ADC master */
<> 144:ef7eb2e8f9f7 5203 /* (Depending on STM32F3 product, there may be up to 2 ADC slaves) */
<> 144:ef7eb2e8f9f7 5204 ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
<> 144:ef7eb2e8f9f7 5205
<> 144:ef7eb2e8f9f7 5206 if (tmphadcSlave.Instance == NULL)
<> 144:ef7eb2e8f9f7 5207 {
<> 144:ef7eb2e8f9f7 5208 /* Update ADC state machine (ADC master) to error */
<> 144:ef7eb2e8f9f7 5209 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
<> 144:ef7eb2e8f9f7 5210
<> 144:ef7eb2e8f9f7 5211 /* Process unlocked */
<> 144:ef7eb2e8f9f7 5212 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 5213
<> 144:ef7eb2e8f9f7 5214 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 5215 }
<> 144:ef7eb2e8f9f7 5216
<> 144:ef7eb2e8f9f7 5217 /* Procedure to disable the ADC peripheral: wait for conversions */
<> 144:ef7eb2e8f9f7 5218 /* effectively stopped (ADC master and ADC slave), then disable ADC */
<> 144:ef7eb2e8f9f7 5219
<> 144:ef7eb2e8f9f7 5220 /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/
<> 144:ef7eb2e8f9f7 5221 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 5222
<> 144:ef7eb2e8f9f7 5223 while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) ||
<> 144:ef7eb2e8f9f7 5224 ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) )
<> 144:ef7eb2e8f9f7 5225 {
<> 144:ef7eb2e8f9f7 5226 if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
<> 144:ef7eb2e8f9f7 5227 {
<> 144:ef7eb2e8f9f7 5228 /* Update ADC state machine (ADC master) to error */
<> 144:ef7eb2e8f9f7 5229 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 5230
<> 144:ef7eb2e8f9f7 5231 /* Process unlocked */
<> 144:ef7eb2e8f9f7 5232 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 5233
<> 144:ef7eb2e8f9f7 5234 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 5235 }
<> 144:ef7eb2e8f9f7 5236 }
<> 144:ef7eb2e8f9f7 5237
<> 144:ef7eb2e8f9f7 5238 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
<> 144:ef7eb2e8f9f7 5239 /* while DMA transfer is on going) */
<> 144:ef7eb2e8f9f7 5240 /* Note: In case of ADC slave using its own DMA channel (multimode */
<> 144:ef7eb2e8f9f7 5241 /* parameter "DMAAccessMode" set to disabled): */
<> 144:ef7eb2e8f9f7 5242 /* DMA channel of ADC slave should stopped after this function with */
<> 144:ef7eb2e8f9f7 5243 /* function HAL_ADC_Stop_DMA. */
<> 144:ef7eb2e8f9f7 5244 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
<> 144:ef7eb2e8f9f7 5245
<> 144:ef7eb2e8f9f7 5246 /* Check if DMA channel effectively disabled */
<> 144:ef7eb2e8f9f7 5247 if (tmp_hal_status != HAL_OK)
<> 144:ef7eb2e8f9f7 5248 {
<> 144:ef7eb2e8f9f7 5249 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 5250 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
<> 144:ef7eb2e8f9f7 5251 }
<> 144:ef7eb2e8f9f7 5252
<> 144:ef7eb2e8f9f7 5253 /* Disable ADC overrun interrupt */
<> 144:ef7eb2e8f9f7 5254 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
<> 144:ef7eb2e8f9f7 5255
<> 144:ef7eb2e8f9f7 5256
<> 144:ef7eb2e8f9f7 5257
<> 144:ef7eb2e8f9f7 5258 /* 2. Disable the ADC peripherals: master and slave */
<> 144:ef7eb2e8f9f7 5259 /* Update "tmp_hal_status" only if DMA channel disabling passed, */
<> 144:ef7eb2e8f9f7 5260 /* to retain a potential failing status. */
<> 144:ef7eb2e8f9f7 5261 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 5262 {
<> 144:ef7eb2e8f9f7 5263 /* Check if ADC are effectively disabled */
<> 144:ef7eb2e8f9f7 5264 if ((ADC_Disable(hadc) != HAL_ERROR) &&
<> 144:ef7eb2e8f9f7 5265 (ADC_Disable(&tmphadcSlave) != HAL_ERROR) )
<> 144:ef7eb2e8f9f7 5266 {
<> 144:ef7eb2e8f9f7 5267 tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 5268
<> 144:ef7eb2e8f9f7 5269 /* Change ADC state (ADC master) */
<> 144:ef7eb2e8f9f7 5270 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 5271 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 144:ef7eb2e8f9f7 5272 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 5273 }
<> 144:ef7eb2e8f9f7 5274 }
<> 144:ef7eb2e8f9f7 5275 else
<> 144:ef7eb2e8f9f7 5276 {
<> 144:ef7eb2e8f9f7 5277 /* In case of error, attempt to disable ADC instances anyway */
<> 144:ef7eb2e8f9f7 5278 ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 5279 ADC_Disable(&tmphadcSlave);
<> 144:ef7eb2e8f9f7 5280
<> 144:ef7eb2e8f9f7 5281 /* Update ADC state machine (ADC master) to error */
<> 144:ef7eb2e8f9f7 5282 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 5283 }
<> 144:ef7eb2e8f9f7 5284
<> 144:ef7eb2e8f9f7 5285 }
<> 144:ef7eb2e8f9f7 5286 /* Conversion on ADC group regular group is stopped, but ADC is not */
<> 144:ef7eb2e8f9f7 5287 /* disabled since conversion on ADC group injected is still on going. */
<> 144:ef7eb2e8f9f7 5288 else
<> 144:ef7eb2e8f9f7 5289 {
<> 144:ef7eb2e8f9f7 5290 /* Set ADC state */
<> 144:ef7eb2e8f9f7 5291 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 5292 }
<> 144:ef7eb2e8f9f7 5293
<> 144:ef7eb2e8f9f7 5294 /* Process unlocked */
<> 144:ef7eb2e8f9f7 5295 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 5296
<> 144:ef7eb2e8f9f7 5297 /* Return function status */
<> 144:ef7eb2e8f9f7 5298 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 5299 }
<> 144:ef7eb2e8f9f7 5300 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 5301 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 5302 /* STM32F303x8 || STM32F334x8 || STM32F328xx */
<> 144:ef7eb2e8f9f7 5303
<> 144:ef7eb2e8f9f7 5304
<> 144:ef7eb2e8f9f7 5305 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 5306 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 5307 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 5308 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 5309
<> 144:ef7eb2e8f9f7 5310 /**
<> 144:ef7eb2e8f9f7 5311 * @brief Injected conversion complete callback in non blocking mode
<> 144:ef7eb2e8f9f7 5312 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 5313 * @retval None
<> 144:ef7eb2e8f9f7 5314 */
<> 144:ef7eb2e8f9f7 5315 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 5316 {
<> 144:ef7eb2e8f9f7 5317 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 5318 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 5319
<> 144:ef7eb2e8f9f7 5320 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 5321 the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 5322 */
<> 144:ef7eb2e8f9f7 5323 }
<> 144:ef7eb2e8f9f7 5324
<> 144:ef7eb2e8f9f7 5325 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 5326 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 5327 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 5328 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 5329 /**
<> 144:ef7eb2e8f9f7 5330 * @brief Injected context queue overflow flag callback.
<> 144:ef7eb2e8f9f7 5331 * @note This callback is called if injected context queue is enabled
<> 144:ef7eb2e8f9f7 5332 (parameter "QueueInjectedContext" in injected channel configuration)
<> 144:ef7eb2e8f9f7 5333 and if a new injected context is set when queue is full (maximum 2
<> 144:ef7eb2e8f9f7 5334 contexts).
<> 144:ef7eb2e8f9f7 5335 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 5336 * @retval None
<> 144:ef7eb2e8f9f7 5337 */
<> 144:ef7eb2e8f9f7 5338 __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 5339 {
<> 144:ef7eb2e8f9f7 5340 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 5341 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 5342
<> 144:ef7eb2e8f9f7 5343 /* NOTE : This function should not be modified. When the callback is needed,
<> 144:ef7eb2e8f9f7 5344 function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented
<> 144:ef7eb2e8f9f7 5345 in the user file.
<> 144:ef7eb2e8f9f7 5346 */
<> 144:ef7eb2e8f9f7 5347 }
<> 144:ef7eb2e8f9f7 5348
<> 144:ef7eb2e8f9f7 5349 /**
<> 144:ef7eb2e8f9f7 5350 * @brief Analog watchdog 2 callback in non blocking mode.
<> 144:ef7eb2e8f9f7 5351 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 5352 * @retval None
<> 144:ef7eb2e8f9f7 5353 */
<> 144:ef7eb2e8f9f7 5354 __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 5355 {
<> 144:ef7eb2e8f9f7 5356 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 5357 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 5358
<> 144:ef7eb2e8f9f7 5359 /* NOTE : This function should not be modified. When the callback is needed,
<> 144:ef7eb2e8f9f7 5360 function HAL_ADC_LevelOoutOfWindow2Callback must be implemented in the user file.
<> 144:ef7eb2e8f9f7 5361 */
<> 144:ef7eb2e8f9f7 5362 }
<> 144:ef7eb2e8f9f7 5363
<> 144:ef7eb2e8f9f7 5364 /**
<> 144:ef7eb2e8f9f7 5365 * @brief Analog watchdog 3 callback in non blocking mode.
<> 144:ef7eb2e8f9f7 5366 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 5367 * @retval None
<> 144:ef7eb2e8f9f7 5368 */
<> 144:ef7eb2e8f9f7 5369 __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 5370 {
<> 144:ef7eb2e8f9f7 5371 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 5372 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 5373
<> 144:ef7eb2e8f9f7 5374 /* NOTE : This function should not be modified. When the callback is needed,
<> 144:ef7eb2e8f9f7 5375 function HAL_ADC_LevelOoutOfWindow3Callback must be implemented in the user file.
<> 144:ef7eb2e8f9f7 5376 */
<> 144:ef7eb2e8f9f7 5377 }
<> 144:ef7eb2e8f9f7 5378 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 5379 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 5380 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 5381 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 5382
<> 144:ef7eb2e8f9f7 5383 /**
<> 144:ef7eb2e8f9f7 5384 * @}
<> 144:ef7eb2e8f9f7 5385 */
<> 144:ef7eb2e8f9f7 5386
<> 144:ef7eb2e8f9f7 5387 /** @defgroup ADCEx_Exported_Functions_Group3 ADCEx Peripheral Control functions
<> 144:ef7eb2e8f9f7 5388 * @brief ADC Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 5389 *
<> 144:ef7eb2e8f9f7 5390 @verbatim
<> 144:ef7eb2e8f9f7 5391 ===============================================================================
<> 144:ef7eb2e8f9f7 5392 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 5393 ===============================================================================
<> 144:ef7eb2e8f9f7 5394 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 5395 (+) Configure channels on regular group
<> 144:ef7eb2e8f9f7 5396 (+) Configure channels on injected group
<> 144:ef7eb2e8f9f7 5397 (+) Configure multimode
<> 144:ef7eb2e8f9f7 5398 (+) Configure the analog watchdog
<> 144:ef7eb2e8f9f7 5399
<> 144:ef7eb2e8f9f7 5400 @endverbatim
<> 144:ef7eb2e8f9f7 5401 * @{
<> 144:ef7eb2e8f9f7 5402 */
<> 144:ef7eb2e8f9f7 5403
<> 144:ef7eb2e8f9f7 5404
<> 144:ef7eb2e8f9f7 5405 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 5406 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 5407 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 5408 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 5409 /**
<> 144:ef7eb2e8f9f7 5410 * @brief Configures the the selected channel to be linked to the regular
<> 144:ef7eb2e8f9f7 5411 * group.
<> 144:ef7eb2e8f9f7 5412 * @note In case of usage of internal measurement channels:
<> 144:ef7eb2e8f9f7 5413 * Vbat/VrefInt/TempSensor.
<> 144:ef7eb2e8f9f7 5414 * The recommended sampling time is at least:
<> 144:ef7eb2e8f9f7 5415 * - For devices STM32F37x: 17.1us for temperature sensor
<> 144:ef7eb2e8f9f7 5416 * - For the other STM32F3 devices: 2.2us for each of channels
<> 144:ef7eb2e8f9f7 5417 * Vbat/VrefInt/TempSensor.
<> 144:ef7eb2e8f9f7 5418 * These internal paths can be be disabled using function
<> 144:ef7eb2e8f9f7 5419 * HAL_ADC_DeInit().
<> 144:ef7eb2e8f9f7 5420 * @note Possibility to update parameters on the fly:
<> 144:ef7eb2e8f9f7 5421 * This function initializes channel into regular group, following
<> 144:ef7eb2e8f9f7 5422 * calls to this function can be used to reconfigure some parameters
<> 144:ef7eb2e8f9f7 5423 * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
<> 144:ef7eb2e8f9f7 5424 * the ADC.
<> 144:ef7eb2e8f9f7 5425 * The setting of these parameters is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 5426 * For parameters constraints, see comments of structure
<> 144:ef7eb2e8f9f7 5427 * "ADC_ChannelConfTypeDef".
<> 144:ef7eb2e8f9f7 5428 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 5429 * @param sConfig: Structure ADC channel for regular group.
<> 144:ef7eb2e8f9f7 5430 * @retval HAL status
<> 144:ef7eb2e8f9f7 5431 */
<> 144:ef7eb2e8f9f7 5432 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
<> 144:ef7eb2e8f9f7 5433 {
<> 144:ef7eb2e8f9f7 5434 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 5435 ADC_Common_TypeDef *tmpADC_Common;
<> 144:ef7eb2e8f9f7 5436 ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
<> 144:ef7eb2e8f9f7 5437 uint32_t tmpOffsetShifted;
<> 144:ef7eb2e8f9f7 5438 __IO uint32_t wait_loop_index = 0;
<> 144:ef7eb2e8f9f7 5439
<> 144:ef7eb2e8f9f7 5440 /* Check the parameters */
<> 144:ef7eb2e8f9f7 5441 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 5442 assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
<> 144:ef7eb2e8f9f7 5443 assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
<> 144:ef7eb2e8f9f7 5444 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
<> 144:ef7eb2e8f9f7 5445 assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
<> 144:ef7eb2e8f9f7 5446 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
<> 144:ef7eb2e8f9f7 5447
<> 144:ef7eb2e8f9f7 5448
<> 144:ef7eb2e8f9f7 5449 /* Verification of channel number: Channels 1 to 14 are available in */
<> 144:ef7eb2e8f9f7 5450 /* differential mode. Channels 15, 16, 17, 18 can be used only in */
<> 144:ef7eb2e8f9f7 5451 /* single-ended mode. */
<> 144:ef7eb2e8f9f7 5452 if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
<> 144:ef7eb2e8f9f7 5453 {
<> 144:ef7eb2e8f9f7 5454 assert_param(IS_ADC_CHANNEL(sConfig->Channel));
<> 144:ef7eb2e8f9f7 5455 }
<> 144:ef7eb2e8f9f7 5456 else
<> 144:ef7eb2e8f9f7 5457 {
<> 144:ef7eb2e8f9f7 5458 assert_param(IS_ADC_DIFF_CHANNEL(sConfig->Channel));
<> 144:ef7eb2e8f9f7 5459 }
<> 144:ef7eb2e8f9f7 5460
<> 144:ef7eb2e8f9f7 5461 /* Process locked */
<> 144:ef7eb2e8f9f7 5462 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 5463
<> 144:ef7eb2e8f9f7 5464
<> 144:ef7eb2e8f9f7 5465 /* Parameters update conditioned to ADC state: */
<> 144:ef7eb2e8f9f7 5466 /* Parameters that can be updated when ADC is disabled or enabled without */
<> 144:ef7eb2e8f9f7 5467 /* conversion on going on regular group: */
<> 144:ef7eb2e8f9f7 5468 /* - Channel number */
<> 144:ef7eb2e8f9f7 5469 /* - Channel rank */
<> 144:ef7eb2e8f9f7 5470 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<> 144:ef7eb2e8f9f7 5471 {
<> 144:ef7eb2e8f9f7 5472 /* Regular sequence configuration */
<> 144:ef7eb2e8f9f7 5473 /* For Rank 1 to 4 */
<> 144:ef7eb2e8f9f7 5474 if (sConfig->Rank < 5)
<> 144:ef7eb2e8f9f7 5475 {
<> 144:ef7eb2e8f9f7 5476 MODIFY_REG(hadc->Instance->SQR1,
<> 144:ef7eb2e8f9f7 5477 ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank) ,
<> 144:ef7eb2e8f9f7 5478 ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
<> 144:ef7eb2e8f9f7 5479 }
<> 144:ef7eb2e8f9f7 5480 /* For Rank 5 to 9 */
<> 144:ef7eb2e8f9f7 5481 else if (sConfig->Rank < 10)
<> 144:ef7eb2e8f9f7 5482 {
<> 144:ef7eb2e8f9f7 5483 MODIFY_REG(hadc->Instance->SQR2,
<> 144:ef7eb2e8f9f7 5484 ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank) ,
<> 144:ef7eb2e8f9f7 5485 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
<> 144:ef7eb2e8f9f7 5486 }
<> 144:ef7eb2e8f9f7 5487 /* For Rank 10 to 14 */
<> 144:ef7eb2e8f9f7 5488 else if (sConfig->Rank < 15)
<> 144:ef7eb2e8f9f7 5489 {
<> 144:ef7eb2e8f9f7 5490 MODIFY_REG(hadc->Instance->SQR3 ,
<> 144:ef7eb2e8f9f7 5491 ADC_SQR3_RK(ADC_SQR3_SQ10, sConfig->Rank) ,
<> 144:ef7eb2e8f9f7 5492 ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
<> 144:ef7eb2e8f9f7 5493 }
<> 144:ef7eb2e8f9f7 5494 /* For Rank 15 to 16 */
<> 144:ef7eb2e8f9f7 5495 else
<> 144:ef7eb2e8f9f7 5496 {
<> 144:ef7eb2e8f9f7 5497 MODIFY_REG(hadc->Instance->SQR4 ,
<> 144:ef7eb2e8f9f7 5498 ADC_SQR4_RK(ADC_SQR4_SQ15, sConfig->Rank) ,
<> 144:ef7eb2e8f9f7 5499 ADC_SQR4_RK(sConfig->Channel, sConfig->Rank) );
<> 144:ef7eb2e8f9f7 5500 }
<> 144:ef7eb2e8f9f7 5501
<> 144:ef7eb2e8f9f7 5502
<> 144:ef7eb2e8f9f7 5503 /* Parameters update conditioned to ADC state: */
<> 144:ef7eb2e8f9f7 5504 /* Parameters that can be updated when ADC is disabled or enabled without */
<> 144:ef7eb2e8f9f7 5505 /* conversion on going on regular group: */
<> 144:ef7eb2e8f9f7 5506 /* - Channel sampling time */
<> 144:ef7eb2e8f9f7 5507 /* - Channel offset */
<> 144:ef7eb2e8f9f7 5508 if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
<> 144:ef7eb2e8f9f7 5509 {
<> 144:ef7eb2e8f9f7 5510 /* Channel sampling time configuration */
<> 144:ef7eb2e8f9f7 5511 /* For channels 10 to 18 */
<> 144:ef7eb2e8f9f7 5512 if (sConfig->Channel >= ADC_CHANNEL_10)
<> 144:ef7eb2e8f9f7 5513 {
<> 144:ef7eb2e8f9f7 5514 MODIFY_REG(hadc->Instance->SMPR2 ,
<> 144:ef7eb2e8f9f7 5515 ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel) ,
<> 144:ef7eb2e8f9f7 5516 ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
<> 144:ef7eb2e8f9f7 5517 }
<> 144:ef7eb2e8f9f7 5518 else /* For channels 1 to 9 */
<> 144:ef7eb2e8f9f7 5519 {
<> 144:ef7eb2e8f9f7 5520 MODIFY_REG(hadc->Instance->SMPR1 ,
<> 144:ef7eb2e8f9f7 5521 ADC_SMPR1(ADC_SMPR1_SMP0, sConfig->Channel) ,
<> 144:ef7eb2e8f9f7 5522 ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
<> 144:ef7eb2e8f9f7 5523 }
<> 144:ef7eb2e8f9f7 5524
<> 144:ef7eb2e8f9f7 5525
<> 144:ef7eb2e8f9f7 5526 /* Configure the offset: offset enable/disable, channel, offset value */
<> 144:ef7eb2e8f9f7 5527
<> 144:ef7eb2e8f9f7 5528 /* Shift the offset in function of the selected ADC resolution. */
<> 144:ef7eb2e8f9f7 5529 /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set */
<> 144:ef7eb2e8f9f7 5530 /* to 0. */
<> 144:ef7eb2e8f9f7 5531 tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset);
<> 144:ef7eb2e8f9f7 5532
<> 144:ef7eb2e8f9f7 5533 /* Configure the selected offset register: */
<> 144:ef7eb2e8f9f7 5534 /* - Enable offset */
<> 144:ef7eb2e8f9f7 5535 /* - Set channel number */
<> 144:ef7eb2e8f9f7 5536 /* - Set offset value */
<> 144:ef7eb2e8f9f7 5537 switch (sConfig->OffsetNumber)
<> 144:ef7eb2e8f9f7 5538 {
<> 144:ef7eb2e8f9f7 5539 case ADC_OFFSET_1:
<> 144:ef7eb2e8f9f7 5540 /* Configure offset register 1 */
<> 144:ef7eb2e8f9f7 5541 MODIFY_REG(hadc->Instance->OFR1 ,
<> 144:ef7eb2e8f9f7 5542 ADC_OFR1_OFFSET1_CH |
<> 144:ef7eb2e8f9f7 5543 ADC_OFR1_OFFSET1 ,
<> 144:ef7eb2e8f9f7 5544 ADC_OFR1_OFFSET1_EN |
<> 144:ef7eb2e8f9f7 5545 ADC_OFR_CHANNEL(sConfig->Channel) |
<> 144:ef7eb2e8f9f7 5546 tmpOffsetShifted );
<> 144:ef7eb2e8f9f7 5547 break;
<> 144:ef7eb2e8f9f7 5548
<> 144:ef7eb2e8f9f7 5549 case ADC_OFFSET_2:
<> 144:ef7eb2e8f9f7 5550 /* Configure offset register 2 */
<> 144:ef7eb2e8f9f7 5551 MODIFY_REG(hadc->Instance->OFR2 ,
<> 144:ef7eb2e8f9f7 5552 ADC_OFR2_OFFSET2_CH |
<> 144:ef7eb2e8f9f7 5553 ADC_OFR2_OFFSET2 ,
<> 144:ef7eb2e8f9f7 5554 ADC_OFR2_OFFSET2_EN |
<> 144:ef7eb2e8f9f7 5555 ADC_OFR_CHANNEL(sConfig->Channel) |
<> 144:ef7eb2e8f9f7 5556 tmpOffsetShifted );
<> 144:ef7eb2e8f9f7 5557 break;
<> 144:ef7eb2e8f9f7 5558
<> 144:ef7eb2e8f9f7 5559 case ADC_OFFSET_3:
<> 144:ef7eb2e8f9f7 5560 /* Configure offset register 3 */
<> 144:ef7eb2e8f9f7 5561 MODIFY_REG(hadc->Instance->OFR3 ,
<> 144:ef7eb2e8f9f7 5562 ADC_OFR3_OFFSET3_CH |
<> 144:ef7eb2e8f9f7 5563 ADC_OFR3_OFFSET3 ,
<> 144:ef7eb2e8f9f7 5564 ADC_OFR3_OFFSET3_EN |
<> 144:ef7eb2e8f9f7 5565 ADC_OFR_CHANNEL(sConfig->Channel) |
<> 144:ef7eb2e8f9f7 5566 tmpOffsetShifted );
<> 144:ef7eb2e8f9f7 5567 break;
<> 144:ef7eb2e8f9f7 5568
<> 144:ef7eb2e8f9f7 5569 case ADC_OFFSET_4:
<> 144:ef7eb2e8f9f7 5570 /* Configure offset register 4 */
<> 144:ef7eb2e8f9f7 5571 MODIFY_REG(hadc->Instance->OFR4 ,
<> 144:ef7eb2e8f9f7 5572 ADC_OFR4_OFFSET4_CH |
<> 144:ef7eb2e8f9f7 5573 ADC_OFR4_OFFSET4 ,
<> 144:ef7eb2e8f9f7 5574 ADC_OFR4_OFFSET4_EN |
<> 144:ef7eb2e8f9f7 5575 ADC_OFR_CHANNEL(sConfig->Channel) |
<> 144:ef7eb2e8f9f7 5576 tmpOffsetShifted );
<> 144:ef7eb2e8f9f7 5577 break;
<> 144:ef7eb2e8f9f7 5578
<> 144:ef7eb2e8f9f7 5579 /* Case ADC_OFFSET_NONE */
<> 144:ef7eb2e8f9f7 5580 default :
<> 144:ef7eb2e8f9f7 5581 /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is */
<> 144:ef7eb2e8f9f7 5582 /* enabled. If this is the case, offset OFRx is disabled. */
<> 144:ef7eb2e8f9f7 5583 if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
<> 144:ef7eb2e8f9f7 5584 {
<> 144:ef7eb2e8f9f7 5585 /* Disable offset OFR1*/
<> 144:ef7eb2e8f9f7 5586 CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
<> 144:ef7eb2e8f9f7 5587 }
<> 144:ef7eb2e8f9f7 5588 if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
<> 144:ef7eb2e8f9f7 5589 {
<> 144:ef7eb2e8f9f7 5590 /* Disable offset OFR2*/
<> 144:ef7eb2e8f9f7 5591 CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN);
<> 144:ef7eb2e8f9f7 5592 }
<> 144:ef7eb2e8f9f7 5593 if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
<> 144:ef7eb2e8f9f7 5594 {
<> 144:ef7eb2e8f9f7 5595 /* Disable offset OFR3*/
<> 144:ef7eb2e8f9f7 5596 CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN);
<> 144:ef7eb2e8f9f7 5597 }
<> 144:ef7eb2e8f9f7 5598 if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
<> 144:ef7eb2e8f9f7 5599 {
<> 144:ef7eb2e8f9f7 5600 /* Disable offset OFR4*/
<> 144:ef7eb2e8f9f7 5601 CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN);
<> 144:ef7eb2e8f9f7 5602 }
<> 144:ef7eb2e8f9f7 5603 break;
<> 144:ef7eb2e8f9f7 5604 }
<> 144:ef7eb2e8f9f7 5605
<> 144:ef7eb2e8f9f7 5606 }
<> 144:ef7eb2e8f9f7 5607
<> 144:ef7eb2e8f9f7 5608
<> 144:ef7eb2e8f9f7 5609 /* Parameters update conditioned to ADC state: */
<> 144:ef7eb2e8f9f7 5610 /* Parameters that can be updated only when ADC is disabled: */
<> 144:ef7eb2e8f9f7 5611 /* - Single or differential mode */
<> 144:ef7eb2e8f9f7 5612 /* - Internal measurement channels: Vbat/VrefInt/TempSensor */
<> 144:ef7eb2e8f9f7 5613 if (ADC_IS_ENABLE(hadc) == RESET)
<> 144:ef7eb2e8f9f7 5614 {
<> 144:ef7eb2e8f9f7 5615 /* Configuration of differential mode */
<> 144:ef7eb2e8f9f7 5616 if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
<> 144:ef7eb2e8f9f7 5617 {
<> 144:ef7eb2e8f9f7 5618 /* Disable differential mode (default mode: single-ended) */
<> 144:ef7eb2e8f9f7 5619 CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
<> 144:ef7eb2e8f9f7 5620 }
<> 144:ef7eb2e8f9f7 5621 else
<> 144:ef7eb2e8f9f7 5622 {
<> 144:ef7eb2e8f9f7 5623 /* Enable differential mode */
<> 144:ef7eb2e8f9f7 5624 SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
<> 144:ef7eb2e8f9f7 5625
<> 144:ef7eb2e8f9f7 5626 /* Channel sampling time configuration (channel ADC_INx +1 */
<> 144:ef7eb2e8f9f7 5627 /* corresponding to differential negative input). */
<> 144:ef7eb2e8f9f7 5628 /* For channels 10 to 18 */
<> 144:ef7eb2e8f9f7 5629 if (sConfig->Channel >= ADC_CHANNEL_10)
<> 144:ef7eb2e8f9f7 5630 {
<> 144:ef7eb2e8f9f7 5631 MODIFY_REG(hadc->Instance->SMPR2,
<> 144:ef7eb2e8f9f7 5632 ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel +1) ,
<> 144:ef7eb2e8f9f7 5633 ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel +1) );
<> 144:ef7eb2e8f9f7 5634 }
<> 144:ef7eb2e8f9f7 5635 else /* For channels 1 to 9 */
<> 144:ef7eb2e8f9f7 5636 {
<> 144:ef7eb2e8f9f7 5637 MODIFY_REG(hadc->Instance->SMPR1,
<> 144:ef7eb2e8f9f7 5638 ADC_SMPR1(ADC_SMPR1_SMP0, sConfig->Channel +1) ,
<> 144:ef7eb2e8f9f7 5639 ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel +1) );
<> 144:ef7eb2e8f9f7 5640 }
<> 144:ef7eb2e8f9f7 5641 }
<> 144:ef7eb2e8f9f7 5642
<> 144:ef7eb2e8f9f7 5643
<> 144:ef7eb2e8f9f7 5644 /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
<> 144:ef7eb2e8f9f7 5645 /* internal measurement paths enable: If internal channel selected, */
<> 144:ef7eb2e8f9f7 5646 /* enable dedicated internal buffers and path. */
<> 144:ef7eb2e8f9f7 5647 /* Note: these internal measurement paths can be disabled using */
<> 144:ef7eb2e8f9f7 5648 /* HAL_ADC_DeInit(). */
<> 144:ef7eb2e8f9f7 5649
<> 144:ef7eb2e8f9f7 5650 /* Configuration of common ADC parameters */
<> 144:ef7eb2e8f9f7 5651 /* Pointer to the common control register to which is belonging hadc */
<> 144:ef7eb2e8f9f7 5652 /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
<> 144:ef7eb2e8f9f7 5653 /* control registers) */
<> 144:ef7eb2e8f9f7 5654 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
<> 144:ef7eb2e8f9f7 5655
<> 144:ef7eb2e8f9f7 5656 /* If the requested internal measurement path has already been enabled, */
<> 144:ef7eb2e8f9f7 5657 /* bypass the configuration processing. */
<> 144:ef7eb2e8f9f7 5658 if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
<> 144:ef7eb2e8f9f7 5659 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) ||
<> 144:ef7eb2e8f9f7 5660 ( (sConfig->Channel == ADC_CHANNEL_VBAT) &&
<> 144:ef7eb2e8f9f7 5661 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) ||
<> 144:ef7eb2e8f9f7 5662 ( (sConfig->Channel == ADC_CHANNEL_VREFINT) &&
<> 144:ef7eb2e8f9f7 5663 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
<> 144:ef7eb2e8f9f7 5664 )
<> 144:ef7eb2e8f9f7 5665 {
<> 144:ef7eb2e8f9f7 5666 /* Configuration of common ADC parameters (continuation) */
<> 144:ef7eb2e8f9f7 5667 /* Set handle of the other ADC sharing the same common register */
<> 144:ef7eb2e8f9f7 5668 ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
<> 144:ef7eb2e8f9f7 5669
<> 144:ef7eb2e8f9f7 5670 /* Software is allowed to change common parameters only when all ADCs */
<> 144:ef7eb2e8f9f7 5671 /* of the common group are disabled. */
<> 144:ef7eb2e8f9f7 5672 if ((ADC_IS_ENABLE(hadc) == RESET) &&
<> 144:ef7eb2e8f9f7 5673 ( (tmphadcSharingSameCommonRegister.Instance == NULL) ||
<> 144:ef7eb2e8f9f7 5674 (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) )
<> 144:ef7eb2e8f9f7 5675 {
<> 144:ef7eb2e8f9f7 5676 /* If Channel_16 is selected, enable Temp. sensor measurement path */
<> 144:ef7eb2e8f9f7 5677 /* Note: Temp. sensor internal channels available on ADC1 only */
<> 144:ef7eb2e8f9f7 5678 if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1))
<> 144:ef7eb2e8f9f7 5679 {
<> 144:ef7eb2e8f9f7 5680 SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
<> 144:ef7eb2e8f9f7 5681
<> 144:ef7eb2e8f9f7 5682 /* Delay for temperature sensor stabilization time */
<> 144:ef7eb2e8f9f7 5683 /* Compute number of CPU cycles to wait for */
<> 144:ef7eb2e8f9f7 5684 wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
<> 144:ef7eb2e8f9f7 5685 while(wait_loop_index != 0)
<> 144:ef7eb2e8f9f7 5686 {
<> 144:ef7eb2e8f9f7 5687 wait_loop_index--;
<> 144:ef7eb2e8f9f7 5688 }
<> 144:ef7eb2e8f9f7 5689 }
<> 144:ef7eb2e8f9f7 5690 /* If Channel_17 is selected, enable VBAT measurement path */
<> 144:ef7eb2e8f9f7 5691 /* Note: VBAT internal channels available on ADC1 only */
<> 144:ef7eb2e8f9f7 5692 else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && (hadc->Instance == ADC1))
<> 144:ef7eb2e8f9f7 5693 {
<> 144:ef7eb2e8f9f7 5694 SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
<> 144:ef7eb2e8f9f7 5695 }
<> 144:ef7eb2e8f9f7 5696 /* If Channel_18 is selected, enable VREFINT measurement path */
<> 144:ef7eb2e8f9f7 5697 /* Note: VrefInt internal channels available on all ADCs, but only */
<> 144:ef7eb2e8f9f7 5698 /* one ADC is allowed to be connected to VrefInt at the same */
<> 144:ef7eb2e8f9f7 5699 /* time. */
<> 144:ef7eb2e8f9f7 5700 else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
<> 144:ef7eb2e8f9f7 5701 {
<> 144:ef7eb2e8f9f7 5702 SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
<> 144:ef7eb2e8f9f7 5703 }
<> 144:ef7eb2e8f9f7 5704 }
<> 144:ef7eb2e8f9f7 5705 /* If the requested internal measurement path has already been */
<> 144:ef7eb2e8f9f7 5706 /* enabled and other ADC of the common group are enabled, internal */
<> 144:ef7eb2e8f9f7 5707 /* measurement paths cannot be enabled. */
<> 144:ef7eb2e8f9f7 5708 else
<> 144:ef7eb2e8f9f7 5709 {
<> 144:ef7eb2e8f9f7 5710 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 5711 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 5712
<> 144:ef7eb2e8f9f7 5713 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 5714 }
<> 144:ef7eb2e8f9f7 5715 }
<> 144:ef7eb2e8f9f7 5716
<> 144:ef7eb2e8f9f7 5717 }
<> 144:ef7eb2e8f9f7 5718
<> 144:ef7eb2e8f9f7 5719 }
<> 144:ef7eb2e8f9f7 5720 /* If a conversion is on going on regular group, no update on regular */
<> 144:ef7eb2e8f9f7 5721 /* channel could be done on neither of the channel configuration structure */
<> 144:ef7eb2e8f9f7 5722 /* parameters. */
<> 144:ef7eb2e8f9f7 5723 else
<> 144:ef7eb2e8f9f7 5724 {
<> 144:ef7eb2e8f9f7 5725 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 5726 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 5727
<> 144:ef7eb2e8f9f7 5728 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 5729 }
<> 144:ef7eb2e8f9f7 5730
<> 144:ef7eb2e8f9f7 5731 /* Process unlocked */
<> 144:ef7eb2e8f9f7 5732 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 5733
<> 144:ef7eb2e8f9f7 5734 /* Return function status */
<> 144:ef7eb2e8f9f7 5735 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 5736 }
<> 144:ef7eb2e8f9f7 5737 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 5738 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 5739 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 5740 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 5741
<> 144:ef7eb2e8f9f7 5742 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 5743 /**
<> 144:ef7eb2e8f9f7 5744 * @brief Configures the the selected channel to be linked to the regular
<> 144:ef7eb2e8f9f7 5745 * group.
<> 144:ef7eb2e8f9f7 5746 * @note In case of usage of internal measurement channels:
<> 144:ef7eb2e8f9f7 5747 * Vbat/VrefInt/TempSensor.
<> 144:ef7eb2e8f9f7 5748 * The recommended sampling time is at least:
<> 144:ef7eb2e8f9f7 5749 * - For devices STM32F37x: 17.1us for temperature sensor
<> 144:ef7eb2e8f9f7 5750 * - For the other STM32F3 devices: 2.2us for each of channels
<> 144:ef7eb2e8f9f7 5751 * Vbat/VrefInt/TempSensor.
<> 144:ef7eb2e8f9f7 5752 * These internal paths can be be disabled using function
<> 144:ef7eb2e8f9f7 5753 * HAL_ADC_DeInit().
<> 144:ef7eb2e8f9f7 5754 * @note Possibility to update parameters on the fly:
<> 144:ef7eb2e8f9f7 5755 * This function initializes channel into regular group, following
<> 144:ef7eb2e8f9f7 5756 * calls to this function can be used to reconfigure some parameters
<> 144:ef7eb2e8f9f7 5757 * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
<> 144:ef7eb2e8f9f7 5758 * the ADC.
<> 144:ef7eb2e8f9f7 5759 * The setting of these parameters is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 5760 * For parameters constraints, see comments of structure
<> 144:ef7eb2e8f9f7 5761 * "ADC_ChannelConfTypeDef".
<> 144:ef7eb2e8f9f7 5762 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 5763 * @param sConfig: Structure of ADC channel for regular group.
<> 144:ef7eb2e8f9f7 5764 * @retval HAL status
<> 144:ef7eb2e8f9f7 5765 */
<> 144:ef7eb2e8f9f7 5766 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
<> 144:ef7eb2e8f9f7 5767 {
<> 144:ef7eb2e8f9f7 5768 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 5769 __IO uint32_t wait_loop_index = 0;
<> 144:ef7eb2e8f9f7 5770
<> 144:ef7eb2e8f9f7 5771 /* Check the parameters */
<> 144:ef7eb2e8f9f7 5772 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 5773 assert_param(IS_ADC_CHANNEL(sConfig->Channel));
<> 144:ef7eb2e8f9f7 5774 assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
<> 144:ef7eb2e8f9f7 5775 assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
<> 144:ef7eb2e8f9f7 5776
<> 144:ef7eb2e8f9f7 5777 /* Process locked */
<> 144:ef7eb2e8f9f7 5778 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 5779
<> 144:ef7eb2e8f9f7 5780
<> 144:ef7eb2e8f9f7 5781 /* Regular sequence configuration */
<> 144:ef7eb2e8f9f7 5782 /* For Rank 1 to 6 */
<> 144:ef7eb2e8f9f7 5783 if (sConfig->Rank < 7)
<> 144:ef7eb2e8f9f7 5784 {
<> 144:ef7eb2e8f9f7 5785 MODIFY_REG(hadc->Instance->SQR3 ,
<> 144:ef7eb2e8f9f7 5786 ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) ,
<> 144:ef7eb2e8f9f7 5787 ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
<> 144:ef7eb2e8f9f7 5788 }
<> 144:ef7eb2e8f9f7 5789 /* For Rank 7 to 12 */
<> 144:ef7eb2e8f9f7 5790 else if (sConfig->Rank < 13)
<> 144:ef7eb2e8f9f7 5791 {
<> 144:ef7eb2e8f9f7 5792 MODIFY_REG(hadc->Instance->SQR2 ,
<> 144:ef7eb2e8f9f7 5793 ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank) ,
<> 144:ef7eb2e8f9f7 5794 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
<> 144:ef7eb2e8f9f7 5795 }
<> 144:ef7eb2e8f9f7 5796 /* For Rank 13 to 16 */
<> 144:ef7eb2e8f9f7 5797 else
<> 144:ef7eb2e8f9f7 5798 {
<> 144:ef7eb2e8f9f7 5799 MODIFY_REG(hadc->Instance->SQR1 ,
<> 144:ef7eb2e8f9f7 5800 ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank) ,
<> 144:ef7eb2e8f9f7 5801 ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
<> 144:ef7eb2e8f9f7 5802 }
<> 144:ef7eb2e8f9f7 5803
<> 144:ef7eb2e8f9f7 5804
<> 144:ef7eb2e8f9f7 5805 /* Channel sampling time configuration */
<> 144:ef7eb2e8f9f7 5806 /* For channels 10 to 18 */
<> 144:ef7eb2e8f9f7 5807 if (sConfig->Channel > ADC_CHANNEL_10)
<> 144:ef7eb2e8f9f7 5808 {
<> 144:ef7eb2e8f9f7 5809 MODIFY_REG(hadc->Instance->SMPR1 ,
<> 144:ef7eb2e8f9f7 5810 ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) ,
<> 144:ef7eb2e8f9f7 5811 ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
<> 144:ef7eb2e8f9f7 5812 }
<> 144:ef7eb2e8f9f7 5813 else /* For channels 0 to 9 */
<> 144:ef7eb2e8f9f7 5814 {
<> 144:ef7eb2e8f9f7 5815 MODIFY_REG(hadc->Instance->SMPR2 ,
<> 144:ef7eb2e8f9f7 5816 ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel) ,
<> 144:ef7eb2e8f9f7 5817 ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
<> 144:ef7eb2e8f9f7 5818 }
<> 144:ef7eb2e8f9f7 5819
<> 144:ef7eb2e8f9f7 5820 /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
<> 144:ef7eb2e8f9f7 5821 /* and VREFINT measurement path. */
<> 144:ef7eb2e8f9f7 5822 if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
<> 144:ef7eb2e8f9f7 5823 (sConfig->Channel == ADC_CHANNEL_VREFINT) )
<> 144:ef7eb2e8f9f7 5824 {
<> 144:ef7eb2e8f9f7 5825 SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
<> 144:ef7eb2e8f9f7 5826
<> 144:ef7eb2e8f9f7 5827 if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
<> 144:ef7eb2e8f9f7 5828 {
<> 144:ef7eb2e8f9f7 5829 /* Delay for temperature sensor stabilization time */
<> 144:ef7eb2e8f9f7 5830 /* Compute number of CPU cycles to wait for */
<> 144:ef7eb2e8f9f7 5831 wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
<> 144:ef7eb2e8f9f7 5832 while(wait_loop_index != 0)
<> 144:ef7eb2e8f9f7 5833 {
<> 144:ef7eb2e8f9f7 5834 wait_loop_index--;
<> 144:ef7eb2e8f9f7 5835 }
<> 144:ef7eb2e8f9f7 5836 }
<> 144:ef7eb2e8f9f7 5837 }
<> 144:ef7eb2e8f9f7 5838 /* if ADC1 Channel_18 is selected, enable VBAT measurement path */
<> 144:ef7eb2e8f9f7 5839 else if (sConfig->Channel == ADC_CHANNEL_VBAT)
<> 144:ef7eb2e8f9f7 5840 {
<> 144:ef7eb2e8f9f7 5841 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
<> 144:ef7eb2e8f9f7 5842 }
<> 144:ef7eb2e8f9f7 5843
<> 144:ef7eb2e8f9f7 5844
<> 144:ef7eb2e8f9f7 5845 /* Process unlocked */
<> 144:ef7eb2e8f9f7 5846 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 5847
<> 144:ef7eb2e8f9f7 5848 /* Return function status */
<> 144:ef7eb2e8f9f7 5849 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 5850 }
<> 144:ef7eb2e8f9f7 5851 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 5852
<> 144:ef7eb2e8f9f7 5853 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 5854 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 5855 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 5856 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 5857 /**
<> 144:ef7eb2e8f9f7 5858 * @brief Configures the ADC injected group and the selected channel to be
<> 144:ef7eb2e8f9f7 5859 * linked to the injected group.
<> 144:ef7eb2e8f9f7 5860 * @note Possibility to update parameters on the fly:
<> 144:ef7eb2e8f9f7 5861 * This function initializes injected group, following calls to this
<> 144:ef7eb2e8f9f7 5862 * function can be used to reconfigure some parameters of structure
<> 144:ef7eb2e8f9f7 5863 * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC.
<> 144:ef7eb2e8f9f7 5864 * The setting of these parameters is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 5865 * For parameters constraints, see comments of structure
<> 144:ef7eb2e8f9f7 5866 * "ADC_InjectionConfTypeDef".
<> 144:ef7eb2e8f9f7 5867 * @note In case of usage of internal measurement channels:
<> 144:ef7eb2e8f9f7 5868 * Vbat/VrefInt/TempSensor.
<> 144:ef7eb2e8f9f7 5869 * The recommended sampling time is at least:
<> 144:ef7eb2e8f9f7 5870 * - For devices STM32F37x: 17.1us for temperature sensor
<> 144:ef7eb2e8f9f7 5871 * - For the other STM32F3 devices: 2.2us for each of channels
<> 144:ef7eb2e8f9f7 5872 * Vbat/VrefInt/TempSensor.
<> 144:ef7eb2e8f9f7 5873 * These internal paths can be be disabled using function
<> 144:ef7eb2e8f9f7 5874 * HAL_ADC_DeInit().
<> 144:ef7eb2e8f9f7 5875 * @note To reset injected sequencer, function HAL_ADCEx_InjectedStop() can
<> 144:ef7eb2e8f9f7 5876 * be used.
<> 144:ef7eb2e8f9f7 5877 * @note Caution: For Injected Context Queue use: a context must be fully
<> 144:ef7eb2e8f9f7 5878 * defined before start of injected conversion: all channels configured
<> 144:ef7eb2e8f9f7 5879 * consecutively for the same ADC instance. Therefore, Number of calls of
<> 144:ef7eb2e8f9f7 5880 * HAL_ADCEx_InjectedConfigChannel() must correspond to value of parameter
<> 144:ef7eb2e8f9f7 5881 * InjectedNbrOfConversion for each context.
<> 144:ef7eb2e8f9f7 5882 * - Example 1: If 1 context intended to be used (or not use of this feature:
<> 144:ef7eb2e8f9f7 5883 * QueueInjectedContext=DISABLE) and usage of the 3 first injected ranks
<> 144:ef7eb2e8f9f7 5884 * (InjectedNbrOfConversion=3), HAL_ADCEx_InjectedConfigChannel() must be
<> 144:ef7eb2e8f9f7 5885 * called once for each channel (3 times) before launching a conversion.
<> 144:ef7eb2e8f9f7 5886 * This function must not be called to configure the 4th injected channel:
<> 144:ef7eb2e8f9f7 5887 * it would start a new context into context queue.
<> 144:ef7eb2e8f9f7 5888 * - Example 2: If 2 contexts intended to be used and usage of the 3 first
<> 144:ef7eb2e8f9f7 5889 * injected ranks (InjectedNbrOfConversion=3),
<> 144:ef7eb2e8f9f7 5890 * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
<> 144:ef7eb2e8f9f7 5891 * for each context (3 channels x 2 contexts = 6 calls). Conversion can
<> 144:ef7eb2e8f9f7 5892 * start once the 1st context is set. The 2nd context can be set on the fly.
<> 144:ef7eb2e8f9f7 5893 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 5894 * @param sConfigInjected: Structure of ADC injected group and ADC channel for
<> 144:ef7eb2e8f9f7 5895 * injected group.
<> 144:ef7eb2e8f9f7 5896 * @retval None
<> 144:ef7eb2e8f9f7 5897 */
<> 144:ef7eb2e8f9f7 5898 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
<> 144:ef7eb2e8f9f7 5899 {
<> 144:ef7eb2e8f9f7 5900 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 5901 ADC_Common_TypeDef *tmpADC_Common;
<> 144:ef7eb2e8f9f7 5902 ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
<> 144:ef7eb2e8f9f7 5903 uint32_t tmpOffsetShifted;
<> 144:ef7eb2e8f9f7 5904 __IO uint32_t wait_loop_index = 0;
<> 144:ef7eb2e8f9f7 5905
<> 144:ef7eb2e8f9f7 5906 /* Injected context queue feature: temporary JSQR variables defined in */
<> 144:ef7eb2e8f9f7 5907 /* static to be passed over calls of this function */
<> 144:ef7eb2e8f9f7 5908 uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0;
<> 144:ef7eb2e8f9f7 5909
<> 144:ef7eb2e8f9f7 5910 /* Check the parameters */
<> 144:ef7eb2e8f9f7 5911 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 5912 assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
<> 144:ef7eb2e8f9f7 5913 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff));
<> 144:ef7eb2e8f9f7 5914 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
<> 144:ef7eb2e8f9f7 5915 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext));
<> 144:ef7eb2e8f9f7 5916 assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
<> 144:ef7eb2e8f9f7 5917 assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
<> 144:ef7eb2e8f9f7 5918 assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
<> 144:ef7eb2e8f9f7 5919 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
<> 144:ef7eb2e8f9f7 5920
<> 144:ef7eb2e8f9f7 5921 if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
<> 144:ef7eb2e8f9f7 5922 {
<> 144:ef7eb2e8f9f7 5923 assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
<> 144:ef7eb2e8f9f7 5924 assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
<> 144:ef7eb2e8f9f7 5925 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
<> 144:ef7eb2e8f9f7 5926 }
<> 144:ef7eb2e8f9f7 5927
<> 144:ef7eb2e8f9f7 5928 /* Verification of channel number: Channels 1 to 14 are available in */
<> 144:ef7eb2e8f9f7 5929 /* differential mode. Channels 15, 16, 17, 18 can be used only in */
<> 144:ef7eb2e8f9f7 5930 /* single-ended mode. */
<> 144:ef7eb2e8f9f7 5931 if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
<> 144:ef7eb2e8f9f7 5932 {
<> 144:ef7eb2e8f9f7 5933 assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
<> 144:ef7eb2e8f9f7 5934 }
<> 144:ef7eb2e8f9f7 5935 else
<> 144:ef7eb2e8f9f7 5936 {
<> 144:ef7eb2e8f9f7 5937 assert_param(IS_ADC_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
<> 144:ef7eb2e8f9f7 5938 }
<> 144:ef7eb2e8f9f7 5939
<> 144:ef7eb2e8f9f7 5940 /* Process locked */
<> 144:ef7eb2e8f9f7 5941 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 5942
<> 144:ef7eb2e8f9f7 5943 /* Configuration of Injected group sequencer. */
<> 144:ef7eb2e8f9f7 5944 /* Hardware constraint: Must fully define injected context register JSQR */
<> 144:ef7eb2e8f9f7 5945 /* before make it entering into injected sequencer queue. */
<> 144:ef7eb2e8f9f7 5946 /* */
<> 144:ef7eb2e8f9f7 5947 /* - if scan mode is disabled: */
<> 144:ef7eb2e8f9f7 5948 /* * Injected channels sequence length is set to 0x00: 1 channel */
<> 144:ef7eb2e8f9f7 5949 /* converted (channel on injected rank 1) */
<> 144:ef7eb2e8f9f7 5950 /* Parameter "InjectedNbrOfConversion" is discarded. */
<> 144:ef7eb2e8f9f7 5951 /* * Injected context register JSQR setting is simple: register is fully */
<> 144:ef7eb2e8f9f7 5952 /* defined on one call of this function (for injected rank 1) and can */
<> 144:ef7eb2e8f9f7 5953 /* be entered into queue directly. */
<> 144:ef7eb2e8f9f7 5954 /* - if scan mode is enabled: */
<> 144:ef7eb2e8f9f7 5955 /* * Injected channels sequence length is set to parameter */
<> 144:ef7eb2e8f9f7 5956 /* "InjectedNbrOfConversion". */
<> 144:ef7eb2e8f9f7 5957 /* * Injected context register JSQR setting more complex: register is */
<> 144:ef7eb2e8f9f7 5958 /* fully defined over successive calls of this function, for each */
<> 144:ef7eb2e8f9f7 5959 /* injected channel rank. It is entered into queue only when all */
<> 144:ef7eb2e8f9f7 5960 /* injected ranks have been set. */
<> 144:ef7eb2e8f9f7 5961 /* Note: Scan mode is not present by hardware on this device, but used */
<> 144:ef7eb2e8f9f7 5962 /* by software for alignment over all STM32 devices. */
<> 144:ef7eb2e8f9f7 5963
<> 144:ef7eb2e8f9f7 5964 if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) ||
<> 144:ef7eb2e8f9f7 5965 (sConfigInjected->InjectedNbrOfConversion == 1) )
<> 144:ef7eb2e8f9f7 5966 {
<> 144:ef7eb2e8f9f7 5967 /* Configuration of context register JSQR: */
<> 144:ef7eb2e8f9f7 5968 /* - number of ranks in injected group sequencer: fixed to 1st rank */
<> 144:ef7eb2e8f9f7 5969 /* (scan mode disabled, only rank 1 used) */
<> 144:ef7eb2e8f9f7 5970 /* - external trigger to start conversion */
<> 144:ef7eb2e8f9f7 5971 /* - external trigger polarity */
<> 144:ef7eb2e8f9f7 5972 /* - channel set to rank 1 (scan mode disabled, only rank 1 used) */
<> 144:ef7eb2e8f9f7 5973
<> 144:ef7eb2e8f9f7 5974 if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
<> 144:ef7eb2e8f9f7 5975 {
<> 144:ef7eb2e8f9f7 5976 /* Enable external trigger if trigger selection is different of */
<> 144:ef7eb2e8f9f7 5977 /* software start. */
<> 144:ef7eb2e8f9f7 5978 /* Note: This configuration keeps the hardware feature of parameter */
<> 144:ef7eb2e8f9f7 5979 /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
<> 144:ef7eb2e8f9f7 5980 /* software start. */
<> 144:ef7eb2e8f9f7 5981 if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
<> 144:ef7eb2e8f9f7 5982 {
<> 144:ef7eb2e8f9f7 5983 SET_BIT(tmp_JSQR_ContextQueueBeingBuilt, ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) |
<> 144:ef7eb2e8f9f7 5984 ADC_JSQR_JEXTSEL_SET(hadc, sConfigInjected->ExternalTrigInjecConv) |
<> 144:ef7eb2e8f9f7 5985 sConfigInjected->ExternalTrigInjecConvEdge );
<> 144:ef7eb2e8f9f7 5986 }
<> 144:ef7eb2e8f9f7 5987 else
<> 144:ef7eb2e8f9f7 5988 {
<> 144:ef7eb2e8f9f7 5989 SET_BIT(tmp_JSQR_ContextQueueBeingBuilt, ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) );
<> 144:ef7eb2e8f9f7 5990 }
<> 144:ef7eb2e8f9f7 5991
<> 144:ef7eb2e8f9f7 5992 /* Update ADC register JSQR */
<> 144:ef7eb2e8f9f7 5993 MODIFY_REG(hadc->Instance->JSQR ,
<> 144:ef7eb2e8f9f7 5994 ADC_JSQR_JSQ4 |
<> 144:ef7eb2e8f9f7 5995 ADC_JSQR_JSQ3 |
<> 144:ef7eb2e8f9f7 5996 ADC_JSQR_JSQ2 |
<> 144:ef7eb2e8f9f7 5997 ADC_JSQR_JSQ1 |
<> 144:ef7eb2e8f9f7 5998 ADC_JSQR_JEXTEN |
<> 144:ef7eb2e8f9f7 5999 ADC_JSQR_JEXTSEL |
<> 144:ef7eb2e8f9f7 6000 ADC_JSQR_JL ,
<> 144:ef7eb2e8f9f7 6001 tmp_JSQR_ContextQueueBeingBuilt );
<> 144:ef7eb2e8f9f7 6002
<> 144:ef7eb2e8f9f7 6003 /* For debug and informative reasons, hadc handle saves JSQR setting */
<> 144:ef7eb2e8f9f7 6004 hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt;
<> 144:ef7eb2e8f9f7 6005 }
<> 144:ef7eb2e8f9f7 6006 /* If another injected rank than rank1 was intended to be set, and could */
<> 144:ef7eb2e8f9f7 6007 /* not due to ScanConvMode disabled, error is reported. */
<> 144:ef7eb2e8f9f7 6008 else
<> 144:ef7eb2e8f9f7 6009 {
<> 144:ef7eb2e8f9f7 6010 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 6011 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 6012
<> 144:ef7eb2e8f9f7 6013 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 6014 }
<> 144:ef7eb2e8f9f7 6015
<> 144:ef7eb2e8f9f7 6016 }
<> 144:ef7eb2e8f9f7 6017 else
<> 144:ef7eb2e8f9f7 6018 {
<> 144:ef7eb2e8f9f7 6019 /* Case of scan mode enabled, several channels to set into injected group */
<> 144:ef7eb2e8f9f7 6020 /* sequencer. */
<> 144:ef7eb2e8f9f7 6021 /* Procedure to define injected context register JSQR over successive */
<> 144:ef7eb2e8f9f7 6022 /* calls of this function, for each injected channel rank: */
<> 144:ef7eb2e8f9f7 6023
<> 144:ef7eb2e8f9f7 6024 /* 1. Start new context and set parameters related to all injected */
<> 144:ef7eb2e8f9f7 6025 /* channels: injected sequence length and trigger */
<> 144:ef7eb2e8f9f7 6026 if (hadc->InjectionConfig.ChannelCount == 0)
<> 144:ef7eb2e8f9f7 6027 {
<> 144:ef7eb2e8f9f7 6028 /* Initialize number of channels that will be configured on the context */
<> 144:ef7eb2e8f9f7 6029 /* being built */
<> 144:ef7eb2e8f9f7 6030 hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion;
<> 144:ef7eb2e8f9f7 6031 /* Initialize value that will be set into register JSQR */
<> 144:ef7eb2e8f9f7 6032 hadc->InjectionConfig.ContextQueue = (uint32_t)0x00000000;
<> 144:ef7eb2e8f9f7 6033
<> 144:ef7eb2e8f9f7 6034 /* Configuration of context register JSQR: */
<> 144:ef7eb2e8f9f7 6035 /* - number of ranks in injected group sequencer */
<> 144:ef7eb2e8f9f7 6036 /* - external trigger to start conversion */
<> 144:ef7eb2e8f9f7 6037 /* - external trigger polarity */
<> 144:ef7eb2e8f9f7 6038
<> 144:ef7eb2e8f9f7 6039 /* Enable external trigger if trigger selection is different of */
<> 144:ef7eb2e8f9f7 6040 /* software start. */
<> 144:ef7eb2e8f9f7 6041 /* Note: This configuration keeps the hardware feature of parameter */
<> 144:ef7eb2e8f9f7 6042 /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
<> 144:ef7eb2e8f9f7 6043 /* software start. */
<> 144:ef7eb2e8f9f7 6044 if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
<> 144:ef7eb2e8f9f7 6045 {
<> 144:ef7eb2e8f9f7 6046 SET_BIT(hadc->InjectionConfig.ContextQueue, (sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) |
<> 144:ef7eb2e8f9f7 6047 ADC_JSQR_JEXTSEL_SET(hadc, sConfigInjected->ExternalTrigInjecConv) |
<> 144:ef7eb2e8f9f7 6048 sConfigInjected->ExternalTrigInjecConvEdge );
<> 144:ef7eb2e8f9f7 6049 }
<> 144:ef7eb2e8f9f7 6050 else
<> 144:ef7eb2e8f9f7 6051 {
<> 144:ef7eb2e8f9f7 6052 SET_BIT(hadc->InjectionConfig.ContextQueue, (sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) );
<> 144:ef7eb2e8f9f7 6053 }
<> 144:ef7eb2e8f9f7 6054
<> 144:ef7eb2e8f9f7 6055 }
<> 144:ef7eb2e8f9f7 6056
<> 144:ef7eb2e8f9f7 6057 /* 2. Continue setting of context under definition with parameter */
<> 144:ef7eb2e8f9f7 6058 /* related to each channel: channel rank sequence */
<> 144:ef7eb2e8f9f7 6059
<> 144:ef7eb2e8f9f7 6060 /* Set the JSQx bits for the selected rank */
<> 144:ef7eb2e8f9f7 6061 MODIFY_REG(hadc->InjectionConfig.ContextQueue ,
<> 144:ef7eb2e8f9f7 6062 ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank) ,
<> 144:ef7eb2e8f9f7 6063 ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank) );
<> 144:ef7eb2e8f9f7 6064
<> 144:ef7eb2e8f9f7 6065 /* Decrease channel count after setting into temporary JSQR variable */
<> 144:ef7eb2e8f9f7 6066 hadc->InjectionConfig.ChannelCount --;
<> 144:ef7eb2e8f9f7 6067
<> 144:ef7eb2e8f9f7 6068 /* 3. End of context setting: If last channel set, then write context */
<> 144:ef7eb2e8f9f7 6069 /* into register JSQR and make it enter into queue */
<> 144:ef7eb2e8f9f7 6070 if (hadc->InjectionConfig.ChannelCount == 0)
<> 144:ef7eb2e8f9f7 6071 {
<> 144:ef7eb2e8f9f7 6072 /* Update ADC register JSQR */
<> 144:ef7eb2e8f9f7 6073 MODIFY_REG(hadc->Instance->JSQR ,
<> 144:ef7eb2e8f9f7 6074 ADC_JSQR_JSQ4 |
<> 144:ef7eb2e8f9f7 6075 ADC_JSQR_JSQ3 |
<> 144:ef7eb2e8f9f7 6076 ADC_JSQR_JSQ2 |
<> 144:ef7eb2e8f9f7 6077 ADC_JSQR_JSQ1 |
<> 144:ef7eb2e8f9f7 6078 ADC_JSQR_JEXTEN |
<> 144:ef7eb2e8f9f7 6079 ADC_JSQR_JEXTSEL |
<> 144:ef7eb2e8f9f7 6080 ADC_JSQR_JL ,
<> 144:ef7eb2e8f9f7 6081 hadc->InjectionConfig.ContextQueue );
<> 144:ef7eb2e8f9f7 6082 }
<> 144:ef7eb2e8f9f7 6083
<> 144:ef7eb2e8f9f7 6084 }
<> 144:ef7eb2e8f9f7 6085
<> 144:ef7eb2e8f9f7 6086
<> 144:ef7eb2e8f9f7 6087 /* Parameters update conditioned to ADC state: */
<> 144:ef7eb2e8f9f7 6088 /* Parameters that can be updated when ADC is disabled or enabled without */
<> 144:ef7eb2e8f9f7 6089 /* conversion on going on injected group: */
<> 144:ef7eb2e8f9f7 6090 /* - Injected context queue: Queue disable (active context is kept) or */
<> 144:ef7eb2e8f9f7 6091 /* enable (context decremented, up to 2 contexts queued) */
<> 144:ef7eb2e8f9f7 6092 /* - Injected discontinuous mode: can be enabled only if auto-injected */
<> 144:ef7eb2e8f9f7 6093 /* mode is disabled. */
<> 144:ef7eb2e8f9f7 6094 if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
<> 144:ef7eb2e8f9f7 6095 {
<> 144:ef7eb2e8f9f7 6096 /* If auto-injected mode is disabled: no constraint */
<> 144:ef7eb2e8f9f7 6097 if (sConfigInjected->AutoInjectedConv == DISABLE)
<> 144:ef7eb2e8f9f7 6098 {
<> 144:ef7eb2e8f9f7 6099 MODIFY_REG(hadc->Instance->CFGR ,
<> 144:ef7eb2e8f9f7 6100 ADC_CFGR_JQM |
<> 144:ef7eb2e8f9f7 6101 ADC_CFGR_JDISCEN ,
<> 144:ef7eb2e8f9f7 6102 ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) |
<> 144:ef7eb2e8f9f7 6103 ADC_CFGR_INJECT_DISCCONTINUOUS(sConfigInjected->InjectedDiscontinuousConvMode) );
<> 144:ef7eb2e8f9f7 6104 }
<> 144:ef7eb2e8f9f7 6105 /* If auto-injected mode is enabled: Injected discontinuous setting is */
<> 144:ef7eb2e8f9f7 6106 /* discarded. */
<> 144:ef7eb2e8f9f7 6107 else
<> 144:ef7eb2e8f9f7 6108 {
<> 144:ef7eb2e8f9f7 6109 MODIFY_REG(hadc->Instance->CFGR ,
<> 144:ef7eb2e8f9f7 6110 ADC_CFGR_JQM |
<> 144:ef7eb2e8f9f7 6111 ADC_CFGR_JDISCEN ,
<> 144:ef7eb2e8f9f7 6112 ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) );
<> 144:ef7eb2e8f9f7 6113
<> 144:ef7eb2e8f9f7 6114 /* If injected discontinuous mode was intended to be set and could not */
<> 144:ef7eb2e8f9f7 6115 /* due to auto-injected enabled, error is reported. */
<> 144:ef7eb2e8f9f7 6116 if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
<> 144:ef7eb2e8f9f7 6117 {
<> 144:ef7eb2e8f9f7 6118 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 6119 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 6120
<> 144:ef7eb2e8f9f7 6121 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 6122 }
<> 144:ef7eb2e8f9f7 6123 }
<> 144:ef7eb2e8f9f7 6124
<> 144:ef7eb2e8f9f7 6125 }
<> 144:ef7eb2e8f9f7 6126
<> 144:ef7eb2e8f9f7 6127
<> 144:ef7eb2e8f9f7 6128 /* Parameters update conditioned to ADC state: */
<> 144:ef7eb2e8f9f7 6129 /* Parameters that can be updated when ADC is disabled or enabled without */
<> 144:ef7eb2e8f9f7 6130 /* conversion on going on regular and injected groups: */
<> 144:ef7eb2e8f9f7 6131 /* - Automatic injected conversion: can be enabled if injected group */
<> 144:ef7eb2e8f9f7 6132 /* external triggers are disabled. */
<> 144:ef7eb2e8f9f7 6133 /* - Channel sampling time */
<> 144:ef7eb2e8f9f7 6134 /* - Channel offset */
<> 144:ef7eb2e8f9f7 6135 if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
<> 144:ef7eb2e8f9f7 6136 {
<> 144:ef7eb2e8f9f7 6137 /* If injected group external triggers are disabled (set to injected */
<> 144:ef7eb2e8f9f7 6138 /* software start): no constraint */
<> 144:ef7eb2e8f9f7 6139 if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
<> 144:ef7eb2e8f9f7 6140 {
<> 144:ef7eb2e8f9f7 6141 MODIFY_REG(hadc->Instance->CFGR ,
<> 144:ef7eb2e8f9f7 6142 ADC_CFGR_JAUTO ,
<> 144:ef7eb2e8f9f7 6143 ADC_CFGR_INJECT_AUTO_CONVERSION(sConfigInjected->AutoInjectedConv) );
<> 144:ef7eb2e8f9f7 6144 }
<> 144:ef7eb2e8f9f7 6145 /* If Automatic injected conversion was intended to be set and could not */
<> 144:ef7eb2e8f9f7 6146 /* due to injected group external triggers enabled, error is reported. */
<> 144:ef7eb2e8f9f7 6147 else
<> 144:ef7eb2e8f9f7 6148 {
<> 144:ef7eb2e8f9f7 6149 /* Disable Automatic injected conversion */
<> 144:ef7eb2e8f9f7 6150 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
<> 144:ef7eb2e8f9f7 6151
<> 144:ef7eb2e8f9f7 6152 if (sConfigInjected->AutoInjectedConv == ENABLE)
<> 144:ef7eb2e8f9f7 6153 {
<> 144:ef7eb2e8f9f7 6154 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 6155 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 6156
<> 144:ef7eb2e8f9f7 6157 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 6158 }
<> 144:ef7eb2e8f9f7 6159 }
<> 144:ef7eb2e8f9f7 6160
<> 144:ef7eb2e8f9f7 6161
<> 144:ef7eb2e8f9f7 6162 /* Channel sampling time configuration */
<> 144:ef7eb2e8f9f7 6163 /* For channels 10 to 18 */
<> 144:ef7eb2e8f9f7 6164 if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
<> 144:ef7eb2e8f9f7 6165 {
<> 144:ef7eb2e8f9f7 6166 MODIFY_REG(hadc->Instance->SMPR2 ,
<> 144:ef7eb2e8f9f7 6167 ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel) ,
<> 144:ef7eb2e8f9f7 6168 ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
<> 144:ef7eb2e8f9f7 6169 }
<> 144:ef7eb2e8f9f7 6170 else /* For channels 1 to 9 */
<> 144:ef7eb2e8f9f7 6171 {
<> 144:ef7eb2e8f9f7 6172 MODIFY_REG(hadc->Instance->SMPR1 ,
<> 144:ef7eb2e8f9f7 6173 ADC_SMPR1(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel) ,
<> 144:ef7eb2e8f9f7 6174 ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
<> 144:ef7eb2e8f9f7 6175 }
<> 144:ef7eb2e8f9f7 6176
<> 144:ef7eb2e8f9f7 6177 /* Configure the offset: offset enable/disable, channel, offset value */
<> 144:ef7eb2e8f9f7 6178
<> 144:ef7eb2e8f9f7 6179 /* Shift the offset in function of the selected ADC resolution. */
<> 144:ef7eb2e8f9f7 6180 /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set */
<> 144:ef7eb2e8f9f7 6181 /* to 0. */
<> 144:ef7eb2e8f9f7 6182 tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
<> 144:ef7eb2e8f9f7 6183
<> 144:ef7eb2e8f9f7 6184 /* Configure the selected offset register: */
<> 144:ef7eb2e8f9f7 6185 /* - Enable offset */
<> 144:ef7eb2e8f9f7 6186 /* - Set channel number */
<> 144:ef7eb2e8f9f7 6187 /* - Set offset value */
<> 144:ef7eb2e8f9f7 6188 switch (sConfigInjected->InjectedOffsetNumber)
<> 144:ef7eb2e8f9f7 6189 {
<> 144:ef7eb2e8f9f7 6190 case ADC_OFFSET_1:
<> 144:ef7eb2e8f9f7 6191 /* Configure offset register 1 */
<> 144:ef7eb2e8f9f7 6192 MODIFY_REG(hadc->Instance->OFR1 ,
<> 144:ef7eb2e8f9f7 6193 ADC_OFR1_OFFSET1_CH |
<> 144:ef7eb2e8f9f7 6194 ADC_OFR1_OFFSET1 ,
<> 144:ef7eb2e8f9f7 6195 ADC_OFR1_OFFSET1_EN |
<> 144:ef7eb2e8f9f7 6196 ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
<> 144:ef7eb2e8f9f7 6197 tmpOffsetShifted );
<> 144:ef7eb2e8f9f7 6198 break;
<> 144:ef7eb2e8f9f7 6199
<> 144:ef7eb2e8f9f7 6200 case ADC_OFFSET_2:
<> 144:ef7eb2e8f9f7 6201 /* Configure offset register 2 */
<> 144:ef7eb2e8f9f7 6202 MODIFY_REG(hadc->Instance->OFR2 ,
<> 144:ef7eb2e8f9f7 6203 ADC_OFR2_OFFSET2_CH |
<> 144:ef7eb2e8f9f7 6204 ADC_OFR2_OFFSET2 ,
<> 144:ef7eb2e8f9f7 6205 ADC_OFR2_OFFSET2_EN |
<> 144:ef7eb2e8f9f7 6206 ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
<> 144:ef7eb2e8f9f7 6207 tmpOffsetShifted );
<> 144:ef7eb2e8f9f7 6208 break;
<> 144:ef7eb2e8f9f7 6209
<> 144:ef7eb2e8f9f7 6210 case ADC_OFFSET_3:
<> 144:ef7eb2e8f9f7 6211 /* Configure offset register 3 */
<> 144:ef7eb2e8f9f7 6212 MODIFY_REG(hadc->Instance->OFR3 ,
<> 144:ef7eb2e8f9f7 6213 ADC_OFR3_OFFSET3_CH |
<> 144:ef7eb2e8f9f7 6214 ADC_OFR3_OFFSET3 ,
<> 144:ef7eb2e8f9f7 6215 ADC_OFR3_OFFSET3_EN |
<> 144:ef7eb2e8f9f7 6216 ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
<> 144:ef7eb2e8f9f7 6217 tmpOffsetShifted );
<> 144:ef7eb2e8f9f7 6218 break;
<> 144:ef7eb2e8f9f7 6219
<> 144:ef7eb2e8f9f7 6220 case ADC_OFFSET_4:
<> 144:ef7eb2e8f9f7 6221 /* Configure offset register 4 */
<> 144:ef7eb2e8f9f7 6222 MODIFY_REG(hadc->Instance->OFR4 ,
<> 144:ef7eb2e8f9f7 6223 ADC_OFR4_OFFSET4_CH |
<> 144:ef7eb2e8f9f7 6224 ADC_OFR4_OFFSET4 ,
<> 144:ef7eb2e8f9f7 6225 ADC_OFR4_OFFSET4_EN |
<> 144:ef7eb2e8f9f7 6226 ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
<> 144:ef7eb2e8f9f7 6227 tmpOffsetShifted );
<> 144:ef7eb2e8f9f7 6228 break;
<> 144:ef7eb2e8f9f7 6229
<> 144:ef7eb2e8f9f7 6230 /* Case ADC_OFFSET_NONE */
<> 144:ef7eb2e8f9f7 6231 default :
<> 144:ef7eb2e8f9f7 6232 /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is */
<> 144:ef7eb2e8f9f7 6233 /* enabled. If this is the case, offset OFRx is disabled. */
<> 144:ef7eb2e8f9f7 6234 if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
<> 144:ef7eb2e8f9f7 6235 {
<> 144:ef7eb2e8f9f7 6236 /* Disable offset OFR1*/
<> 144:ef7eb2e8f9f7 6237 CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
<> 144:ef7eb2e8f9f7 6238 }
<> 144:ef7eb2e8f9f7 6239 if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
<> 144:ef7eb2e8f9f7 6240 {
<> 144:ef7eb2e8f9f7 6241 /* Disable offset OFR2*/
<> 144:ef7eb2e8f9f7 6242 CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN);
<> 144:ef7eb2e8f9f7 6243 }
<> 144:ef7eb2e8f9f7 6244 if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
<> 144:ef7eb2e8f9f7 6245 {
<> 144:ef7eb2e8f9f7 6246 /* Disable offset OFR3*/
<> 144:ef7eb2e8f9f7 6247 CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN);
<> 144:ef7eb2e8f9f7 6248 }
<> 144:ef7eb2e8f9f7 6249 if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
<> 144:ef7eb2e8f9f7 6250 {
<> 144:ef7eb2e8f9f7 6251 /* Disable offset OFR4*/
<> 144:ef7eb2e8f9f7 6252 CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN);
<> 144:ef7eb2e8f9f7 6253 }
<> 144:ef7eb2e8f9f7 6254 break;
<> 144:ef7eb2e8f9f7 6255 }
<> 144:ef7eb2e8f9f7 6256
<> 144:ef7eb2e8f9f7 6257 }
<> 144:ef7eb2e8f9f7 6258
<> 144:ef7eb2e8f9f7 6259
<> 144:ef7eb2e8f9f7 6260 /* Parameters update conditioned to ADC state: */
<> 144:ef7eb2e8f9f7 6261 /* Parameters that can be updated only when ADC is disabled: */
<> 144:ef7eb2e8f9f7 6262 /* - Single or differential mode */
<> 144:ef7eb2e8f9f7 6263 /* - Internal measurement channels: Vbat/VrefInt/TempSensor */
<> 144:ef7eb2e8f9f7 6264 if (ADC_IS_ENABLE(hadc) == RESET)
<> 144:ef7eb2e8f9f7 6265 {
<> 144:ef7eb2e8f9f7 6266 /* Configuration of differential mode */
<> 144:ef7eb2e8f9f7 6267 if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
<> 144:ef7eb2e8f9f7 6268 {
<> 144:ef7eb2e8f9f7 6269 /* Disable differential mode (default mode: single-ended) */
<> 144:ef7eb2e8f9f7 6270 CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
<> 144:ef7eb2e8f9f7 6271 }
<> 144:ef7eb2e8f9f7 6272 else
<> 144:ef7eb2e8f9f7 6273 {
<> 144:ef7eb2e8f9f7 6274 /* Enable differential mode */
<> 144:ef7eb2e8f9f7 6275 SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
<> 144:ef7eb2e8f9f7 6276
<> 144:ef7eb2e8f9f7 6277 /* Channel sampling time configuration (channel ADC_INx +1 */
<> 144:ef7eb2e8f9f7 6278 /* corresponding to differential negative input). */
<> 144:ef7eb2e8f9f7 6279 /* For channels 10 to 18 */
<> 144:ef7eb2e8f9f7 6280 if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
<> 144:ef7eb2e8f9f7 6281 {
<> 144:ef7eb2e8f9f7 6282 MODIFY_REG(hadc->Instance->SMPR2,
<> 144:ef7eb2e8f9f7 6283 ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel +1),
<> 144:ef7eb2e8f9f7 6284 ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1) );
<> 144:ef7eb2e8f9f7 6285 }
<> 144:ef7eb2e8f9f7 6286 else /* For channels 1 to 9 */
<> 144:ef7eb2e8f9f7 6287 {
<> 144:ef7eb2e8f9f7 6288 MODIFY_REG(hadc->Instance->SMPR1,
<> 144:ef7eb2e8f9f7 6289 ADC_SMPR1(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel +1),
<> 144:ef7eb2e8f9f7 6290 ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1) );
<> 144:ef7eb2e8f9f7 6291 }
<> 144:ef7eb2e8f9f7 6292 }
<> 144:ef7eb2e8f9f7 6293
<> 144:ef7eb2e8f9f7 6294
<> 144:ef7eb2e8f9f7 6295 /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
<> 144:ef7eb2e8f9f7 6296 /* internal measurement paths enable: If internal channel selected, */
<> 144:ef7eb2e8f9f7 6297 /* enable dedicated internal buffers and path. */
<> 144:ef7eb2e8f9f7 6298 /* Note: these internal measurement paths can be disabled using */
<> 144:ef7eb2e8f9f7 6299 /* HAL_ADC_deInit(). */
<> 144:ef7eb2e8f9f7 6300
<> 144:ef7eb2e8f9f7 6301 /* Configuration of common ADC parameters */
<> 144:ef7eb2e8f9f7 6302 /* Pointer to the common control register to which is belonging hadc */
<> 144:ef7eb2e8f9f7 6303 /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
<> 144:ef7eb2e8f9f7 6304 /* control registers) */
<> 144:ef7eb2e8f9f7 6305 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
<> 144:ef7eb2e8f9f7 6306
<> 144:ef7eb2e8f9f7 6307 /* If the requested internal measurement path has already been enabled, */
<> 144:ef7eb2e8f9f7 6308 /* bypass the configuration processing. */
<> 144:ef7eb2e8f9f7 6309 if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) &&
<> 144:ef7eb2e8f9f7 6310 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) ||
<> 144:ef7eb2e8f9f7 6311 ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) &&
<> 144:ef7eb2e8f9f7 6312 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) ||
<> 144:ef7eb2e8f9f7 6313 ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) &&
<> 144:ef7eb2e8f9f7 6314 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
<> 144:ef7eb2e8f9f7 6315 )
<> 144:ef7eb2e8f9f7 6316 {
<> 144:ef7eb2e8f9f7 6317 /* Configuration of common ADC parameters (continuation) */
<> 144:ef7eb2e8f9f7 6318 /* Set handle of the other ADC sharing the same common register */
<> 144:ef7eb2e8f9f7 6319 ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
<> 144:ef7eb2e8f9f7 6320
<> 144:ef7eb2e8f9f7 6321 /* Software is allowed to change common parameters only when all ADCs */
<> 144:ef7eb2e8f9f7 6322 /* of the common group are disabled. */
<> 144:ef7eb2e8f9f7 6323 if ((ADC_IS_ENABLE(hadc) == RESET) &&
<> 144:ef7eb2e8f9f7 6324 ( (tmphadcSharingSameCommonRegister.Instance == NULL) ||
<> 144:ef7eb2e8f9f7 6325 (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) )
<> 144:ef7eb2e8f9f7 6326 {
<> 144:ef7eb2e8f9f7 6327 /* If Channel_16 is selected, enable Temp. sensor measurement path */
<> 144:ef7eb2e8f9f7 6328 /* Note: Temp. sensor internal channels available on ADC1 only */
<> 144:ef7eb2e8f9f7 6329 if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1))
<> 144:ef7eb2e8f9f7 6330 {
<> 144:ef7eb2e8f9f7 6331 SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
<> 144:ef7eb2e8f9f7 6332
<> 144:ef7eb2e8f9f7 6333 /* Delay for temperature sensor stabilization time */
<> 144:ef7eb2e8f9f7 6334 /* Compute number of CPU cycles to wait for */
<> 144:ef7eb2e8f9f7 6335 wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
<> 144:ef7eb2e8f9f7 6336 while(wait_loop_index != 0)
<> 144:ef7eb2e8f9f7 6337 {
<> 144:ef7eb2e8f9f7 6338 wait_loop_index--;
<> 144:ef7eb2e8f9f7 6339 }
<> 144:ef7eb2e8f9f7 6340 }
<> 144:ef7eb2e8f9f7 6341 /* If Channel_17 is selected, enable VBAT measurement path */
<> 144:ef7eb2e8f9f7 6342 /* Note: VBAT internal channels available on ADC1 only */
<> 144:ef7eb2e8f9f7 6343 else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && (hadc->Instance == ADC1))
<> 144:ef7eb2e8f9f7 6344 {
<> 144:ef7eb2e8f9f7 6345 SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
<> 144:ef7eb2e8f9f7 6346 }
<> 144:ef7eb2e8f9f7 6347 /* If Channel_18 is selected, enable VREFINT measurement path */
<> 144:ef7eb2e8f9f7 6348 /* Note: VrefInt internal channels available on all ADCs, but only */
<> 144:ef7eb2e8f9f7 6349 /* one ADC is allowed to be connected to VrefInt at the same */
<> 144:ef7eb2e8f9f7 6350 /* time. */
<> 144:ef7eb2e8f9f7 6351 else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
<> 144:ef7eb2e8f9f7 6352 {
<> 144:ef7eb2e8f9f7 6353 SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
<> 144:ef7eb2e8f9f7 6354 }
<> 144:ef7eb2e8f9f7 6355 }
<> 144:ef7eb2e8f9f7 6356 /* If the requested internal measurement path has already been enabled */
<> 144:ef7eb2e8f9f7 6357 /* and other ADC of the common group are enabled, internal */
<> 144:ef7eb2e8f9f7 6358 /* measurement paths cannot be enabled. */
<> 144:ef7eb2e8f9f7 6359 else
<> 144:ef7eb2e8f9f7 6360 {
<> 144:ef7eb2e8f9f7 6361 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 6362 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 6363
<> 144:ef7eb2e8f9f7 6364 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 6365 }
<> 144:ef7eb2e8f9f7 6366 }
<> 144:ef7eb2e8f9f7 6367
<> 144:ef7eb2e8f9f7 6368 }
<> 144:ef7eb2e8f9f7 6369
<> 144:ef7eb2e8f9f7 6370 /* Process unlocked */
<> 144:ef7eb2e8f9f7 6371 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 6372
<> 144:ef7eb2e8f9f7 6373 /* Return function status */
<> 144:ef7eb2e8f9f7 6374 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 6375 }
<> 144:ef7eb2e8f9f7 6376 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 6377 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 6378 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 6379 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 6380
<> 144:ef7eb2e8f9f7 6381 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 6382 /**
<> 144:ef7eb2e8f9f7 6383 * @brief Configures the ADC injected group and the selected channel to be
<> 144:ef7eb2e8f9f7 6384 * linked to the injected group.
<> 144:ef7eb2e8f9f7 6385 * @note Possibility to update parameters on the fly:
<> 144:ef7eb2e8f9f7 6386 * This function initializes injected group, following calls to this
<> 144:ef7eb2e8f9f7 6387 * function can be used to reconfigure some parameters of structure
<> 144:ef7eb2e8f9f7 6388 * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC.
<> 144:ef7eb2e8f9f7 6389 * The setting of these parameters is conditioned to ADC state:
<> 144:ef7eb2e8f9f7 6390 * this function must be called when ADC is not under conversion.
<> 144:ef7eb2e8f9f7 6391 * @note In case of usage of internal measurement channels:
<> 144:ef7eb2e8f9f7 6392 * Vbat/VrefInt/TempSensor.
<> 144:ef7eb2e8f9f7 6393 * The recommended sampling time is at least:
<> 144:ef7eb2e8f9f7 6394 * - For devices STM32F37x: 17.1us for temperature sensor
<> 144:ef7eb2e8f9f7 6395 * - For the other STM32F3 devices: 2.2us for each of channels
<> 144:ef7eb2e8f9f7 6396 * Vbat/VrefInt/TempSensor.
<> 144:ef7eb2e8f9f7 6397 * These internal paths can be be disabled using function
<> 144:ef7eb2e8f9f7 6398 * HAL_ADC_DeInit().
<> 144:ef7eb2e8f9f7 6399 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 6400 * @param sConfigInjected: Structure of ADC injected group and ADC channel for
<> 144:ef7eb2e8f9f7 6401 * injected group.
<> 144:ef7eb2e8f9f7 6402 * @retval None
<> 144:ef7eb2e8f9f7 6403 */
<> 144:ef7eb2e8f9f7 6404 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
<> 144:ef7eb2e8f9f7 6405 {
<> 144:ef7eb2e8f9f7 6406 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 6407 __IO uint32_t wait_loop_index = 0;
<> 144:ef7eb2e8f9f7 6408
<> 144:ef7eb2e8f9f7 6409 /* Check the parameters */
<> 144:ef7eb2e8f9f7 6410 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 6411 assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
<> 144:ef7eb2e8f9f7 6412 assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
<> 144:ef7eb2e8f9f7 6413 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
<> 144:ef7eb2e8f9f7 6414 assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
<> 144:ef7eb2e8f9f7 6415 assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset));
<> 144:ef7eb2e8f9f7 6416
<> 144:ef7eb2e8f9f7 6417 if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
<> 144:ef7eb2e8f9f7 6418 {
<> 144:ef7eb2e8f9f7 6419 assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
<> 144:ef7eb2e8f9f7 6420 assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
<> 144:ef7eb2e8f9f7 6421 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
<> 144:ef7eb2e8f9f7 6422 }
<> 144:ef7eb2e8f9f7 6423
<> 144:ef7eb2e8f9f7 6424 /* Process locked */
<> 144:ef7eb2e8f9f7 6425 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 6426
<> 144:ef7eb2e8f9f7 6427 /* Configuration of injected group sequencer: */
<> 144:ef7eb2e8f9f7 6428 /* - if scan mode is disabled, injected channels sequence length is set to */
<> 144:ef7eb2e8f9f7 6429 /* 0x00: 1 channel converted (channel on regular rank 1) */
<> 144:ef7eb2e8f9f7 6430 /* Parameter "InjectedNbrOfConversion" is discarded. */
<> 144:ef7eb2e8f9f7 6431 /* Note: Scan mode is present by hardware on this device and, if */
<> 144:ef7eb2e8f9f7 6432 /* disabled, discards automatically nb of conversions. Anyway, nb of */
<> 144:ef7eb2e8f9f7 6433 /* conversions is forced to 0x00 for alignment over all STM32 devices. */
<> 144:ef7eb2e8f9f7 6434 /* - if scan mode is enabled, injected channels sequence length is set to */
<> 144:ef7eb2e8f9f7 6435 /* parameter "InjectedNbrOfConversion". */
<> 144:ef7eb2e8f9f7 6436 if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
<> 144:ef7eb2e8f9f7 6437 {
<> 144:ef7eb2e8f9f7 6438 if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
<> 144:ef7eb2e8f9f7 6439 {
<> 144:ef7eb2e8f9f7 6440 /* Clear the old SQx bits for all injected ranks */
<> 144:ef7eb2e8f9f7 6441 MODIFY_REG(hadc->Instance->JSQR ,
<> 144:ef7eb2e8f9f7 6442 ADC_JSQR_JL |
<> 144:ef7eb2e8f9f7 6443 ADC_JSQR_JSQ4 |
<> 144:ef7eb2e8f9f7 6444 ADC_JSQR_JSQ3 |
<> 144:ef7eb2e8f9f7 6445 ADC_JSQR_JSQ2 |
<> 144:ef7eb2e8f9f7 6446 ADC_JSQR_JSQ1 ,
<> 144:ef7eb2e8f9f7 6447 ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
<> 144:ef7eb2e8f9f7 6448 ADC_INJECTED_RANK_1,
<> 144:ef7eb2e8f9f7 6449 0x01) );
<> 144:ef7eb2e8f9f7 6450 }
<> 144:ef7eb2e8f9f7 6451 /* If another injected rank than rank1 was intended to be set, and could */
<> 144:ef7eb2e8f9f7 6452 /* not due to ScanConvMode disabled, error is reported. */
<> 144:ef7eb2e8f9f7 6453 else
<> 144:ef7eb2e8f9f7 6454 {
<> 144:ef7eb2e8f9f7 6455 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 6456 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 6457
<> 144:ef7eb2e8f9f7 6458 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 6459 }
<> 144:ef7eb2e8f9f7 6460 }
<> 144:ef7eb2e8f9f7 6461 else
<> 144:ef7eb2e8f9f7 6462 {
<> 144:ef7eb2e8f9f7 6463 /* Since injected channels rank conv. order depends on total number of */
<> 144:ef7eb2e8f9f7 6464 /* injected conversions, selected rank must be below or equal to total */
<> 144:ef7eb2e8f9f7 6465 /* number of injected conversions to be updated. */
<> 144:ef7eb2e8f9f7 6466 if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion)
<> 144:ef7eb2e8f9f7 6467 {
<> 144:ef7eb2e8f9f7 6468 /* Clear the old SQx bits for the selected rank */
<> 144:ef7eb2e8f9f7 6469 /* Set the SQx bits for the selected rank */
<> 144:ef7eb2e8f9f7 6470 MODIFY_REG(hadc->Instance->JSQR ,
<> 144:ef7eb2e8f9f7 6471
<> 144:ef7eb2e8f9f7 6472 ADC_JSQR_JL |
<> 144:ef7eb2e8f9f7 6473 ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
<> 144:ef7eb2e8f9f7 6474 sConfigInjected->InjectedRank,
<> 144:ef7eb2e8f9f7 6475 sConfigInjected->InjectedNbrOfConversion) ,
<> 144:ef7eb2e8f9f7 6476
<> 144:ef7eb2e8f9f7 6477 ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) |
<> 144:ef7eb2e8f9f7 6478 ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
<> 144:ef7eb2e8f9f7 6479 sConfigInjected->InjectedRank,
<> 144:ef7eb2e8f9f7 6480 sConfigInjected->InjectedNbrOfConversion) );
<> 144:ef7eb2e8f9f7 6481 }
<> 144:ef7eb2e8f9f7 6482 else
<> 144:ef7eb2e8f9f7 6483 {
<> 144:ef7eb2e8f9f7 6484 /* Clear the old SQx bits for the selected rank */
<> 144:ef7eb2e8f9f7 6485 MODIFY_REG(hadc->Instance->JSQR ,
<> 144:ef7eb2e8f9f7 6486
<> 144:ef7eb2e8f9f7 6487 ADC_JSQR_JL |
<> 144:ef7eb2e8f9f7 6488 ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
<> 144:ef7eb2e8f9f7 6489 sConfigInjected->InjectedRank,
<> 144:ef7eb2e8f9f7 6490 sConfigInjected->InjectedNbrOfConversion) ,
<> 144:ef7eb2e8f9f7 6491
<> 144:ef7eb2e8f9f7 6492 0x00000000 );
<> 144:ef7eb2e8f9f7 6493 }
<> 144:ef7eb2e8f9f7 6494 }
<> 144:ef7eb2e8f9f7 6495
<> 144:ef7eb2e8f9f7 6496 /* Configuration of injected group */
<> 144:ef7eb2e8f9f7 6497 /* Parameters update conditioned to ADC state: */
<> 144:ef7eb2e8f9f7 6498 /* Parameters that can be updated only when ADC is disabled: */
<> 144:ef7eb2e8f9f7 6499 /* - external trigger to start conversion */
<> 144:ef7eb2e8f9f7 6500 /* Parameters update not conditioned to ADC state: */
<> 144:ef7eb2e8f9f7 6501 /* - Automatic injected conversion */
<> 144:ef7eb2e8f9f7 6502 /* - Injected discontinuous mode */
<> 144:ef7eb2e8f9f7 6503 /* Note: In case of ADC already enabled, caution to not launch an unwanted */
<> 144:ef7eb2e8f9f7 6504 /* conversion while modifying register CR2 by writing 1 to bit ADON. */
<> 144:ef7eb2e8f9f7 6505 if (ADC_IS_ENABLE(hadc) == RESET)
<> 144:ef7eb2e8f9f7 6506 {
<> 144:ef7eb2e8f9f7 6507 MODIFY_REG(hadc->Instance->CR2 ,
<> 144:ef7eb2e8f9f7 6508 ADC_CR2_JEXTSEL |
<> 144:ef7eb2e8f9f7 6509 ADC_CR2_ADON ,
<> 144:ef7eb2e8f9f7 6510 sConfigInjected->ExternalTrigInjecConv );
<> 144:ef7eb2e8f9f7 6511 }
<> 144:ef7eb2e8f9f7 6512
<> 144:ef7eb2e8f9f7 6513 /* Configuration of injected group */
<> 144:ef7eb2e8f9f7 6514 /* - Automatic injected conversion */
<> 144:ef7eb2e8f9f7 6515 /* - Injected discontinuous mode */
<> 144:ef7eb2e8f9f7 6516
<> 144:ef7eb2e8f9f7 6517 /* Automatic injected conversion can be enabled if injected group */
<> 144:ef7eb2e8f9f7 6518 /* external triggers are disabled. */
<> 144:ef7eb2e8f9f7 6519 if (sConfigInjected->AutoInjectedConv == ENABLE)
<> 144:ef7eb2e8f9f7 6520 {
<> 144:ef7eb2e8f9f7 6521 if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
<> 144:ef7eb2e8f9f7 6522 {
<> 144:ef7eb2e8f9f7 6523 SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO);
<> 144:ef7eb2e8f9f7 6524 }
<> 144:ef7eb2e8f9f7 6525 else
<> 144:ef7eb2e8f9f7 6526 {
<> 144:ef7eb2e8f9f7 6527 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 6528 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 6529
<> 144:ef7eb2e8f9f7 6530 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 6531 }
<> 144:ef7eb2e8f9f7 6532 }
<> 144:ef7eb2e8f9f7 6533
<> 144:ef7eb2e8f9f7 6534 /* Injected discontinuous can be enabled only if auto-injected mode is */
<> 144:ef7eb2e8f9f7 6535 /* disabled. */
<> 144:ef7eb2e8f9f7 6536 if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
<> 144:ef7eb2e8f9f7 6537 {
<> 144:ef7eb2e8f9f7 6538 if (sConfigInjected->AutoInjectedConv == DISABLE)
<> 144:ef7eb2e8f9f7 6539 {
<> 144:ef7eb2e8f9f7 6540 SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN);
<> 144:ef7eb2e8f9f7 6541 }
<> 144:ef7eb2e8f9f7 6542 else
<> 144:ef7eb2e8f9f7 6543 {
<> 144:ef7eb2e8f9f7 6544 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 6545 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 6546
<> 144:ef7eb2e8f9f7 6547 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 6548 }
<> 144:ef7eb2e8f9f7 6549 }
<> 144:ef7eb2e8f9f7 6550
<> 144:ef7eb2e8f9f7 6551
<> 144:ef7eb2e8f9f7 6552 /* InjectedChannel sampling time configuration */
<> 144:ef7eb2e8f9f7 6553 /* For channels 10 to 18 */
<> 144:ef7eb2e8f9f7 6554 if (sConfigInjected->InjectedChannel > ADC_CHANNEL_10)
<> 144:ef7eb2e8f9f7 6555 {
<> 144:ef7eb2e8f9f7 6556 MODIFY_REG(hadc->Instance->SMPR1,
<> 144:ef7eb2e8f9f7 6557 ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel),
<> 144:ef7eb2e8f9f7 6558 ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
<> 144:ef7eb2e8f9f7 6559 }
<> 144:ef7eb2e8f9f7 6560 else /* For channels 1 to 9 */
<> 144:ef7eb2e8f9f7 6561 {
<> 144:ef7eb2e8f9f7 6562 MODIFY_REG(hadc->Instance->SMPR2,
<> 144:ef7eb2e8f9f7 6563 ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel),
<> 144:ef7eb2e8f9f7 6564 ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
<> 144:ef7eb2e8f9f7 6565 }
<> 144:ef7eb2e8f9f7 6566
<> 144:ef7eb2e8f9f7 6567
<> 144:ef7eb2e8f9f7 6568 /* Configure the offset: offset enable/disable, InjectedChannel, offset value */
<> 144:ef7eb2e8f9f7 6569 switch(sConfigInjected->InjectedRank)
<> 144:ef7eb2e8f9f7 6570 {
<> 144:ef7eb2e8f9f7 6571 case 1:
<> 144:ef7eb2e8f9f7 6572 /* Set injected channel 1 offset */
<> 144:ef7eb2e8f9f7 6573 MODIFY_REG(hadc->Instance->JOFR1,
<> 144:ef7eb2e8f9f7 6574 ADC_JOFR1_JOFFSET1,
<> 144:ef7eb2e8f9f7 6575 sConfigInjected->InjectedOffset);
<> 144:ef7eb2e8f9f7 6576 break;
<> 144:ef7eb2e8f9f7 6577 case 2:
<> 144:ef7eb2e8f9f7 6578 /* Set injected channel 2 offset */
<> 144:ef7eb2e8f9f7 6579 MODIFY_REG(hadc->Instance->JOFR2,
<> 144:ef7eb2e8f9f7 6580 ADC_JOFR2_JOFFSET2,
<> 144:ef7eb2e8f9f7 6581 sConfigInjected->InjectedOffset);
<> 144:ef7eb2e8f9f7 6582 break;
<> 144:ef7eb2e8f9f7 6583 case 3:
<> 144:ef7eb2e8f9f7 6584 /* Set injected channel 3 offset */
<> 144:ef7eb2e8f9f7 6585 MODIFY_REG(hadc->Instance->JOFR3,
<> 144:ef7eb2e8f9f7 6586 ADC_JOFR3_JOFFSET3,
<> 144:ef7eb2e8f9f7 6587 sConfigInjected->InjectedOffset);
<> 144:ef7eb2e8f9f7 6588 break;
<> 144:ef7eb2e8f9f7 6589 case 4:
<> 144:ef7eb2e8f9f7 6590 default:
<> 144:ef7eb2e8f9f7 6591 MODIFY_REG(hadc->Instance->JOFR4,
<> 144:ef7eb2e8f9f7 6592 ADC_JOFR4_JOFFSET4,
<> 144:ef7eb2e8f9f7 6593 sConfigInjected->InjectedOffset);
<> 144:ef7eb2e8f9f7 6594 break;
<> 144:ef7eb2e8f9f7 6595 }
<> 144:ef7eb2e8f9f7 6596
<> 144:ef7eb2e8f9f7 6597 /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
<> 144:ef7eb2e8f9f7 6598 /* and VREFINT measurement path. */
<> 144:ef7eb2e8f9f7 6599 if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
<> 144:ef7eb2e8f9f7 6600 (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) )
<> 144:ef7eb2e8f9f7 6601 {
<> 144:ef7eb2e8f9f7 6602 if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
<> 144:ef7eb2e8f9f7 6603 {
<> 144:ef7eb2e8f9f7 6604 SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
<> 144:ef7eb2e8f9f7 6605
<> 144:ef7eb2e8f9f7 6606 if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR))
<> 144:ef7eb2e8f9f7 6607 {
<> 144:ef7eb2e8f9f7 6608 /* Delay for temperature sensor stabilization time */
<> 144:ef7eb2e8f9f7 6609 /* Compute number of CPU cycles to wait for */
<> 144:ef7eb2e8f9f7 6610 wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
<> 144:ef7eb2e8f9f7 6611 while(wait_loop_index != 0)
<> 144:ef7eb2e8f9f7 6612 {
<> 144:ef7eb2e8f9f7 6613 wait_loop_index--;
<> 144:ef7eb2e8f9f7 6614 }
<> 144:ef7eb2e8f9f7 6615 }
<> 144:ef7eb2e8f9f7 6616 }
<> 144:ef7eb2e8f9f7 6617 }
<> 144:ef7eb2e8f9f7 6618 /* if ADC1 Channel_18 is selected, enable VBAT measurement path */
<> 144:ef7eb2e8f9f7 6619 else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
<> 144:ef7eb2e8f9f7 6620 {
<> 144:ef7eb2e8f9f7 6621 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
<> 144:ef7eb2e8f9f7 6622 }
<> 144:ef7eb2e8f9f7 6623
<> 144:ef7eb2e8f9f7 6624 /* Process unlocked */
<> 144:ef7eb2e8f9f7 6625 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 6626
<> 144:ef7eb2e8f9f7 6627 /* Return function status */
<> 144:ef7eb2e8f9f7 6628 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 6629 }
<> 144:ef7eb2e8f9f7 6630 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 6631
<> 144:ef7eb2e8f9f7 6632 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 6633 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 6634 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 6635 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 6636 /**
<> 144:ef7eb2e8f9f7 6637 * @brief Configures the analog watchdog.
<> 144:ef7eb2e8f9f7 6638 * @note Possibility to update parameters on the fly:
<> 144:ef7eb2e8f9f7 6639 * This function initializes the selected analog watchdog, following
<> 144:ef7eb2e8f9f7 6640 * calls to this function can be used to reconfigure some parameters
<> 144:ef7eb2e8f9f7 6641 * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting
<> 144:ef7eb2e8f9f7 6642 * the ADC.
<> 144:ef7eb2e8f9f7 6643 * The setting of these parameters is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 6644 * For parameters constraints, see comments of structure
<> 144:ef7eb2e8f9f7 6645 * "ADC_AnalogWDGConfTypeDef".
<> 144:ef7eb2e8f9f7 6646 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 6647 * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
<> 144:ef7eb2e8f9f7 6648 * @retval HAL status
<> 144:ef7eb2e8f9f7 6649 */
<> 144:ef7eb2e8f9f7 6650 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
<> 144:ef7eb2e8f9f7 6651 {
<> 144:ef7eb2e8f9f7 6652 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 6653
<> 144:ef7eb2e8f9f7 6654 uint32_t tmpAWDHighThresholdShifted;
<> 144:ef7eb2e8f9f7 6655 uint32_t tmpAWDLowThresholdShifted;
<> 144:ef7eb2e8f9f7 6656
<> 144:ef7eb2e8f9f7 6657 uint32_t tmpADCFlagAWD2orAWD3;
<> 144:ef7eb2e8f9f7 6658 uint32_t tmpADCITAWD2orAWD3;
<> 144:ef7eb2e8f9f7 6659
<> 144:ef7eb2e8f9f7 6660 /* Check the parameters */
<> 144:ef7eb2e8f9f7 6661 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 6662 assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
<> 144:ef7eb2e8f9f7 6663 assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
<> 144:ef7eb2e8f9f7 6664 assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
<> 144:ef7eb2e8f9f7 6665
<> 144:ef7eb2e8f9f7 6666 /* Verify if threshold is within the selected ADC resolution */
<> 144:ef7eb2e8f9f7 6667 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
<> 144:ef7eb2e8f9f7 6668 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
<> 144:ef7eb2e8f9f7 6669
<> 144:ef7eb2e8f9f7 6670 if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
<> 144:ef7eb2e8f9f7 6671 (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
<> 144:ef7eb2e8f9f7 6672 (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) )
<> 144:ef7eb2e8f9f7 6673 {
<> 144:ef7eb2e8f9f7 6674 assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
<> 144:ef7eb2e8f9f7 6675 }
<> 144:ef7eb2e8f9f7 6676
<> 144:ef7eb2e8f9f7 6677 /* Process locked */
<> 144:ef7eb2e8f9f7 6678 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 6679
<> 144:ef7eb2e8f9f7 6680 /* Parameters update conditioned to ADC state: */
<> 144:ef7eb2e8f9f7 6681 /* Parameters that can be updated when ADC is disabled or enabled without */
<> 144:ef7eb2e8f9f7 6682 /* conversion on going on regular and injected groups: */
<> 144:ef7eb2e8f9f7 6683 /* - Analog watchdog channels */
<> 144:ef7eb2e8f9f7 6684 /* - Analog watchdog thresholds */
<> 144:ef7eb2e8f9f7 6685 if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
<> 144:ef7eb2e8f9f7 6686 {
<> 144:ef7eb2e8f9f7 6687
<> 144:ef7eb2e8f9f7 6688 /* Analog watchdogs configuration */
<> 144:ef7eb2e8f9f7 6689 if(AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
<> 144:ef7eb2e8f9f7 6690 {
<> 144:ef7eb2e8f9f7 6691 /* Configuration of analog watchdog: */
<> 144:ef7eb2e8f9f7 6692 /* - Set the analog watchdog enable mode: regular and/or injected */
<> 144:ef7eb2e8f9f7 6693 /* groups, one or overall group of channels. */
<> 144:ef7eb2e8f9f7 6694 /* - Set the Analog watchdog channel (is not used if watchdog */
<> 144:ef7eb2e8f9f7 6695 /* mode "all channels": ADC_CFGR_AWD1SGL=0). */
<> 144:ef7eb2e8f9f7 6696 MODIFY_REG(hadc->Instance->CFGR ,
<> 144:ef7eb2e8f9f7 6697 ADC_CFGR_AWD1SGL |
<> 144:ef7eb2e8f9f7 6698 ADC_CFGR_JAWD1EN |
<> 144:ef7eb2e8f9f7 6699 ADC_CFGR_AWD1EN |
<> 144:ef7eb2e8f9f7 6700 ADC_CFGR_AWD1CH ,
<> 144:ef7eb2e8f9f7 6701 AnalogWDGConfig->WatchdogMode |
<> 144:ef7eb2e8f9f7 6702 ADC_CFGR_AWD1CH_SHIFT(AnalogWDGConfig->Channel) );
<> 144:ef7eb2e8f9f7 6703
<> 144:ef7eb2e8f9f7 6704 /* Shift the offset in function of the selected ADC resolution: */
<> 144:ef7eb2e8f9f7 6705 /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
<> 144:ef7eb2e8f9f7 6706 /* are set to 0 */
<> 144:ef7eb2e8f9f7 6707 tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
<> 144:ef7eb2e8f9f7 6708 tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
<> 144:ef7eb2e8f9f7 6709
<> 144:ef7eb2e8f9f7 6710 /* Set the high and low thresholds */
<> 144:ef7eb2e8f9f7 6711 MODIFY_REG(hadc->Instance->TR1 ,
<> 144:ef7eb2e8f9f7 6712 ADC_TR1_HT1 |
<> 144:ef7eb2e8f9f7 6713 ADC_TR1_LT1 ,
<> 144:ef7eb2e8f9f7 6714 ADC_TRX_HIGHTHRESHOLD(tmpAWDHighThresholdShifted) |
<> 144:ef7eb2e8f9f7 6715 tmpAWDLowThresholdShifted );
<> 144:ef7eb2e8f9f7 6716
<> 144:ef7eb2e8f9f7 6717 /* Clear the ADC Analog watchdog flag (in case of left enabled by */
<> 144:ef7eb2e8f9f7 6718 /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
<> 144:ef7eb2e8f9f7 6719 /* or HAL_ADC_PollForEvent(). */
<> 144:ef7eb2e8f9f7 6720 __HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD1);
<> 144:ef7eb2e8f9f7 6721
<> 144:ef7eb2e8f9f7 6722 /* Configure ADC Analog watchdog interrupt */
<> 144:ef7eb2e8f9f7 6723 if(AnalogWDGConfig->ITMode == ENABLE)
<> 144:ef7eb2e8f9f7 6724 {
<> 144:ef7eb2e8f9f7 6725 /* Enable the ADC Analog watchdog interrupt */
<> 144:ef7eb2e8f9f7 6726 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD1);
<> 144:ef7eb2e8f9f7 6727 }
<> 144:ef7eb2e8f9f7 6728 else
<> 144:ef7eb2e8f9f7 6729 {
<> 144:ef7eb2e8f9f7 6730 /* Disable the ADC Analog watchdog interrupt */
<> 144:ef7eb2e8f9f7 6731 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD1);
<> 144:ef7eb2e8f9f7 6732 }
<> 144:ef7eb2e8f9f7 6733
<> 144:ef7eb2e8f9f7 6734 }
<> 144:ef7eb2e8f9f7 6735 /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
<> 144:ef7eb2e8f9f7 6736 else
<> 144:ef7eb2e8f9f7 6737 {
<> 144:ef7eb2e8f9f7 6738 /* Shift the threshold in function of the selected ADC resolution */
<> 144:ef7eb2e8f9f7 6739 /* have to be left-aligned on bit 7, the LSB (right bits) are set to 0 */
<> 144:ef7eb2e8f9f7 6740 tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
<> 144:ef7eb2e8f9f7 6741 tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
<> 144:ef7eb2e8f9f7 6742
<> 144:ef7eb2e8f9f7 6743 if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
<> 144:ef7eb2e8f9f7 6744 {
<> 144:ef7eb2e8f9f7 6745 /* Set the Analog watchdog channel or group of channels. This also */
<> 144:ef7eb2e8f9f7 6746 /* enables the watchdog. */
<> 144:ef7eb2e8f9f7 6747 /* Note: Conditional register reset, because several channels can be */
<> 144:ef7eb2e8f9f7 6748 /* set by successive calls of this function. */
<> 144:ef7eb2e8f9f7 6749 if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
<> 144:ef7eb2e8f9f7 6750 {
<> 144:ef7eb2e8f9f7 6751 /* Set the high and low thresholds */
<> 144:ef7eb2e8f9f7 6752 MODIFY_REG(hadc->Instance->TR2 ,
<> 144:ef7eb2e8f9f7 6753 ADC_TR2_HT2 |
<> 144:ef7eb2e8f9f7 6754 ADC_TR2_LT2 ,
<> 144:ef7eb2e8f9f7 6755 ADC_TRX_HIGHTHRESHOLD(tmpAWDHighThresholdShifted) |
<> 144:ef7eb2e8f9f7 6756 tmpAWDLowThresholdShifted );
<> 144:ef7eb2e8f9f7 6757
<> 144:ef7eb2e8f9f7 6758 SET_BIT(hadc->Instance->AWD2CR, ADC_CFGR_AWD23CR(AnalogWDGConfig->Channel));
<> 144:ef7eb2e8f9f7 6759 }
<> 144:ef7eb2e8f9f7 6760 else
<> 144:ef7eb2e8f9f7 6761 {
<> 144:ef7eb2e8f9f7 6762 CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2);
<> 144:ef7eb2e8f9f7 6763 CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
<> 144:ef7eb2e8f9f7 6764 }
<> 144:ef7eb2e8f9f7 6765
<> 144:ef7eb2e8f9f7 6766 /* Set temporary variable to flag and IT of AWD2 or AWD3 for further */
<> 144:ef7eb2e8f9f7 6767 /* settings. */
<> 144:ef7eb2e8f9f7 6768 tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD2;
<> 144:ef7eb2e8f9f7 6769 tmpADCITAWD2orAWD3 = ADC_IT_AWD2;
<> 144:ef7eb2e8f9f7 6770 }
<> 144:ef7eb2e8f9f7 6771 /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
<> 144:ef7eb2e8f9f7 6772 else
<> 144:ef7eb2e8f9f7 6773 {
<> 144:ef7eb2e8f9f7 6774 /* Set the Analog watchdog channel or group of channels. This also */
<> 144:ef7eb2e8f9f7 6775 /* enables the watchdog. */
<> 144:ef7eb2e8f9f7 6776 /* Note: Conditionnal register reset, because several channels can be */
<> 144:ef7eb2e8f9f7 6777 /* set by successive calls of this function. */
<> 144:ef7eb2e8f9f7 6778 if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
<> 144:ef7eb2e8f9f7 6779 {
<> 144:ef7eb2e8f9f7 6780 /* Set the high and low thresholds */
<> 144:ef7eb2e8f9f7 6781 MODIFY_REG(hadc->Instance->TR3 ,
<> 144:ef7eb2e8f9f7 6782 ADC_TR3_HT3 |
<> 144:ef7eb2e8f9f7 6783 ADC_TR3_LT3 ,
<> 144:ef7eb2e8f9f7 6784 ADC_TRX_HIGHTHRESHOLD(tmpAWDHighThresholdShifted) |
<> 144:ef7eb2e8f9f7 6785 tmpAWDLowThresholdShifted );
<> 144:ef7eb2e8f9f7 6786
<> 144:ef7eb2e8f9f7 6787 SET_BIT(hadc->Instance->AWD3CR, ADC_CFGR_AWD23CR(AnalogWDGConfig->Channel));
<> 144:ef7eb2e8f9f7 6788 }
<> 144:ef7eb2e8f9f7 6789 else
<> 144:ef7eb2e8f9f7 6790 {
<> 144:ef7eb2e8f9f7 6791 CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3);
<> 144:ef7eb2e8f9f7 6792 CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
<> 144:ef7eb2e8f9f7 6793 }
<> 144:ef7eb2e8f9f7 6794
<> 144:ef7eb2e8f9f7 6795 /* Set temporary variable to flag and IT of AWD2 or AWD3 for further */
<> 144:ef7eb2e8f9f7 6796 /* settings. */
<> 144:ef7eb2e8f9f7 6797 tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD3;
<> 144:ef7eb2e8f9f7 6798 tmpADCITAWD2orAWD3 = ADC_IT_AWD3;
<> 144:ef7eb2e8f9f7 6799 }
<> 144:ef7eb2e8f9f7 6800
<> 144:ef7eb2e8f9f7 6801 /* Clear the ADC Analog watchdog flag (in case of left enabled by */
<> 144:ef7eb2e8f9f7 6802 /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
<> 144:ef7eb2e8f9f7 6803 /* or HAL_ADC_PollForEvent(). */
<> 144:ef7eb2e8f9f7 6804 __HAL_ADC_CLEAR_FLAG(hadc, tmpADCFlagAWD2orAWD3);
<> 144:ef7eb2e8f9f7 6805
<> 144:ef7eb2e8f9f7 6806 /* Configure ADC Analog watchdog interrupt */
<> 144:ef7eb2e8f9f7 6807 if(AnalogWDGConfig->ITMode == ENABLE)
<> 144:ef7eb2e8f9f7 6808 {
<> 144:ef7eb2e8f9f7 6809 __HAL_ADC_ENABLE_IT(hadc, tmpADCITAWD2orAWD3);
<> 144:ef7eb2e8f9f7 6810 }
<> 144:ef7eb2e8f9f7 6811 else
<> 144:ef7eb2e8f9f7 6812 {
<> 144:ef7eb2e8f9f7 6813 __HAL_ADC_DISABLE_IT(hadc, tmpADCITAWD2orAWD3);
<> 144:ef7eb2e8f9f7 6814 }
<> 144:ef7eb2e8f9f7 6815 }
<> 144:ef7eb2e8f9f7 6816
<> 144:ef7eb2e8f9f7 6817 }
<> 144:ef7eb2e8f9f7 6818 /* If a conversion is on going on regular or injected groups, no update */
<> 144:ef7eb2e8f9f7 6819 /* could be done on neither of the AWD configuration structure parameters. */
<> 144:ef7eb2e8f9f7 6820 else
<> 144:ef7eb2e8f9f7 6821 {
<> 144:ef7eb2e8f9f7 6822 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 6823 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 6824
<> 144:ef7eb2e8f9f7 6825 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 6826 }
<> 144:ef7eb2e8f9f7 6827
<> 144:ef7eb2e8f9f7 6828
<> 144:ef7eb2e8f9f7 6829 /* Process unlocked */
<> 144:ef7eb2e8f9f7 6830 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 6831
<> 144:ef7eb2e8f9f7 6832 /* Return function status */
<> 144:ef7eb2e8f9f7 6833 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 6834 }
<> 144:ef7eb2e8f9f7 6835 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 6836 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 6837 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 6838 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 6839
<> 144:ef7eb2e8f9f7 6840 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 6841 /**
<> 144:ef7eb2e8f9f7 6842 * @brief Configures the analog watchdog.
<> 144:ef7eb2e8f9f7 6843 * @note Analog watchdog thresholds can be modified while ADC conversion
<> 144:ef7eb2e8f9f7 6844 * is on going.
<> 144:ef7eb2e8f9f7 6845 * In this case, some constraints must be taken into account:
<> 144:ef7eb2e8f9f7 6846 * the programmed threshold values are effective from the next
<> 144:ef7eb2e8f9f7 6847 * ADC EOC (end of unitary conversion).
<> 144:ef7eb2e8f9f7 6848 * Considering that registers write delay may happen due to
<> 144:ef7eb2e8f9f7 6849 * bus activity, this might cause an uncertainty on the
<> 144:ef7eb2e8f9f7 6850 * effective timing of the new programmed threshold values.
<> 144:ef7eb2e8f9f7 6851 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 6852 * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
<> 144:ef7eb2e8f9f7 6853 * @retval HAL status
<> 144:ef7eb2e8f9f7 6854 */
<> 144:ef7eb2e8f9f7 6855 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
<> 144:ef7eb2e8f9f7 6856 {
<> 144:ef7eb2e8f9f7 6857 /* Check the parameters */
<> 144:ef7eb2e8f9f7 6858 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 6859 assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
<> 144:ef7eb2e8f9f7 6860 assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
<> 144:ef7eb2e8f9f7 6861 assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold));
<> 144:ef7eb2e8f9f7 6862 assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold));
<> 144:ef7eb2e8f9f7 6863
<> 144:ef7eb2e8f9f7 6864 if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
<> 144:ef7eb2e8f9f7 6865 (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
<> 144:ef7eb2e8f9f7 6866 (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) )
<> 144:ef7eb2e8f9f7 6867 {
<> 144:ef7eb2e8f9f7 6868 assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
<> 144:ef7eb2e8f9f7 6869 }
<> 144:ef7eb2e8f9f7 6870
<> 144:ef7eb2e8f9f7 6871 /* Process locked */
<> 144:ef7eb2e8f9f7 6872 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 6873
<> 144:ef7eb2e8f9f7 6874 /* Analog watchdog configuration */
<> 144:ef7eb2e8f9f7 6875
<> 144:ef7eb2e8f9f7 6876 /* Configure ADC Analog watchdog interrupt */
<> 144:ef7eb2e8f9f7 6877 if(AnalogWDGConfig->ITMode == ENABLE)
<> 144:ef7eb2e8f9f7 6878 {
<> 144:ef7eb2e8f9f7 6879 /* Enable the ADC Analog watchdog interrupt */
<> 144:ef7eb2e8f9f7 6880 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
<> 144:ef7eb2e8f9f7 6881 }
<> 144:ef7eb2e8f9f7 6882 else
<> 144:ef7eb2e8f9f7 6883 {
<> 144:ef7eb2e8f9f7 6884 /* Disable the ADC Analog watchdog interrupt */
<> 144:ef7eb2e8f9f7 6885 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
<> 144:ef7eb2e8f9f7 6886 }
<> 144:ef7eb2e8f9f7 6887
<> 144:ef7eb2e8f9f7 6888 /* Configuration of analog watchdog: */
<> 144:ef7eb2e8f9f7 6889 /* - Set the analog watchdog enable mode: regular and/or injected groups, */
<> 144:ef7eb2e8f9f7 6890 /* one or all channels. */
<> 144:ef7eb2e8f9f7 6891 /* - Set the Analog watchdog channel (is not used if watchdog */
<> 144:ef7eb2e8f9f7 6892 /* mode "all channels": ADC_CFGR_AWD1SGL=0). */
<> 144:ef7eb2e8f9f7 6893 MODIFY_REG(hadc->Instance->CR1 ,
<> 144:ef7eb2e8f9f7 6894 ADC_CR1_AWDSGL |
<> 144:ef7eb2e8f9f7 6895 ADC_CR1_JAWDEN |
<> 144:ef7eb2e8f9f7 6896 ADC_CR1_AWDEN |
<> 144:ef7eb2e8f9f7 6897 ADC_CR1_AWDCH ,
<> 144:ef7eb2e8f9f7 6898 AnalogWDGConfig->WatchdogMode |
<> 144:ef7eb2e8f9f7 6899 AnalogWDGConfig->Channel );
<> 144:ef7eb2e8f9f7 6900
<> 144:ef7eb2e8f9f7 6901 /* Set the high threshold */
<> 144:ef7eb2e8f9f7 6902 WRITE_REG(hadc->Instance->HTR, AnalogWDGConfig->HighThreshold);
<> 144:ef7eb2e8f9f7 6903
<> 144:ef7eb2e8f9f7 6904 /* Set the low threshold */
<> 144:ef7eb2e8f9f7 6905 WRITE_REG(hadc->Instance->LTR, AnalogWDGConfig->LowThreshold);
<> 144:ef7eb2e8f9f7 6906
<> 144:ef7eb2e8f9f7 6907 /* Process unlocked */
<> 144:ef7eb2e8f9f7 6908 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 6909
<> 144:ef7eb2e8f9f7 6910 /* Return function status */
<> 144:ef7eb2e8f9f7 6911 return HAL_OK;
<> 144:ef7eb2e8f9f7 6912 }
<> 144:ef7eb2e8f9f7 6913 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 6914
<> 144:ef7eb2e8f9f7 6915
<> 144:ef7eb2e8f9f7 6916 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 6917 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 6918 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
<> 144:ef7eb2e8f9f7 6919 /**
<> 144:ef7eb2e8f9f7 6920 * @brief Enable ADC multimode and configure multimode parameters
<> 144:ef7eb2e8f9f7 6921 * @note Possibility to update parameters on the fly:
<> 144:ef7eb2e8f9f7 6922 * This function initializes multimode parameters, following
<> 144:ef7eb2e8f9f7 6923 * calls to this function can be used to reconfigure some parameters
<> 144:ef7eb2e8f9f7 6924 * of structure "ADC_MultiModeTypeDef" on the fly, without reseting
<> 144:ef7eb2e8f9f7 6925 * the ADCs (both ADCs of the common group).
<> 144:ef7eb2e8f9f7 6926 * The setting of these parameters is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 6927 * For parameters constraints, see comments of structure
<> 144:ef7eb2e8f9f7 6928 * "ADC_MultiModeTypeDef".
<> 144:ef7eb2e8f9f7 6929 * @note To change back configuration from multimode to single mode, ADC must
<> 144:ef7eb2e8f9f7 6930 * be reset (using function HAL_ADC_Init() ).
<> 144:ef7eb2e8f9f7 6931 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 6932 * @param multimode : Structure of ADC multimode configuration
<> 144:ef7eb2e8f9f7 6933 * @retval HAL status
<> 144:ef7eb2e8f9f7 6934 */
<> 144:ef7eb2e8f9f7 6935 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
<> 144:ef7eb2e8f9f7 6936 {
<> 144:ef7eb2e8f9f7 6937 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 6938 ADC_Common_TypeDef *tmpADC_Common;
<> 144:ef7eb2e8f9f7 6939 ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
<> 144:ef7eb2e8f9f7 6940
<> 144:ef7eb2e8f9f7 6941 /* Check the parameters */
<> 144:ef7eb2e8f9f7 6942 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 6943 assert_param(IS_ADC_MODE(multimode->Mode));
<> 144:ef7eb2e8f9f7 6944 if(multimode->Mode != ADC_MODE_INDEPENDENT)
<> 144:ef7eb2e8f9f7 6945 {
<> 144:ef7eb2e8f9f7 6946 assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));
<> 144:ef7eb2e8f9f7 6947 assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
<> 144:ef7eb2e8f9f7 6948 }
<> 144:ef7eb2e8f9f7 6949
<> 144:ef7eb2e8f9f7 6950 /* Process locked */
<> 144:ef7eb2e8f9f7 6951 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 6952
<> 144:ef7eb2e8f9f7 6953
<> 144:ef7eb2e8f9f7 6954 /* Set handle of the other ADC sharing the same common register */
<> 144:ef7eb2e8f9f7 6955 ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
<> 144:ef7eb2e8f9f7 6956
<> 144:ef7eb2e8f9f7 6957 /* Parameters update conditioned to ADC state: */
<> 144:ef7eb2e8f9f7 6958 /* Parameters that can be updated when ADC is disabled or enabled without */
<> 144:ef7eb2e8f9f7 6959 /* conversion on going on regular group: */
<> 144:ef7eb2e8f9f7 6960 /* - Multimode DMA configuration */
<> 144:ef7eb2e8f9f7 6961 /* - Multimode DMA mode */
<> 144:ef7eb2e8f9f7 6962 if ( (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<> 144:ef7eb2e8f9f7 6963 && (ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSharingSameCommonRegister) == RESET) )
<> 144:ef7eb2e8f9f7 6964 {
<> 144:ef7eb2e8f9f7 6965 /* Pointer to the common control register to which is belonging hadc */
<> 144:ef7eb2e8f9f7 6966 /* (Depending on STM32F3 product, there may have up to 4 ADC and 2 common */
<> 144:ef7eb2e8f9f7 6967 /* control registers) */
<> 144:ef7eb2e8f9f7 6968 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
<> 144:ef7eb2e8f9f7 6969
<> 144:ef7eb2e8f9f7 6970 /* If multimode is selected, configure all multimode paramaters. */
<> 144:ef7eb2e8f9f7 6971 /* Otherwise, reset multimode parameters (can be used in case of */
<> 144:ef7eb2e8f9f7 6972 /* transition from multimode to independent mode). */
<> 144:ef7eb2e8f9f7 6973 if(multimode->Mode != ADC_MODE_INDEPENDENT)
<> 144:ef7eb2e8f9f7 6974 {
<> 144:ef7eb2e8f9f7 6975 /* Configuration of ADC common group ADC1&ADC2, ADC3&ADC4 if available */
<> 144:ef7eb2e8f9f7 6976 /* (ADC2, ADC3, ADC4 availability depends on STM32 product) */
<> 144:ef7eb2e8f9f7 6977 /* - DMA access mode */
<> 144:ef7eb2e8f9f7 6978 MODIFY_REG(tmpADC_Common->CCR ,
<> 144:ef7eb2e8f9f7 6979 ADC_CCR_MDMA |
<> 144:ef7eb2e8f9f7 6980 ADC_CCR_DMACFG ,
<> 144:ef7eb2e8f9f7 6981 multimode->DMAAccessMode |
<> 144:ef7eb2e8f9f7 6982 ADC_CCR_MULTI_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
<> 144:ef7eb2e8f9f7 6983
<> 144:ef7eb2e8f9f7 6984 /* Parameters that can be updated only when ADC is disabled: */
<> 144:ef7eb2e8f9f7 6985 /* - Multimode mode selection */
<> 144:ef7eb2e8f9f7 6986 /* - Set delay between two sampling phases */
<> 144:ef7eb2e8f9f7 6987 /* Note: Delay range depends on selected resolution: */
<> 144:ef7eb2e8f9f7 6988 /* from 1 to 12 clock cycles for 12 bits */
<> 144:ef7eb2e8f9f7 6989 /* from 1 to 10 clock cycles for 10 bits, */
<> 144:ef7eb2e8f9f7 6990 /* from 1 to 8 clock cycles for 8 bits */
<> 144:ef7eb2e8f9f7 6991 /* from 1 to 6 clock cycles for 6 bits */
<> 144:ef7eb2e8f9f7 6992 /* If a higher delay is selected, it will be clamped to maximum delay */
<> 144:ef7eb2e8f9f7 6993 /* range */
<> 144:ef7eb2e8f9f7 6994 /* Note: If ADC is not in the appropriate state to modify these */
<> 144:ef7eb2e8f9f7 6995 /* parameters, their setting is bypassed without error reporting */
<> 144:ef7eb2e8f9f7 6996 /* (as it can be the expected behaviour in case of intended action */
<> 144:ef7eb2e8f9f7 6997 /* to update parameter above (which fulfills the ADC state */
<> 144:ef7eb2e8f9f7 6998 /* condition: no conversion on going on group regular) */
<> 144:ef7eb2e8f9f7 6999 /* on the fly). */
<> 144:ef7eb2e8f9f7 7000 if ((ADC_IS_ENABLE(hadc) == RESET) &&
<> 144:ef7eb2e8f9f7 7001 (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) )
<> 144:ef7eb2e8f9f7 7002 {
<> 144:ef7eb2e8f9f7 7003 MODIFY_REG(tmpADC_Common->CCR ,
<> 144:ef7eb2e8f9f7 7004 ADC_CCR_MULTI |
<> 144:ef7eb2e8f9f7 7005 ADC_CCR_DELAY ,
<> 144:ef7eb2e8f9f7 7006 multimode->Mode |
<> 144:ef7eb2e8f9f7 7007 multimode->TwoSamplingDelay );
<> 144:ef7eb2e8f9f7 7008 }
<> 144:ef7eb2e8f9f7 7009 }
<> 144:ef7eb2e8f9f7 7010 else /* ADC_MODE_INDEPENDENT */
<> 144:ef7eb2e8f9f7 7011 {
<> 144:ef7eb2e8f9f7 7012 CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
<> 144:ef7eb2e8f9f7 7013
<> 144:ef7eb2e8f9f7 7014 /* Parameters that can be updated only when ADC is disabled: */
<> 144:ef7eb2e8f9f7 7015 /* - Multimode mode selection */
<> 144:ef7eb2e8f9f7 7016 /* - Multimode delay */
<> 144:ef7eb2e8f9f7 7017 if ((ADC_IS_ENABLE(hadc) == RESET) &&
<> 144:ef7eb2e8f9f7 7018 (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) )
<> 144:ef7eb2e8f9f7 7019 {
<> 144:ef7eb2e8f9f7 7020 CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI | ADC_CCR_DELAY);
<> 144:ef7eb2e8f9f7 7021 }
<> 144:ef7eb2e8f9f7 7022 }
<> 144:ef7eb2e8f9f7 7023 }
<> 144:ef7eb2e8f9f7 7024 /* If one of the ADC sharing the same common group is enabled, no update */
<> 144:ef7eb2e8f9f7 7025 /* could be done on neither of the multimode structure parameters. */
<> 144:ef7eb2e8f9f7 7026 else
<> 144:ef7eb2e8f9f7 7027 {
<> 144:ef7eb2e8f9f7 7028 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 7029 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 7030
<> 144:ef7eb2e8f9f7 7031 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 7032 }
<> 144:ef7eb2e8f9f7 7033
<> 144:ef7eb2e8f9f7 7034
<> 144:ef7eb2e8f9f7 7035 /* Process unlocked */
<> 144:ef7eb2e8f9f7 7036 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 7037
<> 144:ef7eb2e8f9f7 7038 /* Return function status */
<> 144:ef7eb2e8f9f7 7039 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 7040 }
<> 144:ef7eb2e8f9f7 7041 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 7042 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 7043 /* STM32F303x8 || STM32F328xx || STM32F334x8 */
<> 144:ef7eb2e8f9f7 7044
<> 144:ef7eb2e8f9f7 7045 /**
<> 144:ef7eb2e8f9f7 7046 * @}
<> 144:ef7eb2e8f9f7 7047 */
<> 144:ef7eb2e8f9f7 7048
<> 144:ef7eb2e8f9f7 7049 /**
<> 144:ef7eb2e8f9f7 7050 * @}
<> 144:ef7eb2e8f9f7 7051 */
<> 144:ef7eb2e8f9f7 7052
<> 144:ef7eb2e8f9f7 7053 /** @defgroup ADCEx_Private_Functions ADCEx Private Functions
<> 144:ef7eb2e8f9f7 7054 * @{
<> 144:ef7eb2e8f9f7 7055 */
<> 144:ef7eb2e8f9f7 7056 /**
<> 144:ef7eb2e8f9f7 7057 * @brief DMA transfer complete callback.
<> 144:ef7eb2e8f9f7 7058 * @param hdma: pointer to DMA handle.
<> 144:ef7eb2e8f9f7 7059 * @retval None
<> 144:ef7eb2e8f9f7 7060 */
<> 144:ef7eb2e8f9f7 7061 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 7062 {
<> 144:ef7eb2e8f9f7 7063 /* Retrieve ADC handle corresponding to current DMA handle */
<> 144:ef7eb2e8f9f7 7064 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 7065
<> 144:ef7eb2e8f9f7 7066 /* Update state machine on conversion status if not in error state */
<> 144:ef7eb2e8f9f7 7067 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
<> 144:ef7eb2e8f9f7 7068 {
<> 144:ef7eb2e8f9f7 7069 /* Update ADC state machine */
<> 144:ef7eb2e8f9f7 7070 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
<> 144:ef7eb2e8f9f7 7071
<> 144:ef7eb2e8f9f7 7072 /* Determine whether any further conversion upcoming on group regular */
<> 144:ef7eb2e8f9f7 7073 /* by external trigger, continuous mode or scan sequence on going. */
<> 144:ef7eb2e8f9f7 7074 /* Note: On STM32F1 devices, in case of sequencer enabled */
<> 144:ef7eb2e8f9f7 7075 /* (several ranks selected), end of conversion flag is raised */
<> 144:ef7eb2e8f9f7 7076 /* at the end of the sequence. */
<> 144:ef7eb2e8f9f7 7077 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 144:ef7eb2e8f9f7 7078 (hadc->Init.ContinuousConvMode == DISABLE) )
<> 144:ef7eb2e8f9f7 7079 {
<> 144:ef7eb2e8f9f7 7080 /* Set ADC state */
<> 144:ef7eb2e8f9f7 7081 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 7082
<> 144:ef7eb2e8f9f7 7083 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<> 144:ef7eb2e8f9f7 7084 {
<> 144:ef7eb2e8f9f7 7085 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 7086 }
<> 144:ef7eb2e8f9f7 7087 }
<> 144:ef7eb2e8f9f7 7088
<> 144:ef7eb2e8f9f7 7089 /* Conversion complete callback */
<> 144:ef7eb2e8f9f7 7090 HAL_ADC_ConvCpltCallback(hadc);
<> 144:ef7eb2e8f9f7 7091 }
<> 144:ef7eb2e8f9f7 7092 else
<> 144:ef7eb2e8f9f7 7093 {
<> 144:ef7eb2e8f9f7 7094 /* Call DMA error callback */
<> 144:ef7eb2e8f9f7 7095 hadc->DMA_Handle->XferErrorCallback(hdma);
<> 144:ef7eb2e8f9f7 7096 }
<> 144:ef7eb2e8f9f7 7097 }
<> 144:ef7eb2e8f9f7 7098
<> 144:ef7eb2e8f9f7 7099 /**
<> 144:ef7eb2e8f9f7 7100 * @brief DMA half transfer complete callback.
<> 144:ef7eb2e8f9f7 7101 * @param hdma: pointer to DMA handle.
<> 144:ef7eb2e8f9f7 7102 * @retval None
<> 144:ef7eb2e8f9f7 7103 */
<> 144:ef7eb2e8f9f7 7104 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 7105 {
<> 144:ef7eb2e8f9f7 7106 /* Retrieve ADC handle corresponding to current DMA handle */
<> 144:ef7eb2e8f9f7 7107 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 7108
<> 144:ef7eb2e8f9f7 7109 /* Half conversion callback */
<> 144:ef7eb2e8f9f7 7110 HAL_ADC_ConvHalfCpltCallback(hadc);
<> 144:ef7eb2e8f9f7 7111 }
<> 144:ef7eb2e8f9f7 7112
<> 144:ef7eb2e8f9f7 7113 /**
<> 144:ef7eb2e8f9f7 7114 * @brief DMA error callback
<> 144:ef7eb2e8f9f7 7115 * @param hdma: pointer to DMA handle.
<> 144:ef7eb2e8f9f7 7116 * @retval None
<> 144:ef7eb2e8f9f7 7117 */
<> 144:ef7eb2e8f9f7 7118 static void ADC_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 7119 {
<> 144:ef7eb2e8f9f7 7120 /* Retrieve ADC handle corresponding to current DMA handle */
<> 144:ef7eb2e8f9f7 7121 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 7122
<> 144:ef7eb2e8f9f7 7123 /* Set ADC state */
<> 144:ef7eb2e8f9f7 7124 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
<> 144:ef7eb2e8f9f7 7125
<> 144:ef7eb2e8f9f7 7126 /* Set ADC error code to DMA error */
<> 144:ef7eb2e8f9f7 7127 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
<> 144:ef7eb2e8f9f7 7128
<> 144:ef7eb2e8f9f7 7129 /* Error callback */
<> 144:ef7eb2e8f9f7 7130 HAL_ADC_ErrorCallback(hadc);
<> 144:ef7eb2e8f9f7 7131 }
<> 144:ef7eb2e8f9f7 7132
<> 144:ef7eb2e8f9f7 7133 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
<> 144:ef7eb2e8f9f7 7134 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
<> 144:ef7eb2e8f9f7 7135 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
<> 144:ef7eb2e8f9f7 7136 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 7137 /**
<> 144:ef7eb2e8f9f7 7138 * @brief Enable the selected ADC.
<> 144:ef7eb2e8f9f7 7139 * @note Prerequisite condition to use this function: ADC must be disabled
<> 144:ef7eb2e8f9f7 7140 * and voltage regulator must be enabled (done into HAL_ADC_Init()).
<> 144:ef7eb2e8f9f7 7141 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 7142 * @retval HAL status.
<> 144:ef7eb2e8f9f7 7143 */
<> 144:ef7eb2e8f9f7 7144 static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 7145 {
<> 144:ef7eb2e8f9f7 7146 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 7147
<> 144:ef7eb2e8f9f7 7148 /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
<> 144:ef7eb2e8f9f7 7149 /* enabling phase not yet completed: flag ADC ready not yet set). */
<> 144:ef7eb2e8f9f7 7150 /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
<> 144:ef7eb2e8f9f7 7151 /* causes: ADC clock not running, ...). */
<> 144:ef7eb2e8f9f7 7152 if (ADC_IS_ENABLE(hadc) == RESET)
<> 144:ef7eb2e8f9f7 7153 {
<> 144:ef7eb2e8f9f7 7154 /* Check if conditions to enable the ADC are fulfilled */
<> 144:ef7eb2e8f9f7 7155 if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
<> 144:ef7eb2e8f9f7 7156 {
<> 144:ef7eb2e8f9f7 7157 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 7158 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 7159
<> 144:ef7eb2e8f9f7 7160 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 7161 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 7162
<> 144:ef7eb2e8f9f7 7163 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 7164 }
<> 144:ef7eb2e8f9f7 7165
<> 144:ef7eb2e8f9f7 7166 /* Enable the ADC peripheral */
<> 144:ef7eb2e8f9f7 7167 __HAL_ADC_ENABLE(hadc);
<> 144:ef7eb2e8f9f7 7168
<> 144:ef7eb2e8f9f7 7169 /* Wait for ADC effectively enabled */
<> 144:ef7eb2e8f9f7 7170 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 7171
<> 144:ef7eb2e8f9f7 7172 while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
<> 144:ef7eb2e8f9f7 7173 {
<> 144:ef7eb2e8f9f7 7174 if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
<> 144:ef7eb2e8f9f7 7175 {
<> 144:ef7eb2e8f9f7 7176 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 7177 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 7178
<> 144:ef7eb2e8f9f7 7179 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 7180 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 7181
<> 144:ef7eb2e8f9f7 7182 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 7183 }
<> 144:ef7eb2e8f9f7 7184 }
<> 144:ef7eb2e8f9f7 7185 }
<> 144:ef7eb2e8f9f7 7186
<> 144:ef7eb2e8f9f7 7187 /* Return HAL status */
<> 144:ef7eb2e8f9f7 7188 return HAL_OK;
<> 144:ef7eb2e8f9f7 7189 }
<> 144:ef7eb2e8f9f7 7190
<> 144:ef7eb2e8f9f7 7191 /**
<> 144:ef7eb2e8f9f7 7192 * @brief Disable the selected ADC.
<> 144:ef7eb2e8f9f7 7193 * @note Prerequisite condition to use this function: ADC conversions must be
<> 144:ef7eb2e8f9f7 7194 * stopped.
<> 144:ef7eb2e8f9f7 7195 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 7196 * @retval HAL status.
<> 144:ef7eb2e8f9f7 7197 */
<> 144:ef7eb2e8f9f7 7198 static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 7199 {
<> 144:ef7eb2e8f9f7 7200 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 7201
<> 144:ef7eb2e8f9f7 7202 /* Verification if ADC is not already disabled: */
<> 144:ef7eb2e8f9f7 7203 /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
<> 144:ef7eb2e8f9f7 7204 /* disabled. */
<> 144:ef7eb2e8f9f7 7205 if (ADC_IS_ENABLE(hadc) != RESET )
<> 144:ef7eb2e8f9f7 7206 {
<> 144:ef7eb2e8f9f7 7207 /* Check if conditions to disable the ADC are fulfilled */
<> 144:ef7eb2e8f9f7 7208 if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
<> 144:ef7eb2e8f9f7 7209 {
<> 144:ef7eb2e8f9f7 7210 /* Disable the ADC peripheral */
<> 144:ef7eb2e8f9f7 7211 __HAL_ADC_DISABLE(hadc);
<> 144:ef7eb2e8f9f7 7212 }
<> 144:ef7eb2e8f9f7 7213 else
<> 144:ef7eb2e8f9f7 7214 {
<> 144:ef7eb2e8f9f7 7215 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 7216 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 7217
<> 144:ef7eb2e8f9f7 7218 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 7219 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 7220
<> 144:ef7eb2e8f9f7 7221 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 7222 }
<> 144:ef7eb2e8f9f7 7223
<> 144:ef7eb2e8f9f7 7224 /* Wait for ADC effectively disabled */
<> 144:ef7eb2e8f9f7 7225 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 7226
<> 144:ef7eb2e8f9f7 7227 while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
<> 144:ef7eb2e8f9f7 7228 {
<> 144:ef7eb2e8f9f7 7229 if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
<> 144:ef7eb2e8f9f7 7230 {
<> 144:ef7eb2e8f9f7 7231 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 7232 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 7233
<> 144:ef7eb2e8f9f7 7234 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 7235 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 7236
<> 144:ef7eb2e8f9f7 7237 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 7238 }
<> 144:ef7eb2e8f9f7 7239 }
<> 144:ef7eb2e8f9f7 7240 }
<> 144:ef7eb2e8f9f7 7241
<> 144:ef7eb2e8f9f7 7242 /* Return HAL status */
<> 144:ef7eb2e8f9f7 7243 return HAL_OK;
<> 144:ef7eb2e8f9f7 7244 }
<> 144:ef7eb2e8f9f7 7245
<> 144:ef7eb2e8f9f7 7246
<> 144:ef7eb2e8f9f7 7247 /**
<> 144:ef7eb2e8f9f7 7248 * @brief Stop ADC conversion.
<> 144:ef7eb2e8f9f7 7249 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 7250 * @param ConversionGroup: ADC group regular and/or injected.
<> 144:ef7eb2e8f9f7 7251 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 7252 * @arg ADC_REGULAR_GROUP: ADC regular conversion type.
<> 144:ef7eb2e8f9f7 7253 * @arg ADC_INJECTED_GROUP: ADC injected conversion type.
<> 144:ef7eb2e8f9f7 7254 * @arg ADC_REGULAR_INJECTED_GROUP: ADC regular and injected conversion type.
<> 144:ef7eb2e8f9f7 7255 * @retval HAL status.
<> 144:ef7eb2e8f9f7 7256 */
<> 144:ef7eb2e8f9f7 7257 static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup)
<> 144:ef7eb2e8f9f7 7258 {
<> 144:ef7eb2e8f9f7 7259 uint32_t tmp_ADC_CR_ADSTART_JADSTART = 0;
<> 144:ef7eb2e8f9f7 7260 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 7261 uint32_t Conversion_Timeout_CPU_cycles = 0;
<> 144:ef7eb2e8f9f7 7262
<> 144:ef7eb2e8f9f7 7263 /* Check the parameters */
<> 144:ef7eb2e8f9f7 7264 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 7265 assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
<> 144:ef7eb2e8f9f7 7266
<> 144:ef7eb2e8f9f7 7267 /* Verification if ADC is not already stopped (on regular and injected */
<> 144:ef7eb2e8f9f7 7268 /* groups) to bypass this function if not needed. */
<> 144:ef7eb2e8f9f7 7269 if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc))
<> 144:ef7eb2e8f9f7 7270 {
<> 144:ef7eb2e8f9f7 7271 /* Particular case of continuous auto-injection mode combined with */
<> 144:ef7eb2e8f9f7 7272 /* auto-delay mode. */
<> 144:ef7eb2e8f9f7 7273 /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
<> 144:ef7eb2e8f9f7 7274 /* injected group stop ADC_CR_JADSTP). */
<> 144:ef7eb2e8f9f7 7275 /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */
<> 144:ef7eb2e8f9f7 7276 /* (see reference manual). */
<> 144:ef7eb2e8f9f7 7277 if ((HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_JAUTO)) &&
<> 144:ef7eb2e8f9f7 7278 (hadc->Init.ContinuousConvMode==ENABLE) &&
<> 144:ef7eb2e8f9f7 7279 (hadc->Init.LowPowerAutoWait==ENABLE) )
<> 144:ef7eb2e8f9f7 7280 {
<> 144:ef7eb2e8f9f7 7281 /* Use stop of regular group */
<> 144:ef7eb2e8f9f7 7282 ConversionGroup = ADC_REGULAR_GROUP;
<> 144:ef7eb2e8f9f7 7283
<> 144:ef7eb2e8f9f7 7284 /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
<> 144:ef7eb2e8f9f7 7285 while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == RESET)
<> 144:ef7eb2e8f9f7 7286 {
<> 144:ef7eb2e8f9f7 7287 if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES *4))
<> 144:ef7eb2e8f9f7 7288 {
<> 144:ef7eb2e8f9f7 7289 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 7290 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 7291
<> 144:ef7eb2e8f9f7 7292 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 7293 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 7294
<> 144:ef7eb2e8f9f7 7295 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 7296 }
<> 144:ef7eb2e8f9f7 7297 Conversion_Timeout_CPU_cycles ++;
<> 144:ef7eb2e8f9f7 7298 }
<> 144:ef7eb2e8f9f7 7299
<> 144:ef7eb2e8f9f7 7300 /* Clear JEOS */
<> 144:ef7eb2e8f9f7 7301 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
<> 144:ef7eb2e8f9f7 7302 }
<> 144:ef7eb2e8f9f7 7303
<> 144:ef7eb2e8f9f7 7304 /* Stop potential conversion on going on regular group */
<> 144:ef7eb2e8f9f7 7305 if (ConversionGroup != ADC_INJECTED_GROUP)
<> 144:ef7eb2e8f9f7 7306 {
<> 144:ef7eb2e8f9f7 7307 /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
<> 144:ef7eb2e8f9f7 7308 if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) &&
<> 144:ef7eb2e8f9f7 7309 HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
<> 144:ef7eb2e8f9f7 7310 {
<> 144:ef7eb2e8f9f7 7311 /* Stop conversions on regular group */
<> 144:ef7eb2e8f9f7 7312 hadc->Instance->CR |= ADC_CR_ADSTP;
<> 144:ef7eb2e8f9f7 7313 }
<> 144:ef7eb2e8f9f7 7314 }
<> 144:ef7eb2e8f9f7 7315
<> 144:ef7eb2e8f9f7 7316 /* Stop potential conversion on going on injected group */
<> 144:ef7eb2e8f9f7 7317 if (ConversionGroup != ADC_REGULAR_GROUP)
<> 144:ef7eb2e8f9f7 7318 {
<> 144:ef7eb2e8f9f7 7319 /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
<> 144:ef7eb2e8f9f7 7320 if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_JADSTART) &&
<> 144:ef7eb2e8f9f7 7321 HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
<> 144:ef7eb2e8f9f7 7322 {
<> 144:ef7eb2e8f9f7 7323 /* Stop conversions on injected group */
<> 144:ef7eb2e8f9f7 7324 hadc->Instance->CR |= ADC_CR_JADSTP;
<> 144:ef7eb2e8f9f7 7325 }
<> 144:ef7eb2e8f9f7 7326 }
<> 144:ef7eb2e8f9f7 7327
<> 144:ef7eb2e8f9f7 7328 /* Selection of start and stop bits in function of regular or injected group */
<> 144:ef7eb2e8f9f7 7329 switch(ConversionGroup)
<> 144:ef7eb2e8f9f7 7330 {
<> 144:ef7eb2e8f9f7 7331 case ADC_REGULAR_INJECTED_GROUP:
<> 144:ef7eb2e8f9f7 7332 tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
<> 144:ef7eb2e8f9f7 7333 break;
<> 144:ef7eb2e8f9f7 7334 case ADC_INJECTED_GROUP:
<> 144:ef7eb2e8f9f7 7335 tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
<> 144:ef7eb2e8f9f7 7336 break;
<> 144:ef7eb2e8f9f7 7337 /* Case ADC_REGULAR_GROUP */
<> 144:ef7eb2e8f9f7 7338 default:
<> 144:ef7eb2e8f9f7 7339 tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
<> 144:ef7eb2e8f9f7 7340 break;
<> 144:ef7eb2e8f9f7 7341 }
<> 144:ef7eb2e8f9f7 7342
<> 144:ef7eb2e8f9f7 7343 /* Wait for conversion effectively stopped */
<> 144:ef7eb2e8f9f7 7344 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 7345
<> 144:ef7eb2e8f9f7 7346 while((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != RESET)
<> 144:ef7eb2e8f9f7 7347 {
<> 144:ef7eb2e8f9f7 7348 if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
<> 144:ef7eb2e8f9f7 7349 {
<> 144:ef7eb2e8f9f7 7350 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 7351 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 7352
<> 144:ef7eb2e8f9f7 7353 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 7354 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 7355
<> 144:ef7eb2e8f9f7 7356 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 7357 }
<> 144:ef7eb2e8f9f7 7358 }
<> 144:ef7eb2e8f9f7 7359
<> 144:ef7eb2e8f9f7 7360 }
<> 144:ef7eb2e8f9f7 7361
<> 144:ef7eb2e8f9f7 7362 /* Return HAL status */
<> 144:ef7eb2e8f9f7 7363 return HAL_OK;
<> 144:ef7eb2e8f9f7 7364 }
<> 144:ef7eb2e8f9f7 7365 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 7366 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 7367 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 7368 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 7369
<> 144:ef7eb2e8f9f7 7370 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 7371 /**
<> 144:ef7eb2e8f9f7 7372 * @brief Enable the selected ADC.
<> 144:ef7eb2e8f9f7 7373 * @note Prerequisite condition to use this function: ADC must be disabled
<> 144:ef7eb2e8f9f7 7374 * and voltage regulator must be enabled (done into HAL_ADC_Init()).
<> 144:ef7eb2e8f9f7 7375 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 7376 * @retval HAL status.
<> 144:ef7eb2e8f9f7 7377 */
<> 144:ef7eb2e8f9f7 7378 static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 7379 {
<> 144:ef7eb2e8f9f7 7380 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 7381 __IO uint32_t wait_loop_index = 0;
<> 144:ef7eb2e8f9f7 7382
<> 144:ef7eb2e8f9f7 7383 /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
<> 144:ef7eb2e8f9f7 7384 /* enabling phase not yet completed: flag ADC ready not yet set). */
<> 144:ef7eb2e8f9f7 7385 /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
<> 144:ef7eb2e8f9f7 7386 /* causes: ADC clock not running, ...). */
<> 144:ef7eb2e8f9f7 7387 if (ADC_IS_ENABLE(hadc) == RESET)
<> 144:ef7eb2e8f9f7 7388 {
<> 144:ef7eb2e8f9f7 7389 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 7390 __HAL_ADC_ENABLE(hadc);
<> 144:ef7eb2e8f9f7 7391
<> 144:ef7eb2e8f9f7 7392 /* Delay for ADC stabilization time */
<> 144:ef7eb2e8f9f7 7393 /* Compute number of CPU cycles to wait for */
<> 144:ef7eb2e8f9f7 7394 wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
<> 144:ef7eb2e8f9f7 7395 while(wait_loop_index != 0)
<> 144:ef7eb2e8f9f7 7396 {
<> 144:ef7eb2e8f9f7 7397 wait_loop_index--;
<> 144:ef7eb2e8f9f7 7398 }
<> 144:ef7eb2e8f9f7 7399
<> 144:ef7eb2e8f9f7 7400 /* Get tick count */
<> 144:ef7eb2e8f9f7 7401 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 7402
<> 144:ef7eb2e8f9f7 7403 /* Wait for ADC effectively enabled */
<> 144:ef7eb2e8f9f7 7404 while(ADC_IS_ENABLE(hadc) == RESET)
<> 144:ef7eb2e8f9f7 7405 {
<> 144:ef7eb2e8f9f7 7406 if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
<> 144:ef7eb2e8f9f7 7407 {
<> 144:ef7eb2e8f9f7 7408 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 7409 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 7410
<> 144:ef7eb2e8f9f7 7411 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 7412 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 7413
<> 144:ef7eb2e8f9f7 7414 /* Process unlocked */
<> 144:ef7eb2e8f9f7 7415 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 7416
<> 144:ef7eb2e8f9f7 7417 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 7418 }
<> 144:ef7eb2e8f9f7 7419 }
<> 144:ef7eb2e8f9f7 7420 }
<> 144:ef7eb2e8f9f7 7421
<> 144:ef7eb2e8f9f7 7422 /* Return HAL status */
<> 144:ef7eb2e8f9f7 7423 return HAL_OK;
<> 144:ef7eb2e8f9f7 7424 }
<> 144:ef7eb2e8f9f7 7425
<> 144:ef7eb2e8f9f7 7426 /**
<> 144:ef7eb2e8f9f7 7427 * @brief Stop ADC conversion and disable the selected ADC
<> 144:ef7eb2e8f9f7 7428 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 7429 * @retval HAL status.
<> 144:ef7eb2e8f9f7 7430 */
<> 144:ef7eb2e8f9f7 7431 static HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 7432 {
<> 144:ef7eb2e8f9f7 7433 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 7434
<> 144:ef7eb2e8f9f7 7435 /* Verification if ADC is not already disabled: */
<> 144:ef7eb2e8f9f7 7436 if (ADC_IS_ENABLE(hadc) != RESET)
<> 144:ef7eb2e8f9f7 7437 {
<> 144:ef7eb2e8f9f7 7438 /* Disable the ADC peripheral */
<> 144:ef7eb2e8f9f7 7439 __HAL_ADC_DISABLE(hadc);
<> 144:ef7eb2e8f9f7 7440
<> 144:ef7eb2e8f9f7 7441 /* Get tick count */
<> 144:ef7eb2e8f9f7 7442 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 7443
<> 144:ef7eb2e8f9f7 7444 /* Wait for ADC effectively disabled */
<> 144:ef7eb2e8f9f7 7445 while(ADC_IS_ENABLE(hadc) != RESET)
<> 144:ef7eb2e8f9f7 7446 {
<> 144:ef7eb2e8f9f7 7447 if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
<> 144:ef7eb2e8f9f7 7448 {
<> 144:ef7eb2e8f9f7 7449 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 7450 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 7451
<> 144:ef7eb2e8f9f7 7452 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 7453 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 7454
<> 144:ef7eb2e8f9f7 7455 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 7456 }
<> 144:ef7eb2e8f9f7 7457 }
<> 144:ef7eb2e8f9f7 7458 }
<> 144:ef7eb2e8f9f7 7459
<> 144:ef7eb2e8f9f7 7460 /* Return HAL status */
<> 144:ef7eb2e8f9f7 7461 return HAL_OK;
<> 144:ef7eb2e8f9f7 7462 }
<> 144:ef7eb2e8f9f7 7463 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 7464 /**
<> 144:ef7eb2e8f9f7 7465 * @}
<> 144:ef7eb2e8f9f7 7466 */
<> 144:ef7eb2e8f9f7 7467
<> 144:ef7eb2e8f9f7 7468 #endif /* HAL_ADC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 7469 /**
<> 144:ef7eb2e8f9f7 7470 * @}
<> 144:ef7eb2e8f9f7 7471 */
<> 144:ef7eb2e8f9f7 7472
<> 144:ef7eb2e8f9f7 7473 /**
<> 144:ef7eb2e8f9f7 7474 * @}
<> 144:ef7eb2e8f9f7 7475 */
<> 144:ef7eb2e8f9f7 7476
<> 144:ef7eb2e8f9f7 7477 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/