shao ziyang / mbed-dev

mbed library sources. Supersedes mbed-src. Add PORTG support for STM32L476JG (SensorTile kit)

Dependents:   SensorTileTest

Fork of mbed-dev by mbed official

Files at this revision

API Documentation at this revision

Revision 154:1375a99fb16d, committed 2017-01-02

Comitter:
shaoziyang
Date:
Mon Jan 02 15:52:04 2017 +0000
Parent:
153:fa9ff456f731
Commit message:
Mbed for ST SensorTile kit, fixed GPIOG bug, add PORTG support.

Changed in this revision

targets/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/PinNames.h Show annotated file Show diff for this revision Revisions of this file
targets/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/PortNames.h Show annotated file Show diff for this revision Revisions of this file
targets/TARGET_STM/TARGET_STM32L4/pinmap.c Show annotated file Show diff for this revision Revisions of this file 
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/PinNames.h	Tue Dec 20 17:27:56 2016 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/PinNames.h	Mon Jan 02 15:52:04 2017 +0000
@@ -163,6 +163,13 @@
     PE_14 = 0x4E, // On P1/P2 connectors
     PE_15 = 0x4F, // On P1/P2 connectors
 
+    PG_9  = 0x69,
+    PG_10 = 0x6A,
+    PG_11 = 0x6B,
+    PG_12 = 0x6C,
+    PG_13 = 0x6D,
+    PG_14 = 0x6E,
+    
     PH_0  = 0x70, // On P1/P2 connectors
     PH_1  = 0x71, // On P1/P2 connectors
 

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/PortNames.h	Tue Dec 20 17:27:56 2016 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/PortNames.h	Mon Jan 02 15:52:04 2017 +0000
@@ -40,6 +40,7 @@
     PortC = 2,
     PortD = 3,
     PortE = 4,
+    PortG = 6,
     PortH = 7
 } PortName;
 

--- a/targets/TARGET_STM/TARGET_STM32L4/pinmap.c	Tue Dec 20 17:27:56 2016 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/pinmap.c	Mon Jan 02 15:52:04 2017 +0000
@@ -80,6 +80,15 @@
             __HAL_RCC_GPIOE_CLK_ENABLE();
             break;
 #endif
+#if defined(GPIOG_BASE)
+        case PortG:
+            gpio_add = GPIOG_BASE;
+            __HAL_RCC_SYSCFG_CLK_ENABLE();
+            __HAL_RCC_PWR_CLK_ENABLE();
+            __HAL_RCC_GPIOG_CLK_ENABLE();
+            HAL_PWREx_EnableVddIO2();
+            break;
+#endif
         case PortH:
             gpio_add = GPIOH_BASE;
             __HAL_RCC_GPIOH_CLK_ENABLE();