shao ziyang / mbed-dev

mbed library sources. Supersedes mbed-src. Add PORTG support for STM32L476JG (SensorTile kit)

Dependents:   SensorTileTest

Fork of mbed-dev by mbed official

targets/TARGET_STM/stm_spi_api.c~@154:1375a99fb16d, 2017-01-02 (annotated)

Committer:
shaoziyang
Date:
Mon Jan 02 15:52:04 2017 +0000
Revision:
154:1375a99fb16d
Parent:
153:fa9ff456f731 
Mbed for ST SensorTile kit, fixed GPIOG bug, add PORTG support.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 153:fa9ff456f731 1 /* mbed Microcontroller Library
<> 153:fa9ff456f731 2 *******************************************************************************
<> 153:fa9ff456f731 3 * Copyright (c) 2015, STMicroelectronics
<> 153:fa9ff456f731 4 * All rights reserved.
<> 153:fa9ff456f731 5 *
<> 153:fa9ff456f731 6 * Redistribution and use in source and binary forms, with or without
<> 153:fa9ff456f731 7 * modification, are permitted provided that the following conditions are met:
<> 153:fa9ff456f731 8 *
<> 153:fa9ff456f731 9 * 1. Redistributions of source code must retain the above copyright notice,
<> 153:fa9ff456f731 10 * this list of conditions and the following disclaimer.
<> 153:fa9ff456f731 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 153:fa9ff456f731 12 * this list of conditions and the following disclaimer in the documentation
<> 153:fa9ff456f731 13 * and/or other materials provided with the distribution.
<> 153:fa9ff456f731 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 153:fa9ff456f731 15 * may be used to endorse or promote products derived from this software
<> 153:fa9ff456f731 16 * without specific prior written permission.
<> 153:fa9ff456f731 17 *
<> 153:fa9ff456f731 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 153:fa9ff456f731 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 153:fa9ff456f731 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 153:fa9ff456f731 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 153:fa9ff456f731 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 153:fa9ff456f731 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 153:fa9ff456f731 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 153:fa9ff456f731 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 153:fa9ff456f731 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 153:fa9ff456f731 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 153:fa9ff456f731 28 *******************************************************************************
<> 153:fa9ff456f731 29 */
<> 153:fa9ff456f731 30 #include "mbed_assert.h"
<> 153:fa9ff456f731 31 #include "mbed_error.h"
<> 153:fa9ff456f731 32 #include "spi_api.h"
<> 153:fa9ff456f731 33
<> 153:fa9ff456f731 34 #if DEVICE_SPI
<> 153:fa9ff456f731 35 #include <stdbool.h>
<> 153:fa9ff456f731 36 #include <math.h>
<> 153:fa9ff456f731 37 #include <string.h>
<> 153:fa9ff456f731 38 #include "cmsis.h"
<> 153:fa9ff456f731 39 #include "pinmap.h"
<> 153:fa9ff456f731 40 #include "PeripheralPins.h"
<> 153:fa9ff456f731 41
<> 153:fa9ff456f731 42 #if DEVICE_SPI_ASYNCH
<> 153:fa9ff456f731 43 #define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi.spi))
<> 153:fa9ff456f731 44 #else
<> 153:fa9ff456f731 45 #define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi))
<> 153:fa9ff456f731 46 #endif
<> 153:fa9ff456f731 47
<> 153:fa9ff456f731 48 #if DEVICE_SPI_ASYNCH
<> 153:fa9ff456f731 49 #define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
<> 153:fa9ff456f731 50 #else
<> 153:fa9ff456f731 51 #define SPI_S(obj) (( struct spi_s *)(obj))
<> 153:fa9ff456f731 52 #endif
<> 153:fa9ff456f731 53
<> 153:fa9ff456f731 54 #ifndef DEBUG_STDIO
<> 153:fa9ff456f731 55 # define DEBUG_STDIO 0
<> 153:fa9ff456f731 56 #endif
<> 153:fa9ff456f731 57
<> 153:fa9ff456f731 58 #if DEBUG_STDIO
<> 153:fa9ff456f731 59 # include <stdio.h>
<> 153:fa9ff456f731 60 # define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0)
<> 153:fa9ff456f731 61 #else
<> 153:fa9ff456f731 62 # define DEBUG_PRINTF(...) {}
<> 153:fa9ff456f731 63 #endif
<> 153:fa9ff456f731 64
<> 153:fa9ff456f731 65 void init_spi(spi_t *obj)
<> 153:fa9ff456f731 66 {
<> 153:fa9ff456f731 67 struct spi_s *spiobj = SPI_S(obj);
<> 153:fa9ff456f731 68 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 153:fa9ff456f731 69
<> 153:fa9ff456f731 70 __HAL_SPI_DISABLE(handle);
<> 153:fa9ff456f731 71
<> 153:fa9ff456f731 72 DEBUG_PRINTF("init_spi: instance=0x%8X\r\n", (int)handle->Instance);
<> 153:fa9ff456f731 73 if (HAL_SPI_Init(handle) != HAL_OK) {
<> 153:fa9ff456f731 74 error("Cannot initialize SPI");
<> 153:fa9ff456f731 75 }
<> 153:fa9ff456f731 76
<> 153:fa9ff456f731 77 __HAL_SPI_ENABLE(handle);
<> 153:fa9ff456f731 78 }
<> 153:fa9ff456f731 79
<> 153:fa9ff456f731 80 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
<> 153:fa9ff456f731 81 {
<> 153:fa9ff456f731 82 struct spi_s *spiobj = SPI_S(obj);
<> 153:fa9ff456f731 83 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 153:fa9ff456f731 84
<> 153:fa9ff456f731 85 // Determine the SPI to use
<> 153:fa9ff456f731 86 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
<> 153:fa9ff456f731 87 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
<> 153:fa9ff456f731 88 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
<> 153:fa9ff456f731 89 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
<> 153:fa9ff456f731 90
<> 153:fa9ff456f731 91 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
<> 153:fa9ff456f731 92 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
<> 153:fa9ff456f731 93
<> 153:fa9ff456f731 94 spiobj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
<> 153:fa9ff456f731 95 MBED_ASSERT(spiobj->spi != (SPIName)NC);
<> 153:fa9ff456f731 96
<> 153:fa9ff456f731 97 #if defined SPI1_BASE
<> 153:fa9ff456f731 98 // Enable SPI clock
<> 153:fa9ff456f731 99 if (spiobj->spi == SPI_1) {
<> 153:fa9ff456f731 100 __HAL_RCC_SPI1_CLK_ENABLE();
<> 153:fa9ff456f731 101 spiobj->spiIRQ = SPI1_IRQn;
<> 153:fa9ff456f731 102 }
<> 153:fa9ff456f731 103 #endif
<> 153:fa9ff456f731 104
<> 153:fa9ff456f731 105 #if defined SPI2_BASE
<> 153:fa9ff456f731 106 if (spiobj->spi == SPI_2) {
<> 153:fa9ff456f731 107 __HAL_RCC_SPI2_CLK_ENABLE();
<> 153:fa9ff456f731 108 spiobj->spiIRQ = SPI2_IRQn;
<> 153:fa9ff456f731 109 }
<> 153:fa9ff456f731 110 #endif
<> 153:fa9ff456f731 111
<> 153:fa9ff456f731 112 #if defined SPI3_BASE
<> 153:fa9ff456f731 113 if (spiobj->spi == SPI_3) {
<> 153:fa9ff456f731 114 __HAL_RCC_SPI3_CLK_ENABLE();
<> 153:fa9ff456f731 115 spiobj->spiIRQ = SPI3_IRQn;
<> 153:fa9ff456f731 116 }
<> 153:fa9ff456f731 117 #endif
<> 153:fa9ff456f731 118
<> 153:fa9ff456f731 119 #if defined SPI4_BASE
<> 153:fa9ff456f731 120 if (spiobj->spi == SPI_4) {
<> 153:fa9ff456f731 121 __HAL_RCC_SPI4_CLK_ENABLE();
<> 153:fa9ff456f731 122 spiobj->spiIRQ = SPI4_IRQn;
<> 153:fa9ff456f731 123 }
<> 153:fa9ff456f731 124 #endif
<> 153:fa9ff456f731 125
<> 153:fa9ff456f731 126 #if defined SPI5_BASE
<> 153:fa9ff456f731 127 if (spiobj->spi == SPI_5) {
<> 153:fa9ff456f731 128 __HAL_RCC_SPI5_CLK_ENABLE();
<> 153:fa9ff456f731 129 spiobj->spiIRQ = SPI5_IRQn;
<> 153:fa9ff456f731 130 }
<> 153:fa9ff456f731 131 #endif
<> 153:fa9ff456f731 132
<> 153:fa9ff456f731 133 #if defined SPI6_BASE
<> 153:fa9ff456f731 134 if (spiobj->spi == SPI_6) {
<> 153:fa9ff456f731 135 __HAL_RCC_SPI6_CLK_ENABLE();
<> 153:fa9ff456f731 136 spiobj->spiIRQ = SPI6_IRQn;
<> 153:fa9ff456f731 137 }
<> 153:fa9ff456f731 138 #endif
<> 153:fa9ff456f731 139
<> 153:fa9ff456f731 140 // Configure the SPI pins
<> 153:fa9ff456f731 141 pinmap_pinout(mosi, PinMap_SPI_MOSI);
<> 153:fa9ff456f731 142 pinmap_pinout(miso, PinMap_SPI_MISO);
<> 153:fa9ff456f731 143 pinmap_pinout(sclk, PinMap_SPI_SCLK);
<> 153:fa9ff456f731 144 spiobj->pin_miso = miso;
<> 153:fa9ff456f731 145 spiobj->pin_mosi = mosi;
<> 153:fa9ff456f731 146 spiobj->pin_sclk = sclk;
<> 153:fa9ff456f731 147 spiobj->pin_ssel = ssel;
<> 153:fa9ff456f731 148 if (ssel != NC) {
<> 153:fa9ff456f731 149 pinmap_pinout(ssel, PinMap_SPI_SSEL);
<> 153:fa9ff456f731 150 } else {
<> 153:fa9ff456f731 151 handle->Init.NSS = SPI_NSS_SOFT;
<> 153:fa9ff456f731 152 }
<> 153:fa9ff456f731 153
<> 153:fa9ff456f731 154 /* Fill default value */
<> 153:fa9ff456f731 155 handle->Instance = SPI_INST(obj);
<> 153:fa9ff456f731 156 handle->Init.Mode = SPI_MODE_MASTER;
<> 153:fa9ff456f731 157 handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
<> 153:fa9ff456f731 158 handle->Init.Direction = SPI_DIRECTION_2LINES;
<> 153:fa9ff456f731 159 handle->Init.CLKPhase = SPI_PHASE_1EDGE;
<> 153:fa9ff456f731 160 handle->Init.CLKPolarity = SPI_POLARITY_LOW;
<> 153:fa9ff456f731 161 handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED;
<> 153:fa9ff456f731 162 handle->Init.CRCPolynomial = 7;
<> 153:fa9ff456f731 163 handle->Init.DataSize = SPI_DATASIZE_8BIT;
<> 153:fa9ff456f731 164 handle->Init.FirstBit = SPI_FIRSTBIT_MSB;
<> 153:fa9ff456f731 165 handle->Init.TIMode = SPI_TIMODE_DISABLED;
<> 153:fa9ff456f731 166
<> 153:fa9ff456f731 167 init_spi(obj);
<> 153:fa9ff456f731 168 }
<> 153:fa9ff456f731 169
<> 153:fa9ff456f731 170 void spi_free(spi_t *obj)
<> 153:fa9ff456f731 171 {
<> 153:fa9ff456f731 172 struct spi_s *spiobj = SPI_S(obj);
<> 153:fa9ff456f731 173 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 153:fa9ff456f731 174
<> 153:fa9ff456f731 175 DEBUG_PRINTF("spi_free\r\n");
<> 153:fa9ff456f731 176
<> 153:fa9ff456f731 177 __HAL_SPI_DISABLE(handle);
<> 153:fa9ff456f731 178 HAL_SPI_DeInit(handle);
<> 153:fa9ff456f731 179
<> 153:fa9ff456f731 180 #if defined SPI1_BASE
<> 153:fa9ff456f731 181 // Reset SPI and disable clock
<> 153:fa9ff456f731 182 if (spiobj->spi == SPI_1) {
<> 153:fa9ff456f731 183 __HAL_RCC_SPI1_FORCE_RESET();
<> 153:fa9ff456f731 184 __HAL_RCC_SPI1_RELEASE_RESET();
<> 153:fa9ff456f731 185 __HAL_RCC_SPI1_CLK_DISABLE();
<> 153:fa9ff456f731 186 }
<> 153:fa9ff456f731 187 #endif
<> 153:fa9ff456f731 188 #if defined SPI2_BASE
<> 153:fa9ff456f731 189 if (spiobj->spi == SPI_2) {
<> 153:fa9ff456f731 190 __HAL_RCC_SPI2_FORCE_RESET();
<> 153:fa9ff456f731 191 __HAL_RCC_SPI2_RELEASE_RESET();
<> 153:fa9ff456f731 192 __HAL_RCC_SPI2_CLK_DISABLE();
<> 153:fa9ff456f731 193 }
<> 153:fa9ff456f731 194 #endif
<> 153:fa9ff456f731 195
<> 153:fa9ff456f731 196 #if defined SPI3_BASE
<> 153:fa9ff456f731 197 if (spiobj->spi == SPI_3) {
<> 153:fa9ff456f731 198 __HAL_RCC_SPI3_FORCE_RESET();
<> 153:fa9ff456f731 199 __HAL_RCC_SPI3_RELEASE_RESET();
<> 153:fa9ff456f731 200 __HAL_RCC_SPI3_CLK_DISABLE();
<> 153:fa9ff456f731 201 }
<> 153:fa9ff456f731 202 #endif
<> 153:fa9ff456f731 203
<> 153:fa9ff456f731 204 #if defined SPI4_BASE
<> 153:fa9ff456f731 205 if (spiobj->spi == SPI_4) {
<> 153:fa9ff456f731 206 __HAL_RCC_SPI4_FORCE_RESET();
<> 153:fa9ff456f731 207 __HAL_RCC_SPI4_RELEASE_RESET();
<> 153:fa9ff456f731 208 __HAL_RCC_SPI4_CLK_DISABLE();
<> 153:fa9ff456f731 209 }
<> 153:fa9ff456f731 210 #endif
<> 153:fa9ff456f731 211
<> 153:fa9ff456f731 212 #if defined SPI5_BASE
<> 153:fa9ff456f731 213 if (spiobj->spi == SPI_5) {
<> 153:fa9ff456f731 214 __HAL_RCC_SPI5_FORCE_RESET();
<> 153:fa9ff456f731 215 __HAL_RCC_SPI5_RELEASE_RESET();
<> 153:fa9ff456f731 216 __HAL_RCC_SPI5_CLK_DISABLE();
<> 153:fa9ff456f731 217 }
<> 153:fa9ff456f731 218 #endif
<> 153:fa9ff456f731 219
<> 153:fa9ff456f731 220 #if defined SPI6_BASE
<> 153:fa9ff456f731 221 if (spiobj->spi == SPI_6) {
<> 153:fa9ff456f731 222 __HAL_RCC_SPI6_FORCE_RESET();
<> 153:fa9ff456f731 223 __HAL_RCC_SPI6_RELEASE_RESET();
<> 153:fa9ff456f731 224 __HAL_RCC_SPI6_CLK_DISABLE();
<> 153:fa9ff456f731 225 }
<> 153:fa9ff456f731 226 #endif
<> 153:fa9ff456f731 227
<> 153:fa9ff456f731 228 // Configure GPIOs
<> 153:fa9ff456f731 229 pin_function(spiobj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
<> 153:fa9ff456f731 230 pin_function(spiobj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
<> 153:fa9ff456f731 231 pin_function(spiobj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
<> 153:fa9ff456f731 232 if (handle->Init.NSS != SPI_NSS_SOFT) {
<> 153:fa9ff456f731 233 pin_function(spiobj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
<> 153:fa9ff456f731 234 }
<> 153:fa9ff456f731 235 }
<> 153:fa9ff456f731 236
<> 153:fa9ff456f731 237 void spi_format(spi_t *obj, int bits, int mode, int slave)
<> 153:fa9ff456f731 238 {
<> 153:fa9ff456f731 239 struct spi_s *spiobj = SPI_S(obj);
<> 153:fa9ff456f731 240 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 153:fa9ff456f731 241
<> 153:fa9ff456f731 242 DEBUG_PRINTF("spi_format, bits:%d, mode:%d, slave?:%d\r\n", bits, mode, slave);
<> 153:fa9ff456f731 243
<> 153:fa9ff456f731 244 // Save new values
<> 153:fa9ff456f731 245 handle->Init.DataSize = (bits == 16) ? SPI_DATASIZE_16BIT : SPI_DATASIZE_8BIT;
<> 153:fa9ff456f731 246
<> 153:fa9ff456f731 247 switch (mode) {
<> 153:fa9ff456f731 248 case 0:
<> 153:fa9ff456f731 249 handle->Init.CLKPolarity = SPI_POLARITY_LOW;
<> 153:fa9ff456f731 250 handle->Init.CLKPhase = SPI_PHASE_1EDGE;
<> 153:fa9ff456f731 251 break;
<> 153:fa9ff456f731 252 case 1:
<> 153:fa9ff456f731 253 handle->Init.CLKPolarity = SPI_POLARITY_LOW;
<> 153:fa9ff456f731 254 handle->Init.CLKPhase = SPI_PHASE_2EDGE;
<> 153:fa9ff456f731 255 break;
<> 153:fa9ff456f731 256 case 2:
<> 153:fa9ff456f731 257 handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
<> 153:fa9ff456f731 258 handle->Init.CLKPhase = SPI_PHASE_1EDGE;
<> 153:fa9ff456f731 259 break;
<> 153:fa9ff456f731 260 default:
<> 153:fa9ff456f731 261 handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
<> 153:fa9ff456f731 262 handle->Init.CLKPhase = SPI_PHASE_2EDGE;
<> 153:fa9ff456f731 263 break;
<> 153:fa9ff456f731 264 }
<> 153:fa9ff456f731 265
<> 153:fa9ff456f731 266 if (handle->Init.NSS != SPI_NSS_SOFT) {
<> 153:fa9ff456f731 267 handle->Init.NSS = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT;
<> 153:fa9ff456f731 268 }
<> 153:fa9ff456f731 269
<> 153:fa9ff456f731 270 handle->Init.Mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER;
<> 153:fa9ff456f731 271
<> 153:fa9ff456f731 272 init_spi(obj);
<> 153:fa9ff456f731 273 }
<> 153:fa9ff456f731 274
<> 153:fa9ff456f731 275 /*
<> 153:fa9ff456f731 276 * Only the IP clock input is family dependant so it computed
<> 153:fa9ff456f731 277 * separately in spi_get_clock_freq
<> 153:fa9ff456f731 278 */
<> 153:fa9ff456f731 279 extern int spi_get_clock_freq(spi_t *obj);
<> 153:fa9ff456f731 280
<> 153:fa9ff456f731 281 static const uint16_t baudrate_prescaler_table[] = {SPI_BAUDRATEPRESCALER_2,
<> 153:fa9ff456f731 282 SPI_BAUDRATEPRESCALER_4,
<> 153:fa9ff456f731 283 SPI_BAUDRATEPRESCALER_8,
<> 153:fa9ff456f731 284 SPI_BAUDRATEPRESCALER_16,
<> 153:fa9ff456f731 285 SPI_BAUDRATEPRESCALER_32,
<> 153:fa9ff456f731 286 SPI_BAUDRATEPRESCALER_64,
<> 153:fa9ff456f731 287 SPI_BAUDRATEPRESCALER_128,
<> 153:fa9ff456f731 288 SPI_BAUDRATEPRESCALER_256};
<> 153:fa9ff456f731 289
<> 153:fa9ff456f731 290 void spi_frequency(spi_t *obj, int hz) {
<> 153:fa9ff456f731 291 struct spi_s *spiobj = SPI_S(obj);
<> 153:fa9ff456f731 292 int spi_hz = 0;
<> 153:fa9ff456f731 293 uint8_t prescaler_rank = 0;
<> 153:fa9ff456f731 294 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 153:fa9ff456f731 295
<> 153:fa9ff456f731 296 /* Get the clock of the peripheral */
<> 153:fa9ff456f731 297 spi_hz = spi_get_clock_freq(obj);
<> 153:fa9ff456f731 298
<> 153:fa9ff456f731 299 /* Define pre-scaler in order to get highest available frequency below requested frequency */
<> 153:fa9ff456f731 300 while ((spi_hz > hz) && (prescaler_rank < sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0]))){
<> 153:fa9ff456f731 301 spi_hz = spi_hz / 2;
<> 153:fa9ff456f731 302 prescaler_rank++;
<> 153:fa9ff456f731 303 }
<> 153:fa9ff456f731 304
<> 153:fa9ff456f731 305 if (prescaler_rank <= sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0])) {
<> 153:fa9ff456f731 306 handle->Init.BaudRatePrescaler = baudrate_prescaler_table[prescaler_rank-1];
<> 153:fa9ff456f731 307 } else {
<> 153:fa9ff456f731 308 error("Couldn't setup requested SPI frequency");
<> 153:fa9ff456f731 309 }
<> 153:fa9ff456f731 310
<> 153:fa9ff456f731 311 init_spi(obj);
<> 153:fa9ff456f731 312 }
<> 153:fa9ff456f731 313
<> 153:fa9ff456f731 314 static inline int ssp_readable(spi_t *obj)
<> 153:fa9ff456f731 315 {
<> 153:fa9ff456f731 316 int status;
<> 153:fa9ff456f731 317 struct spi_s *spiobj = SPI_S(obj);
<> 153:fa9ff456f731 318 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 153:fa9ff456f731 319
<> 153:fa9ff456f731 320 // Check if data is received
<> 153:fa9ff456f731 321 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
<> 153:fa9ff456f731 322 return status;
<> 153:fa9ff456f731 323 }
<> 153:fa9ff456f731 324
<> 153:fa9ff456f731 325 static inline int ssp_writeable(spi_t *obj)
<> 153:fa9ff456f731 326 {
<> 153:fa9ff456f731 327 int status;
<> 153:fa9ff456f731 328 struct spi_s *spiobj = SPI_S(obj);
<> 153:fa9ff456f731 329 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 153:fa9ff456f731 330
<> 153:fa9ff456f731 331 // Check if data is transmitted
<> 153:fa9ff456f731 332 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
<> 153:fa9ff456f731 333 return status;
<> 153:fa9ff456f731 334 }
<> 153:fa9ff456f731 335
<> 153:fa9ff456f731 336 static inline int ssp_busy(spi_t *obj)
<> 153:fa9ff456f731 337 {
<> 153:fa9ff456f731 338 int status;
<> 153:fa9ff456f731 339 struct spi_s *spiobj = SPI_S(obj);
<> 153:fa9ff456f731 340 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 153:fa9ff456f731 341 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
<> 153:fa9ff456f731 342 return status;
<> 153:fa9ff456f731 343 }
<> 153:fa9ff456f731 344
<> 153:fa9ff456f731 345 int spi_master_write(spi_t *obj, int value)
<> 153:fa9ff456f731 346 {
<> 153:fa9ff456f731 347 uint16_t size, Rx, ret;
<> 153:fa9ff456f731 348 struct spi_s *spiobj = SPI_S(obj);
<> 153:fa9ff456f731 349 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 153:fa9ff456f731 350
<> 153:fa9ff456f731 351 size = (handle->Init.DataSize == SPI_DATASIZE_16BIT) ? 2 : 1;
<> 153:fa9ff456f731 352
<> 153:fa9ff456f731 353 /* Use 10ms timeout */
<> 153:fa9ff456f731 354 ret = HAL_SPI_TransmitReceive(handle,(uint8_t*)&value,(uint8_t*)&Rx,size,10);
<> 153:fa9ff456f731 355
<> 153:fa9ff456f731 356 if(ret == HAL_OK) {
<> 153:fa9ff456f731 357 return Rx;
<> 153:fa9ff456f731 358 } else {
<> 153:fa9ff456f731 359 DEBUG_PRINTF("SPI inst=0x%8X ERROR in write\r\n", (int)handle->Instance);
<> 153:fa9ff456f731 360 return -1;
<> 153:fa9ff456f731 361 }
<> 153:fa9ff456f731 362 }
<> 153:fa9ff456f731 363
<> 153:fa9ff456f731 364 int spi_slave_receive(spi_t *obj)
<> 153:fa9ff456f731 365 {
<> 153:fa9ff456f731 366 return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0);
<> 153:fa9ff456f731 367 };
<> 153:fa9ff456f731 368
<> 153:fa9ff456f731 369 int spi_slave_read(spi_t *obj)
<> 153:fa9ff456f731 370 {
<> 153:fa9ff456f731 371 SPI_TypeDef *spi = SPI_INST(obj);
<> 153:fa9ff456f731 372 struct spi_s *spiobj = SPI_S(obj);
<> 153:fa9ff456f731 373 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 153:fa9ff456f731 374 while (!ssp_readable(obj));
<> 153:fa9ff456f731 375 if (handle->Init.DataSize == SPI_DATASIZE_8BIT) {
<> 153:fa9ff456f731 376 // Force 8-bit access to the data register
<> 153:fa9ff456f731 377 uint8_t *p_spi_dr = 0;
<> 153:fa9ff456f731 378 p_spi_dr = (uint8_t *) & (spi->DR);
<> 153:fa9ff456f731 379 return (int)(*p_spi_dr);
<> 153:fa9ff456f731 380 } else {
<> 153:fa9ff456f731 381 return (int)spi->DR;
<> 153:fa9ff456f731 382 }
<> 153:fa9ff456f731 383 }
<> 153:fa9ff456f731 384
<> 153:fa9ff456f731 385 void spi_slave_write(spi_t *obj, int value)
<> 153:fa9ff456f731 386 {
<> 153:fa9ff456f731 387 SPI_TypeDef *spi = SPI_INST(obj);
<> 153:fa9ff456f731 388 struct spi_s *spiobj = SPI_S(obj);
<> 153:fa9ff456f731 389 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 153:fa9ff456f731 390 while (!ssp_writeable(obj));
<> 153:fa9ff456f731 391 if (handle->Init.DataSize == SPI_DATASIZE_8BIT) {
<> 153:fa9ff456f731 392 // Force 8-bit access to the data register
<> 153:fa9ff456f731 393 uint8_t *p_spi_dr = 0;
<> 153:fa9ff456f731 394 p_spi_dr = (uint8_t *) & (spi->DR);
<> 153:fa9ff456f731 395 *p_spi_dr = (uint8_t)value;
<> 153:fa9ff456f731 396 } else { // SPI_DATASIZE_16BIT
<> 153:fa9ff456f731 397 spi->DR = (uint16_t)value;
<> 153:fa9ff456f731 398 }
<> 153:fa9ff456f731 399 }
<> 153:fa9ff456f731 400
<> 153:fa9ff456f731 401 int spi_busy(spi_t *obj)
<> 153:fa9ff456f731 402 {
<> 153:fa9ff456f731 403 return ssp_busy(obj);
<> 153:fa9ff456f731 404 }
<> 153:fa9ff456f731 405
<> 153:fa9ff456f731 406 #ifdef DEVICE_SPI_ASYNCH
<> 153:fa9ff456f731 407 typedef enum {
<> 153:fa9ff456f731 408 SPI_TRANSFER_TYPE_NONE = 0,
<> 153:fa9ff456f731 409 SPI_TRANSFER_TYPE_TX = 1,
<> 153:fa9ff456f731 410 SPI_TRANSFER_TYPE_RX = 2,
<> 153:fa9ff456f731 411 SPI_TRANSFER_TYPE_TXRX = 3,
<> 153:fa9ff456f731 412 } transfer_type_t;
<> 153:fa9ff456f731 413
<> 153:fa9ff456f731 414
<> 153:fa9ff456f731 415 /// @returns the number of bytes transferred, or `0` if nothing transferred
<> 153:fa9ff456f731 416 static int spi_master_start_asynch_transfer(spi_t *obj, transfer_type_t transfer_type, const void *tx, void *rx, size_t length)
<> 153:fa9ff456f731 417 {
<> 153:fa9ff456f731 418 struct spi_s *spiobj = SPI_S(obj);
<> 153:fa9ff456f731 419 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 153:fa9ff456f731 420 bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT);
<> 153:fa9ff456f731 421 // the HAL expects number of transfers instead of number of bytes
<> 153:fa9ff456f731 422 // so for 16 bit transfer width the count needs to be halved
<> 153:fa9ff456f731 423 size_t words;
<> 153:fa9ff456f731 424
<> 153:fa9ff456f731 425 DEBUG_PRINTF("SPI inst=0x%8X Start: %u, %u\r\n", (int)handle->Instance, transfer_type, length);
<> 153:fa9ff456f731 426
<> 153:fa9ff456f731 427 obj->spi.transfer_type = transfer_type;
<> 153:fa9ff456f731 428
<> 153:fa9ff456f731 429 if (is16bit) {
<> 153:fa9ff456f731 430 words = length / 2;
<> 153:fa9ff456f731 431 } else {
<> 153:fa9ff456f731 432 words = length;
<> 153:fa9ff456f731 433 }
<> 153:fa9ff456f731 434
<> 153:fa9ff456f731 435 // enable the interrupt
<> 153:fa9ff456f731 436 IRQn_Type irq_n = spiobj->spiIRQ;
<> 153:fa9ff456f731 437 NVIC_ClearPendingIRQ(irq_n);
<> 153:fa9ff456f731 438 NVIC_DisableIRQ(irq_n);
<> 153:fa9ff456f731 439 NVIC_SetPriority(irq_n, 1);
<> 153:fa9ff456f731 440 NVIC_EnableIRQ(irq_n);
<> 153:fa9ff456f731 441
<> 153:fa9ff456f731 442 // enable the right hal transfer
<> 153:fa9ff456f731 443 int rc = 0;
<> 153:fa9ff456f731 444 switch(transfer_type) {
<> 153:fa9ff456f731 445 case SPI_TRANSFER_TYPE_TXRX:
<> 153:fa9ff456f731 446 rc = HAL_SPI_TransmitReceive_IT(handle, (uint8_t*)tx, (uint8_t*)rx, words);
<> 153:fa9ff456f731 447 break;
<> 153:fa9ff456f731 448 case SPI_TRANSFER_TYPE_TX:
<> 153:fa9ff456f731 449 rc = HAL_SPI_Transmit_IT(handle, (uint8_t*)tx, words);
<> 153:fa9ff456f731 450 break;
<> 153:fa9ff456f731 451 case SPI_TRANSFER_TYPE_RX:
<> 153:fa9ff456f731 452 // the receive function also "transmits" the receive buffer so in order
<> 153:fa9ff456f731 453 // to guarantee that 0xff is on the line, we explicitly memset it here
<> 153:fa9ff456f731 454 memset(rx, SPI_FILL_WORD, length);
<> 153:fa9ff456f731 455 rc = HAL_SPI_Receive_IT(handle, (uint8_t*)rx, words);
<> 153:fa9ff456f731 456 break;
<> 153:fa9ff456f731 457 default:
<> 153:fa9ff456f731 458 length = 0;
<> 153:fa9ff456f731 459 }
<> 153:fa9ff456f731 460
<> 153:fa9ff456f731 461 if (rc) {
<> 153:fa9ff456f731 462 DEBUG_PRINTF("SPI: RC=%u\n", rc);
<> 153:fa9ff456f731 463 length = 0;
<> 153:fa9ff456f731 464 }
<> 153:fa9ff456f731 465
<> 153:fa9ff456f731 466 return length;
<> 153:fa9ff456f731 467 }
<> 153:fa9ff456f731 468
<> 153:fa9ff456f731 469 // asynchronous API
<> 153:fa9ff456f731 470 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
<> 153:fa9ff456f731 471 {
<> 153:fa9ff456f731 472 struct spi_s *spiobj = SPI_S(obj);
<> 153:fa9ff456f731 473 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 153:fa9ff456f731 474
<> 153:fa9ff456f731 475 // TODO: DMA usage is currently ignored
<> 153:fa9ff456f731 476 (void) hint;
<> 153:fa9ff456f731 477
<> 153:fa9ff456f731 478 // check which use-case we have
<> 153:fa9ff456f731 479 bool use_tx = (tx != NULL && tx_length > 0);
<> 153:fa9ff456f731 480 bool use_rx = (rx != NULL && rx_length > 0);
<> 153:fa9ff456f731 481 bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT);
<> 153:fa9ff456f731 482
<> 153:fa9ff456f731 483 // don't do anything, if the buffers aren't valid
<> 153:fa9ff456f731 484 if (!use_tx && !use_rx)
<> 153:fa9ff456f731 485 return;
<> 153:fa9ff456f731 486
<> 153:fa9ff456f731 487 // copy the buffers to the SPI object
<> 153:fa9ff456f731 488 obj->tx_buff.buffer = (void *) tx;
<> 153:fa9ff456f731 489 obj->tx_buff.length = tx_length;
<> 153:fa9ff456f731 490 obj->tx_buff.pos = 0;
<> 153:fa9ff456f731 491 obj->tx_buff.width = is16bit ? 16 : 8;
<> 153:fa9ff456f731 492
<> 153:fa9ff456f731 493 obj->rx_buff.buffer = rx;
<> 153:fa9ff456f731 494 obj->rx_buff.length = rx_length;
<> 153:fa9ff456f731 495 obj->rx_buff.pos = 0;
<> 153:fa9ff456f731 496 obj->rx_buff.width = obj->tx_buff.width;
<> 153:fa9ff456f731 497
<> 153:fa9ff456f731 498 obj->spi.event = event;
<> 153:fa9ff456f731 499
<> 153:fa9ff456f731 500 DEBUG_PRINTF("SPI: Transfer: %u, %u\n", tx_length, rx_length);
<> 153:fa9ff456f731 501
<> 153:fa9ff456f731 502 // register the thunking handler
<> 153:fa9ff456f731 503 IRQn_Type irq_n = spiobj->spiIRQ;
<> 153:fa9ff456f731 504 NVIC_SetVector(irq_n, (uint32_t)handler);
<> 153:fa9ff456f731 505
<> 153:fa9ff456f731 506 // enable the right hal transfer
<> 153:fa9ff456f731 507 if (use_tx && use_rx) {
<> 153:fa9ff456f731 508 // we cannot manage different rx / tx sizes, let's use smaller one
<> 153:fa9ff456f731 509 size_t size = (tx_length < rx_length)? tx_length : rx_length;
<> 153:fa9ff456f731 510 if(tx_length != rx_length) {
<> 153:fa9ff456f731 511 DEBUG_PRINTF("SPI: Full duplex transfer only 1 size: %d\n", size);
<> 153:fa9ff456f731 512 obj->tx_buff.length = size;
<> 153:fa9ff456f731 513 obj->rx_buff.length = size;
<> 153:fa9ff456f731 514 }
<> 153:fa9ff456f731 515 spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TXRX, tx, rx, size);
<> 153:fa9ff456f731 516 } else if (use_tx) {
<> 153:fa9ff456f731 517 spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TX, tx, NULL, tx_length);
<> 153:fa9ff456f731 518 } else if (use_rx) {
<> 153:fa9ff456f731 519 spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_RX, NULL, rx, rx_length);
<> 153:fa9ff456f731 520 }
<> 153:fa9ff456f731 521 }
<> 153:fa9ff456f731 522
<> 153:fa9ff456f731 523 inline uint32_t spi_irq_handler_asynch(spi_t *obj)
<> 153:fa9ff456f731 524 {
<> 153:fa9ff456f731 525 int event = 0;
<> 153:fa9ff456f731 526
<> 153:fa9ff456f731 527 // call the CubeF4 handler, this will update the handle
<> 153:fa9ff456f731 528 HAL_SPI_IRQHandler(&obj->spi.handle);
<> 153:fa9ff456f731 529
<> 153:fa9ff456f731 530 if (obj->spi.handle.State == HAL_SPI_STATE_READY) {
<> 153:fa9ff456f731 531 // When HAL SPI is back to READY state, check if there was an error
<> 153:fa9ff456f731 532 int error = obj->spi.handle.ErrorCode;
<> 153:fa9ff456f731 533 if(error != HAL_SPI_ERROR_NONE) {
<> 153:fa9ff456f731 534 // something went wrong and the transfer has definitely completed
<> 153:fa9ff456f731 535 event = SPI_EVENT_ERROR | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
<> 153:fa9ff456f731 536
<> 153:fa9ff456f731 537 if (error & HAL_SPI_ERROR_OVR) {
<> 153:fa9ff456f731 538 // buffer overrun
<> 153:fa9ff456f731 539 event |= SPI_EVENT_RX_OVERFLOW;
<> 153:fa9ff456f731 540 }
<> 153:fa9ff456f731 541 } else {
<> 153:fa9ff456f731 542 // else we're done
<> 153:fa9ff456f731 543 event = SPI_EVENT_COMPLETE | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
<> 153:fa9ff456f731 544 }
<> 153:fa9ff456f731 545 <<<<<<< HEAD
<> 153:fa9ff456f731 546 =======
<> 153:fa9ff456f731 547 // enable the interrupt
<> 153:fa9ff456f731 548 NVIC_DisableIRQ(obj->spi.spiIRQ);
<> 153:fa9ff456f731 549 NVIC_ClearPendingIRQ(obj->spi.spiIRQ);
<> 153:fa9ff456f731 550 >>>>>>> stm32 spi : IRQ handler light optimization
<> 153:fa9ff456f731 551 }
<> 153:fa9ff456f731 552
<> 153:fa9ff456f731 553
<> 153:fa9ff456f731 554 return (event & (obj->spi.event | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE));
<> 153:fa9ff456f731 555 }
<> 153:fa9ff456f731 556
<> 153:fa9ff456f731 557 uint8_t spi_active(spi_t *obj)
<> 153:fa9ff456f731 558 {
<> 153:fa9ff456f731 559 struct spi_s *spiobj = SPI_S(obj);
<> 153:fa9ff456f731 560 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 153:fa9ff456f731 561 HAL_SPI_StateTypeDef state = HAL_SPI_GetState(handle);
<> 153:fa9ff456f731 562
<> 153:fa9ff456f731 563 switch(state) {
<> 153:fa9ff456f731 564 case HAL_SPI_STATE_RESET:
<> 153:fa9ff456f731 565 case HAL_SPI_STATE_READY:
<> 153:fa9ff456f731 566 case HAL_SPI_STATE_ERROR:
<> 153:fa9ff456f731 567 return 0;
<> 153:fa9ff456f731 568 default:
<> 153:fa9ff456f731 569 return 1;
<> 153:fa9ff456f731 570 }
<> 153:fa9ff456f731 571 }
<> 153:fa9ff456f731 572
<> 153:fa9ff456f731 573 void spi_abort_asynch(spi_t *obj)
<> 153:fa9ff456f731 574 {
<> 153:fa9ff456f731 575 struct spi_s *spiobj = SPI_S(obj);
<> 153:fa9ff456f731 576 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 153:fa9ff456f731 577
<> 153:fa9ff456f731 578 // disable interrupt
<> 153:fa9ff456f731 579 IRQn_Type irq_n = spiobj->spiIRQ;
<> 153:fa9ff456f731 580 NVIC_ClearPendingIRQ(irq_n);
<> 153:fa9ff456f731 581 NVIC_DisableIRQ(irq_n);
<> 153:fa9ff456f731 582
<> 153:fa9ff456f731 583 // clean-up
<> 153:fa9ff456f731 584 __HAL_SPI_DISABLE(handle);
<> 153:fa9ff456f731 585 HAL_SPI_DeInit(handle);
<> 153:fa9ff456f731 586 HAL_SPI_Init(handle);
<> 153:fa9ff456f731 587 __HAL_SPI_ENABLE(handle);
<> 153:fa9ff456f731 588 }
<> 153:fa9ff456f731 589
<> 153:fa9ff456f731 590 #endif //DEVICE_SPI_ASYNCH
<> 153:fa9ff456f731 591
<> 153:fa9ff456f731 592 #endif