mbed library sources. Supersedes mbed-src. Add PORTG support for STM32L476JG (SensorTile kit)
Fork of mbed-dev by
targets/TARGET_ARM_SSG/TARGET_MPS2/spi_api.c@154:1375a99fb16d, 2017-01-02 (annotated)
- Committer:
- shaoziyang
- Date:
- Mon Jan 02 15:52:04 2017 +0000
- Revision:
- 154:1375a99fb16d
- Parent:
- 149:156823d33999
Mbed for ST SensorTile kit, fixed GPIOG bug, add PORTG support.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* mbed Microcontroller Library |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2006-2015 ARM Limited |
<> | 144:ef7eb2e8f9f7 | 3 | * |
<> | 144:ef7eb2e8f9f7 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
<> | 144:ef7eb2e8f9f7 | 5 | * you may not use this file except in compliance with the License. |
<> | 144:ef7eb2e8f9f7 | 6 | * You may obtain a copy of the License at |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
<> | 144:ef7eb2e8f9f7 | 9 | * |
<> | 144:ef7eb2e8f9f7 | 10 | * Unless required by applicable law or agreed to in writing, software |
<> | 144:ef7eb2e8f9f7 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
<> | 144:ef7eb2e8f9f7 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
<> | 144:ef7eb2e8f9f7 | 13 | * See the License for the specific language governing permissions and |
<> | 144:ef7eb2e8f9f7 | 14 | * limitations under the License. |
<> | 144:ef7eb2e8f9f7 | 15 | */ |
<> | 144:ef7eb2e8f9f7 | 16 | #include <math.h> |
<> | 144:ef7eb2e8f9f7 | 17 | |
<> | 144:ef7eb2e8f9f7 | 18 | #include "spi_api.h" |
<> | 144:ef7eb2e8f9f7 | 19 | #include "spi_def.h" |
<> | 144:ef7eb2e8f9f7 | 20 | #include "cmsis.h" |
<> | 144:ef7eb2e8f9f7 | 21 | #include "pinmap.h" |
<> | 144:ef7eb2e8f9f7 | 22 | #include "mbed_error.h" |
<> | 144:ef7eb2e8f9f7 | 23 | #include "wait_api.h" |
<> | 144:ef7eb2e8f9f7 | 24 | |
<> | 144:ef7eb2e8f9f7 | 25 | static const PinMap PinMap_SPI_SCLK[] = { |
<> | 144:ef7eb2e8f9f7 | 26 | {SCLK_SPI , SPI_0, 0}, |
<> | 144:ef7eb2e8f9f7 | 27 | {CLCD_SCLK , SPI_1, 0}, |
<> | 144:ef7eb2e8f9f7 | 28 | {ADC_SCLK , SPI_2, 0}, |
<> | 144:ef7eb2e8f9f7 | 29 | {SHIELD_0_SPI_SCK , SPI_3, 0}, |
<> | 144:ef7eb2e8f9f7 | 30 | {SHIELD_1_SPI_SCK , SPI_4, 0}, |
<> | 144:ef7eb2e8f9f7 | 31 | {NC , NC , 0} |
<> | 144:ef7eb2e8f9f7 | 32 | }; |
<> | 144:ef7eb2e8f9f7 | 33 | |
<> | 144:ef7eb2e8f9f7 | 34 | static const PinMap PinMap_SPI_MOSI[] = { |
<> | 144:ef7eb2e8f9f7 | 35 | {MOSI_SPI, SPI_0, 0}, |
<> | 144:ef7eb2e8f9f7 | 36 | {CLCD_MOSI, SPI_1, 0}, |
<> | 144:ef7eb2e8f9f7 | 37 | {ADC_MOSI, SPI_2, 0}, |
<> | 144:ef7eb2e8f9f7 | 38 | {SHIELD_0_SPI_MOSI, SPI_3, 0}, |
<> | 144:ef7eb2e8f9f7 | 39 | {SHIELD_1_SPI_MOSI, SPI_4, 0}, |
<> | 144:ef7eb2e8f9f7 | 40 | {NC , NC , 0} |
<> | 144:ef7eb2e8f9f7 | 41 | }; |
<> | 144:ef7eb2e8f9f7 | 42 | |
<> | 144:ef7eb2e8f9f7 | 43 | static const PinMap PinMap_SPI_MISO[] = { |
<> | 144:ef7eb2e8f9f7 | 44 | {MISO_SPI, SPI_0, 0}, |
<> | 144:ef7eb2e8f9f7 | 45 | {CLCD_MISO, SPI_1, 0}, |
<> | 144:ef7eb2e8f9f7 | 46 | {ADC_MISO, SPI_2, 0}, |
<> | 144:ef7eb2e8f9f7 | 47 | {SHIELD_0_SPI_MISO, SPI_3, 0}, |
<> | 144:ef7eb2e8f9f7 | 48 | {SHIELD_1_SPI_MISO, SPI_4, 0}, |
<> | 144:ef7eb2e8f9f7 | 49 | {NC , NC , 0} |
<> | 144:ef7eb2e8f9f7 | 50 | }; |
<> | 144:ef7eb2e8f9f7 | 51 | |
<> | 144:ef7eb2e8f9f7 | 52 | static const PinMap PinMap_SPI_SSEL[] = { |
<> | 144:ef7eb2e8f9f7 | 53 | {SSEL_SPI, SPI_0, 0}, |
<> | 144:ef7eb2e8f9f7 | 54 | {CLCD_SSEL, SPI_1, 0}, |
<> | 144:ef7eb2e8f9f7 | 55 | {ADC_SSEL, SPI_2, 0}, |
<> | 144:ef7eb2e8f9f7 | 56 | {SHIELD_0_SPI_nCS, SPI_3, 0}, |
<> | 144:ef7eb2e8f9f7 | 57 | {SHIELD_1_SPI_nCS, SPI_4, 0}, |
<> | 144:ef7eb2e8f9f7 | 58 | {NC , NC , 0} |
<> | 144:ef7eb2e8f9f7 | 59 | }; |
<> | 144:ef7eb2e8f9f7 | 60 | |
<> | 144:ef7eb2e8f9f7 | 61 | static inline int ssp_disable(spi_t *obj); |
<> | 144:ef7eb2e8f9f7 | 62 | static inline int ssp_enable(spi_t *obj); |
<> | 144:ef7eb2e8f9f7 | 63 | |
<> | 144:ef7eb2e8f9f7 | 64 | void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { |
<> | 144:ef7eb2e8f9f7 | 65 | |
<> | 144:ef7eb2e8f9f7 | 66 | int altfunction[4]; |
<> | 144:ef7eb2e8f9f7 | 67 | // determine the SPI to use |
<> | 144:ef7eb2e8f9f7 | 68 | SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); |
<> | 144:ef7eb2e8f9f7 | 69 | SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); |
<> | 144:ef7eb2e8f9f7 | 70 | SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); |
<> | 144:ef7eb2e8f9f7 | 71 | SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); |
<> | 144:ef7eb2e8f9f7 | 72 | SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); |
<> | 144:ef7eb2e8f9f7 | 73 | SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); |
<> | 144:ef7eb2e8f9f7 | 74 | obj->spi = (MPS2_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl); |
<> | 144:ef7eb2e8f9f7 | 75 | if ((int)obj->spi == NC) { |
<> | 144:ef7eb2e8f9f7 | 76 | error("SPI pinout mapping failed"); |
<> | 144:ef7eb2e8f9f7 | 77 | } |
<> | 144:ef7eb2e8f9f7 | 78 | |
<> | 144:ef7eb2e8f9f7 | 79 | // enable power and clocking |
<> | 144:ef7eb2e8f9f7 | 80 | switch ((int)obj->spi) { |
<> | 144:ef7eb2e8f9f7 | 81 | case (int)SPI_0: |
<> | 144:ef7eb2e8f9f7 | 82 | obj->spi->CR1 = 0; |
<> | 144:ef7eb2e8f9f7 | 83 | obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8; |
<> | 144:ef7eb2e8f9f7 | 84 | obj->spi->CPSR = SSP_CPSR_DFLT; |
<> | 144:ef7eb2e8f9f7 | 85 | obj->spi->IMSC = 0x8; |
<> | 144:ef7eb2e8f9f7 | 86 | obj->spi->DMACR = 0; |
<> | 144:ef7eb2e8f9f7 | 87 | obj->spi->CR1 = SSP_CR1_SSE_Msk; |
<> | 144:ef7eb2e8f9f7 | 88 | obj->spi->ICR = 0x3; |
<> | 144:ef7eb2e8f9f7 | 89 | break; |
<> | 144:ef7eb2e8f9f7 | 90 | case (int)SPI_1: |
<> | 144:ef7eb2e8f9f7 | 91 | /* Configure SSP used for LCD */ |
<> | 144:ef7eb2e8f9f7 | 92 | obj->spi->CR1 = 0; /* Synchronous serial port disable */ |
<> | 144:ef7eb2e8f9f7 | 93 | obj->spi->DMACR = 0; /* Disable FIFO DMA */ |
<> | 144:ef7eb2e8f9f7 | 94 | obj->spi->IMSC = 0; /* Mask all FIFO/IRQ interrupts */ |
<> | 144:ef7eb2e8f9f7 | 95 | obj->spi->ICR = ((1ul << 0) | /* Clear SSPRORINTR interrupt */ |
<> | 144:ef7eb2e8f9f7 | 96 | (1ul << 1) ); /* Clear SSPRTINTR interrupt */ |
<> | 144:ef7eb2e8f9f7 | 97 | obj->spi->CR0 = ((7ul << 0) | /* 8 bit data size */ |
<> | 144:ef7eb2e8f9f7 | 98 | (0ul << 4) | /* Motorola frame format */ |
<> | 144:ef7eb2e8f9f7 | 99 | (0ul << 6) | /* CPOL = 0 */ |
<> | 144:ef7eb2e8f9f7 | 100 | (0ul << 7) | /* CPHA = 0 */ |
<> | 144:ef7eb2e8f9f7 | 101 | (1ul << 8) ); /* Set serial clock rate */ |
<> | 144:ef7eb2e8f9f7 | 102 | obj->spi->CPSR = (2ul << 0); /* set SSP clk to 6MHz (6.6MHz max) */ |
<> | 144:ef7eb2e8f9f7 | 103 | obj->spi->CR1 = ((1ul << 1) | /* Synchronous serial port enable */ |
<> | 144:ef7eb2e8f9f7 | 104 | (0ul << 2) ); /* Device configured as master */ |
<> | 144:ef7eb2e8f9f7 | 105 | break; |
<> | 144:ef7eb2e8f9f7 | 106 | case (int)SPI_2: |
<> | 144:ef7eb2e8f9f7 | 107 | obj->spi->CR1 = 0; |
<> | 144:ef7eb2e8f9f7 | 108 | obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8; |
<> | 144:ef7eb2e8f9f7 | 109 | obj->spi->CPSR = SSP_CPSR_DFLT; |
<> | 144:ef7eb2e8f9f7 | 110 | obj->spi->IMSC = 0x8; |
<> | 144:ef7eb2e8f9f7 | 111 | obj->spi->DMACR = 0; |
<> | 144:ef7eb2e8f9f7 | 112 | obj->spi->CR1 = SSP_CR1_SSE_Msk; |
<> | 144:ef7eb2e8f9f7 | 113 | obj->spi->ICR = 0x3; |
<> | 144:ef7eb2e8f9f7 | 114 | break; |
<> | 144:ef7eb2e8f9f7 | 115 | case (int)SPI_3: |
<> | 144:ef7eb2e8f9f7 | 116 | obj->spi->CR1 = 0; |
<> | 144:ef7eb2e8f9f7 | 117 | obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8; |
<> | 144:ef7eb2e8f9f7 | 118 | obj->spi->CPSR = SSP_CPSR_DFLT; |
<> | 144:ef7eb2e8f9f7 | 119 | obj->spi->IMSC = 0x8; |
<> | 144:ef7eb2e8f9f7 | 120 | obj->spi->DMACR = 0; |
<> | 144:ef7eb2e8f9f7 | 121 | obj->spi->CR1 = SSP_CR1_SSE_Msk; |
<> | 144:ef7eb2e8f9f7 | 122 | obj->spi->ICR = 0x3; |
<> | 144:ef7eb2e8f9f7 | 123 | break; |
<> | 144:ef7eb2e8f9f7 | 124 | case (int)SPI_4: |
<> | 144:ef7eb2e8f9f7 | 125 | obj->spi->CR1 = 0; |
<> | 144:ef7eb2e8f9f7 | 126 | obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8; |
<> | 144:ef7eb2e8f9f7 | 127 | obj->spi->CPSR = SSP_CPSR_DFLT; |
<> | 144:ef7eb2e8f9f7 | 128 | obj->spi->IMSC = 0x8; |
<> | 144:ef7eb2e8f9f7 | 129 | obj->spi->DMACR = 0; |
<> | 144:ef7eb2e8f9f7 | 130 | obj->spi->CR1 = SSP_CR1_SSE_Msk; |
<> | 144:ef7eb2e8f9f7 | 131 | obj->spi->ICR = 0x3; |
<> | 144:ef7eb2e8f9f7 | 132 | break; |
<> | 144:ef7eb2e8f9f7 | 133 | } |
<> | 144:ef7eb2e8f9f7 | 134 | |
<> | 144:ef7eb2e8f9f7 | 135 | if(mosi != NC){ altfunction[0] = 1;}else{ altfunction[0] = 0;} |
<> | 144:ef7eb2e8f9f7 | 136 | if(miso != NC){ altfunction[1] = 1;}else{ altfunction[1] = 0;} |
<> | 144:ef7eb2e8f9f7 | 137 | if(sclk != NC){ altfunction[2] = 1;}else{ altfunction[2] = 0;} |
<> | 144:ef7eb2e8f9f7 | 138 | if(ssel != NC){ altfunction[3] = 1;}else{ altfunction[3] = 0;} |
<> | 144:ef7eb2e8f9f7 | 139 | |
<> | 144:ef7eb2e8f9f7 | 140 | // enable alt function |
<> | 144:ef7eb2e8f9f7 | 141 | switch ((int)obj->spi) { |
<> | 144:ef7eb2e8f9f7 | 142 | case (int)SPI_2: |
<> | 144:ef7eb2e8f9f7 | 143 | CMSDK_GPIO1->ALTFUNCSET |= (altfunction[2]<<3 | altfunction[0]<<2 | altfunction[1]<<1 | altfunction[3]); |
<> | 144:ef7eb2e8f9f7 | 144 | break; |
<> | 144:ef7eb2e8f9f7 | 145 | case (int)SPI_3: |
<> | 144:ef7eb2e8f9f7 | 146 | CMSDK_GPIO0->ALTFUNCSET |= (altfunction[1]<<14 | altfunction[0]<<13 | altfunction[3]<<12 | altfunction[2]<<11); |
<> | 144:ef7eb2e8f9f7 | 147 | break; |
<> | 144:ef7eb2e8f9f7 | 148 | case (int)SPI_4: |
<> | 144:ef7eb2e8f9f7 | 149 | CMSDK_GPIO2->ALTFUNCSET |= (altfunction[2]<<12 | altfunction[1]<<8 | altfunction[0]<<7 | altfunction[3]<<6); |
<> | 144:ef7eb2e8f9f7 | 150 | break; |
<> | 144:ef7eb2e8f9f7 | 151 | } |
<> | 144:ef7eb2e8f9f7 | 152 | |
<> | 144:ef7eb2e8f9f7 | 153 | // set default format and frequency |
<> | 144:ef7eb2e8f9f7 | 154 | if (ssel == NC) { |
<> | 144:ef7eb2e8f9f7 | 155 | spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master |
<> | 144:ef7eb2e8f9f7 | 156 | } else { |
<> | 144:ef7eb2e8f9f7 | 157 | spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave |
<> | 144:ef7eb2e8f9f7 | 158 | } |
<> | 144:ef7eb2e8f9f7 | 159 | spi_frequency(obj, 1000000); |
<> | 144:ef7eb2e8f9f7 | 160 | |
<> | 144:ef7eb2e8f9f7 | 161 | // enable the ssp channel |
<> | 144:ef7eb2e8f9f7 | 162 | ssp_enable(obj); |
<> | 144:ef7eb2e8f9f7 | 163 | |
<> | 144:ef7eb2e8f9f7 | 164 | // pin out the spi pins |
<> | 144:ef7eb2e8f9f7 | 165 | pinmap_pinout(mosi, PinMap_SPI_MOSI); |
<> | 144:ef7eb2e8f9f7 | 166 | pinmap_pinout(miso, PinMap_SPI_MISO); |
<> | 144:ef7eb2e8f9f7 | 167 | pinmap_pinout(sclk, PinMap_SPI_SCLK); |
<> | 144:ef7eb2e8f9f7 | 168 | if (ssel != NC) { |
<> | 144:ef7eb2e8f9f7 | 169 | pinmap_pinout(ssel, PinMap_SPI_SSEL); |
<> | 144:ef7eb2e8f9f7 | 170 | } |
<> | 144:ef7eb2e8f9f7 | 171 | } |
<> | 144:ef7eb2e8f9f7 | 172 | |
<> | 144:ef7eb2e8f9f7 | 173 | void spi_free(spi_t *obj) {} |
<> | 144:ef7eb2e8f9f7 | 174 | |
<> | 144:ef7eb2e8f9f7 | 175 | void spi_format(spi_t *obj, int bits, int mode, int slave) { |
<> | 144:ef7eb2e8f9f7 | 176 | ssp_disable(obj); |
<> | 144:ef7eb2e8f9f7 | 177 | if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) { |
<> | 144:ef7eb2e8f9f7 | 178 | error("SPI format error"); |
<> | 144:ef7eb2e8f9f7 | 179 | } |
<> | 144:ef7eb2e8f9f7 | 180 | |
<> | 144:ef7eb2e8f9f7 | 181 | int polarity = (mode & 0x2) ? 1 : 0; |
<> | 144:ef7eb2e8f9f7 | 182 | int phase = (mode & 0x1) ? 1 : 0; |
<> | 144:ef7eb2e8f9f7 | 183 | |
<> | 144:ef7eb2e8f9f7 | 184 | // set it up |
<> | 144:ef7eb2e8f9f7 | 185 | int DSS = bits - 1; // DSS (data select size) |
<> | 144:ef7eb2e8f9f7 | 186 | int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity |
<> | 144:ef7eb2e8f9f7 | 187 | int SPH = (phase) ? 1 : 0; // SPH - clock out phase |
<> | 144:ef7eb2e8f9f7 | 188 | |
<> | 144:ef7eb2e8f9f7 | 189 | int FRF = 0; // FRF (frame format) = SPI |
<> | 144:ef7eb2e8f9f7 | 190 | uint32_t tmp = obj->spi->CR0; |
<> | 144:ef7eb2e8f9f7 | 191 | tmp &= ~(0xFFFF); |
<> | 144:ef7eb2e8f9f7 | 192 | tmp |= DSS << 0 |
<> | 144:ef7eb2e8f9f7 | 193 | | FRF << 4 |
<> | 144:ef7eb2e8f9f7 | 194 | | SPO << 6 |
<> | 144:ef7eb2e8f9f7 | 195 | | SPH << 7; |
<> | 144:ef7eb2e8f9f7 | 196 | obj->spi->CR0 = tmp; |
<> | 144:ef7eb2e8f9f7 | 197 | |
<> | 144:ef7eb2e8f9f7 | 198 | tmp = obj->spi->CR1; |
<> | 144:ef7eb2e8f9f7 | 199 | tmp &= ~(0xD); |
<> | 144:ef7eb2e8f9f7 | 200 | tmp |= 0 << 0 // LBM - loop back mode - off |
<> | 144:ef7eb2e8f9f7 | 201 | | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave |
<> | 144:ef7eb2e8f9f7 | 202 | | 0 << 3; // SOD - slave output disable - na |
<> | 144:ef7eb2e8f9f7 | 203 | obj->spi->CR1 = tmp; |
<> | 144:ef7eb2e8f9f7 | 204 | |
<> | 144:ef7eb2e8f9f7 | 205 | ssp_enable(obj); |
<> | 144:ef7eb2e8f9f7 | 206 | } |
<> | 144:ef7eb2e8f9f7 | 207 | |
<> | 144:ef7eb2e8f9f7 | 208 | void spi_frequency(spi_t *obj, int hz) { |
<> | 144:ef7eb2e8f9f7 | 209 | ssp_disable(obj); |
<> | 144:ef7eb2e8f9f7 | 210 | |
<> | 144:ef7eb2e8f9f7 | 211 | uint32_t PCLK = SystemCoreClock; |
<> | 144:ef7eb2e8f9f7 | 212 | |
<> | 144:ef7eb2e8f9f7 | 213 | int prescaler; |
<> | 144:ef7eb2e8f9f7 | 214 | |
<> | 144:ef7eb2e8f9f7 | 215 | for (prescaler = 2; prescaler <= 254; prescaler += 2) { |
<> | 144:ef7eb2e8f9f7 | 216 | int prescale_hz = PCLK / prescaler; |
<> | 144:ef7eb2e8f9f7 | 217 | |
<> | 144:ef7eb2e8f9f7 | 218 | // calculate the divider |
<> | 144:ef7eb2e8f9f7 | 219 | int divider = floor(((float)prescale_hz / (float)hz) + 0.5f); |
<> | 144:ef7eb2e8f9f7 | 220 | |
<> | 144:ef7eb2e8f9f7 | 221 | // check we can support the divider |
<> | 144:ef7eb2e8f9f7 | 222 | if (divider < 256) { |
<> | 144:ef7eb2e8f9f7 | 223 | // prescaler |
<> | 144:ef7eb2e8f9f7 | 224 | obj->spi->CPSR = prescaler; |
<> | 144:ef7eb2e8f9f7 | 225 | |
<> | 144:ef7eb2e8f9f7 | 226 | // divider |
<> | 144:ef7eb2e8f9f7 | 227 | obj->spi->CR0 &= ~(0xFFFF << 8); |
<> | 144:ef7eb2e8f9f7 | 228 | obj->spi->CR0 |= (divider - 1) << 8; |
<> | 144:ef7eb2e8f9f7 | 229 | ssp_enable(obj); |
<> | 144:ef7eb2e8f9f7 | 230 | return; |
<> | 144:ef7eb2e8f9f7 | 231 | } |
<> | 144:ef7eb2e8f9f7 | 232 | } |
<> | 144:ef7eb2e8f9f7 | 233 | error("Couldn't setup requested SPI frequency"); |
<> | 144:ef7eb2e8f9f7 | 234 | } |
<> | 144:ef7eb2e8f9f7 | 235 | |
<> | 144:ef7eb2e8f9f7 | 236 | static inline int ssp_disable(spi_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 237 | return obj->spi->CR1 &= ~(1 << 1); |
<> | 144:ef7eb2e8f9f7 | 238 | } |
<> | 144:ef7eb2e8f9f7 | 239 | |
<> | 144:ef7eb2e8f9f7 | 240 | static inline int ssp_enable(spi_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 241 | return obj->spi->CR1 |= SSP_CR1_SSE_Msk; |
<> | 144:ef7eb2e8f9f7 | 242 | } |
<> | 144:ef7eb2e8f9f7 | 243 | |
<> | 144:ef7eb2e8f9f7 | 244 | static inline int ssp_readable(spi_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 245 | return obj->spi->SR & (1 << 2); |
<> | 144:ef7eb2e8f9f7 | 246 | } |
<> | 144:ef7eb2e8f9f7 | 247 | |
<> | 144:ef7eb2e8f9f7 | 248 | static inline int ssp_writeable(spi_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 249 | return obj->spi->SR & SSP_SR_BSY_Msk; |
<> | 144:ef7eb2e8f9f7 | 250 | } |
<> | 144:ef7eb2e8f9f7 | 251 | |
<> | 144:ef7eb2e8f9f7 | 252 | static inline void ssp_write(spi_t *obj, int value) { |
<> | 144:ef7eb2e8f9f7 | 253 | obj->spi->DR = value; |
<> | 144:ef7eb2e8f9f7 | 254 | while (ssp_writeable(obj)); |
<> | 144:ef7eb2e8f9f7 | 255 | } |
<> | 144:ef7eb2e8f9f7 | 256 | static inline int ssp_read(spi_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 257 | int read_DR = obj->spi->DR; |
<> | 144:ef7eb2e8f9f7 | 258 | return read_DR; |
<> | 144:ef7eb2e8f9f7 | 259 | } |
<> | 144:ef7eb2e8f9f7 | 260 | |
<> | 144:ef7eb2e8f9f7 | 261 | static inline int ssp_busy(spi_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 262 | return (obj->spi->SR & (1 << 4)) ? (1) : (0); |
<> | 144:ef7eb2e8f9f7 | 263 | } |
<> | 144:ef7eb2e8f9f7 | 264 | |
<> | 144:ef7eb2e8f9f7 | 265 | int spi_master_write(spi_t *obj, int value) { |
<> | 144:ef7eb2e8f9f7 | 266 | ssp_write(obj, value); |
<> | 144:ef7eb2e8f9f7 | 267 | while (obj->spi->SR & SSP_SR_BSY_Msk); /* Wait for send to finish */ |
<> | 144:ef7eb2e8f9f7 | 268 | return (ssp_read(obj)); |
<> | 144:ef7eb2e8f9f7 | 269 | } |
<> | 144:ef7eb2e8f9f7 | 270 | |
<> | 144:ef7eb2e8f9f7 | 271 | int spi_slave_receive(spi_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 272 | return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0); |
<> | 144:ef7eb2e8f9f7 | 273 | } |
<> | 144:ef7eb2e8f9f7 | 274 | |
<> | 144:ef7eb2e8f9f7 | 275 | int spi_slave_read(spi_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 276 | return obj->spi->DR; |
<> | 144:ef7eb2e8f9f7 | 277 | } |
<> | 144:ef7eb2e8f9f7 | 278 | |
<> | 144:ef7eb2e8f9f7 | 279 | void spi_slave_write(spi_t *obj, int value) { |
<> | 144:ef7eb2e8f9f7 | 280 | while (ssp_writeable(obj) == 0) ; |
<> | 144:ef7eb2e8f9f7 | 281 | obj->spi->DR = value; |
<> | 144:ef7eb2e8f9f7 | 282 | } |
<> | 144:ef7eb2e8f9f7 | 283 | |
<> | 144:ef7eb2e8f9f7 | 284 | int spi_busy(spi_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 285 | return ssp_busy(obj); |
<> | 144:ef7eb2e8f9f7 | 286 | } |