Sergey Solodunov / mbed-dev

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targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_idac.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
50:a417edff4437
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 2 * @file efm32zg_idac.h
bogdanm 0:9b334a45a8ff 3 * @brief EFM32ZG_IDAC register and bit field definitions
bogdanm 0:9b334a45a8ff 4 * @version 3.20.6
bogdanm 0:9b334a45a8ff 5 ******************************************************************************
bogdanm 0:9b334a45a8ff 6 * @section License
bogdanm 0:9b334a45a8ff 7 * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
bogdanm 0:9b334a45a8ff 8 ******************************************************************************
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Permission is granted to anyone to use this software for any purpose,
bogdanm 0:9b334a45a8ff 11 * including commercial applications, and to alter it and redistribute it
bogdanm 0:9b334a45a8ff 12 * freely, subject to the following restrictions:
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 * 1. The origin of this software must not be misrepresented; you must not
bogdanm 0:9b334a45a8ff 15 * claim that you wrote the original software.@n
bogdanm 0:9b334a45a8ff 16 * 2. Altered source versions must be plainly marked as such, and must not be
bogdanm 0:9b334a45a8ff 17 * misrepresented as being the original software.@n
bogdanm 0:9b334a45a8ff 18 * 3. This notice may not be removed or altered from any source distribution.
bogdanm 0:9b334a45a8ff 19 *
bogdanm 0:9b334a45a8ff 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
bogdanm 0:9b334a45a8ff 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
bogdanm 0:9b334a45a8ff 22 * providing the Software "AS IS", with no express or implied warranties of any
bogdanm 0:9b334a45a8ff 23 * kind, including, but not limited to, any implied warranties of
bogdanm 0:9b334a45a8ff 24 * merchantability or fitness for any particular purpose or warranties against
bogdanm 0:9b334a45a8ff 25 * infringement of any proprietary rights of a third party.
bogdanm 0:9b334a45a8ff 26 *
bogdanm 0:9b334a45a8ff 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
bogdanm 0:9b334a45a8ff 28 * incidental, or special damages, or any other relief, or for any claim by
bogdanm 0:9b334a45a8ff 29 * any third party, arising from your use of this Software.
bogdanm 0:9b334a45a8ff 30 *
bogdanm 0:9b334a45a8ff 31 *****************************************************************************/
bogdanm 0:9b334a45a8ff 32 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 33 * @defgroup EFM32ZG_IDAC
bogdanm 0:9b334a45a8ff 34 * @{
bogdanm 0:9b334a45a8ff 35 * @brief EFM32ZG_IDAC Register Declaration
bogdanm 0:9b334a45a8ff 36 *****************************************************************************/
bogdanm 0:9b334a45a8ff 37 typedef struct
bogdanm 0:9b334a45a8ff 38 {
bogdanm 0:9b334a45a8ff 39 __IO uint32_t CTRL; /**< Control Register */
bogdanm 0:9b334a45a8ff 40 __IO uint32_t CURPROG; /**< Current Programming Register */
bogdanm 0:9b334a45a8ff 41 __IO uint32_t CAL; /**< Calibration Register */
bogdanm 0:9b334a45a8ff 42 __IO uint32_t DUTYCONFIG; /**< Duty Cycle Configauration Register */
bogdanm 0:9b334a45a8ff 43 } IDAC_TypeDef; /** @} */
bogdanm 0:9b334a45a8ff 44
bogdanm 0:9b334a45a8ff 45 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 46 * @defgroup EFM32ZG_IDAC_BitFields
bogdanm 0:9b334a45a8ff 47 * @{
bogdanm 0:9b334a45a8ff 48 *****************************************************************************/
bogdanm 0:9b334a45a8ff 49
bogdanm 0:9b334a45a8ff 50 /* Bit fields for IDAC CTRL */
bogdanm 0:9b334a45a8ff 51 #define _IDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 52 #define _IDAC_CTRL_MASK 0x0034001FUL /**< Mask for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 53 #define IDAC_CTRL_EN (0x1UL << 0) /**< Current DAC Enable */
bogdanm 0:9b334a45a8ff 54 #define _IDAC_CTRL_EN_SHIFT 0 /**< Shift value for IDAC_EN */
bogdanm 0:9b334a45a8ff 55 #define _IDAC_CTRL_EN_MASK 0x1UL /**< Bit mask for IDAC_EN */
bogdanm 0:9b334a45a8ff 56 #define _IDAC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 57 #define IDAC_CTRL_EN_DEFAULT (_IDAC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 58 #define IDAC_CTRL_CURSINK (0x1UL << 1) /**< Current Sink Enable */
bogdanm 0:9b334a45a8ff 59 #define _IDAC_CTRL_CURSINK_SHIFT 1 /**< Shift value for IDAC_CURSINK */
bogdanm 0:9b334a45a8ff 60 #define _IDAC_CTRL_CURSINK_MASK 0x2UL /**< Bit mask for IDAC_CURSINK */
bogdanm 0:9b334a45a8ff 61 #define _IDAC_CTRL_CURSINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 62 #define IDAC_CTRL_CURSINK_DEFAULT (_IDAC_CTRL_CURSINK_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 63 #define IDAC_CTRL_MINOUTTRANS (0x1UL << 2) /**< Minimum Output Transition Enable */
bogdanm 0:9b334a45a8ff 64 #define _IDAC_CTRL_MINOUTTRANS_SHIFT 2 /**< Shift value for IDAC_MINOUTTRANS */
bogdanm 0:9b334a45a8ff 65 #define _IDAC_CTRL_MINOUTTRANS_MASK 0x4UL /**< Bit mask for IDAC_MINOUTTRANS */
bogdanm 0:9b334a45a8ff 66 #define _IDAC_CTRL_MINOUTTRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 67 #define IDAC_CTRL_MINOUTTRANS_DEFAULT (_IDAC_CTRL_MINOUTTRANS_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 68 #define IDAC_CTRL_OUTEN (0x1UL << 3) /**< Output Enable */
bogdanm 0:9b334a45a8ff 69 #define _IDAC_CTRL_OUTEN_SHIFT 3 /**< Shift value for IDAC_OUTEN */
bogdanm 0:9b334a45a8ff 70 #define _IDAC_CTRL_OUTEN_MASK 0x8UL /**< Bit mask for IDAC_OUTEN */
bogdanm 0:9b334a45a8ff 71 #define _IDAC_CTRL_OUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 72 #define IDAC_CTRL_OUTEN_DEFAULT (_IDAC_CTRL_OUTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 73 #define IDAC_CTRL_OUTMODE (0x1UL << 4) /**< Output Modes */
bogdanm 0:9b334a45a8ff 74 #define _IDAC_CTRL_OUTMODE_SHIFT 4 /**< Shift value for IDAC_OUTMODE */
bogdanm 0:9b334a45a8ff 75 #define _IDAC_CTRL_OUTMODE_MASK 0x10UL /**< Bit mask for IDAC_OUTMODE */
bogdanm 0:9b334a45a8ff 76 #define _IDAC_CTRL_OUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 77 #define _IDAC_CTRL_OUTMODE_PIN 0x00000000UL /**< Mode PIN for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 78 #define _IDAC_CTRL_OUTMODE_ADC 0x00000001UL /**< Mode ADC for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 79 #define IDAC_CTRL_OUTMODE_DEFAULT (_IDAC_CTRL_OUTMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 80 #define IDAC_CTRL_OUTMODE_PIN (_IDAC_CTRL_OUTMODE_PIN << 4) /**< Shifted mode PIN for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 81 #define IDAC_CTRL_OUTMODE_ADC (_IDAC_CTRL_OUTMODE_ADC << 4) /**< Shifted mode ADC for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 82 #define IDAC_CTRL_OUTENPRS (0x1UL << 18) /**< PRS Controlled Output Enable */
bogdanm 0:9b334a45a8ff 83 #define _IDAC_CTRL_OUTENPRS_SHIFT 18 /**< Shift value for IDAC_OUTENPRS */
bogdanm 0:9b334a45a8ff 84 #define _IDAC_CTRL_OUTENPRS_MASK 0x40000UL /**< Bit mask for IDAC_OUTENPRS */
bogdanm 0:9b334a45a8ff 85 #define _IDAC_CTRL_OUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 86 #define IDAC_CTRL_OUTENPRS_DEFAULT (_IDAC_CTRL_OUTENPRS_DEFAULT << 18) /**< Shifted mode DEFAULT for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 87 #define _IDAC_CTRL_PRSSEL_SHIFT 20 /**< Shift value for IDAC_PRSSEL */
bogdanm 0:9b334a45a8ff 88 #define _IDAC_CTRL_PRSSEL_MASK 0x300000UL /**< Bit mask for IDAC_PRSSEL */
bogdanm 0:9b334a45a8ff 89 #define _IDAC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 90 #define _IDAC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 91 #define _IDAC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 92 #define _IDAC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 93 #define _IDAC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 94 #define IDAC_CTRL_PRSSEL_DEFAULT (_IDAC_CTRL_PRSSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 95 #define IDAC_CTRL_PRSSEL_PRSCH0 (_IDAC_CTRL_PRSSEL_PRSCH0 << 20) /**< Shifted mode PRSCH0 for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 96 #define IDAC_CTRL_PRSSEL_PRSCH1 (_IDAC_CTRL_PRSSEL_PRSCH1 << 20) /**< Shifted mode PRSCH1 for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 97 #define IDAC_CTRL_PRSSEL_PRSCH2 (_IDAC_CTRL_PRSSEL_PRSCH2 << 20) /**< Shifted mode PRSCH2 for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 98 #define IDAC_CTRL_PRSSEL_PRSCH3 (_IDAC_CTRL_PRSSEL_PRSCH3 << 20) /**< Shifted mode PRSCH3 for IDAC_CTRL */
bogdanm 0:9b334a45a8ff 99
bogdanm 0:9b334a45a8ff 100 /* Bit fields for IDAC CURPROG */
bogdanm 0:9b334a45a8ff 101 #define _IDAC_CURPROG_RESETVALUE 0x00000000UL /**< Default value for IDAC_CURPROG */
bogdanm 0:9b334a45a8ff 102 #define _IDAC_CURPROG_MASK 0x00001F03UL /**< Mask for IDAC_CURPROG */
bogdanm 0:9b334a45a8ff 103 #define _IDAC_CURPROG_RANGESEL_SHIFT 0 /**< Shift value for IDAC_RANGESEL */
bogdanm 0:9b334a45a8ff 104 #define _IDAC_CURPROG_RANGESEL_MASK 0x3UL /**< Bit mask for IDAC_RANGESEL */
bogdanm 0:9b334a45a8ff 105 #define _IDAC_CURPROG_RANGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */
bogdanm 0:9b334a45a8ff 106 #define _IDAC_CURPROG_RANGESEL_RANGE0 0x00000000UL /**< Mode RANGE0 for IDAC_CURPROG */
bogdanm 0:9b334a45a8ff 107 #define _IDAC_CURPROG_RANGESEL_RANGE1 0x00000001UL /**< Mode RANGE1 for IDAC_CURPROG */
bogdanm 0:9b334a45a8ff 108 #define _IDAC_CURPROG_RANGESEL_RANGE2 0x00000002UL /**< Mode RANGE2 for IDAC_CURPROG */
bogdanm 0:9b334a45a8ff 109 #define _IDAC_CURPROG_RANGESEL_RANGE3 0x00000003UL /**< Mode RANGE3 for IDAC_CURPROG */
bogdanm 0:9b334a45a8ff 110 #define IDAC_CURPROG_RANGESEL_DEFAULT (_IDAC_CURPROG_RANGESEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CURPROG */
bogdanm 0:9b334a45a8ff 111 #define IDAC_CURPROG_RANGESEL_RANGE0 (_IDAC_CURPROG_RANGESEL_RANGE0 << 0) /**< Shifted mode RANGE0 for IDAC_CURPROG */
bogdanm 0:9b334a45a8ff 112 #define IDAC_CURPROG_RANGESEL_RANGE1 (_IDAC_CURPROG_RANGESEL_RANGE1 << 0) /**< Shifted mode RANGE1 for IDAC_CURPROG */
bogdanm 0:9b334a45a8ff 113 #define IDAC_CURPROG_RANGESEL_RANGE2 (_IDAC_CURPROG_RANGESEL_RANGE2 << 0) /**< Shifted mode RANGE2 for IDAC_CURPROG */
bogdanm 0:9b334a45a8ff 114 #define IDAC_CURPROG_RANGESEL_RANGE3 (_IDAC_CURPROG_RANGESEL_RANGE3 << 0) /**< Shifted mode RANGE3 for IDAC_CURPROG */
bogdanm 0:9b334a45a8ff 115 #define _IDAC_CURPROG_STEPSEL_SHIFT 8 /**< Shift value for IDAC_STEPSEL */
bogdanm 0:9b334a45a8ff 116 #define _IDAC_CURPROG_STEPSEL_MASK 0x1F00UL /**< Bit mask for IDAC_STEPSEL */
bogdanm 0:9b334a45a8ff 117 #define _IDAC_CURPROG_STEPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */
bogdanm 0:9b334a45a8ff 118 #define IDAC_CURPROG_STEPSEL_DEFAULT (_IDAC_CURPROG_STEPSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IDAC_CURPROG */
bogdanm 0:9b334a45a8ff 119
bogdanm 0:9b334a45a8ff 120 /* Bit fields for IDAC CAL */
bogdanm 0:9b334a45a8ff 121 #define _IDAC_CAL_RESETVALUE 0x00000000UL /**< Default value for IDAC_CAL */
bogdanm 0:9b334a45a8ff 122 #define _IDAC_CAL_MASK 0x0000007FUL /**< Mask for IDAC_CAL */
bogdanm 0:9b334a45a8ff 123 #define _IDAC_CAL_TUNING_SHIFT 0 /**< Shift value for IDAC_TUNING */
bogdanm 0:9b334a45a8ff 124 #define _IDAC_CAL_TUNING_MASK 0x7FUL /**< Bit mask for IDAC_TUNING */
bogdanm 0:9b334a45a8ff 125 #define _IDAC_CAL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CAL */
bogdanm 0:9b334a45a8ff 126 #define IDAC_CAL_TUNING_DEFAULT (_IDAC_CAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CAL */
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 /* Bit fields for IDAC DUTYCONFIG */
bogdanm 0:9b334a45a8ff 129 #define _IDAC_DUTYCONFIG_RESETVALUE 0x00000000UL /**< Default value for IDAC_DUTYCONFIG */
bogdanm 0:9b334a45a8ff 130 #define _IDAC_DUTYCONFIG_MASK 0x00000003UL /**< Mask for IDAC_DUTYCONFIG */
bogdanm 0:9b334a45a8ff 131 #define IDAC_DUTYCONFIG_DUTYCYCLEEN (0x1UL << 0) /**< Duty Cycle Enable. */
bogdanm 0:9b334a45a8ff 132 #define _IDAC_DUTYCONFIG_DUTYCYCLEEN_SHIFT 0 /**< Shift value for IDAC_DUTYCYCLEEN */
bogdanm 0:9b334a45a8ff 133 #define _IDAC_DUTYCONFIG_DUTYCYCLEEN_MASK 0x1UL /**< Bit mask for IDAC_DUTYCYCLEEN */
bogdanm 0:9b334a45a8ff 134 #define _IDAC_DUTYCONFIG_DUTYCYCLEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_DUTYCONFIG */
bogdanm 0:9b334a45a8ff 135 #define IDAC_DUTYCONFIG_DUTYCYCLEEN_DEFAULT (_IDAC_DUTYCONFIG_DUTYCYCLEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_DUTYCONFIG */
bogdanm 0:9b334a45a8ff 136 #define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS (0x1UL << 1) /**< EM2/EM3 Duty Cycle Disable. */
bogdanm 0:9b334a45a8ff 137 #define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_SHIFT 1 /**< Shift value for IDAC_EM2DUTYCYCLEDIS */
bogdanm 0:9b334a45a8ff 138 #define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_MASK 0x2UL /**< Bit mask for IDAC_EM2DUTYCYCLEDIS */
bogdanm 0:9b334a45a8ff 139 #define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_DUTYCONFIG */
bogdanm 0:9b334a45a8ff 140 #define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT (_IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_DUTYCONFIG */
bogdanm 0:9b334a45a8ff 141
bogdanm 0:9b334a45a8ff 142 /** @} End of group EFM32ZG_IDAC */
bogdanm 0:9b334a45a8ff 143
bogdanm 0:9b334a45a8ff 144