mbed library sources. Supersedes mbed-src.
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Revision 119:3921aeca8633, committed 2016-04-29
- Comitter:
- mbed_official
- Date:
- Fri Apr 29 01:15:11 2016 +0100
- Parent:
- 118:1e9abb17742b
- Child:
- 120:f2ddb8be7462
- Commit message:
- Synchronized with git revision fe9720f24b1adc71ab6962506ec51290f6afd270
Full URL: https://github.com/mbedmicro/mbed/commit/fe9720f24b1adc71ab6962506ec51290f6afd270/
[Renesas RZ/A1H] Enable asynchronous communications
Changed in this revision
--- a/api/CThunk.h Wed Apr 27 19:30:12 2016 +0100 +++ b/api/CThunk.h Fri Apr 29 01:15:11 2016 +0100 @@ -24,7 +24,7 @@ #define CTHUNK_ADDRESS 1 -#if defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__thumb2__) +#if (defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__thumb2__)) && ! defined(__CORTEX_A9) #define CTHUNK_VARIABLES volatile uint32_t code[1] /** * CTHUNK disassembly for Cortex-M3/M4 (thumb2): @@ -38,7 +38,7 @@ */ #define CTHUNK_ASSIGMENT m_thunk.code[0] = 0x8007E89F -#elif defined(__CORTEX_M0PLUS) || defined(__CORTEX_M0) +#elif defined(__CORTEX_M0PLUS) || defined(__CORTEX_M0) || defined(__CORTEX_A9) /* * CTHUNK disassembly for Cortex M0 (thumb): * * push {r0,r1,r2,r3,r4,lr} save touched registers and return address @@ -194,6 +194,24 @@ m_thunk.callback = (uint32_t)&m_callback; m_thunk.trampoline = (uint32_t)&trampoline; +#if defined(__CORTEX_A9) + /* Data cache clean */ + /* Cache control */ + { + uint32_t start_addr = (uint32_t)&m_thunk & 0xFFFFFFE0; + uint32_t end_addr = (uint32_t)&m_thunk + sizeof(m_thunk); + uint32_t addr; + + /* Data cache clean and invalid */ + for (addr = start_addr; addr < end_addr; addr += 0x20) { + __v7_clean_inv_dcache_mva((void *)addr); + } + /* Instruction cache invalid */ + __v7_inv_icache_all(); + __ca9u_inv_tlb_all(); + __v7_inv_btac(); + } +#endif __ISB(); __DSB(); }
--- a/common/SPI.cpp Wed Apr 27 19:30:12 2016 +0100 +++ b/common/SPI.cpp Fri Apr 29 01:15:11 2016 +0100 @@ -124,7 +124,12 @@ if (_transaction_buffer.full()) { return -1; // the buffer is full } else { + __disable_irq(); _transaction_buffer.push(transaction); + if (!spi_active(&_spi)) { + dequeue_transaction(); + } + __enable_irq(); return 0; } #else
--- a/hal/i2c_api.h Wed Apr 27 19:30:12 2016 +0100 +++ b/hal/i2c_api.h Fri Apr 29 01:15:11 2016 +0100 @@ -124,7 +124,7 @@ /** Write one byte. * @param obj The i2c object * @param data Byte to be written - * @return 1 if NAK was received, 0 if ACK was received, 2 for timeout. + * @return 0 if NAK was received, 1 if ACK was received, 2 for timeout. */ int i2c_byte_write(i2c_t *obj, int data);
--- a/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/MBRZA1H.h Wed Apr 27 19:30:12 2016 +0100 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/MBRZA1H.h Fri Apr 29 01:15:11 2016 +0100 @@ -754,11 +754,12 @@ region.outer_norm_t = WB_WA; \ region.mem_t = NORMAL; \ region.sec_t = NON_SECURE; \ - region.xn_t = NON_EXECUTE; \ + region.xn_t = EXECUTE; \ region.priv_t = RW; \ region.user_t = RW; \ region.sh_t = NON_SHARED; \ __get_section_descriptor(&descriptor_l1, region); + //Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 #define section_so(descriptor_l1, region) region.rg_t = SECTION; \ region.domain = 0x0; \ @@ -788,7 +789,7 @@ region.user_t = READ; \ region.sh_t = NON_SHARED; \ __get_section_descriptor(&descriptor_l1, region); - + //Sect_Device_RW. Sect_Device_RO, but writeable #define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \ region.domain = 0x0; \ @@ -832,6 +833,7 @@ region.user_t = RW; \ region.sh_t = NON_SHARED; \ __get_page_descriptor(&descriptor_l1, &descriptor_l2, region); + /*@}*/ /* end of group Renesas_RZ_A1_MemoryMap */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/RZ_A1_Init.c Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,702 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/**************************************************************************//** +* @file RZ_A1_Init.c +* $Rev: 624 $ +* $Date:: 2013-04-24 13:37:48 +0900#$ +* @brief RZ_A1 Initialize +******************************************************************************/ + +/****************************************************************************** +Includes <System Includes> , "Project Includes" +******************************************************************************/ +#include "VKRZA1H.h" +#include "RZ_A1_Init.h" +#include "rza_io_regrw.h" +#include "gpio_iobitmask.h" + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Macro definitions +******************************************************************************/ +#define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040) +#define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040) + +#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu) + +#define CS2_SDRAM + +/****************************************************************************** +Imported global variables and functions (from other files) +******************************************************************************/ + +/****************************************************************************** +Exported global variables and functions (to be accessed by other files) +******************************************************************************/ + +/****************************************************************************** +Private global variables and functions +******************************************************************************/ + +static void PORT_Init(void) +{ + /* ==== BSC settings ==== */ + + /* ---- P7_2 : RAS# ---- */ + /* Port initialize */ + RZA_IO_RegWrite_16(&GPIO.PIBC7, 0, GPIO_PIBC7_PIBC72_SHIFT, GPIO_PIBC7_PIBC72); + RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC72_SHIFT, GPIO_PBDC7_PBDC72); + RZA_IO_RegWrite_16(&GPIO.PM7, 1, GPIO_PM7_PM72_SHIFT, GPIO_PM7_PM72); + RZA_IO_RegWrite_16(&GPIO.PMC7, 0, GPIO_PMC7_PMC72_SHIFT, GPIO_PMC7_PMC72); + RZA_IO_RegWrite_16(&GPIO.PIPC7, 0, GPIO_PIPC7_PIPC72_SHIFT, GPIO_PIPC7_PIPC72); + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + /* Bidirectional mode : Disable */ + RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC72_SHIFT, GPIO_PBDC7_PBDC72); + RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC72_SHIFT, GPIO_PFC7_PFC72); + RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE72_SHIFT, GPIO_PFCE7_PFCE72); + RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE72_SHIFT, GPIO_PFCAE7_PFCAE72); + RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC72_SHIFT, GPIO_PIPC7_PIPC72); + RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC72_SHIFT, GPIO_PMC7_PMC72); + + /* ---- P7_3 : CAS# ---- */ + /* Port initialize */ + RZA_IO_RegWrite_16(&GPIO.PIBC7, 0, GPIO_PIBC7_PIBC73_SHIFT, GPIO_PIBC7_PIBC73); + RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC73_SHIFT, GPIO_PBDC7_PBDC73); + RZA_IO_RegWrite_16(&GPIO.PM7, 1, GPIO_PM7_PM73_SHIFT, GPIO_PM7_PM73); + RZA_IO_RegWrite_16(&GPIO.PMC7, 0, GPIO_PMC7_PMC73_SHIFT, GPIO_PMC7_PMC73); + RZA_IO_RegWrite_16(&GPIO.PIPC7, 0, GPIO_PIPC7_PIPC73_SHIFT, GPIO_PIPC7_PIPC73); + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + /* Bidirectional mode : Disable */ + RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC73_SHIFT, GPIO_PBDC7_PBDC73); + RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC73_SHIFT, GPIO_PFC7_PFC73); + RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE73_SHIFT, GPIO_PFCE7_PFCE73); + RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE73_SHIFT, GPIO_PFCAE7_PFCAE73); + RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC73_SHIFT, GPIO_PIPC7_PIPC73); + RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC73_SHIFT, GPIO_PMC7_PMC73); + + /* ---- P7_4 : CKE ---- */ + /* Port initialize */ + RZA_IO_RegWrite_16(&GPIO.PIBC7, 0, GPIO_PIBC7_PIBC74_SHIFT, GPIO_PIBC7_PIBC74); + RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC74_SHIFT, GPIO_PBDC7_PBDC74); + RZA_IO_RegWrite_16(&GPIO.PM7, 1, GPIO_PM7_PM74_SHIFT, GPIO_PM7_PM74); + RZA_IO_RegWrite_16(&GPIO.PMC7, 0, GPIO_PMC7_PMC74_SHIFT, GPIO_PMC7_PMC74); + RZA_IO_RegWrite_16(&GPIO.PIPC7, 0, GPIO_PIPC7_PIPC74_SHIFT, GPIO_PIPC7_PIPC74); + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + /* Bidirectional mode : Disable */ + RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC74_SHIFT, GPIO_PBDC7_PBDC74); + RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC74_SHIFT, GPIO_PFC7_PFC74); + RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE74_SHIFT, GPIO_PFCE7_PFCE74); + RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE74_SHIFT, GPIO_PFCAE7_PFCAE74); + RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC74_SHIFT, GPIO_PIPC7_PIPC74); + RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC74_SHIFT, GPIO_PMC7_PMC74); + + /* ---- P7_5 : RD/WR# ---- */ + /* Port initialize */ + RZA_IO_RegWrite_16(&GPIO.PIBC7, 0, GPIO_PIBC7_PIBC75_SHIFT, GPIO_PIBC7_PIBC75); + RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC75_SHIFT, GPIO_PBDC7_PBDC75); + RZA_IO_RegWrite_16(&GPIO.PM7, 1, GPIO_PM7_PM75_SHIFT, GPIO_PM7_PM75); + RZA_IO_RegWrite_16(&GPIO.PMC7, 0, GPIO_PMC7_PMC75_SHIFT, GPIO_PMC7_PMC75); + RZA_IO_RegWrite_16(&GPIO.PIPC7, 0, GPIO_PIPC7_PIPC75_SHIFT, GPIO_PIPC7_PIPC75); + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + /* Bidirectional mode : Disable */ + RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC75_SHIFT, GPIO_PBDC7_PBDC75); + RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC75_SHIFT, GPIO_PFC7_PFC75); + RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE75_SHIFT, GPIO_PFCE7_PFCE75); + RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE75_SHIFT, GPIO_PFCAE7_PFCAE75); + RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC75_SHIFT, GPIO_PIPC7_PIPC75); + RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC75_SHIFT, GPIO_PMC7_PMC75); + + /* ---- P7_6 : DQMLL ---- */ + /* Port initialize */ + RZA_IO_RegWrite_16(&GPIO.PIBC7, 0, GPIO_PIBC7_PIBC76_SHIFT, GPIO_PIBC7_PIBC76); + RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC76_SHIFT, GPIO_PBDC7_PBDC76); + RZA_IO_RegWrite_16(&GPIO.PM7, 1, GPIO_PM7_PM76_SHIFT, GPIO_PM7_PM76); + RZA_IO_RegWrite_16(&GPIO.PMC7, 0, GPIO_PMC7_PMC76_SHIFT, GPIO_PMC7_PMC76); + RZA_IO_RegWrite_16(&GPIO.PIPC7, 0, GPIO_PIPC7_PIPC76_SHIFT, GPIO_PIPC7_PIPC76); + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + /* Bidirectional mode : Disable */ + RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC76_SHIFT, GPIO_PBDC7_PBDC76); + RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC76_SHIFT, GPIO_PFC7_PFC76); + RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE76_SHIFT, GPIO_PFCE7_PFCE76); + RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE76_SHIFT, GPIO_PFCAE7_PFCAE76); + RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC76_SHIFT, GPIO_PIPC7_PIPC76); + RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC76_SHIFT, GPIO_PMC7_PMC76); + + /* ---- P7_7 : DQMLU ---- */ + /* Port initialize */ + RZA_IO_RegWrite_16(&GPIO.PIBC7, 0, GPIO_PIBC7_PIBC77_SHIFT, GPIO_PIBC7_PIBC77); + RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC77_SHIFT, GPIO_PBDC7_PBDC77); + RZA_IO_RegWrite_16(&GPIO.PM7, 1, GPIO_PM7_PM77_SHIFT, GPIO_PM7_PM77); + RZA_IO_RegWrite_16(&GPIO.PMC7, 0, GPIO_PMC7_PMC77_SHIFT, GPIO_PMC7_PMC77); + RZA_IO_RegWrite_16(&GPIO.PIPC7, 0, GPIO_PIPC7_PIPC77_SHIFT, GPIO_PIPC7_PIPC77); + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + /* Bidirectional mode : Disable */ + RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC77_SHIFT, GPIO_PBDC7_PBDC77); + RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC77_SHIFT, GPIO_PFC7_PFC77); + RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE77_SHIFT, GPIO_PFCE7_PFCE77); + RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE77_SHIFT, GPIO_PFCAE7_PFCAE77); + RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC77_SHIFT, GPIO_PIPC7_PIPC77); + RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC77_SHIFT, GPIO_PMC7_PMC77); + + /* ---- P5_8 : CS2# ---- */ + /* Port initialize */ + RZA_IO_RegWrite_16(&GPIO.PIBC5, 0, GPIO_PIBC5_PIBC58_SHIFT, GPIO_PIBC5_PIBC58); + RZA_IO_RegWrite_16(&GPIO.PBDC5, 0, GPIO_PBDC5_PBDC58_SHIFT, GPIO_PBDC5_PBDC58); + RZA_IO_RegWrite_16(&GPIO.PM5, 1, GPIO_PM5_PM58_SHIFT, GPIO_PM5_PM58); + RZA_IO_RegWrite_16(&GPIO.PMC5, 0, GPIO_PMC5_PMC58_SHIFT, GPIO_PMC5_PMC58); + RZA_IO_RegWrite_16(&GPIO.PIPC5, 0, GPIO_PIPC5_PIPC58_SHIFT, GPIO_PIPC5_PIPC58); + /* Port mode : Multiplex mode */ + /* Port function setting : 6th multiplex function */ + /* I/O control mode : Peripheral function */ + /* Bidirectional mode : Disable */ + RZA_IO_RegWrite_16(&GPIO.PBDC5, 0, GPIO_PBDC5_PBDC58_SHIFT, GPIO_PBDC5_PBDC58); + RZA_IO_RegWrite_16(&GPIO.PFC5, 1, GPIO_PFC5_PFC58_SHIFT, GPIO_PFC5_PFC58); + RZA_IO_RegWrite_16(&GPIO.PFCE5, 0, GPIO_PFCE5_PFCE58_SHIFT, GPIO_PFCE5_PFCE58); + RZA_IO_RegWrite_16(&GPIO.PFCAE5, 1, GPIO_PFCAE5_PFCAE58_SHIFT, GPIO_PFCAE5_PFCAE58); + RZA_IO_RegWrite_16(&GPIO.PIPC5, 1, GPIO_PIPC5_PIPC58_SHIFT, GPIO_PIPC5_PIPC58); + RZA_IO_RegWrite_16(&GPIO.PMC5, 1, GPIO_PMC5_PMC58_SHIFT, GPIO_PMC5_PMC58); + + /* ---- P7_1 : CS3# ---- */ + /* Port initialize */ +// RZA1_IO_RegWrite_16(&GPIO.PIBC7, 0, GPIO_PIBC7_PIBC71_SHIFT, GPIO_PIBC7_PIBC71); +// RZA1_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC71_SHIFT, GPIO_PBDC7_PBDC71); +// RZA1_IO_RegWrite_16(&GPIO.PM7, 1, GPIO_PM7_PM71_SHIFT, GPIO_PM7_PM71); +// RZA1_IO_RegWrite_16(&GPIO.PMC7, 0, GPIO_PMC7_PMC71_SHIFT, GPIO_PMC7_PMC71); +// RZA1_IO_RegWrite_16(&GPIO.PIPC7, 0, GPIO_PIPC7_PIPC71_SHIFT, GPIO_PIPC7_PIPC71); +// /* Port mode : Multiplex mode */ +// /* Port function setting : 1st multiplex function */ +// /* I/O control mode : Peripheral function */ +// /* Bidirectional mode : Disable */ +// RZA1_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC71_SHIFT, GPIO_PBDC7_PBDC71); +// RZA1_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC71_SHIFT, GPIO_PFC7_PFC71); +// RZA1_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE71_SHIFT, GPIO_PFCE7_PFCE71); +// RZA1_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE71_SHIFT, GPIO_PFCAE7_PFCAE71); +// RZA1_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC71_SHIFT, GPIO_PIPC7_PIPC71); +// RZA1_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC71_SHIFT, GPIO_PMC7_PMC71); +} + +/****************************************************************************** +* Function Name: CS2_PORTInit +* Description : Sets the PORT multiplexed pin to use the CS2 and the CS3 +* : spaces. In this sample code, the PORT setting is executed to +* : use the NOR flash memory in the CS0 and the CS1 spaces. +* Arguments : none +* Return Value : none +******************************************************************************/ +static void CS2_PORTInit(void) +{ + /* ---- P6_0 : D0 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE60_SHIFT, GPIO_PFCAE6_PFCAE60); + RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE60_SHIFT, GPIO_PFCE6_PFCE60); + RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC60_SHIFT, GPIO_PFC6_PFC60); + RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC60_SHIFT, GPIO_PMC6_PMC60); + RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC60_SHIFT, GPIO_PIPC6_PIPC60); + + /* ---- P6_1 : D1 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE61_SHIFT, GPIO_PFCAE6_PFCAE61); + RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE61_SHIFT, GPIO_PFCE6_PFCE61); + RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC61_SHIFT, GPIO_PFC6_PFC61); + RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC61_SHIFT, GPIO_PMC6_PMC61); + RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC61_SHIFT, GPIO_PIPC6_PIPC61); + + /* ---- P6_2 : D2 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE62_SHIFT, GPIO_PFCAE6_PFCAE62); + RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE62_SHIFT, GPIO_PFCE6_PFCE62); + RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC62_SHIFT, GPIO_PFC6_PFC62); + RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC62_SHIFT, GPIO_PMC6_PMC62); + RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC62_SHIFT, GPIO_PIPC6_PIPC62); + + /* ---- P6_3 : D3 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE63_SHIFT, GPIO_PFCAE6_PFCAE63); + RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE63_SHIFT, GPIO_PFCE6_PFCE63); + RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC63_SHIFT, GPIO_PFC6_PFC63); + RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC63_SHIFT, GPIO_PMC6_PMC63); + RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC63_SHIFT, GPIO_PIPC6_PIPC63); + + /* ---- P6_4 : D4 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE64_SHIFT, GPIO_PFCAE6_PFCAE64); + RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE64_SHIFT, GPIO_PFCE6_PFCE64); + RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC64_SHIFT, GPIO_PFC6_PFC64); + RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC64_SHIFT, GPIO_PMC6_PMC64); + RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC64_SHIFT, GPIO_PIPC6_PIPC64); + + /* ---- P6_5 : D5 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE65_SHIFT, GPIO_PFCAE6_PFCAE65); + RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE65_SHIFT, GPIO_PFCE6_PFCE65); + RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC65_SHIFT, GPIO_PFC6_PFC65); + RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC65_SHIFT, GPIO_PMC6_PMC65); + RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC65_SHIFT, GPIO_PIPC6_PIPC65); + + /* ---- P6_6 : D6 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE66_SHIFT, GPIO_PFCAE6_PFCAE66); + RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE66_SHIFT, GPIO_PFCE6_PFCE66); + RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC66_SHIFT, GPIO_PFC6_PFC66); + RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC66_SHIFT, GPIO_PMC6_PMC66); + RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC66_SHIFT, GPIO_PIPC6_PIPC66); + + /* ---- P6_7 : D7 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE67_SHIFT, GPIO_PFCAE6_PFCAE67); + RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE67_SHIFT, GPIO_PFCE6_PFCE67); + RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC67_SHIFT, GPIO_PFC6_PFC67); + RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC67_SHIFT, GPIO_PMC6_PMC67); + RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC67_SHIFT, GPIO_PIPC6_PIPC67); + + /* ---- P6_8 : D8 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE68_SHIFT, GPIO_PFCAE6_PFCAE68); + RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE68_SHIFT, GPIO_PFCE6_PFCE68); + RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC68_SHIFT, GPIO_PFC6_PFC68); + RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC68_SHIFT, GPIO_PMC6_PMC68); + RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC68_SHIFT, GPIO_PIPC6_PIPC68); + + /* ---- P6_9 : D9 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE69_SHIFT, GPIO_PFCAE6_PFCAE69); + RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE69_SHIFT, GPIO_PFCE6_PFCE69); + RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC69_SHIFT, GPIO_PFC6_PFC69); + RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC69_SHIFT, GPIO_PMC6_PMC69); + RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC69_SHIFT, GPIO_PIPC6_PIPC69); + + /* ---- P6_10 : D10 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE610_SHIFT, GPIO_PFCAE6_PFCAE610); + RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE610_SHIFT, GPIO_PFCE6_PFCE610); + RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC610_SHIFT, GPIO_PFC6_PFC610); + RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC610_SHIFT, GPIO_PMC6_PMC610); + RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC610_SHIFT, GPIO_PIPC6_PIPC610); + + /* ---- P6_11 : D11 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE611_SHIFT, GPIO_PFCAE6_PFCAE611); + RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE611_SHIFT, GPIO_PFCE6_PFCE611); + RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC611_SHIFT, GPIO_PFC6_PFC611); + RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC611_SHIFT, GPIO_PMC6_PMC611); + RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC611_SHIFT, GPIO_PIPC6_PIPC611); + + /* ---- P6_12 : D12 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE612_SHIFT, GPIO_PFCAE6_PFCAE612); + RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE612_SHIFT, GPIO_PFCE6_PFCE612); + RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC612_SHIFT, GPIO_PFC6_PFC612); + RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC612_SHIFT, GPIO_PMC6_PMC612); + RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC612_SHIFT, GPIO_PIPC6_PIPC612); + + /* ---- P6_13 : D13 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE613_SHIFT, GPIO_PFCAE6_PFCAE613); + RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE613_SHIFT, GPIO_PFCE6_PFCE613); + RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC613_SHIFT, GPIO_PFC6_PFC613); + RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC613_SHIFT, GPIO_PMC6_PMC613); + RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC613_SHIFT, GPIO_PIPC6_PIPC613); + + /* ---- P6_14 : D14 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE614_SHIFT, GPIO_PFCAE6_PFCAE614); + RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE614_SHIFT, GPIO_PFCE6_PFCE614); + RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC614_SHIFT, GPIO_PFC6_PFC614); + RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC614_SHIFT, GPIO_PMC6_PMC614); + RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC614_SHIFT, GPIO_PIPC6_PIPC614); + + /* ---- P6_15 : D15 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE615_SHIFT, GPIO_PFCAE6_PFCAE615); + RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE615_SHIFT, GPIO_PFCE6_PFCE615); + RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC615_SHIFT, GPIO_PFC6_PFC615); + RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC615_SHIFT, GPIO_PMC6_PMC615); + RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC615_SHIFT, GPIO_PIPC6_PIPC615); + + /* ---- P7_9 : A1 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE79_SHIFT, GPIO_PFCAE7_PFCAE79); + RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE79_SHIFT, GPIO_PFCE7_PFCE79); + RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC79_SHIFT, GPIO_PFC7_PFC79); + RZA_IO_RegWrite_16(&GPIO.PM7, 0, GPIO_PM7_PM79_SHIFT, GPIO_PM7_PM79); + RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC79_SHIFT, GPIO_PMC7_PMC79); + RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC79_SHIFT, GPIO_PIPC7_PIPC79); + + /* ---- P7_10 : A2 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE710_SHIFT, GPIO_PFCAE7_PFCAE710); + RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE710_SHIFT, GPIO_PFCE7_PFCE710); + RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC710_SHIFT, GPIO_PFC7_PFC710); + RZA_IO_RegWrite_16(&GPIO.PM7, 0, GPIO_PM7_PM710_SHIFT, GPIO_PM7_PM710); + RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC710_SHIFT, GPIO_PMC7_PMC710); + RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC710_SHIFT, GPIO_PIPC7_PIPC710); + + /* ---- P7_11 : A3 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE711_SHIFT, GPIO_PFCAE7_PFCAE711); + RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE711_SHIFT, GPIO_PFCE7_PFCE711); + RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC711_SHIFT, GPIO_PFC7_PFC711); + RZA_IO_RegWrite_16(&GPIO.PM7, 0, GPIO_PM7_PM711_SHIFT, GPIO_PM7_PM711); + RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC711_SHIFT, GPIO_PMC7_PMC711); + RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC711_SHIFT, GPIO_PIPC7_PIPC711); + + /* ---- P7_12 : A4 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE712_SHIFT, GPIO_PFCAE7_PFCAE712); + RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE712_SHIFT, GPIO_PFCE7_PFCE712); + RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC712_SHIFT, GPIO_PFC7_PFC712); + RZA_IO_RegWrite_16(&GPIO.PM7, 0, GPIO_PM7_PM712_SHIFT, GPIO_PM7_PM712); + RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC712_SHIFT, GPIO_PMC7_PMC712); + RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC712_SHIFT, GPIO_PIPC7_PIPC712); + + /* ---- P7_13 : A5 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE713_SHIFT, GPIO_PFCAE7_PFCAE713); + RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE713_SHIFT, GPIO_PFCE7_PFCE713); + RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC713_SHIFT, GPIO_PFC7_PFC713); + RZA_IO_RegWrite_16(&GPIO.PM7, 0, GPIO_PM7_PM713_SHIFT, GPIO_PM7_PM713); + RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC713_SHIFT, GPIO_PMC7_PMC713); + RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC713_SHIFT, GPIO_PIPC7_PIPC713); + + /* ---- P7_14 : A6 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE714_SHIFT, GPIO_PFCAE7_PFCAE714); + RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE714_SHIFT, GPIO_PFCE7_PFCE714); + RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC714_SHIFT, GPIO_PFC7_PFC714); + RZA_IO_RegWrite_16(&GPIO.PM7, 0, GPIO_PM7_PM714_SHIFT, GPIO_PM7_PM714); + RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC714_SHIFT, GPIO_PMC7_PMC714); + RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC714_SHIFT, GPIO_PIPC7_PIPC714); + + /* ---- P7_15 : A7 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE715_SHIFT, GPIO_PFCAE7_PFCAE715); + RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE715_SHIFT, GPIO_PFCE7_PFCE715); + RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC715_SHIFT, GPIO_PFC7_PFC715); + RZA_IO_RegWrite_16(&GPIO.PM7, 0, GPIO_PM7_PM715_SHIFT, GPIO_PM7_PM715); + RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC715_SHIFT, GPIO_PMC7_PMC715); + RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC715_SHIFT, GPIO_PIPC7_PIPC715); + + /* ---- P8_0 : A8 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE80_SHIFT, GPIO_PFCAE8_PFCAE80); + RZA_IO_RegWrite_16(&GPIO.PFCE8, 0, GPIO_PFCE8_PFCE80_SHIFT, GPIO_PFCE8_PFCE80); + RZA_IO_RegWrite_16(&GPIO.PFC8, 0, GPIO_PFC8_PFC80_SHIFT, GPIO_PFC8_PFC80); + RZA_IO_RegWrite_16(&GPIO.PMC8, 1, GPIO_PMC8_PMC80_SHIFT, GPIO_PMC8_PMC80); + RZA_IO_RegWrite_16(&GPIO.PIPC8, 1, GPIO_PIPC8_PIPC80_SHIFT, GPIO_PIPC8_PIPC80); + + /* ---- P8_1 : A9 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE81_SHIFT, GPIO_PFCAE8_PFCAE81); + RZA_IO_RegWrite_16(&GPIO.PFCE8, 0, GPIO_PFCE8_PFCE81_SHIFT, GPIO_PFCE8_PFCE81); + RZA_IO_RegWrite_16(&GPIO.PFC8, 0, GPIO_PFC8_PFC81_SHIFT, GPIO_PFC8_PFC81); + RZA_IO_RegWrite_16(&GPIO.PM8, 0, GPIO_PM8_PM81_SHIFT, GPIO_PM8_PM81); + RZA_IO_RegWrite_16(&GPIO.PMC8, 1, GPIO_PMC8_PMC81_SHIFT, GPIO_PMC8_PMC81); + RZA_IO_RegWrite_16(&GPIO.PIPC8, 1, GPIO_PIPC8_PIPC81_SHIFT, GPIO_PIPC8_PIPC81); + + /* ---- P8_2 : A10 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE82_SHIFT, GPIO_PFCAE8_PFCAE82); + RZA_IO_RegWrite_16(&GPIO.PFCE8, 0, GPIO_PFCE8_PFCE82_SHIFT, GPIO_PFCE8_PFCE82); + RZA_IO_RegWrite_16(&GPIO.PFC8, 0, GPIO_PFC8_PFC82_SHIFT, GPIO_PFC8_PFC82); + RZA_IO_RegWrite_16(&GPIO.PM8, 0, GPIO_PM8_PM82_SHIFT, GPIO_PM8_PM82); + RZA_IO_RegWrite_16(&GPIO.PMC8, 1, GPIO_PMC8_PMC82_SHIFT, GPIO_PMC8_PMC82); + RZA_IO_RegWrite_16(&GPIO.PIPC8, 1, GPIO_PIPC8_PIPC82_SHIFT, GPIO_PIPC8_PIPC82); + + /* ---- P8_3 : A11 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE83_SHIFT, GPIO_PFCAE8_PFCAE83); + RZA_IO_RegWrite_16(&GPIO.PFCE8, 0, GPIO_PFCE8_PFCE83_SHIFT, GPIO_PFCE8_PFCE83); + RZA_IO_RegWrite_16(&GPIO.PFC8, 0, GPIO_PFC8_PFC83_SHIFT, GPIO_PFC8_PFC83); + RZA_IO_RegWrite_16(&GPIO.PM8, 0, GPIO_PM8_PM83_SHIFT, GPIO_PM8_PM83); + RZA_IO_RegWrite_16(&GPIO.PMC8, 1, GPIO_PMC8_PMC83_SHIFT, GPIO_PMC8_PMC83); + RZA_IO_RegWrite_16(&GPIO.PIPC8, 1, GPIO_PIPC8_PIPC83_SHIFT, GPIO_PIPC8_PIPC83); + + /* ---- P8_4 : A12 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE84_SHIFT, GPIO_PFCAE8_PFCAE84); + RZA_IO_RegWrite_16(&GPIO.PFCE8, 0, GPIO_PFCE8_PFCE84_SHIFT, GPIO_PFCE8_PFCE84); + RZA_IO_RegWrite_16(&GPIO.PFC8, 0, GPIO_PFC8_PFC84_SHIFT, GPIO_PFC8_PFC84); + RZA_IO_RegWrite_16(&GPIO.PM8, 0, GPIO_PM8_PM84_SHIFT, GPIO_PM8_PM84); + RZA_IO_RegWrite_16(&GPIO.PMC8, 1, GPIO_PMC8_PMC84_SHIFT, GPIO_PMC8_PMC84); + RZA_IO_RegWrite_16(&GPIO.PIPC8, 1, GPIO_PIPC8_PIPC84_SHIFT, GPIO_PIPC8_PIPC84); + + /* ---- P8_5 : A13 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE85_SHIFT, GPIO_PFCAE8_PFCAE85); + RZA_IO_RegWrite_16(&GPIO.PFCE8, 0, GPIO_PFCE8_PFCE85_SHIFT, GPIO_PFCE8_PFCE85); + RZA_IO_RegWrite_16(&GPIO.PFC8, 0, GPIO_PFC8_PFC85_SHIFT, GPIO_PFC8_PFC85); + RZA_IO_RegWrite_16(&GPIO.PM8, 0, GPIO_PM8_PM85_SHIFT, GPIO_PM8_PM85); + RZA_IO_RegWrite_16(&GPIO.PMC8, 1, GPIO_PMC8_PMC85_SHIFT, GPIO_PMC8_PMC85); + RZA_IO_RegWrite_16(&GPIO.PIPC8, 1, GPIO_PIPC8_PIPC85_SHIFT, GPIO_PIPC8_PIPC85); + + /* ---- P8_6 : A14 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE86_SHIFT, GPIO_PFCAE8_PFCAE86); + RZA_IO_RegWrite_16(&GPIO.PFCE8, 0, GPIO_PFCE8_PFCE86_SHIFT, GPIO_PFCE8_PFCE86); + RZA_IO_RegWrite_16(&GPIO.PFC8, 0, GPIO_PFC8_PFC86_SHIFT, GPIO_PFC8_PFC86); + RZA_IO_RegWrite_16(&GPIO.PM8, 0, GPIO_PM8_PM86_SHIFT, GPIO_PM8_PM86); + RZA_IO_RegWrite_16(&GPIO.PMC8, 1, GPIO_PMC8_PMC86_SHIFT, GPIO_PMC8_PMC86); + RZA_IO_RegWrite_16(&GPIO.PIPC8, 1, GPIO_PIPC8_PIPC86_SHIFT, GPIO_PIPC8_PIPC86); + + /* ---- P8_7 : A15 ---- */ + /* Port mode : Multiplex mode */ + /* Port function setting : 1st multiplex function */ + /* I/O control mode : Peripheral function */ + RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE87_SHIFT, GPIO_PFCAE8_PFCAE87); + RZA_IO_RegWrite_16(&GPIO.PFCE8, 0, GPIO_PFCE8_PFCE87_SHIFT, GPIO_PFCE8_PFCE87); + RZA_IO_RegWrite_16(&GPIO.PFC8, 0, GPIO_PFC8_PFC87_SHIFT, GPIO_PFC8_PFC87); + RZA_IO_RegWrite_16(&GPIO.PM8, 0, GPIO_PM8_PM87_SHIFT, GPIO_PM8_PM87); + RZA_IO_RegWrite_16(&GPIO.PMC8, 1, GPIO_PMC8_PMC87_SHIFT, GPIO_PMC8_PMC87); + RZA_IO_RegWrite_16(&GPIO.PIPC8, 1, GPIO_PIPC8_PIPC87_SHIFT, GPIO_PIPC8_PIPC87); +} + + +/****************************************************************************** +* Function Name: Userdef_BSC_CS2Init +* Description : This is the user-defined function called by the R_BSC_Init +* : function. The setting for initialization of the BSC in the CS2 +* : space is required. In this sample code, the setting to use +* : the SDRAM in the CS2 space is executed. Sets the BSC to +* : connect the ISSI IS42S16320B-75 to the CS2 space with 16-bit +* : bus width. +* Arguments : none +* Return Value : none +******************************************************************************/ +static void CS2_BSC_Init(void) +{ + /* ==== CS2BCR settings ==== */ + /* Idle Cycles between Write-read Cycles */ + /* and Write-write Cycles : 0 idle cycles */ + /* Memory type :SDRAM */ + /* Data Bus Size : 16-bit */ + BSC.CS2BCR = 0x00004C00ul; + + /* ==== CS3BCR settings ==== */ + /* SDRAM WORKAROUND - see Note */ + /* Idle Cycles between Write-read Cycles */ + /* and Write-write Cycles : 0 idle cycles */ + /* Memory type :SDRAM */ + /* Data Bus Size : 16-bit */ + BSC.CS3BCR = 0x00004C00ul; + + /* ==== CS2/3WCR settings ==== */ + /* Precharge completion wait cycles: 1 cycle */ + /* Wait cycles between ACTV command */ + /* and READ(A)/WRITE(A) command : 1 cycles */ + /* CAS latency for Area 3 : 2 cycles */ + /* Auto-precharge startup wait cycles : 2 cycles */ + /* Idle cycles from REF command/self-refresh */ + /* Release to ACTV/REF/MRS command : 5 cycles */ + BSC.CS3WCR = 0x00002492ul; + + /* SDRAM WORKAROUND - see Note */ + BSC.CS2WCR = 0x00000480ul; + + /* ==== SDCR settings ==== */ + /* SDRAM WORKAROUND - see Note*/ + /* Row address for Area 2 : 13-bit */ + /* Column Address for Area 2 : 9-bit */ + /* Refresh Control :Refresh */ + /* RMODE :Auto-refresh is performed */ + /* BACTV :Auto-precharge mode */ + /* Row address for Area 3 : 13-bit */ + /* Column Address for Area 3 : 9-bit */ + BSC.SDCR = 0x00110811ul; + + /* ==== RTCOR settings ==== */ + /* 7.8usec / 60nsec */ + /* = 32(0x40)cycles per refresh */ + BSC.RTCOR = 0xA55A0020ul; + + /* ==== RTCSR settings ==== */ + /* initialisation sequence start */ + /* Clock select B-phy/16 */ + /* Refresh count :Once */ + BSC.RTCSR = 0xA55A0010ul; + + + /* ==== SDRAM Mode Register ==== */ + /* Burst read (burst length 1)./Burst write */ + CS2_SDRAM_MODE_16BIT_CAS2_BR_BW = 0; + + /* SDRAM WORKAROUND - see Note */ + CS3_SDRAM_MODE_16BIT_CAS2_BR_BW = 0; + +} + +/**************************************************************************//** +* Function Name: RZ_A1_SetSramWriteEnable +* @brief Initialize Board settings +* +* Description:<br> +* Set SRAM write enable +* @param none +* @retval none +******************************************************************************/ +void RZ_A1_SetSramWriteEnable(void) +{ + /* Enable SRAM write access */ + CPG.SYSCR3 = 0x0F; + + return; +} + +/**************************************************************************//** +* Function Name: RZ_A1_InitClock +* @brief Initialize Board settings +* +* Description:<br> +* Initialize Clock +* @param none +* @retval none +******************************************************************************/ +void RZ_A1_InitClock(void) +{ + /* Cancel L2C standby status before clock change */ + L2CREG15_POWER_CTRL = 0x00000001; + + /* Clock settings */ + /* ClockMode0 */ + CPG.FRQCR = 0x1035; /* CPU Clock =399.99MHz */ + CPG.FRQCR2 = 0x0001; /* G Clock =266.66MHz */ + + return; +} + +/**************************************************************************//** +* Function Name: RZ_A1_IsClockMode0 +* @brief Query Clock Mode +* +* Description:<br> +* Answer ClockMode0 or not +* @param none +* @retval true : clock mode 0 +* @retval false : clock mode 1 +******************************************************************************/ +int RZ_A1_IsClockMode0(void) +{ + /* ClockMode0 */ + return true; +} + +/**************************************************************************//** +* Function Name: RZ_A1_InitBus +* @brief Initialize Bus +* +* Description:<br> +* Initialize Pin Setting +* @param none +* @retval none +******************************************************************************/ +void RZ_A1_InitBus(void) +{ + /*************************************************************************/ + /* If need Pin Setting before run program, the setting will be wrote here*/ + /*************************************************************************/ +#if defined(CS2_SDRAM) + PORT_Init(); + CS2_PORTInit(); + CS2_BSC_Init(); +#else + return; +#endif +} + +/****************************************************************************** +End of file +******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/RZ_A1_Init.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,71 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/**************************************************************************//** +* @file RZ_A1_Init.h +* $Rev: 531 $ +* $Date:: 2013-04-16 13:07:35 +0900#$ +* @brief RZ_A1 Initialize +******************************************************************************/ + +#ifndef RZ_A1_INIT_H +#define RZ_A1_INIT_H + +/****************************************************************************** +Includes <System Includes> , "Project Includes" +******************************************************************************/ +#include <stdio.h> +#include <stdbool.h> +#include "iodefine.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Macro definitions +******************************************************************************/ + +/****************************************************************************** +Variable Externs +******************************************************************************/ + +/****************************************************************************** +Functions Prototypes +******************************************************************************/ + +void RZ_A1_SetSramWriteEnable(void); +void RZ_A1_InitClock(void); +int RZ_A1_IsClockMode0(void); +void RZ_A1_InitBus(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* RZ_A1_INIT_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/TOOLCHAIN_ARM_STD/VKRZA1H.sct Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,42 @@ + + +LOAD_TTB 0x20000000 0x00004000 ; Page 0 of On-Chip Data Retention RAM +{ + TTB +0 EMPTY 0x4000 + { } ; Level-1 Translation Table for MMU +} + +SDRAM 0x08000000 0x02000000 ; 32MB External SDRAM region +{ +} + +SFLASH_DUAL 0x18020000 (32*1024*1024-2*64*1024) +{ + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; S-Flash ROM : Executable cached region + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + VECTORS 0x18020000 FIXED + { + * (RESET, +FIRST) ; Vector table and other (assembler) startup code + * (InRoot$$Sections) ; All (library) code that must be in a root region + * (+RO-CODE) ; Application RO code (.text) + } + + RO_DATA +0 + { * (+RO-DATA) } ; Application RO data (.constdata) + + RW_DATA 0x20020000 + { * (+RW) } ; Application RW data (.data) + + ZI_DATA +0 ALIGN 0x400 + { * (+ZI) } ; Application ZI data (.bss) + + RW_DATA_NC 0x60900000 0x00100000 + { * (NC_DATA) } ; Application RW data Non cached area + + ZI_DATA_NC +0 + { * (NC_BSS) } ; Application ZI data Non cached area +} + +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/TOOLCHAIN_ARM_STD/startup_VKRZA1H.S Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,454 @@ +;/***************************************************************************** +; * @file: startup_VKRZA1H.s +; * @purpose: CMSIS Cortex-A9 Core Device Startup File +; * for the Renesas RZA1H Device Series +; * @version: V1.02, modified for mbed +; * @date: 27. July 2009, modified 3rd Aug 2009 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * Copyright (C) 2009 ARM Limited. All rights reserved. +; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; *****************************************************************************/ + +GICI_BASE EQU 0xe8202000 +ICCIAR_OFFSET EQU 0x0000000C +ICCEOIR_OFFSET EQU 0x00000010 +ICCHPIR_OFFSET EQU 0x00000018 + +GICD_BASE EQU 0xe8201000 +ICDISER0_OFFSET EQU 0x00000100 +ICDICER0_OFFSET EQU 0x00000180 +ICDISPR0_OFFSET EQU 0x00000200 +ICDABR0_OFFSET EQU 0x00000300 +ICDIPR0_OFFSET EQU 0x00000400 + +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UND EQU 0x1B +Mode_SYS EQU 0x1F + +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled +T_Bit EQU 0x20 ; when T bit is set, core is in Thumb state + +GIC_ERRATA_CHECK_1 EQU 0x000003FE +GIC_ERRATA_CHECK_2 EQU 0x000003FF + + +Sect_Normal EQU 0x00005c06 ;outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 +Sect_Normal_Cod EQU 0x0000dc06 ;outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 +Sect_Normal_RO EQU 0x0000dc16 ;as Sect_Normal_Cod, but not executable +Sect_Normal_RW EQU 0x00005c16 ;as Sect_Normal_Cod, but writeable and not executable +Sect_SO EQU 0x00000c12 ;strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 +Sect_Device_RO EQU 0x00008c12 ;device, non-shareable, non-executable, ro, domain 0, base addr 0 +Sect_Device_RW EQU 0x00000c12 ;as Sect_Device_RO, but writeable +Sect_Fault EQU 0x00000000 ;this translation will fault (the bottom 2 bits are important, the rest are ignored) + +RAM_BASE EQU 0x80000000 +VRAM_BASE EQU 0x18000000 +SRAM_BASE EQU 0x2e000000 +ETHERNET EQU 0x1a000000 +CS3_PERIPHERAL_BASE EQU 0x1c000000 + +; <h> Stack Configuration +; <o> Stack Size (in Bytes, per mode) <0x0-0xFFFFFFFF:8> +; </h> + +UND_Stack_Size EQU 0x00000100 +SVC_Stack_Size EQU 0x00008000 +ABT_Stack_Size EQU 0x00000100 +FIQ_Stack_Size EQU 0x00000100 +IRQ_Stack_Size EQU 0x00008000 +USR_Stack_Size EQU 0x00004000 + +ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ + FIQ_Stack_Size + IRQ_Stack_Size) + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE USR_Stack_Size +__initial_sp SPACE ISR_Stack_Size + +Stack_Top + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00080000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + ARM + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, CODE, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors LDR PC, Reset_Addr ; Address of Reset Handler + LDR PC, Undef_Addr ; Address of Undef Handler + LDR PC, SVC_Addr ; Address of SVC Handler + LDR PC, PAbt_Addr ; Address of Prefetch Abort Handler + LDR PC, DAbt_Addr ; Address of Data Abort Handler + NOP ; Reserved Vector + LDR PC, IRQ_Addr ; Address of IRQ Handler + LDR PC, FIQ_Addr ; Address of FIQ Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +Reset_Addr DCD Reset_Handler +Undef_Addr DCD Undef_Handler +SVC_Addr DCD SVC_Handler +PAbt_Addr DCD PAbt_Handler +DAbt_Addr DCD DAbt_Handler +IRQ_Addr DCD IRQ_Handler +FIQ_Addr DCD FIQ_Handler + + AREA |.text|, CODE, READONLY + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT InitMemorySubsystem + IMPORT __main + IMPORT RZ_A1_SetSramWriteEnable + + ; Put any cores other than 0 to sleep + MRC p15, 0, R0, c0, c0, 5 ; Read MPIDR + ANDS R0, R0, #3 +goToSleep + WFINE + BNE goToSleep + +; Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. +; Enables Full Access i.e. in both privileged and non privileged modes + MRC p15, 0, r0, c1, c0, 2 ; Read Coprocessor Access Control Register (CPACR) + ORR r0, r0, #(0xF << 20) ; Enable access to CP 10 & 11 + MCR p15, 0, r0, c1, c0, 2 ; Write Coprocessor Access Control Register (CPACR) + ISB + +; Switch on the VFP and NEON hardware + MOV r0, #0x40000000 + VMSR FPEXC, r0 ; Write FPEXC register, EN bit set + + MRC p15, 0, R0, c1, c0, 0 ; Read CP15 System Control register + BIC R0, R0, #(0x1 << 12) ; Clear I bit 12 to disable I Cache + BIC R0, R0, #(0x1 << 2) ; Clear C bit 2 to disable D Cache + BIC R0, R0, #0x1 ; Clear M bit 0 to disable MMU + BIC R0, R0, #(0x1 << 11) ; Clear Z bit 11 to disable branch prediction + BIC R0, R0, #(0x1 << 13) ; Clear V bit 13 to disable hivecs + MCR p15, 0, R0, c1, c0, 0 ; Write value back to CP15 System Control register + ISB + +; Set Vector Base Address Register (VBAR) to point to this application's vector table + LDR R0, =__Vectors + MCR p15, 0, R0, c12, c0, 0 + +; Setup Stack for each exceptional mode + LDR R0, =Stack_Top + +; Enter Undefined Instruction Mode and set its Stack Pointer + MSR CPSR_C, #Mode_UND:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #UND_Stack_Size + +; Enter Abort Mode and set its Stack Pointer + MSR CPSR_C, #Mode_ABT:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #ABT_Stack_Size + +; Enter FIQ Mode and set its Stack Pointer + MSR CPSR_C, #Mode_FIQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #FIQ_Stack_Size + +; Enter IRQ Mode and set its Stack Pointer + MSR CPSR_C, #Mode_IRQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #IRQ_Stack_Size + +; Enter Supervisor Mode and set its Stack Pointer + MSR CPSR_C, #Mode_SVC:OR:I_Bit:OR:F_Bit + MOV SP, R0 + +; Enter System Mode to complete initialization and enter kernel + MSR CPSR_C, #Mode_SYS:OR:I_Bit:OR:F_Bit + MOV SP, R0 + + ISB + + LDR R0, =RZ_A1_SetSramWriteEnable + BLX R0 + + IMPORT create_translation_table + BL create_translation_table + +; USR/SYS stack pointer will be set during kernel init + + LDR R0, =SystemInit + BLX R0 + LDR R0, =InitMemorySubsystem + BLX R0 + LDR R0, =__main + BLX R0 + + ENDP + +Undef_Handler\ + PROC + EXPORT Undef_Handler [WEAK] + IMPORT CUndefHandler + SRSFD SP!, #Mode_UND + PUSH {R0-R4, R12} ; Save APCS corruptible registers to UND mode stack + + MRS R0, SPSR + TST R0, #T_Bit ; Check mode + MOVEQ R1, #4 ; R1 = 4 ARM mode + MOVNE R1, #2 ; R1 = 2 Thumb mode + SUB R0, LR, R1 + LDREQ R0, [R0] ; ARM mode - R0 points to offending instruction + BEQ undef_cont + + ;Thumb instruction + ;Determine if it is a 32-bit Thumb instruction + LDRH R0, [R0] + MOV R2, #0x1c + CMP R2, R0, LSR #11 + BHS undef_cont ;16-bit Thumb instruction + + ;32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. + LDRH R2, [LR] + ORR R0, R2, R0, LSL #16 +undef_cont + MOV R2, LR ; Set LR to third argument + +; AND R12, SP, #4 ; Ensure stack is 8-byte aligned + MOV R3, SP ; Ensure stack is 8-byte aligned + AND R12, R3, #4 + SUB SP, SP, R12 ; Adjust stack + PUSH {R12, LR} ; Store stack adjustment and dummy LR + + ;R0 Offending instruction + ;R1 =2 (Thumb) or =4 (ARM) + BL CUndefHandler + + POP {R12, LR} ; Get stack adjustment & discard dummy LR + ADD SP, SP, R12 ; Unadjust stack + + LDR LR, [SP, #24] ; Restore stacked LR and possibly adjust for retry + SUB LR, LR, R0 + LDR R0, [SP, #28] ; Restore stacked SPSR + MSR SPSR_CXSF, R0 + POP {R0-R4, R12} ; Restore stacked APCS registers + ADD SP, SP, #8 ; Adjust SP for already-restored banked registers + MOVS PC, LR + ENDP + +PAbt_Handler\ + PROC + EXPORT PAbt_Handler [WEAK] + IMPORT CPAbtHandler + SUB LR, LR, #4 ; Pre-adjust LR + SRSFD SP!, #Mode_ABT ; Save LR and SPRS to ABT mode stack + PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack + MRC p15, 0, R0, c5, c0, 1 ; IFSR + MRC p15, 0, R1, c6, c0, 2 ; IFAR + + MOV R2, LR ; Set LR to third argument + +; AND R12, SP, #4 ; Ensure stack is 8-byte aligned + MOV R3, SP ; Ensure stack is 8-byte aligned + AND R12, R3, #4 + SUB SP, SP, R12 ; Adjust stack + PUSH {R12, LR} ; Store stack adjustment and dummy LR + + BL CPAbtHandler + + POP {R12, LR} ; Get stack adjustment & discard dummy LR + ADD SP, SP, R12 ; Unadjust stack + + POP {R0-R4, R12} ; Restore stack APCS registers + RFEFD SP! ; Return from exception + ENDP + + +DAbt_Handler\ + PROC + EXPORT DAbt_Handler [WEAK] + IMPORT CDAbtHandler + SUB LR, LR, #8 ; Pre-adjust LR + SRSFD SP!, #Mode_ABT ; Save LR and SPRS to ABT mode stack + PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack + CLREX ; State of exclusive monitors unknown after taken data abort + MRC p15, 0, R0, c5, c0, 0 ; DFSR + MRC p15, 0, R1, c6, c0, 0 ; DFAR + + MOV R2, LR ; Set LR to third argument + +; AND R12, SP, #4 ; Ensure stack is 8-byte aligned + MOV R3, SP ; Ensure stack is 8-byte aligned + AND R12, R3, #4 + SUB SP, SP, R12 ; Adjust stack + PUSH {R12, LR} ; Store stack adjustment and dummy LR + + BL CDAbtHandler + + POP {R12, LR} ; Get stack adjustment & discard dummy LR + ADD SP, SP, R12 ; Unadjust stack + + POP {R0-R4, R12} ; Restore stacked APCS registers + RFEFD SP! ; Return from exception + ENDP + +FIQ_Handler\ + PROC + EXPORT FIQ_Handler [WEAK] + ;; An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler, + ;; so if a real FIQ Handler is implemented, this will be needed before returning: + ;; LDR R1, =GICI_BASE + ;; LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 + B . + ENDP + +SVC_Handler\ + PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +IRQ_Handler\ + PROC + EXPORT IRQ_Handler [WEAK] + IMPORT IRQCount + IMPORT IRQTable + IMPORT IRQNestLevel + + ;prologue + SUB LR, LR, #4 ; Pre-adjust LR + SRSFD SP!, #Mode_SVC ; Save LR_IRQ and SPRS_IRQ to SVC mode stack + CPS #Mode_SVC ; Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL + PUSH {R0-R3, R12} ; Save remaining APCS corruptible registers to SVC stack + +; AND R1, SP, #4 ; Ensure stack is 8-byte aligned + MOV R3, SP ; Ensure stack is 8-byte aligned + AND R1, R3, #4 + SUB SP, SP, R1 ; Adjust stack + PUSH {R1, LR} ; Store stack adjustment and LR_SVC to SVC stack + + LDR R0, =IRQNestLevel ; Get address of nesting counter + LDR R1, [R0] + ADD R1, R1, #1 ; Increment nesting counter + STR R1, [R0] + + ;identify and acknowledge interrupt + LDR R1, =GICI_BASE + LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 + LDR R0, [R1, #ICCIAR_OFFSET] ; Read ICCIAR (GIC CPU Interface register) + DSB ; Ensure that interrupt acknowledge completes before re-enabling interrupts + + ; Workaround GIC 390 errata 733075 + ; If the ID is not 0, then service the interrupt as normal. + ; If the ID is 0 and active, then service interrupt ID 0 as normal. + ; If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it + ; with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced. + ; + LDR R2, =GICD_BASE + LDR R3, =GIC_ERRATA_CHECK_1 + CMP R0, R3 + BEQ unlock_cpu + LDR R3, =GIC_ERRATA_CHECK_2 + CMP R0, R3 + BEQ unlock_cpu + CMP R0, #0 + BNE int_active ; If the ID is not 0, then service the interrupt + LDR R3, [R2, #ICDABR0_OFFSET] ; Get the interrupt state + TST R3, #1 + BNE int_active ; If active, then service the interrupt +unlock_cpu + LDR R3, [R2, #ICDIPR0_OFFSET] ; Not active, so unlock the CPU interface + STR R3, [R2, #ICDIPR0_OFFSET] ; with a dummy write + DSB ; Ensure the write completes before continuing + B ret_irq ; Do not service the spurious interrupt + ; End workaround + +int_active + LDR R2, =IRQCount ; Read number of IRQs + LDR R2, [R2] + CMP R0, R2 ; Clean up and return if no handler + BHS ret_irq ; In a single-processor system, spurious interrupt ID 1023 does not need any special handling + LDR R2, =IRQTable ; Get address of handler + LDR R2, [R2, R0, LSL #2] + CMP R2, #0 ; Clean up and return if handler address is 0 + BEQ ret_irq + PUSH {R0,R1} + + CPSIE i ; Now safe to re-enable interrupts + BLX R2 ; Call handler. R0 will be IRQ number + CPSID i ; Disable interrupts again + + ;write EOIR (GIC CPU Interface register) + POP {R0,R1} + DSB ; Ensure that interrupt source is cleared before we write the EOIR +ret_irq + ;epilogue + STR R0, [R1, #ICCEOIR_OFFSET] + + LDR R0, =IRQNestLevel ; Get address of nesting counter + LDR R1, [R0] + SUB R1, R1, #1 ; Decrement nesting counter + STR R1, [R0] + + POP {R1, LR} ; Get stack adjustment and restore LR_SVC + ADD SP, SP, R1 ; Unadjust stack + + POP {R0-R3,R12} ; Restore stacked APCS registers + RFEFD SP! ; Return from exception + ENDP + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + USR_Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ENDIF + + + END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/TOOLCHAIN_GCC_ARM/VKRZA1H.ld Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,219 @@ +/* Linker script for mbed VK_RZ_A1H */ + +/* Linker script to configure memory regions. */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x02000000 + SFLASH_DUAL (rx) : ORIGIN = 0x18020000, LENGTH = 0x01FE0000 + L_TTB (rw) : ORIGIN = 0x20000000, LENGTH = 0x00004000 + RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 0x00700000 + RAM_NC (rwx) : ORIGIN = 0x20900000, LENGTH = 0x00100000 + SDRAM (rwx) : ORIGIN = 0x08000000, LENGTH = 0x02000000 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + + Image$$VECTORS$$Base = .; + *(.isr_vector) + Image$$VECTORS$$Limit = .; + *(SVC_TABLE) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + Image$$RO_DATA$$Base = .; + *(.rodata*) + Image$$RO_DATA$$Limit = .; + + KEEP(*(.eh_frame*)) + } > SFLASH_DUAL + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > SFLASH_DUAL + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > SFLASH_DUAL + __exidx_end = .; + + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__nc_data_start) + LONG (__nc_data_end - __nc_data_start) + __copy_table_end__ = .; + } > SFLASH_DUAL + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__nc_bss_start) + LONG (__nc_bss_end - __nc_bss_start) + __zero_table_end__ = .; + } > SFLASH_DUAL + + __etext = .; + + .ttb : + { + Image$$TTB$$ZI$$Base = .; + . += 0x00004000; + Image$$TTB$$ZI$$Limit = .; + } > L_TTB + + .data : AT (__etext) + { + Image$$RW_DATA$$Base = .; + __data_start__ = .; + *(vtable) + *(.data*) + Image$$RW_DATA$$Limit = .; + + . = ALIGN(4); + /* preinit data */ + PROVIDE (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + + .bss ALIGN(0x400): + { + Image$$ZI_DATA$$Base = .; + __bss_start__ = .; + *(.bss*) + *(COMMON) + __bss_end__ = .; + Image$$ZI_DATA$$Limit = .; + } > RAM + + + .heap : + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy : + { + *(.stack) + } > RAM + + __etext2 = __etext + SIZEOF(.data); + .nc_data : AT (__etext2) + { + Image$$RW_DATA_NC$$Base = .; + __nc_data_start = .; + *(NC_DATA) + + . = ALIGN(4); + __nc_data_end = .; + Image$$RW_DATA_NC$$Limit = .; + } > RAM_NC + + .nc_bss (NOLOAD) : + { + Image$$ZI_DATA_NC$$Base = .; + __nc_bss_start = .; + *(NC_BSS) + + . = ALIGN(4); + __nc_bss_end = .; + Image$$ZI_DATA_NC$$Limit = .; + } > RAM_NC + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,532 @@ +/* File: startup_ARMCM3.s + * Purpose: startup file for Cortex-M3/M4 devices. Should use with + * GNU Tools for ARM Embedded Processors + * Version: V1.1 + * Date: 17 June 2011 + * + * Copyright (C) 2011 ARM Limited. All rights reserved. + * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4 + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + */ + .syntax unified + .extern _start + +@ Standard definitions of mode bits and interrupt (I & F) flags in PSRs + .equ USR_MODE , 0x10 + .equ FIQ_MODE , 0x11 + .equ IRQ_MODE , 0x12 + .equ SVC_MODE , 0x13 + .equ ABT_MODE , 0x17 + .equ UND_MODE , 0x1b + .equ SYS_MODE , 0x1f + .equ Thum_bit , 0x20 @ CPSR/SPSR Thumb bit + + .equ GICI_BASE , 0xe8202000 + .equ ICCIAR_OFFSET , 0x0000000C + .equ ICCEOIR_OFFSET , 0x00000010 + .equ ICCHPIR_OFFSET , 0x00000018 + .equ GICD_BASE , 0xe8201000 + .equ ICDISER0_OFFSET , 0x00000100 + .equ ICDICER0_OFFSET , 0x00000180 + .equ ICDISPR0_OFFSET , 0x00000200 + .equ ICDABR0_OFFSET , 0x00000300 + .equ ICDIPR0_OFFSET , 0x00000400 + + .equ Mode_USR , 0x10 + .equ Mode_FIQ , 0x11 + .equ Mode_IRQ , 0x12 + .equ Mode_SVC , 0x13 + .equ Mode_ABT , 0x17 + .equ Mode_UND , 0x1B + .equ Mode_SYS , 0x1F + + .equ I_Bit , 0x80 @ when I bit is set, IRQ is disabled + .equ F_Bit , 0x40 @ when F bit is set, FIQ is disabled + .equ T_Bit , 0x20 @ when T bit is set, core is in Thumb state + + .equ GIC_ERRATA_CHECK_1, 0x000003FE + .equ GIC_ERRATA_CHECK_2, 0x000003FF + + .equ Sect_Normal , 0x00005c06 @ outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 + .equ Sect_Normal_Cod , 0x0000dc06 @ outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 + .equ Sect_Normal_RO , 0x0000dc16 @ as Sect_Normal_Cod, but not executable + .equ Sect_Normal_RW , 0x00005c16 @ as Sect_Normal_Cod, but writeable and not executable + .equ Sect_SO , 0x00000c12 @ strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 + .equ Sect_Device_RO , 0x00008c12 @ device, non-shareable, non-executable, ro, domain 0, base addr 0 + .equ Sect_Device_RW , 0x00000c12 @ as Sect_Device_RO, but writeable + .equ Sect_Fault , 0x00000000 @ this translation will fault (the bottom 2 bits are important, the rest are ignored) + + .equ RAM_BASE , 0x80000000 + .equ VRAM_BASE , 0x18000000 + .equ SRAM_BASE , 0x2e000000 + .equ ETHERNET , 0x1a000000 + .equ CS3_PERIPHERAL_BASE, 0x1c000000 + + +@ Stack Configuration + + .EQU UND_Stack_Size , 0x00000100 + .EQU SVC_Stack_Size , 0x00008000 + .EQU ABT_Stack_Size , 0x00000100 + .EQU FIQ_Stack_Size , 0x00000100 + .EQU IRQ_Stack_Size , 0x00008000 + .EQU USR_Stack_Size , 0x00004000 + + .EQU ISR_Stack_Size, (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size) + + .section .stack + .align 3 + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space ISR_Stack_Size +__initial_sp: + .space USR_Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + +@ Heap Configuration + + .EQU Heap_Size , 0x00080000 + + .section .heap + .align 3 + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .space Heap_Size + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long 0xe59ff018 /* 0x00 */ + .long 0xe59ff018 /* 0x04 */ + .long 0xe59ff018 /* 0x08 */ + .long 0xe59ff018 /* 0x0c */ + .long 0xe59ff018 /* 0x10 */ + .long 0xe59ff018 /* 0x14 */ + .long 0xe59ff018 /* 0x18 */ + .long 0xe59ff018 /* 0x1c */ + + .long Reset_Handler /* 0x20 */ + .long Undef_Handler /* 0x24 */ + .long SVC_Handler /* 0x28 */ + .long PAbt_Handler /* 0x2c */ + .long DAbt_Handler /* 0x30 */ + .long 0 /* Reserved */ + .long IRQ_Handler /* IRQ */ + .long FIQ_Handler /* FIQ */ + + + .size __isr_vector, . - __isr_vector + + .text + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + @ Put any cores other than 0 to sleep + mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR + ands r0, r0, #3 + +goToSleep: + wfine + bne goToSleep + +@ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. +@ Enables Full Access i.e. in both privileged and non privileged modes + mrc p15, 0, r0, c1, c0, 2 @ Read Coprocessor Access Control Register (CPACR) + orr r0, r0, #(0xF << 20) @ Enable access to CP 10 & 11 + mcr p15, 0, r0, c1, c0, 2 @ Write Coprocessor Access Control Register (CPACR) + isb + +@ Switch on the VFP and NEON hardware + mov r0, #0x40000000 + vmsr fpexc, r0 @ Write FPEXC register, EN bit set + + mrc p15, 0, r0, c1, c0, 0 @ Read CP15 System Control register + bic r0, r0, #(0x1 << 12) @ Clear I bit 12 to disable I Cache + bic r0, r0, #(0x1 << 2) @ Clear C bit 2 to disable D Cache + bic r0, r0, #0x1 @ Clear M bit 0 to disable MMU + bic r0, r0, #(0x1 << 11) @ Clear Z bit 11 to disable branch prediction + bic r0, r0, #(0x1 << 13) @ Clear V bit 13 to disable hivecs + mcr p15, 0, r0, c1, c0, 0 @ Write value back to CP15 System Control register + isb + +@ Set Vector Base Address Register (VBAR) to point to this application's vector table + ldr r0, =__isr_vector + mcr p15, 0, r0, c12, c0, 0 + +@ Setup Stack for each exceptional mode +/* ldr r0, =__StackTop */ + ldr r0, =(__StackTop - USR_Stack_Size) + +@ Enter Undefined Instruction Mode and set its Stack Pointer + msr cpsr_c, #(Mode_UND | I_Bit | F_Bit) + mov sp, r0 + sub r0, r0, #UND_Stack_Size + +@ Enter Abort Mode and set its Stack Pointer + msr cpsr_c, #(Mode_ABT | I_Bit | F_Bit) + mov sp, r0 + sub r0, r0, #ABT_Stack_Size + +@ Enter FIQ Mode and set its Stack Pointer + msr cpsr_c, #(Mode_FIQ | I_Bit | F_Bit) + mov sp, r0 + sub r0, r0, #FIQ_Stack_Size + +@ Enter IRQ Mode and set its Stack Pointer + msr cpsr_c, #(Mode_IRQ | I_Bit | F_Bit) + mov sp, r0 + sub r0, r0, #IRQ_Stack_Size + +@ Enter Supervisor Mode and set its Stack Pointer + msr cpsr_c, #(Mode_SVC | I_Bit | F_Bit) + mov sp, r0 + +@ Enter System Mode to complete initialization and enter kernel + msr cpsr_c, #(Mode_SYS | I_Bit | F_Bit) + mov sp, r0 + + isb + ldr r0, =RZ_A1_SetSramWriteEnable + blx r0 + + .extern create_translation_table + bl create_translation_table + +@ USR/SYS stack pointer will be set during kernel init + ldr r0, =SystemInit + blx r0 + ldr r0, =InitMemorySubsystem + blx r0 + +@ fp_init + mov r0, #0x3000000 + vmsr fpscr, r0 + + +@ data sections copy + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: + +@ bss sections clear + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: + + + ldr r0, =_start + bx r0 + + ldr r0, sf_boot @ dummy to keep boot loader area +loop_here: + b loop_here + +sf_boot: + .word 0x18020000 + + .pool + .size Reset_Handler, . - Reset_Handler + + + .text + +Undef_Handler: + .global Undef_Handler + .func Undef_Handler + .extern CUndefHandler + SRSDB SP!, #Mode_UND + PUSH {R0-R4, R12} /* Save APCS corruptible registers to UND mode stack */ + + MRS R0, SPSR + TST R0, #T_Bit /* Check mode */ + MOVEQ R1, #4 /* R1 = 4 ARM mode */ + MOVNE R1, #2 /* R1 = 2 Thumb mode */ + SUB R0, LR, R1 + LDREQ R0, [R0] /* ARM mode - R0 points to offending instruction */ + BEQ undef_cont + + /* Thumb instruction */ + /* Determine if it is a 32-bit Thumb instruction */ + LDRH R0, [R0] + MOV R2, #0x1c + CMP R2, R0, LSR #11 + BHS undef_cont /* 16-bit Thumb instruction */ + + /* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */ + LDRH R2, [LR] + ORR R0, R2, R0, LSL #16 +undef_cont: + MOV R2, LR /* Set LR to third argument */ + +/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ + MOV R3, SP /* Ensure stack is 8-byte aligned */ + AND R12, R3, #4 + SUB SP, SP, R12 /* Adjust stack */ + PUSH {R12, LR} /* Store stack adjustment and dummy LR */ + + /* R0 Offending instruction */ + /* R1 =2 (Thumb) or =4 (ARM) */ + BL CUndefHandler + + POP {R12, LR} /* Get stack adjustment & discard dummy LR */ + ADD SP, SP, R12 /* Unadjust stack */ + + LDR LR, [SP, #24] /* Restore stacked LR and possibly adjust for retry */ + SUB LR, LR, R0 + LDR R0, [SP, #28] /* Restore stacked SPSR */ + MSR SPSR_cxsf, R0 + POP {R0-R4, R12} /* Restore stacked APCS registers */ + ADD SP, SP, #8 /* Adjust SP for already-restored banked registers */ + MOVS PC, LR + .endfunc + +PAbt_Handler: + .global PAbt_Handler + .func PAbt_Handler + .extern CPAbtHandler + SUB LR, LR, #4 /* Pre-adjust LR */ + SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */ + PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */ + MRC p15, 0, R0, c5, c0, 1 /* IFSR */ + MRC p15, 0, R1, c6, c0, 2 /* IFAR */ + + MOV R2, LR /* Set LR to third argument */ + +/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ + MOV R3, SP /* Ensure stack is 8-byte aligned */ + AND R12, R3, #4 + SUB SP, SP, R12 /* Adjust stack */ + PUSH {R12, LR} /* Store stack adjustment and dummy LR */ + + BL CPAbtHandler + + POP {R12, LR} /* Get stack adjustment & discard dummy LR */ + ADD SP, SP, R12 /* Unadjust stack */ + + POP {R0-R4, R12} /* Restore stack APCS registers */ + RFEFD SP! /* Return from exception */ + .endfunc + +DAbt_Handler: + .global DAbt_Handler + .func DAbt_Handler + .extern CDAbtHandler + SUB LR, LR, #8 /* Pre-adjust LR */ + SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */ + PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */ + CLREX /* State of exclusive monitors unknown after taken data abort */ + MRC p15, 0, R0, c5, c0, 0 /* DFSR */ + MRC p15, 0, R1, c6, c0, 0 /* DFAR */ + + MOV R2, LR /* Set LR to third argument */ + +/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ + MOV R3, SP /* Ensure stack is 8-byte aligned */ + AND R12, R3, #4 + SUB SP, SP, R12 /* Adjust stack */ + PUSH {R12, LR} /* Store stack adjustment and dummy LR */ + + BL CDAbtHandler + + POP {R12, LR} /* Get stack adjustment & discard dummy LR */ + ADD SP, SP, R12 /* Unadjust stack */ + + POP {R0-R4, R12} /* Restore stacked APCS registers */ + RFEFD SP! /* Return from exception */ + .endfunc + +FIQ_Handler: + .global FIQ_Handler + .func FIQ_Handler + /* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler, + * so if a real FIQ Handler is implemented, this will be needed before returning: + */ + /* LDR R1, =GICI_BASE + LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 + */ + B . + .endfunc + + .extern SVC_Handler /* refer RTX function */ + +IRQ_Handler: + .global IRQ_Handler + .func IRQ_Handler + .extern IRQCount + .extern IRQTable + .extern IRQNestLevel + + /* prologue */ + SUB LR, LR, #4 /* Pre-adjust LR */ + SRSDB SP!, #Mode_SVC /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */ + CPS #Mode_SVC /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */ + PUSH {R0-R3, R12} /* Save remaining APCS corruptible registers to SVC stack */ + +/* AND R1, SP, #4 */ /* Ensure stack is 8-byte aligned */ + MOV R3, SP /* Ensure stack is 8-byte aligned */ + AND R1, R3, #4 + SUB SP, SP, R1 /* Adjust stack */ + PUSH {R1, LR} /* Store stack adjustment and LR_SVC to SVC stack */ + + LDR R0, =IRQNestLevel /* Get address of nesting counter */ + LDR R1, [R0] + ADD R1, R1, #1 /* Increment nesting counter */ + STR R1, [R0] + + /* identify and acknowledge interrupt */ + LDR R1, =GICI_BASE + LDR R0, [R1, #ICCHPIR_OFFSET] /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */ + LDR R0, [R1, #ICCIAR_OFFSET] /* Read ICCIAR (GIC CPU Interface register) */ + DSB /* Ensure that interrupt acknowledge completes before re-enabling interrupts */ + + /* Workaround GIC 390 errata 733075 + * If the ID is not 0, then service the interrupt as normal. + * If the ID is 0 and active, then service interrupt ID 0 as normal. + * If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it + * with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced. + */ + LDR R2, =GICD_BASE + LDR R3, =GIC_ERRATA_CHECK_1 + CMP R0, R3 + BEQ unlock_cpu + LDR R3, =GIC_ERRATA_CHECK_2 + CMP R0, R3 + BEQ unlock_cpu + CMP R0, #0 + BNE int_active /* If the ID is not 0, then service the interrupt */ + LDR R3, [R2, #ICDABR0_OFFSET] /* Get the interrupt state */ + TST R3, #1 + BNE int_active /* If active, then service the interrupt */ +unlock_cpu: + LDR R3, [R2, #ICDIPR0_OFFSET] /* Not active, so unlock the CPU interface */ + STR R3, [R2, #ICDIPR0_OFFSET] /* with a dummy write */ + DSB /* Ensure the write completes before continuing */ + B ret_irq /* Do not service the spurious interrupt */ + /* End workaround */ + +int_active: + LDR R2, =IRQCount /* Read number of IRQs */ + LDR R2, [R2] + CMP R0, R2 /* Clean up and return if no handler */ + BHS ret_irq /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */ + LDR R2, =IRQTable /* Get address of handler */ + LDR R2, [R2, R0, LSL #2] + CMP R2, #0 /* Clean up and return if handler address is 0 */ + BEQ ret_irq + PUSH {R0,R1} + + CPSIE i /* Now safe to re-enable interrupts */ + BLX R2 /* Call handler. R0 will be IRQ number */ + CPSID i /* Disable interrupts again */ + + /* write EOIR (GIC CPU Interface register) */ + POP {R0,R1} + DSB /* Ensure that interrupt source is cleared before we write the EOIR */ +ret_irq: + /* epilogue */ + STR R0, [R1, #ICCEOIR_OFFSET] + + LDR R0, =IRQNestLevel /* Get address of nesting counter */ + LDR R1, [R0] + SUB R1, R1, #1 /* Decrement nesting counter */ + STR R1, [R0] + + POP {R1, LR} /* Get stack adjustment and restore LR_SVC */ + ADD SP, SP, R1 /* Unadjust stack */ + + POP {R0-R3,R12} /* Restore stacked APCS registers */ + RFEFD SP! /* Return from exception */ + .endfunc + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler SVC_Handler + + +/* User Initial Stack & Heap */ + + .ifdef __MICROLIB + + .global __initial_sp + .global __heap_base + .global __heap_limit + + .else + + .extern __use_two_region_memory + .global __user_initial_stackheap +__user_initial_stackheap: + + LDR R0, = __HeapBase + LDR R1, =(__StackTop) + LDR R2, = (__HeapBase + Heap_Size) + LDR R3, = (__StackTop - USR_Stack_Size) + BX LR + + .endif + + + .END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/TOOLCHAIN_IAR/VKRZA1H.icf Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,65 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x18020000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x18020000; +define symbol __ICFEDIT_region_ROM_end__ = 0x19FFFFFF; +define symbol __ICFEDIT_region_TTB_start__ = 0x20000000; +define symbol __ICFEDIT_region_TTB_end__ = 0x2001FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20020000; +define symbol __ICFEDIT_region_RAM_end__ = 0x209FFFFF; +define symbol __ICFEDIT_region_SDRAM_start__ = 0x08000000; +define symbol __ICFEDIT_region_SDRAM_end__ = 0x09FFFFFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x00004000; +define symbol __ICFEDIT_size_svcstack__ = 0x00008000; +define symbol __ICFEDIT_size_irqstack__ = 0x00008000; +define symbol __ICFEDIT_size_fiqstack__ = 0x00000100; +define symbol __ICFEDIT_size_undstack__ = 0x00000100; +define symbol __ICFEDIT_size_abtstack__ = 0x00000100; +define symbol __ICFEDIT_size_heap__ = 0x00080000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __ICFEDIT_region_RetRAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RetRAM_end__ = 0x2001FFFF; + +define symbol __ICFEDIT_region_MirrorRAM_start__ = 0x60900000; +define symbol __ICFEDIT_region_MirrorRAM_end__ = 0x609FFFFF; + +define symbol __ICFEDIT_region_MirrorRetRAM_start__ = 0x60000000; +define symbol __ICFEDIT_region_MirrorRetRAM_end__ = 0x6001FFFF; + +define memory mem with size = 4G; + +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region SDRAM_region = mem:[from __ICFEDIT_region_SDRAM_start__ to __ICFEDIT_region_SDRAM_end__]; +define region RetRAM_region = mem:[from __ICFEDIT_region_RetRAM_start__ to __ICFEDIT_region_RetRAM_end__]; +define region MirrorRAM_region = mem:[from __ICFEDIT_region_MirrorRAM_start__ to __ICFEDIT_region_MirrorRAM_end__]; +define region MirrorRetRAM_region = mem:[from __ICFEDIT_region_MirrorRetRAM_start__ to __ICFEDIT_region_MirrorRetRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +do not initialize { section MMU_TT }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP }; + +place in RetRAM_region { section .retram }; +place in MirrorRAM_region { section .mirrorram }; +place in MirrorRetRAM_region { section .mirrorretram };
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/TOOLCHAIN_IAR/startup_VKRZA1H.s Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,505 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Part one of the system initialization code, +;; contains low-level +;; initialization. +;; +;; Copyright 2007 IAR Systems. All rights reserved. +;; +;; $Revision: 49919 $ +;; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION SVC_STACK:DATA:NOROOT(3) + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION ABT_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION UND_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + +; +; The module in this file are included in the libraries, and may be +; replaced by any user-defined modules that define the PUBLIC symbol +; __iar_program_start or a user defined start symbol. +; +; To override the cstartup defined in the library, simply add your +; modified version to the workbench project. + + SECTION .intvec:CODE:NOROOT(2) + + PUBLIC __vector + PUBLIC __iar_program_start + PUBLIC Undefined_Handler + EXTERN SWI_Handler + PUBLIC Prefetch_Handler + PUBLIC Abort_Handler + PUBLIC IRQ_Handler + PUBLIC FIQ_Handler + EXTERN VbarInit + EXTERN SetLowVectors + EXTERN init_TTB + EXTERN enable_mmu + EXTERN Peripheral_BasicInit + EXTERN initsct + EXTERN PowerON_Reset + PUBLIC FPUEnable + + + DATA + +__iar_init$$done: ; The vector table is not needed + ; until after copy initialization is done + +__vector: ; Make this a DATA label, so that stack usage + ; analysis doesn't consider it an uncalled fun + + ARM + + ; All default exception handlers (except reset) are + ; defined as weak symbol definitions. + ; If a handler is defined by the application it will take precedence. + LDR PC,Reset_Addr ; Reset + LDR PC,Undefined_Addr ; Undefined instructions + LDR PC,SWI_Addr ; Software interrupt (SWI/SVC) + LDR PC,Prefetch_Addr ; Prefetch abort + LDR PC,Abort_Addr ; Data abort + DCD 0 ; RESERVED + LDR PC,IRQ_Addr ; IRQ + LDR PC,FIQ_Addr ; FIQ + + DATA + +Reset_Addr: DCD __iar_program_start +Undefined_Addr: DCD Undefined_Handler +SWI_Addr: DCD SWI_Handler +Prefetch_Addr: DCD Prefetch_Handler +Abort_Addr: DCD Abort_Handler +IRQ_Addr: DCD IRQ_Handler +FIQ_Addr: DCD FIQ_Handler + + +; -------------------------------------------------- +; ?cstartup -- low-level system initialization code. +; +; After a reset execution starts here, the mode is ARM, supervisor +; with interrupts disabled. +; + + + + SECTION .text:CODE:NOROOT(2) + EXTERN RZ_A1_SetSramWriteEnable + EXTERN create_translation_table + EXTERN SystemInit + EXTERN InitMemorySubsystem + EXTERN __cmain + REQUIRE __vector + EXTWEAK __iar_init_core + EXTWEAK __iar_init_vfp + + + ARM + +__iar_program_start: +?cstartup: + + +;;; @ Put any cores other than 0 to sleep + mrc p15, 0, r0, c0, c0, 5 ;;; @ Read MPIDR + ands r0, r0, #3 + +goToSleep: + wfine + bne goToSleep + + +//@ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. +//@ Enables Full Access i.e. in both privileged and non privileged modes + mrc p15, 0, r0, c1, c0, 2 ;@ Read Coprocessor Access Control Register (CPACR) + orr r0, r0, #(0xF << 20) ;@ Enable access to CP 10 & 11 + mcr p15, 0, r0, c1, c0, 2 ;@ Write Coprocessor Access Control Register (CPACR) + isb + + +;; Switch on the VFP and NEON hardware + mov r0, #0x40000000 + vmsr fpexc, r0 ;@ Write FPEXC register, EN bit set + + mrc p15, 0, r0, c1, c0, 0 ;@ Read CP15 System Control register + bic r0, r0, #(0x1 << 12) ;@ Clear I bit 12 to disable I Cache + bic r0, r0, #(0x1 << 2) ;@ Clear C bit 2 to disable D Cache + bic r0, r0, #0x1 ;@ Clear M bit 0 to disable MMU + bic r0, r0, #(0x1 << 11) ;@ Clear Z bit 11 to disable branch prediction + bic r0, r0, #(0x1 << 13) ;@ Clear V bit 13 to disable hivecs + mcr p15, 0, r0, c1, c0, 0 ;@ Write value back to CP15 System Control register + isb + + +;; Set Vector Base Address Register (VBAR) to point to this application's vector table + ldr r0, =__vector + mcr p15, 0, r0, c12, c0, 0 + + +; +; Add initialization needed before setup of stackpointers here. +; + +; +; Initialize the stack pointers. +; The pattern below can be used for any of the exception stacks: +; FIQ, IRQ, SVC, ABT, UND, SYS. +; The USR mode uses the same stack as SYS. +; The stack segments must be defined in the linker command file, +; and be declared above. +; + + +; -------------------- +; Mode, correspords to bits 0-5 in CPSR + +#define MODE_MSK 0x1F ; Bit mask for mode bits in CPSR + +#define USR_MODE 0x10 ; User mode +#define FIQ_MODE 0x11 ; Fast Interrupt Request mode +#define IRQ_MODE 0x12 ; Interrupt Request mode +#define SVC_MODE 0x13 ; Supervisor mode +#define ABT_MODE 0x17 ; Abort mode +#define UND_MODE 0x1B ; Undefined Instruction mode +#define SYS_MODE 0x1F ; System mode + +#define Mode_SVC 0x13 +#define Mode_ABT 0x17 +#define Mode_UND 0x1B +#define GICI_BASE 0xe8202000 +#define ICCIAR_OFFSET 0x0000000C +#define ICCEOIR_OFFSET 0x00000010 +#define ICCHPIR_OFFSET 0x00000018 +#define GICD_BASE 0xe8201000 +#define GIC_ERRATA_CHECK_1 0x000003FE +#define GIC_ERRATA_CHECK_2 0x000003FF +#define ICDABR0_OFFSET 0x00000300 +#define ICDIPR0_OFFSET 0x00000400 +#define T_Bit 0x20 ; when T bit is set, core is in Thumb state + + MRS r0, cpsr ; Original PSR value + + ;; Set up the SVC stack pointer. + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #SVC_MODE ; Set SVC mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(SVC_STACK) ; End of SVC_STACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + ;; Set up the interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + ;; Set up the fast interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #FIQ_MODE ; Set FIR mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + + ;; Set up the ABT stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #ABT_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(ABT_STACK) ; End of CSTACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + + ;; Set up the UDF stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #UND_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(UND_STACK) ; End of CSTACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + ;; Set up the normal stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #SYS_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(CSTACK) ; End of CSTACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + +;;; + + isb + ldr r0, =RZ_A1_SetSramWriteEnable + blx r0 + + bl create_translation_table + +; USR/SYS stack pointer will be set during kernel init + ldr r0, =SystemInit + blx r0 + ldr r0, =InitMemorySubsystem + blx r0 + +; fp_init + mov r0, #0x3000000 + vmsr fpscr, r0 + + + +;;; Continue to __cmain for C-level initialization. + + FUNCALL __iar_program_start, __cmain + B __cmain + + + ldr r0, sf_boot ;@ dummy to keep boot loader area +loop_here: + b loop_here + +sf_boot: + DC32 0x00000001 + +Undefined_Handler: + EXTERN CUndefHandler + SRSDB SP!, #Mode_UND + PUSH {R0-R4, R12} /* Save APCS corruptible registers to UND mode stack */ + + MRS R0, SPSR + TST R0, #T_Bit /* Check mode */ + MOVEQ R1, #4 /* R1 = 4 ARM mode */ + MOVNE R1, #2 /* R1 = 2 Thumb mode */ + SUB R0, LR, R1 + LDREQ R0, [R0] /* ARM mode - R0 points to offending instruction */ + BEQ undef_cont + + /* Thumb instruction */ + /* Determine if it is a 32-bit Thumb instruction */ + LDRH R0, [R0] + MOV R2, #0x1c + CMP R2, R0, LSR #11 + BHS undef_cont /* 16-bit Thumb instruction */ + + /* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */ + LDRH R2, [LR] + ORR R0, R2, R0, LSL #16 +undef_cont: + MOV R2, LR /* Set LR to third argument */ + +/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ + MOV R3, SP /* Ensure stack is 8-byte aligned */ + AND R12, R3, #4 + SUB SP, SP, R12 /* Adjust stack */ + PUSH {R12, LR} /* Store stack adjustment and dummy LR */ + + /* R0 Offending instruction */ + /* R1 =2 (Thumb) or =4 (ARM) */ + BL CUndefHandler + + POP {R12, LR} /* Get stack adjustment & discard dummy LR */ + ADD SP, SP, R12 /* Unadjust stack */ + + LDR LR, [SP, #24] /* Restore stacked LR and possibly adjust for retry */ + SUB LR, LR, R0 + LDR R0, [SP, #28] /* Restore stacked SPSR */ + MSR SPSR_cxsf, R0 + POP {R0-R4, R12} /* Restore stacked APCS registers */ + ADD SP, SP, #8 /* Adjust SP for already-restored banked registers */ + MOVS PC, LR + +Prefetch_Handler: + EXTERN CPAbtHandler + SUB LR, LR, #4 /* Pre-adjust LR */ + SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */ + PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */ + MRC p15, 0, R0, c5, c0, 1 /* IFSR */ + MRC p15, 0, R1, c6, c0, 2 /* IFAR */ + + MOV R2, LR /* Set LR to third argument */ + +/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ + MOV R3, SP /* Ensure stack is 8-byte aligned */ + AND R12, R3, #4 + SUB SP, SP, R12 /* Adjust stack */ + PUSH {R12, LR} /* Store stack adjustment and dummy LR */ + + BL CPAbtHandler + + POP {R12, LR} /* Get stack adjustment & discard dummy LR */ + ADD SP, SP, R12 /* Unadjust stack */ + + POP {R0-R4, R12} /* Restore stack APCS registers */ + RFEFD SP! /* Return from exception */ + +Abort_Handler: + EXTERN CDAbtHandler + SUB LR, LR, #8 /* Pre-adjust LR */ + SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */ + PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */ + CLREX /* State of exclusive monitors unknown after taken data abort */ + MRC p15, 0, R0, c5, c0, 0 /* DFSR */ + MRC p15, 0, R1, c6, c0, 0 /* DFAR */ + + MOV R2, LR /* Set LR to third argument */ + +/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ + MOV R3, SP /* Ensure stack is 8-byte aligned */ + AND R12, R3, #4 + SUB SP, SP, R12 /* Adjust stack */ + PUSH {R12, LR} /* Store stack adjustment and dummy LR */ + + BL CDAbtHandler + + POP {R12, LR} /* Get stack adjustment & discard dummy LR */ + ADD SP, SP, R12 /* Unadjust stack */ + + POP {R0-R4, R12} /* Restore stacked APCS registers */ + RFEFD SP! /* Return from exception */ + +FIQ_Handler: + /* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler, + * so if a real FIQ Handler is implemented, this will be needed before returning: + */ + /* LDR R1, =GICI_BASE + LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 + */ + B . + + EXTERN SVC_Handler /* refer RTX function */ + +IRQ_Handler: + EXTERN IRQCount + EXTERN IRQTable + EXTERN IRQNestLevel + + /* prologue */ + SUB LR, LR, #4 /* Pre-adjust LR */ + SRSDB SP!, #Mode_SVC /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */ + CPS #Mode_SVC /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */ + PUSH {R0-R3, R12} /* Save remaining APCS corruptible registers to SVC stack */ + +/* AND R1, SP, #4 */ /* Ensure stack is 8-byte aligned */ + MOV R3, SP /* Ensure stack is 8-byte aligned */ + AND R1, R3, #4 + SUB SP, SP, R1 /* Adjust stack */ + PUSH {R1, LR} /* Store stack adjustment and LR_SVC to SVC stack */ + + LDR R0, =IRQNestLevel /* Get address of nesting counter */ + LDR R1, [R0] + ADD R1, R1, #1 /* Increment nesting counter */ + STR R1, [R0] + + /* identify and acknowledge interrupt */ + LDR R1, =GICI_BASE + LDR R0, [R1, #ICCHPIR_OFFSET] /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */ + LDR R0, [R1, #ICCIAR_OFFSET] /* Read ICCIAR (GIC CPU Interface register) */ + DSB /* Ensure that interrupt acknowledge completes before re-enabling interrupts */ + + /* Workaround GIC 390 errata 733075 + * If the ID is not 0, then service the interrupt as normal. + * If the ID is 0 and active, then service interrupt ID 0 as normal. + * If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it + * with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced. + */ + LDR R2, =GICD_BASE + LDR R3, =GIC_ERRATA_CHECK_1 + CMP R0, R3 + BEQ unlock_cpu + LDR R3, =GIC_ERRATA_CHECK_2 + CMP R0, R3 + BEQ unlock_cpu + CMP R0, #0 + BNE int_active /* If the ID is not 0, then service the interrupt */ + LDR R3, [R2, #ICDABR0_OFFSET] /* Get the interrupt state */ + TST R3, #1 + BNE int_active /* If active, then service the interrupt */ +unlock_cpu: + LDR R3, [R2, #ICDIPR0_OFFSET] /* Not active, so unlock the CPU interface */ + STR R3, [R2, #ICDIPR0_OFFSET] /* with a dummy write */ + DSB /* Ensure the write completes before continuing */ + B ret_irq /* Do not service the spurious interrupt */ + /* End workaround */ + +int_active: + LDR R2, =IRQCount /* Read number of IRQs */ + LDR R2, [R2] + CMP R0, R2 /* Clean up and return if no handler */ + BHS ret_irq /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */ + LDR R2, =IRQTable /* Get address of handler */ + LDR R2, [R2, R0, LSL #2] + CMP R2, #0 /* Clean up and return if handler address is 0 */ + BEQ ret_irq + PUSH {R0,R1} + + CPSIE i /* Now safe to re-enable interrupts */ + BLX R2 /* Call handler. R0 will be IRQ number */ + CPSID i /* Disable interrupts again */ + + /* write EOIR (GIC CPU Interface register) */ + POP {R0,R1} + DSB /* Ensure that interrupt source is cleared before we write the EOIR */ +ret_irq: + /* epilogue */ + STR R0, [R1, #ICCEOIR_OFFSET] + + LDR R0, =IRQNestLevel /* Get address of nesting counter */ + LDR R1, [R0] + SUB R1, R1, #1 /* Decrement nesting counter */ + STR R1, [R0] + + POP {R1, LR} /* Get stack adjustment and restore LR_SVC */ + ADD SP, SP, R1 /* Unadjust stack */ + + POP {R0-R3,R12} /* Restore stacked APCS registers */ + RFEFD SP! /* Return from exception */ +;;; +;;; Add more initialization here +;;; +FPUEnable: + ARM + + //Permit access to VFP registers by modifying CPACR + MRC p15,0,R1,c1,c0,2 + ORR R1,R1,#0x00F00000 + MCR p15,0,R1,c1,c0,2 + + //Enable VFP + VMRS R1,FPEXC + ORR R1,R1,#0x40000000 + VMSR FPEXC,R1 + + //Initialise VFP registers to 0 + MOV R2,#0 + VMOV D0, R2,R2 + VMOV D1, R2,R2 + VMOV D2, R2,R2 + VMOV D3, R2,R2 + VMOV D4, R2,R2 + VMOV D5, R2,R2 + VMOV D6, R2,R2 + VMOV D7, R2,R2 + VMOV D8, R2,R2 + VMOV D9, R2,R2 + VMOV D10,R2,R2 + VMOV D11,R2,R2 + VMOV D12,R2,R2 + VMOV D13,R2,R2 + VMOV D14,R2,R2 + VMOV D15,R2,R2 + + //Initialise FPSCR to a known state + VMRS R2,FPSCR + LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + AND R2,R2,R3 + VMSR FPSCR,R2 + + BX LR + + END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/VKRZA1H.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,1075 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/**************************************************************************//** + * @file VKRZA1H.h + * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File for + * Renesas RZA1H Device Series + * @version + * @date 19 Sept 2013 + * + * @note + * + ******************************************************************************/ + +#ifndef __VKRZA1H_H__ +#define __VKRZA1H_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum IRQn +{ +/****** SGI Interrupts Numbers ****************************************/ + SGI0_IRQn = 0, + SGI1_IRQn = 1, + SGI2_IRQn = 2, + SGI3_IRQn = 3, + SGI4_IRQn = 4, + SGI5_IRQn = 5, + SGI6_IRQn = 6, + SGI7_IRQn = 7, + SGI8_IRQn = 8, + SGI9_IRQn = 9, + SGI10_IRQn = 10, + SGI11_IRQn = 11, + SGI12_IRQn = 12, + SGI13_IRQn = 13, + SGI14_IRQn = 14, + SGI15_IRQn = 15, + +/****** Cortex-A9 Processor Exceptions Numbers ****************************************/ + /* 16 - 578 */ + PMUIRQ0_IRQn = 16, + COMMRX0_IRQn = 17, + COMMTX0_IRQn = 18, + CTIIRQ0_IRQn = 19, + + IRQ0_IRQn = 32, + IRQ1_IRQn = 33, + IRQ2_IRQn = 34, + IRQ3_IRQn = 35, + IRQ4_IRQn = 36, + IRQ5_IRQn = 37, + IRQ6_IRQn = 38, + IRQ7_IRQn = 39, + + PL310ERR_IRQn = 40, + + DMAINT0_IRQn = 41, /*!< DMAC Interrupt */ + DMAINT1_IRQn = 42, /*!< DMAC Interrupt */ + DMAINT2_IRQn = 43, /*!< DMAC Interrupt */ + DMAINT3_IRQn = 44, /*!< DMAC Interrupt */ + DMAINT4_IRQn = 45, /*!< DMAC Interrupt */ + DMAINT5_IRQn = 46, /*!< DMAC Interrupt */ + DMAINT6_IRQn = 47, /*!< DMAC Interrupt */ + DMAINT7_IRQn = 48, /*!< DMAC Interrupt */ + DMAINT8_IRQn = 49, /*!< DMAC Interrupt */ + DMAINT9_IRQn = 50, /*!< DMAC Interrupt */ + DMAINT10_IRQn = 51, /*!< DMAC Interrupt */ + DMAINT11_IRQn = 52, /*!< DMAC Interrupt */ + DMAINT12_IRQn = 53, /*!< DMAC Interrupt */ + DMAINT13_IRQn = 54, /*!< DMAC Interrupt */ + DMAINT14_IRQn = 55, /*!< DMAC Interrupt */ + DMAINT15_IRQn = 56, /*!< DMAC Interrupt */ + DMAERR_IRQn = 57, /*!< DMAC Interrupt */ + + /* 58-72 Reserved */ + + USBI0_IRQn = 73, + USBI1_IRQn = 74, + + S0_VI_VSYNC0_IRQn = 75, + S0_LO_VSYNC0_IRQn = 76, + S0_VSYNCERR0_IRQn = 77, + GR3_VLINE0_IRQn = 78, + S0_VFIELD0_IRQn = 79, + IV1_VBUFERR0_IRQn = 80, + IV3_VBUFERR0_IRQn = 81, + IV5_VBUFERR0_IRQn = 82, + IV6_VBUFERR0_IRQn = 83, + S0_WLINE0_IRQn = 84, + S1_VI_VSYNC0_IRQn = 85, + S1_LO_VSYNC0_IRQn = 86, + S1_VSYNCERR0_IRQn = 87, + S1_VFIELD0_IRQn = 88, + IV2_VBUFERR0_IRQn = 89, + IV4_VBUFERR0_IRQn = 90, + S1_WLINE0_IRQn = 91, + OIR_VI_VSYNC0_IRQn = 92, + OIR_LO_VSYNC0_IRQn = 93, + OIR_VSYNCERR0_IRQn = 94, + OIR_VFIELD0_IRQn = 95, + IV7_VBUFERR0_IRQn = 96, + IV8_VBUFERR0_IRQn = 97, + /* 98 Reserved */ + S0_VI_VSYNC1_IRQn = 99, + S0_LO_VSYNC1_IRQn = 100, + S0_VSYNCERR1_IRQn = 101, + GR3_VLINE1_IRQn = 102, + S0_VFIELD1_IRQn = 103, + IV1_VBUFERR1_IRQn = 104, + IV3_VBUFERR1_IRQn = 105, + IV5_VBUFERR1_IRQn = 106, + IV6_VBUFERR1_IRQn = 107, + S0_WLINE1_IRQn = 108, + S1_VI_VSYNC1_IRQn = 109, + S1_LO_VSYNC1_IRQn = 110, + S1_VSYNCERR1_IRQn = 111, + S1_VFIELD1_IRQn = 112, + IV2_VBUFERR1_IRQn = 113, + IV4_VBUFERR1_IRQn = 114, + S1_WLINE1_IRQn = 115, + OIR_VI_VSYNC1_IRQn = 116, + OIR_LO_VSYNC1_IRQn = 117, + OIR_VSYNCERR1_IRQn = 118, + OIR_VFIELD1_IRQn = 119, + IV7_VBUFERR1_IRQn = 120, + IV8_VBUFERR1_IRQn = 121, + /* Reserved = 122 */ + + IMRDI_IRQn = 123, + IMR2I0_IRQn = 124, + IMR2I1_IRQn = 125, + + JEDI_IRQn = 126, + JDTI_IRQn = 127, + + CMP0_IRQn = 128, + CMP1_IRQn = 129, + + INT0_IRQn = 130, + INT1_IRQn = 131, + INT2_IRQn = 132, + INT3_IRQn = 133, + + OSTMI0TINT_IRQn = 134, /*!< OSTM Interrupt */ + OSTMI1TINT_IRQn = 135, /*!< OSTM Interrupt */ + + CMI_IRQn = 136, + WTOUT_IRQn = 137, + + ITI_IRQn = 138, + + TGI0A_IRQn = 139, + TGI0B_IRQn = 140, + TGI0C_IRQn = 141, + TGI0D_IRQn = 142, + TGI0V_IRQn = 143, + TGI0E_IRQn = 144, + TGI0F_IRQn = 145, + TGI1A_IRQn = 146, + TGI1B_IRQn = 147, + TGI1V_IRQn = 148, + TGI1U_IRQn = 149, + TGI2A_IRQn = 150, + TGI2B_IRQn = 151, + TGI2V_IRQn = 152, + TGI2U_IRQn = 153, + TGI3A_IRQn = 154, + TGI3B_IRQn = 155, + TGI3C_IRQn = 156, + TGI3D_IRQn = 157, + TGI3V_IRQn = 158, + TGI4A_IRQn = 159, + TGI4B_IRQn = 160, + TGI4C_IRQn = 161, + TGI4D_IRQn = 162, + TGI4V_IRQn = 163, + + CMI1_IRQn = 164, + CMI2_IRQn = 165, + + SGDEI0_IRQn = 166, + SGDEI1_IRQn = 167, + SGDEI2_IRQn = 168, + SGDEI3_IRQn = 169, + + ADI_IRQn = 170, + LMTI_IRQn = 171, + + SSII0_IRQn = 172, /*!< SSIF Interrupt */ + SSIRXI0_IRQn = 173, /*!< SSIF Interrupt */ + SSITXI0_IRQn = 174, /*!< SSIF Interrupt */ + SSII1_IRQn = 175, /*!< SSIF Interrupt */ + SSIRXI1_IRQn = 176, /*!< SSIF Interrupt */ + SSITXI1_IRQn = 177, /*!< SSIF Interrupt */ + SSII2_IRQn = 178, /*!< SSIF Interrupt */ + SSIRTI2_IRQn = 179, /*!< SSIF Interrupt */ + SSII3_IRQn = 180, /*!< SSIF Interrupt */ + SSIRXI3_IRQn = 181, /*!< SSIF Interrupt */ + SSITXI3_IRQn = 182, /*!< SSIF Interrupt */ + SSII4_IRQn = 183, /*!< SSIF Interrupt */ + SSIRTI4_IRQn = 184, /*!< SSIF Interrupt */ + SSII5_IRQn = 185, /*!< SSIF Interrupt */ + SSIRXI5_IRQn = 186, /*!< SSIF Interrupt */ + SSITXI5_IRQn = 187, /*!< SSIF Interrupt */ + + SPDIFI_IRQn = 188, + + INTIICTEI0_IRQn = 189, /*!< RIIC Interrupt */ + INTIICRI0_IRQn = 190, /*!< RIIC Interrupt */ + INTIICTI0_IRQn = 191, /*!< RIIC Interrupt */ + INTIICSPI0_IRQn = 192, /*!< RIIC Interrupt */ + INTIICSTI0_IRQn = 193, /*!< RIIC Interrupt */ + INTIICNAKI0_IRQn = 194, /*!< RIIC Interrupt */ + INTIICALI0_IRQn = 195, /*!< RIIC Interrupt */ + INTIICTMOI0_IRQn = 196, /*!< RIIC Interrupt */ + INTIICTEI1_IRQn = 197, /*!< RIIC Interrupt */ + INTIICRI1_IRQn = 198, /*!< RIIC Interrupt */ + INTIICTI1_IRQn = 199, /*!< RIIC Interrupt */ + INTIICSPI1_IRQn = 200, /*!< RIIC Interrupt */ + INTIICSTI1_IRQn = 201, /*!< RIIC Interrupt */ + INTIICNAKI1_IRQn = 202, /*!< RIIC Interrupt */ + INTIICALI1_IRQn = 203, /*!< RIIC Interrupt */ + INTIICTMOI1_IRQn = 204, /*!< RIIC Interrupt */ + INTIICTEI2_IRQn = 205, /*!< RIIC Interrupt */ + INTIICRI2_IRQn = 206, /*!< RIIC Interrupt */ + INTIICTI2_IRQn = 207, /*!< RIIC Interrupt */ + INTIICSPI2_IRQn = 208, /*!< RIIC Interrupt */ + INTIICSTI2_IRQn = 209, /*!< RIIC Interrupt */ + INTIICNAKI2_IRQn = 210, /*!< RIIC Interrupt */ + INTIICALI2_IRQn = 211, /*!< RIIC Interrupt */ + INTIICTMOI2_IRQn = 212, /*!< RIIC Interrupt */ + INTIICTEI3_IRQn = 213, /*!< RIIC Interrupt */ + INTIICRI3_IRQn = 214, /*!< RIIC Interrupt */ + INTIICTI3_IRQn = 215, /*!< RIIC Interrupt */ + INTIICSPI3_IRQn = 216, /*!< RIIC Interrupt */ + INTIICSTI3_IRQn = 217, /*!< RIIC Interrupt */ + INTIICNAKI3_IRQn = 218, /*!< RIIC Interrupt */ + INTIICALI3_IRQn = 219, /*!< RIIC Interrupt */ + INTIICTMOI3_IRQn = 220, /*!< RIIC Interrupt */ + + SCIFBRI0_IRQn = 221, /*!< SCIF Interrupt */ + SCIFERI0_IRQn = 222, /*!< SCIF Interrupt */ + SCIFRXI0_IRQn = 223, /*!< SCIF Interrupt */ + SCIFTXI0_IRQn = 224, /*!< SCIF Interrupt */ + SCIFBRI1_IRQn = 225, /*!< SCIF Interrupt */ + SCIFERI1_IRQn = 226, /*!< SCIF Interrupt */ + SCIFRXI1_IRQn = 227, /*!< SCIF Interrupt */ + SCIFTXI1_IRQn = 228, /*!< SCIF Interrupt */ + SCIFBRI2_IRQn = 229, /*!< SCIF Interrupt */ + SCIFERI2_IRQn = 230, /*!< SCIF Interrupt */ + SCIFRXI2_IRQn = 231, /*!< SCIF Interrupt */ + SCIFTXI2_IRQn = 232, /*!< SCIF Interrupt */ + SCIFBRI3_IRQn = 233, /*!< SCIF Interrupt */ + SCIFERI3_IRQn = 234, /*!< SCIF Interrupt */ + SCIFRXI3_IRQn = 235, /*!< SCIF Interrupt */ + SCIFTXI3_IRQn = 236, /*!< SCIF Interrupt */ + SCIFBRI4_IRQn = 237, /*!< SCIF Interrupt */ + SCIFERI4_IRQn = 238, /*!< SCIF Interrupt */ + SCIFRXI4_IRQn = 239, /*!< SCIF Interrupt */ + SCIFTXI4_IRQn = 240, /*!< SCIF Interrupt */ + SCIFBRI5_IRQn = 241, /*!< SCIF Interrupt */ + SCIFERI5_IRQn = 242, /*!< SCIF Interrupt */ + SCIFRXI5_IRQn = 243, /*!< SCIF Interrupt */ + SCIFTXI5_IRQn = 244, /*!< SCIF Interrupt */ + SCIFBRI6_IRQn = 245, /*!< SCIF Interrupt */ + SCIFERI6_IRQn = 246, /*!< SCIF Interrupt */ + SCIFRXI6_IRQn = 247, /*!< SCIF Interrupt */ + SCIFTXI6_IRQn = 248, /*!< SCIF Interrupt */ + SCIFBRI7_IRQn = 249, /*!< SCIF Interrupt */ + SCIFERI7_IRQn = 250, /*!< SCIF Interrupt */ + SCIFRXI7_IRQn = 251, /*!< SCIF Interrupt */ + SCIFTXI7_IRQn = 252, /*!< SCIF Interrupt */ + + INTRCANGERR_IRQn = 253, + INTRCANGRECC_IRQn = 254, + INTRCAN0REC_IRQn = 255, + INTRCAN0ERR_IRQn = 256, + INTRCAN0TRX_IRQn = 257, + INTRCAN1REC_IRQn = 258, + INTRCAN1ERR_IRQn = 259, + INTRCAN1TRX_IRQn = 260, + INTRCAN2REC_IRQn = 261, + INTRCAN2ERR_IRQn = 262, + INTRCAN2TRX_IRQn = 263, + INTRCAN3REC_IRQn = 264, + INTRCAN3ERR_IRQn = 265, + INTRCAN3TRX_IRQn = 266, + INTRCAN4REC_IRQn = 267, + INTRCAN4ERR_IRQn = 268, + INTRCAN4TRX_IRQn = 269, + + RSPISPEI0_IRQn = 270, /*!< RSPI Interrupt */ + RSPISPRI0_IRQn = 271, /*!< RSPI Interrupt */ + RSPISPTI0_IRQn = 272, /*!< RSPI Interrupt */ + RSPISPEI1_IRQn = 273, /*!< RSPI Interrupt */ + RSPISPRI1_IRQn = 274, /*!< RSPI Interrupt */ + RSPISPTI1_IRQn = 275, /*!< RSPI Interrupt */ + RSPISPEI2_IRQn = 276, /*!< RSPI Interrupt */ + RSPISPRI2_IRQn = 277, /*!< RSPI Interrupt */ + RSPISPTI2_IRQn = 278, /*!< RSPI Interrupt */ + RSPISPEI3_IRQn = 279, /*!< RSPI Interrupt */ + RSPISPRI3_IRQn = 280, /*!< RSPI Interrupt */ + RSPISPTI3_IRQn = 281, /*!< RSPI Interrupt */ + RSPISPEI4_IRQn = 282, /*!< RSPI Interrupt */ + RSPISPRI4_IRQn = 283, /*!< RSPI Interrupt */ + RSPISPTI4_IRQn = 284, /*!< RSPI Interrupt */ + + IEBBTD_IRQn = 285, + IEBBTERR_IRQn = 286, + IEBBTSTA_IRQn = 287, + IEBBTV_IRQn = 288, + + ISY_IRQn = 289, + IERR_IRQn = 290, + ITARG_IRQn = 291, + ISEC_IRQn = 292, + IBUF_IRQn = 293, + IREADY_IRQn = 294, + + STERB_IRQn = 295, + FLTENDI_IRQn = 296, + FLTREQ0I_IRQn = 297, + FLTREQ1I_IRQn = 298, + + MMC0_IRQn = 299, + MMC1_IRQn = 300, + MMC2_IRQn = 301, + + SCHI0_3_IRQn = 302, + SDHI0_0_IRQn = 303, + SDHI0_1_IRQn = 304, + SCHI1_3_IRQn = 305, + SDHI1_0_IRQn = 306, + SDHI1_1_IRQn = 307, + + ARM_IRQn = 308, + PRD_IRQn = 309, + CUP_IRQn = 310, + + SCUAI0_IRQn = 311, + SCUAI1_IRQn = 312, + SCUFDI0_IRQn = 313, + SCUFDI1_IRQn = 314, + SCUFDI2_IRQn = 315, + SCUFDI3_IRQn = 316, + SCUFUI0_IRQn = 317, + SCUFUI1_IRQn = 318, + SCUFUI2_IRQn = 319, + SCUFUI3_IRQn = 320, + SCUDVI0_IRQn = 321, + SCUDVI1_IRQn = 322, + SCUDVI2_IRQn = 323, + SCUDVI3_IRQn = 324, + + MLB_CINT_IRQn = 325, + MLB_SINT_IRQn = 326, + + DRC10_IRQn = 327, + DRC11_IRQn = 328, + + /* 329-330 Reserved */ + + LINI0_INT_T_IRQn = 331, + LINI0_INT_R_IRQn = 332, + LINI0_INT_S_IRQn = 333, + LINI0_INT_M_IRQn = 334, + LINI1_INT_T_IRQn = 335, + LINI1_INT_R_IRQn = 336, + LINI1_INT_S_IRQn = 337, + LINI1_INT_M_IRQn = 338, + + /* 339-346 Reserved */ + + SCIERI0_IRQn = 347, + SCIRXI0_IRQn = 348, + SCITXI0_IRQn = 349, + SCITEI0_IRQn = 350, + SCIERI1_IRQn = 351, + SCIRXI1_IRQn = 352, + SCITXI1_IRQn = 353, + SCITEI1_IRQn = 354, + + AVBI_DATA = 355, + AVBI_ERROR = 356, + AVBI_MANAGE = 357, + AVBI_MAC = 358, + + ETHERI_IRQn = 359, + + /* 360-363 Reserved */ + + CEUI_IRQn = 364, + + /* 365-380 Reserved */ + + + H2XMLB_ERRINT_IRQn = 381, + H2XIC1_ERRINT_IRQn = 382, + X2HPERI1_ERRINT_IRQn = 383, + X2HPERR2_ERRINT_IRQn = 384, + X2HPERR34_ERRINT_IRQn= 385, + X2HPERR5_ERRINT_IRQn = 386, + X2HPERR67_ERRINT_IRQn= 387, + X2HDBGR_ERRINT_IRQn = 388, + X2HBSC_ERRINT_IRQn = 389, + X2HSPI1_ERRINT_IRQn = 390, + X2HSPI2_ERRINT_IRQn = 391, + PRRI_IRQn = 392, + + IFEI0_IRQn = 393, + OFFI0_IRQn = 394, + PFVEI0_IRQn = 395, + IFEI1_IRQn = 396, + OFFI1_IRQn = 397, + PFVEI1_IRQn = 398, + + /* 399-415 Reserved */ + TINT0_IRQn = 416, + TINT1_IRQn = 417, + TINT2_IRQn = 418, + TINT3_IRQn = 419, + TINT4_IRQn = 420, + TINT5_IRQn = 421, + TINT6_IRQn = 422, + TINT7_IRQn = 423, + TINT8_IRQn = 424, + TINT9_IRQn = 425, + TINT10_IRQn = 426, + TINT11_IRQn = 427, + TINT12_IRQn = 428, + TINT13_IRQn = 429, + TINT14_IRQn = 430, + TINT15_IRQn = 431, + TINT16_IRQn = 432, + TINT17_IRQn = 433, + TINT18_IRQn = 434, + TINT19_IRQn = 435, + TINT20_IRQn = 436, + TINT21_IRQn = 437, + TINT22_IRQn = 438, + TINT23_IRQn = 439, + TINT24_IRQn = 440, + TINT25_IRQn = 441, + TINT26_IRQn = 442, + TINT27_IRQn = 443, + TINT28_IRQn = 444, + TINT29_IRQn = 445, + TINT30_IRQn = 446, + TINT31_IRQn = 447, + TINT32_IRQn = 448, + TINT33_IRQn = 449, + TINT34_IRQn = 450, + TINT35_IRQn = 451, + TINT36_IRQn = 452, + TINT37_IRQn = 453, + TINT38_IRQn = 454, + TINT39_IRQn = 455, + TINT40_IRQn = 456, + TINT41_IRQn = 457, + TINT42_IRQn = 458, + TINT43_IRQn = 459, + TINT44_IRQn = 460, + TINT45_IRQn = 461, + TINT46_IRQn = 462, + TINT47_IRQn = 463, + TINT48_IRQn = 464, + TINT49_IRQn = 465, + TINT50_IRQn = 466, + TINT51_IRQn = 467, + TINT52_IRQn = 468, + TINT53_IRQn = 469, + TINT54_IRQn = 470, + TINT55_IRQn = 471, + TINT56_IRQn = 472, + TINT57_IRQn = 473, + TINT58_IRQn = 474, + TINT59_IRQn = 475, + TINT60_IRQn = 476, + TINT61_IRQn = 477, + TINT62_IRQn = 478, + TINT63_IRQn = 479, + TINT64_IRQn = 480, + TINT65_IRQn = 481, + TINT66_IRQn = 482, + TINT67_IRQn = 483, + TINT68_IRQn = 484, + TINT69_IRQn = 485, + TINT70_IRQn = 486, + TINT71_IRQn = 487, + TINT72_IRQn = 488, + TINT73_IRQn = 489, + TINT74_IRQn = 490, + TINT75_IRQn = 491, + TINT76_IRQn = 492, + TINT77_IRQn = 493, + TINT78_IRQn = 494, + TINT79_IRQn = 495, + TINT80_IRQn = 496, + TINT81_IRQn = 497, + TINT82_IRQn = 498, + TINT83_IRQn = 499, + TINT84_IRQn = 500, + TINT85_IRQn = 501, + TINT86_IRQn = 502, + TINT87_IRQn = 503, + TINT88_IRQn = 504, + TINT89_IRQn = 505, + TINT90_IRQn = 506, + TINT91_IRQn = 507, + TINT92_IRQn = 508, + TINT93_IRQn = 509, + TINT94_IRQn = 510, + TINT95_IRQn = 511, + TINT96_IRQn = 512, + TINT97_IRQn = 513, + TINT98_IRQn = 514, + TINT99_IRQn = 515, + TINT100_IRQn = 516, + TINT101_IRQn = 517, + TINT102_IRQn = 518, + TINT103_IRQn = 519, + TINT104_IRQn = 520, + TINT105_IRQn = 521, + TINT106_IRQn = 522, + TINT107_IRQn = 523, + TINT108_IRQn = 524, + TINT109_IRQn = 525, + TINT110_IRQn = 526, + TINT111_IRQn = 527, + TINT112_IRQn = 528, + TINT113_IRQn = 529, + TINT114_IRQn = 530, + TINT115_IRQn = 531, + TINT116_IRQn = 532, + TINT117_IRQn = 533, + TINT118_IRQn = 534, + TINT119_IRQn = 535, + TINT120_IRQn = 536, + TINT121_IRQn = 537, + TINT122_IRQn = 538, + TINT123_IRQn = 539, + TINT124_IRQn = 540, + TINT125_IRQn = 541, + TINT126_IRQn = 542, + TINT127_IRQn = 543, + TINT128_IRQn = 544, + TINT129_IRQn = 545, + TINT130_IRQn = 546, + TINT131_IRQn = 547, + TINT132_IRQn = 548, + TINT133_IRQn = 549, + TINT134_IRQn = 550, + TINT135_IRQn = 551, + TINT136_IRQn = 552, + TINT137_IRQn = 553, + TINT138_IRQn = 554, + TINT139_IRQn = 555, + TINT140_IRQn = 556, + TINT141_IRQn = 557, + TINT142_IRQn = 558, + TINT143_IRQn = 559, + TINT144_IRQn = 560, + TINT145_IRQn = 561, + TINT146_IRQn = 562, + TINT147_IRQn = 563, + TINT148_IRQn = 564, + TINT149_IRQn = 565, + TINT150_IRQn = 566, + TINT151_IRQn = 567, + TINT152_IRQn = 568, + TINT153_IRQn = 569, + TINT154_IRQn = 570, + TINT155_IRQn = 571, + TINT156_IRQn = 572, + TINT157_IRQn = 573, + TINT158_IRQn = 574, + TINT159_IRQn = 575, + TINT160_IRQn = 576, + TINT161_IRQn = 577, + TINT162_IRQn = 578, + TINT163_IRQn = 579, + TINT164_IRQn = 580, + TINT165_IRQn = 581, + TINT166_IRQn = 582, + TINT167_IRQn = 583, + TINT168_IRQn = 584, + TINT169_IRQn = 585, + TINT170_IRQn = 586 + +} IRQn_Type; + +#define Renesas_RZ_A1_IRQ_MAX TINT170_IRQn + +/* -------- Configuration of the Cortex-A9 Processor and Core Peripherals ------- */ +#define __CA9_REV 0x0000 /*!< Core revision r0 */ + +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +#define __FPU_PRESENT 1 /*!< FPU present or not */ + +#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +#include <core_ca9.h> +#include "system_VKRZA1H.h" + + +/******************************************************************************/ +/* Device Specific Peripheral Section */ +/******************************************************************************/ +/** @addtogroup Renesas_RZ_A1_Peripherals Renesas_RZ_A1 Peripherals + Renesas_RZ_A1 Device Specific Peripheral registers structures + @{ +*/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +#include "pl310.h" +#include "gic.h" +#include "nvic_wrapper.h" +#include "cmsis_nvic.h" + +#include "ostm_iodefine.h" +#include "gpio_iodefine.h" +#include "cpg_iodefine.h" +#include "l2c_iodefine.h" + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +/*@}*/ /* end of group Renesas_RZ_A1_Peripherals */ + + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/** @addtogroup Renesas_RZ_A1_MemoryMap Renesas_RZ_A1 Memory Mapping + @{ +*/ + +/* R7S72100 CPU board */ +#define Renesas_RZ_A1_NORFLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */ +#define Renesas_RZ_A1_NORFLASH_BASE1 (0x04000000UL) /*!< (FLASH1 ) Base Address */ +#define Renesas_RZ_A1_SDRAM_BASE0 (0x08000000UL) /*!< (SDRAM0 ) Base Address */ +#define Renesas_RZ_A1_SDRAM_BASE1 (0x0C000000UL) /*!< (SDRAM1 ) Base Address */ +#define Renesas_RZ_A1_USER_AREA0 (0x10000000UL) /*!< (USER0 ) Base Address */ +#define Renesas_RZ_A1_USER_AREA1 (0x14000000UL) /*!< (USER1 ) Base Address */ +#define Renesas_RZ_A1_SPI_IO0 (0x18000000UL) /*!< (SPI_IO0 ) Base Address */ +#define Renesas_RZ_A1_SPI_IO1 (0x1C000000UL) /*!< (SPI_IO1 ) Base Address */ +#define Renesas_RZ_A1_ONCHIP_SRAM_BASE (0x20000000UL) /*!< (SRAM_OC ) Base Address */ +#define Renesas_RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */ +#define Renesas_RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */ +#define Renesas_RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */ +#define Renesas_RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */ +#define Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE (0xe8201000UL) /*!< (GIC DIST ) Base Address */ +#define Renesas_RZ_A1_GIC_INTERFACE_BASE (0xe8202000UL) /*!< (GIC CPU IF) Base Address */ +#define Renesas_RZ_A1_PL310_BASE (0x3ffff000UL) /*!< (PL310 ) Base Address */ +#define Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE (0x60000000UL) /*!< (SRAM_OC ) Base Address */ + +//Following macros define the descriptors and attributes used to define the Renesas_RZ_A1 MMU flat-map +//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0. +#define section_normal(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = NON_SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + __get_section_descriptor(&descriptor_l1, region); + +#define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + __get_section_descriptor(&descriptor_l1, region); + +//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0. +#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = NON_SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + __get_section_descriptor(&descriptor_l1, region); + +//Sect_Normal_RO. Sect_Normal_Cod, but not executable +#define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = NON_SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + __get_section_descriptor(&descriptor_l1, region); + +#ifdef __RAM_DEBUG__ +//Sect_Normal_RWX. Sect_Normal_Cod, but writeable +#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = NON_SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + __get_section_descriptor(&descriptor_l1, region); +#else +//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable +#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = NON_SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + __get_section_descriptor(&descriptor_l1, region); +#endif + +//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 +#define section_so(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + __get_section_descriptor(&descriptor_l1, region); + +//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0 +#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + __get_section_descriptor(&descriptor_l1, region); + +//Sect_Device_RW. Sect_Device_RO, but writeable +#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + __get_section_descriptor(&descriptor_l1, region); +//Page_4k_Device_RW. Shared device, not executable, rw, domain 0 +#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = SHARED_DEVICE; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + __get_page_descriptor(&descriptor_l1, &descriptor_l2, region); + +//Page_64k_Device_RW. Shared device, not executable, rw, domain 0 +#define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = SHARED_DEVICE; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + __get_page_descriptor(&descriptor_l1, &descriptor_l2, region); + +/*@}*/ /* end of group Renesas_RZ_A1_MemoryMap */ + +/******************************************************************************/ +/* Clock Settings */ +/******************************************************************************/ +/** @addtogroup Renesas_RZ_A1_H_Clocks Renesas_RZ_A1 Clock definitions + @{ +*/ + +/* + * Clock Mode 0 settings + * SW1-4(MD_CLK):ON + * SW1-5(MD_CLKS):ON + * FRQCR=0x1035 + * CLKEN2 = 0b - unstable + * CLKEN[1:0]=01b - Output, Low, Low + * IFC[1:0] =00b - CPU clock is 1/1 PLL clock + * FRQCR2=0x0001 + * GFC[1:0] =01b - Graphic clock is 2/3 bus clock + */ +#define CM0_RENESAS_RZ_A1_CLKIN ( 13333333u) +#define CM0_RENESAS_RZ_A1_CLKO ( 66666666u) +#define CM0_RENESAS_RZ_A1_I_CLK (400000000u) +#define CM0_RENESAS_RZ_A1_G_CLK (266666666u) +#define CM0_RENESAS_RZ_A1_B_CLK (133333333u) +#define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u) +#define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u) + +/* + * Clock Mode 1 settings + * SW1-4(MD_CLK):OFF + * SW1-5(MD_CLKS):ON + * FRQCR=0x1335 + * CLKEN2 = 0b - unstable + * CLKEN[1:0]=01b - Output, Low, Low + * IFC[1:0] =11b - CPU clock is 1/3 PLL clock + * FRQCR2=0x0003 + * GFC[1:0] =11b - graphic clock is 1/3 bus clock + */ +#define CM1_RENESAS_RZ_A1_CLKIN ( 48000000u) +#define CM1_RENESAS_RZ_A1_CLKO ( 64000000u) +#define CM1_RENESAS_RZ_A1_I_CLK (128000000u) +#define CM1_RENESAS_RZ_A1_G_CLK (128000000u) +#define CM1_RENESAS_RZ_A1_B_CLK (128000000u) +#define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u) +#define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u) + +/*@}*/ /* end of group Renesas_RZ_A1_Clocks */ + +/******************************************************************************/ +/* CPG Settings */ +/******************************************************************************/ +/** @addtogroup Renesas_RZ_A1_H_CPG Renesas_RZ_A1 CPG Bit definitions + @{ +*/ + +#define CPG_FRQCR_SHIFT_CKOEN2 (14) +#define CPG_FRQCR_BIT_CKOEN2 (0x1 << CPG_FRQCR_SHIFT_CKOEN2) +#define CPG_FRQCR_SHIFT_CKOEN0 (12) +#define CPG_FRQCR_BITS_CKOEN0 (0x3 << CPG_FRQCR_SHIFT_CKOEN0) +#define CPG_FRQCR_SHIFT_IFC (8) +#define CPG_FRQCR_BITS_IFC (0x3 << CPG_FRQCR_SHIFT_IFC) + +#define CPG_FRQCR2_SHIFT_GFC (0) +#define CPG_FRQCR2_BITS_GFC (0x3 << CPG_FRQCR2_SHIFT_GFC) + + +#define CPG_STBCR1_BIT_STBY (0x80u) +#define CPG_STBCR1_BIT_DEEP (0x40u) +#define CPG_STBCR2_BIT_HIZ (0x80u) +#define CPG_STBCR2_BIT_MSTP20 (0x01u) /* CoreSight */ +#define CPG_STBCR3_BIT_MSTP37 (0x80u) /* IEBus */ +#define CPG_STBCR3_BIT_MSTP36 (0x40u) /* IrDA */ +#define CPG_STBCR3_BIT_MSTP35 (0x20u) /* LIN0 */ +#define CPG_STBCR3_BIT_MSTP34 (0x10u) /* LIN1 */ +#define CPG_STBCR3_BIT_MSTP33 (0x08u) /* Multi-Function Timer */ +#define CPG_STBCR3_BIT_MSTP32 (0x04u) /* CAN */ +#define CPG_STBCR3_BIT_MSTP30 (0x01u) /* Motor Control PWM Timer */ +#define CPG_STBCR4_BIT_MSTP47 (0x80u) /* SCIF0 */ +#define CPG_STBCR4_BIT_MSTP46 (0x40u) /* SCIF1 */ +#define CPG_STBCR4_BIT_MSTP45 (0x20u) /* SCIF2 */ +#define CPG_STBCR4_BIT_MSTP44 (0x10u) /* SCIF3 */ +#define CPG_STBCR4_BIT_MSTP43 (0x08u) /* SCIF4 */ +#define CPG_STBCR4_BIT_MSTP42 (0x04u) /* SCIF5 */ +#define CPG_STBCR4_BIT_MSTP41 (0x02u) /* SCIF6 */ +#define CPG_STBCR4_BIT_MSTP40 (0x01u) /* SCIF7 */ +#define CPG_STBCR5_BIT_MSTP57 (0x80u) /* SCI0 */ +#define CPG_STBCR5_BIT_MSTP56 (0x40u) /* SCI1 */ +#define CPG_STBCR5_BIT_MSTP55 (0x20u) /* Sound Generator0 */ +#define CPG_STBCR5_BIT_MSTP54 (0x10u) /* Sound Generator1 */ +#define CPG_STBCR5_BIT_MSTP53 (0x08u) /* Sound Generator2 */ +#define CPG_STBCR5_BIT_MSTP52 (0x04u) /* Sound Generator3 */ +#define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */ +#define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */ +#define CPG_STBCR6_BIT_MSTP67 (0x80u) /* General A/D Comvertor */ +#define CPG_STBCR6_BIT_MSTP66 (0x40u) /* Capture Engine */ +#define CPG_STBCR6_BIT_MSTP65 (0x20u) /* Display out comparison0 */ +#define CPG_STBCR6_BIT_MSTP64 (0x10u) /* Display out comparison1 */ +#define CPG_STBCR6_BIT_MSTP63 (0x08u) /* Dynamic Range Compalator0 */ +#define CPG_STBCR6_BIT_MSTP62 (0x04u) /* Dynamic Range Compalator1 */ +#define CPG_STBCR6_BIT_MSTP61 (0x02u) /* JPEG Decoder */ +#define CPG_STBCR6_BIT_MSTP60 (0x01u) /* Realtime Clock */ +#define CPG_STBCR7_BIT_MSTP77 (0x80u) /* Video Decoder0 */ +#define CPG_STBCR7_BIT_MSTP76 (0x40u) /* Video Decoder1 */ +#define CPG_STBCR7_BIT_MSTP74 (0x10u) /* Ether */ +#define CPG_STBCR7_BIT_MSTP73 (0x04u) /* NAND Flash Memory Controller */ +#define CPG_STBCR7_BIT_MSTP71 (0x02u) /* USB0 */ +#define CPG_STBCR7_BIT_MSTP70 (0x01u) /* USB1 */ +#define CPG_STBCR8_BIT_MSTP87 (0x80u) /* IMR-LS2_0 */ +#define CPG_STBCR8_BIT_MSTP86 (0x40u) /* IMR-LS2_1 */ +#define CPG_STBCR8_BIT_MSTP85 (0x20u) /* IMR-LSD */ +#define CPG_STBCR8_BIT_MSTP84 (0x10u) /* MMC Host Interface */ +#define CPG_STBCR8_BIT_MSTP83 (0x08u) /* MediaLB */ +#define CPG_STBCR8_BIT_MSTP81 (0x02u) /* SCUX */ +#define CPG_STBCR9_BIT_MSTP97 (0x80u) /* RIIC0 */ +#define CPG_STBCR9_BIT_MSTP96 (0x40u) /* RIIC1 */ +#define CPG_STBCR9_BIT_MSTP95 (0x20u) /* RIIC2 */ +#define CPG_STBCR9_BIT_MSTP94 (0x10u) /* RIIC3 */ +#define CPG_STBCR9_BIT_MSTP93 (0x08u) /* SPI Multi I/O Bus Controller0 */ +#define CPG_STBCR9_BIT_MSTP92 (0x04u) /* SPI Multi I/O Bus Controller1 */ +#define CPG_STBCR9_BIT_MSTP91 (0x02u) /* VDC5_0 */ +#define CPG_STBCR9_BIT_MSTP90 (0x01u) /* VDC5_1 */ +#define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */ +#define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */ +#define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */ +#define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */ +#define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */ +#define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */ +#define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */ +#define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */ +#define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */ +#define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */ +#define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */ +#define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */ +#define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */ +#define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */ +#define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */ +#define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */ +#define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */ +#define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */ +#define CPG_CSTBCR1_BIT_CMSTP11 (0x02u) /* PFV */ +#define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */ +#define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */ +#define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */ +#define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */ +#define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */ +#define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */ +#define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */ +#define CPG_SWRSTCR2_BIT_SRST27 (0x80u) /* Display out comparison0 */ +#define CPG_SWRSTCR2_BIT_SRST26 (0x40u) /* Display out comparison1 */ +#define CPG_SWRSTCR2_BIT_SRST25 (0x20u) /* Dynamic Range Compalator0 */ +#define CPG_SWRSTCR2_BIT_SRST24 (0x10u) /* Dynamic Range Compalator1 */ +#define CPG_SWRSTCR2_BIT_SRST23 (0x08u) /* VDC5_0 */ +#define CPG_SWRSTCR2_BIT_SRST22 (0x04u) /* VDC5_1 */ +#define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */ +#define CPG_SWRSTCR3_BIT_SRST36 (0x40u) /* DMA */ +#define CPG_SWRSTCR3_BIT_SRST35 (0x20u) /* IMR-LS2_0 */ +#define CPG_SWRSTCR3_BIT_SRST34 (0x10u) /* IMR-LS2_1 */ +#define CPG_SWRSTCR3_BIT_SRST33 (0x08u) /* IMR-LSD? */ +#define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */ +#define CPG_SWRSTCR3_BIT_SRST31 (0x02u) /* Capture Engine */ +#define CPG_SWRSTCR4_BIT_SRST41 (0x02u) /* Video Decoder0 */ +#define CPG_SWRSTCR4_BIT_SRST40 (0x01u) /* Video Decoder1 */ +#define CPG_SYSCR1_BIT_VRAME4 (0x10u) /* VRAM E Page4 */ +#define CPG_SYSCR1_BIT_VRAME3 (0x08u) /* VRAM E Page3 */ +#define CPG_SYSCR1_BIT_VRAME2 (0x04u) /* VRAM E Page2 */ +#define CPG_SYSCR1_BIT_VRAME1 (0x02u) /* VRAM E Page1 */ +#define CPG_SYSCR1_BIT_VRAME0 (0x01u) /* VRAM E Page0 */ +#define CPG_SYSCR2_BIT_VRAMWE4 (0x10u) /* VRAM WE Page4 */ +#define CPG_SYSCR2_BIT_VRAMWE3 (0x08u) /* VRAM WE Page3 */ +#define CPG_SYSCR2_BIT_VRAMWE2 (0x04u) /* VRAM WE Page2 */ +#define CPG_SYSCR2_BIT_VRAMWE1 (0x02u) /* VRAM WE Page1 */ +#define CPG_SYSCR2_BIT_VRAMWE0 (0x01u) /* VRAM WE Page0 */ +#define CPG_SYSCR3_BIT_RRAMWE3 (0x08u) /* RRAM WE Page3 */ +#define CPG_SYSCR3_BIT_RRAMWE2 (0x04u) /* RRAM WE Page2 */ +#define CPG_SYSCR3_BIT_RRAMWE1 (0x02u) /* RRAM WE Page1 */ +#define CPG_SYSCR3_BIT_RRAMWE0 (0x01u) /* RRAM WE Page0 */ + +/*@}*/ /* end of group Renesas_RZ_A1_CPG */ + +/******************************************************************************/ +/* GPIO Settings */ +/******************************************************************************/ +/** @addtogroup Renesas_RZ_A1_H_GPIO Renesas_RZ_A1 GPIO Bit definitions + @{ +*/ + +#define GPIO_BIT_N0 (1u << 0) +#define GPIO_BIT_N1 (1u << 1) +#define GPIO_BIT_N2 (1u << 2) +#define GPIO_BIT_N3 (1u << 3) +#define GPIO_BIT_N4 (1u << 4) +#define GPIO_BIT_N5 (1u << 5) +#define GPIO_BIT_N6 (1u << 6) +#define GPIO_BIT_N7 (1u << 7) +#define GPIO_BIT_N8 (1u << 8) +#define GPIO_BIT_N9 (1u << 9) +#define GPIO_BIT_N10 (1u << 10) +#define GPIO_BIT_N11 (1u << 11) +#define GPIO_BIT_N12 (1u << 12) +#define GPIO_BIT_N13 (1u << 13) +#define GPIO_BIT_N14 (1u << 14) +#define GPIO_BIT_N15 (1u << 15) + + +#define MD_BOOT10_MASK (0x3) + +#define MD_BOOT10_BM0 (0x0) +#define MD_BOOT10_BM1 (0x2) +#define MD_BOOT10_BM3 (0x1) +#define MD_BOOT10_BM4_5 (0x3) + +#define MD_CLK (1u << 2) +#define MD_CLKS (1u << 3) + +/*@}*/ /* end of group Renesas_RZ_A1_GPIO */ + +#ifdef __cplusplus +} +#endif + +#endif // __VKRZA1H_H__
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/cmsis.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,12 @@ +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC1768 specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "VKRZA1H.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/cmsis_nvic.c Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,42 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2015 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "VKRZA1H.h" + +extern IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1]; + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + InterruptHandlerRegister(IRQn, (IRQHandler)vector); +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t vectors = (uint32_t)IRQTable[IRQn]; + return vectors; +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/cmsis_nvic.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,46 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2015 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/dev_drv.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,85 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/****************************************************************************** +* File Name : dev_drv.h +* $Rev: 809 $ +* $Date:: 2014-04-09 15:06:36 +0900#$ +* Description : Device driver header +******************************************************************************/ +#ifndef DEV_DRV_H +#define DEV_DRV_H + +/****************************************************************************** +Includes <System Includes> , "Project Includes" +******************************************************************************/ + + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + + +/****************************************************************************** +Macro definitions +******************************************************************************/ +/* ==== Arguments, Return values ==== */ +#define DEVDRV_SUCCESS (0) /* Success */ +#define DEVDRV_ERROR (-1) /* Failure */ + +/* ==== Flags ==== */ +#define DEVDRV_FLAG_OFF (0) /* Flag OFF */ +#define DEVDRV_FLAG_ON (1) /* Flag ON */ + +/* ==== Channels ==== */ +typedef enum devdrv_ch +{ + DEVDRV_CH_0, /* Channel 0 */ + DEVDRV_CH_1, /* Channel 1 */ + DEVDRV_CH_2, /* Channel 2 */ + DEVDRV_CH_3, /* Channel 3 */ + DEVDRV_CH_4, /* Channel 4 */ + DEVDRV_CH_5, /* Channel 5 */ + DEVDRV_CH_6, /* Channel 6 */ + DEVDRV_CH_7, /* Channel 7 */ + DEVDRV_CH_8, /* Channel 8 */ + DEVDRV_CH_9, /* Channel 9 */ + DEVDRV_CH_10, /* Channel 10 */ + DEVDRV_CH_11, /* Channel 11 */ + DEVDRV_CH_12, /* Channel 12 */ + DEVDRV_CH_13, /* Channel 13 */ + DEVDRV_CH_14, /* Channel 14 */ + DEVDRV_CH_15 /* Channel 15 */ +} devdrv_ch_t; + +/****************************************************************************** +Variable Externs +******************************************************************************/ + + +/****************************************************************************** +Functions Prototypes +******************************************************************************/ + +#endif /* DEV_DRV_H */ + +/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/gic.c Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,305 @@ +/**************************************************************************//** + * @file gic.c + * @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File + * @version + * @date 19 Sept 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2011 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#include "VKRZA1H.h" + +#define GICDistributor ((GICDistributor_Type *) Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE ) /*!< GIC Distributor configuration struct */ +#define GICInterface ((GICInterface_Type *) Renesas_RZ_A1_GIC_INTERFACE_BASE ) /*!< GIC Interface configuration struct */ + +/* Globals for use of post-scatterloading code that must access GIC */ +const uint32_t GICDistributor_BASE = Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE; +const uint32_t GICInterface_BASE = Renesas_RZ_A1_GIC_INTERFACE_BASE; + +void GIC_EnableDistributor(void) +{ + GICDistributor->ICDDCR |= 1; //enable distributor +} + +void GIC_DisableDistributor(void) +{ + GICDistributor->ICDDCR &=~1; //disable distributor +} + +uint32_t GIC_DistributorInfo(void) +{ + return (uint32_t)(GICDistributor->ICDICTR); +} + +uint32_t GIC_DistributorImplementer(void) +{ + return (uint32_t)(GICDistributor->ICDIIDR); +} + +void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target) +{ + volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]); + field += IRQn % 4; + *field = (uint8_t)cpu_target & 0xf; +} + +void GIC_SetICDICFR (const uint32_t *ICDICFRn) +{ + uint32_t i, num_irq; + + //Get the maximum number of interrupts that the GIC supports + num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1); + + for (i = 0; i < (num_irq/16); i++) + { + GICDistributor->ICDISPR[i] = *ICDICFRn++; + } +} + +uint32_t GIC_GetTarget(IRQn_Type IRQn) +{ + volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]); + field += IRQn % 4; + return ((uint32_t)*field & 0xf); +} + +void GIC_EnableInterface(void) +{ + GICInterface->ICCICR |= 1; //enable interface +} + +void GIC_DisableInterface(void) +{ + GICInterface->ICCICR &=~1; //disable distributor +} + +IRQn_Type GIC_AcknowledgePending(void) +{ + return (IRQn_Type)(GICInterface->ICCIAR); +} + +void GIC_EndInterrupt(IRQn_Type IRQn) +{ + GICInterface->ICCEOIR = IRQn; +} + +void GIC_EnableIRQ(IRQn_Type IRQn) +{ + GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32); +} + +void GIC_DisableIRQ(IRQn_Type IRQn) +{ + GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32); +} + +void GIC_SetPendingIRQ(IRQn_Type IRQn) +{ + GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32); +} + +void GIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32); +} + +void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model) +{ + volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDICFR[IRQn / 16]); + int bit_shift = (IRQn % 16)<<1; + uint8_t save_byte; + + field += (bit_shift / 8); + bit_shift %= 8; + + save_byte = *field; + save_byte &= ((uint8_t)~(3u << bit_shift)); + + *field = save_byte | ((uint8_t)((edge_level<<1) | model)<< bit_shift); +} + +void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]); + field += (IRQn % 4); + *field = (uint8_t)priority; +} + +uint32_t GIC_GetPriority(IRQn_Type IRQn) +{ + volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]); + field += (IRQn % 4); + return (uint32_t)*field; +} + +void GIC_InterfacePriorityMask(uint32_t priority) +{ + GICInterface->ICCPMR = priority & 0xff; //set priority mask +} + +void GIC_SetBinaryPoint(uint32_t binary_point) +{ + GICInterface->ICCBPR = binary_point & 0x07; //set binary point +} + +uint32_t GIC_GetBinaryPoint(uint32_t binary_point) +{ + return (uint32_t)GICInterface->ICCBPR; +} + +uint32_t GIC_GetIRQStatus(IRQn_Type IRQn) +{ + uint32_t pending, active; + + active = ((GICDistributor->ICDABR[IRQn / 32]) >> (IRQn % 32)) & 0x1; + pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1; + + return ((active<<1) | pending); +} + +void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list) +{ + GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) | ((target_list & 0xff) << 16) | (IRQn & 0xf); +} + +void GIC_DistInit(void) +{ + //IRQn_Type i; + uint32_t i; + uint32_t num_irq = 0; + uint32_t priority_field; + + //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableDistributor(); + //Get the maximum number of interrupts that the GIC supports + num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an ICDIPR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0, 0xff); + priority_field = GIC_GetPriority((IRQn_Type)0); + + for (i = 32; i < num_irq; i++) + { + //Disable all SPI the interrupts + GIC_DisableIRQ((IRQn_Type)i); + //Set level-sensitive and N-N model + //GIC_SetLevelModel(i, 0, 0); + //Set priority + GIC_SetPriority((IRQn_Type)i, priority_field/2); + //Set target list to "all cpus" + GIC_SetTarget((IRQn_Type)i, 0xff); + } + /* Set level-edge and 1-N model */ + /* GICDistributor->ICDICFR[ 0] is read only */ + GICDistributor->ICDICFR[ 1] = 0x00000055; + GICDistributor->ICDICFR[ 2] = 0xFFFD5555; + GICDistributor->ICDICFR[ 3] = 0x555FFFFF; + GICDistributor->ICDICFR[ 4] = 0x55555555; + GICDistributor->ICDICFR[ 5] = 0x55555555; + GICDistributor->ICDICFR[ 6] = 0x55555555; + GICDistributor->ICDICFR[ 7] = 0x55555555; + GICDistributor->ICDICFR[ 8] = 0x5555F555; + GICDistributor->ICDICFR[ 9] = 0x55555555; + GICDistributor->ICDICFR[10] = 0x55555555; + GICDistributor->ICDICFR[11] = 0xF5555555; + GICDistributor->ICDICFR[12] = 0xF555F555; + GICDistributor->ICDICFR[13] = 0x5555F555; + GICDistributor->ICDICFR[14] = 0x55555555; + GICDistributor->ICDICFR[15] = 0x55555555; + GICDistributor->ICDICFR[16] = 0x55555555; + GICDistributor->ICDICFR[17] = 0xFD555555; + GICDistributor->ICDICFR[18] = 0x55555557; + GICDistributor->ICDICFR[19] = 0x55555555; + GICDistributor->ICDICFR[20] = 0xFFD55555; + GICDistributor->ICDICFR[21] = 0x5F55557F; + GICDistributor->ICDICFR[22] = 0xFD55555F; + GICDistributor->ICDICFR[23] = 0x55555557; + GICDistributor->ICDICFR[24] = 0x55555555; + GICDistributor->ICDICFR[25] = 0x55555555; + GICDistributor->ICDICFR[26] = 0x55555555; + GICDistributor->ICDICFR[27] = 0x55555555; + GICDistributor->ICDICFR[28] = 0x55555555; + GICDistributor->ICDICFR[29] = 0x55555555; + GICDistributor->ICDICFR[30] = 0x55555555; + GICDistributor->ICDICFR[31] = 0x55555555; + GICDistributor->ICDICFR[32] = 0x55555555; + GICDistributor->ICDICFR[33] = 0x55555555; + + //Enable distributor + GIC_EnableDistributor(); +} + +void GIC_CPUInterfaceInit(void) +{ + IRQn_Type i; + uint32_t priority_field; + + //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableInterface(); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an ICDIPR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0, 0xff); + priority_field = GIC_GetPriority((IRQn_Type)0); + + //SGI and PPI + for (i = (IRQn_Type)0; i < 32; i++) + { + //Set level-sensitive and N-N model for PPI + //if(i > 15) + //GIC_SetLevelModel(i, 0, 0); + //Disable SGI and PPI interrupts + GIC_DisableIRQ(i); + //Set priority + GIC_SetPriority(i, priority_field/2); + } + //Enable interface + GIC_EnableInterface(); + //Set binary point to 0 + GIC_SetBinaryPoint(0); + //Set priority mask + GIC_InterfacePriorityMask(0xff); +} + +void GIC_Enable(void) +{ + GIC_DistInit(); + GIC_CPUInterfaceInit(); //per CPU +} +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/gic.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,316 @@ +/**************************************************************************//** + * @file gic.h + * @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File + * @version + * @date 29 August 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2011 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#ifndef GIC_H_ +#define GIC_H_ + +/* IO definitions (access restrictions to peripheral registers) */ +/** +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD) + */ +typedef struct +{ + __IO uint32_t ICDDCR; + __I uint32_t ICDICTR; + __I uint32_t ICDIIDR; + uint32_t RESERVED0[29]; + __IO uint32_t ICDISR[32]; + __IO uint32_t ICDISER[32]; + __IO uint32_t ICDICER[32]; + __IO uint32_t ICDISPR[32]; + __IO uint32_t ICDICPR[32]; + __I uint32_t ICDABR[32]; + uint32_t RESERVED1[32]; + __IO uint32_t ICDIPR[256]; + __IO uint32_t ICDIPTR[256]; + __IO uint32_t ICDICFR[64]; + uint32_t RESERVED2[128]; + __IO uint32_t ICDSGIR; +} GICDistributor_Type; + +/** \brief Structure type to access the Controller Interface (GICC) + */ +typedef struct +{ + __IO uint32_t ICCICR; // +0x000 - RW - CPU Interface Control Register + __IO uint32_t ICCPMR; // +0x004 - RW - Interrupt Priority Mask Register + __IO uint32_t ICCBPR; // +0x008 - RW - Binary Point Register + __I uint32_t ICCIAR; // +0x00C - RO - Interrupt Acknowledge Register + __IO uint32_t ICCEOIR; // +0x010 - WO - End of Interrupt Register + __I uint32_t ICCRPR; // +0x014 - RO - Running Priority Register + __I uint32_t ICCHPIR; // +0x018 - RO - Highest Pending Interrupt Register + __IO uint32_t ICCABPR; // +0x01C - RW - Aliased Binary Point Register + + uint32_t RESERVED[55]; + + __I uint32_t ICCIIDR; // +0x0FC - RO - CPU Interface Identification Register +} GICInterface_Type; + +/*@} end of GICD */ + +/* ########################## GIC functions #################################### */ +/** \brief Functions that manage interrupts via the GIC. + @{ + */ + +/** \brief Enable DistributorGICInterface->ICCICR |= 1; //enable interface + + Enables the forwarding of pending interrupts to the CPU interfaces. + + */ +void GIC_EnableDistributor(void); + +/** \brief Disable Distributor + + Disables the forwarding of pending interrupts to the CPU interfaces. + + */ +void GIC_DisableDistributor(void); + +/** \brief Provides information about the configuration of the GIC. + Provides information about the configuration of the GIC. + - whether the GIC implements the Security Extensions + - the maximum number of interrupt IDs that the GIC supports + - the number of CPU interfaces implemented + - if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs). + + \return Distributor Information. + */ +uint32_t GIC_DistributorInfo(void); + +/** \brief Distributor Implementer Identification Register. + + Distributor Implementer Identification Register + + \return Implementer Information. + */ +uint32_t GIC_DistributorImplementer(void); + +/** \brief Set list of processors that the interrupt is sent to if it is asserted. + + The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC. + This field stores the list of processors that the interrupt is sent to if it is asserted. + + \param [in] IRQn Interrupt number. + \param [in] target CPU target + */ +void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target); + +/** \brief Get list of processors that the interrupt is sent to if it is asserted. + + The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC. + This field stores the list of processors that the interrupt is sent to if it is asserted. + + \param [in] IRQn Interrupt number. + \param [in] target CPU target +*/ +uint32_t GIC_GetTarget(IRQn_Type IRQn); + +/** \brief Enable Interface + + Enables the signalling of interrupts to the target processors. + + */ +void GIC_EnableInterface(void); + +/** \brief Disable Interface + + Disables the signalling of interrupts to the target processors. + + */ +void GIC_DisableInterface(void); + +/** \brief Acknowledge Interrupt + + The function acknowledges the highest priority pending interrupt and returns its IRQ number. + + \return Interrupt number + */ +IRQn_Type GIC_AcknowledgePending(void); + +/** \brief End Interrupt + + The function writes the end of interrupt register, indicating that handling of the interrupt is complete. + + \param [in] IRQn Interrupt number. + */ +void GIC_EndInterrupt(IRQn_Type IRQn); + + +/** \brief Enable Interrupt + + Set-enable bit for each interrupt supported by the GIC. + + \param [in] IRQn External interrupt number. + */ +void GIC_EnableIRQ(IRQn_Type IRQn); + +/** \brief Disable Interrupt + + Clear-enable bit for each interrupt supported by the GIC. + + \param [in] IRQn Number of the external interrupt to disable + */ +void GIC_DisableIRQ(IRQn_Type IRQn); + +/** \brief Set Pending Interrupt + + Set-pending bit for each interrupt supported by the GIC. + + \param [in] IRQn Interrupt number. + */ +void GIC_SetPendingIRQ(IRQn_Type IRQn); + +/** \brief Clear Pending Interrupt + + Clear-pending bit for each interrupt supported by the GIC + + \param [in] IRQn Number of the interrupt for clear pending + */ +void GIC_ClearPendingIRQ(IRQn_Type IRQn); + +/** \brief Int_config field for each interrupt supported by the GIC. + + This field identifies whether the corresponding interrupt is: + (1) edge-triggered or (0) level-sensitive + (1) 1-N model or (0) N-N model + + \param [in] IRQn Interrupt number. + \param [in] edge_level (1) edge-triggered or (0) level-sensitive + \param [in] model (1) 1-N model or (0) N-N model + */ +void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model); + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority); + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + */ +uint32_t GIC_GetPriority(IRQn_Type IRQn); + +/** \brief CPU Interface Priority Mask Register + + The priority mask level for the CPU interface. If the priority of an interrupt is higher than the + value indicated by this field, the interface signals the interrupt to the processor. + + \param [in] Mask. + */ +void GIC_InterfacePriorityMask(uint32_t priority); + +/** \brief Set the binary point. + + Set the point at which the priority value fields split into two parts, the group priority field and the subpriority field. + + \param [in] Mask. + */ +void GIC_SetBinaryPoint(uint32_t binary_point); + +/** \brief Get the binary point. + + Get the point at which the priority value fields split into two parts, the group priority field and the subpriority field. + + \return Binary point. + */ +uint32_t GIC_GetBinaryPoint(uint32_t binary_point); + +/** \brief Get Interrupt state. + + Get the interrupt state, whether pending and/or active + + \return 0 - inactive, 1 - pending, 2 - active, 3 - pending and active + */ +uint32_t GIC_GetIRQStatus(IRQn_Type IRQn); + +/** \brief Send Software Generated interrupt + + Provides an interrupt priority filter. Only interrupts with higher priority than the value in this register can be signalled to the processor. +GIC_InterfacePriorityMask + \param [in] IRQn The Interrupt ID of the SGI. + \param [in] target_list CPUTargetList + \param [in] filter_list TargetListFilter + */ +void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list); + +/** \brief API call to initialise the interrupt distributor + + API call to initialise the interrupt distributor + + */ +void GIC_DistInit(void); + +/** \brief API call to initialise the CPU interface + + API call to initialise the CPU interface + + */ +void GIC_CPUInterfaceInit(void); + +/** \brief API call to set the Interrupt Configuration Registers + + API call to initialise the Interrupt Configuration Registers + + */ +void GIC_SetICDICFR (const uint32_t *ICDICFRn); + +/** \brief API call to Enable the GIC + + API call to Enable the GIC + + */ +void GIC_Enable(void); + +#endif /* GIC_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/bsc_iobitmask.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,357 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : bsc_iobitmask.h +* $Rev: 1115 $ +* $Date:: 2014-07-09 15:35:02 +0900#$ +* Description : BSC register define header +*******************************************************************************/ +#ifndef BSC_IOBITMASK_H +#define BSC_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ +#define BSC_CMNCR_HIZCNT (0x00000001uL) +#define BSC_CMNCR_HIZMEM (0x00000002uL) +#define BSC_CMNCR_DPRTY (0x00000600uL) +#define BSC_CMNCR_AL0 (0x01000000uL) +#define BSC_CMNCR_TL0 (0x10000000uL) + +#define BSC_CS0BCR_BSZ (0x00000600uL) +#define BSC_CS0BCR_TYPE (0x00007000uL) +#define BSC_CS0BCR_IWRRS (0x00070000uL) +#define BSC_CS0BCR_IWRRD (0x00380000uL) +#define BSC_CS0BCR_IWRWS (0x01C00000uL) +#define BSC_CS0BCR_IWRWD (0x0E000000uL) +#define BSC_CS0BCR_IWW (0x70000000uL) + +#define BSC_CS1BCR_BSZ (0x00000600uL) +#define BSC_CS1BCR_TYPE (0x00007000uL) +#define BSC_CS1BCR_IWRRS (0x00070000uL) +#define BSC_CS1BCR_IWRRD (0x00380000uL) +#define BSC_CS1BCR_IWRWS (0x01C00000uL) +#define BSC_CS1BCR_IWRWD (0x0E000000uL) +#define BSC_CS1BCR_IWW (0x70000000uL) + +#define BSC_CS2BCR_BSZ (0x00000600uL) +#define BSC_CS2BCR_TYPE (0x00007000uL) +#define BSC_CS2BCR_IWRRS (0x00070000uL) +#define BSC_CS2BCR_IWRRD (0x00380000uL) +#define BSC_CS2BCR_IWRWS (0x01C00000uL) +#define BSC_CS2BCR_IWRWD (0x0E000000uL) +#define BSC_CS2BCR_IWW (0x70000000uL) + +#define BSC_CS3BCR_BSZ (0x00000600uL) +#define BSC_CS3BCR_TYPE (0x00007000uL) +#define BSC_CS3BCR_IWRRS (0x00070000uL) +#define BSC_CS3BCR_IWRRD (0x00380000uL) +#define BSC_CS3BCR_IWRWS (0x01C00000uL) +#define BSC_CS3BCR_IWRWD (0x0E000000uL) +#define BSC_CS3BCR_IWW (0x70000000uL) + +#define BSC_CS4BCR_BSZ (0x00000600uL) +#define BSC_CS4BCR_TYPE (0x00007000uL) +#define BSC_CS4BCR_IWRRS (0x00070000uL) +#define BSC_CS4BCR_IWRRD (0x00380000uL) +#define BSC_CS4BCR_IWRWS (0x01C00000uL) +#define BSC_CS4BCR_IWRWD (0x0E000000uL) +#define BSC_CS4BCR_IWW (0x70000000uL) + +#define BSC_CS5BCR_BSZ (0x00000600uL) +#define BSC_CS5BCR_TYPE (0x00007000uL) +#define BSC_CS5BCR_IWRRS (0x00070000uL) +#define BSC_CS5BCR_IWRRD (0x00380000uL) +#define BSC_CS5BCR_IWRWS (0x01C00000uL) +#define BSC_CS5BCR_IWRWD (0x0E000000uL) +#define BSC_CS5BCR_IWW (0x70000000uL) + +#define BSC_CS0WCR_NORMAL_HW (0x00000003uL) +#define BSC_CS0WCR_NORMAL_WM (0x00000040uL) +#define BSC_CS0WCR_NORMAL_WR (0x00000780uL) +#define BSC_CS0WCR_NORMAL_SW (0x00001800uL) +#define BSC_CS0WCR_NORMAL_BAS (0x00100000uL) + +#define BSC_CS1WCR_NORMAL_HW (0x00000003uL) +#define BSC_CS1WCR_NORMAL_WM (0x00000040uL) +#define BSC_CS1WCR_NORMAL_WR (0x00000780uL) +#define BSC_CS1WCR_NORMAL_SW (0x00001800uL) +#define BSC_CS1WCR_NORMAL_WW (0x00070000uL) +#define BSC_CS1WCR_NORMAL_BAS (0x00100000uL) + +#define BSC_CS2WCR_NORMAL_WM (0x00000040uL) +#define BSC_CS2WCR_NORMAL_WR (0x00000780uL) +#define BSC_CS2WCR_NORMAL_BAS (0x00100000uL) + +#define BSC_CS3WCR_NORMAL_WM (0x00000040uL) +#define BSC_CS3WCR_NORMAL_WR (0x00000780uL) +#define BSC_CS3WCR_NORMAL_BAS (0x00100000uL) + +#define BSC_CS4WCR_NORMAL_HW (0x00000003uL) +#define BSC_CS4WCR_NORMAL_WM (0x00000040uL) +#define BSC_CS4WCR_NORMAL_WR (0x00000780uL) +#define BSC_CS4WCR_NORMAL_SW (0x00001800uL) +#define BSC_CS4WCR_NORMAL_WW (0x00070000uL) +#define BSC_CS4WCR_NORMAL_BAS (0x00100000uL) + +#define BSC_CS5WCR_NORMAL_HW (0x00000003uL) +#define BSC_CS5WCR_NORMAL_WM (0x00000040uL) +#define BSC_CS5WCR_NORMAL_WR (0x00000780uL) +#define BSC_CS5WCR_NORMAL_SW (0x00001800uL) +#define BSC_CS5WCR_NORMAL_WW (0x00070000uL) +#define BSC_CS5WCR_NORMAL_MPXWBAS (0x00100000uL) +#define BSC_CS5WCR_NORMAL_SZSEL (0x00200000uL) + +#define BSC_CS0WCR_BROM_ASY_WM (0x00000040uL) +#define BSC_CS0WCR_BROM_ASY_W (0x00000780uL) +#define BSC_CS0WCR_BROM_ASY_BW (0x00030000uL) +#define BSC_CS0WCR_BROM_ASY_BST (0x00300000uL) + +#define BSC_CS4WCR_BROM_ASY_HW (0x00000003uL) +#define BSC_CS4WCR_BROM_ASY_WM (0x00000040uL) +#define BSC_CS4WCR_BROM_ASY_W (0x00000780uL) +#define BSC_CS4WCR_BROM_ASY_SW (0x00001800uL) +#define BSC_CS4WCR_BROM_ASY_BW (0x00030000uL) +#define BSC_CS4WCR_BROM_ASY_BST (0x00300000uL) + +#define BSC_CS2WCR_SDRAM_A2CL (0x00000180uL) + +#define BSC_CS3WCR_SDRAM_WTRC (0x00000003uL) +#define BSC_CS3WCR_SDRAM_TRWL (0x00000018uL) +#define BSC_CS3WCR_SDRAM_A3CL (0x00000180uL) +#define BSC_CS3WCR_SDRAM_WTRCD (0x00000C00uL) +#define BSC_CS3WCR_SDRAM_WTRP (0x00006000uL) + +#define BSC_CS0WCR_BROM_SY_WM (0x00000040uL) +#define BSC_CS0WCR_BROM_SY_W (0x00000780uL) +#define BSC_CS0WCR_BROM_SY_BW (0x00030000uL) + +#define BSC_SDCR_A3COL (0x00000003uL) +#define BSC_SDCR_A3ROW (0x00000018uL) +#define BSC_SDCR_BACTV (0x00000100uL) +#define BSC_SDCR_PDOWN (0x00000200uL) +#define BSC_SDCR_RMODE (0x00000400uL) +#define BSC_SDCR_RFSH (0x00000800uL) +#define BSC_SDCR_DEEP (0x00002000uL) +#define BSC_SDCR_A2COL (0x00030000uL) +#define BSC_SDCR_A2ROW (0x00180000uL) + +#define BSC_RTCSR_RRC (0x00000007uL) +#define BSC_RTCSR_CKS (0x00000038uL) +#define BSC_RTCSR_CMIE (0x00000040uL) +#define BSC_RTCSR_CMF (0x00000080uL) + +#define BSC_RTCNT_D (0xFFFFFFFFuL) + +#define BSC_RTCOR_D (0xFFFFFFFFuL) + +#define BSC_TOSCOR0_D (0x0000FFFFuL) + +#define BSC_TOSCOR1_D (0x0000FFFFuL) + +#define BSC_TOSCOR2_D (0x0000FFFFuL) + +#define BSC_TOSCOR3_D (0x0000FFFFuL) + +#define BSC_TOSCOR4_D (0x0000FFFFuL) + +#define BSC_TOSCOR5_D (0x0000FFFFuL) + +#define BSC_TOSTR_CS0TOSTF (0x00000001uL) +#define BSC_TOSTR_CS1TOSTF (0x00000002uL) +#define BSC_TOSTR_CS2TOSTF (0x00000004uL) +#define BSC_TOSTR_CS3TOSTF (0x00000008uL) +#define BSC_TOSTR_CS4TOSTF (0x00000010uL) +#define BSC_TOSTR_CS5TOSTF (0x00000020uL) + +#define BSC_TOENR_CS0TOEN (0x00000001uL) +#define BSC_TOENR_CS1TOEN (0x00000002uL) +#define BSC_TOENR_CS2TOEN (0x00000004uL) +#define BSC_TOENR_CS3TOEN (0x00000008uL) +#define BSC_TOENR_CS4TOEN (0x00000010uL) +#define BSC_TOENR_CS5TOEN (0x00000020uL) + + +/* ==== Shift values for IO registers ==== */ +#define BSC_CMNCR_HIZCNT_SHIFT (0u) +#define BSC_CMNCR_HIZMEM_SHIFT (1u) +#define BSC_CMNCR_DPRTY_SHIFT (9u) +#define BSC_CMNCR_AL0_SHIFT (24u) +#define BSC_CMNCR_TL0_SHIFT (28u) + +#define BSC_CS0BCR_BSZ_SHIFT (9u) +#define BSC_CS0BCR_TYPE_SHIFT (12u) +#define BSC_CS0BCR_IWRRS_SHIFT (16u) +#define BSC_CS0BCR_IWRRD_SHIFT (19u) +#define BSC_CS0BCR_IWRWS_SHIFT (22u) +#define BSC_CS0BCR_IWRWD_SHIFT (25u) +#define BSC_CS0BCR_IWW_SHIFT (28u) + +#define BSC_CS1BCR_BSZ_SHIFT (9u) +#define BSC_CS1BCR_TYPE_SHIFT (12u) +#define BSC_CS1BCR_IWRRS_SHIFT (16u) +#define BSC_CS1BCR_IWRRD_SHIFT (19u) +#define BSC_CS1BCR_IWRWS_SHIFT (22u) +#define BSC_CS1BCR_IWRWD_SHIFT (25u) +#define BSC_CS1BCR_IWW_SHIFT (28u) + +#define BSC_CS2BCR_BSZ_SHIFT (9u) +#define BSC_CS2BCR_TYPE_SHIFT (12u) +#define BSC_CS2BCR_IWRRS_SHIFT (16u) +#define BSC_CS2BCR_IWRRD_SHIFT (19u) +#define BSC_CS2BCR_IWRWS_SHIFT (22u) +#define BSC_CS2BCR_IWRWD_SHIFT (25u) +#define BSC_CS2BCR_IWW_SHIFT (28u) + +#define BSC_CS3BCR_BSZ_SHIFT (9u) +#define BSC_CS3BCR_TYPE_SHIFT (12u) +#define BSC_CS3BCR_IWRRS_SHIFT (16u) +#define BSC_CS3BCR_IWRRD_SHIFT (19u) +#define BSC_CS3BCR_IWRWS_SHIFT (22u) +#define BSC_CS3BCR_IWRWD_SHIFT (25u) +#define BSC_CS3BCR_IWW_SHIFT (28u) + +#define BSC_CS4BCR_BSZ_SHIFT (9u) +#define BSC_CS4BCR_TYPE_SHIFT (12u) +#define BSC_CS4BCR_IWRRS_SHIFT (16u) +#define BSC_CS4BCR_IWRRD_SHIFT (19u) +#define BSC_CS4BCR_IWRWS_SHIFT (22u) +#define BSC_CS4BCR_IWRWD_SHIFT (25u) +#define BSC_CS4BCR_IWW_SHIFT (28u) + +#define BSC_CS5BCR_BSZ_SHIFT (9u) +#define BSC_CS5BCR_TYPE_SHIFT (12u) +#define BSC_CS5BCR_IWRRS_SHIFT (16u) +#define BSC_CS5BCR_IWRRD_SHIFT (19u) +#define BSC_CS5BCR_IWRWS_SHIFT (22u) +#define BSC_CS5BCR_IWRWD_SHIFT (25u) +#define BSC_CS5BCR_IWW_SHIFT (28u) + +#define BSC_CS0WCR_NORMAL_HW_SHIFT (0u) +#define BSC_CS0WCR_NORMAL_WM_SHIFT (6u) +#define BSC_CS0WCR_NORMAL_WR_SHIFT (7u) +#define BSC_CS0WCR_NORMAL_SW_SHIFT (11u) +#define BSC_CS0WCR_NORMAL_BAS_SHIFT (20u) + +#define BSC_CS1WCR_NORMAL_HW_SHIFT (0u) +#define BSC_CS1WCR_NORMAL_WM_SHIFT (6u) +#define BSC_CS1WCR_NORMAL_WR_SHIFT (7u) +#define BSC_CS1WCR_NORMAL_SW_SHIFT (11u) +#define BSC_CS1WCR_NORMAL_WW_SHIFT (16u) +#define BSC_CS1WCR_NORMAL_BAS_SHIFT (20u) + +#define BSC_CS2WCR_NORMAL_WM_SHIFT (6u) +#define BSC_CS2WCR_NORMAL_WR_SHIFT (7u) +#define BSC_CS2WCR_NORMAL_BAS_SHIFT (20u) + +#define BSC_CS3WCR_NORMAL_WM_SHIFT (6u) +#define BSC_CS3WCR_NORMAL_WR_SHIFT (7u) +#define BSC_CS3WCR_NORMAL_BAS_SHIFT (20u) + +#define BSC_CS4WCR_NORMAL_HW_SHIFT (0u) +#define BSC_CS4WCR_NORMAL_WM_SHIFT (6u) +#define BSC_CS4WCR_NORMAL_WR_SHIFT (7u) +#define BSC_CS4WCR_NORMAL_SW_SHIFT (11u) +#define BSC_CS4WCR_NORMAL_WW_SHIFT (16u) +#define BSC_CS4WCR_NORMAL_BAS_SHIFT (20u) + +#define BSC_CS5WCR_NORMAL_HW_SHIFT (0u) +#define BSC_CS5WCR_NORMAL_WM_SHIFT (6u) +#define BSC_CS5WCR_NORMAL_WR_SHIFT (7u) +#define BSC_CS5WCR_NORMAL_SW_SHIFT (11u) +#define BSC_CS5WCR_NORMAL_WW_SHIFT (16u) +#define BSC_CS5WCR_NORMAL_MPXWBAS_SHIFT (20u) +#define BSC_CS5WCR_NORMAL_SZSEL_SHIFT (21u) + +#define BSC_CS0WCR_BROM_ASY_WM_SHIFT (6u) +#define BSC_CS0WCR_BROM_ASY_W_SHIFT (7u) +#define BSC_CS0WCR_BROM_ASY_BW_SHIFT (16u) +#define BSC_CS0WCR_BROM_ASY_BST_SHIFT (20u) + +#define BSC_CS4WCR_BROM_ASY_HW_SHIFT (0u) +#define BSC_CS4WCR_BROM_ASY_WM_SHIFT (6u) +#define BSC_CS4WCR_BROM_ASY_W_SHIFT (7u) +#define BSC_CS4WCR_BROM_ASY_SW_SHIFT (11u) +#define BSC_CS4WCR_BROM_ASY_BW_SHIFT (16u) +#define BSC_CS4WCR_BROM_ASY_BST_SHIFT (20u) + +#define BSC_CS2WCR_SDRAM_A2CL_SHIFT (7u) + +#define BSC_CS3WCR_SDRAM_WTRC_SHIFT (0u) +#define BSC_CS3WCR_SDRAM_TRWL_SHIFT (3u) +#define BSC_CS3WCR_SDRAM_A3CL_SHIFT (7u) +#define BSC_CS3WCR_SDRAM_WTRCD_SHIFT (10u) +#define BSC_CS3WCR_SDRAM_WTRP_SHIFT (13u) + +#define BSC_CS0WCR_BROM_SY_WM_SHIFT (6u) +#define BSC_CS0WCR_BROM_SY_W_SHIFT (7u) +#define BSC_CS0WCR_BROM_SY_BW_SHIFT (16u) + +#define BSC_SDCR_A3COL_SHIFT (0u) +#define BSC_SDCR_A3ROW_SHIFT (3u) +#define BSC_SDCR_BACTV_SHIFT (8u) +#define BSC_SDCR_PDOWN_SHIFT (9u) +#define BSC_SDCR_RMODE_SHIFT (10u) +#define BSC_SDCR_RFSH_SHIFT (11u) +#define BSC_SDCR_DEEP_SHIFT (13u) +#define BSC_SDCR_A2COL_SHIFT (16u) +#define BSC_SDCR_A2ROW_SHIFT (19u) + +#define BSC_RTCSR_RRC_SHIFT (0u) +#define BSC_RTCSR_CKS_SHIFT (3u) +#define BSC_RTCSR_CMIE_SHIFT (6u) +#define BSC_RTCSR_CMF_SHIFT (7u) + +#define BSC_RTCNT_D_SHIFT (0u) + +#define BSC_RTCOR_D_SHIFT (0u) + +#define BSC_TOSCOR0_D_SHIFT (0u) + +#define BSC_TOSCOR1_D_SHIFT (0u) + +#define BSC_TOSCOR2_D_SHIFT (0u) + +#define BSC_TOSCOR3_D_SHIFT (0u) + +#define BSC_TOSCOR4_D_SHIFT (0u) + +#define BSC_TOSCOR5_D_SHIFT (0u) + +#define BSC_TOSTR_CS0TOSTF_SHIFT (0u) +#define BSC_TOSTR_CS1TOSTF_SHIFT (1u) +#define BSC_TOSTR_CS2TOSTF_SHIFT (2u) +#define BSC_TOSTR_CS3TOSTF_SHIFT (3u) +#define BSC_TOSTR_CS4TOSTF_SHIFT (4u) +#define BSC_TOSTR_CS5TOSTF_SHIFT (5u) + +#define BSC_TOENR_CS0TOEN_SHIFT (0u) +#define BSC_TOENR_CS1TOEN_SHIFT (1u) +#define BSC_TOENR_CS2TOEN_SHIFT (2u) +#define BSC_TOENR_CS3TOEN_SHIFT (3u) +#define BSC_TOENR_CS4TOEN_SHIFT (4u) +#define BSC_TOENR_CS5TOEN_SHIFT (5u) + + +#endif /* BSC_IOBITMASK_H */ + +/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/cpg_iobitmask.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,461 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : cpg_iobitmask.h +* $Rev: 1115 $ +* $Date:: 2014-07-09 15:35:02 +0900#$ +* Description : CPG register define header +*******************************************************************************/ +#ifndef CPG_IOBITMASK_H +#define CPG_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ +#define CPG_FRQCR_IFC (0x0300u) +#define CPG_FRQCR_CKOEN (0x3000u) +#define CPG_FRQCR_CKOEN2 (0x4000u) + +#define CPG_FRQCR2_GFC (0x0003u) + +#define CPG_CPUSTS_ISBUSY (0x10u) + +#define CPG_STBCR1_DEEP (0x40u) +#define CPG_STBCR1_STBY (0x80u) + +#define CPG_STBCR2_MSTP20 (0x01u) +#define CPG_STBCR2_HIZ (0x80u) + +#define CPG_STBREQ1_STBRQ10 (0x01u) +#define CPG_STBREQ1_STBRQ12 (0x04u) +#define CPG_STBREQ1_STBRQ13 (0x08u) +#define CPG_STBREQ1_STBRQ15 (0x20u) + +#define CPG_STBREQ2_STBRQ20 (0x01u) +#define CPG_STBREQ2_STBRQ21 (0x02u) +#define CPG_STBREQ2_STBRQ22 (0x04u) +#define CPG_STBREQ2_STBRQ23 (0x08u) +#define CPG_STBREQ2_STBRQ24 (0x10u) +#define CPG_STBREQ2_STBRQ25 (0x20u) +#define CPG_STBREQ2_STBRQ26 (0x40u) +#define CPG_STBREQ2_STBRQ27 (0x80u) + +#define CPG_STBACK1_STBAK10 (0x01u) +#define CPG_STBACK1_STBAK12 (0x04u) +#define CPG_STBACK1_STBAK13 (0x08u) +#define CPG_STBACK1_STBAK15 (0x20u) + +#define CPG_STBACK2_STBAK20 (0x01u) +#define CPG_STBACK2_STBAK21 (0x02u) +#define CPG_STBACK2_STBAK22 (0x04u) +#define CPG_STBACK2_STBAK23 (0x08u) +#define CPG_STBACK2_STBAK24 (0x10u) +#define CPG_STBACK2_STBAK25 (0x20u) +#define CPG_STBACK2_STBAK26 (0x40u) +#define CPG_STBACK2_STBAK27 (0x80u) + +#define CPG_SYSCR1_VRAME0 (0x01u) +#define CPG_SYSCR1_VRAME1 (0x02u) +#define CPG_SYSCR1_VRAME2 (0x04u) +#define CPG_SYSCR1_VRAME3 (0x08u) +#define CPG_SYSCR1_VRAME4 (0x10u) + +#define CPG_SYSCR2_VRAMWE0 (0x01u) +#define CPG_SYSCR2_VRAMWE1 (0x02u) +#define CPG_SYSCR2_VRAMWE2 (0x04u) +#define CPG_SYSCR2_VRAMWE3 (0x08u) +#define CPG_SYSCR2_VRAMWE4 (0x10u) + +#define CPG_SYSCR3_RRAMWE0 (0x01u) +#define CPG_SYSCR3_RRAMWE1 (0x02u) +#define CPG_SYSCR3_RRAMWE2 (0x04u) +#define CPG_SYSCR3_RRAMWE3 (0x08u) + +#define CPG_STBCR3_MSTP30 (0x01u) +#define CPG_STBCR3_MSTP31 (0x02u) +#define CPG_STBCR3_MSTP32 (0x04u) +#define CPG_STBCR3_MSTP33 (0x08u) +#define CPG_STBCR3_MSTP34 (0x10u) +#define CPG_STBCR3_MSTP35 (0x20u) +#define CPG_STBCR3_MSTP36 (0x40u) +#define CPG_STBCR3_MSTP37 (0x80u) + +#define CPG_STBCR4_MSTP40 (0x01u) +#define CPG_STBCR4_MSTP41 (0x02u) +#define CPG_STBCR4_MSTP42 (0x04u) +#define CPG_STBCR4_MSTP43 (0x08u) +#define CPG_STBCR4_MSTP44 (0x10u) +#define CPG_STBCR4_MSTP45 (0x20u) +#define CPG_STBCR4_MSTP46 (0x40u) +#define CPG_STBCR4_MSTP47 (0x80u) + +#define CPG_STBCR5_MSTP50 (0x01u) +#define CPG_STBCR5_MSTP51 (0x02u) +#define CPG_STBCR5_MSTP52 (0x04u) +#define CPG_STBCR5_MSTP53 (0x08u) +#define CPG_STBCR5_MSTP54 (0x10u) +#define CPG_STBCR5_MSTP55 (0x20u) +#define CPG_STBCR5_MSTP56 (0x40u) +#define CPG_STBCR5_MSTP57 (0x80u) + +#define CPG_STBCR6_MSTP60 (0x01u) +#define CPG_STBCR6_MSTP61 (0x02u) +#define CPG_STBCR6_MSTP62 (0x04u) +#define CPG_STBCR6_MSTP63 (0x08u) +#define CPG_STBCR6_MSTP64 (0x10u) +#define CPG_STBCR6_MSTP65 (0x20u) +#define CPG_STBCR6_MSTP66 (0x40u) +#define CPG_STBCR6_MSTP67 (0x80u) + +#define CPG_STBCR7_MSTP70 (0x01u) +#define CPG_STBCR7_MSTP71 (0x02u) +#define CPG_STBCR7_MSTP73 (0x08u) +#define CPG_STBCR7_MSTP74 (0x10u) +#define CPG_STBCR7_MSTP76 (0x40u) +#define CPG_STBCR7_MSTP77 (0x80u) + +#define CPG_STBCR8_MSTP81 (0x02u) +#define CPG_STBCR8_MSTP82 (0x04u) +#define CPG_STBCR8_MSTP83 (0x08u) +#define CPG_STBCR8_MSTP84 (0x10u) +#define CPG_STBCR8_MSTP85 (0x20u) +#define CPG_STBCR8_MSTP86 (0x40u) +#define CPG_STBCR8_MSTP87 (0x80u) + +#define CPG_STBCR9_MSTP90 (0x01u) +#define CPG_STBCR9_MSTP91 (0x02u) +#define CPG_STBCR9_MSTP92 (0x04u) +#define CPG_STBCR9_MSTP93 (0x08u) +#define CPG_STBCR9_MSTP94 (0x10u) +#define CPG_STBCR9_MSTP95 (0x20u) +#define CPG_STBCR9_MSTP96 (0x40u) +#define CPG_STBCR9_MSTP97 (0x80u) + +#define CPG_STBCR10_MSTP100 (0x01u) +#define CPG_STBCR10_MSTP101 (0x02u) +#define CPG_STBCR10_MSTP102 (0x04u) +#define CPG_STBCR10_MSTP103 (0x08u) +#define CPG_STBCR10_MSTP104 (0x10u) +#define CPG_STBCR10_MSTP105 (0x20u) +#define CPG_STBCR10_MSTP106 (0x40u) +#define CPG_STBCR10_MSTP107 (0x80u) + +#define CPG_STBCR11_MSTP110 (0x01u) +#define CPG_STBCR11_MSTP111 (0x02u) +#define CPG_STBCR11_MSTP112 (0x04u) +#define CPG_STBCR11_MSTP113 (0x08u) +#define CPG_STBCR11_MSTP114 (0x10u) +#define CPG_STBCR11_MSTP115 (0x20u) + +#define CPG_STBCR12_MSTP120 (0x01u) +#define CPG_STBCR12_MSTP121 (0x02u) +#define CPG_STBCR12_MSTP122 (0x04u) +#define CPG_STBCR12_MSTP123 (0x08u) + +#define CPG_STBCR13_MSTP131 (0x02u) +#define CPG_STBCR13_MSTP132 (0x04u) + +#define CPG_SWRSTCR1_SRST11 (0x02u) +#define CPG_SWRSTCR1_SRST12 (0x04u) +#define CPG_SWRSTCR1_SRST13 (0x08u) +#define CPG_SWRSTCR1_SRST14 (0x10u) +#define CPG_SWRSTCR1_SRST15 (0x20u) +#define CPG_SWRSTCR1_SRST16 (0x40u) +#define CPG_SWRSTCR1_AXTALE (0x80u) + +#define CPG_SWRSTCR2_SRST21 (0x02u) + +#define CPG_SWRSTCR3_SRST32 (0x04u) + +#define CPG_RRAMKP_RRAMKP0 (0x01u) +#define CPG_RRAMKP_RRAMKP1 (0x02u) +#define CPG_RRAMKP_RRAMKP2 (0x04u) +#define CPG_RRAMKP_RRAMKP3 (0x08u) + +#define CPG_DSCTR_RAMBOOT (0x40u) +#define CPG_DSCTR_EBUSKEEPE (0x80u) + +#define CPG_DSSSR_P8_2 (0x0001u) +#define CPG_DSSSR_P9_1 (0x0002u) +#define CPG_DSSSR_P2_15 (0x0004u) +#define CPG_DSSSR_P7_8 (0x0008u) +#define CPG_DSSSR_P5_9 (0x0010u) +#define CPG_DSSSR_P6_4 (0x0020u) +#define CPG_DSSSR_RTCAR (0x0040u) +#define CPG_DSSSR_NMI (0x0100u) +#define CPG_DSSSR_P3_3 (0x0200u) +#define CPG_DSSSR_P8_7 (0x0400u) +#define CPG_DSSSR_P2_12 (0x0800u) +#define CPG_DSSSR_P3_1 (0x1000u) +#define CPG_DSSSR_P3_9 (0x2000u) +#define CPG_DSSSR_P6_2 (0x4000u) + +#define CPG_DSESR_P8_2E (0x0001u) +#define CPG_DSESR_P9_1E (0x0002u) +#define CPG_DSESR_P2_15E (0x0004u) +#define CPG_DSESR_P7_8E (0x0008u) +#define CPG_DSESR_P5_9E (0x0010u) +#define CPG_DSESR_P6_4E (0x0020u) +#define CPG_DSESR_NMIE (0x0100u) +#define CPG_DSESR_P3_3E (0x0200u) +#define CPG_DSESR_P8_7E (0x0400u) +#define CPG_DSESR_P2_12E (0x0800u) +#define CPG_DSESR_P3_1E (0x1000u) +#define CPG_DSESR_P3_9E (0x2000u) +#define CPG_DSESR_P6_2E (0x4000u) + +#define CPG_DSFR_P8_2F (0x0001u) +#define CPG_DSFR_P9_1F (0x0002u) +#define CPG_DSFR_P2_15F (0x0004u) +#define CPG_DSFR_P7_8F (0x0008u) +#define CPG_DSFR_P5_9F (0x0010u) +#define CPG_DSFR_P6_4F (0x0020u) +#define CPG_DSFR_RTCARF (0x0040u) +#define CPG_DSFR_NMIF (0x0100u) +#define CPG_DSFR_P3_3F (0x0200u) +#define CPG_DSFR_P8_7F (0x0400u) +#define CPG_DSFR_P2_12F (0x0800u) +#define CPG_DSFR_P3_1F (0x1000u) +#define CPG_DSFR_P3_9F (0x2000u) +#define CPG_DSFR_P6_2F (0x4000u) +#define CPG_DSFR_IOKEEP (0x8000u) + +#define CPG_XTALCTR_GAIN0 (0x01u) +#define CPG_XTALCTR_GAIN1 (0x02u) + + +/* ==== Shift values for IO registers ==== */ +#define CPG_FRQCR_IFC_SHIFT (8u) +#define CPG_FRQCR_CKOEN_SHIFT (12u) +#define CPG_FRQCR_CKOEN2_SHIFT (14u) + +#define CPG_FRQCR2_GFC_SHIFT (0u) + +#define CPG_CPUSTS_ISBUSY_SHIFT (4u) + +#define CPG_STBCR1_DEEP_SHIFT (6u) +#define CPG_STBCR1_STBY_SHIFT (7u) + +#define CPG_STBCR2_MSTP20_SHIFT (0u) +#define CPG_STBCR2_HIZ_SHIFT (7u) + +#define CPG_STBREQ1_STBRQ10_SHIFT (0u) +#define CPG_STBREQ1_STBRQ12_SHIFT (2u) +#define CPG_STBREQ1_STBRQ13_SHIFT (3u) +#define CPG_STBREQ1_STBRQ15_SHIFT (5u) + +#define CPG_STBREQ2_STBRQ20_SHIFT (0u) +#define CPG_STBREQ2_STBRQ21_SHIFT (1u) +#define CPG_STBREQ2_STBRQ22_SHIFT (2u) +#define CPG_STBREQ2_STBRQ23_SHIFT (3u) +#define CPG_STBREQ2_STBRQ24_SHIFT (4u) +#define CPG_STBREQ2_STBRQ25_SHIFT (5u) +#define CPG_STBREQ2_STBRQ26_SHIFT (6u) +#define CPG_STBREQ2_STBRQ27_SHIFT (7u) + +#define CPG_STBACK1_STBAK10_SHIFT (0u) +#define CPG_STBACK1_STBAK12_SHIFT (2u) +#define CPG_STBACK1_STBAK13_SHIFT (3u) +#define CPG_STBACK1_STBAK15_SHIFT (5u) + +#define CPG_STBACK2_STBAK20_SHIFT (0u) +#define CPG_STBACK2_STBAK21_SHIFT (1u) +#define CPG_STBACK2_STBAK22_SHIFT (2u) +#define CPG_STBACK2_STBAK23_SHIFT (3u) +#define CPG_STBACK2_STBAK24_SHIFT (4u) +#define CPG_STBACK2_STBAK25_SHIFT (5u) +#define CPG_STBACK2_STBAK26_SHIFT (6u) +#define CPG_STBACK2_STBAK27_SHIFT (7u) + +#define CPG_SYSCR1_VRAME0_SHIFT (0u) +#define CPG_SYSCR1_VRAME1_SHIFT (1u) +#define CPG_SYSCR1_VRAME2_SHIFT (2u) +#define CPG_SYSCR1_VRAME3_SHIFT (3u) +#define CPG_SYSCR1_VRAME4_SHIFT (4u) + +#define CPG_SYSCR2_VRAMWE0_SHIFT (0u) +#define CPG_SYSCR2_VRAMWE1_SHIFT (1u) +#define CPG_SYSCR2_VRAMWE2_SHIFT (2u) +#define CPG_SYSCR2_VRAMWE3_SHIFT (3u) +#define CPG_SYSCR2_VRAMWE4_SHIFT (4u) + +#define CPG_SYSCR3_RRAMWE0_SHIFT (0u) +#define CPG_SYSCR3_RRAMWE1_SHIFT (1u) +#define CPG_SYSCR3_RRAMWE2_SHIFT (2u) +#define CPG_SYSCR3_RRAMWE3_SHIFT (3u) + +#define CPG_STBCR3_MSTP30_SHIFT (0u) +#define CPG_STBCR3_MSTP31_SHIFT (1u) +#define CPG_STBCR3_MSTP32_SHIFT (2u) +#define CPG_STBCR3_MSTP33_SHIFT (3u) +#define CPG_STBCR3_MSTP34_SHIFT (4u) +#define CPG_STBCR3_MSTP35_SHIFT (5u) +#define CPG_STBCR3_MSTP36_SHIFT (6u) +#define CPG_STBCR3_MSTP37_SHIFT (7u) + +#define CPG_STBCR4_MSTP40_SHIFT (0u) +#define CPG_STBCR4_MSTP41_SHIFT (1u) +#define CPG_STBCR4_MSTP42_SHIFT (2u) +#define CPG_STBCR4_MSTP43_SHIFT (3u) +#define CPG_STBCR4_MSTP44_SHIFT (4u) +#define CPG_STBCR4_MSTP45_SHIFT (5u) +#define CPG_STBCR4_MSTP46_SHIFT (6u) +#define CPG_STBCR4_MSTP47_SHIFT (7u) + +#define CPG_STBCR5_MSTP50_SHIFT (0u) +#define CPG_STBCR5_MSTP51_SHIFT (1u) +#define CPG_STBCR5_MSTP52_SHIFT (2u) +#define CPG_STBCR5_MSTP53_SHIFT (3u) +#define CPG_STBCR5_MSTP54_SHIFT (4u) +#define CPG_STBCR5_MSTP55_SHIFT (5u) +#define CPG_STBCR5_MSTP56_SHIFT (6u) +#define CPG_STBCR5_MSTP57_SHIFT (7u) + +#define CPG_STBCR6_MSTP60_SHIFT (0u) +#define CPG_STBCR6_MSTP61_SHIFT (1u) +#define CPG_STBCR6_MSTP62_SHIFT (2u) +#define CPG_STBCR6_MSTP63_SHIFT (3u) +#define CPG_STBCR6_MSTP64_SHIFT (4u) +#define CPG_STBCR6_MSTP65_SHIFT (5u) +#define CPG_STBCR6_MSTP66_SHIFT (6u) +#define CPG_STBCR6_MSTP67_SHIFT (7u) + +#define CPG_STBCR7_MSTP70_SHIFT (0u) +#define CPG_STBCR7_MSTP71_SHIFT (1u) +#define CPG_STBCR7_MSTP73_SHIFT (3u) +#define CPG_STBCR7_MSTP74_SHIFT (4u) +#define CPG_STBCR7_MSTP76_SHIFT (6u) +#define CPG_STBCR7_MSTP77_SHIFT (7u) + +#define CPG_STBCR8_MSTP81_SHIFT (1u) +#define CPG_STBCR8_MSTP82_SHIFT (2u) +#define CPG_STBCR8_MSTP83_SHIFT (3u) +#define CPG_STBCR8_MSTP84_SHIFT (4u) +#define CPG_STBCR8_MSTP85_SHIFT (5u) +#define CPG_STBCR8_MSTP86_SHIFT (6u) +#define CPG_STBCR8_MSTP87_SHIFT (7u) + +#define CPG_STBCR9_MSTP90_SHIFT (0u) +#define CPG_STBCR9_MSTP91_SHIFT (1u) +#define CPG_STBCR9_MSTP92_SHIFT (2u) +#define CPG_STBCR9_MSTP93_SHIFT (3u) +#define CPG_STBCR9_MSTP94_SHIFT (4u) +#define CPG_STBCR9_MSTP95_SHIFT (5u) +#define CPG_STBCR9_MSTP96_SHIFT (6u) +#define CPG_STBCR9_MSTP97_SHIFT (7u) + +#define CPG_STBCR10_MSTP100_SHIFT (0u) +#define CPG_STBCR10_MSTP101_SHIFT (1u) +#define CPG_STBCR10_MSTP102_SHIFT (2u) +#define CPG_STBCR10_MSTP103_SHIFT (3u) +#define CPG_STBCR10_MSTP104_SHIFT (4u) +#define CPG_STBCR10_MSTP105_SHIFT (5u) +#define CPG_STBCR10_MSTP106_SHIFT (6u) +#define CPG_STBCR10_MSTP107_SHIFT (7u) + +#define CPG_STBCR11_MSTP110_SHIFT (0u) +#define CPG_STBCR11_MSTP111_SHIFT (1u) +#define CPG_STBCR11_MSTP112_SHIFT (2u) +#define CPG_STBCR11_MSTP113_SHIFT (3u) +#define CPG_STBCR11_MSTP114_SHIFT (4u) +#define CPG_STBCR11_MSTP115_SHIFT (5u) + +#define CPG_STBCR12_MSTP120_SHIFT (0u) +#define CPG_STBCR12_MSTP121_SHIFT (1u) +#define CPG_STBCR12_MSTP122_SHIFT (2u) +#define CPG_STBCR12_MSTP123_SHIFT (3u) + +#define CPG_STBCR13_MSTP131_SHIFT (1u) +#define CPG_STBCR13_MSTP132_SHIFT (2u) + +#define CPG_SWRSTCR1_SRST11_SHIFT (1u) +#define CPG_SWRSTCR1_SRST12_SHIFT (2u) +#define CPG_SWRSTCR1_SRST13_SHIFT (3u) +#define CPG_SWRSTCR1_SRST14_SHIFT (4u) +#define CPG_SWRSTCR1_SRST15_SHIFT (5u) +#define CPG_SWRSTCR1_SRST16_SHIFT (6u) +#define CPG_SWRSTCR1_AXTALE_SHIFT (7u) + +#define CPG_SWRSTCR2_SRST21_SHIFT (1u) + +#define CPG_SWRSTCR3_SRST32_SHIFT (2u) + +#define CPG_RRAMKP_RRAMKP0_SHIFT (0u) +#define CPG_RRAMKP_RRAMKP1_SHIFT (1u) +#define CPG_RRAMKP_RRAMKP2_SHIFT (2u) +#define CPG_RRAMKP_RRAMKP3_SHIFT (3u) + +#define CPG_DSCTR_RAMBOOT_SHIFT (6u) +#define CPG_DSCTR_EBUSKEEPE_SHIFT (7u) + +#define CPG_DSSSR_P8_2_SHIFT (0u) +#define CPG_DSSSR_P9_1_SHIFT (1u) +#define CPG_DSSSR_P2_15_SHIFT (2u) +#define CPG_DSSSR_P7_8_SHIFT (3u) +#define CPG_DSSSR_P5_9_SHIFT (4u) +#define CPG_DSSSR_P6_4_SHIFT (5u) +#define CPG_DSSSR_RTCAR_SHIFT (6u) +#define CPG_DSSSR_NMI_SHIFT (8u) +#define CPG_DSSSR_P3_3_SHIFT (9u) +#define CPG_DSSSR_P8_7_SHIFT (10u) +#define CPG_DSSSR_P2_12_SHIFT (11u) +#define CPG_DSSSR_P3_1_SHIFT (12u) +#define CPG_DSSSR_P3_9_SHIFT (13u) +#define CPG_DSSSR_P6_2_SHIFT (14u) + +#define CPG_DSESR_P8_2E_SHIFT (0u) +#define CPG_DSESR_P9_1E_SHIFT (1u) +#define CPG_DSESR_P2_15E_SHIFT (2u) +#define CPG_DSESR_P7_8E_SHIFT (3u) +#define CPG_DSESR_P5_9E_SHIFT (4u) +#define CPG_DSESR_P6_4E_SHIFT (5u) +#define CPG_DSESR_NMIE_SHIFT (8u) +#define CPG_DSESR_P3_3E_SHIFT (9u) +#define CPG_DSESR_P8_7E_SHIFT (10u) +#define CPG_DSESR_P2_12E_SHIFT (11u) +#define CPG_DSESR_P3_1E_SHIFT (12u) +#define CPG_DSESR_P3_9E_SHIFT (13u) +#define CPG_DSESR_P6_2E_SHIFT (14u) + +#define CPG_DSFR_P8_2F_SHIFT (0u) +#define CPG_DSFR_P9_1F_SHIFT (1u) +#define CPG_DSFR_P2_15F_SHIFT (2u) +#define CPG_DSFR_P7_8F_SHIFT (3u) +#define CPG_DSFR_P5_9F_SHIFT (4u) +#define CPG_DSFR_P6_4F_SHIFT (5u) +#define CPG_DSFR_RTCARF_SHIFT (6u) +#define CPG_DSFR_NMIF_SHIFT (8u) +#define CPG_DSFR_P3_3F_SHIFT (9u) +#define CPG_DSFR_P8_7F_SHIFT (10u) +#define CPG_DSFR_P2_12F_SHIFT (11u) +#define CPG_DSFR_P3_1F_SHIFT (12u) +#define CPG_DSFR_P3_9F_SHIFT (13u) +#define CPG_DSFR_P6_2F_SHIFT (14u) +#define CPG_DSFR_IOKEEP_SHIFT (15u) + +#define CPG_XTALCTR_GAIN0_SHIFT (0u) +#define CPG_XTALCTR_GAIN1_SHIFT (1u) + + +#endif /* CPG_IOBITMASK_H */ + +/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/dmac_iobitmask.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,2675 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : dmac_iobitmask.h +* $Rev: 1114 $ +* $Date:: 2014-07-09 14:56:39 +0900#$ +* Description : DMAC register define header +*******************************************************************************/ +#ifndef DMAC_IOBITMASK_H +#define DMAC_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ +/* ---- DMAC0 ---- */ +#define DMAC0_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC0_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC0_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC0_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC0_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC0_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC0_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC0_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC0_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC0_CHSTAT_n_EN (0x00000001uL) +#define DMAC0_CHSTAT_n_RQST (0x00000002uL) +#define DMAC0_CHSTAT_n_TACT (0x00000004uL) +#define DMAC0_CHSTAT_n_SUS (0x00000008uL) +#define DMAC0_CHSTAT_n_ER (0x00000010uL) +#define DMAC0_CHSTAT_n_END (0x00000020uL) +#define DMAC0_CHSTAT_n_TC (0x00000040uL) +#define DMAC0_CHSTAT_n_SR (0x00000080uL) +#define DMAC0_CHSTAT_n_DL (0x00000100uL) +#define DMAC0_CHSTAT_n_DW (0x00000200uL) +#define DMAC0_CHSTAT_n_DER (0x00000400uL) +#define DMAC0_CHSTAT_n_MODE (0x00000800uL) +#define DMAC0_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC0_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC0_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC0_CHCTRL_n_STG (0x00000004uL) +#define DMAC0_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC0_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC0_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC0_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC0_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC0_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC0_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC0_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC0_CHCFG_n_SEL (0x00000007uL) +#define DMAC0_CHCFG_n_REQD (0x00000008uL) +#define DMAC0_CHCFG_n_LOEN (0x00000010uL) +#define DMAC0_CHCFG_n_HIEN (0x00000020uL) +#define DMAC0_CHCFG_n_LVL (0x00000040uL) +#define DMAC0_CHCFG_n_AM (0x00000700uL) +#define DMAC0_CHCFG_n_SDS (0x0000F000uL) +#define DMAC0_CHCFG_n_DDS (0x000F0000uL) +#define DMAC0_CHCFG_n_SAD (0x00100000uL) +#define DMAC0_CHCFG_n_DAD (0x00200000uL) +#define DMAC0_CHCFG_n_TM (0x00400000uL) +#define DMAC0_CHCFG_n_DEM (0x01000000uL) +#define DMAC0_CHCFG_n_TCM (0x02000000uL) +#define DMAC0_CHCFG_n_SBE (0x08000000uL) +#define DMAC0_CHCFG_n_RSEL (0x10000000uL) +#define DMAC0_CHCFG_n_RSW (0x20000000uL) +#define DMAC0_CHCFG_n_REN (0x40000000uL) +#define DMAC0_CHCFG_n_DMS (0x80000000uL) + +#define DMAC0_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC0_CHEXT_n_SCA (0x000000F0uL) +#define DMAC0_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC0_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC0_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC1 ---- */ +#define DMAC1_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC1_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC1_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC1_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC1_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC1_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC1_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC1_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC1_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC1_CHSTAT_n_EN (0x00000001uL) +#define DMAC1_CHSTAT_n_RQST (0x00000002uL) +#define DMAC1_CHSTAT_n_TACT (0x00000004uL) +#define DMAC1_CHSTAT_n_SUS (0x00000008uL) +#define DMAC1_CHSTAT_n_ER (0x00000010uL) +#define DMAC1_CHSTAT_n_END (0x00000020uL) +#define DMAC1_CHSTAT_n_TC (0x00000040uL) +#define DMAC1_CHSTAT_n_SR (0x00000080uL) +#define DMAC1_CHSTAT_n_DL (0x00000100uL) +#define DMAC1_CHSTAT_n_DW (0x00000200uL) +#define DMAC1_CHSTAT_n_DER (0x00000400uL) +#define DMAC1_CHSTAT_n_MODE (0x00000800uL) +#define DMAC1_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC1_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC1_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC1_CHCTRL_n_STG (0x00000004uL) +#define DMAC1_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC1_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC1_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC1_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC1_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC1_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC1_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC1_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC1_CHCFG_n_SEL (0x00000007uL) +#define DMAC1_CHCFG_n_REQD (0x00000008uL) +#define DMAC1_CHCFG_n_LOEN (0x00000010uL) +#define DMAC1_CHCFG_n_HIEN (0x00000020uL) +#define DMAC1_CHCFG_n_LVL (0x00000040uL) +#define DMAC1_CHCFG_n_AM (0x00000700uL) +#define DMAC1_CHCFG_n_SDS (0x0000F000uL) +#define DMAC1_CHCFG_n_DDS (0x000F0000uL) +#define DMAC1_CHCFG_n_SAD (0x00100000uL) +#define DMAC1_CHCFG_n_DAD (0x00200000uL) +#define DMAC1_CHCFG_n_TM (0x00400000uL) +#define DMAC1_CHCFG_n_DEM (0x01000000uL) +#define DMAC1_CHCFG_n_TCM (0x02000000uL) +#define DMAC1_CHCFG_n_SBE (0x08000000uL) +#define DMAC1_CHCFG_n_RSEL (0x10000000uL) +#define DMAC1_CHCFG_n_RSW (0x20000000uL) +#define DMAC1_CHCFG_n_REN (0x40000000uL) +#define DMAC1_CHCFG_n_DMS (0x80000000uL) + +#define DMAC1_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC1_CHEXT_n_SCA (0x000000F0uL) +#define DMAC1_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC1_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC1_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC2 ---- */ +#define DMAC2_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC2_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC2_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC2_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC2_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC2_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC2_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC2_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC2_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC2_CHSTAT_n_EN (0x00000001uL) +#define DMAC2_CHSTAT_n_RQST (0x00000002uL) +#define DMAC2_CHSTAT_n_TACT (0x00000004uL) +#define DMAC2_CHSTAT_n_SUS (0x00000008uL) +#define DMAC2_CHSTAT_n_ER (0x00000010uL) +#define DMAC2_CHSTAT_n_END (0x00000020uL) +#define DMAC2_CHSTAT_n_TC (0x00000040uL) +#define DMAC2_CHSTAT_n_SR (0x00000080uL) +#define DMAC2_CHSTAT_n_DL (0x00000100uL) +#define DMAC2_CHSTAT_n_DW (0x00000200uL) +#define DMAC2_CHSTAT_n_DER (0x00000400uL) +#define DMAC2_CHSTAT_n_MODE (0x00000800uL) +#define DMAC2_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC2_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC2_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC2_CHCTRL_n_STG (0x00000004uL) +#define DMAC2_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC2_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC2_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC2_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC2_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC2_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC2_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC2_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC2_CHCFG_n_SEL (0x00000007uL) +#define DMAC2_CHCFG_n_REQD (0x00000008uL) +#define DMAC2_CHCFG_n_LOEN (0x00000010uL) +#define DMAC2_CHCFG_n_HIEN (0x00000020uL) +#define DMAC2_CHCFG_n_LVL (0x00000040uL) +#define DMAC2_CHCFG_n_AM (0x00000700uL) +#define DMAC2_CHCFG_n_SDS (0x0000F000uL) +#define DMAC2_CHCFG_n_DDS (0x000F0000uL) +#define DMAC2_CHCFG_n_SAD (0x00100000uL) +#define DMAC2_CHCFG_n_DAD (0x00200000uL) +#define DMAC2_CHCFG_n_TM (0x00400000uL) +#define DMAC2_CHCFG_n_DEM (0x01000000uL) +#define DMAC2_CHCFG_n_TCM (0x02000000uL) +#define DMAC2_CHCFG_n_SBE (0x08000000uL) +#define DMAC2_CHCFG_n_RSEL (0x10000000uL) +#define DMAC2_CHCFG_n_RSW (0x20000000uL) +#define DMAC2_CHCFG_n_REN (0x40000000uL) +#define DMAC2_CHCFG_n_DMS (0x80000000uL) + +#define DMAC2_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC2_CHEXT_n_SCA (0x000000F0uL) +#define DMAC2_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC2_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC2_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC3 ---- */ +#define DMAC3_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC3_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC3_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC3_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC3_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC3_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC3_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC3_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC3_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC3_CHSTAT_n_EN (0x00000001uL) +#define DMAC3_CHSTAT_n_RQST (0x00000002uL) +#define DMAC3_CHSTAT_n_TACT (0x00000004uL) +#define DMAC3_CHSTAT_n_SUS (0x00000008uL) +#define DMAC3_CHSTAT_n_ER (0x00000010uL) +#define DMAC3_CHSTAT_n_END (0x00000020uL) +#define DMAC3_CHSTAT_n_TC (0x00000040uL) +#define DMAC3_CHSTAT_n_SR (0x00000080uL) +#define DMAC3_CHSTAT_n_DL (0x00000100uL) +#define DMAC3_CHSTAT_n_DW (0x00000200uL) +#define DMAC3_CHSTAT_n_DER (0x00000400uL) +#define DMAC3_CHSTAT_n_MODE (0x00000800uL) +#define DMAC3_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC3_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC3_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC3_CHCTRL_n_STG (0x00000004uL) +#define DMAC3_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC3_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC3_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC3_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC3_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC3_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC3_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC3_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC3_CHCFG_n_SEL (0x00000007uL) +#define DMAC3_CHCFG_n_REQD (0x00000008uL) +#define DMAC3_CHCFG_n_LOEN (0x00000010uL) +#define DMAC3_CHCFG_n_HIEN (0x00000020uL) +#define DMAC3_CHCFG_n_LVL (0x00000040uL) +#define DMAC3_CHCFG_n_AM (0x00000700uL) +#define DMAC3_CHCFG_n_SDS (0x0000F000uL) +#define DMAC3_CHCFG_n_DDS (0x000F0000uL) +#define DMAC3_CHCFG_n_SAD (0x00100000uL) +#define DMAC3_CHCFG_n_DAD (0x00200000uL) +#define DMAC3_CHCFG_n_TM (0x00400000uL) +#define DMAC3_CHCFG_n_DEM (0x01000000uL) +#define DMAC3_CHCFG_n_TCM (0x02000000uL) +#define DMAC3_CHCFG_n_SBE (0x08000000uL) +#define DMAC3_CHCFG_n_RSEL (0x10000000uL) +#define DMAC3_CHCFG_n_RSW (0x20000000uL) +#define DMAC3_CHCFG_n_REN (0x40000000uL) +#define DMAC3_CHCFG_n_DMS (0x80000000uL) + +#define DMAC3_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC3_CHEXT_n_SCA (0x000000F0uL) +#define DMAC3_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC3_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC3_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC4 ---- */ +#define DMAC4_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC4_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC4_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC4_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC4_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC4_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC4_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC4_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC4_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC4_CHSTAT_n_EN (0x00000001uL) +#define DMAC4_CHSTAT_n_RQST (0x00000002uL) +#define DMAC4_CHSTAT_n_TACT (0x00000004uL) +#define DMAC4_CHSTAT_n_SUS (0x00000008uL) +#define DMAC4_CHSTAT_n_ER (0x00000010uL) +#define DMAC4_CHSTAT_n_END (0x00000020uL) +#define DMAC4_CHSTAT_n_TC (0x00000040uL) +#define DMAC4_CHSTAT_n_SR (0x00000080uL) +#define DMAC4_CHSTAT_n_DL (0x00000100uL) +#define DMAC4_CHSTAT_n_DW (0x00000200uL) +#define DMAC4_CHSTAT_n_DER (0x00000400uL) +#define DMAC4_CHSTAT_n_MODE (0x00000800uL) +#define DMAC4_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC4_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC4_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC4_CHCTRL_n_STG (0x00000004uL) +#define DMAC4_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC4_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC4_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC4_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC4_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC4_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC4_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC4_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC4_CHCFG_n_SEL (0x00000007uL) +#define DMAC4_CHCFG_n_REQD (0x00000008uL) +#define DMAC4_CHCFG_n_LOEN (0x00000010uL) +#define DMAC4_CHCFG_n_HIEN (0x00000020uL) +#define DMAC4_CHCFG_n_LVL (0x00000040uL) +#define DMAC4_CHCFG_n_AM (0x00000700uL) +#define DMAC4_CHCFG_n_SDS (0x0000F000uL) +#define DMAC4_CHCFG_n_DDS (0x000F0000uL) +#define DMAC4_CHCFG_n_SAD (0x00100000uL) +#define DMAC4_CHCFG_n_DAD (0x00200000uL) +#define DMAC4_CHCFG_n_TM (0x00400000uL) +#define DMAC4_CHCFG_n_DEM (0x01000000uL) +#define DMAC4_CHCFG_n_TCM (0x02000000uL) +#define DMAC4_CHCFG_n_SBE (0x08000000uL) +#define DMAC4_CHCFG_n_RSEL (0x10000000uL) +#define DMAC4_CHCFG_n_RSW (0x20000000uL) +#define DMAC4_CHCFG_n_REN (0x40000000uL) +#define DMAC4_CHCFG_n_DMS (0x80000000uL) + +#define DMAC4_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC4_CHEXT_n_SCA (0x000000F0uL) +#define DMAC4_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC4_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC4_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC5 ---- */ +#define DMAC5_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC5_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC5_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC5_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC5_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC5_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC5_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC5_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC5_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC5_CHSTAT_n_EN (0x00000001uL) +#define DMAC5_CHSTAT_n_RQST (0x00000002uL) +#define DMAC5_CHSTAT_n_TACT (0x00000004uL) +#define DMAC5_CHSTAT_n_SUS (0x00000008uL) +#define DMAC5_CHSTAT_n_ER (0x00000010uL) +#define DMAC5_CHSTAT_n_END (0x00000020uL) +#define DMAC5_CHSTAT_n_TC (0x00000040uL) +#define DMAC5_CHSTAT_n_SR (0x00000080uL) +#define DMAC5_CHSTAT_n_DL (0x00000100uL) +#define DMAC5_CHSTAT_n_DW (0x00000200uL) +#define DMAC5_CHSTAT_n_DER (0x00000400uL) +#define DMAC5_CHSTAT_n_MODE (0x00000800uL) +#define DMAC5_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC5_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC5_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC5_CHCTRL_n_STG (0x00000004uL) +#define DMAC5_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC5_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC5_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC5_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC5_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC5_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC5_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC5_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC5_CHCFG_n_SEL (0x00000007uL) +#define DMAC5_CHCFG_n_REQD (0x00000008uL) +#define DMAC5_CHCFG_n_LOEN (0x00000010uL) +#define DMAC5_CHCFG_n_HIEN (0x00000020uL) +#define DMAC5_CHCFG_n_LVL (0x00000040uL) +#define DMAC5_CHCFG_n_AM (0x00000700uL) +#define DMAC5_CHCFG_n_SDS (0x0000F000uL) +#define DMAC5_CHCFG_n_DDS (0x000F0000uL) +#define DMAC5_CHCFG_n_SAD (0x00100000uL) +#define DMAC5_CHCFG_n_DAD (0x00200000uL) +#define DMAC5_CHCFG_n_TM (0x00400000uL) +#define DMAC5_CHCFG_n_DEM (0x01000000uL) +#define DMAC5_CHCFG_n_TCM (0x02000000uL) +#define DMAC5_CHCFG_n_SBE (0x08000000uL) +#define DMAC5_CHCFG_n_RSEL (0x10000000uL) +#define DMAC5_CHCFG_n_RSW (0x20000000uL) +#define DMAC5_CHCFG_n_REN (0x40000000uL) +#define DMAC5_CHCFG_n_DMS (0x80000000uL) + +#define DMAC5_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC5_CHEXT_n_SCA (0x000000F0uL) +#define DMAC5_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC5_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC5_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC6 ---- */ +#define DMAC6_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC6_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC6_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC6_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC6_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC6_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC6_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC6_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC6_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC6_CHSTAT_n_EN (0x00000001uL) +#define DMAC6_CHSTAT_n_RQST (0x00000002uL) +#define DMAC6_CHSTAT_n_TACT (0x00000004uL) +#define DMAC6_CHSTAT_n_SUS (0x00000008uL) +#define DMAC6_CHSTAT_n_ER (0x00000010uL) +#define DMAC6_CHSTAT_n_END (0x00000020uL) +#define DMAC6_CHSTAT_n_TC (0x00000040uL) +#define DMAC6_CHSTAT_n_SR (0x00000080uL) +#define DMAC6_CHSTAT_n_DL (0x00000100uL) +#define DMAC6_CHSTAT_n_DW (0x00000200uL) +#define DMAC6_CHSTAT_n_DER (0x00000400uL) +#define DMAC6_CHSTAT_n_MODE (0x00000800uL) +#define DMAC6_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC6_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC6_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC6_CHCTRL_n_STG (0x00000004uL) +#define DMAC6_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC6_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC6_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC6_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC6_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC6_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC6_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC6_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC6_CHCFG_n_SEL (0x00000007uL) +#define DMAC6_CHCFG_n_REQD (0x00000008uL) +#define DMAC6_CHCFG_n_LOEN (0x00000010uL) +#define DMAC6_CHCFG_n_HIEN (0x00000020uL) +#define DMAC6_CHCFG_n_LVL (0x00000040uL) +#define DMAC6_CHCFG_n_AM (0x00000700uL) +#define DMAC6_CHCFG_n_SDS (0x0000F000uL) +#define DMAC6_CHCFG_n_DDS (0x000F0000uL) +#define DMAC6_CHCFG_n_SAD (0x00100000uL) +#define DMAC6_CHCFG_n_DAD (0x00200000uL) +#define DMAC6_CHCFG_n_TM (0x00400000uL) +#define DMAC6_CHCFG_n_DEM (0x01000000uL) +#define DMAC6_CHCFG_n_TCM (0x02000000uL) +#define DMAC6_CHCFG_n_SBE (0x08000000uL) +#define DMAC6_CHCFG_n_RSEL (0x10000000uL) +#define DMAC6_CHCFG_n_RSW (0x20000000uL) +#define DMAC6_CHCFG_n_REN (0x40000000uL) +#define DMAC6_CHCFG_n_DMS (0x80000000uL) + +#define DMAC6_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC6_CHEXT_n_SCA (0x000000F0uL) +#define DMAC6_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC6_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC6_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC7 ---- */ +#define DMAC7_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC7_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC7_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC7_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC7_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC7_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC7_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC7_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC7_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC7_CHSTAT_n_EN (0x00000001uL) +#define DMAC7_CHSTAT_n_RQST (0x00000002uL) +#define DMAC7_CHSTAT_n_TACT (0x00000004uL) +#define DMAC7_CHSTAT_n_SUS (0x00000008uL) +#define DMAC7_CHSTAT_n_ER (0x00000010uL) +#define DMAC7_CHSTAT_n_END (0x00000020uL) +#define DMAC7_CHSTAT_n_TC (0x00000040uL) +#define DMAC7_CHSTAT_n_SR (0x00000080uL) +#define DMAC7_CHSTAT_n_DL (0x00000100uL) +#define DMAC7_CHSTAT_n_DW (0x00000200uL) +#define DMAC7_CHSTAT_n_DER (0x00000400uL) +#define DMAC7_CHSTAT_n_MODE (0x00000800uL) +#define DMAC7_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC7_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC7_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC7_CHCTRL_n_STG (0x00000004uL) +#define DMAC7_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC7_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC7_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC7_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC7_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC7_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC7_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC7_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC7_CHCFG_n_SEL (0x00000007uL) +#define DMAC7_CHCFG_n_REQD (0x00000008uL) +#define DMAC7_CHCFG_n_LOEN (0x00000010uL) +#define DMAC7_CHCFG_n_HIEN (0x00000020uL) +#define DMAC7_CHCFG_n_LVL (0x00000040uL) +#define DMAC7_CHCFG_n_AM (0x00000700uL) +#define DMAC7_CHCFG_n_SDS (0x0000F000uL) +#define DMAC7_CHCFG_n_DDS (0x000F0000uL) +#define DMAC7_CHCFG_n_SAD (0x00100000uL) +#define DMAC7_CHCFG_n_DAD (0x00200000uL) +#define DMAC7_CHCFG_n_TM (0x00400000uL) +#define DMAC7_CHCFG_n_DEM (0x01000000uL) +#define DMAC7_CHCFG_n_TCM (0x02000000uL) +#define DMAC7_CHCFG_n_SBE (0x08000000uL) +#define DMAC7_CHCFG_n_RSEL (0x10000000uL) +#define DMAC7_CHCFG_n_RSW (0x20000000uL) +#define DMAC7_CHCFG_n_REN (0x40000000uL) +#define DMAC7_CHCFG_n_DMS (0x80000000uL) + +#define DMAC7_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC7_CHEXT_n_SCA (0x000000F0uL) +#define DMAC7_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC7_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC7_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC0-7 ---- */ +#define DMAC07_DCTRL_0_7_PR (0x00000001uL) +#define DMAC07_DCTRL_0_7_LVINT (0x00000002uL) +#define DMAC07_DCTRL_0_7_LDCA (0x0000003CuL) +#define DMAC07_DCTRL_0_7_LWCA (0x000003C0uL) + +#define DMAC07_DSTAT_EN_0_7_EN0 (0x00000001uL) +#define DMAC07_DSTAT_EN_0_7_EN1 (0x00000002uL) +#define DMAC07_DSTAT_EN_0_7_EN2 (0x00000004uL) +#define DMAC07_DSTAT_EN_0_7_EN3 (0x00000008uL) +#define DMAC07_DSTAT_EN_0_7_EN4 (0x00000010uL) +#define DMAC07_DSTAT_EN_0_7_EN5 (0x00000020uL) +#define DMAC07_DSTAT_EN_0_7_EN6 (0x00000040uL) +#define DMAC07_DSTAT_EN_0_7_EN7 (0x00000080uL) + +#define DMAC07_DSTAT_ER_0_7_ER0 (0x00000001uL) +#define DMAC07_DSTAT_ER_0_7_ER1 (0x00000002uL) +#define DMAC07_DSTAT_ER_0_7_ER2 (0x00000004uL) +#define DMAC07_DSTAT_ER_0_7_ER3 (0x00000008uL) +#define DMAC07_DSTAT_ER_0_7_ER4 (0x00000010uL) +#define DMAC07_DSTAT_ER_0_7_ER5 (0x00000020uL) +#define DMAC07_DSTAT_ER_0_7_ER6 (0x00000040uL) +#define DMAC07_DSTAT_ER_0_7_ER7 (0x00000080uL) + +#define DMAC07_DSTAT_END_0_7_END0 (0x00000001uL) +#define DMAC07_DSTAT_END_0_7_END1 (0x00000002uL) +#define DMAC07_DSTAT_END_0_7_END2 (0x00000004uL) +#define DMAC07_DSTAT_END_0_7_END3 (0x00000008uL) +#define DMAC07_DSTAT_END_0_7_END4 (0x00000010uL) +#define DMAC07_DSTAT_END_0_7_END5 (0x00000020uL) +#define DMAC07_DSTAT_END_0_7_END6 (0x00000040uL) +#define DMAC07_DSTAT_END_0_7_END7 (0x00000080uL) + +#define DMAC07_DSTAT_TC_0_7_TC0 (0x00000001uL) +#define DMAC07_DSTAT_TC_0_7_TC1 (0x00000002uL) +#define DMAC07_DSTAT_TC_0_7_TC2 (0x00000004uL) +#define DMAC07_DSTAT_TC_0_7_TC3 (0x00000008uL) +#define DMAC07_DSTAT_TC_0_7_TC4 (0x00000010uL) +#define DMAC07_DSTAT_TC_0_7_TC5 (0x00000020uL) +#define DMAC07_DSTAT_TC_0_7_TC6 (0x00000040uL) +#define DMAC07_DSTAT_TC_0_7_TC7 (0x00000080uL) + +#define DMAC07_DSTAT_SUS_0_7_SUS0 (0x00000001uL) +#define DMAC07_DSTAT_SUS_0_7_SUS1 (0x00000002uL) +#define DMAC07_DSTAT_SUS_0_7_SUS2 (0x00000004uL) +#define DMAC07_DSTAT_SUS_0_7_SUS3 (0x00000008uL) +#define DMAC07_DSTAT_SUS_0_7_SUS4 (0x00000010uL) +#define DMAC07_DSTAT_SUS_0_7_SUS5 (0x00000020uL) +#define DMAC07_DSTAT_SUS_0_7_SUS6 (0x00000040uL) +#define DMAC07_DSTAT_SUS_0_7_SUS7 (0x00000080uL) + +/* ---- DMAC8 ---- */ +#define DMAC8_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC8_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC8_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC8_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC8_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC8_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC8_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC8_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC8_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC8_CHSTAT_n_EN (0x00000001uL) +#define DMAC8_CHSTAT_n_RQST (0x00000002uL) +#define DMAC8_CHSTAT_n_TACT (0x00000004uL) +#define DMAC8_CHSTAT_n_SUS (0x00000008uL) +#define DMAC8_CHSTAT_n_ER (0x00000010uL) +#define DMAC8_CHSTAT_n_END (0x00000020uL) +#define DMAC8_CHSTAT_n_TC (0x00000040uL) +#define DMAC8_CHSTAT_n_SR (0x00000080uL) +#define DMAC8_CHSTAT_n_DL (0x00000100uL) +#define DMAC8_CHSTAT_n_DW (0x00000200uL) +#define DMAC8_CHSTAT_n_DER (0x00000400uL) +#define DMAC8_CHSTAT_n_MODE (0x00000800uL) +#define DMAC8_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC8_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC8_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC8_CHCTRL_n_STG (0x00000004uL) +#define DMAC8_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC8_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC8_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC8_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC8_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC8_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC8_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC8_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC8_CHCFG_n_SEL (0x00000007uL) +#define DMAC8_CHCFG_n_REQD (0x00000008uL) +#define DMAC8_CHCFG_n_LOEN (0x00000010uL) +#define DMAC8_CHCFG_n_HIEN (0x00000020uL) +#define DMAC8_CHCFG_n_LVL (0x00000040uL) +#define DMAC8_CHCFG_n_AM (0x00000700uL) +#define DMAC8_CHCFG_n_SDS (0x0000F000uL) +#define DMAC8_CHCFG_n_DDS (0x000F0000uL) +#define DMAC8_CHCFG_n_SAD (0x00100000uL) +#define DMAC8_CHCFG_n_DAD (0x00200000uL) +#define DMAC8_CHCFG_n_TM (0x00400000uL) +#define DMAC8_CHCFG_n_DEM (0x01000000uL) +#define DMAC8_CHCFG_n_TCM (0x02000000uL) +#define DMAC8_CHCFG_n_SBE (0x08000000uL) +#define DMAC8_CHCFG_n_RSEL (0x10000000uL) +#define DMAC8_CHCFG_n_RSW (0x20000000uL) +#define DMAC8_CHCFG_n_REN (0x40000000uL) +#define DMAC8_CHCFG_n_DMS (0x80000000uL) + +#define DMAC8_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC8_CHEXT_n_SCA (0x000000F0uL) +#define DMAC8_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC8_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC8_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC9 ---- */ +#define DMAC9_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC9_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC9_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC9_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC9_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC9_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC9_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC9_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC9_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC9_CHSTAT_n_EN (0x00000001uL) +#define DMAC9_CHSTAT_n_RQST (0x00000002uL) +#define DMAC9_CHSTAT_n_TACT (0x00000004uL) +#define DMAC9_CHSTAT_n_SUS (0x00000008uL) +#define DMAC9_CHSTAT_n_ER (0x00000010uL) +#define DMAC9_CHSTAT_n_END (0x00000020uL) +#define DMAC9_CHSTAT_n_TC (0x00000040uL) +#define DMAC9_CHSTAT_n_SR (0x00000080uL) +#define DMAC9_CHSTAT_n_DL (0x00000100uL) +#define DMAC9_CHSTAT_n_DW (0x00000200uL) +#define DMAC9_CHSTAT_n_DER (0x00000400uL) +#define DMAC9_CHSTAT_n_MODE (0x00000800uL) +#define DMAC9_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC9_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC9_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC9_CHCTRL_n_STG (0x00000004uL) +#define DMAC9_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC9_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC9_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC9_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC9_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC9_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC9_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC9_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC9_CHCFG_n_SEL (0x00000007uL) +#define DMAC9_CHCFG_n_REQD (0x00000008uL) +#define DMAC9_CHCFG_n_LOEN (0x00000010uL) +#define DMAC9_CHCFG_n_HIEN (0x00000020uL) +#define DMAC9_CHCFG_n_LVL (0x00000040uL) +#define DMAC9_CHCFG_n_AM (0x00000700uL) +#define DMAC9_CHCFG_n_SDS (0x0000F000uL) +#define DMAC9_CHCFG_n_DDS (0x000F0000uL) +#define DMAC9_CHCFG_n_SAD (0x00100000uL) +#define DMAC9_CHCFG_n_DAD (0x00200000uL) +#define DMAC9_CHCFG_n_TM (0x00400000uL) +#define DMAC9_CHCFG_n_DEM (0x01000000uL) +#define DMAC9_CHCFG_n_TCM (0x02000000uL) +#define DMAC9_CHCFG_n_SBE (0x08000000uL) +#define DMAC9_CHCFG_n_RSEL (0x10000000uL) +#define DMAC9_CHCFG_n_RSW (0x20000000uL) +#define DMAC9_CHCFG_n_REN (0x40000000uL) +#define DMAC9_CHCFG_n_DMS (0x80000000uL) + +#define DMAC9_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC9_CHEXT_n_SCA (0x000000F0uL) +#define DMAC9_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC9_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC9_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC10 ---- */ +#define DMAC10_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC10_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC10_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC10_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC10_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC10_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC10_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC10_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC10_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC10_CHSTAT_n_EN (0x00000001uL) +#define DMAC10_CHSTAT_n_RQST (0x00000002uL) +#define DMAC10_CHSTAT_n_TACT (0x00000004uL) +#define DMAC10_CHSTAT_n_SUS (0x00000008uL) +#define DMAC10_CHSTAT_n_ER (0x00000010uL) +#define DMAC10_CHSTAT_n_END (0x00000020uL) +#define DMAC10_CHSTAT_n_TC (0x00000040uL) +#define DMAC10_CHSTAT_n_SR (0x00000080uL) +#define DMAC10_CHSTAT_n_DL (0x00000100uL) +#define DMAC10_CHSTAT_n_DW (0x00000200uL) +#define DMAC10_CHSTAT_n_DER (0x00000400uL) +#define DMAC10_CHSTAT_n_MODE (0x00000800uL) +#define DMAC10_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC10_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC10_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC10_CHCTRL_n_STG (0x00000004uL) +#define DMAC10_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC10_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC10_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC10_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC10_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC10_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC10_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC10_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC10_CHCFG_n_SEL (0x00000007uL) +#define DMAC10_CHCFG_n_REQD (0x00000008uL) +#define DMAC10_CHCFG_n_LOEN (0x00000010uL) +#define DMAC10_CHCFG_n_HIEN (0x00000020uL) +#define DMAC10_CHCFG_n_LVL (0x00000040uL) +#define DMAC10_CHCFG_n_AM (0x00000700uL) +#define DMAC10_CHCFG_n_SDS (0x0000F000uL) +#define DMAC10_CHCFG_n_DDS (0x000F0000uL) +#define DMAC10_CHCFG_n_SAD (0x00100000uL) +#define DMAC10_CHCFG_n_DAD (0x00200000uL) +#define DMAC10_CHCFG_n_TM (0x00400000uL) +#define DMAC10_CHCFG_n_DEM (0x01000000uL) +#define DMAC10_CHCFG_n_TCM (0x02000000uL) +#define DMAC10_CHCFG_n_SBE (0x08000000uL) +#define DMAC10_CHCFG_n_RSEL (0x10000000uL) +#define DMAC10_CHCFG_n_RSW (0x20000000uL) +#define DMAC10_CHCFG_n_REN (0x40000000uL) +#define DMAC10_CHCFG_n_DMS (0x80000000uL) + +#define DMAC10_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC10_CHEXT_n_SCA (0x000000F0uL) +#define DMAC10_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC10_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC10_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC11 ---- */ +#define DMAC11_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC11_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC11_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC11_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC11_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC11_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC11_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC11_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC11_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC11_CHSTAT_n_EN (0x00000001uL) +#define DMAC11_CHSTAT_n_RQST (0x00000002uL) +#define DMAC11_CHSTAT_n_TACT (0x00000004uL) +#define DMAC11_CHSTAT_n_SUS (0x00000008uL) +#define DMAC11_CHSTAT_n_ER (0x00000010uL) +#define DMAC11_CHSTAT_n_END (0x00000020uL) +#define DMAC11_CHSTAT_n_TC (0x00000040uL) +#define DMAC11_CHSTAT_n_SR (0x00000080uL) +#define DMAC11_CHSTAT_n_DL (0x00000100uL) +#define DMAC11_CHSTAT_n_DW (0x00000200uL) +#define DMAC11_CHSTAT_n_DER (0x00000400uL) +#define DMAC11_CHSTAT_n_MODE (0x00000800uL) +#define DMAC11_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC11_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC11_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC11_CHCTRL_n_STG (0x00000004uL) +#define DMAC11_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC11_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC11_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC11_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC11_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC11_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC11_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC11_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC11_CHCFG_n_SEL (0x00000007uL) +#define DMAC11_CHCFG_n_REQD (0x00000008uL) +#define DMAC11_CHCFG_n_LOEN (0x00000010uL) +#define DMAC11_CHCFG_n_HIEN (0x00000020uL) +#define DMAC11_CHCFG_n_LVL (0x00000040uL) +#define DMAC11_CHCFG_n_AM (0x00000700uL) +#define DMAC11_CHCFG_n_SDS (0x0000F000uL) +#define DMAC11_CHCFG_n_DDS (0x000F0000uL) +#define DMAC11_CHCFG_n_SAD (0x00100000uL) +#define DMAC11_CHCFG_n_DAD (0x00200000uL) +#define DMAC11_CHCFG_n_TM (0x00400000uL) +#define DMAC11_CHCFG_n_DEM (0x01000000uL) +#define DMAC11_CHCFG_n_TCM (0x02000000uL) +#define DMAC11_CHCFG_n_SBE (0x08000000uL) +#define DMAC11_CHCFG_n_RSEL (0x10000000uL) +#define DMAC11_CHCFG_n_RSW (0x20000000uL) +#define DMAC11_CHCFG_n_REN (0x40000000uL) +#define DMAC11_CHCFG_n_DMS (0x80000000uL) + +#define DMAC11_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC11_CHEXT_n_SCA (0x000000F0uL) +#define DMAC11_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC11_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC11_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC12 ---- */ +#define DMAC12_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC12_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC12_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC12_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC12_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC12_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC12_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC12_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC12_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC12_CHSTAT_n_EN (0x00000001uL) +#define DMAC12_CHSTAT_n_RQST (0x00000002uL) +#define DMAC12_CHSTAT_n_TACT (0x00000004uL) +#define DMAC12_CHSTAT_n_SUS (0x00000008uL) +#define DMAC12_CHSTAT_n_ER (0x00000010uL) +#define DMAC12_CHSTAT_n_END (0x00000020uL) +#define DMAC12_CHSTAT_n_TC (0x00000040uL) +#define DMAC12_CHSTAT_n_SR (0x00000080uL) +#define DMAC12_CHSTAT_n_DL (0x00000100uL) +#define DMAC12_CHSTAT_n_DW (0x00000200uL) +#define DMAC12_CHSTAT_n_DER (0x00000400uL) +#define DMAC12_CHSTAT_n_MODE (0x00000800uL) +#define DMAC12_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC12_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC12_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC12_CHCTRL_n_STG (0x00000004uL) +#define DMAC12_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC12_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC12_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC12_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC12_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC12_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC12_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC12_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC12_CHCFG_n_SEL (0x00000007uL) +#define DMAC12_CHCFG_n_REQD (0x00000008uL) +#define DMAC12_CHCFG_n_LOEN (0x00000010uL) +#define DMAC12_CHCFG_n_HIEN (0x00000020uL) +#define DMAC12_CHCFG_n_LVL (0x00000040uL) +#define DMAC12_CHCFG_n_AM (0x00000700uL) +#define DMAC12_CHCFG_n_SDS (0x0000F000uL) +#define DMAC12_CHCFG_n_DDS (0x000F0000uL) +#define DMAC12_CHCFG_n_SAD (0x00100000uL) +#define DMAC12_CHCFG_n_DAD (0x00200000uL) +#define DMAC12_CHCFG_n_TM (0x00400000uL) +#define DMAC12_CHCFG_n_DEM (0x01000000uL) +#define DMAC12_CHCFG_n_TCM (0x02000000uL) +#define DMAC12_CHCFG_n_SBE (0x08000000uL) +#define DMAC12_CHCFG_n_RSEL (0x10000000uL) +#define DMAC12_CHCFG_n_RSW (0x20000000uL) +#define DMAC12_CHCFG_n_REN (0x40000000uL) +#define DMAC12_CHCFG_n_DMS (0x80000000uL) + +#define DMAC12_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC12_CHEXT_n_SCA (0x000000F0uL) +#define DMAC12_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC12_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC12_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC13 ---- */ +#define DMAC13_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC13_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC13_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC13_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC13_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC13_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC13_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC13_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC13_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC13_CHSTAT_n_EN (0x00000001uL) +#define DMAC13_CHSTAT_n_RQST (0x00000002uL) +#define DMAC13_CHSTAT_n_TACT (0x00000004uL) +#define DMAC13_CHSTAT_n_SUS (0x00000008uL) +#define DMAC13_CHSTAT_n_ER (0x00000010uL) +#define DMAC13_CHSTAT_n_END (0x00000020uL) +#define DMAC13_CHSTAT_n_TC (0x00000040uL) +#define DMAC13_CHSTAT_n_SR (0x00000080uL) +#define DMAC13_CHSTAT_n_DL (0x00000100uL) +#define DMAC13_CHSTAT_n_DW (0x00000200uL) +#define DMAC13_CHSTAT_n_DER (0x00000400uL) +#define DMAC13_CHSTAT_n_MODE (0x00000800uL) +#define DMAC13_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC13_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC13_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC13_CHCTRL_n_STG (0x00000004uL) +#define DMAC13_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC13_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC13_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC13_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC13_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC13_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC13_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC13_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC13_CHCFG_n_SEL (0x00000007uL) +#define DMAC13_CHCFG_n_REQD (0x00000008uL) +#define DMAC13_CHCFG_n_LOEN (0x00000010uL) +#define DMAC13_CHCFG_n_HIEN (0x00000020uL) +#define DMAC13_CHCFG_n_LVL (0x00000040uL) +#define DMAC13_CHCFG_n_AM (0x00000700uL) +#define DMAC13_CHCFG_n_SDS (0x0000F000uL) +#define DMAC13_CHCFG_n_DDS (0x000F0000uL) +#define DMAC13_CHCFG_n_SAD (0x00100000uL) +#define DMAC13_CHCFG_n_DAD (0x00200000uL) +#define DMAC13_CHCFG_n_TM (0x00400000uL) +#define DMAC13_CHCFG_n_DEM (0x01000000uL) +#define DMAC13_CHCFG_n_TCM (0x02000000uL) +#define DMAC13_CHCFG_n_SBE (0x08000000uL) +#define DMAC13_CHCFG_n_RSEL (0x10000000uL) +#define DMAC13_CHCFG_n_RSW (0x20000000uL) +#define DMAC13_CHCFG_n_REN (0x40000000uL) +#define DMAC13_CHCFG_n_DMS (0x80000000uL) + +#define DMAC13_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC13_CHEXT_n_SCA (0x000000F0uL) +#define DMAC13_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC13_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC13_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC14 ---- */ +#define DMAC14_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC14_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC14_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC14_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC14_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC14_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC14_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC14_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC14_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC14_CHSTAT_n_EN (0x00000001uL) +#define DMAC14_CHSTAT_n_RQST (0x00000002uL) +#define DMAC14_CHSTAT_n_TACT (0x00000004uL) +#define DMAC14_CHSTAT_n_SUS (0x00000008uL) +#define DMAC14_CHSTAT_n_ER (0x00000010uL) +#define DMAC14_CHSTAT_n_END (0x00000020uL) +#define DMAC14_CHSTAT_n_TC (0x00000040uL) +#define DMAC14_CHSTAT_n_SR (0x00000080uL) +#define DMAC14_CHSTAT_n_DL (0x00000100uL) +#define DMAC14_CHSTAT_n_DW (0x00000200uL) +#define DMAC14_CHSTAT_n_DER (0x00000400uL) +#define DMAC14_CHSTAT_n_MODE (0x00000800uL) +#define DMAC14_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC14_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC14_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC14_CHCTRL_n_STG (0x00000004uL) +#define DMAC14_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC14_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC14_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC14_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC14_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC14_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC14_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC14_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC14_CHCFG_n_SEL (0x00000007uL) +#define DMAC14_CHCFG_n_REQD (0x00000008uL) +#define DMAC14_CHCFG_n_LOEN (0x00000010uL) +#define DMAC14_CHCFG_n_HIEN (0x00000020uL) +#define DMAC14_CHCFG_n_LVL (0x00000040uL) +#define DMAC14_CHCFG_n_AM (0x00000700uL) +#define DMAC14_CHCFG_n_SDS (0x0000F000uL) +#define DMAC14_CHCFG_n_DDS (0x000F0000uL) +#define DMAC14_CHCFG_n_SAD (0x00100000uL) +#define DMAC14_CHCFG_n_DAD (0x00200000uL) +#define DMAC14_CHCFG_n_TM (0x00400000uL) +#define DMAC14_CHCFG_n_DEM (0x01000000uL) +#define DMAC14_CHCFG_n_TCM (0x02000000uL) +#define DMAC14_CHCFG_n_SBE (0x08000000uL) +#define DMAC14_CHCFG_n_RSEL (0x10000000uL) +#define DMAC14_CHCFG_n_RSW (0x20000000uL) +#define DMAC14_CHCFG_n_REN (0x40000000uL) +#define DMAC14_CHCFG_n_DMS (0x80000000uL) + +#define DMAC14_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC14_CHEXT_n_SCA (0x000000F0uL) +#define DMAC14_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC14_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC14_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC15 ---- */ +#define DMAC15_N0SA_n_SA (0xFFFFFFFFuL) + +#define DMAC15_N0DA_n_DA (0xFFFFFFFFuL) + +#define DMAC15_N0TB_n_TB (0xFFFFFFFFuL) + +#define DMAC15_N1SA_n_SA (0xFFFFFFFFuL) + +#define DMAC15_N1DA_n_DA (0xFFFFFFFFuL) + +#define DMAC15_N1TB_n_TB (0xFFFFFFFFuL) + +#define DMAC15_CRSA_n_CRSA (0xFFFFFFFFuL) + +#define DMAC15_CRDA_n_CRDA (0xFFFFFFFFuL) + +#define DMAC15_CRTB_n_CRTB (0xFFFFFFFFuL) + +#define DMAC15_CHSTAT_n_EN (0x00000001uL) +#define DMAC15_CHSTAT_n_RQST (0x00000002uL) +#define DMAC15_CHSTAT_n_TACT (0x00000004uL) +#define DMAC15_CHSTAT_n_SUS (0x00000008uL) +#define DMAC15_CHSTAT_n_ER (0x00000010uL) +#define DMAC15_CHSTAT_n_END (0x00000020uL) +#define DMAC15_CHSTAT_n_TC (0x00000040uL) +#define DMAC15_CHSTAT_n_SR (0x00000080uL) +#define DMAC15_CHSTAT_n_DL (0x00000100uL) +#define DMAC15_CHSTAT_n_DW (0x00000200uL) +#define DMAC15_CHSTAT_n_DER (0x00000400uL) +#define DMAC15_CHSTAT_n_MODE (0x00000800uL) +#define DMAC15_CHSTAT_n_INTMSK (0x00010000uL) + +#define DMAC15_CHCTRL_n_SETEN (0x00000001uL) +#define DMAC15_CHCTRL_n_CLREN (0x00000002uL) +#define DMAC15_CHCTRL_n_STG (0x00000004uL) +#define DMAC15_CHCTRL_n_SWRST (0x00000008uL) +#define DMAC15_CHCTRL_n_CLRRQ (0x00000010uL) +#define DMAC15_CHCTRL_n_CLREND (0x00000020uL) +#define DMAC15_CHCTRL_n_CLRTC (0x00000040uL) +#define DMAC15_CHCTRL_n_SETSUS (0x00000100uL) +#define DMAC15_CHCTRL_n_CLRSUS (0x00000200uL) +#define DMAC15_CHCTRL_n_SETINTMSK (0x00010000uL) +#define DMAC15_CHCTRL_n_CLRINTMSK (0x00020000uL) + +#define DMAC15_CHCFG_n_SEL (0x00000007uL) +#define DMAC15_CHCFG_n_REQD (0x00000008uL) +#define DMAC15_CHCFG_n_LOEN (0x00000010uL) +#define DMAC15_CHCFG_n_HIEN (0x00000020uL) +#define DMAC15_CHCFG_n_LVL (0x00000040uL) +#define DMAC15_CHCFG_n_AM (0x00000700uL) +#define DMAC15_CHCFG_n_SDS (0x0000F000uL) +#define DMAC15_CHCFG_n_DDS (0x000F0000uL) +#define DMAC15_CHCFG_n_SAD (0x00100000uL) +#define DMAC15_CHCFG_n_DAD (0x00200000uL) +#define DMAC15_CHCFG_n_TM (0x00400000uL) +#define DMAC15_CHCFG_n_DEM (0x01000000uL) +#define DMAC15_CHCFG_n_TCM (0x02000000uL) +#define DMAC15_CHCFG_n_SBE (0x08000000uL) +#define DMAC15_CHCFG_n_RSEL (0x10000000uL) +#define DMAC15_CHCFG_n_RSW (0x20000000uL) +#define DMAC15_CHCFG_n_REN (0x40000000uL) +#define DMAC15_CHCFG_n_DMS (0x80000000uL) + +#define DMAC15_CHITVL_n_ITVL (0x0000FFFFuL) + +#define DMAC15_CHEXT_n_SCA (0x000000F0uL) +#define DMAC15_CHEXT_n_DCA (0x0000F000uL) + +#define DMAC15_NXLA_n_NXLA (0xFFFFFFFFuL) + +#define DMAC15_CRLA_n_CRLA (0xFFFFFFFFuL) + +/* ---- DMAC8-15 ---- */ +#define DMAC815_DCTRL_8_15_PR (0x00000001uL) +#define DMAC815_DCTRL_8_15_LVINT (0x00000002uL) +#define DMAC815_DCTRL_8_15_LDCA (0x0000003CuL) +#define DMAC815_DCTRL_8_15_LWCA (0x00003C00uL) + +#define DMAC815_DSTAT_EN_8_15_EN8 (0x00000001uL) +#define DMAC815_DSTAT_EN_8_15_EN9 (0x00000002uL) +#define DMAC815_DSTAT_EN_8_15_EN10 (0x00000004uL) +#define DMAC815_DSTAT_EN_8_15_EN11 (0x00000008uL) +#define DMAC815_DSTAT_EN_8_15_EN12 (0x00000010uL) +#define DMAC815_DSTAT_EN_8_15_EN13 (0x00000020uL) +#define DMAC815_DSTAT_EN_8_15_EN14 (0x00000040uL) +#define DMAC815_DSTAT_EN_8_15_EN15 (0x00000080uL) + +#define DMAC815_DSTAT_ER_8_15_ER8 (0x00000001uL) +#define DMAC815_DSTAT_ER_8_15_ER9 (0x00000002uL) +#define DMAC815_DSTAT_ER_8_15_ER10 (0x00000004uL) +#define DMAC815_DSTAT_ER_8_15_ER11 (0x00000008uL) +#define DMAC815_DSTAT_ER_8_15_ER12 (0x00000010uL) +#define DMAC815_DSTAT_ER_8_15_ER13 (0x00000020uL) +#define DMAC815_DSTAT_ER_8_15_ER14 (0x00000040uL) +#define DMAC815_DSTAT_ER_8_15_ER15 (0x00000080uL) + +#define DMAC815_DSTAT_END_8_15_END8 (0x00000001uL) +#define DMAC815_DSTAT_END_8_15_END9 (0x00000002uL) +#define DMAC815_DSTAT_END_8_15_END10 (0x00000004uL) +#define DMAC815_DSTAT_END_8_15_END11 (0x00000008uL) +#define DMAC815_DSTAT_END_8_15_END12 (0x00000010uL) +#define DMAC815_DSTAT_END_8_15_END13 (0x00000020uL) +#define DMAC815_DSTAT_END_8_15_END14 (0x00000040uL) +#define DMAC815_DSTAT_END_8_15_END15 (0x00000080uL) + +#define DMAC815_DSTAT_TC_8_15_TC8 (0x00000001uL) +#define DMAC815_DSTAT_TC_8_15_TC9 (0x00000002uL) +#define DMAC815_DSTAT_TC_8_15_TC10 (0x00000004uL) +#define DMAC815_DSTAT_TC_8_15_TC11 (0x00000008uL) +#define DMAC815_DSTAT_TC_8_15_TC12 (0x00000010uL) +#define DMAC815_DSTAT_TC_8_15_TC13 (0x00000020uL) +#define DMAC815_DSTAT_TC_8_15_TC14 (0x00000040uL) +#define DMAC815_DSTAT_TC_8_15_TC15 (0x00000080uL) + +#define DMAC815_DSTAT_SUS_8_15_SUS8 (0x00000001uL) +#define DMAC815_DSTAT_SUS_8_15_SUS9 (0x00000002uL) +#define DMAC815_DSTAT_SUS_8_15_SUS10 (0x00000004uL) +#define DMAC815_DSTAT_SUS_8_15_SUS11 (0x00000008uL) +#define DMAC815_DSTAT_SUS_8_15_SUS12 (0x00000010uL) +#define DMAC815_DSTAT_SUS_8_15_SUS13 (0x00000020uL) +#define DMAC815_DSTAT_SUS_8_15_SUS14 (0x00000040uL) +#define DMAC815_DSTAT_SUS_8_15_SUS15 (0x00000080uL) + +/* ---- DMAC0-1 ---- */ +#define DMAC01_DMARS_CH0_RID (0x00000003uL) +#define DMAC01_DMARS_CH0_MID (0x000001FCuL) +#define DMAC01_DMARS_CH1_RID (0x00030000uL) +#define DMAC01_DMARS_CH1_MID (0x01FC0000uL) + +/* ---- DMAC2-3 ---- */ +#define DMAC23_DMARS_CH2_RID (0x00000003uL) +#define DMAC23_DMARS_CH2_MID (0x000001FCuL) +#define DMAC23_DMARS_CH3_RID (0x00030000uL) +#define DMAC23_DMARS_CH3_MID (0x01FC0000uL) + +/* ---- DMAC4-5 ---- */ +#define DMAC45_DMARS_CH4_RID (0x00000003uL) +#define DMAC45_DMARS_CH4_MID (0x000001FCuL) +#define DMAC45_DMARS_CH5_RID (0x00030000uL) +#define DMAC45_DMARS_CH5_MID (0x01FC0000uL) + +/* ---- DMAC6-7 ---- */ +#define DMAC67_DMARS_CH6_RID (0x00000003uL) +#define DMAC67_DMARS_CH6_MID (0x000001FCuL) +#define DMAC67_DMARS_CH7_RID (0x00030000uL) +#define DMAC67_DMARS_CH7_MID (0x01FC0000uL) + +/* ---- DMAC8-9 ---- */ +#define DMAC89_DMARS_CH8_RID (0x00000003uL) +#define DMAC89_DMARS_CH8_MID (0x000001FCuL) +#define DMAC89_DMARS_CH9_RID (0x00030000uL) +#define DMAC89_DMARS_CH9_MID (0x01FC0000uL) + +/* ---- DMAC10-11 ---- */ +#define DMAC1011_DMARS_CH10_RID (0x00000003uL) +#define DMAC1011_DMARS_CH10_MID (0x000001FCuL) +#define DMAC1011_DMARS_CH11_RID (0x00030000uL) +#define DMAC1011_DMARS_CH11_MID (0x01FC0000uL) + +/* ---- DMAC12-13 ---- */ +#define DMAC1213_DMARS_CH12_RID (0x00000003uL) +#define DMAC1213_DMARS_CH12_MID (0x000001FCuL) +#define DMAC1213_DMARS_CH13_RID (0x00030000uL) +#define DMAC1213_DMARS_CH13_MID (0x01FC0000uL) + +/* ---- DMAC14-15 ---- */ +#define DMAC1415_DMARS_CH14_RID (0x00000003uL) +#define DMAC1415_DMARS_CH14_MID (0x000001FCuL) +#define DMAC1415_DMARS_CH15_RID (0x00030000uL) +#define DMAC1415_DMARS_CH15_MID (0x01FC0000uL) + + +/* ==== Shift values for IO registers ==== */ +/* ---- DMAC0 ---- */ +#define DMAC0_N0SA_n_SA_SHIFT (0u) + +#define DMAC0_N0DA_n_DA_SHIFT (0u) + +#define DMAC0_N0TB_n_TB_SHIFT (0u) + +#define DMAC0_N1SA_n_SA_SHIFT (0u) + +#define DMAC0_N1DA_n_DA_SHIFT (0u) + +#define DMAC0_N1TB_n_TB_SHIFT (0u) + +#define DMAC0_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC0_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC0_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC0_CHSTAT_n_EN_SHIFT (0u) +#define DMAC0_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC0_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC0_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC0_CHSTAT_n_ER_SHIFT (4u) +#define DMAC0_CHSTAT_n_END_SHIFT (5u) +#define DMAC0_CHSTAT_n_TC_SHIFT (6u) +#define DMAC0_CHSTAT_n_SR_SHIFT (7u) +#define DMAC0_CHSTAT_n_DL_SHIFT (8u) +#define DMAC0_CHSTAT_n_DW_SHIFT (9u) +#define DMAC0_CHSTAT_n_DER_SHIFT (10u) +#define DMAC0_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC0_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC0_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC0_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC0_CHCTRL_n_STG_SHIFT (2u) +#define DMAC0_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC0_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC0_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC0_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC0_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC0_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC0_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC0_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC0_CHCFG_n_SEL_SHIFT (0u) +#define DMAC0_CHCFG_n_REQD_SHIFT (3u) +#define DMAC0_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC0_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC0_CHCFG_n_LVL_SHIFT (6u) +#define DMAC0_CHCFG_n_AM_SHIFT (8u) +#define DMAC0_CHCFG_n_SDS_SHIFT (12u) +#define DMAC0_CHCFG_n_DDS_SHIFT (16u) +#define DMAC0_CHCFG_n_SAD_SHIFT (20u) +#define DMAC0_CHCFG_n_DAD_SHIFT (21u) +#define DMAC0_CHCFG_n_TM_SHIFT (22u) +#define DMAC0_CHCFG_n_DEM_SHIFT (24u) +#define DMAC0_CHCFG_n_TCM_SHIFT (25u) +#define DMAC0_CHCFG_n_SBE_SHIFT (27u) +#define DMAC0_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC0_CHCFG_n_RSW_SHIFT (29u) +#define DMAC0_CHCFG_n_REN_SHIFT (30u) +#define DMAC0_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC0_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC0_CHEXT_n_SCA_SHIFT (4u) +#define DMAC0_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC0_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC0_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC1 ---- */ +#define DMAC1_N0SA_n_SA_SHIFT (0u) + +#define DMAC1_N0DA_n_DA_SHIFT (0u) + +#define DMAC1_N0TB_n_TB_SHIFT (0u) + +#define DMAC1_N1SA_n_SA_SHIFT (0u) + +#define DMAC1_N1DA_n_DA_SHIFT (0u) + +#define DMAC1_N1TB_n_TB_SHIFT (0u) + +#define DMAC1_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC1_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC1_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC1_CHSTAT_n_EN_SHIFT (0u) +#define DMAC1_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC1_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC1_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC1_CHSTAT_n_ER_SHIFT (4u) +#define DMAC1_CHSTAT_n_END_SHIFT (5u) +#define DMAC1_CHSTAT_n_TC_SHIFT (6u) +#define DMAC1_CHSTAT_n_SR_SHIFT (7u) +#define DMAC1_CHSTAT_n_DL_SHIFT (8u) +#define DMAC1_CHSTAT_n_DW_SHIFT (9u) +#define DMAC1_CHSTAT_n_DER_SHIFT (10u) +#define DMAC1_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC1_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC1_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC1_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC1_CHCTRL_n_STG_SHIFT (2u) +#define DMAC1_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC1_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC1_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC1_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC1_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC1_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC1_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC1_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC1_CHCFG_n_SEL_SHIFT (0u) +#define DMAC1_CHCFG_n_REQD_SHIFT (3u) +#define DMAC1_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC1_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC1_CHCFG_n_LVL_SHIFT (6u) +#define DMAC1_CHCFG_n_AM_SHIFT (8u) +#define DMAC1_CHCFG_n_SDS_SHIFT (12u) +#define DMAC1_CHCFG_n_DDS_SHIFT (16u) +#define DMAC1_CHCFG_n_SAD_SHIFT (20u) +#define DMAC1_CHCFG_n_DAD_SHIFT (21u) +#define DMAC1_CHCFG_n_TM_SHIFT (22u) +#define DMAC1_CHCFG_n_DEM_SHIFT (24u) +#define DMAC1_CHCFG_n_TCM_SHIFT (25u) +#define DMAC1_CHCFG_n_SBE_SHIFT (27u) +#define DMAC1_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC1_CHCFG_n_RSW_SHIFT (29u) +#define DMAC1_CHCFG_n_REN_SHIFT (30u) +#define DMAC1_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC1_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC1_CHEXT_n_SCA_SHIFT (4u) +#define DMAC1_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC1_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC1_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC2 ---- */ +#define DMAC2_N0SA_n_SA_SHIFT (0u) + +#define DMAC2_N0DA_n_DA_SHIFT (0u) + +#define DMAC2_N0TB_n_TB_SHIFT (0u) + +#define DMAC2_N1SA_n_SA_SHIFT (0u) + +#define DMAC2_N1DA_n_DA_SHIFT (0u) + +#define DMAC2_N1TB_n_TB_SHIFT (0u) + +#define DMAC2_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC2_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC2_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC2_CHSTAT_n_EN_SHIFT (0u) +#define DMAC2_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC2_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC2_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC2_CHSTAT_n_ER_SHIFT (4u) +#define DMAC2_CHSTAT_n_END_SHIFT (5u) +#define DMAC2_CHSTAT_n_TC_SHIFT (6u) +#define DMAC2_CHSTAT_n_SR_SHIFT (7u) +#define DMAC2_CHSTAT_n_DL_SHIFT (8u) +#define DMAC2_CHSTAT_n_DW_SHIFT (9u) +#define DMAC2_CHSTAT_n_DER_SHIFT (10u) +#define DMAC2_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC2_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC2_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC2_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC2_CHCTRL_n_STG_SHIFT (2u) +#define DMAC2_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC2_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC2_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC2_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC2_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC2_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC2_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC2_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC2_CHCFG_n_SEL_SHIFT (0u) +#define DMAC2_CHCFG_n_REQD_SHIFT (3u) +#define DMAC2_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC2_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC2_CHCFG_n_LVL_SHIFT (6u) +#define DMAC2_CHCFG_n_AM_SHIFT (8u) +#define DMAC2_CHCFG_n_SDS_SHIFT (12u) +#define DMAC2_CHCFG_n_DDS_SHIFT (16u) +#define DMAC2_CHCFG_n_SAD_SHIFT (20u) +#define DMAC2_CHCFG_n_DAD_SHIFT (21u) +#define DMAC2_CHCFG_n_TM_SHIFT (22u) +#define DMAC2_CHCFG_n_DEM_SHIFT (24u) +#define DMAC2_CHCFG_n_TCM_SHIFT (25u) +#define DMAC2_CHCFG_n_SBE_SHIFT (27u) +#define DMAC2_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC2_CHCFG_n_RSW_SHIFT (29u) +#define DMAC2_CHCFG_n_REN_SHIFT (30u) +#define DMAC2_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC2_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC2_CHEXT_n_SCA_SHIFT (4u) +#define DMAC2_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC2_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC2_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC3 ---- */ +#define DMAC3_N0SA_n_SA_SHIFT (0u) + +#define DMAC3_N0DA_n_DA_SHIFT (0u) + +#define DMAC3_N0TB_n_TB_SHIFT (0u) + +#define DMAC3_N1SA_n_SA_SHIFT (0u) + +#define DMAC3_N1DA_n_DA_SHIFT (0u) + +#define DMAC3_N1TB_n_TB_SHIFT (0u) + +#define DMAC3_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC3_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC3_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC3_CHSTAT_n_EN_SHIFT (0u) +#define DMAC3_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC3_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC3_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC3_CHSTAT_n_ER_SHIFT (4u) +#define DMAC3_CHSTAT_n_END_SHIFT (5u) +#define DMAC3_CHSTAT_n_TC_SHIFT (6u) +#define DMAC3_CHSTAT_n_SR_SHIFT (7u) +#define DMAC3_CHSTAT_n_DL_SHIFT (8u) +#define DMAC3_CHSTAT_n_DW_SHIFT (9u) +#define DMAC3_CHSTAT_n_DER_SHIFT (10u) +#define DMAC3_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC3_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC3_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC3_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC3_CHCTRL_n_STG_SHIFT (2u) +#define DMAC3_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC3_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC3_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC3_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC3_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC3_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC3_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC3_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC3_CHCFG_n_SEL_SHIFT (0u) +#define DMAC3_CHCFG_n_REQD_SHIFT (3u) +#define DMAC3_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC3_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC3_CHCFG_n_LVL_SHIFT (6u) +#define DMAC3_CHCFG_n_AM_SHIFT (8u) +#define DMAC3_CHCFG_n_SDS_SHIFT (12u) +#define DMAC3_CHCFG_n_DDS_SHIFT (16u) +#define DMAC3_CHCFG_n_SAD_SHIFT (20u) +#define DMAC3_CHCFG_n_DAD_SHIFT (21u) +#define DMAC3_CHCFG_n_TM_SHIFT (22u) +#define DMAC3_CHCFG_n_DEM_SHIFT (24u) +#define DMAC3_CHCFG_n_TCM_SHIFT (25u) +#define DMAC3_CHCFG_n_SBE_SHIFT (27u) +#define DMAC3_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC3_CHCFG_n_RSW_SHIFT (29u) +#define DMAC3_CHCFG_n_REN_SHIFT (30u) +#define DMAC3_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC3_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC3_CHEXT_n_SCA_SHIFT (4u) +#define DMAC3_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC3_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC3_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC4 ---- */ +#define DMAC4_N0SA_n_SA_SHIFT (0u) + +#define DMAC4_N0DA_n_DA_SHIFT (0u) + +#define DMAC4_N0TB_n_TB_SHIFT (0u) + +#define DMAC4_N1SA_n_SA_SHIFT (0u) + +#define DMAC4_N1DA_n_DA_SHIFT (0u) + +#define DMAC4_N1TB_n_TB_SHIFT (0u) + +#define DMAC4_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC4_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC4_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC4_CHSTAT_n_EN_SHIFT (0u) +#define DMAC4_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC4_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC4_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC4_CHSTAT_n_ER_SHIFT (4u) +#define DMAC4_CHSTAT_n_END_SHIFT (5u) +#define DMAC4_CHSTAT_n_TC_SHIFT (6u) +#define DMAC4_CHSTAT_n_SR_SHIFT (7u) +#define DMAC4_CHSTAT_n_DL_SHIFT (8u) +#define DMAC4_CHSTAT_n_DW_SHIFT (9u) +#define DMAC4_CHSTAT_n_DER_SHIFT (10u) +#define DMAC4_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC4_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC4_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC4_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC4_CHCTRL_n_STG_SHIFT (2u) +#define DMAC4_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC4_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC4_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC4_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC4_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC4_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC4_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC4_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC4_CHCFG_n_SEL_SHIFT (0u) +#define DMAC4_CHCFG_n_REQD_SHIFT (3u) +#define DMAC4_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC4_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC4_CHCFG_n_LVL_SHIFT (6u) +#define DMAC4_CHCFG_n_AM_SHIFT (8u) +#define DMAC4_CHCFG_n_SDS_SHIFT (12u) +#define DMAC4_CHCFG_n_DDS_SHIFT (16u) +#define DMAC4_CHCFG_n_SAD_SHIFT (20u) +#define DMAC4_CHCFG_n_DAD_SHIFT (21u) +#define DMAC4_CHCFG_n_TM_SHIFT (22u) +#define DMAC4_CHCFG_n_DEM_SHIFT (24u) +#define DMAC4_CHCFG_n_TCM_SHIFT (25u) +#define DMAC4_CHCFG_n_SBE_SHIFT (27u) +#define DMAC4_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC4_CHCFG_n_RSW_SHIFT (29u) +#define DMAC4_CHCFG_n_REN_SHIFT (30u) +#define DMAC4_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC4_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC4_CHEXT_n_SCA_SHIFT (4u) +#define DMAC4_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC4_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC4_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC5 ---- */ +#define DMAC5_N0SA_n_SA_SHIFT (0u) + +#define DMAC5_N0DA_n_DA_SHIFT (0u) + +#define DMAC5_N0TB_n_TB_SHIFT (0u) + +#define DMAC5_N1SA_n_SA_SHIFT (0u) + +#define DMAC5_N1DA_n_DA_SHIFT (0u) + +#define DMAC5_N1TB_n_TB_SHIFT (0u) + +#define DMAC5_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC5_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC5_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC5_CHSTAT_n_EN_SHIFT (0u) +#define DMAC5_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC5_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC5_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC5_CHSTAT_n_ER_SHIFT (4u) +#define DMAC5_CHSTAT_n_END_SHIFT (5u) +#define DMAC5_CHSTAT_n_TC_SHIFT (6u) +#define DMAC5_CHSTAT_n_SR_SHIFT (7u) +#define DMAC5_CHSTAT_n_DL_SHIFT (8u) +#define DMAC5_CHSTAT_n_DW_SHIFT (9u) +#define DMAC5_CHSTAT_n_DER_SHIFT (10u) +#define DMAC5_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC5_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC5_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC5_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC5_CHCTRL_n_STG_SHIFT (2u) +#define DMAC5_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC5_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC5_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC5_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC5_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC5_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC5_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC5_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC5_CHCFG_n_SEL_SHIFT (0u) +#define DMAC5_CHCFG_n_REQD_SHIFT (3u) +#define DMAC5_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC5_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC5_CHCFG_n_LVL_SHIFT (6u) +#define DMAC5_CHCFG_n_AM_SHIFT (8u) +#define DMAC5_CHCFG_n_SDS_SHIFT (12u) +#define DMAC5_CHCFG_n_DDS_SHIFT (16u) +#define DMAC5_CHCFG_n_SAD_SHIFT (20u) +#define DMAC5_CHCFG_n_DAD_SHIFT (21u) +#define DMAC5_CHCFG_n_TM_SHIFT (22u) +#define DMAC5_CHCFG_n_DEM_SHIFT (24u) +#define DMAC5_CHCFG_n_TCM_SHIFT (25u) +#define DMAC5_CHCFG_n_SBE_SHIFT (27u) +#define DMAC5_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC5_CHCFG_n_RSW_SHIFT (29u) +#define DMAC5_CHCFG_n_REN_SHIFT (30u) +#define DMAC5_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC5_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC5_CHEXT_n_SCA_SHIFT (4u) +#define DMAC5_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC5_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC5_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC6 ---- */ +#define DMAC6_N0SA_n_SA_SHIFT (0u) + +#define DMAC6_N0DA_n_DA_SHIFT (0u) + +#define DMAC6_N0TB_n_TB_SHIFT (0u) + +#define DMAC6_N1SA_n_SA_SHIFT (0u) + +#define DMAC6_N1DA_n_DA_SHIFT (0u) + +#define DMAC6_N1TB_n_TB_SHIFT (0u) + +#define DMAC6_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC6_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC6_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC6_CHSTAT_n_EN_SHIFT (0u) +#define DMAC6_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC6_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC6_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC6_CHSTAT_n_ER_SHIFT (4u) +#define DMAC6_CHSTAT_n_END_SHIFT (5u) +#define DMAC6_CHSTAT_n_TC_SHIFT (6u) +#define DMAC6_CHSTAT_n_SR_SHIFT (7u) +#define DMAC6_CHSTAT_n_DL_SHIFT (8u) +#define DMAC6_CHSTAT_n_DW_SHIFT (9u) +#define DMAC6_CHSTAT_n_DER_SHIFT (10u) +#define DMAC6_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC6_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC6_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC6_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC6_CHCTRL_n_STG_SHIFT (2u) +#define DMAC6_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC6_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC6_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC6_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC6_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC6_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC6_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC6_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC6_CHCFG_n_SEL_SHIFT (0u) +#define DMAC6_CHCFG_n_REQD_SHIFT (3u) +#define DMAC6_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC6_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC6_CHCFG_n_LVL_SHIFT (6u) +#define DMAC6_CHCFG_n_AM_SHIFT (8u) +#define DMAC6_CHCFG_n_SDS_SHIFT (12u) +#define DMAC6_CHCFG_n_DDS_SHIFT (16u) +#define DMAC6_CHCFG_n_SAD_SHIFT (20u) +#define DMAC6_CHCFG_n_DAD_SHIFT (21u) +#define DMAC6_CHCFG_n_TM_SHIFT (22u) +#define DMAC6_CHCFG_n_DEM_SHIFT (24u) +#define DMAC6_CHCFG_n_TCM_SHIFT (25u) +#define DMAC6_CHCFG_n_SBE_SHIFT (27u) +#define DMAC6_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC6_CHCFG_n_RSW_SHIFT (29u) +#define DMAC6_CHCFG_n_REN_SHIFT (30u) +#define DMAC6_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC6_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC6_CHEXT_n_SCA_SHIFT (4u) +#define DMAC6_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC6_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC6_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC7 ---- */ +#define DMAC7_N0SA_n_SA_SHIFT (0u) + +#define DMAC7_N0DA_n_DA_SHIFT (0u) + +#define DMAC7_N0TB_n_TB_SHIFT (0u) + +#define DMAC7_N1SA_n_SA_SHIFT (0u) + +#define DMAC7_N1DA_n_DA_SHIFT (0u) + +#define DMAC7_N1TB_n_TB_SHIFT (0u) + +#define DMAC7_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC7_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC7_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC7_CHSTAT_n_EN_SHIFT (0u) +#define DMAC7_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC7_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC7_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC7_CHSTAT_n_ER_SHIFT (4u) +#define DMAC7_CHSTAT_n_END_SHIFT (5u) +#define DMAC7_CHSTAT_n_TC_SHIFT (6u) +#define DMAC7_CHSTAT_n_SR_SHIFT (7u) +#define DMAC7_CHSTAT_n_DL_SHIFT (8u) +#define DMAC7_CHSTAT_n_DW_SHIFT (9u) +#define DMAC7_CHSTAT_n_DER_SHIFT (10u) +#define DMAC7_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC7_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC7_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC7_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC7_CHCTRL_n_STG_SHIFT (2u) +#define DMAC7_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC7_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC7_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC7_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC7_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC7_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC7_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC7_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC7_CHCFG_n_SEL_SHIFT (0u) +#define DMAC7_CHCFG_n_REQD_SHIFT (3u) +#define DMAC7_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC7_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC7_CHCFG_n_LVL_SHIFT (6u) +#define DMAC7_CHCFG_n_AM_SHIFT (8u) +#define DMAC7_CHCFG_n_SDS_SHIFT (12u) +#define DMAC7_CHCFG_n_DDS_SHIFT (16u) +#define DMAC7_CHCFG_n_SAD_SHIFT (20u) +#define DMAC7_CHCFG_n_DAD_SHIFT (21u) +#define DMAC7_CHCFG_n_TM_SHIFT (22u) +#define DMAC7_CHCFG_n_DEM_SHIFT (24u) +#define DMAC7_CHCFG_n_TCM_SHIFT (25u) +#define DMAC7_CHCFG_n_SBE_SHIFT (27u) +#define DMAC7_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC7_CHCFG_n_RSW_SHIFT (29u) +#define DMAC7_CHCFG_n_REN_SHIFT (30u) +#define DMAC7_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC7_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC7_CHEXT_n_SCA_SHIFT (4u) +#define DMAC7_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC7_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC7_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC0-7 ---- */ +#define DMAC07_DCTRL_0_7_PR_SHIFT (0u) +#define DMAC07_DCTRL_0_7_LVINT_SHIFT (1u) +#define DMAC07_DCTRL_0_7_LDCA_SHIFT (2u) +#define DMAC07_DCTRL_0_7_LWCA_SHIFT (6u) + +#define DMAC07_DSTAT_EN_0_7_EN0_SHIFT (0u) +#define DMAC07_DSTAT_EN_0_7_EN1_SHIFT (1u) +#define DMAC07_DSTAT_EN_0_7_EN2_SHIFT (2u) +#define DMAC07_DSTAT_EN_0_7_EN3_SHIFT (3u) +#define DMAC07_DSTAT_EN_0_7_EN4_SHIFT (4u) +#define DMAC07_DSTAT_EN_0_7_EN5_SHIFT (5u) +#define DMAC07_DSTAT_EN_0_7_EN6_SHIFT (6u) +#define DMAC07_DSTAT_EN_0_7_EN7_SHIFT (7u) + +#define DMAC07_DSTAT_ER_0_7_ER0_SHIFT (0u) +#define DMAC07_DSTAT_ER_0_7_ER1_SHIFT (1u) +#define DMAC07_DSTAT_ER_0_7_ER2_SHIFT (2u) +#define DMAC07_DSTAT_ER_0_7_ER3_SHIFT (3u) +#define DMAC07_DSTAT_ER_0_7_ER4_SHIFT (4u) +#define DMAC07_DSTAT_ER_0_7_ER5_SHIFT (5u) +#define DMAC07_DSTAT_ER_0_7_ER6_SHIFT (6u) +#define DMAC07_DSTAT_ER_0_7_ER7_SHIFT (7u) + +#define DMAC07_DSTAT_END_0_7_END0_SHIFT (0u) +#define DMAC07_DSTAT_END_0_7_END1_SHIFT (1u) +#define DMAC07_DSTAT_END_0_7_END2_SHIFT (2u) +#define DMAC07_DSTAT_END_0_7_END3_SHIFT (3u) +#define DMAC07_DSTAT_END_0_7_END4_SHIFT (4u) +#define DMAC07_DSTAT_END_0_7_END5_SHIFT (5u) +#define DMAC07_DSTAT_END_0_7_END6_SHIFT (6u) +#define DMAC07_DSTAT_END_0_7_END7_SHIFT (7u) + +#define DMAC07_DSTAT_TC_0_7_TC0_SHIFT (0u) +#define DMAC07_DSTAT_TC_0_7_TC1_SHIFT (1u) +#define DMAC07_DSTAT_TC_0_7_TC2_SHIFT (2u) +#define DMAC07_DSTAT_TC_0_7_TC3_SHIFT (3u) +#define DMAC07_DSTAT_TC_0_7_TC4_SHIFT (4u) +#define DMAC07_DSTAT_TC_0_7_TC5_SHIFT (5u) +#define DMAC07_DSTAT_TC_0_7_TC6_SHIFT (6u) +#define DMAC07_DSTAT_TC_0_7_TC7_SHIFT (7u) + +#define DMAC07_DSTAT_SUS_0_7_SUS0_SHIFT (0u) +#define DMAC07_DSTAT_SUS_0_7_SUS1_SHIFT (1u) +#define DMAC07_DSTAT_SUS_0_7_SUS2_SHIFT (2u) +#define DMAC07_DSTAT_SUS_0_7_SUS3_SHIFT (3u) +#define DMAC07_DSTAT_SUS_0_7_SUS4_SHIFT (4u) +#define DMAC07_DSTAT_SUS_0_7_SUS5_SHIFT (5u) +#define DMAC07_DSTAT_SUS_0_7_SUS6_SHIFT (6u) +#define DMAC07_DSTAT_SUS_0_7_SUS7_SHIFT (7u) + +/* ---- DMAC8 ---- */ +#define DMAC8_N0SA_n_SA_SHIFT (0u) + +#define DMAC8_N0DA_n_DA_SHIFT (0u) + +#define DMAC8_N0TB_n_TB_SHIFT (0u) + +#define DMAC8_N1SA_n_SA_SHIFT (0u) + +#define DMAC8_N1DA_n_DA_SHIFT (0u) + +#define DMAC8_N1TB_n_TB_SHIFT (0u) + +#define DMAC8_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC8_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC8_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC8_CHSTAT_n_EN_SHIFT (0u) +#define DMAC8_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC8_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC8_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC8_CHSTAT_n_ER_SHIFT (4u) +#define DMAC8_CHSTAT_n_END_SHIFT (5u) +#define DMAC8_CHSTAT_n_TC_SHIFT (6u) +#define DMAC8_CHSTAT_n_SR_SHIFT (7u) +#define DMAC8_CHSTAT_n_DL_SHIFT (8u) +#define DMAC8_CHSTAT_n_DW_SHIFT (9u) +#define DMAC8_CHSTAT_n_DER_SHIFT (10u) +#define DMAC8_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC8_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC8_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC8_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC8_CHCTRL_n_STG_SHIFT (2u) +#define DMAC8_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC8_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC8_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC8_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC8_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC8_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC8_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC8_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC8_CHCFG_n_SEL_SHIFT (0u) +#define DMAC8_CHCFG_n_REQD_SHIFT (3u) +#define DMAC8_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC8_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC8_CHCFG_n_LVL_SHIFT (6u) +#define DMAC8_CHCFG_n_AM_SHIFT (8u) +#define DMAC8_CHCFG_n_SDS_SHIFT (12u) +#define DMAC8_CHCFG_n_DDS_SHIFT (16u) +#define DMAC8_CHCFG_n_SAD_SHIFT (20u) +#define DMAC8_CHCFG_n_DAD_SHIFT (21u) +#define DMAC8_CHCFG_n_TM_SHIFT (22u) +#define DMAC8_CHCFG_n_DEM_SHIFT (24u) +#define DMAC8_CHCFG_n_TCM_SHIFT (25u) +#define DMAC8_CHCFG_n_SBE_SHIFT (27u) +#define DMAC8_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC8_CHCFG_n_RSW_SHIFT (29u) +#define DMAC8_CHCFG_n_REN_SHIFT (30u) +#define DMAC8_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC8_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC8_CHEXT_n_SCA_SHIFT (4u) +#define DMAC8_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC8_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC8_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC9 ---- */ +#define DMAC9_N0SA_n_SA_SHIFT (0u) + +#define DMAC9_N0DA_n_DA_SHIFT (0u) + +#define DMAC9_N0TB_n_TB_SHIFT (0u) + +#define DMAC9_N1SA_n_SA_SHIFT (0u) + +#define DMAC9_N1DA_n_DA_SHIFT (0u) + +#define DMAC9_N1TB_n_TB_SHIFT (0u) + +#define DMAC9_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC9_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC9_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC9_CHSTAT_n_EN_SHIFT (0u) +#define DMAC9_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC9_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC9_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC9_CHSTAT_n_ER_SHIFT (4u) +#define DMAC9_CHSTAT_n_END_SHIFT (5u) +#define DMAC9_CHSTAT_n_TC_SHIFT (6u) +#define DMAC9_CHSTAT_n_SR_SHIFT (7u) +#define DMAC9_CHSTAT_n_DL_SHIFT (8u) +#define DMAC9_CHSTAT_n_DW_SHIFT (9u) +#define DMAC9_CHSTAT_n_DER_SHIFT (10u) +#define DMAC9_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC9_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC9_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC9_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC9_CHCTRL_n_STG_SHIFT (2u) +#define DMAC9_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC9_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC9_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC9_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC9_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC9_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC9_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC9_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC9_CHCFG_n_SEL_SHIFT (0u) +#define DMAC9_CHCFG_n_REQD_SHIFT (3u) +#define DMAC9_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC9_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC9_CHCFG_n_LVL_SHIFT (6u) +#define DMAC9_CHCFG_n_AM_SHIFT (8u) +#define DMAC9_CHCFG_n_SDS_SHIFT (12u) +#define DMAC9_CHCFG_n_DDS_SHIFT (16u) +#define DMAC9_CHCFG_n_SAD_SHIFT (20u) +#define DMAC9_CHCFG_n_DAD_SHIFT (21u) +#define DMAC9_CHCFG_n_TM_SHIFT (22u) +#define DMAC9_CHCFG_n_DEM_SHIFT (24u) +#define DMAC9_CHCFG_n_TCM_SHIFT (25u) +#define DMAC9_CHCFG_n_SBE_SHIFT (27u) +#define DMAC9_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC9_CHCFG_n_RSW_SHIFT (29u) +#define DMAC9_CHCFG_n_REN_SHIFT (30u) +#define DMAC9_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC9_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC9_CHEXT_n_SCA_SHIFT (4u) +#define DMAC9_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC9_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC9_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC10 ---- */ +#define DMAC10_N0SA_n_SA_SHIFT (0u) + +#define DMAC10_N0DA_n_DA_SHIFT (0u) + +#define DMAC10_N0TB_n_TB_SHIFT (0u) + +#define DMAC10_N1SA_n_SA_SHIFT (0u) + +#define DMAC10_N1DA_n_DA_SHIFT (0u) + +#define DMAC10_N1TB_n_TB_SHIFT (0u) + +#define DMAC10_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC10_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC10_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC10_CHSTAT_n_EN_SHIFT (0u) +#define DMAC10_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC10_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC10_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC10_CHSTAT_n_ER_SHIFT (4u) +#define DMAC10_CHSTAT_n_END_SHIFT (5u) +#define DMAC10_CHSTAT_n_TC_SHIFT (6u) +#define DMAC10_CHSTAT_n_SR_SHIFT (7u) +#define DMAC10_CHSTAT_n_DL_SHIFT (8u) +#define DMAC10_CHSTAT_n_DW_SHIFT (9u) +#define DMAC10_CHSTAT_n_DER_SHIFT (10u) +#define DMAC10_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC10_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC10_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC10_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC10_CHCTRL_n_STG_SHIFT (2u) +#define DMAC10_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC10_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC10_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC10_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC10_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC10_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC10_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC10_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC10_CHCFG_n_SEL_SHIFT (0u) +#define DMAC10_CHCFG_n_REQD_SHIFT (3u) +#define DMAC10_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC10_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC10_CHCFG_n_LVL_SHIFT (6u) +#define DMAC10_CHCFG_n_AM_SHIFT (8u) +#define DMAC10_CHCFG_n_SDS_SHIFT (12u) +#define DMAC10_CHCFG_n_DDS_SHIFT (16u) +#define DMAC10_CHCFG_n_SAD_SHIFT (20u) +#define DMAC10_CHCFG_n_DAD_SHIFT (21u) +#define DMAC10_CHCFG_n_TM_SHIFT (22u) +#define DMAC10_CHCFG_n_DEM_SHIFT (24u) +#define DMAC10_CHCFG_n_TCM_SHIFT (25u) +#define DMAC10_CHCFG_n_SBE_SHIFT (27u) +#define DMAC10_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC10_CHCFG_n_RSW_SHIFT (29u) +#define DMAC10_CHCFG_n_REN_SHIFT (30u) +#define DMAC10_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC10_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC10_CHEXT_n_SCA_SHIFT (4u) +#define DMAC10_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC10_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC10_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC11 ---- */ +#define DMAC11_N0SA_n_SA_SHIFT (0u) + +#define DMAC11_N0DA_n_DA_SHIFT (0u) + +#define DMAC11_N0TB_n_TB_SHIFT (0u) + +#define DMAC11_N1SA_n_SA_SHIFT (0u) + +#define DMAC11_N1DA_n_DA_SHIFT (0u) + +#define DMAC11_N1TB_n_TB_SHIFT (0u) + +#define DMAC11_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC11_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC11_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC11_CHSTAT_n_EN_SHIFT (0u) +#define DMAC11_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC11_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC11_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC11_CHSTAT_n_ER_SHIFT (4u) +#define DMAC11_CHSTAT_n_END_SHIFT (5u) +#define DMAC11_CHSTAT_n_TC_SHIFT (6u) +#define DMAC11_CHSTAT_n_SR_SHIFT (7u) +#define DMAC11_CHSTAT_n_DL_SHIFT (8u) +#define DMAC11_CHSTAT_n_DW_SHIFT (9u) +#define DMAC11_CHSTAT_n_DER_SHIFT (10u) +#define DMAC11_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC11_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC11_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC11_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC11_CHCTRL_n_STG_SHIFT (2u) +#define DMAC11_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC11_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC11_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC11_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC11_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC11_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC11_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC11_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC11_CHCFG_n_SEL_SHIFT (0u) +#define DMAC11_CHCFG_n_REQD_SHIFT (3u) +#define DMAC11_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC11_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC11_CHCFG_n_LVL_SHIFT (6u) +#define DMAC11_CHCFG_n_AM_SHIFT (8u) +#define DMAC11_CHCFG_n_SDS_SHIFT (12u) +#define DMAC11_CHCFG_n_DDS_SHIFT (16u) +#define DMAC11_CHCFG_n_SAD_SHIFT (20u) +#define DMAC11_CHCFG_n_DAD_SHIFT (21u) +#define DMAC11_CHCFG_n_TM_SHIFT (22u) +#define DMAC11_CHCFG_n_DEM_SHIFT (24u) +#define DMAC11_CHCFG_n_TCM_SHIFT (25u) +#define DMAC11_CHCFG_n_SBE_SHIFT (27u) +#define DMAC11_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC11_CHCFG_n_RSW_SHIFT (29u) +#define DMAC11_CHCFG_n_REN_SHIFT (30u) +#define DMAC11_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC11_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC11_CHEXT_n_SCA_SHIFT (4u) +#define DMAC11_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC11_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC11_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC12 ---- */ +#define DMAC12_N0SA_n_SA_SHIFT (0u) + +#define DMAC12_N0DA_n_DA_SHIFT (0u) + +#define DMAC12_N0TB_n_TB_SHIFT (0u) + +#define DMAC12_N1SA_n_SA_SHIFT (0u) + +#define DMAC12_N1DA_n_DA_SHIFT (0u) + +#define DMAC12_N1TB_n_TB_SHIFT (0u) + +#define DMAC12_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC12_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC12_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC12_CHSTAT_n_EN_SHIFT (0u) +#define DMAC12_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC12_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC12_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC12_CHSTAT_n_ER_SHIFT (4u) +#define DMAC12_CHSTAT_n_END_SHIFT (5u) +#define DMAC12_CHSTAT_n_TC_SHIFT (6u) +#define DMAC12_CHSTAT_n_SR_SHIFT (7u) +#define DMAC12_CHSTAT_n_DL_SHIFT (8u) +#define DMAC12_CHSTAT_n_DW_SHIFT (9u) +#define DMAC12_CHSTAT_n_DER_SHIFT (10u) +#define DMAC12_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC12_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC12_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC12_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC12_CHCTRL_n_STG_SHIFT (2u) +#define DMAC12_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC12_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC12_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC12_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC12_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC12_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC12_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC12_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC12_CHCFG_n_SEL_SHIFT (0u) +#define DMAC12_CHCFG_n_REQD_SHIFT (3u) +#define DMAC12_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC12_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC12_CHCFG_n_LVL_SHIFT (6u) +#define DMAC12_CHCFG_n_AM_SHIFT (8u) +#define DMAC12_CHCFG_n_SDS_SHIFT (12u) +#define DMAC12_CHCFG_n_DDS_SHIFT (16u) +#define DMAC12_CHCFG_n_SAD_SHIFT (20u) +#define DMAC12_CHCFG_n_DAD_SHIFT (21u) +#define DMAC12_CHCFG_n_TM_SHIFT (22u) +#define DMAC12_CHCFG_n_DEM_SHIFT (24u) +#define DMAC12_CHCFG_n_TCM_SHIFT (25u) +#define DMAC12_CHCFG_n_SBE_SHIFT (27u) +#define DMAC12_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC12_CHCFG_n_RSW_SHIFT (29u) +#define DMAC12_CHCFG_n_REN_SHIFT (30u) +#define DMAC12_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC12_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC12_CHEXT_n_SCA_SHIFT (4u) +#define DMAC12_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC12_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC12_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC13 ---- */ +#define DMAC13_N0SA_n_SA_SHIFT (0u) + +#define DMAC13_N0DA_n_DA_SHIFT (0u) + +#define DMAC13_N0TB_n_TB_SHIFT (0u) + +#define DMAC13_N1SA_n_SA_SHIFT (0u) + +#define DMAC13_N1DA_n_DA_SHIFT (0u) + +#define DMAC13_N1TB_n_TB_SHIFT (0u) + +#define DMAC13_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC13_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC13_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC13_CHSTAT_n_EN_SHIFT (0u) +#define DMAC13_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC13_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC13_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC13_CHSTAT_n_ER_SHIFT (4u) +#define DMAC13_CHSTAT_n_END_SHIFT (5u) +#define DMAC13_CHSTAT_n_TC_SHIFT (6u) +#define DMAC13_CHSTAT_n_SR_SHIFT (7u) +#define DMAC13_CHSTAT_n_DL_SHIFT (8u) +#define DMAC13_CHSTAT_n_DW_SHIFT (9u) +#define DMAC13_CHSTAT_n_DER_SHIFT (10u) +#define DMAC13_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC13_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC13_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC13_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC13_CHCTRL_n_STG_SHIFT (2u) +#define DMAC13_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC13_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC13_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC13_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC13_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC13_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC13_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC13_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC13_CHCFG_n_SEL_SHIFT (0u) +#define DMAC13_CHCFG_n_REQD_SHIFT (3u) +#define DMAC13_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC13_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC13_CHCFG_n_LVL_SHIFT (6u) +#define DMAC13_CHCFG_n_AM_SHIFT (8u) +#define DMAC13_CHCFG_n_SDS_SHIFT (12u) +#define DMAC13_CHCFG_n_DDS_SHIFT (16u) +#define DMAC13_CHCFG_n_SAD_SHIFT (20u) +#define DMAC13_CHCFG_n_DAD_SHIFT (21u) +#define DMAC13_CHCFG_n_TM_SHIFT (22u) +#define DMAC13_CHCFG_n_DEM_SHIFT (24u) +#define DMAC13_CHCFG_n_TCM_SHIFT (25u) +#define DMAC13_CHCFG_n_SBE_SHIFT (27u) +#define DMAC13_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC13_CHCFG_n_RSW_SHIFT (29u) +#define DMAC13_CHCFG_n_REN_SHIFT (30u) +#define DMAC13_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC13_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC13_CHEXT_n_SCA_SHIFT (4u) +#define DMAC13_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC13_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC13_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC14 ---- */ +#define DMAC14_N0SA_n_SA_SHIFT (0u) + +#define DMAC14_N0DA_n_DA_SHIFT (0u) + +#define DMAC14_N0TB_n_TB_SHIFT (0u) + +#define DMAC14_N1SA_n_SA_SHIFT (0u) + +#define DMAC14_N1DA_n_DA_SHIFT (0u) + +#define DMAC14_N1TB_n_TB_SHIFT (0u) + +#define DMAC14_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC14_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC14_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC14_CHSTAT_n_EN_SHIFT (0u) +#define DMAC14_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC14_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC14_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC14_CHSTAT_n_ER_SHIFT (4u) +#define DMAC14_CHSTAT_n_END_SHIFT (5u) +#define DMAC14_CHSTAT_n_TC_SHIFT (6u) +#define DMAC14_CHSTAT_n_SR_SHIFT (7u) +#define DMAC14_CHSTAT_n_DL_SHIFT (8u) +#define DMAC14_CHSTAT_n_DW_SHIFT (9u) +#define DMAC14_CHSTAT_n_DER_SHIFT (10u) +#define DMAC14_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC14_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC14_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC14_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC14_CHCTRL_n_STG_SHIFT (2u) +#define DMAC14_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC14_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC14_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC14_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC14_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC14_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC14_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC14_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC14_CHCFG_n_SEL_SHIFT (0u) +#define DMAC14_CHCFG_n_REQD_SHIFT (3u) +#define DMAC14_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC14_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC14_CHCFG_n_LVL_SHIFT (6u) +#define DMAC14_CHCFG_n_AM_SHIFT (8u) +#define DMAC14_CHCFG_n_SDS_SHIFT (12u) +#define DMAC14_CHCFG_n_DDS_SHIFT (16u) +#define DMAC14_CHCFG_n_SAD_SHIFT (20u) +#define DMAC14_CHCFG_n_DAD_SHIFT (21u) +#define DMAC14_CHCFG_n_TM_SHIFT (22u) +#define DMAC14_CHCFG_n_DEM_SHIFT (24u) +#define DMAC14_CHCFG_n_TCM_SHIFT (25u) +#define DMAC14_CHCFG_n_SBE_SHIFT (27u) +#define DMAC14_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC14_CHCFG_n_RSW_SHIFT (29u) +#define DMAC14_CHCFG_n_REN_SHIFT (30u) +#define DMAC14_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC14_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC14_CHEXT_n_SCA_SHIFT (4u) +#define DMAC14_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC14_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC14_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC15 ---- */ +#define DMAC15_N0SA_n_SA_SHIFT (0u) + +#define DMAC15_N0DA_n_DA_SHIFT (0u) + +#define DMAC15_N0TB_n_TB_SHIFT (0u) + +#define DMAC15_N1SA_n_SA_SHIFT (0u) + +#define DMAC15_N1DA_n_DA_SHIFT (0u) + +#define DMAC15_N1TB_n_TB_SHIFT (0u) + +#define DMAC15_CRSA_n_CRSA_SHIFT (0u) + +#define DMAC15_CRDA_n_CRDA_SHIFT (0u) + +#define DMAC15_CRTB_n_CRTB_SHIFT (0u) + +#define DMAC15_CHSTAT_n_EN_SHIFT (0u) +#define DMAC15_CHSTAT_n_RQST_SHIFT (1u) +#define DMAC15_CHSTAT_n_TACT_SHIFT (2u) +#define DMAC15_CHSTAT_n_SUS_SHIFT (3u) +#define DMAC15_CHSTAT_n_ER_SHIFT (4u) +#define DMAC15_CHSTAT_n_END_SHIFT (5u) +#define DMAC15_CHSTAT_n_TC_SHIFT (6u) +#define DMAC15_CHSTAT_n_SR_SHIFT (7u) +#define DMAC15_CHSTAT_n_DL_SHIFT (8u) +#define DMAC15_CHSTAT_n_DW_SHIFT (9u) +#define DMAC15_CHSTAT_n_DER_SHIFT (10u) +#define DMAC15_CHSTAT_n_MODE_SHIFT (11u) +#define DMAC15_CHSTAT_n_INTMSK_SHIFT (16u) + +#define DMAC15_CHCTRL_n_SETEN_SHIFT (0u) +#define DMAC15_CHCTRL_n_CLREN_SHIFT (1u) +#define DMAC15_CHCTRL_n_STG_SHIFT (2u) +#define DMAC15_CHCTRL_n_SWRST_SHIFT (3u) +#define DMAC15_CHCTRL_n_CLRRQ_SHIFT (4u) +#define DMAC15_CHCTRL_n_CLREND_SHIFT (5u) +#define DMAC15_CHCTRL_n_CLRTC_SHIFT (6u) +#define DMAC15_CHCTRL_n_SETSUS_SHIFT (8u) +#define DMAC15_CHCTRL_n_CLRSUS_SHIFT (9u) +#define DMAC15_CHCTRL_n_SETINTMSK_SHIFT (16u) +#define DMAC15_CHCTRL_n_CLRINTMSK_SHIFT (17u) + +#define DMAC15_CHCFG_n_SEL_SHIFT (0u) +#define DMAC15_CHCFG_n_REQD_SHIFT (3u) +#define DMAC15_CHCFG_n_LOEN_SHIFT (4u) +#define DMAC15_CHCFG_n_HIEN_SHIFT (5u) +#define DMAC15_CHCFG_n_LVL_SHIFT (6u) +#define DMAC15_CHCFG_n_AM_SHIFT (8u) +#define DMAC15_CHCFG_n_SDS_SHIFT (12u) +#define DMAC15_CHCFG_n_DDS_SHIFT (16u) +#define DMAC15_CHCFG_n_SAD_SHIFT (20u) +#define DMAC15_CHCFG_n_DAD_SHIFT (21u) +#define DMAC15_CHCFG_n_TM_SHIFT (22u) +#define DMAC15_CHCFG_n_DEM_SHIFT (24u) +#define DMAC15_CHCFG_n_TCM_SHIFT (25u) +#define DMAC15_CHCFG_n_SBE_SHIFT (27u) +#define DMAC15_CHCFG_n_RSEL_SHIFT (28u) +#define DMAC15_CHCFG_n_RSW_SHIFT (29u) +#define DMAC15_CHCFG_n_REN_SHIFT (30u) +#define DMAC15_CHCFG_n_DMS_SHIFT (31u) + +#define DMAC15_CHITVL_n_ITVL_SHIFT (0u) + +#define DMAC15_CHEXT_n_SCA_SHIFT (4u) +#define DMAC15_CHEXT_n_DCA_SHIFT (12u) + +#define DMAC15_NXLA_n_NXLA_SHIFT (0u) + +#define DMAC15_CRLA_n_CRLA_SHIFT (0u) + +/* ---- DMAC8-15 ---- */ +#define DMAC815_DCTRL_8_15_PR_SHIFT (0u) +#define DMAC815_DCTRL_8_15_LVINT_SHIFT (1u) +#define DMAC815_DCTRL_8_15_LDCA_SHIFT (2u) +#define DMAC815_DCTRL_8_15_LWCA_SHIFT (10u) + +#define DMAC815_DSTAT_EN_8_15_EN8_SHIFT (0u) +#define DMAC815_DSTAT_EN_8_15_EN9_SHIFT (1u) +#define DMAC815_DSTAT_EN_8_15_EN10_SHIFT (2u) +#define DMAC815_DSTAT_EN_8_15_EN11_SHIFT (3u) +#define DMAC815_DSTAT_EN_8_15_EN12_SHIFT (4u) +#define DMAC815_DSTAT_EN_8_15_EN13_SHIFT (5u) +#define DMAC815_DSTAT_EN_8_15_EN14_SHIFT (6u) +#define DMAC815_DSTAT_EN_8_15_EN15_SHIFT (7u) + +#define DMAC815_DSTAT_ER_8_15_ER8_SHIFT (0u) +#define DMAC815_DSTAT_ER_8_15_ER9_SHIFT (1u) +#define DMAC815_DSTAT_ER_8_15_ER10_SHIFT (2u) +#define DMAC815_DSTAT_ER_8_15_ER11_SHIFT (3u) +#define DMAC815_DSTAT_ER_8_15_ER12_SHIFT (4u) +#define DMAC815_DSTAT_ER_8_15_ER13_SHIFT (5u) +#define DMAC815_DSTAT_ER_8_15_ER14_SHIFT (6u) +#define DMAC815_DSTAT_ER_8_15_ER15_SHIFT (7u) + +#define DMAC815_DSTAT_END_8_15_END8_SHIFT (0u) +#define DMAC815_DSTAT_END_8_15_END9_SHIFT (1u) +#define DMAC815_DSTAT_END_8_15_END10_SHIFT (2u) +#define DMAC815_DSTAT_END_8_15_END11_SHIFT (3u) +#define DMAC815_DSTAT_END_8_15_END12_SHIFT (4u) +#define DMAC815_DSTAT_END_8_15_END13_SHIFT (5u) +#define DMAC815_DSTAT_END_8_15_END14_SHIFT (6u) +#define DMAC815_DSTAT_END_8_15_END15_SHIFT (7u) + +#define DMAC815_DSTAT_TC_8_15_TC8_SHIFT (0u) +#define DMAC815_DSTAT_TC_8_15_TC9_SHIFT (1u) +#define DMAC815_DSTAT_TC_8_15_TC10_SHIFT (2u) +#define DMAC815_DSTAT_TC_8_15_TC11_SHIFT (3u) +#define DMAC815_DSTAT_TC_8_15_TC12_SHIFT (4u) +#define DMAC815_DSTAT_TC_8_15_TC13_SHIFT (5u) +#define DMAC815_DSTAT_TC_8_15_TC14_SHIFT (6u) +#define DMAC815_DSTAT_TC_8_15_TC15_SHIFT (7u) + +#define DMAC815_DSTAT_SUS_8_15_SUS8_SHIFT (0u) +#define DMAC815_DSTAT_SUS_8_15_SUS9_SHIFT (1u) +#define DMAC815_DSTAT_SUS_8_15_SUS10_SHIFT (2u) +#define DMAC815_DSTAT_SUS_8_15_SUS11_SHIFT (3u) +#define DMAC815_DSTAT_SUS_8_15_SUS12_SHIFT (4u) +#define DMAC815_DSTAT_SUS_8_15_SUS13_SHIFT (5u) +#define DMAC815_DSTAT_SUS_8_15_SUS14_SHIFT (6u) +#define DMAC815_DSTAT_SUS_8_15_SUS15_SHIFT (7u) + +/* ---- DMAC0-1 ---- */ +#define DMAC01_DMARS_CH0_RID_SHIFT (0u) +#define DMAC01_DMARS_CH0_MID_SHIFT (2u) +#define DMAC01_DMARS_CH1_RID_SHIFT (16u) +#define DMAC01_DMARS_CH1_MID_SHIFT (18u) + +/* ---- DMAC2-3 ---- */ +#define DMAC23_DMARS_CH2_RID_SHIFT (0u) +#define DMAC23_DMARS_CH2_MID_SHIFT (2u) +#define DMAC23_DMARS_CH3_RID_SHIFT (16u) +#define DMAC23_DMARS_CH3_MID_SHIFT (18u) + +/* ---- DMAC4-5 ---- */ +#define DMAC45_DMARS_CH4_RID_SHIFT (0u) +#define DMAC45_DMARS_CH4_MID_SHIFT (2u) +#define DMAC45_DMARS_CH5_RID_SHIFT (16u) +#define DMAC45_DMARS_CH5_MID_SHIFT (18u) + +/* ---- DMAC6-7 ---- */ +#define DMAC67_DMARS_CH6_RID_SHIFT (0u) +#define DMAC67_DMARS_CH6_MID_SHIFT (2u) +#define DMAC67_DMARS_CH7_RID_SHIFT (16u) +#define DMAC67_DMARS_CH7_MID_SHIFT (18u) + +/* ---- DMAC8-9 ---- */ +#define DMAC89_DMARS_CH8_RID_SHIFT (0u) +#define DMAC89_DMARS_CH8_MID_SHIFT (2u) +#define DMAC89_DMARS_CH9_RID_SHIFT (16u) +#define DMAC89_DMARS_CH9_MID_SHIFT (18u) + +/* ---- DMAC10-11 ---- */ +#define DMAC1011_DMARS_CH10_RID_SHIFT (0u) +#define DMAC1011_DMARS_CH10_MID_SHIFT (2u) +#define DMAC1011_DMARS_CH11_RID_SHIFT (16u) +#define DMAC1011_DMARS_CH11_MID_SHIFT (18u) + +/* ---- DMAC12-13 ---- */ +#define DMAC1213_DMARS_CH12_RID_SHIFT (0u) +#define DMAC1213_DMARS_CH12_MID_SHIFT (2u) +#define DMAC1213_DMARS_CH13_RID_SHIFT (16u) +#define DMAC1213_DMARS_CH13_MID_SHIFT (18u) + +/* ---- DMAC14-15 ---- */ +#define DMAC1415_DMARS_CH14_RID_SHIFT (0u) +#define DMAC1415_DMARS_CH14_MID_SHIFT (2u) +#define DMAC1415_DMARS_CH15_RID_SHIFT (16u) +#define DMAC1415_DMARS_CH15_MID_SHIFT (18u) + + +#endif /* DMAC_IOBITMASK_H */ + +/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/gpio_iobitmask.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,5793 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : gpio_iobitmask.h +* $Rev: 1115 $ +* $Date:: 2014-07-09 15:35:02 +0900#$ +* Description : General purpose I/O ports register define header +*******************************************************************************/ +#ifndef GPIO_IOBITMASK_H +#define GPIO_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ +/* ---- P0 ---- */ +#define GPIO_PPR0_PPR00 (0x0001u) +#define GPIO_PPR0_PPR01 (0x0002u) +#define GPIO_PPR0_PPR02 (0x0004u) +#define GPIO_PPR0_PPR03 (0x0008u) +#define GPIO_PPR0_PPR04 (0x0010u) +#define GPIO_PPR0_PPR05 (0x0020u) + +#define GPIO_PMC0_PMC04 (0x0010u) +#define GPIO_PMC0_PMC05 (0x0020u) + +#define GPIO_PMCSR0_PMCSR04 (0x00000010uL) +#define GPIO_PMCSR0_PMCSR05 (0x00000020uL) + +#define GPIO_PIBC0_PIBC00 (0x0001u) +#define GPIO_PIBC0_PIBC01 (0x0002u) +#define GPIO_PIBC0_PIBC02 (0x0004u) +#define GPIO_PIBC0_PIBC03 (0x0008u) +#define GPIO_PIBC0_PIBC04 (0x0010u) +#define GPIO_PIBC0_PIBC05 (0x0020u) + +/* ---- P1 ---- */ +#define GPIO_P1_P10 (0x0001u) +#define GPIO_P1_P11 (0x0002u) +#define GPIO_P1_P12 (0x0004u) +#define GPIO_P1_P13 (0x0008u) +#define GPIO_P1_P14 (0x0010u) +#define GPIO_P1_P15 (0x0020u) +#define GPIO_P1_P16 (0x0040u) +#define GPIO_P1_P17 (0x0080u) + +#define GPIO_PSR1_PSR10 (0x00000001uL) +#define GPIO_PSR1_PSR11 (0x00000002uL) +#define GPIO_PSR1_PSR12 (0x00000004uL) +#define GPIO_PSR1_PSR13 (0x00000008uL) +#define GPIO_PSR1_PSR14 (0x00000010uL) +#define GPIO_PSR1_PSR15 (0x00000020uL) +#define GPIO_PSR1_PSR16 (0x00000040uL) +#define GPIO_PSR1_PSR17 (0x00000080uL) +#define GPIO_PSR1_PSR116 (0x00010000uL) +#define GPIO_PSR1_PSR117 (0x00020000uL) +#define GPIO_PSR1_PSR118 (0x00040000uL) +#define GPIO_PSR1_PSR119 (0x00080000uL) +#define GPIO_PSR1_PSR120 (0x00100000uL) +#define GPIO_PSR1_PSR121 (0x00200000uL) +#define GPIO_PSR1_PSR122 (0x00400000uL) +#define GPIO_PSR1_PSR123 (0x00800000uL) + +#define GPIO_PPR1_PPR10 (0x0001u) +#define GPIO_PPR1_PPR11 (0x0002u) +#define GPIO_PPR1_PPR12 (0x0004u) +#define GPIO_PPR1_PPR13 (0x0008u) +#define GPIO_PPR1_PPR14 (0x0010u) +#define GPIO_PPR1_PPR15 (0x0020u) +#define GPIO_PPR1_PPR16 (0x0040u) +#define GPIO_PPR1_PPR17 (0x0080u) +#define GPIO_PPR1_PPR18 (0x0100u) +#define GPIO_PPR1_PPR19 (0x0200u) +#define GPIO_PPR1_PPR110 (0x0400u) +#define GPIO_PPR1_PPR111 (0x0800u) +#define GPIO_PPR1_PPR112 (0x1000u) +#define GPIO_PPR1_PPR113 (0x2000u) +#define GPIO_PPR1_PPR114 (0x4000u) +#define GPIO_PPR1_PPR115 (0x8000u) + +#define GPIO_PM1_PM10 (0x0001u) +#define GPIO_PM1_PM11 (0x0002u) +#define GPIO_PM1_PM12 (0x0004u) +#define GPIO_PM1_PM13 (0x0008u) +#define GPIO_PM1_PM14 (0x0010u) +#define GPIO_PM1_PM15 (0x0020u) +#define GPIO_PM1_PM16 (0x0040u) +#define GPIO_PM1_PM17 (0x0080u) + +#define GPIO_PMC1_PMC10 (0x0001u) +#define GPIO_PMC1_PMC11 (0x0002u) +#define GPIO_PMC1_PMC12 (0x0004u) +#define GPIO_PMC1_PMC13 (0x0008u) +#define GPIO_PMC1_PMC14 (0x0010u) +#define GPIO_PMC1_PMC15 (0x0020u) +#define GPIO_PMC1_PMC16 (0x0040u) +#define GPIO_PMC1_PMC17 (0x0080u) +#define GPIO_PMC1_PMC18 (0x0100u) +#define GPIO_PMC1_PMC19 (0x0200u) +#define GPIO_PMC1_PMC110 (0x0400u) +#define GPIO_PMC1_PMC111 (0x0800u) +#define GPIO_PMC1_PMC112 (0x1000u) +#define GPIO_PMC1_PMC113 (0x2000u) +#define GPIO_PMC1_PMC114 (0x4000u) +#define GPIO_PMC1_PMC115 (0x8000u) + +#define GPIO_PFC1_PFC10 (0x0001u) +#define GPIO_PFC1_PFC11 (0x0002u) +#define GPIO_PFC1_PFC12 (0x0004u) +#define GPIO_PFC1_PFC13 (0x0008u) +#define GPIO_PFC1_PFC14 (0x0010u) +#define GPIO_PFC1_PFC15 (0x0020u) +#define GPIO_PFC1_PFC16 (0x0040u) +#define GPIO_PFC1_PFC17 (0x0080u) +#define GPIO_PFC1_PFC18 (0x0100u) +#define GPIO_PFC1_PFC19 (0x0200u) +#define GPIO_PFC1_PFC110 (0x0400u) +#define GPIO_PFC1_PFC111 (0x0800u) +#define GPIO_PFC1_PFC112 (0x1000u) +#define GPIO_PFC1_PFC113 (0x2000u) +#define GPIO_PFC1_PFC114 (0x4000u) +#define GPIO_PFC1_PFC115 (0x8000u) + +#define GPIO_PFCE1_PFCE10 (0x0001u) +#define GPIO_PFCE1_PFCE11 (0x0002u) +#define GPIO_PFCE1_PFCE12 (0x0004u) +#define GPIO_PFCE1_PFCE13 (0x0008u) +#define GPIO_PFCE1_PFCE14 (0x0010u) +#define GPIO_PFCE1_PFCE15 (0x0020u) +#define GPIO_PFCE1_PFCE16 (0x0040u) +#define GPIO_PFCE1_PFCE17 (0x0080u) +#define GPIO_PFCE1_PFCE18 (0x0100u) +#define GPIO_PFCE1_PFCE19 (0x0200u) +#define GPIO_PFCE1_PFCE110 (0x0400u) +#define GPIO_PFCE1_PFCE111 (0x0800u) +#define GPIO_PFCE1_PFCE112 (0x1000u) +#define GPIO_PFCE1_PFCE113 (0x2000u) +#define GPIO_PFCE1_PFCE114 (0x4000u) +#define GPIO_PFCE1_PFCE115 (0x8000u) + +#define GPIO_PNOT1_PNOT10 (0x0001u) +#define GPIO_PNOT1_PNOT11 (0x0002u) +#define GPIO_PNOT1_PNOT12 (0x0004u) +#define GPIO_PNOT1_PNOT13 (0x0008u) +#define GPIO_PNOT1_PNOT14 (0x0010u) +#define GPIO_PNOT1_PNOT15 (0x0020u) +#define GPIO_PNOT1_PNOT16 (0x0040u) +#define GPIO_PNOT1_PNOT17 (0x0080u) + +#define GPIO_PMSR1_PMSR10 (0x00000001uL) +#define GPIO_PMSR1_PMSR11 (0x00000002uL) +#define GPIO_PMSR1_PMSR12 (0x00000004uL) +#define GPIO_PMSR1_PMSR13 (0x00000008uL) +#define GPIO_PMSR1_PMSR14 (0x00000010uL) +#define GPIO_PMSR1_PMSR15 (0x00000020uL) +#define GPIO_PMSR1_PMSR16 (0x00000040uL) +#define GPIO_PMSR1_PMSR17 (0x00000080uL) +#define GPIO_PMSR1_PMSR116 (0x00010000uL) +#define GPIO_PMSR1_PMSR117 (0x00020000uL) +#define GPIO_PMSR1_PMSR118 (0x00040000uL) +#define GPIO_PMSR1_PMSR119 (0x00080000uL) +#define GPIO_PMSR1_PMSR120 (0x00100000uL) +#define GPIO_PMSR1_PMSR121 (0x00200000uL) +#define GPIO_PMSR1_PMSR122 (0x00400000uL) +#define GPIO_PMSR1_PMSR123 (0x00800000uL) + +#define GPIO_PMCSR1_PMCSR10 (0x00000001uL) +#define GPIO_PMCSR1_PMCSR11 (0x00000002uL) +#define GPIO_PMCSR1_PMCSR12 (0x00000004uL) +#define GPIO_PMCSR1_PMCSR13 (0x00000008uL) +#define GPIO_PMCSR1_PMCSR14 (0x00000010uL) +#define GPIO_PMCSR1_PMCSR15 (0x00000020uL) +#define GPIO_PMCSR1_PMCSR16 (0x00000040uL) +#define GPIO_PMCSR1_PMCSR17 (0x00000080uL) +#define GPIO_PMCSR1_PMCSR116 (0x00010000uL) +#define GPIO_PMCSR1_PMCSR117 (0x00020000uL) +#define GPIO_PMCSR1_PMCSR118 (0x00040000uL) +#define GPIO_PMCSR1_PMCSR119 (0x00080000uL) +#define GPIO_PMCSR1_PMCSR120 (0x00100000uL) +#define GPIO_PMCSR1_PMCSR121 (0x00200000uL) +#define GPIO_PMCSR1_PMCSR122 (0x00400000uL) +#define GPIO_PMCSR1_PMCSR123 (0x00800000uL) + +#define GPIO_PFCAE1_PFCAE10 (0x0001u) +#define GPIO_PFCAE1_PFCAE11 (0x0002u) +#define GPIO_PFCAE1_PFCAE12 (0x0004u) +#define GPIO_PFCAE1_PFCAE13 (0x0008u) +#define GPIO_PFCAE1_PFCAE14 (0x0010u) +#define GPIO_PFCAE1_PFCAE15 (0x0020u) +#define GPIO_PFCAE1_PFCAE16 (0x0040u) +#define GPIO_PFCAE1_PFCAE17 (0x0080u) +#define GPIO_PFCAE1_PFCAE18 (0x0100u) +#define GPIO_PFCAE1_PFCAE19 (0x0200u) +#define GPIO_PFCAE1_PFCAE110 (0x0400u) +#define GPIO_PFCAE1_PFCAE111 (0x0800u) +#define GPIO_PFCAE1_PFCAE112 (0x1000u) +#define GPIO_PFCAE1_PFCAE113 (0x2000u) +#define GPIO_PFCAE1_PFCAE114 (0x4000u) +#define GPIO_PFCAE1_PFCAE115 (0x8000u) + +#define GPIO_PIBC1_PIBC10 (0x0001u) +#define GPIO_PIBC1_PIBC11 (0x0002u) +#define GPIO_PIBC1_PIBC12 (0x0004u) +#define GPIO_PIBC1_PIBC13 (0x0008u) +#define GPIO_PIBC1_PIBC14 (0x0010u) +#define GPIO_PIBC1_PIBC15 (0x0020u) +#define GPIO_PIBC1_PIBC16 (0x0040u) +#define GPIO_PIBC1_PIBC17 (0x0080u) +#define GPIO_PIBC1_PIBC18 (0x0100u) +#define GPIO_PIBC1_PIBC19 (0x0200u) +#define GPIO_PIBC1_PIBC110 (0x0400u) +#define GPIO_PIBC1_PIBC111 (0x0800u) +#define GPIO_PIBC1_PIBC112 (0x1000u) +#define GPIO_PIBC1_PIBC113 (0x2000u) +#define GPIO_PIBC1_PIBC114 (0x4000u) +#define GPIO_PIBC1_PIBC115 (0x8000u) + +#define GPIO_PBDC1_PBDC10 (0x0001u) +#define GPIO_PBDC1_PBDC11 (0x0002u) +#define GPIO_PBDC1_PBDC12 (0x0004u) +#define GPIO_PBDC1_PBDC13 (0x0008u) +#define GPIO_PBDC1_PBDC14 (0x0010u) +#define GPIO_PBDC1_PBDC15 (0x0020u) +#define GPIO_PBDC1_PBDC16 (0x0040u) +#define GPIO_PBDC1_PBDC17 (0x0080u) +#define GPIO_PBDC1_PBDC18 (0x0100u) +#define GPIO_PBDC1_PBDC19 (0x0200u) +#define GPIO_PBDC1_PBDC110 (0x0400u) +#define GPIO_PBDC1_PBDC111 (0x0800u) +#define GPIO_PBDC1_PBDC112 (0x1000u) +#define GPIO_PBDC1_PBDC113 (0x2000u) +#define GPIO_PBDC1_PBDC114 (0x4000u) +#define GPIO_PBDC1_PBDC115 (0x8000u) + +#define GPIO_PIPC1_PIPC10 (0x0001u) +#define GPIO_PIPC1_PIPC11 (0x0002u) +#define GPIO_PIPC1_PIPC12 (0x0004u) +#define GPIO_PIPC1_PIPC13 (0x0008u) +#define GPIO_PIPC1_PIPC14 (0x0010u) +#define GPIO_PIPC1_PIPC15 (0x0020u) +#define GPIO_PIPC1_PIPC16 (0x0040u) +#define GPIO_PIPC1_PIPC17 (0x0080u) + +/* ---- P2 ---- */ +#define GPIO_P2_P20 (0x0001u) +#define GPIO_P2_P21 (0x0002u) +#define GPIO_P2_P22 (0x0004u) +#define GPIO_P2_P23 (0x0008u) +#define GPIO_P2_P24 (0x0010u) +#define GPIO_P2_P25 (0x0020u) +#define GPIO_P2_P26 (0x0040u) +#define GPIO_P2_P27 (0x0080u) +#define GPIO_P2_P28 (0x0100u) +#define GPIO_P2_P29 (0x0200u) +#define GPIO_P2_P210 (0x0400u) +#define GPIO_P2_P211 (0x0800u) +#define GPIO_P2_P212 (0x1000u) +#define GPIO_P2_P213 (0x2000u) +#define GPIO_P2_P214 (0x4000u) +#define GPIO_P2_P215 (0x8000u) + +#define GPIO_PSR2_PSR20 (0x00000001uL) +#define GPIO_PSR2_PSR21 (0x00000002uL) +#define GPIO_PSR2_PSR22 (0x00000004uL) +#define GPIO_PSR2_PSR23 (0x00000008uL) +#define GPIO_PSR2_PSR24 (0x00000010uL) +#define GPIO_PSR2_PSR25 (0x00000020uL) +#define GPIO_PSR2_PSR26 (0x00000040uL) +#define GPIO_PSR2_PSR27 (0x00000080uL) +#define GPIO_PSR2_PSR28 (0x00000100uL) +#define GPIO_PSR2_PSR29 (0x00000200uL) +#define GPIO_PSR2_PSR210 (0x00000400uL) +#define GPIO_PSR2_PSR211 (0x00000800uL) +#define GPIO_PSR2_PSR212 (0x00001000uL) +#define GPIO_PSR2_PSR213 (0x00002000uL) +#define GPIO_PSR2_PSR214 (0x00004000uL) +#define GPIO_PSR2_PSR215 (0x00008000uL) +#define GPIO_PSR2_PSR216 (0x00010000uL) +#define GPIO_PSR2_PSR217 (0x00020000uL) +#define GPIO_PSR2_PSR218 (0x00040000uL) +#define GPIO_PSR2_PSR219 (0x00080000uL) +#define GPIO_PSR2_PSR220 (0x00100000uL) +#define GPIO_PSR2_PSR221 (0x00200000uL) +#define GPIO_PSR2_PSR222 (0x00400000uL) +#define GPIO_PSR2_PSR223 (0x00800000uL) +#define GPIO_PSR2_PSR224 (0x01000000uL) +#define GPIO_PSR2_PSR225 (0x02000000uL) +#define GPIO_PSR2_PSR226 (0x04000000uL) +#define GPIO_PSR2_PSR227 (0x08000000uL) +#define GPIO_PSR2_PSR228 (0x10000000uL) +#define GPIO_PSR2_PSR229 (0x20000000uL) +#define GPIO_PSR2_PSR230 (0x40000000uL) +#define GPIO_PSR2_PSR231 (0x80000000uL) + +#define GPIO_PPR2_PPR20 (0x0001u) +#define GPIO_PPR2_PPR21 (0x0002u) +#define GPIO_PPR2_PPR22 (0x0004u) +#define GPIO_PPR2_PPR23 (0x0008u) +#define GPIO_PPR2_PPR24 (0x0010u) +#define GPIO_PPR2_PPR25 (0x0020u) +#define GPIO_PPR2_PPR26 (0x0040u) +#define GPIO_PPR2_PPR27 (0x0080u) +#define GPIO_PPR2_PPR28 (0x0100u) +#define GPIO_PPR2_PPR29 (0x0200u) +#define GPIO_PPR2_PPR210 (0x0400u) +#define GPIO_PPR2_PPR211 (0x0800u) +#define GPIO_PPR2_PPR212 (0x1000u) +#define GPIO_PPR2_PPR213 (0x2000u) +#define GPIO_PPR2_PPR214 (0x4000u) +#define GPIO_PPR2_PPR215 (0x8000u) + +#define GPIO_PM2_PM20 (0x0001u) +#define GPIO_PM2_PM21 (0x0002u) +#define GPIO_PM2_PM22 (0x0004u) +#define GPIO_PM2_PM23 (0x0008u) +#define GPIO_PM2_PM24 (0x0010u) +#define GPIO_PM2_PM25 (0x0020u) +#define GPIO_PM2_PM26 (0x0040u) +#define GPIO_PM2_PM27 (0x0080u) +#define GPIO_PM2_PM28 (0x0100u) +#define GPIO_PM2_PM29 (0x0200u) +#define GPIO_PM2_PM210 (0x0400u) +#define GPIO_PM2_PM211 (0x0800u) +#define GPIO_PM2_PM212 (0x1000u) +#define GPIO_PM2_PM213 (0x2000u) +#define GPIO_PM2_PM214 (0x4000u) +#define GPIO_PM2_PM215 (0x8000u) + +#define GPIO_PMC2_PMC20 (0x0001u) +#define GPIO_PMC2_PMC21 (0x0002u) +#define GPIO_PMC2_PMC22 (0x0004u) +#define GPIO_PMC2_PMC23 (0x0008u) +#define GPIO_PMC2_PMC24 (0x0010u) +#define GPIO_PMC2_PMC25 (0x0020u) +#define GPIO_PMC2_PMC26 (0x0040u) +#define GPIO_PMC2_PMC27 (0x0080u) +#define GPIO_PMC2_PMC28 (0x0100u) +#define GPIO_PMC2_PMC29 (0x0200u) +#define GPIO_PMC2_PMC210 (0x0400u) +#define GPIO_PMC2_PMC211 (0x0800u) +#define GPIO_PMC2_PMC212 (0x1000u) +#define GPIO_PMC2_PMC213 (0x2000u) +#define GPIO_PMC2_PMC214 (0x4000u) +#define GPIO_PMC2_PMC215 (0x8000u) + +#define GPIO_PFC2_PFC20 (0x0001u) +#define GPIO_PFC2_PFC21 (0x0002u) +#define GPIO_PFC2_PFC22 (0x0004u) +#define GPIO_PFC2_PFC23 (0x0008u) +#define GPIO_PFC2_PFC24 (0x0010u) +#define GPIO_PFC2_PFC25 (0x0020u) +#define GPIO_PFC2_PFC26 (0x0040u) +#define GPIO_PFC2_PFC27 (0x0080u) +#define GPIO_PFC2_PFC28 (0x0100u) +#define GPIO_PFC2_PFC29 (0x0200u) +#define GPIO_PFC2_PFC210 (0x0400u) +#define GPIO_PFC2_PFC211 (0x0800u) +#define GPIO_PFC2_PFC212 (0x1000u) +#define GPIO_PFC2_PFC213 (0x2000u) +#define GPIO_PFC2_PFC214 (0x4000u) +#define GPIO_PFC2_PFC215 (0x8000u) + +#define GPIO_PFCE2_PFCE20 (0x0001u) +#define GPIO_PFCE2_PFCE21 (0x0002u) +#define GPIO_PFCE2_PFCE22 (0x0004u) +#define GPIO_PFCE2_PFCE23 (0x0008u) +#define GPIO_PFCE2_PFCE24 (0x0010u) +#define GPIO_PFCE2_PFCE25 (0x0020u) +#define GPIO_PFCE2_PFCE26 (0x0040u) +#define GPIO_PFCE2_PFCE27 (0x0080u) +#define GPIO_PFCE2_PFCE28 (0x0100u) +#define GPIO_PFCE2_PFCE29 (0x0200u) +#define GPIO_PFCE2_PFCE210 (0x0400u) +#define GPIO_PFCE2_PFCE211 (0x0800u) +#define GPIO_PFCE2_PFCE212 (0x1000u) +#define GPIO_PFCE2_PFCE213 (0x2000u) +#define GPIO_PFCE2_PFCE214 (0x4000u) +#define GPIO_PFCE2_PFCE215 (0x8000u) + +#define GPIO_PNOT2_PNOT20 (0x0001u) +#define GPIO_PNOT2_PNOT21 (0x0002u) +#define GPIO_PNOT2_PNOT22 (0x0004u) +#define GPIO_PNOT2_PNOT23 (0x0008u) +#define GPIO_PNOT2_PNOT24 (0x0010u) +#define GPIO_PNOT2_PNOT25 (0x0020u) +#define GPIO_PNOT2_PNOT26 (0x0040u) +#define GPIO_PNOT2_PNOT27 (0x0080u) +#define GPIO_PNOT2_PNOT28 (0x0100u) +#define GPIO_PNOT2_PNOT29 (0x0200u) +#define GPIO_PNOT2_PNOT210 (0x0400u) +#define GPIO_PNOT2_PNOT211 (0x0800u) +#define GPIO_PNOT2_PNOT212 (0x1000u) +#define GPIO_PNOT2_PNOT213 (0x2000u) +#define GPIO_PNOT2_PNOT214 (0x4000u) +#define GPIO_PNOT2_PNOT215 (0x8000u) + +#define GPIO_PMSR2_PMSR20 (0x00000001uL) +#define GPIO_PMSR2_PMSR21 (0x00000002uL) +#define GPIO_PMSR2_PMSR22 (0x00000004uL) +#define GPIO_PMSR2_PMSR23 (0x00000008uL) +#define GPIO_PMSR2_PMSR24 (0x00000010uL) +#define GPIO_PMSR2_PMSR25 (0x00000020uL) +#define GPIO_PMSR2_PMSR26 (0x00000040uL) +#define GPIO_PMSR2_PMSR27 (0x00000080uL) +#define GPIO_PMSR2_PMSR28 (0x00000100uL) +#define GPIO_PMSR2_PMSR29 (0x00000200uL) +#define GPIO_PMSR2_PMSR210 (0x00000400uL) +#define GPIO_PMSR2_PMSR211 (0x00000800uL) +#define GPIO_PMSR2_PMSR212 (0x00001000uL) +#define GPIO_PMSR2_PMSR213 (0x00002000uL) +#define GPIO_PMSR2_PMSR214 (0x00004000uL) +#define GPIO_PMSR2_PMSR215 (0x00008000uL) +#define GPIO_PMSR2_PMSR216 (0x00010000uL) +#define GPIO_PMSR2_PMSR217 (0x00020000uL) +#define GPIO_PMSR2_PMSR218 (0x00040000uL) +#define GPIO_PMSR2_PMSR219 (0x00080000uL) +#define GPIO_PMSR2_PMSR220 (0x00100000uL) +#define GPIO_PMSR2_PMSR221 (0x00200000uL) +#define GPIO_PMSR2_PMSR222 (0x00400000uL) +#define GPIO_PMSR2_PMSR223 (0x00800000uL) +#define GPIO_PMSR2_PMSR224 (0x01000000uL) +#define GPIO_PMSR2_PMSR225 (0x02000000uL) +#define GPIO_PMSR2_PMSR226 (0x04000000uL) +#define GPIO_PMSR2_PMSR227 (0x08000000uL) +#define GPIO_PMSR2_PMSR228 (0x10000000uL) +#define GPIO_PMSR2_PMSR229 (0x20000000uL) +#define GPIO_PMSR2_PMSR230 (0x40000000uL) +#define GPIO_PMSR2_PMSR231 (0x80000000uL) + +#define GPIO_PMCSR2_PMCSR20 (0x00000001uL) +#define GPIO_PMCSR2_PMCSR21 (0x00000002uL) +#define GPIO_PMCSR2_PMCSR22 (0x00000004uL) +#define GPIO_PMCSR2_PMCSR23 (0x00000008uL) +#define GPIO_PMCSR2_PMCSR24 (0x00000010uL) +#define GPIO_PMCSR2_PMCSR25 (0x00000020uL) +#define GPIO_PMCSR2_PMCSR26 (0x00000040uL) +#define GPIO_PMCSR2_PMCSR27 (0x00000080uL) +#define GPIO_PMCSR2_PMCSR28 (0x00000100uL) +#define GPIO_PMCSR2_PMCSR29 (0x00000200uL) +#define GPIO_PMCSR2_PMCSR210 (0x00000400uL) +#define GPIO_PMCSR2_PMCSR211 (0x00000800uL) +#define GPIO_PMCSR2_PMCSR212 (0x00001000uL) +#define GPIO_PMCSR2_PMCSR213 (0x00002000uL) +#define GPIO_PMCSR2_PMCSR214 (0x00004000uL) +#define GPIO_PMCSR2_PMCSR215 (0x00008000uL) +#define GPIO_PMCSR2_PMCSR216 (0x00010000uL) +#define GPIO_PMCSR2_PMCSR217 (0x00020000uL) +#define GPIO_PMCSR2_PMCSR218 (0x00040000uL) +#define GPIO_PMCSR2_PMCSR219 (0x00080000uL) +#define GPIO_PMCSR2_PMCSR220 (0x00100000uL) +#define GPIO_PMCSR2_PMCSR221 (0x00200000uL) +#define GPIO_PMCSR2_PMCSR222 (0x00400000uL) +#define GPIO_PMCSR2_PMCSR223 (0x00800000uL) +#define GPIO_PMCSR2_PMCSR224 (0x01000000uL) +#define GPIO_PMCSR2_PMCSR225 (0x02000000uL) +#define GPIO_PMCSR2_PMCSR226 (0x04000000uL) +#define GPIO_PMCSR2_PMCSR227 (0x08000000uL) +#define GPIO_PMCSR2_PMCSR228 (0x10000000uL) +#define GPIO_PMCSR2_PMCSR229 (0x20000000uL) +#define GPIO_PMCSR2_PMCSR230 (0x40000000uL) +#define GPIO_PMCSR2_PMCSR231 (0x80000000uL) + +#define GPIO_PFCAE2_PFCAE20 (0x0001u) +#define GPIO_PFCAE2_PFCAE21 (0x0002u) +#define GPIO_PFCAE2_PFCAE22 (0x0004u) +#define GPIO_PFCAE2_PFCAE23 (0x0008u) +#define GPIO_PFCAE2_PFCAE24 (0x0010u) +#define GPIO_PFCAE2_PFCAE25 (0x0020u) +#define GPIO_PFCAE2_PFCAE26 (0x0040u) +#define GPIO_PFCAE2_PFCAE27 (0x0080u) +#define GPIO_PFCAE2_PFCAE28 (0x0100u) +#define GPIO_PFCAE2_PFCAE29 (0x0200u) +#define GPIO_PFCAE2_PFCAE210 (0x0400u) +#define GPIO_PFCAE2_PFCAE211 (0x0800u) +#define GPIO_PFCAE2_PFCAE212 (0x1000u) +#define GPIO_PFCAE2_PFCAE213 (0x2000u) +#define GPIO_PFCAE2_PFCAE214 (0x4000u) +#define GPIO_PFCAE2_PFCAE215 (0x8000u) + +#define GPIO_PIBC2_PIBC20 (0x0001u) +#define GPIO_PIBC2_PIBC21 (0x0002u) +#define GPIO_PIBC2_PIBC22 (0x0004u) +#define GPIO_PIBC2_PIBC23 (0x0008u) +#define GPIO_PIBC2_PIBC24 (0x0010u) +#define GPIO_PIBC2_PIBC25 (0x0020u) +#define GPIO_PIBC2_PIBC26 (0x0040u) +#define GPIO_PIBC2_PIBC27 (0x0080u) +#define GPIO_PIBC2_PIBC28 (0x0100u) +#define GPIO_PIBC2_PIBC29 (0x0200u) +#define GPIO_PIBC2_PIBC210 (0x0400u) +#define GPIO_PIBC2_PIBC211 (0x0800u) +#define GPIO_PIBC2_PIBC212 (0x1000u) +#define GPIO_PIBC2_PIBC213 (0x2000u) +#define GPIO_PIBC2_PIBC214 (0x4000u) +#define GPIO_PIBC2_PIBC215 (0x8000u) + +#define GPIO_PBDC2_PBDC20 (0x0001u) +#define GPIO_PBDC2_PBDC21 (0x0002u) +#define GPIO_PBDC2_PBDC22 (0x0004u) +#define GPIO_PBDC2_PBDC23 (0x0008u) +#define GPIO_PBDC2_PBDC24 (0x0010u) +#define GPIO_PBDC2_PBDC25 (0x0020u) +#define GPIO_PBDC2_PBDC26 (0x0040u) +#define GPIO_PBDC2_PBDC27 (0x0080u) +#define GPIO_PBDC2_PBDC28 (0x0100u) +#define GPIO_PBDC2_PBDC29 (0x0200u) +#define GPIO_PBDC2_PBDC210 (0x0400u) +#define GPIO_PBDC2_PBDC211 (0x0800u) +#define GPIO_PBDC2_PBDC212 (0x1000u) +#define GPIO_PBDC2_PBDC213 (0x2000u) +#define GPIO_PBDC2_PBDC214 (0x4000u) +#define GPIO_PBDC2_PBDC215 (0x8000u) + +#define GPIO_PIPC2_PIPC20 (0x0001u) +#define GPIO_PIPC2_PIPC21 (0x0002u) +#define GPIO_PIPC2_PIPC22 (0x0004u) +#define GPIO_PIPC2_PIPC23 (0x0008u) +#define GPIO_PIPC2_PIPC24 (0x0010u) +#define GPIO_PIPC2_PIPC25 (0x0020u) +#define GPIO_PIPC2_PIPC26 (0x0040u) +#define GPIO_PIPC2_PIPC27 (0x0080u) +#define GPIO_PIPC2_PIPC28 (0x0100u) +#define GPIO_PIPC2_PIPC29 (0x0200u) +#define GPIO_PIPC2_PIPC210 (0x0400u) +#define GPIO_PIPC2_PIPC211 (0x0800u) +#define GPIO_PIPC2_PIPC212 (0x1000u) +#define GPIO_PIPC2_PIPC213 (0x2000u) +#define GPIO_PIPC2_PIPC214 (0x4000u) +#define GPIO_PIPC2_PIPC215 (0x8000u) + +/* ---- P3 ---- */ +#define GPIO_P3_P30 (0x0001u) +#define GPIO_P3_P31 (0x0002u) +#define GPIO_P3_P32 (0x0004u) +#define GPIO_P3_P33 (0x0008u) +#define GPIO_P3_P34 (0x0010u) +#define GPIO_P3_P35 (0x0020u) +#define GPIO_P3_P36 (0x0040u) +#define GPIO_P3_P37 (0x0080u) +#define GPIO_P3_P38 (0x0100u) +#define GPIO_P3_P39 (0x0200u) +#define GPIO_P3_P310 (0x0400u) +#define GPIO_P3_P311 (0x0800u) +#define GPIO_P3_P312 (0x1000u) +#define GPIO_P3_P313 (0x2000u) +#define GPIO_P3_P314 (0x4000u) +#define GPIO_P3_P315 (0x8000u) + +#define GPIO_PSR3_PSR30 (0x00000001uL) +#define GPIO_PSR3_PSR31 (0x00000002uL) +#define GPIO_PSR3_PSR32 (0x00000004uL) +#define GPIO_PSR3_PSR33 (0x00000008uL) +#define GPIO_PSR3_PSR34 (0x00000010uL) +#define GPIO_PSR3_PSR35 (0x00000020uL) +#define GPIO_PSR3_PSR36 (0x00000040uL) +#define GPIO_PSR3_PSR37 (0x00000080uL) +#define GPIO_PSR3_PSR38 (0x00000100uL) +#define GPIO_PSR3_PSR39 (0x00000200uL) +#define GPIO_PSR3_PSR310 (0x00000400uL) +#define GPIO_PSR3_PSR311 (0x00000800uL) +#define GPIO_PSR3_PSR312 (0x00001000uL) +#define GPIO_PSR3_PSR313 (0x00002000uL) +#define GPIO_PSR3_PSR314 (0x00004000uL) +#define GPIO_PSR3_PSR315 (0x00008000uL) +#define GPIO_PSR3_PSR316 (0x00010000uL) +#define GPIO_PSR3_PSR317 (0x00020000uL) +#define GPIO_PSR3_PSR318 (0x00040000uL) +#define GPIO_PSR3_PSR319 (0x00080000uL) +#define GPIO_PSR3_PSR320 (0x00100000uL) +#define GPIO_PSR3_PSR321 (0x00200000uL) +#define GPIO_PSR3_PSR322 (0x00400000uL) +#define GPIO_PSR3_PSR323 (0x00800000uL) +#define GPIO_PSR3_PSR324 (0x01000000uL) +#define GPIO_PSR3_PSR325 (0x02000000uL) +#define GPIO_PSR3_PSR326 (0x04000000uL) +#define GPIO_PSR3_PSR327 (0x08000000uL) +#define GPIO_PSR3_PSR328 (0x10000000uL) +#define GPIO_PSR3_PSR329 (0x20000000uL) +#define GPIO_PSR3_PSR330 (0x40000000uL) +#define GPIO_PSR3_PSR331 (0x80000000uL) + +#define GPIO_PPR3_PPR30 (0x0001u) +#define GPIO_PPR3_PPR31 (0x0002u) +#define GPIO_PPR3_PPR32 (0x0004u) +#define GPIO_PPR3_PPR33 (0x0008u) +#define GPIO_PPR3_PPR34 (0x0010u) +#define GPIO_PPR3_PPR35 (0x0020u) +#define GPIO_PPR3_PPR36 (0x0040u) +#define GPIO_PPR3_PPR37 (0x0080u) +#define GPIO_PPR3_PPR38 (0x0100u) +#define GPIO_PPR3_PPR39 (0x0200u) +#define GPIO_PPR3_PPR310 (0x0400u) +#define GPIO_PPR3_PPR311 (0x0800u) +#define GPIO_PPR3_PPR312 (0x1000u) +#define GPIO_PPR3_PPR313 (0x2000u) +#define GPIO_PPR3_PPR314 (0x4000u) +#define GPIO_PPR3_PPR315 (0x8000u) + +#define GPIO_PM3_PM30 (0x0001u) +#define GPIO_PM3_PM31 (0x0002u) +#define GPIO_PM3_PM32 (0x0004u) +#define GPIO_PM3_PM33 (0x0008u) +#define GPIO_PM3_PM34 (0x0010u) +#define GPIO_PM3_PM35 (0x0020u) +#define GPIO_PM3_PM36 (0x0040u) +#define GPIO_PM3_PM37 (0x0080u) +#define GPIO_PM3_PM38 (0x0100u) +#define GPIO_PM3_PM39 (0x0200u) +#define GPIO_PM3_PM310 (0x0400u) +#define GPIO_PM3_PM311 (0x0800u) +#define GPIO_PM3_PM312 (0x1000u) +#define GPIO_PM3_PM313 (0x2000u) +#define GPIO_PM3_PM314 (0x4000u) +#define GPIO_PM3_PM315 (0x8000u) + +#define GPIO_PMC3_PMC30 (0x0001u) +#define GPIO_PMC3_PMC31 (0x0002u) +#define GPIO_PMC3_PMC32 (0x0004u) +#define GPIO_PMC3_PMC33 (0x0008u) +#define GPIO_PMC3_PMC34 (0x0010u) +#define GPIO_PMC3_PMC35 (0x0020u) +#define GPIO_PMC3_PMC36 (0x0040u) +#define GPIO_PMC3_PMC37 (0x0080u) +#define GPIO_PMC3_PMC38 (0x0100u) +#define GPIO_PMC3_PMC39 (0x0200u) +#define GPIO_PMC3_PMC310 (0x0400u) +#define GPIO_PMC3_PMC311 (0x0800u) +#define GPIO_PMC3_PMC312 (0x1000u) +#define GPIO_PMC3_PMC313 (0x2000u) +#define GPIO_PMC3_PMC314 (0x4000u) +#define GPIO_PMC3_PMC315 (0x8000u) + +#define GPIO_PFC3_PFC30 (0x0001u) +#define GPIO_PFC3_PFC31 (0x0002u) +#define GPIO_PFC3_PFC32 (0x0004u) +#define GPIO_PFC3_PFC33 (0x0008u) +#define GPIO_PFC3_PFC34 (0x0010u) +#define GPIO_PFC3_PFC35 (0x0020u) +#define GPIO_PFC3_PFC36 (0x0040u) +#define GPIO_PFC3_PFC37 (0x0080u) +#define GPIO_PFC3_PFC38 (0x0100u) +#define GPIO_PFC3_PFC39 (0x0200u) +#define GPIO_PFC3_PFC310 (0x0400u) +#define GPIO_PFC3_PFC311 (0x0800u) +#define GPIO_PFC3_PFC312 (0x1000u) +#define GPIO_PFC3_PFC313 (0x2000u) +#define GPIO_PFC3_PFC314 (0x4000u) +#define GPIO_PFC3_PFC315 (0x8000u) + +#define GPIO_PFCE3_PFCE30 (0x0001u) +#define GPIO_PFCE3_PFCE31 (0x0002u) +#define GPIO_PFCE3_PFCE32 (0x0004u) +#define GPIO_PFCE3_PFCE33 (0x0008u) +#define GPIO_PFCE3_PFCE34 (0x0010u) +#define GPIO_PFCE3_PFCE35 (0x0020u) +#define GPIO_PFCE3_PFCE36 (0x0040u) +#define GPIO_PFCE3_PFCE37 (0x0080u) +#define GPIO_PFCE3_PFCE38 (0x0100u) +#define GPIO_PFCE3_PFCE39 (0x0200u) +#define GPIO_PFCE3_PFCE310 (0x0400u) +#define GPIO_PFCE3_PFCE311 (0x0800u) +#define GPIO_PFCE3_PFCE312 (0x1000u) +#define GPIO_PFCE3_PFCE313 (0x2000u) +#define GPIO_PFCE3_PFCE314 (0x4000u) +#define GPIO_PFCE3_PFCE315 (0x8000u) + +#define GPIO_PNOT3_PNOT30 (0x0001u) +#define GPIO_PNOT3_PNOT31 (0x0002u) +#define GPIO_PNOT3_PNOT32 (0x0004u) +#define GPIO_PNOT3_PNOT33 (0x0008u) +#define GPIO_PNOT3_PNOT34 (0x0010u) +#define GPIO_PNOT3_PNOT35 (0x0020u) +#define GPIO_PNOT3_PNOT36 (0x0040u) +#define GPIO_PNOT3_PNOT37 (0x0080u) +#define GPIO_PNOT3_PNOT38 (0x0100u) +#define GPIO_PNOT3_PNOT39 (0x0200u) +#define GPIO_PNOT3_PNOT310 (0x0400u) +#define GPIO_PNOT3_PNOT311 (0x0800u) +#define GPIO_PNOT3_PNOT312 (0x1000u) +#define GPIO_PNOT3_PNOT313 (0x2000u) +#define GPIO_PNOT3_PNOT314 (0x4000u) +#define GPIO_PNOT3_PNOT315 (0x8000u) + +#define GPIO_PMSR3_PMSR30 (0x00000001uL) +#define GPIO_PMSR3_PMSR31 (0x00000002uL) +#define GPIO_PMSR3_PMSR32 (0x00000004uL) +#define GPIO_PMSR3_PMSR33 (0x00000008uL) +#define GPIO_PMSR3_PMSR34 (0x00000010uL) +#define GPIO_PMSR3_PMSR35 (0x00000020uL) +#define GPIO_PMSR3_PMSR36 (0x00000040uL) +#define GPIO_PMSR3_PMSR37 (0x00000080uL) +#define GPIO_PMSR3_PMSR38 (0x00000100uL) +#define GPIO_PMSR3_PMSR39 (0x00000200uL) +#define GPIO_PMSR3_PMSR310 (0x00000400uL) +#define GPIO_PMSR3_PMSR311 (0x00000800uL) +#define GPIO_PMSR3_PMSR312 (0x00001000uL) +#define GPIO_PMSR3_PMSR313 (0x00002000uL) +#define GPIO_PMSR3_PMSR314 (0x00004000uL) +#define GPIO_PMSR3_PMSR315 (0x00008000uL) +#define GPIO_PMSR3_PMSR316 (0x00010000uL) +#define GPIO_PMSR3_PMSR317 (0x00020000uL) +#define GPIO_PMSR3_PMSR318 (0x00040000uL) +#define GPIO_PMSR3_PMSR319 (0x00080000uL) +#define GPIO_PMSR3_PMSR320 (0x00100000uL) +#define GPIO_PMSR3_PMSR321 (0x00200000uL) +#define GPIO_PMSR3_PMSR322 (0x00400000uL) +#define GPIO_PMSR3_PMSR323 (0x00800000uL) +#define GPIO_PMSR3_PMSR324 (0x01000000uL) +#define GPIO_PMSR3_PMSR325 (0x02000000uL) +#define GPIO_PMSR3_PMSR326 (0x04000000uL) +#define GPIO_PMSR3_PMSR327 (0x08000000uL) +#define GPIO_PMSR3_PMSR328 (0x10000000uL) +#define GPIO_PMSR3_PMSR329 (0x20000000uL) +#define GPIO_PMSR3_PMSR330 (0x40000000uL) +#define GPIO_PMSR3_PMSR331 (0x80000000uL) + +#define GPIO_PMCSR3_PMCSR30 (0x00000001uL) +#define GPIO_PMCSR3_PMCSR31 (0x00000002uL) +#define GPIO_PMCSR3_PMCSR32 (0x00000004uL) +#define GPIO_PMCSR3_PMCSR33 (0x00000008uL) +#define GPIO_PMCSR3_PMCSR34 (0x00000010uL) +#define GPIO_PMCSR3_PMCSR35 (0x00000020uL) +#define GPIO_PMCSR3_PMCSR36 (0x00000040uL) +#define GPIO_PMCSR3_PMCSR37 (0x00000080uL) +#define GPIO_PMCSR3_PMCSR38 (0x00000100uL) +#define GPIO_PMCSR3_PMCSR39 (0x00000200uL) +#define GPIO_PMCSR3_PMCSR310 (0x00000400uL) +#define GPIO_PMCSR3_PMCSR311 (0x00000800uL) +#define GPIO_PMCSR3_PMCSR312 (0x00001000uL) +#define GPIO_PMCSR3_PMCSR313 (0x00002000uL) +#define GPIO_PMCSR3_PMCSR314 (0x00004000uL) +#define GPIO_PMCSR3_PMCSR315 (0x00008000uL) +#define GPIO_PMCSR3_PMCSR316 (0x00010000uL) +#define GPIO_PMCSR3_PMCSR317 (0x00020000uL) +#define GPIO_PMCSR3_PMCSR318 (0x00040000uL) +#define GPIO_PMCSR3_PMCSR319 (0x00080000uL) +#define GPIO_PMCSR3_PMCSR320 (0x00100000uL) +#define GPIO_PMCSR3_PMCSR321 (0x00200000uL) +#define GPIO_PMCSR3_PMCSR322 (0x00400000uL) +#define GPIO_PMCSR3_PMCSR323 (0x00800000uL) +#define GPIO_PMCSR3_PMCSR324 (0x01000000uL) +#define GPIO_PMCSR3_PMCSR325 (0x02000000uL) +#define GPIO_PMCSR3_PMCSR326 (0x04000000uL) +#define GPIO_PMCSR3_PMCSR327 (0x08000000uL) +#define GPIO_PMCSR3_PMCSR328 (0x10000000uL) +#define GPIO_PMCSR3_PMCSR329 (0x20000000uL) +#define GPIO_PMCSR3_PMCSR330 (0x40000000uL) +#define GPIO_PMCSR3_PMCSR331 (0x80000000uL) + +#define GPIO_PFCAE3_PFCAE30 (0x0001u) +#define GPIO_PFCAE3_PFCAE31 (0x0002u) +#define GPIO_PFCAE3_PFCAE32 (0x0004u) +#define GPIO_PFCAE3_PFCAE33 (0x0008u) +#define GPIO_PFCAE3_PFCAE34 (0x0010u) +#define GPIO_PFCAE3_PFCAE35 (0x0020u) +#define GPIO_PFCAE3_PFCAE36 (0x0040u) +#define GPIO_PFCAE3_PFCAE37 (0x0080u) +#define GPIO_PFCAE3_PFCAE38 (0x0100u) +#define GPIO_PFCAE3_PFCAE39 (0x0200u) +#define GPIO_PFCAE3_PFCAE310 (0x0400u) +#define GPIO_PFCAE3_PFCAE311 (0x0800u) +#define GPIO_PFCAE3_PFCAE312 (0x1000u) +#define GPIO_PFCAE3_PFCAE313 (0x2000u) +#define GPIO_PFCAE3_PFCAE314 (0x4000u) +#define GPIO_PFCAE3_PFCAE315 (0x8000u) + +#define GPIO_PIBC3_PIBC30 (0x0001u) +#define GPIO_PIBC3_PIBC31 (0x0002u) +#define GPIO_PIBC3_PIBC32 (0x0004u) +#define GPIO_PIBC3_PIBC33 (0x0008u) +#define GPIO_PIBC3_PIBC34 (0x0010u) +#define GPIO_PIBC3_PIBC35 (0x0020u) +#define GPIO_PIBC3_PIBC36 (0x0040u) +#define GPIO_PIBC3_PIBC37 (0x0080u) +#define GPIO_PIBC3_PIBC38 (0x0100u) +#define GPIO_PIBC3_PIBC39 (0x0200u) +#define GPIO_PIBC3_PIBC310 (0x0400u) +#define GPIO_PIBC3_PIBC311 (0x0800u) +#define GPIO_PIBC3_PIBC312 (0x1000u) +#define GPIO_PIBC3_PIBC313 (0x2000u) +#define GPIO_PIBC3_PIBC314 (0x4000u) +#define GPIO_PIBC3_PIBC315 (0x8000u) + +#define GPIO_PBDC3_PBDC30 (0x0001u) +#define GPIO_PBDC3_PBDC31 (0x0002u) +#define GPIO_PBDC3_PBDC32 (0x0004u) +#define GPIO_PBDC3_PBDC33 (0x0008u) +#define GPIO_PBDC3_PBDC34 (0x0010u) +#define GPIO_PBDC3_PBDC35 (0x0020u) +#define GPIO_PBDC3_PBDC36 (0x0040u) +#define GPIO_PBDC3_PBDC37 (0x0080u) +#define GPIO_PBDC3_PBDC38 (0x0100u) +#define GPIO_PBDC3_PBDC39 (0x0200u) +#define GPIO_PBDC3_PBDC310 (0x0400u) +#define GPIO_PBDC3_PBDC311 (0x0800u) +#define GPIO_PBDC3_PBDC312 (0x1000u) +#define GPIO_PBDC3_PBDC313 (0x2000u) +#define GPIO_PBDC3_PBDC314 (0x4000u) +#define GPIO_PBDC3_PBDC315 (0x8000u) + +#define GPIO_PIPC3_PIPC30 (0x0001u) +#define GPIO_PIPC3_PIPC31 (0x0002u) +#define GPIO_PIPC3_PIPC32 (0x0004u) +#define GPIO_PIPC3_PIPC33 (0x0008u) +#define GPIO_PIPC3_PIPC34 (0x0010u) +#define GPIO_PIPC3_PIPC35 (0x0020u) +#define GPIO_PIPC3_PIPC36 (0x0040u) +#define GPIO_PIPC3_PIPC37 (0x0080u) +#define GPIO_PIPC3_PIPC38 (0x0100u) +#define GPIO_PIPC3_PIPC39 (0x0200u) +#define GPIO_PIPC3_PIPC310 (0x0400u) +#define GPIO_PIPC3_PIPC311 (0x0800u) +#define GPIO_PIPC3_PIPC312 (0x1000u) +#define GPIO_PIPC3_PIPC313 (0x2000u) +#define GPIO_PIPC3_PIPC314 (0x4000u) +#define GPIO_PIPC3_PIPC315 (0x8000u) + +/* ---- P4 ---- */ +#define GPIO_P4_P40 (0x0001u) +#define GPIO_P4_P41 (0x0002u) +#define GPIO_P4_P42 (0x0004u) +#define GPIO_P4_P43 (0x0008u) +#define GPIO_P4_P44 (0x0010u) +#define GPIO_P4_P45 (0x0020u) +#define GPIO_P4_P46 (0x0040u) +#define GPIO_P4_P47 (0x0080u) +#define GPIO_P4_P48 (0x0100u) +#define GPIO_P4_P49 (0x0200u) +#define GPIO_P4_P410 (0x0400u) +#define GPIO_P4_P411 (0x0800u) +#define GPIO_P4_P412 (0x1000u) +#define GPIO_P4_P413 (0x2000u) +#define GPIO_P4_P414 (0x4000u) +#define GPIO_P4_P415 (0x8000u) + +#define GPIO_PSR4_PSR40 (0x00000001uL) +#define GPIO_PSR4_PSR41 (0x00000002uL) +#define GPIO_PSR4_PSR42 (0x00000004uL) +#define GPIO_PSR4_PSR43 (0x00000008uL) +#define GPIO_PSR4_PSR44 (0x00000010uL) +#define GPIO_PSR4_PSR45 (0x00000020uL) +#define GPIO_PSR4_PSR46 (0x00000040uL) +#define GPIO_PSR4_PSR47 (0x00000080uL) +#define GPIO_PSR4_PSR48 (0x00000100uL) +#define GPIO_PSR4_PSR49 (0x00000200uL) +#define GPIO_PSR4_PSR410 (0x00000400uL) +#define GPIO_PSR4_PSR411 (0x00000800uL) +#define GPIO_PSR4_PSR412 (0x00001000uL) +#define GPIO_PSR4_PSR413 (0x00002000uL) +#define GPIO_PSR4_PSR414 (0x00004000uL) +#define GPIO_PSR4_PSR415 (0x00008000uL) +#define GPIO_PSR4_PSR416 (0x00010000uL) +#define GPIO_PSR4_PSR417 (0x00020000uL) +#define GPIO_PSR4_PSR418 (0x00040000uL) +#define GPIO_PSR4_PSR419 (0x00080000uL) +#define GPIO_PSR4_PSR420 (0x00100000uL) +#define GPIO_PSR4_PSR421 (0x00200000uL) +#define GPIO_PSR4_PSR422 (0x00400000uL) +#define GPIO_PSR4_PSR423 (0x00800000uL) +#define GPIO_PSR4_PSR424 (0x01000000uL) +#define GPIO_PSR4_PSR425 (0x02000000uL) +#define GPIO_PSR4_PSR426 (0x04000000uL) +#define GPIO_PSR4_PSR427 (0x08000000uL) +#define GPIO_PSR4_PSR428 (0x10000000uL) +#define GPIO_PSR4_PSR429 (0x20000000uL) +#define GPIO_PSR4_PSR430 (0x40000000uL) +#define GPIO_PSR4_PSR431 (0x80000000uL) + +#define GPIO_PPR4_PPR40 (0x0001u) +#define GPIO_PPR4_PPR41 (0x0002u) +#define GPIO_PPR4_PPR42 (0x0004u) +#define GPIO_PPR4_PPR43 (0x0008u) +#define GPIO_PPR4_PPR44 (0x0010u) +#define GPIO_PPR4_PPR45 (0x0020u) +#define GPIO_PPR4_PPR46 (0x0040u) +#define GPIO_PPR4_PPR47 (0x0080u) +#define GPIO_PPR4_PPR48 (0x0100u) +#define GPIO_PPR4_PPR49 (0x0200u) +#define GPIO_PPR4_PPR410 (0x0400u) +#define GPIO_PPR4_PPR411 (0x0800u) +#define GPIO_PPR4_PPR412 (0x1000u) +#define GPIO_PPR4_PPR413 (0x2000u) +#define GPIO_PPR4_PPR414 (0x4000u) +#define GPIO_PPR4_PPR415 (0x8000u) + +#define GPIO_PM4_PM40 (0x0001u) +#define GPIO_PM4_PM41 (0x0002u) +#define GPIO_PM4_PM42 (0x0004u) +#define GPIO_PM4_PM43 (0x0008u) +#define GPIO_PM4_PM44 (0x0010u) +#define GPIO_PM4_PM45 (0x0020u) +#define GPIO_PM4_PM46 (0x0040u) +#define GPIO_PM4_PM47 (0x0080u) +#define GPIO_PM4_PM48 (0x0100u) +#define GPIO_PM4_PM49 (0x0200u) +#define GPIO_PM4_PM410 (0x0400u) +#define GPIO_PM4_PM411 (0x0800u) +#define GPIO_PM4_PM412 (0x1000u) +#define GPIO_PM4_PM413 (0x2000u) +#define GPIO_PM4_PM414 (0x4000u) +#define GPIO_PM4_PM415 (0x8000u) + +#define GPIO_PMC4_PMC40 (0x0001u) +#define GPIO_PMC4_PMC41 (0x0002u) +#define GPIO_PMC4_PMC42 (0x0004u) +#define GPIO_PMC4_PMC43 (0x0008u) +#define GPIO_PMC4_PMC44 (0x0010u) +#define GPIO_PMC4_PMC45 (0x0020u) +#define GPIO_PMC4_PMC46 (0x0040u) +#define GPIO_PMC4_PMC47 (0x0080u) +#define GPIO_PMC4_PMC48 (0x0100u) +#define GPIO_PMC4_PMC49 (0x0200u) +#define GPIO_PMC4_PMC410 (0x0400u) +#define GPIO_PMC4_PMC411 (0x0800u) +#define GPIO_PMC4_PMC412 (0x1000u) +#define GPIO_PMC4_PMC413 (0x2000u) +#define GPIO_PMC4_PMC414 (0x4000u) +#define GPIO_PMC4_PMC415 (0x8000u) + +#define GPIO_PFC4_PFC40 (0x0001u) +#define GPIO_PFC4_PFC41 (0x0002u) +#define GPIO_PFC4_PFC42 (0x0004u) +#define GPIO_PFC4_PFC43 (0x0008u) +#define GPIO_PFC4_PFC44 (0x0010u) +#define GPIO_PFC4_PFC45 (0x0020u) +#define GPIO_PFC4_PFC46 (0x0040u) +#define GPIO_PFC4_PFC47 (0x0080u) +#define GPIO_PFC4_PFC48 (0x0100u) +#define GPIO_PFC4_PFC49 (0x0200u) +#define GPIO_PFC4_PFC410 (0x0400u) +#define GPIO_PFC4_PFC411 (0x0800u) +#define GPIO_PFC4_PFC412 (0x1000u) +#define GPIO_PFC4_PFC413 (0x2000u) +#define GPIO_PFC4_PFC414 (0x4000u) +#define GPIO_PFC4_PFC415 (0x8000u) + +#define GPIO_PFCE4_PFCE40 (0x0001u) +#define GPIO_PFCE4_PFCE41 (0x0002u) +#define GPIO_PFCE4_PFCE42 (0x0004u) +#define GPIO_PFCE4_PFCE43 (0x0008u) +#define GPIO_PFCE4_PFCE44 (0x0010u) +#define GPIO_PFCE4_PFCE45 (0x0020u) +#define GPIO_PFCE4_PFCE46 (0x0040u) +#define GPIO_PFCE4_PFCE47 (0x0080u) +#define GPIO_PFCE4_PFCE48 (0x0100u) +#define GPIO_PFCE4_PFCE49 (0x0200u) +#define GPIO_PFCE4_PFCE410 (0x0400u) +#define GPIO_PFCE4_PFCE411 (0x0800u) +#define GPIO_PFCE4_PFCE412 (0x1000u) +#define GPIO_PFCE4_PFCE413 (0x2000u) +#define GPIO_PFCE4_PFCE414 (0x4000u) +#define GPIO_PFCE4_PFCE415 (0x8000u) + +#define GPIO_PNOT4_PNOT40 (0x0001u) +#define GPIO_PNOT4_PNOT41 (0x0002u) +#define GPIO_PNOT4_PNOT42 (0x0004u) +#define GPIO_PNOT4_PNOT43 (0x0008u) +#define GPIO_PNOT4_PNOT44 (0x0010u) +#define GPIO_PNOT4_PNOT45 (0x0020u) +#define GPIO_PNOT4_PNOT46 (0x0040u) +#define GPIO_PNOT4_PNOT47 (0x0080u) +#define GPIO_PNOT4_PNOT48 (0x0100u) +#define GPIO_PNOT4_PNOT49 (0x0200u) +#define GPIO_PNOT4_PNOT410 (0x0400u) +#define GPIO_PNOT4_PNOT411 (0x0800u) +#define GPIO_PNOT4_PNOT412 (0x1000u) +#define GPIO_PNOT4_PNOT413 (0x2000u) +#define GPIO_PNOT4_PNOT414 (0x4000u) +#define GPIO_PNOT4_PNOT415 (0x8000u) + +#define GPIO_PMSR4_PMSR40 (0x00000001uL) +#define GPIO_PMSR4_PMSR41 (0x00000002uL) +#define GPIO_PMSR4_PMSR42 (0x00000004uL) +#define GPIO_PMSR4_PMSR43 (0x00000008uL) +#define GPIO_PMSR4_PMSR44 (0x00000010uL) +#define GPIO_PMSR4_PMSR45 (0x00000020uL) +#define GPIO_PMSR4_PMSR46 (0x00000040uL) +#define GPIO_PMSR4_PMSR47 (0x00000080uL) +#define GPIO_PMSR4_PMSR48 (0x00000100uL) +#define GPIO_PMSR4_PMSR49 (0x00000200uL) +#define GPIO_PMSR4_PMSR410 (0x00000400uL) +#define GPIO_PMSR4_PMSR411 (0x00000800uL) +#define GPIO_PMSR4_PMSR412 (0x00001000uL) +#define GPIO_PMSR4_PMSR413 (0x00002000uL) +#define GPIO_PMSR4_PMSR414 (0x00004000uL) +#define GPIO_PMSR4_PMSR415 (0x00008000uL) +#define GPIO_PMSR4_PMSR416 (0x00010000uL) +#define GPIO_PMSR4_PMSR417 (0x00020000uL) +#define GPIO_PMSR4_PMSR418 (0x00040000uL) +#define GPIO_PMSR4_PMSR419 (0x00080000uL) +#define GPIO_PMSR4_PMSR420 (0x00100000uL) +#define GPIO_PMSR4_PMSR421 (0x00200000uL) +#define GPIO_PMSR4_PMSR422 (0x00400000uL) +#define GPIO_PMSR4_PMSR423 (0x00800000uL) +#define GPIO_PMSR4_PMSR424 (0x01000000uL) +#define GPIO_PMSR4_PMSR425 (0x02000000uL) +#define GPIO_PMSR4_PMSR426 (0x04000000uL) +#define GPIO_PMSR4_PMSR427 (0x08000000uL) +#define GPIO_PMSR4_PMSR428 (0x10000000uL) +#define GPIO_PMSR4_PMSR429 (0x20000000uL) +#define GPIO_PMSR4_PMSR430 (0x40000000uL) +#define GPIO_PMSR4_PMSR431 (0x80000000uL) + +#define GPIO_PMCSR4_PMCSR40 (0x00000001uL) +#define GPIO_PMCSR4_PMCSR41 (0x00000002uL) +#define GPIO_PMCSR4_PMCSR42 (0x00000004uL) +#define GPIO_PMCSR4_PMCSR43 (0x00000008uL) +#define GPIO_PMCSR4_PMCSR44 (0x00000010uL) +#define GPIO_PMCSR4_PMCSR45 (0x00000020uL) +#define GPIO_PMCSR4_PMCSR46 (0x00000040uL) +#define GPIO_PMCSR4_PMCSR47 (0x00000080uL) +#define GPIO_PMCSR4_PMCSR48 (0x00000100uL) +#define GPIO_PMCSR4_PMCSR49 (0x00000200uL) +#define GPIO_PMCSR4_PMCSR410 (0x00000400uL) +#define GPIO_PMCSR4_PMCSR411 (0x00000800uL) +#define GPIO_PMCSR4_PMCSR412 (0x00001000uL) +#define GPIO_PMCSR4_PMCSR413 (0x00002000uL) +#define GPIO_PMCSR4_PMCSR414 (0x00004000uL) +#define GPIO_PMCSR4_PMCSR415 (0x00008000uL) +#define GPIO_PMCSR4_PMCSR416 (0x00010000uL) +#define GPIO_PMCSR4_PMCSR417 (0x00020000uL) +#define GPIO_PMCSR4_PMCSR418 (0x00040000uL) +#define GPIO_PMCSR4_PMCSR419 (0x00080000uL) +#define GPIO_PMCSR4_PMCSR420 (0x00100000uL) +#define GPIO_PMCSR4_PMCSR421 (0x00200000uL) +#define GPIO_PMCSR4_PMCSR422 (0x00400000uL) +#define GPIO_PMCSR4_PMCSR423 (0x00800000uL) +#define GPIO_PMCSR4_PMCSR424 (0x01000000uL) +#define GPIO_PMCSR4_PMCSR425 (0x02000000uL) +#define GPIO_PMCSR4_PMCSR426 (0x04000000uL) +#define GPIO_PMCSR4_PMCSR427 (0x08000000uL) +#define GPIO_PMCSR4_PMCSR428 (0x10000000uL) +#define GPIO_PMCSR4_PMCSR429 (0x20000000uL) +#define GPIO_PMCSR4_PMCSR430 (0x40000000uL) +#define GPIO_PMCSR4_PMCSR431 (0x80000000uL) + +#define GPIO_PFCAE4_PFCAE40 (0x0001u) +#define GPIO_PFCAE4_PFCAE41 (0x0002u) +#define GPIO_PFCAE4_PFCAE42 (0x0004u) +#define GPIO_PFCAE4_PFCAE43 (0x0008u) +#define GPIO_PFCAE4_PFCAE44 (0x0010u) +#define GPIO_PFCAE4_PFCAE45 (0x0020u) +#define GPIO_PFCAE4_PFCAE46 (0x0040u) +#define GPIO_PFCAE4_PFCAE47 (0x0080u) +#define GPIO_PFCAE4_PFCAE48 (0x0100u) +#define GPIO_PFCAE4_PFCAE49 (0x0200u) +#define GPIO_PFCAE4_PFCAE410 (0x0400u) +#define GPIO_PFCAE4_PFCAE411 (0x0800u) +#define GPIO_PFCAE4_PFCAE412 (0x1000u) +#define GPIO_PFCAE4_PFCAE413 (0x2000u) +#define GPIO_PFCAE4_PFCAE414 (0x4000u) +#define GPIO_PFCAE4_PFCAE415 (0x8000u) + +#define GPIO_PIBC4_PIBC40 (0x0001u) +#define GPIO_PIBC4_PIBC41 (0x0002u) +#define GPIO_PIBC4_PIBC42 (0x0004u) +#define GPIO_PIBC4_PIBC43 (0x0008u) +#define GPIO_PIBC4_PIBC44 (0x0010u) +#define GPIO_PIBC4_PIBC45 (0x0020u) +#define GPIO_PIBC4_PIBC46 (0x0040u) +#define GPIO_PIBC4_PIBC47 (0x0080u) +#define GPIO_PIBC4_PIBC48 (0x0100u) +#define GPIO_PIBC4_PIBC49 (0x0200u) +#define GPIO_PIBC4_PIBC410 (0x0400u) +#define GPIO_PIBC4_PIBC411 (0x0800u) +#define GPIO_PIBC4_PIBC412 (0x1000u) +#define GPIO_PIBC4_PIBC413 (0x2000u) +#define GPIO_PIBC4_PIBC414 (0x4000u) +#define GPIO_PIBC4_PIBC415 (0x8000u) + +#define GPIO_PBDC4_PBDC40 (0x0001u) +#define GPIO_PBDC4_PBDC41 (0x0002u) +#define GPIO_PBDC4_PBDC42 (0x0004u) +#define GPIO_PBDC4_PBDC43 (0x0008u) +#define GPIO_PBDC4_PBDC44 (0x0010u) +#define GPIO_PBDC4_PBDC45 (0x0020u) +#define GPIO_PBDC4_PBDC46 (0x0040u) +#define GPIO_PBDC4_PBDC47 (0x0080u) +#define GPIO_PBDC4_PBDC48 (0x0100u) +#define GPIO_PBDC4_PBDC49 (0x0200u) +#define GPIO_PBDC4_PBDC410 (0x0400u) +#define GPIO_PBDC4_PBDC411 (0x0800u) +#define GPIO_PBDC4_PBDC412 (0x1000u) +#define GPIO_PBDC4_PBDC413 (0x2000u) +#define GPIO_PBDC4_PBDC414 (0x4000u) +#define GPIO_PBDC4_PBDC415 (0x8000u) + +#define GPIO_PIPC4_PIPC40 (0x0001u) +#define GPIO_PIPC4_PIPC41 (0x0002u) +#define GPIO_PIPC4_PIPC42 (0x0004u) +#define GPIO_PIPC4_PIPC43 (0x0008u) +#define GPIO_PIPC4_PIPC44 (0x0010u) +#define GPIO_PIPC4_PIPC45 (0x0020u) +#define GPIO_PIPC4_PIPC46 (0x0040u) +#define GPIO_PIPC4_PIPC47 (0x0080u) +#define GPIO_PIPC4_PIPC48 (0x0100u) +#define GPIO_PIPC4_PIPC49 (0x0200u) +#define GPIO_PIPC4_PIPC410 (0x0400u) +#define GPIO_PIPC4_PIPC411 (0x0800u) +#define GPIO_PIPC4_PIPC412 (0x1000u) +#define GPIO_PIPC4_PIPC413 (0x2000u) +#define GPIO_PIPC4_PIPC414 (0x4000u) +#define GPIO_PIPC4_PIPC415 (0x8000u) + +/* ---- P5 ---- */ +#define GPIO_P5_P50 (0x0001u) +#define GPIO_P5_P51 (0x0002u) +#define GPIO_P5_P52 (0x0004u) +#define GPIO_P5_P53 (0x0008u) +#define GPIO_P5_P54 (0x0010u) +#define GPIO_P5_P55 (0x0020u) +#define GPIO_P5_P56 (0x0040u) +#define GPIO_P5_P57 (0x0080u) +#define GPIO_P5_P58 (0x0100u) +#define GPIO_P5_P59 (0x0200u) +#define GPIO_P5_P510 (0x0400u) + +#define GPIO_PSR5_PSR50 (0x00000001uL) +#define GPIO_PSR5_PSR51 (0x00000002uL) +#define GPIO_PSR5_PSR52 (0x00000004uL) +#define GPIO_PSR5_PSR53 (0x00000008uL) +#define GPIO_PSR5_PSR54 (0x00000010uL) +#define GPIO_PSR5_PSR55 (0x00000020uL) +#define GPIO_PSR5_PSR56 (0x00000040uL) +#define GPIO_PSR5_PSR57 (0x00000080uL) +#define GPIO_PSR5_PSR58 (0x00000100uL) +#define GPIO_PSR5_PSR59 (0x00000200uL) +#define GPIO_PSR5_PSR510 (0x00000400uL) +#define GPIO_PSR5_PSR516 (0x00010000uL) +#define GPIO_PSR5_PSR517 (0x00020000uL) +#define GPIO_PSR5_PSR518 (0x00040000uL) +#define GPIO_PSR5_PSR519 (0x00080000uL) +#define GPIO_PSR5_PSR520 (0x00100000uL) +#define GPIO_PSR5_PSR521 (0x00200000uL) +#define GPIO_PSR5_PSR522 (0x00400000uL) +#define GPIO_PSR5_PSR523 (0x00800000uL) +#define GPIO_PSR5_PSR524 (0x01000000uL) +#define GPIO_PSR5_PSR525 (0x02000000uL) +#define GPIO_PSR5_PSR526 (0x04000000uL) + +#define GPIO_PPR5_PPR50 (0x0001u) +#define GPIO_PPR5_PPR51 (0x0002u) +#define GPIO_PPR5_PPR52 (0x0004u) +#define GPIO_PPR5_PPR53 (0x0008u) +#define GPIO_PPR5_PPR54 (0x0010u) +#define GPIO_PPR5_PPR55 (0x0020u) +#define GPIO_PPR5_PPR56 (0x0040u) +#define GPIO_PPR5_PPR57 (0x0080u) +#define GPIO_PPR5_PPR58 (0x0100u) +#define GPIO_PPR5_PPR59 (0x0200u) +#define GPIO_PPR5_PPR510 (0x0400u) + +#define GPIO_PM5_PM50 (0x0001u) +#define GPIO_PM5_PM51 (0x0002u) +#define GPIO_PM5_PM52 (0x0004u) +#define GPIO_PM5_PM53 (0x0008u) +#define GPIO_PM5_PM54 (0x0010u) +#define GPIO_PM5_PM55 (0x0020u) +#define GPIO_PM5_PM56 (0x0040u) +#define GPIO_PM5_PM57 (0x0080u) +#define GPIO_PM5_PM58 (0x0100u) +#define GPIO_PM5_PM59 (0x0200u) +#define GPIO_PM5_PM510 (0x0400u) + +#define GPIO_PMC5_PMC50 (0x0001u) +#define GPIO_PMC5_PMC51 (0x0002u) +#define GPIO_PMC5_PMC52 (0x0004u) +#define GPIO_PMC5_PMC53 (0x0008u) +#define GPIO_PMC5_PMC54 (0x0010u) +#define GPIO_PMC5_PMC55 (0x0020u) +#define GPIO_PMC5_PMC56 (0x0040u) +#define GPIO_PMC5_PMC57 (0x0080u) +#define GPIO_PMC5_PMC58 (0x0100u) +#define GPIO_PMC5_PMC59 (0x0200u) +#define GPIO_PMC5_PMC510 (0x0400u) + +#define GPIO_PFC5_PFC50 (0x0001u) +#define GPIO_PFC5_PFC51 (0x0002u) +#define GPIO_PFC5_PFC52 (0x0004u) +#define GPIO_PFC5_PFC53 (0x0008u) +#define GPIO_PFC5_PFC54 (0x0010u) +#define GPIO_PFC5_PFC55 (0x0020u) +#define GPIO_PFC5_PFC56 (0x0040u) +#define GPIO_PFC5_PFC57 (0x0080u) +#define GPIO_PFC5_PFC58 (0x0100u) +#define GPIO_PFC5_PFC59 (0x0200u) +#define GPIO_PFC5_PFC510 (0x0400u) + +#define GPIO_PFCE5_PFCE50 (0x0001u) +#define GPIO_PFCE5_PFCE51 (0x0002u) +#define GPIO_PFCE5_PFCE52 (0x0004u) +#define GPIO_PFCE5_PFCE53 (0x0008u) +#define GPIO_PFCE5_PFCE54 (0x0010u) +#define GPIO_PFCE5_PFCE55 (0x0020u) +#define GPIO_PFCE5_PFCE56 (0x0040u) +#define GPIO_PFCE5_PFCE57 (0x0080u) +#define GPIO_PFCE5_PFCE58 (0x0100u) +#define GPIO_PFCE5_PFCE59 (0x0200u) +#define GPIO_PFCE5_PFCE510 (0x0400u) + +#define GPIO_PNOT5_PNOT50 (0x0001u) +#define GPIO_PNOT5_PNOT51 (0x0002u) +#define GPIO_PNOT5_PNOT52 (0x0004u) +#define GPIO_PNOT5_PNOT53 (0x0008u) +#define GPIO_PNOT5_PNOT54 (0x0010u) +#define GPIO_PNOT5_PNOT55 (0x0020u) +#define GPIO_PNOT5_PNOT56 (0x0040u) +#define GPIO_PNOT5_PNOT57 (0x0080u) +#define GPIO_PNOT5_PNOT58 (0x0100u) +#define GPIO_PNOT5_PNOT59 (0x0200u) +#define GPIO_PNOT5_PNOT510 (0x0400u) + +#define GPIO_PMSR5_PMSR50 (0x00000001uL) +#define GPIO_PMSR5_PMSR51 (0x00000002uL) +#define GPIO_PMSR5_PMSR52 (0x00000004uL) +#define GPIO_PMSR5_PMSR53 (0x00000008uL) +#define GPIO_PMSR5_PMSR54 (0x00000010uL) +#define GPIO_PMSR5_PMSR55 (0x00000020uL) +#define GPIO_PMSR5_PMSR56 (0x00000040uL) +#define GPIO_PMSR5_PMSR57 (0x00000080uL) +#define GPIO_PMSR5_PMSR58 (0x00000100uL) +#define GPIO_PMSR5_PMSR59 (0x00000200uL) +#define GPIO_PMSR5_PMSR510 (0x00000400uL) +#define GPIO_PMSR5_PMSR516 (0x00010000uL) +#define GPIO_PMSR5_PMSR517 (0x00020000uL) +#define GPIO_PMSR5_PMSR518 (0x00040000uL) +#define GPIO_PMSR5_PMSR519 (0x00080000uL) +#define GPIO_PMSR5_PMSR520 (0x00100000uL) +#define GPIO_PMSR5_PMSR521 (0x00200000uL) +#define GPIO_PMSR5_PMSR522 (0x00400000uL) +#define GPIO_PMSR5_PMSR523 (0x00800000uL) +#define GPIO_PMSR5_PMSR524 (0x01000000uL) +#define GPIO_PMSR5_PMSR525 (0x02000000uL) +#define GPIO_PMSR5_PMSR526 (0x04000000uL) + +#define GPIO_PMCSR5_PMCSR50 (0x00000001uL) +#define GPIO_PMCSR5_PMCSR51 (0x00000002uL) +#define GPIO_PMCSR5_PMCSR52 (0x00000004uL) +#define GPIO_PMCSR5_PMCSR53 (0x00000008uL) +#define GPIO_PMCSR5_PMCSR54 (0x00000010uL) +#define GPIO_PMCSR5_PMCSR55 (0x00000020uL) +#define GPIO_PMCSR5_PMCSR56 (0x00000040uL) +#define GPIO_PMCSR5_PMCSR57 (0x00000080uL) +#define GPIO_PMCSR5_PMCSR58 (0x00000100uL) +#define GPIO_PMCSR5_PMCSR59 (0x00000200uL) +#define GPIO_PMCSR5_PMCSR510 (0x00000400uL) +#define GPIO_PMCSR5_PMCSR516 (0x00010000uL) +#define GPIO_PMCSR5_PMCSR517 (0x00020000uL) +#define GPIO_PMCSR5_PMCSR518 (0x00040000uL) +#define GPIO_PMCSR5_PMCSR519 (0x00080000uL) +#define GPIO_PMCSR5_PMCSR520 (0x00100000uL) +#define GPIO_PMCSR5_PMCSR521 (0x00200000uL) +#define GPIO_PMCSR5_PMCSR522 (0x00400000uL) +#define GPIO_PMCSR5_PMCSR523 (0x00800000uL) +#define GPIO_PMCSR5_PMCSR524 (0x01000000uL) +#define GPIO_PMCSR5_PMCSR525 (0x02000000uL) +#define GPIO_PMCSR5_PMCSR526 (0x04000000uL) + +#define GPIO_PFCAE5_PFCAE50 (0x0001u) +#define GPIO_PFCAE5_PFCAE51 (0x0002u) +#define GPIO_PFCAE5_PFCAE52 (0x0004u) +#define GPIO_PFCAE5_PFCAE53 (0x0008u) +#define GPIO_PFCAE5_PFCAE54 (0x0010u) +#define GPIO_PFCAE5_PFCAE55 (0x0020u) +#define GPIO_PFCAE5_PFCAE56 (0x0040u) +#define GPIO_PFCAE5_PFCAE57 (0x0080u) +#define GPIO_PFCAE5_PFCAE58 (0x0100u) +#define GPIO_PFCAE5_PFCAE59 (0x0200u) +#define GPIO_PFCAE5_PFCAE510 (0x0400u) + +#define GPIO_PIBC5_PIBC50 (0x0001u) +#define GPIO_PIBC5_PIBC51 (0x0002u) +#define GPIO_PIBC5_PIBC52 (0x0004u) +#define GPIO_PIBC5_PIBC53 (0x0008u) +#define GPIO_PIBC5_PIBC54 (0x0010u) +#define GPIO_PIBC5_PIBC55 (0x0020u) +#define GPIO_PIBC5_PIBC56 (0x0040u) +#define GPIO_PIBC5_PIBC57 (0x0080u) +#define GPIO_PIBC5_PIBC58 (0x0100u) +#define GPIO_PIBC5_PIBC59 (0x0200u) +#define GPIO_PIBC5_PIBC510 (0x0400u) + +#define GPIO_PBDC5_PBDC50 (0x0001u) +#define GPIO_PBDC5_PBDC51 (0x0002u) +#define GPIO_PBDC5_PBDC52 (0x0004u) +#define GPIO_PBDC5_PBDC53 (0x0008u) +#define GPIO_PBDC5_PBDC54 (0x0010u) +#define GPIO_PBDC5_PBDC55 (0x0020u) +#define GPIO_PBDC5_PBDC56 (0x0040u) +#define GPIO_PBDC5_PBDC57 (0x0080u) +#define GPIO_PBDC5_PBDC58 (0x0100u) +#define GPIO_PBDC5_PBDC59 (0x0200u) +#define GPIO_PBDC5_PBDC510 (0x0400u) + +#define GPIO_PIPC5_PIPC50 (0x0001u) +#define GPIO_PIPC5_PIPC51 (0x0002u) +#define GPIO_PIPC5_PIPC52 (0x0004u) +#define GPIO_PIPC5_PIPC53 (0x0008u) +#define GPIO_PIPC5_PIPC54 (0x0010u) +#define GPIO_PIPC5_PIPC55 (0x0020u) +#define GPIO_PIPC5_PIPC56 (0x0040u) +#define GPIO_PIPC5_PIPC57 (0x0080u) +#define GPIO_PIPC5_PIPC58 (0x0100u) +#define GPIO_PIPC5_PIPC59 (0x0200u) +#define GPIO_PIPC5_PIPC510 (0x0400u) + +/* ---- P6 ---- */ +#define GPIO_P6_P60 (0x0001u) +#define GPIO_P6_P61 (0x0002u) +#define GPIO_P6_P62 (0x0004u) +#define GPIO_P6_P63 (0x0008u) +#define GPIO_P6_P64 (0x0010u) +#define GPIO_P6_P65 (0x0020u) +#define GPIO_P6_P66 (0x0040u) +#define GPIO_P6_P67 (0x0080u) +#define GPIO_P6_P68 (0x0100u) +#define GPIO_P6_P69 (0x0200u) +#define GPIO_P6_P610 (0x0400u) +#define GPIO_P6_P611 (0x0800u) +#define GPIO_P6_P612 (0x1000u) +#define GPIO_P6_P613 (0x2000u) +#define GPIO_P6_P614 (0x4000u) +#define GPIO_P6_P615 (0x8000u) + +#define GPIO_PSR6_PSR60 (0x00000001uL) +#define GPIO_PSR6_PSR61 (0x00000002uL) +#define GPIO_PSR6_PSR62 (0x00000004uL) +#define GPIO_PSR6_PSR63 (0x00000008uL) +#define GPIO_PSR6_PSR64 (0x00000010uL) +#define GPIO_PSR6_PSR65 (0x00000020uL) +#define GPIO_PSR6_PSR66 (0x00000040uL) +#define GPIO_PSR6_PSR67 (0x00000080uL) +#define GPIO_PSR6_PSR68 (0x00000100uL) +#define GPIO_PSR6_PSR69 (0x00000200uL) +#define GPIO_PSR6_PSR610 (0x00000400uL) +#define GPIO_PSR6_PSR611 (0x00000800uL) +#define GPIO_PSR6_PSR612 (0x00001000uL) +#define GPIO_PSR6_PSR613 (0x00002000uL) +#define GPIO_PSR6_PSR614 (0x00004000uL) +#define GPIO_PSR6_PSR615 (0x00008000uL) +#define GPIO_PSR6_PSR616 (0x00010000uL) +#define GPIO_PSR6_PSR617 (0x00020000uL) +#define GPIO_PSR6_PSR618 (0x00040000uL) +#define GPIO_PSR6_PSR619 (0x00080000uL) +#define GPIO_PSR6_PSR620 (0x00100000uL) +#define GPIO_PSR6_PSR621 (0x00200000uL) +#define GPIO_PSR6_PSR622 (0x00400000uL) +#define GPIO_PSR6_PSR623 (0x00800000uL) +#define GPIO_PSR6_PSR624 (0x01000000uL) +#define GPIO_PSR6_PSR625 (0x02000000uL) +#define GPIO_PSR6_PSR626 (0x04000000uL) +#define GPIO_PSR6_PSR627 (0x08000000uL) +#define GPIO_PSR6_PSR628 (0x10000000uL) +#define GPIO_PSR6_PSR629 (0x20000000uL) +#define GPIO_PSR6_PSR630 (0x40000000uL) +#define GPIO_PSR6_PSR631 (0x80000000uL) + +#define GPIO_PPR6_PPR60 (0x0001u) +#define GPIO_PPR6_PPR61 (0x0002u) +#define GPIO_PPR6_PPR62 (0x0004u) +#define GPIO_PPR6_PPR63 (0x0008u) +#define GPIO_PPR6_PPR64 (0x0010u) +#define GPIO_PPR6_PPR65 (0x0020u) +#define GPIO_PPR6_PPR66 (0x0040u) +#define GPIO_PPR6_PPR67 (0x0080u) +#define GPIO_PPR6_PPR68 (0x0100u) +#define GPIO_PPR6_PPR69 (0x0200u) +#define GPIO_PPR6_PPR610 (0x0400u) +#define GPIO_PPR6_PPR611 (0x0800u) +#define GPIO_PPR6_PPR612 (0x1000u) +#define GPIO_PPR6_PPR613 (0x2000u) +#define GPIO_PPR6_PPR614 (0x4000u) +#define GPIO_PPR6_PPR615 (0x8000u) + +#define GPIO_PM6_PM60 (0x0001u) +#define GPIO_PM6_PM61 (0x0002u) +#define GPIO_PM6_PM62 (0x0004u) +#define GPIO_PM6_PM63 (0x0008u) +#define GPIO_PM6_PM64 (0x0010u) +#define GPIO_PM6_PM65 (0x0020u) +#define GPIO_PM6_PM66 (0x0040u) +#define GPIO_PM6_PM67 (0x0080u) +#define GPIO_PM6_PM68 (0x0100u) +#define GPIO_PM6_PM69 (0x0200u) +#define GPIO_PM6_PM610 (0x0400u) +#define GPIO_PM6_PM611 (0x0800u) +#define GPIO_PM6_PM612 (0x1000u) +#define GPIO_PM6_PM613 (0x2000u) +#define GPIO_PM6_PM614 (0x4000u) +#define GPIO_PM6_PM615 (0x8000u) + +#define GPIO_PMC6_PMC60 (0x0001u) +#define GPIO_PMC6_PMC61 (0x0002u) +#define GPIO_PMC6_PMC62 (0x0004u) +#define GPIO_PMC6_PMC63 (0x0008u) +#define GPIO_PMC6_PMC64 (0x0010u) +#define GPIO_PMC6_PMC65 (0x0020u) +#define GPIO_PMC6_PMC66 (0x0040u) +#define GPIO_PMC6_PMC67 (0x0080u) +#define GPIO_PMC6_PMC68 (0x0100u) +#define GPIO_PMC6_PMC69 (0x0200u) +#define GPIO_PMC6_PMC610 (0x0400u) +#define GPIO_PMC6_PMC611 (0x0800u) +#define GPIO_PMC6_PMC612 (0x1000u) +#define GPIO_PMC6_PMC613 (0x2000u) +#define GPIO_PMC6_PMC614 (0x4000u) +#define GPIO_PMC6_PMC615 (0x8000u) + +#define GPIO_PFC6_PFC60 (0x0001u) +#define GPIO_PFC6_PFC61 (0x0002u) +#define GPIO_PFC6_PFC62 (0x0004u) +#define GPIO_PFC6_PFC63 (0x0008u) +#define GPIO_PFC6_PFC64 (0x0010u) +#define GPIO_PFC6_PFC65 (0x0020u) +#define GPIO_PFC6_PFC66 (0x0040u) +#define GPIO_PFC6_PFC67 (0x0080u) +#define GPIO_PFC6_PFC68 (0x0100u) +#define GPIO_PFC6_PFC69 (0x0200u) +#define GPIO_PFC6_PFC610 (0x0400u) +#define GPIO_PFC6_PFC611 (0x0800u) +#define GPIO_PFC6_PFC612 (0x1000u) +#define GPIO_PFC6_PFC613 (0x2000u) +#define GPIO_PFC6_PFC614 (0x4000u) +#define GPIO_PFC6_PFC615 (0x8000u) + +#define GPIO_PFCE6_PFCE60 (0x0001u) +#define GPIO_PFCE6_PFCE61 (0x0002u) +#define GPIO_PFCE6_PFCE62 (0x0004u) +#define GPIO_PFCE6_PFCE63 (0x0008u) +#define GPIO_PFCE6_PFCE64 (0x0010u) +#define GPIO_PFCE6_PFCE65 (0x0020u) +#define GPIO_PFCE6_PFCE66 (0x0040u) +#define GPIO_PFCE6_PFCE67 (0x0080u) +#define GPIO_PFCE6_PFCE68 (0x0100u) +#define GPIO_PFCE6_PFCE69 (0x0200u) +#define GPIO_PFCE6_PFCE610 (0x0400u) +#define GPIO_PFCE6_PFCE611 (0x0800u) +#define GPIO_PFCE6_PFCE612 (0x1000u) +#define GPIO_PFCE6_PFCE613 (0x2000u) +#define GPIO_PFCE6_PFCE614 (0x4000u) +#define GPIO_PFCE6_PFCE615 (0x8000u) + +#define GPIO_PNOT6_PNOT60 (0x0001u) +#define GPIO_PNOT6_PNOT61 (0x0002u) +#define GPIO_PNOT6_PNOT62 (0x0004u) +#define GPIO_PNOT6_PNOT63 (0x0008u) +#define GPIO_PNOT6_PNOT64 (0x0010u) +#define GPIO_PNOT6_PNOT65 (0x0020u) +#define GPIO_PNOT6_PNOT66 (0x0040u) +#define GPIO_PNOT6_PNOT67 (0x0080u) +#define GPIO_PNOT6_PNOT68 (0x0100u) +#define GPIO_PNOT6_PNOT69 (0x0200u) +#define GPIO_PNOT6_PNOT610 (0x0400u) +#define GPIO_PNOT6_PNOT611 (0x0800u) +#define GPIO_PNOT6_PNOT612 (0x1000u) +#define GPIO_PNOT6_PNOT613 (0x2000u) +#define GPIO_PNOT6_PNOT614 (0x4000u) +#define GPIO_PNOT6_PNOT615 (0x8000u) + +#define GPIO_PMSR6_PMSR60 (0x00000001uL) +#define GPIO_PMSR6_PMSR61 (0x00000002uL) +#define GPIO_PMSR6_PMSR62 (0x00000004uL) +#define GPIO_PMSR6_PMSR63 (0x00000008uL) +#define GPIO_PMSR6_PMSR64 (0x00000010uL) +#define GPIO_PMSR6_PMSR65 (0x00000020uL) +#define GPIO_PMSR6_PMSR66 (0x00000040uL) +#define GPIO_PMSR6_PMSR67 (0x00000080uL) +#define GPIO_PMSR6_PMSR68 (0x00000100uL) +#define GPIO_PMSR6_PMSR69 (0x00000200uL) +#define GPIO_PMSR6_PMSR610 (0x00000400uL) +#define GPIO_PMSR6_PMSR611 (0x00000800uL) +#define GPIO_PMSR6_PMSR612 (0x00001000uL) +#define GPIO_PMSR6_PMSR613 (0x00002000uL) +#define GPIO_PMSR6_PMSR614 (0x00004000uL) +#define GPIO_PMSR6_PMSR615 (0x00008000uL) +#define GPIO_PMSR6_PMSR616 (0x00010000uL) +#define GPIO_PMSR6_PMSR617 (0x00020000uL) +#define GPIO_PMSR6_PMSR618 (0x00040000uL) +#define GPIO_PMSR6_PMSR619 (0x00080000uL) +#define GPIO_PMSR6_PMSR620 (0x00100000uL) +#define GPIO_PMSR6_PMSR621 (0x00200000uL) +#define GPIO_PMSR6_PMSR622 (0x00400000uL) +#define GPIO_PMSR6_PMSR623 (0x00800000uL) +#define GPIO_PMSR6_PMSR624 (0x01000000uL) +#define GPIO_PMSR6_PMSR625 (0x02000000uL) +#define GPIO_PMSR6_PMSR626 (0x04000000uL) +#define GPIO_PMSR6_PMSR627 (0x08000000uL) +#define GPIO_PMSR6_PMSR628 (0x10000000uL) +#define GPIO_PMSR6_PMSR629 (0x20000000uL) +#define GPIO_PMSR6_PMSR630 (0x40000000uL) +#define GPIO_PMSR6_PMSR631 (0x80000000uL) + +#define GPIO_PMCSR6_PMCSR60 (0x00000001uL) +#define GPIO_PMCSR6_PMCSR61 (0x00000002uL) +#define GPIO_PMCSR6_PMCSR62 (0x00000004uL) +#define GPIO_PMCSR6_PMCSR63 (0x00000008uL) +#define GPIO_PMCSR6_PMCSR64 (0x00000010uL) +#define GPIO_PMCSR6_PMCSR65 (0x00000020uL) +#define GPIO_PMCSR6_PMCSR66 (0x00000040uL) +#define GPIO_PMCSR6_PMCSR67 (0x00000080uL) +#define GPIO_PMCSR6_PMCSR68 (0x00000100uL) +#define GPIO_PMCSR6_PMCSR69 (0x00000200uL) +#define GPIO_PMCSR6_PMCSR610 (0x00000400uL) +#define GPIO_PMCSR6_PMCSR611 (0x00000800uL) +#define GPIO_PMCSR6_PMCSR612 (0x00001000uL) +#define GPIO_PMCSR6_PMCSR613 (0x00002000uL) +#define GPIO_PMCSR6_PMCSR614 (0x00004000uL) +#define GPIO_PMCSR6_PMCSR615 (0x00008000uL) +#define GPIO_PMCSR6_PMCSR616 (0x00010000uL) +#define GPIO_PMCSR6_PMCSR617 (0x00020000uL) +#define GPIO_PMCSR6_PMCSR618 (0x00040000uL) +#define GPIO_PMCSR6_PMCSR619 (0x00080000uL) +#define GPIO_PMCSR6_PMCSR620 (0x00100000uL) +#define GPIO_PMCSR6_PMCSR621 (0x00200000uL) +#define GPIO_PMCSR6_PMCSR622 (0x00400000uL) +#define GPIO_PMCSR6_PMCSR623 (0x00800000uL) +#define GPIO_PMCSR6_PMCSR624 (0x01000000uL) +#define GPIO_PMCSR6_PMCSR625 (0x02000000uL) +#define GPIO_PMCSR6_PMCSR626 (0x04000000uL) +#define GPIO_PMCSR6_PMCSR627 (0x08000000uL) +#define GPIO_PMCSR6_PMCSR628 (0x10000000uL) +#define GPIO_PMCSR6_PMCSR629 (0x20000000uL) +#define GPIO_PMCSR6_PMCSR630 (0x40000000uL) +#define GPIO_PMCSR6_PMCSR631 (0x80000000uL) + +#define GPIO_PFCAE6_PFCAE60 (0x0001u) +#define GPIO_PFCAE6_PFCAE61 (0x0002u) +#define GPIO_PFCAE6_PFCAE62 (0x0004u) +#define GPIO_PFCAE6_PFCAE63 (0x0008u) +#define GPIO_PFCAE6_PFCAE64 (0x0010u) +#define GPIO_PFCAE6_PFCAE65 (0x0020u) +#define GPIO_PFCAE6_PFCAE66 (0x0040u) +#define GPIO_PFCAE6_PFCAE67 (0x0080u) +#define GPIO_PFCAE6_PFCAE68 (0x0100u) +#define GPIO_PFCAE6_PFCAE69 (0x0200u) +#define GPIO_PFCAE6_PFCAE610 (0x0400u) +#define GPIO_PFCAE6_PFCAE611 (0x0800u) +#define GPIO_PFCAE6_PFCAE612 (0x1000u) +#define GPIO_PFCAE6_PFCAE613 (0x2000u) +#define GPIO_PFCAE6_PFCAE614 (0x4000u) +#define GPIO_PFCAE6_PFCAE615 (0x8000u) + +#define GPIO_PIBC6_PIBC60 (0x0001u) +#define GPIO_PIBC6_PIBC61 (0x0002u) +#define GPIO_PIBC6_PIBC62 (0x0004u) +#define GPIO_PIBC6_PIBC63 (0x0008u) +#define GPIO_PIBC6_PIBC64 (0x0010u) +#define GPIO_PIBC6_PIBC65 (0x0020u) +#define GPIO_PIBC6_PIBC66 (0x0040u) +#define GPIO_PIBC6_PIBC67 (0x0080u) +#define GPIO_PIBC6_PIBC68 (0x0100u) +#define GPIO_PIBC6_PIBC69 (0x0200u) +#define GPIO_PIBC6_PIBC610 (0x0400u) +#define GPIO_PIBC6_PIBC611 (0x0800u) +#define GPIO_PIBC6_PIBC612 (0x1000u) +#define GPIO_PIBC6_PIBC613 (0x2000u) +#define GPIO_PIBC6_PIBC614 (0x4000u) +#define GPIO_PIBC6_PIBC615 (0x8000u) + +#define GPIO_PBDC6_PBDC60 (0x0001u) +#define GPIO_PBDC6_PBDC61 (0x0002u) +#define GPIO_PBDC6_PBDC62 (0x0004u) +#define GPIO_PBDC6_PBDC63 (0x0008u) +#define GPIO_PBDC6_PBDC64 (0x0010u) +#define GPIO_PBDC6_PBDC65 (0x0020u) +#define GPIO_PBDC6_PBDC66 (0x0040u) +#define GPIO_PBDC6_PBDC67 (0x0080u) +#define GPIO_PBDC6_PBDC68 (0x0100u) +#define GPIO_PBDC6_PBDC69 (0x0200u) +#define GPIO_PBDC6_PBDC610 (0x0400u) +#define GPIO_PBDC6_PBDC611 (0x0800u) +#define GPIO_PBDC6_PBDC612 (0x1000u) +#define GPIO_PBDC6_PBDC613 (0x2000u) +#define GPIO_PBDC6_PBDC614 (0x4000u) +#define GPIO_PBDC6_PBDC615 (0x8000u) + +#define GPIO_PIPC6_PIPC60 (0x0001u) +#define GPIO_PIPC6_PIPC61 (0x0002u) +#define GPIO_PIPC6_PIPC62 (0x0004u) +#define GPIO_PIPC6_PIPC63 (0x0008u) +#define GPIO_PIPC6_PIPC64 (0x0010u) +#define GPIO_PIPC6_PIPC65 (0x0020u) +#define GPIO_PIPC6_PIPC66 (0x0040u) +#define GPIO_PIPC6_PIPC67 (0x0080u) +#define GPIO_PIPC6_PIPC68 (0x0100u) +#define GPIO_PIPC6_PIPC69 (0x0200u) +#define GPIO_PIPC6_PIPC610 (0x0400u) +#define GPIO_PIPC6_PIPC611 (0x0800u) +#define GPIO_PIPC6_PIPC612 (0x1000u) +#define GPIO_PIPC6_PIPC613 (0x2000u) +#define GPIO_PIPC6_PIPC614 (0x4000u) +#define GPIO_PIPC6_PIPC615 (0x8000u) + +/* ---- P7 ---- */ +#define GPIO_P7_P70 (0x0001u) +#define GPIO_P7_P71 (0x0002u) +#define GPIO_P7_P72 (0x0004u) +#define GPIO_P7_P73 (0x0008u) +#define GPIO_P7_P74 (0x0010u) +#define GPIO_P7_P75 (0x0020u) +#define GPIO_P7_P76 (0x0040u) +#define GPIO_P7_P77 (0x0080u) +#define GPIO_P7_P78 (0x0100u) +#define GPIO_P7_P79 (0x0200u) +#define GPIO_P7_P710 (0x0400u) +#define GPIO_P7_P711 (0x0800u) +#define GPIO_P7_P712 (0x1000u) +#define GPIO_P7_P713 (0x2000u) +#define GPIO_P7_P714 (0x4000u) +#define GPIO_P7_P715 (0x8000u) + +#define GPIO_PSR7_PSR70 (0x00000001uL) +#define GPIO_PSR7_PSR71 (0x00000002uL) +#define GPIO_PSR7_PSR72 (0x00000004uL) +#define GPIO_PSR7_PSR73 (0x00000008uL) +#define GPIO_PSR7_PSR74 (0x00000010uL) +#define GPIO_PSR7_PSR75 (0x00000020uL) +#define GPIO_PSR7_PSR76 (0x00000040uL) +#define GPIO_PSR7_PSR77 (0x00000080uL) +#define GPIO_PSR7_PSR78 (0x00000100uL) +#define GPIO_PSR7_PSR79 (0x00000200uL) +#define GPIO_PSR7_PSR710 (0x00000400uL) +#define GPIO_PSR7_PSR711 (0x00000800uL) +#define GPIO_PSR7_PSR712 (0x00001000uL) +#define GPIO_PSR7_PSR713 (0x00002000uL) +#define GPIO_PSR7_PSR714 (0x00004000uL) +#define GPIO_PSR7_PSR715 (0x00008000uL) +#define GPIO_PSR7_PSR716 (0x00010000uL) +#define GPIO_PSR7_PSR717 (0x00020000uL) +#define GPIO_PSR7_PSR718 (0x00040000uL) +#define GPIO_PSR7_PSR719 (0x00080000uL) +#define GPIO_PSR7_PSR720 (0x00100000uL) +#define GPIO_PSR7_PSR721 (0x00200000uL) +#define GPIO_PSR7_PSR722 (0x00400000uL) +#define GPIO_PSR7_PSR723 (0x00800000uL) +#define GPIO_PSR7_PSR724 (0x01000000uL) +#define GPIO_PSR7_PSR725 (0x02000000uL) +#define GPIO_PSR7_PSR726 (0x04000000uL) +#define GPIO_PSR7_PSR727 (0x08000000uL) +#define GPIO_PSR7_PSR728 (0x10000000uL) +#define GPIO_PSR7_PSR729 (0x20000000uL) +#define GPIO_PSR7_PSR730 (0x40000000uL) +#define GPIO_PSR7_PSR731 (0x80000000uL) + +#define GPIO_PPR7_PPR70 (0x0001u) +#define GPIO_PPR7_PPR71 (0x0002u) +#define GPIO_PPR7_PPR72 (0x0004u) +#define GPIO_PPR7_PPR73 (0x0008u) +#define GPIO_PPR7_PPR74 (0x0010u) +#define GPIO_PPR7_PPR75 (0x0020u) +#define GPIO_PPR7_PPR76 (0x0040u) +#define GPIO_PPR7_PPR77 (0x0080u) +#define GPIO_PPR7_PPR78 (0x0100u) +#define GPIO_PPR7_PPR79 (0x0200u) +#define GPIO_PPR7_PPR710 (0x0400u) +#define GPIO_PPR7_PPR711 (0x0800u) +#define GPIO_PPR7_PPR712 (0x1000u) +#define GPIO_PPR7_PPR713 (0x2000u) +#define GPIO_PPR7_PPR714 (0x4000u) +#define GPIO_PPR7_PPR715 (0x8000u) + +#define GPIO_PM7_PM70 (0x0001u) +#define GPIO_PM7_PM71 (0x0002u) +#define GPIO_PM7_PM72 (0x0004u) +#define GPIO_PM7_PM73 (0x0008u) +#define GPIO_PM7_PM74 (0x0010u) +#define GPIO_PM7_PM75 (0x0020u) +#define GPIO_PM7_PM76 (0x0040u) +#define GPIO_PM7_PM77 (0x0080u) +#define GPIO_PM7_PM78 (0x0100u) +#define GPIO_PM7_PM79 (0x0200u) +#define GPIO_PM7_PM710 (0x0400u) +#define GPIO_PM7_PM711 (0x0800u) +#define GPIO_PM7_PM712 (0x1000u) +#define GPIO_PM7_PM713 (0x2000u) +#define GPIO_PM7_PM714 (0x4000u) +#define GPIO_PM7_PM715 (0x8000u) + +#define GPIO_PMC7_PMC70 (0x0001u) +#define GPIO_PMC7_PMC71 (0x0002u) +#define GPIO_PMC7_PMC72 (0x0004u) +#define GPIO_PMC7_PMC73 (0x0008u) +#define GPIO_PMC7_PMC74 (0x0010u) +#define GPIO_PMC7_PMC75 (0x0020u) +#define GPIO_PMC7_PMC76 (0x0040u) +#define GPIO_PMC7_PMC77 (0x0080u) +#define GPIO_PMC7_PMC78 (0x0100u) +#define GPIO_PMC7_PMC79 (0x0200u) +#define GPIO_PMC7_PMC710 (0x0400u) +#define GPIO_PMC7_PMC711 (0x0800u) +#define GPIO_PMC7_PMC712 (0x1000u) +#define GPIO_PMC7_PMC713 (0x2000u) +#define GPIO_PMC7_PMC714 (0x4000u) +#define GPIO_PMC7_PMC715 (0x8000u) + +#define GPIO_PFC7_PFC70 (0x0001u) +#define GPIO_PFC7_PFC71 (0x0002u) +#define GPIO_PFC7_PFC72 (0x0004u) +#define GPIO_PFC7_PFC73 (0x0008u) +#define GPIO_PFC7_PFC74 (0x0010u) +#define GPIO_PFC7_PFC75 (0x0020u) +#define GPIO_PFC7_PFC76 (0x0040u) +#define GPIO_PFC7_PFC77 (0x0080u) +#define GPIO_PFC7_PFC78 (0x0100u) +#define GPIO_PFC7_PFC79 (0x0200u) +#define GPIO_PFC7_PFC710 (0x0400u) +#define GPIO_PFC7_PFC711 (0x0800u) +#define GPIO_PFC7_PFC712 (0x1000u) +#define GPIO_PFC7_PFC713 (0x2000u) +#define GPIO_PFC7_PFC714 (0x4000u) +#define GPIO_PFC7_PFC715 (0x8000u) + +#define GPIO_PFCE7_PFCE70 (0x0001u) +#define GPIO_PFCE7_PFCE71 (0x0002u) +#define GPIO_PFCE7_PFCE72 (0x0004u) +#define GPIO_PFCE7_PFCE73 (0x0008u) +#define GPIO_PFCE7_PFCE74 (0x0010u) +#define GPIO_PFCE7_PFCE75 (0x0020u) +#define GPIO_PFCE7_PFCE76 (0x0040u) +#define GPIO_PFCE7_PFCE77 (0x0080u) +#define GPIO_PFCE7_PFCE78 (0x0100u) +#define GPIO_PFCE7_PFCE79 (0x0200u) +#define GPIO_PFCE7_PFCE710 (0x0400u) +#define GPIO_PFCE7_PFCE711 (0x0800u) +#define GPIO_PFCE7_PFCE712 (0x1000u) +#define GPIO_PFCE7_PFCE713 (0x2000u) +#define GPIO_PFCE7_PFCE714 (0x4000u) +#define GPIO_PFCE7_PFCE715 (0x8000u) + +#define GPIO_PNOT7_PNOT70 (0x0001u) +#define GPIO_PNOT7_PNOT71 (0x0002u) +#define GPIO_PNOT7_PNOT72 (0x0004u) +#define GPIO_PNOT7_PNOT73 (0x0008u) +#define GPIO_PNOT7_PNOT74 (0x0010u) +#define GPIO_PNOT7_PNOT75 (0x0020u) +#define GPIO_PNOT7_PNOT76 (0x0040u) +#define GPIO_PNOT7_PNOT77 (0x0080u) +#define GPIO_PNOT7_PNOT78 (0x0100u) +#define GPIO_PNOT7_PNOT79 (0x0200u) +#define GPIO_PNOT7_PNOT710 (0x0400u) +#define GPIO_PNOT7_PNOT711 (0x0800u) +#define GPIO_PNOT7_PNOT712 (0x1000u) +#define GPIO_PNOT7_PNOT713 (0x2000u) +#define GPIO_PNOT7_PNOT714 (0x4000u) +#define GPIO_PNOT7_PNOT715 (0x8000u) + +#define GPIO_PMSR7_PMSR70 (0x00000001uL) +#define GPIO_PMSR7_PMSR71 (0x00000002uL) +#define GPIO_PMSR7_PMSR72 (0x00000004uL) +#define GPIO_PMSR7_PMSR73 (0x00000008uL) +#define GPIO_PMSR7_PMSR74 (0x00000010uL) +#define GPIO_PMSR7_PMSR75 (0x00000020uL) +#define GPIO_PMSR7_PMSR76 (0x00000040uL) +#define GPIO_PMSR7_PMSR77 (0x00000080uL) +#define GPIO_PMSR7_PMSR78 (0x00000100uL) +#define GPIO_PMSR7_PMSR79 (0x00000200uL) +#define GPIO_PMSR7_PMSR710 (0x00000400uL) +#define GPIO_PMSR7_PMSR711 (0x00000800uL) +#define GPIO_PMSR7_PMSR712 (0x00001000uL) +#define GPIO_PMSR7_PMSR713 (0x00002000uL) +#define GPIO_PMSR7_PMSR714 (0x00004000uL) +#define GPIO_PMSR7_PMSR715 (0x00008000uL) +#define GPIO_PMSR7_PMSR716 (0x00010000uL) +#define GPIO_PMSR7_PMSR717 (0x00020000uL) +#define GPIO_PMSR7_PMSR718 (0x00040000uL) +#define GPIO_PMSR7_PMSR719 (0x00080000uL) +#define GPIO_PMSR7_PMSR720 (0x00100000uL) +#define GPIO_PMSR7_PMSR721 (0x00200000uL) +#define GPIO_PMSR7_PMSR722 (0x00400000uL) +#define GPIO_PMSR7_PMSR723 (0x00800000uL) +#define GPIO_PMSR7_PMSR724 (0x01000000uL) +#define GPIO_PMSR7_PMSR725 (0x02000000uL) +#define GPIO_PMSR7_PMSR726 (0x04000000uL) +#define GPIO_PMSR7_PMSR727 (0x08000000uL) +#define GPIO_PMSR7_PMSR728 (0x10000000uL) +#define GPIO_PMSR7_PMSR729 (0x20000000uL) +#define GPIO_PMSR7_PMSR730 (0x40000000uL) +#define GPIO_PMSR7_PMSR731 (0x80000000uL) + +#define GPIO_PMCSR7_PMCSR70 (0x00000001uL) +#define GPIO_PMCSR7_PMCSR71 (0x00000002uL) +#define GPIO_PMCSR7_PMCSR72 (0x00000004uL) +#define GPIO_PMCSR7_PMCSR73 (0x00000008uL) +#define GPIO_PMCSR7_PMCSR74 (0x00000010uL) +#define GPIO_PMCSR7_PMCSR75 (0x00000020uL) +#define GPIO_PMCSR7_PMCSR76 (0x00000040uL) +#define GPIO_PMCSR7_PMCSR77 (0x00000080uL) +#define GPIO_PMCSR7_PMCSR78 (0x00000100uL) +#define GPIO_PMCSR7_PMCSR79 (0x00000200uL) +#define GPIO_PMCSR7_PMCSR710 (0x00000400uL) +#define GPIO_PMCSR7_PMCSR711 (0x00000800uL) +#define GPIO_PMCSR7_PMCSR712 (0x00001000uL) +#define GPIO_PMCSR7_PMCSR713 (0x00002000uL) +#define GPIO_PMCSR7_PMCSR714 (0x00004000uL) +#define GPIO_PMCSR7_PMCSR715 (0x00008000uL) +#define GPIO_PMCSR7_PMCSR716 (0x00010000uL) +#define GPIO_PMCSR7_PMCSR717 (0x00020000uL) +#define GPIO_PMCSR7_PMCSR718 (0x00040000uL) +#define GPIO_PMCSR7_PMCSR719 (0x00080000uL) +#define GPIO_PMCSR7_PMCSR720 (0x00100000uL) +#define GPIO_PMCSR7_PMCSR721 (0x00200000uL) +#define GPIO_PMCSR7_PMCSR722 (0x00400000uL) +#define GPIO_PMCSR7_PMCSR723 (0x00800000uL) +#define GPIO_PMCSR7_PMCSR724 (0x01000000uL) +#define GPIO_PMCSR7_PMCSR725 (0x02000000uL) +#define GPIO_PMCSR7_PMCSR726 (0x04000000uL) +#define GPIO_PMCSR7_PMCSR727 (0x08000000uL) +#define GPIO_PMCSR7_PMCSR728 (0x10000000uL) +#define GPIO_PMCSR7_PMCSR729 (0x20000000uL) +#define GPIO_PMCSR7_PMCSR730 (0x40000000uL) +#define GPIO_PMCSR7_PMCSR731 (0x80000000uL) + +#define GPIO_PFCAE7_PFCAE70 (0x0001u) +#define GPIO_PFCAE7_PFCAE71 (0x0002u) +#define GPIO_PFCAE7_PFCAE72 (0x0004u) +#define GPIO_PFCAE7_PFCAE73 (0x0008u) +#define GPIO_PFCAE7_PFCAE74 (0x0010u) +#define GPIO_PFCAE7_PFCAE75 (0x0020u) +#define GPIO_PFCAE7_PFCAE76 (0x0040u) +#define GPIO_PFCAE7_PFCAE77 (0x0080u) +#define GPIO_PFCAE7_PFCAE78 (0x0100u) +#define GPIO_PFCAE7_PFCAE79 (0x0200u) +#define GPIO_PFCAE7_PFCAE710 (0x0400u) +#define GPIO_PFCAE7_PFCAE711 (0x0800u) +#define GPIO_PFCAE7_PFCAE712 (0x1000u) +#define GPIO_PFCAE7_PFCAE713 (0x2000u) +#define GPIO_PFCAE7_PFCAE714 (0x4000u) +#define GPIO_PFCAE7_PFCAE715 (0x8000u) + +#define GPIO_PIBC7_PIBC70 (0x0001u) +#define GPIO_PIBC7_PIBC71 (0x0002u) +#define GPIO_PIBC7_PIBC72 (0x0004u) +#define GPIO_PIBC7_PIBC73 (0x0008u) +#define GPIO_PIBC7_PIBC74 (0x0010u) +#define GPIO_PIBC7_PIBC75 (0x0020u) +#define GPIO_PIBC7_PIBC76 (0x0040u) +#define GPIO_PIBC7_PIBC77 (0x0080u) +#define GPIO_PIBC7_PIBC78 (0x0100u) +#define GPIO_PIBC7_PIBC79 (0x0200u) +#define GPIO_PIBC7_PIBC710 (0x0400u) +#define GPIO_PIBC7_PIBC711 (0x0800u) +#define GPIO_PIBC7_PIBC712 (0x1000u) +#define GPIO_PIBC7_PIBC713 (0x2000u) +#define GPIO_PIBC7_PIBC714 (0x4000u) +#define GPIO_PIBC7_PIBC715 (0x8000u) + +#define GPIO_PBDC7_PBDC70 (0x0001u) +#define GPIO_PBDC7_PBDC71 (0x0002u) +#define GPIO_PBDC7_PBDC72 (0x0004u) +#define GPIO_PBDC7_PBDC73 (0x0008u) +#define GPIO_PBDC7_PBDC74 (0x0010u) +#define GPIO_PBDC7_PBDC75 (0x0020u) +#define GPIO_PBDC7_PBDC76 (0x0040u) +#define GPIO_PBDC7_PBDC77 (0x0080u) +#define GPIO_PBDC7_PBDC78 (0x0100u) +#define GPIO_PBDC7_PBDC79 (0x0200u) +#define GPIO_PBDC7_PBDC710 (0x0400u) +#define GPIO_PBDC7_PBDC711 (0x0800u) +#define GPIO_PBDC7_PBDC712 (0x1000u) +#define GPIO_PBDC7_PBDC713 (0x2000u) +#define GPIO_PBDC7_PBDC714 (0x4000u) +#define GPIO_PBDC7_PBDC715 (0x8000u) + +#define GPIO_PIPC7_PIPC70 (0x0001u) +#define GPIO_PIPC7_PIPC71 (0x0002u) +#define GPIO_PIPC7_PIPC72 (0x0004u) +#define GPIO_PIPC7_PIPC73 (0x0008u) +#define GPIO_PIPC7_PIPC74 (0x0010u) +#define GPIO_PIPC7_PIPC75 (0x0020u) +#define GPIO_PIPC7_PIPC76 (0x0040u) +#define GPIO_PIPC7_PIPC77 (0x0080u) +#define GPIO_PIPC7_PIPC78 (0x0100u) +#define GPIO_PIPC7_PIPC79 (0x0200u) +#define GPIO_PIPC7_PIPC710 (0x0400u) +#define GPIO_PIPC7_PIPC711 (0x0800u) +#define GPIO_PIPC7_PIPC712 (0x1000u) +#define GPIO_PIPC7_PIPC713 (0x2000u) +#define GPIO_PIPC7_PIPC714 (0x4000u) +#define GPIO_PIPC7_PIPC715 (0x8000u) + +/* ---- P8 ---- */ +#define GPIO_P8_P80 (0x0001u) +#define GPIO_P8_P81 (0x0002u) +#define GPIO_P8_P82 (0x0004u) +#define GPIO_P8_P83 (0x0008u) +#define GPIO_P8_P84 (0x0010u) +#define GPIO_P8_P85 (0x0020u) +#define GPIO_P8_P86 (0x0040u) +#define GPIO_P8_P87 (0x0080u) +#define GPIO_P8_P88 (0x0100u) +#define GPIO_P8_P89 (0x0200u) +#define GPIO_P8_P810 (0x0400u) +#define GPIO_P8_P811 (0x0800u) +#define GPIO_P8_P812 (0x1000u) +#define GPIO_P8_P813 (0x2000u) +#define GPIO_P8_P814 (0x4000u) +#define GPIO_P8_P815 (0x8000u) + +#define GPIO_PSR8_PSR80 (0x00000001uL) +#define GPIO_PSR8_PSR81 (0x00000002uL) +#define GPIO_PSR8_PSR82 (0x00000004uL) +#define GPIO_PSR8_PSR83 (0x00000008uL) +#define GPIO_PSR8_PSR84 (0x00000010uL) +#define GPIO_PSR8_PSR85 (0x00000020uL) +#define GPIO_PSR8_PSR86 (0x00000040uL) +#define GPIO_PSR8_PSR87 (0x00000080uL) +#define GPIO_PSR8_PSR88 (0x00000100uL) +#define GPIO_PSR8_PSR89 (0x00000200uL) +#define GPIO_PSR8_PSR810 (0x00000400uL) +#define GPIO_PSR8_PSR811 (0x00000800uL) +#define GPIO_PSR8_PSR812 (0x00001000uL) +#define GPIO_PSR8_PSR813 (0x00002000uL) +#define GPIO_PSR8_PSR814 (0x00004000uL) +#define GPIO_PSR8_PSR815 (0x00008000uL) +#define GPIO_PSR8_PSR816 (0x00010000uL) +#define GPIO_PSR8_PSR817 (0x00020000uL) +#define GPIO_PSR8_PSR818 (0x00040000uL) +#define GPIO_PSR8_PSR819 (0x00080000uL) +#define GPIO_PSR8_PSR820 (0x00100000uL) +#define GPIO_PSR8_PSR821 (0x00200000uL) +#define GPIO_PSR8_PSR822 (0x00400000uL) +#define GPIO_PSR8_PSR823 (0x00800000uL) +#define GPIO_PSR8_PSR824 (0x01000000uL) +#define GPIO_PSR8_PSR825 (0x02000000uL) +#define GPIO_PSR8_PSR826 (0x04000000uL) +#define GPIO_PSR8_PSR827 (0x08000000uL) +#define GPIO_PSR8_PSR828 (0x10000000uL) +#define GPIO_PSR8_PSR829 (0x20000000uL) +#define GPIO_PSR8_PSR830 (0x40000000uL) +#define GPIO_PSR8_PSR831 (0x80000000uL) + +#define GPIO_PPR8_PPR80 (0x0001u) +#define GPIO_PPR8_PPR81 (0x0002u) +#define GPIO_PPR8_PPR82 (0x0004u) +#define GPIO_PPR8_PPR83 (0x0008u) +#define GPIO_PPR8_PPR84 (0x0010u) +#define GPIO_PPR8_PPR85 (0x0020u) +#define GPIO_PPR8_PPR86 (0x0040u) +#define GPIO_PPR8_PPR87 (0x0080u) +#define GPIO_PPR8_PPR88 (0x0100u) +#define GPIO_PPR8_PPR89 (0x0200u) +#define GPIO_PPR8_PPR810 (0x0400u) +#define GPIO_PPR8_PPR811 (0x0800u) +#define GPIO_PPR8_PPR812 (0x1000u) +#define GPIO_PPR8_PPR813 (0x2000u) +#define GPIO_PPR8_PPR814 (0x4000u) +#define GPIO_PPR8_PPR815 (0x8000u) + +#define GPIO_PM8_PM80 (0x0001u) +#define GPIO_PM8_PM81 (0x0002u) +#define GPIO_PM8_PM82 (0x0004u) +#define GPIO_PM8_PM83 (0x0008u) +#define GPIO_PM8_PM84 (0x0010u) +#define GPIO_PM8_PM85 (0x0020u) +#define GPIO_PM8_PM86 (0x0040u) +#define GPIO_PM8_PM87 (0x0080u) +#define GPIO_PM8_PM88 (0x0100u) +#define GPIO_PM8_PM89 (0x0200u) +#define GPIO_PM8_PM810 (0x0400u) +#define GPIO_PM8_PM811 (0x0800u) +#define GPIO_PM8_PM812 (0x1000u) +#define GPIO_PM8_PM813 (0x2000u) +#define GPIO_PM8_PM814 (0x4000u) +#define GPIO_PM8_PM815 (0x8000u) + +#define GPIO_PMC8_PMC80 (0x0001u) +#define GPIO_PMC8_PMC81 (0x0002u) +#define GPIO_PMC8_PMC82 (0x0004u) +#define GPIO_PMC8_PMC83 (0x0008u) +#define GPIO_PMC8_PMC84 (0x0010u) +#define GPIO_PMC8_PMC85 (0x0020u) +#define GPIO_PMC8_PMC86 (0x0040u) +#define GPIO_PMC8_PMC87 (0x0080u) +#define GPIO_PMC8_PMC88 (0x0100u) +#define GPIO_PMC8_PMC89 (0x0200u) +#define GPIO_PMC8_PMC810 (0x0400u) +#define GPIO_PMC8_PMC811 (0x0800u) +#define GPIO_PMC8_PMC812 (0x1000u) +#define GPIO_PMC8_PMC813 (0x2000u) +#define GPIO_PMC8_PMC814 (0x4000u) +#define GPIO_PMC8_PMC815 (0x8000u) + +#define GPIO_PFC8_PFC80 (0x0001u) +#define GPIO_PFC8_PFC81 (0x0002u) +#define GPIO_PFC8_PFC82 (0x0004u) +#define GPIO_PFC8_PFC83 (0x0008u) +#define GPIO_PFC8_PFC84 (0x0010u) +#define GPIO_PFC8_PFC85 (0x0020u) +#define GPIO_PFC8_PFC86 (0x0040u) +#define GPIO_PFC8_PFC87 (0x0080u) +#define GPIO_PFC8_PFC88 (0x0100u) +#define GPIO_PFC8_PFC89 (0x0200u) +#define GPIO_PFC8_PFC810 (0x0400u) +#define GPIO_PFC8_PFC811 (0x0800u) +#define GPIO_PFC8_PFC812 (0x1000u) +#define GPIO_PFC8_PFC813 (0x2000u) +#define GPIO_PFC8_PFC814 (0x4000u) +#define GPIO_PFC8_PFC815 (0x8000u) + +#define GPIO_PFCE8_PFCE80 (0x0001u) +#define GPIO_PFCE8_PFCE81 (0x0002u) +#define GPIO_PFCE8_PFCE82 (0x0004u) +#define GPIO_PFCE8_PFCE83 (0x0008u) +#define GPIO_PFCE8_PFCE84 (0x0010u) +#define GPIO_PFCE8_PFCE85 (0x0020u) +#define GPIO_PFCE8_PFCE86 (0x0040u) +#define GPIO_PFCE8_PFCE87 (0x0080u) +#define GPIO_PFCE8_PFCE88 (0x0100u) +#define GPIO_PFCE8_PFCE89 (0x0200u) +#define GPIO_PFCE8_PFCE810 (0x0400u) +#define GPIO_PFCE8_PFCE811 (0x0800u) +#define GPIO_PFCE8_PFCE812 (0x1000u) +#define GPIO_PFCE8_PFCE813 (0x2000u) +#define GPIO_PFCE8_PFCE814 (0x4000u) +#define GPIO_PFCE8_PFCE815 (0x8000u) + +#define GPIO_PNOT8_PNOT80 (0x0001u) +#define GPIO_PNOT8_PNOT81 (0x0002u) +#define GPIO_PNOT8_PNOT82 (0x0004u) +#define GPIO_PNOT8_PNOT83 (0x0008u) +#define GPIO_PNOT8_PNOT84 (0x0010u) +#define GPIO_PNOT8_PNOT85 (0x0020u) +#define GPIO_PNOT8_PNOT86 (0x0040u) +#define GPIO_PNOT8_PNOT87 (0x0080u) +#define GPIO_PNOT8_PNOT88 (0x0100u) +#define GPIO_PNOT8_PNOT89 (0x0200u) +#define GPIO_PNOT8_PNOT810 (0x0400u) +#define GPIO_PNOT8_PNOT811 (0x0800u) +#define GPIO_PNOT8_PNOT812 (0x1000u) +#define GPIO_PNOT8_PNOT813 (0x2000u) +#define GPIO_PNOT8_PNOT814 (0x4000u) +#define GPIO_PNOT8_PNOT815 (0x8000u) + +#define GPIO_PMSR8_PMSR80 (0x00000001uL) +#define GPIO_PMSR8_PMSR81 (0x00000002uL) +#define GPIO_PMSR8_PMSR82 (0x00000004uL) +#define GPIO_PMSR8_PMSR83 (0x00000008uL) +#define GPIO_PMSR8_PMSR84 (0x00000010uL) +#define GPIO_PMSR8_PMSR85 (0x00000020uL) +#define GPIO_PMSR8_PMSR86 (0x00000040uL) +#define GPIO_PMSR8_PMSR87 (0x00000080uL) +#define GPIO_PMSR8_PMSR88 (0x00000100uL) +#define GPIO_PMSR8_PMSR89 (0x00000200uL) +#define GPIO_PMSR8_PMSR810 (0x00000400uL) +#define GPIO_PMSR8_PMSR811 (0x00000800uL) +#define GPIO_PMSR8_PMSR812 (0x00001000uL) +#define GPIO_PMSR8_PMSR813 (0x00002000uL) +#define GPIO_PMSR8_PMSR814 (0x00004000uL) +#define GPIO_PMSR8_PMSR815 (0x00008000uL) +#define GPIO_PMSR8_PMSR816 (0x00010000uL) +#define GPIO_PMSR8_PMSR817 (0x00020000uL) +#define GPIO_PMSR8_PMSR818 (0x00040000uL) +#define GPIO_PMSR8_PMSR819 (0x00080000uL) +#define GPIO_PMSR8_PMSR820 (0x00100000uL) +#define GPIO_PMSR8_PMSR821 (0x00200000uL) +#define GPIO_PMSR8_PMSR822 (0x00400000uL) +#define GPIO_PMSR8_PMSR823 (0x00800000uL) +#define GPIO_PMSR8_PMSR824 (0x01000000uL) +#define GPIO_PMSR8_PMSR825 (0x02000000uL) +#define GPIO_PMSR8_PMSR826 (0x04000000uL) +#define GPIO_PMSR8_PMSR827 (0x08000000uL) +#define GPIO_PMSR8_PMSR828 (0x10000000uL) +#define GPIO_PMSR8_PMSR829 (0x20000000uL) +#define GPIO_PMSR8_PMSR830 (0x40000000uL) +#define GPIO_PMSR8_PMSR831 (0x80000000uL) + +#define GPIO_PMCSR8_PMCSR80 (0x00000001uL) +#define GPIO_PMCSR8_PMCSR81 (0x00000002uL) +#define GPIO_PMCSR8_PMCSR82 (0x00000004uL) +#define GPIO_PMCSR8_PMCSR83 (0x00000008uL) +#define GPIO_PMCSR8_PMCSR84 (0x00000010uL) +#define GPIO_PMCSR8_PMCSR85 (0x00000020uL) +#define GPIO_PMCSR8_PMCSR86 (0x00000040uL) +#define GPIO_PMCSR8_PMCSR87 (0x00000080uL) +#define GPIO_PMCSR8_PMCSR88 (0x00000100uL) +#define GPIO_PMCSR8_PMCSR89 (0x00000200uL) +#define GPIO_PMCSR8_PMCSR810 (0x00000400uL) +#define GPIO_PMCSR8_PMCSR811 (0x00000800uL) +#define GPIO_PMCSR8_PMCSR812 (0x00001000uL) +#define GPIO_PMCSR8_PMCSR813 (0x00002000uL) +#define GPIO_PMCSR8_PMCSR814 (0x00004000uL) +#define GPIO_PMCSR8_PMCSR815 (0x00008000uL) +#define GPIO_PMCSR8_PMCSR816 (0x00010000uL) +#define GPIO_PMCSR8_PMCSR817 (0x00020000uL) +#define GPIO_PMCSR8_PMCSR818 (0x00040000uL) +#define GPIO_PMCSR8_PMCSR819 (0x00080000uL) +#define GPIO_PMCSR8_PMCSR820 (0x00100000uL) +#define GPIO_PMCSR8_PMCSR821 (0x00200000uL) +#define GPIO_PMCSR8_PMCSR822 (0x00400000uL) +#define GPIO_PMCSR8_PMCSR823 (0x00800000uL) +#define GPIO_PMCSR8_PMCSR824 (0x01000000uL) +#define GPIO_PMCSR8_PMCSR825 (0x02000000uL) +#define GPIO_PMCSR8_PMCSR826 (0x04000000uL) +#define GPIO_PMCSR8_PMCSR827 (0x08000000uL) +#define GPIO_PMCSR8_PMCSR828 (0x10000000uL) +#define GPIO_PMCSR8_PMCSR829 (0x20000000uL) +#define GPIO_PMCSR8_PMCSR830 (0x40000000uL) +#define GPIO_PMCSR8_PMCSR831 (0x80000000uL) + +#define GPIO_PFCAE8_PFCAE80 (0x0001u) +#define GPIO_PFCAE8_PFCAE81 (0x0002u) +#define GPIO_PFCAE8_PFCAE82 (0x0004u) +#define GPIO_PFCAE8_PFCAE83 (0x0008u) +#define GPIO_PFCAE8_PFCAE84 (0x0010u) +#define GPIO_PFCAE8_PFCAE85 (0x0020u) +#define GPIO_PFCAE8_PFCAE86 (0x0040u) +#define GPIO_PFCAE8_PFCAE87 (0x0080u) +#define GPIO_PFCAE8_PFCAE88 (0x0100u) +#define GPIO_PFCAE8_PFCAE89 (0x0200u) +#define GPIO_PFCAE8_PFCAE810 (0x0400u) +#define GPIO_PFCAE8_PFCAE811 (0x0800u) +#define GPIO_PFCAE8_PFCAE812 (0x1000u) +#define GPIO_PFCAE8_PFCAE813 (0x2000u) +#define GPIO_PFCAE8_PFCAE814 (0x4000u) +#define GPIO_PFCAE8_PFCAE815 (0x8000u) + +#define GPIO_PIBC8_PIBC80 (0x0001u) +#define GPIO_PIBC8_PIBC81 (0x0002u) +#define GPIO_PIBC8_PIBC82 (0x0004u) +#define GPIO_PIBC8_PIBC83 (0x0008u) +#define GPIO_PIBC8_PIBC84 (0x0010u) +#define GPIO_PIBC8_PIBC85 (0x0020u) +#define GPIO_PIBC8_PIBC86 (0x0040u) +#define GPIO_PIBC8_PIBC87 (0x0080u) +#define GPIO_PIBC8_PIBC88 (0x0100u) +#define GPIO_PIBC8_PIBC89 (0x0200u) +#define GPIO_PIBC8_PIBC810 (0x0400u) +#define GPIO_PIBC8_PIBC811 (0x0800u) +#define GPIO_PIBC8_PIBC812 (0x1000u) +#define GPIO_PIBC8_PIBC813 (0x2000u) +#define GPIO_PIBC8_PIBC814 (0x4000u) +#define GPIO_PIBC8_PIBC815 (0x8000u) + +#define GPIO_PBDC8_PBDC80 (0x0001u) +#define GPIO_PBDC8_PBDC81 (0x0002u) +#define GPIO_PBDC8_PBDC82 (0x0004u) +#define GPIO_PBDC8_PBDC83 (0x0008u) +#define GPIO_PBDC8_PBDC84 (0x0010u) +#define GPIO_PBDC8_PBDC85 (0x0020u) +#define GPIO_PBDC8_PBDC86 (0x0040u) +#define GPIO_PBDC8_PBDC87 (0x0080u) +#define GPIO_PBDC8_PBDC88 (0x0100u) +#define GPIO_PBDC8_PBDC89 (0x0200u) +#define GPIO_PBDC8_PBDC810 (0x0400u) +#define GPIO_PBDC8_PBDC811 (0x0800u) +#define GPIO_PBDC8_PBDC812 (0x1000u) +#define GPIO_PBDC8_PBDC813 (0x2000u) +#define GPIO_PBDC8_PBDC814 (0x4000u) +#define GPIO_PBDC8_PBDC815 (0x8000u) + +#define GPIO_PIPC8_PIPC80 (0x0001u) +#define GPIO_PIPC8_PIPC81 (0x0002u) +#define GPIO_PIPC8_PIPC82 (0x0004u) +#define GPIO_PIPC8_PIPC83 (0x0008u) +#define GPIO_PIPC8_PIPC84 (0x0010u) +#define GPIO_PIPC8_PIPC85 (0x0020u) +#define GPIO_PIPC8_PIPC86 (0x0040u) +#define GPIO_PIPC8_PIPC87 (0x0080u) +#define GPIO_PIPC8_PIPC88 (0x0100u) +#define GPIO_PIPC8_PIPC89 (0x0200u) +#define GPIO_PIPC8_PIPC810 (0x0400u) +#define GPIO_PIPC8_PIPC811 (0x0800u) +#define GPIO_PIPC8_PIPC812 (0x1000u) +#define GPIO_PIPC8_PIPC813 (0x2000u) +#define GPIO_PIPC8_PIPC814 (0x4000u) +#define GPIO_PIPC8_PIPC815 (0x8000u) + +/* ---- P9 ---- */ +#define GPIO_P9_P90 (0x0001u) +#define GPIO_P9_P91 (0x0002u) +#define GPIO_P9_P92 (0x0004u) +#define GPIO_P9_P93 (0x0008u) +#define GPIO_P9_P94 (0x0010u) +#define GPIO_P9_P95 (0x0020u) +#define GPIO_P9_P96 (0x0040u) +#define GPIO_P9_P97 (0x0080u) + +#define GPIO_PSR9_PSR90 (0x00000001uL) +#define GPIO_PSR9_PSR91 (0x00000002uL) +#define GPIO_PSR9_PSR92 (0x00000004uL) +#define GPIO_PSR9_PSR93 (0x00000008uL) +#define GPIO_PSR9_PSR94 (0x00000010uL) +#define GPIO_PSR9_PSR95 (0x00000020uL) +#define GPIO_PSR9_PSR96 (0x00000040uL) +#define GPIO_PSR9_PSR97 (0x00000080uL) +#define GPIO_PSR9_PSR916 (0x00010000uL) +#define GPIO_PSR9_PSR917 (0x00020000uL) +#define GPIO_PSR9_PSR918 (0x00040000uL) +#define GPIO_PSR9_PSR919 (0x00080000uL) +#define GPIO_PSR9_PSR920 (0x00100000uL) +#define GPIO_PSR9_PSR921 (0x00200000uL) +#define GPIO_PSR9_PSR922 (0x00400000uL) +#define GPIO_PSR9_PSR923 (0x00800000uL) + +#define GPIO_PPR9_PPR90 (0x0001u) +#define GPIO_PPR9_PPR91 (0x0002u) +#define GPIO_PPR9_PPR92 (0x0004u) +#define GPIO_PPR9_PPR93 (0x0008u) +#define GPIO_PPR9_PPR94 (0x0010u) +#define GPIO_PPR9_PPR95 (0x0020u) +#define GPIO_PPR9_PPR96 (0x0040u) +#define GPIO_PPR9_PPR97 (0x0080u) + +#define GPIO_PM9_PM90 (0x0001u) +#define GPIO_PM9_PM91 (0x0002u) +#define GPIO_PM9_PM92 (0x0004u) +#define GPIO_PM9_PM93 (0x0008u) +#define GPIO_PM9_PM94 (0x0010u) +#define GPIO_PM9_PM95 (0x0020u) +#define GPIO_PM9_PM96 (0x0040u) +#define GPIO_PM9_PM97 (0x0080u) + +#define GPIO_PMC9_PMC90 (0x0001u) +#define GPIO_PMC9_PMC91 (0x0002u) +#define GPIO_PMC9_PMC92 (0x0004u) +#define GPIO_PMC9_PMC93 (0x0008u) +#define GPIO_PMC9_PMC94 (0x0010u) +#define GPIO_PMC9_PMC95 (0x0020u) +#define GPIO_PMC9_PMC96 (0x0040u) +#define GPIO_PMC9_PMC97 (0x0080u) + +#define GPIO_PFC9_PFC90 (0x0001u) +#define GPIO_PFC9_PFC91 (0x0002u) +#define GPIO_PFC9_PFC92 (0x0004u) +#define GPIO_PFC9_PFC93 (0x0008u) +#define GPIO_PFC9_PFC94 (0x0010u) +#define GPIO_PFC9_PFC95 (0x0020u) +#define GPIO_PFC9_PFC96 (0x0040u) +#define GPIO_PFC9_PFC97 (0x0080u) + +#define GPIO_PFCE9_PFCE90 (0x0001u) +#define GPIO_PFCE9_PFCE91 (0x0002u) +#define GPIO_PFCE9_PFCE92 (0x0004u) +#define GPIO_PFCE9_PFCE93 (0x0008u) +#define GPIO_PFCE9_PFCE94 (0x0010u) +#define GPIO_PFCE9_PFCE95 (0x0020u) +#define GPIO_PFCE9_PFCE96 (0x0040u) +#define GPIO_PFCE9_PFCE97 (0x0080u) + +#define GPIO_PNOT9_PNOT90 (0x0001u) +#define GPIO_PNOT9_PNOT91 (0x0002u) +#define GPIO_PNOT9_PNOT92 (0x0004u) +#define GPIO_PNOT9_PNOT93 (0x0008u) +#define GPIO_PNOT9_PNOT94 (0x0010u) +#define GPIO_PNOT9_PNOT95 (0x0020u) +#define GPIO_PNOT9_PNOT96 (0x0040u) +#define GPIO_PNOT9_PNOT97 (0x0080u) + +#define GPIO_PMSR9_PMSR90 (0x00000001uL) +#define GPIO_PMSR9_PMSR91 (0x00000002uL) +#define GPIO_PMSR9_PMSR92 (0x00000004uL) +#define GPIO_PMSR9_PMSR93 (0x00000008uL) +#define GPIO_PMSR9_PMSR94 (0x00000010uL) +#define GPIO_PMSR9_PMSR95 (0x00000020uL) +#define GPIO_PMSR9_PMSR96 (0x00000040uL) +#define GPIO_PMSR9_PMSR97 (0x00000080uL) +#define GPIO_PMSR9_PMSR916 (0x00010000uL) +#define GPIO_PMSR9_PMSR917 (0x00020000uL) +#define GPIO_PMSR9_PMSR918 (0x00040000uL) +#define GPIO_PMSR9_PMSR919 (0x00080000uL) +#define GPIO_PMSR9_PMSR920 (0x00100000uL) +#define GPIO_PMSR9_PMSR921 (0x00200000uL) +#define GPIO_PMSR9_PMSR922 (0x00400000uL) +#define GPIO_PMSR9_PMSR923 (0x00800000uL) + +#define GPIO_PMCSR9_PMCSR90 (0x00000001uL) +#define GPIO_PMCSR9_PMCSR91 (0x00000002uL) +#define GPIO_PMCSR9_PMCSR92 (0x00000004uL) +#define GPIO_PMCSR9_PMCSR93 (0x00000008uL) +#define GPIO_PMCSR9_PMCSR94 (0x00000010uL) +#define GPIO_PMCSR9_PMCSR95 (0x00000020uL) +#define GPIO_PMCSR9_PMCSR96 (0x00000040uL) +#define GPIO_PMCSR9_PMCSR97 (0x00000080uL) +#define GPIO_PMCSR9_PMCSR916 (0x00010000uL) +#define GPIO_PMCSR9_PMCSR917 (0x00020000uL) +#define GPIO_PMCSR9_PMCSR918 (0x00040000uL) +#define GPIO_PMCSR9_PMCSR919 (0x00080000uL) +#define GPIO_PMCSR9_PMCSR920 (0x00100000uL) +#define GPIO_PMCSR9_PMCSR921 (0x00200000uL) +#define GPIO_PMCSR9_PMCSR922 (0x00400000uL) +#define GPIO_PMCSR9_PMCSR923 (0x00800000uL) + +#define GPIO_PFCAE9_PFCAE90 (0x0001u) +#define GPIO_PFCAE9_PFCAE91 (0x0002u) +#define GPIO_PFCAE9_PFCAE92 (0x0004u) +#define GPIO_PFCAE9_PFCAE93 (0x0008u) +#define GPIO_PFCAE9_PFCAE94 (0x0010u) +#define GPIO_PFCAE9_PFCAE95 (0x0020u) +#define GPIO_PFCAE9_PFCAE96 (0x0040u) +#define GPIO_PFCAE9_PFCAE97 (0x0080u) + +#define GPIO_PIBC9_PIBC90 (0x0001u) +#define GPIO_PIBC9_PIBC91 (0x0002u) +#define GPIO_PIBC9_PIBC92 (0x0004u) +#define GPIO_PIBC9_PIBC93 (0x0008u) +#define GPIO_PIBC9_PIBC94 (0x0010u) +#define GPIO_PIBC9_PIBC95 (0x0020u) +#define GPIO_PIBC9_PIBC96 (0x0040u) +#define GPIO_PIBC9_PIBC97 (0x0080u) + +#define GPIO_PBDC9_PBDC90 (0x0001u) +#define GPIO_PBDC9_PBDC91 (0x0002u) +#define GPIO_PBDC9_PBDC92 (0x0004u) +#define GPIO_PBDC9_PBDC93 (0x0008u) +#define GPIO_PBDC9_PBDC94 (0x0010u) +#define GPIO_PBDC9_PBDC95 (0x0020u) +#define GPIO_PBDC9_PBDC96 (0x0040u) +#define GPIO_PBDC9_PBDC97 (0x0080u) + +#define GPIO_PIPC9_PIPC90 (0x0001u) +#define GPIO_PIPC9_PIPC91 (0x0002u) +#define GPIO_PIPC9_PIPC92 (0x0004u) +#define GPIO_PIPC9_PIPC93 (0x0008u) +#define GPIO_PIPC9_PIPC94 (0x0010u) +#define GPIO_PIPC9_PIPC95 (0x0020u) +#define GPIO_PIPC9_PIPC96 (0x0040u) +#define GPIO_PIPC9_PIPC97 (0x0080u) + +/* ---- P10 ---- */ +#define GPIO_P10_P100 (0x0001u) +#define GPIO_P10_P101 (0x0002u) +#define GPIO_P10_P102 (0x0004u) +#define GPIO_P10_P103 (0x0008u) +#define GPIO_P10_P104 (0x0010u) +#define GPIO_P10_P105 (0x0020u) +#define GPIO_P10_P106 (0x0040u) +#define GPIO_P10_P107 (0x0080u) +#define GPIO_P10_P108 (0x0100u) +#define GPIO_P10_P109 (0x0200u) +#define GPIO_P10_P1010 (0x0400u) +#define GPIO_P10_P1011 (0x0800u) +#define GPIO_P10_P1012 (0x1000u) +#define GPIO_P10_P1013 (0x2000u) +#define GPIO_P10_P1014 (0x4000u) +#define GPIO_P10_P1015 (0x8000u) + +#define GPIO_PSR10_PSR100 (0x00000001uL) +#define GPIO_PSR10_PSR101 (0x00000002uL) +#define GPIO_PSR10_PSR102 (0x00000004uL) +#define GPIO_PSR10_PSR103 (0x00000008uL) +#define GPIO_PSR10_PSR104 (0x00000010uL) +#define GPIO_PSR10_PSR105 (0x00000020uL) +#define GPIO_PSR10_PSR106 (0x00000040uL) +#define GPIO_PSR10_PSR107 (0x00000080uL) +#define GPIO_PSR10_PSR108 (0x00000100uL) +#define GPIO_PSR10_PSR109 (0x00000200uL) +#define GPIO_PSR10_PSR1010 (0x00000400uL) +#define GPIO_PSR10_PSR1011 (0x00000800uL) +#define GPIO_PSR10_PSR1012 (0x00001000uL) +#define GPIO_PSR10_PSR1013 (0x00002000uL) +#define GPIO_PSR10_PSR1014 (0x00004000uL) +#define GPIO_PSR10_PSR1015 (0x00008000uL) +#define GPIO_PSR10_PSR1016 (0x00010000uL) +#define GPIO_PSR10_PSR1017 (0x00020000uL) +#define GPIO_PSR10_PSR1018 (0x00040000uL) +#define GPIO_PSR10_PSR1019 (0x00080000uL) +#define GPIO_PSR10_PSR1020 (0x00100000uL) +#define GPIO_PSR10_PSR1021 (0x00200000uL) +#define GPIO_PSR10_PSR1022 (0x00400000uL) +#define GPIO_PSR10_PSR1023 (0x00800000uL) +#define GPIO_PSR10_PSR1024 (0x01000000uL) +#define GPIO_PSR10_PSR1025 (0x02000000uL) +#define GPIO_PSR10_PSR1026 (0x04000000uL) +#define GPIO_PSR10_PSR1027 (0x08000000uL) +#define GPIO_PSR10_PSR1028 (0x10000000uL) +#define GPIO_PSR10_PSR1029 (0x20000000uL) +#define GPIO_PSR10_PSR1030 (0x40000000uL) +#define GPIO_PSR10_PSR1031 (0x80000000uL) + +#define GPIO_PPR10_PPR100 (0x0001u) +#define GPIO_PPR10_PPR101 (0x0002u) +#define GPIO_PPR10_PPR102 (0x0004u) +#define GPIO_PPR10_PPR103 (0x0008u) +#define GPIO_PPR10_PPR104 (0x0010u) +#define GPIO_PPR10_PPR105 (0x0020u) +#define GPIO_PPR10_PPR106 (0x0040u) +#define GPIO_PPR10_PPR107 (0x0080u) +#define GPIO_PPR10_PPR108 (0x0100u) +#define GPIO_PPR10_PPR109 (0x0200u) +#define GPIO_PPR10_PPR1010 (0x0400u) +#define GPIO_PPR10_PPR1011 (0x0800u) +#define GPIO_PPR10_PPR1012 (0x1000u) +#define GPIO_PPR10_PPR1013 (0x2000u) +#define GPIO_PPR10_PPR1014 (0x4000u) +#define GPIO_PPR10_PPR1015 (0x8000u) + +#define GPIO_PM10_PM100 (0x0001u) +#define GPIO_PM10_PM101 (0x0002u) +#define GPIO_PM10_PM102 (0x0004u) +#define GPIO_PM10_PM103 (0x0008u) +#define GPIO_PM10_PM104 (0x0010u) +#define GPIO_PM10_PM105 (0x0020u) +#define GPIO_PM10_PM106 (0x0040u) +#define GPIO_PM10_PM107 (0x0080u) +#define GPIO_PM10_PM108 (0x0100u) +#define GPIO_PM10_PM109 (0x0200u) +#define GPIO_PM10_PM1010 (0x0400u) +#define GPIO_PM10_PM1011 (0x0800u) +#define GPIO_PM10_PM1012 (0x1000u) +#define GPIO_PM10_PM1013 (0x2000u) +#define GPIO_PM10_PM1014 (0x4000u) +#define GPIO_PM10_PM1015 (0x8000u) + +#define GPIO_PMC10_PMC100 (0x0001u) +#define GPIO_PMC10_PMC101 (0x0002u) +#define GPIO_PMC10_PMC102 (0x0004u) +#define GPIO_PMC10_PMC103 (0x0008u) +#define GPIO_PMC10_PMC104 (0x0010u) +#define GPIO_PMC10_PMC105 (0x0020u) +#define GPIO_PMC10_PMC106 (0x0040u) +#define GPIO_PMC10_PMC107 (0x0080u) +#define GPIO_PMC10_PMC108 (0x0100u) +#define GPIO_PMC10_PMC109 (0x0200u) +#define GPIO_PMC10_PMC1010 (0x0400u) +#define GPIO_PMC10_PMC1011 (0x0800u) +#define GPIO_PMC10_PMC1012 (0x1000u) +#define GPIO_PMC10_PMC1013 (0x2000u) +#define GPIO_PMC10_PMC1014 (0x4000u) +#define GPIO_PMC10_PMC1015 (0x8000u) + +#define GPIO_PFC10_PFC100 (0x0001u) +#define GPIO_PFC10_PFC101 (0x0002u) +#define GPIO_PFC10_PFC102 (0x0004u) +#define GPIO_PFC10_PFC103 (0x0008u) +#define GPIO_PFC10_PFC104 (0x0010u) +#define GPIO_PFC10_PFC105 (0x0020u) +#define GPIO_PFC10_PFC106 (0x0040u) +#define GPIO_PFC10_PFC107 (0x0080u) +#define GPIO_PFC10_PFC108 (0x0100u) +#define GPIO_PFC10_PFC109 (0x0200u) +#define GPIO_PFC10_PFC1010 (0x0400u) +#define GPIO_PFC10_PFC1011 (0x0800u) +#define GPIO_PFC10_PFC1012 (0x1000u) +#define GPIO_PFC10_PFC1013 (0x2000u) +#define GPIO_PFC10_PFC1014 (0x4000u) +#define GPIO_PFC10_PFC1015 (0x8000u) + +#define GPIO_PFCE10_PFCE100 (0x0001u) +#define GPIO_PFCE10_PFCE101 (0x0002u) +#define GPIO_PFCE10_PFCE102 (0x0004u) +#define GPIO_PFCE10_PFCE103 (0x0008u) +#define GPIO_PFCE10_PFCE104 (0x0010u) +#define GPIO_PFCE10_PFCE105 (0x0020u) +#define GPIO_PFCE10_PFCE106 (0x0040u) +#define GPIO_PFCE10_PFCE107 (0x0080u) +#define GPIO_PFCE10_PFCE108 (0x0100u) +#define GPIO_PFCE10_PFCE109 (0x0200u) +#define GPIO_PFCE10_PFCE1010 (0x0400u) +#define GPIO_PFCE10_PFCE1011 (0x0800u) +#define GPIO_PFCE10_PFCE1012 (0x1000u) +#define GPIO_PFCE10_PFCE1013 (0x2000u) +#define GPIO_PFCE10_PFCE1014 (0x4000u) +#define GPIO_PFCE10_PFCE1015 (0x8000u) + +#define GPIO_PNOT10_PNOT100 (0x0001u) +#define GPIO_PNOT10_PNOT101 (0x0002u) +#define GPIO_PNOT10_PNOT102 (0x0004u) +#define GPIO_PNOT10_PNOT103 (0x0008u) +#define GPIO_PNOT10_PNOT104 (0x0010u) +#define GPIO_PNOT10_PNOT105 (0x0020u) +#define GPIO_PNOT10_PNOT106 (0x0040u) +#define GPIO_PNOT10_PNOT107 (0x0080u) +#define GPIO_PNOT10_PNOT108 (0x0100u) +#define GPIO_PNOT10_PNOT109 (0x0200u) +#define GPIO_PNOT10_PNOT1010 (0x0400u) +#define GPIO_PNOT10_PNOT1011 (0x0800u) +#define GPIO_PNOT10_PNOT1012 (0x1000u) +#define GPIO_PNOT10_PNOT1013 (0x2000u) +#define GPIO_PNOT10_PNOT1014 (0x4000u) +#define GPIO_PNOT10_PNOT1015 (0x8000u) + +#define GPIO_PMSR10_PMSR100 (0x00000001uL) +#define GPIO_PMSR10_PMSR101 (0x00000002uL) +#define GPIO_PMSR10_PMSR102 (0x00000004uL) +#define GPIO_PMSR10_PMSR103 (0x00000008uL) +#define GPIO_PMSR10_PMSR104 (0x00000010uL) +#define GPIO_PMSR10_PMSR105 (0x00000020uL) +#define GPIO_PMSR10_PMSR106 (0x00000040uL) +#define GPIO_PMSR10_PMSR107 (0x00000080uL) +#define GPIO_PMSR10_PMSR108 (0x00000100uL) +#define GPIO_PMSR10_PMSR109 (0x00000200uL) +#define GPIO_PMSR10_PMSR1010 (0x00000400uL) +#define GPIO_PMSR10_PMSR1011 (0x00000800uL) +#define GPIO_PMSR10_PMSR1012 (0x00001000uL) +#define GPIO_PMSR10_PMSR1013 (0x00002000uL) +#define GPIO_PMSR10_PMSR1014 (0x00004000uL) +#define GPIO_PMSR10_PMSR1015 (0x00008000uL) +#define GPIO_PMSR10_PMSR1016 (0x00010000uL) +#define GPIO_PMSR10_PMSR1017 (0x00020000uL) +#define GPIO_PMSR10_PMSR1018 (0x00040000uL) +#define GPIO_PMSR10_PMSR1019 (0x00080000uL) +#define GPIO_PMSR10_PMSR1020 (0x00100000uL) +#define GPIO_PMSR10_PMSR1021 (0x00200000uL) +#define GPIO_PMSR10_PMSR1022 (0x00400000uL) +#define GPIO_PMSR10_PMSR1023 (0x00800000uL) +#define GPIO_PMSR10_PMSR1024 (0x01000000uL) +#define GPIO_PMSR10_PMSR1025 (0x02000000uL) +#define GPIO_PMSR10_PMSR1026 (0x04000000uL) +#define GPIO_PMSR10_PMSR1027 (0x08000000uL) +#define GPIO_PMSR10_PMSR1028 (0x10000000uL) +#define GPIO_PMSR10_PMSR1029 (0x20000000uL) +#define GPIO_PMSR10_PMSR1030 (0x40000000uL) +#define GPIO_PMSR10_PMSR1031 (0x80000000uL) + +#define GPIO_PMCSR10_PMCSR100 (0x00000001uL) +#define GPIO_PMCSR10_PMCSR101 (0x00000002uL) +#define GPIO_PMCSR10_PMCSR102 (0x00000004uL) +#define GPIO_PMCSR10_PMCSR103 (0x00000008uL) +#define GPIO_PMCSR10_PMCSR104 (0x00000010uL) +#define GPIO_PMCSR10_PMCSR105 (0x00000020uL) +#define GPIO_PMCSR10_PMCSR106 (0x00000040uL) +#define GPIO_PMCSR10_PMCSR107 (0x00000080uL) +#define GPIO_PMCSR10_PMCSR108 (0x00000100uL) +#define GPIO_PMCSR10_PMCSR109 (0x00000200uL) +#define GPIO_PMCSR10_PMCSR1010 (0x00000400uL) +#define GPIO_PMCSR10_PMCSR1011 (0x00000800uL) +#define GPIO_PMCSR10_PMCSR1012 (0x00001000uL) +#define GPIO_PMCSR10_PMCSR1013 (0x00002000uL) +#define GPIO_PMCSR10_PMCSR1014 (0x00004000uL) +#define GPIO_PMCSR10_PMCSR1015 (0x00008000uL) +#define GPIO_PMCSR10_PMCSR1016 (0x00010000uL) +#define GPIO_PMCSR10_PMCSR1017 (0x00020000uL) +#define GPIO_PMCSR10_PMCSR1018 (0x00040000uL) +#define GPIO_PMCSR10_PMCSR1019 (0x00080000uL) +#define GPIO_PMCSR10_PMCSR1020 (0x00100000uL) +#define GPIO_PMCSR10_PMCSR1021 (0x00200000uL) +#define GPIO_PMCSR10_PMCSR1022 (0x00400000uL) +#define GPIO_PMCSR10_PMCSR1023 (0x00800000uL) +#define GPIO_PMCSR10_PMCSR1024 (0x01000000uL) +#define GPIO_PMCSR10_PMCSR1025 (0x02000000uL) +#define GPIO_PMCSR10_PMCSR1026 (0x04000000uL) +#define GPIO_PMCSR10_PMCSR1027 (0x08000000uL) +#define GPIO_PMCSR10_PMCSR1028 (0x10000000uL) +#define GPIO_PMCSR10_PMCSR1029 (0x20000000uL) +#define GPIO_PMCSR10_PMCSR1030 (0x40000000uL) +#define GPIO_PMCSR10_PMCSR1031 (0x80000000uL) + +#define GPIO_PFCAE10_PFCAE100 (0x0001u) +#define GPIO_PFCAE10_PFCAE101 (0x0002u) +#define GPIO_PFCAE10_PFCAE102 (0x0004u) +#define GPIO_PFCAE10_PFCAE103 (0x0008u) +#define GPIO_PFCAE10_PFCAE104 (0x0010u) +#define GPIO_PFCAE10_PFCAE105 (0x0020u) +#define GPIO_PFCAE10_PFCAE106 (0x0040u) +#define GPIO_PFCAE10_PFCAE107 (0x0080u) +#define GPIO_PFCAE10_PFCAE108 (0x0100u) +#define GPIO_PFCAE10_PFCAE109 (0x0200u) +#define GPIO_PFCAE10_PFCAE1010 (0x0400u) +#define GPIO_PFCAE10_PFCAE1011 (0x0800u) +#define GPIO_PFCAE10_PFCAE1012 (0x1000u) +#define GPIO_PFCAE10_PFCAE1013 (0x2000u) +#define GPIO_PFCAE10_PFCAE1014 (0x4000u) +#define GPIO_PFCAE10_PFCAE1015 (0x8000u) + +#define GPIO_PIBC10_PIBC100 (0x0001u) +#define GPIO_PIBC10_PIBC101 (0x0002u) +#define GPIO_PIBC10_PIBC102 (0x0004u) +#define GPIO_PIBC10_PIBC103 (0x0008u) +#define GPIO_PIBC10_PIBC104 (0x0010u) +#define GPIO_PIBC10_PIBC105 (0x0020u) +#define GPIO_PIBC10_PIBC106 (0x0040u) +#define GPIO_PIBC10_PIBC107 (0x0080u) +#define GPIO_PIBC10_PIBC108 (0x0100u) +#define GPIO_PIBC10_PIBC109 (0x0200u) +#define GPIO_PIBC10_PIBC1010 (0x0400u) +#define GPIO_PIBC10_PIBC1011 (0x0800u) +#define GPIO_PIBC10_PIBC1012 (0x1000u) +#define GPIO_PIBC10_PIBC1013 (0x2000u) +#define GPIO_PIBC10_PIBC1014 (0x4000u) +#define GPIO_PIBC10_PIBC1015 (0x8000u) + +#define GPIO_PBDC10_PBDC100 (0x0001u) +#define GPIO_PBDC10_PBDC101 (0x0002u) +#define GPIO_PBDC10_PBDC102 (0x0004u) +#define GPIO_PBDC10_PBDC103 (0x0008u) +#define GPIO_PBDC10_PBDC104 (0x0010u) +#define GPIO_PBDC10_PBDC105 (0x0020u) +#define GPIO_PBDC10_PBDC106 (0x0040u) +#define GPIO_PBDC10_PBDC107 (0x0080u) +#define GPIO_PBDC10_PBDC108 (0x0100u) +#define GPIO_PBDC10_PBDC109 (0x0200u) +#define GPIO_PBDC10_PBDC1010 (0x0400u) +#define GPIO_PBDC10_PBDC1011 (0x0800u) +#define GPIO_PBDC10_PBDC1012 (0x1000u) +#define GPIO_PBDC10_PBDC1013 (0x2000u) +#define GPIO_PBDC10_PBDC1014 (0x4000u) +#define GPIO_PBDC10_PBDC1015 (0x8000u) + +#define GPIO_PIPC10_PIPC100 (0x0001u) +#define GPIO_PIPC10_PIPC101 (0x0002u) +#define GPIO_PIPC10_PIPC102 (0x0004u) +#define GPIO_PIPC10_PIPC103 (0x0008u) +#define GPIO_PIPC10_PIPC104 (0x0010u) +#define GPIO_PIPC10_PIPC105 (0x0020u) +#define GPIO_PIPC10_PIPC106 (0x0040u) +#define GPIO_PIPC10_PIPC107 (0x0080u) +#define GPIO_PIPC10_PIPC108 (0x0100u) +#define GPIO_PIPC10_PIPC109 (0x0200u) +#define GPIO_PIPC10_PIPC1010 (0x0400u) +#define GPIO_PIPC10_PIPC1011 (0x0800u) +#define GPIO_PIPC10_PIPC1012 (0x1000u) +#define GPIO_PIPC10_PIPC1013 (0x2000u) +#define GPIO_PIPC10_PIPC1014 (0x4000u) +#define GPIO_PIPC10_PIPC1015 (0x8000u) + +/* ---- P11 ---- */ +#define GPIO_P11_P110 (0x0001u) +#define GPIO_P11_P111 (0x0002u) +#define GPIO_P11_P112 (0x0004u) +#define GPIO_P11_P113 (0x0008u) +#define GPIO_P11_P114 (0x0010u) +#define GPIO_P11_P115 (0x0020u) +#define GPIO_P11_P116 (0x0040u) +#define GPIO_P11_P117 (0x0080u) +#define GPIO_P11_P118 (0x0100u) +#define GPIO_P11_P119 (0x0200u) +#define GPIO_P11_P1110 (0x0400u) +#define GPIO_P11_P1111 (0x0800u) +#define GPIO_P11_P1112 (0x1000u) +#define GPIO_P11_P1113 (0x2000u) +#define GPIO_P11_P1114 (0x4000u) +#define GPIO_P11_P1115 (0x8000u) + +#define GPIO_PSR11_PSR110 (0x00000001uL) +#define GPIO_PSR11_PSR111 (0x00000002uL) +#define GPIO_PSR11_PSR112 (0x00000004uL) +#define GPIO_PSR11_PSR113 (0x00000008uL) +#define GPIO_PSR11_PSR114 (0x00000010uL) +#define GPIO_PSR11_PSR115 (0x00000020uL) +#define GPIO_PSR11_PSR116 (0x00000040uL) +#define GPIO_PSR11_PSR117 (0x00000080uL) +#define GPIO_PSR11_PSR118 (0x00000100uL) +#define GPIO_PSR11_PSR119 (0x00000200uL) +#define GPIO_PSR11_PSR1110 (0x00000400uL) +#define GPIO_PSR11_PSR1111 (0x00000800uL) +#define GPIO_PSR11_PSR1112 (0x00001000uL) +#define GPIO_PSR11_PSR1113 (0x00002000uL) +#define GPIO_PSR11_PSR1114 (0x00004000uL) +#define GPIO_PSR11_PSR1115 (0x00008000uL) +#define GPIO_PSR11_PSR1116 (0x00010000uL) +#define GPIO_PSR11_PSR1117 (0x00020000uL) +#define GPIO_PSR11_PSR1118 (0x00040000uL) +#define GPIO_PSR11_PSR1119 (0x00080000uL) +#define GPIO_PSR11_PSR1120 (0x00100000uL) +#define GPIO_PSR11_PSR1121 (0x00200000uL) +#define GPIO_PSR11_PSR1122 (0x00400000uL) +#define GPIO_PSR11_PSR1123 (0x00800000uL) +#define GPIO_PSR11_PSR1124 (0x01000000uL) +#define GPIO_PSR11_PSR1125 (0x02000000uL) +#define GPIO_PSR11_PSR1126 (0x04000000uL) +#define GPIO_PSR11_PSR1127 (0x08000000uL) +#define GPIO_PSR11_PSR1128 (0x10000000uL) +#define GPIO_PSR11_PSR1129 (0x20000000uL) +#define GPIO_PSR11_PSR1130 (0x40000000uL) +#define GPIO_PSR11_PSR1131 (0x80000000uL) + +#define GPIO_PPR11_PPR110 (0x0001u) +#define GPIO_PPR11_PPR111 (0x0002u) +#define GPIO_PPR11_PPR112 (0x0004u) +#define GPIO_PPR11_PPR113 (0x0008u) +#define GPIO_PPR11_PPR114 (0x0010u) +#define GPIO_PPR11_PPR115 (0x0020u) +#define GPIO_PPR11_PPR116 (0x0040u) +#define GPIO_PPR11_PPR117 (0x0080u) +#define GPIO_PPR11_PPR118 (0x0100u) +#define GPIO_PPR11_PPR119 (0x0200u) +#define GPIO_PPR11_PPR1110 (0x0400u) +#define GPIO_PPR11_PPR1111 (0x0800u) +#define GPIO_PPR11_PPR1112 (0x1000u) +#define GPIO_PPR11_PPR1113 (0x2000u) +#define GPIO_PPR11_PPR1114 (0x4000u) +#define GPIO_PPR11_PPR1115 (0x8000u) + +#define GPIO_PM11_PM110 (0x0001u) +#define GPIO_PM11_PM111 (0x0002u) +#define GPIO_PM11_PM112 (0x0004u) +#define GPIO_PM11_PM113 (0x0008u) +#define GPIO_PM11_PM114 (0x0010u) +#define GPIO_PM11_PM115 (0x0020u) +#define GPIO_PM11_PM116 (0x0040u) +#define GPIO_PM11_PM117 (0x0080u) +#define GPIO_PM11_PM118 (0x0100u) +#define GPIO_PM11_PM119 (0x0200u) +#define GPIO_PM11_PM1110 (0x0400u) +#define GPIO_PM11_PM1111 (0x0800u) +#define GPIO_PM11_PM1112 (0x1000u) +#define GPIO_PM11_PM1113 (0x2000u) +#define GPIO_PM11_PM1114 (0x4000u) +#define GPIO_PM11_PM1115 (0x8000u) + +#define GPIO_PMC11_PMC110 (0x0001u) +#define GPIO_PMC11_PMC111 (0x0002u) +#define GPIO_PMC11_PMC112 (0x0004u) +#define GPIO_PMC11_PMC113 (0x0008u) +#define GPIO_PMC11_PMC114 (0x0010u) +#define GPIO_PMC11_PMC115 (0x0020u) +#define GPIO_PMC11_PMC116 (0x0040u) +#define GPIO_PMC11_PMC117 (0x0080u) +#define GPIO_PMC11_PMC118 (0x0100u) +#define GPIO_PMC11_PMC119 (0x0200u) +#define GPIO_PMC11_PMC1110 (0x0400u) +#define GPIO_PMC11_PMC1111 (0x0800u) +#define GPIO_PMC11_PMC1112 (0x1000u) +#define GPIO_PMC11_PMC1113 (0x2000u) +#define GPIO_PMC11_PMC1114 (0x4000u) +#define GPIO_PMC11_PMC1115 (0x8000u) + +#define GPIO_PFC11_PFC110 (0x0001u) +#define GPIO_PFC11_PFC111 (0x0002u) +#define GPIO_PFC11_PFC112 (0x0004u) +#define GPIO_PFC11_PFC113 (0x0008u) +#define GPIO_PFC11_PFC114 (0x0010u) +#define GPIO_PFC11_PFC115 (0x0020u) +#define GPIO_PFC11_PFC116 (0x0040u) +#define GPIO_PFC11_PFC117 (0x0080u) +#define GPIO_PFC11_PFC118 (0x0100u) +#define GPIO_PFC11_PFC119 (0x0200u) +#define GPIO_PFC11_PFC1110 (0x0400u) +#define GPIO_PFC11_PFC1111 (0x0800u) +#define GPIO_PFC11_PFC1112 (0x1000u) +#define GPIO_PFC11_PFC1113 (0x2000u) +#define GPIO_PFC11_PFC1114 (0x4000u) +#define GPIO_PFC11_PFC1115 (0x8000u) + +#define GPIO_PFCE11_PFCE110 (0x0001u) +#define GPIO_PFCE11_PFCE111 (0x0002u) +#define GPIO_PFCE11_PFCE112 (0x0004u) +#define GPIO_PFCE11_PFCE113 (0x0008u) +#define GPIO_PFCE11_PFCE114 (0x0010u) +#define GPIO_PFCE11_PFCE115 (0x0020u) +#define GPIO_PFCE11_PFCE116 (0x0040u) +#define GPIO_PFCE11_PFCE117 (0x0080u) +#define GPIO_PFCE11_PFCE118 (0x0100u) +#define GPIO_PFCE11_PFCE119 (0x0200u) +#define GPIO_PFCE11_PFCE1110 (0x0400u) +#define GPIO_PFCE11_PFCE1111 (0x0800u) +#define GPIO_PFCE11_PFCE1112 (0x1000u) +#define GPIO_PFCE11_PFCE1113 (0x2000u) +#define GPIO_PFCE11_PFCE1114 (0x4000u) +#define GPIO_PFCE11_PFCE1115 (0x8000u) + +#define GPIO_PNOT11_PNOT110 (0x0001u) +#define GPIO_PNOT11_PNOT111 (0x0002u) +#define GPIO_PNOT11_PNOT112 (0x0004u) +#define GPIO_PNOT11_PNOT113 (0x0008u) +#define GPIO_PNOT11_PNOT114 (0x0010u) +#define GPIO_PNOT11_PNOT115 (0x0020u) +#define GPIO_PNOT11_PNOT116 (0x0040u) +#define GPIO_PNOT11_PNOT117 (0x0080u) +#define GPIO_PNOT11_PNOT118 (0x0100u) +#define GPIO_PNOT11_PNOT119 (0x0200u) +#define GPIO_PNOT11_PNOT1110 (0x0400u) +#define GPIO_PNOT11_PNOT1111 (0x0800u) +#define GPIO_PNOT11_PNOT1112 (0x1000u) +#define GPIO_PNOT11_PNOT1113 (0x2000u) +#define GPIO_PNOT11_PNOT1114 (0x4000u) +#define GPIO_PNOT11_PNOT1115 (0x8000u) + +#define GPIO_PMSR11_PMSR110 (0x00000001uL) +#define GPIO_PMSR11_PMSR111 (0x00000002uL) +#define GPIO_PMSR11_PMSR112 (0x00000004uL) +#define GPIO_PMSR11_PMSR113 (0x00000008uL) +#define GPIO_PMSR11_PMSR114 (0x00000010uL) +#define GPIO_PMSR11_PMSR115 (0x00000020uL) +#define GPIO_PMSR11_PMSR116 (0x00000040uL) +#define GPIO_PMSR11_PMSR117 (0x00000080uL) +#define GPIO_PMSR11_PMSR118 (0x00000100uL) +#define GPIO_PMSR11_PMSR119 (0x00000200uL) +#define GPIO_PMSR11_PMSR1110 (0x00000400uL) +#define GPIO_PMSR11_PMSR1111 (0x00000800uL) +#define GPIO_PMSR11_PMSR1112 (0x00001000uL) +#define GPIO_PMSR11_PMSR1113 (0x00002000uL) +#define GPIO_PMSR11_PMSR1114 (0x00004000uL) +#define GPIO_PMSR11_PMSR1115 (0x00008000uL) +#define GPIO_PMSR11_PMSR1116 (0x00010000uL) +#define GPIO_PMSR11_PMSR1117 (0x00020000uL) +#define GPIO_PMSR11_PMSR1118 (0x00040000uL) +#define GPIO_PMSR11_PMSR1119 (0x00080000uL) +#define GPIO_PMSR11_PMSR1120 (0x00100000uL) +#define GPIO_PMSR11_PMSR1121 (0x00200000uL) +#define GPIO_PMSR11_PMSR1122 (0x00400000uL) +#define GPIO_PMSR11_PMSR1123 (0x00800000uL) +#define GPIO_PMSR11_PMSR1124 (0x01000000uL) +#define GPIO_PMSR11_PMSR1125 (0x02000000uL) +#define GPIO_PMSR11_PMSR1126 (0x04000000uL) +#define GPIO_PMSR11_PMSR1127 (0x08000000uL) +#define GPIO_PMSR11_PMSR1128 (0x10000000uL) +#define GPIO_PMSR11_PMSR1129 (0x20000000uL) +#define GPIO_PMSR11_PMSR1130 (0x40000000uL) +#define GPIO_PMSR11_PMSR1131 (0x80000000uL) + +#define GPIO_PMCSR11_PMCSR110 (0x00000001uL) +#define GPIO_PMCSR11_PMCSR111 (0x00000002uL) +#define GPIO_PMCSR11_PMCSR112 (0x00000004uL) +#define GPIO_PMCSR11_PMCSR113 (0x00000008uL) +#define GPIO_PMCSR11_PMCSR114 (0x00000010uL) +#define GPIO_PMCSR11_PMCSR115 (0x00000020uL) +#define GPIO_PMCSR11_PMCSR116 (0x00000040uL) +#define GPIO_PMCSR11_PMCSR117 (0x00000080uL) +#define GPIO_PMCSR11_PMCSR118 (0x00000100uL) +#define GPIO_PMCSR11_PMCSR119 (0x00000200uL) +#define GPIO_PMCSR11_PMCSR1110 (0x00000400uL) +#define GPIO_PMCSR11_PMCSR1111 (0x00000800uL) +#define GPIO_PMCSR11_PMCSR1112 (0x00001000uL) +#define GPIO_PMCSR11_PMCSR1113 (0x00002000uL) +#define GPIO_PMCSR11_PMCSR1114 (0x00004000uL) +#define GPIO_PMCSR11_PMCSR1115 (0x00008000uL) +#define GPIO_PMCSR11_PMCSR1116 (0x00010000uL) +#define GPIO_PMCSR11_PMCSR1117 (0x00020000uL) +#define GPIO_PMCSR11_PMCSR1118 (0x00040000uL) +#define GPIO_PMCSR11_PMCSR1119 (0x00080000uL) +#define GPIO_PMCSR11_PMCSR1120 (0x00100000uL) +#define GPIO_PMCSR11_PMCSR1121 (0x00200000uL) +#define GPIO_PMCSR11_PMCSR1122 (0x00400000uL) +#define GPIO_PMCSR11_PMCSR1123 (0x00800000uL) +#define GPIO_PMCSR11_PMCSR1124 (0x01000000uL) +#define GPIO_PMCSR11_PMCSR1125 (0x02000000uL) +#define GPIO_PMCSR11_PMCSR1126 (0x04000000uL) +#define GPIO_PMCSR11_PMCSR1127 (0x08000000uL) +#define GPIO_PMCSR11_PMCSR1128 (0x10000000uL) +#define GPIO_PMCSR11_PMCSR1129 (0x20000000uL) +#define GPIO_PMCSR11_PMCSR1130 (0x40000000uL) +#define GPIO_PMCSR11_PMCSR1131 (0x80000000uL) + +#define GPIO_PFCAE11_PFCAE110 (0x0001u) +#define GPIO_PFCAE11_PFCAE111 (0x0002u) +#define GPIO_PFCAE11_PFCAE112 (0x0004u) +#define GPIO_PFCAE11_PFCAE113 (0x0008u) +#define GPIO_PFCAE11_PFCAE114 (0x0010u) +#define GPIO_PFCAE11_PFCAE115 (0x0020u) +#define GPIO_PFCAE11_PFCAE116 (0x0040u) +#define GPIO_PFCAE11_PFCAE117 (0x0080u) +#define GPIO_PFCAE11_PFCAE118 (0x0100u) +#define GPIO_PFCAE11_PFCAE119 (0x0200u) +#define GPIO_PFCAE11_PFCAE1110 (0x0400u) +#define GPIO_PFCAE11_PFCAE1111 (0x0800u) +#define GPIO_PFCAE11_PFCAE1112 (0x1000u) +#define GPIO_PFCAE11_PFCAE1113 (0x2000u) +#define GPIO_PFCAE11_PFCAE1114 (0x4000u) +#define GPIO_PFCAE11_PFCAE1115 (0x8000u) + +#define GPIO_PIBC11_PIBC110 (0x0001u) +#define GPIO_PIBC11_PIBC111 (0x0002u) +#define GPIO_PIBC11_PIBC112 (0x0004u) +#define GPIO_PIBC11_PIBC113 (0x0008u) +#define GPIO_PIBC11_PIBC114 (0x0010u) +#define GPIO_PIBC11_PIBC115 (0x0020u) +#define GPIO_PIBC11_PIBC116 (0x0040u) +#define GPIO_PIBC11_PIBC117 (0x0080u) +#define GPIO_PIBC11_PIBC118 (0x0100u) +#define GPIO_PIBC11_PIBC119 (0x0200u) +#define GPIO_PIBC11_PIBC1110 (0x0400u) +#define GPIO_PIBC11_PIBC1111 (0x0800u) +#define GPIO_PIBC11_PIBC1112 (0x1000u) +#define GPIO_PIBC11_PIBC1113 (0x2000u) +#define GPIO_PIBC11_PIBC1114 (0x4000u) +#define GPIO_PIBC11_PIBC1115 (0x8000u) + +#define GPIO_PBDC11_PBDC110 (0x0001u) +#define GPIO_PBDC11_PBDC111 (0x0002u) +#define GPIO_PBDC11_PBDC112 (0x0004u) +#define GPIO_PBDC11_PBDC113 (0x0008u) +#define GPIO_PBDC11_PBDC114 (0x0010u) +#define GPIO_PBDC11_PBDC115 (0x0020u) +#define GPIO_PBDC11_PBDC116 (0x0040u) +#define GPIO_PBDC11_PBDC117 (0x0080u) +#define GPIO_PBDC11_PBDC118 (0x0100u) +#define GPIO_PBDC11_PBDC119 (0x0200u) +#define GPIO_PBDC11_PBDC1110 (0x0400u) +#define GPIO_PBDC11_PBDC1111 (0x0800u) +#define GPIO_PBDC11_PBDC1112 (0x1000u) +#define GPIO_PBDC11_PBDC1113 (0x2000u) +#define GPIO_PBDC11_PBDC1114 (0x4000u) +#define GPIO_PBDC11_PBDC1115 (0x8000u) + +#define GPIO_PIPC11_PIPC110 (0x0001u) +#define GPIO_PIPC11_PIPC111 (0x0002u) +#define GPIO_PIPC11_PIPC112 (0x0004u) +#define GPIO_PIPC11_PIPC113 (0x0008u) +#define GPIO_PIPC11_PIPC114 (0x0010u) +#define GPIO_PIPC11_PIPC115 (0x0020u) +#define GPIO_PIPC11_PIPC116 (0x0040u) +#define GPIO_PIPC11_PIPC117 (0x0080u) +#define GPIO_PIPC11_PIPC118 (0x0100u) +#define GPIO_PIPC11_PIPC119 (0x0200u) +#define GPIO_PIPC11_PIPC1110 (0x0400u) +#define GPIO_PIPC11_PIPC1111 (0x0800u) +#define GPIO_PIPC11_PIPC1112 (0x1000u) +#define GPIO_PIPC11_PIPC1113 (0x2000u) +#define GPIO_PIPC11_PIPC1114 (0x4000u) +#define GPIO_PIPC11_PIPC1115 (0x8000u) + + +/* ==== Shift values for IO registers ==== */ +/* ---- P0 ---- */ +#define GPIO_PPR0_PPR00_SHIFT (0u) +#define GPIO_PPR0_PPR01_SHIFT (1u) +#define GPIO_PPR0_PPR02_SHIFT (2u) +#define GPIO_PPR0_PPR03_SHIFT (3u) +#define GPIO_PPR0_PPR04_SHIFT (4u) +#define GPIO_PPR0_PPR05_SHIFT (5u) + +#define GPIO_PMC0_PMC04_SHIFT (4u) +#define GPIO_PMC0_PMC05_SHIFT (5u) + +#define GPIO_PMCSR0_PMCSR04_SHIFT (4u) +#define GPIO_PMCSR0_PMCSR05_SHIFT (5u) + +#define GPIO_PIBC0_PIBC00_SHIFT (0u) +#define GPIO_PIBC0_PIBC01_SHIFT (1u) +#define GPIO_PIBC0_PIBC02_SHIFT (2u) +#define GPIO_PIBC0_PIBC03_SHIFT (3u) +#define GPIO_PIBC0_PIBC04_SHIFT (4u) +#define GPIO_PIBC0_PIBC05_SHIFT (5u) + +/* ---- P1 ---- */ +#define GPIO_P1_P10_SHIFT (0u) +#define GPIO_P1_P11_SHIFT (1u) +#define GPIO_P1_P12_SHIFT (2u) +#define GPIO_P1_P13_SHIFT (3u) +#define GPIO_P1_P14_SHIFT (4u) +#define GPIO_P1_P15_SHIFT (5u) +#define GPIO_P1_P16_SHIFT (6u) +#define GPIO_P1_P17_SHIFT (7u) + +#define GPIO_PSR1_PSR10_SHIFT (0u) +#define GPIO_PSR1_PSR11_SHIFT (1u) +#define GPIO_PSR1_PSR12_SHIFT (2u) +#define GPIO_PSR1_PSR13_SHIFT (3u) +#define GPIO_PSR1_PSR14_SHIFT (4u) +#define GPIO_PSR1_PSR15_SHIFT (5u) +#define GPIO_PSR1_PSR16_SHIFT (6u) +#define GPIO_PSR1_PSR17_SHIFT (7u) +#define GPIO_PSR1_PSR116_SHIFT (16u) +#define GPIO_PSR1_PSR117_SHIFT (17u) +#define GPIO_PSR1_PSR118_SHIFT (18u) +#define GPIO_PSR1_PSR119_SHIFT (19u) +#define GPIO_PSR1_PSR120_SHIFT (20u) +#define GPIO_PSR1_PSR121_SHIFT (21u) +#define GPIO_PSR1_PSR122_SHIFT (22u) +#define GPIO_PSR1_PSR123_SHIFT (23u) + +#define GPIO_PPR1_PPR10_SHIFT (0u) +#define GPIO_PPR1_PPR11_SHIFT (1u) +#define GPIO_PPR1_PPR12_SHIFT (2u) +#define GPIO_PPR1_PPR13_SHIFT (3u) +#define GPIO_PPR1_PPR14_SHIFT (4u) +#define GPIO_PPR1_PPR15_SHIFT (5u) +#define GPIO_PPR1_PPR16_SHIFT (6u) +#define GPIO_PPR1_PPR17_SHIFT (7u) +#define GPIO_PPR1_PPR18_SHIFT (8u) +#define GPIO_PPR1_PPR19_SHIFT (9u) +#define GPIO_PPR1_PPR110_SHIFT (10u) +#define GPIO_PPR1_PPR111_SHIFT (11u) +#define GPIO_PPR1_PPR112_SHIFT (12u) +#define GPIO_PPR1_PPR113_SHIFT (13u) +#define GPIO_PPR1_PPR114_SHIFT (14u) +#define GPIO_PPR1_PPR115_SHIFT (15u) + +#define GPIO_PM1_PM10_SHIFT (0u) +#define GPIO_PM1_PM11_SHIFT (1u) +#define GPIO_PM1_PM12_SHIFT (2u) +#define GPIO_PM1_PM13_SHIFT (3u) +#define GPIO_PM1_PM14_SHIFT (4u) +#define GPIO_PM1_PM15_SHIFT (5u) +#define GPIO_PM1_PM16_SHIFT (6u) +#define GPIO_PM1_PM17_SHIFT (7u) + +#define GPIO_PMC1_PMC10_SHIFT (0u) +#define GPIO_PMC1_PMC11_SHIFT (1u) +#define GPIO_PMC1_PMC12_SHIFT (2u) +#define GPIO_PMC1_PMC13_SHIFT (3u) +#define GPIO_PMC1_PMC14_SHIFT (4u) +#define GPIO_PMC1_PMC15_SHIFT (5u) +#define GPIO_PMC1_PMC16_SHIFT (6u) +#define GPIO_PMC1_PMC17_SHIFT (7u) +#define GPIO_PMC1_PMC18_SHIFT (8u) +#define GPIO_PMC1_PMC19_SHIFT (9u) +#define GPIO_PMC1_PMC110_SHIFT (10u) +#define GPIO_PMC1_PMC111_SHIFT (11u) +#define GPIO_PMC1_PMC112_SHIFT (12u) +#define GPIO_PMC1_PMC113_SHIFT (13u) +#define GPIO_PMC1_PMC114_SHIFT (14u) +#define GPIO_PMC1_PMC115_SHIFT (15u) + +#define GPIO_PFC1_PFC10_SHIFT (0u) +#define GPIO_PFC1_PFC11_SHIFT (1u) +#define GPIO_PFC1_PFC12_SHIFT (2u) +#define GPIO_PFC1_PFC13_SHIFT (3u) +#define GPIO_PFC1_PFC14_SHIFT (4u) +#define GPIO_PFC1_PFC15_SHIFT (5u) +#define GPIO_PFC1_PFC16_SHIFT (6u) +#define GPIO_PFC1_PFC17_SHIFT (7u) +#define GPIO_PFC1_PFC18_SHIFT (8u) +#define GPIO_PFC1_PFC19_SHIFT (9u) +#define GPIO_PFC1_PFC110_SHIFT (10u) +#define GPIO_PFC1_PFC111_SHIFT (11u) +#define GPIO_PFC1_PFC112_SHIFT (12u) +#define GPIO_PFC1_PFC113_SHIFT (13u) +#define GPIO_PFC1_PFC114_SHIFT (14u) +#define GPIO_PFC1_PFC115_SHIFT (15u) + +#define GPIO_PFCE1_PFCE10_SHIFT (0u) +#define GPIO_PFCE1_PFCE11_SHIFT (1u) +#define GPIO_PFCE1_PFCE12_SHIFT (2u) +#define GPIO_PFCE1_PFCE13_SHIFT (3u) +#define GPIO_PFCE1_PFCE14_SHIFT (4u) +#define GPIO_PFCE1_PFCE15_SHIFT (5u) +#define GPIO_PFCE1_PFCE16_SHIFT (6u) +#define GPIO_PFCE1_PFCE17_SHIFT (7u) +#define GPIO_PFCE1_PFCE18_SHIFT (8u) +#define GPIO_PFCE1_PFCE19_SHIFT (9u) +#define GPIO_PFCE1_PFCE110_SHIFT (10u) +#define GPIO_PFCE1_PFCE111_SHIFT (11u) +#define GPIO_PFCE1_PFCE112_SHIFT (12u) +#define GPIO_PFCE1_PFCE113_SHIFT (13u) +#define GPIO_PFCE1_PFCE114_SHIFT (14u) +#define GPIO_PFCE1_PFCE115_SHIFT (15u) + +#define GPIO_PNOT1_PNOT10_SHIFT (0u) +#define GPIO_PNOT1_PNOT11_SHIFT (1u) +#define GPIO_PNOT1_PNOT12_SHIFT (2u) +#define GPIO_PNOT1_PNOT13_SHIFT (3u) +#define GPIO_PNOT1_PNOT14_SHIFT (4u) +#define GPIO_PNOT1_PNOT15_SHIFT (5u) +#define GPIO_PNOT1_PNOT16_SHIFT (6u) +#define GPIO_PNOT1_PNOT17_SHIFT (7u) + +#define GPIO_PMSR1_PMSR10_SHIFT (0u) +#define GPIO_PMSR1_PMSR11_SHIFT (1u) +#define GPIO_PMSR1_PMSR12_SHIFT (2u) +#define GPIO_PMSR1_PMSR13_SHIFT (3u) +#define GPIO_PMSR1_PMSR14_SHIFT (4u) +#define GPIO_PMSR1_PMSR15_SHIFT (5u) +#define GPIO_PMSR1_PMSR16_SHIFT (6u) +#define GPIO_PMSR1_PMSR17_SHIFT (7u) +#define GPIO_PMSR1_PMSR116_SHIFT (16u) +#define GPIO_PMSR1_PMSR117_SHIFT (17u) +#define GPIO_PMSR1_PMSR118_SHIFT (18u) +#define GPIO_PMSR1_PMSR119_SHIFT (19u) +#define GPIO_PMSR1_PMSR120_SHIFT (20u) +#define GPIO_PMSR1_PMSR121_SHIFT (21u) +#define GPIO_PMSR1_PMSR122_SHIFT (22u) +#define GPIO_PMSR1_PMSR123_SHIFT (23u) + +#define GPIO_PMCSR1_PMCSR10_SHIFT (0u) +#define GPIO_PMCSR1_PMCSR11_SHIFT (1u) +#define GPIO_PMCSR1_PMCSR12_SHIFT (2u) +#define GPIO_PMCSR1_PMCSR13_SHIFT (3u) +#define GPIO_PMCSR1_PMCSR14_SHIFT (4u) +#define GPIO_PMCSR1_PMCSR15_SHIFT (5u) +#define GPIO_PMCSR1_PMCSR16_SHIFT (6u) +#define GPIO_PMCSR1_PMCSR17_SHIFT (7u) +#define GPIO_PMCSR1_PMCSR116_SHIFT (16u) +#define GPIO_PMCSR1_PMCSR117_SHIFT (17u) +#define GPIO_PMCSR1_PMCSR118_SHIFT (18u) +#define GPIO_PMCSR1_PMCSR119_SHIFT (19u) +#define GPIO_PMCSR1_PMCSR120_SHIFT (20u) +#define GPIO_PMCSR1_PMCSR121_SHIFT (21u) +#define GPIO_PMCSR1_PMCSR122_SHIFT (22u) +#define GPIO_PMCSR1_PMCSR123_SHIFT (23u) + +#define GPIO_PFCAE1_PFCAE10_SHIFT (0u) +#define GPIO_PFCAE1_PFCAE11_SHIFT (1u) +#define GPIO_PFCAE1_PFCAE12_SHIFT (2u) +#define GPIO_PFCAE1_PFCAE13_SHIFT (3u) +#define GPIO_PFCAE1_PFCAE14_SHIFT (4u) +#define GPIO_PFCAE1_PFCAE15_SHIFT (5u) +#define GPIO_PFCAE1_PFCAE16_SHIFT (6u) +#define GPIO_PFCAE1_PFCAE17_SHIFT (7u) +#define GPIO_PFCAE1_PFCAE18_SHIFT (8u) +#define GPIO_PFCAE1_PFCAE19_SHIFT (9u) +#define GPIO_PFCAE1_PFCAE110_SHIFT (10u) +#define GPIO_PFCAE1_PFCAE111_SHIFT (11u) +#define GPIO_PFCAE1_PFCAE112_SHIFT (12u) +#define GPIO_PFCAE1_PFCAE113_SHIFT (13u) +#define GPIO_PFCAE1_PFCAE114_SHIFT (14u) +#define GPIO_PFCAE1_PFCAE115_SHIFT (15u) + +#define GPIO_PIBC1_PIBC10_SHIFT (0u) +#define GPIO_PIBC1_PIBC11_SHIFT (1u) +#define GPIO_PIBC1_PIBC12_SHIFT (2u) +#define GPIO_PIBC1_PIBC13_SHIFT (3u) +#define GPIO_PIBC1_PIBC14_SHIFT (4u) +#define GPIO_PIBC1_PIBC15_SHIFT (5u) +#define GPIO_PIBC1_PIBC16_SHIFT (6u) +#define GPIO_PIBC1_PIBC17_SHIFT (7u) +#define GPIO_PIBC1_PIBC18_SHIFT (8u) +#define GPIO_PIBC1_PIBC19_SHIFT (9u) +#define GPIO_PIBC1_PIBC110_SHIFT (10u) +#define GPIO_PIBC1_PIBC111_SHIFT (11u) +#define GPIO_PIBC1_PIBC112_SHIFT (12u) +#define GPIO_PIBC1_PIBC113_SHIFT (13u) +#define GPIO_PIBC1_PIBC114_SHIFT (14u) +#define GPIO_PIBC1_PIBC115_SHIFT (15u) + +#define GPIO_PBDC1_PBDC10_SHIFT (0u) +#define GPIO_PBDC1_PBDC11_SHIFT (1u) +#define GPIO_PBDC1_PBDC12_SHIFT (2u) +#define GPIO_PBDC1_PBDC13_SHIFT (3u) +#define GPIO_PBDC1_PBDC14_SHIFT (4u) +#define GPIO_PBDC1_PBDC15_SHIFT (5u) +#define GPIO_PBDC1_PBDC16_SHIFT (6u) +#define GPIO_PBDC1_PBDC17_SHIFT (7u) +#define GPIO_PBDC1_PBDC18_SHIFT (8u) +#define GPIO_PBDC1_PBDC19_SHIFT (9u) +#define GPIO_PBDC1_PBDC110_SHIFT (10u) +#define GPIO_PBDC1_PBDC111_SHIFT (11u) +#define GPIO_PBDC1_PBDC112_SHIFT (12u) +#define GPIO_PBDC1_PBDC113_SHIFT (13u) +#define GPIO_PBDC1_PBDC114_SHIFT (14u) +#define GPIO_PBDC1_PBDC115_SHIFT (15u) + +#define GPIO_PIPC1_PIPC10_SHIFT (0u) +#define GPIO_PIPC1_PIPC11_SHIFT (1u) +#define GPIO_PIPC1_PIPC12_SHIFT (2u) +#define GPIO_PIPC1_PIPC13_SHIFT (3u) +#define GPIO_PIPC1_PIPC14_SHIFT (4u) +#define GPIO_PIPC1_PIPC15_SHIFT (5u) +#define GPIO_PIPC1_PIPC16_SHIFT (6u) +#define GPIO_PIPC1_PIPC17_SHIFT (7u) + +/* ---- P2 ---- */ +#define GPIO_P2_P20_SHIFT (0u) +#define GPIO_P2_P21_SHIFT (1u) +#define GPIO_P2_P22_SHIFT (2u) +#define GPIO_P2_P23_SHIFT (3u) +#define GPIO_P2_P24_SHIFT (4u) +#define GPIO_P2_P25_SHIFT (5u) +#define GPIO_P2_P26_SHIFT (6u) +#define GPIO_P2_P27_SHIFT (7u) +#define GPIO_P2_P28_SHIFT (8u) +#define GPIO_P2_P29_SHIFT (9u) +#define GPIO_P2_P210_SHIFT (10u) +#define GPIO_P2_P211_SHIFT (11u) +#define GPIO_P2_P212_SHIFT (12u) +#define GPIO_P2_P213_SHIFT (13u) +#define GPIO_P2_P214_SHIFT (14u) +#define GPIO_P2_P215_SHIFT (15u) + +#define GPIO_PSR2_PSR20_SHIFT (0u) +#define GPIO_PSR2_PSR21_SHIFT (1u) +#define GPIO_PSR2_PSR22_SHIFT (2u) +#define GPIO_PSR2_PSR23_SHIFT (3u) +#define GPIO_PSR2_PSR24_SHIFT (4u) +#define GPIO_PSR2_PSR25_SHIFT (5u) +#define GPIO_PSR2_PSR26_SHIFT (6u) +#define GPIO_PSR2_PSR27_SHIFT (7u) +#define GPIO_PSR2_PSR28_SHIFT (8u) +#define GPIO_PSR2_PSR29_SHIFT (9u) +#define GPIO_PSR2_PSR210_SHIFT (10u) +#define GPIO_PSR2_PSR211_SHIFT (11u) +#define GPIO_PSR2_PSR212_SHIFT (12u) +#define GPIO_PSR2_PSR213_SHIFT (13u) +#define GPIO_PSR2_PSR214_SHIFT (14u) +#define GPIO_PSR2_PSR215_SHIFT (15u) +#define GPIO_PSR2_PSR216_SHIFT (16u) +#define GPIO_PSR2_PSR217_SHIFT (17u) +#define GPIO_PSR2_PSR218_SHIFT (18u) +#define GPIO_PSR2_PSR219_SHIFT (19u) +#define GPIO_PSR2_PSR220_SHIFT (20u) +#define GPIO_PSR2_PSR221_SHIFT (21u) +#define GPIO_PSR2_PSR222_SHIFT (22u) +#define GPIO_PSR2_PSR223_SHIFT (23u) +#define GPIO_PSR2_PSR224_SHIFT (24u) +#define GPIO_PSR2_PSR225_SHIFT (25u) +#define GPIO_PSR2_PSR226_SHIFT (26u) +#define GPIO_PSR2_PSR227_SHIFT (27u) +#define GPIO_PSR2_PSR228_SHIFT (28u) +#define GPIO_PSR2_PSR229_SHIFT (29u) +#define GPIO_PSR2_PSR230_SHIFT (30u) +#define GPIO_PSR2_PSR231_SHIFT (31u) + +#define GPIO_PPR2_PPR20_SHIFT (0u) +#define GPIO_PPR2_PPR21_SHIFT (1u) +#define GPIO_PPR2_PPR22_SHIFT (2u) +#define GPIO_PPR2_PPR23_SHIFT (3u) +#define GPIO_PPR2_PPR24_SHIFT (4u) +#define GPIO_PPR2_PPR25_SHIFT (5u) +#define GPIO_PPR2_PPR26_SHIFT (6u) +#define GPIO_PPR2_PPR27_SHIFT (7u) +#define GPIO_PPR2_PPR28_SHIFT (8u) +#define GPIO_PPR2_PPR29_SHIFT (9u) +#define GPIO_PPR2_PPR210_SHIFT (10u) +#define GPIO_PPR2_PPR211_SHIFT (11u) +#define GPIO_PPR2_PPR212_SHIFT (12u) +#define GPIO_PPR2_PPR213_SHIFT (13u) +#define GPIO_PPR2_PPR214_SHIFT (14u) +#define GPIO_PPR2_PPR215_SHIFT (15u) + +#define GPIO_PM2_PM20_SHIFT (0u) +#define GPIO_PM2_PM21_SHIFT (1u) +#define GPIO_PM2_PM22_SHIFT (2u) +#define GPIO_PM2_PM23_SHIFT (3u) +#define GPIO_PM2_PM24_SHIFT (4u) +#define GPIO_PM2_PM25_SHIFT (5u) +#define GPIO_PM2_PM26_SHIFT (6u) +#define GPIO_PM2_PM27_SHIFT (7u) +#define GPIO_PM2_PM28_SHIFT (8u) +#define GPIO_PM2_PM29_SHIFT (9u) +#define GPIO_PM2_PM210_SHIFT (10u) +#define GPIO_PM2_PM211_SHIFT (11u) +#define GPIO_PM2_PM212_SHIFT (12u) +#define GPIO_PM2_PM213_SHIFT (13u) +#define GPIO_PM2_PM214_SHIFT (14u) +#define GPIO_PM2_PM215_SHIFT (15u) + +#define GPIO_PMC2_PMC20_SHIFT (0u) +#define GPIO_PMC2_PMC21_SHIFT (1u) +#define GPIO_PMC2_PMC22_SHIFT (2u) +#define GPIO_PMC2_PMC23_SHIFT (3u) +#define GPIO_PMC2_PMC24_SHIFT (4u) +#define GPIO_PMC2_PMC25_SHIFT (5u) +#define GPIO_PMC2_PMC26_SHIFT (6u) +#define GPIO_PMC2_PMC27_SHIFT (7u) +#define GPIO_PMC2_PMC28_SHIFT (8u) +#define GPIO_PMC2_PMC29_SHIFT (9u) +#define GPIO_PMC2_PMC210_SHIFT (10u) +#define GPIO_PMC2_PMC211_SHIFT (11u) +#define GPIO_PMC2_PMC212_SHIFT (12u) +#define GPIO_PMC2_PMC213_SHIFT (13u) +#define GPIO_PMC2_PMC214_SHIFT (14u) +#define GPIO_PMC2_PMC215_SHIFT (15u) + +#define GPIO_PFC2_PFC20_SHIFT (0u) +#define GPIO_PFC2_PFC21_SHIFT (1u) +#define GPIO_PFC2_PFC22_SHIFT (2u) +#define GPIO_PFC2_PFC23_SHIFT (3u) +#define GPIO_PFC2_PFC24_SHIFT (4u) +#define GPIO_PFC2_PFC25_SHIFT (5u) +#define GPIO_PFC2_PFC26_SHIFT (6u) +#define GPIO_PFC2_PFC27_SHIFT (7u) +#define GPIO_PFC2_PFC28_SHIFT (8u) +#define GPIO_PFC2_PFC29_SHIFT (9u) +#define GPIO_PFC2_PFC210_SHIFT (10u) +#define GPIO_PFC2_PFC211_SHIFT (11u) +#define GPIO_PFC2_PFC212_SHIFT (12u) +#define GPIO_PFC2_PFC213_SHIFT (13u) +#define GPIO_PFC2_PFC214_SHIFT (14u) +#define GPIO_PFC2_PFC215_SHIFT (15u) + +#define GPIO_PFCE2_PFCE20_SHIFT (0u) +#define GPIO_PFCE2_PFCE21_SHIFT (1u) +#define GPIO_PFCE2_PFCE22_SHIFT (2u) +#define GPIO_PFCE2_PFCE23_SHIFT (3u) +#define GPIO_PFCE2_PFCE24_SHIFT (4u) +#define GPIO_PFCE2_PFCE25_SHIFT (5u) +#define GPIO_PFCE2_PFCE26_SHIFT (6u) +#define GPIO_PFCE2_PFCE27_SHIFT (7u) +#define GPIO_PFCE2_PFCE28_SHIFT (8u) +#define GPIO_PFCE2_PFCE29_SHIFT (9u) +#define GPIO_PFCE2_PFCE210_SHIFT (10u) +#define GPIO_PFCE2_PFCE211_SHIFT (11u) +#define GPIO_PFCE2_PFCE212_SHIFT (12u) +#define GPIO_PFCE2_PFCE213_SHIFT (13u) +#define GPIO_PFCE2_PFCE214_SHIFT (14u) +#define GPIO_PFCE2_PFCE215_SHIFT (15u) + +#define GPIO_PNOT2_PNOT20_SHIFT (0u) +#define GPIO_PNOT2_PNOT21_SHIFT (1u) +#define GPIO_PNOT2_PNOT22_SHIFT (2u) +#define GPIO_PNOT2_PNOT23_SHIFT (3u) +#define GPIO_PNOT2_PNOT24_SHIFT (4u) +#define GPIO_PNOT2_PNOT25_SHIFT (5u) +#define GPIO_PNOT2_PNOT26_SHIFT (6u) +#define GPIO_PNOT2_PNOT27_SHIFT (7u) +#define GPIO_PNOT2_PNOT28_SHIFT (8u) +#define GPIO_PNOT2_PNOT29_SHIFT (9u) +#define GPIO_PNOT2_PNOT210_SHIFT (10u) +#define GPIO_PNOT2_PNOT211_SHIFT (11u) +#define GPIO_PNOT2_PNOT212_SHIFT (12u) +#define GPIO_PNOT2_PNOT213_SHIFT (13u) +#define GPIO_PNOT2_PNOT214_SHIFT (14u) +#define GPIO_PNOT2_PNOT215_SHIFT (15u) + +#define GPIO_PMSR2_PMSR20_SHIFT (0u) +#define GPIO_PMSR2_PMSR21_SHIFT (1u) +#define GPIO_PMSR2_PMSR22_SHIFT (2u) +#define GPIO_PMSR2_PMSR23_SHIFT (3u) +#define GPIO_PMSR2_PMSR24_SHIFT (4u) +#define GPIO_PMSR2_PMSR25_SHIFT (5u) +#define GPIO_PMSR2_PMSR26_SHIFT (6u) +#define GPIO_PMSR2_PMSR27_SHIFT (7u) +#define GPIO_PMSR2_PMSR28_SHIFT (8u) +#define GPIO_PMSR2_PMSR29_SHIFT (9u) +#define GPIO_PMSR2_PMSR210_SHIFT (10u) +#define GPIO_PMSR2_PMSR211_SHIFT (11u) +#define GPIO_PMSR2_PMSR212_SHIFT (12u) +#define GPIO_PMSR2_PMSR213_SHIFT (13u) +#define GPIO_PMSR2_PMSR214_SHIFT (14u) +#define GPIO_PMSR2_PMSR215_SHIFT (15u) +#define GPIO_PMSR2_PMSR216_SHIFT (16u) +#define GPIO_PMSR2_PMSR217_SHIFT (17u) +#define GPIO_PMSR2_PMSR218_SHIFT (18u) +#define GPIO_PMSR2_PMSR219_SHIFT (19u) +#define GPIO_PMSR2_PMSR220_SHIFT (20u) +#define GPIO_PMSR2_PMSR221_SHIFT (21u) +#define GPIO_PMSR2_PMSR222_SHIFT (22u) +#define GPIO_PMSR2_PMSR223_SHIFT (23u) +#define GPIO_PMSR2_PMSR224_SHIFT (24u) +#define GPIO_PMSR2_PMSR225_SHIFT (25u) +#define GPIO_PMSR2_PMSR226_SHIFT (26u) +#define GPIO_PMSR2_PMSR227_SHIFT (27u) +#define GPIO_PMSR2_PMSR228_SHIFT (28u) +#define GPIO_PMSR2_PMSR229_SHIFT (29u) +#define GPIO_PMSR2_PMSR230_SHIFT (30u) +#define GPIO_PMSR2_PMSR231_SHIFT (31u) + +#define GPIO_PMCSR2_PMCSR20_SHIFT (0u) +#define GPIO_PMCSR2_PMCSR21_SHIFT (1u) +#define GPIO_PMCSR2_PMCSR22_SHIFT (2u) +#define GPIO_PMCSR2_PMCSR23_SHIFT (3u) +#define GPIO_PMCSR2_PMCSR24_SHIFT (4u) +#define GPIO_PMCSR2_PMCSR25_SHIFT (5u) +#define GPIO_PMCSR2_PMCSR26_SHIFT (6u) +#define GPIO_PMCSR2_PMCSR27_SHIFT (7u) +#define GPIO_PMCSR2_PMCSR28_SHIFT (8u) +#define GPIO_PMCSR2_PMCSR29_SHIFT (9u) +#define GPIO_PMCSR2_PMCSR210_SHIFT (10u) +#define GPIO_PMCSR2_PMCSR211_SHIFT (11u) +#define GPIO_PMCSR2_PMCSR212_SHIFT (12u) +#define GPIO_PMCSR2_PMCSR213_SHIFT (13u) +#define GPIO_PMCSR2_PMCSR214_SHIFT (14u) +#define GPIO_PMCSR2_PMCSR215_SHIFT (15u) +#define GPIO_PMCSR2_PMCSR216_SHIFT (16u) +#define GPIO_PMCSR2_PMCSR217_SHIFT (17u) +#define GPIO_PMCSR2_PMCSR218_SHIFT (18u) +#define GPIO_PMCSR2_PMCSR219_SHIFT (19u) +#define GPIO_PMCSR2_PMCSR220_SHIFT (20u) +#define GPIO_PMCSR2_PMCSR221_SHIFT (21u) +#define GPIO_PMCSR2_PMCSR222_SHIFT (22u) +#define GPIO_PMCSR2_PMCSR223_SHIFT (23u) +#define GPIO_PMCSR2_PMCSR224_SHIFT (24u) +#define GPIO_PMCSR2_PMCSR225_SHIFT (25u) +#define GPIO_PMCSR2_PMCSR226_SHIFT (26u) +#define GPIO_PMCSR2_PMCSR227_SHIFT (27u) +#define GPIO_PMCSR2_PMCSR228_SHIFT (28u) +#define GPIO_PMCSR2_PMCSR229_SHIFT (29u) +#define GPIO_PMCSR2_PMCSR230_SHIFT (30u) +#define GPIO_PMCSR2_PMCSR231_SHIFT (31u) + +#define GPIO_PFCAE2_PFCAE20_SHIFT (0u) +#define GPIO_PFCAE2_PFCAE21_SHIFT (1u) +#define GPIO_PFCAE2_PFCAE22_SHIFT (2u) +#define GPIO_PFCAE2_PFCAE23_SHIFT (3u) +#define GPIO_PFCAE2_PFCAE24_SHIFT (4u) +#define GPIO_PFCAE2_PFCAE25_SHIFT (5u) +#define GPIO_PFCAE2_PFCAE26_SHIFT (6u) +#define GPIO_PFCAE2_PFCAE27_SHIFT (7u) +#define GPIO_PFCAE2_PFCAE28_SHIFT (8u) +#define GPIO_PFCAE2_PFCAE29_SHIFT (9u) +#define GPIO_PFCAE2_PFCAE210_SHIFT (10u) +#define GPIO_PFCAE2_PFCAE211_SHIFT (11u) +#define GPIO_PFCAE2_PFCAE212_SHIFT (12u) +#define GPIO_PFCAE2_PFCAE213_SHIFT (13u) +#define GPIO_PFCAE2_PFCAE214_SHIFT (14u) +#define GPIO_PFCAE2_PFCAE215_SHIFT (15u) + +#define GPIO_PIBC2_PIBC20_SHIFT (0u) +#define GPIO_PIBC2_PIBC21_SHIFT (1u) +#define GPIO_PIBC2_PIBC22_SHIFT (2u) +#define GPIO_PIBC2_PIBC23_SHIFT (3u) +#define GPIO_PIBC2_PIBC24_SHIFT (4u) +#define GPIO_PIBC2_PIBC25_SHIFT (5u) +#define GPIO_PIBC2_PIBC26_SHIFT (6u) +#define GPIO_PIBC2_PIBC27_SHIFT (7u) +#define GPIO_PIBC2_PIBC28_SHIFT (8u) +#define GPIO_PIBC2_PIBC29_SHIFT (9u) +#define GPIO_PIBC2_PIBC210_SHIFT (10u) +#define GPIO_PIBC2_PIBC211_SHIFT (11u) +#define GPIO_PIBC2_PIBC212_SHIFT (12u) +#define GPIO_PIBC2_PIBC213_SHIFT (13u) +#define GPIO_PIBC2_PIBC214_SHIFT (14u) +#define GPIO_PIBC2_PIBC215_SHIFT (15u) + +#define GPIO_PBDC2_PBDC20_SHIFT (0u) +#define GPIO_PBDC2_PBDC21_SHIFT (1u) +#define GPIO_PBDC2_PBDC22_SHIFT (2u) +#define GPIO_PBDC2_PBDC23_SHIFT (3u) +#define GPIO_PBDC2_PBDC24_SHIFT (4u) +#define GPIO_PBDC2_PBDC25_SHIFT (5u) +#define GPIO_PBDC2_PBDC26_SHIFT (6u) +#define GPIO_PBDC2_PBDC27_SHIFT (7u) +#define GPIO_PBDC2_PBDC28_SHIFT (8u) +#define GPIO_PBDC2_PBDC29_SHIFT (9u) +#define GPIO_PBDC2_PBDC210_SHIFT (10u) +#define GPIO_PBDC2_PBDC211_SHIFT (11u) +#define GPIO_PBDC2_PBDC212_SHIFT (12u) +#define GPIO_PBDC2_PBDC213_SHIFT (13u) +#define GPIO_PBDC2_PBDC214_SHIFT (14u) +#define GPIO_PBDC2_PBDC215_SHIFT (15u) + +#define GPIO_PIPC2_PIPC20_SHIFT (0u) +#define GPIO_PIPC2_PIPC21_SHIFT (1u) +#define GPIO_PIPC2_PIPC22_SHIFT (2u) +#define GPIO_PIPC2_PIPC23_SHIFT (3u) +#define GPIO_PIPC2_PIPC24_SHIFT (4u) +#define GPIO_PIPC2_PIPC25_SHIFT (5u) +#define GPIO_PIPC2_PIPC26_SHIFT (6u) +#define GPIO_PIPC2_PIPC27_SHIFT (7u) +#define GPIO_PIPC2_PIPC28_SHIFT (8u) +#define GPIO_PIPC2_PIPC29_SHIFT (9u) +#define GPIO_PIPC2_PIPC210_SHIFT (10u) +#define GPIO_PIPC2_PIPC211_SHIFT (11u) +#define GPIO_PIPC2_PIPC212_SHIFT (12u) +#define GPIO_PIPC2_PIPC213_SHIFT (13u) +#define GPIO_PIPC2_PIPC214_SHIFT (14u) +#define GPIO_PIPC2_PIPC215_SHIFT (15u) + +/* ---- P3 ---- */ +#define GPIO_P3_P30_SHIFT (0u) +#define GPIO_P3_P31_SHIFT (1u) +#define GPIO_P3_P32_SHIFT (2u) +#define GPIO_P3_P33_SHIFT (3u) +#define GPIO_P3_P34_SHIFT (4u) +#define GPIO_P3_P35_SHIFT (5u) +#define GPIO_P3_P36_SHIFT (6u) +#define GPIO_P3_P37_SHIFT (7u) +#define GPIO_P3_P38_SHIFT (8u) +#define GPIO_P3_P39_SHIFT (9u) +#define GPIO_P3_P310_SHIFT (10u) +#define GPIO_P3_P311_SHIFT (11u) +#define GPIO_P3_P312_SHIFT (12u) +#define GPIO_P3_P313_SHIFT (13u) +#define GPIO_P3_P314_SHIFT (14u) +#define GPIO_P3_P315_SHIFT (15u) + +#define GPIO_PSR3_PSR30_SHIFT (0u) +#define GPIO_PSR3_PSR31_SHIFT (1u) +#define GPIO_PSR3_PSR32_SHIFT (2u) +#define GPIO_PSR3_PSR33_SHIFT (3u) +#define GPIO_PSR3_PSR34_SHIFT (4u) +#define GPIO_PSR3_PSR35_SHIFT (5u) +#define GPIO_PSR3_PSR36_SHIFT (6u) +#define GPIO_PSR3_PSR37_SHIFT (7u) +#define GPIO_PSR3_PSR38_SHIFT (8u) +#define GPIO_PSR3_PSR39_SHIFT (9u) +#define GPIO_PSR3_PSR310_SHIFT (10u) +#define GPIO_PSR3_PSR311_SHIFT (11u) +#define GPIO_PSR3_PSR312_SHIFT (12u) +#define GPIO_PSR3_PSR313_SHIFT (13u) +#define GPIO_PSR3_PSR314_SHIFT (14u) +#define GPIO_PSR3_PSR315_SHIFT (15u) +#define GPIO_PSR3_PSR316_SHIFT (16u) +#define GPIO_PSR3_PSR317_SHIFT (17u) +#define GPIO_PSR3_PSR318_SHIFT (18u) +#define GPIO_PSR3_PSR319_SHIFT (19u) +#define GPIO_PSR3_PSR320_SHIFT (20u) +#define GPIO_PSR3_PSR321_SHIFT (21u) +#define GPIO_PSR3_PSR322_SHIFT (22u) +#define GPIO_PSR3_PSR323_SHIFT (23u) +#define GPIO_PSR3_PSR324_SHIFT (24u) +#define GPIO_PSR3_PSR325_SHIFT (25u) +#define GPIO_PSR3_PSR326_SHIFT (26u) +#define GPIO_PSR3_PSR327_SHIFT (27u) +#define GPIO_PSR3_PSR328_SHIFT (28u) +#define GPIO_PSR3_PSR329_SHIFT (29u) +#define GPIO_PSR3_PSR330_SHIFT (30u) +#define GPIO_PSR3_PSR331_SHIFT (31u) + +#define GPIO_PPR3_PPR30_SHIFT (0u) +#define GPIO_PPR3_PPR31_SHIFT (1u) +#define GPIO_PPR3_PPR32_SHIFT (2u) +#define GPIO_PPR3_PPR33_SHIFT (3u) +#define GPIO_PPR3_PPR34_SHIFT (4u) +#define GPIO_PPR3_PPR35_SHIFT (5u) +#define GPIO_PPR3_PPR36_SHIFT (6u) +#define GPIO_PPR3_PPR37_SHIFT (7u) +#define GPIO_PPR3_PPR38_SHIFT (8u) +#define GPIO_PPR3_PPR39_SHIFT (9u) +#define GPIO_PPR3_PPR310_SHIFT (10u) +#define GPIO_PPR3_PPR311_SHIFT (11u) +#define GPIO_PPR3_PPR312_SHIFT (12u) +#define GPIO_PPR3_PPR313_SHIFT (13u) +#define GPIO_PPR3_PPR314_SHIFT (14u) +#define GPIO_PPR3_PPR315_SHIFT (15u) + +#define GPIO_PM3_PM30_SHIFT (0u) +#define GPIO_PM3_PM31_SHIFT (1u) +#define GPIO_PM3_PM32_SHIFT (2u) +#define GPIO_PM3_PM33_SHIFT (3u) +#define GPIO_PM3_PM34_SHIFT (4u) +#define GPIO_PM3_PM35_SHIFT (5u) +#define GPIO_PM3_PM36_SHIFT (6u) +#define GPIO_PM3_PM37_SHIFT (7u) +#define GPIO_PM3_PM38_SHIFT (8u) +#define GPIO_PM3_PM39_SHIFT (9u) +#define GPIO_PM3_PM310_SHIFT (10u) +#define GPIO_PM3_PM311_SHIFT (11u) +#define GPIO_PM3_PM312_SHIFT (12u) +#define GPIO_PM3_PM313_SHIFT (13u) +#define GPIO_PM3_PM314_SHIFT (14u) +#define GPIO_PM3_PM315_SHIFT (15u) + +#define GPIO_PMC3_PMC30_SHIFT (0u) +#define GPIO_PMC3_PMC31_SHIFT (1u) +#define GPIO_PMC3_PMC32_SHIFT (2u) +#define GPIO_PMC3_PMC33_SHIFT (3u) +#define GPIO_PMC3_PMC34_SHIFT (4u) +#define GPIO_PMC3_PMC35_SHIFT (5u) +#define GPIO_PMC3_PMC36_SHIFT (6u) +#define GPIO_PMC3_PMC37_SHIFT (7u) +#define GPIO_PMC3_PMC38_SHIFT (8u) +#define GPIO_PMC3_PMC39_SHIFT (9u) +#define GPIO_PMC3_PMC310_SHIFT (10u) +#define GPIO_PMC3_PMC311_SHIFT (11u) +#define GPIO_PMC3_PMC312_SHIFT (12u) +#define GPIO_PMC3_PMC313_SHIFT (13u) +#define GPIO_PMC3_PMC314_SHIFT (14u) +#define GPIO_PMC3_PMC315_SHIFT (15u) + +#define GPIO_PFC3_PFC30_SHIFT (0u) +#define GPIO_PFC3_PFC31_SHIFT (1u) +#define GPIO_PFC3_PFC32_SHIFT (2u) +#define GPIO_PFC3_PFC33_SHIFT (3u) +#define GPIO_PFC3_PFC34_SHIFT (4u) +#define GPIO_PFC3_PFC35_SHIFT (5u) +#define GPIO_PFC3_PFC36_SHIFT (6u) +#define GPIO_PFC3_PFC37_SHIFT (7u) +#define GPIO_PFC3_PFC38_SHIFT (8u) +#define GPIO_PFC3_PFC39_SHIFT (9u) +#define GPIO_PFC3_PFC310_SHIFT (10u) +#define GPIO_PFC3_PFC311_SHIFT (11u) +#define GPIO_PFC3_PFC312_SHIFT (12u) +#define GPIO_PFC3_PFC313_SHIFT (13u) +#define GPIO_PFC3_PFC314_SHIFT (14u) +#define GPIO_PFC3_PFC315_SHIFT (15u) + +#define GPIO_PFCE3_PFCE30_SHIFT (0u) +#define GPIO_PFCE3_PFCE31_SHIFT (1u) +#define GPIO_PFCE3_PFCE32_SHIFT (2u) +#define GPIO_PFCE3_PFCE33_SHIFT (3u) +#define GPIO_PFCE3_PFCE34_SHIFT (4u) +#define GPIO_PFCE3_PFCE35_SHIFT (5u) +#define GPIO_PFCE3_PFCE36_SHIFT (6u) +#define GPIO_PFCE3_PFCE37_SHIFT (7u) +#define GPIO_PFCE3_PFCE38_SHIFT (8u) +#define GPIO_PFCE3_PFCE39_SHIFT (9u) +#define GPIO_PFCE3_PFCE310_SHIFT (10u) +#define GPIO_PFCE3_PFCE311_SHIFT (11u) +#define GPIO_PFCE3_PFCE312_SHIFT (12u) +#define GPIO_PFCE3_PFCE313_SHIFT (13u) +#define GPIO_PFCE3_PFCE314_SHIFT (14u) +#define GPIO_PFCE3_PFCE315_SHIFT (15u) + +#define GPIO_PNOT3_PNOT30_SHIFT (0u) +#define GPIO_PNOT3_PNOT31_SHIFT (1u) +#define GPIO_PNOT3_PNOT32_SHIFT (2u) +#define GPIO_PNOT3_PNOT33_SHIFT (3u) +#define GPIO_PNOT3_PNOT34_SHIFT (4u) +#define GPIO_PNOT3_PNOT35_SHIFT (5u) +#define GPIO_PNOT3_PNOT36_SHIFT (6u) +#define GPIO_PNOT3_PNOT37_SHIFT (7u) +#define GPIO_PNOT3_PNOT38_SHIFT (8u) +#define GPIO_PNOT3_PNOT39_SHIFT (9u) +#define GPIO_PNOT3_PNOT310_SHIFT (10u) +#define GPIO_PNOT3_PNOT311_SHIFT (11u) +#define GPIO_PNOT3_PNOT312_SHIFT (12u) +#define GPIO_PNOT3_PNOT313_SHIFT (13u) +#define GPIO_PNOT3_PNOT314_SHIFT (14u) +#define GPIO_PNOT3_PNOT315_SHIFT (15u) + +#define GPIO_PMSR3_PMSR30_SHIFT (0u) +#define GPIO_PMSR3_PMSR31_SHIFT (1u) +#define GPIO_PMSR3_PMSR32_SHIFT (2u) +#define GPIO_PMSR3_PMSR33_SHIFT (3u) +#define GPIO_PMSR3_PMSR34_SHIFT (4u) +#define GPIO_PMSR3_PMSR35_SHIFT (5u) +#define GPIO_PMSR3_PMSR36_SHIFT (6u) +#define GPIO_PMSR3_PMSR37_SHIFT (7u) +#define GPIO_PMSR3_PMSR38_SHIFT (8u) +#define GPIO_PMSR3_PMSR39_SHIFT (9u) +#define GPIO_PMSR3_PMSR310_SHIFT (10u) +#define GPIO_PMSR3_PMSR311_SHIFT (11u) +#define GPIO_PMSR3_PMSR312_SHIFT (12u) +#define GPIO_PMSR3_PMSR313_SHIFT (13u) +#define GPIO_PMSR3_PMSR314_SHIFT (14u) +#define GPIO_PMSR3_PMSR315_SHIFT (15u) +#define GPIO_PMSR3_PMSR316_SHIFT (16u) +#define GPIO_PMSR3_PMSR317_SHIFT (17u) +#define GPIO_PMSR3_PMSR318_SHIFT (18u) +#define GPIO_PMSR3_PMSR319_SHIFT (19u) +#define GPIO_PMSR3_PMSR320_SHIFT (20u) +#define GPIO_PMSR3_PMSR321_SHIFT (21u) +#define GPIO_PMSR3_PMSR322_SHIFT (22u) +#define GPIO_PMSR3_PMSR323_SHIFT (23u) +#define GPIO_PMSR3_PMSR324_SHIFT (24u) +#define GPIO_PMSR3_PMSR325_SHIFT (25u) +#define GPIO_PMSR3_PMSR326_SHIFT (26u) +#define GPIO_PMSR3_PMSR327_SHIFT (27u) +#define GPIO_PMSR3_PMSR328_SHIFT (28u) +#define GPIO_PMSR3_PMSR329_SHIFT (29u) +#define GPIO_PMSR3_PMSR330_SHIFT (30u) +#define GPIO_PMSR3_PMSR331_SHIFT (31u) + +#define GPIO_PMCSR3_PMCSR30_SHIFT (0u) +#define GPIO_PMCSR3_PMCSR31_SHIFT (1u) +#define GPIO_PMCSR3_PMCSR32_SHIFT (2u) +#define GPIO_PMCSR3_PMCSR33_SHIFT (3u) +#define GPIO_PMCSR3_PMCSR34_SHIFT (4u) +#define GPIO_PMCSR3_PMCSR35_SHIFT (5u) +#define GPIO_PMCSR3_PMCSR36_SHIFT (6u) +#define GPIO_PMCSR3_PMCSR37_SHIFT (7u) +#define GPIO_PMCSR3_PMCSR38_SHIFT (8u) +#define GPIO_PMCSR3_PMCSR39_SHIFT (9u) +#define GPIO_PMCSR3_PMCSR310_SHIFT (10u) +#define GPIO_PMCSR3_PMCSR311_SHIFT (11u) +#define GPIO_PMCSR3_PMCSR312_SHIFT (12u) +#define GPIO_PMCSR3_PMCSR313_SHIFT (13u) +#define GPIO_PMCSR3_PMCSR314_SHIFT (14u) +#define GPIO_PMCSR3_PMCSR315_SHIFT (15u) +#define GPIO_PMCSR3_PMCSR316_SHIFT (16u) +#define GPIO_PMCSR3_PMCSR317_SHIFT (17u) +#define GPIO_PMCSR3_PMCSR318_SHIFT (18u) +#define GPIO_PMCSR3_PMCSR319_SHIFT (19u) +#define GPIO_PMCSR3_PMCSR320_SHIFT (20u) +#define GPIO_PMCSR3_PMCSR321_SHIFT (21u) +#define GPIO_PMCSR3_PMCSR322_SHIFT (22u) +#define GPIO_PMCSR3_PMCSR323_SHIFT (23u) +#define GPIO_PMCSR3_PMCSR324_SHIFT (24u) +#define GPIO_PMCSR3_PMCSR325_SHIFT (25u) +#define GPIO_PMCSR3_PMCSR326_SHIFT (26u) +#define GPIO_PMCSR3_PMCSR327_SHIFT (27u) +#define GPIO_PMCSR3_PMCSR328_SHIFT (28u) +#define GPIO_PMCSR3_PMCSR329_SHIFT (29u) +#define GPIO_PMCSR3_PMCSR330_SHIFT (30u) +#define GPIO_PMCSR3_PMCSR331_SHIFT (31u) + +#define GPIO_PFCAE3_PFCAE30_SHIFT (0u) +#define GPIO_PFCAE3_PFCAE31_SHIFT (1u) +#define GPIO_PFCAE3_PFCAE32_SHIFT (2u) +#define GPIO_PFCAE3_PFCAE33_SHIFT (3u) +#define GPIO_PFCAE3_PFCAE34_SHIFT (4u) +#define GPIO_PFCAE3_PFCAE35_SHIFT (5u) +#define GPIO_PFCAE3_PFCAE36_SHIFT (6u) +#define GPIO_PFCAE3_PFCAE37_SHIFT (7u) +#define GPIO_PFCAE3_PFCAE38_SHIFT (8u) +#define GPIO_PFCAE3_PFCAE39_SHIFT (9u) +#define GPIO_PFCAE3_PFCAE310_SHIFT (10u) +#define GPIO_PFCAE3_PFCAE311_SHIFT (11u) +#define GPIO_PFCAE3_PFCAE312_SHIFT (12u) +#define GPIO_PFCAE3_PFCAE313_SHIFT (13u) +#define GPIO_PFCAE3_PFCAE314_SHIFT (14u) +#define GPIO_PFCAE3_PFCAE315_SHIFT (15u) + +#define GPIO_PIBC3_PIBC30_SHIFT (0u) +#define GPIO_PIBC3_PIBC31_SHIFT (1u) +#define GPIO_PIBC3_PIBC32_SHIFT (2u) +#define GPIO_PIBC3_PIBC33_SHIFT (3u) +#define GPIO_PIBC3_PIBC34_SHIFT (4u) +#define GPIO_PIBC3_PIBC35_SHIFT (5u) +#define GPIO_PIBC3_PIBC36_SHIFT (6u) +#define GPIO_PIBC3_PIBC37_SHIFT (7u) +#define GPIO_PIBC3_PIBC38_SHIFT (8u) +#define GPIO_PIBC3_PIBC39_SHIFT (9u) +#define GPIO_PIBC3_PIBC310_SHIFT (10u) +#define GPIO_PIBC3_PIBC311_SHIFT (11u) +#define GPIO_PIBC3_PIBC312_SHIFT (12u) +#define GPIO_PIBC3_PIBC313_SHIFT (13u) +#define GPIO_PIBC3_PIBC314_SHIFT (14u) +#define GPIO_PIBC3_PIBC315_SHIFT (15u) + +#define GPIO_PBDC3_PBDC30_SHIFT (0u) +#define GPIO_PBDC3_PBDC31_SHIFT (1u) +#define GPIO_PBDC3_PBDC32_SHIFT (2u) +#define GPIO_PBDC3_PBDC33_SHIFT (3u) +#define GPIO_PBDC3_PBDC34_SHIFT (4u) +#define GPIO_PBDC3_PBDC35_SHIFT (5u) +#define GPIO_PBDC3_PBDC36_SHIFT (6u) +#define GPIO_PBDC3_PBDC37_SHIFT (7u) +#define GPIO_PBDC3_PBDC38_SHIFT (8u) +#define GPIO_PBDC3_PBDC39_SHIFT (9u) +#define GPIO_PBDC3_PBDC310_SHIFT (10u) +#define GPIO_PBDC3_PBDC311_SHIFT (11u) +#define GPIO_PBDC3_PBDC312_SHIFT (12u) +#define GPIO_PBDC3_PBDC313_SHIFT (13u) +#define GPIO_PBDC3_PBDC314_SHIFT (14u) +#define GPIO_PBDC3_PBDC315_SHIFT (15u) + +#define GPIO_PIPC3_PIPC30_SHIFT (0u) +#define GPIO_PIPC3_PIPC31_SHIFT (1u) +#define GPIO_PIPC3_PIPC32_SHIFT (2u) +#define GPIO_PIPC3_PIPC33_SHIFT (3u) +#define GPIO_PIPC3_PIPC34_SHIFT (4u) +#define GPIO_PIPC3_PIPC35_SHIFT (5u) +#define GPIO_PIPC3_PIPC36_SHIFT (6u) +#define GPIO_PIPC3_PIPC37_SHIFT (7u) +#define GPIO_PIPC3_PIPC38_SHIFT (8u) +#define GPIO_PIPC3_PIPC39_SHIFT (9u) +#define GPIO_PIPC3_PIPC310_SHIFT (10u) +#define GPIO_PIPC3_PIPC311_SHIFT (11u) +#define GPIO_PIPC3_PIPC312_SHIFT (12u) +#define GPIO_PIPC3_PIPC313_SHIFT (13u) +#define GPIO_PIPC3_PIPC314_SHIFT (14u) +#define GPIO_PIPC3_PIPC315_SHIFT (15u) + +/* ---- P4 ---- */ +#define GPIO_P4_P40_SHIFT (0u) +#define GPIO_P4_P41_SHIFT (1u) +#define GPIO_P4_P42_SHIFT (2u) +#define GPIO_P4_P43_SHIFT (3u) +#define GPIO_P4_P44_SHIFT (4u) +#define GPIO_P4_P45_SHIFT (5u) +#define GPIO_P4_P46_SHIFT (6u) +#define GPIO_P4_P47_SHIFT (7u) +#define GPIO_P4_P48_SHIFT (8u) +#define GPIO_P4_P49_SHIFT (9u) +#define GPIO_P4_P410_SHIFT (10u) +#define GPIO_P4_P411_SHIFT (11u) +#define GPIO_P4_P412_SHIFT (12u) +#define GPIO_P4_P413_SHIFT (13u) +#define GPIO_P4_P414_SHIFT (14u) +#define GPIO_P4_P415_SHIFT (15u) + +#define GPIO_PSR4_PSR40_SHIFT (0u) +#define GPIO_PSR4_PSR41_SHIFT (1u) +#define GPIO_PSR4_PSR42_SHIFT (2u) +#define GPIO_PSR4_PSR43_SHIFT (3u) +#define GPIO_PSR4_PSR44_SHIFT (4u) +#define GPIO_PSR4_PSR45_SHIFT (5u) +#define GPIO_PSR4_PSR46_SHIFT (6u) +#define GPIO_PSR4_PSR47_SHIFT (7u) +#define GPIO_PSR4_PSR48_SHIFT (8u) +#define GPIO_PSR4_PSR49_SHIFT (9u) +#define GPIO_PSR4_PSR410_SHIFT (10u) +#define GPIO_PSR4_PSR411_SHIFT (11u) +#define GPIO_PSR4_PSR412_SHIFT (12u) +#define GPIO_PSR4_PSR413_SHIFT (13u) +#define GPIO_PSR4_PSR414_SHIFT (14u) +#define GPIO_PSR4_PSR415_SHIFT (15u) +#define GPIO_PSR4_PSR416_SHIFT (16u) +#define GPIO_PSR4_PSR417_SHIFT (17u) +#define GPIO_PSR4_PSR418_SHIFT (18u) +#define GPIO_PSR4_PSR419_SHIFT (19u) +#define GPIO_PSR4_PSR420_SHIFT (20u) +#define GPIO_PSR4_PSR421_SHIFT (21u) +#define GPIO_PSR4_PSR422_SHIFT (22u) +#define GPIO_PSR4_PSR423_SHIFT (23u) +#define GPIO_PSR4_PSR424_SHIFT (24u) +#define GPIO_PSR4_PSR425_SHIFT (25u) +#define GPIO_PSR4_PSR426_SHIFT (26u) +#define GPIO_PSR4_PSR427_SHIFT (27u) +#define GPIO_PSR4_PSR428_SHIFT (28u) +#define GPIO_PSR4_PSR429_SHIFT (29u) +#define GPIO_PSR4_PSR430_SHIFT (30u) +#define GPIO_PSR4_PSR431_SHIFT (31u) + +#define GPIO_PPR4_PPR40_SHIFT (0u) +#define GPIO_PPR4_PPR41_SHIFT (1u) +#define GPIO_PPR4_PPR42_SHIFT (2u) +#define GPIO_PPR4_PPR43_SHIFT (3u) +#define GPIO_PPR4_PPR44_SHIFT (4u) +#define GPIO_PPR4_PPR45_SHIFT (5u) +#define GPIO_PPR4_PPR46_SHIFT (6u) +#define GPIO_PPR4_PPR47_SHIFT (7u) +#define GPIO_PPR4_PPR48_SHIFT (8u) +#define GPIO_PPR4_PPR49_SHIFT (9u) +#define GPIO_PPR4_PPR410_SHIFT (10u) +#define GPIO_PPR4_PPR411_SHIFT (11u) +#define GPIO_PPR4_PPR412_SHIFT (12u) +#define GPIO_PPR4_PPR413_SHIFT (13u) +#define GPIO_PPR4_PPR414_SHIFT (14u) +#define GPIO_PPR4_PPR415_SHIFT (15u) + +#define GPIO_PM4_PM40_SHIFT (0u) +#define GPIO_PM4_PM41_SHIFT (1u) +#define GPIO_PM4_PM42_SHIFT (2u) +#define GPIO_PM4_PM43_SHIFT (3u) +#define GPIO_PM4_PM44_SHIFT (4u) +#define GPIO_PM4_PM45_SHIFT (5u) +#define GPIO_PM4_PM46_SHIFT (6u) +#define GPIO_PM4_PM47_SHIFT (7u) +#define GPIO_PM4_PM48_SHIFT (8u) +#define GPIO_PM4_PM49_SHIFT (9u) +#define GPIO_PM4_PM410_SHIFT (10u) +#define GPIO_PM4_PM411_SHIFT (11u) +#define GPIO_PM4_PM412_SHIFT (12u) +#define GPIO_PM4_PM413_SHIFT (13u) +#define GPIO_PM4_PM414_SHIFT (14u) +#define GPIO_PM4_PM415_SHIFT (15u) + +#define GPIO_PMC4_PMC40_SHIFT (0u) +#define GPIO_PMC4_PMC41_SHIFT (1u) +#define GPIO_PMC4_PMC42_SHIFT (2u) +#define GPIO_PMC4_PMC43_SHIFT (3u) +#define GPIO_PMC4_PMC44_SHIFT (4u) +#define GPIO_PMC4_PMC45_SHIFT (5u) +#define GPIO_PMC4_PMC46_SHIFT (6u) +#define GPIO_PMC4_PMC47_SHIFT (7u) +#define GPIO_PMC4_PMC48_SHIFT (8u) +#define GPIO_PMC4_PMC49_SHIFT (9u) +#define GPIO_PMC4_PMC410_SHIFT (10u) +#define GPIO_PMC4_PMC411_SHIFT (11u) +#define GPIO_PMC4_PMC412_SHIFT (12u) +#define GPIO_PMC4_PMC413_SHIFT (13u) +#define GPIO_PMC4_PMC414_SHIFT (14u) +#define GPIO_PMC4_PMC415_SHIFT (15u) + +#define GPIO_PFC4_PFC40_SHIFT (0u) +#define GPIO_PFC4_PFC41_SHIFT (1u) +#define GPIO_PFC4_PFC42_SHIFT (2u) +#define GPIO_PFC4_PFC43_SHIFT (3u) +#define GPIO_PFC4_PFC44_SHIFT (4u) +#define GPIO_PFC4_PFC45_SHIFT (5u) +#define GPIO_PFC4_PFC46_SHIFT (6u) +#define GPIO_PFC4_PFC47_SHIFT (7u) +#define GPIO_PFC4_PFC48_SHIFT (8u) +#define GPIO_PFC4_PFC49_SHIFT (9u) +#define GPIO_PFC4_PFC410_SHIFT (10u) +#define GPIO_PFC4_PFC411_SHIFT (11u) +#define GPIO_PFC4_PFC412_SHIFT (12u) +#define GPIO_PFC4_PFC413_SHIFT (13u) +#define GPIO_PFC4_PFC414_SHIFT (14u) +#define GPIO_PFC4_PFC415_SHIFT (15u) + +#define GPIO_PFCE4_PFCE40_SHIFT (0u) +#define GPIO_PFCE4_PFCE41_SHIFT (1u) +#define GPIO_PFCE4_PFCE42_SHIFT (2u) +#define GPIO_PFCE4_PFCE43_SHIFT (3u) +#define GPIO_PFCE4_PFCE44_SHIFT (4u) +#define GPIO_PFCE4_PFCE45_SHIFT (5u) +#define GPIO_PFCE4_PFCE46_SHIFT (6u) +#define GPIO_PFCE4_PFCE47_SHIFT (7u) +#define GPIO_PFCE4_PFCE48_SHIFT (8u) +#define GPIO_PFCE4_PFCE49_SHIFT (9u) +#define GPIO_PFCE4_PFCE410_SHIFT (10u) +#define GPIO_PFCE4_PFCE411_SHIFT (11u) +#define GPIO_PFCE4_PFCE412_SHIFT (12u) +#define GPIO_PFCE4_PFCE413_SHIFT (13u) +#define GPIO_PFCE4_PFCE414_SHIFT (14u) +#define GPIO_PFCE4_PFCE415_SHIFT (15u) + +#define GPIO_PNOT4_PNOT40_SHIFT (0u) +#define GPIO_PNOT4_PNOT41_SHIFT (1u) +#define GPIO_PNOT4_PNOT42_SHIFT (2u) +#define GPIO_PNOT4_PNOT43_SHIFT (3u) +#define GPIO_PNOT4_PNOT44_SHIFT (4u) +#define GPIO_PNOT4_PNOT45_SHIFT (5u) +#define GPIO_PNOT4_PNOT46_SHIFT (6u) +#define GPIO_PNOT4_PNOT47_SHIFT (7u) +#define GPIO_PNOT4_PNOT48_SHIFT (8u) +#define GPIO_PNOT4_PNOT49_SHIFT (9u) +#define GPIO_PNOT4_PNOT410_SHIFT (10u) +#define GPIO_PNOT4_PNOT411_SHIFT (11u) +#define GPIO_PNOT4_PNOT412_SHIFT (12u) +#define GPIO_PNOT4_PNOT413_SHIFT (13u) +#define GPIO_PNOT4_PNOT414_SHIFT (14u) +#define GPIO_PNOT4_PNOT415_SHIFT (15u) + +#define GPIO_PMSR4_PMSR40_SHIFT (0u) +#define GPIO_PMSR4_PMSR41_SHIFT (1u) +#define GPIO_PMSR4_PMSR42_SHIFT (2u) +#define GPIO_PMSR4_PMSR43_SHIFT (3u) +#define GPIO_PMSR4_PMSR44_SHIFT (4u) +#define GPIO_PMSR4_PMSR45_SHIFT (5u) +#define GPIO_PMSR4_PMSR46_SHIFT (6u) +#define GPIO_PMSR4_PMSR47_SHIFT (7u) +#define GPIO_PMSR4_PMSR48_SHIFT (8u) +#define GPIO_PMSR4_PMSR49_SHIFT (9u) +#define GPIO_PMSR4_PMSR410_SHIFT (10u) +#define GPIO_PMSR4_PMSR411_SHIFT (11u) +#define GPIO_PMSR4_PMSR412_SHIFT (12u) +#define GPIO_PMSR4_PMSR413_SHIFT (13u) +#define GPIO_PMSR4_PMSR414_SHIFT (14u) +#define GPIO_PMSR4_PMSR415_SHIFT (15u) +#define GPIO_PMSR4_PMSR416_SHIFT (16u) +#define GPIO_PMSR4_PMSR417_SHIFT (17u) +#define GPIO_PMSR4_PMSR418_SHIFT (18u) +#define GPIO_PMSR4_PMSR419_SHIFT (19u) +#define GPIO_PMSR4_PMSR420_SHIFT (20u) +#define GPIO_PMSR4_PMSR421_SHIFT (21u) +#define GPIO_PMSR4_PMSR422_SHIFT (22u) +#define GPIO_PMSR4_PMSR423_SHIFT (23u) +#define GPIO_PMSR4_PMSR424_SHIFT (24u) +#define GPIO_PMSR4_PMSR425_SHIFT (25u) +#define GPIO_PMSR4_PMSR426_SHIFT (26u) +#define GPIO_PMSR4_PMSR427_SHIFT (27u) +#define GPIO_PMSR4_PMSR428_SHIFT (28u) +#define GPIO_PMSR4_PMSR429_SHIFT (29u) +#define GPIO_PMSR4_PMSR430_SHIFT (30u) +#define GPIO_PMSR4_PMSR431_SHIFT (31u) + +#define GPIO_PMCSR4_PMCSR40_SHIFT (0u) +#define GPIO_PMCSR4_PMCSR41_SHIFT (1u) +#define GPIO_PMCSR4_PMCSR42_SHIFT (2u) +#define GPIO_PMCSR4_PMCSR43_SHIFT (3u) +#define GPIO_PMCSR4_PMCSR44_SHIFT (4u) +#define GPIO_PMCSR4_PMCSR45_SHIFT (5u) +#define GPIO_PMCSR4_PMCSR46_SHIFT (6u) +#define GPIO_PMCSR4_PMCSR47_SHIFT (7u) +#define GPIO_PMCSR4_PMCSR48_SHIFT (8u) +#define GPIO_PMCSR4_PMCSR49_SHIFT (9u) +#define GPIO_PMCSR4_PMCSR410_SHIFT (10u) +#define GPIO_PMCSR4_PMCSR411_SHIFT (11u) +#define GPIO_PMCSR4_PMCSR412_SHIFT (12u) +#define GPIO_PMCSR4_PMCSR413_SHIFT (13u) +#define GPIO_PMCSR4_PMCSR414_SHIFT (14u) +#define GPIO_PMCSR4_PMCSR415_SHIFT (15u) +#define GPIO_PMCSR4_PMCSR416_SHIFT (16u) +#define GPIO_PMCSR4_PMCSR417_SHIFT (17u) +#define GPIO_PMCSR4_PMCSR418_SHIFT (18u) +#define GPIO_PMCSR4_PMCSR419_SHIFT (19u) +#define GPIO_PMCSR4_PMCSR420_SHIFT (20u) +#define GPIO_PMCSR4_PMCSR421_SHIFT (21u) +#define GPIO_PMCSR4_PMCSR422_SHIFT (22u) +#define GPIO_PMCSR4_PMCSR423_SHIFT (23u) +#define GPIO_PMCSR4_PMCSR424_SHIFT (24u) +#define GPIO_PMCSR4_PMCSR425_SHIFT (25u) +#define GPIO_PMCSR4_PMCSR426_SHIFT (26u) +#define GPIO_PMCSR4_PMCSR427_SHIFT (27u) +#define GPIO_PMCSR4_PMCSR428_SHIFT (28u) +#define GPIO_PMCSR4_PMCSR429_SHIFT (29u) +#define GPIO_PMCSR4_PMCSR430_SHIFT (30u) +#define GPIO_PMCSR4_PMCSR431_SHIFT (31u) + +#define GPIO_PFCAE4_PFCAE40_SHIFT (0u) +#define GPIO_PFCAE4_PFCAE41_SHIFT (1u) +#define GPIO_PFCAE4_PFCAE42_SHIFT (2u) +#define GPIO_PFCAE4_PFCAE43_SHIFT (3u) +#define GPIO_PFCAE4_PFCAE44_SHIFT (4u) +#define GPIO_PFCAE4_PFCAE45_SHIFT (5u) +#define GPIO_PFCAE4_PFCAE46_SHIFT (6u) +#define GPIO_PFCAE4_PFCAE47_SHIFT (7u) +#define GPIO_PFCAE4_PFCAE48_SHIFT (8u) +#define GPIO_PFCAE4_PFCAE49_SHIFT (9u) +#define GPIO_PFCAE4_PFCAE410_SHIFT (10u) +#define GPIO_PFCAE4_PFCAE411_SHIFT (11u) +#define GPIO_PFCAE4_PFCAE412_SHIFT (12u) +#define GPIO_PFCAE4_PFCAE413_SHIFT (13u) +#define GPIO_PFCAE4_PFCAE414_SHIFT (14u) +#define GPIO_PFCAE4_PFCAE415_SHIFT (15u) + +#define GPIO_PIBC4_PIBC40_SHIFT (0u) +#define GPIO_PIBC4_PIBC41_SHIFT (1u) +#define GPIO_PIBC4_PIBC42_SHIFT (2u) +#define GPIO_PIBC4_PIBC43_SHIFT (3u) +#define GPIO_PIBC4_PIBC44_SHIFT (4u) +#define GPIO_PIBC4_PIBC45_SHIFT (5u) +#define GPIO_PIBC4_PIBC46_SHIFT (6u) +#define GPIO_PIBC4_PIBC47_SHIFT (7u) +#define GPIO_PIBC4_PIBC48_SHIFT (8u) +#define GPIO_PIBC4_PIBC49_SHIFT (9u) +#define GPIO_PIBC4_PIBC410_SHIFT (10u) +#define GPIO_PIBC4_PIBC411_SHIFT (11u) +#define GPIO_PIBC4_PIBC412_SHIFT (12u) +#define GPIO_PIBC4_PIBC413_SHIFT (13u) +#define GPIO_PIBC4_PIBC414_SHIFT (14u) +#define GPIO_PIBC4_PIBC415_SHIFT (15u) + +#define GPIO_PBDC4_PBDC40_SHIFT (0u) +#define GPIO_PBDC4_PBDC41_SHIFT (1u) +#define GPIO_PBDC4_PBDC42_SHIFT (2u) +#define GPIO_PBDC4_PBDC43_SHIFT (3u) +#define GPIO_PBDC4_PBDC44_SHIFT (4u) +#define GPIO_PBDC4_PBDC45_SHIFT (5u) +#define GPIO_PBDC4_PBDC46_SHIFT (6u) +#define GPIO_PBDC4_PBDC47_SHIFT (7u) +#define GPIO_PBDC4_PBDC48_SHIFT (8u) +#define GPIO_PBDC4_PBDC49_SHIFT (9u) +#define GPIO_PBDC4_PBDC410_SHIFT (10u) +#define GPIO_PBDC4_PBDC411_SHIFT (11u) +#define GPIO_PBDC4_PBDC412_SHIFT (12u) +#define GPIO_PBDC4_PBDC413_SHIFT (13u) +#define GPIO_PBDC4_PBDC414_SHIFT (14u) +#define GPIO_PBDC4_PBDC415_SHIFT (15u) + +#define GPIO_PIPC4_PIPC40_SHIFT (0u) +#define GPIO_PIPC4_PIPC41_SHIFT (1u) +#define GPIO_PIPC4_PIPC42_SHIFT (2u) +#define GPIO_PIPC4_PIPC43_SHIFT (3u) +#define GPIO_PIPC4_PIPC44_SHIFT (4u) +#define GPIO_PIPC4_PIPC45_SHIFT (5u) +#define GPIO_PIPC4_PIPC46_SHIFT (6u) +#define GPIO_PIPC4_PIPC47_SHIFT (7u) +#define GPIO_PIPC4_PIPC48_SHIFT (8u) +#define GPIO_PIPC4_PIPC49_SHIFT (9u) +#define GPIO_PIPC4_PIPC410_SHIFT (10u) +#define GPIO_PIPC4_PIPC411_SHIFT (11u) +#define GPIO_PIPC4_PIPC412_SHIFT (12u) +#define GPIO_PIPC4_PIPC413_SHIFT (13u) +#define GPIO_PIPC4_PIPC414_SHIFT (14u) +#define GPIO_PIPC4_PIPC415_SHIFT (15u) + +/* ---- P5 ---- */ +#define GPIO_P5_P50_SHIFT (0u) +#define GPIO_P5_P51_SHIFT (1u) +#define GPIO_P5_P52_SHIFT (2u) +#define GPIO_P5_P53_SHIFT (3u) +#define GPIO_P5_P54_SHIFT (4u) +#define GPIO_P5_P55_SHIFT (5u) +#define GPIO_P5_P56_SHIFT (6u) +#define GPIO_P5_P57_SHIFT (7u) +#define GPIO_P5_P58_SHIFT (8u) +#define GPIO_P5_P59_SHIFT (9u) +#define GPIO_P5_P510_SHIFT (10u) + +#define GPIO_PSR5_PSR50_SHIFT (0u) +#define GPIO_PSR5_PSR51_SHIFT (1u) +#define GPIO_PSR5_PSR52_SHIFT (2u) +#define GPIO_PSR5_PSR53_SHIFT (3u) +#define GPIO_PSR5_PSR54_SHIFT (4u) +#define GPIO_PSR5_PSR55_SHIFT (5u) +#define GPIO_PSR5_PSR56_SHIFT (6u) +#define GPIO_PSR5_PSR57_SHIFT (7u) +#define GPIO_PSR5_PSR58_SHIFT (8u) +#define GPIO_PSR5_PSR59_SHIFT (9u) +#define GPIO_PSR5_PSR510_SHIFT (10u) +#define GPIO_PSR5_PSR516_SHIFT (16u) +#define GPIO_PSR5_PSR517_SHIFT (17u) +#define GPIO_PSR5_PSR518_SHIFT (18u) +#define GPIO_PSR5_PSR519_SHIFT (19u) +#define GPIO_PSR5_PSR520_SHIFT (20u) +#define GPIO_PSR5_PSR521_SHIFT (21u) +#define GPIO_PSR5_PSR522_SHIFT (22u) +#define GPIO_PSR5_PSR523_SHIFT (23u) +#define GPIO_PSR5_PSR524_SHIFT (24u) +#define GPIO_PSR5_PSR525_SHIFT (25u) +#define GPIO_PSR5_PSR526_SHIFT (26u) + +#define GPIO_PPR5_PPR50_SHIFT (0u) +#define GPIO_PPR5_PPR51_SHIFT (1u) +#define GPIO_PPR5_PPR52_SHIFT (2u) +#define GPIO_PPR5_PPR53_SHIFT (3u) +#define GPIO_PPR5_PPR54_SHIFT (4u) +#define GPIO_PPR5_PPR55_SHIFT (5u) +#define GPIO_PPR5_PPR56_SHIFT (6u) +#define GPIO_PPR5_PPR57_SHIFT (7u) +#define GPIO_PPR5_PPR58_SHIFT (8u) +#define GPIO_PPR5_PPR59_SHIFT (9u) +#define GPIO_PPR5_PPR510_SHIFT (10u) + +#define GPIO_PM5_PM50_SHIFT (0u) +#define GPIO_PM5_PM51_SHIFT (1u) +#define GPIO_PM5_PM52_SHIFT (2u) +#define GPIO_PM5_PM53_SHIFT (3u) +#define GPIO_PM5_PM54_SHIFT (4u) +#define GPIO_PM5_PM55_SHIFT (5u) +#define GPIO_PM5_PM56_SHIFT (6u) +#define GPIO_PM5_PM57_SHIFT (7u) +#define GPIO_PM5_PM58_SHIFT (8u) +#define GPIO_PM5_PM59_SHIFT (9u) +#define GPIO_PM5_PM510_SHIFT (10u) + +#define GPIO_PMC5_PMC50_SHIFT (0u) +#define GPIO_PMC5_PMC51_SHIFT (1u) +#define GPIO_PMC5_PMC52_SHIFT (2u) +#define GPIO_PMC5_PMC53_SHIFT (3u) +#define GPIO_PMC5_PMC54_SHIFT (4u) +#define GPIO_PMC5_PMC55_SHIFT (5u) +#define GPIO_PMC5_PMC56_SHIFT (6u) +#define GPIO_PMC5_PMC57_SHIFT (7u) +#define GPIO_PMC5_PMC58_SHIFT (8u) +#define GPIO_PMC5_PMC59_SHIFT (9u) +#define GPIO_PMC5_PMC510_SHIFT (10u) + +#define GPIO_PFC5_PFC50_SHIFT (0u) +#define GPIO_PFC5_PFC51_SHIFT (1u) +#define GPIO_PFC5_PFC52_SHIFT (2u) +#define GPIO_PFC5_PFC53_SHIFT (3u) +#define GPIO_PFC5_PFC54_SHIFT (4u) +#define GPIO_PFC5_PFC55_SHIFT (5u) +#define GPIO_PFC5_PFC56_SHIFT (6u) +#define GPIO_PFC5_PFC57_SHIFT (7u) +#define GPIO_PFC5_PFC58_SHIFT (8u) +#define GPIO_PFC5_PFC59_SHIFT (9u) +#define GPIO_PFC5_PFC510_SHIFT (10u) + +#define GPIO_PFCE5_PFCE50_SHIFT (0u) +#define GPIO_PFCE5_PFCE51_SHIFT (1u) +#define GPIO_PFCE5_PFCE52_SHIFT (2u) +#define GPIO_PFCE5_PFCE53_SHIFT (3u) +#define GPIO_PFCE5_PFCE54_SHIFT (4u) +#define GPIO_PFCE5_PFCE55_SHIFT (5u) +#define GPIO_PFCE5_PFCE56_SHIFT (6u) +#define GPIO_PFCE5_PFCE57_SHIFT (7u) +#define GPIO_PFCE5_PFCE58_SHIFT (8u) +#define GPIO_PFCE5_PFCE59_SHIFT (9u) +#define GPIO_PFCE5_PFCE510_SHIFT (10u) + +#define GPIO_PNOT5_PNOT50_SHIFT (0u) +#define GPIO_PNOT5_PNOT51_SHIFT (1u) +#define GPIO_PNOT5_PNOT52_SHIFT (2u) +#define GPIO_PNOT5_PNOT53_SHIFT (3u) +#define GPIO_PNOT5_PNOT54_SHIFT (4u) +#define GPIO_PNOT5_PNOT55_SHIFT (5u) +#define GPIO_PNOT5_PNOT56_SHIFT (6u) +#define GPIO_PNOT5_PNOT57_SHIFT (7u) +#define GPIO_PNOT5_PNOT58_SHIFT (8u) +#define GPIO_PNOT5_PNOT59_SHIFT (9u) +#define GPIO_PNOT5_PNOT510_SHIFT (10u) + +#define GPIO_PMSR5_PMSR50_SHIFT (0u) +#define GPIO_PMSR5_PMSR51_SHIFT (1u) +#define GPIO_PMSR5_PMSR52_SHIFT (2u) +#define GPIO_PMSR5_PMSR53_SHIFT (3u) +#define GPIO_PMSR5_PMSR54_SHIFT (4u) +#define GPIO_PMSR5_PMSR55_SHIFT (5u) +#define GPIO_PMSR5_PMSR56_SHIFT (6u) +#define GPIO_PMSR5_PMSR57_SHIFT (7u) +#define GPIO_PMSR5_PMSR58_SHIFT (8u) +#define GPIO_PMSR5_PMSR59_SHIFT (9u) +#define GPIO_PMSR5_PMSR510_SHIFT (10u) +#define GPIO_PMSR5_PMSR516_SHIFT (16u) +#define GPIO_PMSR5_PMSR517_SHIFT (17u) +#define GPIO_PMSR5_PMSR518_SHIFT (18u) +#define GPIO_PMSR5_PMSR519_SHIFT (19u) +#define GPIO_PMSR5_PMSR520_SHIFT (20u) +#define GPIO_PMSR5_PMSR521_SHIFT (21u) +#define GPIO_PMSR5_PMSR522_SHIFT (22u) +#define GPIO_PMSR5_PMSR523_SHIFT (23u) +#define GPIO_PMSR5_PMSR524_SHIFT (24u) +#define GPIO_PMSR5_PMSR525_SHIFT (25u) +#define GPIO_PMSR5_PMSR526_SHIFT (26u) + +#define GPIO_PMCSR5_PMCSR50_SHIFT (0u) +#define GPIO_PMCSR5_PMCSR51_SHIFT (1u) +#define GPIO_PMCSR5_PMCSR52_SHIFT (2u) +#define GPIO_PMCSR5_PMCSR53_SHIFT (3u) +#define GPIO_PMCSR5_PMCSR54_SHIFT (4u) +#define GPIO_PMCSR5_PMCSR55_SHIFT (5u) +#define GPIO_PMCSR5_PMCSR56_SHIFT (6u) +#define GPIO_PMCSR5_PMCSR57_SHIFT (7u) +#define GPIO_PMCSR5_PMCSR58_SHIFT (8u) +#define GPIO_PMCSR5_PMCSR59_SHIFT (9u) +#define GPIO_PMCSR5_PMCSR510_SHIFT (10u) +#define GPIO_PMCSR5_PMCSR516_SHIFT (16u) +#define GPIO_PMCSR5_PMCSR517_SHIFT (17u) +#define GPIO_PMCSR5_PMCSR518_SHIFT (18u) +#define GPIO_PMCSR5_PMCSR519_SHIFT (19u) +#define GPIO_PMCSR5_PMCSR520_SHIFT (20u) +#define GPIO_PMCSR5_PMCSR521_SHIFT (21u) +#define GPIO_PMCSR5_PMCSR522_SHIFT (22u) +#define GPIO_PMCSR5_PMCSR523_SHIFT (23u) +#define GPIO_PMCSR5_PMCSR524_SHIFT (24u) +#define GPIO_PMCSR5_PMCSR525_SHIFT (25u) +#define GPIO_PMCSR5_PMCSR526_SHIFT (26u) + +#define GPIO_PFCAE5_PFCAE50_SHIFT (0u) +#define GPIO_PFCAE5_PFCAE51_SHIFT (1u) +#define GPIO_PFCAE5_PFCAE52_SHIFT (2u) +#define GPIO_PFCAE5_PFCAE53_SHIFT (3u) +#define GPIO_PFCAE5_PFCAE54_SHIFT (4u) +#define GPIO_PFCAE5_PFCAE55_SHIFT (5u) +#define GPIO_PFCAE5_PFCAE56_SHIFT (6u) +#define GPIO_PFCAE5_PFCAE57_SHIFT (7u) +#define GPIO_PFCAE5_PFCAE58_SHIFT (8u) +#define GPIO_PFCAE5_PFCAE59_SHIFT (9u) +#define GPIO_PFCAE5_PFCAE510_SHIFT (10u) + +#define GPIO_PIBC5_PIBC50_SHIFT (0u) +#define GPIO_PIBC5_PIBC51_SHIFT (1u) +#define GPIO_PIBC5_PIBC52_SHIFT (2u) +#define GPIO_PIBC5_PIBC53_SHIFT (3u) +#define GPIO_PIBC5_PIBC54_SHIFT (4u) +#define GPIO_PIBC5_PIBC55_SHIFT (5u) +#define GPIO_PIBC5_PIBC56_SHIFT (6u) +#define GPIO_PIBC5_PIBC57_SHIFT (7u) +#define GPIO_PIBC5_PIBC58_SHIFT (8u) +#define GPIO_PIBC5_PIBC59_SHIFT (9u) +#define GPIO_PIBC5_PIBC510_SHIFT (10u) + +#define GPIO_PBDC5_PBDC50_SHIFT (0u) +#define GPIO_PBDC5_PBDC51_SHIFT (1u) +#define GPIO_PBDC5_PBDC52_SHIFT (2u) +#define GPIO_PBDC5_PBDC53_SHIFT (3u) +#define GPIO_PBDC5_PBDC54_SHIFT (4u) +#define GPIO_PBDC5_PBDC55_SHIFT (5u) +#define GPIO_PBDC5_PBDC56_SHIFT (6u) +#define GPIO_PBDC5_PBDC57_SHIFT (7u) +#define GPIO_PBDC5_PBDC58_SHIFT (8u) +#define GPIO_PBDC5_PBDC59_SHIFT (9u) +#define GPIO_PBDC5_PBDC510_SHIFT (10u) + +#define GPIO_PIPC5_PIPC50_SHIFT (0u) +#define GPIO_PIPC5_PIPC51_SHIFT (1u) +#define GPIO_PIPC5_PIPC52_SHIFT (2u) +#define GPIO_PIPC5_PIPC53_SHIFT (3u) +#define GPIO_PIPC5_PIPC54_SHIFT (4u) +#define GPIO_PIPC5_PIPC55_SHIFT (5u) +#define GPIO_PIPC5_PIPC56_SHIFT (6u) +#define GPIO_PIPC5_PIPC57_SHIFT (7u) +#define GPIO_PIPC5_PIPC58_SHIFT (8u) +#define GPIO_PIPC5_PIPC59_SHIFT (9u) +#define GPIO_PIPC5_PIPC510_SHIFT (10u) + +/* ---- P6 ---- */ +#define GPIO_P6_P60_SHIFT (0u) +#define GPIO_P6_P61_SHIFT (1u) +#define GPIO_P6_P62_SHIFT (2u) +#define GPIO_P6_P63_SHIFT (3u) +#define GPIO_P6_P64_SHIFT (4u) +#define GPIO_P6_P65_SHIFT (5u) +#define GPIO_P6_P66_SHIFT (6u) +#define GPIO_P6_P67_SHIFT (7u) +#define GPIO_P6_P68_SHIFT (8u) +#define GPIO_P6_P69_SHIFT (9u) +#define GPIO_P6_P610_SHIFT (10u) +#define GPIO_P6_P611_SHIFT (11u) +#define GPIO_P6_P612_SHIFT (12u) +#define GPIO_P6_P613_SHIFT (13u) +#define GPIO_P6_P614_SHIFT (14u) +#define GPIO_P6_P615_SHIFT (15u) + +#define GPIO_PSR6_PSR60_SHIFT (0u) +#define GPIO_PSR6_PSR61_SHIFT (1u) +#define GPIO_PSR6_PSR62_SHIFT (2u) +#define GPIO_PSR6_PSR63_SHIFT (3u) +#define GPIO_PSR6_PSR64_SHIFT (4u) +#define GPIO_PSR6_PSR65_SHIFT (5u) +#define GPIO_PSR6_PSR66_SHIFT (6u) +#define GPIO_PSR6_PSR67_SHIFT (7u) +#define GPIO_PSR6_PSR68_SHIFT (8u) +#define GPIO_PSR6_PSR69_SHIFT (9u) +#define GPIO_PSR6_PSR610_SHIFT (10u) +#define GPIO_PSR6_PSR611_SHIFT (11u) +#define GPIO_PSR6_PSR612_SHIFT (12u) +#define GPIO_PSR6_PSR613_SHIFT (13u) +#define GPIO_PSR6_PSR614_SHIFT (14u) +#define GPIO_PSR6_PSR615_SHIFT (15u) +#define GPIO_PSR6_PSR616_SHIFT (16u) +#define GPIO_PSR6_PSR617_SHIFT (17u) +#define GPIO_PSR6_PSR618_SHIFT (18u) +#define GPIO_PSR6_PSR619_SHIFT (19u) +#define GPIO_PSR6_PSR620_SHIFT (20u) +#define GPIO_PSR6_PSR621_SHIFT (21u) +#define GPIO_PSR6_PSR622_SHIFT (22u) +#define GPIO_PSR6_PSR623_SHIFT (23u) +#define GPIO_PSR6_PSR624_SHIFT (24u) +#define GPIO_PSR6_PSR625_SHIFT (25u) +#define GPIO_PSR6_PSR626_SHIFT (26u) +#define GPIO_PSR6_PSR627_SHIFT (27u) +#define GPIO_PSR6_PSR628_SHIFT (28u) +#define GPIO_PSR6_PSR629_SHIFT (29u) +#define GPIO_PSR6_PSR630_SHIFT (30u) +#define GPIO_PSR6_PSR631_SHIFT (31u) + +#define GPIO_PPR6_PPR60_SHIFT (0u) +#define GPIO_PPR6_PPR61_SHIFT (1u) +#define GPIO_PPR6_PPR62_SHIFT (2u) +#define GPIO_PPR6_PPR63_SHIFT (3u) +#define GPIO_PPR6_PPR64_SHIFT (4u) +#define GPIO_PPR6_PPR65_SHIFT (5u) +#define GPIO_PPR6_PPR66_SHIFT (6u) +#define GPIO_PPR6_PPR67_SHIFT (7u) +#define GPIO_PPR6_PPR68_SHIFT (8u) +#define GPIO_PPR6_PPR69_SHIFT (9u) +#define GPIO_PPR6_PPR610_SHIFT (10u) +#define GPIO_PPR6_PPR611_SHIFT (11u) +#define GPIO_PPR6_PPR612_SHIFT (12u) +#define GPIO_PPR6_PPR613_SHIFT (13u) +#define GPIO_PPR6_PPR614_SHIFT (14u) +#define GPIO_PPR6_PPR615_SHIFT (15u) + +#define GPIO_PM6_PM60_SHIFT (0u) +#define GPIO_PM6_PM61_SHIFT (1u) +#define GPIO_PM6_PM62_SHIFT (2u) +#define GPIO_PM6_PM63_SHIFT (3u) +#define GPIO_PM6_PM64_SHIFT (4u) +#define GPIO_PM6_PM65_SHIFT (5u) +#define GPIO_PM6_PM66_SHIFT (6u) +#define GPIO_PM6_PM67_SHIFT (7u) +#define GPIO_PM6_PM68_SHIFT (8u) +#define GPIO_PM6_PM69_SHIFT (9u) +#define GPIO_PM6_PM610_SHIFT (10u) +#define GPIO_PM6_PM611_SHIFT (11u) +#define GPIO_PM6_PM612_SHIFT (12u) +#define GPIO_PM6_PM613_SHIFT (13u) +#define GPIO_PM6_PM614_SHIFT (14u) +#define GPIO_PM6_PM615_SHIFT (15u) + +#define GPIO_PMC6_PMC60_SHIFT (0u) +#define GPIO_PMC6_PMC61_SHIFT (1u) +#define GPIO_PMC6_PMC62_SHIFT (2u) +#define GPIO_PMC6_PMC63_SHIFT (3u) +#define GPIO_PMC6_PMC64_SHIFT (4u) +#define GPIO_PMC6_PMC65_SHIFT (5u) +#define GPIO_PMC6_PMC66_SHIFT (6u) +#define GPIO_PMC6_PMC67_SHIFT (7u) +#define GPIO_PMC6_PMC68_SHIFT (8u) +#define GPIO_PMC6_PMC69_SHIFT (9u) +#define GPIO_PMC6_PMC610_SHIFT (10u) +#define GPIO_PMC6_PMC611_SHIFT (11u) +#define GPIO_PMC6_PMC612_SHIFT (12u) +#define GPIO_PMC6_PMC613_SHIFT (13u) +#define GPIO_PMC6_PMC614_SHIFT (14u) +#define GPIO_PMC6_PMC615_SHIFT (15u) + +#define GPIO_PFC6_PFC60_SHIFT (0u) +#define GPIO_PFC6_PFC61_SHIFT (1u) +#define GPIO_PFC6_PFC62_SHIFT (2u) +#define GPIO_PFC6_PFC63_SHIFT (3u) +#define GPIO_PFC6_PFC64_SHIFT (4u) +#define GPIO_PFC6_PFC65_SHIFT (5u) +#define GPIO_PFC6_PFC66_SHIFT (6u) +#define GPIO_PFC6_PFC67_SHIFT (7u) +#define GPIO_PFC6_PFC68_SHIFT (8u) +#define GPIO_PFC6_PFC69_SHIFT (9u) +#define GPIO_PFC6_PFC610_SHIFT (10u) +#define GPIO_PFC6_PFC611_SHIFT (11u) +#define GPIO_PFC6_PFC612_SHIFT (12u) +#define GPIO_PFC6_PFC613_SHIFT (13u) +#define GPIO_PFC6_PFC614_SHIFT (14u) +#define GPIO_PFC6_PFC615_SHIFT (15u) + +#define GPIO_PFCE6_PFCE60_SHIFT (0u) +#define GPIO_PFCE6_PFCE61_SHIFT (1u) +#define GPIO_PFCE6_PFCE62_SHIFT (2u) +#define GPIO_PFCE6_PFCE63_SHIFT (3u) +#define GPIO_PFCE6_PFCE64_SHIFT (4u) +#define GPIO_PFCE6_PFCE65_SHIFT (5u) +#define GPIO_PFCE6_PFCE66_SHIFT (6u) +#define GPIO_PFCE6_PFCE67_SHIFT (7u) +#define GPIO_PFCE6_PFCE68_SHIFT (8u) +#define GPIO_PFCE6_PFCE69_SHIFT (9u) +#define GPIO_PFCE6_PFCE610_SHIFT (10u) +#define GPIO_PFCE6_PFCE611_SHIFT (11u) +#define GPIO_PFCE6_PFCE612_SHIFT (12u) +#define GPIO_PFCE6_PFCE613_SHIFT (13u) +#define GPIO_PFCE6_PFCE614_SHIFT (14u) +#define GPIO_PFCE6_PFCE615_SHIFT (15u) + +#define GPIO_PNOT6_PNOT60_SHIFT (0u) +#define GPIO_PNOT6_PNOT61_SHIFT (1u) +#define GPIO_PNOT6_PNOT62_SHIFT (2u) +#define GPIO_PNOT6_PNOT63_SHIFT (3u) +#define GPIO_PNOT6_PNOT64_SHIFT (4u) +#define GPIO_PNOT6_PNOT65_SHIFT (5u) +#define GPIO_PNOT6_PNOT66_SHIFT (6u) +#define GPIO_PNOT6_PNOT67_SHIFT (7u) +#define GPIO_PNOT6_PNOT68_SHIFT (8u) +#define GPIO_PNOT6_PNOT69_SHIFT (9u) +#define GPIO_PNOT6_PNOT610_SHIFT (10u) +#define GPIO_PNOT6_PNOT611_SHIFT (11u) +#define GPIO_PNOT6_PNOT612_SHIFT (12u) +#define GPIO_PNOT6_PNOT613_SHIFT (13u) +#define GPIO_PNOT6_PNOT614_SHIFT (14u) +#define GPIO_PNOT6_PNOT615_SHIFT (15u) + +#define GPIO_PMSR6_PMSR60_SHIFT (0u) +#define GPIO_PMSR6_PMSR61_SHIFT (1u) +#define GPIO_PMSR6_PMSR62_SHIFT (2u) +#define GPIO_PMSR6_PMSR63_SHIFT (3u) +#define GPIO_PMSR6_PMSR64_SHIFT (4u) +#define GPIO_PMSR6_PMSR65_SHIFT (5u) +#define GPIO_PMSR6_PMSR66_SHIFT (6u) +#define GPIO_PMSR6_PMSR67_SHIFT (7u) +#define GPIO_PMSR6_PMSR68_SHIFT (8u) +#define GPIO_PMSR6_PMSR69_SHIFT (9u) +#define GPIO_PMSR6_PMSR610_SHIFT (10u) +#define GPIO_PMSR6_PMSR611_SHIFT (11u) +#define GPIO_PMSR6_PMSR612_SHIFT (12u) +#define GPIO_PMSR6_PMSR613_SHIFT (13u) +#define GPIO_PMSR6_PMSR614_SHIFT (14u) +#define GPIO_PMSR6_PMSR615_SHIFT (15u) +#define GPIO_PMSR6_PMSR616_SHIFT (16u) +#define GPIO_PMSR6_PMSR617_SHIFT (17u) +#define GPIO_PMSR6_PMSR618_SHIFT (18u) +#define GPIO_PMSR6_PMSR619_SHIFT (19u) +#define GPIO_PMSR6_PMSR620_SHIFT (20u) +#define GPIO_PMSR6_PMSR621_SHIFT (21u) +#define GPIO_PMSR6_PMSR622_SHIFT (22u) +#define GPIO_PMSR6_PMSR623_SHIFT (23u) +#define GPIO_PMSR6_PMSR624_SHIFT (24u) +#define GPIO_PMSR6_PMSR625_SHIFT (25u) +#define GPIO_PMSR6_PMSR626_SHIFT (26u) +#define GPIO_PMSR6_PMSR627_SHIFT (27u) +#define GPIO_PMSR6_PMSR628_SHIFT (28u) +#define GPIO_PMSR6_PMSR629_SHIFT (29u) +#define GPIO_PMSR6_PMSR630_SHIFT (30u) +#define GPIO_PMSR6_PMSR631_SHIFT (31u) + +#define GPIO_PMCSR6_PMCSR60_SHIFT (0u) +#define GPIO_PMCSR6_PMCSR61_SHIFT (1u) +#define GPIO_PMCSR6_PMCSR62_SHIFT (2u) +#define GPIO_PMCSR6_PMCSR63_SHIFT (3u) +#define GPIO_PMCSR6_PMCSR64_SHIFT (4u) +#define GPIO_PMCSR6_PMCSR65_SHIFT (5u) +#define GPIO_PMCSR6_PMCSR66_SHIFT (6u) +#define GPIO_PMCSR6_PMCSR67_SHIFT (7u) +#define GPIO_PMCSR6_PMCSR68_SHIFT (8u) +#define GPIO_PMCSR6_PMCSR69_SHIFT (9u) +#define GPIO_PMCSR6_PMCSR610_SHIFT (10u) +#define GPIO_PMCSR6_PMCSR611_SHIFT (11u) +#define GPIO_PMCSR6_PMCSR612_SHIFT (12u) +#define GPIO_PMCSR6_PMCSR613_SHIFT (13u) +#define GPIO_PMCSR6_PMCSR614_SHIFT (14u) +#define GPIO_PMCSR6_PMCSR615_SHIFT (15u) +#define GPIO_PMCSR6_PMCSR616_SHIFT (16u) +#define GPIO_PMCSR6_PMCSR617_SHIFT (17u) +#define GPIO_PMCSR6_PMCSR618_SHIFT (18u) +#define GPIO_PMCSR6_PMCSR619_SHIFT (19u) +#define GPIO_PMCSR6_PMCSR620_SHIFT (20u) +#define GPIO_PMCSR6_PMCSR621_SHIFT (21u) +#define GPIO_PMCSR6_PMCSR622_SHIFT (22u) +#define GPIO_PMCSR6_PMCSR623_SHIFT (23u) +#define GPIO_PMCSR6_PMCSR624_SHIFT (24u) +#define GPIO_PMCSR6_PMCSR625_SHIFT (25u) +#define GPIO_PMCSR6_PMCSR626_SHIFT (26u) +#define GPIO_PMCSR6_PMCSR627_SHIFT (27u) +#define GPIO_PMCSR6_PMCSR628_SHIFT (28u) +#define GPIO_PMCSR6_PMCSR629_SHIFT (29u) +#define GPIO_PMCSR6_PMCSR630_SHIFT (30u) +#define GPIO_PMCSR6_PMCSR631_SHIFT (31u) + +#define GPIO_PFCAE6_PFCAE60_SHIFT (0u) +#define GPIO_PFCAE6_PFCAE61_SHIFT (1u) +#define GPIO_PFCAE6_PFCAE62_SHIFT (2u) +#define GPIO_PFCAE6_PFCAE63_SHIFT (3u) +#define GPIO_PFCAE6_PFCAE64_SHIFT (4u) +#define GPIO_PFCAE6_PFCAE65_SHIFT (5u) +#define GPIO_PFCAE6_PFCAE66_SHIFT (6u) +#define GPIO_PFCAE6_PFCAE67_SHIFT (7u) +#define GPIO_PFCAE6_PFCAE68_SHIFT (8u) +#define GPIO_PFCAE6_PFCAE69_SHIFT (9u) +#define GPIO_PFCAE6_PFCAE610_SHIFT (10u) +#define GPIO_PFCAE6_PFCAE611_SHIFT (11u) +#define GPIO_PFCAE6_PFCAE612_SHIFT (12u) +#define GPIO_PFCAE6_PFCAE613_SHIFT (13u) +#define GPIO_PFCAE6_PFCAE614_SHIFT (14u) +#define GPIO_PFCAE6_PFCAE615_SHIFT (15u) + +#define GPIO_PIBC6_PIBC60_SHIFT (0u) +#define GPIO_PIBC6_PIBC61_SHIFT (1u) +#define GPIO_PIBC6_PIBC62_SHIFT (2u) +#define GPIO_PIBC6_PIBC63_SHIFT (3u) +#define GPIO_PIBC6_PIBC64_SHIFT (4u) +#define GPIO_PIBC6_PIBC65_SHIFT (5u) +#define GPIO_PIBC6_PIBC66_SHIFT (6u) +#define GPIO_PIBC6_PIBC67_SHIFT (7u) +#define GPIO_PIBC6_PIBC68_SHIFT (8u) +#define GPIO_PIBC6_PIBC69_SHIFT (9u) +#define GPIO_PIBC6_PIBC610_SHIFT (10u) +#define GPIO_PIBC6_PIBC611_SHIFT (11u) +#define GPIO_PIBC6_PIBC612_SHIFT (12u) +#define GPIO_PIBC6_PIBC613_SHIFT (13u) +#define GPIO_PIBC6_PIBC614_SHIFT (14u) +#define GPIO_PIBC6_PIBC615_SHIFT (15u) + +#define GPIO_PBDC6_PBDC60_SHIFT (0u) +#define GPIO_PBDC6_PBDC61_SHIFT (1u) +#define GPIO_PBDC6_PBDC62_SHIFT (2u) +#define GPIO_PBDC6_PBDC63_SHIFT (3u) +#define GPIO_PBDC6_PBDC64_SHIFT (4u) +#define GPIO_PBDC6_PBDC65_SHIFT (5u) +#define GPIO_PBDC6_PBDC66_SHIFT (6u) +#define GPIO_PBDC6_PBDC67_SHIFT (7u) +#define GPIO_PBDC6_PBDC68_SHIFT (8u) +#define GPIO_PBDC6_PBDC69_SHIFT (9u) +#define GPIO_PBDC6_PBDC610_SHIFT (10u) +#define GPIO_PBDC6_PBDC611_SHIFT (11u) +#define GPIO_PBDC6_PBDC612_SHIFT (12u) +#define GPIO_PBDC6_PBDC613_SHIFT (13u) +#define GPIO_PBDC6_PBDC614_SHIFT (14u) +#define GPIO_PBDC6_PBDC615_SHIFT (15u) + +#define GPIO_PIPC6_PIPC60_SHIFT (0u) +#define GPIO_PIPC6_PIPC61_SHIFT (1u) +#define GPIO_PIPC6_PIPC62_SHIFT (2u) +#define GPIO_PIPC6_PIPC63_SHIFT (3u) +#define GPIO_PIPC6_PIPC64_SHIFT (4u) +#define GPIO_PIPC6_PIPC65_SHIFT (5u) +#define GPIO_PIPC6_PIPC66_SHIFT (6u) +#define GPIO_PIPC6_PIPC67_SHIFT (7u) +#define GPIO_PIPC6_PIPC68_SHIFT (8u) +#define GPIO_PIPC6_PIPC69_SHIFT (9u) +#define GPIO_PIPC6_PIPC610_SHIFT (10u) +#define GPIO_PIPC6_PIPC611_SHIFT (11u) +#define GPIO_PIPC6_PIPC612_SHIFT (12u) +#define GPIO_PIPC6_PIPC613_SHIFT (13u) +#define GPIO_PIPC6_PIPC614_SHIFT (14u) +#define GPIO_PIPC6_PIPC615_SHIFT (15u) + +/* ---- P7 ---- */ +#define GPIO_P7_P70_SHIFT (0u) +#define GPIO_P7_P71_SHIFT (1u) +#define GPIO_P7_P72_SHIFT (2u) +#define GPIO_P7_P73_SHIFT (3u) +#define GPIO_P7_P74_SHIFT (4u) +#define GPIO_P7_P75_SHIFT (5u) +#define GPIO_P7_P76_SHIFT (6u) +#define GPIO_P7_P77_SHIFT (7u) +#define GPIO_P7_P78_SHIFT (8u) +#define GPIO_P7_P79_SHIFT (9u) +#define GPIO_P7_P710_SHIFT (10u) +#define GPIO_P7_P711_SHIFT (11u) +#define GPIO_P7_P712_SHIFT (12u) +#define GPIO_P7_P713_SHIFT (13u) +#define GPIO_P7_P714_SHIFT (14u) +#define GPIO_P7_P715_SHIFT (15u) + +#define GPIO_PSR7_PSR70_SHIFT (0u) +#define GPIO_PSR7_PSR71_SHIFT (1u) +#define GPIO_PSR7_PSR72_SHIFT (2u) +#define GPIO_PSR7_PSR73_SHIFT (3u) +#define GPIO_PSR7_PSR74_SHIFT (4u) +#define GPIO_PSR7_PSR75_SHIFT (5u) +#define GPIO_PSR7_PSR76_SHIFT (6u) +#define GPIO_PSR7_PSR77_SHIFT (7u) +#define GPIO_PSR7_PSR78_SHIFT (8u) +#define GPIO_PSR7_PSR79_SHIFT (9u) +#define GPIO_PSR7_PSR710_SHIFT (10u) +#define GPIO_PSR7_PSR711_SHIFT (11u) +#define GPIO_PSR7_PSR712_SHIFT (12u) +#define GPIO_PSR7_PSR713_SHIFT (13u) +#define GPIO_PSR7_PSR714_SHIFT (14u) +#define GPIO_PSR7_PSR715_SHIFT (15u) +#define GPIO_PSR7_PSR716_SHIFT (16u) +#define GPIO_PSR7_PSR717_SHIFT (17u) +#define GPIO_PSR7_PSR718_SHIFT (18u) +#define GPIO_PSR7_PSR719_SHIFT (19u) +#define GPIO_PSR7_PSR720_SHIFT (20u) +#define GPIO_PSR7_PSR721_SHIFT (21u) +#define GPIO_PSR7_PSR722_SHIFT (22u) +#define GPIO_PSR7_PSR723_SHIFT (23u) +#define GPIO_PSR7_PSR724_SHIFT (24u) +#define GPIO_PSR7_PSR725_SHIFT (25u) +#define GPIO_PSR7_PSR726_SHIFT (26u) +#define GPIO_PSR7_PSR727_SHIFT (27u) +#define GPIO_PSR7_PSR728_SHIFT (28u) +#define GPIO_PSR7_PSR729_SHIFT (29u) +#define GPIO_PSR7_PSR730_SHIFT (30u) +#define GPIO_PSR7_PSR731_SHIFT (31u) + +#define GPIO_PPR7_PPR70_SHIFT (0u) +#define GPIO_PPR7_PPR71_SHIFT (1u) +#define GPIO_PPR7_PPR72_SHIFT (2u) +#define GPIO_PPR7_PPR73_SHIFT (3u) +#define GPIO_PPR7_PPR74_SHIFT (4u) +#define GPIO_PPR7_PPR75_SHIFT (5u) +#define GPIO_PPR7_PPR76_SHIFT (6u) +#define GPIO_PPR7_PPR77_SHIFT (7u) +#define GPIO_PPR7_PPR78_SHIFT (8u) +#define GPIO_PPR7_PPR79_SHIFT (9u) +#define GPIO_PPR7_PPR710_SHIFT (10u) +#define GPIO_PPR7_PPR711_SHIFT (11u) +#define GPIO_PPR7_PPR712_SHIFT (12u) +#define GPIO_PPR7_PPR713_SHIFT (13u) +#define GPIO_PPR7_PPR714_SHIFT (14u) +#define GPIO_PPR7_PPR715_SHIFT (15u) + +#define GPIO_PM7_PM70_SHIFT (0u) +#define GPIO_PM7_PM71_SHIFT (1u) +#define GPIO_PM7_PM72_SHIFT (2u) +#define GPIO_PM7_PM73_SHIFT (3u) +#define GPIO_PM7_PM74_SHIFT (4u) +#define GPIO_PM7_PM75_SHIFT (5u) +#define GPIO_PM7_PM76_SHIFT (6u) +#define GPIO_PM7_PM77_SHIFT (7u) +#define GPIO_PM7_PM78_SHIFT (8u) +#define GPIO_PM7_PM79_SHIFT (9u) +#define GPIO_PM7_PM710_SHIFT (10u) +#define GPIO_PM7_PM711_SHIFT (11u) +#define GPIO_PM7_PM712_SHIFT (12u) +#define GPIO_PM7_PM713_SHIFT (13u) +#define GPIO_PM7_PM714_SHIFT (14u) +#define GPIO_PM7_PM715_SHIFT (15u) + +#define GPIO_PMC7_PMC70_SHIFT (0u) +#define GPIO_PMC7_PMC71_SHIFT (1u) +#define GPIO_PMC7_PMC72_SHIFT (2u) +#define GPIO_PMC7_PMC73_SHIFT (3u) +#define GPIO_PMC7_PMC74_SHIFT (4u) +#define GPIO_PMC7_PMC75_SHIFT (5u) +#define GPIO_PMC7_PMC76_SHIFT (6u) +#define GPIO_PMC7_PMC77_SHIFT (7u) +#define GPIO_PMC7_PMC78_SHIFT (8u) +#define GPIO_PMC7_PMC79_SHIFT (9u) +#define GPIO_PMC7_PMC710_SHIFT (10u) +#define GPIO_PMC7_PMC711_SHIFT (11u) +#define GPIO_PMC7_PMC712_SHIFT (12u) +#define GPIO_PMC7_PMC713_SHIFT (13u) +#define GPIO_PMC7_PMC714_SHIFT (14u) +#define GPIO_PMC7_PMC715_SHIFT (15u) + +#define GPIO_PFC7_PFC70_SHIFT (0u) +#define GPIO_PFC7_PFC71_SHIFT (1u) +#define GPIO_PFC7_PFC72_SHIFT (2u) +#define GPIO_PFC7_PFC73_SHIFT (3u) +#define GPIO_PFC7_PFC74_SHIFT (4u) +#define GPIO_PFC7_PFC75_SHIFT (5u) +#define GPIO_PFC7_PFC76_SHIFT (6u) +#define GPIO_PFC7_PFC77_SHIFT (7u) +#define GPIO_PFC7_PFC78_SHIFT (8u) +#define GPIO_PFC7_PFC79_SHIFT (9u) +#define GPIO_PFC7_PFC710_SHIFT (10u) +#define GPIO_PFC7_PFC711_SHIFT (11u) +#define GPIO_PFC7_PFC712_SHIFT (12u) +#define GPIO_PFC7_PFC713_SHIFT (13u) +#define GPIO_PFC7_PFC714_SHIFT (14u) +#define GPIO_PFC7_PFC715_SHIFT (15u) + +#define GPIO_PFCE7_PFCE70_SHIFT (0u) +#define GPIO_PFCE7_PFCE71_SHIFT (1u) +#define GPIO_PFCE7_PFCE72_SHIFT (2u) +#define GPIO_PFCE7_PFCE73_SHIFT (3u) +#define GPIO_PFCE7_PFCE74_SHIFT (4u) +#define GPIO_PFCE7_PFCE75_SHIFT (5u) +#define GPIO_PFCE7_PFCE76_SHIFT (6u) +#define GPIO_PFCE7_PFCE77_SHIFT (7u) +#define GPIO_PFCE7_PFCE78_SHIFT (8u) +#define GPIO_PFCE7_PFCE79_SHIFT (9u) +#define GPIO_PFCE7_PFCE710_SHIFT (10u) +#define GPIO_PFCE7_PFCE711_SHIFT (11u) +#define GPIO_PFCE7_PFCE712_SHIFT (12u) +#define GPIO_PFCE7_PFCE713_SHIFT (13u) +#define GPIO_PFCE7_PFCE714_SHIFT (14u) +#define GPIO_PFCE7_PFCE715_SHIFT (15u) + +#define GPIO_PNOT7_PNOT70_SHIFT (0u) +#define GPIO_PNOT7_PNOT71_SHIFT (1u) +#define GPIO_PNOT7_PNOT72_SHIFT (2u) +#define GPIO_PNOT7_PNOT73_SHIFT (3u) +#define GPIO_PNOT7_PNOT74_SHIFT (4u) +#define GPIO_PNOT7_PNOT75_SHIFT (5u) +#define GPIO_PNOT7_PNOT76_SHIFT (6u) +#define GPIO_PNOT7_PNOT77_SHIFT (7u) +#define GPIO_PNOT7_PNOT78_SHIFT (8u) +#define GPIO_PNOT7_PNOT79_SHIFT (9u) +#define GPIO_PNOT7_PNOT710_SHIFT (10u) +#define GPIO_PNOT7_PNOT711_SHIFT (11u) +#define GPIO_PNOT7_PNOT712_SHIFT (12u) +#define GPIO_PNOT7_PNOT713_SHIFT (13u) +#define GPIO_PNOT7_PNOT714_SHIFT (14u) +#define GPIO_PNOT7_PNOT715_SHIFT (15u) + +#define GPIO_PMSR7_PMSR70_SHIFT (0u) +#define GPIO_PMSR7_PMSR71_SHIFT (1u) +#define GPIO_PMSR7_PMSR72_SHIFT (2u) +#define GPIO_PMSR7_PMSR73_SHIFT (3u) +#define GPIO_PMSR7_PMSR74_SHIFT (4u) +#define GPIO_PMSR7_PMSR75_SHIFT (5u) +#define GPIO_PMSR7_PMSR76_SHIFT (6u) +#define GPIO_PMSR7_PMSR77_SHIFT (7u) +#define GPIO_PMSR7_PMSR78_SHIFT (8u) +#define GPIO_PMSR7_PMSR79_SHIFT (9u) +#define GPIO_PMSR7_PMSR710_SHIFT (10u) +#define GPIO_PMSR7_PMSR711_SHIFT (11u) +#define GPIO_PMSR7_PMSR712_SHIFT (12u) +#define GPIO_PMSR7_PMSR713_SHIFT (13u) +#define GPIO_PMSR7_PMSR714_SHIFT (14u) +#define GPIO_PMSR7_PMSR715_SHIFT (15u) +#define GPIO_PMSR7_PMSR716_SHIFT (16u) +#define GPIO_PMSR7_PMSR717_SHIFT (17u) +#define GPIO_PMSR7_PMSR718_SHIFT (18u) +#define GPIO_PMSR7_PMSR719_SHIFT (19u) +#define GPIO_PMSR7_PMSR720_SHIFT (20u) +#define GPIO_PMSR7_PMSR721_SHIFT (21u) +#define GPIO_PMSR7_PMSR722_SHIFT (22u) +#define GPIO_PMSR7_PMSR723_SHIFT (23u) +#define GPIO_PMSR7_PMSR724_SHIFT (24u) +#define GPIO_PMSR7_PMSR725_SHIFT (25u) +#define GPIO_PMSR7_PMSR726_SHIFT (26u) +#define GPIO_PMSR7_PMSR727_SHIFT (27u) +#define GPIO_PMSR7_PMSR728_SHIFT (28u) +#define GPIO_PMSR7_PMSR729_SHIFT (29u) +#define GPIO_PMSR7_PMSR730_SHIFT (30u) +#define GPIO_PMSR7_PMSR731_SHIFT (31u) + +#define GPIO_PMCSR7_PMCSR70_SHIFT (0u) +#define GPIO_PMCSR7_PMCSR71_SHIFT (1u) +#define GPIO_PMCSR7_PMCSR72_SHIFT (2u) +#define GPIO_PMCSR7_PMCSR73_SHIFT (3u) +#define GPIO_PMCSR7_PMCSR74_SHIFT (4u) +#define GPIO_PMCSR7_PMCSR75_SHIFT (5u) +#define GPIO_PMCSR7_PMCSR76_SHIFT (6u) +#define GPIO_PMCSR7_PMCSR77_SHIFT (7u) +#define GPIO_PMCSR7_PMCSR78_SHIFT (8u) +#define GPIO_PMCSR7_PMCSR79_SHIFT (9u) +#define GPIO_PMCSR7_PMCSR710_SHIFT (10u) +#define GPIO_PMCSR7_PMCSR711_SHIFT (11u) +#define GPIO_PMCSR7_PMCSR712_SHIFT (12u) +#define GPIO_PMCSR7_PMCSR713_SHIFT (13u) +#define GPIO_PMCSR7_PMCSR714_SHIFT (14u) +#define GPIO_PMCSR7_PMCSR715_SHIFT (15u) +#define GPIO_PMCSR7_PMCSR716_SHIFT (16u) +#define GPIO_PMCSR7_PMCSR717_SHIFT (17u) +#define GPIO_PMCSR7_PMCSR718_SHIFT (18u) +#define GPIO_PMCSR7_PMCSR719_SHIFT (19u) +#define GPIO_PMCSR7_PMCSR720_SHIFT (20u) +#define GPIO_PMCSR7_PMCSR721_SHIFT (21u) +#define GPIO_PMCSR7_PMCSR722_SHIFT (22u) +#define GPIO_PMCSR7_PMCSR723_SHIFT (23u) +#define GPIO_PMCSR7_PMCSR724_SHIFT (24u) +#define GPIO_PMCSR7_PMCSR725_SHIFT (25u) +#define GPIO_PMCSR7_PMCSR726_SHIFT (26u) +#define GPIO_PMCSR7_PMCSR727_SHIFT (27u) +#define GPIO_PMCSR7_PMCSR728_SHIFT (28u) +#define GPIO_PMCSR7_PMCSR729_SHIFT (29u) +#define GPIO_PMCSR7_PMCSR730_SHIFT (30u) +#define GPIO_PMCSR7_PMCSR731_SHIFT (31u) + +#define GPIO_PFCAE7_PFCAE70_SHIFT (0u) +#define GPIO_PFCAE7_PFCAE71_SHIFT (1u) +#define GPIO_PFCAE7_PFCAE72_SHIFT (2u) +#define GPIO_PFCAE7_PFCAE73_SHIFT (3u) +#define GPIO_PFCAE7_PFCAE74_SHIFT (4u) +#define GPIO_PFCAE7_PFCAE75_SHIFT (5u) +#define GPIO_PFCAE7_PFCAE76_SHIFT (6u) +#define GPIO_PFCAE7_PFCAE77_SHIFT (7u) +#define GPIO_PFCAE7_PFCAE78_SHIFT (8u) +#define GPIO_PFCAE7_PFCAE79_SHIFT (9u) +#define GPIO_PFCAE7_PFCAE710_SHIFT (10u) +#define GPIO_PFCAE7_PFCAE711_SHIFT (11u) +#define GPIO_PFCAE7_PFCAE712_SHIFT (12u) +#define GPIO_PFCAE7_PFCAE713_SHIFT (13u) +#define GPIO_PFCAE7_PFCAE714_SHIFT (14u) +#define GPIO_PFCAE7_PFCAE715_SHIFT (15u) + +#define GPIO_PIBC7_PIBC70_SHIFT (0u) +#define GPIO_PIBC7_PIBC71_SHIFT (1u) +#define GPIO_PIBC7_PIBC72_SHIFT (2u) +#define GPIO_PIBC7_PIBC73_SHIFT (3u) +#define GPIO_PIBC7_PIBC74_SHIFT (4u) +#define GPIO_PIBC7_PIBC75_SHIFT (5u) +#define GPIO_PIBC7_PIBC76_SHIFT (6u) +#define GPIO_PIBC7_PIBC77_SHIFT (7u) +#define GPIO_PIBC7_PIBC78_SHIFT (8u) +#define GPIO_PIBC7_PIBC79_SHIFT (9u) +#define GPIO_PIBC7_PIBC710_SHIFT (10u) +#define GPIO_PIBC7_PIBC711_SHIFT (11u) +#define GPIO_PIBC7_PIBC712_SHIFT (12u) +#define GPIO_PIBC7_PIBC713_SHIFT (13u) +#define GPIO_PIBC7_PIBC714_SHIFT (14u) +#define GPIO_PIBC7_PIBC715_SHIFT (15u) + +#define GPIO_PBDC7_PBDC70_SHIFT (0u) +#define GPIO_PBDC7_PBDC71_SHIFT (1u) +#define GPIO_PBDC7_PBDC72_SHIFT (2u) +#define GPIO_PBDC7_PBDC73_SHIFT (3u) +#define GPIO_PBDC7_PBDC74_SHIFT (4u) +#define GPIO_PBDC7_PBDC75_SHIFT (5u) +#define GPIO_PBDC7_PBDC76_SHIFT (6u) +#define GPIO_PBDC7_PBDC77_SHIFT (7u) +#define GPIO_PBDC7_PBDC78_SHIFT (8u) +#define GPIO_PBDC7_PBDC79_SHIFT (9u) +#define GPIO_PBDC7_PBDC710_SHIFT (10u) +#define GPIO_PBDC7_PBDC711_SHIFT (11u) +#define GPIO_PBDC7_PBDC712_SHIFT (12u) +#define GPIO_PBDC7_PBDC713_SHIFT (13u) +#define GPIO_PBDC7_PBDC714_SHIFT (14u) +#define GPIO_PBDC7_PBDC715_SHIFT (15u) + +#define GPIO_PIPC7_PIPC70_SHIFT (0u) +#define GPIO_PIPC7_PIPC71_SHIFT (1u) +#define GPIO_PIPC7_PIPC72_SHIFT (2u) +#define GPIO_PIPC7_PIPC73_SHIFT (3u) +#define GPIO_PIPC7_PIPC74_SHIFT (4u) +#define GPIO_PIPC7_PIPC75_SHIFT (5u) +#define GPIO_PIPC7_PIPC76_SHIFT (6u) +#define GPIO_PIPC7_PIPC77_SHIFT (7u) +#define GPIO_PIPC7_PIPC78_SHIFT (8u) +#define GPIO_PIPC7_PIPC79_SHIFT (9u) +#define GPIO_PIPC7_PIPC710_SHIFT (10u) +#define GPIO_PIPC7_PIPC711_SHIFT (11u) +#define GPIO_PIPC7_PIPC712_SHIFT (12u) +#define GPIO_PIPC7_PIPC713_SHIFT (13u) +#define GPIO_PIPC7_PIPC714_SHIFT (14u) +#define GPIO_PIPC7_PIPC715_SHIFT (15u) + +/* ---- P8 ---- */ +#define GPIO_P8_P80_SHIFT (0u) +#define GPIO_P8_P81_SHIFT (1u) +#define GPIO_P8_P82_SHIFT (2u) +#define GPIO_P8_P83_SHIFT (3u) +#define GPIO_P8_P84_SHIFT (4u) +#define GPIO_P8_P85_SHIFT (5u) +#define GPIO_P8_P86_SHIFT (6u) +#define GPIO_P8_P87_SHIFT (7u) +#define GPIO_P8_P88_SHIFT (8u) +#define GPIO_P8_P89_SHIFT (9u) +#define GPIO_P8_P810_SHIFT (10u) +#define GPIO_P8_P811_SHIFT (11u) +#define GPIO_P8_P812_SHIFT (12u) +#define GPIO_P8_P813_SHIFT (13u) +#define GPIO_P8_P814_SHIFT (14u) +#define GPIO_P8_P815_SHIFT (15u) + +#define GPIO_PSR8_PSR80_SHIFT (0u) +#define GPIO_PSR8_PSR81_SHIFT (1u) +#define GPIO_PSR8_PSR82_SHIFT (2u) +#define GPIO_PSR8_PSR83_SHIFT (3u) +#define GPIO_PSR8_PSR84_SHIFT (4u) +#define GPIO_PSR8_PSR85_SHIFT (5u) +#define GPIO_PSR8_PSR86_SHIFT (6u) +#define GPIO_PSR8_PSR87_SHIFT (7u) +#define GPIO_PSR8_PSR88_SHIFT (8u) +#define GPIO_PSR8_PSR89_SHIFT (9u) +#define GPIO_PSR8_PSR810_SHIFT (10u) +#define GPIO_PSR8_PSR811_SHIFT (11u) +#define GPIO_PSR8_PSR812_SHIFT (12u) +#define GPIO_PSR8_PSR813_SHIFT (13u) +#define GPIO_PSR8_PSR814_SHIFT (14u) +#define GPIO_PSR8_PSR815_SHIFT (15u) +#define GPIO_PSR8_PSR816_SHIFT (16u) +#define GPIO_PSR8_PSR817_SHIFT (17u) +#define GPIO_PSR8_PSR818_SHIFT (18u) +#define GPIO_PSR8_PSR819_SHIFT (19u) +#define GPIO_PSR8_PSR820_SHIFT (20u) +#define GPIO_PSR8_PSR821_SHIFT (21u) +#define GPIO_PSR8_PSR822_SHIFT (22u) +#define GPIO_PSR8_PSR823_SHIFT (23u) +#define GPIO_PSR8_PSR824_SHIFT (24u) +#define GPIO_PSR8_PSR825_SHIFT (25u) +#define GPIO_PSR8_PSR826_SHIFT (26u) +#define GPIO_PSR8_PSR827_SHIFT (27u) +#define GPIO_PSR8_PSR828_SHIFT (28u) +#define GPIO_PSR8_PSR829_SHIFT (29u) +#define GPIO_PSR8_PSR830_SHIFT (30u) +#define GPIO_PSR8_PSR831_SHIFT (31u) + +#define GPIO_PPR8_PPR80_SHIFT (0u) +#define GPIO_PPR8_PPR81_SHIFT (1u) +#define GPIO_PPR8_PPR82_SHIFT (2u) +#define GPIO_PPR8_PPR83_SHIFT (3u) +#define GPIO_PPR8_PPR84_SHIFT (4u) +#define GPIO_PPR8_PPR85_SHIFT (5u) +#define GPIO_PPR8_PPR86_SHIFT (6u) +#define GPIO_PPR8_PPR87_SHIFT (7u) +#define GPIO_PPR8_PPR88_SHIFT (8u) +#define GPIO_PPR8_PPR89_SHIFT (9u) +#define GPIO_PPR8_PPR810_SHIFT (10u) +#define GPIO_PPR8_PPR811_SHIFT (11u) +#define GPIO_PPR8_PPR812_SHIFT (12u) +#define GPIO_PPR8_PPR813_SHIFT (13u) +#define GPIO_PPR8_PPR814_SHIFT (14u) +#define GPIO_PPR8_PPR815_SHIFT (15u) + +#define GPIO_PM8_PM80_SHIFT (0u) +#define GPIO_PM8_PM81_SHIFT (1u) +#define GPIO_PM8_PM82_SHIFT (2u) +#define GPIO_PM8_PM83_SHIFT (3u) +#define GPIO_PM8_PM84_SHIFT (4u) +#define GPIO_PM8_PM85_SHIFT (5u) +#define GPIO_PM8_PM86_SHIFT (6u) +#define GPIO_PM8_PM87_SHIFT (7u) +#define GPIO_PM8_PM88_SHIFT (8u) +#define GPIO_PM8_PM89_SHIFT (9u) +#define GPIO_PM8_PM810_SHIFT (10u) +#define GPIO_PM8_PM811_SHIFT (11u) +#define GPIO_PM8_PM812_SHIFT (12u) +#define GPIO_PM8_PM813_SHIFT (13u) +#define GPIO_PM8_PM814_SHIFT (14u) +#define GPIO_PM8_PM815_SHIFT (15u) + +#define GPIO_PMC8_PMC80_SHIFT (0u) +#define GPIO_PMC8_PMC81_SHIFT (1u) +#define GPIO_PMC8_PMC82_SHIFT (2u) +#define GPIO_PMC8_PMC83_SHIFT (3u) +#define GPIO_PMC8_PMC84_SHIFT (4u) +#define GPIO_PMC8_PMC85_SHIFT (5u) +#define GPIO_PMC8_PMC86_SHIFT (6u) +#define GPIO_PMC8_PMC87_SHIFT (7u) +#define GPIO_PMC8_PMC88_SHIFT (8u) +#define GPIO_PMC8_PMC89_SHIFT (9u) +#define GPIO_PMC8_PMC810_SHIFT (10u) +#define GPIO_PMC8_PMC811_SHIFT (11u) +#define GPIO_PMC8_PMC812_SHIFT (12u) +#define GPIO_PMC8_PMC813_SHIFT (13u) +#define GPIO_PMC8_PMC814_SHIFT (14u) +#define GPIO_PMC8_PMC815_SHIFT (15u) + +#define GPIO_PFC8_PFC80_SHIFT (0u) +#define GPIO_PFC8_PFC81_SHIFT (1u) +#define GPIO_PFC8_PFC82_SHIFT (2u) +#define GPIO_PFC8_PFC83_SHIFT (3u) +#define GPIO_PFC8_PFC84_SHIFT (4u) +#define GPIO_PFC8_PFC85_SHIFT (5u) +#define GPIO_PFC8_PFC86_SHIFT (6u) +#define GPIO_PFC8_PFC87_SHIFT (7u) +#define GPIO_PFC8_PFC88_SHIFT (8u) +#define GPIO_PFC8_PFC89_SHIFT (9u) +#define GPIO_PFC8_PFC810_SHIFT (10u) +#define GPIO_PFC8_PFC811_SHIFT (11u) +#define GPIO_PFC8_PFC812_SHIFT (12u) +#define GPIO_PFC8_PFC813_SHIFT (13u) +#define GPIO_PFC8_PFC814_SHIFT (14u) +#define GPIO_PFC8_PFC815_SHIFT (15u) + +#define GPIO_PFCE8_PFCE80_SHIFT (0u) +#define GPIO_PFCE8_PFCE81_SHIFT (1u) +#define GPIO_PFCE8_PFCE82_SHIFT (2u) +#define GPIO_PFCE8_PFCE83_SHIFT (3u) +#define GPIO_PFCE8_PFCE84_SHIFT (4u) +#define GPIO_PFCE8_PFCE85_SHIFT (5u) +#define GPIO_PFCE8_PFCE86_SHIFT (6u) +#define GPIO_PFCE8_PFCE87_SHIFT (7u) +#define GPIO_PFCE8_PFCE88_SHIFT (8u) +#define GPIO_PFCE8_PFCE89_SHIFT (9u) +#define GPIO_PFCE8_PFCE810_SHIFT (10u) +#define GPIO_PFCE8_PFCE811_SHIFT (11u) +#define GPIO_PFCE8_PFCE812_SHIFT (12u) +#define GPIO_PFCE8_PFCE813_SHIFT (13u) +#define GPIO_PFCE8_PFCE814_SHIFT (14u) +#define GPIO_PFCE8_PFCE815_SHIFT (15u) + +#define GPIO_PNOT8_PNOT80_SHIFT (0u) +#define GPIO_PNOT8_PNOT81_SHIFT (1u) +#define GPIO_PNOT8_PNOT82_SHIFT (2u) +#define GPIO_PNOT8_PNOT83_SHIFT (3u) +#define GPIO_PNOT8_PNOT84_SHIFT (4u) +#define GPIO_PNOT8_PNOT85_SHIFT (5u) +#define GPIO_PNOT8_PNOT86_SHIFT (6u) +#define GPIO_PNOT8_PNOT87_SHIFT (7u) +#define GPIO_PNOT8_PNOT88_SHIFT (8u) +#define GPIO_PNOT8_PNOT89_SHIFT (9u) +#define GPIO_PNOT8_PNOT810_SHIFT (10u) +#define GPIO_PNOT8_PNOT811_SHIFT (11u) +#define GPIO_PNOT8_PNOT812_SHIFT (12u) +#define GPIO_PNOT8_PNOT813_SHIFT (13u) +#define GPIO_PNOT8_PNOT814_SHIFT (14u) +#define GPIO_PNOT8_PNOT815_SHIFT (15u) + +#define GPIO_PMSR8_PMSR80_SHIFT (0u) +#define GPIO_PMSR8_PMSR81_SHIFT (1u) +#define GPIO_PMSR8_PMSR82_SHIFT (2u) +#define GPIO_PMSR8_PMSR83_SHIFT (3u) +#define GPIO_PMSR8_PMSR84_SHIFT (4u) +#define GPIO_PMSR8_PMSR85_SHIFT (5u) +#define GPIO_PMSR8_PMSR86_SHIFT (6u) +#define GPIO_PMSR8_PMSR87_SHIFT (7u) +#define GPIO_PMSR8_PMSR88_SHIFT (8u) +#define GPIO_PMSR8_PMSR89_SHIFT (9u) +#define GPIO_PMSR8_PMSR810_SHIFT (10u) +#define GPIO_PMSR8_PMSR811_SHIFT (11u) +#define GPIO_PMSR8_PMSR812_SHIFT (12u) +#define GPIO_PMSR8_PMSR813_SHIFT (13u) +#define GPIO_PMSR8_PMSR814_SHIFT (14u) +#define GPIO_PMSR8_PMSR815_SHIFT (15u) +#define GPIO_PMSR8_PMSR816_SHIFT (16u) +#define GPIO_PMSR8_PMSR817_SHIFT (17u) +#define GPIO_PMSR8_PMSR818_SHIFT (18u) +#define GPIO_PMSR8_PMSR819_SHIFT (19u) +#define GPIO_PMSR8_PMSR820_SHIFT (20u) +#define GPIO_PMSR8_PMSR821_SHIFT (21u) +#define GPIO_PMSR8_PMSR822_SHIFT (22u) +#define GPIO_PMSR8_PMSR823_SHIFT (23u) +#define GPIO_PMSR8_PMSR824_SHIFT (24u) +#define GPIO_PMSR8_PMSR825_SHIFT (25u) +#define GPIO_PMSR8_PMSR826_SHIFT (26u) +#define GPIO_PMSR8_PMSR827_SHIFT (27u) +#define GPIO_PMSR8_PMSR828_SHIFT (28u) +#define GPIO_PMSR8_PMSR829_SHIFT (29u) +#define GPIO_PMSR8_PMSR830_SHIFT (30u) +#define GPIO_PMSR8_PMSR831_SHIFT (31u) + +#define GPIO_PMCSR8_PMCSR80_SHIFT (0u) +#define GPIO_PMCSR8_PMCSR81_SHIFT (1u) +#define GPIO_PMCSR8_PMCSR82_SHIFT (2u) +#define GPIO_PMCSR8_PMCSR83_SHIFT (3u) +#define GPIO_PMCSR8_PMCSR84_SHIFT (4u) +#define GPIO_PMCSR8_PMCSR85_SHIFT (5u) +#define GPIO_PMCSR8_PMCSR86_SHIFT (6u) +#define GPIO_PMCSR8_PMCSR87_SHIFT (7u) +#define GPIO_PMCSR8_PMCSR88_SHIFT (8u) +#define GPIO_PMCSR8_PMCSR89_SHIFT (9u) +#define GPIO_PMCSR8_PMCSR810_SHIFT (10u) +#define GPIO_PMCSR8_PMCSR811_SHIFT (11u) +#define GPIO_PMCSR8_PMCSR812_SHIFT (12u) +#define GPIO_PMCSR8_PMCSR813_SHIFT (13u) +#define GPIO_PMCSR8_PMCSR814_SHIFT (14u) +#define GPIO_PMCSR8_PMCSR815_SHIFT (15u) +#define GPIO_PMCSR8_PMCSR816_SHIFT (16u) +#define GPIO_PMCSR8_PMCSR817_SHIFT (17u) +#define GPIO_PMCSR8_PMCSR818_SHIFT (18u) +#define GPIO_PMCSR8_PMCSR819_SHIFT (19u) +#define GPIO_PMCSR8_PMCSR820_SHIFT (20u) +#define GPIO_PMCSR8_PMCSR821_SHIFT (21u) +#define GPIO_PMCSR8_PMCSR822_SHIFT (22u) +#define GPIO_PMCSR8_PMCSR823_SHIFT (23u) +#define GPIO_PMCSR8_PMCSR824_SHIFT (24u) +#define GPIO_PMCSR8_PMCSR825_SHIFT (25u) +#define GPIO_PMCSR8_PMCSR826_SHIFT (26u) +#define GPIO_PMCSR8_PMCSR827_SHIFT (27u) +#define GPIO_PMCSR8_PMCSR828_SHIFT (28u) +#define GPIO_PMCSR8_PMCSR829_SHIFT (29u) +#define GPIO_PMCSR8_PMCSR830_SHIFT (30u) +#define GPIO_PMCSR8_PMCSR831_SHIFT (31u) + +#define GPIO_PFCAE8_PFCAE80_SHIFT (0u) +#define GPIO_PFCAE8_PFCAE81_SHIFT (1u) +#define GPIO_PFCAE8_PFCAE82_SHIFT (2u) +#define GPIO_PFCAE8_PFCAE83_SHIFT (3u) +#define GPIO_PFCAE8_PFCAE84_SHIFT (4u) +#define GPIO_PFCAE8_PFCAE85_SHIFT (5u) +#define GPIO_PFCAE8_PFCAE86_SHIFT (6u) +#define GPIO_PFCAE8_PFCAE87_SHIFT (7u) +#define GPIO_PFCAE8_PFCAE88_SHIFT (8u) +#define GPIO_PFCAE8_PFCAE89_SHIFT (9u) +#define GPIO_PFCAE8_PFCAE810_SHIFT (10u) +#define GPIO_PFCAE8_PFCAE811_SHIFT (11u) +#define GPIO_PFCAE8_PFCAE812_SHIFT (12u) +#define GPIO_PFCAE8_PFCAE813_SHIFT (13u) +#define GPIO_PFCAE8_PFCAE814_SHIFT (14u) +#define GPIO_PFCAE8_PFCAE815_SHIFT (15u) + +#define GPIO_PIBC8_PIBC80_SHIFT (0u) +#define GPIO_PIBC8_PIBC81_SHIFT (1u) +#define GPIO_PIBC8_PIBC82_SHIFT (2u) +#define GPIO_PIBC8_PIBC83_SHIFT (3u) +#define GPIO_PIBC8_PIBC84_SHIFT (4u) +#define GPIO_PIBC8_PIBC85_SHIFT (5u) +#define GPIO_PIBC8_PIBC86_SHIFT (6u) +#define GPIO_PIBC8_PIBC87_SHIFT (7u) +#define GPIO_PIBC8_PIBC88_SHIFT (8u) +#define GPIO_PIBC8_PIBC89_SHIFT (9u) +#define GPIO_PIBC8_PIBC810_SHIFT (10u) +#define GPIO_PIBC8_PIBC811_SHIFT (11u) +#define GPIO_PIBC8_PIBC812_SHIFT (12u) +#define GPIO_PIBC8_PIBC813_SHIFT (13u) +#define GPIO_PIBC8_PIBC814_SHIFT (14u) +#define GPIO_PIBC8_PIBC815_SHIFT (15u) + +#define GPIO_PBDC8_PBDC80_SHIFT (0u) +#define GPIO_PBDC8_PBDC81_SHIFT (1u) +#define GPIO_PBDC8_PBDC82_SHIFT (2u) +#define GPIO_PBDC8_PBDC83_SHIFT (3u) +#define GPIO_PBDC8_PBDC84_SHIFT (4u) +#define GPIO_PBDC8_PBDC85_SHIFT (5u) +#define GPIO_PBDC8_PBDC86_SHIFT (6u) +#define GPIO_PBDC8_PBDC87_SHIFT (7u) +#define GPIO_PBDC8_PBDC88_SHIFT (8u) +#define GPIO_PBDC8_PBDC89_SHIFT (9u) +#define GPIO_PBDC8_PBDC810_SHIFT (10u) +#define GPIO_PBDC8_PBDC811_SHIFT (11u) +#define GPIO_PBDC8_PBDC812_SHIFT (12u) +#define GPIO_PBDC8_PBDC813_SHIFT (13u) +#define GPIO_PBDC8_PBDC814_SHIFT (14u) +#define GPIO_PBDC8_PBDC815_SHIFT (15u) + +#define GPIO_PIPC8_PIPC80_SHIFT (0u) +#define GPIO_PIPC8_PIPC81_SHIFT (1u) +#define GPIO_PIPC8_PIPC82_SHIFT (2u) +#define GPIO_PIPC8_PIPC83_SHIFT (3u) +#define GPIO_PIPC8_PIPC84_SHIFT (4u) +#define GPIO_PIPC8_PIPC85_SHIFT (5u) +#define GPIO_PIPC8_PIPC86_SHIFT (6u) +#define GPIO_PIPC8_PIPC87_SHIFT (7u) +#define GPIO_PIPC8_PIPC88_SHIFT (8u) +#define GPIO_PIPC8_PIPC89_SHIFT (9u) +#define GPIO_PIPC8_PIPC810_SHIFT (10u) +#define GPIO_PIPC8_PIPC811_SHIFT (11u) +#define GPIO_PIPC8_PIPC812_SHIFT (12u) +#define GPIO_PIPC8_PIPC813_SHIFT (13u) +#define GPIO_PIPC8_PIPC814_SHIFT (14u) +#define GPIO_PIPC8_PIPC815_SHIFT (15u) + +/* ---- P9 ---- */ +#define GPIO_P9_P90_SHIFT (0u) +#define GPIO_P9_P91_SHIFT (1u) +#define GPIO_P9_P92_SHIFT (2u) +#define GPIO_P9_P93_SHIFT (3u) +#define GPIO_P9_P94_SHIFT (4u) +#define GPIO_P9_P95_SHIFT (5u) +#define GPIO_P9_P96_SHIFT (6u) +#define GPIO_P9_P97_SHIFT (7u) + +#define GPIO_PSR9_PSR90_SHIFT (0u) +#define GPIO_PSR9_PSR91_SHIFT (1u) +#define GPIO_PSR9_PSR92_SHIFT (2u) +#define GPIO_PSR9_PSR93_SHIFT (3u) +#define GPIO_PSR9_PSR94_SHIFT (4u) +#define GPIO_PSR9_PSR95_SHIFT (5u) +#define GPIO_PSR9_PSR96_SHIFT (6u) +#define GPIO_PSR9_PSR97_SHIFT (7u) +#define GPIO_PSR9_PSR916_SHIFT (16u) +#define GPIO_PSR9_PSR917_SHIFT (17u) +#define GPIO_PSR9_PSR918_SHIFT (18u) +#define GPIO_PSR9_PSR919_SHIFT (19u) +#define GPIO_PSR9_PSR920_SHIFT (20u) +#define GPIO_PSR9_PSR921_SHIFT (21u) +#define GPIO_PSR9_PSR922_SHIFT (22u) +#define GPIO_PSR9_PSR923_SHIFT (23u) + +#define GPIO_PPR9_PPR90_SHIFT (0u) +#define GPIO_PPR9_PPR91_SHIFT (1u) +#define GPIO_PPR9_PPR92_SHIFT (2u) +#define GPIO_PPR9_PPR93_SHIFT (3u) +#define GPIO_PPR9_PPR94_SHIFT (4u) +#define GPIO_PPR9_PPR95_SHIFT (5u) +#define GPIO_PPR9_PPR96_SHIFT (6u) +#define GPIO_PPR9_PPR97_SHIFT (7u) + +#define GPIO_PM9_PM90_SHIFT (0u) +#define GPIO_PM9_PM91_SHIFT (1u) +#define GPIO_PM9_PM92_SHIFT (2u) +#define GPIO_PM9_PM93_SHIFT (3u) +#define GPIO_PM9_PM94_SHIFT (4u) +#define GPIO_PM9_PM95_SHIFT (5u) +#define GPIO_PM9_PM96_SHIFT (6u) +#define GPIO_PM9_PM97_SHIFT (7u) + +#define GPIO_PMC9_PMC90_SHIFT (0u) +#define GPIO_PMC9_PMC91_SHIFT (1u) +#define GPIO_PMC9_PMC92_SHIFT (2u) +#define GPIO_PMC9_PMC93_SHIFT (3u) +#define GPIO_PMC9_PMC94_SHIFT (4u) +#define GPIO_PMC9_PMC95_SHIFT (5u) +#define GPIO_PMC9_PMC96_SHIFT (6u) +#define GPIO_PMC9_PMC97_SHIFT (7u) + +#define GPIO_PFC9_PFC90_SHIFT (0u) +#define GPIO_PFC9_PFC91_SHIFT (1u) +#define GPIO_PFC9_PFC92_SHIFT (2u) +#define GPIO_PFC9_PFC93_SHIFT (3u) +#define GPIO_PFC9_PFC94_SHIFT (4u) +#define GPIO_PFC9_PFC95_SHIFT (5u) +#define GPIO_PFC9_PFC96_SHIFT (6u) +#define GPIO_PFC9_PFC97_SHIFT (7u) + +#define GPIO_PFCE9_PFCE90_SHIFT (0u) +#define GPIO_PFCE9_PFCE91_SHIFT (1u) +#define GPIO_PFCE9_PFCE92_SHIFT (2u) +#define GPIO_PFCE9_PFCE93_SHIFT (3u) +#define GPIO_PFCE9_PFCE94_SHIFT (4u) +#define GPIO_PFCE9_PFCE95_SHIFT (5u) +#define GPIO_PFCE9_PFCE96_SHIFT (6u) +#define GPIO_PFCE9_PFCE97_SHIFT (7u) + +#define GPIO_PNOT9_PNOT90_SHIFT (0u) +#define GPIO_PNOT9_PNOT91_SHIFT (1u) +#define GPIO_PNOT9_PNOT92_SHIFT (2u) +#define GPIO_PNOT9_PNOT93_SHIFT (3u) +#define GPIO_PNOT9_PNOT94_SHIFT (4u) +#define GPIO_PNOT9_PNOT95_SHIFT (5u) +#define GPIO_PNOT9_PNOT96_SHIFT (6u) +#define GPIO_PNOT9_PNOT97_SHIFT (7u) + +#define GPIO_PMSR9_PMSR90_SHIFT (0u) +#define GPIO_PMSR9_PMSR91_SHIFT (1u) +#define GPIO_PMSR9_PMSR92_SHIFT (2u) +#define GPIO_PMSR9_PMSR93_SHIFT (3u) +#define GPIO_PMSR9_PMSR94_SHIFT (4u) +#define GPIO_PMSR9_PMSR95_SHIFT (5u) +#define GPIO_PMSR9_PMSR96_SHIFT (6u) +#define GPIO_PMSR9_PMSR97_SHIFT (7u) +#define GPIO_PMSR9_PMSR916_SHIFT (16u) +#define GPIO_PMSR9_PMSR917_SHIFT (17u) +#define GPIO_PMSR9_PMSR918_SHIFT (18u) +#define GPIO_PMSR9_PMSR919_SHIFT (19u) +#define GPIO_PMSR9_PMSR920_SHIFT (20u) +#define GPIO_PMSR9_PMSR921_SHIFT (21u) +#define GPIO_PMSR9_PMSR922_SHIFT (22u) +#define GPIO_PMSR9_PMSR923_SHIFT (23u) + +#define GPIO_PMCSR9_PMCSR90_SHIFT (0u) +#define GPIO_PMCSR9_PMCSR91_SHIFT (1u) +#define GPIO_PMCSR9_PMCSR92_SHIFT (2u) +#define GPIO_PMCSR9_PMCSR93_SHIFT (3u) +#define GPIO_PMCSR9_PMCSR94_SHIFT (4u) +#define GPIO_PMCSR9_PMCSR95_SHIFT (5u) +#define GPIO_PMCSR9_PMCSR96_SHIFT (6u) +#define GPIO_PMCSR9_PMCSR97_SHIFT (7u) +#define GPIO_PMCSR9_PMCSR916_SHIFT (16u) +#define GPIO_PMCSR9_PMCSR917_SHIFT (17u) +#define GPIO_PMCSR9_PMCSR918_SHIFT (18u) +#define GPIO_PMCSR9_PMCSR919_SHIFT (19u) +#define GPIO_PMCSR9_PMCSR920_SHIFT (20u) +#define GPIO_PMCSR9_PMCSR921_SHIFT (21u) +#define GPIO_PMCSR9_PMCSR922_SHIFT (22u) +#define GPIO_PMCSR9_PMCSR923_SHIFT (23u) + +#define GPIO_PFCAE9_PFCAE90_SHIFT (0u) +#define GPIO_PFCAE9_PFCAE91_SHIFT (1u) +#define GPIO_PFCAE9_PFCAE92_SHIFT (2u) +#define GPIO_PFCAE9_PFCAE93_SHIFT (3u) +#define GPIO_PFCAE9_PFCAE94_SHIFT (4u) +#define GPIO_PFCAE9_PFCAE95_SHIFT (5u) +#define GPIO_PFCAE9_PFCAE96_SHIFT (6u) +#define GPIO_PFCAE9_PFCAE97_SHIFT (7u) + +#define GPIO_PIBC9_PIBC90_SHIFT (0u) +#define GPIO_PIBC9_PIBC91_SHIFT (1u) +#define GPIO_PIBC9_PIBC92_SHIFT (2u) +#define GPIO_PIBC9_PIBC93_SHIFT (3u) +#define GPIO_PIBC9_PIBC94_SHIFT (4u) +#define GPIO_PIBC9_PIBC95_SHIFT (5u) +#define GPIO_PIBC9_PIBC96_SHIFT (6u) +#define GPIO_PIBC9_PIBC97_SHIFT (7u) + +#define GPIO_PBDC9_PBDC90_SHIFT (0u) +#define GPIO_PBDC9_PBDC91_SHIFT (1u) +#define GPIO_PBDC9_PBDC92_SHIFT (2u) +#define GPIO_PBDC9_PBDC93_SHIFT (3u) +#define GPIO_PBDC9_PBDC94_SHIFT (4u) +#define GPIO_PBDC9_PBDC95_SHIFT (5u) +#define GPIO_PBDC9_PBDC96_SHIFT (6u) +#define GPIO_PBDC9_PBDC97_SHIFT (7u) + +#define GPIO_PIPC9_PIPC90_SHIFT (0u) +#define GPIO_PIPC9_PIPC91_SHIFT (1u) +#define GPIO_PIPC9_PIPC92_SHIFT (2u) +#define GPIO_PIPC9_PIPC93_SHIFT (3u) +#define GPIO_PIPC9_PIPC94_SHIFT (4u) +#define GPIO_PIPC9_PIPC95_SHIFT (5u) +#define GPIO_PIPC9_PIPC96_SHIFT (6u) +#define GPIO_PIPC9_PIPC97_SHIFT (7u) + +/* ---- P10 ---- */ +#define GPIO_P10_P100_SHIFT (0u) +#define GPIO_P10_P101_SHIFT (1u) +#define GPIO_P10_P102_SHIFT (2u) +#define GPIO_P10_P103_SHIFT (3u) +#define GPIO_P10_P104_SHIFT (4u) +#define GPIO_P10_P105_SHIFT (5u) +#define GPIO_P10_P106_SHIFT (6u) +#define GPIO_P10_P107_SHIFT (7u) +#define GPIO_P10_P108_SHIFT (8u) +#define GPIO_P10_P109_SHIFT (9u) +#define GPIO_P10_P1010_SHIFT (10u) +#define GPIO_P10_P1011_SHIFT (11u) +#define GPIO_P10_P1012_SHIFT (12u) +#define GPIO_P10_P1013_SHIFT (13u) +#define GPIO_P10_P1014_SHIFT (14u) +#define GPIO_P10_P1015_SHIFT (15u) + +#define GPIO_PSR10_PSR100_SHIFT (0u) +#define GPIO_PSR10_PSR101_SHIFT (1u) +#define GPIO_PSR10_PSR102_SHIFT (2u) +#define GPIO_PSR10_PSR103_SHIFT (3u) +#define GPIO_PSR10_PSR104_SHIFT (4u) +#define GPIO_PSR10_PSR105_SHIFT (5u) +#define GPIO_PSR10_PSR106_SHIFT (6u) +#define GPIO_PSR10_PSR107_SHIFT (7u) +#define GPIO_PSR10_PSR108_SHIFT (8u) +#define GPIO_PSR10_PSR109_SHIFT (9u) +#define GPIO_PSR10_PSR1010_SHIFT (10u) +#define GPIO_PSR10_PSR1011_SHIFT (11u) +#define GPIO_PSR10_PSR1012_SHIFT (12u) +#define GPIO_PSR10_PSR1013_SHIFT (13u) +#define GPIO_PSR10_PSR1014_SHIFT (14u) +#define GPIO_PSR10_PSR1015_SHIFT (15u) +#define GPIO_PSR10_PSR1016_SHIFT (16u) +#define GPIO_PSR10_PSR1017_SHIFT (17u) +#define GPIO_PSR10_PSR1018_SHIFT (18u) +#define GPIO_PSR10_PSR1019_SHIFT (19u) +#define GPIO_PSR10_PSR1020_SHIFT (20u) +#define GPIO_PSR10_PSR1021_SHIFT (21u) +#define GPIO_PSR10_PSR1022_SHIFT (22u) +#define GPIO_PSR10_PSR1023_SHIFT (23u) +#define GPIO_PSR10_PSR1024_SHIFT (24u) +#define GPIO_PSR10_PSR1025_SHIFT (25u) +#define GPIO_PSR10_PSR1026_SHIFT (26u) +#define GPIO_PSR10_PSR1027_SHIFT (27u) +#define GPIO_PSR10_PSR1028_SHIFT (28u) +#define GPIO_PSR10_PSR1029_SHIFT (29u) +#define GPIO_PSR10_PSR1030_SHIFT (30u) +#define GPIO_PSR10_PSR1031_SHIFT (31u) + +#define GPIO_PPR10_PPR100_SHIFT (0u) +#define GPIO_PPR10_PPR101_SHIFT (1u) +#define GPIO_PPR10_PPR102_SHIFT (2u) +#define GPIO_PPR10_PPR103_SHIFT (3u) +#define GPIO_PPR10_PPR104_SHIFT (4u) +#define GPIO_PPR10_PPR105_SHIFT (5u) +#define GPIO_PPR10_PPR106_SHIFT (6u) +#define GPIO_PPR10_PPR107_SHIFT (7u) +#define GPIO_PPR10_PPR108_SHIFT (8u) +#define GPIO_PPR10_PPR109_SHIFT (9u) +#define GPIO_PPR10_PPR1010_SHIFT (10u) +#define GPIO_PPR10_PPR1011_SHIFT (11u) +#define GPIO_PPR10_PPR1012_SHIFT (12u) +#define GPIO_PPR10_PPR1013_SHIFT (13u) +#define GPIO_PPR10_PPR1014_SHIFT (14u) +#define GPIO_PPR10_PPR1015_SHIFT (15u) + +#define GPIO_PM10_PM100_SHIFT (0u) +#define GPIO_PM10_PM101_SHIFT (1u) +#define GPIO_PM10_PM102_SHIFT (2u) +#define GPIO_PM10_PM103_SHIFT (3u) +#define GPIO_PM10_PM104_SHIFT (4u) +#define GPIO_PM10_PM105_SHIFT (5u) +#define GPIO_PM10_PM106_SHIFT (6u) +#define GPIO_PM10_PM107_SHIFT (7u) +#define GPIO_PM10_PM108_SHIFT (8u) +#define GPIO_PM10_PM109_SHIFT (9u) +#define GPIO_PM10_PM1010_SHIFT (10u) +#define GPIO_PM10_PM1011_SHIFT (11u) +#define GPIO_PM10_PM1012_SHIFT (12u) +#define GPIO_PM10_PM1013_SHIFT (13u) +#define GPIO_PM10_PM1014_SHIFT (14u) +#define GPIO_PM10_PM1015_SHIFT (15u) + +#define GPIO_PMC10_PMC100_SHIFT (0u) +#define GPIO_PMC10_PMC101_SHIFT (1u) +#define GPIO_PMC10_PMC102_SHIFT (2u) +#define GPIO_PMC10_PMC103_SHIFT (3u) +#define GPIO_PMC10_PMC104_SHIFT (4u) +#define GPIO_PMC10_PMC105_SHIFT (5u) +#define GPIO_PMC10_PMC106_SHIFT (6u) +#define GPIO_PMC10_PMC107_SHIFT (7u) +#define GPIO_PMC10_PMC108_SHIFT (8u) +#define GPIO_PMC10_PMC109_SHIFT (9u) +#define GPIO_PMC10_PMC1010_SHIFT (10u) +#define GPIO_PMC10_PMC1011_SHIFT (11u) +#define GPIO_PMC10_PMC1012_SHIFT (12u) +#define GPIO_PMC10_PMC1013_SHIFT (13u) +#define GPIO_PMC10_PMC1014_SHIFT (14u) +#define GPIO_PMC10_PMC1015_SHIFT (15u) + +#define GPIO_PFC10_PFC100_SHIFT (0u) +#define GPIO_PFC10_PFC101_SHIFT (1u) +#define GPIO_PFC10_PFC102_SHIFT (2u) +#define GPIO_PFC10_PFC103_SHIFT (3u) +#define GPIO_PFC10_PFC104_SHIFT (4u) +#define GPIO_PFC10_PFC105_SHIFT (5u) +#define GPIO_PFC10_PFC106_SHIFT (6u) +#define GPIO_PFC10_PFC107_SHIFT (7u) +#define GPIO_PFC10_PFC108_SHIFT (8u) +#define GPIO_PFC10_PFC109_SHIFT (9u) +#define GPIO_PFC10_PFC1010_SHIFT (10u) +#define GPIO_PFC10_PFC1011_SHIFT (11u) +#define GPIO_PFC10_PFC1012_SHIFT (12u) +#define GPIO_PFC10_PFC1013_SHIFT (13u) +#define GPIO_PFC10_PFC1014_SHIFT (14u) +#define GPIO_PFC10_PFC1015_SHIFT (15u) + +#define GPIO_PFCE10_PFCE100_SHIFT (0u) +#define GPIO_PFCE10_PFCE101_SHIFT (1u) +#define GPIO_PFCE10_PFCE102_SHIFT (2u) +#define GPIO_PFCE10_PFCE103_SHIFT (3u) +#define GPIO_PFCE10_PFCE104_SHIFT (4u) +#define GPIO_PFCE10_PFCE105_SHIFT (5u) +#define GPIO_PFCE10_PFCE106_SHIFT (6u) +#define GPIO_PFCE10_PFCE107_SHIFT (7u) +#define GPIO_PFCE10_PFCE108_SHIFT (8u) +#define GPIO_PFCE10_PFCE109_SHIFT (9u) +#define GPIO_PFCE10_PFCE1010_SHIFT (10u) +#define GPIO_PFCE10_PFCE1011_SHIFT (11u) +#define GPIO_PFCE10_PFCE1012_SHIFT (12u) +#define GPIO_PFCE10_PFCE1013_SHIFT (13u) +#define GPIO_PFCE10_PFCE1014_SHIFT (14u) +#define GPIO_PFCE10_PFCE1015_SHIFT (15u) + +#define GPIO_PNOT10_PNOT100_SHIFT (0u) +#define GPIO_PNOT10_PNOT101_SHIFT (1u) +#define GPIO_PNOT10_PNOT102_SHIFT (2u) +#define GPIO_PNOT10_PNOT103_SHIFT (3u) +#define GPIO_PNOT10_PNOT104_SHIFT (4u) +#define GPIO_PNOT10_PNOT105_SHIFT (5u) +#define GPIO_PNOT10_PNOT106_SHIFT (6u) +#define GPIO_PNOT10_PNOT107_SHIFT (7u) +#define GPIO_PNOT10_PNOT108_SHIFT (8u) +#define GPIO_PNOT10_PNOT109_SHIFT (9u) +#define GPIO_PNOT10_PNOT1010_SHIFT (10u) +#define GPIO_PNOT10_PNOT1011_SHIFT (11u) +#define GPIO_PNOT10_PNOT1012_SHIFT (12u) +#define GPIO_PNOT10_PNOT1013_SHIFT (13u) +#define GPIO_PNOT10_PNOT1014_SHIFT (14u) +#define GPIO_PNOT10_PNOT1015_SHIFT (15u) + +#define GPIO_PMSR10_PMSR100_SHIFT (0u) +#define GPIO_PMSR10_PMSR101_SHIFT (1u) +#define GPIO_PMSR10_PMSR102_SHIFT (2u) +#define GPIO_PMSR10_PMSR103_SHIFT (3u) +#define GPIO_PMSR10_PMSR104_SHIFT (4u) +#define GPIO_PMSR10_PMSR105_SHIFT (5u) +#define GPIO_PMSR10_PMSR106_SHIFT (6u) +#define GPIO_PMSR10_PMSR107_SHIFT (7u) +#define GPIO_PMSR10_PMSR108_SHIFT (8u) +#define GPIO_PMSR10_PMSR109_SHIFT (9u) +#define GPIO_PMSR10_PMSR1010_SHIFT (10u) +#define GPIO_PMSR10_PMSR1011_SHIFT (11u) +#define GPIO_PMSR10_PMSR1012_SHIFT (12u) +#define GPIO_PMSR10_PMSR1013_SHIFT (13u) +#define GPIO_PMSR10_PMSR1014_SHIFT (14u) +#define GPIO_PMSR10_PMSR1015_SHIFT (15u) +#define GPIO_PMSR10_PMSR1016_SHIFT (16u) +#define GPIO_PMSR10_PMSR1017_SHIFT (17u) +#define GPIO_PMSR10_PMSR1018_SHIFT (18u) +#define GPIO_PMSR10_PMSR1019_SHIFT (19u) +#define GPIO_PMSR10_PMSR1020_SHIFT (20u) +#define GPIO_PMSR10_PMSR1021_SHIFT (21u) +#define GPIO_PMSR10_PMSR1022_SHIFT (22u) +#define GPIO_PMSR10_PMSR1023_SHIFT (23u) +#define GPIO_PMSR10_PMSR1024_SHIFT (24u) +#define GPIO_PMSR10_PMSR1025_SHIFT (25u) +#define GPIO_PMSR10_PMSR1026_SHIFT (26u) +#define GPIO_PMSR10_PMSR1027_SHIFT (27u) +#define GPIO_PMSR10_PMSR1028_SHIFT (28u) +#define GPIO_PMSR10_PMSR1029_SHIFT (29u) +#define GPIO_PMSR10_PMSR1030_SHIFT (30u) +#define GPIO_PMSR10_PMSR1031_SHIFT (31u) + +#define GPIO_PMCSR10_PMCSR100_SHIFT (0u) +#define GPIO_PMCSR10_PMCSR101_SHIFT (1u) +#define GPIO_PMCSR10_PMCSR102_SHIFT (2u) +#define GPIO_PMCSR10_PMCSR103_SHIFT (3u) +#define GPIO_PMCSR10_PMCSR104_SHIFT (4u) +#define GPIO_PMCSR10_PMCSR105_SHIFT (5u) +#define GPIO_PMCSR10_PMCSR106_SHIFT (6u) +#define GPIO_PMCSR10_PMCSR107_SHIFT (7u) +#define GPIO_PMCSR10_PMCSR108_SHIFT (8u) +#define GPIO_PMCSR10_PMCSR109_SHIFT (9u) +#define GPIO_PMCSR10_PMCSR1010_SHIFT (10u) +#define GPIO_PMCSR10_PMCSR1011_SHIFT (11u) +#define GPIO_PMCSR10_PMCSR1012_SHIFT (12u) +#define GPIO_PMCSR10_PMCSR1013_SHIFT (13u) +#define GPIO_PMCSR10_PMCSR1014_SHIFT (14u) +#define GPIO_PMCSR10_PMCSR1015_SHIFT (15u) +#define GPIO_PMCSR10_PMCSR1016_SHIFT (16u) +#define GPIO_PMCSR10_PMCSR1017_SHIFT (17u) +#define GPIO_PMCSR10_PMCSR1018_SHIFT (18u) +#define GPIO_PMCSR10_PMCSR1019_SHIFT (19u) +#define GPIO_PMCSR10_PMCSR1020_SHIFT (20u) +#define GPIO_PMCSR10_PMCSR1021_SHIFT (21u) +#define GPIO_PMCSR10_PMCSR1022_SHIFT (22u) +#define GPIO_PMCSR10_PMCSR1023_SHIFT (23u) +#define GPIO_PMCSR10_PMCSR1024_SHIFT (24u) +#define GPIO_PMCSR10_PMCSR1025_SHIFT (25u) +#define GPIO_PMCSR10_PMCSR1026_SHIFT (26u) +#define GPIO_PMCSR10_PMCSR1027_SHIFT (27u) +#define GPIO_PMCSR10_PMCSR1028_SHIFT (28u) +#define GPIO_PMCSR10_PMCSR1029_SHIFT (29u) +#define GPIO_PMCSR10_PMCSR1030_SHIFT (30u) +#define GPIO_PMCSR10_PMCSR1031_SHIFT (31u) + +#define GPIO_PFCAE10_PFCAE100_SHIFT (0u) +#define GPIO_PFCAE10_PFCAE101_SHIFT (1u) +#define GPIO_PFCAE10_PFCAE102_SHIFT (2u) +#define GPIO_PFCAE10_PFCAE103_SHIFT (3u) +#define GPIO_PFCAE10_PFCAE104_SHIFT (4u) +#define GPIO_PFCAE10_PFCAE105_SHIFT (5u) +#define GPIO_PFCAE10_PFCAE106_SHIFT (6u) +#define GPIO_PFCAE10_PFCAE107_SHIFT (7u) +#define GPIO_PFCAE10_PFCAE108_SHIFT (8u) +#define GPIO_PFCAE10_PFCAE109_SHIFT (9u) +#define GPIO_PFCAE10_PFCAE1010_SHIFT (10u) +#define GPIO_PFCAE10_PFCAE1011_SHIFT (11u) +#define GPIO_PFCAE10_PFCAE1012_SHIFT (12u) +#define GPIO_PFCAE10_PFCAE1013_SHIFT (13u) +#define GPIO_PFCAE10_PFCAE1014_SHIFT (14u) +#define GPIO_PFCAE10_PFCAE1015_SHIFT (15u) + +#define GPIO_PIBC10_PIBC100_SHIFT (0u) +#define GPIO_PIBC10_PIBC101_SHIFT (1u) +#define GPIO_PIBC10_PIBC102_SHIFT (2u) +#define GPIO_PIBC10_PIBC103_SHIFT (3u) +#define GPIO_PIBC10_PIBC104_SHIFT (4u) +#define GPIO_PIBC10_PIBC105_SHIFT (5u) +#define GPIO_PIBC10_PIBC106_SHIFT (6u) +#define GPIO_PIBC10_PIBC107_SHIFT (7u) +#define GPIO_PIBC10_PIBC108_SHIFT (8u) +#define GPIO_PIBC10_PIBC109_SHIFT (9u) +#define GPIO_PIBC10_PIBC1010_SHIFT (10u) +#define GPIO_PIBC10_PIBC1011_SHIFT (11u) +#define GPIO_PIBC10_PIBC1012_SHIFT (12u) +#define GPIO_PIBC10_PIBC1013_SHIFT (13u) +#define GPIO_PIBC10_PIBC1014_SHIFT (14u) +#define GPIO_PIBC10_PIBC1015_SHIFT (15u) + +#define GPIO_PBDC10_PBDC100_SHIFT (0u) +#define GPIO_PBDC10_PBDC101_SHIFT (1u) +#define GPIO_PBDC10_PBDC102_SHIFT (2u) +#define GPIO_PBDC10_PBDC103_SHIFT (3u) +#define GPIO_PBDC10_PBDC104_SHIFT (4u) +#define GPIO_PBDC10_PBDC105_SHIFT (5u) +#define GPIO_PBDC10_PBDC106_SHIFT (6u) +#define GPIO_PBDC10_PBDC107_SHIFT (7u) +#define GPIO_PBDC10_PBDC108_SHIFT (8u) +#define GPIO_PBDC10_PBDC109_SHIFT (9u) +#define GPIO_PBDC10_PBDC1010_SHIFT (10u) +#define GPIO_PBDC10_PBDC1011_SHIFT (11u) +#define GPIO_PBDC10_PBDC1012_SHIFT (12u) +#define GPIO_PBDC10_PBDC1013_SHIFT (13u) +#define GPIO_PBDC10_PBDC1014_SHIFT (14u) +#define GPIO_PBDC10_PBDC1015_SHIFT (15u) + +#define GPIO_PIPC10_PIPC100_SHIFT (0u) +#define GPIO_PIPC10_PIPC101_SHIFT (1u) +#define GPIO_PIPC10_PIPC102_SHIFT (2u) +#define GPIO_PIPC10_PIPC103_SHIFT (3u) +#define GPIO_PIPC10_PIPC104_SHIFT (4u) +#define GPIO_PIPC10_PIPC105_SHIFT (5u) +#define GPIO_PIPC10_PIPC106_SHIFT (6u) +#define GPIO_PIPC10_PIPC107_SHIFT (7u) +#define GPIO_PIPC10_PIPC108_SHIFT (8u) +#define GPIO_PIPC10_PIPC109_SHIFT (9u) +#define GPIO_PIPC10_PIPC1010_SHIFT (10u) +#define GPIO_PIPC10_PIPC1011_SHIFT (11u) +#define GPIO_PIPC10_PIPC1012_SHIFT (12u) +#define GPIO_PIPC10_PIPC1013_SHIFT (13u) +#define GPIO_PIPC10_PIPC1014_SHIFT (14u) +#define GPIO_PIPC10_PIPC1015_SHIFT (15u) + +/* ---- P11 ---- */ +#define GPIO_P11_P110_SHIFT (0u) +#define GPIO_P11_P111_SHIFT (1u) +#define GPIO_P11_P112_SHIFT (2u) +#define GPIO_P11_P113_SHIFT (3u) +#define GPIO_P11_P114_SHIFT (4u) +#define GPIO_P11_P115_SHIFT (5u) +#define GPIO_P11_P116_SHIFT (6u) +#define GPIO_P11_P117_SHIFT (7u) +#define GPIO_P11_P118_SHIFT (8u) +#define GPIO_P11_P119_SHIFT (9u) +#define GPIO_P11_P1110_SHIFT (10u) +#define GPIO_P11_P1111_SHIFT (11u) +#define GPIO_P11_P1112_SHIFT (12u) +#define GPIO_P11_P1113_SHIFT (13u) +#define GPIO_P11_P1114_SHIFT (14u) +#define GPIO_P11_P1115_SHIFT (15u) + +#define GPIO_PSR11_PSR110_SHIFT (0u) +#define GPIO_PSR11_PSR111_SHIFT (1u) +#define GPIO_PSR11_PSR112_SHIFT (2u) +#define GPIO_PSR11_PSR113_SHIFT (3u) +#define GPIO_PSR11_PSR114_SHIFT (4u) +#define GPIO_PSR11_PSR115_SHIFT (5u) +#define GPIO_PSR11_PSR116_SHIFT (6u) +#define GPIO_PSR11_PSR117_SHIFT (7u) +#define GPIO_PSR11_PSR118_SHIFT (8u) +#define GPIO_PSR11_PSR119_SHIFT (9u) +#define GPIO_PSR11_PSR1110_SHIFT (10u) +#define GPIO_PSR11_PSR1111_SHIFT (11u) +#define GPIO_PSR11_PSR1112_SHIFT (12u) +#define GPIO_PSR11_PSR1113_SHIFT (13u) +#define GPIO_PSR11_PSR1114_SHIFT (14u) +#define GPIO_PSR11_PSR1115_SHIFT (15u) +#define GPIO_PSR11_PSR1116_SHIFT (16u) +#define GPIO_PSR11_PSR1117_SHIFT (17u) +#define GPIO_PSR11_PSR1118_SHIFT (18u) +#define GPIO_PSR11_PSR1119_SHIFT (19u) +#define GPIO_PSR11_PSR1120_SHIFT (20u) +#define GPIO_PSR11_PSR1121_SHIFT (21u) +#define GPIO_PSR11_PSR1122_SHIFT (22u) +#define GPIO_PSR11_PSR1123_SHIFT (23u) +#define GPIO_PSR11_PSR1124_SHIFT (24u) +#define GPIO_PSR11_PSR1125_SHIFT (25u) +#define GPIO_PSR11_PSR1126_SHIFT (26u) +#define GPIO_PSR11_PSR1127_SHIFT (27u) +#define GPIO_PSR11_PSR1128_SHIFT (28u) +#define GPIO_PSR11_PSR1129_SHIFT (29u) +#define GPIO_PSR11_PSR1130_SHIFT (30u) +#define GPIO_PSR11_PSR1131_SHIFT (31u) + +#define GPIO_PPR11_PPR110_SHIFT (0u) +#define GPIO_PPR11_PPR111_SHIFT (1u) +#define GPIO_PPR11_PPR112_SHIFT (2u) +#define GPIO_PPR11_PPR113_SHIFT (3u) +#define GPIO_PPR11_PPR114_SHIFT (4u) +#define GPIO_PPR11_PPR115_SHIFT (5u) +#define GPIO_PPR11_PPR116_SHIFT (6u) +#define GPIO_PPR11_PPR117_SHIFT (7u) +#define GPIO_PPR11_PPR118_SHIFT (8u) +#define GPIO_PPR11_PPR119_SHIFT (9u) +#define GPIO_PPR11_PPR1110_SHIFT (10u) +#define GPIO_PPR11_PPR1111_SHIFT (11u) +#define GPIO_PPR11_PPR1112_SHIFT (12u) +#define GPIO_PPR11_PPR1113_SHIFT (13u) +#define GPIO_PPR11_PPR1114_SHIFT (14u) +#define GPIO_PPR11_PPR1115_SHIFT (15u) + +#define GPIO_PM11_PM110_SHIFT (0u) +#define GPIO_PM11_PM111_SHIFT (1u) +#define GPIO_PM11_PM112_SHIFT (2u) +#define GPIO_PM11_PM113_SHIFT (3u) +#define GPIO_PM11_PM114_SHIFT (4u) +#define GPIO_PM11_PM115_SHIFT (5u) +#define GPIO_PM11_PM116_SHIFT (6u) +#define GPIO_PM11_PM117_SHIFT (7u) +#define GPIO_PM11_PM118_SHIFT (8u) +#define GPIO_PM11_PM119_SHIFT (9u) +#define GPIO_PM11_PM1110_SHIFT (10u) +#define GPIO_PM11_PM1111_SHIFT (11u) +#define GPIO_PM11_PM1112_SHIFT (12u) +#define GPIO_PM11_PM1113_SHIFT (13u) +#define GPIO_PM11_PM1114_SHIFT (14u) +#define GPIO_PM11_PM1115_SHIFT (15u) + +#define GPIO_PMC11_PMC110_SHIFT (0u) +#define GPIO_PMC11_PMC111_SHIFT (1u) +#define GPIO_PMC11_PMC112_SHIFT (2u) +#define GPIO_PMC11_PMC113_SHIFT (3u) +#define GPIO_PMC11_PMC114_SHIFT (4u) +#define GPIO_PMC11_PMC115_SHIFT (5u) +#define GPIO_PMC11_PMC116_SHIFT (6u) +#define GPIO_PMC11_PMC117_SHIFT (7u) +#define GPIO_PMC11_PMC118_SHIFT (8u) +#define GPIO_PMC11_PMC119_SHIFT (9u) +#define GPIO_PMC11_PMC1110_SHIFT (10u) +#define GPIO_PMC11_PMC1111_SHIFT (11u) +#define GPIO_PMC11_PMC1112_SHIFT (12u) +#define GPIO_PMC11_PMC1113_SHIFT (13u) +#define GPIO_PMC11_PMC1114_SHIFT (14u) +#define GPIO_PMC11_PMC1115_SHIFT (15u) + +#define GPIO_PFC11_PFC110_SHIFT (0u) +#define GPIO_PFC11_PFC111_SHIFT (1u) +#define GPIO_PFC11_PFC112_SHIFT (2u) +#define GPIO_PFC11_PFC113_SHIFT (3u) +#define GPIO_PFC11_PFC114_SHIFT (4u) +#define GPIO_PFC11_PFC115_SHIFT (5u) +#define GPIO_PFC11_PFC116_SHIFT (6u) +#define GPIO_PFC11_PFC117_SHIFT (7u) +#define GPIO_PFC11_PFC118_SHIFT (8u) +#define GPIO_PFC11_PFC119_SHIFT (9u) +#define GPIO_PFC11_PFC1110_SHIFT (10u) +#define GPIO_PFC11_PFC1111_SHIFT (11u) +#define GPIO_PFC11_PFC1112_SHIFT (12u) +#define GPIO_PFC11_PFC1113_SHIFT (13u) +#define GPIO_PFC11_PFC1114_SHIFT (14u) +#define GPIO_PFC11_PFC1115_SHIFT (15u) + +#define GPIO_PFCE11_PFCE110_SHIFT (0u) +#define GPIO_PFCE11_PFCE111_SHIFT (1u) +#define GPIO_PFCE11_PFCE112_SHIFT (2u) +#define GPIO_PFCE11_PFCE113_SHIFT (3u) +#define GPIO_PFCE11_PFCE114_SHIFT (4u) +#define GPIO_PFCE11_PFCE115_SHIFT (5u) +#define GPIO_PFCE11_PFCE116_SHIFT (6u) +#define GPIO_PFCE11_PFCE117_SHIFT (7u) +#define GPIO_PFCE11_PFCE118_SHIFT (8u) +#define GPIO_PFCE11_PFCE119_SHIFT (9u) +#define GPIO_PFCE11_PFCE1110_SHIFT (10u) +#define GPIO_PFCE11_PFCE1111_SHIFT (11u) +#define GPIO_PFCE11_PFCE1112_SHIFT (12u) +#define GPIO_PFCE11_PFCE1113_SHIFT (13u) +#define GPIO_PFCE11_PFCE1114_SHIFT (14u) +#define GPIO_PFCE11_PFCE1115_SHIFT (15u) + +#define GPIO_PNOT11_PNOT110_SHIFT (0u) +#define GPIO_PNOT11_PNOT111_SHIFT (1u) +#define GPIO_PNOT11_PNOT112_SHIFT (2u) +#define GPIO_PNOT11_PNOT113_SHIFT (3u) +#define GPIO_PNOT11_PNOT114_SHIFT (4u) +#define GPIO_PNOT11_PNOT115_SHIFT (5u) +#define GPIO_PNOT11_PNOT116_SHIFT (6u) +#define GPIO_PNOT11_PNOT117_SHIFT (7u) +#define GPIO_PNOT11_PNOT118_SHIFT (8u) +#define GPIO_PNOT11_PNOT119_SHIFT (9u) +#define GPIO_PNOT11_PNOT1110_SHIFT (10u) +#define GPIO_PNOT11_PNOT1111_SHIFT (11u) +#define GPIO_PNOT11_PNOT1112_SHIFT (12u) +#define GPIO_PNOT11_PNOT1113_SHIFT (13u) +#define GPIO_PNOT11_PNOT1114_SHIFT (14u) +#define GPIO_PNOT11_PNOT1115_SHIFT (15u) + +#define GPIO_PMSR11_PMSR110_SHIFT (0u) +#define GPIO_PMSR11_PMSR111_SHIFT (1u) +#define GPIO_PMSR11_PMSR112_SHIFT (2u) +#define GPIO_PMSR11_PMSR113_SHIFT (3u) +#define GPIO_PMSR11_PMSR114_SHIFT (4u) +#define GPIO_PMSR11_PMSR115_SHIFT (5u) +#define GPIO_PMSR11_PMSR116_SHIFT (6u) +#define GPIO_PMSR11_PMSR117_SHIFT (7u) +#define GPIO_PMSR11_PMSR118_SHIFT (8u) +#define GPIO_PMSR11_PMSR119_SHIFT (9u) +#define GPIO_PMSR11_PMSR1110_SHIFT (10u) +#define GPIO_PMSR11_PMSR1111_SHIFT (11u) +#define GPIO_PMSR11_PMSR1112_SHIFT (12u) +#define GPIO_PMSR11_PMSR1113_SHIFT (13u) +#define GPIO_PMSR11_PMSR1114_SHIFT (14u) +#define GPIO_PMSR11_PMSR1115_SHIFT (15u) +#define GPIO_PMSR11_PMSR1116_SHIFT (16u) +#define GPIO_PMSR11_PMSR1117_SHIFT (17u) +#define GPIO_PMSR11_PMSR1118_SHIFT (18u) +#define GPIO_PMSR11_PMSR1119_SHIFT (19u) +#define GPIO_PMSR11_PMSR1120_SHIFT (20u) +#define GPIO_PMSR11_PMSR1121_SHIFT (21u) +#define GPIO_PMSR11_PMSR1122_SHIFT (22u) +#define GPIO_PMSR11_PMSR1123_SHIFT (23u) +#define GPIO_PMSR11_PMSR1124_SHIFT (24u) +#define GPIO_PMSR11_PMSR1125_SHIFT (25u) +#define GPIO_PMSR11_PMSR1126_SHIFT (26u) +#define GPIO_PMSR11_PMSR1127_SHIFT (27u) +#define GPIO_PMSR11_PMSR1128_SHIFT (28u) +#define GPIO_PMSR11_PMSR1129_SHIFT (29u) +#define GPIO_PMSR11_PMSR1130_SHIFT (30u) +#define GPIO_PMSR11_PMSR1131_SHIFT (31u) + +#define GPIO_PMCSR11_PMCSR110_SHIFT (0u) +#define GPIO_PMCSR11_PMCSR111_SHIFT (1u) +#define GPIO_PMCSR11_PMCSR112_SHIFT (2u) +#define GPIO_PMCSR11_PMCSR113_SHIFT (3u) +#define GPIO_PMCSR11_PMCSR114_SHIFT (4u) +#define GPIO_PMCSR11_PMCSR115_SHIFT (5u) +#define GPIO_PMCSR11_PMCSR116_SHIFT (6u) +#define GPIO_PMCSR11_PMCSR117_SHIFT (7u) +#define GPIO_PMCSR11_PMCSR118_SHIFT (8u) +#define GPIO_PMCSR11_PMCSR119_SHIFT (9u) +#define GPIO_PMCSR11_PMCSR1110_SHIFT (10u) +#define GPIO_PMCSR11_PMCSR1111_SHIFT (11u) +#define GPIO_PMCSR11_PMCSR1112_SHIFT (12u) +#define GPIO_PMCSR11_PMCSR1113_SHIFT (13u) +#define GPIO_PMCSR11_PMCSR1114_SHIFT (14u) +#define GPIO_PMCSR11_PMCSR1115_SHIFT (15u) +#define GPIO_PMCSR11_PMCSR1116_SHIFT (16u) +#define GPIO_PMCSR11_PMCSR1117_SHIFT (17u) +#define GPIO_PMCSR11_PMCSR1118_SHIFT (18u) +#define GPIO_PMCSR11_PMCSR1119_SHIFT (19u) +#define GPIO_PMCSR11_PMCSR1120_SHIFT (20u) +#define GPIO_PMCSR11_PMCSR1121_SHIFT (21u) +#define GPIO_PMCSR11_PMCSR1122_SHIFT (22u) +#define GPIO_PMCSR11_PMCSR1123_SHIFT (23u) +#define GPIO_PMCSR11_PMCSR1124_SHIFT (24u) +#define GPIO_PMCSR11_PMCSR1125_SHIFT (25u) +#define GPIO_PMCSR11_PMCSR1126_SHIFT (26u) +#define GPIO_PMCSR11_PMCSR1127_SHIFT (27u) +#define GPIO_PMCSR11_PMCSR1128_SHIFT (28u) +#define GPIO_PMCSR11_PMCSR1129_SHIFT (29u) +#define GPIO_PMCSR11_PMCSR1130_SHIFT (30u) +#define GPIO_PMCSR11_PMCSR1131_SHIFT (31u) + +#define GPIO_PFCAE11_PFCAE110_SHIFT (0u) +#define GPIO_PFCAE11_PFCAE111_SHIFT (1u) +#define GPIO_PFCAE11_PFCAE112_SHIFT (2u) +#define GPIO_PFCAE11_PFCAE113_SHIFT (3u) +#define GPIO_PFCAE11_PFCAE114_SHIFT (4u) +#define GPIO_PFCAE11_PFCAE115_SHIFT (5u) +#define GPIO_PFCAE11_PFCAE116_SHIFT (6u) +#define GPIO_PFCAE11_PFCAE117_SHIFT (7u) +#define GPIO_PFCAE11_PFCAE118_SHIFT (8u) +#define GPIO_PFCAE11_PFCAE119_SHIFT (9u) +#define GPIO_PFCAE11_PFCAE1110_SHIFT (10u) +#define GPIO_PFCAE11_PFCAE1111_SHIFT (11u) +#define GPIO_PFCAE11_PFCAE1112_SHIFT (12u) +#define GPIO_PFCAE11_PFCAE1113_SHIFT (13u) +#define GPIO_PFCAE11_PFCAE1114_SHIFT (14u) +#define GPIO_PFCAE11_PFCAE1115_SHIFT (15u) + +#define GPIO_PIBC11_PIBC110_SHIFT (0u) +#define GPIO_PIBC11_PIBC111_SHIFT (1u) +#define GPIO_PIBC11_PIBC112_SHIFT (2u) +#define GPIO_PIBC11_PIBC113_SHIFT (3u) +#define GPIO_PIBC11_PIBC114_SHIFT (4u) +#define GPIO_PIBC11_PIBC115_SHIFT (5u) +#define GPIO_PIBC11_PIBC116_SHIFT (6u) +#define GPIO_PIBC11_PIBC117_SHIFT (7u) +#define GPIO_PIBC11_PIBC118_SHIFT (8u) +#define GPIO_PIBC11_PIBC119_SHIFT (9u) +#define GPIO_PIBC11_PIBC1110_SHIFT (10u) +#define GPIO_PIBC11_PIBC1111_SHIFT (11u) +#define GPIO_PIBC11_PIBC1112_SHIFT (12u) +#define GPIO_PIBC11_PIBC1113_SHIFT (13u) +#define GPIO_PIBC11_PIBC1114_SHIFT (14u) +#define GPIO_PIBC11_PIBC1115_SHIFT (15u) + +#define GPIO_PBDC11_PBDC110_SHIFT (0u) +#define GPIO_PBDC11_PBDC111_SHIFT (1u) +#define GPIO_PBDC11_PBDC112_SHIFT (2u) +#define GPIO_PBDC11_PBDC113_SHIFT (3u) +#define GPIO_PBDC11_PBDC114_SHIFT (4u) +#define GPIO_PBDC11_PBDC115_SHIFT (5u) +#define GPIO_PBDC11_PBDC116_SHIFT (6u) +#define GPIO_PBDC11_PBDC117_SHIFT (7u) +#define GPIO_PBDC11_PBDC118_SHIFT (8u) +#define GPIO_PBDC11_PBDC119_SHIFT (9u) +#define GPIO_PBDC11_PBDC1110_SHIFT (10u) +#define GPIO_PBDC11_PBDC1111_SHIFT (11u) +#define GPIO_PBDC11_PBDC1112_SHIFT (12u) +#define GPIO_PBDC11_PBDC1113_SHIFT (13u) +#define GPIO_PBDC11_PBDC1114_SHIFT (14u) +#define GPIO_PBDC11_PBDC1115_SHIFT (15u) + +#define GPIO_PIPC11_PIPC110_SHIFT (0u) +#define GPIO_PIPC11_PIPC111_SHIFT (1u) +#define GPIO_PIPC11_PIPC112_SHIFT (2u) +#define GPIO_PIPC11_PIPC113_SHIFT (3u) +#define GPIO_PIPC11_PIPC114_SHIFT (4u) +#define GPIO_PIPC11_PIPC115_SHIFT (5u) +#define GPIO_PIPC11_PIPC116_SHIFT (6u) +#define GPIO_PIPC11_PIPC117_SHIFT (7u) +#define GPIO_PIPC11_PIPC118_SHIFT (8u) +#define GPIO_PIPC11_PIPC119_SHIFT (9u) +#define GPIO_PIPC11_PIPC1110_SHIFT (10u) +#define GPIO_PIPC11_PIPC1111_SHIFT (11u) +#define GPIO_PIPC11_PIPC1112_SHIFT (12u) +#define GPIO_PIPC11_PIPC1113_SHIFT (13u) +#define GPIO_PIPC11_PIPC1114_SHIFT (14u) +#define GPIO_PIPC11_PIPC1115_SHIFT (15u) + + +#endif /* GPIO_IOBITMASK_H */ + +/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/intc_iobitmask.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,11236 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : intc_iobitmask.h +* $Rev: 1115 $ +* $Date:: 2014-07-09 15:35:02 +0900#$ +* Description : INTC register define header +*******************************************************************************/ +#ifndef INTC_IOBITMASK_H +#define INTC_IOBITMASK_H + +/* ==== Mask values for IO registers ==== */ +#define INTC_ICDDCR_Enable (0x00000001uL) + +#define INTC_ICDICTR_ITLinesNumber (0x0000001FuL) +#define INTC_ICDICTR_CPUNumber (0x000000E0uL) +#define INTC_ICDICTR_SecurityExtn (0x00000400uL) +#define INTC_ICDICTR_LSPI (0x0000F800uL) + +#define INTC_ICDIIDR_Implementer (0x00000FFFuL) +#define INTC_ICDIIDR_Revision (0x0000F000uL) +#define INTC_ICDIIDR_Variant (0x000F0000uL) +#define INTC_ICDIIDR_ProductID (0xFF000000uL) + +#define INTC_ICDISR0_SW0 (0x00000001uL) +#define INTC_ICDISR0_SW1 (0x00000002uL) +#define INTC_ICDISR0_SW2 (0x00000004uL) +#define INTC_ICDISR0_SW3 (0x00000008uL) +#define INTC_ICDISR0_SW4 (0x00000010uL) +#define INTC_ICDISR0_SW5 (0x00000020uL) +#define INTC_ICDISR0_SW6 (0x00000040uL) +#define INTC_ICDISR0_SW7 (0x00000080uL) +#define INTC_ICDISR0_SW8 (0x00000100uL) +#define INTC_ICDISR0_SW9 (0x00000200uL) +#define INTC_ICDISR0_SW10 (0x00000400uL) +#define INTC_ICDISR0_SW11 (0x00000800uL) +#define INTC_ICDISR0_SW12 (0x00001000uL) +#define INTC_ICDISR0_SW13 (0x00002000uL) +#define INTC_ICDISR0_SW14 (0x00004000uL) +#define INTC_ICDISR0_SW15 (0x00008000uL) +#define INTC_ICDISR0_PMUIRQ0 (0x00010000uL) +#define INTC_ICDISR0_COMMRX0 (0x00020000uL) +#define INTC_ICDISR0_COMMTX0 (0x00040000uL) +#define INTC_ICDISR0_CTIIRQ0 (0x00080000uL) + +#define INTC_ICDISR1_IRQ0 (0x00000001uL) +#define INTC_ICDISR1_IRQ1 (0x00000002uL) +#define INTC_ICDISR1_IRQ2 (0x00000004uL) +#define INTC_ICDISR1_IRQ3 (0x00000008uL) +#define INTC_ICDISR1_IRQ4 (0x00000010uL) +#define INTC_ICDISR1_IRQ5 (0x00000020uL) +#define INTC_ICDISR1_IRQ6 (0x00000040uL) +#define INTC_ICDISR1_IRQ7 (0x00000080uL) +#define INTC_ICDISR1_PL310ERR (0x00000100uL) +#define INTC_ICDISR1_DMAINT0 (0x00000200uL) +#define INTC_ICDISR1_DMAINT1 (0x00000400uL) +#define INTC_ICDISR1_DMAINT2 (0x00000800uL) +#define INTC_ICDISR1_DMAINT3 (0x00001000uL) +#define INTC_ICDISR1_DMAINT4 (0x00002000uL) +#define INTC_ICDISR1_DMAINT5 (0x00004000uL) +#define INTC_ICDISR1_DMAINT6 (0x00008000uL) +#define INTC_ICDISR1_DMAINT7 (0x00010000uL) +#define INTC_ICDISR1_DMAINT8 (0x00020000uL) +#define INTC_ICDISR1_DMAINT9 (0x00040000uL) +#define INTC_ICDISR1_DMAINT10 (0x00080000uL) +#define INTC_ICDISR1_DMAINT11 (0x00100000uL) +#define INTC_ICDISR1_DMAINT12 (0x00200000uL) +#define INTC_ICDISR1_DMAINT13 (0x00400000uL) +#define INTC_ICDISR1_DMAINT14 (0x00800000uL) +#define INTC_ICDISR1_DMAINT15 (0x01000000uL) +#define INTC_ICDISR1_DMAERR (0x02000000uL) + +#define INTC_ICDISR2_USBI0 (0x00000200uL) +#define INTC_ICDISR2_USBI1 (0x00000400uL) +#define INTC_ICDISR2_S0_VI_VSYNC0 (0x00000800uL) +#define INTC_ICDISR2_S0_LO_VSYNC0 (0x00001000uL) +#define INTC_ICDISR2_S0_VSYNCERR0 (0x00002000uL) +#define INTC_ICDISR2_GR3_VLINE0 (0x00004000uL) +#define INTC_ICDISR2_S0_VFIELD0 (0x00008000uL) +#define INTC_ICDISR2_IV1_VBUFERR0 (0x00010000uL) +#define INTC_ICDISR2_IV3_VBUFERR0 (0x00020000uL) +#define INTC_ICDISR2_IV5_VBUFERR0 (0x00040000uL) +#define INTC_ICDISR2_IV6_VBUFERR0 (0x00080000uL) +#define INTC_ICDISR2_S0_WLINE0 (0x00100000uL) +#define INTC_ICDISR2_S1_VI_VSYNC0 (0x00200000uL) +#define INTC_ICDISR2_S1_LO_VSYNC0 (0x00400000uL) +#define INTC_ICDISR2_S1_VSYNCERR0 (0x00800000uL) +#define INTC_ICDISR2_S1_VFIELD0 (0x01000000uL) +#define INTC_ICDISR2_IV2_VBUFERR0 (0x02000000uL) +#define INTC_ICDISR2_IV4_VBUFERR0 (0x04000000uL) +#define INTC_ICDISR2_S1_WLINE0 (0x08000000uL) +#define INTC_ICDISR2_OIR_VI_VSYNC0 (0x10000000uL) +#define INTC_ICDISR2_OIR_LO_VSYNC0 (0x20000000uL) +#define INTC_ICDISR2_OIR_VSYNCERR0 (0x40000000uL) +#define INTC_ICDISR2_OIR_VFIELD0 (0x80000000uL) + +#define INTC_ICDISR3_IV7_VBUFERR0 (0x00000001uL) +#define INTC_ICDISR3_IV8_VBUFERR0 (0x00000002uL) +#define INTC_ICDISR3_S0_VI_VSYNC1 (0x00000008uL) +#define INTC_ICDISR3_S0_LO_VSYNC1 (0x00000010uL) +#define INTC_ICDISR3_S0_VSYNCERR1 (0x00000020uL) +#define INTC_ICDISR3_GR3_VLINE1 (0x00000040uL) +#define INTC_ICDISR3_S0_VFIELD1 (0x00000080uL) +#define INTC_ICDISR3_IV1_VBUFERR1 (0x00000100uL) +#define INTC_ICDISR3_IV3_VBUFERR1 (0x00000200uL) +#define INTC_ICDISR3_IV5_VBUFERR1 (0x00000400uL) +#define INTC_ICDISR3_IV6_VBUFERR1 (0x00000800uL) +#define INTC_ICDISR3_S0_WLINE1 (0x00001000uL) +#define INTC_ICDISR3_S1_VI_VSYNC1 (0x00002000uL) +#define INTC_ICDISR3_S1_LO_VSYNC1 (0x00004000uL) +#define INTC_ICDISR3_S1_VSYNCERR1 (0x00008000uL) +#define INTC_ICDISR3_S1_VFIELD1 (0x00010000uL) +#define INTC_ICDISR3_IV2_VBUFERR1 (0x00020000uL) +#define INTC_ICDISR3_IV4_VBUFERR1 (0x00040000uL) +#define INTC_ICDISR3_S1_WLINE1 (0x00080000uL) +#define INTC_ICDISR3_OIR_VI_VSYNC1 (0x00100000uL) +#define INTC_ICDISR3_OIR_LO_VSYNC1 (0x00200000uL) +#define INTC_ICDISR3_OIR_VLINE1 (0x00400000uL) +#define INTC_ICDISR3_OIR_VFIELD1 (0x00800000uL) +#define INTC_ICDISR3_IV7_VBUFERR1 (0x01000000uL) +#define INTC_ICDISR3_IV8_VBUFERR1 (0x02000000uL) +#define INTC_ICDISR3_IMRDI (0x08000000uL) +#define INTC_ICDISR3_IMR2I0 (0x10000000uL) +#define INTC_ICDISR3_IMR2I1 (0x20000000uL) +#define INTC_ICDISR3_JEDI (0x40000000uL) +#define INTC_ICDISR3_JDTI (0x80000000uL) + +#define INTC_ICDISR4_CMP0 (0x00000001uL) +#define INTC_ICDISR4_CMP1 (0x00000002uL) +#define INTC_ICDISR4_INT0 (0x00000004uL) +#define INTC_ICDISR4_INT1 (0x00000008uL) +#define INTC_ICDISR4_INT2 (0x00000010uL) +#define INTC_ICDISR4_INT3 (0x00000020uL) +#define INTC_ICDISR4_OSTM0TINT (0x00000040uL) +#define INTC_ICDISR4_OSTM1TINT (0x00000080uL) +#define INTC_ICDISR4_CMI (0x00000100uL) +#define INTC_ICDISR4_WTOUT (0x00000200uL) +#define INTC_ICDISR4_ITI (0x00000400uL) +#define INTC_ICDISR4_TGI0A (0x00000800uL) +#define INTC_ICDISR4_TGI0B (0x00001000uL) +#define INTC_ICDISR4_TGI0C (0x00002000uL) +#define INTC_ICDISR4_TGI0D (0x00004000uL) +#define INTC_ICDISR4_TGI0V (0x00008000uL) +#define INTC_ICDISR4_TGI0E (0x00010000uL) +#define INTC_ICDISR4_TGI0F (0x00020000uL) +#define INTC_ICDISR4_TGI1A (0x00040000uL) +#define INTC_ICDISR4_TGI1B (0x00080000uL) +#define INTC_ICDISR4_TGI1V (0x00100000uL) +#define INTC_ICDISR4_TGI1U (0x00200000uL) +#define INTC_ICDISR4_TGI2A (0x00400000uL) +#define INTC_ICDISR4_TGI2B (0x00800000uL) +#define INTC_ICDISR4_TGI2V (0x01000000uL) +#define INTC_ICDISR4_TGI2U (0x02000000uL) +#define INTC_ICDISR4_TGI3A (0x04000000uL) +#define INTC_ICDISR4_TGI3B (0x08000000uL) +#define INTC_ICDISR4_TGI3C (0x10000000uL) +#define INTC_ICDISR4_TGI3D (0x20000000uL) +#define INTC_ICDISR4_TGI3V (0x40000000uL) +#define INTC_ICDISR4_TGI4A (0x80000000uL) + +#define INTC_ICDISR5_TGI4B (0x00000001uL) +#define INTC_ICDISR5_TGI4C (0x00000002uL) +#define INTC_ICDISR5_TGI4D (0x00000004uL) +#define INTC_ICDISR5_TGI4V (0x00000008uL) +#define INTC_ICDISR5_CMI1 (0x00000010uL) +#define INTC_ICDISR5_CMI2 (0x00000020uL) +#define INTC_ICDISR5_SGDEI0 (0x00000040uL) +#define INTC_ICDISR5_SGDEI1 (0x00000080uL) +#define INTC_ICDISR5_SGDEI2 (0x00000100uL) +#define INTC_ICDISR5_SGDEI3 (0x00000200uL) +#define INTC_ICDISR5_ADI (0x00000400uL) +#define INTC_ICDISR5_LMTI (0x00000800uL) +#define INTC_ICDISR5_SSII0 (0x00001000uL) +#define INTC_ICDISR5_SSIRXI0 (0x00002000uL) +#define INTC_ICDISR5_SSITXI0 (0x00004000uL) +#define INTC_ICDISR5_SSII1 (0x00008000uL) +#define INTC_ICDISR5_SSIRXI1 (0x00010000uL) +#define INTC_ICDISR5_SSITXI1 (0x00020000uL) +#define INTC_ICDISR5_SSII2 (0x00040000uL) +#define INTC_ICDISR5_SSIRTI2 (0x00080000uL) +#define INTC_ICDISR5_SSII3 (0x00100000uL) +#define INTC_ICDISR5_SSIRXI3 (0x00200000uL) +#define INTC_ICDISR5_SSITXI3 (0x00400000uL) +#define INTC_ICDISR5_SSII4 (0x00800000uL) +#define INTC_ICDISR5_SSIRTI4 (0x01000000uL) +#define INTC_ICDISR5_SSII5 (0x02000000uL) +#define INTC_ICDISR5_SSIRXI5 (0x04000000uL) +#define INTC_ICDISR5_SSITXI5 (0x08000000uL) +#define INTC_ICDISR5_SPDIFI (0x10000000uL) +#define INTC_ICDISR5_INTIICTEI0 (0x20000000uL) +#define INTC_ICDISR5_INTIICRI0 (0x40000000uL) +#define INTC_ICDISR5_INTIICTI0 (0x80000000uL) + +#define INTC_ICDISR6_INTIICSPI0 (0x00000001uL) +#define INTC_ICDISR6_INTIICSTI0 (0x00000002uL) +#define INTC_ICDISR6_INTIICNAKI0 (0x00000004uL) +#define INTC_ICDISR6_INTIICALI0 (0x00000008uL) +#define INTC_ICDISR6_INTIICTMOI0 (0x00000010uL) +#define INTC_ICDISR6_INTIICTEI1 (0x00000020uL) +#define INTC_ICDISR6_INTIICRI1 (0x00000040uL) +#define INTC_ICDISR6_INTIICTI1 (0x00000080uL) +#define INTC_ICDISR6_INTIICSPI1 (0x00000100uL) +#define INTC_ICDISR6_INTIICSTI1 (0x00000200uL) +#define INTC_ICDISR6_INTIICNAKI1 (0x00000400uL) +#define INTC_ICDISR6_INTIICALI1 (0x00000800uL) +#define INTC_ICDISR6_INTIICTMOI1 (0x00001000uL) +#define INTC_ICDISR6_INTIICTEI2 (0x00002000uL) +#define INTC_ICDISR6_INTIICRI2 (0x00004000uL) +#define INTC_ICDISR6_INTIICTI2 (0x00008000uL) +#define INTC_ICDISR6_INTIICSPI2 (0x00010000uL) +#define INTC_ICDISR6_INTIICSTI2 (0x00020000uL) +#define INTC_ICDISR6_INTIICNAKI2 (0x00040000uL) +#define INTC_ICDISR6_INTIICALI2 (0x00080000uL) +#define INTC_ICDISR6_INTIICTMOI2 (0x00100000uL) +#define INTC_ICDISR6_INTIICTEI3 (0x00200000uL) +#define INTC_ICDISR6_INTIICRI3 (0x00400000uL) +#define INTC_ICDISR6_INTIICTI3 (0x00800000uL) +#define INTC_ICDISR6_INTIICSPI3 (0x01000000uL) +#define INTC_ICDISR6_INTIICSTI3 (0x02000000uL) +#define INTC_ICDISR6_INTIICNAKI3 (0x04000000uL) +#define INTC_ICDISR6_INTIICALI3 (0x08000000uL) +#define INTC_ICDISR6_INTIICTMOI3 (0x10000000uL) +#define INTC_ICDISR6_BRI0 (0x20000000uL) +#define INTC_ICDISR6_ERI0 (0x40000000uL) +#define INTC_ICDISR6_RXI0 (0x80000000uL) + +#define INTC_ICDISR7_TXI0 (0x00000001uL) +#define INTC_ICDISR7_BRI1 (0x00000002uL) +#define INTC_ICDISR7_ERI1 (0x00000004uL) +#define INTC_ICDISR7_RXI1 (0x00000008uL) +#define INTC_ICDISR7_TXI1 (0x00000010uL) +#define INTC_ICDISR7_BRI2 (0x00000020uL) +#define INTC_ICDISR7_ERI2 (0x00000040uL) +#define INTC_ICDISR7_RXI2 (0x00000080uL) +#define INTC_ICDISR7_TXI2 (0x00000100uL) +#define INTC_ICDISR7_BRI3 (0x00000200uL) +#define INTC_ICDISR7_ERI3 (0x00000400uL) +#define INTC_ICDISR7_RXI3 (0x00000800uL) +#define INTC_ICDISR7_TXI3 (0x00001000uL) +#define INTC_ICDISR7_BRI4 (0x00002000uL) +#define INTC_ICDISR7_ERI4 (0x00004000uL) +#define INTC_ICDISR7_RXI4 (0x00008000uL) +#define INTC_ICDISR7_TXI4 (0x00010000uL) +#define INTC_ICDISR7_BRI5 (0x00020000uL) +#define INTC_ICDISR7_ERI5 (0x00040000uL) +#define INTC_ICDISR7_RXI5 (0x00080000uL) +#define INTC_ICDISR7_TXI5 (0x00100000uL) +#define INTC_ICDISR7_BRI6 (0x00200000uL) +#define INTC_ICDISR7_ERI6 (0x00400000uL) +#define INTC_ICDISR7_RXI6 (0x00800000uL) +#define INTC_ICDISR7_TXI6 (0x01000000uL) +#define INTC_ICDISR7_BRI7 (0x02000000uL) +#define INTC_ICDISR7_ERI7 (0x04000000uL) +#define INTC_ICDISR7_RXI7 (0x08000000uL) +#define INTC_ICDISR7_TXI7 (0x10000000uL) +#define INTC_ICDISR7_INTRCANGERR (0x20000000uL) +#define INTC_ICDISR7_INTRCANGRECC (0x40000000uL) +#define INTC_ICDISR7_INTRCAN0REC (0x80000000uL) + +#define INTC_ICDISR8_INTRCAN0ERR (0x00000001uL) +#define INTC_ICDISR8_INTRCAN0TRX (0x00000002uL) +#define INTC_ICDISR8_INTRCAN1REC (0x00000004uL) +#define INTC_ICDISR8_INTRCAN1ERR (0x00000008uL) +#define INTC_ICDISR8_INTRCAN1TRX (0x00000010uL) +#define INTC_ICDISR8_INTRCAN2REC (0x00000020uL) +#define INTC_ICDISR8_INTRCAN2ERR (0x00000040uL) +#define INTC_ICDISR8_INTRCAN2TRX (0x00000080uL) +#define INTC_ICDISR8_INTRCAN3REC (0x00000100uL) +#define INTC_ICDISR8_INTRCAN3ERR (0x00000200uL) +#define INTC_ICDISR8_INTRCAN3TRX (0x00000400uL) +#define INTC_ICDISR8_INTRCAN4REC (0x00000800uL) +#define INTC_ICDISR8_INTRCAN4ERR (0x00001000uL) +#define INTC_ICDISR8_INTRCAN4TRX (0x00002000uL) +#define INTC_ICDISR8_SPEI0 (0x00004000uL) +#define INTC_ICDISR8_SPRI0 (0x00008000uL) +#define INTC_ICDISR8_SPTI0 (0x00010000uL) +#define INTC_ICDISR8_SPEI1 (0x00020000uL) +#define INTC_ICDISR8_SPRI1 (0x00040000uL) +#define INTC_ICDISR8_SPTI1 (0x00080000uL) +#define INTC_ICDISR8_SPEI2 (0x00100000uL) +#define INTC_ICDISR8_SPRI2 (0x00200000uL) +#define INTC_ICDISR8_SPTI2 (0x00400000uL) +#define INTC_ICDISR8_SPEI3 (0x00800000uL) +#define INTC_ICDISR8_SPRI3 (0x01000000uL) +#define INTC_ICDISR8_SPTI3 (0x02000000uL) +#define INTC_ICDISR8_SPEI4 (0x04000000uL) +#define INTC_ICDISR8_SPRI4 (0x08000000uL) +#define INTC_ICDISR8_SPTI4 (0x10000000uL) +#define INTC_ICDISR8_IEBBTD (0x20000000uL) +#define INTC_ICDISR8_IEBBTERR (0x40000000uL) +#define INTC_ICDISR8_IEBBTSTA (0x80000000uL) + +#define INTC_ICDISR9_IEBBTV (0x00000001uL) +#define INTC_ICDISR9_ISY (0x00000002uL) +#define INTC_ICDISR9_IERR (0x00000004uL) +#define INTC_ICDISR9_ITARG (0x00000008uL) +#define INTC_ICDISR9_ISEC (0x00000010uL) +#define INTC_ICDISR9_IBUF (0x00000020uL) +#define INTC_ICDISR9_IREADY (0x00000040uL) +#define INTC_ICDISR9_FLSTE (0x00000080uL) +#define INTC_ICDISR9_FLTENDI (0x00000100uL) +#define INTC_ICDISR9_FLTREQ0I (0x00000200uL) +#define INTC_ICDISR9_FLTREQ1I (0x00000400uL) +#define INTC_ICDISR9_MMC0 (0x00000800uL) +#define INTC_ICDISR9_MMC1 (0x00001000uL) +#define INTC_ICDISR9_MMC2 (0x00002000uL) +#define INTC_ICDISR9_SDHI0_3 (0x00004000uL) +#define INTC_ICDISR9_SDHI0_0 (0x00008000uL) +#define INTC_ICDISR9_SDHI0_1 (0x00010000uL) +#define INTC_ICDISR9_SDHI1_3 (0x00020000uL) +#define INTC_ICDISR9_SDHI1_0 (0x00040000uL) +#define INTC_ICDISR9_SDHI1_1 (0x00080000uL) +#define INTC_ICDISR9_ARM (0x00100000uL) +#define INTC_ICDISR9_PRD (0x00200000uL) +#define INTC_ICDISR9_CUP (0x00400000uL) +#define INTC_ICDISR9_SCUAI0 (0x00800000uL) +#define INTC_ICDISR9_SCUAI1 (0x01000000uL) +#define INTC_ICDISR9_SCUFDI0 (0x02000000uL) +#define INTC_ICDISR9_SCUFDI1 (0x04000000uL) +#define INTC_ICDISR9_SCUFDI2 (0x08000000uL) +#define INTC_ICDISR9_SCUFDI3 (0x10000000uL) +#define INTC_ICDISR9_SCUFUI0 (0x20000000uL) +#define INTC_ICDISR9_SCUFUI1 (0x40000000uL) +#define INTC_ICDISR9_SCUFUI2 (0x80000000uL) + +#define INTC_ICDISR10_SCUFUI3 (0x00000001uL) +#define INTC_ICDISR10_SCUDVI0 (0x00000002uL) +#define INTC_ICDISR10_SCUDVI1 (0x00000004uL) +#define INTC_ICDISR10_SCUDVI2 (0x00000008uL) +#define INTC_ICDISR10_SCUDVI3 (0x00000010uL) +#define INTC_ICDISR10_MLB_CINT (0x00000020uL) +#define INTC_ICDISR10_MLB_SINT (0x00000040uL) +#define INTC_ICDISR10_DRC0 (0x00000080uL) +#define INTC_ICDISR10_DRC1 (0x00000100uL) +#define INTC_ICDISR10_LINI0_INT_T (0x00000800uL) +#define INTC_ICDISR10_LINI0_INT_R (0x00001000uL) +#define INTC_ICDISR10_LINI0_INT_S (0x00002000uL) +#define INTC_ICDISR10_LINI0_INT_M (0x00004000uL) +#define INTC_ICDISR10_LINI1_INT_T (0x00008000uL) +#define INTC_ICDISR10_LINI1_INT_R (0x00010000uL) +#define INTC_ICDISR10_LINI1_INT_S (0x00020000uL) +#define INTC_ICDISR10_LINI1_INT_M (0x00040000uL) +#define INTC_ICDISR10_ERI0 (0x08000000uL) +#define INTC_ICDISR10_RXI0 (0x10000000uL) +#define INTC_ICDISR10_TXI0 (0x20000000uL) +#define INTC_ICDISR10_TEI0 (0x40000000uL) +#define INTC_ICDISR10_ERI1 (0x80000000uL) + +#define INTC_ICDISR11_RXI1 (0x00000001uL) +#define INTC_ICDISR11_TXI1 (0x00000002uL) +#define INTC_ICDISR11_TEI1 (0x00000004uL) +#define INTC_ICDISR11_AVBI_DATA (0x00000008uL) +#define INTC_ICDISR11_AVBI_ERROR (0x00000010uL) +#define INTC_ICDISR11_AVBI_MANAGE (0x00000020uL) +#define INTC_ICDISR11_AVBI_MAC (0x00000040uL) +#define INTC_ICDISR11_ETHERI (0x00000080uL) +#define INTC_ICDISR11_CEUI (0x00001000uL) +#define INTC_ICDISR11_H2XMLB_ERRINT (0x20000000uL) +#define INTC_ICDISR11_H2XIC1_ERRINT (0x40000000uL) +#define INTC_ICDISR11_X2HPERI1_ERRINT (0x80000000uL) + +#define INTC_ICDISR12_X2HPERI2_ERRINT (0x00000001uL) +#define INTC_ICDISR12_X2HPERI34_ERRINT (0x00000002uL) +#define INTC_ICDISR12_X2HPERI5_ERRINT (0x00000004uL) +#define INTC_ICDISR12_X2HPERI67_ERRINT (0x00000008uL) +#define INTC_ICDISR12_X2HDBGR_ERRINT (0x00000010uL) +#define INTC_ICDISR12_X2HBSC_ERRINT (0x00000020uL) +#define INTC_ICDISR12_X2HSPI1_ERRINT (0x00000040uL) +#define INTC_ICDISR12_X2HSPI2_ERRINT (0x00000080uL) +#define INTC_ICDISR12_PRRI (0x00000100uL) +#define INTC_ICDISR12_IFEI0 (0x00000200uL) +#define INTC_ICDISR12_OFFI0 (0x00000400uL) +#define INTC_ICDISR12_PFVEI0 (0x00000800uL) +#define INTC_ICDISR12_IFEI1 (0x00001000uL) +#define INTC_ICDISR12_OFFI1 (0x00002000uL) +#define INTC_ICDISR12_PFVEI1 (0x00004000uL) + +#define INTC_ICDISR13_TINT0 (0x00000001uL) +#define INTC_ICDISR13_TINT1 (0x00000002uL) +#define INTC_ICDISR13_TINT2 (0x00000004uL) +#define INTC_ICDISR13_TINT3 (0x00000008uL) +#define INTC_ICDISR13_TINT4 (0x00000010uL) +#define INTC_ICDISR13_TINT5 (0x00000020uL) +#define INTC_ICDISR13_TINT6 (0x00000040uL) +#define INTC_ICDISR13_TINT7 (0x00000080uL) +#define INTC_ICDISR13_TINT8 (0x00000100uL) +#define INTC_ICDISR13_TINT9 (0x00000200uL) +#define INTC_ICDISR13_TINT10 (0x00000400uL) +#define INTC_ICDISR13_TINT11 (0x00000800uL) +#define INTC_ICDISR13_TINT12 (0x00001000uL) +#define INTC_ICDISR13_TINT13 (0x00002000uL) +#define INTC_ICDISR13_TINT14 (0x00004000uL) +#define INTC_ICDISR13_TINT15 (0x00008000uL) +#define INTC_ICDISR13_TINT16 (0x00010000uL) +#define INTC_ICDISR13_TINT17 (0x00020000uL) +#define INTC_ICDISR13_TINT18 (0x00040000uL) +#define INTC_ICDISR13_TINT19 (0x00080000uL) +#define INTC_ICDISR13_TINT20 (0x00100000uL) +#define INTC_ICDISR13_TINT21 (0x00200000uL) +#define INTC_ICDISR13_TINT22 (0x00400000uL) +#define INTC_ICDISR13_TINT23 (0x00800000uL) +#define INTC_ICDISR13_TINT24 (0x01000000uL) +#define INTC_ICDISR13_TINT25 (0x02000000uL) +#define INTC_ICDISR13_TINT26 (0x04000000uL) +#define INTC_ICDISR13_TINT27 (0x08000000uL) +#define INTC_ICDISR13_TINT28 (0x10000000uL) +#define INTC_ICDISR13_TINT29 (0x20000000uL) +#define INTC_ICDISR13_TINT30 (0x40000000uL) +#define INTC_ICDISR13_TINT31 (0x80000000uL) + +#define INTC_ICDISR14_TINT32 (0x00000001uL) +#define INTC_ICDISR14_TINT33 (0x00000002uL) +#define INTC_ICDISR14_TINT34 (0x00000004uL) +#define INTC_ICDISR14_TINT35 (0x00000008uL) +#define INTC_ICDISR14_TINT36 (0x00000010uL) +#define INTC_ICDISR14_TINT37 (0x00000020uL) +#define INTC_ICDISR14_TINT38 (0x00000040uL) +#define INTC_ICDISR14_TINT39 (0x00000080uL) +#define INTC_ICDISR14_TINT40 (0x00000100uL) +#define INTC_ICDISR14_TINT41 (0x00000200uL) +#define INTC_ICDISR14_TINT42 (0x00000400uL) +#define INTC_ICDISR14_TINT43 (0x00000800uL) +#define INTC_ICDISR14_TINT44 (0x00001000uL) +#define INTC_ICDISR14_TINT45 (0x00002000uL) +#define INTC_ICDISR14_TINT46 (0x00004000uL) +#define INTC_ICDISR14_TINT47 (0x00008000uL) +#define INTC_ICDISR14_TINT48 (0x00010000uL) +#define INTC_ICDISR14_TINT49 (0x00020000uL) +#define INTC_ICDISR14_TINT50 (0x00040000uL) +#define INTC_ICDISR14_TINT51 (0x00080000uL) +#define INTC_ICDISR14_TINT52 (0x00100000uL) +#define INTC_ICDISR14_TINT53 (0x00200000uL) +#define INTC_ICDISR14_TINT54 (0x00400000uL) +#define INTC_ICDISR14_TINT55 (0x00800000uL) +#define INTC_ICDISR14_TINT56 (0x01000000uL) +#define INTC_ICDISR14_TINT57 (0x02000000uL) +#define INTC_ICDISR14_TINT58 (0x04000000uL) +#define INTC_ICDISR14_TINT59 (0x08000000uL) +#define INTC_ICDISR14_TINT60 (0x10000000uL) +#define INTC_ICDISR14_TINT61 (0x20000000uL) +#define INTC_ICDISR14_TINT62 (0x40000000uL) +#define INTC_ICDISR14_TINT63 (0x80000000uL) + +#define INTC_ICDISR15_TINT64 (0x00000001uL) +#define INTC_ICDISR15_TINT65 (0x00000002uL) +#define INTC_ICDISR15_TINT66 (0x00000004uL) +#define INTC_ICDISR15_TINT67 (0x00000008uL) +#define INTC_ICDISR15_TINT68 (0x00000010uL) +#define INTC_ICDISR15_TINT69 (0x00000020uL) +#define INTC_ICDISR15_TINT70 (0x00000040uL) +#define INTC_ICDISR15_TINT71 (0x00000080uL) +#define INTC_ICDISR15_TINT72 (0x00000100uL) +#define INTC_ICDISR15_TINT73 (0x00000200uL) +#define INTC_ICDISR15_TINT74 (0x00000400uL) +#define INTC_ICDISR15_TINT75 (0x00000800uL) +#define INTC_ICDISR15_TINT76 (0x00001000uL) +#define INTC_ICDISR15_TINT77 (0x00002000uL) +#define INTC_ICDISR15_TINT78 (0x00004000uL) +#define INTC_ICDISR15_TINT79 (0x00008000uL) +#define INTC_ICDISR15_TINT80 (0x00010000uL) +#define INTC_ICDISR15_TINT81 (0x00020000uL) +#define INTC_ICDISR15_TINT82 (0x00040000uL) +#define INTC_ICDISR15_TINT83 (0x00080000uL) +#define INTC_ICDISR15_TINT84 (0x00100000uL) +#define INTC_ICDISR15_TINT85 (0x00200000uL) +#define INTC_ICDISR15_TINT86 (0x00400000uL) +#define INTC_ICDISR15_TINT87 (0x00800000uL) +#define INTC_ICDISR15_TINT88 (0x01000000uL) +#define INTC_ICDISR15_TINT89 (0x02000000uL) +#define INTC_ICDISR15_TINT90 (0x04000000uL) +#define INTC_ICDISR15_TINT91 (0x08000000uL) +#define INTC_ICDISR15_TINT92 (0x10000000uL) +#define INTC_ICDISR15_TINT93 (0x20000000uL) +#define INTC_ICDISR15_TINT94 (0x40000000uL) +#define INTC_ICDISR15_TINT95 (0x80000000uL) + +#define INTC_ICDISR16_TINT96 (0x00000001uL) +#define INTC_ICDISR16_TINT97 (0x00000002uL) +#define INTC_ICDISR16_TINT98 (0x00000004uL) +#define INTC_ICDISR16_TINT99 (0x00000008uL) +#define INTC_ICDISR16_TINT100 (0x00000010uL) +#define INTC_ICDISR16_TINT101 (0x00000020uL) +#define INTC_ICDISR16_TINT102 (0x00000040uL) +#define INTC_ICDISR16_TINT103 (0x00000080uL) +#define INTC_ICDISR16_TINT104 (0x00000100uL) +#define INTC_ICDISR16_TINT105 (0x00000200uL) +#define INTC_ICDISR16_TINT106 (0x00000400uL) +#define INTC_ICDISR16_TINT107 (0x00000800uL) +#define INTC_ICDISR16_TINT108 (0x00001000uL) +#define INTC_ICDISR16_TINT109 (0x00002000uL) +#define INTC_ICDISR16_TINT110 (0x00004000uL) +#define INTC_ICDISR16_TINT111 (0x00008000uL) +#define INTC_ICDISR16_TINT112 (0x00010000uL) +#define INTC_ICDISR16_TINT113 (0x00020000uL) +#define INTC_ICDISR16_TINT114 (0x00040000uL) +#define INTC_ICDISR16_TINT115 (0x00080000uL) +#define INTC_ICDISR16_TINT116 (0x00100000uL) +#define INTC_ICDISR16_TINT117 (0x00200000uL) +#define INTC_ICDISR16_TINT118 (0x00400000uL) +#define INTC_ICDISR16_TINT119 (0x00800000uL) +#define INTC_ICDISR16_TINT120 (0x01000000uL) +#define INTC_ICDISR16_TINT121 (0x02000000uL) +#define INTC_ICDISR16_TINT122 (0x04000000uL) +#define INTC_ICDISR16_TINT123 (0x08000000uL) +#define INTC_ICDISR16_TINT124 (0x10000000uL) +#define INTC_ICDISR16_TINT125 (0x20000000uL) +#define INTC_ICDISR16_TINT126 (0x40000000uL) +#define INTC_ICDISR16_TINT127 (0x80000000uL) + +#define INTC_ICDISR17_TINT128 (0x00000001uL) +#define INTC_ICDISR17_TINT129 (0x00000002uL) +#define INTC_ICDISR17_TINT130 (0x00000004uL) +#define INTC_ICDISR17_TINT131 (0x00000008uL) +#define INTC_ICDISR17_TINT132 (0x00000010uL) +#define INTC_ICDISR17_TINT133 (0x00000020uL) +#define INTC_ICDISR17_TINT134 (0x00000040uL) +#define INTC_ICDISR17_TINT135 (0x00000080uL) +#define INTC_ICDISR17_TINT136 (0x00000100uL) +#define INTC_ICDISR17_TINT137 (0x00000200uL) +#define INTC_ICDISR17_TINT138 (0x00000400uL) +#define INTC_ICDISR17_TINT139 (0x00000800uL) +#define INTC_ICDISR17_TINT140 (0x00001000uL) +#define INTC_ICDISR17_TINT141 (0x00002000uL) +#define INTC_ICDISR17_TINT142 (0x00004000uL) +#define INTC_ICDISR17_TINT143 (0x00008000uL) +#define INTC_ICDISR17_TINT144 (0x00010000uL) +#define INTC_ICDISR17_TINT145 (0x00020000uL) +#define INTC_ICDISR17_TINT146 (0x00040000uL) +#define INTC_ICDISR17_TINT147 (0x00080000uL) +#define INTC_ICDISR17_TINT148 (0x00100000uL) +#define INTC_ICDISR17_TINT149 (0x00200000uL) +#define INTC_ICDISR17_TINT150 (0x00400000uL) +#define INTC_ICDISR17_TINT151 (0x00800000uL) +#define INTC_ICDISR17_TINT152 (0x01000000uL) +#define INTC_ICDISR17_TINT153 (0x02000000uL) +#define INTC_ICDISR17_TINT154 (0x04000000uL) +#define INTC_ICDISR17_TINT155 (0x08000000uL) +#define INTC_ICDISR17_TINT156 (0x10000000uL) +#define INTC_ICDISR17_TINT157 (0x20000000uL) +#define INTC_ICDISR17_TINT158 (0x40000000uL) +#define INTC_ICDISR17_TINT159 (0x80000000uL) + +#define INTC_ICDISR18_TINT160 (0x00000001uL) +#define INTC_ICDISR18_TINT161 (0x00000002uL) +#define INTC_ICDISR18_TINT162 (0x00000004uL) +#define INTC_ICDISR18_TINT163 (0x00000008uL) +#define INTC_ICDISR18_TINT164 (0x00000010uL) +#define INTC_ICDISR18_TINT165 (0x00000020uL) +#define INTC_ICDISR18_TINT166 (0x00000040uL) +#define INTC_ICDISR18_TINT167 (0x00000080uL) +#define INTC_ICDISR18_TINT168 (0x00000100uL) +#define INTC_ICDISR18_TINT169 (0x00000200uL) +#define INTC_ICDISR18_TINT170 (0x00000400uL) + +#define INTC_ICDISER0_SW0 (0x00000001uL) +#define INTC_ICDISER0_SW1 (0x00000002uL) +#define INTC_ICDISER0_SW2 (0x00000004uL) +#define INTC_ICDISER0_SW3 (0x00000008uL) +#define INTC_ICDISER0_SW4 (0x00000010uL) +#define INTC_ICDISER0_SW5 (0x00000020uL) +#define INTC_ICDISER0_SW6 (0x00000040uL) +#define INTC_ICDISER0_SW7 (0x00000080uL) +#define INTC_ICDISER0_SW8 (0x00000100uL) +#define INTC_ICDISER0_SW9 (0x00000200uL) +#define INTC_ICDISER0_SW10 (0x00000400uL) +#define INTC_ICDISER0_SW11 (0x00000800uL) +#define INTC_ICDISER0_SW12 (0x00001000uL) +#define INTC_ICDISER0_SW13 (0x00002000uL) +#define INTC_ICDISER0_SW14 (0x00004000uL) +#define INTC_ICDISER0_SW15 (0x00008000uL) +#define INTC_ICDISER0_PMUIRQ0 (0x00010000uL) +#define INTC_ICDISER0_COMMRX0 (0x00020000uL) +#define INTC_ICDISER0_COMMTX0 (0x00040000uL) +#define INTC_ICDISER0_CTIIRQ0 (0x00080000uL) + +#define INTC_ICDISER1_IRQ0 (0x00000001uL) +#define INTC_ICDISER1_IRQ1 (0x00000002uL) +#define INTC_ICDISER1_IRQ2 (0x00000004uL) +#define INTC_ICDISER1_IRQ3 (0x00000008uL) +#define INTC_ICDISER1_IRQ4 (0x00000010uL) +#define INTC_ICDISER1_IRQ5 (0x00000020uL) +#define INTC_ICDISER1_IRQ6 (0x00000040uL) +#define INTC_ICDISER1_IRQ7 (0x00000080uL) +#define INTC_ICDISER1_PL310ERR (0x00000100uL) +#define INTC_ICDISER1_DMAINT0 (0x00000200uL) +#define INTC_ICDISER1_DMAINT1 (0x00000400uL) +#define INTC_ICDISER1_DMAINT2 (0x00000800uL) +#define INTC_ICDISER1_DMAINT3 (0x00001000uL) +#define INTC_ICDISER1_DMAINT4 (0x00002000uL) +#define INTC_ICDISER1_DMAINT5 (0x00004000uL) +#define INTC_ICDISER1_DMAINT6 (0x00008000uL) +#define INTC_ICDISER1_DMAINT7 (0x00010000uL) +#define INTC_ICDISER1_DMAINT8 (0x00020000uL) +#define INTC_ICDISER1_DMAINT9 (0x00040000uL) +#define INTC_ICDISER1_DMAINT10 (0x00080000uL) +#define INTC_ICDISER1_DMAINT11 (0x00100000uL) +#define INTC_ICDISER1_DMAINT12 (0x00200000uL) +#define INTC_ICDISER1_DMAINT13 (0x00400000uL) +#define INTC_ICDISER1_DMAINT14 (0x00800000uL) +#define INTC_ICDISER1_DMAINT15 (0x01000000uL) +#define INTC_ICDISER1_DMAERR (0x02000000uL) + +#define INTC_ICDISER2_USBI0 (0x00000200uL) +#define INTC_ICDISER2_USBI1 (0x00000400uL) +#define INTC_ICDISER2_S0_VI_VSYNC0 (0x00000800uL) +#define INTC_ICDISER2_S0_LO_VSYNC0 (0x00001000uL) +#define INTC_ICDISER2_S0_VSYNCERR0 (0x00002000uL) +#define INTC_ICDISER2_GR3_VLINE0 (0x00004000uL) +#define INTC_ICDISER2_S0_VFIELD0 (0x00008000uL) +#define INTC_ICDISER2_IV1_VBUFERR0 (0x00010000uL) +#define INTC_ICDISER2_IV3_VBUFERR0 (0x00020000uL) +#define INTC_ICDISER2_IV5_VBUFERR0 (0x00040000uL) +#define INTC_ICDISER2_IV6_VBUFERR0 (0x00080000uL) +#define INTC_ICDISER2_S0_WLINE0 (0x00100000uL) +#define INTC_ICDISER2_S1_VI_VSYNC0 (0x00200000uL) +#define INTC_ICDISER2_S1_LO_VSYNC0 (0x00400000uL) +#define INTC_ICDISER2_S1_VSYNCERR0 (0x00800000uL) +#define INTC_ICDISER2_S1_VFIELD0 (0x01000000uL) +#define INTC_ICDISER2_IV2_VBUFERR0 (0x02000000uL) +#define INTC_ICDISER2_IV4_VBUFERR0 (0x04000000uL) +#define INTC_ICDISER2_S1_WLINE0 (0x08000000uL) +#define INTC_ICDISER2_OIR_VI_VSYNC0 (0x10000000uL) +#define INTC_ICDISER2_OIR_LO_VSYNC0 (0x20000000uL) +#define INTC_ICDISER2_OIR_VSYNCERR0 (0x40000000uL) +#define INTC_ICDISER2_OIR_VFIELD0 (0x80000000uL) + +#define INTC_ICDISER3_IV7_VBUFERR0 (0x00000001uL) +#define INTC_ICDISER3_IV8_VBUFERR0 (0x00000002uL) +#define INTC_ICDISER3_S0_VI_VSYNC1 (0x00000008uL) +#define INTC_ICDISER3_S0_LO_VSYNC1 (0x00000010uL) +#define INTC_ICDISER3_S0_VSYNCERR1 (0x00000020uL) +#define INTC_ICDISER3_GR3_VLINE1 (0x00000040uL) +#define INTC_ICDISER3_S0_VFIELD1 (0x00000080uL) +#define INTC_ICDISER3_IV1_VBUFERR1 (0x00000100uL) +#define INTC_ICDISER3_IV3_VBUFERR1 (0x00000200uL) +#define INTC_ICDISER3_IV5_VBUFERR1 (0x00000400uL) +#define INTC_ICDISER3_IV6_VBUFERR1 (0x00000800uL) +#define INTC_ICDISER3_S0_WLINE1 (0x00001000uL) +#define INTC_ICDISER3_S1_VI_VSYNC1 (0x00002000uL) +#define INTC_ICDISER3_S1_LO_VSYNC1 (0x00004000uL) +#define INTC_ICDISER3_S1_VSYNCERR1 (0x00008000uL) +#define INTC_ICDISER3_S1_VFIELD1 (0x00010000uL) +#define INTC_ICDISER3_IV2_VBUFERR1 (0x00020000uL) +#define INTC_ICDISER3_IV4_VBUFERR1 (0x00040000uL) +#define INTC_ICDISER3_S1_WLINE1 (0x00080000uL) +#define INTC_ICDISER3_OIR_VI_VSYNC1 (0x00100000uL) +#define INTC_ICDISER3_OIR_LO_VSYNC1 (0x00200000uL) +#define INTC_ICDISER3_OIR_VLINE1 (0x00400000uL) +#define INTC_ICDISER3_OIR_VFIELD1 (0x00800000uL) +#define INTC_ICDISER3_IV7_VBUFERR1 (0x01000000uL) +#define INTC_ICDISER3_IV8_VBUFERR1 (0x02000000uL) +#define INTC_ICDISER3_IMRDI (0x08000000uL) +#define INTC_ICDISER3_IMR2I0 (0x10000000uL) +#define INTC_ICDISER3_IMR2I1 (0x20000000uL) +#define INTC_ICDISER3_JEDI (0x40000000uL) +#define INTC_ICDISER3_JDTI (0x80000000uL) + +#define INTC_ICDISER4_CMP0 (0x00000001uL) +#define INTC_ICDISER4_CMP1 (0x00000002uL) +#define INTC_ICDISER4_INT0 (0x00000004uL) +#define INTC_ICDISER4_INT1 (0x00000008uL) +#define INTC_ICDISER4_INT2 (0x00000010uL) +#define INTC_ICDISER4_INT3 (0x00000020uL) +#define INTC_ICDISER4_OSTM0TINT (0x00000040uL) +#define INTC_ICDISER4_OSTM1TINT (0x00000080uL) +#define INTC_ICDISER4_CMI (0x00000100uL) +#define INTC_ICDISER4_WTOUT (0x00000200uL) +#define INTC_ICDISER4_ITI (0x00000400uL) +#define INTC_ICDISER4_TGI0A (0x00000800uL) +#define INTC_ICDISER4_TGI0B (0x00001000uL) +#define INTC_ICDISER4_TGI0C (0x00002000uL) +#define INTC_ICDISER4_TGI0D (0x00004000uL) +#define INTC_ICDISER4_TGI0V (0x00008000uL) +#define INTC_ICDISER4_TGI0E (0x00010000uL) +#define INTC_ICDISER4_TGI0F (0x00020000uL) +#define INTC_ICDISER4_TGI1A (0x00040000uL) +#define INTC_ICDISER4_TGI1B (0x00080000uL) +#define INTC_ICDISER4_TGI1V (0x00100000uL) +#define INTC_ICDISER4_TGI1U (0x00200000uL) +#define INTC_ICDISER4_TGI2A (0x00400000uL) +#define INTC_ICDISER4_TGI2B (0x00800000uL) +#define INTC_ICDISER4_TGI2V (0x01000000uL) +#define INTC_ICDISER4_TGI2U (0x02000000uL) +#define INTC_ICDISER4_TGI3A (0x04000000uL) +#define INTC_ICDISER4_TGI3B (0x08000000uL) +#define INTC_ICDISER4_TGI3C (0x10000000uL) +#define INTC_ICDISER4_TGI3D (0x20000000uL) +#define INTC_ICDISER4_TGI3V (0x40000000uL) +#define INTC_ICDISER4_TGI4A (0x80000000uL) + +#define INTC_ICDISER5_TGI4B (0x00000001uL) +#define INTC_ICDISER5_TGI4C (0x00000002uL) +#define INTC_ICDISER5_TGI4D (0x00000004uL) +#define INTC_ICDISER5_TGI4V (0x00000008uL) +#define INTC_ICDISER5_CMI1 (0x00000010uL) +#define INTC_ICDISER5_CMI2 (0x00000020uL) +#define INTC_ICDISER5_SGDEI0 (0x00000040uL) +#define INTC_ICDISER5_SGDEI1 (0x00000080uL) +#define INTC_ICDISER5_SGDEI2 (0x00000100uL) +#define INTC_ICDISER5_SGDEI3 (0x00000200uL) +#define INTC_ICDISER5_ADI (0x00000400uL) +#define INTC_ICDISER5_LMTI (0x00000800uL) +#define INTC_ICDISER5_SSII0 (0x00001000uL) +#define INTC_ICDISER5_SSIRXI0 (0x00002000uL) +#define INTC_ICDISER5_SSITXI0 (0x00004000uL) +#define INTC_ICDISER5_SSII1 (0x00008000uL) +#define INTC_ICDISER5_SSIRXI1 (0x00010000uL) +#define INTC_ICDISER5_SSITXI1 (0x00020000uL) +#define INTC_ICDISER5_SSII2 (0x00040000uL) +#define INTC_ICDISER5_SSIRTI2 (0x00080000uL) +#define INTC_ICDISER5_SSII3 (0x00100000uL) +#define INTC_ICDISER5_SSIRXI3 (0x00200000uL) +#define INTC_ICDISER5_SSITXI3 (0x00400000uL) +#define INTC_ICDISER5_SSII4 (0x00800000uL) +#define INTC_ICDISER5_SSIRTI4 (0x01000000uL) +#define INTC_ICDISER5_SSII5 (0x02000000uL) +#define INTC_ICDISER5_SSIRXI5 (0x04000000uL) +#define INTC_ICDISER5_SSITXI5 (0x08000000uL) +#define INTC_ICDISER5_SPDIFI (0x10000000uL) +#define INTC_ICDISER5_INTIICTEI0 (0x20000000uL) +#define INTC_ICDISER5_INTIICRI0 (0x40000000uL) +#define INTC_ICDISER5_INTIICTI0 (0x80000000uL) + +#define INTC_ICDISER6_INTIICSPI0 (0x00000001uL) +#define INTC_ICDISER6_INTIICSTI0 (0x00000002uL) +#define INTC_ICDISER6_INTIICNAKI0 (0x00000004uL) +#define INTC_ICDISER6_INTIICALI0 (0x00000008uL) +#define INTC_ICDISER6_INTIICTMOI0 (0x00000010uL) +#define INTC_ICDISER6_INTIICTEI1 (0x00000020uL) +#define INTC_ICDISER6_INTIICRI1 (0x00000040uL) +#define INTC_ICDISER6_INTIICTI1 (0x00000080uL) +#define INTC_ICDISER6_INTIICSPI1 (0x00000100uL) +#define INTC_ICDISER6_INTIICSTI1 (0x00000200uL) +#define INTC_ICDISER6_INTIICNAKI1 (0x00000400uL) +#define INTC_ICDISER6_INTIICALI1 (0x00000800uL) +#define INTC_ICDISER6_INTIICTMOI1 (0x00001000uL) +#define INTC_ICDISER6_INTIICTEI2 (0x00002000uL) +#define INTC_ICDISER6_INTIICRI2 (0x00004000uL) +#define INTC_ICDISER6_INTIICTI2 (0x00008000uL) +#define INTC_ICDISER6_INTIICSPI2 (0x00010000uL) +#define INTC_ICDISER6_INTIICSTI2 (0x00020000uL) +#define INTC_ICDISER6_INTIICNAKI2 (0x00040000uL) +#define INTC_ICDISER6_INTIICALI2 (0x00080000uL) +#define INTC_ICDISER6_INTIICTMOI2 (0x00100000uL) +#define INTC_ICDISER6_INTIICTEI3 (0x00200000uL) +#define INTC_ICDISER6_INTIICRI3 (0x00400000uL) +#define INTC_ICDISER6_INTIICTI3 (0x00800000uL) +#define INTC_ICDISER6_INTIICSPI3 (0x01000000uL) +#define INTC_ICDISER6_INTIICSTI3 (0x02000000uL) +#define INTC_ICDISER6_INTIICNAKI3 (0x04000000uL) +#define INTC_ICDISER6_INTIICALI3 (0x08000000uL) +#define INTC_ICDISER6_INTIICTMOI3 (0x10000000uL) +#define INTC_ICDISER6_BRI0 (0x20000000uL) +#define INTC_ICDISER6_ERI0 (0x40000000uL) +#define INTC_ICDISER6_RXI0 (0x80000000uL) + +#define INTC_ICDISER7_TXI0 (0x00000001uL) +#define INTC_ICDISER7_BRI1 (0x00000002uL) +#define INTC_ICDISER7_ERI1 (0x00000004uL) +#define INTC_ICDISER7_RXI1 (0x00000008uL) +#define INTC_ICDISER7_TXI1 (0x00000010uL) +#define INTC_ICDISER7_BRI2 (0x00000020uL) +#define INTC_ICDISER7_ERI2 (0x00000040uL) +#define INTC_ICDISER7_RXI2 (0x00000080uL) +#define INTC_ICDISER7_TXI2 (0x00000100uL) +#define INTC_ICDISER7_BRI3 (0x00000200uL) +#define INTC_ICDISER7_ERI3 (0x00000400uL) +#define INTC_ICDISER7_RXI3 (0x00000800uL) +#define INTC_ICDISER7_TXI3 (0x00001000uL) +#define INTC_ICDISER7_BRI4 (0x00002000uL) +#define INTC_ICDISER7_ERI4 (0x00004000uL) +#define INTC_ICDISER7_RXI4 (0x00008000uL) +#define INTC_ICDISER7_TXI4 (0x00010000uL) +#define INTC_ICDISER7_BRI5 (0x00020000uL) +#define INTC_ICDISER7_ERI5 (0x00040000uL) +#define INTC_ICDISER7_RXI5 (0x00080000uL) +#define INTC_ICDISER7_TXI5 (0x00100000uL) +#define INTC_ICDISER7_BRI6 (0x00200000uL) +#define INTC_ICDISER7_ERI6 (0x00400000uL) +#define INTC_ICDISER7_RXI6 (0x00800000uL) +#define INTC_ICDISER7_TXI6 (0x01000000uL) +#define INTC_ICDISER7_BRI7 (0x02000000uL) +#define INTC_ICDISER7_ERI7 (0x04000000uL) +#define INTC_ICDISER7_RXI7 (0x08000000uL) +#define INTC_ICDISER7_TXI7 (0x10000000uL) +#define INTC_ICDISER7_INTRCANGERR (0x20000000uL) +#define INTC_ICDISER7_INTRCANGRECC (0x40000000uL) +#define INTC_ICDISER7_INTRCAN0REC (0x80000000uL) + +#define INTC_ICDISER8_INTRCAN0ERR (0x00000001uL) +#define INTC_ICDISER8_INTRCAN0TRX (0x00000002uL) +#define INTC_ICDISER8_INTRCAN1REC (0x00000004uL) +#define INTC_ICDISER8_INTRCAN1ERR (0x00000008uL) +#define INTC_ICDISER8_INTRCAN1TRX (0x00000010uL) +#define INTC_ICDISER8_INTRCAN2REC (0x00000020uL) +#define INTC_ICDISER8_INTRCAN2ERR (0x00000040uL) +#define INTC_ICDISER8_INTRCAN2TRX (0x00000080uL) +#define INTC_ICDISER8_INTRCAN3REC (0x00000100uL) +#define INTC_ICDISER8_INTRCAN3ERR (0x00000200uL) +#define INTC_ICDISER8_INTRCAN3TRX (0x00000400uL) +#define INTC_ICDISER8_INTRCAN4REC (0x00000800uL) +#define INTC_ICDISER8_INTRCAN4ERR (0x00001000uL) +#define INTC_ICDISER8_INTRCAN4TRX (0x00002000uL) +#define INTC_ICDISER8_SPEI0 (0x00004000uL) +#define INTC_ICDISER8_SPRI0 (0x00008000uL) +#define INTC_ICDISER8_SPTI0 (0x00010000uL) +#define INTC_ICDISER8_SPEI1 (0x00020000uL) +#define INTC_ICDISER8_SPRI1 (0x00040000uL) +#define INTC_ICDISER8_SPTI1 (0x00080000uL) +#define INTC_ICDISER8_SPEI2 (0x00100000uL) +#define INTC_ICDISER8_SPRI2 (0x00200000uL) +#define INTC_ICDISER8_SPTI2 (0x00400000uL) +#define INTC_ICDISER8_SPEI3 (0x00800000uL) +#define INTC_ICDISER8_SPRI3 (0x01000000uL) +#define INTC_ICDISER8_SPTI3 (0x02000000uL) +#define INTC_ICDISER8_SPEI4 (0x04000000uL) +#define INTC_ICDISER8_SPRI4 (0x08000000uL) +#define INTC_ICDISER8_SPTI4 (0x10000000uL) +#define INTC_ICDISER8_IEBBTD (0x20000000uL) +#define INTC_ICDISER8_IEBBTERR (0x40000000uL) +#define INTC_ICDISER8_IEBBTSTA (0x80000000uL) + +#define INTC_ICDISER9_IEBBTV (0x00000001uL) +#define INTC_ICDISER9_ISY (0x00000002uL) +#define INTC_ICDISER9_IERR (0x00000004uL) +#define INTC_ICDISER9_ITARG (0x00000008uL) +#define INTC_ICDISER9_ISEC (0x00000010uL) +#define INTC_ICDISER9_IBUF (0x00000020uL) +#define INTC_ICDISER9_IREADY (0x00000040uL) +#define INTC_ICDISER9_FLSTE (0x00000080uL) +#define INTC_ICDISER9_FLTENDI (0x00000100uL) +#define INTC_ICDISER9_FLTREQ0I (0x00000200uL) +#define INTC_ICDISER9_FLTREQ1I (0x00000400uL) +#define INTC_ICDISER9_MMC0 (0x00000800uL) +#define INTC_ICDISER9_MMC1 (0x00001000uL) +#define INTC_ICDISER9_MMC2 (0x00002000uL) +#define INTC_ICDISER9_SDHI0_3 (0x00004000uL) +#define INTC_ICDISER9_SDHI0_0 (0x00008000uL) +#define INTC_ICDISER9_SDHI0_1 (0x00010000uL) +#define INTC_ICDISER9_SDHI1_3 (0x00020000uL) +#define INTC_ICDISER9_SDHI1_0 (0x00040000uL) +#define INTC_ICDISER9_SDHI1_1 (0x00080000uL) +#define INTC_ICDISER9_ARM (0x00100000uL) +#define INTC_ICDISER9_PRD (0x00200000uL) +#define INTC_ICDISER9_CUP (0x00400000uL) +#define INTC_ICDISER9_SCUAI0 (0x00800000uL) +#define INTC_ICDISER9_SCUAI1 (0x01000000uL) +#define INTC_ICDISER9_SCUFDI0 (0x02000000uL) +#define INTC_ICDISER9_SCUFDI1 (0x04000000uL) +#define INTC_ICDISER9_SCUFDI2 (0x08000000uL) +#define INTC_ICDISER9_SCUFDI3 (0x10000000uL) +#define INTC_ICDISER9_SCUFUI0 (0x20000000uL) +#define INTC_ICDISER9_SCUFUI1 (0x40000000uL) +#define INTC_ICDISER9_SCUFUI2 (0x80000000uL) + +#define INTC_ICDISER10_SCUFUI3 (0x00000001uL) +#define INTC_ICDISER10_SCUDVI0 (0x00000002uL) +#define INTC_ICDISER10_SCUDVI1 (0x00000004uL) +#define INTC_ICDISER10_SCUDVI2 (0x00000008uL) +#define INTC_ICDISER10_SCUDVI3 (0x00000010uL) +#define INTC_ICDISER10_MLB_CINT (0x00000020uL) +#define INTC_ICDISER10_MLB_SINT (0x00000040uL) +#define INTC_ICDISER10_DRC0 (0x00000080uL) +#define INTC_ICDISER10_DRC1 (0x00000100uL) +#define INTC_ICDISER10_LINI0_INT_T (0x00000800uL) +#define INTC_ICDISER10_LINI0_INT_R (0x00001000uL) +#define INTC_ICDISER10_LINI0_INT_S (0x00002000uL) +#define INTC_ICDISER10_LINI0_INT_M (0x00004000uL) +#define INTC_ICDISER10_LINI1_INT_T (0x00008000uL) +#define INTC_ICDISER10_LINI1_INT_R (0x00010000uL) +#define INTC_ICDISER10_LINI1_INT_S (0x00020000uL) +#define INTC_ICDISER10_LINI1_INT_M (0x00040000uL) +#define INTC_ICDISER10_ERI0 (0x08000000uL) +#define INTC_ICDISER10_RXI0 (0x10000000uL) +#define INTC_ICDISER10_TXI0 (0x20000000uL) +#define INTC_ICDISER10_TEI0 (0x40000000uL) +#define INTC_ICDISER10_ERI1 (0x80000000uL) + +#define INTC_ICDISER11_RXI1 (0x00000001uL) +#define INTC_ICDISER11_TXI1 (0x00000002uL) +#define INTC_ICDISER11_TEI1 (0x00000004uL) +#define INTC_ICDISER11_AVBI_DATA (0x00000008uL) +#define INTC_ICDISER11_AVBI_ERROR (0x00000010uL) +#define INTC_ICDISER11_AVBI_MANAGE (0x00000020uL) +#define INTC_ICDISER11_AVBI_MAC (0x00000040uL) +#define INTC_ICDISER11_ETHERI (0x00000080uL) +#define INTC_ICDISER11_CEUI (0x00001000uL) +#define INTC_ICDISER11_H2XMLB_ERRINT (0x20000000uL) +#define INTC_ICDISER11_H2XIC1_ERRINT (0x40000000uL) +#define INTC_ICDISER11_X2HPERI1_ERRINT (0x80000000uL) + +#define INTC_ICDISER12_X2HPERI2_ERRINT (0x00000001uL) +#define INTC_ICDISER12_X2HPERI34_ERRINT (0x00000002uL) +#define INTC_ICDISER12_X2HPERI5_ERRINT (0x00000004uL) +#define INTC_ICDISER12_X2HPERI67_ERRINT (0x00000008uL) +#define INTC_ICDISER12_X2HDBGR_ERRINT (0x00000010uL) +#define INTC_ICDISER12_X2HBSC_ERRINT (0x00000020uL) +#define INTC_ICDISER12_X2HSPI1_ERRINT (0x00000040uL) +#define INTC_ICDISER12_X2HSPI2_ERRINT (0x00000080uL) +#define INTC_ICDISER12_PRRI (0x00000100uL) +#define INTC_ICDISER12_IFEI0 (0x00000200uL) +#define INTC_ICDISER12_OFFI0 (0x00000400uL) +#define INTC_ICDISER12_PFVEI0 (0x00000800uL) +#define INTC_ICDISER12_IFEI1 (0x00001000uL) +#define INTC_ICDISER12_OFFI1 (0x00002000uL) +#define INTC_ICDISER12_PFVEI1 (0x00004000uL) + +#define INTC_ICDISER13_TINT0 (0x00000001uL) +#define INTC_ICDISER13_TINT1 (0x00000002uL) +#define INTC_ICDISER13_TINT2 (0x00000004uL) +#define INTC_ICDISER13_TINT3 (0x00000008uL) +#define INTC_ICDISER13_TINT4 (0x00000010uL) +#define INTC_ICDISER13_TINT5 (0x00000020uL) +#define INTC_ICDISER13_TINT6 (0x00000040uL) +#define INTC_ICDISER13_TINT7 (0x00000080uL) +#define INTC_ICDISER13_TINT8 (0x00000100uL) +#define INTC_ICDISER13_TINT9 (0x00000200uL) +#define INTC_ICDISER13_TINT10 (0x00000400uL) +#define INTC_ICDISER13_TINT11 (0x00000800uL) +#define INTC_ICDISER13_TINT12 (0x00001000uL) +#define INTC_ICDISER13_TINT13 (0x00002000uL) +#define INTC_ICDISER13_TINT14 (0x00004000uL) +#define INTC_ICDISER13_TINT15 (0x00008000uL) +#define INTC_ICDISER13_TINT16 (0x00010000uL) +#define INTC_ICDISER13_TINT17 (0x00020000uL) +#define INTC_ICDISER13_TINT18 (0x00040000uL) +#define INTC_ICDISER13_TINT19 (0x00080000uL) +#define INTC_ICDISER13_TINT20 (0x00100000uL) +#define INTC_ICDISER13_TINT21 (0x00200000uL) +#define INTC_ICDISER13_TINT22 (0x00400000uL) +#define INTC_ICDISER13_TINT23 (0x00800000uL) +#define INTC_ICDISER13_TINT24 (0x01000000uL) +#define INTC_ICDISER13_TINT25 (0x02000000uL) +#define INTC_ICDISER13_TINT26 (0x04000000uL) +#define INTC_ICDISER13_TINT27 (0x08000000uL) +#define INTC_ICDISER13_TINT28 (0x10000000uL) +#define INTC_ICDISER13_TINT29 (0x20000000uL) +#define INTC_ICDISER13_TINT30 (0x40000000uL) +#define INTC_ICDISER13_TINT31 (0x80000000uL) + +#define INTC_ICDISER14_TINT32 (0x00000001uL) +#define INTC_ICDISER14_TINT33 (0x00000002uL) +#define INTC_ICDISER14_TINT34 (0x00000004uL) +#define INTC_ICDISER14_TINT35 (0x00000008uL) +#define INTC_ICDISER14_TINT36 (0x00000010uL) +#define INTC_ICDISER14_TINT37 (0x00000020uL) +#define INTC_ICDISER14_TINT38 (0x00000040uL) +#define INTC_ICDISER14_TINT39 (0x00000080uL) +#define INTC_ICDISER14_TINT40 (0x00000100uL) +#define INTC_ICDISER14_TINT41 (0x00000200uL) +#define INTC_ICDISER14_TINT42 (0x00000400uL) +#define INTC_ICDISER14_TINT43 (0x00000800uL) +#define INTC_ICDISER14_TINT44 (0x00001000uL) +#define INTC_ICDISER14_TINT45 (0x00002000uL) +#define INTC_ICDISER14_TINT46 (0x00004000uL) +#define INTC_ICDISER14_TINT47 (0x00008000uL) +#define INTC_ICDISER14_TINT48 (0x00010000uL) +#define INTC_ICDISER14_TINT49 (0x00020000uL) +#define INTC_ICDISER14_TINT50 (0x00040000uL) +#define INTC_ICDISER14_TINT51 (0x00080000uL) +#define INTC_ICDISER14_TINT52 (0x00100000uL) +#define INTC_ICDISER14_TINT53 (0x00200000uL) +#define INTC_ICDISER14_TINT54 (0x00400000uL) +#define INTC_ICDISER14_TINT55 (0x00800000uL) +#define INTC_ICDISER14_TINT56 (0x01000000uL) +#define INTC_ICDISER14_TINT57 (0x02000000uL) +#define INTC_ICDISER14_TINT58 (0x04000000uL) +#define INTC_ICDISER14_TINT59 (0x08000000uL) +#define INTC_ICDISER14_TINT60 (0x10000000uL) +#define INTC_ICDISER14_TINT61 (0x20000000uL) +#define INTC_ICDISER14_TINT62 (0x40000000uL) +#define INTC_ICDISER14_TINT63 (0x80000000uL) + +#define INTC_ICDISER15_TINT64 (0x00000001uL) +#define INTC_ICDISER15_TINT65 (0x00000002uL) +#define INTC_ICDISER15_TINT66 (0x00000004uL) +#define INTC_ICDISER15_TINT67 (0x00000008uL) +#define INTC_ICDISER15_TINT68 (0x00000010uL) +#define INTC_ICDISER15_TINT69 (0x00000020uL) +#define INTC_ICDISER15_TINT70 (0x00000040uL) +#define INTC_ICDISER15_TINT71 (0x00000080uL) +#define INTC_ICDISER15_TINT72 (0x00000100uL) +#define INTC_ICDISER15_TINT73 (0x00000200uL) +#define INTC_ICDISER15_TINT74 (0x00000400uL) +#define INTC_ICDISER15_TINT75 (0x00000800uL) +#define INTC_ICDISER15_TINT76 (0x00001000uL) +#define INTC_ICDISER15_TINT77 (0x00002000uL) +#define INTC_ICDISER15_TINT78 (0x00004000uL) +#define INTC_ICDISER15_TINT79 (0x00008000uL) +#define INTC_ICDISER15_TINT80 (0x00010000uL) +#define INTC_ICDISER15_TINT81 (0x00020000uL) +#define INTC_ICDISER15_TINT82 (0x00040000uL) +#define INTC_ICDISER15_TINT83 (0x00080000uL) +#define INTC_ICDISER15_TINT84 (0x00100000uL) +#define INTC_ICDISER15_TINT85 (0x00200000uL) +#define INTC_ICDISER15_TINT86 (0x00400000uL) +#define INTC_ICDISER15_TINT87 (0x00800000uL) +#define INTC_ICDISER15_TINT88 (0x01000000uL) +#define INTC_ICDISER15_TINT89 (0x02000000uL) +#define INTC_ICDISER15_TINT90 (0x04000000uL) +#define INTC_ICDISER15_TINT91 (0x08000000uL) +#define INTC_ICDISER15_TINT92 (0x10000000uL) +#define INTC_ICDISER15_TINT93 (0x20000000uL) +#define INTC_ICDISER15_TINT94 (0x40000000uL) +#define INTC_ICDISER15_TINT95 (0x80000000uL) + +#define INTC_ICDISER16_TINT96 (0x00000001uL) +#define INTC_ICDISER16_TINT97 (0x00000002uL) +#define INTC_ICDISER16_TINT98 (0x00000004uL) +#define INTC_ICDISER16_TINT99 (0x00000008uL) +#define INTC_ICDISER16_TINT100 (0x00000010uL) +#define INTC_ICDISER16_TINT101 (0x00000020uL) +#define INTC_ICDISER16_TINT102 (0x00000040uL) +#define INTC_ICDISER16_TINT103 (0x00000080uL) +#define INTC_ICDISER16_TINT104 (0x00000100uL) +#define INTC_ICDISER16_TINT105 (0x00000200uL) +#define INTC_ICDISER16_TINT106 (0x00000400uL) +#define INTC_ICDISER16_TINT107 (0x00000800uL) +#define INTC_ICDISER16_TINT108 (0x00001000uL) +#define INTC_ICDISER16_TINT109 (0x00002000uL) +#define INTC_ICDISER16_TINT110 (0x00004000uL) +#define INTC_ICDISER16_TINT111 (0x00008000uL) +#define INTC_ICDISER16_TINT112 (0x00010000uL) +#define INTC_ICDISER16_TINT113 (0x00020000uL) +#define INTC_ICDISER16_TINT114 (0x00040000uL) +#define INTC_ICDISER16_TINT115 (0x00080000uL) +#define INTC_ICDISER16_TINT116 (0x00100000uL) +#define INTC_ICDISER16_TINT117 (0x00200000uL) +#define INTC_ICDISER16_TINT118 (0x00400000uL) +#define INTC_ICDISER16_TINT119 (0x00800000uL) +#define INTC_ICDISER16_TINT120 (0x01000000uL) +#define INTC_ICDISER16_TINT121 (0x02000000uL) +#define INTC_ICDISER16_TINT122 (0x04000000uL) +#define INTC_ICDISER16_TINT123 (0x08000000uL) +#define INTC_ICDISER16_TINT124 (0x10000000uL) +#define INTC_ICDISER16_TINT125 (0x20000000uL) +#define INTC_ICDISER16_TINT126 (0x40000000uL) +#define INTC_ICDISER16_TINT127 (0x80000000uL) + +#define INTC_ICDISER17_TINT128 (0x00000001uL) +#define INTC_ICDISER17_TINT129 (0x00000002uL) +#define INTC_ICDISER17_TINT130 (0x00000004uL) +#define INTC_ICDISER17_TINT131 (0x00000008uL) +#define INTC_ICDISER17_TINT132 (0x00000010uL) +#define INTC_ICDISER17_TINT133 (0x00000020uL) +#define INTC_ICDISER17_TINT134 (0x00000040uL) +#define INTC_ICDISER17_TINT135 (0x00000080uL) +#define INTC_ICDISER17_TINT136 (0x00000100uL) +#define INTC_ICDISER17_TINT137 (0x00000200uL) +#define INTC_ICDISER17_TINT138 (0x00000400uL) +#define INTC_ICDISER17_TINT139 (0x00000800uL) +#define INTC_ICDISER17_TINT140 (0x00001000uL) +#define INTC_ICDISER17_TINT141 (0x00002000uL) +#define INTC_ICDISER17_TINT142 (0x00004000uL) +#define INTC_ICDISER17_TINT143 (0x00008000uL) +#define INTC_ICDISER17_TINT144 (0x00010000uL) +#define INTC_ICDISER17_TINT145 (0x00020000uL) +#define INTC_ICDISER17_TINT146 (0x00040000uL) +#define INTC_ICDISER17_TINT147 (0x00080000uL) +#define INTC_ICDISER17_TINT148 (0x00100000uL) +#define INTC_ICDISER17_TINT149 (0x00200000uL) +#define INTC_ICDISER17_TINT150 (0x00400000uL) +#define INTC_ICDISER17_TINT151 (0x00800000uL) +#define INTC_ICDISER17_TINT152 (0x01000000uL) +#define INTC_ICDISER17_TINT153 (0x02000000uL) +#define INTC_ICDISER17_TINT154 (0x04000000uL) +#define INTC_ICDISER17_TINT155 (0x08000000uL) +#define INTC_ICDISER17_TINT156 (0x10000000uL) +#define INTC_ICDISER17_TINT157 (0x20000000uL) +#define INTC_ICDISER17_TINT158 (0x40000000uL) +#define INTC_ICDISER17_TINT159 (0x80000000uL) + +#define INTC_ICDISER18_TINT160 (0x00000001uL) +#define INTC_ICDISER18_TINT161 (0x00000002uL) +#define INTC_ICDISER18_TINT162 (0x00000004uL) +#define INTC_ICDISER18_TINT163 (0x00000008uL) +#define INTC_ICDISER18_TINT164 (0x00000010uL) +#define INTC_ICDISER18_TINT165 (0x00000020uL) +#define INTC_ICDISER18_TINT166 (0x00000040uL) +#define INTC_ICDISER18_TINT167 (0x00000080uL) +#define INTC_ICDISER18_TINT168 (0x00000100uL) +#define INTC_ICDISER18_TINT169 (0x00000200uL) +#define INTC_ICDISER18_TINT170 (0x00000400uL) + +#define INTC_ICDICER0_SW0 (0x00000001uL) +#define INTC_ICDICER0_SW1 (0x00000002uL) +#define INTC_ICDICER0_SW2 (0x00000004uL) +#define INTC_ICDICER0_SW3 (0x00000008uL) +#define INTC_ICDICER0_SW4 (0x00000010uL) +#define INTC_ICDICER0_SW5 (0x00000020uL) +#define INTC_ICDICER0_SW6 (0x00000040uL) +#define INTC_ICDICER0_SW7 (0x00000080uL) +#define INTC_ICDICER0_SW8 (0x00000100uL) +#define INTC_ICDICER0_SW9 (0x00000200uL) +#define INTC_ICDICER0_SW10 (0x00000400uL) +#define INTC_ICDICER0_SW11 (0x00000800uL) +#define INTC_ICDICER0_SW12 (0x00001000uL) +#define INTC_ICDICER0_SW13 (0x00002000uL) +#define INTC_ICDICER0_SW14 (0x00004000uL) +#define INTC_ICDICER0_SW15 (0x00008000uL) +#define INTC_ICDICER0_PMUIRQ0 (0x00010000uL) +#define INTC_ICDICER0_COMMRX0 (0x00020000uL) +#define INTC_ICDICER0_COMMTX0 (0x00040000uL) +#define INTC_ICDICER0_CTIIRQ0 (0x00080000uL) + +#define INTC_ICDICER1_IRQ0 (0x00000001uL) +#define INTC_ICDICER1_IRQ1 (0x00000002uL) +#define INTC_ICDICER1_IRQ2 (0x00000004uL) +#define INTC_ICDICER1_IRQ3 (0x00000008uL) +#define INTC_ICDICER1_IRQ4 (0x00000010uL) +#define INTC_ICDICER1_IRQ5 (0x00000020uL) +#define INTC_ICDICER1_IRQ6 (0x00000040uL) +#define INTC_ICDICER1_IRQ7 (0x00000080uL) +#define INTC_ICDICER1_PL310ERR (0x00000100uL) +#define INTC_ICDICER1_DMAINT0 (0x00000200uL) +#define INTC_ICDICER1_DMAINT1 (0x00000400uL) +#define INTC_ICDICER1_DMAINT2 (0x00000800uL) +#define INTC_ICDICER1_DMAINT3 (0x00001000uL) +#define INTC_ICDICER1_DMAINT4 (0x00002000uL) +#define INTC_ICDICER1_DMAINT5 (0x00004000uL) +#define INTC_ICDICER1_DMAINT6 (0x00008000uL) +#define INTC_ICDICER1_DMAINT7 (0x00010000uL) +#define INTC_ICDICER1_DMAINT8 (0x00020000uL) +#define INTC_ICDICER1_DMAINT9 (0x00040000uL) +#define INTC_ICDICER1_DMAINT10 (0x00080000uL) +#define INTC_ICDICER1_DMAINT11 (0x00100000uL) +#define INTC_ICDICER1_DMAINT12 (0x00200000uL) +#define INTC_ICDICER1_DMAINT13 (0x00400000uL) +#define INTC_ICDICER1_DMAINT14 (0x00800000uL) +#define INTC_ICDICER1_DMAINT15 (0x01000000uL) +#define INTC_ICDICER1_DMAERR (0x02000000uL) + +#define INTC_ICDICER2_USBI0 (0x00000200uL) +#define INTC_ICDICER2_USBI1 (0x00000400uL) +#define INTC_ICDICER2_S0_VI_VSYNC0 (0x00000800uL) +#define INTC_ICDICER2_S0_LO_VSYNC0 (0x00001000uL) +#define INTC_ICDICER2_S0_VSYNCERR0 (0x00002000uL) +#define INTC_ICDICER2_GR3_VLINE0 (0x00004000uL) +#define INTC_ICDICER2_S0_VFIELD0 (0x00008000uL) +#define INTC_ICDICER2_IV1_VBUFERR0 (0x00010000uL) +#define INTC_ICDICER2_IV3_VBUFERR0 (0x00020000uL) +#define INTC_ICDICER2_IV5_VBUFERR0 (0x00040000uL) +#define INTC_ICDICER2_IV6_VBUFERR0 (0x00080000uL) +#define INTC_ICDICER2_S0_WLINE0 (0x00100000uL) +#define INTC_ICDICER2_S1_VI_VSYNC0 (0x00200000uL) +#define INTC_ICDICER2_S1_LO_VSYNC0 (0x00400000uL) +#define INTC_ICDICER2_S1_VSYNCERR0 (0x00800000uL) +#define INTC_ICDICER2_S1_VFIELD0 (0x01000000uL) +#define INTC_ICDICER2_IV2_VBUFERR0 (0x02000000uL) +#define INTC_ICDICER2_IV4_VBUFERR0 (0x04000000uL) +#define INTC_ICDICER2_S1_WLINE0 (0x08000000uL) +#define INTC_ICDICER2_OIR_VI_VSYNC0 (0x10000000uL) +#define INTC_ICDICER2_OIR_LO_VSYNC0 (0x20000000uL) +#define INTC_ICDICER2_OIR_VSYNCERR0 (0x40000000uL) +#define INTC_ICDICER2_OIR_VFIELD0 (0x80000000uL) + +#define INTC_ICDICER3_IV7_VBUFERR0 (0x00000001uL) +#define INTC_ICDICER3_IV8_VBUFERR0 (0x00000002uL) +#define INTC_ICDICER3_S0_VI_VSYNC1 (0x00000008uL) +#define INTC_ICDICER3_S0_LO_VSYNC1 (0x00000010uL) +#define INTC_ICDICER3_S0_VSYNCERR1 (0x00000020uL) +#define INTC_ICDICER3_GR3_VLINE1 (0x00000040uL) +#define INTC_ICDICER3_S0_VFIELD1 (0x00000080uL) +#define INTC_ICDICER3_IV1_VBUFERR1 (0x00000100uL) +#define INTC_ICDICER3_IV3_VBUFERR1 (0x00000200uL) +#define INTC_ICDICER3_IV5_VBUFERR1 (0x00000400uL) +#define INTC_ICDICER3_IV6_VBUFERR1 (0x00000800uL) +#define INTC_ICDICER3_S0_WLINE1 (0x00001000uL) +#define INTC_ICDICER3_S1_VI_VSYNC1 (0x00002000uL) +#define INTC_ICDICER3_S1_LO_VSYNC1 (0x00004000uL) +#define INTC_ICDICER3_S1_VSYNCERR1 (0x00008000uL) +#define INTC_ICDICER3_S1_VFIELD1 (0x00010000uL) +#define INTC_ICDICER3_IV2_VBUFERR1 (0x00020000uL) +#define INTC_ICDICER3_IV4_VBUFERR1 (0x00040000uL) +#define INTC_ICDICER3_S1_WLINE1 (0x00080000uL) +#define INTC_ICDICER3_OIR_VI_VSYNC1 (0x00100000uL) +#define INTC_ICDICER3_OIR_LO_VSYNC1 (0x00200000uL) +#define INTC_ICDICER3_OIR_VLINE1 (0x00400000uL) +#define INTC_ICDICER3_OIR_VFIELD1 (0x00800000uL) +#define INTC_ICDICER3_IV7_VBUFERR1 (0x01000000uL) +#define INTC_ICDICER3_IV8_VBUFERR1 (0x02000000uL) +#define INTC_ICDICER3_IMRDI (0x08000000uL) +#define INTC_ICDICER3_IMR2I0 (0x10000000uL) +#define INTC_ICDICER3_IMR2I1 (0x20000000uL) +#define INTC_ICDICER3_JEDI (0x40000000uL) +#define INTC_ICDICER3_JDTI (0x80000000uL) + +#define INTC_ICDICER4_CMP0 (0x00000001uL) +#define INTC_ICDICER4_CMP1 (0x00000002uL) +#define INTC_ICDICER4_INT0 (0x00000004uL) +#define INTC_ICDICER4_INT1 (0x00000008uL) +#define INTC_ICDICER4_INT2 (0x00000010uL) +#define INTC_ICDICER4_INT3 (0x00000020uL) +#define INTC_ICDICER4_OSTM0TINT (0x00000040uL) +#define INTC_ICDICER4_OSTM1TINT (0x00000080uL) +#define INTC_ICDICER4_CMI (0x00000100uL) +#define INTC_ICDICER4_WTOUT (0x00000200uL) +#define INTC_ICDICER4_ITI (0x00000400uL) +#define INTC_ICDICER4_TGI0A (0x00000800uL) +#define INTC_ICDICER4_TGI0B (0x00001000uL) +#define INTC_ICDICER4_TGI0C (0x00002000uL) +#define INTC_ICDICER4_TGI0D (0x00004000uL) +#define INTC_ICDICER4_TGI0V (0x00008000uL) +#define INTC_ICDICER4_TGI0E (0x00010000uL) +#define INTC_ICDICER4_TGI0F (0x00020000uL) +#define INTC_ICDICER4_TGI1A (0x00040000uL) +#define INTC_ICDICER4_TGI1B (0x00080000uL) +#define INTC_ICDICER4_TGI1V (0x00100000uL) +#define INTC_ICDICER4_TGI1U (0x00200000uL) +#define INTC_ICDICER4_TGI2A (0x00400000uL) +#define INTC_ICDICER4_TGI2B (0x00800000uL) +#define INTC_ICDICER4_TGI2V (0x01000000uL) +#define INTC_ICDICER4_TGI2U (0x02000000uL) +#define INTC_ICDICER4_TGI3A (0x04000000uL) +#define INTC_ICDICER4_TGI3B (0x08000000uL) +#define INTC_ICDICER4_TGI3C (0x10000000uL) +#define INTC_ICDICER4_TGI3D (0x20000000uL) +#define INTC_ICDICER4_TGI3V (0x40000000uL) +#define INTC_ICDICER4_TGI4A (0x80000000uL) + +#define INTC_ICDICER5_TGI4B (0x00000001uL) +#define INTC_ICDICER5_TGI4C (0x00000002uL) +#define INTC_ICDICER5_TGI4D (0x00000004uL) +#define INTC_ICDICER5_TGI4V (0x00000008uL) +#define INTC_ICDICER5_CMI1 (0x00000010uL) +#define INTC_ICDICER5_CMI2 (0x00000020uL) +#define INTC_ICDICER5_SGDEI0 (0x00000040uL) +#define INTC_ICDICER5_SGDEI1 (0x00000080uL) +#define INTC_ICDICER5_SGDEI2 (0x00000100uL) +#define INTC_ICDICER5_SGDEI3 (0x00000200uL) +#define INTC_ICDICER5_ADI (0x00000400uL) +#define INTC_ICDICER5_LMTI (0x00000800uL) +#define INTC_ICDICER5_SSII0 (0x00001000uL) +#define INTC_ICDICER5_SSIRXI0 (0x00002000uL) +#define INTC_ICDICER5_SSITXI0 (0x00004000uL) +#define INTC_ICDICER5_SSII1 (0x00008000uL) +#define INTC_ICDICER5_SSIRXI1 (0x00010000uL) +#define INTC_ICDICER5_SSITXI1 (0x00020000uL) +#define INTC_ICDICER5_SSII2 (0x00040000uL) +#define INTC_ICDICER5_SSIRTI2 (0x00080000uL) +#define INTC_ICDICER5_SSII3 (0x00100000uL) +#define INTC_ICDICER5_SSIRXI3 (0x00200000uL) +#define INTC_ICDICER5_SSITXI3 (0x00400000uL) +#define INTC_ICDICER5_SSII4 (0x00800000uL) +#define INTC_ICDICER5_SSIRTI4 (0x01000000uL) +#define INTC_ICDICER5_SSII5 (0x02000000uL) +#define INTC_ICDICER5_SSIRXI5 (0x04000000uL) +#define INTC_ICDICER5_SSITXI5 (0x08000000uL) +#define INTC_ICDICER5_SPDIFI (0x10000000uL) +#define INTC_ICDICER5_INTIICTEI0 (0x20000000uL) +#define INTC_ICDICER5_INTIICRI0 (0x40000000uL) +#define INTC_ICDICER5_INTIICTI0 (0x80000000uL) + +#define INTC_ICDICER6_INTIICSPI0 (0x00000001uL) +#define INTC_ICDICER6_INTIICSTI0 (0x00000002uL) +#define INTC_ICDICER6_INTIICNAKI0 (0x00000004uL) +#define INTC_ICDICER6_INTIICALI0 (0x00000008uL) +#define INTC_ICDICER6_INTIICTMOI0 (0x00000010uL) +#define INTC_ICDICER6_INTIICTEI1 (0x00000020uL) +#define INTC_ICDICER6_INTIICRI1 (0x00000040uL) +#define INTC_ICDICER6_INTIICTI1 (0x00000080uL) +#define INTC_ICDICER6_INTIICSPI1 (0x00000100uL) +#define INTC_ICDICER6_INTIICSTI1 (0x00000200uL) +#define INTC_ICDICER6_INTIICNAKI1 (0x00000400uL) +#define INTC_ICDICER6_INTIICALI1 (0x00000800uL) +#define INTC_ICDICER6_INTIICTMOI1 (0x00001000uL) +#define INTC_ICDICER6_INTIICTEI2 (0x00002000uL) +#define INTC_ICDICER6_INTIICRI2 (0x00004000uL) +#define INTC_ICDICER6_INTIICTI2 (0x00008000uL) +#define INTC_ICDICER6_INTIICSPI2 (0x00010000uL) +#define INTC_ICDICER6_INTIICSTI2 (0x00020000uL) +#define INTC_ICDICER6_INTIICNAKI2 (0x00040000uL) +#define INTC_ICDICER6_INTIICALI2 (0x00080000uL) +#define INTC_ICDICER6_INTIICTMOI2 (0x00100000uL) +#define INTC_ICDICER6_INTIICTEI3 (0x00200000uL) +#define INTC_ICDICER6_INTIICRI3 (0x00400000uL) +#define INTC_ICDICER6_INTIICTI3 (0x00800000uL) +#define INTC_ICDICER6_INTIICSPI3 (0x01000000uL) +#define INTC_ICDICER6_INTIICSTI3 (0x02000000uL) +#define INTC_ICDICER6_INTIICNAKI3 (0x04000000uL) +#define INTC_ICDICER6_INTIICALI3 (0x08000000uL) +#define INTC_ICDICER6_INTIICTMOI3 (0x10000000uL) +#define INTC_ICDICER6_BRI0 (0x20000000uL) +#define INTC_ICDICER6_ERI0 (0x40000000uL) +#define INTC_ICDICER6_RXI0 (0x80000000uL) + +#define INTC_ICDICER7_TXI0 (0x00000001uL) +#define INTC_ICDICER7_BRI1 (0x00000002uL) +#define INTC_ICDICER7_ERI1 (0x00000004uL) +#define INTC_ICDICER7_RXI1 (0x00000008uL) +#define INTC_ICDICER7_TXI1 (0x00000010uL) +#define INTC_ICDICER7_BRI2 (0x00000020uL) +#define INTC_ICDICER7_ERI2 (0x00000040uL) +#define INTC_ICDICER7_RXI2 (0x00000080uL) +#define INTC_ICDICER7_TXI2 (0x00000100uL) +#define INTC_ICDICER7_BRI3 (0x00000200uL) +#define INTC_ICDICER7_ERI3 (0x00000400uL) +#define INTC_ICDICER7_RXI3 (0x00000800uL) +#define INTC_ICDICER7_TXI3 (0x00001000uL) +#define INTC_ICDICER7_BRI4 (0x00002000uL) +#define INTC_ICDICER7_ERI4 (0x00004000uL) +#define INTC_ICDICER7_RXI4 (0x00008000uL) +#define INTC_ICDICER7_TXI4 (0x00010000uL) +#define INTC_ICDICER7_BRI5 (0x00020000uL) +#define INTC_ICDICER7_ERI5 (0x00040000uL) +#define INTC_ICDICER7_RXI5 (0x00080000uL) +#define INTC_ICDICER7_TXI5 (0x00100000uL) +#define INTC_ICDICER7_BRI6 (0x00200000uL) +#define INTC_ICDICER7_ERI6 (0x00400000uL) +#define INTC_ICDICER7_RXI6 (0x00800000uL) +#define INTC_ICDICER7_TXI6 (0x01000000uL) +#define INTC_ICDICER7_BRI7 (0x02000000uL) +#define INTC_ICDICER7_ERI7 (0x04000000uL) +#define INTC_ICDICER7_RXI7 (0x08000000uL) +#define INTC_ICDICER7_TXI7 (0x10000000uL) +#define INTC_ICDICER7_INTRCANGERR (0x20000000uL) +#define INTC_ICDICER7_INTRCANGRECC (0x40000000uL) +#define INTC_ICDICER7_INTRCAN0REC (0x80000000uL) + +#define INTC_ICDICER8_INTRCAN0ERR (0x00000001uL) +#define INTC_ICDICER8_INTRCAN0TRX (0x00000002uL) +#define INTC_ICDICER8_INTRCAN1REC (0x00000004uL) +#define INTC_ICDICER8_INTRCAN1ERR (0x00000008uL) +#define INTC_ICDICER8_INTRCAN1TRX (0x00000010uL) +#define INTC_ICDICER8_INTRCAN2REC (0x00000020uL) +#define INTC_ICDICER8_INTRCAN2ERR (0x00000040uL) +#define INTC_ICDICER8_INTRCAN2TRX (0x00000080uL) +#define INTC_ICDICER8_INTRCAN3REC (0x00000100uL) +#define INTC_ICDICER8_INTRCAN3ERR (0x00000200uL) +#define INTC_ICDICER8_INTRCAN3TRX (0x00000400uL) +#define INTC_ICDICER8_INTRCAN4REC (0x00000800uL) +#define INTC_ICDICER8_INTRCAN4ERR (0x00001000uL) +#define INTC_ICDICER8_INTRCAN4TRX (0x00002000uL) +#define INTC_ICDICER8_SPEI0 (0x00004000uL) +#define INTC_ICDICER8_SPRI0 (0x00008000uL) +#define INTC_ICDICER8_SPTI0 (0x00010000uL) +#define INTC_ICDICER8_SPEI1 (0x00020000uL) +#define INTC_ICDICER8_SPRI1 (0x00040000uL) +#define INTC_ICDICER8_SPTI1 (0x00080000uL) +#define INTC_ICDICER8_SPEI2 (0x00100000uL) +#define INTC_ICDICER8_SPRI2 (0x00200000uL) +#define INTC_ICDICER8_SPTI2 (0x00400000uL) +#define INTC_ICDICER8_SPEI3 (0x00800000uL) +#define INTC_ICDICER8_SPRI3 (0x01000000uL) +#define INTC_ICDICER8_SPTI3 (0x02000000uL) +#define INTC_ICDICER8_SPEI4 (0x04000000uL) +#define INTC_ICDICER8_SPRI4 (0x08000000uL) +#define INTC_ICDICER8_SPTI4 (0x10000000uL) +#define INTC_ICDICER8_IEBBTD (0x20000000uL) +#define INTC_ICDICER8_IEBBTERR (0x40000000uL) +#define INTC_ICDICER8_IEBBTSTA (0x80000000uL) + +#define INTC_ICDICER9_IEBBTV (0x00000001uL) +#define INTC_ICDICER9_ISY (0x00000002uL) +#define INTC_ICDICER9_IERR (0x00000004uL) +#define INTC_ICDICER9_ITARG (0x00000008uL) +#define INTC_ICDICER9_ISEC (0x00000010uL) +#define INTC_ICDICER9_IBUF (0x00000020uL) +#define INTC_ICDICER9_IREADY (0x00000040uL) +#define INTC_ICDICER9_FLSTE (0x00000080uL) +#define INTC_ICDICER9_FLTENDI (0x00000100uL) +#define INTC_ICDICER9_FLTREQ0I (0x00000200uL) +#define INTC_ICDICER9_FLTREQ1I (0x00000400uL) +#define INTC_ICDICER9_MMC0 (0x00000800uL) +#define INTC_ICDICER9_MMC1 (0x00001000uL) +#define INTC_ICDICER9_MMC2 (0x00002000uL) +#define INTC_ICDICER9_SDHI0_3 (0x00004000uL) +#define INTC_ICDICER9_SDHI0_0 (0x00008000uL) +#define INTC_ICDICER9_SDHI0_1 (0x00010000uL) +#define INTC_ICDICER9_SDHI1_3 (0x00020000uL) +#define INTC_ICDICER9_SDHI1_0 (0x00040000uL) +#define INTC_ICDICER9_SDHI1_1 (0x00080000uL) +#define INTC_ICDICER9_ARM (0x00100000uL) +#define INTC_ICDICER9_PRD (0x00200000uL) +#define INTC_ICDICER9_CUP (0x00400000uL) +#define INTC_ICDICER9_SCUAI0 (0x00800000uL) +#define INTC_ICDICER9_SCUAI1 (0x01000000uL) +#define INTC_ICDICER9_SCUFDI0 (0x02000000uL) +#define INTC_ICDICER9_SCUFDI1 (0x04000000uL) +#define INTC_ICDICER9_SCUFDI2 (0x08000000uL) +#define INTC_ICDICER9_SCUFDI3 (0x10000000uL) +#define INTC_ICDICER9_SCUFUI0 (0x20000000uL) +#define INTC_ICDICER9_SCUFUI1 (0x40000000uL) +#define INTC_ICDICER9_SCUFUI2 (0x80000000uL) + +#define INTC_ICDICER10_SCUFUI3 (0x00000001uL) +#define INTC_ICDICER10_SCUDVI0 (0x00000002uL) +#define INTC_ICDICER10_SCUDVI1 (0x00000004uL) +#define INTC_ICDICER10_SCUDVI2 (0x00000008uL) +#define INTC_ICDICER10_SCUDVI3 (0x00000010uL) +#define INTC_ICDICER10_MLB_CINT (0x00000020uL) +#define INTC_ICDICER10_MLB_SINT (0x00000040uL) +#define INTC_ICDICER10_DRC0 (0x00000080uL) +#define INTC_ICDICER10_DRC1 (0x00000100uL) +#define INTC_ICDICER10_LINI0_INT_T (0x00000800uL) +#define INTC_ICDICER10_LINI0_INT_R (0x00001000uL) +#define INTC_ICDICER10_LINI0_INT_S (0x00002000uL) +#define INTC_ICDICER10_LINI0_INT_M (0x00004000uL) +#define INTC_ICDICER10_LINI1_INT_T (0x00008000uL) +#define INTC_ICDICER10_LINI1_INT_R (0x00010000uL) +#define INTC_ICDICER10_LINI1_INT_S (0x00020000uL) +#define INTC_ICDICER10_LINI1_INT_M (0x00040000uL) +#define INTC_ICDICER10_ERI0 (0x08000000uL) +#define INTC_ICDICER10_RXI0 (0x10000000uL) +#define INTC_ICDICER10_TXI0 (0x20000000uL) +#define INTC_ICDICER10_TEI0 (0x40000000uL) +#define INTC_ICDICER10_ERI1 (0x80000000uL) + +#define INTC_ICDICER11_RXI1 (0x00000001uL) +#define INTC_ICDICER11_TXI1 (0x00000002uL) +#define INTC_ICDICER11_TEI1 (0x00000004uL) +#define INTC_ICDICER11_AVBI_DATA (0x00000008uL) +#define INTC_ICDICER11_AVBI_ERROR (0x00000010uL) +#define INTC_ICDICER11_AVBI_MANAGE (0x00000020uL) +#define INTC_ICDICER11_AVBI_MAC (0x00000040uL) +#define INTC_ICDICER11_ETHERI (0x00000080uL) +#define INTC_ICDICER11_CEUI (0x00001000uL) +#define INTC_ICDICER11_H2XMLB_ERRINT (0x20000000uL) +#define INTC_ICDICER11_H2XIC1_ERRINT (0x40000000uL) +#define INTC_ICDICER11_X2HPERI1_ERRINT (0x80000000uL) + +#define INTC_ICDICER12_X2HPERI2_ERRINT (0x00000001uL) +#define INTC_ICDICER12_X2HPERI34_ERRINT (0x00000002uL) +#define INTC_ICDICER12_X2HPERI5_ERRINT (0x00000004uL) +#define INTC_ICDICER12_X2HPERI67_ERRINT (0x00000008uL) +#define INTC_ICDICER12_X2HDBGR_ERRINT (0x00000010uL) +#define INTC_ICDICER12_X2HBSC_ERRINT (0x00000020uL) +#define INTC_ICDICER12_X2HSPI1_ERRINT (0x00000040uL) +#define INTC_ICDICER12_X2HSPI2_ERRINT (0x00000080uL) +#define INTC_ICDICER12_PRRI (0x00000100uL) +#define INTC_ICDICER12_IFEI0 (0x00000200uL) +#define INTC_ICDICER12_OFFI0 (0x00000400uL) +#define INTC_ICDICER12_PFVEI0 (0x00000800uL) +#define INTC_ICDICER12_IFEI1 (0x00001000uL) +#define INTC_ICDICER12_OFFI1 (0x00002000uL) +#define INTC_ICDICER12_PFVEI1 (0x00004000uL) + +#define INTC_ICDICER13_TINT0 (0x00000001uL) +#define INTC_ICDICER13_TINT1 (0x00000002uL) +#define INTC_ICDICER13_TINT2 (0x00000004uL) +#define INTC_ICDICER13_TINT3 (0x00000008uL) +#define INTC_ICDICER13_TINT4 (0x00000010uL) +#define INTC_ICDICER13_TINT5 (0x00000020uL) +#define INTC_ICDICER13_TINT6 (0x00000040uL) +#define INTC_ICDICER13_TINT7 (0x00000080uL) +#define INTC_ICDICER13_TINT8 (0x00000100uL) +#define INTC_ICDICER13_TINT9 (0x00000200uL) +#define INTC_ICDICER13_TINT10 (0x00000400uL) +#define INTC_ICDICER13_TINT11 (0x00000800uL) +#define INTC_ICDICER13_TINT12 (0x00001000uL) +#define INTC_ICDICER13_TINT13 (0x00002000uL) +#define INTC_ICDICER13_TINT14 (0x00004000uL) +#define INTC_ICDICER13_TINT15 (0x00008000uL) +#define INTC_ICDICER13_TINT16 (0x00010000uL) +#define INTC_ICDICER13_TINT17 (0x00020000uL) +#define INTC_ICDICER13_TINT18 (0x00040000uL) +#define INTC_ICDICER13_TINT19 (0x00080000uL) +#define INTC_ICDICER13_TINT20 (0x00100000uL) +#define INTC_ICDICER13_TINT21 (0x00200000uL) +#define INTC_ICDICER13_TINT22 (0x00400000uL) +#define INTC_ICDICER13_TINT23 (0x00800000uL) +#define INTC_ICDICER13_TINT24 (0x01000000uL) +#define INTC_ICDICER13_TINT25 (0x02000000uL) +#define INTC_ICDICER13_TINT26 (0x04000000uL) +#define INTC_ICDICER13_TINT27 (0x08000000uL) +#define INTC_ICDICER13_TINT28 (0x10000000uL) +#define INTC_ICDICER13_TINT29 (0x20000000uL) +#define INTC_ICDICER13_TINT30 (0x40000000uL) +#define INTC_ICDICER13_TINT31 (0x80000000uL) + +#define INTC_ICDICER14_TINT32 (0x00000001uL) +#define INTC_ICDICER14_TINT33 (0x00000002uL) +#define INTC_ICDICER14_TINT34 (0x00000004uL) +#define INTC_ICDICER14_TINT35 (0x00000008uL) +#define INTC_ICDICER14_TINT36 (0x00000010uL) +#define INTC_ICDICER14_TINT37 (0x00000020uL) +#define INTC_ICDICER14_TINT38 (0x00000040uL) +#define INTC_ICDICER14_TINT39 (0x00000080uL) +#define INTC_ICDICER14_TINT40 (0x00000100uL) +#define INTC_ICDICER14_TINT41 (0x00000200uL) +#define INTC_ICDICER14_TINT42 (0x00000400uL) +#define INTC_ICDICER14_TINT43 (0x00000800uL) +#define INTC_ICDICER14_TINT44 (0x00001000uL) +#define INTC_ICDICER14_TINT45 (0x00002000uL) +#define INTC_ICDICER14_TINT46 (0x00004000uL) +#define INTC_ICDICER14_TINT47 (0x00008000uL) +#define INTC_ICDICER14_TINT48 (0x00010000uL) +#define INTC_ICDICER14_TINT49 (0x00020000uL) +#define INTC_ICDICER14_TINT50 (0x00040000uL) +#define INTC_ICDICER14_TINT51 (0x00080000uL) +#define INTC_ICDICER14_TINT52 (0x00100000uL) +#define INTC_ICDICER14_TINT53 (0x00200000uL) +#define INTC_ICDICER14_TINT54 (0x00400000uL) +#define INTC_ICDICER14_TINT55 (0x00800000uL) +#define INTC_ICDICER14_TINT56 (0x01000000uL) +#define INTC_ICDICER14_TINT57 (0x02000000uL) +#define INTC_ICDICER14_TINT58 (0x04000000uL) +#define INTC_ICDICER14_TINT59 (0x08000000uL) +#define INTC_ICDICER14_TINT60 (0x10000000uL) +#define INTC_ICDICER14_TINT61 (0x20000000uL) +#define INTC_ICDICER14_TINT62 (0x40000000uL) +#define INTC_ICDICER14_TINT63 (0x80000000uL) + +#define INTC_ICDICER15_TINT64 (0x00000001uL) +#define INTC_ICDICER15_TINT65 (0x00000002uL) +#define INTC_ICDICER15_TINT66 (0x00000004uL) +#define INTC_ICDICER15_TINT67 (0x00000008uL) +#define INTC_ICDICER15_TINT68 (0x00000010uL) +#define INTC_ICDICER15_TINT69 (0x00000020uL) +#define INTC_ICDICER15_TINT70 (0x00000040uL) +#define INTC_ICDICER15_TINT71 (0x00000080uL) +#define INTC_ICDICER15_TINT72 (0x00000100uL) +#define INTC_ICDICER15_TINT73 (0x00000200uL) +#define INTC_ICDICER15_TINT74 (0x00000400uL) +#define INTC_ICDICER15_TINT75 (0x00000800uL) +#define INTC_ICDICER15_TINT76 (0x00001000uL) +#define INTC_ICDICER15_TINT77 (0x00002000uL) +#define INTC_ICDICER15_TINT78 (0x00004000uL) +#define INTC_ICDICER15_TINT79 (0x00008000uL) +#define INTC_ICDICER15_TINT80 (0x00010000uL) +#define INTC_ICDICER15_TINT81 (0x00020000uL) +#define INTC_ICDICER15_TINT82 (0x00040000uL) +#define INTC_ICDICER15_TINT83 (0x00080000uL) +#define INTC_ICDICER15_TINT84 (0x00100000uL) +#define INTC_ICDICER15_TINT85 (0x00200000uL) +#define INTC_ICDICER15_TINT86 (0x00400000uL) +#define INTC_ICDICER15_TINT87 (0x00800000uL) +#define INTC_ICDICER15_TINT88 (0x01000000uL) +#define INTC_ICDICER15_TINT89 (0x02000000uL) +#define INTC_ICDICER15_TINT90 (0x04000000uL) +#define INTC_ICDICER15_TINT91 (0x08000000uL) +#define INTC_ICDICER15_TINT92 (0x10000000uL) +#define INTC_ICDICER15_TINT93 (0x20000000uL) +#define INTC_ICDICER15_TINT94 (0x40000000uL) +#define INTC_ICDICER15_TINT95 (0x80000000uL) + +#define INTC_ICDICER16_TINT96 (0x00000001uL) +#define INTC_ICDICER16_TINT97 (0x00000002uL) +#define INTC_ICDICER16_TINT98 (0x00000004uL) +#define INTC_ICDICER16_TINT99 (0x00000008uL) +#define INTC_ICDICER16_TINT100 (0x00000010uL) +#define INTC_ICDICER16_TINT101 (0x00000020uL) +#define INTC_ICDICER16_TINT102 (0x00000040uL) +#define INTC_ICDICER16_TINT103 (0x00000080uL) +#define INTC_ICDICER16_TINT104 (0x00000100uL) +#define INTC_ICDICER16_TINT105 (0x00000200uL) +#define INTC_ICDICER16_TINT106 (0x00000400uL) +#define INTC_ICDICER16_TINT107 (0x00000800uL) +#define INTC_ICDICER16_TINT108 (0x00001000uL) +#define INTC_ICDICER16_TINT109 (0x00002000uL) +#define INTC_ICDICER16_TINT110 (0x00004000uL) +#define INTC_ICDICER16_TINT111 (0x00008000uL) +#define INTC_ICDICER16_TINT112 (0x00010000uL) +#define INTC_ICDICER16_TINT113 (0x00020000uL) +#define INTC_ICDICER16_TINT114 (0x00040000uL) +#define INTC_ICDICER16_TINT115 (0x00080000uL) +#define INTC_ICDICER16_TINT116 (0x00100000uL) +#define INTC_ICDICER16_TINT117 (0x00200000uL) +#define INTC_ICDICER16_TINT118 (0x00400000uL) +#define INTC_ICDICER16_TINT119 (0x00800000uL) +#define INTC_ICDICER16_TINT120 (0x01000000uL) +#define INTC_ICDICER16_TINT121 (0x02000000uL) +#define INTC_ICDICER16_TINT122 (0x04000000uL) +#define INTC_ICDICER16_TINT123 (0x08000000uL) +#define INTC_ICDICER16_TINT124 (0x10000000uL) +#define INTC_ICDICER16_TINT125 (0x20000000uL) +#define INTC_ICDICER16_TINT126 (0x40000000uL) +#define INTC_ICDICER16_TINT127 (0x80000000uL) + +#define INTC_ICDICER17_TINT128 (0x00000001uL) +#define INTC_ICDICER17_TINT129 (0x00000002uL) +#define INTC_ICDICER17_TINT130 (0x00000004uL) +#define INTC_ICDICER17_TINT131 (0x00000008uL) +#define INTC_ICDICER17_TINT132 (0x00000010uL) +#define INTC_ICDICER17_TINT133 (0x00000020uL) +#define INTC_ICDICER17_TINT134 (0x00000040uL) +#define INTC_ICDICER17_TINT135 (0x00000080uL) +#define INTC_ICDICER17_TINT136 (0x00000100uL) +#define INTC_ICDICER17_TINT137 (0x00000200uL) +#define INTC_ICDICER17_TINT138 (0x00000400uL) +#define INTC_ICDICER17_TINT139 (0x00000800uL) +#define INTC_ICDICER17_TINT140 (0x00001000uL) +#define INTC_ICDICER17_TINT141 (0x00002000uL) +#define INTC_ICDICER17_TINT142 (0x00004000uL) +#define INTC_ICDICER17_TINT143 (0x00008000uL) +#define INTC_ICDICER17_TINT144 (0x00010000uL) +#define INTC_ICDICER17_TINT145 (0x00020000uL) +#define INTC_ICDICER17_TINT146 (0x00040000uL) +#define INTC_ICDICER17_TINT147 (0x00080000uL) +#define INTC_ICDICER17_TINT148 (0x00100000uL) +#define INTC_ICDICER17_TINT149 (0x00200000uL) +#define INTC_ICDICER17_TINT150 (0x00400000uL) +#define INTC_ICDICER17_TINT151 (0x00800000uL) +#define INTC_ICDICER17_TINT152 (0x01000000uL) +#define INTC_ICDICER17_TINT153 (0x02000000uL) +#define INTC_ICDICER17_TINT154 (0x04000000uL) +#define INTC_ICDICER17_TINT155 (0x08000000uL) +#define INTC_ICDICER17_TINT156 (0x10000000uL) +#define INTC_ICDICER17_TINT157 (0x20000000uL) +#define INTC_ICDICER17_TINT158 (0x40000000uL) +#define INTC_ICDICER17_TINT159 (0x80000000uL) + +#define INTC_ICDICER18_TINT160 (0x00000001uL) +#define INTC_ICDICER18_TINT161 (0x00000002uL) +#define INTC_ICDICER18_TINT162 (0x00000004uL) +#define INTC_ICDICER18_TINT163 (0x00000008uL) +#define INTC_ICDICER18_TINT164 (0x00000010uL) +#define INTC_ICDICER18_TINT165 (0x00000020uL) +#define INTC_ICDICER18_TINT166 (0x00000040uL) +#define INTC_ICDICER18_TINT167 (0x00000080uL) +#define INTC_ICDICER18_TINT168 (0x00000100uL) +#define INTC_ICDICER18_TINT169 (0x00000200uL) +#define INTC_ICDICER18_TINT170 (0x00000400uL) + +#define INTC_ICDISPR0_SW0 (0x00000001uL) +#define INTC_ICDISPR0_SW1 (0x00000002uL) +#define INTC_ICDISPR0_SW2 (0x00000004uL) +#define INTC_ICDISPR0_SW3 (0x00000008uL) +#define INTC_ICDISPR0_SW4 (0x00000010uL) +#define INTC_ICDISPR0_SW5 (0x00000020uL) +#define INTC_ICDISPR0_SW6 (0x00000040uL) +#define INTC_ICDISPR0_SW7 (0x00000080uL) +#define INTC_ICDISPR0_SW8 (0x00000100uL) +#define INTC_ICDISPR0_SW9 (0x00000200uL) +#define INTC_ICDISPR0_SW10 (0x00000400uL) +#define INTC_ICDISPR0_SW11 (0x00000800uL) +#define INTC_ICDISPR0_SW12 (0x00001000uL) +#define INTC_ICDISPR0_SW13 (0x00002000uL) +#define INTC_ICDISPR0_SW14 (0x00004000uL) +#define INTC_ICDISPR0_SW15 (0x00008000uL) +#define INTC_ICDISPR0_PMUIRQ0 (0x00010000uL) +#define INTC_ICDISPR0_COMMRX0 (0x00020000uL) +#define INTC_ICDISPR0_COMMTX0 (0x00040000uL) +#define INTC_ICDISPR0_CTIIRQ0 (0x00080000uL) + +#define INTC_ICDISPR1_IRQ0 (0x00000001uL) +#define INTC_ICDISPR1_IRQ1 (0x00000002uL) +#define INTC_ICDISPR1_IRQ2 (0x00000004uL) +#define INTC_ICDISPR1_IRQ3 (0x00000008uL) +#define INTC_ICDISPR1_IRQ4 (0x00000010uL) +#define INTC_ICDISPR1_IRQ5 (0x00000020uL) +#define INTC_ICDISPR1_IRQ6 (0x00000040uL) +#define INTC_ICDISPR1_IRQ7 (0x00000080uL) +#define INTC_ICDISPR1_PL310ERR (0x00000100uL) +#define INTC_ICDISPR1_DMAINT0 (0x00000200uL) +#define INTC_ICDISPR1_DMAINT1 (0x00000400uL) +#define INTC_ICDISPR1_DMAINT2 (0x00000800uL) +#define INTC_ICDISPR1_DMAINT3 (0x00001000uL) +#define INTC_ICDISPR1_DMAINT4 (0x00002000uL) +#define INTC_ICDISPR1_DMAINT5 (0x00004000uL) +#define INTC_ICDISPR1_DMAINT6 (0x00008000uL) +#define INTC_ICDISPR1_DMAINT7 (0x00010000uL) +#define INTC_ICDISPR1_DMAINT8 (0x00020000uL) +#define INTC_ICDISPR1_DMAINT9 (0x00040000uL) +#define INTC_ICDISPR1_DMAINT10 (0x00080000uL) +#define INTC_ICDISPR1_DMAINT11 (0x00100000uL) +#define INTC_ICDISPR1_DMAINT12 (0x00200000uL) +#define INTC_ICDISPR1_DMAINT13 (0x00400000uL) +#define INTC_ICDISPR1_DMAINT14 (0x00800000uL) +#define INTC_ICDISPR1_DMAINT15 (0x01000000uL) +#define INTC_ICDISPR1_DMAERR (0x02000000uL) + +#define INTC_ICDISPR2_USBI0 (0x00000200uL) +#define INTC_ICDISPR2_USBI1 (0x00000400uL) +#define INTC_ICDISPR2_S0_VI_VSYNC0 (0x00000800uL) +#define INTC_ICDISPR2_S0_LO_VSYNC0 (0x00001000uL) +#define INTC_ICDISPR2_S0_VSYNCERR0 (0x00002000uL) +#define INTC_ICDISPR2_GR3_VLINE0 (0x00004000uL) +#define INTC_ICDISPR2_S0_VFIELD0 (0x00008000uL) +#define INTC_ICDISPR2_IV1_VBUFERR0 (0x00010000uL) +#define INTC_ICDISPR2_IV3_VBUFERR0 (0x00020000uL) +#define INTC_ICDISPR2_IV5_VBUFERR0 (0x00040000uL) +#define INTC_ICDISPR2_IV6_VBUFERR0 (0x00080000uL) +#define INTC_ICDISPR2_S0_WLINE0 (0x00100000uL) +#define INTC_ICDISPR2_S1_VI_VSYNC0 (0x00200000uL) +#define INTC_ICDISPR2_S1_LO_VSYNC0 (0x00400000uL) +#define INTC_ICDISPR2_S1_VSYNCERR0 (0x00800000uL) +#define INTC_ICDISPR2_S1_VFIELD0 (0x01000000uL) +#define INTC_ICDISPR2_IV2_VBUFERR0 (0x02000000uL) +#define INTC_ICDISPR2_IV4_VBUFERR0 (0x04000000uL) +#define INTC_ICDISPR2_S1_WLINE0 (0x08000000uL) +#define INTC_ICDISPR2_OIR_VI_VSYNC0 (0x10000000uL) +#define INTC_ICDISPR2_OIR_LO_VSYNC0 (0x20000000uL) +#define INTC_ICDISPR2_OIR_VSYNCERR0 (0x40000000uL) +#define INTC_ICDISPR2_OIR_VFIELD0 (0x80000000uL) + +#define INTC_ICDISPR3_IV7_VBUFERR0 (0x00000001uL) +#define INTC_ICDISPR3_IV8_VBUFERR0 (0x00000002uL) +#define INTC_ICDISPR3_S0_VI_VSYNC1 (0x00000008uL) +#define INTC_ICDISPR3_S0_LO_VSYNC1 (0x00000010uL) +#define INTC_ICDISPR3_S0_VSYNCERR1 (0x00000020uL) +#define INTC_ICDISPR3_GR3_VLINE1 (0x00000040uL) +#define INTC_ICDISPR3_S0_VFIELD1 (0x00000080uL) +#define INTC_ICDISPR3_IV1_VBUFERR1 (0x00000100uL) +#define INTC_ICDISPR3_IV3_VBUFERR1 (0x00000200uL) +#define INTC_ICDISPR3_IV5_VBUFERR1 (0x00000400uL) +#define INTC_ICDISPR3_IV6_VBUFERR1 (0x00000800uL) +#define INTC_ICDISPR3_S0_WLINE1 (0x00001000uL) +#define INTC_ICDISPR3_S1_VI_VSYNC1 (0x00002000uL) +#define INTC_ICDISPR3_S1_LO_VSYNC1 (0x00004000uL) +#define INTC_ICDISPR3_S1_VSYNCERR1 (0x00008000uL) +#define INTC_ICDISPR3_S1_VFIELD1 (0x00010000uL) +#define INTC_ICDISPR3_IV2_VBUFERR1 (0x00020000uL) +#define INTC_ICDISPR3_IV4_VBUFERR1 (0x00040000uL) +#define INTC_ICDISPR3_S1_WLINE1 (0x00080000uL) +#define INTC_ICDISPR3_OIR_VI_VSYNC1 (0x00100000uL) +#define INTC_ICDISPR3_OIR_LO_VSYNC1 (0x00200000uL) +#define INTC_ICDISPR3_OIR_VLINE1 (0x00400000uL) +#define INTC_ICDISPR3_OIR_VFIELD1 (0x00800000uL) +#define INTC_ICDISPR3_IV7_VBUFERR1 (0x01000000uL) +#define INTC_ICDISPR3_IV8_VBUFERR1 (0x02000000uL) +#define INTC_ICDISPR3_IMRDI (0x08000000uL) +#define INTC_ICDISPR3_IMR2I0 (0x10000000uL) +#define INTC_ICDISPR3_IMR2I1 (0x20000000uL) +#define INTC_ICDISPR3_JEDI (0x40000000uL) +#define INTC_ICDISPR3_JDTI (0x80000000uL) + +#define INTC_ICDISPR4_CMP0 (0x00000001uL) +#define INTC_ICDISPR4_CMP1 (0x00000002uL) +#define INTC_ICDISPR4_INT0 (0x00000004uL) +#define INTC_ICDISPR4_INT1 (0x00000008uL) +#define INTC_ICDISPR4_INT2 (0x00000010uL) +#define INTC_ICDISPR4_INT3 (0x00000020uL) +#define INTC_ICDISPR4_OSTM0TINT (0x00000040uL) +#define INTC_ICDISPR4_OSTM1TINT (0x00000080uL) +#define INTC_ICDISPR4_CMI (0x00000100uL) +#define INTC_ICDISPR4_WTOUT (0x00000200uL) +#define INTC_ICDISPR4_ITI (0x00000400uL) +#define INTC_ICDISPR4_TGI0A (0x00000800uL) +#define INTC_ICDISPR4_TGI0B (0x00001000uL) +#define INTC_ICDISPR4_TGI0C (0x00002000uL) +#define INTC_ICDISPR4_TGI0D (0x00004000uL) +#define INTC_ICDISPR4_TGI0V (0x00008000uL) +#define INTC_ICDISPR4_TGI0E (0x00010000uL) +#define INTC_ICDISPR4_TGI0F (0x00020000uL) +#define INTC_ICDISPR4_TGI1A (0x00040000uL) +#define INTC_ICDISPR4_TGI1B (0x00080000uL) +#define INTC_ICDISPR4_TGI1V (0x00100000uL) +#define INTC_ICDISPR4_TGI1U (0x00200000uL) +#define INTC_ICDISPR4_TGI2A (0x00400000uL) +#define INTC_ICDISPR4_TGI2B (0x00800000uL) +#define INTC_ICDISPR4_TGI2V (0x01000000uL) +#define INTC_ICDISPR4_TGI2U (0x02000000uL) +#define INTC_ICDISPR4_TGI3A (0x04000000uL) +#define INTC_ICDISPR4_TGI3B (0x08000000uL) +#define INTC_ICDISPR4_TGI3C (0x10000000uL) +#define INTC_ICDISPR4_TGI3D (0x20000000uL) +#define INTC_ICDISPR4_TGI3V (0x40000000uL) +#define INTC_ICDISPR4_TGI4A (0x80000000uL) + +#define INTC_ICDISPR5_TGI4B (0x00000001uL) +#define INTC_ICDISPR5_TGI4C (0x00000002uL) +#define INTC_ICDISPR5_TGI4D (0x00000004uL) +#define INTC_ICDISPR5_TGI4V (0x00000008uL) +#define INTC_ICDISPR5_CMI1 (0x00000010uL) +#define INTC_ICDISPR5_CMI2 (0x00000020uL) +#define INTC_ICDISPR5_SGDEI0 (0x00000040uL) +#define INTC_ICDISPR5_SGDEI1 (0x00000080uL) +#define INTC_ICDISPR5_SGDEI2 (0x00000100uL) +#define INTC_ICDISPR5_SGDEI3 (0x00000200uL) +#define INTC_ICDISPR5_ADI (0x00000400uL) +#define INTC_ICDISPR5_LMTI (0x00000800uL) +#define INTC_ICDISPR5_SSII0 (0x00001000uL) +#define INTC_ICDISPR5_SSIRXI0 (0x00002000uL) +#define INTC_ICDISPR5_SSITXI0 (0x00004000uL) +#define INTC_ICDISPR5_SSII1 (0x00008000uL) +#define INTC_ICDISPR5_SSIRXI1 (0x00010000uL) +#define INTC_ICDISPR5_SSITXI1 (0x00020000uL) +#define INTC_ICDISPR5_SSII2 (0x00040000uL) +#define INTC_ICDISPR5_SSIRTI2 (0x00080000uL) +#define INTC_ICDISPR5_SSII3 (0x00100000uL) +#define INTC_ICDISPR5_SSIRXI3 (0x00200000uL) +#define INTC_ICDISPR5_SSITXI3 (0x00400000uL) +#define INTC_ICDISPR5_SSII4 (0x00800000uL) +#define INTC_ICDISPR5_SSIRTI4 (0x01000000uL) +#define INTC_ICDISPR5_SSII5 (0x02000000uL) +#define INTC_ICDISPR5_SSIRXI5 (0x04000000uL) +#define INTC_ICDISPR5_SSITXI5 (0x08000000uL) +#define INTC_ICDISPR5_SPDIFI (0x10000000uL) +#define INTC_ICDISPR5_INTIICTEI0 (0x20000000uL) +#define INTC_ICDISPR5_INTIICRI0 (0x40000000uL) +#define INTC_ICDISPR5_INTIICTI0 (0x80000000uL) + +#define INTC_ICDISPR6_INTIICSPI0 (0x00000001uL) +#define INTC_ICDISPR6_INTIICSTI0 (0x00000002uL) +#define INTC_ICDISPR6_INTIICNAKI0 (0x00000004uL) +#define INTC_ICDISPR6_INTIICALI0 (0x00000008uL) +#define INTC_ICDISPR6_INTIICTMOI0 (0x00000010uL) +#define INTC_ICDISPR6_INTIICTEI1 (0x00000020uL) +#define INTC_ICDISPR6_INTIICRI1 (0x00000040uL) +#define INTC_ICDISPR6_INTIICTI1 (0x00000080uL) +#define INTC_ICDISPR6_INTIICSPI1 (0x00000100uL) +#define INTC_ICDISPR6_INTIICSTI1 (0x00000200uL) +#define INTC_ICDISPR6_INTIICNAKI1 (0x00000400uL) +#define INTC_ICDISPR6_INTIICALI1 (0x00000800uL) +#define INTC_ICDISPR6_INTIICTMOI1 (0x00001000uL) +#define INTC_ICDISPR6_INTIICTEI2 (0x00002000uL) +#define INTC_ICDISPR6_INTIICRI2 (0x00004000uL) +#define INTC_ICDISPR6_INTIICTI2 (0x00008000uL) +#define INTC_ICDISPR6_INTIICSPI2 (0x00010000uL) +#define INTC_ICDISPR6_INTIICSTI2 (0x00020000uL) +#define INTC_ICDISPR6_INTIICNAKI2 (0x00040000uL) +#define INTC_ICDISPR6_INTIICALI2 (0x00080000uL) +#define INTC_ICDISPR6_INTIICTMOI2 (0x00100000uL) +#define INTC_ICDISPR6_INTIICTEI3 (0x00200000uL) +#define INTC_ICDISPR6_INTIICRI3 (0x00400000uL) +#define INTC_ICDISPR6_INTIICTI3 (0x00800000uL) +#define INTC_ICDISPR6_INTIICSPI3 (0x01000000uL) +#define INTC_ICDISPR6_INTIICSTI3 (0x02000000uL) +#define INTC_ICDISPR6_INTIICNAKI3 (0x04000000uL) +#define INTC_ICDISPR6_INTIICALI3 (0x08000000uL) +#define INTC_ICDISPR6_INTIICTMOI3 (0x10000000uL) +#define INTC_ICDISPR6_BRI0 (0x20000000uL) +#define INTC_ICDISPR6_ERI0 (0x40000000uL) +#define INTC_ICDISPR6_RXI0 (0x80000000uL) + +#define INTC_ICDISPR7_TXI0 (0x00000001uL) +#define INTC_ICDISPR7_BRI1 (0x00000002uL) +#define INTC_ICDISPR7_ERI1 (0x00000004uL) +#define INTC_ICDISPR7_RXI1 (0x00000008uL) +#define INTC_ICDISPR7_TXI1 (0x00000010uL) +#define INTC_ICDISPR7_BRI2 (0x00000020uL) +#define INTC_ICDISPR7_ERI2 (0x00000040uL) +#define INTC_ICDISPR7_RXI2 (0x00000080uL) +#define INTC_ICDISPR7_TXI2 (0x00000100uL) +#define INTC_ICDISPR7_BRI3 (0x00000200uL) +#define INTC_ICDISPR7_ERI3 (0x00000400uL) +#define INTC_ICDISPR7_RXI3 (0x00000800uL) +#define INTC_ICDISPR7_TXI3 (0x00001000uL) +#define INTC_ICDISPR7_BRI4 (0x00002000uL) +#define INTC_ICDISPR7_ERI4 (0x00004000uL) +#define INTC_ICDISPR7_RXI4 (0x00008000uL) +#define INTC_ICDISPR7_TXI4 (0x00010000uL) +#define INTC_ICDISPR7_BRI5 (0x00020000uL) +#define INTC_ICDISPR7_ERI5 (0x00040000uL) +#define INTC_ICDISPR7_RXI5 (0x00080000uL) +#define INTC_ICDISPR7_TXI5 (0x00100000uL) +#define INTC_ICDISPR7_BRI6 (0x00200000uL) +#define INTC_ICDISPR7_ERI6 (0x00400000uL) +#define INTC_ICDISPR7_RXI6 (0x00800000uL) +#define INTC_ICDISPR7_TXI6 (0x01000000uL) +#define INTC_ICDISPR7_BRI7 (0x02000000uL) +#define INTC_ICDISPR7_ERI7 (0x04000000uL) +#define INTC_ICDISPR7_RXI7 (0x08000000uL) +#define INTC_ICDISPR7_TXI7 (0x10000000uL) +#define INTC_ICDISPR7_INTRCANGERR (0x20000000uL) +#define INTC_ICDISPR7_INTRCANGRECC (0x40000000uL) +#define INTC_ICDISPR7_INTRCAN0REC (0x80000000uL) + +#define INTC_ICDISPR8_INTRCAN0ERR (0x00000001uL) +#define INTC_ICDISPR8_INTRCAN0TRX (0x00000002uL) +#define INTC_ICDISPR8_INTRCAN1REC (0x00000004uL) +#define INTC_ICDISPR8_INTRCAN1ERR (0x00000008uL) +#define INTC_ICDISPR8_INTRCAN1TRX (0x00000010uL) +#define INTC_ICDISPR8_INTRCAN2REC (0x00000020uL) +#define INTC_ICDISPR8_INTRCAN2ERR (0x00000040uL) +#define INTC_ICDISPR8_INTRCAN2TRX (0x00000080uL) +#define INTC_ICDISPR8_INTRCAN3REC (0x00000100uL) +#define INTC_ICDISPR8_INTRCAN3ERR (0x00000200uL) +#define INTC_ICDISPR8_INTRCAN3TRX (0x00000400uL) +#define INTC_ICDISPR8_INTRCAN4REC (0x00000800uL) +#define INTC_ICDISPR8_INTRCAN4ERR (0x00001000uL) +#define INTC_ICDISPR8_INTRCAN4TRX (0x00002000uL) +#define INTC_ICDISPR8_SPEI0 (0x00004000uL) +#define INTC_ICDISPR8_SPRI0 (0x00008000uL) +#define INTC_ICDISPR8_SPTI0 (0x00010000uL) +#define INTC_ICDISPR8_SPEI1 (0x00020000uL) +#define INTC_ICDISPR8_SPRI1 (0x00040000uL) +#define INTC_ICDISPR8_SPTI1 (0x00080000uL) +#define INTC_ICDISPR8_SPEI2 (0x00100000uL) +#define INTC_ICDISPR8_SPRI2 (0x00200000uL) +#define INTC_ICDISPR8_SPTI2 (0x00400000uL) +#define INTC_ICDISPR8_SPEI3 (0x00800000uL) +#define INTC_ICDISPR8_SPRI3 (0x01000000uL) +#define INTC_ICDISPR8_SPTI3 (0x02000000uL) +#define INTC_ICDISPR8_SPEI4 (0x04000000uL) +#define INTC_ICDISPR8_SPRI4 (0x08000000uL) +#define INTC_ICDISPR8_SPTI4 (0x10000000uL) +#define INTC_ICDISPR8_IEBBTD (0x20000000uL) +#define INTC_ICDISPR8_IEBBTERR (0x40000000uL) +#define INTC_ICDISPR8_IEBBTSTA (0x80000000uL) + +#define INTC_ICDISPR9_IEBBTV (0x00000001uL) +#define INTC_ICDISPR9_ISY (0x00000002uL) +#define INTC_ICDISPR9_IERR (0x00000004uL) +#define INTC_ICDISPR9_ITARG (0x00000008uL) +#define INTC_ICDISPR9_ISEC (0x00000010uL) +#define INTC_ICDISPR9_IBUF (0x00000020uL) +#define INTC_ICDISPR9_IREADY (0x00000040uL) +#define INTC_ICDISPR9_FLSTE (0x00000080uL) +#define INTC_ICDISPR9_FLTENDI (0x00000100uL) +#define INTC_ICDISPR9_FLTREQ0I (0x00000200uL) +#define INTC_ICDISPR9_FLTREQ1I (0x00000400uL) +#define INTC_ICDISPR9_MMC0 (0x00000800uL) +#define INTC_ICDISPR9_MMC1 (0x00001000uL) +#define INTC_ICDISPR9_MMC2 (0x00002000uL) +#define INTC_ICDISPR9_SDHI0_3 (0x00004000uL) +#define INTC_ICDISPR9_SDHI0_0 (0x00008000uL) +#define INTC_ICDISPR9_SDHI0_1 (0x00010000uL) +#define INTC_ICDISPR9_SDHI1_3 (0x00020000uL) +#define INTC_ICDISPR9_SDHI1_0 (0x00040000uL) +#define INTC_ICDISPR9_SDHI1_1 (0x00080000uL) +#define INTC_ICDISPR9_ARM (0x00100000uL) +#define INTC_ICDISPR9_PRD (0x00200000uL) +#define INTC_ICDISPR9_CUP (0x00400000uL) +#define INTC_ICDISPR9_SCUAI0 (0x00800000uL) +#define INTC_ICDISPR9_SCUAI1 (0x01000000uL) +#define INTC_ICDISPR9_SCUFDI0 (0x02000000uL) +#define INTC_ICDISPR9_SCUFDI1 (0x04000000uL) +#define INTC_ICDISPR9_SCUFDI2 (0x08000000uL) +#define INTC_ICDISPR9_SCUFDI3 (0x10000000uL) +#define INTC_ICDISPR9_SCUFUI0 (0x20000000uL) +#define INTC_ICDISPR9_SCUFUI1 (0x40000000uL) +#define INTC_ICDISPR9_SCUFUI2 (0x80000000uL) + +#define INTC_ICDISPR10_SCUFUI3 (0x00000001uL) +#define INTC_ICDISPR10_SCUDVI0 (0x00000002uL) +#define INTC_ICDISPR10_SCUDVI1 (0x00000004uL) +#define INTC_ICDISPR10_SCUDVI2 (0x00000008uL) +#define INTC_ICDISPR10_SCUDVI3 (0x00000010uL) +#define INTC_ICDISPR10_MLB_CINT (0x00000020uL) +#define INTC_ICDISPR10_MLB_SINT (0x00000040uL) +#define INTC_ICDISPR10_DRC0 (0x00000080uL) +#define INTC_ICDISPR10_DRC1 (0x00000100uL) +#define INTC_ICDISPR10_LINI0_INT_T (0x00000800uL) +#define INTC_ICDISPR10_LINI0_INT_R (0x00001000uL) +#define INTC_ICDISPR10_LINI0_INT_S (0x00002000uL) +#define INTC_ICDISPR10_LINI0_INT_M (0x00004000uL) +#define INTC_ICDISPR10_LINI1_INT_T (0x00008000uL) +#define INTC_ICDISPR10_LINI1_INT_R (0x00010000uL) +#define INTC_ICDISPR10_LINI1_INT_S (0x00020000uL) +#define INTC_ICDISPR10_LINI1_INT_M (0x00040000uL) +#define INTC_ICDISPR10_ERI0 (0x08000000uL) +#define INTC_ICDISPR10_RXI0 (0x10000000uL) +#define INTC_ICDISPR10_TXI0 (0x20000000uL) +#define INTC_ICDISPR10_TEI0 (0x40000000uL) +#define INTC_ICDISPR10_ERI1 (0x80000000uL) + +#define INTC_ICDISPR11_RXI1 (0x00000001uL) +#define INTC_ICDISPR11_TXI1 (0x00000002uL) +#define INTC_ICDISPR11_TEI1 (0x00000004uL) +#define INTC_ICDISPR11_AVBI_DATA (0x00000008uL) +#define INTC_ICDISPR11_AVBI_ERROR (0x00000010uL) +#define INTC_ICDISPR11_AVBI_MANAGE (0x00000020uL) +#define INTC_ICDISPR11_AVBI_MAC (0x00000040uL) +#define INTC_ICDISPR11_ETHERI (0x00000080uL) +#define INTC_ICDISPR11_CEUI (0x00001000uL) +#define INTC_ICDISPR11_H2XMLB_ERRINT (0x20000000uL) +#define INTC_ICDISPR11_H2XIC1_ERRINT (0x40000000uL) +#define INTC_ICDISPR11_X2HPERI1_ERRINT (0x80000000uL) + +#define INTC_ICDISPR12_X2HPERI2_ERRINT (0x00000001uL) +#define INTC_ICDISPR12_X2HPERI34_ERRINT (0x00000002uL) +#define INTC_ICDISPR12_X2HPERI5_ERRINT (0x00000004uL) +#define INTC_ICDISPR12_X2HPERI67_ERRINT (0x00000008uL) +#define INTC_ICDISPR12_X2HDBGR_ERRINT (0x00000010uL) +#define INTC_ICDISPR12_X2HBSC_ERRINT (0x00000020uL) +#define INTC_ICDISPR12_X2HSPI1_ERRINT (0x00000040uL) +#define INTC_ICDISPR12_X2HSPI2_ERRINT (0x00000080uL) +#define INTC_ICDISPR12_PRRI (0x00000100uL) +#define INTC_ICDISPR12_IFEI0 (0x00000200uL) +#define INTC_ICDISPR12_OFFI0 (0x00000400uL) +#define INTC_ICDISPR12_PFVEI0 (0x00000800uL) +#define INTC_ICDISPR12_IFEI1 (0x00001000uL) +#define INTC_ICDISPR12_OFFI1 (0x00002000uL) +#define INTC_ICDISPR12_PFVEI1 (0x00004000uL) + +#define INTC_ICDISPR13_TINT0 (0x00000001uL) +#define INTC_ICDISPR13_TINT1 (0x00000002uL) +#define INTC_ICDISPR13_TINT2 (0x00000004uL) +#define INTC_ICDISPR13_TINT3 (0x00000008uL) +#define INTC_ICDISPR13_TINT4 (0x00000010uL) +#define INTC_ICDISPR13_TINT5 (0x00000020uL) +#define INTC_ICDISPR13_TINT6 (0x00000040uL) +#define INTC_ICDISPR13_TINT7 (0x00000080uL) +#define INTC_ICDISPR13_TINT8 (0x00000100uL) +#define INTC_ICDISPR13_TINT9 (0x00000200uL) +#define INTC_ICDISPR13_TINT10 (0x00000400uL) +#define INTC_ICDISPR13_TINT11 (0x00000800uL) +#define INTC_ICDISPR13_TINT12 (0x00001000uL) +#define INTC_ICDISPR13_TINT13 (0x00002000uL) +#define INTC_ICDISPR13_TINT14 (0x00004000uL) +#define INTC_ICDISPR13_TINT15 (0x00008000uL) +#define INTC_ICDISPR13_TINT16 (0x00010000uL) +#define INTC_ICDISPR13_TINT17 (0x00020000uL) +#define INTC_ICDISPR13_TINT18 (0x00040000uL) +#define INTC_ICDISPR13_TINT19 (0x00080000uL) +#define INTC_ICDISPR13_TINT20 (0x00100000uL) +#define INTC_ICDISPR13_TINT21 (0x00200000uL) +#define INTC_ICDISPR13_TINT22 (0x00400000uL) +#define INTC_ICDISPR13_TINT23 (0x00800000uL) +#define INTC_ICDISPR13_TINT24 (0x01000000uL) +#define INTC_ICDISPR13_TINT25 (0x02000000uL) +#define INTC_ICDISPR13_TINT26 (0x04000000uL) +#define INTC_ICDISPR13_TINT27 (0x08000000uL) +#define INTC_ICDISPR13_TINT28 (0x10000000uL) +#define INTC_ICDISPR13_TINT29 (0x20000000uL) +#define INTC_ICDISPR13_TINT30 (0x40000000uL) +#define INTC_ICDISPR13_TINT31 (0x80000000uL) + +#define INTC_ICDISPR14_TINT32 (0x00000001uL) +#define INTC_ICDISPR14_TINT33 (0x00000002uL) +#define INTC_ICDISPR14_TINT34 (0x00000004uL) +#define INTC_ICDISPR14_TINT35 (0x00000008uL) +#define INTC_ICDISPR14_TINT36 (0x00000010uL) +#define INTC_ICDISPR14_TINT37 (0x00000020uL) +#define INTC_ICDISPR14_TINT38 (0x00000040uL) +#define INTC_ICDISPR14_TINT39 (0x00000080uL) +#define INTC_ICDISPR14_TINT40 (0x00000100uL) +#define INTC_ICDISPR14_TINT41 (0x00000200uL) +#define INTC_ICDISPR14_TINT42 (0x00000400uL) +#define INTC_ICDISPR14_TINT43 (0x00000800uL) +#define INTC_ICDISPR14_TINT44 (0x00001000uL) +#define INTC_ICDISPR14_TINT45 (0x00002000uL) +#define INTC_ICDISPR14_TINT46 (0x00004000uL) +#define INTC_ICDISPR14_TINT47 (0x00008000uL) +#define INTC_ICDISPR14_TINT48 (0x00010000uL) +#define INTC_ICDISPR14_TINT49 (0x00020000uL) +#define INTC_ICDISPR14_TINT50 (0x00040000uL) +#define INTC_ICDISPR14_TINT51 (0x00080000uL) +#define INTC_ICDISPR14_TINT52 (0x00100000uL) +#define INTC_ICDISPR14_TINT53 (0x00200000uL) +#define INTC_ICDISPR14_TINT54 (0x00400000uL) +#define INTC_ICDISPR14_TINT55 (0x00800000uL) +#define INTC_ICDISPR14_TINT56 (0x01000000uL) +#define INTC_ICDISPR14_TINT57 (0x02000000uL) +#define INTC_ICDISPR14_TINT58 (0x04000000uL) +#define INTC_ICDISPR14_TINT59 (0x08000000uL) +#define INTC_ICDISPR14_TINT60 (0x10000000uL) +#define INTC_ICDISPR14_TINT61 (0x20000000uL) +#define INTC_ICDISPR14_TINT62 (0x40000000uL) +#define INTC_ICDISPR14_TINT63 (0x80000000uL) + +#define INTC_ICDISPR15_TINT64 (0x00000001uL) +#define INTC_ICDISPR15_TINT65 (0x00000002uL) +#define INTC_ICDISPR15_TINT66 (0x00000004uL) +#define INTC_ICDISPR15_TINT67 (0x00000008uL) +#define INTC_ICDISPR15_TINT68 (0x00000010uL) +#define INTC_ICDISPR15_TINT69 (0x00000020uL) +#define INTC_ICDISPR15_TINT70 (0x00000040uL) +#define INTC_ICDISPR15_TINT71 (0x00000080uL) +#define INTC_ICDISPR15_TINT72 (0x00000100uL) +#define INTC_ICDISPR15_TINT73 (0x00000200uL) +#define INTC_ICDISPR15_TINT74 (0x00000400uL) +#define INTC_ICDISPR15_TINT75 (0x00000800uL) +#define INTC_ICDISPR15_TINT76 (0x00001000uL) +#define INTC_ICDISPR15_TINT77 (0x00002000uL) +#define INTC_ICDISPR15_TINT78 (0x00004000uL) +#define INTC_ICDISPR15_TINT79 (0x00008000uL) +#define INTC_ICDISPR15_TINT80 (0x00010000uL) +#define INTC_ICDISPR15_TINT81 (0x00020000uL) +#define INTC_ICDISPR15_TINT82 (0x00040000uL) +#define INTC_ICDISPR15_TINT83 (0x00080000uL) +#define INTC_ICDISPR15_TINT84 (0x00100000uL) +#define INTC_ICDISPR15_TINT85 (0x00200000uL) +#define INTC_ICDISPR15_TINT86 (0x00400000uL) +#define INTC_ICDISPR15_TINT87 (0x00800000uL) +#define INTC_ICDISPR15_TINT88 (0x01000000uL) +#define INTC_ICDISPR15_TINT89 (0x02000000uL) +#define INTC_ICDISPR15_TINT90 (0x04000000uL) +#define INTC_ICDISPR15_TINT91 (0x08000000uL) +#define INTC_ICDISPR15_TINT92 (0x10000000uL) +#define INTC_ICDISPR15_TINT93 (0x20000000uL) +#define INTC_ICDISPR15_TINT94 (0x40000000uL) +#define INTC_ICDISPR15_TINT95 (0x80000000uL) + +#define INTC_ICDISPR16_TINT96 (0x00000001uL) +#define INTC_ICDISPR16_TINT97 (0x00000002uL) +#define INTC_ICDISPR16_TINT98 (0x00000004uL) +#define INTC_ICDISPR16_TINT99 (0x00000008uL) +#define INTC_ICDISPR16_TINT100 (0x00000010uL) +#define INTC_ICDISPR16_TINT101 (0x00000020uL) +#define INTC_ICDISPR16_TINT102 (0x00000040uL) +#define INTC_ICDISPR16_TINT103 (0x00000080uL) +#define INTC_ICDISPR16_TINT104 (0x00000100uL) +#define INTC_ICDISPR16_TINT105 (0x00000200uL) +#define INTC_ICDISPR16_TINT106 (0x00000400uL) +#define INTC_ICDISPR16_TINT107 (0x00000800uL) +#define INTC_ICDISPR16_TINT108 (0x00001000uL) +#define INTC_ICDISPR16_TINT109 (0x00002000uL) +#define INTC_ICDISPR16_TINT110 (0x00004000uL) +#define INTC_ICDISPR16_TINT111 (0x00008000uL) +#define INTC_ICDISPR16_TINT112 (0x00010000uL) +#define INTC_ICDISPR16_TINT113 (0x00020000uL) +#define INTC_ICDISPR16_TINT114 (0x00040000uL) +#define INTC_ICDISPR16_TINT115 (0x00080000uL) +#define INTC_ICDISPR16_TINT116 (0x00100000uL) +#define INTC_ICDISPR16_TINT117 (0x00200000uL) +#define INTC_ICDISPR16_TINT118 (0x00400000uL) +#define INTC_ICDISPR16_TINT119 (0x00800000uL) +#define INTC_ICDISPR16_TINT120 (0x01000000uL) +#define INTC_ICDISPR16_TINT121 (0x02000000uL) +#define INTC_ICDISPR16_TINT122 (0x04000000uL) +#define INTC_ICDISPR16_TINT123 (0x08000000uL) +#define INTC_ICDISPR16_TINT124 (0x10000000uL) +#define INTC_ICDISPR16_TINT125 (0x20000000uL) +#define INTC_ICDISPR16_TINT126 (0x40000000uL) +#define INTC_ICDISPR16_TINT127 (0x80000000uL) + +#define INTC_ICDISPR17_TINT128 (0x00000001uL) +#define INTC_ICDISPR17_TINT129 (0x00000002uL) +#define INTC_ICDISPR17_TINT130 (0x00000004uL) +#define INTC_ICDISPR17_TINT131 (0x00000008uL) +#define INTC_ICDISPR17_TINT132 (0x00000010uL) +#define INTC_ICDISPR17_TINT133 (0x00000020uL) +#define INTC_ICDISPR17_TINT134 (0x00000040uL) +#define INTC_ICDISPR17_TINT135 (0x00000080uL) +#define INTC_ICDISPR17_TINT136 (0x00000100uL) +#define INTC_ICDISPR17_TINT137 (0x00000200uL) +#define INTC_ICDISPR17_TINT138 (0x00000400uL) +#define INTC_ICDISPR17_TINT139 (0x00000800uL) +#define INTC_ICDISPR17_TINT140 (0x00001000uL) +#define INTC_ICDISPR17_TINT141 (0x00002000uL) +#define INTC_ICDISPR17_TINT142 (0x00004000uL) +#define INTC_ICDISPR17_TINT143 (0x00008000uL) +#define INTC_ICDISPR17_TINT144 (0x00010000uL) +#define INTC_ICDISPR17_TINT145 (0x00020000uL) +#define INTC_ICDISPR17_TINT146 (0x00040000uL) +#define INTC_ICDISPR17_TINT147 (0x00080000uL) +#define INTC_ICDISPR17_TINT148 (0x00100000uL) +#define INTC_ICDISPR17_TINT149 (0x00200000uL) +#define INTC_ICDISPR17_TINT150 (0x00400000uL) +#define INTC_ICDISPR17_TINT151 (0x00800000uL) +#define INTC_ICDISPR17_TINT152 (0x01000000uL) +#define INTC_ICDISPR17_TINT153 (0x02000000uL) +#define INTC_ICDISPR17_TINT154 (0x04000000uL) +#define INTC_ICDISPR17_TINT155 (0x08000000uL) +#define INTC_ICDISPR17_TINT156 (0x10000000uL) +#define INTC_ICDISPR17_TINT157 (0x20000000uL) +#define INTC_ICDISPR17_TINT158 (0x40000000uL) +#define INTC_ICDISPR17_TINT159 (0x80000000uL) + +#define INTC_ICDISPR18_TINT160 (0x00000001uL) +#define INTC_ICDISPR18_TINT161 (0x00000002uL) +#define INTC_ICDISPR18_TINT162 (0x00000004uL) +#define INTC_ICDISPR18_TINT163 (0x00000008uL) +#define INTC_ICDISPR18_TINT164 (0x00000010uL) +#define INTC_ICDISPR18_TINT165 (0x00000020uL) +#define INTC_ICDISPR18_TINT166 (0x00000040uL) +#define INTC_ICDISPR18_TINT167 (0x00000080uL) +#define INTC_ICDISPR18_TINT168 (0x00000100uL) +#define INTC_ICDISPR18_TINT169 (0x00000200uL) +#define INTC_ICDISPR18_TINT170 (0x00000400uL) + +#define INTC_ICDICPR0_SW0 (0x00000001uL) +#define INTC_ICDICPR0_SW1 (0x00000002uL) +#define INTC_ICDICPR0_SW2 (0x00000004uL) +#define INTC_ICDICPR0_SW3 (0x00000008uL) +#define INTC_ICDICPR0_SW4 (0x00000010uL) +#define INTC_ICDICPR0_SW5 (0x00000020uL) +#define INTC_ICDICPR0_SW6 (0x00000040uL) +#define INTC_ICDICPR0_SW7 (0x00000080uL) +#define INTC_ICDICPR0_SW8 (0x00000100uL) +#define INTC_ICDICPR0_SW9 (0x00000200uL) +#define INTC_ICDICPR0_SW10 (0x00000400uL) +#define INTC_ICDICPR0_SW11 (0x00000800uL) +#define INTC_ICDICPR0_SW12 (0x00001000uL) +#define INTC_ICDICPR0_SW13 (0x00002000uL) +#define INTC_ICDICPR0_SW14 (0x00004000uL) +#define INTC_ICDICPR0_SW15 (0x00008000uL) +#define INTC_ICDICPR0_PMUIRQ0 (0x00010000uL) +#define INTC_ICDICPR0_COMMRX0 (0x00020000uL) +#define INTC_ICDICPR0_COMMTX0 (0x00040000uL) +#define INTC_ICDICPR0_CTIIRQ0 (0x00080000uL) + +#define INTC_ICDICPR1_IRQ0 (0x00000001uL) +#define INTC_ICDICPR1_IRQ1 (0x00000002uL) +#define INTC_ICDICPR1_IRQ2 (0x00000004uL) +#define INTC_ICDICPR1_IRQ3 (0x00000008uL) +#define INTC_ICDICPR1_IRQ4 (0x00000010uL) +#define INTC_ICDICPR1_IRQ5 (0x00000020uL) +#define INTC_ICDICPR1_IRQ6 (0x00000040uL) +#define INTC_ICDICPR1_IRQ7 (0x00000080uL) +#define INTC_ICDICPR1_PL310ERR (0x00000100uL) +#define INTC_ICDICPR1_DMAINT0 (0x00000200uL) +#define INTC_ICDICPR1_DMAINT1 (0x00000400uL) +#define INTC_ICDICPR1_DMAINT2 (0x00000800uL) +#define INTC_ICDICPR1_DMAINT3 (0x00001000uL) +#define INTC_ICDICPR1_DMAINT4 (0x00002000uL) +#define INTC_ICDICPR1_DMAINT5 (0x00004000uL) +#define INTC_ICDICPR1_DMAINT6 (0x00008000uL) +#define INTC_ICDICPR1_DMAINT7 (0x00010000uL) +#define INTC_ICDICPR1_DMAINT8 (0x00020000uL) +#define INTC_ICDICPR1_DMAINT9 (0x00040000uL) +#define INTC_ICDICPR1_DMAINT10 (0x00080000uL) +#define INTC_ICDICPR1_DMAINT11 (0x00100000uL) +#define INTC_ICDICPR1_DMAINT12 (0x00200000uL) +#define INTC_ICDICPR1_DMAINT13 (0x00400000uL) +#define INTC_ICDICPR1_DMAINT14 (0x00800000uL) +#define INTC_ICDICPR1_DMAINT15 (0x01000000uL) +#define INTC_ICDICPR1_DMAERR (0x02000000uL) + +#define INTC_ICDICPR2_USBI0 (0x00000200uL) +#define INTC_ICDICPR2_USBI1 (0x00000400uL) +#define INTC_ICDICPR2_S0_VI_VSYNC0 (0x00000800uL) +#define INTC_ICDICPR2_S0_LO_VSYNC0 (0x00001000uL) +#define INTC_ICDICPR2_S0_VSYNCERR0 (0x00002000uL) +#define INTC_ICDICPR2_GR3_VLINE0 (0x00004000uL) +#define INTC_ICDICPR2_S0_VFIELD0 (0x00008000uL) +#define INTC_ICDICPR2_IV1_VBUFERR0 (0x00010000uL) +#define INTC_ICDICPR2_IV3_VBUFERR0 (0x00020000uL) +#define INTC_ICDICPR2_IV5_VBUFERR0 (0x00040000uL) +#define INTC_ICDICPR2_IV6_VBUFERR0 (0x00080000uL) +#define INTC_ICDICPR2_S0_WLINE0 (0x00100000uL) +#define INTC_ICDICPR2_S1_VI_VSYNC0 (0x00200000uL) +#define INTC_ICDICPR2_S1_LO_VSYNC0 (0x00400000uL) +#define INTC_ICDICPR2_S1_VSYNCERR0 (0x00800000uL) +#define INTC_ICDICPR2_S1_VFIELD0 (0x01000000uL) +#define INTC_ICDICPR2_IV2_VBUFERR0 (0x02000000uL) +#define INTC_ICDICPR2_IV4_VBUFERR0 (0x04000000uL) +#define INTC_ICDICPR2_S1_WLINE0 (0x08000000uL) +#define INTC_ICDICPR2_OIR_VI_VSYNC0 (0x10000000uL) +#define INTC_ICDICPR2_OIR_LO_VSYNC0 (0x20000000uL) +#define INTC_ICDICPR2_OIR_VSYNCERR0 (0x40000000uL) +#define INTC_ICDICPR2_OIR_VFIELD0 (0x80000000uL) + +#define INTC_ICDICPR3_IV7_VBUFERR0 (0x00000001uL) +#define INTC_ICDICPR3_IV8_VBUFERR0 (0x00000002uL) +#define INTC_ICDICPR3_S0_VI_VSYNC1 (0x00000008uL) +#define INTC_ICDICPR3_S0_LO_VSYNC1 (0x00000010uL) +#define INTC_ICDICPR3_S0_VSYNCERR1 (0x00000020uL) +#define INTC_ICDICPR3_GR3_VLINE1 (0x00000040uL) +#define INTC_ICDICPR3_S0_VFIELD1 (0x00000080uL) +#define INTC_ICDICPR3_IV1_VBUFERR1 (0x00000100uL) +#define INTC_ICDICPR3_IV3_VBUFERR1 (0x00000200uL) +#define INTC_ICDICPR3_IV5_VBUFERR1 (0x00000400uL) +#define INTC_ICDICPR3_IV6_VBUFERR1 (0x00000800uL) +#define INTC_ICDICPR3_S0_WLINE1 (0x00001000uL) +#define INTC_ICDICPR3_S1_VI_VSYNC1 (0x00002000uL) +#define INTC_ICDICPR3_S1_LO_VSYNC1 (0x00004000uL) +#define INTC_ICDICPR3_S1_VSYNCERR1 (0x00008000uL) +#define INTC_ICDICPR3_S1_VFIELD1 (0x00010000uL) +#define INTC_ICDICPR3_IV2_VBUFERR1 (0x00020000uL) +#define INTC_ICDICPR3_IV4_VBUFERR1 (0x00040000uL) +#define INTC_ICDICPR3_S1_WLINE1 (0x00080000uL) +#define INTC_ICDICPR3_OIR_VI_VSYNC1 (0x00100000uL) +#define INTC_ICDICPR3_OIR_LO_VSYNC1 (0x00200000uL) +#define INTC_ICDICPR3_OIR_VLINE1 (0x00400000uL) +#define INTC_ICDICPR3_OIR_VFIELD1 (0x00800000uL) +#define INTC_ICDICPR3_IV7_VBUFERR1 (0x01000000uL) +#define INTC_ICDICPR3_IV8_VBUFERR1 (0x02000000uL) +#define INTC_ICDICPR3_IMRDI (0x08000000uL) +#define INTC_ICDICPR3_IMR2I0 (0x10000000uL) +#define INTC_ICDICPR3_IMR2I1 (0x20000000uL) +#define INTC_ICDICPR3_JEDI (0x40000000uL) +#define INTC_ICDICPR3_JDTI (0x80000000uL) + +#define INTC_ICDICPR4_CMP0 (0x00000001uL) +#define INTC_ICDICPR4_CMP1 (0x00000002uL) +#define INTC_ICDICPR4_INT0 (0x00000004uL) +#define INTC_ICDICPR4_INT1 (0x00000008uL) +#define INTC_ICDICPR4_INT2 (0x00000010uL) +#define INTC_ICDICPR4_INT3 (0x00000020uL) +#define INTC_ICDICPR4_OSTM0TINT (0x00000040uL) +#define INTC_ICDICPR4_OSTM1TINT (0x00000080uL) +#define INTC_ICDICPR4_CMI (0x00000100uL) +#define INTC_ICDICPR4_WTOUT (0x00000200uL) +#define INTC_ICDICPR4_ITI (0x00000400uL) +#define INTC_ICDICPR4_TGI0A (0x00000800uL) +#define INTC_ICDICPR4_TGI0B (0x00001000uL) +#define INTC_ICDICPR4_TGI0C (0x00002000uL) +#define INTC_ICDICPR4_TGI0D (0x00004000uL) +#define INTC_ICDICPR4_TGI0V (0x00008000uL) +#define INTC_ICDICPR4_TGI0E (0x00010000uL) +#define INTC_ICDICPR4_TGI0F (0x00020000uL) +#define INTC_ICDICPR4_TGI1A (0x00040000uL) +#define INTC_ICDICPR4_TGI1B (0x00080000uL) +#define INTC_ICDICPR4_TGI1V (0x00100000uL) +#define INTC_ICDICPR4_TGI1U (0x00200000uL) +#define INTC_ICDICPR4_TGI2A (0x00400000uL) +#define INTC_ICDICPR4_TGI2B (0x00800000uL) +#define INTC_ICDICPR4_TGI2V (0x01000000uL) +#define INTC_ICDICPR4_TGI2U (0x02000000uL) +#define INTC_ICDICPR4_TGI3A (0x04000000uL) +#define INTC_ICDICPR4_TGI3B (0x08000000uL) +#define INTC_ICDICPR4_TGI3C (0x10000000uL) +#define INTC_ICDICPR4_TGI3D (0x20000000uL) +#define INTC_ICDICPR4_TGI3V (0x40000000uL) +#define INTC_ICDICPR4_TGI4A (0x80000000uL) + +#define INTC_ICDICPR5_TGI4B (0x00000001uL) +#define INTC_ICDICPR5_TGI4C (0x00000002uL) +#define INTC_ICDICPR5_TGI4D (0x00000004uL) +#define INTC_ICDICPR5_TGI4V (0x00000008uL) +#define INTC_ICDICPR5_CMI1 (0x00000010uL) +#define INTC_ICDICPR5_CMI2 (0x00000020uL) +#define INTC_ICDICPR5_SGDEI0 (0x00000040uL) +#define INTC_ICDICPR5_SGDEI1 (0x00000080uL) +#define INTC_ICDICPR5_SGDEI2 (0x00000100uL) +#define INTC_ICDICPR5_SGDEI3 (0x00000200uL) +#define INTC_ICDICPR5_ADI (0x00000400uL) +#define INTC_ICDICPR5_LMTI (0x00000800uL) +#define INTC_ICDICPR5_SSII0 (0x00001000uL) +#define INTC_ICDICPR5_SSIRXI0 (0x00002000uL) +#define INTC_ICDICPR5_SSITXI0 (0x00004000uL) +#define INTC_ICDICPR5_SSII1 (0x00008000uL) +#define INTC_ICDICPR5_SSIRXI1 (0x00010000uL) +#define INTC_ICDICPR5_SSITXI1 (0x00020000uL) +#define INTC_ICDICPR5_SSII2 (0x00040000uL) +#define INTC_ICDICPR5_SSIRTI2 (0x00080000uL) +#define INTC_ICDICPR5_SSII3 (0x00100000uL) +#define INTC_ICDICPR5_SSIRXI3 (0x00200000uL) +#define INTC_ICDICPR5_SSITXI3 (0x00400000uL) +#define INTC_ICDICPR5_SSII4 (0x00800000uL) +#define INTC_ICDICPR5_SSIRTI4 (0x01000000uL) +#define INTC_ICDICPR5_SSII5 (0x02000000uL) +#define INTC_ICDICPR5_SSIRXI5 (0x04000000uL) +#define INTC_ICDICPR5_SSITXI5 (0x08000000uL) +#define INTC_ICDICPR5_SPDIFI (0x10000000uL) +#define INTC_ICDICPR5_INTIICTEI0 (0x20000000uL) +#define INTC_ICDICPR5_INTIICRI0 (0x40000000uL) +#define INTC_ICDICPR5_INTIICTI0 (0x80000000uL) + +#define INTC_ICDICPR6_INTIICSPI0 (0x00000001uL) +#define INTC_ICDICPR6_INTIICSTI0 (0x00000002uL) +#define INTC_ICDICPR6_INTIICNAKI0 (0x00000004uL) +#define INTC_ICDICPR6_INTIICALI0 (0x00000008uL) +#define INTC_ICDICPR6_INTIICTMOI0 (0x00000010uL) +#define INTC_ICDICPR6_INTIICTEI1 (0x00000020uL) +#define INTC_ICDICPR6_INTIICRI1 (0x00000040uL) +#define INTC_ICDICPR6_INTIICTI1 (0x00000080uL) +#define INTC_ICDICPR6_INTIICSPI1 (0x00000100uL) +#define INTC_ICDICPR6_INTIICSTI1 (0x00000200uL) +#define INTC_ICDICPR6_INTIICNAKI1 (0x00000400uL) +#define INTC_ICDICPR6_INTIICALI1 (0x00000800uL) +#define INTC_ICDICPR6_INTIICTMOI1 (0x00001000uL) +#define INTC_ICDICPR6_INTIICTEI2 (0x00002000uL) +#define INTC_ICDICPR6_INTIICRI2 (0x00004000uL) +#define INTC_ICDICPR6_INTIICTI2 (0x00008000uL) +#define INTC_ICDICPR6_INTIICSPI2 (0x00010000uL) +#define INTC_ICDICPR6_INTIICSTI2 (0x00020000uL) +#define INTC_ICDICPR6_INTIICNAKI2 (0x00040000uL) +#define INTC_ICDICPR6_INTIICALI2 (0x00080000uL) +#define INTC_ICDICPR6_INTIICTMOI2 (0x00100000uL) +#define INTC_ICDICPR6_INTIICTEI3 (0x00200000uL) +#define INTC_ICDICPR6_INTIICRI3 (0x00400000uL) +#define INTC_ICDICPR6_INTIICTI3 (0x00800000uL) +#define INTC_ICDICPR6_INTIICSPI3 (0x01000000uL) +#define INTC_ICDICPR6_INTIICSTI3 (0x02000000uL) +#define INTC_ICDICPR6_INTIICNAKI3 (0x04000000uL) +#define INTC_ICDICPR6_INTIICALI3 (0x08000000uL) +#define INTC_ICDICPR6_INTIICTMOI3 (0x10000000uL) +#define INTC_ICDICPR6_BRI0 (0x20000000uL) +#define INTC_ICDICPR6_ERI0 (0x40000000uL) +#define INTC_ICDICPR6_RXI0 (0x80000000uL) + +#define INTC_ICDICPR7_TXI0 (0x00000001uL) +#define INTC_ICDICPR7_BRI1 (0x00000002uL) +#define INTC_ICDICPR7_ERI1 (0x00000004uL) +#define INTC_ICDICPR7_RXI1 (0x00000008uL) +#define INTC_ICDICPR7_TXI1 (0x00000010uL) +#define INTC_ICDICPR7_BRI2 (0x00000020uL) +#define INTC_ICDICPR7_ERI2 (0x00000040uL) +#define INTC_ICDICPR7_RXI2 (0x00000080uL) +#define INTC_ICDICPR7_TXI2 (0x00000100uL) +#define INTC_ICDICPR7_BRI3 (0x00000200uL) +#define INTC_ICDICPR7_ERI3 (0x00000400uL) +#define INTC_ICDICPR7_RXI3 (0x00000800uL) +#define INTC_ICDICPR7_TXI3 (0x00001000uL) +#define INTC_ICDICPR7_BRI4 (0x00002000uL) +#define INTC_ICDICPR7_ERI4 (0x00004000uL) +#define INTC_ICDICPR7_RXI4 (0x00008000uL) +#define INTC_ICDICPR7_TXI4 (0x00010000uL) +#define INTC_ICDICPR7_BRI5 (0x00020000uL) +#define INTC_ICDICPR7_ERI5 (0x00040000uL) +#define INTC_ICDICPR7_RXI5 (0x00080000uL) +#define INTC_ICDICPR7_TXI5 (0x00100000uL) +#define INTC_ICDICPR7_BRI6 (0x00200000uL) +#define INTC_ICDICPR7_ERI6 (0x00400000uL) +#define INTC_ICDICPR7_RXI6 (0x00800000uL) +#define INTC_ICDICPR7_TXI6 (0x01000000uL) +#define INTC_ICDICPR7_BRI7 (0x02000000uL) +#define INTC_ICDICPR7_ERI7 (0x04000000uL) +#define INTC_ICDICPR7_RXI7 (0x08000000uL) +#define INTC_ICDICPR7_TXI7 (0x10000000uL) +#define INTC_ICDICPR7_INTRCANGERR (0x20000000uL) +#define INTC_ICDICPR7_INTRCANGRECC (0x40000000uL) +#define INTC_ICDICPR7_INTRCAN0REC (0x80000000uL) + +#define INTC_ICDICPR8_INTRCAN0ERR (0x00000001uL) +#define INTC_ICDICPR8_INTRCAN0TRX (0x00000002uL) +#define INTC_ICDICPR8_INTRCAN1REC (0x00000004uL) +#define INTC_ICDICPR8_INTRCAN1ERR (0x00000008uL) +#define INTC_ICDICPR8_INTRCAN1TRX (0x00000010uL) +#define INTC_ICDICPR8_INTRCAN2REC (0x00000020uL) +#define INTC_ICDICPR8_INTRCAN2ERR (0x00000040uL) +#define INTC_ICDICPR8_INTRCAN2TRX (0x00000080uL) +#define INTC_ICDICPR8_INTRCAN3REC (0x00000100uL) +#define INTC_ICDICPR8_INTRCAN3ERR (0x00000200uL) +#define INTC_ICDICPR8_INTRCAN3TRX (0x00000400uL) +#define INTC_ICDICPR8_INTRCAN4REC (0x00000800uL) +#define INTC_ICDICPR8_INTRCAN4ERR (0x00001000uL) +#define INTC_ICDICPR8_INTRCAN4TRX (0x00002000uL) +#define INTC_ICDICPR8_SPEI0 (0x00004000uL) +#define INTC_ICDICPR8_SPRI0 (0x00008000uL) +#define INTC_ICDICPR8_SPTI0 (0x00010000uL) +#define INTC_ICDICPR8_SPEI1 (0x00020000uL) +#define INTC_ICDICPR8_SPRI1 (0x00040000uL) +#define INTC_ICDICPR8_SPTI1 (0x00080000uL) +#define INTC_ICDICPR8_SPEI2 (0x00100000uL) +#define INTC_ICDICPR8_SPRI2 (0x00200000uL) +#define INTC_ICDICPR8_SPTI2 (0x00400000uL) +#define INTC_ICDICPR8_SPEI3 (0x00800000uL) +#define INTC_ICDICPR8_SPRI3 (0x01000000uL) +#define INTC_ICDICPR8_SPTI3 (0x02000000uL) +#define INTC_ICDICPR8_SPEI4 (0x04000000uL) +#define INTC_ICDICPR8_SPRI4 (0x08000000uL) +#define INTC_ICDICPR8_SPTI4 (0x10000000uL) +#define INTC_ICDICPR8_IEBBTD (0x20000000uL) +#define INTC_ICDICPR8_IEBBTERR (0x40000000uL) +#define INTC_ICDICPR8_IEBBTSTA (0x80000000uL) + +#define INTC_ICDICPR9_IEBBTV (0x00000001uL) +#define INTC_ICDICPR9_ISY (0x00000002uL) +#define INTC_ICDICPR9_IERR (0x00000004uL) +#define INTC_ICDICPR9_ITARG (0x00000008uL) +#define INTC_ICDICPR9_ISEC (0x00000010uL) +#define INTC_ICDICPR9_IBUF (0x00000020uL) +#define INTC_ICDICPR9_IREADY (0x00000040uL) +#define INTC_ICDICPR9_FLSTE (0x00000080uL) +#define INTC_ICDICPR9_FLTENDI (0x00000100uL) +#define INTC_ICDICPR9_FLTREQ0I (0x00000200uL) +#define INTC_ICDICPR9_FLTREQ1I (0x00000400uL) +#define INTC_ICDICPR9_MMC0 (0x00000800uL) +#define INTC_ICDICPR9_MMC1 (0x00001000uL) +#define INTC_ICDICPR9_MMC2 (0x00002000uL) +#define INTC_ICDICPR9_SDHI0_3 (0x00004000uL) +#define INTC_ICDICPR9_SDHI0_0 (0x00008000uL) +#define INTC_ICDICPR9_SDHI0_1 (0x00010000uL) +#define INTC_ICDICPR9_SDHI1_3 (0x00020000uL) +#define INTC_ICDICPR9_SDHI1_0 (0x00040000uL) +#define INTC_ICDICPR9_SDHI1_1 (0x00080000uL) +#define INTC_ICDICPR9_ARM (0x00100000uL) +#define INTC_ICDICPR9_PRD (0x00200000uL) +#define INTC_ICDICPR9_CUP (0x00400000uL) +#define INTC_ICDICPR9_SCUAI0 (0x00800000uL) +#define INTC_ICDICPR9_SCUAI1 (0x01000000uL) +#define INTC_ICDICPR9_SCUFDI0 (0x02000000uL) +#define INTC_ICDICPR9_SCUFDI1 (0x04000000uL) +#define INTC_ICDICPR9_SCUFDI2 (0x08000000uL) +#define INTC_ICDICPR9_SCUFDI3 (0x10000000uL) +#define INTC_ICDICPR9_SCUFUI0 (0x20000000uL) +#define INTC_ICDICPR9_SCUFUI1 (0x40000000uL) +#define INTC_ICDICPR9_SCUFUI2 (0x80000000uL) + +#define INTC_ICDICPR10_SCUFUI3 (0x00000001uL) +#define INTC_ICDICPR10_SCUDVI0 (0x00000002uL) +#define INTC_ICDICPR10_SCUDVI1 (0x00000004uL) +#define INTC_ICDICPR10_SCUDVI2 (0x00000008uL) +#define INTC_ICDICPR10_SCUDVI3 (0x00000010uL) +#define INTC_ICDICPR10_MLB_CINT (0x00000020uL) +#define INTC_ICDICPR10_MLB_SINT (0x00000040uL) +#define INTC_ICDICPR10_DRC0 (0x00000080uL) +#define INTC_ICDICPR10_DRC1 (0x00000100uL) +#define INTC_ICDICPR10_LINI0_INT_T (0x00000800uL) +#define INTC_ICDICPR10_LINI0_INT_R (0x00001000uL) +#define INTC_ICDICPR10_LINI0_INT_S (0x00002000uL) +#define INTC_ICDICPR10_LINI0_INT_M (0x00004000uL) +#define INTC_ICDICPR10_LINI1_INT_T (0x00008000uL) +#define INTC_ICDICPR10_LINI1_INT_R (0x00010000uL) +#define INTC_ICDICPR10_LINI1_INT_S (0x00020000uL) +#define INTC_ICDICPR10_LINI1_INT_M (0x00040000uL) +#define INTC_ICDICPR10_ERI0 (0x08000000uL) +#define INTC_ICDICPR10_RXI0 (0x10000000uL) +#define INTC_ICDICPR10_TXI0 (0x20000000uL) +#define INTC_ICDICPR10_TEI0 (0x40000000uL) +#define INTC_ICDICPR10_ERI1 (0x80000000uL) + +#define INTC_ICDICPR11_RXI1 (0x00000001uL) +#define INTC_ICDICPR11_TXI1 (0x00000002uL) +#define INTC_ICDICPR11_TEI1 (0x00000004uL) +#define INTC_ICDICPR11_AVBI_DATA (0x00000008uL) +#define INTC_ICDICPR11_AVBI_ERROR (0x00000010uL) +#define INTC_ICDICPR11_AVBI_MANAGE (0x00000020uL) +#define INTC_ICDICPR11_AVBI_MAC (0x00000040uL) +#define INTC_ICDICPR11_ETHERI (0x00000080uL) +#define INTC_ICDICPR11_CEUI (0x00001000uL) +#define INTC_ICDICPR11_H2XMLB_ERRINT (0x20000000uL) +#define INTC_ICDICPR11_H2XIC1_ERRINT (0x40000000uL) +#define INTC_ICDICPR11_X2HPERI1_ERRINT (0x80000000uL) + +#define INTC_ICDICPR12_X2HPERI2_ERRINT (0x00000001uL) +#define INTC_ICDICPR12_X2HPERI34_ERRINT (0x00000002uL) +#define INTC_ICDICPR12_X2HPERI5_ERRINT (0x00000004uL) +#define INTC_ICDICPR12_X2HPERI67_ERRINT (0x00000008uL) +#define INTC_ICDICPR12_X2HDBGR_ERRINT (0x00000010uL) +#define INTC_ICDICPR12_X2HBSC_ERRINT (0x00000020uL) +#define INTC_ICDICPR12_X2HSPI1_ERRINT (0x00000040uL) +#define INTC_ICDICPR12_X2HSPI2_ERRINT (0x00000080uL) +#define INTC_ICDICPR12_PRRI (0x00000100uL) +#define INTC_ICDICPR12_IFEI0 (0x00000200uL) +#define INTC_ICDICPR12_OFFI0 (0x00000400uL) +#define INTC_ICDICPR12_PFVEI0 (0x00000800uL) +#define INTC_ICDICPR12_IFEI1 (0x00001000uL) +#define INTC_ICDICPR12_OFFI1 (0x00002000uL) +#define INTC_ICDICPR12_PFVEI1 (0x00004000uL) + +#define INTC_ICDICPR13_TINT0 (0x00000001uL) +#define INTC_ICDICPR13_TINT1 (0x00000002uL) +#define INTC_ICDICPR13_TINT2 (0x00000004uL) +#define INTC_ICDICPR13_TINT3 (0x00000008uL) +#define INTC_ICDICPR13_TINT4 (0x00000010uL) +#define INTC_ICDICPR13_TINT5 (0x00000020uL) +#define INTC_ICDICPR13_TINT6 (0x00000040uL) +#define INTC_ICDICPR13_TINT7 (0x00000080uL) +#define INTC_ICDICPR13_TINT8 (0x00000100uL) +#define INTC_ICDICPR13_TINT9 (0x00000200uL) +#define INTC_ICDICPR13_TINT10 (0x00000400uL) +#define INTC_ICDICPR13_TINT11 (0x00000800uL) +#define INTC_ICDICPR13_TINT12 (0x00001000uL) +#define INTC_ICDICPR13_TINT13 (0x00002000uL) +#define INTC_ICDICPR13_TINT14 (0x00004000uL) +#define INTC_ICDICPR13_TINT15 (0x00008000uL) +#define INTC_ICDICPR13_TINT16 (0x00010000uL) +#define INTC_ICDICPR13_TINT17 (0x00020000uL) +#define INTC_ICDICPR13_TINT18 (0x00040000uL) +#define INTC_ICDICPR13_TINT19 (0x00080000uL) +#define INTC_ICDICPR13_TINT20 (0x00100000uL) +#define INTC_ICDICPR13_TINT21 (0x00200000uL) +#define INTC_ICDICPR13_TINT22 (0x00400000uL) +#define INTC_ICDICPR13_TINT23 (0x00800000uL) +#define INTC_ICDICPR13_TINT24 (0x01000000uL) +#define INTC_ICDICPR13_TINT25 (0x02000000uL) +#define INTC_ICDICPR13_TINT26 (0x04000000uL) +#define INTC_ICDICPR13_TINT27 (0x08000000uL) +#define INTC_ICDICPR13_TINT28 (0x10000000uL) +#define INTC_ICDICPR13_TINT29 (0x20000000uL) +#define INTC_ICDICPR13_TINT30 (0x40000000uL) +#define INTC_ICDICPR13_TINT31 (0x80000000uL) + +#define INTC_ICDICPR14_TINT32 (0x00000001uL) +#define INTC_ICDICPR14_TINT33 (0x00000002uL) +#define INTC_ICDICPR14_TINT34 (0x00000004uL) +#define INTC_ICDICPR14_TINT35 (0x00000008uL) +#define INTC_ICDICPR14_TINT36 (0x00000010uL) +#define INTC_ICDICPR14_TINT37 (0x00000020uL) +#define INTC_ICDICPR14_TINT38 (0x00000040uL) +#define INTC_ICDICPR14_TINT39 (0x00000080uL) +#define INTC_ICDICPR14_TINT40 (0x00000100uL) +#define INTC_ICDICPR14_TINT41 (0x00000200uL) +#define INTC_ICDICPR14_TINT42 (0x00000400uL) +#define INTC_ICDICPR14_TINT43 (0x00000800uL) +#define INTC_ICDICPR14_TINT44 (0x00001000uL) +#define INTC_ICDICPR14_TINT45 (0x00002000uL) +#define INTC_ICDICPR14_TINT46 (0x00004000uL) +#define INTC_ICDICPR14_TINT47 (0x00008000uL) +#define INTC_ICDICPR14_TINT48 (0x00010000uL) +#define INTC_ICDICPR14_TINT49 (0x00020000uL) +#define INTC_ICDICPR14_TINT50 (0x00040000uL) +#define INTC_ICDICPR14_TINT51 (0x00080000uL) +#define INTC_ICDICPR14_TINT52 (0x00100000uL) +#define INTC_ICDICPR14_TINT53 (0x00200000uL) +#define INTC_ICDICPR14_TINT54 (0x00400000uL) +#define INTC_ICDICPR14_TINT55 (0x00800000uL) +#define INTC_ICDICPR14_TINT56 (0x01000000uL) +#define INTC_ICDICPR14_TINT57 (0x02000000uL) +#define INTC_ICDICPR14_TINT58 (0x04000000uL) +#define INTC_ICDICPR14_TINT59 (0x08000000uL) +#define INTC_ICDICPR14_TINT60 (0x10000000uL) +#define INTC_ICDICPR14_TINT61 (0x20000000uL) +#define INTC_ICDICPR14_TINT62 (0x40000000uL) +#define INTC_ICDICPR14_TINT63 (0x80000000uL) + +#define INTC_ICDICPR15_TINT64 (0x00000001uL) +#define INTC_ICDICPR15_TINT65 (0x00000002uL) +#define INTC_ICDICPR15_TINT66 (0x00000004uL) +#define INTC_ICDICPR15_TINT67 (0x00000008uL) +#define INTC_ICDICPR15_TINT68 (0x00000010uL) +#define INTC_ICDICPR15_TINT69 (0x00000020uL) +#define INTC_ICDICPR15_TINT70 (0x00000040uL) +#define INTC_ICDICPR15_TINT71 (0x00000080uL) +#define INTC_ICDICPR15_TINT72 (0x00000100uL) +#define INTC_ICDICPR15_TINT73 (0x00000200uL) +#define INTC_ICDICPR15_TINT74 (0x00000400uL) +#define INTC_ICDICPR15_TINT75 (0x00000800uL) +#define INTC_ICDICPR15_TINT76 (0x00001000uL) +#define INTC_ICDICPR15_TINT77 (0x00002000uL) +#define INTC_ICDICPR15_TINT78 (0x00004000uL) +#define INTC_ICDICPR15_TINT79 (0x00008000uL) +#define INTC_ICDICPR15_TINT80 (0x00010000uL) +#define INTC_ICDICPR15_TINT81 (0x00020000uL) +#define INTC_ICDICPR15_TINT82 (0x00040000uL) +#define INTC_ICDICPR15_TINT83 (0x00080000uL) +#define INTC_ICDICPR15_TINT84 (0x00100000uL) +#define INTC_ICDICPR15_TINT85 (0x00200000uL) +#define INTC_ICDICPR15_TINT86 (0x00400000uL) +#define INTC_ICDICPR15_TINT87 (0x00800000uL) +#define INTC_ICDICPR15_TINT88 (0x01000000uL) +#define INTC_ICDICPR15_TINT89 (0x02000000uL) +#define INTC_ICDICPR15_TINT90 (0x04000000uL) +#define INTC_ICDICPR15_TINT91 (0x08000000uL) +#define INTC_ICDICPR15_TINT92 (0x10000000uL) +#define INTC_ICDICPR15_TINT93 (0x20000000uL) +#define INTC_ICDICPR15_TINT94 (0x40000000uL) +#define INTC_ICDICPR15_TINT95 (0x80000000uL) + +#define INTC_ICDICPR16_TINT96 (0x00000001uL) +#define INTC_ICDICPR16_TINT97 (0x00000002uL) +#define INTC_ICDICPR16_TINT98 (0x00000004uL) +#define INTC_ICDICPR16_TINT99 (0x00000008uL) +#define INTC_ICDICPR16_TINT100 (0x00000010uL) +#define INTC_ICDICPR16_TINT101 (0x00000020uL) +#define INTC_ICDICPR16_TINT102 (0x00000040uL) +#define INTC_ICDICPR16_TINT103 (0x00000080uL) +#define INTC_ICDICPR16_TINT104 (0x00000100uL) +#define INTC_ICDICPR16_TINT105 (0x00000200uL) +#define INTC_ICDICPR16_TINT106 (0x00000400uL) +#define INTC_ICDICPR16_TINT107 (0x00000800uL) +#define INTC_ICDICPR16_TINT108 (0x00001000uL) +#define INTC_ICDICPR16_TINT109 (0x00002000uL) +#define INTC_ICDICPR16_TINT110 (0x00004000uL) +#define INTC_ICDICPR16_TINT111 (0x00008000uL) +#define INTC_ICDICPR16_TINT112 (0x00010000uL) +#define INTC_ICDICPR16_TINT113 (0x00020000uL) +#define INTC_ICDICPR16_TINT114 (0x00040000uL) +#define INTC_ICDICPR16_TINT115 (0x00080000uL) +#define INTC_ICDICPR16_TINT116 (0x00100000uL) +#define INTC_ICDICPR16_TINT117 (0x00200000uL) +#define INTC_ICDICPR16_TINT118 (0x00400000uL) +#define INTC_ICDICPR16_TINT119 (0x00800000uL) +#define INTC_ICDICPR16_TINT120 (0x01000000uL) +#define INTC_ICDICPR16_TINT121 (0x02000000uL) +#define INTC_ICDICPR16_TINT122 (0x04000000uL) +#define INTC_ICDICPR16_TINT123 (0x08000000uL) +#define INTC_ICDICPR16_TINT124 (0x10000000uL) +#define INTC_ICDICPR16_TINT125 (0x20000000uL) +#define INTC_ICDICPR16_TINT126 (0x40000000uL) +#define INTC_ICDICPR16_TINT127 (0x80000000uL) + +#define INTC_ICDICPR17_TINT128 (0x00000001uL) +#define INTC_ICDICPR17_TINT129 (0x00000002uL) +#define INTC_ICDICPR17_TINT130 (0x00000004uL) +#define INTC_ICDICPR17_TINT131 (0x00000008uL) +#define INTC_ICDICPR17_TINT132 (0x00000010uL) +#define INTC_ICDICPR17_TINT133 (0x00000020uL) +#define INTC_ICDICPR17_TINT134 (0x00000040uL) +#define INTC_ICDICPR17_TINT135 (0x00000080uL) +#define INTC_ICDICPR17_TINT136 (0x00000100uL) +#define INTC_ICDICPR17_TINT137 (0x00000200uL) +#define INTC_ICDICPR17_TINT138 (0x00000400uL) +#define INTC_ICDICPR17_TINT139 (0x00000800uL) +#define INTC_ICDICPR17_TINT140 (0x00001000uL) +#define INTC_ICDICPR17_TINT141 (0x00002000uL) +#define INTC_ICDICPR17_TINT142 (0x00004000uL) +#define INTC_ICDICPR17_TINT143 (0x00008000uL) +#define INTC_ICDICPR17_TINT144 (0x00010000uL) +#define INTC_ICDICPR17_TINT145 (0x00020000uL) +#define INTC_ICDICPR17_TINT146 (0x00040000uL) +#define INTC_ICDICPR17_TINT147 (0x00080000uL) +#define INTC_ICDICPR17_TINT148 (0x00100000uL) +#define INTC_ICDICPR17_TINT149 (0x00200000uL) +#define INTC_ICDICPR17_TINT150 (0x00400000uL) +#define INTC_ICDICPR17_TINT151 (0x00800000uL) +#define INTC_ICDICPR17_TINT152 (0x01000000uL) +#define INTC_ICDICPR17_TINT153 (0x02000000uL) +#define INTC_ICDICPR17_TINT154 (0x04000000uL) +#define INTC_ICDICPR17_TINT155 (0x08000000uL) +#define INTC_ICDICPR17_TINT156 (0x10000000uL) +#define INTC_ICDICPR17_TINT157 (0x20000000uL) +#define INTC_ICDICPR17_TINT158 (0x40000000uL) +#define INTC_ICDICPR17_TINT159 (0x80000000uL) + +#define INTC_ICDICPR18_TINT160 (0x00000001uL) +#define INTC_ICDICPR18_TINT161 (0x00000002uL) +#define INTC_ICDICPR18_TINT162 (0x00000004uL) +#define INTC_ICDICPR18_TINT163 (0x00000008uL) +#define INTC_ICDICPR18_TINT164 (0x00000010uL) +#define INTC_ICDICPR18_TINT165 (0x00000020uL) +#define INTC_ICDICPR18_TINT166 (0x00000040uL) +#define INTC_ICDICPR18_TINT167 (0x00000080uL) +#define INTC_ICDICPR18_TINT168 (0x00000100uL) +#define INTC_ICDICPR18_TINT169 (0x00000200uL) +#define INTC_ICDICPR18_TINT170 (0x00000400uL) + +#define INTC_ICDABR0_SW0 (0x00000001uL) +#define INTC_ICDABR0_SW1 (0x00000002uL) +#define INTC_ICDABR0_SW2 (0x00000004uL) +#define INTC_ICDABR0_SW3 (0x00000008uL) +#define INTC_ICDABR0_SW4 (0x00000010uL) +#define INTC_ICDABR0_SW5 (0x00000020uL) +#define INTC_ICDABR0_SW6 (0x00000040uL) +#define INTC_ICDABR0_SW7 (0x00000080uL) +#define INTC_ICDABR0_SW8 (0x00000100uL) +#define INTC_ICDABR0_SW9 (0x00000200uL) +#define INTC_ICDABR0_SW10 (0x00000400uL) +#define INTC_ICDABR0_SW11 (0x00000800uL) +#define INTC_ICDABR0_SW12 (0x00001000uL) +#define INTC_ICDABR0_SW13 (0x00002000uL) +#define INTC_ICDABR0_SW14 (0x00004000uL) +#define INTC_ICDABR0_SW15 (0x00008000uL) +#define INTC_ICDABR0_PMUIRQ0 (0x00010000uL) +#define INTC_ICDABR0_COMMRX0 (0x00020000uL) +#define INTC_ICDABR0_COMMTX0 (0x00040000uL) +#define INTC_ICDABR0_CTIIRQ0 (0x00080000uL) + +#define INTC_ICDABR1_IRQ0 (0x00000001uL) +#define INTC_ICDABR1_IRQ1 (0x00000002uL) +#define INTC_ICDABR1_IRQ2 (0x00000004uL) +#define INTC_ICDABR1_IRQ3 (0x00000008uL) +#define INTC_ICDABR1_IRQ4 (0x00000010uL) +#define INTC_ICDABR1_IRQ5 (0x00000020uL) +#define INTC_ICDABR1_IRQ6 (0x00000040uL) +#define INTC_ICDABR1_IRQ7 (0x00000080uL) +#define INTC_ICDABR1_PL310ERR (0x00000100uL) +#define INTC_ICDABR1_DMAINT0 (0x00000200uL) +#define INTC_ICDABR1_DMAINT1 (0x00000400uL) +#define INTC_ICDABR1_DMAINT2 (0x00000800uL) +#define INTC_ICDABR1_DMAINT3 (0x00001000uL) +#define INTC_ICDABR1_DMAINT4 (0x00002000uL) +#define INTC_ICDABR1_DMAINT5 (0x00004000uL) +#define INTC_ICDABR1_DMAINT6 (0x00008000uL) +#define INTC_ICDABR1_DMAINT7 (0x00010000uL) +#define INTC_ICDABR1_DMAINT8 (0x00020000uL) +#define INTC_ICDABR1_DMAINT9 (0x00040000uL) +#define INTC_ICDABR1_DMAINT10 (0x00080000uL) +#define INTC_ICDABR1_DMAINT11 (0x00100000uL) +#define INTC_ICDABR1_DMAINT12 (0x00200000uL) +#define INTC_ICDABR1_DMAINT13 (0x00400000uL) +#define INTC_ICDABR1_DMAINT14 (0x00800000uL) +#define INTC_ICDABR1_DMAINT15 (0x01000000uL) +#define INTC_ICDABR1_DMAERR (0x02000000uL) + +#define INTC_ICDABR2_USBI0 (0x00000200uL) +#define INTC_ICDABR2_USBI1 (0x00000400uL) +#define INTC_ICDABR2_S0_VI_VSYNC0 (0x00000800uL) +#define INTC_ICDABR2_S0_LO_VSYNC0 (0x00001000uL) +#define INTC_ICDABR2_S0_VSYNCERR0 (0x00002000uL) +#define INTC_ICDABR2_GR3_VLINE0 (0x00004000uL) +#define INTC_ICDABR2_S0_VFIELD0 (0x00008000uL) +#define INTC_ICDABR2_IV1_VBUFERR0 (0x00010000uL) +#define INTC_ICDABR2_IV3_VBUFERR0 (0x00020000uL) +#define INTC_ICDABR2_IV5_VBUFERR0 (0x00040000uL) +#define INTC_ICDABR2_IV6_VBUFERR0 (0x00080000uL) +#define INTC_ICDABR2_S0_WLINE0 (0x00100000uL) +#define INTC_ICDABR2_S1_VI_VSYNC0 (0x00200000uL) +#define INTC_ICDABR2_S1_LO_VSYNC0 (0x00400000uL) +#define INTC_ICDABR2_S1_VSYNCERR0 (0x00800000uL) +#define INTC_ICDABR2_S1_VFIELD0 (0x01000000uL) +#define INTC_ICDABR2_IV2_VBUFERR0 (0x02000000uL) +#define INTC_ICDABR2_IV4_VBUFERR0 (0x04000000uL) +#define INTC_ICDABR2_S1_WLINE0 (0x08000000uL) +#define INTC_ICDABR2_OIR_VI_VSYNC0 (0x10000000uL) +#define INTC_ICDABR2_OIR_LO_VSYNC0 (0x20000000uL) +#define INTC_ICDABR2_OIR_VSYNCERR0 (0x40000000uL) +#define INTC_ICDABR2_OIR_VFIELD0 (0x80000000uL) + +#define INTC_ICDABR3_IV7_VBUFERR0 (0x00000001uL) +#define INTC_ICDABR3_IV8_VBUFERR0 (0x00000002uL) +#define INTC_ICDABR3_S0_VI_VSYNC1 (0x00000008uL) +#define INTC_ICDABR3_S0_LO_VSYNC1 (0x00000010uL) +#define INTC_ICDABR3_S0_VSYNCERR1 (0x00000020uL) +#define INTC_ICDABR3_GR3_VLINE1 (0x00000040uL) +#define INTC_ICDABR3_S0_VFIELD1 (0x00000080uL) +#define INTC_ICDABR3_IV1_VBUFERR1 (0x00000100uL) +#define INTC_ICDABR3_IV3_VBUFERR1 (0x00000200uL) +#define INTC_ICDABR3_IV5_VBUFERR1 (0x00000400uL) +#define INTC_ICDABR3_IV6_VBUFERR1 (0x00000800uL) +#define INTC_ICDABR3_S0_WLINE1 (0x00001000uL) +#define INTC_ICDABR3_S1_VI_VSYNC1 (0x00002000uL) +#define INTC_ICDABR3_S1_LO_VSYNC1 (0x00004000uL) +#define INTC_ICDABR3_S1_VSYNCERR1 (0x00008000uL) +#define INTC_ICDABR3_S1_VFIELD1 (0x00010000uL) +#define INTC_ICDABR3_IV2_VBUFERR1 (0x00020000uL) +#define INTC_ICDABR3_IV4_VBUFERR1 (0x00040000uL) +#define INTC_ICDABR3_S1_WLINE1 (0x00080000uL) +#define INTC_ICDABR3_OIR_VI_VSYNC1 (0x00100000uL) +#define INTC_ICDABR3_OIR_LO_VSYNC1 (0x00200000uL) +#define INTC_ICDABR3_OIR_VLINE1 (0x00400000uL) +#define INTC_ICDABR3_OIR_VFIELD1 (0x00800000uL) +#define INTC_ICDABR3_IV7_VBUFERR1 (0x01000000uL) +#define INTC_ICDABR3_IV8_VBUFERR1 (0x02000000uL) +#define INTC_ICDABR3_IMRDI (0x08000000uL) +#define INTC_ICDABR3_IMR2I0 (0x10000000uL) +#define INTC_ICDABR3_IMR2I1 (0x20000000uL) +#define INTC_ICDABR3_JEDI (0x40000000uL) +#define INTC_ICDABR3_JDTI (0x80000000uL) + +#define INTC_ICDABR4_CMP0 (0x00000001uL) +#define INTC_ICDABR4_CMP1 (0x00000002uL) +#define INTC_ICDABR4_INT0 (0x00000004uL) +#define INTC_ICDABR4_INT1 (0x00000008uL) +#define INTC_ICDABR4_INT2 (0x00000010uL) +#define INTC_ICDABR4_INT3 (0x00000020uL) +#define INTC_ICDABR4_OSTM0TINT (0x00000040uL) +#define INTC_ICDABR4_OSTM1TINT (0x00000080uL) +#define INTC_ICDABR4_CMI (0x00000100uL) +#define INTC_ICDABR4_WTOUT (0x00000200uL) +#define INTC_ICDABR4_ITI (0x00000400uL) +#define INTC_ICDABR4_TGI0A (0x00000800uL) +#define INTC_ICDABR4_TGI0B (0x00001000uL) +#define INTC_ICDABR4_TGI0C (0x00002000uL) +#define INTC_ICDABR4_TGI0D (0x00004000uL) +#define INTC_ICDABR4_TGI0V (0x00008000uL) +#define INTC_ICDABR4_TGI0E (0x00010000uL) +#define INTC_ICDABR4_TGI0F (0x00020000uL) +#define INTC_ICDABR4_TGI1A (0x00040000uL) +#define INTC_ICDABR4_TGI1B (0x00080000uL) +#define INTC_ICDABR4_TGI1V (0x00100000uL) +#define INTC_ICDABR4_TGI1U (0x00200000uL) +#define INTC_ICDABR4_TGI2A (0x00400000uL) +#define INTC_ICDABR4_TGI2B (0x00800000uL) +#define INTC_ICDABR4_TGI2V (0x01000000uL) +#define INTC_ICDABR4_TGI2U (0x02000000uL) +#define INTC_ICDABR4_TGI3A (0x04000000uL) +#define INTC_ICDABR4_TGI3B (0x08000000uL) +#define INTC_ICDABR4_TGI3C (0x10000000uL) +#define INTC_ICDABR4_TGI3D (0x20000000uL) +#define INTC_ICDABR4_TGI3V (0x40000000uL) +#define INTC_ICDABR4_TGI4A (0x80000000uL) + +#define INTC_ICDABR5_TGI4B (0x00000001uL) +#define INTC_ICDABR5_TGI4C (0x00000002uL) +#define INTC_ICDABR5_TGI4D (0x00000004uL) +#define INTC_ICDABR5_TGI4V (0x00000008uL) +#define INTC_ICDABR5_CMI1 (0x00000010uL) +#define INTC_ICDABR5_CMI2 (0x00000020uL) +#define INTC_ICDABR5_SGDEI0 (0x00000040uL) +#define INTC_ICDABR5_SGDEI1 (0x00000080uL) +#define INTC_ICDABR5_SGDEI2 (0x00000100uL) +#define INTC_ICDABR5_SGDEI3 (0x00000200uL) +#define INTC_ICDABR5_ADI (0x00000400uL) +#define INTC_ICDABR5_LMTI (0x00000800uL) +#define INTC_ICDABR5_SSII0 (0x00001000uL) +#define INTC_ICDABR5_SSIRXI0 (0x00002000uL) +#define INTC_ICDABR5_SSITXI0 (0x00004000uL) +#define INTC_ICDABR5_SSII1 (0x00008000uL) +#define INTC_ICDABR5_SSIRXI1 (0x00010000uL) +#define INTC_ICDABR5_SSITXI1 (0x00020000uL) +#define INTC_ICDABR5_SSII2 (0x00040000uL) +#define INTC_ICDABR5_SSIRTI2 (0x00080000uL) +#define INTC_ICDABR5_SSII3 (0x00100000uL) +#define INTC_ICDABR5_SSIRXI3 (0x00200000uL) +#define INTC_ICDABR5_SSITXI3 (0x00400000uL) +#define INTC_ICDABR5_SSII4 (0x00800000uL) +#define INTC_ICDABR5_SSIRTI4 (0x01000000uL) +#define INTC_ICDABR5_SSII5 (0x02000000uL) +#define INTC_ICDABR5_SSIRXI5 (0x04000000uL) +#define INTC_ICDABR5_SSITXI5 (0x08000000uL) +#define INTC_ICDABR5_SPDIFI (0x10000000uL) +#define INTC_ICDABR5_INTIICTEI0 (0x20000000uL) +#define INTC_ICDABR5_INTIICRI0 (0x40000000uL) +#define INTC_ICDABR5_INTIICTI0 (0x80000000uL) + +#define INTC_ICDABR6_INTIICSPI0 (0x00000001uL) +#define INTC_ICDABR6_INTIICSTI0 (0x00000002uL) +#define INTC_ICDABR6_INTIICNAKI0 (0x00000004uL) +#define INTC_ICDABR6_INTIICALI0 (0x00000008uL) +#define INTC_ICDABR6_INTIICTMOI0 (0x00000010uL) +#define INTC_ICDABR6_INTIICTEI1 (0x00000020uL) +#define INTC_ICDABR6_INTIICRI1 (0x00000040uL) +#define INTC_ICDABR6_INTIICTI1 (0x00000080uL) +#define INTC_ICDABR6_INTIICSPI1 (0x00000100uL) +#define INTC_ICDABR6_INTIICSTI1 (0x00000200uL) +#define INTC_ICDABR6_INTIICNAKI1 (0x00000400uL) +#define INTC_ICDABR6_INTIICALI1 (0x00000800uL) +#define INTC_ICDABR6_INTIICTMOI1 (0x00001000uL) +#define INTC_ICDABR6_INTIICTEI2 (0x00002000uL) +#define INTC_ICDABR6_INTIICRI2 (0x00004000uL) +#define INTC_ICDABR6_INTIICTI2 (0x00008000uL) +#define INTC_ICDABR6_INTIICSPI2 (0x00010000uL) +#define INTC_ICDABR6_INTIICSTI2 (0x00020000uL) +#define INTC_ICDABR6_INTIICNAKI2 (0x00040000uL) +#define INTC_ICDABR6_INTIICALI2 (0x00080000uL) +#define INTC_ICDABR6_INTIICTMOI2 (0x00100000uL) +#define INTC_ICDABR6_INTIICTEI3 (0x00200000uL) +#define INTC_ICDABR6_INTIICRI3 (0x00400000uL) +#define INTC_ICDABR6_INTIICTI3 (0x00800000uL) +#define INTC_ICDABR6_INTIICSPI3 (0x01000000uL) +#define INTC_ICDABR6_INTIICSTI3 (0x02000000uL) +#define INTC_ICDABR6_INTIICNAKI3 (0x04000000uL) +#define INTC_ICDABR6_INTIICALI3 (0x08000000uL) +#define INTC_ICDABR6_INTIICTMOI3 (0x10000000uL) +#define INTC_ICDABR6_BRI0 (0x20000000uL) +#define INTC_ICDABR6_ERI0 (0x40000000uL) +#define INTC_ICDABR6_RXI0 (0x80000000uL) + +#define INTC_ICDABR7_TXI0 (0x00000001uL) +#define INTC_ICDABR7_BRI1 (0x00000002uL) +#define INTC_ICDABR7_ERI1 (0x00000004uL) +#define INTC_ICDABR7_RXI1 (0x00000008uL) +#define INTC_ICDABR7_TXI1 (0x00000010uL) +#define INTC_ICDABR7_BRI2 (0x00000020uL) +#define INTC_ICDABR7_ERI2 (0x00000040uL) +#define INTC_ICDABR7_RXI2 (0x00000080uL) +#define INTC_ICDABR7_TXI2 (0x00000100uL) +#define INTC_ICDABR7_BRI3 (0x00000200uL) +#define INTC_ICDABR7_ERI3 (0x00000400uL) +#define INTC_ICDABR7_RXI3 (0x00000800uL) +#define INTC_ICDABR7_TXI3 (0x00001000uL) +#define INTC_ICDABR7_BRI4 (0x00002000uL) +#define INTC_ICDABR7_ERI4 (0x00004000uL) +#define INTC_ICDABR7_RXI4 (0x00008000uL) +#define INTC_ICDABR7_TXI4 (0x00010000uL) +#define INTC_ICDABR7_BRI5 (0x00020000uL) +#define INTC_ICDABR7_ERI5 (0x00040000uL) +#define INTC_ICDABR7_RXI5 (0x00080000uL) +#define INTC_ICDABR7_TXI5 (0x00100000uL) +#define INTC_ICDABR7_BRI6 (0x00200000uL) +#define INTC_ICDABR7_ERI6 (0x00400000uL) +#define INTC_ICDABR7_RXI6 (0x00800000uL) +#define INTC_ICDABR7_TXI6 (0x01000000uL) +#define INTC_ICDABR7_BRI7 (0x02000000uL) +#define INTC_ICDABR7_ERI7 (0x04000000uL) +#define INTC_ICDABR7_RXI7 (0x08000000uL) +#define INTC_ICDABR7_TXI7 (0x10000000uL) +#define INTC_ICDABR7_INTRCANGERR (0x20000000uL) +#define INTC_ICDABR7_INTRCANGRECC (0x40000000uL) +#define INTC_ICDABR7_INTRCAN0REC (0x80000000uL) + +#define INTC_ICDABR8_INTRCAN0ERR (0x00000001uL) +#define INTC_ICDABR8_INTRCAN0TRX (0x00000002uL) +#define INTC_ICDABR8_INTRCAN1REC (0x00000004uL) +#define INTC_ICDABR8_INTRCAN1ERR (0x00000008uL) +#define INTC_ICDABR8_INTRCAN1TRX (0x00000010uL) +#define INTC_ICDABR8_INTRCAN2REC (0x00000020uL) +#define INTC_ICDABR8_INTRCAN2ERR (0x00000040uL) +#define INTC_ICDABR8_INTRCAN2TRX (0x00000080uL) +#define INTC_ICDABR8_INTRCAN3REC (0x00000100uL) +#define INTC_ICDABR8_INTRCAN3ERR (0x00000200uL) +#define INTC_ICDABR8_INTRCAN3TRX (0x00000400uL) +#define INTC_ICDABR8_INTRCAN4REC (0x00000800uL) +#define INTC_ICDABR8_INTRCAN4ERR (0x00001000uL) +#define INTC_ICDABR8_INTRCAN4TRX (0x00002000uL) +#define INTC_ICDABR8_SPEI0 (0x00004000uL) +#define INTC_ICDABR8_SPRI0 (0x00008000uL) +#define INTC_ICDABR8_SPTI0 (0x00010000uL) +#define INTC_ICDABR8_SPEI1 (0x00020000uL) +#define INTC_ICDABR8_SPRI1 (0x00040000uL) +#define INTC_ICDABR8_SPTI1 (0x00080000uL) +#define INTC_ICDABR8_SPEI2 (0x00100000uL) +#define INTC_ICDABR8_SPRI2 (0x00200000uL) +#define INTC_ICDABR8_SPTI2 (0x00400000uL) +#define INTC_ICDABR8_SPEI3 (0x00800000uL) +#define INTC_ICDABR8_SPRI3 (0x01000000uL) +#define INTC_ICDABR8_SPTI3 (0x02000000uL) +#define INTC_ICDABR8_SPEI4 (0x04000000uL) +#define INTC_ICDABR8_SPRI4 (0x08000000uL) +#define INTC_ICDABR8_SPTI4 (0x10000000uL) +#define INTC_ICDABR8_IEBBTD (0x20000000uL) +#define INTC_ICDABR8_IEBBTERR (0x40000000uL) +#define INTC_ICDABR8_IEBBTSTA (0x80000000uL) + +#define INTC_ICDABR9_IEBBTV (0x00000001uL) +#define INTC_ICDABR9_ISY (0x00000002uL) +#define INTC_ICDABR9_IERR (0x00000004uL) +#define INTC_ICDABR9_ITARG (0x00000008uL) +#define INTC_ICDABR9_ISEC (0x00000010uL) +#define INTC_ICDABR9_IBUF (0x00000020uL) +#define INTC_ICDABR9_IREADY (0x00000040uL) +#define INTC_ICDABR9_FLSTE (0x00000080uL) +#define INTC_ICDABR9_FLTENDI (0x00000100uL) +#define INTC_ICDABR9_FLTREQ0I (0x00000200uL) +#define INTC_ICDABR9_FLTREQ1I (0x00000400uL) +#define INTC_ICDABR9_MMC0 (0x00000800uL) +#define INTC_ICDABR9_MMC1 (0x00001000uL) +#define INTC_ICDABR9_MMC2 (0x00002000uL) +#define INTC_ICDABR9_SDHI0_3 (0x00004000uL) +#define INTC_ICDABR9_SDHI0_0 (0x00008000uL) +#define INTC_ICDABR9_SDHI0_1 (0x00010000uL) +#define INTC_ICDABR9_SDHI1_3 (0x00020000uL) +#define INTC_ICDABR9_SDHI1_0 (0x00040000uL) +#define INTC_ICDABR9_SDHI1_1 (0x00080000uL) +#define INTC_ICDABR9_ARM (0x00100000uL) +#define INTC_ICDABR9_PRD (0x00200000uL) +#define INTC_ICDABR9_CUP (0x00400000uL) +#define INTC_ICDABR9_SCUAI0 (0x00800000uL) +#define INTC_ICDABR9_SCUAI1 (0x01000000uL) +#define INTC_ICDABR9_SCUFDI0 (0x02000000uL) +#define INTC_ICDABR9_SCUFDI1 (0x04000000uL) +#define INTC_ICDABR9_SCUFDI2 (0x08000000uL) +#define INTC_ICDABR9_SCUFDI3 (0x10000000uL) +#define INTC_ICDABR9_SCUFUI0 (0x20000000uL) +#define INTC_ICDABR9_SCUFUI1 (0x40000000uL) +#define INTC_ICDABR9_SCUFUI2 (0x80000000uL) + +#define INTC_ICDABR10_SCUFUI3 (0x00000001uL) +#define INTC_ICDABR10_SCUDVI0 (0x00000002uL) +#define INTC_ICDABR10_SCUDVI1 (0x00000004uL) +#define INTC_ICDABR10_SCUDVI2 (0x00000008uL) +#define INTC_ICDABR10_SCUDVI3 (0x00000010uL) +#define INTC_ICDABR10_MLB_CINT (0x00000020uL) +#define INTC_ICDABR10_MLB_SINT (0x00000040uL) +#define INTC_ICDABR10_DRC0 (0x00000080uL) +#define INTC_ICDABR10_DRC1 (0x00000100uL) +#define INTC_ICDABR10_LINI0_INT_T (0x00000800uL) +#define INTC_ICDABR10_LINI0_INT_R (0x00001000uL) +#define INTC_ICDABR10_LINI0_INT_S (0x00002000uL) +#define INTC_ICDABR10_LINI0_INT_M (0x00004000uL) +#define INTC_ICDABR10_LINI1_INT_T (0x00008000uL) +#define INTC_ICDABR10_LINI1_INT_R (0x00010000uL) +#define INTC_ICDABR10_LINI1_INT_S (0x00020000uL) +#define INTC_ICDABR10_LINI1_INT_M (0x00040000uL) +#define INTC_ICDABR10_ERI0 (0x08000000uL) +#define INTC_ICDABR10_RXI0 (0x10000000uL) +#define INTC_ICDABR10_TXI0 (0x20000000uL) +#define INTC_ICDABR10_TEI0 (0x40000000uL) +#define INTC_ICDABR10_ERI1 (0x80000000uL) + +#define INTC_ICDABR11_RXI1 (0x00000001uL) +#define INTC_ICDABR11_TXI1 (0x00000002uL) +#define INTC_ICDABR11_TEI1 (0x00000004uL) +#define INTC_ICDABR11_AVBI_DATA (0x00000008uL) +#define INTC_ICDABR11_AVBI_ERROR (0x00000010uL) +#define INTC_ICDABR11_AVBI_MANAGE (0x00000020uL) +#define INTC_ICDABR11_AVBI_MAC (0x00000040uL) +#define INTC_ICDABR11_ETHERI (0x00000080uL) +#define INTC_ICDABR11_CEUI (0x00001000uL) +#define INTC_ICDABR11_H2XMLB_ERRINT (0x20000000uL) +#define INTC_ICDABR11_H2XIC1_ERRINT (0x40000000uL) +#define INTC_ICDABR11_X2HPERI1_ERRINT (0x80000000uL) + +#define INTC_ICDABR12_X2HPERI2_ERRINT (0x00000001uL) +#define INTC_ICDABR12_X2HPERI34_ERRINT (0x00000002uL) +#define INTC_ICDABR12_X2HPERI5_ERRINT (0x00000004uL) +#define INTC_ICDABR12_X2HPERI67_ERRINT (0x00000008uL) +#define INTC_ICDABR12_X2HDBGR_ERRINT (0x00000010uL) +#define INTC_ICDABR12_X2HBSC_ERRINT (0x00000020uL) +#define INTC_ICDABR12_X2HSPI1_ERRINT (0x00000040uL) +#define INTC_ICDABR12_X2HSPI2_ERRINT (0x00000080uL) +#define INTC_ICDABR12_PRRI (0x00000100uL) +#define INTC_ICDABR12_IFEI0 (0x00000200uL) +#define INTC_ICDABR12_OFFI0 (0x00000400uL) +#define INTC_ICDABR12_PFVEI0 (0x00000800uL) +#define INTC_ICDABR12_IFEI1 (0x00001000uL) +#define INTC_ICDABR12_OFFI1 (0x00002000uL) +#define INTC_ICDABR12_PFVEI1 (0x00004000uL) + +#define INTC_ICDABR13_TINT0 (0x00000001uL) +#define INTC_ICDABR13_TINT1 (0x00000002uL) +#define INTC_ICDABR13_TINT2 (0x00000004uL) +#define INTC_ICDABR13_TINT3 (0x00000008uL) +#define INTC_ICDABR13_TINT4 (0x00000010uL) +#define INTC_ICDABR13_TINT5 (0x00000020uL) +#define INTC_ICDABR13_TINT6 (0x00000040uL) +#define INTC_ICDABR13_TINT7 (0x00000080uL) +#define INTC_ICDABR13_TINT8 (0x00000100uL) +#define INTC_ICDABR13_TINT9 (0x00000200uL) +#define INTC_ICDABR13_TINT10 (0x00000400uL) +#define INTC_ICDABR13_TINT11 (0x00000800uL) +#define INTC_ICDABR13_TINT12 (0x00001000uL) +#define INTC_ICDABR13_TINT13 (0x00002000uL) +#define INTC_ICDABR13_TINT14 (0x00004000uL) +#define INTC_ICDABR13_TINT15 (0x00008000uL) +#define INTC_ICDABR13_TINT16 (0x00010000uL) +#define INTC_ICDABR13_TINT17 (0x00020000uL) +#define INTC_ICDABR13_TINT18 (0x00040000uL) +#define INTC_ICDABR13_TINT19 (0x00080000uL) +#define INTC_ICDABR13_TINT20 (0x00100000uL) +#define INTC_ICDABR13_TINT21 (0x00200000uL) +#define INTC_ICDABR13_TINT22 (0x00400000uL) +#define INTC_ICDABR13_TINT23 (0x00800000uL) +#define INTC_ICDABR13_TINT24 (0x01000000uL) +#define INTC_ICDABR13_TINT25 (0x02000000uL) +#define INTC_ICDABR13_TINT26 (0x04000000uL) +#define INTC_ICDABR13_TINT27 (0x08000000uL) +#define INTC_ICDABR13_TINT28 (0x10000000uL) +#define INTC_ICDABR13_TINT29 (0x20000000uL) +#define INTC_ICDABR13_TINT30 (0x40000000uL) +#define INTC_ICDABR13_TINT31 (0x80000000uL) + +#define INTC_ICDABR14_TINT32 (0x00000001uL) +#define INTC_ICDABR14_TINT33 (0x00000002uL) +#define INTC_ICDABR14_TINT34 (0x00000004uL) +#define INTC_ICDABR14_TINT35 (0x00000008uL) +#define INTC_ICDABR14_TINT36 (0x00000010uL) +#define INTC_ICDABR14_TINT37 (0x00000020uL) +#define INTC_ICDABR14_TINT38 (0x00000040uL) +#define INTC_ICDABR14_TINT39 (0x00000080uL) +#define INTC_ICDABR14_TINT40 (0x00000100uL) +#define INTC_ICDABR14_TINT41 (0x00000200uL) +#define INTC_ICDABR14_TINT42 (0x00000400uL) +#define INTC_ICDABR14_TINT43 (0x00000800uL) +#define INTC_ICDABR14_TINT44 (0x00001000uL) +#define INTC_ICDABR14_TINT45 (0x00002000uL) +#define INTC_ICDABR14_TINT46 (0x00004000uL) +#define INTC_ICDABR14_TINT47 (0x00008000uL) +#define INTC_ICDABR14_TINT48 (0x00010000uL) +#define INTC_ICDABR14_TINT49 (0x00020000uL) +#define INTC_ICDABR14_TINT50 (0x00040000uL) +#define INTC_ICDABR14_TINT51 (0x00080000uL) +#define INTC_ICDABR14_TINT52 (0x00100000uL) +#define INTC_ICDABR14_TINT53 (0x00200000uL) +#define INTC_ICDABR14_TINT54 (0x00400000uL) +#define INTC_ICDABR14_TINT55 (0x00800000uL) +#define INTC_ICDABR14_TINT56 (0x01000000uL) +#define INTC_ICDABR14_TINT57 (0x02000000uL) +#define INTC_ICDABR14_TINT58 (0x04000000uL) +#define INTC_ICDABR14_TINT59 (0x08000000uL) +#define INTC_ICDABR14_TINT60 (0x10000000uL) +#define INTC_ICDABR14_TINT61 (0x20000000uL) +#define INTC_ICDABR14_TINT62 (0x40000000uL) +#define INTC_ICDABR14_TINT63 (0x80000000uL) + +#define INTC_ICDABR15_TINT64 (0x00000001uL) +#define INTC_ICDABR15_TINT65 (0x00000002uL) +#define INTC_ICDABR15_TINT66 (0x00000004uL) +#define INTC_ICDABR15_TINT67 (0x00000008uL) +#define INTC_ICDABR15_TINT68 (0x00000010uL) +#define INTC_ICDABR15_TINT69 (0x00000020uL) +#define INTC_ICDABR15_TINT70 (0x00000040uL) +#define INTC_ICDABR15_TINT71 (0x00000080uL) +#define INTC_ICDABR15_TINT72 (0x00000100uL) +#define INTC_ICDABR15_TINT73 (0x00000200uL) +#define INTC_ICDABR15_TINT74 (0x00000400uL) +#define INTC_ICDABR15_TINT75 (0x00000800uL) +#define INTC_ICDABR15_TINT76 (0x00001000uL) +#define INTC_ICDABR15_TINT77 (0x00002000uL) +#define INTC_ICDABR15_TINT78 (0x00004000uL) +#define INTC_ICDABR15_TINT79 (0x00008000uL) +#define INTC_ICDABR15_TINT80 (0x00010000uL) +#define INTC_ICDABR15_TINT81 (0x00020000uL) +#define INTC_ICDABR15_TINT82 (0x00040000uL) +#define INTC_ICDABR15_TINT83 (0x00080000uL) +#define INTC_ICDABR15_TINT84 (0x00100000uL) +#define INTC_ICDABR15_TINT85 (0x00200000uL) +#define INTC_ICDABR15_TINT86 (0x00400000uL) +#define INTC_ICDABR15_TINT87 (0x00800000uL) +#define INTC_ICDABR15_TINT88 (0x01000000uL) +#define INTC_ICDABR15_TINT89 (0x02000000uL) +#define INTC_ICDABR15_TINT90 (0x04000000uL) +#define INTC_ICDABR15_TINT91 (0x08000000uL) +#define INTC_ICDABR15_TINT92 (0x10000000uL) +#define INTC_ICDABR15_TINT93 (0x20000000uL) +#define INTC_ICDABR15_TINT94 (0x40000000uL) +#define INTC_ICDABR15_TINT95 (0x80000000uL) + +#define INTC_ICDABR16_TINT96 (0x00000001uL) +#define INTC_ICDABR16_TINT97 (0x00000002uL) +#define INTC_ICDABR16_TINT98 (0x00000004uL) +#define INTC_ICDABR16_TINT99 (0x00000008uL) +#define INTC_ICDABR16_TINT100 (0x00000010uL) +#define INTC_ICDABR16_TINT101 (0x00000020uL) +#define INTC_ICDABR16_TINT102 (0x00000040uL) +#define INTC_ICDABR16_TINT103 (0x00000080uL) +#define INTC_ICDABR16_TINT104 (0x00000100uL) +#define INTC_ICDABR16_TINT105 (0x00000200uL) +#define INTC_ICDABR16_TINT106 (0x00000400uL) +#define INTC_ICDABR16_TINT107 (0x00000800uL) +#define INTC_ICDABR16_TINT108 (0x00001000uL) +#define INTC_ICDABR16_TINT109 (0x00002000uL) +#define INTC_ICDABR16_TINT110 (0x00004000uL) +#define INTC_ICDABR16_TINT111 (0x00008000uL) +#define INTC_ICDABR16_TINT112 (0x00010000uL) +#define INTC_ICDABR16_TINT113 (0x00020000uL) +#define INTC_ICDABR16_TINT114 (0x00040000uL) +#define INTC_ICDABR16_TINT115 (0x00080000uL) +#define INTC_ICDABR16_TINT116 (0x00100000uL) +#define INTC_ICDABR16_TINT117 (0x00200000uL) +#define INTC_ICDABR16_TINT118 (0x00400000uL) +#define INTC_ICDABR16_TINT119 (0x00800000uL) +#define INTC_ICDABR16_TINT120 (0x01000000uL) +#define INTC_ICDABR16_TINT121 (0x02000000uL) +#define INTC_ICDABR16_TINT122 (0x04000000uL) +#define INTC_ICDABR16_TINT123 (0x08000000uL) +#define INTC_ICDABR16_TINT124 (0x10000000uL) +#define INTC_ICDABR16_TINT125 (0x20000000uL) +#define INTC_ICDABR16_TINT126 (0x40000000uL) +#define INTC_ICDABR16_TINT127 (0x80000000uL) + +#define INTC_ICDABR17_TINT128 (0x00000001uL) +#define INTC_ICDABR17_TINT129 (0x00000002uL) +#define INTC_ICDABR17_TINT130 (0x00000004uL) +#define INTC_ICDABR17_TINT131 (0x00000008uL) +#define INTC_ICDABR17_TINT132 (0x00000010uL) +#define INTC_ICDABR17_TINT133 (0x00000020uL) +#define INTC_ICDABR17_TINT134 (0x00000040uL) +#define INTC_ICDABR17_TINT135 (0x00000080uL) +#define INTC_ICDABR17_TINT136 (0x00000100uL) +#define INTC_ICDABR17_TINT137 (0x00000200uL) +#define INTC_ICDABR17_TINT138 (0x00000400uL) +#define INTC_ICDABR17_TINT139 (0x00000800uL) +#define INTC_ICDABR17_TINT140 (0x00001000uL) +#define INTC_ICDABR17_TINT141 (0x00002000uL) +#define INTC_ICDABR17_TINT142 (0x00004000uL) +#define INTC_ICDABR17_TINT143 (0x00008000uL) +#define INTC_ICDABR17_TINT144 (0x00010000uL) +#define INTC_ICDABR17_TINT145 (0x00020000uL) +#define INTC_ICDABR17_TINT146 (0x00040000uL) +#define INTC_ICDABR17_TINT147 (0x00080000uL) +#define INTC_ICDABR17_TINT148 (0x00100000uL) +#define INTC_ICDABR17_TINT149 (0x00200000uL) +#define INTC_ICDABR17_TINT150 (0x00400000uL) +#define INTC_ICDABR17_TINT151 (0x00800000uL) +#define INTC_ICDABR17_TINT152 (0x01000000uL) +#define INTC_ICDABR17_TINT153 (0x02000000uL) +#define INTC_ICDABR17_TINT154 (0x04000000uL) +#define INTC_ICDABR17_TINT155 (0x08000000uL) +#define INTC_ICDABR17_TINT156 (0x10000000uL) +#define INTC_ICDABR17_TINT157 (0x20000000uL) +#define INTC_ICDABR17_TINT158 (0x40000000uL) +#define INTC_ICDABR17_TINT159 (0x80000000uL) + +#define INTC_ICDABR18_TINT160 (0x00000001uL) +#define INTC_ICDABR18_TINT161 (0x00000002uL) +#define INTC_ICDABR18_TINT162 (0x00000004uL) +#define INTC_ICDABR18_TINT163 (0x00000008uL) +#define INTC_ICDABR18_TINT164 (0x00000010uL) +#define INTC_ICDABR18_TINT165 (0x00000020uL) +#define INTC_ICDABR18_TINT166 (0x00000040uL) +#define INTC_ICDABR18_TINT167 (0x00000080uL) +#define INTC_ICDABR18_TINT168 (0x00000100uL) +#define INTC_ICDABR18_TINT169 (0x00000200uL) +#define INTC_ICDABR18_TINT170 (0x00000400uL) + +#define INTC_ICDIPR0_SW0 (0x000000FFuL) +#define INTC_ICDIPR0_SW1 (0x0000FF00uL) +#define INTC_ICDIPR0_SW2 (0x00FF0000uL) +#define INTC_ICDIPR0_SW3 (0xFF000000uL) + +#define INTC_ICDIPR1_SW4 (0x000000FFuL) +#define INTC_ICDIPR1_SW5 (0x0000FF00uL) +#define INTC_ICDIPR1_SW6 (0x00FF0000uL) +#define INTC_ICDIPR1_SW7 (0xFF000000uL) + +#define INTC_ICDIPR2_SW8 (0x000000FFuL) +#define INTC_ICDIPR2_SW9 (0x0000FF00uL) +#define INTC_ICDIPR2_SW10 (0x00FF0000uL) +#define INTC_ICDIPR2_SW11 (0xFF000000uL) + +#define INTC_ICDIPR3_SW12 (0x000000FFuL) +#define INTC_ICDIPR3_SW13 (0x0000FF00uL) +#define INTC_ICDIPR3_SW14 (0x00FF0000uL) +#define INTC_ICDIPR3_SW15 (0xFF000000uL) + +#define INTC_ICDIPR4_PMUIRQ0 (0x000000FFuL) +#define INTC_ICDIPR4_COMMRX0 (0x0000FF00uL) +#define INTC_ICDIPR4_COMMTX0 (0x00FF0000uL) +#define INTC_ICDIPR4_CTIIRQ0 (0xFF000000uL) + +#define INTC_ICDIPR8_IRQ0 (0x000000FFuL) +#define INTC_ICDIPR8_IRQ1 (0x0000FF00uL) +#define INTC_ICDIPR8_IRQ2 (0x00FF0000uL) +#define INTC_ICDIPR8_IRQ3 (0xFF000000uL) + +#define INTC_ICDIPR9_IRQ4 (0x000000FFuL) +#define INTC_ICDIPR9_IRQ5 (0x0000FF00uL) +#define INTC_ICDIPR9_IRQ6 (0x00FF0000uL) +#define INTC_ICDIPR9_IRQ7 (0xFF000000uL) + +#define INTC_ICDIPR10_PL310ERR (0x000000FFuL) +#define INTC_ICDIPR10_DMAINT0 (0x0000FF00uL) +#define INTC_ICDIPR10_DMAINT1 (0x00FF0000uL) +#define INTC_ICDIPR10_DMAINT2 (0xFF000000uL) + +#define INTC_ICDIPR11_DMAINT3 (0x000000FFuL) +#define INTC_ICDIPR11_DMAINT4 (0x0000FF00uL) +#define INTC_ICDIPR11_DMAINT5 (0x00FF0000uL) +#define INTC_ICDIPR11_DMAINT6 (0xFF000000uL) + +#define INTC_ICDIPR12_DMAINT7 (0x000000FFuL) +#define INTC_ICDIPR12_DMAINT8 (0x0000FF00uL) +#define INTC_ICDIPR12_DMAINT9 (0x00FF0000uL) +#define INTC_ICDIPR12_DMAINT10 (0xFF000000uL) + +#define INTC_ICDIPR13_DMAINT11 (0x000000FFuL) +#define INTC_ICDIPR13_DMAINT12 (0x0000FF00uL) +#define INTC_ICDIPR13_DMAINT13 (0x00FF0000uL) +#define INTC_ICDIPR13_DMAINT14 (0xFF000000uL) + +#define INTC_ICDIPR14_DMAINT15 (0x000000FFuL) +#define INTC_ICDIPR14_DMAERR (0x0000FF00uL) + +#define INTC_ICDIPR18_USBI0 (0x0000FF00uL) +#define INTC_ICDIPR18_USBI1 (0x00FF0000uL) +#define INTC_ICDIPR18_S0_VI_VSYNC0 (0xFF000000uL) + +#define INTC_ICDIPR19_S0_LO_VSYNC0 (0x000000FFuL) +#define INTC_ICDIPR19_S0_VSYNCERR0 (0x0000FF00uL) +#define INTC_ICDIPR19_GR3_VLINE0 (0x00FF0000uL) +#define INTC_ICDIPR19_S0_VFIELD0 (0xFF000000uL) + +#define INTC_ICDIPR20_IV1_VBUFERR0 (0x000000FFuL) +#define INTC_ICDIPR20_IV3_VBUFERR0 (0x0000FF00uL) +#define INTC_ICDIPR20_IV5_VBUFERR0 (0x00FF0000uL) +#define INTC_ICDIPR20_IV6_VBUFERR0 (0xFF000000uL) + +#define INTC_ICDIPR21_S0_WLINE0 (0x000000FFuL) +#define INTC_ICDIPR21_S1_VI_VSYNC0 (0x0000FF00uL) +#define INTC_ICDIPR21_S1_LO_VSYNC0 (0x00FF0000uL) +#define INTC_ICDIPR21_S1_VSYNCERR0 (0xFF000000uL) + +#define INTC_ICDIPR22_S1_VFIELD0 (0x000000FFuL) +#define INTC_ICDIPR22_IV2_VBUFERR0 (0x0000FF00uL) +#define INTC_ICDIPR22_IV4_VBUFERR0 (0x00FF0000uL) +#define INTC_ICDIPR22_S1_WLINE0 (0xFF000000uL) + +#define INTC_ICDIPR23_OIR_VI_VSYNC0 (0x000000FFuL) +#define INTC_ICDIPR23_OIR_LO_VSYNC0 (0x0000FF00uL) +#define INTC_ICDIPR23_OIR_VSYNCERR0 (0x00FF0000uL) +#define INTC_ICDIPR23_OIR_VFIELD0 (0xFF000000uL) + +#define INTC_ICDIPR24_IV7_VBUFERR0 (0x000000FFuL) +#define INTC_ICDIPR24_IV8_VBUFERR0 (0x0000FF00uL) +#define INTC_ICDIPR24_S0_VI_VSYNC1 (0xFF000000uL) + +#define INTC_ICDIPR25_S0_LO_VSYNC1 (0x000000FFuL) +#define INTC_ICDIPR25_S0_VSYNCERR1 (0x0000FF00uL) +#define INTC_ICDIPR25_GR3_VLINE1 (0x00FF0000uL) +#define INTC_ICDIPR25_S0_VFIELD1 (0xFF000000uL) + +#define INTC_ICDIPR26_IV1_VBUFERR1 (0x000000FFuL) +#define INTC_ICDIPR26_IV3_VBUFERR1 (0x0000FF00uL) +#define INTC_ICDIPR26_IV5_VBUFERR1 (0x00FF0000uL) +#define INTC_ICDIPR26_IV6_VBUFERR1 (0xFF000000uL) + +#define INTC_ICDIPR27_S0_WLINE1 (0x000000FFuL) +#define INTC_ICDIPR27_S1_VI_VSYNC1 (0x0000FF00uL) +#define INTC_ICDIPR27_S1_LO_VSYNC1 (0x00FF0000uL) +#define INTC_ICDIPR27_S1_VSYNCERR1 (0xFF000000uL) + +#define INTC_ICDIPR28_S1_VFIELD1 (0x000000FFuL) +#define INTC_ICDIPR28_IV2_VBUFERR1 (0x0000FF00uL) +#define INTC_ICDIPR28_IV4_VBUFERR1 (0x00FF0000uL) +#define INTC_ICDIPR28_S1_WLINE1 (0xFF000000uL) + +#define INTC_ICDIPR29_OIR_VI_VSYNC1 (0x000000FFuL) +#define INTC_ICDIPR29_OIR_LO_VSYNC1 (0x0000FF00uL) +#define INTC_ICDIPR29_OIR_VLINE1 (0x00FF0000uL) +#define INTC_ICDIPR29_OIR_VFIELD1 (0xFF000000uL) + +#define INTC_ICDIPR30_IV7_VBUFERR1 (0x000000FFuL) +#define INTC_ICDIPR30_IV8_VBUFERR1 (0x0000FF00uL) +#define INTC_ICDIPR30_IMRDI (0xFF000000uL) + +#define INTC_ICDIPR31_IMR2I0 (0x000000FFuL) +#define INTC_ICDIPR31_IMR2I1 (0x0000FF00uL) +#define INTC_ICDIPR31_JEDI (0x00FF0000uL) +#define INTC_ICDIPR31_JDTI (0xFF000000uL) + +#define INTC_ICDIPR32_CMP0 (0x000000FFuL) +#define INTC_ICDIPR32_CMP1 (0x0000FF00uL) +#define INTC_ICDIPR32_INT0 (0x00FF0000uL) +#define INTC_ICDIPR32_INT1 (0xFF000000uL) + +#define INTC_ICDIPR33_INT2 (0x000000FFuL) +#define INTC_ICDIPR33_INT3 (0x0000FF00uL) +#define INTC_ICDIPR33_OSTM0TINT (0x00FF0000uL) +#define INTC_ICDIPR33_OSTM1TINT (0xFF000000uL) + +#define INTC_ICDIPR34_CMI (0x000000FFuL) +#define INTC_ICDIPR34_WTOUT (0x0000FF00uL) +#define INTC_ICDIPR34_ITI (0x00FF0000uL) +#define INTC_ICDIPR34_TGI0A (0xFF000000uL) + +#define INTC_ICDIPR35_TGI0B (0x000000FFuL) +#define INTC_ICDIPR35_TGI0C (0x0000FF00uL) +#define INTC_ICDIPR35_TGI0D (0x00FF0000uL) +#define INTC_ICDIPR35_TGI0V (0xFF000000uL) + +#define INTC_ICDIPR36_TGI0E (0x000000FFuL) +#define INTC_ICDIPR36_TGI0F (0x0000FF00uL) +#define INTC_ICDIPR36_TGI1A (0x00FF0000uL) +#define INTC_ICDIPR36_TGI1B (0xFF000000uL) + +#define INTC_ICDIPR37_TGI1V (0x000000FFuL) +#define INTC_ICDIPR37_TGI1U (0x0000FF00uL) +#define INTC_ICDIPR37_TGI2A (0x00FF0000uL) +#define INTC_ICDIPR37_TGI2B (0xFF000000uL) + +#define INTC_ICDIPR38_TGI2V (0x000000FFuL) +#define INTC_ICDIPR38_TGI2U (0x0000FF00uL) +#define INTC_ICDIPR38_TGI3A (0x00FF0000uL) +#define INTC_ICDIPR38_TGI3B (0xFF000000uL) + +#define INTC_ICDIPR39_TGI3C (0x000000FFuL) +#define INTC_ICDIPR39_TGI3D (0x0000FF00uL) +#define INTC_ICDIPR39_TGI3V (0x00FF0000uL) +#define INTC_ICDIPR39_TGI4A (0xFF000000uL) + +#define INTC_ICDIPR40_TGI4B (0x000000FFuL) +#define INTC_ICDIPR40_TGI4C (0x0000FF00uL) +#define INTC_ICDIPR40_TGI4D (0x00FF0000uL) +#define INTC_ICDIPR40_TGI4V (0xFF000000uL) + +#define INTC_ICDIPR41_CMI1 (0x000000FFuL) +#define INTC_ICDIPR41_CMI2 (0x0000FF00uL) +#define INTC_ICDIPR41_SGDEI0 (0x00FF0000uL) +#define INTC_ICDIPR41_SGDEI1 (0xFF000000uL) + +#define INTC_ICDIPR42_SGDEI2 (0x000000FFuL) +#define INTC_ICDIPR42_SGDEI3 (0x0000FF00uL) +#define INTC_ICDIPR42_ADI (0x00FF0000uL) +#define INTC_ICDIPR42_LMTI (0xFF000000uL) + +#define INTC_ICDIPR43_SSII0 (0x000000FFuL) +#define INTC_ICDIPR43_SSIRXI0 (0x0000FF00uL) +#define INTC_ICDIPR43_SSITXI0 (0x00FF0000uL) +#define INTC_ICDIPR43_SSII1 (0xFF000000uL) + +#define INTC_ICDIPR44_SSIRXI1 (0x000000FFuL) +#define INTC_ICDIPR44_SSITXI1 (0x0000FF00uL) +#define INTC_ICDIPR44_SSII2 (0x00FF0000uL) +#define INTC_ICDIPR44_SSIRTI2 (0xFF000000uL) + +#define INTC_ICDIPR45_SSII3 (0x000000FFuL) +#define INTC_ICDIPR45_SSIRXI3 (0x0000FF00uL) +#define INTC_ICDIPR45_SSITXI3 (0x00FF0000uL) +#define INTC_ICDIPR45_SSII4 (0xFF000000uL) + +#define INTC_ICDIPR46_SSIRTI4 (0x000000FFuL) +#define INTC_ICDIPR46_SSII5 (0x0000FF00uL) +#define INTC_ICDIPR46_SSIRXI5 (0x00FF0000uL) +#define INTC_ICDIPR46_SSITXI5 (0xFF000000uL) + +#define INTC_ICDIPR47_SPDIFI (0x000000FFuL) +#define INTC_ICDIPR47_INTIICTEI0 (0x0000FF00uL) +#define INTC_ICDIPR47_INTIICRI0 (0x00FF0000uL) +#define INTC_ICDIPR47_INTIICTI0 (0xFF000000uL) + +#define INTC_ICDIPR48_INTIICSPI0 (0x000000FFuL) +#define INTC_ICDIPR48_INTIICSTI0 (0x0000FF00uL) +#define INTC_ICDIPR48_INTIICNAKI0 (0x00FF0000uL) +#define INTC_ICDIPR48_INTIICALI0 (0xFF000000uL) + +#define INTC_ICDIPR49_INTIICTMOI0 (0x000000FFuL) +#define INTC_ICDIPR49_INTIICTEI1 (0x0000FF00uL) +#define INTC_ICDIPR49_INTIICRI1 (0x00FF0000uL) +#define INTC_ICDIPR49_INTIICTI1 (0xFF000000uL) + +#define INTC_ICDIPR50_INTIICSPI1 (0x000000FFuL) +#define INTC_ICDIPR50_INTIICSTI1 (0x0000FF00uL) +#define INTC_ICDIPR50_INTIICNAKI1 (0x00FF0000uL) +#define INTC_ICDIPR50_INTIICALI1 (0xFF000000uL) + +#define INTC_ICDIPR51_INTIICTMOI1 (0x000000FFuL) +#define INTC_ICDIPR51_INTIICTEI2 (0x0000FF00uL) +#define INTC_ICDIPR51_INTIICRI2 (0x00FF0000uL) +#define INTC_ICDIPR51_INTIICTI2 (0xFF000000uL) + +#define INTC_ICDIPR52_INTIICSPI2 (0x000000FFuL) +#define INTC_ICDIPR52_INTIICSTI2 (0x0000FF00uL) +#define INTC_ICDIPR52_INTIICNAKI2 (0x00FF0000uL) +#define INTC_ICDIPR52_INTIICALI2 (0xFF000000uL) + +#define INTC_ICDIPR53_INTIICTMOI2 (0x000000FFuL) +#define INTC_ICDIPR53_INTIICTEI3 (0x0000FF00uL) +#define INTC_ICDIPR53_INTIICRI3 (0x00FF0000uL) +#define INTC_ICDIPR53_INTIICTI3 (0xFF000000uL) + +#define INTC_ICDIPR54_INTIICSPI3 (0x000000FFuL) +#define INTC_ICDIPR54_INTIICSTI3 (0x0000FF00uL) +#define INTC_ICDIPR54_INTIICNAKI3 (0x00FF0000uL) +#define INTC_ICDIPR54_INTIICALI3 (0xFF000000uL) + +#define INTC_ICDIPR55_INTIICTMOI3 (0x000000FFuL) +#define INTC_ICDIPR55_BRI0 (0x0000FF00uL) +#define INTC_ICDIPR55_ERI0 (0x00FF0000uL) +#define INTC_ICDIPR55_RXI0 (0xFF000000uL) + +#define INTC_ICDIPR56_TXI0 (0x000000FFuL) +#define INTC_ICDIPR56_BRI1 (0x0000FF00uL) +#define INTC_ICDIPR56_ERI1 (0x00FF0000uL) +#define INTC_ICDIPR56_RXI1 (0xFF000000uL) + +#define INTC_ICDIPR57_TXI1 (0x000000FFuL) +#define INTC_ICDIPR57_BRI2 (0x0000FF00uL) +#define INTC_ICDIPR57_ERI2 (0x00FF0000uL) +#define INTC_ICDIPR57_RXI2 (0xFF000000uL) + +#define INTC_ICDIPR58_TXI2 (0x000000FFuL) +#define INTC_ICDIPR58_BRI3 (0x0000FF00uL) +#define INTC_ICDIPR58_ERI3 (0x00FF0000uL) +#define INTC_ICDIPR58_RXI3 (0xFF000000uL) + +#define INTC_ICDIPR59_TXI3 (0x000000FFuL) +#define INTC_ICDIPR59_BRI4 (0x0000FF00uL) +#define INTC_ICDIPR59_ERI4 (0x00FF0000uL) +#define INTC_ICDIPR59_RXI4 (0xFF000000uL) + +#define INTC_ICDIPR60_TXI4 (0x000000FFuL) +#define INTC_ICDIPR60_BRI5 (0x0000FF00uL) +#define INTC_ICDIPR60_ERI5 (0x00FF0000uL) +#define INTC_ICDIPR60_RXI5 (0xFF000000uL) + +#define INTC_ICDIPR61_TXI5 (0x000000FFuL) +#define INTC_ICDIPR61_BRI6 (0x0000FF00uL) +#define INTC_ICDIPR61_ERI6 (0x00FF0000uL) +#define INTC_ICDIPR61_RXI6 (0xFF000000uL) + +#define INTC_ICDIPR62_TXI6 (0x000000FFuL) +#define INTC_ICDIPR62_BRI7 (0x0000FF00uL) +#define INTC_ICDIPR62_ERI7 (0x00FF0000uL) +#define INTC_ICDIPR62_RXI7 (0xFF000000uL) + +#define INTC_ICDIPR63_TXI7 (0x000000FFuL) +#define INTC_ICDIPR63_INTRCANGERR (0x0000FF00uL) +#define INTC_ICDIPR63_INTRCANGRECC (0x00FF0000uL) +#define INTC_ICDIPR63_INTRCAN0REC (0xFF000000uL) + +#define INTC_ICDIPR64_INTRCAN0ERR (0x000000FFuL) +#define INTC_ICDIPR64_INTRCAN0TRX (0x0000FF00uL) +#define INTC_ICDIPR64_INTRCAN1REC (0x00FF0000uL) +#define INTC_ICDIPR64_INTRCAN1ERR (0xFF000000uL) + +#define INTC_ICDIPR65_INTRCAN1TRX (0x000000FFuL) +#define INTC_ICDIPR65_INTRCAN2REC (0x0000FF00uL) +#define INTC_ICDIPR65_INTRCAN2ERR (0x00FF0000uL) +#define INTC_ICDIPR65_INTRCAN2TRX (0xFF000000uL) + +#define INTC_ICDIPR66_INTRCAN3REC (0x000000FFuL) +#define INTC_ICDIPR66_INTRCAN3ERR (0x0000FF00uL) +#define INTC_ICDIPR66_INTRCAN3TRX (0x00FF0000uL) +#define INTC_ICDIPR66_INTRCAN4REC (0xFF000000uL) + +#define INTC_ICDIPR67_INTRCAN4ERR (0x000000FFuL) +#define INTC_ICDIPR67_INTRCAN4TRX (0x0000FF00uL) +#define INTC_ICDIPR67_SPEI0 (0x00FF0000uL) +#define INTC_ICDIPR67_SPRI0 (0xFF000000uL) + +#define INTC_ICDIPR68_SPTI0 (0x000000FFuL) +#define INTC_ICDIPR68_SPEI1 (0x0000FF00uL) +#define INTC_ICDIPR68_SPRI1 (0x00FF0000uL) +#define INTC_ICDIPR68_SPTI1 (0xFF000000uL) + +#define INTC_ICDIPR69_SPEI2 (0x000000FFuL) +#define INTC_ICDIPR69_SPRI2 (0x0000FF00uL) +#define INTC_ICDIPR69_SPTI2 (0x00FF0000uL) +#define INTC_ICDIPR69_SPEI3 (0xFF000000uL) + +#define INTC_ICDIPR70_SPRI3 (0x000000FFuL) +#define INTC_ICDIPR70_SPTI3 (0x0000FF00uL) +#define INTC_ICDIPR70_SPEI4 (0x00FF0000uL) +#define INTC_ICDIPR70_SPRI4 (0xFF000000uL) + +#define INTC_ICDIPR71_SPTI4 (0x000000FFuL) +#define INTC_ICDIPR71_IEBBTD (0x0000FF00uL) +#define INTC_ICDIPR71_IEBBTERR (0x00FF0000uL) +#define INTC_ICDIPR71_IEBBTSTA (0xFF000000uL) + +#define INTC_ICDIPR72_IEBBTV (0x000000FFuL) +#define INTC_ICDIPR72_ISY (0x0000FF00uL) +#define INTC_ICDIPR72_IERR (0x00FF0000uL) +#define INTC_ICDIPR72_ITARG (0xFF000000uL) + +#define INTC_ICDIPR73_ISEC (0x000000FFuL) +#define INTC_ICDIPR73_IBUF (0x0000FF00uL) +#define INTC_ICDIPR73_IREADY (0x00FF0000uL) +#define INTC_ICDIPR73_FLSTE (0xFF000000uL) + +#define INTC_ICDIPR74_FLTENDI (0x000000FFuL) +#define INTC_ICDIPR74_FLTREQ0I (0x0000FF00uL) +#define INTC_ICDIPR74_FLTREQ1I (0x00FF0000uL) +#define INTC_ICDIPR74_MMC0 (0xFF000000uL) + +#define INTC_ICDIPR75_MMC1 (0x000000FFuL) +#define INTC_ICDIPR75_MMC2 (0x0000FF00uL) +#define INTC_ICDIPR75_SDHI0_3 (0x00FF0000uL) +#define INTC_ICDIPR75_SDHI0_0 (0xFF000000uL) + +#define INTC_ICDIPR76_SDHI0_1 (0x000000FFuL) +#define INTC_ICDIPR76_SDHI1_3 (0x0000FF00uL) +#define INTC_ICDIPR76_SDHI1_0 (0x00FF0000uL) +#define INTC_ICDIPR76_SDHI1_1 (0xFF000000uL) + +#define INTC_ICDIPR77_ARM (0x000000FFuL) +#define INTC_ICDIPR77_PRD (0x0000FF00uL) +#define INTC_ICDIPR77_CUP (0x00FF0000uL) +#define INTC_ICDIPR77_SCUAI0 (0xFF000000uL) + +#define INTC_ICDIPR78_SCUAI1 (0x000000FFuL) +#define INTC_ICDIPR78_SCUFDI0 (0x0000FF00uL) +#define INTC_ICDIPR78_SCUFDI1 (0x00FF0000uL) +#define INTC_ICDIPR78_SCUFDI2 (0xFF000000uL) + +#define INTC_ICDIPR79_SCUFDI3 (0x000000FFuL) +#define INTC_ICDIPR79_SCUFUI0 (0x0000FF00uL) +#define INTC_ICDIPR79_SCUFUI1 (0x00FF0000uL) +#define INTC_ICDIPR79_SCUFUI2 (0xFF000000uL) + +#define INTC_ICDIPR80_SCUFUI3 (0x000000FFuL) +#define INTC_ICDIPR80_SCUDVI0 (0x0000FF00uL) +#define INTC_ICDIPR80_SCUDVI1 (0x00FF0000uL) +#define INTC_ICDIPR80_SCUDVI2 (0xFF000000uL) + +#define INTC_ICDIPR81_SCUDVI3 (0x000000FFuL) +#define INTC_ICDIPR81_MLB_CINT (0x0000FF00uL) +#define INTC_ICDIPR81_MLB_SINT (0x00FF0000uL) +#define INTC_ICDIPR81_DRC0 (0xFF000000uL) + +#define INTC_ICDIPR82_DRC1 (0x000000FFuL) +#define INTC_ICDIPR82_LINI0_INT_T (0xFF000000uL) + +#define INTC_ICDIPR83_LINI0_INT_R (0x000000FFuL) +#define INTC_ICDIPR83_LINI0_INT_S (0x0000FF00uL) +#define INTC_ICDIPR83_LINI0_INT_M (0x00FF0000uL) +#define INTC_ICDIPR83_LINI1_INT_T (0xFF000000uL) + +#define INTC_ICDIPR84_LINI1_INT_R (0x000000FFuL) +#define INTC_ICDIPR84_LINI1_INT_S (0x0000FF00uL) +#define INTC_ICDIPR84_LINI1_INT_M (0x00FF0000uL) + +#define INTC_ICDIPR86_ERI0 (0xFF000000uL) + +#define INTC_ICDIPR87_RXI0 (0x000000FFuL) +#define INTC_ICDIPR87_TXI0 (0x0000FF00uL) +#define INTC_ICDIPR87_TEI0 (0x00FF0000uL) +#define INTC_ICDIPR87_ERI1 (0xFF000000uL) + +#define INTC_ICDIPR88_RXI1 (0x000000FFuL) +#define INTC_ICDIPR88_TXI1 (0x0000FF00uL) +#define INTC_ICDIPR88_TEI1 (0x00FF0000uL) +#define INTC_ICDIPR88_AVBI_DATA (0xFF000000uL) + +#define INTC_ICDIPR89_AVBI_ERROR (0x000000FFuL) +#define INTC_ICDIPR89_AVBI_MANAGE (0x0000FF00uL) +#define INTC_ICDIPR89_AVBI_MAC (0x00FF0000uL) +#define INTC_ICDIPR89_ETHERI (0xFF000000uL) + +#define INTC_ICDIPR91_CEUI (0x000000FFuL) + +#define INTC_ICDIPR95_H2XMLB_ERRINT (0x0000FF00uL) +#define INTC_ICDIPR95_H2XIC1_ERRINT (0x00FF0000uL) +#define INTC_ICDIPR95_X2HPERI1_ERRINT (0xFF000000uL) + +#define INTC_ICDIPR96_X2HPERI2_ERRINT (0x000000FFuL) +#define INTC_ICDIPR96_X2HPERI34_ERRINT (0x0000FF00uL) +#define INTC_ICDIPR96_X2HPERI5_ERRINT (0x00FF0000uL) +#define INTC_ICDIPR96_X2HPERI67_ERRINT (0xFF000000uL) + +#define INTC_ICDIPR97_X2HDBGR_ERRINT (0x000000FFuL) +#define INTC_ICDIPR97_X2HBSC_ERRINT (0x0000FF00uL) +#define INTC_ICDIPR97_X2HSPI1_ERRINT (0x00FF0000uL) +#define INTC_ICDIPR97_X2HSPI2_ERRINT (0xFF000000uL) + +#define INTC_ICDIPR98_PRRI (0x000000FFuL) +#define INTC_ICDIPR98_IFEI0 (0x0000FF00uL) +#define INTC_ICDIPR98_OFFI0 (0x00FF0000uL) +#define INTC_ICDIPR98_PFVEI0 (0xFF000000uL) + +#define INTC_ICDIPR99_IFEI1 (0x000000FFuL) +#define INTC_ICDIPR99_OFFI1 (0x0000FF00uL) +#define INTC_ICDIPR99_PFVEI1 (0x00FF0000uL) + +#define INTC_ICDIPR104_TINT0 (0x000000FFuL) +#define INTC_ICDIPR104_TINT1 (0x0000FF00uL) +#define INTC_ICDIPR104_TINT2 (0x00FF0000uL) +#define INTC_ICDIPR104_TINT3 (0xFF000000uL) + +#define INTC_ICDIPR105_TINT4 (0x000000FFuL) +#define INTC_ICDIPR105_TINT5 (0x0000FF00uL) +#define INTC_ICDIPR105_TINT6 (0x00FF0000uL) +#define INTC_ICDIPR105_TINT7 (0xFF000000uL) + +#define INTC_ICDIPR106_TINT8 (0x000000FFuL) +#define INTC_ICDIPR106_TINT9 (0x0000FF00uL) +#define INTC_ICDIPR106_TINT10 (0x00FF0000uL) +#define INTC_ICDIPR106_TINT11 (0xFF000000uL) + +#define INTC_ICDIPR107_TINT12 (0x000000FFuL) +#define INTC_ICDIPR107_TINT13 (0x0000FF00uL) +#define INTC_ICDIPR107_TINT14 (0x00FF0000uL) +#define INTC_ICDIPR107_TINT15 (0xFF000000uL) + +#define INTC_ICDIPR108_TINT16 (0x000000FFuL) +#define INTC_ICDIPR108_TINT17 (0x0000FF00uL) +#define INTC_ICDIPR108_TINT18 (0x00FF0000uL) +#define INTC_ICDIPR108_TINT19 (0xFF000000uL) + +#define INTC_ICDIPR109_TINT20 (0x000000FFuL) +#define INTC_ICDIPR109_TINT21 (0x0000FF00uL) +#define INTC_ICDIPR109_TINT22 (0x00FF0000uL) +#define INTC_ICDIPR109_TINT23 (0xFF000000uL) + +#define INTC_ICDIPR110_TINT24 (0x000000FFuL) +#define INTC_ICDIPR110_TINT25 (0x0000FF00uL) +#define INTC_ICDIPR110_TINT26 (0x00FF0000uL) +#define INTC_ICDIPR110_TINT27 (0xFF000000uL) + +#define INTC_ICDIPR111_TINT28 (0x000000FFuL) +#define INTC_ICDIPR111_TINT29 (0x0000FF00uL) +#define INTC_ICDIPR111_TINT30 (0x00FF0000uL) +#define INTC_ICDIPR111_TINT31 (0xFF000000uL) + +#define INTC_ICDIPR112_TINT32 (0x000000FFuL) +#define INTC_ICDIPR112_TINT33 (0x0000FF00uL) +#define INTC_ICDIPR112_TINT34 (0x00FF0000uL) +#define INTC_ICDIPR112_TINT35 (0xFF000000uL) + +#define INTC_ICDIPR113_TINT36 (0x000000FFuL) +#define INTC_ICDIPR113_TINT37 (0x0000FF00uL) +#define INTC_ICDIPR113_TINT38 (0x00FF0000uL) +#define INTC_ICDIPR113_TINT39 (0xFF000000uL) + +#define INTC_ICDIPR114_TINT40 (0x000000FFuL) +#define INTC_ICDIPR114_TINT41 (0x0000FF00uL) +#define INTC_ICDIPR114_TINT42 (0x00FF0000uL) +#define INTC_ICDIPR114_TINT43 (0xFF000000uL) + +#define INTC_ICDIPR115_TINT44 (0x000000FFuL) +#define INTC_ICDIPR115_TINT45 (0x0000FF00uL) +#define INTC_ICDIPR115_TINT46 (0x00FF0000uL) +#define INTC_ICDIPR115_TINT47 (0xFF000000uL) + +#define INTC_ICDIPR116_TINT48 (0x000000FFuL) +#define INTC_ICDIPR116_TINT49 (0x0000FF00uL) +#define INTC_ICDIPR116_TINT50 (0x00FF0000uL) +#define INTC_ICDIPR116_TINT51 (0xFF000000uL) + +#define INTC_ICDIPR117_TINT52 (0x000000FFuL) +#define INTC_ICDIPR117_TINT53 (0x0000FF00uL) +#define INTC_ICDIPR117_TINT54 (0x00FF0000uL) +#define INTC_ICDIPR117_TINT55 (0xFF000000uL) + +#define INTC_ICDIPR118_TINT56 (0x000000FFuL) +#define INTC_ICDIPR118_TINT57 (0x0000FF00uL) +#define INTC_ICDIPR118_TINT58 (0x00FF0000uL) +#define INTC_ICDIPR118_TINT59 (0xFF000000uL) + +#define INTC_ICDIPR119_TINT60 (0x000000FFuL) +#define INTC_ICDIPR119_TINT61 (0x0000FF00uL) +#define INTC_ICDIPR119_TINT62 (0x00FF0000uL) +#define INTC_ICDIPR119_TINT63 (0xFF000000uL) + +#define INTC_ICDIPR120_TINT64 (0x000000FFuL) +#define INTC_ICDIPR120_TINT65 (0x0000FF00uL) +#define INTC_ICDIPR120_TINT66 (0x00FF0000uL) +#define INTC_ICDIPR120_TINT67 (0xFF000000uL) + +#define INTC_ICDIPR121_TINT68 (0x000000FFuL) +#define INTC_ICDIPR121_TINT69 (0x0000FF00uL) +#define INTC_ICDIPR121_TINT70 (0x00FF0000uL) +#define INTC_ICDIPR121_TINT71 (0xFF000000uL) + +#define INTC_ICDIPR122_TINT72 (0x000000FFuL) +#define INTC_ICDIPR122_TINT73 (0x0000FF00uL) +#define INTC_ICDIPR122_TINT74 (0x00FF0000uL) +#define INTC_ICDIPR122_TINT75 (0xFF000000uL) + +#define INTC_ICDIPR123_TINT76 (0x000000FFuL) +#define INTC_ICDIPR123_TINT77 (0x0000FF00uL) +#define INTC_ICDIPR123_TINT78 (0x00FF0000uL) +#define INTC_ICDIPR123_TINT79 (0xFF000000uL) + +#define INTC_ICDIPR124_TINT80 (0x000000FFuL) +#define INTC_ICDIPR124_TINT81 (0x0000FF00uL) +#define INTC_ICDIPR124_TINT82 (0x00FF0000uL) +#define INTC_ICDIPR124_TINT83 (0xFF000000uL) + +#define INTC_ICDIPR125_TINT84 (0x000000FFuL) +#define INTC_ICDIPR125_TINT85 (0x0000FF00uL) +#define INTC_ICDIPR125_TINT86 (0x00FF0000uL) +#define INTC_ICDIPR125_TINT87 (0xFF000000uL) + +#define INTC_ICDIPR126_TINT88 (0x000000FFuL) +#define INTC_ICDIPR126_TINT89 (0x0000FF00uL) +#define INTC_ICDIPR126_TINT90 (0x00FF0000uL) +#define INTC_ICDIPR126_TINT91 (0xFF000000uL) + +#define INTC_ICDIPR127_TINT92 (0x000000FFuL) +#define INTC_ICDIPR127_TINT93 (0x0000FF00uL) +#define INTC_ICDIPR127_TINT94 (0x00FF0000uL) +#define INTC_ICDIPR127_TINT95 (0xFF000000uL) + +#define INTC_ICDIPR128_TINT96 (0x000000FFuL) +#define INTC_ICDIPR128_TINT97 (0x0000FF00uL) +#define INTC_ICDIPR128_TINT98 (0x00FF0000uL) +#define INTC_ICDIPR128_TINT99 (0xFF000000uL) + +#define INTC_ICDIPR129_TINT100 (0x000000FFuL) +#define INTC_ICDIPR129_TINT101 (0x0000FF00uL) +#define INTC_ICDIPR129_TINT102 (0x00FF0000uL) +#define INTC_ICDIPR129_TINT103 (0xFF000000uL) + +#define INTC_ICDIPR130_TINT104 (0x000000FFuL) +#define INTC_ICDIPR130_TINT105 (0x0000FF00uL) +#define INTC_ICDIPR130_TINT106 (0x00FF0000uL) +#define INTC_ICDIPR130_TINT107 (0xFF000000uL) + +#define INTC_ICDIPR131_TINT108 (0x000000FFuL) +#define INTC_ICDIPR131_TINT109 (0x0000FF00uL) +#define INTC_ICDIPR131_TINT110 (0x00FF0000uL) +#define INTC_ICDIPR131_TINT111 (0xFF000000uL) + +#define INTC_ICDIPR132_TINT112 (0x000000FFuL) +#define INTC_ICDIPR132_TINT113 (0x0000FF00uL) +#define INTC_ICDIPR132_TINT114 (0x00FF0000uL) +#define INTC_ICDIPR132_TINT115 (0xFF000000uL) + +#define INTC_ICDIPR133_TINT116 (0x000000FFuL) +#define INTC_ICDIPR133_TINT117 (0x0000FF00uL) +#define INTC_ICDIPR133_TINT118 (0x00FF0000uL) +#define INTC_ICDIPR133_TINT119 (0xFF000000uL) + +#define INTC_ICDIPR134_TINT120 (0x000000FFuL) +#define INTC_ICDIPR134_TINT121 (0x0000FF00uL) +#define INTC_ICDIPR134_TINT122 (0x00FF0000uL) +#define INTC_ICDIPR134_TINT123 (0xFF000000uL) + +#define INTC_ICDIPR135_TINT124 (0x000000FFuL) +#define INTC_ICDIPR135_TINT125 (0x0000FF00uL) +#define INTC_ICDIPR135_TINT126 (0x00FF0000uL) +#define INTC_ICDIPR135_TINT127 (0xFF000000uL) + +#define INTC_ICDIPR136_TINT128 (0x000000FFuL) +#define INTC_ICDIPR136_TINT129 (0x0000FF00uL) +#define INTC_ICDIPR136_TINT130 (0x00FF0000uL) +#define INTC_ICDIPR136_TINT131 (0xFF000000uL) + +#define INTC_ICDIPR137_TINT132 (0x000000FFuL) +#define INTC_ICDIPR137_TINT133 (0x0000FF00uL) +#define INTC_ICDIPR137_TINT134 (0x00FF0000uL) +#define INTC_ICDIPR137_TINT135 (0xFF000000uL) + +#define INTC_ICDIPR138_TINT136 (0x000000FFuL) +#define INTC_ICDIPR138_TINT137 (0x0000FF00uL) +#define INTC_ICDIPR138_TINT138 (0x00FF0000uL) +#define INTC_ICDIPR138_TINT139 (0xFF000000uL) + +#define INTC_ICDIPR139_TINT140 (0x000000FFuL) +#define INTC_ICDIPR139_TINT141 (0x0000FF00uL) +#define INTC_ICDIPR139_TINT142 (0x00FF0000uL) +#define INTC_ICDIPR139_TINT143 (0xFF000000uL) + +#define INTC_ICDIPR140_TINT144 (0x000000FFuL) +#define INTC_ICDIPR140_TINT145 (0x0000FF00uL) +#define INTC_ICDIPR140_TINT146 (0x00FF0000uL) +#define INTC_ICDIPR140_TINT147 (0xFF000000uL) + +#define INTC_ICDIPR141_TINT148 (0x000000FFuL) +#define INTC_ICDIPR141_TINT149 (0x0000FF00uL) +#define INTC_ICDIPR141_TINT150 (0x00FF0000uL) +#define INTC_ICDIPR141_TINT151 (0xFF000000uL) + +#define INTC_ICDIPR142_TINT152 (0x000000FFuL) +#define INTC_ICDIPR142_TINT153 (0x0000FF00uL) +#define INTC_ICDIPR142_TINT154 (0x00FF0000uL) +#define INTC_ICDIPR142_TINT155 (0xFF000000uL) + +#define INTC_ICDIPR143_TINT156 (0x000000FFuL) +#define INTC_ICDIPR143_TINT157 (0x0000FF00uL) +#define INTC_ICDIPR143_TINT158 (0x00FF0000uL) +#define INTC_ICDIPR143_TINT159 (0xFF000000uL) + +#define INTC_ICDIPR144_TINT160 (0x000000FFuL) +#define INTC_ICDIPR144_TINT161 (0x0000FF00uL) +#define INTC_ICDIPR144_TINT162 (0x00FF0000uL) +#define INTC_ICDIPR144_TINT163 (0xFF000000uL) + +#define INTC_ICDIPR145_TINT164 (0x000000FFuL) +#define INTC_ICDIPR145_TINT165 (0x0000FF00uL) +#define INTC_ICDIPR145_TINT166 (0x00FF0000uL) +#define INTC_ICDIPR145_TINT167 (0xFF000000uL) + +#define INTC_ICDIPR146_TINT168 (0x000000FFuL) +#define INTC_ICDIPR146_TINT169 (0x0000FF00uL) +#define INTC_ICDIPR146_TINT170 (0x00FF0000uL) + +#define INTC_ICDIPTR0_SW0 (0x000000FFuL) +#define INTC_ICDIPTR0_SW1 (0x0000FF00uL) +#define INTC_ICDIPTR0_SW2 (0x00FF0000uL) +#define INTC_ICDIPTR0_SW3 (0xFF000000uL) + +#define INTC_ICDIPTR1_SW4 (0x000000FFuL) +#define INTC_ICDIPTR1_SW5 (0x0000FF00uL) +#define INTC_ICDIPTR1_SW6 (0x00FF0000uL) +#define INTC_ICDIPTR1_SW7 (0xFF000000uL) + +#define INTC_ICDIPTR2_SW8 (0x000000FFuL) +#define INTC_ICDIPTR2_SW9 (0x0000FF00uL) +#define INTC_ICDIPTR2_SW10 (0x00FF0000uL) +#define INTC_ICDIPTR2_SW11 (0xFF000000uL) + +#define INTC_ICDIPTR3_SW12 (0x000000FFuL) +#define INTC_ICDIPTR3_SW13 (0x0000FF00uL) +#define INTC_ICDIPTR3_SW14 (0x00FF0000uL) +#define INTC_ICDIPTR3_SW15 (0xFF000000uL) + +#define INTC_ICDIPTR4_PMUIRQ0 (0x000000FFuL) +#define INTC_ICDIPTR4_COMMRX0 (0x0000FF00uL) +#define INTC_ICDIPTR4_COMMTX0 (0x00FF0000uL) +#define INTC_ICDIPTR4_CTIIRQ0 (0xFF000000uL) + +#define INTC_ICDIPTR8_IRQ0 (0x000000FFuL) +#define INTC_ICDIPTR8_IRQ1 (0x0000FF00uL) +#define INTC_ICDIPTR8_IRQ2 (0x00FF0000uL) +#define INTC_ICDIPTR8_IRQ3 (0xFF000000uL) + +#define INTC_ICDIPTR9_IRQ4 (0x000000FFuL) +#define INTC_ICDIPTR9_IRQ5 (0x0000FF00uL) +#define INTC_ICDIPTR9_IRQ6 (0x00FF0000uL) +#define INTC_ICDIPTR9_IRQ7 (0xFF000000uL) + +#define INTC_ICDIPTR10_PL310ERR (0x000000FFuL) +#define INTC_ICDIPTR10_DMAINT0 (0x0000FF00uL) +#define INTC_ICDIPTR10_DMAINT1 (0x00FF0000uL) +#define INTC_ICDIPTR10_DMAINT2 (0xFF000000uL) + +#define INTC_ICDIPTR11_DMAINT3 (0x000000FFuL) +#define INTC_ICDIPTR11_DMAINT4 (0x0000FF00uL) +#define INTC_ICDIPTR11_DMAINT5 (0x00FF0000uL) +#define INTC_ICDIPTR11_DMAINT6 (0xFF000000uL) + +#define INTC_ICDIPTR12_DMAINT7 (0x000000FFuL) +#define INTC_ICDIPTR12_DMAINT8 (0x0000FF00uL) +#define INTC_ICDIPTR12_DMAINT9 (0x00FF0000uL) +#define INTC_ICDIPTR12_DMAINT10 (0xFF000000uL) + +#define INTC_ICDIPTR13_DMAINT11 (0x000000FFuL) +#define INTC_ICDIPTR13_DMAINT12 (0x0000FF00uL) +#define INTC_ICDIPTR13_DMAINT13 (0x00FF0000uL) +#define INTC_ICDIPTR13_DMAINT14 (0xFF000000uL) + +#define INTC_ICDIPTR14_DMAINT15 (0x000000FFuL) +#define INTC_ICDIPTR14_DMAERR (0x0000FF00uL) + +#define INTC_ICDIPTR18_USBI0 (0x0000FF00uL) +#define INTC_ICDIPTR18_USBI1 (0x00FF0000uL) +#define INTC_ICDIPTR18_S0_VI_VSYNC0 (0xFF000000uL) + +#define INTC_ICDIPTR19_S0_LO_VSYNC0 (0x000000FFuL) +#define INTC_ICDIPTR19_S0_VSYNCERR0 (0x0000FF00uL) +#define INTC_ICDIPTR19_GR3_VLINE0 (0x00FF0000uL) +#define INTC_ICDIPTR19_S0_VFIELD0 (0xFF000000uL) + +#define INTC_ICDIPTR20_IV1_VBUFERR0 (0x000000FFuL) +#define INTC_ICDIPTR20_IV3_VBUFERR0 (0x0000FF00uL) +#define INTC_ICDIPTR20_IV5_VBUFERR0 (0x00FF0000uL) +#define INTC_ICDIPTR20_IV6_VBUFERR0 (0xFF000000uL) + +#define INTC_ICDIPTR21_S0_WLINE0 (0x000000FFuL) +#define INTC_ICDIPTR21_S1_VI_VSYNC0 (0x0000FF00uL) +#define INTC_ICDIPTR21_S1_LO_VSYNC0 (0x00FF0000uL) +#define INTC_ICDIPTR21_S1_VSYNCERR0 (0xFF000000uL) + +#define INTC_ICDIPTR22_S1_VFIELD0 (0x000000FFuL) +#define INTC_ICDIPTR22_IV2_VBUFERR0 (0x0000FF00uL) +#define INTC_ICDIPTR22_IV4_VBUFERR0 (0x00FF0000uL) +#define INTC_ICDIPTR22_S1_WLINE0 (0xFF000000uL) + +#define INTC_ICDIPTR23_OIR_VI_VSYNC0 (0x000000FFuL) +#define INTC_ICDIPTR23_OIR_LO_VSYNC0 (0x0000FF00uL) +#define INTC_ICDIPTR23_OIR_VSYNCERR0 (0x00FF0000uL) +#define INTC_ICDIPTR23_OIR_VFIELD0 (0xFF000000uL) + +#define INTC_ICDIPTR24_IV7_VBUFERR0 (0x000000FFuL) +#define INTC_ICDIPTR24_IV8_VBUFERR0 (0x0000FF00uL) +#define INTC_ICDIPTR24_S0_VI_VSYNC1 (0xFF000000uL) + +#define INTC_ICDIPTR25_S0_LO_VSYNC1 (0x000000FFuL) +#define INTC_ICDIPTR25_S0_VSYNCERR1 (0x0000FF00uL) +#define INTC_ICDIPTR25_GR3_VLINE1 (0x00FF0000uL) +#define INTC_ICDIPTR25_S0_VFIELD1 (0xFF000000uL) + +#define INTC_ICDIPTR26_IV1_VBUFERR1 (0x000000FFuL) +#define INTC_ICDIPTR26_IV3_VBUFERR1 (0x0000FF00uL) +#define INTC_ICDIPTR26_IV5_VBUFERR1 (0x00FF0000uL) +#define INTC_ICDIPTR26_IV6_VBUFERR1 (0xFF000000uL) + +#define INTC_ICDIPTR27_S0_WLINE1 (0x000000FFuL) +#define INTC_ICDIPTR27_S1_VI_VSYNC1 (0x0000FF00uL) +#define INTC_ICDIPTR27_S1_LO_VSYNC1 (0x00FF0000uL) +#define INTC_ICDIPTR27_S1_VSYNCERR1 (0xFF000000uL) + +#define INTC_ICDIPTR28_S1_VFIELD1 (0x000000FFuL) +#define INTC_ICDIPTR28_IV2_VBUFERR1 (0x0000FF00uL) +#define INTC_ICDIPTR28_IV4_VBUFERR1 (0x00FF0000uL) +#define INTC_ICDIPTR28_S1_WLINE1 (0xFF000000uL) + +#define INTC_ICDIPTR29_OIR_VI_VSYNC1 (0x000000FFuL) +#define INTC_ICDIPTR29_OIR_LO_VSYNC1 (0x0000FF00uL) +#define INTC_ICDIPTR29_OIR_VLINE1 (0x00FF0000uL) +#define INTC_ICDIPTR29_OIR_VFIELD1 (0xFF000000uL) + +#define INTC_ICDIPTR30_IV7_VBUFERR1 (0x000000FFuL) +#define INTC_ICDIPTR30_IV8_VBUFERR1 (0x0000FF00uL) +#define INTC_ICDIPTR30_IMRDI (0xFF000000uL) + +#define INTC_ICDIPTR31_IMR2I0 (0x000000FFuL) +#define INTC_ICDIPTR31_IMR2I1 (0x0000FF00uL) +#define INTC_ICDIPTR31_JEDI (0x00FF0000uL) +#define INTC_ICDIPTR31_JDTI (0xFF000000uL) + +#define INTC_ICDIPTR32_CMP0 (0x000000FFuL) +#define INTC_ICDIPTR32_CMP1 (0x0000FF00uL) +#define INTC_ICDIPTR32_INT0 (0x00FF0000uL) +#define INTC_ICDIPTR32_INT1 (0xFF000000uL) + +#define INTC_ICDIPTR33_INT2 (0x000000FFuL) +#define INTC_ICDIPTR33_INT3 (0x0000FF00uL) +#define INTC_ICDIPTR33_OSTM0TINT (0x00FF0000uL) +#define INTC_ICDIPTR33_OSTM1TINT (0xFF000000uL) + +#define INTC_ICDIPTR34_CMI (0x000000FFuL) +#define INTC_ICDIPTR34_WTOUT (0x0000FF00uL) +#define INTC_ICDIPTR34_ITI (0x00FF0000uL) +#define INTC_ICDIPTR34_TGI0A (0xFF000000uL) + +#define INTC_ICDIPTR35_TGI0B (0x000000FFuL) +#define INTC_ICDIPTR35_TGI0C (0x0000FF00uL) +#define INTC_ICDIPTR35_TGI0D (0x00FF0000uL) +#define INTC_ICDIPTR35_TGI0V (0xFF000000uL) + +#define INTC_ICDIPTR36_TGI0E (0x000000FFuL) +#define INTC_ICDIPTR36_TGI0F (0x0000FF00uL) +#define INTC_ICDIPTR36_TGI1A (0x00FF0000uL) +#define INTC_ICDIPTR36_TGI1B (0xFF000000uL) + +#define INTC_ICDIPTR37_TGI1V (0x000000FFuL) +#define INTC_ICDIPTR37_TGI1U (0x0000FF00uL) +#define INTC_ICDIPTR37_TGI2A (0x00FF0000uL) +#define INTC_ICDIPTR37_TGI2B (0xFF000000uL) + +#define INTC_ICDIPTR38_TGI2V (0x000000FFuL) +#define INTC_ICDIPTR38_TGI2U (0x0000FF00uL) +#define INTC_ICDIPTR38_TGI3A (0x00FF0000uL) +#define INTC_ICDIPTR38_TGI3B (0xFF000000uL) + +#define INTC_ICDIPTR39_TGI3C (0x000000FFuL) +#define INTC_ICDIPTR39_TGI3D (0x0000FF00uL) +#define INTC_ICDIPTR39_TGI3V (0x00FF0000uL) +#define INTC_ICDIPTR39_TGI4A (0xFF000000uL) + +#define INTC_ICDIPTR40_TGI4B (0x000000FFuL) +#define INTC_ICDIPTR40_TGI4C (0x0000FF00uL) +#define INTC_ICDIPTR40_TGI4D (0x00FF0000uL) +#define INTC_ICDIPTR40_TGI4V (0xFF000000uL) + +#define INTC_ICDIPTR41_CMI1 (0x000000FFuL) +#define INTC_ICDIPTR41_CMI2 (0x0000FF00uL) +#define INTC_ICDIPTR41_SGDEI0 (0x00FF0000uL) +#define INTC_ICDIPTR41_SGDEI1 (0xFF000000uL) + +#define INTC_ICDIPTR42_SGDEI2 (0x000000FFuL) +#define INTC_ICDIPTR42_SGDEI3 (0x0000FF00uL) +#define INTC_ICDIPTR42_ADI (0x00FF0000uL) +#define INTC_ICDIPTR42_LMTI (0xFF000000uL) + +#define INTC_ICDIPTR43_SSII0 (0x000000FFuL) +#define INTC_ICDIPTR43_SSIRXI0 (0x0000FF00uL) +#define INTC_ICDIPTR43_SSITXI0 (0x00FF0000uL) +#define INTC_ICDIPTR43_SSII1 (0xFF000000uL) + +#define INTC_ICDIPTR44_SSIRXI1 (0x000000FFuL) +#define INTC_ICDIPTR44_SSITXI1 (0x0000FF00uL) +#define INTC_ICDIPTR44_SSII2 (0x00FF0000uL) +#define INTC_ICDIPTR44_SSIRTI2 (0xFF000000uL) + +#define INTC_ICDIPTR45_SSII3 (0x000000FFuL) +#define INTC_ICDIPTR45_SSIRXI3 (0x0000FF00uL) +#define INTC_ICDIPTR45_SSITXI3 (0x00FF0000uL) +#define INTC_ICDIPTR45_SSII4 (0xFF000000uL) + +#define INTC_ICDIPTR46_SSIRTI4 (0x000000FFuL) +#define INTC_ICDIPTR46_SSII5 (0x0000FF00uL) +#define INTC_ICDIPTR46_SSIRXI5 (0x00FF0000uL) +#define INTC_ICDIPTR46_SSITXI5 (0xFF000000uL) + +#define INTC_ICDIPTR47_SPDIFI (0x000000FFuL) +#define INTC_ICDIPTR47_INTIICTEI0 (0x0000FF00uL) +#define INTC_ICDIPTR47_INTIICRI0 (0x00FF0000uL) +#define INTC_ICDIPTR47_INTIICTI0 (0xFF000000uL) + +#define INTC_ICDIPTR48_INTIICSPI0 (0x000000FFuL) +#define INTC_ICDIPTR48_INTIICSTI0 (0x0000FF00uL) +#define INTC_ICDIPTR48_INTIICNAKI0 (0x00FF0000uL) +#define INTC_ICDIPTR48_INTIICALI0 (0xFF000000uL) + +#define INTC_ICDIPTR49_INTIICTMOI0 (0x000000FFuL) +#define INTC_ICDIPTR49_INTIICTEI1 (0x0000FF00uL) +#define INTC_ICDIPTR49_INTIICRI1 (0x00FF0000uL) +#define INTC_ICDIPTR49_INTIICTI1 (0xFF000000uL) + +#define INTC_ICDIPTR50_INTIICSPI1 (0x000000FFuL) +#define INTC_ICDIPTR50_INTIICSTI1 (0x0000FF00uL) +#define INTC_ICDIPTR50_INTIICNAKI1 (0x00FF0000uL) +#define INTC_ICDIPTR50_INTIICALI1 (0xFF000000uL) + +#define INTC_ICDIPTR51_INTIICTMOI1 (0x000000FFuL) +#define INTC_ICDIPTR51_INTIICTEI2 (0x0000FF00uL) +#define INTC_ICDIPTR51_INTIICRI2 (0x00FF0000uL) +#define INTC_ICDIPTR51_INTIICTI2 (0xFF000000uL) + +#define INTC_ICDIPTR52_INTIICSPI2 (0x000000FFuL) +#define INTC_ICDIPTR52_INTIICSTI2 (0x0000FF00uL) +#define INTC_ICDIPTR52_INTIICNAKI2 (0x00FF0000uL) +#define INTC_ICDIPTR52_INTIICALI2 (0xFF000000uL) + +#define INTC_ICDIPTR53_INTIICTMOI2 (0x000000FFuL) +#define INTC_ICDIPTR53_INTIICTEI3 (0x0000FF00uL) +#define INTC_ICDIPTR53_INTIICRI3 (0x00FF0000uL) +#define INTC_ICDIPTR53_INTIICTI3 (0xFF000000uL) + +#define INTC_ICDIPTR54_INTIICSPI3 (0x000000FFuL) +#define INTC_ICDIPTR54_INTIICSTI3 (0x0000FF00uL) +#define INTC_ICDIPTR54_INTIICNAKI3 (0x00FF0000uL) +#define INTC_ICDIPTR54_INTIICALI3 (0xFF000000uL) + +#define INTC_ICDIPTR55_INTIICTMOI3 (0x000000FFuL) +#define INTC_ICDIPTR55_BRI0 (0x0000FF00uL) +#define INTC_ICDIPTR55_ERI0 (0x00FF0000uL) +#define INTC_ICDIPTR55_RXI0 (0xFF000000uL) + +#define INTC_ICDIPTR56_TXI0 (0x000000FFuL) +#define INTC_ICDIPTR56_BRI1 (0x0000FF00uL) +#define INTC_ICDIPTR56_ERI1 (0x00FF0000uL) +#define INTC_ICDIPTR56_RXI1 (0xFF000000uL) + +#define INTC_ICDIPTR57_TXI1 (0x000000FFuL) +#define INTC_ICDIPTR57_BRI2 (0x0000FF00uL) +#define INTC_ICDIPTR57_ERI2 (0x00FF0000uL) +#define INTC_ICDIPTR57_RXI2 (0xFF000000uL) + +#define INTC_ICDIPTR58_TXI2 (0x000000FFuL) +#define INTC_ICDIPTR58_BRI3 (0x0000FF00uL) +#define INTC_ICDIPTR58_ERI3 (0x00FF0000uL) +#define INTC_ICDIPTR58_RXI3 (0xFF000000uL) + +#define INTC_ICDIPTR59_TXI3 (0x000000FFuL) +#define INTC_ICDIPTR59_BRI4 (0x0000FF00uL) +#define INTC_ICDIPTR59_ERI4 (0x00FF0000uL) +#define INTC_ICDIPTR59_RXI4 (0xFF000000uL) + +#define INTC_ICDIPTR60_TXI4 (0x000000FFuL) +#define INTC_ICDIPTR60_BRI5 (0x0000FF00uL) +#define INTC_ICDIPTR60_ERI5 (0x00FF0000uL) +#define INTC_ICDIPTR60_RXI5 (0xFF000000uL) + +#define INTC_ICDIPTR61_TXI5 (0x000000FFuL) +#define INTC_ICDIPTR61_BRI6 (0x0000FF00uL) +#define INTC_ICDIPTR61_ERI6 (0x00FF0000uL) +#define INTC_ICDIPTR61_RXI6 (0xFF000000uL) + +#define INTC_ICDIPTR62_TXI6 (0x000000FFuL) +#define INTC_ICDIPTR62_BRI7 (0x0000FF00uL) +#define INTC_ICDIPTR62_ERI7 (0x00FF0000uL) +#define INTC_ICDIPTR62_RXI7 (0xFF000000uL) + +#define INTC_ICDIPTR63_TXI7 (0x000000FFuL) +#define INTC_ICDIPTR63_INTRCANGERR (0x0000FF00uL) +#define INTC_ICDIPTR63_INTRCANGRECC (0x00FF0000uL) +#define INTC_ICDIPTR63_INTRCAN0REC (0xFF000000uL) + +#define INTC_ICDIPTR64_INTRCAN0ERR (0x000000FFuL) +#define INTC_ICDIPTR64_INTRCAN0TRX (0x0000FF00uL) +#define INTC_ICDIPTR64_INTRCAN1REC (0x00FF0000uL) +#define INTC_ICDIPTR64_INTRCAN1ERR (0xFF000000uL) + +#define INTC_ICDIPTR65_INTRCAN1TRX (0x000000FFuL) +#define INTC_ICDIPTR65_INTRCAN2REC (0x0000FF00uL) +#define INTC_ICDIPTR65_INTRCAN2ERR (0x00FF0000uL) +#define INTC_ICDIPTR65_INTRCAN2TRX (0xFF000000uL) + +#define INTC_ICDIPTR66_INTRCAN3REC (0x000000FFuL) +#define INTC_ICDIPTR66_INTRCAN3ERR (0x0000FF00uL) +#define INTC_ICDIPTR66_INTRCAN3TRX (0x00FF0000uL) +#define INTC_ICDIPTR66_INTRCAN4REC (0xFF000000uL) + +#define INTC_ICDIPTR67_INTRCAN4ERR (0x000000FFuL) +#define INTC_ICDIPTR67_INTRCAN4TRX (0x0000FF00uL) +#define INTC_ICDIPTR67_SPEI0 (0x00FF0000uL) +#define INTC_ICDIPTR67_SPRI0 (0xFF000000uL) + +#define INTC_ICDIPTR68_SPTI0 (0x000000FFuL) +#define INTC_ICDIPTR68_SPEI1 (0x0000FF00uL) +#define INTC_ICDIPTR68_SPRI1 (0x00FF0000uL) +#define INTC_ICDIPTR68_SPTI1 (0xFF000000uL) + +#define INTC_ICDIPTR69_SPEI2 (0x000000FFuL) +#define INTC_ICDIPTR69_SPRI2 (0x0000FF00uL) +#define INTC_ICDIPTR69_SPTI2 (0x00FF0000uL) +#define INTC_ICDIPTR69_SPEI3 (0xFF000000uL) + +#define INTC_ICDIPTR70_SPRI3 (0x000000FFuL) +#define INTC_ICDIPTR70_SPTI3 (0x0000FF00uL) +#define INTC_ICDIPTR70_SPEI4 (0x00FF0000uL) +#define INTC_ICDIPTR70_SPRI4 (0xFF000000uL) + +#define INTC_ICDIPTR71_SPTI4 (0x000000FFuL) +#define INTC_ICDIPTR71_IEBBTD (0x0000FF00uL) +#define INTC_ICDIPTR71_IEBBTERR (0x00FF0000uL) +#define INTC_ICDIPTR71_IEBBTSTA (0xFF000000uL) + +#define INTC_ICDIPTR72_IEBBTV (0x000000FFuL) +#define INTC_ICDIPTR72_ISY (0x0000FF00uL) +#define INTC_ICDIPTR72_IERR (0x00FF0000uL) +#define INTC_ICDIPTR72_ITARG (0xFF000000uL) + +#define INTC_ICDIPTR73_ISEC (0x000000FFuL) +#define INTC_ICDIPTR73_IBUF (0x0000FF00uL) +#define INTC_ICDIPTR73_IREADY (0x00FF0000uL) +#define INTC_ICDIPTR73_FLSTE (0xFF000000uL) + +#define INTC_ICDIPTR74_FLTENDI (0x000000FFuL) +#define INTC_ICDIPTR74_FLTREQ0I (0x0000FF00uL) +#define INTC_ICDIPTR74_FLTREQ1I (0x00FF0000uL) +#define INTC_ICDIPTR74_MMC0 (0xFF000000uL) + +#define INTC_ICDIPTR75_MMC1 (0x000000FFuL) +#define INTC_ICDIPTR75_MMC2 (0x0000FF00uL) +#define INTC_ICDIPTR75_SDHI0_3 (0x00FF0000uL) +#define INTC_ICDIPTR75_SDHI0_0 (0xFF000000uL) + +#define INTC_ICDIPTR76_SDHI0_1 (0x000000FFuL) +#define INTC_ICDIPTR76_SDHI1_3 (0x0000FF00uL) +#define INTC_ICDIPTR76_SDHI1_0 (0x00FF0000uL) +#define INTC_ICDIPTR76_SDHI1_1 (0xFF000000uL) + +#define INTC_ICDIPTR77_ARM (0x000000FFuL) +#define INTC_ICDIPTR77_PRD (0x0000FF00uL) +#define INTC_ICDIPTR77_CUP (0x00FF0000uL) +#define INTC_ICDIPTR77_SCUAI0 (0xFF000000uL) + +#define INTC_ICDIPTR78_SCUAI1 (0x000000FFuL) +#define INTC_ICDIPTR78_SCUFDI0 (0x0000FF00uL) +#define INTC_ICDIPTR78_SCUFDI1 (0x00FF0000uL) +#define INTC_ICDIPTR78_SCUFDI2 (0xFF000000uL) + +#define INTC_ICDIPTR79_SCUFDI3 (0x000000FFuL) +#define INTC_ICDIPTR79_SCUFUI0 (0x0000FF00uL) +#define INTC_ICDIPTR79_SCUFUI1 (0x00FF0000uL) +#define INTC_ICDIPTR79_SCUFUI2 (0xFF000000uL) + +#define INTC_ICDIPTR80_SCUFUI3 (0x000000FFuL) +#define INTC_ICDIPTR80_SCUDVI0 (0x0000FF00uL) +#define INTC_ICDIPTR80_SCUDVI1 (0x00FF0000uL) +#define INTC_ICDIPTR80_SCUDVI2 (0xFF000000uL) + +#define INTC_ICDIPTR81_SCUDVI3 (0x000000FFuL) +#define INTC_ICDIPTR81_MLB_CINT (0x0000FF00uL) +#define INTC_ICDIPTR81_MLB_SINT (0x00FF0000uL) +#define INTC_ICDIPTR81_DRC0 (0xFF000000uL) + +#define INTC_ICDIPTR82_DRC1 (0x000000FFuL) +#define INTC_ICDIPTR82_LINI0_INT_T (0xFF000000uL) + +#define INTC_ICDIPTR83_LINI0_INT_R (0x000000FFuL) +#define INTC_ICDIPTR83_LINI0_INT_S (0x0000FF00uL) +#define INTC_ICDIPTR83_LINI0_INT_M (0x00FF0000uL) +#define INTC_ICDIPTR83_LINI1_INT_T (0xFF000000uL) + +#define INTC_ICDIPTR84_LINI1_INT_R (0x000000FFuL) +#define INTC_ICDIPTR84_LINI1_INT_S (0x0000FF00uL) +#define INTC_ICDIPTR84_LINI1_INT_M (0x00FF0000uL) + +#define INTC_ICDIPTR86_ERI0 (0xFF000000uL) + +#define INTC_ICDIPTR87_RXI0 (0x000000FFuL) +#define INTC_ICDIPTR87_TXI0 (0x0000FF00uL) +#define INTC_ICDIPTR87_TEI0 (0x00FF0000uL) +#define INTC_ICDIPTR87_ERI1 (0xFF000000uL) + +#define INTC_ICDIPTR88_RXI1 (0x000000FFuL) +#define INTC_ICDIPTR88_TXI1 (0x0000FF00uL) +#define INTC_ICDIPTR88_TEI1 (0x00FF0000uL) +#define INTC_ICDIPTR88_AVBI_DATA (0xFF000000uL) + +#define INTC_ICDIPTR89_AVBI_ERROR (0x000000FFuL) +#define INTC_ICDIPTR89_AVBI_MANAGE (0x0000FF00uL) +#define INTC_ICDIPTR89_AVBI_MAC (0x00FF0000uL) +#define INTC_ICDIPTR89_ETHERI (0xFF000000uL) + +#define INTC_ICDIPTR91_CEUI (0x000000FFuL) + +#define INTC_ICDIPTR95_H2XMLB_ERRINT (0x0000FF00uL) +#define INTC_ICDIPTR95_H2XIC1_ERRINT (0x00FF0000uL) +#define INTC_ICDIPTR95_X2HPERI1_ERRINT (0xFF000000uL) + +#define INTC_ICDIPTR96_X2HPERI2_ERRINT (0x000000FFuL) +#define INTC_ICDIPTR96_X2HPERI34_ERRINT (0x0000FF00uL) +#define INTC_ICDIPTR96_X2HPERI5_ERRINT (0x00FF0000uL) +#define INTC_ICDIPTR96_X2HPERI67_ERRINT (0xFF000000uL) + +#define INTC_ICDIPTR97_X2HDBGR_ERRINT (0x000000FFuL) +#define INTC_ICDIPTR97_X2HBSC_ERRINT (0x0000FF00uL) +#define INTC_ICDIPTR97_X2HSPI1_ERRINT (0x00FF0000uL) +#define INTC_ICDIPTR97_X2HSPI2_ERRINT (0xFF000000uL) + +#define INTC_ICDIPTR98_PRRI (0x000000FFuL) +#define INTC_ICDIPTR98_IFEI0 (0x0000FF00uL) +#define INTC_ICDIPTR98_OFFI0 (0x00FF0000uL) +#define INTC_ICDIPTR98_PFVEI0 (0xFF000000uL) + +#define INTC_ICDIPTR99_IFEI1 (0x000000FFuL) +#define INTC_ICDIPTR99_OFFI1 (0x0000FF00uL) +#define INTC_ICDIPTR99_PFVEI1 (0x00FF0000uL) + +#define INTC_ICDIPTR104_TINT0 (0x000000FFuL) +#define INTC_ICDIPTR104_TINT1 (0x0000FF00uL) +#define INTC_ICDIPTR104_TINT2 (0x00FF0000uL) +#define INTC_ICDIPTR104_TINT3 (0xFF000000uL) + +#define INTC_ICDIPTR105_TINT4 (0x000000FFuL) +#define INTC_ICDIPTR105_TINT5 (0x0000FF00uL) +#define INTC_ICDIPTR105_TINT6 (0x00FF0000uL) +#define INTC_ICDIPTR105_TINT7 (0xFF000000uL) + +#define INTC_ICDIPTR106_TINT8 (0x000000FFuL) +#define INTC_ICDIPTR106_TINT9 (0x0000FF00uL) +#define INTC_ICDIPTR106_TINT10 (0x00FF0000uL) +#define INTC_ICDIPTR106_TINT11 (0xFF000000uL) + +#define INTC_ICDIPTR107_TINT12 (0x000000FFuL) +#define INTC_ICDIPTR107_TINT13 (0x0000FF00uL) +#define INTC_ICDIPTR107_TINT14 (0x00FF0000uL) +#define INTC_ICDIPTR107_TINT15 (0xFF000000uL) + +#define INTC_ICDIPTR108_TINT16 (0x000000FFuL) +#define INTC_ICDIPTR108_TINT17 (0x0000FF00uL) +#define INTC_ICDIPTR108_TINT18 (0x00FF0000uL) +#define INTC_ICDIPTR108_TINT19 (0xFF000000uL) + +#define INTC_ICDIPTR109_TINT20 (0x000000FFuL) +#define INTC_ICDIPTR109_TINT21 (0x0000FF00uL) +#define INTC_ICDIPTR109_TINT22 (0x00FF0000uL) +#define INTC_ICDIPTR109_TINT23 (0xFF000000uL) + +#define INTC_ICDIPTR110_TINT24 (0x000000FFuL) +#define INTC_ICDIPTR110_TINT25 (0x0000FF00uL) +#define INTC_ICDIPTR110_TINT26 (0x00FF0000uL) +#define INTC_ICDIPTR110_TINT27 (0xFF000000uL) + +#define INTC_ICDIPTR111_TINT28 (0x000000FFuL) +#define INTC_ICDIPTR111_TINT29 (0x0000FF00uL) +#define INTC_ICDIPTR111_TINT30 (0x00FF0000uL) +#define INTC_ICDIPTR111_TINT31 (0xFF000000uL) + +#define INTC_ICDIPTR112_TINT32 (0x000000FFuL) +#define INTC_ICDIPTR112_TINT33 (0x0000FF00uL) +#define INTC_ICDIPTR112_TINT34 (0x00FF0000uL) +#define INTC_ICDIPTR112_TINT35 (0xFF000000uL) + +#define INTC_ICDIPTR113_TINT36 (0x000000FFuL) +#define INTC_ICDIPTR113_TINT37 (0x0000FF00uL) +#define INTC_ICDIPTR113_TINT38 (0x00FF0000uL) +#define INTC_ICDIPTR113_TINT39 (0xFF000000uL) + +#define INTC_ICDIPTR114_TINT40 (0x000000FFuL) +#define INTC_ICDIPTR114_TINT41 (0x0000FF00uL) +#define INTC_ICDIPTR114_TINT42 (0x00FF0000uL) +#define INTC_ICDIPTR114_TINT43 (0xFF000000uL) + +#define INTC_ICDIPTR115_TINT44 (0x000000FFuL) +#define INTC_ICDIPTR115_TINT45 (0x0000FF00uL) +#define INTC_ICDIPTR115_TINT46 (0x00FF0000uL) +#define INTC_ICDIPTR115_TINT47 (0xFF000000uL) + +#define INTC_ICDIPTR116_TINT48 (0x000000FFuL) +#define INTC_ICDIPTR116_TINT49 (0x0000FF00uL) +#define INTC_ICDIPTR116_TINT50 (0x00FF0000uL) +#define INTC_ICDIPTR116_TINT51 (0xFF000000uL) + +#define INTC_ICDIPTR117_TINT52 (0x000000FFuL) +#define INTC_ICDIPTR117_TINT53 (0x0000FF00uL) +#define INTC_ICDIPTR117_TINT54 (0x00FF0000uL) +#define INTC_ICDIPTR117_TINT55 (0xFF000000uL) + +#define INTC_ICDIPTR118_TINT56 (0x000000FFuL) +#define INTC_ICDIPTR118_TINT57 (0x0000FF00uL) +#define INTC_ICDIPTR118_TINT58 (0x00FF0000uL) +#define INTC_ICDIPTR118_TINT59 (0xFF000000uL) + +#define INTC_ICDIPTR119_TINT60 (0x000000FFuL) +#define INTC_ICDIPTR119_TINT61 (0x0000FF00uL) +#define INTC_ICDIPTR119_TINT62 (0x00FF0000uL) +#define INTC_ICDIPTR119_TINT63 (0xFF000000uL) + +#define INTC_ICDIPTR120_TINT64 (0x000000FFuL) +#define INTC_ICDIPTR120_TINT65 (0x0000FF00uL) +#define INTC_ICDIPTR120_TINT66 (0x00FF0000uL) +#define INTC_ICDIPTR120_TINT67 (0xFF000000uL) + +#define INTC_ICDIPTR121_TINT68 (0x000000FFuL) +#define INTC_ICDIPTR121_TINT69 (0x0000FF00uL) +#define INTC_ICDIPTR121_TINT70 (0x00FF0000uL) +#define INTC_ICDIPTR121_TINT71 (0xFF000000uL) + +#define INTC_ICDIPTR122_TINT72 (0x000000FFuL) +#define INTC_ICDIPTR122_TINT73 (0x0000FF00uL) +#define INTC_ICDIPTR122_TINT74 (0x00FF0000uL) +#define INTC_ICDIPTR122_TINT75 (0xFF000000uL) + +#define INTC_ICDIPTR123_TINT76 (0x000000FFuL) +#define INTC_ICDIPTR123_TINT77 (0x0000FF00uL) +#define INTC_ICDIPTR123_TINT78 (0x00FF0000uL) +#define INTC_ICDIPTR123_TINT79 (0xFF000000uL) + +#define INTC_ICDIPTR124_TINT80 (0x000000FFuL) +#define INTC_ICDIPTR124_TINT81 (0x0000FF00uL) +#define INTC_ICDIPTR124_TINT82 (0x00FF0000uL) +#define INTC_ICDIPTR124_TINT83 (0xFF000000uL) + +#define INTC_ICDIPTR125_TINT84 (0x000000FFuL) +#define INTC_ICDIPTR125_TINT85 (0x0000FF00uL) +#define INTC_ICDIPTR125_TINT86 (0x00FF0000uL) +#define INTC_ICDIPTR125_TINT87 (0xFF000000uL) + +#define INTC_ICDIPTR126_TINT88 (0x000000FFuL) +#define INTC_ICDIPTR126_TINT89 (0x0000FF00uL) +#define INTC_ICDIPTR126_TINT90 (0x00FF0000uL) +#define INTC_ICDIPTR126_TINT91 (0xFF000000uL) + +#define INTC_ICDIPTR127_TINT92 (0x000000FFuL) +#define INTC_ICDIPTR127_TINT93 (0x0000FF00uL) +#define INTC_ICDIPTR127_TINT94 (0x00FF0000uL) +#define INTC_ICDIPTR127_TINT95 (0xFF000000uL) + +#define INTC_ICDIPTR128_TINT96 (0x000000FFuL) +#define INTC_ICDIPTR128_TINT97 (0x0000FF00uL) +#define INTC_ICDIPTR128_TINT98 (0x00FF0000uL) +#define INTC_ICDIPTR128_TINT99 (0xFF000000uL) + +#define INTC_ICDIPTR129_TINT100 (0x000000FFuL) +#define INTC_ICDIPTR129_TINT101 (0x0000FF00uL) +#define INTC_ICDIPTR129_TINT102 (0x00FF0000uL) +#define INTC_ICDIPTR129_TINT103 (0xFF000000uL) + +#define INTC_ICDIPTR130_TINT104 (0x000000FFuL) +#define INTC_ICDIPTR130_TINT105 (0x0000FF00uL) +#define INTC_ICDIPTR130_TINT106 (0x00FF0000uL) +#define INTC_ICDIPTR130_TINT107 (0xFF000000uL) + +#define INTC_ICDIPTR131_TINT108 (0x000000FFuL) +#define INTC_ICDIPTR131_TINT109 (0x0000FF00uL) +#define INTC_ICDIPTR131_TINT110 (0x00FF0000uL) +#define INTC_ICDIPTR131_TINT111 (0xFF000000uL) + +#define INTC_ICDIPTR132_TINT112 (0x000000FFuL) +#define INTC_ICDIPTR132_TINT113 (0x0000FF00uL) +#define INTC_ICDIPTR132_TINT114 (0x00FF0000uL) +#define INTC_ICDIPTR132_TINT115 (0xFF000000uL) + +#define INTC_ICDIPTR133_TINT116 (0x000000FFuL) +#define INTC_ICDIPTR133_TINT117 (0x0000FF00uL) +#define INTC_ICDIPTR133_TINT118 (0x00FF0000uL) +#define INTC_ICDIPTR133_TINT119 (0xFF000000uL) + +#define INTC_ICDIPTR134_TINT120 (0x000000FFuL) +#define INTC_ICDIPTR134_TINT121 (0x0000FF00uL) +#define INTC_ICDIPTR134_TINT122 (0x00FF0000uL) +#define INTC_ICDIPTR134_TINT123 (0xFF000000uL) + +#define INTC_ICDIPTR135_TINT124 (0x000000FFuL) +#define INTC_ICDIPTR135_TINT125 (0x0000FF00uL) +#define INTC_ICDIPTR135_TINT126 (0x00FF0000uL) +#define INTC_ICDIPTR135_TINT127 (0xFF000000uL) + +#define INTC_ICDIPTR136_TINT128 (0x000000FFuL) +#define INTC_ICDIPTR136_TINT129 (0x0000FF00uL) +#define INTC_ICDIPTR136_TINT130 (0x00FF0000uL) +#define INTC_ICDIPTR136_TINT131 (0xFF000000uL) + +#define INTC_ICDIPTR137_TINT132 (0x000000FFuL) +#define INTC_ICDIPTR137_TINT133 (0x0000FF00uL) +#define INTC_ICDIPTR137_TINT134 (0x00FF0000uL) +#define INTC_ICDIPTR137_TINT135 (0xFF000000uL) + +#define INTC_ICDIPTR138_TINT136 (0x000000FFuL) +#define INTC_ICDIPTR138_TINT137 (0x0000FF00uL) +#define INTC_ICDIPTR138_TINT138 (0x00FF0000uL) +#define INTC_ICDIPTR138_TINT139 (0xFF000000uL) + +#define INTC_ICDIPTR139_TINT140 (0x000000FFuL) +#define INTC_ICDIPTR139_TINT141 (0x0000FF00uL) +#define INTC_ICDIPTR139_TINT142 (0x00FF0000uL) +#define INTC_ICDIPTR139_TINT143 (0xFF000000uL) + +#define INTC_ICDIPTR140_TINT144 (0x000000FFuL) +#define INTC_ICDIPTR140_TINT145 (0x0000FF00uL) +#define INTC_ICDIPTR140_TINT146 (0x00FF0000uL) +#define INTC_ICDIPTR140_TINT147 (0xFF000000uL) + +#define INTC_ICDIPTR141_TINT148 (0x000000FFuL) +#define INTC_ICDIPTR141_TINT149 (0x0000FF00uL) +#define INTC_ICDIPTR141_TINT150 (0x00FF0000uL) +#define INTC_ICDIPTR141_TINT151 (0xFF000000uL) + +#define INTC_ICDIPTR142_TINT152 (0x000000FFuL) +#define INTC_ICDIPTR142_TINT153 (0x0000FF00uL) +#define INTC_ICDIPTR142_TINT154 (0x00FF0000uL) +#define INTC_ICDIPTR142_TINT155 (0xFF000000uL) + +#define INTC_ICDIPTR143_TINT156 (0x000000FFuL) +#define INTC_ICDIPTR143_TINT157 (0x0000FF00uL) +#define INTC_ICDIPTR143_TINT158 (0x00FF0000uL) +#define INTC_ICDIPTR143_TINT159 (0xFF000000uL) + +#define INTC_ICDIPTR144_TINT160 (0x000000FFuL) +#define INTC_ICDIPTR144_TINT161 (0x0000FF00uL) +#define INTC_ICDIPTR144_TINT162 (0x00FF0000uL) +#define INTC_ICDIPTR144_TINT163 (0xFF000000uL) + +#define INTC_ICDIPTR145_TINT164 (0x000000FFuL) +#define INTC_ICDIPTR145_TINT165 (0x0000FF00uL) +#define INTC_ICDIPTR145_TINT166 (0x00FF0000uL) +#define INTC_ICDIPTR145_TINT167 (0xFF000000uL) + +#define INTC_ICDIPTR146_TINT168 (0x000000FFuL) +#define INTC_ICDIPTR146_TINT169 (0x0000FF00uL) +#define INTC_ICDIPTR146_TINT170 (0x00FF0000uL) + +#define INTC_ICDICFR0_SW0_0 (0x00000001uL) +#define INTC_ICDICFR0_SW0_1 (0x00000002uL) +#define INTC_ICDICFR0_SW1_0 (0x00000004uL) +#define INTC_ICDICFR0_SW1_1 (0x00000008uL) +#define INTC_ICDICFR0_SW2_0 (0x00000010uL) +#define INTC_ICDICFR0_SW2_1 (0x00000020uL) +#define INTC_ICDICFR0_SW3_0 (0x00000040uL) +#define INTC_ICDICFR0_SW3_1 (0x00000080uL) +#define INTC_ICDICFR0_SW4_0 (0x00000100uL) +#define INTC_ICDICFR0_SW4_1 (0x00000200uL) +#define INTC_ICDICFR0_SW5_0 (0x00000400uL) +#define INTC_ICDICFR0_SW5_1 (0x00000800uL) +#define INTC_ICDICFR0_SW6_0 (0x00001000uL) +#define INTC_ICDICFR0_SW6_1 (0x00002000uL) +#define INTC_ICDICFR0_SW7_0 (0x00004000uL) +#define INTC_ICDICFR0_SW7_1 (0x00008000uL) +#define INTC_ICDICFR0_SW8_0 (0x00010000uL) +#define INTC_ICDICFR0_SW8_1 (0x00020000uL) +#define INTC_ICDICFR0_SW9_0 (0x00040000uL) +#define INTC_ICDICFR0_SW9_1 (0x00080000uL) +#define INTC_ICDICFR0_SW10_0 (0x00100000uL) +#define INTC_ICDICFR0_SW10_1 (0x00200000uL) +#define INTC_ICDICFR0_SW11_0 (0x00400000uL) +#define INTC_ICDICFR0_SW11_1 (0x00800000uL) +#define INTC_ICDICFR0_SW12_0 (0x01000000uL) +#define INTC_ICDICFR0_SW12_1 (0x02000000uL) +#define INTC_ICDICFR0_SW13_0 (0x04000000uL) +#define INTC_ICDICFR0_SW13_1 (0x08000000uL) +#define INTC_ICDICFR0_SW14_0 (0x10000000uL) +#define INTC_ICDICFR0_SW14_1 (0x20000000uL) +#define INTC_ICDICFR0_SW15_0 (0x40000000uL) +#define INTC_ICDICFR0_SW15_1 (0x80000000uL) + +#define INTC_ICDICFR1_PMUIRQ0_0 (0x00000001uL) +#define INTC_ICDICFR1_PMUIRQ0_1 (0x00000002uL) +#define INTC_ICDICFR1_COMMRX0_0 (0x00000004uL) +#define INTC_ICDICFR1_COMMRX0_1 (0x00000008uL) +#define INTC_ICDICFR1_COMMTX0_0 (0x00000010uL) +#define INTC_ICDICFR1_COMMTX0_1 (0x00000020uL) +#define INTC_ICDICFR1_CTIIRQ0_0 (0x00000040uL) +#define INTC_ICDICFR1_CTIIRQ0_1 (0x00000080uL) + +#define INTC_ICDICFR2_IRQ0_0 (0x00000001uL) +#define INTC_ICDICFR2_IRQ0_1 (0x00000002uL) +#define INTC_ICDICFR2_IRQ1_0 (0x00000004uL) +#define INTC_ICDICFR2_IRQ1_1 (0x00000008uL) +#define INTC_ICDICFR2_IRQ2_0 (0x00000010uL) +#define INTC_ICDICFR2_IRQ2_1 (0x00000020uL) +#define INTC_ICDICFR2_IRQ3_0 (0x00000040uL) +#define INTC_ICDICFR2_IRQ3_1 (0x00000080uL) +#define INTC_ICDICFR2_IRQ4_0 (0x00000100uL) +#define INTC_ICDICFR2_IRQ4_1 (0x00000200uL) +#define INTC_ICDICFR2_IRQ5_0 (0x00000400uL) +#define INTC_ICDICFR2_IRQ5_1 (0x00000800uL) +#define INTC_ICDICFR2_IRQ6_0 (0x00001000uL) +#define INTC_ICDICFR2_IRQ6_1 (0x00002000uL) +#define INTC_ICDICFR2_IRQ7_0 (0x00004000uL) +#define INTC_ICDICFR2_IRQ7_1 (0x00008000uL) +#define INTC_ICDICFR2_PL310ERR_0 (0x00010000uL) +#define INTC_ICDICFR2_PL310ERR_1 (0x00020000uL) +#define INTC_ICDICFR2_DMAINT0_0 (0x00040000uL) +#define INTC_ICDICFR2_DMAINT0_1 (0x00080000uL) +#define INTC_ICDICFR2_DMAINT1_0 (0x00100000uL) +#define INTC_ICDICFR2_DMAINT1_1 (0x00200000uL) +#define INTC_ICDICFR2_DMAINT2_0 (0x00400000uL) +#define INTC_ICDICFR2_DMAINT2_1 (0x00800000uL) +#define INTC_ICDICFR2_DMAINT3_0 (0x01000000uL) +#define INTC_ICDICFR2_DMAINT3_1 (0x02000000uL) +#define INTC_ICDICFR2_DMAINT4_0 (0x04000000uL) +#define INTC_ICDICFR2_DMAINT4_1 (0x08000000uL) +#define INTC_ICDICFR2_DMAINT5_0 (0x10000000uL) +#define INTC_ICDICFR2_DMAINT5_1 (0x20000000uL) +#define INTC_ICDICFR2_DMAINT6_0 (0x40000000uL) +#define INTC_ICDICFR2_DMAINT6_1 (0x80000000uL) + +#define INTC_ICDICFR3_DMAINT7_0 (0x00000001uL) +#define INTC_ICDICFR3_DMAINT7_1 (0x00000002uL) +#define INTC_ICDICFR3_DMAINT8_0 (0x00000004uL) +#define INTC_ICDICFR3_DMAINT8_1 (0x00000008uL) +#define INTC_ICDICFR3_DMAINT9_0 (0x00000010uL) +#define INTC_ICDICFR3_DMAINT9_1 (0x00000020uL) +#define INTC_ICDICFR3_DMAINT10_0 (0x00000040uL) +#define INTC_ICDICFR3_DMAINT10_1 (0x00000080uL) +#define INTC_ICDICFR3_DMAINT11_0 (0x00000100uL) +#define INTC_ICDICFR3_DMAINT11_1 (0x00000200uL) +#define INTC_ICDICFR3_DMAINT12_0 (0x00000400uL) +#define INTC_ICDICFR3_DMAINT12_1 (0x00000800uL) +#define INTC_ICDICFR3_DMAINT13_0 (0x00001000uL) +#define INTC_ICDICFR3_DMAINT13_1 (0x00002000uL) +#define INTC_ICDICFR3_DMAINT14_0 (0x00004000uL) +#define INTC_ICDICFR3_DMAINT14_1 (0x00008000uL) +#define INTC_ICDICFR3_DMAINT15_0 (0x00010000uL) +#define INTC_ICDICFR3_DMAINT15_1 (0x00020000uL) +#define INTC_ICDICFR3_DMAERR_0 (0x00040000uL) +#define INTC_ICDICFR3_DMAERR_1 (0x00080000uL) + +#define INTC_ICDICFR4_USBI0_0 (0x00040000uL) +#define INTC_ICDICFR4_USBI0_1 (0x00080000uL) +#define INTC_ICDICFR4_USBI1_0 (0x00100000uL) +#define INTC_ICDICFR4_USBI1_1 (0x00200000uL) +#define INTC_ICDICFR4_S0_VI_VSYNC0_0 (0x00400000uL) +#define INTC_ICDICFR4_S0_VI_VSYNC0_1 (0x00800000uL) +#define INTC_ICDICFR4_S0_LO_VSYNC0_0 (0x01000000uL) +#define INTC_ICDICFR4_S0_LO_VSYNC0_1 (0x02000000uL) +#define INTC_ICDICFR4_S0_VSYNCERR0_0 (0x04000000uL) +#define INTC_ICDICFR4_S0_VSYNCERR0_1 (0x08000000uL) +#define INTC_ICDICFR4_GR3_VLINE0_0 (0x10000000uL) +#define INTC_ICDICFR4_GR3_VLINE0_1 (0x20000000uL) +#define INTC_ICDICFR4_S0_VFIELD0_0 (0x40000000uL) +#define INTC_ICDICFR4_S0_VFIELD0_1 (0x80000000uL) + +#define INTC_ICDICFR5_IV1_VBUFERR0_0 (0x00000001uL) +#define INTC_ICDICFR5_IV1_VBUFERR0_1 (0x00000002uL) +#define INTC_ICDICFR5_IV3_VBUFERR0_0 (0x00000004uL) +#define INTC_ICDICFR5_IV3_VBUFERR0_1 (0x00000008uL) +#define INTC_ICDICFR5_IV5_VBUFERR0_0 (0x00000010uL) +#define INTC_ICDICFR5_IV5_VBUFERR0_1 (0x00000020uL) +#define INTC_ICDICFR5_IV6_VBUFERR0_0 (0x00000040uL) +#define INTC_ICDICFR5_IV6_VBUFERR0_1 (0x00000080uL) +#define INTC_ICDICFR5_S0_WLINE0_0 (0x00000100uL) +#define INTC_ICDICFR5_S0_WLINE0_1 (0x00000200uL) +#define INTC_ICDICFR5_S1_VI_VSYNC0_0 (0x00000400uL) +#define INTC_ICDICFR5_S1_VI_VSYNC0_1 (0x00000800uL) +#define INTC_ICDICFR5_S1_LO_VSYNC0_0 (0x00001000uL) +#define INTC_ICDICFR5_S1_LO_VSYNC0_1 (0x00002000uL) +#define INTC_ICDICFR5_S1_VSYNCERR0_0 (0x00004000uL) +#define INTC_ICDICFR5_S1_VSYNCERR0_1 (0x00008000uL) +#define INTC_ICDICFR5_S1_VFIELD0_0 (0x00010000uL) +#define INTC_ICDICFR5_S1_VFIELD0_1 (0x00020000uL) +#define INTC_ICDICFR5_IV2_VBUFERR0_0 (0x00040000uL) +#define INTC_ICDICFR5_IV2_VBUFERR0_1 (0x00080000uL) +#define INTC_ICDICFR5_IV4_VBUFERR0_0 (0x00100000uL) +#define INTC_ICDICFR5_IV4_VBUFERR0_1 (0x00200000uL) +#define INTC_ICDICFR5_S1_WLINE0_0 (0x00400000uL) +#define INTC_ICDICFR5_S1_WLINE0_1 (0x00800000uL) +#define INTC_ICDICFR5_OIR_VI_VSYNC0_0 (0x01000000uL) +#define INTC_ICDICFR5_OIR_VI_VSYNC0_1 (0x02000000uL) +#define INTC_ICDICFR5_OIR_LO_VSYNC0_0 (0x04000000uL) +#define INTC_ICDICFR5_OIR_LO_VSYNC0_1 (0x08000000uL) +#define INTC_ICDICFR5_OIR_VSYNCERR0_0 (0x10000000uL) +#define INTC_ICDICFR5_OIR_VSYNCERR0_1 (0x20000000uL) +#define INTC_ICDICFR5_OIR_VFIELD0_0 (0x40000000uL) +#define INTC_ICDICFR5_OIR_VFIELD0_1 (0x80000000uL) + +#define INTC_ICDICFR6_IV7_VBUFERR0_0 (0x00000001uL) +#define INTC_ICDICFR6_IV7_VBUFERR0_1 (0x00000002uL) +#define INTC_ICDICFR6_IV8_VBUFERR0_0 (0x00000004uL) +#define INTC_ICDICFR6_IV8_VBUFERR0_1 (0x00000008uL) +#define INTC_ICDICFR6_S0_VI_VSYNC1_0 (0x00000040uL) +#define INTC_ICDICFR6_S0_VI_VSYNC1_1 (0x00000080uL) +#define INTC_ICDICFR6_S0_LO_VSYNC1_0 (0x00000100uL) +#define INTC_ICDICFR6_S0_LO_VSYNC1_1 (0x00000200uL) +#define INTC_ICDICFR6_S0_VSYNCERR1_0 (0x00000400uL) +#define INTC_ICDICFR6_S0_VSYNCERR1_1 (0x00000800uL) +#define INTC_ICDICFR6_GR3_VLINE1_0 (0x00001000uL) +#define INTC_ICDICFR6_GR3_VLINE1_1 (0x00002000uL) +#define INTC_ICDICFR6_S0_VFIELD1_0 (0x00004000uL) +#define INTC_ICDICFR6_S0_VFIELD1_1 (0x00008000uL) +#define INTC_ICDICFR6_IV1_VBUFERR1_0 (0x00010000uL) +#define INTC_ICDICFR6_IV1_VBUFERR1_1 (0x00020000uL) +#define INTC_ICDICFR6_IV3_VBUFERR1_0 (0x00040000uL) +#define INTC_ICDICFR6_IV3_VBUFERR1_1 (0x00080000uL) +#define INTC_ICDICFR6_IV5_VBUFERR1_0 (0x00100000uL) +#define INTC_ICDICFR6_IV5_VBUFERR1_1 (0x00200000uL) +#define INTC_ICDICFR6_IV6_VBUFERR1_0 (0x00400000uL) +#define INTC_ICDICFR6_IV6_VBUFERR1_1 (0x00800000uL) +#define INTC_ICDICFR6_S0_WLINE1_0 (0x01000000uL) +#define INTC_ICDICFR6_S0_WLINE1_1 (0x02000000uL) +#define INTC_ICDICFR6_S1_VI_VSYNC1_0 (0x04000000uL) +#define INTC_ICDICFR6_S1_VI_VSYNC1_1 (0x08000000uL) +#define INTC_ICDICFR6_S1_LO_VSYNC1_0 (0x10000000uL) +#define INTC_ICDICFR6_S1_LO_VSYNC1_1 (0x20000000uL) +#define INTC_ICDICFR6_S1_VSYNCERR1_0 (0x40000000uL) +#define INTC_ICDICFR6_S1_VSYNCERR1_1 (0x80000000uL) + +#define INTC_ICDICFR7_S1_VFIELD1_0 (0x00000001uL) +#define INTC_ICDICFR7_S1_VFIELD1_1 (0x00000002uL) +#define INTC_ICDICFR7_IV2_VBUFERR1_0 (0x00000004uL) +#define INTC_ICDICFR7_IV2_VBUFERR1_1 (0x00000008uL) +#define INTC_ICDICFR7_IV4_VBUFERR1_0 (0x00000010uL) +#define INTC_ICDICFR7_IV4_VBUFERR1_1 (0x00000020uL) +#define INTC_ICDICFR7_S1_WLINE1_0 (0x00000040uL) +#define INTC_ICDICFR7_S1_WLINE1_1 (0x00000080uL) +#define INTC_ICDICFR7_OIR_VI_VSYNC1_0 (0x00000100uL) +#define INTC_ICDICFR7_OIR_VI_VSYNC1_1 (0x00000200uL) +#define INTC_ICDICFR7_OIR_LO_VSYNC1_0 (0x00000400uL) +#define INTC_ICDICFR7_OIR_LO_VSYNC1_1 (0x00000800uL) +#define INTC_ICDICFR7_OIR_VLINE1_0 (0x00001000uL) +#define INTC_ICDICFR7_OIR_VLINE1_1 (0x00002000uL) +#define INTC_ICDICFR7_OIR_VFIELD1_0 (0x00004000uL) +#define INTC_ICDICFR7_OIR_VFIELD1_1 (0x00008000uL) +#define INTC_ICDICFR7_IV7_VBUFERR1_0 (0x00010000uL) +#define INTC_ICDICFR7_IV7_VBUFERR1_1 (0x00020000uL) +#define INTC_ICDICFR7_IV8_VBUFERR1_0 (0x00040000uL) +#define INTC_ICDICFR7_IV8_VBUFERR1_1 (0x00080000uL) +#define INTC_ICDICFR7_IMRDI_0 (0x00400000uL) +#define INTC_ICDICFR7_IMRDI_1 (0x00800000uL) +#define INTC_ICDICFR7_IMR2I0_0 (0x01000000uL) +#define INTC_ICDICFR7_IMR2I0_1 (0x02000000uL) +#define INTC_ICDICFR7_IMR2I1_0 (0x04000000uL) +#define INTC_ICDICFR7_IMR2I1_1 (0x08000000uL) +#define INTC_ICDICFR7_JEDI_0 (0x10000000uL) +#define INTC_ICDICFR7_JEDI_1 (0x20000000uL) +#define INTC_ICDICFR7_JDTI_0 (0x40000000uL) +#define INTC_ICDICFR7_JDTI_1 (0x80000000uL) + +#define INTC_ICDICFR8_CMP0_0 (0x00000001uL) +#define INTC_ICDICFR8_CMP0_1 (0x00000002uL) +#define INTC_ICDICFR8_CMP1_0 (0x00000004uL) +#define INTC_ICDICFR8_CMP1_1 (0x00000008uL) +#define INTC_ICDICFR8_INT0_0 (0x00000010uL) +#define INTC_ICDICFR8_INT0_1 (0x00000020uL) +#define INTC_ICDICFR8_INT1_0 (0x00000040uL) +#define INTC_ICDICFR8_INT1_1 (0x00000080uL) +#define INTC_ICDICFR8_INT2_0 (0x00000100uL) +#define INTC_ICDICFR8_INT2_1 (0x00000200uL) +#define INTC_ICDICFR8_INT3_0 (0x00000400uL) +#define INTC_ICDICFR8_INT3_1 (0x00000800uL) +#define INTC_ICDICFR8_OSTM0TINT_0 (0x00001000uL) +#define INTC_ICDICFR8_OSTM0TINT_1 (0x00002000uL) +#define INTC_ICDICFR8_OSTM1TINT_0 (0x00004000uL) +#define INTC_ICDICFR8_OSTM1TINT_1 (0x00008000uL) +#define INTC_ICDICFR8_CMI_0 (0x00010000uL) +#define INTC_ICDICFR8_CMI_1 (0x00020000uL) +#define INTC_ICDICFR8_WTOUT_0 (0x00040000uL) +#define INTC_ICDICFR8_WTOUT_1 (0x00080000uL) +#define INTC_ICDICFR8_ITI_0 (0x00100000uL) +#define INTC_ICDICFR8_ITI_1 (0x00200000uL) +#define INTC_ICDICFR8_TGI0A_0 (0x00400000uL) +#define INTC_ICDICFR8_TGI0A_1 (0x00800000uL) +#define INTC_ICDICFR8_TGI0B_0 (0x01000000uL) +#define INTC_ICDICFR8_TGI0B_1 (0x02000000uL) +#define INTC_ICDICFR8_TGI0C_0 (0x04000000uL) +#define INTC_ICDICFR8_TGI0C_1 (0x08000000uL) +#define INTC_ICDICFR8_TGI0D_0 (0x10000000uL) +#define INTC_ICDICFR8_TGI0D_1 (0x20000000uL) +#define INTC_ICDICFR8_TGI0V_0 (0x40000000uL) +#define INTC_ICDICFR8_TGI0V_1 (0x80000000uL) + +#define INTC_ICDICFR9_TGI0E_0 (0x00000001uL) +#define INTC_ICDICFR9_TGI0E_1 (0x00000002uL) +#define INTC_ICDICFR9_TGI0F_0 (0x00000004uL) +#define INTC_ICDICFR9_TGI0F_1 (0x00000008uL) +#define INTC_ICDICFR9_TGI1A_0 (0x00000010uL) +#define INTC_ICDICFR9_TGI1A_1 (0x00000020uL) +#define INTC_ICDICFR9_TGI1B_0 (0x00000040uL) +#define INTC_ICDICFR9_TGI1B_1 (0x00000080uL) +#define INTC_ICDICFR9_TGI1V_0 (0x00000100uL) +#define INTC_ICDICFR9_TGI1V_1 (0x00000200uL) +#define INTC_ICDICFR9_TGI1U_0 (0x00000400uL) +#define INTC_ICDICFR9_TGI1U_1 (0x00000800uL) +#define INTC_ICDICFR9_TGI2A_0 (0x00001000uL) +#define INTC_ICDICFR9_TGI2A_1 (0x00002000uL) +#define INTC_ICDICFR9_TGI2B_0 (0x00004000uL) +#define INTC_ICDICFR9_TGI2B_1 (0x00008000uL) +#define INTC_ICDICFR9_TGI2V_0 (0x00010000uL) +#define INTC_ICDICFR9_TGI2V_1 (0x00020000uL) +#define INTC_ICDICFR9_TGI2U_0 (0x00040000uL) +#define INTC_ICDICFR9_TGI2U_1 (0x00080000uL) +#define INTC_ICDICFR9_TGI3A_0 (0x00100000uL) +#define INTC_ICDICFR9_TGI3A_1 (0x00200000uL) +#define INTC_ICDICFR9_TGI3B_0 (0x00400000uL) +#define INTC_ICDICFR9_TGI3B_1 (0x00800000uL) +#define INTC_ICDICFR9_TGI3C_0 (0x01000000uL) +#define INTC_ICDICFR9_TGI3C_1 (0x02000000uL) +#define INTC_ICDICFR9_TGI3D_0 (0x04000000uL) +#define INTC_ICDICFR9_TGI3D_1 (0x08000000uL) +#define INTC_ICDICFR9_TGI3V_0 (0x10000000uL) +#define INTC_ICDICFR9_TGI3V_1 (0x20000000uL) +#define INTC_ICDICFR9_TGI4A_0 (0x40000000uL) +#define INTC_ICDICFR9_TGI4A_1 (0x80000000uL) + +#define INTC_ICDICFR10_TGI4B_0 (0x00000001uL) +#define INTC_ICDICFR10_TGI4B_1 (0x00000002uL) +#define INTC_ICDICFR10_TGI4C_0 (0x00000004uL) +#define INTC_ICDICFR10_TGI4C_1 (0x00000008uL) +#define INTC_ICDICFR10_TGI4D_0 (0x00000010uL) +#define INTC_ICDICFR10_TGI4D_1 (0x00000020uL) +#define INTC_ICDICFR10_TGI4V_0 (0x00000040uL) +#define INTC_ICDICFR10_TGI4V_1 (0x00000080uL) +#define INTC_ICDICFR10_CMI1_0 (0x00000100uL) +#define INTC_ICDICFR10_CMI1_1 (0x00000200uL) +#define INTC_ICDICFR10_CMI2_0 (0x00000400uL) +#define INTC_ICDICFR10_CMI2_1 (0x00000800uL) +#define INTC_ICDICFR10_SGDEI0_0 (0x00001000uL) +#define INTC_ICDICFR10_SGDEI0_1 (0x00002000uL) +#define INTC_ICDICFR10_SGDEI1_0 (0x00004000uL) +#define INTC_ICDICFR10_SGDEI1_1 (0x00008000uL) +#define INTC_ICDICFR10_SGDEI2_0 (0x00010000uL) +#define INTC_ICDICFR10_SGDEI2_1 (0x00020000uL) +#define INTC_ICDICFR10_SGDEI3_0 (0x00040000uL) +#define INTC_ICDICFR10_SGDEI3_1 (0x00080000uL) +#define INTC_ICDICFR10_ADI_0 (0x00100000uL) +#define INTC_ICDICFR10_ADI_1 (0x00200000uL) +#define INTC_ICDICFR10_LMTI_0 (0x00400000uL) +#define INTC_ICDICFR10_LMTI_1 (0x00800000uL) +#define INTC_ICDICFR10_SSII0_0 (0x01000000uL) +#define INTC_ICDICFR10_SSII0_1 (0x02000000uL) +#define INTC_ICDICFR10_SSIRXI0_0 (0x04000000uL) +#define INTC_ICDICFR10_SSIRXI0_1 (0x08000000uL) +#define INTC_ICDICFR10_SSITXI0_0 (0x10000000uL) +#define INTC_ICDICFR10_SSITXI0_1 (0x20000000uL) +#define INTC_ICDICFR10_SSII1_0 (0x40000000uL) +#define INTC_ICDICFR10_SSII1_1 (0x80000000uL) + +#define INTC_ICDICFR11_SSIRXI1_0 (0x00000001uL) +#define INTC_ICDICFR11_SSIRXI1_1 (0x00000002uL) +#define INTC_ICDICFR11_SSITXI1_0 (0x00000004uL) +#define INTC_ICDICFR11_SSITXI1_1 (0x00000008uL) +#define INTC_ICDICFR11_SSII2_0 (0x00000010uL) +#define INTC_ICDICFR11_SSII2_1 (0x00000020uL) +#define INTC_ICDICFR11_SSIRTI2_0 (0x00000040uL) +#define INTC_ICDICFR11_SSIRTI2_1 (0x00000080uL) +#define INTC_ICDICFR11_SSII3_0 (0x00000100uL) +#define INTC_ICDICFR11_SSII3_1 (0x00000200uL) +#define INTC_ICDICFR11_SSIRXI3_0 (0x00000400uL) +#define INTC_ICDICFR11_SSIRXI3_1 (0x00000800uL) +#define INTC_ICDICFR11_SSITXI3_0 (0x00001000uL) +#define INTC_ICDICFR11_SSITXI3_1 (0x00002000uL) +#define INTC_ICDICFR11_SSII4_0 (0x00004000uL) +#define INTC_ICDICFR11_SSII4_1 (0x00008000uL) +#define INTC_ICDICFR11_SSIRTI4_0 (0x00010000uL) +#define INTC_ICDICFR11_SSIRTI4_1 (0x00020000uL) +#define INTC_ICDICFR11_SSII5_0 (0x00040000uL) +#define INTC_ICDICFR11_SSII5_1 (0x00080000uL) +#define INTC_ICDICFR11_SSIRXI5_0 (0x00100000uL) +#define INTC_ICDICFR11_SSIRXI5_1 (0x00200000uL) +#define INTC_ICDICFR11_SSITXI5_0 (0x00400000uL) +#define INTC_ICDICFR11_SSITXI5_1 (0x00800000uL) +#define INTC_ICDICFR11_SPDIFI_0 (0x01000000uL) +#define INTC_ICDICFR11_SPDIFI_1 (0x02000000uL) +#define INTC_ICDICFR11_INTIICTEI0_0 (0x04000000uL) +#define INTC_ICDICFR11_INTIICTEI0_1 (0x08000000uL) +#define INTC_ICDICFR11_INTIICRI0_0 (0x10000000uL) +#define INTC_ICDICFR11_INTIICRI0_1 (0x20000000uL) +#define INTC_ICDICFR11_INTIICTI0_0 (0x40000000uL) +#define INTC_ICDICFR11_INTIICTI0_1 (0x80000000uL) + +#define INTC_ICDICFR12_INTIICSPI0_0 (0x00000001uL) +#define INTC_ICDICFR12_INTIICSPI0_1 (0x00000002uL) +#define INTC_ICDICFR12_INTIICSTI0_0 (0x00000004uL) +#define INTC_ICDICFR12_INTIICSTI0_1 (0x00000008uL) +#define INTC_ICDICFR12_INTIICNAKI0_0 (0x00000010uL) +#define INTC_ICDICFR12_INTIICNAKI0_1 (0x00000020uL) +#define INTC_ICDICFR12_INTIICALI0_0 (0x00000040uL) +#define INTC_ICDICFR12_INTIICALI0_1 (0x00000080uL) +#define INTC_ICDICFR12_INTIICTMOI0_0 (0x00000100uL) +#define INTC_ICDICFR12_INTIICTMOI0_1 (0x00000200uL) +#define INTC_ICDICFR12_INTIICTEI1_0 (0x00000400uL) +#define INTC_ICDICFR12_INTIICTEI1_1 (0x00000800uL) +#define INTC_ICDICFR12_INTIICRI1_0 (0x00001000uL) +#define INTC_ICDICFR12_INTIICRI1_1 (0x00002000uL) +#define INTC_ICDICFR12_INTIICTI1_0 (0x00004000uL) +#define INTC_ICDICFR12_INTIICTI1_1 (0x00008000uL) +#define INTC_ICDICFR12_INTIICSPI1_0 (0x00010000uL) +#define INTC_ICDICFR12_INTIICSPI1_1 (0x00020000uL) +#define INTC_ICDICFR12_INTIICSTI1_0 (0x00040000uL) +#define INTC_ICDICFR12_INTIICSTI1_1 (0x00080000uL) +#define INTC_ICDICFR12_INTIICNAKI1_0 (0x00100000uL) +#define INTC_ICDICFR12_INTIICNAKI1_1 (0x00200000uL) +#define INTC_ICDICFR12_INTIICALI1_0 (0x00400000uL) +#define INTC_ICDICFR12_INTIICALI1_1 (0x00800000uL) +#define INTC_ICDICFR12_INTIICTMOI1_0 (0x01000000uL) +#define INTC_ICDICFR12_INTIICTMOI1_1 (0x02000000uL) +#define INTC_ICDICFR12_INTIICTEI2_0 (0x04000000uL) +#define INTC_ICDICFR12_INTIICTEI2_1 (0x08000000uL) +#define INTC_ICDICFR12_INTIICRI2_0 (0x10000000uL) +#define INTC_ICDICFR12_INTIICRI2_1 (0x20000000uL) +#define INTC_ICDICFR12_INTIICTI2_0 (0x40000000uL) +#define INTC_ICDICFR12_INTIICTI2_1 (0x80000000uL) + +#define INTC_ICDICFR13_INTIICSPI2_0 (0x00000001uL) +#define INTC_ICDICFR13_INTIICSPI2_1 (0x00000002uL) +#define INTC_ICDICFR13_INTIICSTI2_0 (0x00000004uL) +#define INTC_ICDICFR13_INTIICSTI2_1 (0x00000008uL) +#define INTC_ICDICFR13_INTIICNAKI2_0 (0x00000010uL) +#define INTC_ICDICFR13_INTIICNAKI2_1 (0x00000020uL) +#define INTC_ICDICFR13_INTIICALI2_0 (0x00000040uL) +#define INTC_ICDICFR13_INTIICALI2_1 (0x00000080uL) +#define INTC_ICDICFR13_INTIICTMOI2_0 (0x00000100uL) +#define INTC_ICDICFR13_INTIICTMOI2_1 (0x00000200uL) +#define INTC_ICDICFR13_INTIICTEI3_0 (0x00000400uL) +#define INTC_ICDICFR13_INTIICTEI3_1 (0x00000800uL) +#define INTC_ICDICFR13_INTIICRI3_0 (0x00001000uL) +#define INTC_ICDICFR13_INTIICRI3_1 (0x00002000uL) +#define INTC_ICDICFR13_INTIICTI3_0 (0x00004000uL) +#define INTC_ICDICFR13_INTIICTI3_1 (0x00008000uL) +#define INTC_ICDICFR13_INTIICSPI3_0 (0x00010000uL) +#define INTC_ICDICFR13_INTIICSPI3_1 (0x00020000uL) +#define INTC_ICDICFR13_INTIICSTI3_0 (0x00040000uL) +#define INTC_ICDICFR13_INTIICSTI3_1 (0x00080000uL) +#define INTC_ICDICFR13_INTIICNAKI3_0 (0x00100000uL) +#define INTC_ICDICFR13_INTIICNAKI3_1 (0x00200000uL) +#define INTC_ICDICFR13_INTIICALI3_0 (0x00400000uL) +#define INTC_ICDICFR13_INTIICALI3_1 (0x00800000uL) +#define INTC_ICDICFR13_INTIICTMOI3_0 (0x01000000uL) +#define INTC_ICDICFR13_INTIICTMOI3_1 (0x02000000uL) +#define INTC_ICDICFR13_BRI0_0 (0x04000000uL) +#define INTC_ICDICFR13_BRI0_1 (0x08000000uL) +#define INTC_ICDICFR13_ERI0_0 (0x10000000uL) +#define INTC_ICDICFR13_ERI0_1 (0x20000000uL) +#define INTC_ICDICFR13_RXI0_0 (0x40000000uL) +#define INTC_ICDICFR13_RXI0_1 (0x80000000uL) + +#define INTC_ICDICFR14_TXI0_0 (0x00000001uL) +#define INTC_ICDICFR14_TXI0_1 (0x00000002uL) +#define INTC_ICDICFR14_BRI1_0 (0x00000004uL) +#define INTC_ICDICFR14_BRI1_1 (0x00000008uL) +#define INTC_ICDICFR14_ERI1_0 (0x00000010uL) +#define INTC_ICDICFR14_ERI1_1 (0x00000020uL) +#define INTC_ICDICFR14_RXI1_0 (0x00000040uL) +#define INTC_ICDICFR14_RXI1_1 (0x00000080uL) +#define INTC_ICDICFR14_TXI1_0 (0x00000100uL) +#define INTC_ICDICFR14_TXI1_1 (0x00000200uL) +#define INTC_ICDICFR14_BRI2_0 (0x00000400uL) +#define INTC_ICDICFR14_BRI2_1 (0x00000800uL) +#define INTC_ICDICFR14_ERI2_0 (0x00001000uL) +#define INTC_ICDICFR14_ERI2_1 (0x00002000uL) +#define INTC_ICDICFR14_RXI2_0 (0x00004000uL) +#define INTC_ICDICFR14_RXI2_1 (0x00008000uL) +#define INTC_ICDICFR14_TXI2_0 (0x00010000uL) +#define INTC_ICDICFR14_TXI2_1 (0x00020000uL) +#define INTC_ICDICFR14_BRI3_0 (0x00040000uL) +#define INTC_ICDICFR14_BRI3_1 (0x00080000uL) +#define INTC_ICDICFR14_ERI3_0 (0x00100000uL) +#define INTC_ICDICFR14_ERI3_1 (0x00200000uL) +#define INTC_ICDICFR14_RXI3_0 (0x00400000uL) +#define INTC_ICDICFR14_RXI3_1 (0x00800000uL) +#define INTC_ICDICFR14_TXI3_0 (0x01000000uL) +#define INTC_ICDICFR14_TXI3_1 (0x02000000uL) +#define INTC_ICDICFR14_BRI4_0 (0x04000000uL) +#define INTC_ICDICFR14_BRI4_1 (0x08000000uL) +#define INTC_ICDICFR14_ERI4_0 (0x10000000uL) +#define INTC_ICDICFR14_ERI4_1 (0x20000000uL) +#define INTC_ICDICFR14_RXI4_0 (0x40000000uL) +#define INTC_ICDICFR14_RXI4_1 (0x80000000uL) + +#define INTC_ICDICFR15_TXI4_0 (0x00000001uL) +#define INTC_ICDICFR15_TXI4_1 (0x00000002uL) +#define INTC_ICDICFR15_BRI5_0 (0x00000004uL) +#define INTC_ICDICFR15_BRI5_1 (0x00000008uL) +#define INTC_ICDICFR15_ERI5_0 (0x00000010uL) +#define INTC_ICDICFR15_ERI5_1 (0x00000020uL) +#define INTC_ICDICFR15_RXI5_0 (0x00000040uL) +#define INTC_ICDICFR15_RXI5_1 (0x00000080uL) +#define INTC_ICDICFR15_TXI5_0 (0x00000100uL) +#define INTC_ICDICFR15_TXI5_1 (0x00000200uL) +#define INTC_ICDICFR15_BRI6_0 (0x00000400uL) +#define INTC_ICDICFR15_BRI6_1 (0x00000800uL) +#define INTC_ICDICFR15_ERI6_0 (0x00001000uL) +#define INTC_ICDICFR15_ERI6_1 (0x00002000uL) +#define INTC_ICDICFR15_RXI6_0 (0x00004000uL) +#define INTC_ICDICFR15_RXI6_1 (0x00008000uL) +#define INTC_ICDICFR15_TXI6_0 (0x00010000uL) +#define INTC_ICDICFR15_TXI6_1 (0x00020000uL) +#define INTC_ICDICFR15_BRI7_0 (0x00040000uL) +#define INTC_ICDICFR15_BRI7_1 (0x00080000uL) +#define INTC_ICDICFR15_ERI7_0 (0x00100000uL) +#define INTC_ICDICFR15_ERI7_1 (0x00200000uL) +#define INTC_ICDICFR15_RXI7_0 (0x00400000uL) +#define INTC_ICDICFR15_RXI7_1 (0x00800000uL) +#define INTC_ICDICFR15_TXI7_0 (0x01000000uL) +#define INTC_ICDICFR15_TXI7_1 (0x02000000uL) +#define INTC_ICDICFR15_INTRCANGERR_0 (0x04000000uL) +#define INTC_ICDICFR15_INTRCANGERR_1 (0x08000000uL) +#define INTC_ICDICFR15_INTRCANGRECC_0 (0x10000000uL) +#define INTC_ICDICFR15_INTRCANGRECC_1 (0x20000000uL) +#define INTC_ICDICFR15_INTRCAN0REC_0 (0x40000000uL) +#define INTC_ICDICFR15_INTRCAN0REC_1 (0x80000000uL) + +#define INTC_ICDICFR16_INTRCAN0ERR_0 (0x00000001uL) +#define INTC_ICDICFR16_INTRCAN0ERR_1 (0x00000002uL) +#define INTC_ICDICFR16_INTRCAN0TRX_0 (0x00000004uL) +#define INTC_ICDICFR16_INTRCAN0TRX_1 (0x00000008uL) +#define INTC_ICDICFR16_INTRCAN1REC_0 (0x00000010uL) +#define INTC_ICDICFR16_INTRCAN1REC_1 (0x00000020uL) +#define INTC_ICDICFR16_INTRCAN1ERR_0 (0x00000040uL) +#define INTC_ICDICFR16_INTRCAN1ERR_1 (0x00000080uL) +#define INTC_ICDICFR16_INTRCAN1TRX_0 (0x00000100uL) +#define INTC_ICDICFR16_INTRCAN1TRX_1 (0x00000200uL) +#define INTC_ICDICFR16_INTRCAN2REC_0 (0x00000400uL) +#define INTC_ICDICFR16_INTRCAN2REC_1 (0x00000800uL) +#define INTC_ICDICFR16_INTRCAN2ERR_0 (0x00001000uL) +#define INTC_ICDICFR16_INTRCAN2ERR_1 (0x00002000uL) +#define INTC_ICDICFR16_INTRCAN2TRX_0 (0x00004000uL) +#define INTC_ICDICFR16_INTRCAN2TRX_1 (0x00008000uL) +#define INTC_ICDICFR16_INTRCAN3REC_0 (0x00010000uL) +#define INTC_ICDICFR16_INTRCAN3REC_1 (0x00020000uL) +#define INTC_ICDICFR16_INTRCAN3ERR_0 (0x00040000uL) +#define INTC_ICDICFR16_INTRCAN3ERR_1 (0x00080000uL) +#define INTC_ICDICFR16_INTRCAN3TRX_0 (0x00100000uL) +#define INTC_ICDICFR16_INTRCAN3TRX_1 (0x00200000uL) +#define INTC_ICDICFR16_INTRCAN4REC_0 (0x00400000uL) +#define INTC_ICDICFR16_INTRCAN4REC_1 (0x00800000uL) +#define INTC_ICDICFR16_INTRCAN4ERR_0 (0x01000000uL) +#define INTC_ICDICFR16_INTRCAN4ERR_1 (0x02000000uL) +#define INTC_ICDICFR16_INTRCAN4TRX_0 (0x04000000uL) +#define INTC_ICDICFR16_INTRCAN4TRX_1 (0x08000000uL) +#define INTC_ICDICFR16_SPEI0_0 (0x10000000uL) +#define INTC_ICDICFR16_SPEI0_1 (0x20000000uL) +#define INTC_ICDICFR16_SPRI0_0 (0x40000000uL) +#define INTC_ICDICFR16_SPRI0_1 (0x80000000uL) + +#define INTC_ICDICFR17_SPTI0_0 (0x00000001uL) +#define INTC_ICDICFR17_SPTI0_1 (0x00000002uL) +#define INTC_ICDICFR17_SPEI1_0 (0x00000004uL) +#define INTC_ICDICFR17_SPEI1_1 (0x00000008uL) +#define INTC_ICDICFR17_SPRI1_0 (0x00000010uL) +#define INTC_ICDICFR17_SPRI1_1 (0x00000020uL) +#define INTC_ICDICFR17_SPTI1_0 (0x00000040uL) +#define INTC_ICDICFR17_SPTI1_1 (0x00000080uL) +#define INTC_ICDICFR17_SPEI2_0 (0x00000100uL) +#define INTC_ICDICFR17_SPEI2_1 (0x00000200uL) +#define INTC_ICDICFR17_SPRI2_0 (0x00000400uL) +#define INTC_ICDICFR17_SPRI2_1 (0x00000800uL) +#define INTC_ICDICFR17_SPTI2_0 (0x00001000uL) +#define INTC_ICDICFR17_SPTI2_1 (0x00002000uL) +#define INTC_ICDICFR17_SPEI3_0 (0x00004000uL) +#define INTC_ICDICFR17_SPEI3_1 (0x00008000uL) +#define INTC_ICDICFR17_SPRI3_0 (0x00010000uL) +#define INTC_ICDICFR17_SPRI3_1 (0x00020000uL) +#define INTC_ICDICFR17_SPTI3_0 (0x00040000uL) +#define INTC_ICDICFR17_SPTI3_1 (0x00080000uL) +#define INTC_ICDICFR17_SPEI4_0 (0x00100000uL) +#define INTC_ICDICFR17_SPEI4_1 (0x00200000uL) +#define INTC_ICDICFR17_SPRI4_0 (0x00400000uL) +#define INTC_ICDICFR17_SPRI4_1 (0x00800000uL) +#define INTC_ICDICFR17_SPTI4_0 (0x01000000uL) +#define INTC_ICDICFR17_SPTI4_1 (0x02000000uL) +#define INTC_ICDICFR17_IEBBTD_0 (0x04000000uL) +#define INTC_ICDICFR17_IEBBTD_1 (0x08000000uL) +#define INTC_ICDICFR17_IEBBTERR_0 (0x10000000uL) +#define INTC_ICDICFR17_IEBBTERR_1 (0x20000000uL) +#define INTC_ICDICFR17_IEBBTSTA_0 (0x40000000uL) +#define INTC_ICDICFR17_IEBBTSTA_1 (0x80000000uL) + +#define INTC_ICDICFR18_IEBBTV_0 (0x00000001uL) +#define INTC_ICDICFR18_IEBBTV_1 (0x00000002uL) +#define INTC_ICDICFR18_ISY_0 (0x00000004uL) +#define INTC_ICDICFR18_ISY_1 (0x00000008uL) +#define INTC_ICDICFR18_IERR_0 (0x00000010uL) +#define INTC_ICDICFR18_IERR_1 (0x00000020uL) +#define INTC_ICDICFR18_ITARG_0 (0x00000040uL) +#define INTC_ICDICFR18_ITARG_1 (0x00000080uL) +#define INTC_ICDICFR18_ISEC_0 (0x00000100uL) +#define INTC_ICDICFR18_ISEC_1 (0x00000200uL) +#define INTC_ICDICFR18_IBUF_0 (0x00000400uL) +#define INTC_ICDICFR18_IBUF_1 (0x00000800uL) +#define INTC_ICDICFR18_IREADY_0 (0x00001000uL) +#define INTC_ICDICFR18_IREADY_1 (0x00002000uL) +#define INTC_ICDICFR18_FLSTE_0 (0x00004000uL) +#define INTC_ICDICFR18_FLSTE_1 (0x00008000uL) +#define INTC_ICDICFR18_FLTENDI_0 (0x00010000uL) +#define INTC_ICDICFR18_FLTENDI_1 (0x00020000uL) +#define INTC_ICDICFR18_FLTREQ0I_0 (0x00040000uL) +#define INTC_ICDICFR18_FLTREQ0I_1 (0x00080000uL) +#define INTC_ICDICFR18_FLTREQ1I_0 (0x00100000uL) +#define INTC_ICDICFR18_FLTREQ1I_1 (0x00200000uL) +#define INTC_ICDICFR18_MMC0_0 (0x00400000uL) +#define INTC_ICDICFR18_MMC0_1 (0x00800000uL) +#define INTC_ICDICFR18_MMC1_0 (0x01000000uL) +#define INTC_ICDICFR18_MMC1_1 (0x02000000uL) +#define INTC_ICDICFR18_MMC2_0 (0x04000000uL) +#define INTC_ICDICFR18_MMC2_1 (0x08000000uL) +#define INTC_ICDICFR18_SDHI0_3_0 (0x10000000uL) +#define INTC_ICDICFR18_SDHI0_3_1 (0x20000000uL) +#define INTC_ICDICFR18_SDHI0_0_0 (0x40000000uL) +#define INTC_ICDICFR18_SDHI0_0_1 (0x80000000uL) + +#define INTC_ICDICFR19_SDHI0_1_0 (0x00000001uL) +#define INTC_ICDICFR19_SDHI0_1_1 (0x00000002uL) +#define INTC_ICDICFR19_SDHI1_3_0 (0x00000004uL) +#define INTC_ICDICFR19_SDHI1_3_1 (0x00000008uL) +#define INTC_ICDICFR19_SDHI1_0_0 (0x00000010uL) +#define INTC_ICDICFR19_SDHI1_0_1 (0x00000020uL) +#define INTC_ICDICFR19_SDHI1_1_0 (0x00000040uL) +#define INTC_ICDICFR19_SDHI1_1_1 (0x00000080uL) +#define INTC_ICDICFR19_ARM_0 (0x00000100uL) +#define INTC_ICDICFR19_ARM_1 (0x00000200uL) +#define INTC_ICDICFR19_PRD_0 (0x00000400uL) +#define INTC_ICDICFR19_PRD_1 (0x00000800uL) +#define INTC_ICDICFR19_CUP_0 (0x00001000uL) +#define INTC_ICDICFR19_CUP_1 (0x00002000uL) +#define INTC_ICDICFR19_SCUAI0_0 (0x00004000uL) +#define INTC_ICDICFR19_SCUAI0_1 (0x00008000uL) +#define INTC_ICDICFR19_SCUAI1_0 (0x00010000uL) +#define INTC_ICDICFR19_SCUAI1_1 (0x00020000uL) +#define INTC_ICDICFR19_SCUFDI0_0 (0x00040000uL) +#define INTC_ICDICFR19_SCUFDI0_1 (0x00080000uL) +#define INTC_ICDICFR19_SCUFDI1_0 (0x00100000uL) +#define INTC_ICDICFR19_SCUFDI1_1 (0x00200000uL) +#define INTC_ICDICFR19_SCUFDI2_0 (0x00400000uL) +#define INTC_ICDICFR19_SCUFDI2_1 (0x00800000uL) +#define INTC_ICDICFR19_SCUFDI3_0 (0x01000000uL) +#define INTC_ICDICFR19_SCUFDI3_1 (0x02000000uL) +#define INTC_ICDICFR19_SCUFUI0_0 (0x04000000uL) +#define INTC_ICDICFR19_SCUFUI0_1 (0x08000000uL) +#define INTC_ICDICFR19_SCUFUI1_0 (0x10000000uL) +#define INTC_ICDICFR19_SCUFUI1_1 (0x20000000uL) +#define INTC_ICDICFR19_SCUFUI2_0 (0x40000000uL) +#define INTC_ICDICFR19_SCUFUI2_1 (0x80000000uL) + +#define INTC_ICDICFR20_SCUFUI3_0 (0x00000001uL) +#define INTC_ICDICFR20_SCUFUI3_1 (0x00000002uL) +#define INTC_ICDICFR20_SCUDVI0_0 (0x00000004uL) +#define INTC_ICDICFR20_SCUDVI0_1 (0x00000008uL) +#define INTC_ICDICFR20_SCUDVI1_0 (0x00000010uL) +#define INTC_ICDICFR20_SCUDVI1_1 (0x00000020uL) +#define INTC_ICDICFR20_SCUDVI2_0 (0x00000040uL) +#define INTC_ICDICFR20_SCUDVI2_1 (0x00000080uL) +#define INTC_ICDICFR20_SCUDVI3_0 (0x00000100uL) +#define INTC_ICDICFR20_SCUDVI3_1 (0x00000200uL) +#define INTC_ICDICFR20_MLB_CINT_0 (0x00000400uL) +#define INTC_ICDICFR20_MLB_CINT_1 (0x00000800uL) +#define INTC_ICDICFR20_MLB_SINT_0 (0x00001000uL) +#define INTC_ICDICFR20_MLB_SINT_1 (0x00002000uL) +#define INTC_ICDICFR20_DRC0_0 (0x00004000uL) +#define INTC_ICDICFR20_DRC0_1 (0x00008000uL) +#define INTC_ICDICFR20_DRC1_0 (0x00010000uL) +#define INTC_ICDICFR20_DRC1_1 (0x00020000uL) +#define INTC_ICDICFR20_LINI0_INT_T_0 (0x00400000uL) +#define INTC_ICDICFR20_LINI0_INT_T_1 (0x00800000uL) +#define INTC_ICDICFR20_LINI0_INT_R_0 (0x01000000uL) +#define INTC_ICDICFR20_LINI0_INT_R_1 (0x02000000uL) +#define INTC_ICDICFR20_LINI0_INT_S_0 (0x04000000uL) +#define INTC_ICDICFR20_LINI0_INT_S_1 (0x08000000uL) +#define INTC_ICDICFR20_LINI0_INT_M_0 (0x10000000uL) +#define INTC_ICDICFR20_LINI0_INT_M_1 (0x20000000uL) +#define INTC_ICDICFR20_LINI1_INT_T_0 (0x40000000uL) +#define INTC_ICDICFR20_LINI1_INT_T_1 (0x80000000uL) + +#define INTC_ICDICFR21_LINI1_INT_R_0 (0x00000001uL) +#define INTC_ICDICFR21_LINI1_INT_R_1 (0x00000002uL) +#define INTC_ICDICFR21_LINI1_INT_S_0 (0x00000004uL) +#define INTC_ICDICFR21_LINI1_INT_S_1 (0x00000008uL) +#define INTC_ICDICFR21_LINI1_INT_M_0 (0x00000010uL) +#define INTC_ICDICFR21_LINI1_INT_M_1 (0x00000020uL) +#define INTC_ICDICFR21_ERI0_0 (0x00400000uL) +#define INTC_ICDICFR21_ERI0_1 (0x00800000uL) +#define INTC_ICDICFR21_RXI0_0 (0x01000000uL) +#define INTC_ICDICFR21_RXI0_1 (0x02000000uL) +#define INTC_ICDICFR21_TXI0_0 (0x04000000uL) +#define INTC_ICDICFR21_TXI0_1 (0x08000000uL) +#define INTC_ICDICFR21_TEI0_0 (0x10000000uL) +#define INTC_ICDICFR21_TEI0_1 (0x20000000uL) +#define INTC_ICDICFR21_ERI1_0 (0x40000000uL) +#define INTC_ICDICFR21_ERI1_1 (0x80000000uL) + +#define INTC_ICDICFR22_RXI1_0 (0x00000001uL) +#define INTC_ICDICFR22_RXI1_1 (0x00000002uL) +#define INTC_ICDICFR22_TXI1_0 (0x00000004uL) +#define INTC_ICDICFR22_TXI1_1 (0x00000008uL) +#define INTC_ICDICFR22_TEI1_0 (0x00000010uL) +#define INTC_ICDICFR22_TEI1_1 (0x00000020uL) +#define INTC_ICDICFR22_AVBI_DATA_0 (0x00000040uL) +#define INTC_ICDICFR22_AVBI_DATA_1 (0x00000080uL) +#define INTC_ICDICFR22_AVBI_ERROR_0 (0x00000100uL) +#define INTC_ICDICFR22_AVBI_ERROR_1 (0x00000200uL) +#define INTC_ICDICFR22_AVBI_MANAGE_0 (0x00000400uL) +#define INTC_ICDICFR22_AVBI_MANAGE_1 (0x00000800uL) +#define INTC_ICDICFR22_AVBI_MAC_0 (0x00001000uL) +#define INTC_ICDICFR22_AVBI_MAC_1 (0x00002000uL) +#define INTC_ICDICFR22_ETHERI_0 (0x00004000uL) +#define INTC_ICDICFR22_ETHERI_1 (0x00008000uL) +#define INTC_ICDICFR22_CEUI_0 (0x01000000uL) +#define INTC_ICDICFR22_CEUI_1 (0x02000000uL) + +#define INTC_ICDICFR23_H2XMLB_ERRINT_0 (0x04000000uL) +#define INTC_ICDICFR23_H2XMLB_ERRINT_1 (0x08000000uL) +#define INTC_ICDICFR23_H2XIC1_ERRINT_0 (0x10000000uL) +#define INTC_ICDICFR23_H2XIC1_ERRINT_1 (0x20000000uL) +#define INTC_ICDICFR23_X2HPERI1_ERRINT_0 (0x40000000uL) +#define INTC_ICDICFR23_X2HPERI1_ERRINT_1 (0x80000000uL) + +#define INTC_ICDICFR24_X2HPERI2_ERRINT_0 (0x00000001uL) +#define INTC_ICDICFR24_X2HPERI2_ERRINT_1 (0x00000002uL) +#define INTC_ICDICFR24_X2HPERI34_ERRINT_0 (0x00000004uL) +#define INTC_ICDICFR24_X2HPERI34_ERRINT_1 (0x00000008uL) +#define INTC_ICDICFR24_X2HPERI5_ERRINT_0 (0x00000010uL) +#define INTC_ICDICFR24_X2HPERI5_ERRINT_1 (0x00000020uL) +#define INTC_ICDICFR24_X2HPERI67_ERRINT_0 (0x00000040uL) +#define INTC_ICDICFR24_X2HPERI67_ERRINT_1 (0x00000080uL) +#define INTC_ICDICFR24_X2HDBGR_ERRINT_0 (0x00000100uL) +#define INTC_ICDICFR24_X2HDBGR_ERRINT_1 (0x00000200uL) +#define INTC_ICDICFR24_X2HBSC_ERRINT_0 (0x00000400uL) +#define INTC_ICDICFR24_X2HBSC_ERRINT_1 (0x00000800uL) +#define INTC_ICDICFR24_X2HSPI1_ERRINT_0 (0x00001000uL) +#define INTC_ICDICFR24_X2HSPI1_ERRINT_1 (0x00002000uL) +#define INTC_ICDICFR24_X2HSPI2_ERRINT_0 (0x00004000uL) +#define INTC_ICDICFR24_X2HSPI2_ERRINT_1 (0x00008000uL) +#define INTC_ICDICFR24_PRRI_0 (0x00010000uL) +#define INTC_ICDICFR24_PRRI_1 (0x00020000uL) +#define INTC_ICDICFR24_IFEI0_0 (0x00040000uL) +#define INTC_ICDICFR24_IFEI0_1 (0x00080000uL) +#define INTC_ICDICFR24_OFFI0_0 (0x00100000uL) +#define INTC_ICDICFR24_OFFI0_1 (0x00200000uL) +#define INTC_ICDICFR24_PFVEI0_0 (0x00400000uL) +#define INTC_ICDICFR24_PFVEI0_1 (0x00800000uL) +#define INTC_ICDICFR24_IFEI1_0 (0x01000000uL) +#define INTC_ICDICFR24_IFEI1_1 (0x02000000uL) +#define INTC_ICDICFR24_OFFI1_0 (0x04000000uL) +#define INTC_ICDICFR24_OFFI1_1 (0x08000000uL) +#define INTC_ICDICFR24_PFVEI1_0 (0x10000000uL) +#define INTC_ICDICFR24_PFVEI1_1 (0x20000000uL) + +#define INTC_ICDICFR26_TINT0_0 (0x00000001uL) +#define INTC_ICDICFR26_TINT0_1 (0x00000002uL) +#define INTC_ICDICFR26_TINT1_0 (0x00000004uL) +#define INTC_ICDICFR26_TINT1_1 (0x00000008uL) +#define INTC_ICDICFR26_TINT2_0 (0x00000010uL) +#define INTC_ICDICFR26_TINT2_1 (0x00000020uL) +#define INTC_ICDICFR26_TINT3_0 (0x00000040uL) +#define INTC_ICDICFR26_TINT3_1 (0x00000080uL) +#define INTC_ICDICFR26_TINT4_0 (0x00000100uL) +#define INTC_ICDICFR26_TINT4_1 (0x00000200uL) +#define INTC_ICDICFR26_TINT5_0 (0x00000400uL) +#define INTC_ICDICFR26_TINT5_1 (0x00000800uL) +#define INTC_ICDICFR26_TINT6_0 (0x00001000uL) +#define INTC_ICDICFR26_TINT6_1 (0x00002000uL) +#define INTC_ICDICFR26_TINT7_0 (0x00004000uL) +#define INTC_ICDICFR26_TINT7_1 (0x00008000uL) +#define INTC_ICDICFR26_TINT8_0 (0x00010000uL) +#define INTC_ICDICFR26_TINT8_1 (0x00020000uL) +#define INTC_ICDICFR26_TINT9_0 (0x00040000uL) +#define INTC_ICDICFR26_TINT9_1 (0x00080000uL) +#define INTC_ICDICFR26_TINT10_0 (0x00100000uL) +#define INTC_ICDICFR26_TINT10_1 (0x00200000uL) +#define INTC_ICDICFR26_TINT11_0 (0x00400000uL) +#define INTC_ICDICFR26_TINT11_1 (0x00800000uL) +#define INTC_ICDICFR26_TINT12_0 (0x01000000uL) +#define INTC_ICDICFR26_TINT12_1 (0x02000000uL) +#define INTC_ICDICFR26_TINT13_0 (0x04000000uL) +#define INTC_ICDICFR26_TINT13_1 (0x08000000uL) +#define INTC_ICDICFR26_TINT14_0 (0x10000000uL) +#define INTC_ICDICFR26_TINT14_1 (0x20000000uL) +#define INTC_ICDICFR26_TINT15_0 (0x40000000uL) +#define INTC_ICDICFR26_TINT15_1 (0x80000000uL) + +#define INTC_ICDICFR27_TINT16_0 (0x00000001uL) +#define INTC_ICDICFR27_TINT16_1 (0x00000002uL) +#define INTC_ICDICFR27_TINT17_0 (0x00000004uL) +#define INTC_ICDICFR27_TINT17_1 (0x00000008uL) +#define INTC_ICDICFR27_TINT18_0 (0x00000010uL) +#define INTC_ICDICFR27_TINT18_1 (0x00000020uL) +#define INTC_ICDICFR27_TINT19_0 (0x00000040uL) +#define INTC_ICDICFR27_TINT19_1 (0x00000080uL) +#define INTC_ICDICFR27_TINT20_0 (0x00000100uL) +#define INTC_ICDICFR27_TINT20_1 (0x00000200uL) +#define INTC_ICDICFR27_TINT21_0 (0x00000400uL) +#define INTC_ICDICFR27_TINT21_1 (0x00000800uL) +#define INTC_ICDICFR27_TINT22_0 (0x00001000uL) +#define INTC_ICDICFR27_TINT22_1 (0x00002000uL) +#define INTC_ICDICFR27_TINT23_0 (0x00004000uL) +#define INTC_ICDICFR27_TINT23_1 (0x00008000uL) +#define INTC_ICDICFR27_TINT24_0 (0x00010000uL) +#define INTC_ICDICFR27_TINT24_1 (0x00020000uL) +#define INTC_ICDICFR27_TINT25_0 (0x00040000uL) +#define INTC_ICDICFR27_TINT25_1 (0x00080000uL) +#define INTC_ICDICFR27_TINT26_0 (0x00100000uL) +#define INTC_ICDICFR27_TINT26_1 (0x00200000uL) +#define INTC_ICDICFR27_TINT27_0 (0x00400000uL) +#define INTC_ICDICFR27_TINT27_1 (0x00800000uL) +#define INTC_ICDICFR27_TINT28_0 (0x01000000uL) +#define INTC_ICDICFR27_TINT28_1 (0x02000000uL) +#define INTC_ICDICFR27_TINT29_0 (0x04000000uL) +#define INTC_ICDICFR27_TINT29_1 (0x08000000uL) +#define INTC_ICDICFR27_TINT30_0 (0x10000000uL) +#define INTC_ICDICFR27_TINT30_1 (0x20000000uL) +#define INTC_ICDICFR27_TINT31_0 (0x40000000uL) +#define INTC_ICDICFR27_TINT31_1 (0x80000000uL) + +#define INTC_ICDICFR28_TINT32_0 (0x00000001uL) +#define INTC_ICDICFR28_TINT32_1 (0x00000002uL) +#define INTC_ICDICFR28_TINT33_0 (0x00000004uL) +#define INTC_ICDICFR28_TINT33_1 (0x00000008uL) +#define INTC_ICDICFR28_TINT34_0 (0x00000010uL) +#define INTC_ICDICFR28_TINT34_1 (0x00000020uL) +#define INTC_ICDICFR28_TINT35_0 (0x00000040uL) +#define INTC_ICDICFR28_TINT35_1 (0x00000080uL) +#define INTC_ICDICFR28_TINT36_0 (0x00000100uL) +#define INTC_ICDICFR28_TINT36_1 (0x00000200uL) +#define INTC_ICDICFR28_TINT37_0 (0x00000400uL) +#define INTC_ICDICFR28_TINT37_1 (0x00000800uL) +#define INTC_ICDICFR28_TINT38_0 (0x00001000uL) +#define INTC_ICDICFR28_TINT38_1 (0x00002000uL) +#define INTC_ICDICFR28_TINT39_0 (0x00004000uL) +#define INTC_ICDICFR28_TINT39_1 (0x00008000uL) +#define INTC_ICDICFR28_TINT40_0 (0x00010000uL) +#define INTC_ICDICFR28_TINT40_1 (0x00020000uL) +#define INTC_ICDICFR28_TINT41_0 (0x00040000uL) +#define INTC_ICDICFR28_TINT41_1 (0x00080000uL) +#define INTC_ICDICFR28_TINT42_0 (0x00100000uL) +#define INTC_ICDICFR28_TINT42_1 (0x00200000uL) +#define INTC_ICDICFR28_TINT43_0 (0x00400000uL) +#define INTC_ICDICFR28_TINT43_1 (0x00800000uL) +#define INTC_ICDICFR28_TINT44_0 (0x01000000uL) +#define INTC_ICDICFR28_TINT44_1 (0x02000000uL) +#define INTC_ICDICFR28_TINT45_0 (0x04000000uL) +#define INTC_ICDICFR28_TINT45_1 (0x08000000uL) +#define INTC_ICDICFR28_TINT46_0 (0x10000000uL) +#define INTC_ICDICFR28_TINT46_1 (0x20000000uL) +#define INTC_ICDICFR28_TINT47_0 (0x40000000uL) +#define INTC_ICDICFR28_TINT47_1 (0x80000000uL) + +#define INTC_ICDICFR29_TINT48_0 (0x00000001uL) +#define INTC_ICDICFR29_TINT48_1 (0x00000002uL) +#define INTC_ICDICFR29_TINT49_0 (0x00000004uL) +#define INTC_ICDICFR29_TINT49_1 (0x00000008uL) +#define INTC_ICDICFR29_TINT50_0 (0x00000010uL) +#define INTC_ICDICFR29_TINT50_1 (0x00000020uL) +#define INTC_ICDICFR29_TINT51_0 (0x00000040uL) +#define INTC_ICDICFR29_TINT51_1 (0x00000080uL) +#define INTC_ICDICFR29_TINT52_0 (0x00000100uL) +#define INTC_ICDICFR29_TINT52_1 (0x00000200uL) +#define INTC_ICDICFR29_TINT53_0 (0x00000400uL) +#define INTC_ICDICFR29_TINT53_1 (0x00000800uL) +#define INTC_ICDICFR29_TINT54_0 (0x00001000uL) +#define INTC_ICDICFR29_TINT54_1 (0x00002000uL) +#define INTC_ICDICFR29_TINT55_0 (0x00004000uL) +#define INTC_ICDICFR29_TINT55_1 (0x00008000uL) +#define INTC_ICDICFR29_TINT56_0 (0x00010000uL) +#define INTC_ICDICFR29_TINT56_1 (0x00020000uL) +#define INTC_ICDICFR29_TINT57_0 (0x00040000uL) +#define INTC_ICDICFR29_TINT57_1 (0x00080000uL) +#define INTC_ICDICFR29_TINT58_0 (0x00100000uL) +#define INTC_ICDICFR29_TINT58_1 (0x00200000uL) +#define INTC_ICDICFR29_TINT59_0 (0x00400000uL) +#define INTC_ICDICFR29_TINT59_1 (0x00800000uL) +#define INTC_ICDICFR29_TINT60_0 (0x01000000uL) +#define INTC_ICDICFR29_TINT60_1 (0x02000000uL) +#define INTC_ICDICFR29_TINT61_0 (0x04000000uL) +#define INTC_ICDICFR29_TINT61_1 (0x08000000uL) +#define INTC_ICDICFR29_TINT62_0 (0x10000000uL) +#define INTC_ICDICFR29_TINT62_1 (0x20000000uL) +#define INTC_ICDICFR29_TINT63_0 (0x40000000uL) +#define INTC_ICDICFR29_TINT63_1 (0x80000000uL) + +#define INTC_ICDICFR30_TINT64_0 (0x00000001uL) +#define INTC_ICDICFR30_TINT64_1 (0x00000002uL) +#define INTC_ICDICFR30_TINT65_0 (0x00000004uL) +#define INTC_ICDICFR30_TINT65_1 (0x00000008uL) +#define INTC_ICDICFR30_TINT66_0 (0x00000010uL) +#define INTC_ICDICFR30_TINT66_1 (0x00000020uL) +#define INTC_ICDICFR30_TINT67_0 (0x00000040uL) +#define INTC_ICDICFR30_TINT67_1 (0x00000080uL) +#define INTC_ICDICFR30_TINT68_0 (0x00000100uL) +#define INTC_ICDICFR30_TINT68_1 (0x00000200uL) +#define INTC_ICDICFR30_TINT69_0 (0x00000400uL) +#define INTC_ICDICFR30_TINT69_1 (0x00000800uL) +#define INTC_ICDICFR30_TINT70_0 (0x00001000uL) +#define INTC_ICDICFR30_TINT70_1 (0x00002000uL) +#define INTC_ICDICFR30_TINT71_0 (0x00004000uL) +#define INTC_ICDICFR30_TINT71_1 (0x00008000uL) +#define INTC_ICDICFR30_TINT72_0 (0x00010000uL) +#define INTC_ICDICFR30_TINT72_1 (0x00020000uL) +#define INTC_ICDICFR30_TINT73_0 (0x00040000uL) +#define INTC_ICDICFR30_TINT73_1 (0x00080000uL) +#define INTC_ICDICFR30_TINT74_0 (0x00100000uL) +#define INTC_ICDICFR30_TINT74_1 (0x00200000uL) +#define INTC_ICDICFR30_TINT75_0 (0x00400000uL) +#define INTC_ICDICFR30_TINT75_1 (0x00800000uL) +#define INTC_ICDICFR30_TINT76_0 (0x01000000uL) +#define INTC_ICDICFR30_TINT76_1 (0x02000000uL) +#define INTC_ICDICFR30_TINT77_0 (0x04000000uL) +#define INTC_ICDICFR30_TINT77_1 (0x08000000uL) +#define INTC_ICDICFR30_TINT78_0 (0x10000000uL) +#define INTC_ICDICFR30_TINT78_1 (0x20000000uL) +#define INTC_ICDICFR30_TINT79_0 (0x40000000uL) +#define INTC_ICDICFR30_TINT79_1 (0x80000000uL) + +#define INTC_ICDICFR31_TINT80_0 (0x00000001uL) +#define INTC_ICDICFR31_TINT80_1 (0x00000002uL) +#define INTC_ICDICFR31_TINT81_0 (0x00000004uL) +#define INTC_ICDICFR31_TINT81_1 (0x00000008uL) +#define INTC_ICDICFR31_TINT82_0 (0x00000010uL) +#define INTC_ICDICFR31_TINT82_1 (0x00000020uL) +#define INTC_ICDICFR31_TINT83_0 (0x00000040uL) +#define INTC_ICDICFR31_TINT83_1 (0x00000080uL) +#define INTC_ICDICFR31_TINT84_0 (0x00000100uL) +#define INTC_ICDICFR31_TINT84_1 (0x00000200uL) +#define INTC_ICDICFR31_TINT85_0 (0x00000400uL) +#define INTC_ICDICFR31_TINT85_1 (0x00000800uL) +#define INTC_ICDICFR31_TINT86_0 (0x00001000uL) +#define INTC_ICDICFR31_TINT86_1 (0x00002000uL) +#define INTC_ICDICFR31_TINT87_0 (0x00004000uL) +#define INTC_ICDICFR31_TINT87_1 (0x00008000uL) +#define INTC_ICDICFR31_TINT88_0 (0x00010000uL) +#define INTC_ICDICFR31_TINT88_1 (0x00020000uL) +#define INTC_ICDICFR31_TINT89_0 (0x00040000uL) +#define INTC_ICDICFR31_TINT89_1 (0x00080000uL) +#define INTC_ICDICFR31_TINT90_0 (0x00100000uL) +#define INTC_ICDICFR31_TINT90_1 (0x00200000uL) +#define INTC_ICDICFR31_TINT91_0 (0x00400000uL) +#define INTC_ICDICFR31_TINT91_1 (0x00800000uL) +#define INTC_ICDICFR31_TINT92_0 (0x01000000uL) +#define INTC_ICDICFR31_TINT92_1 (0x02000000uL) +#define INTC_ICDICFR31_TINT93_0 (0x04000000uL) +#define INTC_ICDICFR31_TINT93_1 (0x08000000uL) +#define INTC_ICDICFR31_TINT94_0 (0x10000000uL) +#define INTC_ICDICFR31_TINT94_1 (0x20000000uL) +#define INTC_ICDICFR31_TINT95_0 (0x40000000uL) +#define INTC_ICDICFR31_TINT95_1 (0x80000000uL) + +#define INTC_ICDICFR32_TINT96_0 (0x00000001uL) +#define INTC_ICDICFR32_TINT96_1 (0x00000002uL) +#define INTC_ICDICFR32_TINT97_0 (0x00000004uL) +#define INTC_ICDICFR32_TINT97_1 (0x00000008uL) +#define INTC_ICDICFR32_TINT98_0 (0x00000010uL) +#define INTC_ICDICFR32_TINT98_1 (0x00000020uL) +#define INTC_ICDICFR32_TINT99_0 (0x00000040uL) +#define INTC_ICDICFR32_TINT99_1 (0x00000080uL) +#define INTC_ICDICFR32_TINT100_0 (0x00000100uL) +#define INTC_ICDICFR32_TINT100_1 (0x00000200uL) +#define INTC_ICDICFR32_TINT101_0 (0x00000400uL) +#define INTC_ICDICFR32_TINT101_1 (0x00000800uL) +#define INTC_ICDICFR32_TINT102_0 (0x00001000uL) +#define INTC_ICDICFR32_TINT102_1 (0x00002000uL) +#define INTC_ICDICFR32_TINT103_0 (0x00004000uL) +#define INTC_ICDICFR32_TINT103_1 (0x00008000uL) +#define INTC_ICDICFR32_TINT104_0 (0x00010000uL) +#define INTC_ICDICFR32_TINT104_1 (0x00020000uL) +#define INTC_ICDICFR32_TINT105_0 (0x00040000uL) +#define INTC_ICDICFR32_TINT105_1 (0x00080000uL) +#define INTC_ICDICFR32_TINT106_0 (0x00100000uL) +#define INTC_ICDICFR32_TINT106_1 (0x00200000uL) +#define INTC_ICDICFR32_TINT107_0 (0x00400000uL) +#define INTC_ICDICFR32_TINT107_1 (0x00800000uL) +#define INTC_ICDICFR32_TINT108_0 (0x01000000uL) +#define INTC_ICDICFR32_TINT108_1 (0x02000000uL) +#define INTC_ICDICFR32_TINT109_0 (0x04000000uL) +#define INTC_ICDICFR32_TINT109_1 (0x08000000uL) +#define INTC_ICDICFR32_TINT110_0 (0x10000000uL) +#define INTC_ICDICFR32_TINT110_1 (0x20000000uL) +#define INTC_ICDICFR32_TINT111_0 (0x40000000uL) +#define INTC_ICDICFR32_TINT111_1 (0x80000000uL) + +#define INTC_ICDICFR33_TINT112_0 (0x00000001uL) +#define INTC_ICDICFR33_TINT112_1 (0x00000002uL) +#define INTC_ICDICFR33_TINT113_0 (0x00000004uL) +#define INTC_ICDICFR33_TINT113_1 (0x00000008uL) +#define INTC_ICDICFR33_TINT114_0 (0x00000010uL) +#define INTC_ICDICFR33_TINT114_1 (0x00000020uL) +#define INTC_ICDICFR33_TINT115_0 (0x00000040uL) +#define INTC_ICDICFR33_TINT115_1 (0x00000080uL) +#define INTC_ICDICFR33_TINT116_0 (0x00000100uL) +#define INTC_ICDICFR33_TINT116_1 (0x00000200uL) +#define INTC_ICDICFR33_TINT117_0 (0x00000400uL) +#define INTC_ICDICFR33_TINT117_1 (0x00000800uL) +#define INTC_ICDICFR33_TINT118_0 (0x00001000uL) +#define INTC_ICDICFR33_TINT118_1 (0x00002000uL) +#define INTC_ICDICFR33_TINT119_0 (0x00004000uL) +#define INTC_ICDICFR33_TINT119_1 (0x00008000uL) +#define INTC_ICDICFR33_TINT120_0 (0x00010000uL) +#define INTC_ICDICFR33_TINT120_1 (0x00020000uL) +#define INTC_ICDICFR33_TINT121_0 (0x00040000uL) +#define INTC_ICDICFR33_TINT121_1 (0x00080000uL) +#define INTC_ICDICFR33_TINT122_0 (0x00100000uL) +#define INTC_ICDICFR33_TINT122_1 (0x00200000uL) +#define INTC_ICDICFR33_TINT123_0 (0x00400000uL) +#define INTC_ICDICFR33_TINT123_1 (0x00800000uL) +#define INTC_ICDICFR33_TINT124_0 (0x01000000uL) +#define INTC_ICDICFR33_TINT124_1 (0x02000000uL) +#define INTC_ICDICFR33_TINT125_0 (0x04000000uL) +#define INTC_ICDICFR33_TINT125_1 (0x08000000uL) +#define INTC_ICDICFR33_TINT126_0 (0x10000000uL) +#define INTC_ICDICFR33_TINT126_1 (0x20000000uL) +#define INTC_ICDICFR33_TINT127_0 (0x40000000uL) +#define INTC_ICDICFR33_TINT127_1 (0x80000000uL) + +#define INTC_ICDICFR34_TINT128_0 (0x00000001uL) +#define INTC_ICDICFR34_TINT128_1 (0x00000002uL) +#define INTC_ICDICFR34_TINT129_0 (0x00000004uL) +#define INTC_ICDICFR34_TINT129_1 (0x00000008uL) +#define INTC_ICDICFR34_TINT130_0 (0x00000010uL) +#define INTC_ICDICFR34_TINT130_1 (0x00000020uL) +#define INTC_ICDICFR34_TINT131_0 (0x00000040uL) +#define INTC_ICDICFR34_TINT131_1 (0x00000080uL) +#define INTC_ICDICFR34_TINT132_0 (0x00000100uL) +#define INTC_ICDICFR34_TINT132_1 (0x00000200uL) +#define INTC_ICDICFR34_TINT133_0 (0x00000400uL) +#define INTC_ICDICFR34_TINT133_1 (0x00000800uL) +#define INTC_ICDICFR34_TINT134_0 (0x00001000uL) +#define INTC_ICDICFR34_TINT134_1 (0x00002000uL) +#define INTC_ICDICFR34_TINT135_0 (0x00004000uL) +#define INTC_ICDICFR34_TINT135_1 (0x00008000uL) +#define INTC_ICDICFR34_TINT136_0 (0x00010000uL) +#define INTC_ICDICFR34_TINT136_1 (0x00020000uL) +#define INTC_ICDICFR34_TINT137_0 (0x00040000uL) +#define INTC_ICDICFR34_TINT137_1 (0x00080000uL) +#define INTC_ICDICFR34_TINT138_0 (0x00100000uL) +#define INTC_ICDICFR34_TINT138_1 (0x00200000uL) +#define INTC_ICDICFR34_TINT139_0 (0x00400000uL) +#define INTC_ICDICFR34_TINT139_1 (0x00800000uL) +#define INTC_ICDICFR34_TINT140_0 (0x01000000uL) +#define INTC_ICDICFR34_TINT140_1 (0x02000000uL) +#define INTC_ICDICFR34_TINT141_0 (0x04000000uL) +#define INTC_ICDICFR34_TINT141_1 (0x08000000uL) +#define INTC_ICDICFR34_TINT142_0 (0x10000000uL) +#define INTC_ICDICFR34_TINT142_1 (0x20000000uL) +#define INTC_ICDICFR34_TINT143_0 (0x40000000uL) +#define INTC_ICDICFR34_TINT143_1 (0x80000000uL) + +#define INTC_ICDICFR35_TINT144_0 (0x00000001uL) +#define INTC_ICDICFR35_TINT144_1 (0x00000002uL) +#define INTC_ICDICFR35_TINT145_0 (0x00000004uL) +#define INTC_ICDICFR35_TINT145_1 (0x00000008uL) +#define INTC_ICDICFR35_TINT146_0 (0x00000010uL) +#define INTC_ICDICFR35_TINT146_1 (0x00000020uL) +#define INTC_ICDICFR35_TINT147_0 (0x00000040uL) +#define INTC_ICDICFR35_TINT147_1 (0x00000080uL) +#define INTC_ICDICFR35_TINT148_0 (0x00000100uL) +#define INTC_ICDICFR35_TINT148_1 (0x00000200uL) +#define INTC_ICDICFR35_TINT149_0 (0x00000400uL) +#define INTC_ICDICFR35_TINT149_1 (0x00000800uL) +#define INTC_ICDICFR35_TINT150_0 (0x00001000uL) +#define INTC_ICDICFR35_TINT150_1 (0x00002000uL) +#define INTC_ICDICFR35_TINT151_0 (0x00004000uL) +#define INTC_ICDICFR35_TINT151_1 (0x00008000uL) +#define INTC_ICDICFR35_TINT152_0 (0x00010000uL) +#define INTC_ICDICFR35_TINT152_1 (0x00020000uL) +#define INTC_ICDICFR35_TINT153_0 (0x00040000uL) +#define INTC_ICDICFR35_TINT153_1 (0x00080000uL) +#define INTC_ICDICFR35_TINT154_0 (0x00100000uL) +#define INTC_ICDICFR35_TINT154_1 (0x00200000uL) +#define INTC_ICDICFR35_TINT155_0 (0x00400000uL) +#define INTC_ICDICFR35_TINT155_1 (0x00800000uL) +#define INTC_ICDICFR35_TINT156_0 (0x01000000uL) +#define INTC_ICDICFR35_TINT156_1 (0x02000000uL) +#define INTC_ICDICFR35_TINT157_0 (0x04000000uL) +#define INTC_ICDICFR35_TINT157_1 (0x08000000uL) +#define INTC_ICDICFR35_TINT158_0 (0x10000000uL) +#define INTC_ICDICFR35_TINT158_1 (0x20000000uL) +#define INTC_ICDICFR35_TINT159_0 (0x40000000uL) +#define INTC_ICDICFR35_TINT159_1 (0x80000000uL) + +#define INTC_ICDICFR36_TINT160_0 (0x00000001uL) +#define INTC_ICDICFR36_TINT160_1 (0x00000002uL) +#define INTC_ICDICFR36_TINT161_0 (0x00000004uL) +#define INTC_ICDICFR36_TINT161_1 (0x00000008uL) +#define INTC_ICDICFR36_TINT162_0 (0x00000010uL) +#define INTC_ICDICFR36_TINT162_1 (0x00000020uL) +#define INTC_ICDICFR36_TINT163_0 (0x00000040uL) +#define INTC_ICDICFR36_TINT163_1 (0x00000080uL) +#define INTC_ICDICFR36_TINT164_0 (0x00000100uL) +#define INTC_ICDICFR36_TINT164_1 (0x00000200uL) +#define INTC_ICDICFR36_TINT165_0 (0x00000400uL) +#define INTC_ICDICFR36_TINT165_1 (0x00000800uL) +#define INTC_ICDICFR36_TINT166_0 (0x00001000uL) +#define INTC_ICDICFR36_TINT166_1 (0x00002000uL) +#define INTC_ICDICFR36_TINT167_0 (0x00004000uL) +#define INTC_ICDICFR36_TINT167_1 (0x00008000uL) +#define INTC_ICDICFR36_TINT168_0 (0x00010000uL) +#define INTC_ICDICFR36_TINT168_1 (0x00020000uL) +#define INTC_ICDICFR36_TINT169_0 (0x00040000uL) +#define INTC_ICDICFR36_TINT169_1 (0x00080000uL) +#define INTC_ICDICFR36_TINT170_0 (0x00100000uL) +#define INTC_ICDICFR36_TINT170_1 (0x00200000uL) + +#define INTC_ICDSGIR_SGIINTID (0x0000000FuL) +#define INTC_ICDSGIR_SATT (0x00008000uL) +#define INTC_ICDSGIR_CPUTargetList (0x00FF0000uL) +#define INTC_ICDSGIR_TargetListFilter (0x03000000uL) + +#define INTC_ICCICR_EnableS (0x00000001uL) +#define INTC_ICCICR_EnableNS (0x00000002uL) +#define INTC_ICCICR_AckCtl (0x00000004uL) +#define INTC_ICCICR_FIQEn (0x00000008uL) +#define INTC_ICCICR_SBPR (0x00000010uL) + +#define INTC_ICCPMR_Priority (0x000000FFuL) + +#define INTC_ICCBPR_Binarypoint (0x00000007uL) + +#define INTC_ICCIAR_ACKINTID (0x000003FFuL) +#define INTC_ICCIAR_CPUID (0x00001C00uL) + +#define INTC_ICCEOIR_EOIINTID (0x000003FFuL) +#define INTC_ICCEOIR_CPUID (0x00001C00uL) + +#define INTC_ICCRPR_Priority (0x000000FFuL) + +#define INTC_ICCHPIR_PENDINTID (0x000003FFuL) +#define INTC_ICCHPIR_CPUID (0x00001C00uL) + +#define INTC_ICCABPR_Binarypoint (0x00000007uL) + +#define INTC_ICCIIDR_Implementer (0x00000FFFuL) +#define INTC_ICCIIDR_Revision (0x0000F000uL) +#define INTC_ICCIIDR_Architecture_version (0x000F0000uL) +#define INTC_ICCIIDR_ProductID (0xFFF00000uL) + +#define INTC_ICR0_NMIF (0x0002u) +#define INTC_ICR0_NMIE (0x0100u) +#define INTC_ICR0_NMIL (0x8000u) + +#define INTC_ICR1_IRQ00S (0x0001u) +#define INTC_ICR1_IRQ01S (0x0002u) +#define INTC_ICR1_IRQ10S (0x0004u) +#define INTC_ICR1_IRQ11S (0x0008u) +#define INTC_ICR1_IRQ20S (0x0010u) +#define INTC_ICR1_IRQ21S (0x0020u) +#define INTC_ICR1_IRQ30S (0x0040u) +#define INTC_ICR1_IRQ31S (0x0080u) +#define INTC_ICR1_IRQ40S (0x0100u) +#define INTC_ICR1_IRQ41S (0x0200u) +#define INTC_ICR1_IRQ50S (0x0400u) +#define INTC_ICR1_IRQ51S (0x0800u) +#define INTC_ICR1_IRQ60S (0x1000u) +#define INTC_ICR1_IRQ61S (0x2000u) +#define INTC_ICR1_IRQ70S (0x4000u) +#define INTC_ICR1_IRQ71S (0x8000u) + +#define INTC_IRQRR_IRQ0F (0x0001u) +#define INTC_IRQRR_IRQ1F (0x0002u) +#define INTC_IRQRR_IRQ2F (0x0004u) +#define INTC_IRQRR_IRQ3F (0x0008u) +#define INTC_IRQRR_IRQ4F (0x0010u) +#define INTC_IRQRR_IRQ5F (0x0020u) +#define INTC_IRQRR_IRQ6F (0x0040u) +#define INTC_IRQRR_IRQ7F (0x0080u) + + +/* ==== Shift values for IO registers ==== */ +#define INTC_ICDDCR_Enable_SHIFT (0u) + +#define INTC_ICDICTR_ITLinesNumber_SHIFT (0u) +#define INTC_ICDICTR_CPUNumber_SHIFT (5u) +#define INTC_ICDICTR_SecurityExtn_SHIFT (10u) +#define INTC_ICDICTR_LSPI_SHIFT (11u) + +#define INTC_ICDIIDR_Implementer_SHIFT (0u) +#define INTC_ICDIIDR_Revision_SHIFT (12u) +#define INTC_ICDIIDR_Variant_SHIFT (16u) +#define INTC_ICDIIDR_ProductID_SHIFT (24u) + +#define INTC_ICDISR0_SW0_SHIFT (0u) +#define INTC_ICDISR0_SW1_SHIFT (1u) +#define INTC_ICDISR0_SW2_SHIFT (2u) +#define INTC_ICDISR0_SW3_SHIFT (3u) +#define INTC_ICDISR0_SW4_SHIFT (4u) +#define INTC_ICDISR0_SW5_SHIFT (5u) +#define INTC_ICDISR0_SW6_SHIFT (6u) +#define INTC_ICDISR0_SW7_SHIFT (7u) +#define INTC_ICDISR0_SW8_SHIFT (8u) +#define INTC_ICDISR0_SW9_SHIFT (9u) +#define INTC_ICDISR0_SW10_SHIFT (10u) +#define INTC_ICDISR0_SW11_SHIFT (11u) +#define INTC_ICDISR0_SW12_SHIFT (12u) +#define INTC_ICDISR0_SW13_SHIFT (13u) +#define INTC_ICDISR0_SW14_SHIFT (14u) +#define INTC_ICDISR0_SW15_SHIFT (15u) +#define INTC_ICDISR0_PMUIRQ0_SHIFT (16u) +#define INTC_ICDISR0_COMMRX0_SHIFT (17u) +#define INTC_ICDISR0_COMMTX0_SHIFT (18u) +#define INTC_ICDISR0_CTIIRQ0_SHIFT (19u) + +#define INTC_ICDISR1_IRQ0_SHIFT (0u) +#define INTC_ICDISR1_IRQ1_SHIFT (1u) +#define INTC_ICDISR1_IRQ2_SHIFT (2u) +#define INTC_ICDISR1_IRQ3_SHIFT (3u) +#define INTC_ICDISR1_IRQ4_SHIFT (4u) +#define INTC_ICDISR1_IRQ5_SHIFT (5u) +#define INTC_ICDISR1_IRQ6_SHIFT (6u) +#define INTC_ICDISR1_IRQ7_SHIFT (7u) +#define INTC_ICDISR1_PL310ERR_SHIFT (8u) +#define INTC_ICDISR1_DMAINT0_SHIFT (9u) +#define INTC_ICDISR1_DMAINT1_SHIFT (10u) +#define INTC_ICDISR1_DMAINT2_SHIFT (11u) +#define INTC_ICDISR1_DMAINT3_SHIFT (12u) +#define INTC_ICDISR1_DMAINT4_SHIFT (13u) +#define INTC_ICDISR1_DMAINT5_SHIFT (14u) +#define INTC_ICDISR1_DMAINT6_SHIFT (15u) +#define INTC_ICDISR1_DMAINT7_SHIFT (16u) +#define INTC_ICDISR1_DMAINT8_SHIFT (17u) +#define INTC_ICDISR1_DMAINT9_SHIFT (18u) +#define INTC_ICDISR1_DMAINT10_SHIFT (19u) +#define INTC_ICDISR1_DMAINT11_SHIFT (20u) +#define INTC_ICDISR1_DMAINT12_SHIFT (21u) +#define INTC_ICDISR1_DMAINT13_SHIFT (22u) +#define INTC_ICDISR1_DMAINT14_SHIFT (23u) +#define INTC_ICDISR1_DMAINT15_SHIFT (24u) +#define INTC_ICDISR1_DMAERR_SHIFT (25u) + +#define INTC_ICDISR2_USBI0_SHIFT (9u) +#define INTC_ICDISR2_USBI1_SHIFT (10u) +#define INTC_ICDISR2_S0_VI_VSYNC0_SHIFT (11u) +#define INTC_ICDISR2_S0_LO_VSYNC0_SHIFT (12u) +#define INTC_ICDISR2_S0_VSYNCERR0_SHIFT (13u) +#define INTC_ICDISR2_GR3_VLINE0_SHIFT (14u) +#define INTC_ICDISR2_S0_VFIELD0_SHIFT (15u) +#define INTC_ICDISR2_IV1_VBUFERR0_SHIFT (16u) +#define INTC_ICDISR2_IV3_VBUFERR0_SHIFT (17u) +#define INTC_ICDISR2_IV5_VBUFERR0_SHIFT (18u) +#define INTC_ICDISR2_IV6_VBUFERR0_SHIFT (19u) +#define INTC_ICDISR2_S0_WLINE0_SHIFT (20u) +#define INTC_ICDISR2_S1_VI_VSYNC0_SHIFT (21u) +#define INTC_ICDISR2_S1_LO_VSYNC0_SHIFT (22u) +#define INTC_ICDISR2_S1_VSYNCERR0_SHIFT (23u) +#define INTC_ICDISR2_S1_VFIELD0_SHIFT (24u) +#define INTC_ICDISR2_IV2_VBUFERR0_SHIFT (25u) +#define INTC_ICDISR2_IV4_VBUFERR0_SHIFT (26u) +#define INTC_ICDISR2_S1_WLINE0_SHIFT (27u) +#define INTC_ICDISR2_OIR_VI_VSYNC0_SHIFT (28u) +#define INTC_ICDISR2_OIR_LO_VSYNC0_SHIFT (29u) +#define INTC_ICDISR2_OIR_VSYNCERR0_SHIFT (30u) +#define INTC_ICDISR2_OIR_VFIELD0_SHIFT (31u) + +#define INTC_ICDISR3_IV7_VBUFERR0_SHIFT (0u) +#define INTC_ICDISR3_IV8_VBUFERR0_SHIFT (1u) +#define INTC_ICDISR3_S0_VI_VSYNC1_SHIFT (3u) +#define INTC_ICDISR3_S0_LO_VSYNC1_SHIFT (4u) +#define INTC_ICDISR3_S0_VSYNCERR1_SHIFT (5u) +#define INTC_ICDISR3_GR3_VLINE1_SHIFT (6u) +#define INTC_ICDISR3_S0_VFIELD1_SHIFT (7u) +#define INTC_ICDISR3_IV1_VBUFERR1_SHIFT (8u) +#define INTC_ICDISR3_IV3_VBUFERR1_SHIFT (9u) +#define INTC_ICDISR3_IV5_VBUFERR1_SHIFT (10u) +#define INTC_ICDISR3_IV6_VBUFERR1_SHIFT (11u) +#define INTC_ICDISR3_S0_WLINE1_SHIFT (12u) +#define INTC_ICDISR3_S1_VI_VSYNC1_SHIFT (13u) +#define INTC_ICDISR3_S1_LO_VSYNC1_SHIFT (14u) +#define INTC_ICDISR3_S1_VSYNCERR1_SHIFT (15u) +#define INTC_ICDISR3_S1_VFIELD1_SHIFT (16u) +#define INTC_ICDISR3_IV2_VBUFERR1_SHIFT (17u) +#define INTC_ICDISR3_IV4_VBUFERR1_SHIFT (18u) +#define INTC_ICDISR3_S1_WLINE1_SHIFT (19u) +#define INTC_ICDISR3_OIR_VI_VSYNC1_SHIFT (20u) +#define INTC_ICDISR3_OIR_LO_VSYNC1_SHIFT (21u) +#define INTC_ICDISR3_OIR_VLINE1_SHIFT (22u) +#define INTC_ICDISR3_OIR_VFIELD1_SHIFT (23u) +#define INTC_ICDISR3_IV7_VBUFERR1_SHIFT (24u) +#define INTC_ICDISR3_IV8_VBUFERR1_SHIFT (25u) +#define INTC_ICDISR3_IMRDI_SHIFT (27u) +#define INTC_ICDISR3_IMR2I0_SHIFT (28u) +#define INTC_ICDISR3_IMR2I1_SHIFT (29u) +#define INTC_ICDISR3_JEDI_SHIFT (30u) +#define INTC_ICDISR3_JDTI_SHIFT (31u) + +#define INTC_ICDISR4_CMP0_SHIFT (0u) +#define INTC_ICDISR4_CMP1_SHIFT (1u) +#define INTC_ICDISR4_INT0_SHIFT (2u) +#define INTC_ICDISR4_INT1_SHIFT (3u) +#define INTC_ICDISR4_INT2_SHIFT (4u) +#define INTC_ICDISR4_INT3_SHIFT (5u) +#define INTC_ICDISR4_OSTM0TINT_SHIFT (6u) +#define INTC_ICDISR4_OSTM1TINT_SHIFT (7u) +#define INTC_ICDISR4_CMI_SHIFT (8u) +#define INTC_ICDISR4_WTOUT_SHIFT (9u) +#define INTC_ICDISR4_ITI_SHIFT (10u) +#define INTC_ICDISR4_TGI0A_SHIFT (11u) +#define INTC_ICDISR4_TGI0B_SHIFT (12u) +#define INTC_ICDISR4_TGI0C_SHIFT (13u) +#define INTC_ICDISR4_TGI0D_SHIFT (14u) +#define INTC_ICDISR4_TGI0V_SHIFT (15u) +#define INTC_ICDISR4_TGI0E_SHIFT (16u) +#define INTC_ICDISR4_TGI0F_SHIFT (17u) +#define INTC_ICDISR4_TGI1A_SHIFT (18u) +#define INTC_ICDISR4_TGI1B_SHIFT (19u) +#define INTC_ICDISR4_TGI1V_SHIFT (20u) +#define INTC_ICDISR4_TGI1U_SHIFT (21u) +#define INTC_ICDISR4_TGI2A_SHIFT (22u) +#define INTC_ICDISR4_TGI2B_SHIFT (23u) +#define INTC_ICDISR4_TGI2V_SHIFT (24u) +#define INTC_ICDISR4_TGI2U_SHIFT (25u) +#define INTC_ICDISR4_TGI3A_SHIFT (26u) +#define INTC_ICDISR4_TGI3B_SHIFT (27u) +#define INTC_ICDISR4_TGI3C_SHIFT (28u) +#define INTC_ICDISR4_TGI3D_SHIFT (29u) +#define INTC_ICDISR4_TGI3V_SHIFT (30u) +#define INTC_ICDISR4_TGI4A_SHIFT (31u) + +#define INTC_ICDISR5_TGI4B_SHIFT (0u) +#define INTC_ICDISR5_TGI4C_SHIFT (1u) +#define INTC_ICDISR5_TGI4D_SHIFT (2u) +#define INTC_ICDISR5_TGI4V_SHIFT (3u) +#define INTC_ICDISR5_CMI1_SHIFT (4u) +#define INTC_ICDISR5_CMI2_SHIFT (5u) +#define INTC_ICDISR5_SGDEI0_SHIFT (6u) +#define INTC_ICDISR5_SGDEI1_SHIFT (7u) +#define INTC_ICDISR5_SGDEI2_SHIFT (8u) +#define INTC_ICDISR5_SGDEI3_SHIFT (9u) +#define INTC_ICDISR5_ADI_SHIFT (10u) +#define INTC_ICDISR5_LMTI_SHIFT (11u) +#define INTC_ICDISR5_SSII0_SHIFT (12u) +#define INTC_ICDISR5_SSIRXI0_SHIFT (13u) +#define INTC_ICDISR5_SSITXI0_SHIFT (14u) +#define INTC_ICDISR5_SSII1_SHIFT (15u) +#define INTC_ICDISR5_SSIRXI1_SHIFT (16u) +#define INTC_ICDISR5_SSITXI1_SHIFT (17u) +#define INTC_ICDISR5_SSII2_SHIFT (18u) +#define INTC_ICDISR5_SSIRTI2_SHIFT (19u) +#define INTC_ICDISR5_SSII3_SHIFT (20u) +#define INTC_ICDISR5_SSIRXI3_SHIFT (21u) +#define INTC_ICDISR5_SSITXI3_SHIFT (22u) +#define INTC_ICDISR5_SSII4_SHIFT (23u) +#define INTC_ICDISR5_SSIRTI4_SHIFT (24u) +#define INTC_ICDISR5_SSII5_SHIFT (25u) +#define INTC_ICDISR5_SSIRXI5_SHIFT (26u) +#define INTC_ICDISR5_SSITXI5_SHIFT (27u) +#define INTC_ICDISR5_SPDIFI_SHIFT (28u) +#define INTC_ICDISR5_INTIICTEI0_SHIFT (29u) +#define INTC_ICDISR5_INTIICRI0_SHIFT (30u) +#define INTC_ICDISR5_INTIICTI0_SHIFT (31u) + +#define INTC_ICDISR6_INTIICSPI0_SHIFT (0u) +#define INTC_ICDISR6_INTIICSTI0_SHIFT (1u) +#define INTC_ICDISR6_INTIICNAKI0_SHIFT (2u) +#define INTC_ICDISR6_INTIICALI0_SHIFT (3u) +#define INTC_ICDISR6_INTIICTMOI0_SHIFT (4u) +#define INTC_ICDISR6_INTIICTEI1_SHIFT (5u) +#define INTC_ICDISR6_INTIICRI1_SHIFT (6u) +#define INTC_ICDISR6_INTIICTI1_SHIFT (7u) +#define INTC_ICDISR6_INTIICSPI1_SHIFT (8u) +#define INTC_ICDISR6_INTIICSTI1_SHIFT (9u) +#define INTC_ICDISR6_INTIICNAKI1_SHIFT (10u) +#define INTC_ICDISR6_INTIICALI1_SHIFT (11u) +#define INTC_ICDISR6_INTIICTMOI1_SHIFT (12u) +#define INTC_ICDISR6_INTIICTEI2_SHIFT (13u) +#define INTC_ICDISR6_INTIICRI2_SHIFT (14u) +#define INTC_ICDISR6_INTIICTI2_SHIFT (15u) +#define INTC_ICDISR6_INTIICSPI2_SHIFT (16u) +#define INTC_ICDISR6_INTIICSTI2_SHIFT (17u) +#define INTC_ICDISR6_INTIICNAKI2_SHIFT (18u) +#define INTC_ICDISR6_INTIICALI2_SHIFT (19u) +#define INTC_ICDISR6_INTIICTMOI2_SHIFT (20u) +#define INTC_ICDISR6_INTIICTEI3_SHIFT (21u) +#define INTC_ICDISR6_INTIICRI3_SHIFT (22u) +#define INTC_ICDISR6_INTIICTI3_SHIFT (23u) +#define INTC_ICDISR6_INTIICSPI3_SHIFT (24u) +#define INTC_ICDISR6_INTIICSTI3_SHIFT (25u) +#define INTC_ICDISR6_INTIICNAKI3_SHIFT (26u) +#define INTC_ICDISR6_INTIICALI3_SHIFT (27u) +#define INTC_ICDISR6_INTIICTMOI3_SHIFT (28u) +#define INTC_ICDISR6_BRI0_SHIFT (29u) +#define INTC_ICDISR6_ERI0_SHIFT (30u) +#define INTC_ICDISR6_RXI0_SHIFT (31u) + +#define INTC_ICDISR7_TXI0_SHIFT (0u) +#define INTC_ICDISR7_BRI1_SHIFT (1u) +#define INTC_ICDISR7_ERI1_SHIFT (2u) +#define INTC_ICDISR7_RXI1_SHIFT (3u) +#define INTC_ICDISR7_TXI1_SHIFT (4u) +#define INTC_ICDISR7_BRI2_SHIFT (5u) +#define INTC_ICDISR7_ERI2_SHIFT (6u) +#define INTC_ICDISR7_RXI2_SHIFT (7u) +#define INTC_ICDISR7_TXI2_SHIFT (8u) +#define INTC_ICDISR7_BRI3_SHIFT (9u) +#define INTC_ICDISR7_ERI3_SHIFT (10u) +#define INTC_ICDISR7_RXI3_SHIFT (11u) +#define INTC_ICDISR7_TXI3_SHIFT (12u) +#define INTC_ICDISR7_BRI4_SHIFT (13u) +#define INTC_ICDISR7_ERI4_SHIFT (14u) +#define INTC_ICDISR7_RXI4_SHIFT (15u) +#define INTC_ICDISR7_TXI4_SHIFT (16u) +#define INTC_ICDISR7_BRI5_SHIFT (17u) +#define INTC_ICDISR7_ERI5_SHIFT (18u) +#define INTC_ICDISR7_RXI5_SHIFT (19u) +#define INTC_ICDISR7_TXI5_SHIFT (20u) +#define INTC_ICDISR7_BRI6_SHIFT (21u) +#define INTC_ICDISR7_ERI6_SHIFT (22u) +#define INTC_ICDISR7_RXI6_SHIFT (23u) +#define INTC_ICDISR7_TXI6_SHIFT (24u) +#define INTC_ICDISR7_BRI7_SHIFT (25u) +#define INTC_ICDISR7_ERI7_SHIFT (26u) +#define INTC_ICDISR7_RXI7_SHIFT (27u) +#define INTC_ICDISR7_TXI7_SHIFT (28u) +#define INTC_ICDISR7_INTRCANGERR_SHIFT (29u) +#define INTC_ICDISR7_INTRCANGRECC_SHIFT (30u) +#define INTC_ICDISR7_INTRCAN0REC_SHIFT (31u) + +#define INTC_ICDISR8_INTRCAN0ERR_SHIFT (0u) +#define INTC_ICDISR8_INTRCAN0TRX_SHIFT (1u) +#define INTC_ICDISR8_INTRCAN1REC_SHIFT (2u) +#define INTC_ICDISR8_INTRCAN1ERR_SHIFT (3u) +#define INTC_ICDISR8_INTRCAN1TRX_SHIFT (4u) +#define INTC_ICDISR8_INTRCAN2REC_SHIFT (5u) +#define INTC_ICDISR8_INTRCAN2ERR_SHIFT (6u) +#define INTC_ICDISR8_INTRCAN2TRX_SHIFT (7u) +#define INTC_ICDISR8_INTRCAN3REC_SHIFT (8u) +#define INTC_ICDISR8_INTRCAN3ERR_SHIFT (9u) +#define INTC_ICDISR8_INTRCAN3TRX_SHIFT (10u) +#define INTC_ICDISR8_INTRCAN4REC_SHIFT (11u) +#define INTC_ICDISR8_INTRCAN4ERR_SHIFT (12u) +#define INTC_ICDISR8_INTRCAN4TRX_SHIFT (13u) +#define INTC_ICDISR8_SPEI0_SHIFT (14u) +#define INTC_ICDISR8_SPRI0_SHIFT (15u) +#define INTC_ICDISR8_SPTI0_SHIFT (16u) +#define INTC_ICDISR8_SPEI1_SHIFT (17u) +#define INTC_ICDISR8_SPRI1_SHIFT (18u) +#define INTC_ICDISR8_SPTI1_SHIFT (19u) +#define INTC_ICDISR8_SPEI2_SHIFT (20u) +#define INTC_ICDISR8_SPRI2_SHIFT (21u) +#define INTC_ICDISR8_SPTI2_SHIFT (22u) +#define INTC_ICDISR8_SPEI3_SHIFT (23u) +#define INTC_ICDISR8_SPRI3_SHIFT (24u) +#define INTC_ICDISR8_SPTI3_SHIFT (25u) +#define INTC_ICDISR8_SPEI4_SHIFT (26u) +#define INTC_ICDISR8_SPRI4_SHIFT (27u) +#define INTC_ICDISR8_SPTI4_SHIFT (28u) +#define INTC_ICDISR8_IEBBTD_SHIFT (29u) +#define INTC_ICDISR8_IEBBTERR_SHIFT (30u) +#define INTC_ICDISR8_IEBBTSTA_SHIFT (31u) + +#define INTC_ICDISR9_IEBBTV_SHIFT (0u) +#define INTC_ICDISR9_ISY_SHIFT (1u) +#define INTC_ICDISR9_IERR_SHIFT (2u) +#define INTC_ICDISR9_ITARG_SHIFT (3u) +#define INTC_ICDISR9_ISEC_SHIFT (4u) +#define INTC_ICDISR9_IBUF_SHIFT (5u) +#define INTC_ICDISR9_IREADY_SHIFT (6u) +#define INTC_ICDISR9_FLSTE_SHIFT (7u) +#define INTC_ICDISR9_FLTENDI_SHIFT (8u) +#define INTC_ICDISR9_FLTREQ0I_SHIFT (9u) +#define INTC_ICDISR9_FLTREQ1I_SHIFT (10u) +#define INTC_ICDISR9_MMC0_SHIFT (11u) +#define INTC_ICDISR9_MMC1_SHIFT (12u) +#define INTC_ICDISR9_MMC2_SHIFT (13u) +#define INTC_ICDISR9_SDHI0_3_SHIFT (14u) +#define INTC_ICDISR9_SDHI0_0_SHIFT (15u) +#define INTC_ICDISR9_SDHI0_1_SHIFT (16u) +#define INTC_ICDISR9_SDHI1_3_SHIFT (17u) +#define INTC_ICDISR9_SDHI1_0_SHIFT (18u) +#define INTC_ICDISR9_SDHI1_1_SHIFT (19u) +#define INTC_ICDISR9_ARM_SHIFT (20u) +#define INTC_ICDISR9_PRD_SHIFT (21u) +#define INTC_ICDISR9_CUP_SHIFT (22u) +#define INTC_ICDISR9_SCUAI0_SHIFT (23u) +#define INTC_ICDISR9_SCUAI1_SHIFT (24u) +#define INTC_ICDISR9_SCUFDI0_SHIFT (25u) +#define INTC_ICDISR9_SCUFDI1_SHIFT (26u) +#define INTC_ICDISR9_SCUFDI2_SHIFT (27u) +#define INTC_ICDISR9_SCUFDI3_SHIFT (28u) +#define INTC_ICDISR9_SCUFUI0_SHIFT (29u) +#define INTC_ICDISR9_SCUFUI1_SHIFT (30u) +#define INTC_ICDISR9_SCUFUI2_SHIFT (31u) + +#define INTC_ICDISR10_SCUFUI3_SHIFT (0u) +#define INTC_ICDISR10_SCUDVI0_SHIFT (1u) +#define INTC_ICDISR10_SCUDVI1_SHIFT (2u) +#define INTC_ICDISR10_SCUDVI2_SHIFT (3u) +#define INTC_ICDISR10_SCUDVI3_SHIFT (4u) +#define INTC_ICDISR10_MLB_CINT_SHIFT (5u) +#define INTC_ICDISR10_MLB_SINT_SHIFT (6u) +#define INTC_ICDISR10_DRC0_SHIFT (7u) +#define INTC_ICDISR10_DRC1_SHIFT (8u) +#define INTC_ICDISR10_LINI0_INT_T_SHIFT (11u) +#define INTC_ICDISR10_LINI0_INT_R_SHIFT (12u) +#define INTC_ICDISR10_LINI0_INT_S_SHIFT (13u) +#define INTC_ICDISR10_LINI0_INT_M_SHIFT (14u) +#define INTC_ICDISR10_LINI1_INT_T_SHIFT (15u) +#define INTC_ICDISR10_LINI1_INT_R_SHIFT (16u) +#define INTC_ICDISR10_LINI1_INT_S_SHIFT (17u) +#define INTC_ICDISR10_LINI1_INT_M_SHIFT (18u) +#define INTC_ICDISR10_ERI0_SHIFT (27u) +#define INTC_ICDISR10_RXI0_SHIFT (28u) +#define INTC_ICDISR10_TXI0_SHIFT (29u) +#define INTC_ICDISR10_TEI0_SHIFT (30u) +#define INTC_ICDISR10_ERI1_SHIFT (31u) + +#define INTC_ICDISR11_RXI1_SHIFT (0u) +#define INTC_ICDISR11_TXI1_SHIFT (1u) +#define INTC_ICDISR11_TEI1_SHIFT (2u) +#define INTC_ICDISR11_AVBI_DATA_SHIFT (3u) +#define INTC_ICDISR11_AVBI_ERROR_SHIFT (4u) +#define INTC_ICDISR11_AVBI_MANAGE_SHIFT (5u) +#define INTC_ICDISR11_AVBI_MAC_SHIFT (6u) +#define INTC_ICDISR11_ETHERI_SHIFT (7u) +#define INTC_ICDISR11_CEUI_SHIFT (12u) +#define INTC_ICDISR11_H2XMLB_ERRINT_SHIFT (29u) +#define INTC_ICDISR11_H2XIC1_ERRINT_SHIFT (30u) +#define INTC_ICDISR11_X2HPERI1_ERRINT_SHIFT (31u) + +#define INTC_ICDISR12_X2HPERI2_ERRINT_SHIFT (0u) +#define INTC_ICDISR12_X2HPERI34_ERRINT_SHIFT (1u) +#define INTC_ICDISR12_X2HPERI5_ERRINT_SHIFT (2u) +#define INTC_ICDISR12_X2HPERI67_ERRINT_SHIFT (3u) +#define INTC_ICDISR12_X2HDBGR_ERRINT_SHIFT (4u) +#define INTC_ICDISR12_X2HBSC_ERRINT_SHIFT (5u) +#define INTC_ICDISR12_X2HSPI1_ERRINT_SHIFT (6u) +#define INTC_ICDISR12_X2HSPI2_ERRINT_SHIFT (7u) +#define INTC_ICDISR12_PRRI_SHIFT (8u) +#define INTC_ICDISR12_IFEI0_SHIFT (9u) +#define INTC_ICDISR12_OFFI0_SHIFT (10u) +#define INTC_ICDISR12_PFVEI0_SHIFT (11u) +#define INTC_ICDISR12_IFEI1_SHIFT (12u) +#define INTC_ICDISR12_OFFI1_SHIFT (13u) +#define INTC_ICDISR12_PFVEI1_SHIFT (14u) + +#define INTC_ICDISR13_TINT0_SHIFT (0u) +#define INTC_ICDISR13_TINT1_SHIFT (1u) +#define INTC_ICDISR13_TINT2_SHIFT (2u) +#define INTC_ICDISR13_TINT3_SHIFT (3u) +#define INTC_ICDISR13_TINT4_SHIFT (4u) +#define INTC_ICDISR13_TINT5_SHIFT (5u) +#define INTC_ICDISR13_TINT6_SHIFT (6u) +#define INTC_ICDISR13_TINT7_SHIFT (7u) +#define INTC_ICDISR13_TINT8_SHIFT (8u) +#define INTC_ICDISR13_TINT9_SHIFT (9u) +#define INTC_ICDISR13_TINT10_SHIFT (10u) +#define INTC_ICDISR13_TINT11_SHIFT (11u) +#define INTC_ICDISR13_TINT12_SHIFT (12u) +#define INTC_ICDISR13_TINT13_SHIFT (13u) +#define INTC_ICDISR13_TINT14_SHIFT (14u) +#define INTC_ICDISR13_TINT15_SHIFT (15u) +#define INTC_ICDISR13_TINT16_SHIFT (16u) +#define INTC_ICDISR13_TINT17_SHIFT (17u) +#define INTC_ICDISR13_TINT18_SHIFT (18u) +#define INTC_ICDISR13_TINT19_SHIFT (19u) +#define INTC_ICDISR13_TINT20_SHIFT (20u) +#define INTC_ICDISR13_TINT21_SHIFT (21u) +#define INTC_ICDISR13_TINT22_SHIFT (22u) +#define INTC_ICDISR13_TINT23_SHIFT (23u) +#define INTC_ICDISR13_TINT24_SHIFT (24u) +#define INTC_ICDISR13_TINT25_SHIFT (25u) +#define INTC_ICDISR13_TINT26_SHIFT (26u) +#define INTC_ICDISR13_TINT27_SHIFT (27u) +#define INTC_ICDISR13_TINT28_SHIFT (28u) +#define INTC_ICDISR13_TINT29_SHIFT (29u) +#define INTC_ICDISR13_TINT30_SHIFT (30u) +#define INTC_ICDISR13_TINT31_SHIFT (31u) + +#define INTC_ICDISR14_TINT32_SHIFT (0u) +#define INTC_ICDISR14_TINT33_SHIFT (1u) +#define INTC_ICDISR14_TINT34_SHIFT (2u) +#define INTC_ICDISR14_TINT35_SHIFT (3u) +#define INTC_ICDISR14_TINT36_SHIFT (4u) +#define INTC_ICDISR14_TINT37_SHIFT (5u) +#define INTC_ICDISR14_TINT38_SHIFT (6u) +#define INTC_ICDISR14_TINT39_SHIFT (7u) +#define INTC_ICDISR14_TINT40_SHIFT (8u) +#define INTC_ICDISR14_TINT41_SHIFT (9u) +#define INTC_ICDISR14_TINT42_SHIFT (10u) +#define INTC_ICDISR14_TINT43_SHIFT (11u) +#define INTC_ICDISR14_TINT44_SHIFT (12u) +#define INTC_ICDISR14_TINT45_SHIFT (13u) +#define INTC_ICDISR14_TINT46_SHIFT (14u) +#define INTC_ICDISR14_TINT47_SHIFT (15u) +#define INTC_ICDISR14_TINT48_SHIFT (16u) +#define INTC_ICDISR14_TINT49_SHIFT (17u) +#define INTC_ICDISR14_TINT50_SHIFT (18u) +#define INTC_ICDISR14_TINT51_SHIFT (19u) +#define INTC_ICDISR14_TINT52_SHIFT (20u) +#define INTC_ICDISR14_TINT53_SHIFT (21u) +#define INTC_ICDISR14_TINT54_SHIFT (22u) +#define INTC_ICDISR14_TINT55_SHIFT (23u) +#define INTC_ICDISR14_TINT56_SHIFT (24u) +#define INTC_ICDISR14_TINT57_SHIFT (25u) +#define INTC_ICDISR14_TINT58_SHIFT (26u) +#define INTC_ICDISR14_TINT59_SHIFT (27u) +#define INTC_ICDISR14_TINT60_SHIFT (28u) +#define INTC_ICDISR14_TINT61_SHIFT (29u) +#define INTC_ICDISR14_TINT62_SHIFT (30u) +#define INTC_ICDISR14_TINT63_SHIFT (31u) + +#define INTC_ICDISR15_TINT64_SHIFT (0u) +#define INTC_ICDISR15_TINT65_SHIFT (1u) +#define INTC_ICDISR15_TINT66_SHIFT (2u) +#define INTC_ICDISR15_TINT67_SHIFT (3u) +#define INTC_ICDISR15_TINT68_SHIFT (4u) +#define INTC_ICDISR15_TINT69_SHIFT (5u) +#define INTC_ICDISR15_TINT70_SHIFT (6u) +#define INTC_ICDISR15_TINT71_SHIFT (7u) +#define INTC_ICDISR15_TINT72_SHIFT (8u) +#define INTC_ICDISR15_TINT73_SHIFT (9u) +#define INTC_ICDISR15_TINT74_SHIFT (10u) +#define INTC_ICDISR15_TINT75_SHIFT (11u) +#define INTC_ICDISR15_TINT76_SHIFT (12u) +#define INTC_ICDISR15_TINT77_SHIFT (13u) +#define INTC_ICDISR15_TINT78_SHIFT (14u) +#define INTC_ICDISR15_TINT79_SHIFT (15u) +#define INTC_ICDISR15_TINT80_SHIFT (16u) +#define INTC_ICDISR15_TINT81_SHIFT (17u) +#define INTC_ICDISR15_TINT82_SHIFT (18u) +#define INTC_ICDISR15_TINT83_SHIFT (19u) +#define INTC_ICDISR15_TINT84_SHIFT (20u) +#define INTC_ICDISR15_TINT85_SHIFT (21u) +#define INTC_ICDISR15_TINT86_SHIFT (22u) +#define INTC_ICDISR15_TINT87_SHIFT (23u) +#define INTC_ICDISR15_TINT88_SHIFT (24u) +#define INTC_ICDISR15_TINT89_SHIFT (25u) +#define INTC_ICDISR15_TINT90_SHIFT (26u) +#define INTC_ICDISR15_TINT91_SHIFT (27u) +#define INTC_ICDISR15_TINT92_SHIFT (28u) +#define INTC_ICDISR15_TINT93_SHIFT (29u) +#define INTC_ICDISR15_TINT94_SHIFT (30u) +#define INTC_ICDISR15_TINT95_SHIFT (31u) + +#define INTC_ICDISR16_TINT96_SHIFT (0u) +#define INTC_ICDISR16_TINT97_SHIFT (1u) +#define INTC_ICDISR16_TINT98_SHIFT (2u) +#define INTC_ICDISR16_TINT99_SHIFT (3u) +#define INTC_ICDISR16_TINT100_SHIFT (4u) +#define INTC_ICDISR16_TINT101_SHIFT (5u) +#define INTC_ICDISR16_TINT102_SHIFT (6u) +#define INTC_ICDISR16_TINT103_SHIFT (7u) +#define INTC_ICDISR16_TINT104_SHIFT (8u) +#define INTC_ICDISR16_TINT105_SHIFT (9u) +#define INTC_ICDISR16_TINT106_SHIFT (10u) +#define INTC_ICDISR16_TINT107_SHIFT (11u) +#define INTC_ICDISR16_TINT108_SHIFT (12u) +#define INTC_ICDISR16_TINT109_SHIFT (13u) +#define INTC_ICDISR16_TINT110_SHIFT (14u) +#define INTC_ICDISR16_TINT111_SHIFT (15u) +#define INTC_ICDISR16_TINT112_SHIFT (16u) +#define INTC_ICDISR16_TINT113_SHIFT (17u) +#define INTC_ICDISR16_TINT114_SHIFT (18u) +#define INTC_ICDISR16_TINT115_SHIFT (19u) +#define INTC_ICDISR16_TINT116_SHIFT (20u) +#define INTC_ICDISR16_TINT117_SHIFT (21u) +#define INTC_ICDISR16_TINT118_SHIFT (22u) +#define INTC_ICDISR16_TINT119_SHIFT (23u) +#define INTC_ICDISR16_TINT120_SHIFT (24u) +#define INTC_ICDISR16_TINT121_SHIFT (25u) +#define INTC_ICDISR16_TINT122_SHIFT (26u) +#define INTC_ICDISR16_TINT123_SHIFT (27u) +#define INTC_ICDISR16_TINT124_SHIFT (28u) +#define INTC_ICDISR16_TINT125_SHIFT (29u) +#define INTC_ICDISR16_TINT126_SHIFT (30u) +#define INTC_ICDISR16_TINT127_SHIFT (31u) + +#define INTC_ICDISR17_TINT128_SHIFT (0u) +#define INTC_ICDISR17_TINT129_SHIFT (1u) +#define INTC_ICDISR17_TINT130_SHIFT (2u) +#define INTC_ICDISR17_TINT131_SHIFT (3u) +#define INTC_ICDISR17_TINT132_SHIFT (4u) +#define INTC_ICDISR17_TINT133_SHIFT (5u) +#define INTC_ICDISR17_TINT134_SHIFT (6u) +#define INTC_ICDISR17_TINT135_SHIFT (7u) +#define INTC_ICDISR17_TINT136_SHIFT (8u) +#define INTC_ICDISR17_TINT137_SHIFT (9u) +#define INTC_ICDISR17_TINT138_SHIFT (10u) +#define INTC_ICDISR17_TINT139_SHIFT (11u) +#define INTC_ICDISR17_TINT140_SHIFT (12u) +#define INTC_ICDISR17_TINT141_SHIFT (13u) +#define INTC_ICDISR17_TINT142_SHIFT (14u) +#define INTC_ICDISR17_TINT143_SHIFT (15u) +#define INTC_ICDISR17_TINT144_SHIFT (16u) +#define INTC_ICDISR17_TINT145_SHIFT (17u) +#define INTC_ICDISR17_TINT146_SHIFT (18u) +#define INTC_ICDISR17_TINT147_SHIFT (19u) +#define INTC_ICDISR17_TINT148_SHIFT (20u) +#define INTC_ICDISR17_TINT149_SHIFT (21u) +#define INTC_ICDISR17_TINT150_SHIFT (22u) +#define INTC_ICDISR17_TINT151_SHIFT (23u) +#define INTC_ICDISR17_TINT152_SHIFT (24u) +#define INTC_ICDISR17_TINT153_SHIFT (25u) +#define INTC_ICDISR17_TINT154_SHIFT (26u) +#define INTC_ICDISR17_TINT155_SHIFT (27u) +#define INTC_ICDISR17_TINT156_SHIFT (28u) +#define INTC_ICDISR17_TINT157_SHIFT (29u) +#define INTC_ICDISR17_TINT158_SHIFT (30u) +#define INTC_ICDISR17_TINT159_SHIFT (31u) + +#define INTC_ICDISR18_TINT160_SHIFT (0u) +#define INTC_ICDISR18_TINT161_SHIFT (1u) +#define INTC_ICDISR18_TINT162_SHIFT (2u) +#define INTC_ICDISR18_TINT163_SHIFT (3u) +#define INTC_ICDISR18_TINT164_SHIFT (4u) +#define INTC_ICDISR18_TINT165_SHIFT (5u) +#define INTC_ICDISR18_TINT166_SHIFT (6u) +#define INTC_ICDISR18_TINT167_SHIFT (7u) +#define INTC_ICDISR18_TINT168_SHIFT (8u) +#define INTC_ICDISR18_TINT169_SHIFT (9u) +#define INTC_ICDISR18_TINT170_SHIFT (10u) + +#define INTC_ICDISER0_SW0_SHIFT (0u) +#define INTC_ICDISER0_SW1_SHIFT (1u) +#define INTC_ICDISER0_SW2_SHIFT (2u) +#define INTC_ICDISER0_SW3_SHIFT (3u) +#define INTC_ICDISER0_SW4_SHIFT (4u) +#define INTC_ICDISER0_SW5_SHIFT (5u) +#define INTC_ICDISER0_SW6_SHIFT (6u) +#define INTC_ICDISER0_SW7_SHIFT (7u) +#define INTC_ICDISER0_SW8_SHIFT (8u) +#define INTC_ICDISER0_SW9_SHIFT (9u) +#define INTC_ICDISER0_SW10_SHIFT (10u) +#define INTC_ICDISER0_SW11_SHIFT (11u) +#define INTC_ICDISER0_SW12_SHIFT (12u) +#define INTC_ICDISER0_SW13_SHIFT (13u) +#define INTC_ICDISER0_SW14_SHIFT (14u) +#define INTC_ICDISER0_SW15_SHIFT (15u) +#define INTC_ICDISER0_PMUIRQ0_SHIFT (16u) +#define INTC_ICDISER0_COMMRX0_SHIFT (17u) +#define INTC_ICDISER0_COMMTX0_SHIFT (18u) +#define INTC_ICDISER0_CTIIRQ0_SHIFT (19u) + +#define INTC_ICDISER1_IRQ0_SHIFT (0u) +#define INTC_ICDISER1_IRQ1_SHIFT (1u) +#define INTC_ICDISER1_IRQ2_SHIFT (2u) +#define INTC_ICDISER1_IRQ3_SHIFT (3u) +#define INTC_ICDISER1_IRQ4_SHIFT (4u) +#define INTC_ICDISER1_IRQ5_SHIFT (5u) +#define INTC_ICDISER1_IRQ6_SHIFT (6u) +#define INTC_ICDISER1_IRQ7_SHIFT (7u) +#define INTC_ICDISER1_PL310ERR_SHIFT (8u) +#define INTC_ICDISER1_DMAINT0_SHIFT (9u) +#define INTC_ICDISER1_DMAINT1_SHIFT (10u) +#define INTC_ICDISER1_DMAINT2_SHIFT (11u) +#define INTC_ICDISER1_DMAINT3_SHIFT (12u) +#define INTC_ICDISER1_DMAINT4_SHIFT (13u) +#define INTC_ICDISER1_DMAINT5_SHIFT (14u) +#define INTC_ICDISER1_DMAINT6_SHIFT (15u) +#define INTC_ICDISER1_DMAINT7_SHIFT (16u) +#define INTC_ICDISER1_DMAINT8_SHIFT (17u) +#define INTC_ICDISER1_DMAINT9_SHIFT (18u) +#define INTC_ICDISER1_DMAINT10_SHIFT (19u) +#define INTC_ICDISER1_DMAINT11_SHIFT (20u) +#define INTC_ICDISER1_DMAINT12_SHIFT (21u) +#define INTC_ICDISER1_DMAINT13_SHIFT (22u) +#define INTC_ICDISER1_DMAINT14_SHIFT (23u) +#define INTC_ICDISER1_DMAINT15_SHIFT (24u) +#define INTC_ICDISER1_DMAERR_SHIFT (25u) + +#define INTC_ICDISER2_USBI0_SHIFT (9u) +#define INTC_ICDISER2_USBI1_SHIFT (10u) +#define INTC_ICDISER2_S0_VI_VSYNC0_SHIFT (11u) +#define INTC_ICDISER2_S0_LO_VSYNC0_SHIFT (12u) +#define INTC_ICDISER2_S0_VSYNCERR0_SHIFT (13u) +#define INTC_ICDISER2_GR3_VLINE0_SHIFT (14u) +#define INTC_ICDISER2_S0_VFIELD0_SHIFT (15u) +#define INTC_ICDISER2_IV1_VBUFERR0_SHIFT (16u) +#define INTC_ICDISER2_IV3_VBUFERR0_SHIFT (17u) +#define INTC_ICDISER2_IV5_VBUFERR0_SHIFT (18u) +#define INTC_ICDISER2_IV6_VBUFERR0_SHIFT (19u) +#define INTC_ICDISER2_S0_WLINE0_SHIFT (20u) +#define INTC_ICDISER2_S1_VI_VSYNC0_SHIFT (21u) +#define INTC_ICDISER2_S1_LO_VSYNC0_SHIFT (22u) +#define INTC_ICDISER2_S1_VSYNCERR0_SHIFT (23u) +#define INTC_ICDISER2_S1_VFIELD0_SHIFT (24u) +#define INTC_ICDISER2_IV2_VBUFERR0_SHIFT (25u) +#define INTC_ICDISER2_IV4_VBUFERR0_SHIFT (26u) +#define INTC_ICDISER2_S1_WLINE0_SHIFT (27u) +#define INTC_ICDISER2_OIR_VI_VSYNC0_SHIFT (28u) +#define INTC_ICDISER2_OIR_LO_VSYNC0_SHIFT (29u) +#define INTC_ICDISER2_OIR_VSYNCERR0_SHIFT (30u) +#define INTC_ICDISER2_OIR_VFIELD0_SHIFT (31u) + +#define INTC_ICDISER3_IV7_VBUFERR0_SHIFT (0u) +#define INTC_ICDISER3_IV8_VBUFERR0_SHIFT (1u) +#define INTC_ICDISER3_S0_VI_VSYNC1_SHIFT (3u) +#define INTC_ICDISER3_S0_LO_VSYNC1_SHIFT (4u) +#define INTC_ICDISER3_S0_VSYNCERR1_SHIFT (5u) +#define INTC_ICDISER3_GR3_VLINE1_SHIFT (6u) +#define INTC_ICDISER3_S0_VFIELD1_SHIFT (7u) +#define INTC_ICDISER3_IV1_VBUFERR1_SHIFT (8u) +#define INTC_ICDISER3_IV3_VBUFERR1_SHIFT (9u) +#define INTC_ICDISER3_IV5_VBUFERR1_SHIFT (10u) +#define INTC_ICDISER3_IV6_VBUFERR1_SHIFT (11u) +#define INTC_ICDISER3_S0_WLINE1_SHIFT (12u) +#define INTC_ICDISER3_S1_VI_VSYNC1_SHIFT (13u) +#define INTC_ICDISER3_S1_LO_VSYNC1_SHIFT (14u) +#define INTC_ICDISER3_S1_VSYNCERR1_SHIFT (15u) +#define INTC_ICDISER3_S1_VFIELD1_SHIFT (16u) +#define INTC_ICDISER3_IV2_VBUFERR1_SHIFT (17u) +#define INTC_ICDISER3_IV4_VBUFERR1_SHIFT (18u) +#define INTC_ICDISER3_S1_WLINE1_SHIFT (19u) +#define INTC_ICDISER3_OIR_VI_VSYNC1_SHIFT (20u) +#define INTC_ICDISER3_OIR_LO_VSYNC1_SHIFT (21u) +#define INTC_ICDISER3_OIR_VLINE1_SHIFT (22u) +#define INTC_ICDISER3_OIR_VFIELD1_SHIFT (23u) +#define INTC_ICDISER3_IV7_VBUFERR1_SHIFT (24u) +#define INTC_ICDISER3_IV8_VBUFERR1_SHIFT (25u) +#define INTC_ICDISER3_IMRDI_SHIFT (27u) +#define INTC_ICDISER3_IMR2I0_SHIFT (28u) +#define INTC_ICDISER3_IMR2I1_SHIFT (29u) +#define INTC_ICDISER3_JEDI_SHIFT (30u) +#define INTC_ICDISER3_JDTI_SHIFT (31u) + +#define INTC_ICDISER4_CMP0_SHIFT (0u) +#define INTC_ICDISER4_CMP1_SHIFT (1u) +#define INTC_ICDISER4_INT0_SHIFT (2u) +#define INTC_ICDISER4_INT1_SHIFT (3u) +#define INTC_ICDISER4_INT2_SHIFT (4u) +#define INTC_ICDISER4_INT3_SHIFT (5u) +#define INTC_ICDISER4_OSTM0TINT_SHIFT (6u) +#define INTC_ICDISER4_OSTM1TINT_SHIFT (7u) +#define INTC_ICDISER4_CMI_SHIFT (8u) +#define INTC_ICDISER4_WTOUT_SHIFT (9u) +#define INTC_ICDISER4_ITI_SHIFT (10u) +#define INTC_ICDISER4_TGI0A_SHIFT (11u) +#define INTC_ICDISER4_TGI0B_SHIFT (12u) +#define INTC_ICDISER4_TGI0C_SHIFT (13u) +#define INTC_ICDISER4_TGI0D_SHIFT (14u) +#define INTC_ICDISER4_TGI0V_SHIFT (15u) +#define INTC_ICDISER4_TGI0E_SHIFT (16u) +#define INTC_ICDISER4_TGI0F_SHIFT (17u) +#define INTC_ICDISER4_TGI1A_SHIFT (18u) +#define INTC_ICDISER4_TGI1B_SHIFT (19u) +#define INTC_ICDISER4_TGI1V_SHIFT (20u) +#define INTC_ICDISER4_TGI1U_SHIFT (21u) +#define INTC_ICDISER4_TGI2A_SHIFT (22u) +#define INTC_ICDISER4_TGI2B_SHIFT (23u) +#define INTC_ICDISER4_TGI2V_SHIFT (24u) +#define INTC_ICDISER4_TGI2U_SHIFT (25u) +#define INTC_ICDISER4_TGI3A_SHIFT (26u) +#define INTC_ICDISER4_TGI3B_SHIFT (27u) +#define INTC_ICDISER4_TGI3C_SHIFT (28u) +#define INTC_ICDISER4_TGI3D_SHIFT (29u) +#define INTC_ICDISER4_TGI3V_SHIFT (30u) +#define INTC_ICDISER4_TGI4A_SHIFT (31u) + +#define INTC_ICDISER5_TGI4B_SHIFT (0u) +#define INTC_ICDISER5_TGI4C_SHIFT (1u) +#define INTC_ICDISER5_TGI4D_SHIFT (2u) +#define INTC_ICDISER5_TGI4V_SHIFT (3u) +#define INTC_ICDISER5_CMI1_SHIFT (4u) +#define INTC_ICDISER5_CMI2_SHIFT (5u) +#define INTC_ICDISER5_SGDEI0_SHIFT (6u) +#define INTC_ICDISER5_SGDEI1_SHIFT (7u) +#define INTC_ICDISER5_SGDEI2_SHIFT (8u) +#define INTC_ICDISER5_SGDEI3_SHIFT (9u) +#define INTC_ICDISER5_ADI_SHIFT (10u) +#define INTC_ICDISER5_LMTI_SHIFT (11u) +#define INTC_ICDISER5_SSII0_SHIFT (12u) +#define INTC_ICDISER5_SSIRXI0_SHIFT (13u) +#define INTC_ICDISER5_SSITXI0_SHIFT (14u) +#define INTC_ICDISER5_SSII1_SHIFT (15u) +#define INTC_ICDISER5_SSIRXI1_SHIFT (16u) +#define INTC_ICDISER5_SSITXI1_SHIFT (17u) +#define INTC_ICDISER5_SSII2_SHIFT (18u) +#define INTC_ICDISER5_SSIRTI2_SHIFT (19u) +#define INTC_ICDISER5_SSII3_SHIFT (20u) +#define INTC_ICDISER5_SSIRXI3_SHIFT (21u) +#define INTC_ICDISER5_SSITXI3_SHIFT (22u) +#define INTC_ICDISER5_SSII4_SHIFT (23u) +#define INTC_ICDISER5_SSIRTI4_SHIFT (24u) +#define INTC_ICDISER5_SSII5_SHIFT (25u) +#define INTC_ICDISER5_SSIRXI5_SHIFT (26u) +#define INTC_ICDISER5_SSITXI5_SHIFT (27u) +#define INTC_ICDISER5_SPDIFI_SHIFT (28u) +#define INTC_ICDISER5_INTIICTEI0_SHIFT (29u) +#define INTC_ICDISER5_INTIICRI0_SHIFT (30u) +#define INTC_ICDISER5_INTIICTI0_SHIFT (31u) + +#define INTC_ICDISER6_INTIICSPI0_SHIFT (0u) +#define INTC_ICDISER6_INTIICSTI0_SHIFT (1u) +#define INTC_ICDISER6_INTIICNAKI0_SHIFT (2u) +#define INTC_ICDISER6_INTIICALI0_SHIFT (3u) +#define INTC_ICDISER6_INTIICTMOI0_SHIFT (4u) +#define INTC_ICDISER6_INTIICTEI1_SHIFT (5u) +#define INTC_ICDISER6_INTIICRI1_SHIFT (6u) +#define INTC_ICDISER6_INTIICTI1_SHIFT (7u) +#define INTC_ICDISER6_INTIICSPI1_SHIFT (8u) +#define INTC_ICDISER6_INTIICSTI1_SHIFT (9u) +#define INTC_ICDISER6_INTIICNAKI1_SHIFT (10u) +#define INTC_ICDISER6_INTIICALI1_SHIFT (11u) +#define INTC_ICDISER6_INTIICTMOI1_SHIFT (12u) +#define INTC_ICDISER6_INTIICTEI2_SHIFT (13u) +#define INTC_ICDISER6_INTIICRI2_SHIFT (14u) +#define INTC_ICDISER6_INTIICTI2_SHIFT (15u) +#define INTC_ICDISER6_INTIICSPI2_SHIFT (16u) +#define INTC_ICDISER6_INTIICSTI2_SHIFT (17u) +#define INTC_ICDISER6_INTIICNAKI2_SHIFT (18u) +#define INTC_ICDISER6_INTIICALI2_SHIFT (19u) +#define INTC_ICDISER6_INTIICTMOI2_SHIFT (20u) +#define INTC_ICDISER6_INTIICTEI3_SHIFT (21u) +#define INTC_ICDISER6_INTIICRI3_SHIFT (22u) +#define INTC_ICDISER6_INTIICTI3_SHIFT (23u) +#define INTC_ICDISER6_INTIICSPI3_SHIFT (24u) +#define INTC_ICDISER6_INTIICSTI3_SHIFT (25u) +#define INTC_ICDISER6_INTIICNAKI3_SHIFT (26u) +#define INTC_ICDISER6_INTIICALI3_SHIFT (27u) +#define INTC_ICDISER6_INTIICTMOI3_SHIFT (28u) +#define INTC_ICDISER6_BRI0_SHIFT (29u) +#define INTC_ICDISER6_ERI0_SHIFT (30u) +#define INTC_ICDISER6_RXI0_SHIFT (31u) + +#define INTC_ICDISER7_TXI0_SHIFT (0u) +#define INTC_ICDISER7_BRI1_SHIFT (1u) +#define INTC_ICDISER7_ERI1_SHIFT (2u) +#define INTC_ICDISER7_RXI1_SHIFT (3u) +#define INTC_ICDISER7_TXI1_SHIFT (4u) +#define INTC_ICDISER7_BRI2_SHIFT (5u) +#define INTC_ICDISER7_ERI2_SHIFT (6u) +#define INTC_ICDISER7_RXI2_SHIFT (7u) +#define INTC_ICDISER7_TXI2_SHIFT (8u) +#define INTC_ICDISER7_BRI3_SHIFT (9u) +#define INTC_ICDISER7_ERI3_SHIFT (10u) +#define INTC_ICDISER7_RXI3_SHIFT (11u) +#define INTC_ICDISER7_TXI3_SHIFT (12u) +#define INTC_ICDISER7_BRI4_SHIFT (13u) +#define INTC_ICDISER7_ERI4_SHIFT (14u) +#define INTC_ICDISER7_RXI4_SHIFT (15u) +#define INTC_ICDISER7_TXI4_SHIFT (16u) +#define INTC_ICDISER7_BRI5_SHIFT (17u) +#define INTC_ICDISER7_ERI5_SHIFT (18u) +#define INTC_ICDISER7_RXI5_SHIFT (19u) +#define INTC_ICDISER7_TXI5_SHIFT (20u) +#define INTC_ICDISER7_BRI6_SHIFT (21u) +#define INTC_ICDISER7_ERI6_SHIFT (22u) +#define INTC_ICDISER7_RXI6_SHIFT (23u) +#define INTC_ICDISER7_TXI6_SHIFT (24u) +#define INTC_ICDISER7_BRI7_SHIFT (25u) +#define INTC_ICDISER7_ERI7_SHIFT (26u) +#define INTC_ICDISER7_RXI7_SHIFT (27u) +#define INTC_ICDISER7_TXI7_SHIFT (28u) +#define INTC_ICDISER7_INTRCANGERR_SHIFT (29u) +#define INTC_ICDISER7_INTRCANGRECC_SHIFT (30u) +#define INTC_ICDISER7_INTRCAN0REC_SHIFT (31u) + +#define INTC_ICDISER8_INTRCAN0ERR_SHIFT (0u) +#define INTC_ICDISER8_INTRCAN0TRX_SHIFT (1u) +#define INTC_ICDISER8_INTRCAN1REC_SHIFT (2u) +#define INTC_ICDISER8_INTRCAN1ERR_SHIFT (3u) +#define INTC_ICDISER8_INTRCAN1TRX_SHIFT (4u) +#define INTC_ICDISER8_INTRCAN2REC_SHIFT (5u) +#define INTC_ICDISER8_INTRCAN2ERR_SHIFT (6u) +#define INTC_ICDISER8_INTRCAN2TRX_SHIFT (7u) +#define INTC_ICDISER8_INTRCAN3REC_SHIFT (8u) +#define INTC_ICDISER8_INTRCAN3ERR_SHIFT (9u) +#define INTC_ICDISER8_INTRCAN3TRX_SHIFT (10u) +#define INTC_ICDISER8_INTRCAN4REC_SHIFT (11u) +#define INTC_ICDISER8_INTRCAN4ERR_SHIFT (12u) +#define INTC_ICDISER8_INTRCAN4TRX_SHIFT (13u) +#define INTC_ICDISER8_SPEI0_SHIFT (14u) +#define INTC_ICDISER8_SPRI0_SHIFT (15u) +#define INTC_ICDISER8_SPTI0_SHIFT (16u) +#define INTC_ICDISER8_SPEI1_SHIFT (17u) +#define INTC_ICDISER8_SPRI1_SHIFT (18u) +#define INTC_ICDISER8_SPTI1_SHIFT (19u) +#define INTC_ICDISER8_SPEI2_SHIFT (20u) +#define INTC_ICDISER8_SPRI2_SHIFT (21u) +#define INTC_ICDISER8_SPTI2_SHIFT (22u) +#define INTC_ICDISER8_SPEI3_SHIFT (23u) +#define INTC_ICDISER8_SPRI3_SHIFT (24u) +#define INTC_ICDISER8_SPTI3_SHIFT (25u) +#define INTC_ICDISER8_SPEI4_SHIFT (26u) +#define INTC_ICDISER8_SPRI4_SHIFT (27u) +#define INTC_ICDISER8_SPTI4_SHIFT (28u) +#define INTC_ICDISER8_IEBBTD_SHIFT (29u) +#define INTC_ICDISER8_IEBBTERR_SHIFT (30u) +#define INTC_ICDISER8_IEBBTSTA_SHIFT (31u) + +#define INTC_ICDISER9_IEBBTV_SHIFT (0u) +#define INTC_ICDISER9_ISY_SHIFT (1u) +#define INTC_ICDISER9_IERR_SHIFT (2u) +#define INTC_ICDISER9_ITARG_SHIFT (3u) +#define INTC_ICDISER9_ISEC_SHIFT (4u) +#define INTC_ICDISER9_IBUF_SHIFT (5u) +#define INTC_ICDISER9_IREADY_SHIFT (6u) +#define INTC_ICDISER9_FLSTE_SHIFT (7u) +#define INTC_ICDISER9_FLTENDI_SHIFT (8u) +#define INTC_ICDISER9_FLTREQ0I_SHIFT (9u) +#define INTC_ICDISER9_FLTREQ1I_SHIFT (10u) +#define INTC_ICDISER9_MMC0_SHIFT (11u) +#define INTC_ICDISER9_MMC1_SHIFT (12u) +#define INTC_ICDISER9_MMC2_SHIFT (13u) +#define INTC_ICDISER9_SDHI0_3_SHIFT (14u) +#define INTC_ICDISER9_SDHI0_0_SHIFT (15u) +#define INTC_ICDISER9_SDHI0_1_SHIFT (16u) +#define INTC_ICDISER9_SDHI1_3_SHIFT (17u) +#define INTC_ICDISER9_SDHI1_0_SHIFT (18u) +#define INTC_ICDISER9_SDHI1_1_SHIFT (19u) +#define INTC_ICDISER9_ARM_SHIFT (20u) +#define INTC_ICDISER9_PRD_SHIFT (21u) +#define INTC_ICDISER9_CUP_SHIFT (22u) +#define INTC_ICDISER9_SCUAI0_SHIFT (23u) +#define INTC_ICDISER9_SCUAI1_SHIFT (24u) +#define INTC_ICDISER9_SCUFDI0_SHIFT (25u) +#define INTC_ICDISER9_SCUFDI1_SHIFT (26u) +#define INTC_ICDISER9_SCUFDI2_SHIFT (27u) +#define INTC_ICDISER9_SCUFDI3_SHIFT (28u) +#define INTC_ICDISER9_SCUFUI0_SHIFT (29u) +#define INTC_ICDISER9_SCUFUI1_SHIFT (30u) +#define INTC_ICDISER9_SCUFUI2_SHIFT (31u) + +#define INTC_ICDISER10_SCUFUI3_SHIFT (0u) +#define INTC_ICDISER10_SCUDVI0_SHIFT (1u) +#define INTC_ICDISER10_SCUDVI1_SHIFT (2u) +#define INTC_ICDISER10_SCUDVI2_SHIFT (3u) +#define INTC_ICDISER10_SCUDVI3_SHIFT (4u) +#define INTC_ICDISER10_MLB_CINT_SHIFT (5u) +#define INTC_ICDISER10_MLB_SINT_SHIFT (6u) +#define INTC_ICDISER10_DRC0_SHIFT (7u) +#define INTC_ICDISER10_DRC1_SHIFT (8u) +#define INTC_ICDISER10_LINI0_INT_T_SHIFT (11u) +#define INTC_ICDISER10_LINI0_INT_R_SHIFT (12u) +#define INTC_ICDISER10_LINI0_INT_S_SHIFT (13u) +#define INTC_ICDISER10_LINI0_INT_M_SHIFT (14u) +#define INTC_ICDISER10_LINI1_INT_T_SHIFT (15u) +#define INTC_ICDISER10_LINI1_INT_R_SHIFT (16u) +#define INTC_ICDISER10_LINI1_INT_S_SHIFT (17u) +#define INTC_ICDISER10_LINI1_INT_M_SHIFT (18u) +#define INTC_ICDISER10_ERI0_SHIFT (27u) +#define INTC_ICDISER10_RXI0_SHIFT (28u) +#define INTC_ICDISER10_TXI0_SHIFT (29u) +#define INTC_ICDISER10_TEI0_SHIFT (30u) +#define INTC_ICDISER10_ERI1_SHIFT (31u) + +#define INTC_ICDISER11_RXI1_SHIFT (0u) +#define INTC_ICDISER11_TXI1_SHIFT (1u) +#define INTC_ICDISER11_TEI1_SHIFT (2u) +#define INTC_ICDISER11_AVBI_DATA_SHIFT (3u) +#define INTC_ICDISER11_AVBI_ERROR_SHIFT (4u) +#define INTC_ICDISER11_AVBI_MANAGE_SHIFT (5u) +#define INTC_ICDISER11_AVBI_MAC_SHIFT (6u) +#define INTC_ICDISER11_ETHERI_SHIFT (7u) +#define INTC_ICDISER11_CEUI_SHIFT (12u) +#define INTC_ICDISER11_H2XMLB_ERRINT_SHIFT (29u) +#define INTC_ICDISER11_H2XIC1_ERRINT_SHIFT (30u) +#define INTC_ICDISER11_X2HPERI1_ERRINT_SHIFT (31u) + +#define INTC_ICDISER12_X2HPERI2_ERRINT_SHIFT (0u) +#define INTC_ICDISER12_X2HPERI34_ERRINT_SHIFT (1u) +#define INTC_ICDISER12_X2HPERI5_ERRINT_SHIFT (2u) +#define INTC_ICDISER12_X2HPERI67_ERRINT_SHIFT (3u) +#define INTC_ICDISER12_X2HDBGR_ERRINT_SHIFT (4u) +#define INTC_ICDISER12_X2HBSC_ERRINT_SHIFT (5u) +#define INTC_ICDISER12_X2HSPI1_ERRINT_SHIFT (6u) +#define INTC_ICDISER12_X2HSPI2_ERRINT_SHIFT (7u) +#define INTC_ICDISER12_PRRI_SHIFT (8u) +#define INTC_ICDISER12_IFEI0_SHIFT (9u) +#define INTC_ICDISER12_OFFI0_SHIFT (10u) +#define INTC_ICDISER12_PFVEI0_SHIFT (11u) +#define INTC_ICDISER12_IFEI1_SHIFT (12u) +#define INTC_ICDISER12_OFFI1_SHIFT (13u) +#define INTC_ICDISER12_PFVEI1_SHIFT (14u) + +#define INTC_ICDISER13_TINT0_SHIFT (0u) +#define INTC_ICDISER13_TINT1_SHIFT (1u) +#define INTC_ICDISER13_TINT2_SHIFT (2u) +#define INTC_ICDISER13_TINT3_SHIFT (3u) +#define INTC_ICDISER13_TINT4_SHIFT (4u) +#define INTC_ICDISER13_TINT5_SHIFT (5u) +#define INTC_ICDISER13_TINT6_SHIFT (6u) +#define INTC_ICDISER13_TINT7_SHIFT (7u) +#define INTC_ICDISER13_TINT8_SHIFT (8u) +#define INTC_ICDISER13_TINT9_SHIFT (9u) +#define INTC_ICDISER13_TINT10_SHIFT (10u) +#define INTC_ICDISER13_TINT11_SHIFT (11u) +#define INTC_ICDISER13_TINT12_SHIFT (12u) +#define INTC_ICDISER13_TINT13_SHIFT (13u) +#define INTC_ICDISER13_TINT14_SHIFT (14u) +#define INTC_ICDISER13_TINT15_SHIFT (15u) +#define INTC_ICDISER13_TINT16_SHIFT (16u) +#define INTC_ICDISER13_TINT17_SHIFT (17u) +#define INTC_ICDISER13_TINT18_SHIFT (18u) +#define INTC_ICDISER13_TINT19_SHIFT (19u) +#define INTC_ICDISER13_TINT20_SHIFT (20u) +#define INTC_ICDISER13_TINT21_SHIFT (21u) +#define INTC_ICDISER13_TINT22_SHIFT (22u) +#define INTC_ICDISER13_TINT23_SHIFT (23u) +#define INTC_ICDISER13_TINT24_SHIFT (24u) +#define INTC_ICDISER13_TINT25_SHIFT (25u) +#define INTC_ICDISER13_TINT26_SHIFT (26u) +#define INTC_ICDISER13_TINT27_SHIFT (27u) +#define INTC_ICDISER13_TINT28_SHIFT (28u) +#define INTC_ICDISER13_TINT29_SHIFT (29u) +#define INTC_ICDISER13_TINT30_SHIFT (30u) +#define INTC_ICDISER13_TINT31_SHIFT (31u) + +#define INTC_ICDISER14_TINT32_SHIFT (0u) +#define INTC_ICDISER14_TINT33_SHIFT (1u) +#define INTC_ICDISER14_TINT34_SHIFT (2u) +#define INTC_ICDISER14_TINT35_SHIFT (3u) +#define INTC_ICDISER14_TINT36_SHIFT (4u) +#define INTC_ICDISER14_TINT37_SHIFT (5u) +#define INTC_ICDISER14_TINT38_SHIFT (6u) +#define INTC_ICDISER14_TINT39_SHIFT (7u) +#define INTC_ICDISER14_TINT40_SHIFT (8u) +#define INTC_ICDISER14_TINT41_SHIFT (9u) +#define INTC_ICDISER14_TINT42_SHIFT (10u) +#define INTC_ICDISER14_TINT43_SHIFT (11u) +#define INTC_ICDISER14_TINT44_SHIFT (12u) +#define INTC_ICDISER14_TINT45_SHIFT (13u) +#define INTC_ICDISER14_TINT46_SHIFT (14u) +#define INTC_ICDISER14_TINT47_SHIFT (15u) +#define INTC_ICDISER14_TINT48_SHIFT (16u) +#define INTC_ICDISER14_TINT49_SHIFT (17u) +#define INTC_ICDISER14_TINT50_SHIFT (18u) +#define INTC_ICDISER14_TINT51_SHIFT (19u) +#define INTC_ICDISER14_TINT52_SHIFT (20u) +#define INTC_ICDISER14_TINT53_SHIFT (21u) +#define INTC_ICDISER14_TINT54_SHIFT (22u) +#define INTC_ICDISER14_TINT55_SHIFT (23u) +#define INTC_ICDISER14_TINT56_SHIFT (24u) +#define INTC_ICDISER14_TINT57_SHIFT (25u) +#define INTC_ICDISER14_TINT58_SHIFT (26u) +#define INTC_ICDISER14_TINT59_SHIFT (27u) +#define INTC_ICDISER14_TINT60_SHIFT (28u) +#define INTC_ICDISER14_TINT61_SHIFT (29u) +#define INTC_ICDISER14_TINT62_SHIFT (30u) +#define INTC_ICDISER14_TINT63_SHIFT (31u) + +#define INTC_ICDISER15_TINT64_SHIFT (0u) +#define INTC_ICDISER15_TINT65_SHIFT (1u) +#define INTC_ICDISER15_TINT66_SHIFT (2u) +#define INTC_ICDISER15_TINT67_SHIFT (3u) +#define INTC_ICDISER15_TINT68_SHIFT (4u) +#define INTC_ICDISER15_TINT69_SHIFT (5u) +#define INTC_ICDISER15_TINT70_SHIFT (6u) +#define INTC_ICDISER15_TINT71_SHIFT (7u) +#define INTC_ICDISER15_TINT72_SHIFT (8u) +#define INTC_ICDISER15_TINT73_SHIFT (9u) +#define INTC_ICDISER15_TINT74_SHIFT (10u) +#define INTC_ICDISER15_TINT75_SHIFT (11u) +#define INTC_ICDISER15_TINT76_SHIFT (12u) +#define INTC_ICDISER15_TINT77_SHIFT (13u) +#define INTC_ICDISER15_TINT78_SHIFT (14u) +#define INTC_ICDISER15_TINT79_SHIFT (15u) +#define INTC_ICDISER15_TINT80_SHIFT (16u) +#define INTC_ICDISER15_TINT81_SHIFT (17u) +#define INTC_ICDISER15_TINT82_SHIFT (18u) +#define INTC_ICDISER15_TINT83_SHIFT (19u) +#define INTC_ICDISER15_TINT84_SHIFT (20u) +#define INTC_ICDISER15_TINT85_SHIFT (21u) +#define INTC_ICDISER15_TINT86_SHIFT (22u) +#define INTC_ICDISER15_TINT87_SHIFT (23u) +#define INTC_ICDISER15_TINT88_SHIFT (24u) +#define INTC_ICDISER15_TINT89_SHIFT (25u) +#define INTC_ICDISER15_TINT90_SHIFT (26u) +#define INTC_ICDISER15_TINT91_SHIFT (27u) +#define INTC_ICDISER15_TINT92_SHIFT (28u) +#define INTC_ICDISER15_TINT93_SHIFT (29u) +#define INTC_ICDISER15_TINT94_SHIFT (30u) +#define INTC_ICDISER15_TINT95_SHIFT (31u) + +#define INTC_ICDISER16_TINT96_SHIFT (0u) +#define INTC_ICDISER16_TINT97_SHIFT (1u) +#define INTC_ICDISER16_TINT98_SHIFT (2u) +#define INTC_ICDISER16_TINT99_SHIFT (3u) +#define INTC_ICDISER16_TINT100_SHIFT (4u) +#define INTC_ICDISER16_TINT101_SHIFT (5u) +#define INTC_ICDISER16_TINT102_SHIFT (6u) +#define INTC_ICDISER16_TINT103_SHIFT (7u) +#define INTC_ICDISER16_TINT104_SHIFT (8u) +#define INTC_ICDISER16_TINT105_SHIFT (9u) +#define INTC_ICDISER16_TINT106_SHIFT (10u) +#define INTC_ICDISER16_TINT107_SHIFT (11u) +#define INTC_ICDISER16_TINT108_SHIFT (12u) +#define INTC_ICDISER16_TINT109_SHIFT (13u) +#define INTC_ICDISER16_TINT110_SHIFT (14u) +#define INTC_ICDISER16_TINT111_SHIFT (15u) +#define INTC_ICDISER16_TINT112_SHIFT (16u) +#define INTC_ICDISER16_TINT113_SHIFT (17u) +#define INTC_ICDISER16_TINT114_SHIFT (18u) +#define INTC_ICDISER16_TINT115_SHIFT (19u) +#define INTC_ICDISER16_TINT116_SHIFT (20u) +#define INTC_ICDISER16_TINT117_SHIFT (21u) +#define INTC_ICDISER16_TINT118_SHIFT (22u) +#define INTC_ICDISER16_TINT119_SHIFT (23u) +#define INTC_ICDISER16_TINT120_SHIFT (24u) +#define INTC_ICDISER16_TINT121_SHIFT (25u) +#define INTC_ICDISER16_TINT122_SHIFT (26u) +#define INTC_ICDISER16_TINT123_SHIFT (27u) +#define INTC_ICDISER16_TINT124_SHIFT (28u) +#define INTC_ICDISER16_TINT125_SHIFT (29u) +#define INTC_ICDISER16_TINT126_SHIFT (30u) +#define INTC_ICDISER16_TINT127_SHIFT (31u) + +#define INTC_ICDISER17_TINT128_SHIFT (0u) +#define INTC_ICDISER17_TINT129_SHIFT (1u) +#define INTC_ICDISER17_TINT130_SHIFT (2u) +#define INTC_ICDISER17_TINT131_SHIFT (3u) +#define INTC_ICDISER17_TINT132_SHIFT (4u) +#define INTC_ICDISER17_TINT133_SHIFT (5u) +#define INTC_ICDISER17_TINT134_SHIFT (6u) +#define INTC_ICDISER17_TINT135_SHIFT (7u) +#define INTC_ICDISER17_TINT136_SHIFT (8u) +#define INTC_ICDISER17_TINT137_SHIFT (9u) +#define INTC_ICDISER17_TINT138_SHIFT (10u) +#define INTC_ICDISER17_TINT139_SHIFT (11u) +#define INTC_ICDISER17_TINT140_SHIFT (12u) +#define INTC_ICDISER17_TINT141_SHIFT (13u) +#define INTC_ICDISER17_TINT142_SHIFT (14u) +#define INTC_ICDISER17_TINT143_SHIFT (15u) +#define INTC_ICDISER17_TINT144_SHIFT (16u) +#define INTC_ICDISER17_TINT145_SHIFT (17u) +#define INTC_ICDISER17_TINT146_SHIFT (18u) +#define INTC_ICDISER17_TINT147_SHIFT (19u) +#define INTC_ICDISER17_TINT148_SHIFT (20u) +#define INTC_ICDISER17_TINT149_SHIFT (21u) +#define INTC_ICDISER17_TINT150_SHIFT (22u) +#define INTC_ICDISER17_TINT151_SHIFT (23u) +#define INTC_ICDISER17_TINT152_SHIFT (24u) +#define INTC_ICDISER17_TINT153_SHIFT (25u) +#define INTC_ICDISER17_TINT154_SHIFT (26u) +#define INTC_ICDISER17_TINT155_SHIFT (27u) +#define INTC_ICDISER17_TINT156_SHIFT (28u) +#define INTC_ICDISER17_TINT157_SHIFT (29u) +#define INTC_ICDISER17_TINT158_SHIFT (30u) +#define INTC_ICDISER17_TINT159_SHIFT (31u) + +#define INTC_ICDISER18_TINT160_SHIFT (0u) +#define INTC_ICDISER18_TINT161_SHIFT (1u) +#define INTC_ICDISER18_TINT162_SHIFT (2u) +#define INTC_ICDISER18_TINT163_SHIFT (3u) +#define INTC_ICDISER18_TINT164_SHIFT (4u) +#define INTC_ICDISER18_TINT165_SHIFT (5u) +#define INTC_ICDISER18_TINT166_SHIFT (6u) +#define INTC_ICDISER18_TINT167_SHIFT (7u) +#define INTC_ICDISER18_TINT168_SHIFT (8u) +#define INTC_ICDISER18_TINT169_SHIFT (9u) +#define INTC_ICDISER18_TINT170_SHIFT (10u) + +#define INTC_ICDICER0_SW0_SHIFT (0u) +#define INTC_ICDICER0_SW1_SHIFT (1u) +#define INTC_ICDICER0_SW2_SHIFT (2u) +#define INTC_ICDICER0_SW3_SHIFT (3u) +#define INTC_ICDICER0_SW4_SHIFT (4u) +#define INTC_ICDICER0_SW5_SHIFT (5u) +#define INTC_ICDICER0_SW6_SHIFT (6u) +#define INTC_ICDICER0_SW7_SHIFT (7u) +#define INTC_ICDICER0_SW8_SHIFT (8u) +#define INTC_ICDICER0_SW9_SHIFT (9u) +#define INTC_ICDICER0_SW10_SHIFT (10u) +#define INTC_ICDICER0_SW11_SHIFT (11u) +#define INTC_ICDICER0_SW12_SHIFT (12u) +#define INTC_ICDICER0_SW13_SHIFT (13u) +#define INTC_ICDICER0_SW14_SHIFT (14u) +#define INTC_ICDICER0_SW15_SHIFT (15u) +#define INTC_ICDICER0_PMUIRQ0_SHIFT (16u) +#define INTC_ICDICER0_COMMRX0_SHIFT (17u) +#define INTC_ICDICER0_COMMTX0_SHIFT (18u) +#define INTC_ICDICER0_CTIIRQ0_SHIFT (19u) + +#define INTC_ICDICER1_IRQ0_SHIFT (0u) +#define INTC_ICDICER1_IRQ1_SHIFT (1u) +#define INTC_ICDICER1_IRQ2_SHIFT (2u) +#define INTC_ICDICER1_IRQ3_SHIFT (3u) +#define INTC_ICDICER1_IRQ4_SHIFT (4u) +#define INTC_ICDICER1_IRQ5_SHIFT (5u) +#define INTC_ICDICER1_IRQ6_SHIFT (6u) +#define INTC_ICDICER1_IRQ7_SHIFT (7u) +#define INTC_ICDICER1_PL310ERR_SHIFT (8u) +#define INTC_ICDICER1_DMAINT0_SHIFT (9u) +#define INTC_ICDICER1_DMAINT1_SHIFT (10u) +#define INTC_ICDICER1_DMAINT2_SHIFT (11u) +#define INTC_ICDICER1_DMAINT3_SHIFT (12u) +#define INTC_ICDICER1_DMAINT4_SHIFT (13u) +#define INTC_ICDICER1_DMAINT5_SHIFT (14u) +#define INTC_ICDICER1_DMAINT6_SHIFT (15u) +#define INTC_ICDICER1_DMAINT7_SHIFT (16u) +#define INTC_ICDICER1_DMAINT8_SHIFT (17u) +#define INTC_ICDICER1_DMAINT9_SHIFT (18u) +#define INTC_ICDICER1_DMAINT10_SHIFT (19u) +#define INTC_ICDICER1_DMAINT11_SHIFT (20u) +#define INTC_ICDICER1_DMAINT12_SHIFT (21u) +#define INTC_ICDICER1_DMAINT13_SHIFT (22u) +#define INTC_ICDICER1_DMAINT14_SHIFT (23u) +#define INTC_ICDICER1_DMAINT15_SHIFT (24u) +#define INTC_ICDICER1_DMAERR_SHIFT (25u) + +#define INTC_ICDICER2_USBI0_SHIFT (9u) +#define INTC_ICDICER2_USBI1_SHIFT (10u) +#define INTC_ICDICER2_S0_VI_VSYNC0_SHIFT (11u) +#define INTC_ICDICER2_S0_LO_VSYNC0_SHIFT (12u) +#define INTC_ICDICER2_S0_VSYNCERR0_SHIFT (13u) +#define INTC_ICDICER2_GR3_VLINE0_SHIFT (14u) +#define INTC_ICDICER2_S0_VFIELD0_SHIFT (15u) +#define INTC_ICDICER2_IV1_VBUFERR0_SHIFT (16u) +#define INTC_ICDICER2_IV3_VBUFERR0_SHIFT (17u) +#define INTC_ICDICER2_IV5_VBUFERR0_SHIFT (18u) +#define INTC_ICDICER2_IV6_VBUFERR0_SHIFT (19u) +#define INTC_ICDICER2_S0_WLINE0_SHIFT (20u) +#define INTC_ICDICER2_S1_VI_VSYNC0_SHIFT (21u) +#define INTC_ICDICER2_S1_LO_VSYNC0_SHIFT (22u) +#define INTC_ICDICER2_S1_VSYNCERR0_SHIFT (23u) +#define INTC_ICDICER2_S1_VFIELD0_SHIFT (24u) +#define INTC_ICDICER2_IV2_VBUFERR0_SHIFT (25u) +#define INTC_ICDICER2_IV4_VBUFERR0_SHIFT (26u) +#define INTC_ICDICER2_S1_WLINE0_SHIFT (27u) +#define INTC_ICDICER2_OIR_VI_VSYNC0_SHIFT (28u) +#define INTC_ICDICER2_OIR_LO_VSYNC0_SHIFT (29u) +#define INTC_ICDICER2_OIR_VSYNCERR0_SHIFT (30u) +#define INTC_ICDICER2_OIR_VFIELD0_SHIFT (31u) + +#define INTC_ICDICER3_IV7_VBUFERR0_SHIFT (0u) +#define INTC_ICDICER3_IV8_VBUFERR0_SHIFT (1u) +#define INTC_ICDICER3_S0_VI_VSYNC1_SHIFT (3u) +#define INTC_ICDICER3_S0_LO_VSYNC1_SHIFT (4u) +#define INTC_ICDICER3_S0_VSYNCERR1_SHIFT (5u) +#define INTC_ICDICER3_GR3_VLINE1_SHIFT (6u) +#define INTC_ICDICER3_S0_VFIELD1_SHIFT (7u) +#define INTC_ICDICER3_IV1_VBUFERR1_SHIFT (8u) +#define INTC_ICDICER3_IV3_VBUFERR1_SHIFT (9u) +#define INTC_ICDICER3_IV5_VBUFERR1_SHIFT (10u) +#define INTC_ICDICER3_IV6_VBUFERR1_SHIFT (11u) +#define INTC_ICDICER3_S0_WLINE1_SHIFT (12u) +#define INTC_ICDICER3_S1_VI_VSYNC1_SHIFT (13u) +#define INTC_ICDICER3_S1_LO_VSYNC1_SHIFT (14u) +#define INTC_ICDICER3_S1_VSYNCERR1_SHIFT (15u) +#define INTC_ICDICER3_S1_VFIELD1_SHIFT (16u) +#define INTC_ICDICER3_IV2_VBUFERR1_SHIFT (17u) +#define INTC_ICDICER3_IV4_VBUFERR1_SHIFT (18u) +#define INTC_ICDICER3_S1_WLINE1_SHIFT (19u) +#define INTC_ICDICER3_OIR_VI_VSYNC1_SHIFT (20u) +#define INTC_ICDICER3_OIR_LO_VSYNC1_SHIFT (21u) +#define INTC_ICDICER3_OIR_VLINE1_SHIFT (22u) +#define INTC_ICDICER3_OIR_VFIELD1_SHIFT (23u) +#define INTC_ICDICER3_IV7_VBUFERR1_SHIFT (24u) +#define INTC_ICDICER3_IV8_VBUFERR1_SHIFT (25u) +#define INTC_ICDICER3_IMRDI_SHIFT (27u) +#define INTC_ICDICER3_IMR2I0_SHIFT (28u) +#define INTC_ICDICER3_IMR2I1_SHIFT (29u) +#define INTC_ICDICER3_JEDI_SHIFT (30u) +#define INTC_ICDICER3_JDTI_SHIFT (31u) + +#define INTC_ICDICER4_CMP0_SHIFT (0u) +#define INTC_ICDICER4_CMP1_SHIFT (1u) +#define INTC_ICDICER4_INT0_SHIFT (2u) +#define INTC_ICDICER4_INT1_SHIFT (3u) +#define INTC_ICDICER4_INT2_SHIFT (4u) +#define INTC_ICDICER4_INT3_SHIFT (5u) +#define INTC_ICDICER4_OSTM0TINT_SHIFT (6u) +#define INTC_ICDICER4_OSTM1TINT_SHIFT (7u) +#define INTC_ICDICER4_CMI_SHIFT (8u) +#define INTC_ICDICER4_WTOUT_SHIFT (9u) +#define INTC_ICDICER4_ITI_SHIFT (10u) +#define INTC_ICDICER4_TGI0A_SHIFT (11u) +#define INTC_ICDICER4_TGI0B_SHIFT (12u) +#define INTC_ICDICER4_TGI0C_SHIFT (13u) +#define INTC_ICDICER4_TGI0D_SHIFT (14u) +#define INTC_ICDICER4_TGI0V_SHIFT (15u) +#define INTC_ICDICER4_TGI0E_SHIFT (16u) +#define INTC_ICDICER4_TGI0F_SHIFT (17u) +#define INTC_ICDICER4_TGI1A_SHIFT (18u) +#define INTC_ICDICER4_TGI1B_SHIFT (19u) +#define INTC_ICDICER4_TGI1V_SHIFT (20u) +#define INTC_ICDICER4_TGI1U_SHIFT (21u) +#define INTC_ICDICER4_TGI2A_SHIFT (22u) +#define INTC_ICDICER4_TGI2B_SHIFT (23u) +#define INTC_ICDICER4_TGI2V_SHIFT (24u) +#define INTC_ICDICER4_TGI2U_SHIFT (25u) +#define INTC_ICDICER4_TGI3A_SHIFT (26u) +#define INTC_ICDICER4_TGI3B_SHIFT (27u) +#define INTC_ICDICER4_TGI3C_SHIFT (28u) +#define INTC_ICDICER4_TGI3D_SHIFT (29u) +#define INTC_ICDICER4_TGI3V_SHIFT (30u) +#define INTC_ICDICER4_TGI4A_SHIFT (31u) + +#define INTC_ICDICER5_TGI4B_SHIFT (0u) +#define INTC_ICDICER5_TGI4C_SHIFT (1u) +#define INTC_ICDICER5_TGI4D_SHIFT (2u) +#define INTC_ICDICER5_TGI4V_SHIFT (3u) +#define INTC_ICDICER5_CMI1_SHIFT (4u) +#define INTC_ICDICER5_CMI2_SHIFT (5u) +#define INTC_ICDICER5_SGDEI0_SHIFT (6u) +#define INTC_ICDICER5_SGDEI1_SHIFT (7u) +#define INTC_ICDICER5_SGDEI2_SHIFT (8u) +#define INTC_ICDICER5_SGDEI3_SHIFT (9u) +#define INTC_ICDICER5_ADI_SHIFT (10u) +#define INTC_ICDICER5_LMTI_SHIFT (11u) +#define INTC_ICDICER5_SSII0_SHIFT (12u) +#define INTC_ICDICER5_SSIRXI0_SHIFT (13u) +#define INTC_ICDICER5_SSITXI0_SHIFT (14u) +#define INTC_ICDICER5_SSII1_SHIFT (15u) +#define INTC_ICDICER5_SSIRXI1_SHIFT (16u) +#define INTC_ICDICER5_SSITXI1_SHIFT (17u) +#define INTC_ICDICER5_SSII2_SHIFT (18u) +#define INTC_ICDICER5_SSIRTI2_SHIFT (19u) +#define INTC_ICDICER5_SSII3_SHIFT (20u) +#define INTC_ICDICER5_SSIRXI3_SHIFT (21u) +#define INTC_ICDICER5_SSITXI3_SHIFT (22u) +#define INTC_ICDICER5_SSII4_SHIFT (23u) +#define INTC_ICDICER5_SSIRTI4_SHIFT (24u) +#define INTC_ICDICER5_SSII5_SHIFT (25u) +#define INTC_ICDICER5_SSIRXI5_SHIFT (26u) +#define INTC_ICDICER5_SSITXI5_SHIFT (27u) +#define INTC_ICDICER5_SPDIFI_SHIFT (28u) +#define INTC_ICDICER5_INTIICTEI0_SHIFT (29u) +#define INTC_ICDICER5_INTIICRI0_SHIFT (30u) +#define INTC_ICDICER5_INTIICTI0_SHIFT (31u) + +#define INTC_ICDICER6_INTIICSPI0_SHIFT (0u) +#define INTC_ICDICER6_INTIICSTI0_SHIFT (1u) +#define INTC_ICDICER6_INTIICNAKI0_SHIFT (2u) +#define INTC_ICDICER6_INTIICALI0_SHIFT (3u) +#define INTC_ICDICER6_INTIICTMOI0_SHIFT (4u) +#define INTC_ICDICER6_INTIICTEI1_SHIFT (5u) +#define INTC_ICDICER6_INTIICRI1_SHIFT (6u) +#define INTC_ICDICER6_INTIICTI1_SHIFT (7u) +#define INTC_ICDICER6_INTIICSPI1_SHIFT (8u) +#define INTC_ICDICER6_INTIICSTI1_SHIFT (9u) +#define INTC_ICDICER6_INTIICNAKI1_SHIFT (10u) +#define INTC_ICDICER6_INTIICALI1_SHIFT (11u) +#define INTC_ICDICER6_INTIICTMOI1_SHIFT (12u) +#define INTC_ICDICER6_INTIICTEI2_SHIFT (13u) +#define INTC_ICDICER6_INTIICRI2_SHIFT (14u) +#define INTC_ICDICER6_INTIICTI2_SHIFT (15u) +#define INTC_ICDICER6_INTIICSPI2_SHIFT (16u) +#define INTC_ICDICER6_INTIICSTI2_SHIFT (17u) +#define INTC_ICDICER6_INTIICNAKI2_SHIFT (18u) +#define INTC_ICDICER6_INTIICALI2_SHIFT (19u) +#define INTC_ICDICER6_INTIICTMOI2_SHIFT (20u) +#define INTC_ICDICER6_INTIICTEI3_SHIFT (21u) +#define INTC_ICDICER6_INTIICRI3_SHIFT (22u) +#define INTC_ICDICER6_INTIICTI3_SHIFT (23u) +#define INTC_ICDICER6_INTIICSPI3_SHIFT (24u) +#define INTC_ICDICER6_INTIICSTI3_SHIFT (25u) +#define INTC_ICDICER6_INTIICNAKI3_SHIFT (26u) +#define INTC_ICDICER6_INTIICALI3_SHIFT (27u) +#define INTC_ICDICER6_INTIICTMOI3_SHIFT (28u) +#define INTC_ICDICER6_BRI0_SHIFT (29u) +#define INTC_ICDICER6_ERI0_SHIFT (30u) +#define INTC_ICDICER6_RXI0_SHIFT (31u) + +#define INTC_ICDICER7_TXI0_SHIFT (0u) +#define INTC_ICDICER7_BRI1_SHIFT (1u) +#define INTC_ICDICER7_ERI1_SHIFT (2u) +#define INTC_ICDICER7_RXI1_SHIFT (3u) +#define INTC_ICDICER7_TXI1_SHIFT (4u) +#define INTC_ICDICER7_BRI2_SHIFT (5u) +#define INTC_ICDICER7_ERI2_SHIFT (6u) +#define INTC_ICDICER7_RXI2_SHIFT (7u) +#define INTC_ICDICER7_TXI2_SHIFT (8u) +#define INTC_ICDICER7_BRI3_SHIFT (9u) +#define INTC_ICDICER7_ERI3_SHIFT (10u) +#define INTC_ICDICER7_RXI3_SHIFT (11u) +#define INTC_ICDICER7_TXI3_SHIFT (12u) +#define INTC_ICDICER7_BRI4_SHIFT (13u) +#define INTC_ICDICER7_ERI4_SHIFT (14u) +#define INTC_ICDICER7_RXI4_SHIFT (15u) +#define INTC_ICDICER7_TXI4_SHIFT (16u) +#define INTC_ICDICER7_BRI5_SHIFT (17u) +#define INTC_ICDICER7_ERI5_SHIFT (18u) +#define INTC_ICDICER7_RXI5_SHIFT (19u) +#define INTC_ICDICER7_TXI5_SHIFT (20u) +#define INTC_ICDICER7_BRI6_SHIFT (21u) +#define INTC_ICDICER7_ERI6_SHIFT (22u) +#define INTC_ICDICER7_RXI6_SHIFT (23u) +#define INTC_ICDICER7_TXI6_SHIFT (24u) +#define INTC_ICDICER7_BRI7_SHIFT (25u) +#define INTC_ICDICER7_ERI7_SHIFT (26u) +#define INTC_ICDICER7_RXI7_SHIFT (27u) +#define INTC_ICDICER7_TXI7_SHIFT (28u) +#define INTC_ICDICER7_INTRCANGERR_SHIFT (29u) +#define INTC_ICDICER7_INTRCANGRECC_SHIFT (30u) +#define INTC_ICDICER7_INTRCAN0REC_SHIFT (31u) + +#define INTC_ICDICER8_INTRCAN0ERR_SHIFT (0u) +#define INTC_ICDICER8_INTRCAN0TRX_SHIFT (1u) +#define INTC_ICDICER8_INTRCAN1REC_SHIFT (2u) +#define INTC_ICDICER8_INTRCAN1ERR_SHIFT (3u) +#define INTC_ICDICER8_INTRCAN1TRX_SHIFT (4u) +#define INTC_ICDICER8_INTRCAN2REC_SHIFT (5u) +#define INTC_ICDICER8_INTRCAN2ERR_SHIFT (6u) +#define INTC_ICDICER8_INTRCAN2TRX_SHIFT (7u) +#define INTC_ICDICER8_INTRCAN3REC_SHIFT (8u) +#define INTC_ICDICER8_INTRCAN3ERR_SHIFT (9u) +#define INTC_ICDICER8_INTRCAN3TRX_SHIFT (10u) +#define INTC_ICDICER8_INTRCAN4REC_SHIFT (11u) +#define INTC_ICDICER8_INTRCAN4ERR_SHIFT (12u) +#define INTC_ICDICER8_INTRCAN4TRX_SHIFT (13u) +#define INTC_ICDICER8_SPEI0_SHIFT (14u) +#define INTC_ICDICER8_SPRI0_SHIFT (15u) +#define INTC_ICDICER8_SPTI0_SHIFT (16u) +#define INTC_ICDICER8_SPEI1_SHIFT (17u) +#define INTC_ICDICER8_SPRI1_SHIFT (18u) +#define INTC_ICDICER8_SPTI1_SHIFT (19u) +#define INTC_ICDICER8_SPEI2_SHIFT (20u) +#define INTC_ICDICER8_SPRI2_SHIFT (21u) +#define INTC_ICDICER8_SPTI2_SHIFT (22u) +#define INTC_ICDICER8_SPEI3_SHIFT (23u) +#define INTC_ICDICER8_SPRI3_SHIFT (24u) +#define INTC_ICDICER8_SPTI3_SHIFT (25u) +#define INTC_ICDICER8_SPEI4_SHIFT (26u) +#define INTC_ICDICER8_SPRI4_SHIFT (27u) +#define INTC_ICDICER8_SPTI4_SHIFT (28u) +#define INTC_ICDICER8_IEBBTD_SHIFT (29u) +#define INTC_ICDICER8_IEBBTERR_SHIFT (30u) +#define INTC_ICDICER8_IEBBTSTA_SHIFT (31u) + +#define INTC_ICDICER9_IEBBTV_SHIFT (0u) +#define INTC_ICDICER9_ISY_SHIFT (1u) +#define INTC_ICDICER9_IERR_SHIFT (2u) +#define INTC_ICDICER9_ITARG_SHIFT (3u) +#define INTC_ICDICER9_ISEC_SHIFT (4u) +#define INTC_ICDICER9_IBUF_SHIFT (5u) +#define INTC_ICDICER9_IREADY_SHIFT (6u) +#define INTC_ICDICER9_FLSTE_SHIFT (7u) +#define INTC_ICDICER9_FLTENDI_SHIFT (8u) +#define INTC_ICDICER9_FLTREQ0I_SHIFT (9u) +#define INTC_ICDICER9_FLTREQ1I_SHIFT (10u) +#define INTC_ICDICER9_MMC0_SHIFT (11u) +#define INTC_ICDICER9_MMC1_SHIFT (12u) +#define INTC_ICDICER9_MMC2_SHIFT (13u) +#define INTC_ICDICER9_SDHI0_3_SHIFT (14u) +#define INTC_ICDICER9_SDHI0_0_SHIFT (15u) +#define INTC_ICDICER9_SDHI0_1_SHIFT (16u) +#define INTC_ICDICER9_SDHI1_3_SHIFT (17u) +#define INTC_ICDICER9_SDHI1_0_SHIFT (18u) +#define INTC_ICDICER9_SDHI1_1_SHIFT (19u) +#define INTC_ICDICER9_ARM_SHIFT (20u) +#define INTC_ICDICER9_PRD_SHIFT (21u) +#define INTC_ICDICER9_CUP_SHIFT (22u) +#define INTC_ICDICER9_SCUAI0_SHIFT (23u) +#define INTC_ICDICER9_SCUAI1_SHIFT (24u) +#define INTC_ICDICER9_SCUFDI0_SHIFT (25u) +#define INTC_ICDICER9_SCUFDI1_SHIFT (26u) +#define INTC_ICDICER9_SCUFDI2_SHIFT (27u) +#define INTC_ICDICER9_SCUFDI3_SHIFT (28u) +#define INTC_ICDICER9_SCUFUI0_SHIFT (29u) +#define INTC_ICDICER9_SCUFUI1_SHIFT (30u) +#define INTC_ICDICER9_SCUFUI2_SHIFT (31u) + +#define INTC_ICDICER10_SCUFUI3_SHIFT (0u) +#define INTC_ICDICER10_SCUDVI0_SHIFT (1u) +#define INTC_ICDICER10_SCUDVI1_SHIFT (2u) +#define INTC_ICDICER10_SCUDVI2_SHIFT (3u) +#define INTC_ICDICER10_SCUDVI3_SHIFT (4u) +#define INTC_ICDICER10_MLB_CINT_SHIFT (5u) +#define INTC_ICDICER10_MLB_SINT_SHIFT (6u) +#define INTC_ICDICER10_DRC0_SHIFT (7u) +#define INTC_ICDICER10_DRC1_SHIFT (8u) +#define INTC_ICDICER10_LINI0_INT_T_SHIFT (11u) +#define INTC_ICDICER10_LINI0_INT_R_SHIFT (12u) +#define INTC_ICDICER10_LINI0_INT_S_SHIFT (13u) +#define INTC_ICDICER10_LINI0_INT_M_SHIFT (14u) +#define INTC_ICDICER10_LINI1_INT_T_SHIFT (15u) +#define INTC_ICDICER10_LINI1_INT_R_SHIFT (16u) +#define INTC_ICDICER10_LINI1_INT_S_SHIFT (17u) +#define INTC_ICDICER10_LINI1_INT_M_SHIFT (18u) +#define INTC_ICDICER10_ERI0_SHIFT (27u) +#define INTC_ICDICER10_RXI0_SHIFT (28u) +#define INTC_ICDICER10_TXI0_SHIFT (29u) +#define INTC_ICDICER10_TEI0_SHIFT (30u) +#define INTC_ICDICER10_ERI1_SHIFT (31u) + +#define INTC_ICDICER11_RXI1_SHIFT (0u) +#define INTC_ICDICER11_TXI1_SHIFT (1u) +#define INTC_ICDICER11_TEI1_SHIFT (2u) +#define INTC_ICDICER11_AVBI_DATA_SHIFT (3u) +#define INTC_ICDICER11_AVBI_ERROR_SHIFT (4u) +#define INTC_ICDICER11_AVBI_MANAGE_SHIFT (5u) +#define INTC_ICDICER11_AVBI_MAC_SHIFT (6u) +#define INTC_ICDICER11_ETHERI_SHIFT (7u) +#define INTC_ICDICER11_CEUI_SHIFT (12u) +#define INTC_ICDICER11_H2XMLB_ERRINT_SHIFT (29u) +#define INTC_ICDICER11_H2XIC1_ERRINT_SHIFT (30u) +#define INTC_ICDICER11_X2HPERI1_ERRINT_SHIFT (31u) + +#define INTC_ICDICER12_X2HPERI2_ERRINT_SHIFT (0u) +#define INTC_ICDICER12_X2HPERI34_ERRINT_SHIFT (1u) +#define INTC_ICDICER12_X2HPERI5_ERRINT_SHIFT (2u) +#define INTC_ICDICER12_X2HPERI67_ERRINT_SHIFT (3u) +#define INTC_ICDICER12_X2HDBGR_ERRINT_SHIFT (4u) +#define INTC_ICDICER12_X2HBSC_ERRINT_SHIFT (5u) +#define INTC_ICDICER12_X2HSPI1_ERRINT_SHIFT (6u) +#define INTC_ICDICER12_X2HSPI2_ERRINT_SHIFT (7u) +#define INTC_ICDICER12_PRRI_SHIFT (8u) +#define INTC_ICDICER12_IFEI0_SHIFT (9u) +#define INTC_ICDICER12_OFFI0_SHIFT (10u) +#define INTC_ICDICER12_PFVEI0_SHIFT (11u) +#define INTC_ICDICER12_IFEI1_SHIFT (12u) +#define INTC_ICDICER12_OFFI1_SHIFT (13u) +#define INTC_ICDICER12_PFVEI1_SHIFT (14u) + +#define INTC_ICDICER13_TINT0_SHIFT (0u) +#define INTC_ICDICER13_TINT1_SHIFT (1u) +#define INTC_ICDICER13_TINT2_SHIFT (2u) +#define INTC_ICDICER13_TINT3_SHIFT (3u) +#define INTC_ICDICER13_TINT4_SHIFT (4u) +#define INTC_ICDICER13_TINT5_SHIFT (5u) +#define INTC_ICDICER13_TINT6_SHIFT (6u) +#define INTC_ICDICER13_TINT7_SHIFT (7u) +#define INTC_ICDICER13_TINT8_SHIFT (8u) +#define INTC_ICDICER13_TINT9_SHIFT (9u) +#define INTC_ICDICER13_TINT10_SHIFT (10u) +#define INTC_ICDICER13_TINT11_SHIFT (11u) +#define INTC_ICDICER13_TINT12_SHIFT (12u) +#define INTC_ICDICER13_TINT13_SHIFT (13u) +#define INTC_ICDICER13_TINT14_SHIFT (14u) +#define INTC_ICDICER13_TINT15_SHIFT (15u) +#define INTC_ICDICER13_TINT16_SHIFT (16u) +#define INTC_ICDICER13_TINT17_SHIFT (17u) +#define INTC_ICDICER13_TINT18_SHIFT (18u) +#define INTC_ICDICER13_TINT19_SHIFT (19u) +#define INTC_ICDICER13_TINT20_SHIFT (20u) +#define INTC_ICDICER13_TINT21_SHIFT (21u) +#define INTC_ICDICER13_TINT22_SHIFT (22u) +#define INTC_ICDICER13_TINT23_SHIFT (23u) +#define INTC_ICDICER13_TINT24_SHIFT (24u) +#define INTC_ICDICER13_TINT25_SHIFT (25u) +#define INTC_ICDICER13_TINT26_SHIFT (26u) +#define INTC_ICDICER13_TINT27_SHIFT (27u) +#define INTC_ICDICER13_TINT28_SHIFT (28u) +#define INTC_ICDICER13_TINT29_SHIFT (29u) +#define INTC_ICDICER13_TINT30_SHIFT (30u) +#define INTC_ICDICER13_TINT31_SHIFT (31u) + +#define INTC_ICDICER14_TINT32_SHIFT (0u) +#define INTC_ICDICER14_TINT33_SHIFT (1u) +#define INTC_ICDICER14_TINT34_SHIFT (2u) +#define INTC_ICDICER14_TINT35_SHIFT (3u) +#define INTC_ICDICER14_TINT36_SHIFT (4u) +#define INTC_ICDICER14_TINT37_SHIFT (5u) +#define INTC_ICDICER14_TINT38_SHIFT (6u) +#define INTC_ICDICER14_TINT39_SHIFT (7u) +#define INTC_ICDICER14_TINT40_SHIFT (8u) +#define INTC_ICDICER14_TINT41_SHIFT (9u) +#define INTC_ICDICER14_TINT42_SHIFT (10u) +#define INTC_ICDICER14_TINT43_SHIFT (11u) +#define INTC_ICDICER14_TINT44_SHIFT (12u) +#define INTC_ICDICER14_TINT45_SHIFT (13u) +#define INTC_ICDICER14_TINT46_SHIFT (14u) +#define INTC_ICDICER14_TINT47_SHIFT (15u) +#define INTC_ICDICER14_TINT48_SHIFT (16u) +#define INTC_ICDICER14_TINT49_SHIFT (17u) +#define INTC_ICDICER14_TINT50_SHIFT (18u) +#define INTC_ICDICER14_TINT51_SHIFT (19u) +#define INTC_ICDICER14_TINT52_SHIFT (20u) +#define INTC_ICDICER14_TINT53_SHIFT (21u) +#define INTC_ICDICER14_TINT54_SHIFT (22u) +#define INTC_ICDICER14_TINT55_SHIFT (23u) +#define INTC_ICDICER14_TINT56_SHIFT (24u) +#define INTC_ICDICER14_TINT57_SHIFT (25u) +#define INTC_ICDICER14_TINT58_SHIFT (26u) +#define INTC_ICDICER14_TINT59_SHIFT (27u) +#define INTC_ICDICER14_TINT60_SHIFT (28u) +#define INTC_ICDICER14_TINT61_SHIFT (29u) +#define INTC_ICDICER14_TINT62_SHIFT (30u) +#define INTC_ICDICER14_TINT63_SHIFT (31u) + +#define INTC_ICDICER15_TINT64_SHIFT (0u) +#define INTC_ICDICER15_TINT65_SHIFT (1u) +#define INTC_ICDICER15_TINT66_SHIFT (2u) +#define INTC_ICDICER15_TINT67_SHIFT (3u) +#define INTC_ICDICER15_TINT68_SHIFT (4u) +#define INTC_ICDICER15_TINT69_SHIFT (5u) +#define INTC_ICDICER15_TINT70_SHIFT (6u) +#define INTC_ICDICER15_TINT71_SHIFT (7u) +#define INTC_ICDICER15_TINT72_SHIFT (8u) +#define INTC_ICDICER15_TINT73_SHIFT (9u) +#define INTC_ICDICER15_TINT74_SHIFT (10u) +#define INTC_ICDICER15_TINT75_SHIFT (11u) +#define INTC_ICDICER15_TINT76_SHIFT (12u) +#define INTC_ICDICER15_TINT77_SHIFT (13u) +#define INTC_ICDICER15_TINT78_SHIFT (14u) +#define INTC_ICDICER15_TINT79_SHIFT (15u) +#define INTC_ICDICER15_TINT80_SHIFT (16u) +#define INTC_ICDICER15_TINT81_SHIFT (17u) +#define INTC_ICDICER15_TINT82_SHIFT (18u) +#define INTC_ICDICER15_TINT83_SHIFT (19u) +#define INTC_ICDICER15_TINT84_SHIFT (20u) +#define INTC_ICDICER15_TINT85_SHIFT (21u) +#define INTC_ICDICER15_TINT86_SHIFT (22u) +#define INTC_ICDICER15_TINT87_SHIFT (23u) +#define INTC_ICDICER15_TINT88_SHIFT (24u) +#define INTC_ICDICER15_TINT89_SHIFT (25u) +#define INTC_ICDICER15_TINT90_SHIFT (26u) +#define INTC_ICDICER15_TINT91_SHIFT (27u) +#define INTC_ICDICER15_TINT92_SHIFT (28u) +#define INTC_ICDICER15_TINT93_SHIFT (29u) +#define INTC_ICDICER15_TINT94_SHIFT (30u) +#define INTC_ICDICER15_TINT95_SHIFT (31u) + +#define INTC_ICDICER16_TINT96_SHIFT (0u) +#define INTC_ICDICER16_TINT97_SHIFT (1u) +#define INTC_ICDICER16_TINT98_SHIFT (2u) +#define INTC_ICDICER16_TINT99_SHIFT (3u) +#define INTC_ICDICER16_TINT100_SHIFT (4u) +#define INTC_ICDICER16_TINT101_SHIFT (5u) +#define INTC_ICDICER16_TINT102_SHIFT (6u) +#define INTC_ICDICER16_TINT103_SHIFT (7u) +#define INTC_ICDICER16_TINT104_SHIFT (8u) +#define INTC_ICDICER16_TINT105_SHIFT (9u) +#define INTC_ICDICER16_TINT106_SHIFT (10u) +#define INTC_ICDICER16_TINT107_SHIFT (11u) +#define INTC_ICDICER16_TINT108_SHIFT (12u) +#define INTC_ICDICER16_TINT109_SHIFT (13u) +#define INTC_ICDICER16_TINT110_SHIFT (14u) +#define INTC_ICDICER16_TINT111_SHIFT (15u) +#define INTC_ICDICER16_TINT112_SHIFT (16u) +#define INTC_ICDICER16_TINT113_SHIFT (17u) +#define INTC_ICDICER16_TINT114_SHIFT (18u) +#define INTC_ICDICER16_TINT115_SHIFT (19u) +#define INTC_ICDICER16_TINT116_SHIFT (20u) +#define INTC_ICDICER16_TINT117_SHIFT (21u) +#define INTC_ICDICER16_TINT118_SHIFT (22u) +#define INTC_ICDICER16_TINT119_SHIFT (23u) +#define INTC_ICDICER16_TINT120_SHIFT (24u) +#define INTC_ICDICER16_TINT121_SHIFT (25u) +#define INTC_ICDICER16_TINT122_SHIFT (26u) +#define INTC_ICDICER16_TINT123_SHIFT (27u) +#define INTC_ICDICER16_TINT124_SHIFT (28u) +#define INTC_ICDICER16_TINT125_SHIFT (29u) +#define INTC_ICDICER16_TINT126_SHIFT (30u) +#define INTC_ICDICER16_TINT127_SHIFT (31u) + +#define INTC_ICDICER17_TINT128_SHIFT (0u) +#define INTC_ICDICER17_TINT129_SHIFT (1u) +#define INTC_ICDICER17_TINT130_SHIFT (2u) +#define INTC_ICDICER17_TINT131_SHIFT (3u) +#define INTC_ICDICER17_TINT132_SHIFT (4u) +#define INTC_ICDICER17_TINT133_SHIFT (5u) +#define INTC_ICDICER17_TINT134_SHIFT (6u) +#define INTC_ICDICER17_TINT135_SHIFT (7u) +#define INTC_ICDICER17_TINT136_SHIFT (8u) +#define INTC_ICDICER17_TINT137_SHIFT (9u) +#define INTC_ICDICER17_TINT138_SHIFT (10u) +#define INTC_ICDICER17_TINT139_SHIFT (11u) +#define INTC_ICDICER17_TINT140_SHIFT (12u) +#define INTC_ICDICER17_TINT141_SHIFT (13u) +#define INTC_ICDICER17_TINT142_SHIFT (14u) +#define INTC_ICDICER17_TINT143_SHIFT (15u) +#define INTC_ICDICER17_TINT144_SHIFT (16u) +#define INTC_ICDICER17_TINT145_SHIFT (17u) +#define INTC_ICDICER17_TINT146_SHIFT (18u) +#define INTC_ICDICER17_TINT147_SHIFT (19u) +#define INTC_ICDICER17_TINT148_SHIFT (20u) +#define INTC_ICDICER17_TINT149_SHIFT (21u) +#define INTC_ICDICER17_TINT150_SHIFT (22u) +#define INTC_ICDICER17_TINT151_SHIFT (23u) +#define INTC_ICDICER17_TINT152_SHIFT (24u) +#define INTC_ICDICER17_TINT153_SHIFT (25u) +#define INTC_ICDICER17_TINT154_SHIFT (26u) +#define INTC_ICDICER17_TINT155_SHIFT (27u) +#define INTC_ICDICER17_TINT156_SHIFT (28u) +#define INTC_ICDICER17_TINT157_SHIFT (29u) +#define INTC_ICDICER17_TINT158_SHIFT (30u) +#define INTC_ICDICER17_TINT159_SHIFT (31u) + +#define INTC_ICDICER18_TINT160_SHIFT (0u) +#define INTC_ICDICER18_TINT161_SHIFT (1u) +#define INTC_ICDICER18_TINT162_SHIFT (2u) +#define INTC_ICDICER18_TINT163_SHIFT (3u) +#define INTC_ICDICER18_TINT164_SHIFT (4u) +#define INTC_ICDICER18_TINT165_SHIFT (5u) +#define INTC_ICDICER18_TINT166_SHIFT (6u) +#define INTC_ICDICER18_TINT167_SHIFT (7u) +#define INTC_ICDICER18_TINT168_SHIFT (8u) +#define INTC_ICDICER18_TINT169_SHIFT (9u) +#define INTC_ICDICER18_TINT170_SHIFT (10u) + +#define INTC_ICDISPR0_SW0_SHIFT (0u) +#define INTC_ICDISPR0_SW1_SHIFT (1u) +#define INTC_ICDISPR0_SW2_SHIFT (2u) +#define INTC_ICDISPR0_SW3_SHIFT (3u) +#define INTC_ICDISPR0_SW4_SHIFT (4u) +#define INTC_ICDISPR0_SW5_SHIFT (5u) +#define INTC_ICDISPR0_SW6_SHIFT (6u) +#define INTC_ICDISPR0_SW7_SHIFT (7u) +#define INTC_ICDISPR0_SW8_SHIFT (8u) +#define INTC_ICDISPR0_SW9_SHIFT (9u) +#define INTC_ICDISPR0_SW10_SHIFT (10u) +#define INTC_ICDISPR0_SW11_SHIFT (11u) +#define INTC_ICDISPR0_SW12_SHIFT (12u) +#define INTC_ICDISPR0_SW13_SHIFT (13u) +#define INTC_ICDISPR0_SW14_SHIFT (14u) +#define INTC_ICDISPR0_SW15_SHIFT (15u) +#define INTC_ICDISPR0_PMUIRQ0_SHIFT (16u) +#define INTC_ICDISPR0_COMMRX0_SHIFT (17u) +#define INTC_ICDISPR0_COMMTX0_SHIFT (18u) +#define INTC_ICDISPR0_CTIIRQ0_SHIFT (19u) + +#define INTC_ICDISPR1_IRQ0_SHIFT (0u) +#define INTC_ICDISPR1_IRQ1_SHIFT (1u) +#define INTC_ICDISPR1_IRQ2_SHIFT (2u) +#define INTC_ICDISPR1_IRQ3_SHIFT (3u) +#define INTC_ICDISPR1_IRQ4_SHIFT (4u) +#define INTC_ICDISPR1_IRQ5_SHIFT (5u) +#define INTC_ICDISPR1_IRQ6_SHIFT (6u) +#define INTC_ICDISPR1_IRQ7_SHIFT (7u) +#define INTC_ICDISPR1_PL310ERR_SHIFT (8u) +#define INTC_ICDISPR1_DMAINT0_SHIFT (9u) +#define INTC_ICDISPR1_DMAINT1_SHIFT (10u) +#define INTC_ICDISPR1_DMAINT2_SHIFT (11u) +#define INTC_ICDISPR1_DMAINT3_SHIFT (12u) +#define INTC_ICDISPR1_DMAINT4_SHIFT (13u) +#define INTC_ICDISPR1_DMAINT5_SHIFT (14u) +#define INTC_ICDISPR1_DMAINT6_SHIFT (15u) +#define INTC_ICDISPR1_DMAINT7_SHIFT (16u) +#define INTC_ICDISPR1_DMAINT8_SHIFT (17u) +#define INTC_ICDISPR1_DMAINT9_SHIFT (18u) +#define INTC_ICDISPR1_DMAINT10_SHIFT (19u) +#define INTC_ICDISPR1_DMAINT11_SHIFT (20u) +#define INTC_ICDISPR1_DMAINT12_SHIFT (21u) +#define INTC_ICDISPR1_DMAINT13_SHIFT (22u) +#define INTC_ICDISPR1_DMAINT14_SHIFT (23u) +#define INTC_ICDISPR1_DMAINT15_SHIFT (24u) +#define INTC_ICDISPR1_DMAERR_SHIFT (25u) + +#define INTC_ICDISPR2_USBI0_SHIFT (9u) +#define INTC_ICDISPR2_USBI1_SHIFT (10u) +#define INTC_ICDISPR2_S0_VI_VSYNC0_SHIFT (11u) +#define INTC_ICDISPR2_S0_LO_VSYNC0_SHIFT (12u) +#define INTC_ICDISPR2_S0_VSYNCERR0_SHIFT (13u) +#define INTC_ICDISPR2_GR3_VLINE0_SHIFT (14u) +#define INTC_ICDISPR2_S0_VFIELD0_SHIFT (15u) +#define INTC_ICDISPR2_IV1_VBUFERR0_SHIFT (16u) +#define INTC_ICDISPR2_IV3_VBUFERR0_SHIFT (17u) +#define INTC_ICDISPR2_IV5_VBUFERR0_SHIFT (18u) +#define INTC_ICDISPR2_IV6_VBUFERR0_SHIFT (19u) +#define INTC_ICDISPR2_S0_WLINE0_SHIFT (20u) +#define INTC_ICDISPR2_S1_VI_VSYNC0_SHIFT (21u) +#define INTC_ICDISPR2_S1_LO_VSYNC0_SHIFT (22u) +#define INTC_ICDISPR2_S1_VSYNCERR0_SHIFT (23u) +#define INTC_ICDISPR2_S1_VFIELD0_SHIFT (24u) +#define INTC_ICDISPR2_IV2_VBUFERR0_SHIFT (25u) +#define INTC_ICDISPR2_IV4_VBUFERR0_SHIFT (26u) +#define INTC_ICDISPR2_S1_WLINE0_SHIFT (27u) +#define INTC_ICDISPR2_OIR_VI_VSYNC0_SHIFT (28u) +#define INTC_ICDISPR2_OIR_LO_VSYNC0_SHIFT (29u) +#define INTC_ICDISPR2_OIR_VSYNCERR0_SHIFT (30u) +#define INTC_ICDISPR2_OIR_VFIELD0_SHIFT (31u) + +#define INTC_ICDISPR3_IV7_VBUFERR0_SHIFT (0u) +#define INTC_ICDISPR3_IV8_VBUFERR0_SHIFT (1u) +#define INTC_ICDISPR3_S0_VI_VSYNC1_SHIFT (3u) +#define INTC_ICDISPR3_S0_LO_VSYNC1_SHIFT (4u) +#define INTC_ICDISPR3_S0_VSYNCERR1_SHIFT (5u) +#define INTC_ICDISPR3_GR3_VLINE1_SHIFT (6u) +#define INTC_ICDISPR3_S0_VFIELD1_SHIFT (7u) +#define INTC_ICDISPR3_IV1_VBUFERR1_SHIFT (8u) +#define INTC_ICDISPR3_IV3_VBUFERR1_SHIFT (9u) +#define INTC_ICDISPR3_IV5_VBUFERR1_SHIFT (10u) +#define INTC_ICDISPR3_IV6_VBUFERR1_SHIFT (11u) +#define INTC_ICDISPR3_S0_WLINE1_SHIFT (12u) +#define INTC_ICDISPR3_S1_VI_VSYNC1_SHIFT (13u) +#define INTC_ICDISPR3_S1_LO_VSYNC1_SHIFT (14u) +#define INTC_ICDISPR3_S1_VSYNCERR1_SHIFT (15u) +#define INTC_ICDISPR3_S1_VFIELD1_SHIFT (16u) +#define INTC_ICDISPR3_IV2_VBUFERR1_SHIFT (17u) +#define INTC_ICDISPR3_IV4_VBUFERR1_SHIFT (18u) +#define INTC_ICDISPR3_S1_WLINE1_SHIFT (19u) +#define INTC_ICDISPR3_OIR_VI_VSYNC1_SHIFT (20u) +#define INTC_ICDISPR3_OIR_LO_VSYNC1_SHIFT (21u) +#define INTC_ICDISPR3_OIR_VLINE1_SHIFT (22u) +#define INTC_ICDISPR3_OIR_VFIELD1_SHIFT (23u) +#define INTC_ICDISPR3_IV7_VBUFERR1_SHIFT (24u) +#define INTC_ICDISPR3_IV8_VBUFERR1_SHIFT (25u) +#define INTC_ICDISPR3_IMRDI_SHIFT (27u) +#define INTC_ICDISPR3_IMR2I0_SHIFT (28u) +#define INTC_ICDISPR3_IMR2I1_SHIFT (29u) +#define INTC_ICDISPR3_JEDI_SHIFT (30u) +#define INTC_ICDISPR3_JDTI_SHIFT (31u) + +#define INTC_ICDISPR4_CMP0_SHIFT (0u) +#define INTC_ICDISPR4_CMP1_SHIFT (1u) +#define INTC_ICDISPR4_INT0_SHIFT (2u) +#define INTC_ICDISPR4_INT1_SHIFT (3u) +#define INTC_ICDISPR4_INT2_SHIFT (4u) +#define INTC_ICDISPR4_INT3_SHIFT (5u) +#define INTC_ICDISPR4_OSTM0TINT_SHIFT (6u) +#define INTC_ICDISPR4_OSTM1TINT_SHIFT (7u) +#define INTC_ICDISPR4_CMI_SHIFT (8u) +#define INTC_ICDISPR4_WTOUT_SHIFT (9u) +#define INTC_ICDISPR4_ITI_SHIFT (10u) +#define INTC_ICDISPR4_TGI0A_SHIFT (11u) +#define INTC_ICDISPR4_TGI0B_SHIFT (12u) +#define INTC_ICDISPR4_TGI0C_SHIFT (13u) +#define INTC_ICDISPR4_TGI0D_SHIFT (14u) +#define INTC_ICDISPR4_TGI0V_SHIFT (15u) +#define INTC_ICDISPR4_TGI0E_SHIFT (16u) +#define INTC_ICDISPR4_TGI0F_SHIFT (17u) +#define INTC_ICDISPR4_TGI1A_SHIFT (18u) +#define INTC_ICDISPR4_TGI1B_SHIFT (19u) +#define INTC_ICDISPR4_TGI1V_SHIFT (20u) +#define INTC_ICDISPR4_TGI1U_SHIFT (21u) +#define INTC_ICDISPR4_TGI2A_SHIFT (22u) +#define INTC_ICDISPR4_TGI2B_SHIFT (23u) +#define INTC_ICDISPR4_TGI2V_SHIFT (24u) +#define INTC_ICDISPR4_TGI2U_SHIFT (25u) +#define INTC_ICDISPR4_TGI3A_SHIFT (26u) +#define INTC_ICDISPR4_TGI3B_SHIFT (27u) +#define INTC_ICDISPR4_TGI3C_SHIFT (28u) +#define INTC_ICDISPR4_TGI3D_SHIFT (29u) +#define INTC_ICDISPR4_TGI3V_SHIFT (30u) +#define INTC_ICDISPR4_TGI4A_SHIFT (31u) + +#define INTC_ICDISPR5_TGI4B_SHIFT (0u) +#define INTC_ICDISPR5_TGI4C_SHIFT (1u) +#define INTC_ICDISPR5_TGI4D_SHIFT (2u) +#define INTC_ICDISPR5_TGI4V_SHIFT (3u) +#define INTC_ICDISPR5_CMI1_SHIFT (4u) +#define INTC_ICDISPR5_CMI2_SHIFT (5u) +#define INTC_ICDISPR5_SGDEI0_SHIFT (6u) +#define INTC_ICDISPR5_SGDEI1_SHIFT (7u) +#define INTC_ICDISPR5_SGDEI2_SHIFT (8u) +#define INTC_ICDISPR5_SGDEI3_SHIFT (9u) +#define INTC_ICDISPR5_ADI_SHIFT (10u) +#define INTC_ICDISPR5_LMTI_SHIFT (11u) +#define INTC_ICDISPR5_SSII0_SHIFT (12u) +#define INTC_ICDISPR5_SSIRXI0_SHIFT (13u) +#define INTC_ICDISPR5_SSITXI0_SHIFT (14u) +#define INTC_ICDISPR5_SSII1_SHIFT (15u) +#define INTC_ICDISPR5_SSIRXI1_SHIFT (16u) +#define INTC_ICDISPR5_SSITXI1_SHIFT (17u) +#define INTC_ICDISPR5_SSII2_SHIFT (18u) +#define INTC_ICDISPR5_SSIRTI2_SHIFT (19u) +#define INTC_ICDISPR5_SSII3_SHIFT (20u) +#define INTC_ICDISPR5_SSIRXI3_SHIFT (21u) +#define INTC_ICDISPR5_SSITXI3_SHIFT (22u) +#define INTC_ICDISPR5_SSII4_SHIFT (23u) +#define INTC_ICDISPR5_SSIRTI4_SHIFT (24u) +#define INTC_ICDISPR5_SSII5_SHIFT (25u) +#define INTC_ICDISPR5_SSIRXI5_SHIFT (26u) +#define INTC_ICDISPR5_SSITXI5_SHIFT (27u) +#define INTC_ICDISPR5_SPDIFI_SHIFT (28u) +#define INTC_ICDISPR5_INTIICTEI0_SHIFT (29u) +#define INTC_ICDISPR5_INTIICRI0_SHIFT (30u) +#define INTC_ICDISPR5_INTIICTI0_SHIFT (31u) + +#define INTC_ICDISPR6_INTIICSPI0_SHIFT (0u) +#define INTC_ICDISPR6_INTIICSTI0_SHIFT (1u) +#define INTC_ICDISPR6_INTIICNAKI0_SHIFT (2u) +#define INTC_ICDISPR6_INTIICALI0_SHIFT (3u) +#define INTC_ICDISPR6_INTIICTMOI0_SHIFT (4u) +#define INTC_ICDISPR6_INTIICTEI1_SHIFT (5u) +#define INTC_ICDISPR6_INTIICRI1_SHIFT (6u) +#define INTC_ICDISPR6_INTIICTI1_SHIFT (7u) +#define INTC_ICDISPR6_INTIICSPI1_SHIFT (8u) +#define INTC_ICDISPR6_INTIICSTI1_SHIFT (9u) +#define INTC_ICDISPR6_INTIICNAKI1_SHIFT (10u) +#define INTC_ICDISPR6_INTIICALI1_SHIFT (11u) +#define INTC_ICDISPR6_INTIICTMOI1_SHIFT (12u) +#define INTC_ICDISPR6_INTIICTEI2_SHIFT (13u) +#define INTC_ICDISPR6_INTIICRI2_SHIFT (14u) +#define INTC_ICDISPR6_INTIICTI2_SHIFT (15u) +#define INTC_ICDISPR6_INTIICSPI2_SHIFT (16u) +#define INTC_ICDISPR6_INTIICSTI2_SHIFT (17u) +#define INTC_ICDISPR6_INTIICNAKI2_SHIFT (18u) +#define INTC_ICDISPR6_INTIICALI2_SHIFT (19u) +#define INTC_ICDISPR6_INTIICTMOI2_SHIFT (20u) +#define INTC_ICDISPR6_INTIICTEI3_SHIFT (21u) +#define INTC_ICDISPR6_INTIICRI3_SHIFT (22u) +#define INTC_ICDISPR6_INTIICTI3_SHIFT (23u) +#define INTC_ICDISPR6_INTIICSPI3_SHIFT (24u) +#define INTC_ICDISPR6_INTIICSTI3_SHIFT (25u) +#define INTC_ICDISPR6_INTIICNAKI3_SHIFT (26u) +#define INTC_ICDISPR6_INTIICALI3_SHIFT (27u) +#define INTC_ICDISPR6_INTIICTMOI3_SHIFT (28u) +#define INTC_ICDISPR6_BRI0_SHIFT (29u) +#define INTC_ICDISPR6_ERI0_SHIFT (30u) +#define INTC_ICDISPR6_RXI0_SHIFT (31u) + +#define INTC_ICDISPR7_TXI0_SHIFT (0u) +#define INTC_ICDISPR7_BRI1_SHIFT (1u) +#define INTC_ICDISPR7_ERI1_SHIFT (2u) +#define INTC_ICDISPR7_RXI1_SHIFT (3u) +#define INTC_ICDISPR7_TXI1_SHIFT (4u) +#define INTC_ICDISPR7_BRI2_SHIFT (5u) +#define INTC_ICDISPR7_ERI2_SHIFT (6u) +#define INTC_ICDISPR7_RXI2_SHIFT (7u) +#define INTC_ICDISPR7_TXI2_SHIFT (8u) +#define INTC_ICDISPR7_BRI3_SHIFT (9u) +#define INTC_ICDISPR7_ERI3_SHIFT (10u) +#define INTC_ICDISPR7_RXI3_SHIFT (11u) +#define INTC_ICDISPR7_TXI3_SHIFT (12u) +#define INTC_ICDISPR7_BRI4_SHIFT (13u) +#define INTC_ICDISPR7_ERI4_SHIFT (14u) +#define INTC_ICDISPR7_RXI4_SHIFT (15u) +#define INTC_ICDISPR7_TXI4_SHIFT (16u) +#define INTC_ICDISPR7_BRI5_SHIFT (17u) +#define INTC_ICDISPR7_ERI5_SHIFT (18u) +#define INTC_ICDISPR7_RXI5_SHIFT (19u) +#define INTC_ICDISPR7_TXI5_SHIFT (20u) +#define INTC_ICDISPR7_BRI6_SHIFT (21u) +#define INTC_ICDISPR7_ERI6_SHIFT (22u) +#define INTC_ICDISPR7_RXI6_SHIFT (23u) +#define INTC_ICDISPR7_TXI6_SHIFT (24u) +#define INTC_ICDISPR7_BRI7_SHIFT (25u) +#define INTC_ICDISPR7_ERI7_SHIFT (26u) +#define INTC_ICDISPR7_RXI7_SHIFT (27u) +#define INTC_ICDISPR7_TXI7_SHIFT (28u) +#define INTC_ICDISPR7_INTRCANGERR_SHIFT (29u) +#define INTC_ICDISPR7_INTRCANGRECC_SHIFT (30u) +#define INTC_ICDISPR7_INTRCAN0REC_SHIFT (31u) + +#define INTC_ICDISPR8_INTRCAN0ERR_SHIFT (0u) +#define INTC_ICDISPR8_INTRCAN0TRX_SHIFT (1u) +#define INTC_ICDISPR8_INTRCAN1REC_SHIFT (2u) +#define INTC_ICDISPR8_INTRCAN1ERR_SHIFT (3u) +#define INTC_ICDISPR8_INTRCAN1TRX_SHIFT (4u) +#define INTC_ICDISPR8_INTRCAN2REC_SHIFT (5u) +#define INTC_ICDISPR8_INTRCAN2ERR_SHIFT (6u) +#define INTC_ICDISPR8_INTRCAN2TRX_SHIFT (7u) +#define INTC_ICDISPR8_INTRCAN3REC_SHIFT (8u) +#define INTC_ICDISPR8_INTRCAN3ERR_SHIFT (9u) +#define INTC_ICDISPR8_INTRCAN3TRX_SHIFT (10u) +#define INTC_ICDISPR8_INTRCAN4REC_SHIFT (11u) +#define INTC_ICDISPR8_INTRCAN4ERR_SHIFT (12u) +#define INTC_ICDISPR8_INTRCAN4TRX_SHIFT (13u) +#define INTC_ICDISPR8_SPEI0_SHIFT (14u) +#define INTC_ICDISPR8_SPRI0_SHIFT (15u) +#define INTC_ICDISPR8_SPTI0_SHIFT (16u) +#define INTC_ICDISPR8_SPEI1_SHIFT (17u) +#define INTC_ICDISPR8_SPRI1_SHIFT (18u) +#define INTC_ICDISPR8_SPTI1_SHIFT (19u) +#define INTC_ICDISPR8_SPEI2_SHIFT (20u) +#define INTC_ICDISPR8_SPRI2_SHIFT (21u) +#define INTC_ICDISPR8_SPTI2_SHIFT (22u) +#define INTC_ICDISPR8_SPEI3_SHIFT (23u) +#define INTC_ICDISPR8_SPRI3_SHIFT (24u) +#define INTC_ICDISPR8_SPTI3_SHIFT (25u) +#define INTC_ICDISPR8_SPEI4_SHIFT (26u) +#define INTC_ICDISPR8_SPRI4_SHIFT (27u) +#define INTC_ICDISPR8_SPTI4_SHIFT (28u) +#define INTC_ICDISPR8_IEBBTD_SHIFT (29u) +#define INTC_ICDISPR8_IEBBTERR_SHIFT (30u) +#define INTC_ICDISPR8_IEBBTSTA_SHIFT (31u) + +#define INTC_ICDISPR9_IEBBTV_SHIFT (0u) +#define INTC_ICDISPR9_ISY_SHIFT (1u) +#define INTC_ICDISPR9_IERR_SHIFT (2u) +#define INTC_ICDISPR9_ITARG_SHIFT (3u) +#define INTC_ICDISPR9_ISEC_SHIFT (4u) +#define INTC_ICDISPR9_IBUF_SHIFT (5u) +#define INTC_ICDISPR9_IREADY_SHIFT (6u) +#define INTC_ICDISPR9_FLSTE_SHIFT (7u) +#define INTC_ICDISPR9_FLTENDI_SHIFT (8u) +#define INTC_ICDISPR9_FLTREQ0I_SHIFT (9u) +#define INTC_ICDISPR9_FLTREQ1I_SHIFT (10u) +#define INTC_ICDISPR9_MMC0_SHIFT (11u) +#define INTC_ICDISPR9_MMC1_SHIFT (12u) +#define INTC_ICDISPR9_MMC2_SHIFT (13u) +#define INTC_ICDISPR9_SDHI0_3_SHIFT (14u) +#define INTC_ICDISPR9_SDHI0_0_SHIFT (15u) +#define INTC_ICDISPR9_SDHI0_1_SHIFT (16u) +#define INTC_ICDISPR9_SDHI1_3_SHIFT (17u) +#define INTC_ICDISPR9_SDHI1_0_SHIFT (18u) +#define INTC_ICDISPR9_SDHI1_1_SHIFT (19u) +#define INTC_ICDISPR9_ARM_SHIFT (20u) +#define INTC_ICDISPR9_PRD_SHIFT (21u) +#define INTC_ICDISPR9_CUP_SHIFT (22u) +#define INTC_ICDISPR9_SCUAI0_SHIFT (23u) +#define INTC_ICDISPR9_SCUAI1_SHIFT (24u) +#define INTC_ICDISPR9_SCUFDI0_SHIFT (25u) +#define INTC_ICDISPR9_SCUFDI1_SHIFT (26u) +#define INTC_ICDISPR9_SCUFDI2_SHIFT (27u) +#define INTC_ICDISPR9_SCUFDI3_SHIFT (28u) +#define INTC_ICDISPR9_SCUFUI0_SHIFT (29u) +#define INTC_ICDISPR9_SCUFUI1_SHIFT (30u) +#define INTC_ICDISPR9_SCUFUI2_SHIFT (31u) + +#define INTC_ICDISPR10_SCUFUI3_SHIFT (0u) +#define INTC_ICDISPR10_SCUDVI0_SHIFT (1u) +#define INTC_ICDISPR10_SCUDVI1_SHIFT (2u) +#define INTC_ICDISPR10_SCUDVI2_SHIFT (3u) +#define INTC_ICDISPR10_SCUDVI3_SHIFT (4u) +#define INTC_ICDISPR10_MLB_CINT_SHIFT (5u) +#define INTC_ICDISPR10_MLB_SINT_SHIFT (6u) +#define INTC_ICDISPR10_DRC0_SHIFT (7u) +#define INTC_ICDISPR10_DRC1_SHIFT (8u) +#define INTC_ICDISPR10_LINI0_INT_T_SHIFT (11u) +#define INTC_ICDISPR10_LINI0_INT_R_SHIFT (12u) +#define INTC_ICDISPR10_LINI0_INT_S_SHIFT (13u) +#define INTC_ICDISPR10_LINI0_INT_M_SHIFT (14u) +#define INTC_ICDISPR10_LINI1_INT_T_SHIFT (15u) +#define INTC_ICDISPR10_LINI1_INT_R_SHIFT (16u) +#define INTC_ICDISPR10_LINI1_INT_S_SHIFT (17u) +#define INTC_ICDISPR10_LINI1_INT_M_SHIFT (18u) +#define INTC_ICDISPR10_ERI0_SHIFT (27u) +#define INTC_ICDISPR10_RXI0_SHIFT (28u) +#define INTC_ICDISPR10_TXI0_SHIFT (29u) +#define INTC_ICDISPR10_TEI0_SHIFT (30u) +#define INTC_ICDISPR10_ERI1_SHIFT (31u) + +#define INTC_ICDISPR11_RXI1_SHIFT (0u) +#define INTC_ICDISPR11_TXI1_SHIFT (1u) +#define INTC_ICDISPR11_TEI1_SHIFT (2u) +#define INTC_ICDISPR11_AVBI_DATA_SHIFT (3u) +#define INTC_ICDISPR11_AVBI_ERROR_SHIFT (4u) +#define INTC_ICDISPR11_AVBI_MANAGE_SHIFT (5u) +#define INTC_ICDISPR11_AVBI_MAC_SHIFT (6u) +#define INTC_ICDISPR11_ETHERI_SHIFT (7u) +#define INTC_ICDISPR11_CEUI_SHIFT (12u) +#define INTC_ICDISPR11_H2XMLB_ERRINT_SHIFT (29u) +#define INTC_ICDISPR11_H2XIC1_ERRINT_SHIFT (30u) +#define INTC_ICDISPR11_X2HPERI1_ERRINT_SHIFT (31u) + +#define INTC_ICDISPR12_X2HPERI2_ERRINT_SHIFT (0u) +#define INTC_ICDISPR12_X2HPERI34_ERRINT_SHIFT (1u) +#define INTC_ICDISPR12_X2HPERI5_ERRINT_SHIFT (2u) +#define INTC_ICDISPR12_X2HPERI67_ERRINT_SHIFT (3u) +#define INTC_ICDISPR12_X2HDBGR_ERRINT_SHIFT (4u) +#define INTC_ICDISPR12_X2HBSC_ERRINT_SHIFT (5u) +#define INTC_ICDISPR12_X2HSPI1_ERRINT_SHIFT (6u) +#define INTC_ICDISPR12_X2HSPI2_ERRINT_SHIFT (7u) +#define INTC_ICDISPR12_PRRI_SHIFT (8u) +#define INTC_ICDISPR12_IFEI0_SHIFT (9u) +#define INTC_ICDISPR12_OFFI0_SHIFT (10u) +#define INTC_ICDISPR12_PFVEI0_SHIFT (11u) +#define INTC_ICDISPR12_IFEI1_SHIFT (12u) +#define INTC_ICDISPR12_OFFI1_SHIFT (13u) +#define INTC_ICDISPR12_PFVEI1_SHIFT (14u) + +#define INTC_ICDISPR13_TINT0_SHIFT (0u) +#define INTC_ICDISPR13_TINT1_SHIFT (1u) +#define INTC_ICDISPR13_TINT2_SHIFT (2u) +#define INTC_ICDISPR13_TINT3_SHIFT (3u) +#define INTC_ICDISPR13_TINT4_SHIFT (4u) +#define INTC_ICDISPR13_TINT5_SHIFT (5u) +#define INTC_ICDISPR13_TINT6_SHIFT (6u) +#define INTC_ICDISPR13_TINT7_SHIFT (7u) +#define INTC_ICDISPR13_TINT8_SHIFT (8u) +#define INTC_ICDISPR13_TINT9_SHIFT (9u) +#define INTC_ICDISPR13_TINT10_SHIFT (10u) +#define INTC_ICDISPR13_TINT11_SHIFT (11u) +#define INTC_ICDISPR13_TINT12_SHIFT (12u) +#define INTC_ICDISPR13_TINT13_SHIFT (13u) +#define INTC_ICDISPR13_TINT14_SHIFT (14u) +#define INTC_ICDISPR13_TINT15_SHIFT (15u) +#define INTC_ICDISPR13_TINT16_SHIFT (16u) +#define INTC_ICDISPR13_TINT17_SHIFT (17u) +#define INTC_ICDISPR13_TINT18_SHIFT (18u) +#define INTC_ICDISPR13_TINT19_SHIFT (19u) +#define INTC_ICDISPR13_TINT20_SHIFT (20u) +#define INTC_ICDISPR13_TINT21_SHIFT (21u) +#define INTC_ICDISPR13_TINT22_SHIFT (22u) +#define INTC_ICDISPR13_TINT23_SHIFT (23u) +#define INTC_ICDISPR13_TINT24_SHIFT (24u) +#define INTC_ICDISPR13_TINT25_SHIFT (25u) +#define INTC_ICDISPR13_TINT26_SHIFT (26u) +#define INTC_ICDISPR13_TINT27_SHIFT (27u) +#define INTC_ICDISPR13_TINT28_SHIFT (28u) +#define INTC_ICDISPR13_TINT29_SHIFT (29u) +#define INTC_ICDISPR13_TINT30_SHIFT (30u) +#define INTC_ICDISPR13_TINT31_SHIFT (31u) + +#define INTC_ICDISPR14_TINT32_SHIFT (0u) +#define INTC_ICDISPR14_TINT33_SHIFT (1u) +#define INTC_ICDISPR14_TINT34_SHIFT (2u) +#define INTC_ICDISPR14_TINT35_SHIFT (3u) +#define INTC_ICDISPR14_TINT36_SHIFT (4u) +#define INTC_ICDISPR14_TINT37_SHIFT (5u) +#define INTC_ICDISPR14_TINT38_SHIFT (6u) +#define INTC_ICDISPR14_TINT39_SHIFT (7u) +#define INTC_ICDISPR14_TINT40_SHIFT (8u) +#define INTC_ICDISPR14_TINT41_SHIFT (9u) +#define INTC_ICDISPR14_TINT42_SHIFT (10u) +#define INTC_ICDISPR14_TINT43_SHIFT (11u) +#define INTC_ICDISPR14_TINT44_SHIFT (12u) +#define INTC_ICDISPR14_TINT45_SHIFT (13u) +#define INTC_ICDISPR14_TINT46_SHIFT (14u) +#define INTC_ICDISPR14_TINT47_SHIFT (15u) +#define INTC_ICDISPR14_TINT48_SHIFT (16u) +#define INTC_ICDISPR14_TINT49_SHIFT (17u) +#define INTC_ICDISPR14_TINT50_SHIFT (18u) +#define INTC_ICDISPR14_TINT51_SHIFT (19u) +#define INTC_ICDISPR14_TINT52_SHIFT (20u) +#define INTC_ICDISPR14_TINT53_SHIFT (21u) +#define INTC_ICDISPR14_TINT54_SHIFT (22u) +#define INTC_ICDISPR14_TINT55_SHIFT (23u) +#define INTC_ICDISPR14_TINT56_SHIFT (24u) +#define INTC_ICDISPR14_TINT57_SHIFT (25u) +#define INTC_ICDISPR14_TINT58_SHIFT (26u) +#define INTC_ICDISPR14_TINT59_SHIFT (27u) +#define INTC_ICDISPR14_TINT60_SHIFT (28u) +#define INTC_ICDISPR14_TINT61_SHIFT (29u) +#define INTC_ICDISPR14_TINT62_SHIFT (30u) +#define INTC_ICDISPR14_TINT63_SHIFT (31u) + +#define INTC_ICDISPR15_TINT64_SHIFT (0u) +#define INTC_ICDISPR15_TINT65_SHIFT (1u) +#define INTC_ICDISPR15_TINT66_SHIFT (2u) +#define INTC_ICDISPR15_TINT67_SHIFT (3u) +#define INTC_ICDISPR15_TINT68_SHIFT (4u) +#define INTC_ICDISPR15_TINT69_SHIFT (5u) +#define INTC_ICDISPR15_TINT70_SHIFT (6u) +#define INTC_ICDISPR15_TINT71_SHIFT (7u) +#define INTC_ICDISPR15_TINT72_SHIFT (8u) +#define INTC_ICDISPR15_TINT73_SHIFT (9u) +#define INTC_ICDISPR15_TINT74_SHIFT (10u) +#define INTC_ICDISPR15_TINT75_SHIFT (11u) +#define INTC_ICDISPR15_TINT76_SHIFT (12u) +#define INTC_ICDISPR15_TINT77_SHIFT (13u) +#define INTC_ICDISPR15_TINT78_SHIFT (14u) +#define INTC_ICDISPR15_TINT79_SHIFT (15u) +#define INTC_ICDISPR15_TINT80_SHIFT (16u) +#define INTC_ICDISPR15_TINT81_SHIFT (17u) +#define INTC_ICDISPR15_TINT82_SHIFT (18u) +#define INTC_ICDISPR15_TINT83_SHIFT (19u) +#define INTC_ICDISPR15_TINT84_SHIFT (20u) +#define INTC_ICDISPR15_TINT85_SHIFT (21u) +#define INTC_ICDISPR15_TINT86_SHIFT (22u) +#define INTC_ICDISPR15_TINT87_SHIFT (23u) +#define INTC_ICDISPR15_TINT88_SHIFT (24u) +#define INTC_ICDISPR15_TINT89_SHIFT (25u) +#define INTC_ICDISPR15_TINT90_SHIFT (26u) +#define INTC_ICDISPR15_TINT91_SHIFT (27u) +#define INTC_ICDISPR15_TINT92_SHIFT (28u) +#define INTC_ICDISPR15_TINT93_SHIFT (29u) +#define INTC_ICDISPR15_TINT94_SHIFT (30u) +#define INTC_ICDISPR15_TINT95_SHIFT (31u) + +#define INTC_ICDISPR16_TINT96_SHIFT (0u) +#define INTC_ICDISPR16_TINT97_SHIFT (1u) +#define INTC_ICDISPR16_TINT98_SHIFT (2u) +#define INTC_ICDISPR16_TINT99_SHIFT (3u) +#define INTC_ICDISPR16_TINT100_SHIFT (4u) +#define INTC_ICDISPR16_TINT101_SHIFT (5u) +#define INTC_ICDISPR16_TINT102_SHIFT (6u) +#define INTC_ICDISPR16_TINT103_SHIFT (7u) +#define INTC_ICDISPR16_TINT104_SHIFT (8u) +#define INTC_ICDISPR16_TINT105_SHIFT (9u) +#define INTC_ICDISPR16_TINT106_SHIFT (10u) +#define INTC_ICDISPR16_TINT107_SHIFT (11u) +#define INTC_ICDISPR16_TINT108_SHIFT (12u) +#define INTC_ICDISPR16_TINT109_SHIFT (13u) +#define INTC_ICDISPR16_TINT110_SHIFT (14u) +#define INTC_ICDISPR16_TINT111_SHIFT (15u) +#define INTC_ICDISPR16_TINT112_SHIFT (16u) +#define INTC_ICDISPR16_TINT113_SHIFT (17u) +#define INTC_ICDISPR16_TINT114_SHIFT (18u) +#define INTC_ICDISPR16_TINT115_SHIFT (19u) +#define INTC_ICDISPR16_TINT116_SHIFT (20u) +#define INTC_ICDISPR16_TINT117_SHIFT (21u) +#define INTC_ICDISPR16_TINT118_SHIFT (22u) +#define INTC_ICDISPR16_TINT119_SHIFT (23u) +#define INTC_ICDISPR16_TINT120_SHIFT (24u) +#define INTC_ICDISPR16_TINT121_SHIFT (25u) +#define INTC_ICDISPR16_TINT122_SHIFT (26u) +#define INTC_ICDISPR16_TINT123_SHIFT (27u) +#define INTC_ICDISPR16_TINT124_SHIFT (28u) +#define INTC_ICDISPR16_TINT125_SHIFT (29u) +#define INTC_ICDISPR16_TINT126_SHIFT (30u) +#define INTC_ICDISPR16_TINT127_SHIFT (31u) + +#define INTC_ICDISPR17_TINT128_SHIFT (0u) +#define INTC_ICDISPR17_TINT129_SHIFT (1u) +#define INTC_ICDISPR17_TINT130_SHIFT (2u) +#define INTC_ICDISPR17_TINT131_SHIFT (3u) +#define INTC_ICDISPR17_TINT132_SHIFT (4u) +#define INTC_ICDISPR17_TINT133_SHIFT (5u) +#define INTC_ICDISPR17_TINT134_SHIFT (6u) +#define INTC_ICDISPR17_TINT135_SHIFT (7u) +#define INTC_ICDISPR17_TINT136_SHIFT (8u) +#define INTC_ICDISPR17_TINT137_SHIFT (9u) +#define INTC_ICDISPR17_TINT138_SHIFT (10u) +#define INTC_ICDISPR17_TINT139_SHIFT (11u) +#define INTC_ICDISPR17_TINT140_SHIFT (12u) +#define INTC_ICDISPR17_TINT141_SHIFT (13u) +#define INTC_ICDISPR17_TINT142_SHIFT (14u) +#define INTC_ICDISPR17_TINT143_SHIFT (15u) +#define INTC_ICDISPR17_TINT144_SHIFT (16u) +#define INTC_ICDISPR17_TINT145_SHIFT (17u) +#define INTC_ICDISPR17_TINT146_SHIFT (18u) +#define INTC_ICDISPR17_TINT147_SHIFT (19u) +#define INTC_ICDISPR17_TINT148_SHIFT (20u) +#define INTC_ICDISPR17_TINT149_SHIFT (21u) +#define INTC_ICDISPR17_TINT150_SHIFT (22u) +#define INTC_ICDISPR17_TINT151_SHIFT (23u) +#define INTC_ICDISPR17_TINT152_SHIFT (24u) +#define INTC_ICDISPR17_TINT153_SHIFT (25u) +#define INTC_ICDISPR17_TINT154_SHIFT (26u) +#define INTC_ICDISPR17_TINT155_SHIFT (27u) +#define INTC_ICDISPR17_TINT156_SHIFT (28u) +#define INTC_ICDISPR17_TINT157_SHIFT (29u) +#define INTC_ICDISPR17_TINT158_SHIFT (30u) +#define INTC_ICDISPR17_TINT159_SHIFT (31u) + +#define INTC_ICDISPR18_TINT160_SHIFT (0u) +#define INTC_ICDISPR18_TINT161_SHIFT (1u) +#define INTC_ICDISPR18_TINT162_SHIFT (2u) +#define INTC_ICDISPR18_TINT163_SHIFT (3u) +#define INTC_ICDISPR18_TINT164_SHIFT (4u) +#define INTC_ICDISPR18_TINT165_SHIFT (5u) +#define INTC_ICDISPR18_TINT166_SHIFT (6u) +#define INTC_ICDISPR18_TINT167_SHIFT (7u) +#define INTC_ICDISPR18_TINT168_SHIFT (8u) +#define INTC_ICDISPR18_TINT169_SHIFT (9u) +#define INTC_ICDISPR18_TINT170_SHIFT (10u) + +#define INTC_ICDICPR0_SW0_SHIFT (0u) +#define INTC_ICDICPR0_SW1_SHIFT (1u) +#define INTC_ICDICPR0_SW2_SHIFT (2u) +#define INTC_ICDICPR0_SW3_SHIFT (3u) +#define INTC_ICDICPR0_SW4_SHIFT (4u) +#define INTC_ICDICPR0_SW5_SHIFT (5u) +#define INTC_ICDICPR0_SW6_SHIFT (6u) +#define INTC_ICDICPR0_SW7_SHIFT (7u) +#define INTC_ICDICPR0_SW8_SHIFT (8u) +#define INTC_ICDICPR0_SW9_SHIFT (9u) +#define INTC_ICDICPR0_SW10_SHIFT (10u) +#define INTC_ICDICPR0_SW11_SHIFT (11u) +#define INTC_ICDICPR0_SW12_SHIFT (12u) +#define INTC_ICDICPR0_SW13_SHIFT (13u) +#define INTC_ICDICPR0_SW14_SHIFT (14u) +#define INTC_ICDICPR0_SW15_SHIFT (15u) +#define INTC_ICDICPR0_PMUIRQ0_SHIFT (16u) +#define INTC_ICDICPR0_COMMRX0_SHIFT (17u) +#define INTC_ICDICPR0_COMMTX0_SHIFT (18u) +#define INTC_ICDICPR0_CTIIRQ0_SHIFT (19u) + +#define INTC_ICDICPR1_IRQ0_SHIFT (0u) +#define INTC_ICDICPR1_IRQ1_SHIFT (1u) +#define INTC_ICDICPR1_IRQ2_SHIFT (2u) +#define INTC_ICDICPR1_IRQ3_SHIFT (3u) +#define INTC_ICDICPR1_IRQ4_SHIFT (4u) +#define INTC_ICDICPR1_IRQ5_SHIFT (5u) +#define INTC_ICDICPR1_IRQ6_SHIFT (6u) +#define INTC_ICDICPR1_IRQ7_SHIFT (7u) +#define INTC_ICDICPR1_PL310ERR_SHIFT (8u) +#define INTC_ICDICPR1_DMAINT0_SHIFT (9u) +#define INTC_ICDICPR1_DMAINT1_SHIFT (10u) +#define INTC_ICDICPR1_DMAINT2_SHIFT (11u) +#define INTC_ICDICPR1_DMAINT3_SHIFT (12u) +#define INTC_ICDICPR1_DMAINT4_SHIFT (13u) +#define INTC_ICDICPR1_DMAINT5_SHIFT (14u) +#define INTC_ICDICPR1_DMAINT6_SHIFT (15u) +#define INTC_ICDICPR1_DMAINT7_SHIFT (16u) +#define INTC_ICDICPR1_DMAINT8_SHIFT (17u) +#define INTC_ICDICPR1_DMAINT9_SHIFT (18u) +#define INTC_ICDICPR1_DMAINT10_SHIFT (19u) +#define INTC_ICDICPR1_DMAINT11_SHIFT (20u) +#define INTC_ICDICPR1_DMAINT12_SHIFT (21u) +#define INTC_ICDICPR1_DMAINT13_SHIFT (22u) +#define INTC_ICDICPR1_DMAINT14_SHIFT (23u) +#define INTC_ICDICPR1_DMAINT15_SHIFT (24u) +#define INTC_ICDICPR1_DMAERR_SHIFT (25u) + +#define INTC_ICDICPR2_USBI0_SHIFT (9u) +#define INTC_ICDICPR2_USBI1_SHIFT (10u) +#define INTC_ICDICPR2_S0_VI_VSYNC0_SHIFT (11u) +#define INTC_ICDICPR2_S0_LO_VSYNC0_SHIFT (12u) +#define INTC_ICDICPR2_S0_VSYNCERR0_SHIFT (13u) +#define INTC_ICDICPR2_GR3_VLINE0_SHIFT (14u) +#define INTC_ICDICPR2_S0_VFIELD0_SHIFT (15u) +#define INTC_ICDICPR2_IV1_VBUFERR0_SHIFT (16u) +#define INTC_ICDICPR2_IV3_VBUFERR0_SHIFT (17u) +#define INTC_ICDICPR2_IV5_VBUFERR0_SHIFT (18u) +#define INTC_ICDICPR2_IV6_VBUFERR0_SHIFT (19u) +#define INTC_ICDICPR2_S0_WLINE0_SHIFT (20u) +#define INTC_ICDICPR2_S1_VI_VSYNC0_SHIFT (21u) +#define INTC_ICDICPR2_S1_LO_VSYNC0_SHIFT (22u) +#define INTC_ICDICPR2_S1_VSYNCERR0_SHIFT (23u) +#define INTC_ICDICPR2_S1_VFIELD0_SHIFT (24u) +#define INTC_ICDICPR2_IV2_VBUFERR0_SHIFT (25u) +#define INTC_ICDICPR2_IV4_VBUFERR0_SHIFT (26u) +#define INTC_ICDICPR2_S1_WLINE0_SHIFT (27u) +#define INTC_ICDICPR2_OIR_VI_VSYNC0_SHIFT (28u) +#define INTC_ICDICPR2_OIR_LO_VSYNC0_SHIFT (29u) +#define INTC_ICDICPR2_OIR_VSYNCERR0_SHIFT (30u) +#define INTC_ICDICPR2_OIR_VFIELD0_SHIFT (31u) + +#define INTC_ICDICPR3_IV7_VBUFERR0_SHIFT (0u) +#define INTC_ICDICPR3_IV8_VBUFERR0_SHIFT (1u) +#define INTC_ICDICPR3_S0_VI_VSYNC1_SHIFT (3u) +#define INTC_ICDICPR3_S0_LO_VSYNC1_SHIFT (4u) +#define INTC_ICDICPR3_S0_VSYNCERR1_SHIFT (5u) +#define INTC_ICDICPR3_GR3_VLINE1_SHIFT (6u) +#define INTC_ICDICPR3_S0_VFIELD1_SHIFT (7u) +#define INTC_ICDICPR3_IV1_VBUFERR1_SHIFT (8u) +#define INTC_ICDICPR3_IV3_VBUFERR1_SHIFT (9u) +#define INTC_ICDICPR3_IV5_VBUFERR1_SHIFT (10u) +#define INTC_ICDICPR3_IV6_VBUFERR1_SHIFT (11u) +#define INTC_ICDICPR3_S0_WLINE1_SHIFT (12u) +#define INTC_ICDICPR3_S1_VI_VSYNC1_SHIFT (13u) +#define INTC_ICDICPR3_S1_LO_VSYNC1_SHIFT (14u) +#define INTC_ICDICPR3_S1_VSYNCERR1_SHIFT (15u) +#define INTC_ICDICPR3_S1_VFIELD1_SHIFT (16u) +#define INTC_ICDICPR3_IV2_VBUFERR1_SHIFT (17u) +#define INTC_ICDICPR3_IV4_VBUFERR1_SHIFT (18u) +#define INTC_ICDICPR3_S1_WLINE1_SHIFT (19u) +#define INTC_ICDICPR3_OIR_VI_VSYNC1_SHIFT (20u) +#define INTC_ICDICPR3_OIR_LO_VSYNC1_SHIFT (21u) +#define INTC_ICDICPR3_OIR_VLINE1_SHIFT (22u) +#define INTC_ICDICPR3_OIR_VFIELD1_SHIFT (23u) +#define INTC_ICDICPR3_IV7_VBUFERR1_SHIFT (24u) +#define INTC_ICDICPR3_IV8_VBUFERR1_SHIFT (25u) +#define INTC_ICDICPR3_IMRDI_SHIFT (27u) +#define INTC_ICDICPR3_IMR2I0_SHIFT (28u) +#define INTC_ICDICPR3_IMR2I1_SHIFT (29u) +#define INTC_ICDICPR3_JEDI_SHIFT (30u) +#define INTC_ICDICPR3_JDTI_SHIFT (31u) + +#define INTC_ICDICPR4_CMP0_SHIFT (0u) +#define INTC_ICDICPR4_CMP1_SHIFT (1u) +#define INTC_ICDICPR4_INT0_SHIFT (2u) +#define INTC_ICDICPR4_INT1_SHIFT (3u) +#define INTC_ICDICPR4_INT2_SHIFT (4u) +#define INTC_ICDICPR4_INT3_SHIFT (5u) +#define INTC_ICDICPR4_OSTM0TINT_SHIFT (6u) +#define INTC_ICDICPR4_OSTM1TINT_SHIFT (7u) +#define INTC_ICDICPR4_CMI_SHIFT (8u) +#define INTC_ICDICPR4_WTOUT_SHIFT (9u) +#define INTC_ICDICPR4_ITI_SHIFT (10u) +#define INTC_ICDICPR4_TGI0A_SHIFT (11u) +#define INTC_ICDICPR4_TGI0B_SHIFT (12u) +#define INTC_ICDICPR4_TGI0C_SHIFT (13u) +#define INTC_ICDICPR4_TGI0D_SHIFT (14u) +#define INTC_ICDICPR4_TGI0V_SHIFT (15u) +#define INTC_ICDICPR4_TGI0E_SHIFT (16u) +#define INTC_ICDICPR4_TGI0F_SHIFT (17u) +#define INTC_ICDICPR4_TGI1A_SHIFT (18u) +#define INTC_ICDICPR4_TGI1B_SHIFT (19u) +#define INTC_ICDICPR4_TGI1V_SHIFT (20u) +#define INTC_ICDICPR4_TGI1U_SHIFT (21u) +#define INTC_ICDICPR4_TGI2A_SHIFT (22u) +#define INTC_ICDICPR4_TGI2B_SHIFT (23u) +#define INTC_ICDICPR4_TGI2V_SHIFT (24u) +#define INTC_ICDICPR4_TGI2U_SHIFT (25u) +#define INTC_ICDICPR4_TGI3A_SHIFT (26u) +#define INTC_ICDICPR4_TGI3B_SHIFT (27u) +#define INTC_ICDICPR4_TGI3C_SHIFT (28u) +#define INTC_ICDICPR4_TGI3D_SHIFT (29u) +#define INTC_ICDICPR4_TGI3V_SHIFT (30u) +#define INTC_ICDICPR4_TGI4A_SHIFT (31u) + +#define INTC_ICDICPR5_TGI4B_SHIFT (0u) +#define INTC_ICDICPR5_TGI4C_SHIFT (1u) +#define INTC_ICDICPR5_TGI4D_SHIFT (2u) +#define INTC_ICDICPR5_TGI4V_SHIFT (3u) +#define INTC_ICDICPR5_CMI1_SHIFT (4u) +#define INTC_ICDICPR5_CMI2_SHIFT (5u) +#define INTC_ICDICPR5_SGDEI0_SHIFT (6u) +#define INTC_ICDICPR5_SGDEI1_SHIFT (7u) +#define INTC_ICDICPR5_SGDEI2_SHIFT (8u) +#define INTC_ICDICPR5_SGDEI3_SHIFT (9u) +#define INTC_ICDICPR5_ADI_SHIFT (10u) +#define INTC_ICDICPR5_LMTI_SHIFT (11u) +#define INTC_ICDICPR5_SSII0_SHIFT (12u) +#define INTC_ICDICPR5_SSIRXI0_SHIFT (13u) +#define INTC_ICDICPR5_SSITXI0_SHIFT (14u) +#define INTC_ICDICPR5_SSII1_SHIFT (15u) +#define INTC_ICDICPR5_SSIRXI1_SHIFT (16u) +#define INTC_ICDICPR5_SSITXI1_SHIFT (17u) +#define INTC_ICDICPR5_SSII2_SHIFT (18u) +#define INTC_ICDICPR5_SSIRTI2_SHIFT (19u) +#define INTC_ICDICPR5_SSII3_SHIFT (20u) +#define INTC_ICDICPR5_SSIRXI3_SHIFT (21u) +#define INTC_ICDICPR5_SSITXI3_SHIFT (22u) +#define INTC_ICDICPR5_SSII4_SHIFT (23u) +#define INTC_ICDICPR5_SSIRTI4_SHIFT (24u) +#define INTC_ICDICPR5_SSII5_SHIFT (25u) +#define INTC_ICDICPR5_SSIRXI5_SHIFT (26u) +#define INTC_ICDICPR5_SSITXI5_SHIFT (27u) +#define INTC_ICDICPR5_SPDIFI_SHIFT (28u) +#define INTC_ICDICPR5_INTIICTEI0_SHIFT (29u) +#define INTC_ICDICPR5_INTIICRI0_SHIFT (30u) +#define INTC_ICDICPR5_INTIICTI0_SHIFT (31u) + +#define INTC_ICDICPR6_INTIICSPI0_SHIFT (0u) +#define INTC_ICDICPR6_INTIICSTI0_SHIFT (1u) +#define INTC_ICDICPR6_INTIICNAKI0_SHIFT (2u) +#define INTC_ICDICPR6_INTIICALI0_SHIFT (3u) +#define INTC_ICDICPR6_INTIICTMOI0_SHIFT (4u) +#define INTC_ICDICPR6_INTIICTEI1_SHIFT (5u) +#define INTC_ICDICPR6_INTIICRI1_SHIFT (6u) +#define INTC_ICDICPR6_INTIICTI1_SHIFT (7u) +#define INTC_ICDICPR6_INTIICSPI1_SHIFT (8u) +#define INTC_ICDICPR6_INTIICSTI1_SHIFT (9u) +#define INTC_ICDICPR6_INTIICNAKI1_SHIFT (10u) +#define INTC_ICDICPR6_INTIICALI1_SHIFT (11u) +#define INTC_ICDICPR6_INTIICTMOI1_SHIFT (12u) +#define INTC_ICDICPR6_INTIICTEI2_SHIFT (13u) +#define INTC_ICDICPR6_INTIICRI2_SHIFT (14u) +#define INTC_ICDICPR6_INTIICTI2_SHIFT (15u) +#define INTC_ICDICPR6_INTIICSPI2_SHIFT (16u) +#define INTC_ICDICPR6_INTIICSTI2_SHIFT (17u) +#define INTC_ICDICPR6_INTIICNAKI2_SHIFT (18u) +#define INTC_ICDICPR6_INTIICALI2_SHIFT (19u) +#define INTC_ICDICPR6_INTIICTMOI2_SHIFT (20u) +#define INTC_ICDICPR6_INTIICTEI3_SHIFT (21u) +#define INTC_ICDICPR6_INTIICRI3_SHIFT (22u) +#define INTC_ICDICPR6_INTIICTI3_SHIFT (23u) +#define INTC_ICDICPR6_INTIICSPI3_SHIFT (24u) +#define INTC_ICDICPR6_INTIICSTI3_SHIFT (25u) +#define INTC_ICDICPR6_INTIICNAKI3_SHIFT (26u) +#define INTC_ICDICPR6_INTIICALI3_SHIFT (27u) +#define INTC_ICDICPR6_INTIICTMOI3_SHIFT (28u) +#define INTC_ICDICPR6_BRI0_SHIFT (29u) +#define INTC_ICDICPR6_ERI0_SHIFT (30u) +#define INTC_ICDICPR6_RXI0_SHIFT (31u) + +#define INTC_ICDICPR7_TXI0_SHIFT (0u) +#define INTC_ICDICPR7_BRI1_SHIFT (1u) +#define INTC_ICDICPR7_ERI1_SHIFT (2u) +#define INTC_ICDICPR7_RXI1_SHIFT (3u) +#define INTC_ICDICPR7_TXI1_SHIFT (4u) +#define INTC_ICDICPR7_BRI2_SHIFT (5u) +#define INTC_ICDICPR7_ERI2_SHIFT (6u) +#define INTC_ICDICPR7_RXI2_SHIFT (7u) +#define INTC_ICDICPR7_TXI2_SHIFT (8u) +#define INTC_ICDICPR7_BRI3_SHIFT (9u) +#define INTC_ICDICPR7_ERI3_SHIFT (10u) +#define INTC_ICDICPR7_RXI3_SHIFT (11u) +#define INTC_ICDICPR7_TXI3_SHIFT (12u) +#define INTC_ICDICPR7_BRI4_SHIFT (13u) +#define INTC_ICDICPR7_ERI4_SHIFT (14u) +#define INTC_ICDICPR7_RXI4_SHIFT (15u) +#define INTC_ICDICPR7_TXI4_SHIFT (16u) +#define INTC_ICDICPR7_BRI5_SHIFT (17u) +#define INTC_ICDICPR7_ERI5_SHIFT (18u) +#define INTC_ICDICPR7_RXI5_SHIFT (19u) +#define INTC_ICDICPR7_TXI5_SHIFT (20u) +#define INTC_ICDICPR7_BRI6_SHIFT (21u) +#define INTC_ICDICPR7_ERI6_SHIFT (22u) +#define INTC_ICDICPR7_RXI6_SHIFT (23u) +#define INTC_ICDICPR7_TXI6_SHIFT (24u) +#define INTC_ICDICPR7_BRI7_SHIFT (25u) +#define INTC_ICDICPR7_ERI7_SHIFT (26u) +#define INTC_ICDICPR7_RXI7_SHIFT (27u) +#define INTC_ICDICPR7_TXI7_SHIFT (28u) +#define INTC_ICDICPR7_INTRCANGERR_SHIFT (29u) +#define INTC_ICDICPR7_INTRCANGRECC_SHIFT (30u) +#define INTC_ICDICPR7_INTRCAN0REC_SHIFT (31u) + +#define INTC_ICDICPR8_INTRCAN0ERR_SHIFT (0u) +#define INTC_ICDICPR8_INTRCAN0TRX_SHIFT (1u) +#define INTC_ICDICPR8_INTRCAN1REC_SHIFT (2u) +#define INTC_ICDICPR8_INTRCAN1ERR_SHIFT (3u) +#define INTC_ICDICPR8_INTRCAN1TRX_SHIFT (4u) +#define INTC_ICDICPR8_INTRCAN2REC_SHIFT (5u) +#define INTC_ICDICPR8_INTRCAN2ERR_SHIFT (6u) +#define INTC_ICDICPR8_INTRCAN2TRX_SHIFT (7u) +#define INTC_ICDICPR8_INTRCAN3REC_SHIFT (8u) +#define INTC_ICDICPR8_INTRCAN3ERR_SHIFT (9u) +#define INTC_ICDICPR8_INTRCAN3TRX_SHIFT (10u) +#define INTC_ICDICPR8_INTRCAN4REC_SHIFT (11u) +#define INTC_ICDICPR8_INTRCAN4ERR_SHIFT (12u) +#define INTC_ICDICPR8_INTRCAN4TRX_SHIFT (13u) +#define INTC_ICDICPR8_SPEI0_SHIFT (14u) +#define INTC_ICDICPR8_SPRI0_SHIFT (15u) +#define INTC_ICDICPR8_SPTI0_SHIFT (16u) +#define INTC_ICDICPR8_SPEI1_SHIFT (17u) +#define INTC_ICDICPR8_SPRI1_SHIFT (18u) +#define INTC_ICDICPR8_SPTI1_SHIFT (19u) +#define INTC_ICDICPR8_SPEI2_SHIFT (20u) +#define INTC_ICDICPR8_SPRI2_SHIFT (21u) +#define INTC_ICDICPR8_SPTI2_SHIFT (22u) +#define INTC_ICDICPR8_SPEI3_SHIFT (23u) +#define INTC_ICDICPR8_SPRI3_SHIFT (24u) +#define INTC_ICDICPR8_SPTI3_SHIFT (25u) +#define INTC_ICDICPR8_SPEI4_SHIFT (26u) +#define INTC_ICDICPR8_SPRI4_SHIFT (27u) +#define INTC_ICDICPR8_SPTI4_SHIFT (28u) +#define INTC_ICDICPR8_IEBBTD_SHIFT (29u) +#define INTC_ICDICPR8_IEBBTERR_SHIFT (30u) +#define INTC_ICDICPR8_IEBBTSTA_SHIFT (31u) + +#define INTC_ICDICPR9_IEBBTV_SHIFT (0u) +#define INTC_ICDICPR9_ISY_SHIFT (1u) +#define INTC_ICDICPR9_IERR_SHIFT (2u) +#define INTC_ICDICPR9_ITARG_SHIFT (3u) +#define INTC_ICDICPR9_ISEC_SHIFT (4u) +#define INTC_ICDICPR9_IBUF_SHIFT (5u) +#define INTC_ICDICPR9_IREADY_SHIFT (6u) +#define INTC_ICDICPR9_FLSTE_SHIFT (7u) +#define INTC_ICDICPR9_FLTENDI_SHIFT (8u) +#define INTC_ICDICPR9_FLTREQ0I_SHIFT (9u) +#define INTC_ICDICPR9_FLTREQ1I_SHIFT (10u) +#define INTC_ICDICPR9_MMC0_SHIFT (11u) +#define INTC_ICDICPR9_MMC1_SHIFT (12u) +#define INTC_ICDICPR9_MMC2_SHIFT (13u) +#define INTC_ICDICPR9_SDHI0_3_SHIFT (14u) +#define INTC_ICDICPR9_SDHI0_0_SHIFT (15u) +#define INTC_ICDICPR9_SDHI0_1_SHIFT (16u) +#define INTC_ICDICPR9_SDHI1_3_SHIFT (17u) +#define INTC_ICDICPR9_SDHI1_0_SHIFT (18u) +#define INTC_ICDICPR9_SDHI1_1_SHIFT (19u) +#define INTC_ICDICPR9_ARM_SHIFT (20u) +#define INTC_ICDICPR9_PRD_SHIFT (21u) +#define INTC_ICDICPR9_CUP_SHIFT (22u) +#define INTC_ICDICPR9_SCUAI0_SHIFT (23u) +#define INTC_ICDICPR9_SCUAI1_SHIFT (24u) +#define INTC_ICDICPR9_SCUFDI0_SHIFT (25u) +#define INTC_ICDICPR9_SCUFDI1_SHIFT (26u) +#define INTC_ICDICPR9_SCUFDI2_SHIFT (27u) +#define INTC_ICDICPR9_SCUFDI3_SHIFT (28u) +#define INTC_ICDICPR9_SCUFUI0_SHIFT (29u) +#define INTC_ICDICPR9_SCUFUI1_SHIFT (30u) +#define INTC_ICDICPR9_SCUFUI2_SHIFT (31u) + +#define INTC_ICDICPR10_SCUFUI3_SHIFT (0u) +#define INTC_ICDICPR10_SCUDVI0_SHIFT (1u) +#define INTC_ICDICPR10_SCUDVI1_SHIFT (2u) +#define INTC_ICDICPR10_SCUDVI2_SHIFT (3u) +#define INTC_ICDICPR10_SCUDVI3_SHIFT (4u) +#define INTC_ICDICPR10_MLB_CINT_SHIFT (5u) +#define INTC_ICDICPR10_MLB_SINT_SHIFT (6u) +#define INTC_ICDICPR10_DRC0_SHIFT (7u) +#define INTC_ICDICPR10_DRC1_SHIFT (8u) +#define INTC_ICDICPR10_LINI0_INT_T_SHIFT (11u) +#define INTC_ICDICPR10_LINI0_INT_R_SHIFT (12u) +#define INTC_ICDICPR10_LINI0_INT_S_SHIFT (13u) +#define INTC_ICDICPR10_LINI0_INT_M_SHIFT (14u) +#define INTC_ICDICPR10_LINI1_INT_T_SHIFT (15u) +#define INTC_ICDICPR10_LINI1_INT_R_SHIFT (16u) +#define INTC_ICDICPR10_LINI1_INT_S_SHIFT (17u) +#define INTC_ICDICPR10_LINI1_INT_M_SHIFT (18u) +#define INTC_ICDICPR10_ERI0_SHIFT (27u) +#define INTC_ICDICPR10_RXI0_SHIFT (28u) +#define INTC_ICDICPR10_TXI0_SHIFT (29u) +#define INTC_ICDICPR10_TEI0_SHIFT (30u) +#define INTC_ICDICPR10_ERI1_SHIFT (31u) + +#define INTC_ICDICPR11_RXI1_SHIFT (0u) +#define INTC_ICDICPR11_TXI1_SHIFT (1u) +#define INTC_ICDICPR11_TEI1_SHIFT (2u) +#define INTC_ICDICPR11_AVBI_DATA_SHIFT (3u) +#define INTC_ICDICPR11_AVBI_ERROR_SHIFT (4u) +#define INTC_ICDICPR11_AVBI_MANAGE_SHIFT (5u) +#define INTC_ICDICPR11_AVBI_MAC_SHIFT (6u) +#define INTC_ICDICPR11_ETHERI_SHIFT (7u) +#define INTC_ICDICPR11_CEUI_SHIFT (12u) +#define INTC_ICDICPR11_H2XMLB_ERRINT_SHIFT (29u) +#define INTC_ICDICPR11_H2XIC1_ERRINT_SHIFT (30u) +#define INTC_ICDICPR11_X2HPERI1_ERRINT_SHIFT (31u) + +#define INTC_ICDICPR12_X2HPERI2_ERRINT_SHIFT (0u) +#define INTC_ICDICPR12_X2HPERI34_ERRINT_SHIFT (1u) +#define INTC_ICDICPR12_X2HPERI5_ERRINT_SHIFT (2u) +#define INTC_ICDICPR12_X2HPERI67_ERRINT_SHIFT (3u) +#define INTC_ICDICPR12_X2HDBGR_ERRINT_SHIFT (4u) +#define INTC_ICDICPR12_X2HBSC_ERRINT_SHIFT (5u) +#define INTC_ICDICPR12_X2HSPI1_ERRINT_SHIFT (6u) +#define INTC_ICDICPR12_X2HSPI2_ERRINT_SHIFT (7u) +#define INTC_ICDICPR12_PRRI_SHIFT (8u) +#define INTC_ICDICPR12_IFEI0_SHIFT (9u) +#define INTC_ICDICPR12_OFFI0_SHIFT (10u) +#define INTC_ICDICPR12_PFVEI0_SHIFT (11u) +#define INTC_ICDICPR12_IFEI1_SHIFT (12u) +#define INTC_ICDICPR12_OFFI1_SHIFT (13u) +#define INTC_ICDICPR12_PFVEI1_SHIFT (14u) + +#define INTC_ICDICPR13_TINT0_SHIFT (0u) +#define INTC_ICDICPR13_TINT1_SHIFT (1u) +#define INTC_ICDICPR13_TINT2_SHIFT (2u) +#define INTC_ICDICPR13_TINT3_SHIFT (3u) +#define INTC_ICDICPR13_TINT4_SHIFT (4u) +#define INTC_ICDICPR13_TINT5_SHIFT (5u) +#define INTC_ICDICPR13_TINT6_SHIFT (6u) +#define INTC_ICDICPR13_TINT7_SHIFT (7u) +#define INTC_ICDICPR13_TINT8_SHIFT (8u) +#define INTC_ICDICPR13_TINT9_SHIFT (9u) +#define INTC_ICDICPR13_TINT10_SHIFT (10u) +#define INTC_ICDICPR13_TINT11_SHIFT (11u) +#define INTC_ICDICPR13_TINT12_SHIFT (12u) +#define INTC_ICDICPR13_TINT13_SHIFT (13u) +#define INTC_ICDICPR13_TINT14_SHIFT (14u) +#define INTC_ICDICPR13_TINT15_SHIFT (15u) +#define INTC_ICDICPR13_TINT16_SHIFT (16u) +#define INTC_ICDICPR13_TINT17_SHIFT (17u) +#define INTC_ICDICPR13_TINT18_SHIFT (18u) +#define INTC_ICDICPR13_TINT19_SHIFT (19u) +#define INTC_ICDICPR13_TINT20_SHIFT (20u) +#define INTC_ICDICPR13_TINT21_SHIFT (21u) +#define INTC_ICDICPR13_TINT22_SHIFT (22u) +#define INTC_ICDICPR13_TINT23_SHIFT (23u) +#define INTC_ICDICPR13_TINT24_SHIFT (24u) +#define INTC_ICDICPR13_TINT25_SHIFT (25u) +#define INTC_ICDICPR13_TINT26_SHIFT (26u) +#define INTC_ICDICPR13_TINT27_SHIFT (27u) +#define INTC_ICDICPR13_TINT28_SHIFT (28u) +#define INTC_ICDICPR13_TINT29_SHIFT (29u) +#define INTC_ICDICPR13_TINT30_SHIFT (30u) +#define INTC_ICDICPR13_TINT31_SHIFT (31u) + +#define INTC_ICDICPR14_TINT32_SHIFT (0u) +#define INTC_ICDICPR14_TINT33_SHIFT (1u) +#define INTC_ICDICPR14_TINT34_SHIFT (2u) +#define INTC_ICDICPR14_TINT35_SHIFT (3u) +#define INTC_ICDICPR14_TINT36_SHIFT (4u) +#define INTC_ICDICPR14_TINT37_SHIFT (5u) +#define INTC_ICDICPR14_TINT38_SHIFT (6u) +#define INTC_ICDICPR14_TINT39_SHIFT (7u) +#define INTC_ICDICPR14_TINT40_SHIFT (8u) +#define INTC_ICDICPR14_TINT41_SHIFT (9u) +#define INTC_ICDICPR14_TINT42_SHIFT (10u) +#define INTC_ICDICPR14_TINT43_SHIFT (11u) +#define INTC_ICDICPR14_TINT44_SHIFT (12u) +#define INTC_ICDICPR14_TINT45_SHIFT (13u) +#define INTC_ICDICPR14_TINT46_SHIFT (14u) +#define INTC_ICDICPR14_TINT47_SHIFT (15u) +#define INTC_ICDICPR14_TINT48_SHIFT (16u) +#define INTC_ICDICPR14_TINT49_SHIFT (17u) +#define INTC_ICDICPR14_TINT50_SHIFT (18u) +#define INTC_ICDICPR14_TINT51_SHIFT (19u) +#define INTC_ICDICPR14_TINT52_SHIFT (20u) +#define INTC_ICDICPR14_TINT53_SHIFT (21u) +#define INTC_ICDICPR14_TINT54_SHIFT (22u) +#define INTC_ICDICPR14_TINT55_SHIFT (23u) +#define INTC_ICDICPR14_TINT56_SHIFT (24u) +#define INTC_ICDICPR14_TINT57_SHIFT (25u) +#define INTC_ICDICPR14_TINT58_SHIFT (26u) +#define INTC_ICDICPR14_TINT59_SHIFT (27u) +#define INTC_ICDICPR14_TINT60_SHIFT (28u) +#define INTC_ICDICPR14_TINT61_SHIFT (29u) +#define INTC_ICDICPR14_TINT62_SHIFT (30u) +#define INTC_ICDICPR14_TINT63_SHIFT (31u) + +#define INTC_ICDICPR15_TINT64_SHIFT (0u) +#define INTC_ICDICPR15_TINT65_SHIFT (1u) +#define INTC_ICDICPR15_TINT66_SHIFT (2u) +#define INTC_ICDICPR15_TINT67_SHIFT (3u) +#define INTC_ICDICPR15_TINT68_SHIFT (4u) +#define INTC_ICDICPR15_TINT69_SHIFT (5u) +#define INTC_ICDICPR15_TINT70_SHIFT (6u) +#define INTC_ICDICPR15_TINT71_SHIFT (7u) +#define INTC_ICDICPR15_TINT72_SHIFT (8u) +#define INTC_ICDICPR15_TINT73_SHIFT (9u) +#define INTC_ICDICPR15_TINT74_SHIFT (10u) +#define INTC_ICDICPR15_TINT75_SHIFT (11u) +#define INTC_ICDICPR15_TINT76_SHIFT (12u) +#define INTC_ICDICPR15_TINT77_SHIFT (13u) +#define INTC_ICDICPR15_TINT78_SHIFT (14u) +#define INTC_ICDICPR15_TINT79_SHIFT (15u) +#define INTC_ICDICPR15_TINT80_SHIFT (16u) +#define INTC_ICDICPR15_TINT81_SHIFT (17u) +#define INTC_ICDICPR15_TINT82_SHIFT (18u) +#define INTC_ICDICPR15_TINT83_SHIFT (19u) +#define INTC_ICDICPR15_TINT84_SHIFT (20u) +#define INTC_ICDICPR15_TINT85_SHIFT (21u) +#define INTC_ICDICPR15_TINT86_SHIFT (22u) +#define INTC_ICDICPR15_TINT87_SHIFT (23u) +#define INTC_ICDICPR15_TINT88_SHIFT (24u) +#define INTC_ICDICPR15_TINT89_SHIFT (25u) +#define INTC_ICDICPR15_TINT90_SHIFT (26u) +#define INTC_ICDICPR15_TINT91_SHIFT (27u) +#define INTC_ICDICPR15_TINT92_SHIFT (28u) +#define INTC_ICDICPR15_TINT93_SHIFT (29u) +#define INTC_ICDICPR15_TINT94_SHIFT (30u) +#define INTC_ICDICPR15_TINT95_SHIFT (31u) + +#define INTC_ICDICPR16_TINT96_SHIFT (0u) +#define INTC_ICDICPR16_TINT97_SHIFT (1u) +#define INTC_ICDICPR16_TINT98_SHIFT (2u) +#define INTC_ICDICPR16_TINT99_SHIFT (3u) +#define INTC_ICDICPR16_TINT100_SHIFT (4u) +#define INTC_ICDICPR16_TINT101_SHIFT (5u) +#define INTC_ICDICPR16_TINT102_SHIFT (6u) +#define INTC_ICDICPR16_TINT103_SHIFT (7u) +#define INTC_ICDICPR16_TINT104_SHIFT (8u) +#define INTC_ICDICPR16_TINT105_SHIFT (9u) +#define INTC_ICDICPR16_TINT106_SHIFT (10u) +#define INTC_ICDICPR16_TINT107_SHIFT (11u) +#define INTC_ICDICPR16_TINT108_SHIFT (12u) +#define INTC_ICDICPR16_TINT109_SHIFT (13u) +#define INTC_ICDICPR16_TINT110_SHIFT (14u) +#define INTC_ICDICPR16_TINT111_SHIFT (15u) +#define INTC_ICDICPR16_TINT112_SHIFT (16u) +#define INTC_ICDICPR16_TINT113_SHIFT (17u) +#define INTC_ICDICPR16_TINT114_SHIFT (18u) +#define INTC_ICDICPR16_TINT115_SHIFT (19u) +#define INTC_ICDICPR16_TINT116_SHIFT (20u) +#define INTC_ICDICPR16_TINT117_SHIFT (21u) +#define INTC_ICDICPR16_TINT118_SHIFT (22u) +#define INTC_ICDICPR16_TINT119_SHIFT (23u) +#define INTC_ICDICPR16_TINT120_SHIFT (24u) +#define INTC_ICDICPR16_TINT121_SHIFT (25u) +#define INTC_ICDICPR16_TINT122_SHIFT (26u) +#define INTC_ICDICPR16_TINT123_SHIFT (27u) +#define INTC_ICDICPR16_TINT124_SHIFT (28u) +#define INTC_ICDICPR16_TINT125_SHIFT (29u) +#define INTC_ICDICPR16_TINT126_SHIFT (30u) +#define INTC_ICDICPR16_TINT127_SHIFT (31u) + +#define INTC_ICDICPR17_TINT128_SHIFT (0u) +#define INTC_ICDICPR17_TINT129_SHIFT (1u) +#define INTC_ICDICPR17_TINT130_SHIFT (2u) +#define INTC_ICDICPR17_TINT131_SHIFT (3u) +#define INTC_ICDICPR17_TINT132_SHIFT (4u) +#define INTC_ICDICPR17_TINT133_SHIFT (5u) +#define INTC_ICDICPR17_TINT134_SHIFT (6u) +#define INTC_ICDICPR17_TINT135_SHIFT (7u) +#define INTC_ICDICPR17_TINT136_SHIFT (8u) +#define INTC_ICDICPR17_TINT137_SHIFT (9u) +#define INTC_ICDICPR17_TINT138_SHIFT (10u) +#define INTC_ICDICPR17_TINT139_SHIFT (11u) +#define INTC_ICDICPR17_TINT140_SHIFT (12u) +#define INTC_ICDICPR17_TINT141_SHIFT (13u) +#define INTC_ICDICPR17_TINT142_SHIFT (14u) +#define INTC_ICDICPR17_TINT143_SHIFT (15u) +#define INTC_ICDICPR17_TINT144_SHIFT (16u) +#define INTC_ICDICPR17_TINT145_SHIFT (17u) +#define INTC_ICDICPR17_TINT146_SHIFT (18u) +#define INTC_ICDICPR17_TINT147_SHIFT (19u) +#define INTC_ICDICPR17_TINT148_SHIFT (20u) +#define INTC_ICDICPR17_TINT149_SHIFT (21u) +#define INTC_ICDICPR17_TINT150_SHIFT (22u) +#define INTC_ICDICPR17_TINT151_SHIFT (23u) +#define INTC_ICDICPR17_TINT152_SHIFT (24u) +#define INTC_ICDICPR17_TINT153_SHIFT (25u) +#define INTC_ICDICPR17_TINT154_SHIFT (26u) +#define INTC_ICDICPR17_TINT155_SHIFT (27u) +#define INTC_ICDICPR17_TINT156_SHIFT (28u) +#define INTC_ICDICPR17_TINT157_SHIFT (29u) +#define INTC_ICDICPR17_TINT158_SHIFT (30u) +#define INTC_ICDICPR17_TINT159_SHIFT (31u) + +#define INTC_ICDICPR18_TINT160_SHIFT (0u) +#define INTC_ICDICPR18_TINT161_SHIFT (1u) +#define INTC_ICDICPR18_TINT162_SHIFT (2u) +#define INTC_ICDICPR18_TINT163_SHIFT (3u) +#define INTC_ICDICPR18_TINT164_SHIFT (4u) +#define INTC_ICDICPR18_TINT165_SHIFT (5u) +#define INTC_ICDICPR18_TINT166_SHIFT (6u) +#define INTC_ICDICPR18_TINT167_SHIFT (7u) +#define INTC_ICDICPR18_TINT168_SHIFT (8u) +#define INTC_ICDICPR18_TINT169_SHIFT (9u) +#define INTC_ICDICPR18_TINT170_SHIFT (10u) + +#define INTC_ICDABR0_SW0_SHIFT (0u) +#define INTC_ICDABR0_SW1_SHIFT (1u) +#define INTC_ICDABR0_SW2_SHIFT (2u) +#define INTC_ICDABR0_SW3_SHIFT (3u) +#define INTC_ICDABR0_SW4_SHIFT (4u) +#define INTC_ICDABR0_SW5_SHIFT (5u) +#define INTC_ICDABR0_SW6_SHIFT (6u) +#define INTC_ICDABR0_SW7_SHIFT (7u) +#define INTC_ICDABR0_SW8_SHIFT (8u) +#define INTC_ICDABR0_SW9_SHIFT (9u) +#define INTC_ICDABR0_SW10_SHIFT (10u) +#define INTC_ICDABR0_SW11_SHIFT (11u) +#define INTC_ICDABR0_SW12_SHIFT (12u) +#define INTC_ICDABR0_SW13_SHIFT (13u) +#define INTC_ICDABR0_SW14_SHIFT (14u) +#define INTC_ICDABR0_SW15_SHIFT (15u) +#define INTC_ICDABR0_PMUIRQ0_SHIFT (16u) +#define INTC_ICDABR0_COMMRX0_SHIFT (17u) +#define INTC_ICDABR0_COMMTX0_SHIFT (18u) +#define INTC_ICDABR0_CTIIRQ0_SHIFT (19u) + +#define INTC_ICDABR1_IRQ0_SHIFT (0u) +#define INTC_ICDABR1_IRQ1_SHIFT (1u) +#define INTC_ICDABR1_IRQ2_SHIFT (2u) +#define INTC_ICDABR1_IRQ3_SHIFT (3u) +#define INTC_ICDABR1_IRQ4_SHIFT (4u) +#define INTC_ICDABR1_IRQ5_SHIFT (5u) +#define INTC_ICDABR1_IRQ6_SHIFT (6u) +#define INTC_ICDABR1_IRQ7_SHIFT (7u) +#define INTC_ICDABR1_PL310ERR_SHIFT (8u) +#define INTC_ICDABR1_DMAINT0_SHIFT (9u) +#define INTC_ICDABR1_DMAINT1_SHIFT (10u) +#define INTC_ICDABR1_DMAINT2_SHIFT (11u) +#define INTC_ICDABR1_DMAINT3_SHIFT (12u) +#define INTC_ICDABR1_DMAINT4_SHIFT (13u) +#define INTC_ICDABR1_DMAINT5_SHIFT (14u) +#define INTC_ICDABR1_DMAINT6_SHIFT (15u) +#define INTC_ICDABR1_DMAINT7_SHIFT (16u) +#define INTC_ICDABR1_DMAINT8_SHIFT (17u) +#define INTC_ICDABR1_DMAINT9_SHIFT (18u) +#define INTC_ICDABR1_DMAINT10_SHIFT (19u) +#define INTC_ICDABR1_DMAINT11_SHIFT (20u) +#define INTC_ICDABR1_DMAINT12_SHIFT (21u) +#define INTC_ICDABR1_DMAINT13_SHIFT (22u) +#define INTC_ICDABR1_DMAINT14_SHIFT (23u) +#define INTC_ICDABR1_DMAINT15_SHIFT (24u) +#define INTC_ICDABR1_DMAERR_SHIFT (25u) + +#define INTC_ICDABR2_USBI0_SHIFT (9u) +#define INTC_ICDABR2_USBI1_SHIFT (10u) +#define INTC_ICDABR2_S0_VI_VSYNC0_SHIFT (11u) +#define INTC_ICDABR2_S0_LO_VSYNC0_SHIFT (12u) +#define INTC_ICDABR2_S0_VSYNCERR0_SHIFT (13u) +#define INTC_ICDABR2_GR3_VLINE0_SHIFT (14u) +#define INTC_ICDABR2_S0_VFIELD0_SHIFT (15u) +#define INTC_ICDABR2_IV1_VBUFERR0_SHIFT (16u) +#define INTC_ICDABR2_IV3_VBUFERR0_SHIFT (17u) +#define INTC_ICDABR2_IV5_VBUFERR0_SHIFT (18u) +#define INTC_ICDABR2_IV6_VBUFERR0_SHIFT (19u) +#define INTC_ICDABR2_S0_WLINE0_SHIFT (20u) +#define INTC_ICDABR2_S1_VI_VSYNC0_SHIFT (21u) +#define INTC_ICDABR2_S1_LO_VSYNC0_SHIFT (22u) +#define INTC_ICDABR2_S1_VSYNCERR0_SHIFT (23u) +#define INTC_ICDABR2_S1_VFIELD0_SHIFT (24u) +#define INTC_ICDABR2_IV2_VBUFERR0_SHIFT (25u) +#define INTC_ICDABR2_IV4_VBUFERR0_SHIFT (26u) +#define INTC_ICDABR2_S1_WLINE0_SHIFT (27u) +#define INTC_ICDABR2_OIR_VI_VSYNC0_SHIFT (28u) +#define INTC_ICDABR2_OIR_LO_VSYNC0_SHIFT (29u) +#define INTC_ICDABR2_OIR_VSYNCERR0_SHIFT (30u) +#define INTC_ICDABR2_OIR_VFIELD0_SHIFT (31u) + +#define INTC_ICDABR3_IV7_VBUFERR0_SHIFT (0u) +#define INTC_ICDABR3_IV8_VBUFERR0_SHIFT (1u) +#define INTC_ICDABR3_S0_VI_VSYNC1_SHIFT (3u) +#define INTC_ICDABR3_S0_LO_VSYNC1_SHIFT (4u) +#define INTC_ICDABR3_S0_VSYNCERR1_SHIFT (5u) +#define INTC_ICDABR3_GR3_VLINE1_SHIFT (6u) +#define INTC_ICDABR3_S0_VFIELD1_SHIFT (7u) +#define INTC_ICDABR3_IV1_VBUFERR1_SHIFT (8u) +#define INTC_ICDABR3_IV3_VBUFERR1_SHIFT (9u) +#define INTC_ICDABR3_IV5_VBUFERR1_SHIFT (10u) +#define INTC_ICDABR3_IV6_VBUFERR1_SHIFT (11u) +#define INTC_ICDABR3_S0_WLINE1_SHIFT (12u) +#define INTC_ICDABR3_S1_VI_VSYNC1_SHIFT (13u) +#define INTC_ICDABR3_S1_LO_VSYNC1_SHIFT (14u) +#define INTC_ICDABR3_S1_VSYNCERR1_SHIFT (15u) +#define INTC_ICDABR3_S1_VFIELD1_SHIFT (16u) +#define INTC_ICDABR3_IV2_VBUFERR1_SHIFT (17u) +#define INTC_ICDABR3_IV4_VBUFERR1_SHIFT (18u) +#define INTC_ICDABR3_S1_WLINE1_SHIFT (19u) +#define INTC_ICDABR3_OIR_VI_VSYNC1_SHIFT (20u) +#define INTC_ICDABR3_OIR_LO_VSYNC1_SHIFT (21u) +#define INTC_ICDABR3_OIR_VLINE1_SHIFT (22u) +#define INTC_ICDABR3_OIR_VFIELD1_SHIFT (23u) +#define INTC_ICDABR3_IV7_VBUFERR1_SHIFT (24u) +#define INTC_ICDABR3_IV8_VBUFERR1_SHIFT (25u) +#define INTC_ICDABR3_IMRDI_SHIFT (27u) +#define INTC_ICDABR3_IMR2I0_SHIFT (28u) +#define INTC_ICDABR3_IMR2I1_SHIFT (29u) +#define INTC_ICDABR3_JEDI_SHIFT (30u) +#define INTC_ICDABR3_JDTI_SHIFT (31u) + +#define INTC_ICDABR4_CMP0_SHIFT (0u) +#define INTC_ICDABR4_CMP1_SHIFT (1u) +#define INTC_ICDABR4_INT0_SHIFT (2u) +#define INTC_ICDABR4_INT1_SHIFT (3u) +#define INTC_ICDABR4_INT2_SHIFT (4u) +#define INTC_ICDABR4_INT3_SHIFT (5u) +#define INTC_ICDABR4_OSTM0TINT_SHIFT (6u) +#define INTC_ICDABR4_OSTM1TINT_SHIFT (7u) +#define INTC_ICDABR4_CMI_SHIFT (8u) +#define INTC_ICDABR4_WTOUT_SHIFT (9u) +#define INTC_ICDABR4_ITI_SHIFT (10u) +#define INTC_ICDABR4_TGI0A_SHIFT (11u) +#define INTC_ICDABR4_TGI0B_SHIFT (12u) +#define INTC_ICDABR4_TGI0C_SHIFT (13u) +#define INTC_ICDABR4_TGI0D_SHIFT (14u) +#define INTC_ICDABR4_TGI0V_SHIFT (15u) +#define INTC_ICDABR4_TGI0E_SHIFT (16u) +#define INTC_ICDABR4_TGI0F_SHIFT (17u) +#define INTC_ICDABR4_TGI1A_SHIFT (18u) +#define INTC_ICDABR4_TGI1B_SHIFT (19u) +#define INTC_ICDABR4_TGI1V_SHIFT (20u) +#define INTC_ICDABR4_TGI1U_SHIFT (21u) +#define INTC_ICDABR4_TGI2A_SHIFT (22u) +#define INTC_ICDABR4_TGI2B_SHIFT (23u) +#define INTC_ICDABR4_TGI2V_SHIFT (24u) +#define INTC_ICDABR4_TGI2U_SHIFT (25u) +#define INTC_ICDABR4_TGI3A_SHIFT (26u) +#define INTC_ICDABR4_TGI3B_SHIFT (27u) +#define INTC_ICDABR4_TGI3C_SHIFT (28u) +#define INTC_ICDABR4_TGI3D_SHIFT (29u) +#define INTC_ICDABR4_TGI3V_SHIFT (30u) +#define INTC_ICDABR4_TGI4A_SHIFT (31u) + +#define INTC_ICDABR5_TGI4B_SHIFT (0u) +#define INTC_ICDABR5_TGI4C_SHIFT (1u) +#define INTC_ICDABR5_TGI4D_SHIFT (2u) +#define INTC_ICDABR5_TGI4V_SHIFT (3u) +#define INTC_ICDABR5_CMI1_SHIFT (4u) +#define INTC_ICDABR5_CMI2_SHIFT (5u) +#define INTC_ICDABR5_SGDEI0_SHIFT (6u) +#define INTC_ICDABR5_SGDEI1_SHIFT (7u) +#define INTC_ICDABR5_SGDEI2_SHIFT (8u) +#define INTC_ICDABR5_SGDEI3_SHIFT (9u) +#define INTC_ICDABR5_ADI_SHIFT (10u) +#define INTC_ICDABR5_LMTI_SHIFT (11u) +#define INTC_ICDABR5_SSII0_SHIFT (12u) +#define INTC_ICDABR5_SSIRXI0_SHIFT (13u) +#define INTC_ICDABR5_SSITXI0_SHIFT (14u) +#define INTC_ICDABR5_SSII1_SHIFT (15u) +#define INTC_ICDABR5_SSIRXI1_SHIFT (16u) +#define INTC_ICDABR5_SSITXI1_SHIFT (17u) +#define INTC_ICDABR5_SSII2_SHIFT (18u) +#define INTC_ICDABR5_SSIRTI2_SHIFT (19u) +#define INTC_ICDABR5_SSII3_SHIFT (20u) +#define INTC_ICDABR5_SSIRXI3_SHIFT (21u) +#define INTC_ICDABR5_SSITXI3_SHIFT (22u) +#define INTC_ICDABR5_SSII4_SHIFT (23u) +#define INTC_ICDABR5_SSIRTI4_SHIFT (24u) +#define INTC_ICDABR5_SSII5_SHIFT (25u) +#define INTC_ICDABR5_SSIRXI5_SHIFT (26u) +#define INTC_ICDABR5_SSITXI5_SHIFT (27u) +#define INTC_ICDABR5_SPDIFI_SHIFT (28u) +#define INTC_ICDABR5_INTIICTEI0_SHIFT (29u) +#define INTC_ICDABR5_INTIICRI0_SHIFT (30u) +#define INTC_ICDABR5_INTIICTI0_SHIFT (31u) + +#define INTC_ICDABR6_INTIICSPI0_SHIFT (0u) +#define INTC_ICDABR6_INTIICSTI0_SHIFT (1u) +#define INTC_ICDABR6_INTIICNAKI0_SHIFT (2u) +#define INTC_ICDABR6_INTIICALI0_SHIFT (3u) +#define INTC_ICDABR6_INTIICTMOI0_SHIFT (4u) +#define INTC_ICDABR6_INTIICTEI1_SHIFT (5u) +#define INTC_ICDABR6_INTIICRI1_SHIFT (6u) +#define INTC_ICDABR6_INTIICTI1_SHIFT (7u) +#define INTC_ICDABR6_INTIICSPI1_SHIFT (8u) +#define INTC_ICDABR6_INTIICSTI1_SHIFT (9u) +#define INTC_ICDABR6_INTIICNAKI1_SHIFT (10u) +#define INTC_ICDABR6_INTIICALI1_SHIFT (11u) +#define INTC_ICDABR6_INTIICTMOI1_SHIFT (12u) +#define INTC_ICDABR6_INTIICTEI2_SHIFT (13u) +#define INTC_ICDABR6_INTIICRI2_SHIFT (14u) +#define INTC_ICDABR6_INTIICTI2_SHIFT (15u) +#define INTC_ICDABR6_INTIICSPI2_SHIFT (16u) +#define INTC_ICDABR6_INTIICSTI2_SHIFT (17u) +#define INTC_ICDABR6_INTIICNAKI2_SHIFT (18u) +#define INTC_ICDABR6_INTIICALI2_SHIFT (19u) +#define INTC_ICDABR6_INTIICTMOI2_SHIFT (20u) +#define INTC_ICDABR6_INTIICTEI3_SHIFT (21u) +#define INTC_ICDABR6_INTIICRI3_SHIFT (22u) +#define INTC_ICDABR6_INTIICTI3_SHIFT (23u) +#define INTC_ICDABR6_INTIICSPI3_SHIFT (24u) +#define INTC_ICDABR6_INTIICSTI3_SHIFT (25u) +#define INTC_ICDABR6_INTIICNAKI3_SHIFT (26u) +#define INTC_ICDABR6_INTIICALI3_SHIFT (27u) +#define INTC_ICDABR6_INTIICTMOI3_SHIFT (28u) +#define INTC_ICDABR6_BRI0_SHIFT (29u) +#define INTC_ICDABR6_ERI0_SHIFT (30u) +#define INTC_ICDABR6_RXI0_SHIFT (31u) + +#define INTC_ICDABR7_TXI0_SHIFT (0u) +#define INTC_ICDABR7_BRI1_SHIFT (1u) +#define INTC_ICDABR7_ERI1_SHIFT (2u) +#define INTC_ICDABR7_RXI1_SHIFT (3u) +#define INTC_ICDABR7_TXI1_SHIFT (4u) +#define INTC_ICDABR7_BRI2_SHIFT (5u) +#define INTC_ICDABR7_ERI2_SHIFT (6u) +#define INTC_ICDABR7_RXI2_SHIFT (7u) +#define INTC_ICDABR7_TXI2_SHIFT (8u) +#define INTC_ICDABR7_BRI3_SHIFT (9u) +#define INTC_ICDABR7_ERI3_SHIFT (10u) +#define INTC_ICDABR7_RXI3_SHIFT (11u) +#define INTC_ICDABR7_TXI3_SHIFT (12u) +#define INTC_ICDABR7_BRI4_SHIFT (13u) +#define INTC_ICDABR7_ERI4_SHIFT (14u) +#define INTC_ICDABR7_RXI4_SHIFT (15u) +#define INTC_ICDABR7_TXI4_SHIFT (16u) +#define INTC_ICDABR7_BRI5_SHIFT (17u) +#define INTC_ICDABR7_ERI5_SHIFT (18u) +#define INTC_ICDABR7_RXI5_SHIFT (19u) +#define INTC_ICDABR7_TXI5_SHIFT (20u) +#define INTC_ICDABR7_BRI6_SHIFT (21u) +#define INTC_ICDABR7_ERI6_SHIFT (22u) +#define INTC_ICDABR7_RXI6_SHIFT (23u) +#define INTC_ICDABR7_TXI6_SHIFT (24u) +#define INTC_ICDABR7_BRI7_SHIFT (25u) +#define INTC_ICDABR7_ERI7_SHIFT (26u) +#define INTC_ICDABR7_RXI7_SHIFT (27u) +#define INTC_ICDABR7_TXI7_SHIFT (28u) +#define INTC_ICDABR7_INTRCANGERR_SHIFT (29u) +#define INTC_ICDABR7_INTRCANGRECC_SHIFT (30u) +#define INTC_ICDABR7_INTRCAN0REC_SHIFT (31u) + +#define INTC_ICDABR8_INTRCAN0ERR_SHIFT (0u) +#define INTC_ICDABR8_INTRCAN0TRX_SHIFT (1u) +#define INTC_ICDABR8_INTRCAN1REC_SHIFT (2u) +#define INTC_ICDABR8_INTRCAN1ERR_SHIFT (3u) +#define INTC_ICDABR8_INTRCAN1TRX_SHIFT (4u) +#define INTC_ICDABR8_INTRCAN2REC_SHIFT (5u) +#define INTC_ICDABR8_INTRCAN2ERR_SHIFT (6u) +#define INTC_ICDABR8_INTRCAN2TRX_SHIFT (7u) +#define INTC_ICDABR8_INTRCAN3REC_SHIFT (8u) +#define INTC_ICDABR8_INTRCAN3ERR_SHIFT (9u) +#define INTC_ICDABR8_INTRCAN3TRX_SHIFT (10u) +#define INTC_ICDABR8_INTRCAN4REC_SHIFT (11u) +#define INTC_ICDABR8_INTRCAN4ERR_SHIFT (12u) +#define INTC_ICDABR8_INTRCAN4TRX_SHIFT (13u) +#define INTC_ICDABR8_SPEI0_SHIFT (14u) +#define INTC_ICDABR8_SPRI0_SHIFT (15u) +#define INTC_ICDABR8_SPTI0_SHIFT (16u) +#define INTC_ICDABR8_SPEI1_SHIFT (17u) +#define INTC_ICDABR8_SPRI1_SHIFT (18u) +#define INTC_ICDABR8_SPTI1_SHIFT (19u) +#define INTC_ICDABR8_SPEI2_SHIFT (20u) +#define INTC_ICDABR8_SPRI2_SHIFT (21u) +#define INTC_ICDABR8_SPTI2_SHIFT (22u) +#define INTC_ICDABR8_SPEI3_SHIFT (23u) +#define INTC_ICDABR8_SPRI3_SHIFT (24u) +#define INTC_ICDABR8_SPTI3_SHIFT (25u) +#define INTC_ICDABR8_SPEI4_SHIFT (26u) +#define INTC_ICDABR8_SPRI4_SHIFT (27u) +#define INTC_ICDABR8_SPTI4_SHIFT (28u) +#define INTC_ICDABR8_IEBBTD_SHIFT (29u) +#define INTC_ICDABR8_IEBBTERR_SHIFT (30u) +#define INTC_ICDABR8_IEBBTSTA_SHIFT (31u) + +#define INTC_ICDABR9_IEBBTV_SHIFT (0u) +#define INTC_ICDABR9_ISY_SHIFT (1u) +#define INTC_ICDABR9_IERR_SHIFT (2u) +#define INTC_ICDABR9_ITARG_SHIFT (3u) +#define INTC_ICDABR9_ISEC_SHIFT (4u) +#define INTC_ICDABR9_IBUF_SHIFT (5u) +#define INTC_ICDABR9_IREADY_SHIFT (6u) +#define INTC_ICDABR9_FLSTE_SHIFT (7u) +#define INTC_ICDABR9_FLTENDI_SHIFT (8u) +#define INTC_ICDABR9_FLTREQ0I_SHIFT (9u) +#define INTC_ICDABR9_FLTREQ1I_SHIFT (10u) +#define INTC_ICDABR9_MMC0_SHIFT (11u) +#define INTC_ICDABR9_MMC1_SHIFT (12u) +#define INTC_ICDABR9_MMC2_SHIFT (13u) +#define INTC_ICDABR9_SDHI0_3_SHIFT (14u) +#define INTC_ICDABR9_SDHI0_0_SHIFT (15u) +#define INTC_ICDABR9_SDHI0_1_SHIFT (16u) +#define INTC_ICDABR9_SDHI1_3_SHIFT (17u) +#define INTC_ICDABR9_SDHI1_0_SHIFT (18u) +#define INTC_ICDABR9_SDHI1_1_SHIFT (19u) +#define INTC_ICDABR9_ARM_SHIFT (20u) +#define INTC_ICDABR9_PRD_SHIFT (21u) +#define INTC_ICDABR9_CUP_SHIFT (22u) +#define INTC_ICDABR9_SCUAI0_SHIFT (23u) +#define INTC_ICDABR9_SCUAI1_SHIFT (24u) +#define INTC_ICDABR9_SCUFDI0_SHIFT (25u) +#define INTC_ICDABR9_SCUFDI1_SHIFT (26u) +#define INTC_ICDABR9_SCUFDI2_SHIFT (27u) +#define INTC_ICDABR9_SCUFDI3_SHIFT (28u) +#define INTC_ICDABR9_SCUFUI0_SHIFT (29u) +#define INTC_ICDABR9_SCUFUI1_SHIFT (30u) +#define INTC_ICDABR9_SCUFUI2_SHIFT (31u) + +#define INTC_ICDABR10_SCUFUI3_SHIFT (0u) +#define INTC_ICDABR10_SCUDVI0_SHIFT (1u) +#define INTC_ICDABR10_SCUDVI1_SHIFT (2u) +#define INTC_ICDABR10_SCUDVI2_SHIFT (3u) +#define INTC_ICDABR10_SCUDVI3_SHIFT (4u) +#define INTC_ICDABR10_MLB_CINT_SHIFT (5u) +#define INTC_ICDABR10_MLB_SINT_SHIFT (6u) +#define INTC_ICDABR10_DRC0_SHIFT (7u) +#define INTC_ICDABR10_DRC1_SHIFT (8u) +#define INTC_ICDABR10_LINI0_INT_T_SHIFT (11u) +#define INTC_ICDABR10_LINI0_INT_R_SHIFT (12u) +#define INTC_ICDABR10_LINI0_INT_S_SHIFT (13u) +#define INTC_ICDABR10_LINI0_INT_M_SHIFT (14u) +#define INTC_ICDABR10_LINI1_INT_T_SHIFT (15u) +#define INTC_ICDABR10_LINI1_INT_R_SHIFT (16u) +#define INTC_ICDABR10_LINI1_INT_S_SHIFT (17u) +#define INTC_ICDABR10_LINI1_INT_M_SHIFT (18u) +#define INTC_ICDABR10_ERI0_SHIFT (27u) +#define INTC_ICDABR10_RXI0_SHIFT (28u) +#define INTC_ICDABR10_TXI0_SHIFT (29u) +#define INTC_ICDABR10_TEI0_SHIFT (30u) +#define INTC_ICDABR10_ERI1_SHIFT (31u) + +#define INTC_ICDABR11_RXI1_SHIFT (0u) +#define INTC_ICDABR11_TXI1_SHIFT (1u) +#define INTC_ICDABR11_TEI1_SHIFT (2u) +#define INTC_ICDABR11_AVBI_DATA_SHIFT (3u) +#define INTC_ICDABR11_AVBI_ERROR_SHIFT (4u) +#define INTC_ICDABR11_AVBI_MANAGE_SHIFT (5u) +#define INTC_ICDABR11_AVBI_MAC_SHIFT (6u) +#define INTC_ICDABR11_ETHERI_SHIFT (7u) +#define INTC_ICDABR11_CEUI_SHIFT (12u) +#define INTC_ICDABR11_H2XMLB_ERRINT_SHIFT (29u) +#define INTC_ICDABR11_H2XIC1_ERRINT_SHIFT (30u) +#define INTC_ICDABR11_X2HPERI1_ERRINT_SHIFT (31u) + +#define INTC_ICDABR12_X2HPERI2_ERRINT_SHIFT (0u) +#define INTC_ICDABR12_X2HPERI34_ERRINT_SHIFT (1u) +#define INTC_ICDABR12_X2HPERI5_ERRINT_SHIFT (2u) +#define INTC_ICDABR12_X2HPERI67_ERRINT_SHIFT (3u) +#define INTC_ICDABR12_X2HDBGR_ERRINT_SHIFT (4u) +#define INTC_ICDABR12_X2HBSC_ERRINT_SHIFT (5u) +#define INTC_ICDABR12_X2HSPI1_ERRINT_SHIFT (6u) +#define INTC_ICDABR12_X2HSPI2_ERRINT_SHIFT (7u) +#define INTC_ICDABR12_PRRI_SHIFT (8u) +#define INTC_ICDABR12_IFEI0_SHIFT (9u) +#define INTC_ICDABR12_OFFI0_SHIFT (10u) +#define INTC_ICDABR12_PFVEI0_SHIFT (11u) +#define INTC_ICDABR12_IFEI1_SHIFT (12u) +#define INTC_ICDABR12_OFFI1_SHIFT (13u) +#define INTC_ICDABR12_PFVEI1_SHIFT (14u) + +#define INTC_ICDABR13_TINT0_SHIFT (0u) +#define INTC_ICDABR13_TINT1_SHIFT (1u) +#define INTC_ICDABR13_TINT2_SHIFT (2u) +#define INTC_ICDABR13_TINT3_SHIFT (3u) +#define INTC_ICDABR13_TINT4_SHIFT (4u) +#define INTC_ICDABR13_TINT5_SHIFT (5u) +#define INTC_ICDABR13_TINT6_SHIFT (6u) +#define INTC_ICDABR13_TINT7_SHIFT (7u) +#define INTC_ICDABR13_TINT8_SHIFT (8u) +#define INTC_ICDABR13_TINT9_SHIFT (9u) +#define INTC_ICDABR13_TINT10_SHIFT (10u) +#define INTC_ICDABR13_TINT11_SHIFT (11u) +#define INTC_ICDABR13_TINT12_SHIFT (12u) +#define INTC_ICDABR13_TINT13_SHIFT (13u) +#define INTC_ICDABR13_TINT14_SHIFT (14u) +#define INTC_ICDABR13_TINT15_SHIFT (15u) +#define INTC_ICDABR13_TINT16_SHIFT (16u) +#define INTC_ICDABR13_TINT17_SHIFT (17u) +#define INTC_ICDABR13_TINT18_SHIFT (18u) +#define INTC_ICDABR13_TINT19_SHIFT (19u) +#define INTC_ICDABR13_TINT20_SHIFT (20u) +#define INTC_ICDABR13_TINT21_SHIFT (21u) +#define INTC_ICDABR13_TINT22_SHIFT (22u) +#define INTC_ICDABR13_TINT23_SHIFT (23u) +#define INTC_ICDABR13_TINT24_SHIFT (24u) +#define INTC_ICDABR13_TINT25_SHIFT (25u) +#define INTC_ICDABR13_TINT26_SHIFT (26u) +#define INTC_ICDABR13_TINT27_SHIFT (27u) +#define INTC_ICDABR13_TINT28_SHIFT (28u) +#define INTC_ICDABR13_TINT29_SHIFT (29u) +#define INTC_ICDABR13_TINT30_SHIFT (30u) +#define INTC_ICDABR13_TINT31_SHIFT (31u) + +#define INTC_ICDABR14_TINT32_SHIFT (0u) +#define INTC_ICDABR14_TINT33_SHIFT (1u) +#define INTC_ICDABR14_TINT34_SHIFT (2u) +#define INTC_ICDABR14_TINT35_SHIFT (3u) +#define INTC_ICDABR14_TINT36_SHIFT (4u) +#define INTC_ICDABR14_TINT37_SHIFT (5u) +#define INTC_ICDABR14_TINT38_SHIFT (6u) +#define INTC_ICDABR14_TINT39_SHIFT (7u) +#define INTC_ICDABR14_TINT40_SHIFT (8u) +#define INTC_ICDABR14_TINT41_SHIFT (9u) +#define INTC_ICDABR14_TINT42_SHIFT (10u) +#define INTC_ICDABR14_TINT43_SHIFT (11u) +#define INTC_ICDABR14_TINT44_SHIFT (12u) +#define INTC_ICDABR14_TINT45_SHIFT (13u) +#define INTC_ICDABR14_TINT46_SHIFT (14u) +#define INTC_ICDABR14_TINT47_SHIFT (15u) +#define INTC_ICDABR14_TINT48_SHIFT (16u) +#define INTC_ICDABR14_TINT49_SHIFT (17u) +#define INTC_ICDABR14_TINT50_SHIFT (18u) +#define INTC_ICDABR14_TINT51_SHIFT (19u) +#define INTC_ICDABR14_TINT52_SHIFT (20u) +#define INTC_ICDABR14_TINT53_SHIFT (21u) +#define INTC_ICDABR14_TINT54_SHIFT (22u) +#define INTC_ICDABR14_TINT55_SHIFT (23u) +#define INTC_ICDABR14_TINT56_SHIFT (24u) +#define INTC_ICDABR14_TINT57_SHIFT (25u) +#define INTC_ICDABR14_TINT58_SHIFT (26u) +#define INTC_ICDABR14_TINT59_SHIFT (27u) +#define INTC_ICDABR14_TINT60_SHIFT (28u) +#define INTC_ICDABR14_TINT61_SHIFT (29u) +#define INTC_ICDABR14_TINT62_SHIFT (30u) +#define INTC_ICDABR14_TINT63_SHIFT (31u) + +#define INTC_ICDABR15_TINT64_SHIFT (0u) +#define INTC_ICDABR15_TINT65_SHIFT (1u) +#define INTC_ICDABR15_TINT66_SHIFT (2u) +#define INTC_ICDABR15_TINT67_SHIFT (3u) +#define INTC_ICDABR15_TINT68_SHIFT (4u) +#define INTC_ICDABR15_TINT69_SHIFT (5u) +#define INTC_ICDABR15_TINT70_SHIFT (6u) +#define INTC_ICDABR15_TINT71_SHIFT (7u) +#define INTC_ICDABR15_TINT72_SHIFT (8u) +#define INTC_ICDABR15_TINT73_SHIFT (9u) +#define INTC_ICDABR15_TINT74_SHIFT (10u) +#define INTC_ICDABR15_TINT75_SHIFT (11u) +#define INTC_ICDABR15_TINT76_SHIFT (12u) +#define INTC_ICDABR15_TINT77_SHIFT (13u) +#define INTC_ICDABR15_TINT78_SHIFT (14u) +#define INTC_ICDABR15_TINT79_SHIFT (15u) +#define INTC_ICDABR15_TINT80_SHIFT (16u) +#define INTC_ICDABR15_TINT81_SHIFT (17u) +#define INTC_ICDABR15_TINT82_SHIFT (18u) +#define INTC_ICDABR15_TINT83_SHIFT (19u) +#define INTC_ICDABR15_TINT84_SHIFT (20u) +#define INTC_ICDABR15_TINT85_SHIFT (21u) +#define INTC_ICDABR15_TINT86_SHIFT (22u) +#define INTC_ICDABR15_TINT87_SHIFT (23u) +#define INTC_ICDABR15_TINT88_SHIFT (24u) +#define INTC_ICDABR15_TINT89_SHIFT (25u) +#define INTC_ICDABR15_TINT90_SHIFT (26u) +#define INTC_ICDABR15_TINT91_SHIFT (27u) +#define INTC_ICDABR15_TINT92_SHIFT (28u) +#define INTC_ICDABR15_TINT93_SHIFT (29u) +#define INTC_ICDABR15_TINT94_SHIFT (30u) +#define INTC_ICDABR15_TINT95_SHIFT (31u) + +#define INTC_ICDABR16_TINT96_SHIFT (0u) +#define INTC_ICDABR16_TINT97_SHIFT (1u) +#define INTC_ICDABR16_TINT98_SHIFT (2u) +#define INTC_ICDABR16_TINT99_SHIFT (3u) +#define INTC_ICDABR16_TINT100_SHIFT (4u) +#define INTC_ICDABR16_TINT101_SHIFT (5u) +#define INTC_ICDABR16_TINT102_SHIFT (6u) +#define INTC_ICDABR16_TINT103_SHIFT (7u) +#define INTC_ICDABR16_TINT104_SHIFT (8u) +#define INTC_ICDABR16_TINT105_SHIFT (9u) +#define INTC_ICDABR16_TINT106_SHIFT (10u) +#define INTC_ICDABR16_TINT107_SHIFT (11u) +#define INTC_ICDABR16_TINT108_SHIFT (12u) +#define INTC_ICDABR16_TINT109_SHIFT (13u) +#define INTC_ICDABR16_TINT110_SHIFT (14u) +#define INTC_ICDABR16_TINT111_SHIFT (15u) +#define INTC_ICDABR16_TINT112_SHIFT (16u) +#define INTC_ICDABR16_TINT113_SHIFT (17u) +#define INTC_ICDABR16_TINT114_SHIFT (18u) +#define INTC_ICDABR16_TINT115_SHIFT (19u) +#define INTC_ICDABR16_TINT116_SHIFT (20u) +#define INTC_ICDABR16_TINT117_SHIFT (21u) +#define INTC_ICDABR16_TINT118_SHIFT (22u) +#define INTC_ICDABR16_TINT119_SHIFT (23u) +#define INTC_ICDABR16_TINT120_SHIFT (24u) +#define INTC_ICDABR16_TINT121_SHIFT (25u) +#define INTC_ICDABR16_TINT122_SHIFT (26u) +#define INTC_ICDABR16_TINT123_SHIFT (27u) +#define INTC_ICDABR16_TINT124_SHIFT (28u) +#define INTC_ICDABR16_TINT125_SHIFT (29u) +#define INTC_ICDABR16_TINT126_SHIFT (30u) +#define INTC_ICDABR16_TINT127_SHIFT (31u) + +#define INTC_ICDABR17_TINT128_SHIFT (0u) +#define INTC_ICDABR17_TINT129_SHIFT (1u) +#define INTC_ICDABR17_TINT130_SHIFT (2u) +#define INTC_ICDABR17_TINT131_SHIFT (3u) +#define INTC_ICDABR17_TINT132_SHIFT (4u) +#define INTC_ICDABR17_TINT133_SHIFT (5u) +#define INTC_ICDABR17_TINT134_SHIFT (6u) +#define INTC_ICDABR17_TINT135_SHIFT (7u) +#define INTC_ICDABR17_TINT136_SHIFT (8u) +#define INTC_ICDABR17_TINT137_SHIFT (9u) +#define INTC_ICDABR17_TINT138_SHIFT (10u) +#define INTC_ICDABR17_TINT139_SHIFT (11u) +#define INTC_ICDABR17_TINT140_SHIFT (12u) +#define INTC_ICDABR17_TINT141_SHIFT (13u) +#define INTC_ICDABR17_TINT142_SHIFT (14u) +#define INTC_ICDABR17_TINT143_SHIFT (15u) +#define INTC_ICDABR17_TINT144_SHIFT (16u) +#define INTC_ICDABR17_TINT145_SHIFT (17u) +#define INTC_ICDABR17_TINT146_SHIFT (18u) +#define INTC_ICDABR17_TINT147_SHIFT (19u) +#define INTC_ICDABR17_TINT148_SHIFT (20u) +#define INTC_ICDABR17_TINT149_SHIFT (21u) +#define INTC_ICDABR17_TINT150_SHIFT (22u) +#define INTC_ICDABR17_TINT151_SHIFT (23u) +#define INTC_ICDABR17_TINT152_SHIFT (24u) +#define INTC_ICDABR17_TINT153_SHIFT (25u) +#define INTC_ICDABR17_TINT154_SHIFT (26u) +#define INTC_ICDABR17_TINT155_SHIFT (27u) +#define INTC_ICDABR17_TINT156_SHIFT (28u) +#define INTC_ICDABR17_TINT157_SHIFT (29u) +#define INTC_ICDABR17_TINT158_SHIFT (30u) +#define INTC_ICDABR17_TINT159_SHIFT (31u) + +#define INTC_ICDABR18_TINT160_SHIFT (0u) +#define INTC_ICDABR18_TINT161_SHIFT (1u) +#define INTC_ICDABR18_TINT162_SHIFT (2u) +#define INTC_ICDABR18_TINT163_SHIFT (3u) +#define INTC_ICDABR18_TINT164_SHIFT (4u) +#define INTC_ICDABR18_TINT165_SHIFT (5u) +#define INTC_ICDABR18_TINT166_SHIFT (6u) +#define INTC_ICDABR18_TINT167_SHIFT (7u) +#define INTC_ICDABR18_TINT168_SHIFT (8u) +#define INTC_ICDABR18_TINT169_SHIFT (9u) +#define INTC_ICDABR18_TINT170_SHIFT (10u) + +#define INTC_ICDIPR0_SW0_SHIFT (0u) +#define INTC_ICDIPR0_SW1_SHIFT (8u) +#define INTC_ICDIPR0_SW2_SHIFT (16u) +#define INTC_ICDIPR0_SW3_SHIFT (24u) + +#define INTC_ICDIPR1_SW4_SHIFT (0u) +#define INTC_ICDIPR1_SW5_SHIFT (8u) +#define INTC_ICDIPR1_SW6_SHIFT (16u) +#define INTC_ICDIPR1_SW7_SHIFT (24u) + +#define INTC_ICDIPR2_SW8_SHIFT (0u) +#define INTC_ICDIPR2_SW9_SHIFT (8u) +#define INTC_ICDIPR2_SW10_SHIFT (16u) +#define INTC_ICDIPR2_SW11_SHIFT (24u) + +#define INTC_ICDIPR3_SW12_SHIFT (0u) +#define INTC_ICDIPR3_SW13_SHIFT (8u) +#define INTC_ICDIPR3_SW14_SHIFT (16u) +#define INTC_ICDIPR3_SW15_SHIFT (24u) + +#define INTC_ICDIPR4_PMUIRQ0_SHIFT (0u) +#define INTC_ICDIPR4_COMMRX0_SHIFT (8u) +#define INTC_ICDIPR4_COMMTX0_SHIFT (16u) +#define INTC_ICDIPR4_CTIIRQ0_SHIFT (24u) + +#define INTC_ICDIPR8_IRQ0_SHIFT (0u) +#define INTC_ICDIPR8_IRQ1_SHIFT (8u) +#define INTC_ICDIPR8_IRQ2_SHIFT (16u) +#define INTC_ICDIPR8_IRQ3_SHIFT (24u) + +#define INTC_ICDIPR9_IRQ4_SHIFT (0u) +#define INTC_ICDIPR9_IRQ5_SHIFT (8u) +#define INTC_ICDIPR9_IRQ6_SHIFT (16u) +#define INTC_ICDIPR9_IRQ7_SHIFT (24u) + +#define INTC_ICDIPR10_PL310ERR_SHIFT (0u) +#define INTC_ICDIPR10_DMAINT0_SHIFT (8u) +#define INTC_ICDIPR10_DMAINT1_SHIFT (16u) +#define INTC_ICDIPR10_DMAINT2_SHIFT (24u) + +#define INTC_ICDIPR11_DMAINT3_SHIFT (0u) +#define INTC_ICDIPR11_DMAINT4_SHIFT (8u) +#define INTC_ICDIPR11_DMAINT5_SHIFT (16u) +#define INTC_ICDIPR11_DMAINT6_SHIFT (24u) + +#define INTC_ICDIPR12_DMAINT7_SHIFT (0u) +#define INTC_ICDIPR12_DMAINT8_SHIFT (8u) +#define INTC_ICDIPR12_DMAINT9_SHIFT (16u) +#define INTC_ICDIPR12_DMAINT10_SHIFT (24u) + +#define INTC_ICDIPR13_DMAINT11_SHIFT (0u) +#define INTC_ICDIPR13_DMAINT12_SHIFT (8u) +#define INTC_ICDIPR13_DMAINT13_SHIFT (16u) +#define INTC_ICDIPR13_DMAINT14_SHIFT (24u) + +#define INTC_ICDIPR14_DMAINT15_SHIFT (0u) +#define INTC_ICDIPR14_DMAERR_SHIFT (8u) + +#define INTC_ICDIPR18_USBI0_SHIFT (8u) +#define INTC_ICDIPR18_USBI1_SHIFT (16u) +#define INTC_ICDIPR18_S0_VI_VSYNC0_SHIFT (24u) + +#define INTC_ICDIPR19_S0_LO_VSYNC0_SHIFT (0u) +#define INTC_ICDIPR19_S0_VSYNCERR0_SHIFT (8u) +#define INTC_ICDIPR19_GR3_VLINE0_SHIFT (16u) +#define INTC_ICDIPR19_S0_VFIELD0_SHIFT (24u) + +#define INTC_ICDIPR20_IV1_VBUFERR0_SHIFT (0u) +#define INTC_ICDIPR20_IV3_VBUFERR0_SHIFT (8u) +#define INTC_ICDIPR20_IV5_VBUFERR0_SHIFT (16u) +#define INTC_ICDIPR20_IV6_VBUFERR0_SHIFT (24u) + +#define INTC_ICDIPR21_S0_WLINE0_SHIFT (0u) +#define INTC_ICDIPR21_S1_VI_VSYNC0_SHIFT (8u) +#define INTC_ICDIPR21_S1_LO_VSYNC0_SHIFT (16u) +#define INTC_ICDIPR21_S1_VSYNCERR0_SHIFT (24u) + +#define INTC_ICDIPR22_S1_VFIELD0_SHIFT (0u) +#define INTC_ICDIPR22_IV2_VBUFERR0_SHIFT (8u) +#define INTC_ICDIPR22_IV4_VBUFERR0_SHIFT (16u) +#define INTC_ICDIPR22_S1_WLINE0_SHIFT (24u) + +#define INTC_ICDIPR23_OIR_VI_VSYNC0_SHIFT (0u) +#define INTC_ICDIPR23_OIR_LO_VSYNC0_SHIFT (8u) +#define INTC_ICDIPR23_OIR_VSYNCERR0_SHIFT (16u) +#define INTC_ICDIPR23_OIR_VFIELD0_SHIFT (24u) + +#define INTC_ICDIPR24_IV7_VBUFERR0_SHIFT (0u) +#define INTC_ICDIPR24_IV8_VBUFERR0_SHIFT (8u) +#define INTC_ICDIPR24_S0_VI_VSYNC1_SHIFT (24u) + +#define INTC_ICDIPR25_S0_LO_VSYNC1_SHIFT (0u) +#define INTC_ICDIPR25_S0_VSYNCERR1_SHIFT (8u) +#define INTC_ICDIPR25_GR3_VLINE1_SHIFT (16u) +#define INTC_ICDIPR25_S0_VFIELD1_SHIFT (24u) + +#define INTC_ICDIPR26_IV1_VBUFERR1_SHIFT (0u) +#define INTC_ICDIPR26_IV3_VBUFERR1_SHIFT (8u) +#define INTC_ICDIPR26_IV5_VBUFERR1_SHIFT (16u) +#define INTC_ICDIPR26_IV6_VBUFERR1_SHIFT (24u) + +#define INTC_ICDIPR27_S0_WLINE1_SHIFT (0u) +#define INTC_ICDIPR27_S1_VI_VSYNC1_SHIFT (8u) +#define INTC_ICDIPR27_S1_LO_VSYNC1_SHIFT (16u) +#define INTC_ICDIPR27_S1_VSYNCERR1_SHIFT (24u) + +#define INTC_ICDIPR28_S1_VFIELD1_SHIFT (0u) +#define INTC_ICDIPR28_IV2_VBUFERR1_SHIFT (8u) +#define INTC_ICDIPR28_IV4_VBUFERR1_SHIFT (16u) +#define INTC_ICDIPR28_S1_WLINE1_SHIFT (24u) + +#define INTC_ICDIPR29_OIR_VI_VSYNC1_SHIFT (0u) +#define INTC_ICDIPR29_OIR_LO_VSYNC1_SHIFT (8u) +#define INTC_ICDIPR29_OIR_VLINE1_SHIFT (16u) +#define INTC_ICDIPR29_OIR_VFIELD1_SHIFT (24u) + +#define INTC_ICDIPR30_IV7_VBUFERR1_SHIFT (0u) +#define INTC_ICDIPR30_IV8_VBUFERR1_SHIFT (8u) +#define INTC_ICDIPR30_IMRDI_SHIFT (24u) + +#define INTC_ICDIPR31_IMR2I0_SHIFT (0u) +#define INTC_ICDIPR31_IMR2I1_SHIFT (8u) +#define INTC_ICDIPR31_JEDI_SHIFT (16u) +#define INTC_ICDIPR31_JDTI_SHIFT (24u) + +#define INTC_ICDIPR32_CMP0_SHIFT (0u) +#define INTC_ICDIPR32_CMP1_SHIFT (8u) +#define INTC_ICDIPR32_INT0_SHIFT (16u) +#define INTC_ICDIPR32_INT1_SHIFT (24u) + +#define INTC_ICDIPR33_INT2_SHIFT (0u) +#define INTC_ICDIPR33_INT3_SHIFT (8u) +#define INTC_ICDIPR33_OSTM0TINT_SHIFT (16u) +#define INTC_ICDIPR33_OSTM1TINT_SHIFT (24u) + +#define INTC_ICDIPR34_CMI_SHIFT (0u) +#define INTC_ICDIPR34_WTOUT_SHIFT (8u) +#define INTC_ICDIPR34_ITI_SHIFT (16u) +#define INTC_ICDIPR34_TGI0A_SHIFT (24u) + +#define INTC_ICDIPR35_TGI0B_SHIFT (0u) +#define INTC_ICDIPR35_TGI0C_SHIFT (8u) +#define INTC_ICDIPR35_TGI0D_SHIFT (16u) +#define INTC_ICDIPR35_TGI0V_SHIFT (24u) + +#define INTC_ICDIPR36_TGI0E_SHIFT (0u) +#define INTC_ICDIPR36_TGI0F_SHIFT (8u) +#define INTC_ICDIPR36_TGI1A_SHIFT (16u) +#define INTC_ICDIPR36_TGI1B_SHIFT (24u) + +#define INTC_ICDIPR37_TGI1V_SHIFT (0u) +#define INTC_ICDIPR37_TGI1U_SHIFT (8u) +#define INTC_ICDIPR37_TGI2A_SHIFT (16u) +#define INTC_ICDIPR37_TGI2B_SHIFT (24u) + +#define INTC_ICDIPR38_TGI2V_SHIFT (0u) +#define INTC_ICDIPR38_TGI2U_SHIFT (8u) +#define INTC_ICDIPR38_TGI3A_SHIFT (16u) +#define INTC_ICDIPR38_TGI3B_SHIFT (24u) + +#define INTC_ICDIPR39_TGI3C_SHIFT (0u) +#define INTC_ICDIPR39_TGI3D_SHIFT (8u) +#define INTC_ICDIPR39_TGI3V_SHIFT (16u) +#define INTC_ICDIPR39_TGI4A_SHIFT (24u) + +#define INTC_ICDIPR40_TGI4B_SHIFT (0u) +#define INTC_ICDIPR40_TGI4C_SHIFT (8u) +#define INTC_ICDIPR40_TGI4D_SHIFT (16u) +#define INTC_ICDIPR40_TGI4V_SHIFT (24u) + +#define INTC_ICDIPR41_CMI1_SHIFT (0u) +#define INTC_ICDIPR41_CMI2_SHIFT (8u) +#define INTC_ICDIPR41_SGDEI0_SHIFT (16u) +#define INTC_ICDIPR41_SGDEI1_SHIFT (24u) + +#define INTC_ICDIPR42_SGDEI2_SHIFT (0u) +#define INTC_ICDIPR42_SGDEI3_SHIFT (8u) +#define INTC_ICDIPR42_ADI_SHIFT (16u) +#define INTC_ICDIPR42_LMTI_SHIFT (24u) + +#define INTC_ICDIPR43_SSII0_SHIFT (0u) +#define INTC_ICDIPR43_SSIRXI0_SHIFT (8u) +#define INTC_ICDIPR43_SSITXI0_SHIFT (16u) +#define INTC_ICDIPR43_SSII1_SHIFT (24u) + +#define INTC_ICDIPR44_SSIRXI1_SHIFT (0u) +#define INTC_ICDIPR44_SSITXI1_SHIFT (8u) +#define INTC_ICDIPR44_SSII2_SHIFT (16u) +#define INTC_ICDIPR44_SSIRTI2_SHIFT (24u) + +#define INTC_ICDIPR45_SSII3_SHIFT (0u) +#define INTC_ICDIPR45_SSIRXI3_SHIFT (8u) +#define INTC_ICDIPR45_SSITXI3_SHIFT (16u) +#define INTC_ICDIPR45_SSII4_SHIFT (24u) + +#define INTC_ICDIPR46_SSIRTI4_SHIFT (0u) +#define INTC_ICDIPR46_SSII5_SHIFT (8u) +#define INTC_ICDIPR46_SSIRXI5_SHIFT (16u) +#define INTC_ICDIPR46_SSITXI5_SHIFT (24u) + +#define INTC_ICDIPR47_SPDIFI_SHIFT (0u) +#define INTC_ICDIPR47_INTIICTEI0_SHIFT (8u) +#define INTC_ICDIPR47_INTIICRI0_SHIFT (16u) +#define INTC_ICDIPR47_INTIICTI0_SHIFT (24u) + +#define INTC_ICDIPR48_INTIICSPI0_SHIFT (0u) +#define INTC_ICDIPR48_INTIICSTI0_SHIFT (8u) +#define INTC_ICDIPR48_INTIICNAKI0_SHIFT (16u) +#define INTC_ICDIPR48_INTIICALI0_SHIFT (24u) + +#define INTC_ICDIPR49_INTIICTMOI0_SHIFT (0u) +#define INTC_ICDIPR49_INTIICTEI1_SHIFT (8u) +#define INTC_ICDIPR49_INTIICRI1_SHIFT (16u) +#define INTC_ICDIPR49_INTIICTI1_SHIFT (24u) + +#define INTC_ICDIPR50_INTIICSPI1_SHIFT (0u) +#define INTC_ICDIPR50_INTIICSTI1_SHIFT (8u) +#define INTC_ICDIPR50_INTIICNAKI1_SHIFT (16u) +#define INTC_ICDIPR50_INTIICALI1_SHIFT (24u) + +#define INTC_ICDIPR51_INTIICTMOI1_SHIFT (0u) +#define INTC_ICDIPR51_INTIICTEI2_SHIFT (8u) +#define INTC_ICDIPR51_INTIICRI2_SHIFT (16u) +#define INTC_ICDIPR51_INTIICTI2_SHIFT (24u) + +#define INTC_ICDIPR52_INTIICSPI2_SHIFT (0u) +#define INTC_ICDIPR52_INTIICSTI2_SHIFT (8u) +#define INTC_ICDIPR52_INTIICNAKI2_SHIFT (16u) +#define INTC_ICDIPR52_INTIICALI2_SHIFT (24u) + +#define INTC_ICDIPR53_INTIICTMOI2_SHIFT (0u) +#define INTC_ICDIPR53_INTIICTEI3_SHIFT (8u) +#define INTC_ICDIPR53_INTIICRI3_SHIFT (16u) +#define INTC_ICDIPR53_INTIICTI3_SHIFT (24u) + +#define INTC_ICDIPR54_INTIICSPI3_SHIFT (0u) +#define INTC_ICDIPR54_INTIICSTI3_SHIFT (8u) +#define INTC_ICDIPR54_INTIICNAKI3_SHIFT (16u) +#define INTC_ICDIPR54_INTIICALI3_SHIFT (24u) + +#define INTC_ICDIPR55_INTIICTMOI3_SHIFT (0u) +#define INTC_ICDIPR55_BRI0_SHIFT (8u) +#define INTC_ICDIPR55_ERI0_SHIFT (16u) +#define INTC_ICDIPR55_RXI0_SHIFT (24u) + +#define INTC_ICDIPR56_TXI0_SHIFT (0u) +#define INTC_ICDIPR56_BRI1_SHIFT (8u) +#define INTC_ICDIPR56_ERI1_SHIFT (16u) +#define INTC_ICDIPR56_RXI1_SHIFT (24u) + +#define INTC_ICDIPR57_TXI1_SHIFT (0u) +#define INTC_ICDIPR57_BRI2_SHIFT (8u) +#define INTC_ICDIPR57_ERI2_SHIFT (16u) +#define INTC_ICDIPR57_RXI2_SHIFT (24u) + +#define INTC_ICDIPR58_TXI2_SHIFT (0u) +#define INTC_ICDIPR58_BRI3_SHIFT (8u) +#define INTC_ICDIPR58_ERI3_SHIFT (16u) +#define INTC_ICDIPR58_RXI3_SHIFT (24u) + +#define INTC_ICDIPR59_TXI3_SHIFT (0u) +#define INTC_ICDIPR59_BRI4_SHIFT (8u) +#define INTC_ICDIPR59_ERI4_SHIFT (16u) +#define INTC_ICDIPR59_RXI4_SHIFT (24u) + +#define INTC_ICDIPR60_TXI4_SHIFT (0u) +#define INTC_ICDIPR60_BRI5_SHIFT (8u) +#define INTC_ICDIPR60_ERI5_SHIFT (16u) +#define INTC_ICDIPR60_RXI5_SHIFT (24u) + +#define INTC_ICDIPR61_TXI5_SHIFT (0u) +#define INTC_ICDIPR61_BRI6_SHIFT (8u) +#define INTC_ICDIPR61_ERI6_SHIFT (16u) +#define INTC_ICDIPR61_RXI6_SHIFT (24u) + +#define INTC_ICDIPR62_TXI6_SHIFT (0u) +#define INTC_ICDIPR62_BRI7_SHIFT (8u) +#define INTC_ICDIPR62_ERI7_SHIFT (16u) +#define INTC_ICDIPR62_RXI7_SHIFT (24u) + +#define INTC_ICDIPR63_TXI7_SHIFT (0u) +#define INTC_ICDIPR63_INTRCANGERR_SHIFT (8u) +#define INTC_ICDIPR63_INTRCANGRECC_SHIFT (16u) +#define INTC_ICDIPR63_INTRCAN0REC_SHIFT (24u) + +#define INTC_ICDIPR64_INTRCAN0ERR_SHIFT (0u) +#define INTC_ICDIPR64_INTRCAN0TRX_SHIFT (8u) +#define INTC_ICDIPR64_INTRCAN1REC_SHIFT (16u) +#define INTC_ICDIPR64_INTRCAN1ERR_SHIFT (24u) + +#define INTC_ICDIPR65_INTRCAN1TRX_SHIFT (0u) +#define INTC_ICDIPR65_INTRCAN2REC_SHIFT (8u) +#define INTC_ICDIPR65_INTRCAN2ERR_SHIFT (16u) +#define INTC_ICDIPR65_INTRCAN2TRX_SHIFT (24u) + +#define INTC_ICDIPR66_INTRCAN3REC_SHIFT (0u) +#define INTC_ICDIPR66_INTRCAN3ERR_SHIFT (8u) +#define INTC_ICDIPR66_INTRCAN3TRX_SHIFT (16u) +#define INTC_ICDIPR66_INTRCAN4REC_SHIFT (24u) + +#define INTC_ICDIPR67_INTRCAN4ERR_SHIFT (0u) +#define INTC_ICDIPR67_INTRCAN4TRX_SHIFT (8u) +#define INTC_ICDIPR67_SPEI0_SHIFT (16u) +#define INTC_ICDIPR67_SPRI0_SHIFT (24u) + +#define INTC_ICDIPR68_SPTI0_SHIFT (0u) +#define INTC_ICDIPR68_SPEI1_SHIFT (8u) +#define INTC_ICDIPR68_SPRI1_SHIFT (16u) +#define INTC_ICDIPR68_SPTI1_SHIFT (24u) + +#define INTC_ICDIPR69_SPEI2_SHIFT (0u) +#define INTC_ICDIPR69_SPRI2_SHIFT (8u) +#define INTC_ICDIPR69_SPTI2_SHIFT (16u) +#define INTC_ICDIPR69_SPEI3_SHIFT (24u) + +#define INTC_ICDIPR70_SPRI3_SHIFT (0u) +#define INTC_ICDIPR70_SPTI3_SHIFT (8u) +#define INTC_ICDIPR70_SPEI4_SHIFT (16u) +#define INTC_ICDIPR70_SPRI4_SHIFT (24u) + +#define INTC_ICDIPR71_SPTI4_SHIFT (0u) +#define INTC_ICDIPR71_IEBBTD_SHIFT (8u) +#define INTC_ICDIPR71_IEBBTERR_SHIFT (16u) +#define INTC_ICDIPR71_IEBBTSTA_SHIFT (24u) + +#define INTC_ICDIPR72_IEBBTV_SHIFT (0u) +#define INTC_ICDIPR72_ISY_SHIFT (8u) +#define INTC_ICDIPR72_IERR_SHIFT (16u) +#define INTC_ICDIPR72_ITARG_SHIFT (24u) + +#define INTC_ICDIPR73_ISEC_SHIFT (0u) +#define INTC_ICDIPR73_IBUF_SHIFT (8u) +#define INTC_ICDIPR73_IREADY_SHIFT (16u) +#define INTC_ICDIPR73_FLSTE_SHIFT (24u) + +#define INTC_ICDIPR74_FLTENDI_SHIFT (0u) +#define INTC_ICDIPR74_FLTREQ0I_SHIFT (8u) +#define INTC_ICDIPR74_FLTREQ1I_SHIFT (16u) +#define INTC_ICDIPR74_MMC0_SHIFT (24u) + +#define INTC_ICDIPR75_MMC1_SHIFT (0u) +#define INTC_ICDIPR75_MMC2_SHIFT (8u) +#define INTC_ICDIPR75_SDHI0_3_SHIFT (16u) +#define INTC_ICDIPR75_SDHI0_0_SHIFT (24u) + +#define INTC_ICDIPR76_SDHI0_1_SHIFT (0u) +#define INTC_ICDIPR76_SDHI1_3_SHIFT (8u) +#define INTC_ICDIPR76_SDHI1_0_SHIFT (16u) +#define INTC_ICDIPR76_SDHI1_1_SHIFT (24u) + +#define INTC_ICDIPR77_ARM_SHIFT (0u) +#define INTC_ICDIPR77_PRD_SHIFT (8u) +#define INTC_ICDIPR77_CUP_SHIFT (16u) +#define INTC_ICDIPR77_SCUAI0_SHIFT (24u) + +#define INTC_ICDIPR78_SCUAI1_SHIFT (0u) +#define INTC_ICDIPR78_SCUFDI0_SHIFT (8u) +#define INTC_ICDIPR78_SCUFDI1_SHIFT (16u) +#define INTC_ICDIPR78_SCUFDI2_SHIFT (24u) + +#define INTC_ICDIPR79_SCUFDI3_SHIFT (0u) +#define INTC_ICDIPR79_SCUFUI0_SHIFT (8u) +#define INTC_ICDIPR79_SCUFUI1_SHIFT (16u) +#define INTC_ICDIPR79_SCUFUI2_SHIFT (24u) + +#define INTC_ICDIPR80_SCUFUI3_SHIFT (0u) +#define INTC_ICDIPR80_SCUDVI0_SHIFT (8u) +#define INTC_ICDIPR80_SCUDVI1_SHIFT (16u) +#define INTC_ICDIPR80_SCUDVI2_SHIFT (24u) + +#define INTC_ICDIPR81_SCUDVI3_SHIFT (0u) +#define INTC_ICDIPR81_MLB_CINT_SHIFT (8u) +#define INTC_ICDIPR81_MLB_SINT_SHIFT (16u) +#define INTC_ICDIPR81_DRC0_SHIFT (24u) + +#define INTC_ICDIPR82_DRC1_SHIFT (0u) +#define INTC_ICDIPR82_LINI0_INT_T_SHIFT (24u) + +#define INTC_ICDIPR83_LINI0_INT_R_SHIFT (0u) +#define INTC_ICDIPR83_LINI0_INT_S_SHIFT (8u) +#define INTC_ICDIPR83_LINI0_INT_M_SHIFT (16u) +#define INTC_ICDIPR83_LINI1_INT_T_SHIFT (24u) + +#define INTC_ICDIPR84_LINI1_INT_R_SHIFT (0u) +#define INTC_ICDIPR84_LINI1_INT_S_SHIFT (8u) +#define INTC_ICDIPR84_LINI1_INT_M_SHIFT (16u) + +#define INTC_ICDIPR86_ERI0_SHIFT (24u) + +#define INTC_ICDIPR87_RXI0_SHIFT (0u) +#define INTC_ICDIPR87_TXI0_SHIFT (8u) +#define INTC_ICDIPR87_TEI0_SHIFT (16u) +#define INTC_ICDIPR87_ERI1_SHIFT (24u) + +#define INTC_ICDIPR88_RXI1_SHIFT (0u) +#define INTC_ICDIPR88_TXI1_SHIFT (8u) +#define INTC_ICDIPR88_TEI1_SHIFT (16u) +#define INTC_ICDIPR88_AVBI_DATA_SHIFT (24u) + +#define INTC_ICDIPR89_AVBI_ERROR_SHIFT (0u) +#define INTC_ICDIPR89_AVBI_MANAGE_SHIFT (8u) +#define INTC_ICDIPR89_AVBI_MAC_SHIFT (16u) +#define INTC_ICDIPR89_ETHERI_SHIFT (24u) + +#define INTC_ICDIPR91_CEUI_SHIFT (0u) + +#define INTC_ICDIPR95_H2XMLB_ERRINT_SHIFT (8u) +#define INTC_ICDIPR95_H2XIC1_ERRINT_SHIFT (16u) +#define INTC_ICDIPR95_X2HPERI1_ERRINT_SHIFT (24u) + +#define INTC_ICDIPR96_X2HPERI2_ERRINT_SHIFT (0u) +#define INTC_ICDIPR96_X2HPERI34_ERRINT_SHIFT (8u) +#define INTC_ICDIPR96_X2HPERI5_ERRINT_SHIFT (16u) +#define INTC_ICDIPR96_X2HPERI67_ERRINT_SHIFT (24u) + +#define INTC_ICDIPR97_X2HDBGR_ERRINT_SHIFT (0u) +#define INTC_ICDIPR97_X2HBSC_ERRINT_SHIFT (8u) +#define INTC_ICDIPR97_X2HSPI1_ERRINT_SHIFT (16u) +#define INTC_ICDIPR97_X2HSPI2_ERRINT_SHIFT (24u) + +#define INTC_ICDIPR98_PRRI_SHIFT (0u) +#define INTC_ICDIPR98_IFEI0_SHIFT (8u) +#define INTC_ICDIPR98_OFFI0_SHIFT (16u) +#define INTC_ICDIPR98_PFVEI0_SHIFT (24u) + +#define INTC_ICDIPR99_IFEI1_SHIFT (0u) +#define INTC_ICDIPR99_OFFI1_SHIFT (8u) +#define INTC_ICDIPR99_PFVEI1_SHIFT (16u) + +#define INTC_ICDIPR104_TINT0_SHIFT (0u) +#define INTC_ICDIPR104_TINT1_SHIFT (8u) +#define INTC_ICDIPR104_TINT2_SHIFT (16u) +#define INTC_ICDIPR104_TINT3_SHIFT (24u) + +#define INTC_ICDIPR105_TINT4_SHIFT (0u) +#define INTC_ICDIPR105_TINT5_SHIFT (8u) +#define INTC_ICDIPR105_TINT6_SHIFT (16u) +#define INTC_ICDIPR105_TINT7_SHIFT (24u) + +#define INTC_ICDIPR106_TINT8_SHIFT (0u) +#define INTC_ICDIPR106_TINT9_SHIFT (8u) +#define INTC_ICDIPR106_TINT10_SHIFT (16u) +#define INTC_ICDIPR106_TINT11_SHIFT (24u) + +#define INTC_ICDIPR107_TINT12_SHIFT (0u) +#define INTC_ICDIPR107_TINT13_SHIFT (8u) +#define INTC_ICDIPR107_TINT14_SHIFT (16u) +#define INTC_ICDIPR107_TINT15_SHIFT (24u) + +#define INTC_ICDIPR108_TINT16_SHIFT (0u) +#define INTC_ICDIPR108_TINT17_SHIFT (8u) +#define INTC_ICDIPR108_TINT18_SHIFT (16u) +#define INTC_ICDIPR108_TINT19_SHIFT (24u) + +#define INTC_ICDIPR109_TINT20_SHIFT (0u) +#define INTC_ICDIPR109_TINT21_SHIFT (8u) +#define INTC_ICDIPR109_TINT22_SHIFT (16u) +#define INTC_ICDIPR109_TINT23_SHIFT (24u) + +#define INTC_ICDIPR110_TINT24_SHIFT (0u) +#define INTC_ICDIPR110_TINT25_SHIFT (8u) +#define INTC_ICDIPR110_TINT26_SHIFT (16u) +#define INTC_ICDIPR110_TINT27_SHIFT (24u) + +#define INTC_ICDIPR111_TINT28_SHIFT (0u) +#define INTC_ICDIPR111_TINT29_SHIFT (8u) +#define INTC_ICDIPR111_TINT30_SHIFT (16u) +#define INTC_ICDIPR111_TINT31_SHIFT (24u) + +#define INTC_ICDIPR112_TINT32_SHIFT (0u) +#define INTC_ICDIPR112_TINT33_SHIFT (8u) +#define INTC_ICDIPR112_TINT34_SHIFT (16u) +#define INTC_ICDIPR112_TINT35_SHIFT (24u) + +#define INTC_ICDIPR113_TINT36_SHIFT (0u) +#define INTC_ICDIPR113_TINT37_SHIFT (8u) +#define INTC_ICDIPR113_TINT38_SHIFT (16u) +#define INTC_ICDIPR113_TINT39_SHIFT (24u) + +#define INTC_ICDIPR114_TINT40_SHIFT (0u) +#define INTC_ICDIPR114_TINT41_SHIFT (8u) +#define INTC_ICDIPR114_TINT42_SHIFT (16u) +#define INTC_ICDIPR114_TINT43_SHIFT (24u) + +#define INTC_ICDIPR115_TINT44_SHIFT (0u) +#define INTC_ICDIPR115_TINT45_SHIFT (8u) +#define INTC_ICDIPR115_TINT46_SHIFT (16u) +#define INTC_ICDIPR115_TINT47_SHIFT (24u) + +#define INTC_ICDIPR116_TINT48_SHIFT (0u) +#define INTC_ICDIPR116_TINT49_SHIFT (8u) +#define INTC_ICDIPR116_TINT50_SHIFT (16u) +#define INTC_ICDIPR116_TINT51_SHIFT (24u) + +#define INTC_ICDIPR117_TINT52_SHIFT (0u) +#define INTC_ICDIPR117_TINT53_SHIFT (8u) +#define INTC_ICDIPR117_TINT54_SHIFT (16u) +#define INTC_ICDIPR117_TINT55_SHIFT (24u) + +#define INTC_ICDIPR118_TINT56_SHIFT (0u) +#define INTC_ICDIPR118_TINT57_SHIFT (8u) +#define INTC_ICDIPR118_TINT58_SHIFT (16u) +#define INTC_ICDIPR118_TINT59_SHIFT (24u) + +#define INTC_ICDIPR119_TINT60_SHIFT (0u) +#define INTC_ICDIPR119_TINT61_SHIFT (8u) +#define INTC_ICDIPR119_TINT62_SHIFT (16u) +#define INTC_ICDIPR119_TINT63_SHIFT (24u) + +#define INTC_ICDIPR120_TINT64_SHIFT (0u) +#define INTC_ICDIPR120_TINT65_SHIFT (8u) +#define INTC_ICDIPR120_TINT66_SHIFT (16u) +#define INTC_ICDIPR120_TINT67_SHIFT (24u) + +#define INTC_ICDIPR121_TINT68_SHIFT (0u) +#define INTC_ICDIPR121_TINT69_SHIFT (8u) +#define INTC_ICDIPR121_TINT70_SHIFT (16u) +#define INTC_ICDIPR121_TINT71_SHIFT (24u) + +#define INTC_ICDIPR122_TINT72_SHIFT (0u) +#define INTC_ICDIPR122_TINT73_SHIFT (8u) +#define INTC_ICDIPR122_TINT74_SHIFT (16u) +#define INTC_ICDIPR122_TINT75_SHIFT (24u) + +#define INTC_ICDIPR123_TINT76_SHIFT (0u) +#define INTC_ICDIPR123_TINT77_SHIFT (8u) +#define INTC_ICDIPR123_TINT78_SHIFT (16u) +#define INTC_ICDIPR123_TINT79_SHIFT (24u) + +#define INTC_ICDIPR124_TINT80_SHIFT (0u) +#define INTC_ICDIPR124_TINT81_SHIFT (8u) +#define INTC_ICDIPR124_TINT82_SHIFT (16u) +#define INTC_ICDIPR124_TINT83_SHIFT (24u) + +#define INTC_ICDIPR125_TINT84_SHIFT (0u) +#define INTC_ICDIPR125_TINT85_SHIFT (8u) +#define INTC_ICDIPR125_TINT86_SHIFT (16u) +#define INTC_ICDIPR125_TINT87_SHIFT (24u) + +#define INTC_ICDIPR126_TINT88_SHIFT (0u) +#define INTC_ICDIPR126_TINT89_SHIFT (8u) +#define INTC_ICDIPR126_TINT90_SHIFT (16u) +#define INTC_ICDIPR126_TINT91_SHIFT (24u) + +#define INTC_ICDIPR127_TINT92_SHIFT (0u) +#define INTC_ICDIPR127_TINT93_SHIFT (8u) +#define INTC_ICDIPR127_TINT94_SHIFT (16u) +#define INTC_ICDIPR127_TINT95_SHIFT (24u) + +#define INTC_ICDIPR128_TINT96_SHIFT (0u) +#define INTC_ICDIPR128_TINT97_SHIFT (8u) +#define INTC_ICDIPR128_TINT98_SHIFT (16u) +#define INTC_ICDIPR128_TINT99_SHIFT (24u) + +#define INTC_ICDIPR129_TINT100_SHIFT (0u) +#define INTC_ICDIPR129_TINT101_SHIFT (8u) +#define INTC_ICDIPR129_TINT102_SHIFT (16u) +#define INTC_ICDIPR129_TINT103_SHIFT (24u) + +#define INTC_ICDIPR130_TINT104_SHIFT (0u) +#define INTC_ICDIPR130_TINT105_SHIFT (8u) +#define INTC_ICDIPR130_TINT106_SHIFT (16u) +#define INTC_ICDIPR130_TINT107_SHIFT (24u) + +#define INTC_ICDIPR131_TINT108_SHIFT (0u) +#define INTC_ICDIPR131_TINT109_SHIFT (8u) +#define INTC_ICDIPR131_TINT110_SHIFT (16u) +#define INTC_ICDIPR131_TINT111_SHIFT (24u) + +#define INTC_ICDIPR132_TINT112_SHIFT (0u) +#define INTC_ICDIPR132_TINT113_SHIFT (8u) +#define INTC_ICDIPR132_TINT114_SHIFT (16u) +#define INTC_ICDIPR132_TINT115_SHIFT (24u) + +#define INTC_ICDIPR133_TINT116_SHIFT (0u) +#define INTC_ICDIPR133_TINT117_SHIFT (8u) +#define INTC_ICDIPR133_TINT118_SHIFT (16u) +#define INTC_ICDIPR133_TINT119_SHIFT (24u) + +#define INTC_ICDIPR134_TINT120_SHIFT (0u) +#define INTC_ICDIPR134_TINT121_SHIFT (8u) +#define INTC_ICDIPR134_TINT122_SHIFT (16u) +#define INTC_ICDIPR134_TINT123_SHIFT (24u) + +#define INTC_ICDIPR135_TINT124_SHIFT (0u) +#define INTC_ICDIPR135_TINT125_SHIFT (8u) +#define INTC_ICDIPR135_TINT126_SHIFT (16u) +#define INTC_ICDIPR135_TINT127_SHIFT (24u) + +#define INTC_ICDIPR136_TINT128_SHIFT (0u) +#define INTC_ICDIPR136_TINT129_SHIFT (8u) +#define INTC_ICDIPR136_TINT130_SHIFT (16u) +#define INTC_ICDIPR136_TINT131_SHIFT (24u) + +#define INTC_ICDIPR137_TINT132_SHIFT (0u) +#define INTC_ICDIPR137_TINT133_SHIFT (8u) +#define INTC_ICDIPR137_TINT134_SHIFT (16u) +#define INTC_ICDIPR137_TINT135_SHIFT (24u) + +#define INTC_ICDIPR138_TINT136_SHIFT (0u) +#define INTC_ICDIPR138_TINT137_SHIFT (8u) +#define INTC_ICDIPR138_TINT138_SHIFT (16u) +#define INTC_ICDIPR138_TINT139_SHIFT (24u) + +#define INTC_ICDIPR139_TINT140_SHIFT (0u) +#define INTC_ICDIPR139_TINT141_SHIFT (8u) +#define INTC_ICDIPR139_TINT142_SHIFT (16u) +#define INTC_ICDIPR139_TINT143_SHIFT (24u) + +#define INTC_ICDIPR140_TINT144_SHIFT (0u) +#define INTC_ICDIPR140_TINT145_SHIFT (8u) +#define INTC_ICDIPR140_TINT146_SHIFT (16u) +#define INTC_ICDIPR140_TINT147_SHIFT (24u) + +#define INTC_ICDIPR141_TINT148_SHIFT (0u) +#define INTC_ICDIPR141_TINT149_SHIFT (8u) +#define INTC_ICDIPR141_TINT150_SHIFT (16u) +#define INTC_ICDIPR141_TINT151_SHIFT (24u) + +#define INTC_ICDIPR142_TINT152_SHIFT (0u) +#define INTC_ICDIPR142_TINT153_SHIFT (8u) +#define INTC_ICDIPR142_TINT154_SHIFT (16u) +#define INTC_ICDIPR142_TINT155_SHIFT (24u) + +#define INTC_ICDIPR143_TINT156_SHIFT (0u) +#define INTC_ICDIPR143_TINT157_SHIFT (8u) +#define INTC_ICDIPR143_TINT158_SHIFT (16u) +#define INTC_ICDIPR143_TINT159_SHIFT (24u) + +#define INTC_ICDIPR144_TINT160_SHIFT (0u) +#define INTC_ICDIPR144_TINT161_SHIFT (8u) +#define INTC_ICDIPR144_TINT162_SHIFT (16u) +#define INTC_ICDIPR144_TINT163_SHIFT (24u) + +#define INTC_ICDIPR145_TINT164_SHIFT (0u) +#define INTC_ICDIPR145_TINT165_SHIFT (8u) +#define INTC_ICDIPR145_TINT166_SHIFT (16u) +#define INTC_ICDIPR145_TINT167_SHIFT (24u) + +#define INTC_ICDIPR146_TINT168_SHIFT (0u) +#define INTC_ICDIPR146_TINT169_SHIFT (8u) +#define INTC_ICDIPR146_TINT170_SHIFT (16u) + +#define INTC_ICDIPTR0_SW0_SHIFT (0u) +#define INTC_ICDIPTR0_SW1_SHIFT (8u) +#define INTC_ICDIPTR0_SW2_SHIFT (16u) +#define INTC_ICDIPTR0_SW3_SHIFT (24u) + +#define INTC_ICDIPTR1_SW4_SHIFT (0u) +#define INTC_ICDIPTR1_SW5_SHIFT (8u) +#define INTC_ICDIPTR1_SW6_SHIFT (16u) +#define INTC_ICDIPTR1_SW7_SHIFT (24u) + +#define INTC_ICDIPTR2_SW8_SHIFT (0u) +#define INTC_ICDIPTR2_SW9_SHIFT (8u) +#define INTC_ICDIPTR2_SW10_SHIFT (16u) +#define INTC_ICDIPTR2_SW11_SHIFT (24u) + +#define INTC_ICDIPTR3_SW12_SHIFT (0u) +#define INTC_ICDIPTR3_SW13_SHIFT (8u) +#define INTC_ICDIPTR3_SW14_SHIFT (16u) +#define INTC_ICDIPTR3_SW15_SHIFT (24u) + +#define INTC_ICDIPTR4_PMUIRQ0_SHIFT (0u) +#define INTC_ICDIPTR4_COMMRX0_SHIFT (8u) +#define INTC_ICDIPTR4_COMMTX0_SHIFT (16u) +#define INTC_ICDIPTR4_CTIIRQ0_SHIFT (24u) + +#define INTC_ICDIPTR8_IRQ0_SHIFT (0u) +#define INTC_ICDIPTR8_IRQ1_SHIFT (8u) +#define INTC_ICDIPTR8_IRQ2_SHIFT (16u) +#define INTC_ICDIPTR8_IRQ3_SHIFT (24u) + +#define INTC_ICDIPTR9_IRQ4_SHIFT (0u) +#define INTC_ICDIPTR9_IRQ5_SHIFT (8u) +#define INTC_ICDIPTR9_IRQ6_SHIFT (16u) +#define INTC_ICDIPTR9_IRQ7_SHIFT (24u) + +#define INTC_ICDIPTR10_PL310ERR_SHIFT (0u) +#define INTC_ICDIPTR10_DMAINT0_SHIFT (8u) +#define INTC_ICDIPTR10_DMAINT1_SHIFT (16u) +#define INTC_ICDIPTR10_DMAINT2_SHIFT (24u) + +#define INTC_ICDIPTR11_DMAINT3_SHIFT (0u) +#define INTC_ICDIPTR11_DMAINT4_SHIFT (8u) +#define INTC_ICDIPTR11_DMAINT5_SHIFT (16u) +#define INTC_ICDIPTR11_DMAINT6_SHIFT (24u) + +#define INTC_ICDIPTR12_DMAINT7_SHIFT (0u) +#define INTC_ICDIPTR12_DMAINT8_SHIFT (8u) +#define INTC_ICDIPTR12_DMAINT9_SHIFT (16u) +#define INTC_ICDIPTR12_DMAINT10_SHIFT (24u) + +#define INTC_ICDIPTR13_DMAINT11_SHIFT (0u) +#define INTC_ICDIPTR13_DMAINT12_SHIFT (8u) +#define INTC_ICDIPTR13_DMAINT13_SHIFT (16u) +#define INTC_ICDIPTR13_DMAINT14_SHIFT (24u) + +#define INTC_ICDIPTR14_DMAINT15_SHIFT (0u) +#define INTC_ICDIPTR14_DMAERR_SHIFT (8u) + +#define INTC_ICDIPTR18_USBI0_SHIFT (8u) +#define INTC_ICDIPTR18_USBI1_SHIFT (16u) +#define INTC_ICDIPTR18_S0_VI_VSYNC0_SHIFT (24u) + +#define INTC_ICDIPTR19_S0_LO_VSYNC0_SHIFT (0u) +#define INTC_ICDIPTR19_S0_VSYNCERR0_SHIFT (8u) +#define INTC_ICDIPTR19_GR3_VLINE0_SHIFT (16u) +#define INTC_ICDIPTR19_S0_VFIELD0_SHIFT (24u) + +#define INTC_ICDIPTR20_IV1_VBUFERR0_SHIFT (0u) +#define INTC_ICDIPTR20_IV3_VBUFERR0_SHIFT (8u) +#define INTC_ICDIPTR20_IV5_VBUFERR0_SHIFT (16u) +#define INTC_ICDIPTR20_IV6_VBUFERR0_SHIFT (24u) + +#define INTC_ICDIPTR21_S0_WLINE0_SHIFT (0u) +#define INTC_ICDIPTR21_S1_VI_VSYNC0_SHIFT (8u) +#define INTC_ICDIPTR21_S1_LO_VSYNC0_SHIFT (16u) +#define INTC_ICDIPTR21_S1_VSYNCERR0_SHIFT (24u) + +#define INTC_ICDIPTR22_S1_VFIELD0_SHIFT (0u) +#define INTC_ICDIPTR22_IV2_VBUFERR0_SHIFT (8u) +#define INTC_ICDIPTR22_IV4_VBUFERR0_SHIFT (16u) +#define INTC_ICDIPTR22_S1_WLINE0_SHIFT (24u) + +#define INTC_ICDIPTR23_OIR_VI_VSYNC0_SHIFT (0u) +#define INTC_ICDIPTR23_OIR_LO_VSYNC0_SHIFT (8u) +#define INTC_ICDIPTR23_OIR_VSYNCERR0_SHIFT (16u) +#define INTC_ICDIPTR23_OIR_VFIELD0_SHIFT (24u) + +#define INTC_ICDIPTR24_IV7_VBUFERR0_SHIFT (0u) +#define INTC_ICDIPTR24_IV8_VBUFERR0_SHIFT (8u) +#define INTC_ICDIPTR24_S0_VI_VSYNC1_SHIFT (24u) + +#define INTC_ICDIPTR25_S0_LO_VSYNC1_SHIFT (0u) +#define INTC_ICDIPTR25_S0_VSYNCERR1_SHIFT (8u) +#define INTC_ICDIPTR25_GR3_VLINE1_SHIFT (16u) +#define INTC_ICDIPTR25_S0_VFIELD1_SHIFT (24u) + +#define INTC_ICDIPTR26_IV1_VBUFERR1_SHIFT (0u) +#define INTC_ICDIPTR26_IV3_VBUFERR1_SHIFT (8u) +#define INTC_ICDIPTR26_IV5_VBUFERR1_SHIFT (16u) +#define INTC_ICDIPTR26_IV6_VBUFERR1_SHIFT (24u) + +#define INTC_ICDIPTR27_S0_WLINE1_SHIFT (0u) +#define INTC_ICDIPTR27_S1_VI_VSYNC1_SHIFT (8u) +#define INTC_ICDIPTR27_S1_LO_VSYNC1_SHIFT (16u) +#define INTC_ICDIPTR27_S1_VSYNCERR1_SHIFT (24u) + +#define INTC_ICDIPTR28_S1_VFIELD1_SHIFT (0u) +#define INTC_ICDIPTR28_IV2_VBUFERR1_SHIFT (8u) +#define INTC_ICDIPTR28_IV4_VBUFERR1_SHIFT (16u) +#define INTC_ICDIPTR28_S1_WLINE1_SHIFT (24u) + +#define INTC_ICDIPTR29_OIR_VI_VSYNC1_SHIFT (0u) +#define INTC_ICDIPTR29_OIR_LO_VSYNC1_SHIFT (8u) +#define INTC_ICDIPTR29_OIR_VLINE1_SHIFT (16u) +#define INTC_ICDIPTR29_OIR_VFIELD1_SHIFT (24u) + +#define INTC_ICDIPTR30_IV7_VBUFERR1_SHIFT (0u) +#define INTC_ICDIPTR30_IV8_VBUFERR1_SHIFT (8u) +#define INTC_ICDIPTR30_IMRDI_SHIFT (24u) + +#define INTC_ICDIPTR31_IMR2I0_SHIFT (0u) +#define INTC_ICDIPTR31_IMR2I1_SHIFT (8u) +#define INTC_ICDIPTR31_JEDI_SHIFT (16u) +#define INTC_ICDIPTR31_JDTI_SHIFT (24u) + +#define INTC_ICDIPTR32_CMP0_SHIFT (0u) +#define INTC_ICDIPTR32_CMP1_SHIFT (8u) +#define INTC_ICDIPTR32_INT0_SHIFT (16u) +#define INTC_ICDIPTR32_INT1_SHIFT (24u) + +#define INTC_ICDIPTR33_INT2_SHIFT (0u) +#define INTC_ICDIPTR33_INT3_SHIFT (8u) +#define INTC_ICDIPTR33_OSTM0TINT_SHIFT (16u) +#define INTC_ICDIPTR33_OSTM1TINT_SHIFT (24u) + +#define INTC_ICDIPTR34_CMI_SHIFT (0u) +#define INTC_ICDIPTR34_WTOUT_SHIFT (8u) +#define INTC_ICDIPTR34_ITI_SHIFT (16u) +#define INTC_ICDIPTR34_TGI0A_SHIFT (24u) + +#define INTC_ICDIPTR35_TGI0B_SHIFT (0u) +#define INTC_ICDIPTR35_TGI0C_SHIFT (8u) +#define INTC_ICDIPTR35_TGI0D_SHIFT (16u) +#define INTC_ICDIPTR35_TGI0V_SHIFT (24u) + +#define INTC_ICDIPTR36_TGI0E_SHIFT (0u) +#define INTC_ICDIPTR36_TGI0F_SHIFT (8u) +#define INTC_ICDIPTR36_TGI1A_SHIFT (16u) +#define INTC_ICDIPTR36_TGI1B_SHIFT (24u) + +#define INTC_ICDIPTR37_TGI1V_SHIFT (0u) +#define INTC_ICDIPTR37_TGI1U_SHIFT (8u) +#define INTC_ICDIPTR37_TGI2A_SHIFT (16u) +#define INTC_ICDIPTR37_TGI2B_SHIFT (24u) + +#define INTC_ICDIPTR38_TGI2V_SHIFT (0u) +#define INTC_ICDIPTR38_TGI2U_SHIFT (8u) +#define INTC_ICDIPTR38_TGI3A_SHIFT (16u) +#define INTC_ICDIPTR38_TGI3B_SHIFT (24u) + +#define INTC_ICDIPTR39_TGI3C_SHIFT (0u) +#define INTC_ICDIPTR39_TGI3D_SHIFT (8u) +#define INTC_ICDIPTR39_TGI3V_SHIFT (16u) +#define INTC_ICDIPTR39_TGI4A_SHIFT (24u) + +#define INTC_ICDIPTR40_TGI4B_SHIFT (0u) +#define INTC_ICDIPTR40_TGI4C_SHIFT (8u) +#define INTC_ICDIPTR40_TGI4D_SHIFT (16u) +#define INTC_ICDIPTR40_TGI4V_SHIFT (24u) + +#define INTC_ICDIPTR41_CMI1_SHIFT (0u) +#define INTC_ICDIPTR41_CMI2_SHIFT (8u) +#define INTC_ICDIPTR41_SGDEI0_SHIFT (16u) +#define INTC_ICDIPTR41_SGDEI1_SHIFT (24u) + +#define INTC_ICDIPTR42_SGDEI2_SHIFT (0u) +#define INTC_ICDIPTR42_SGDEI3_SHIFT (8u) +#define INTC_ICDIPTR42_ADI_SHIFT (16u) +#define INTC_ICDIPTR42_LMTI_SHIFT (24u) + +#define INTC_ICDIPTR43_SSII0_SHIFT (0u) +#define INTC_ICDIPTR43_SSIRXI0_SHIFT (8u) +#define INTC_ICDIPTR43_SSITXI0_SHIFT (16u) +#define INTC_ICDIPTR43_SSII1_SHIFT (24u) + +#define INTC_ICDIPTR44_SSIRXI1_SHIFT (0u) +#define INTC_ICDIPTR44_SSITXI1_SHIFT (8u) +#define INTC_ICDIPTR44_SSII2_SHIFT (16u) +#define INTC_ICDIPTR44_SSIRTI2_SHIFT (24u) + +#define INTC_ICDIPTR45_SSII3_SHIFT (0u) +#define INTC_ICDIPTR45_SSIRXI3_SHIFT (8u) +#define INTC_ICDIPTR45_SSITXI3_SHIFT (16u) +#define INTC_ICDIPTR45_SSII4_SHIFT (24u) + +#define INTC_ICDIPTR46_SSIRTI4_SHIFT (0u) +#define INTC_ICDIPTR46_SSII5_SHIFT (8u) +#define INTC_ICDIPTR46_SSIRXI5_SHIFT (16u) +#define INTC_ICDIPTR46_SSITXI5_SHIFT (24u) + +#define INTC_ICDIPTR47_SPDIFI_SHIFT (0u) +#define INTC_ICDIPTR47_INTIICTEI0_SHIFT (8u) +#define INTC_ICDIPTR47_INTIICRI0_SHIFT (16u) +#define INTC_ICDIPTR47_INTIICTI0_SHIFT (24u) + +#define INTC_ICDIPTR48_INTIICSPI0_SHIFT (0u) +#define INTC_ICDIPTR48_INTIICSTI0_SHIFT (8u) +#define INTC_ICDIPTR48_INTIICNAKI0_SHIFT (16u) +#define INTC_ICDIPTR48_INTIICALI0_SHIFT (24u) + +#define INTC_ICDIPTR49_INTIICTMOI0_SHIFT (0u) +#define INTC_ICDIPTR49_INTIICTEI1_SHIFT (8u) +#define INTC_ICDIPTR49_INTIICRI1_SHIFT (16u) +#define INTC_ICDIPTR49_INTIICTI1_SHIFT (24u) + +#define INTC_ICDIPTR50_INTIICSPI1_SHIFT (0u) +#define INTC_ICDIPTR50_INTIICSTI1_SHIFT (8u) +#define INTC_ICDIPTR50_INTIICNAKI1_SHIFT (16u) +#define INTC_ICDIPTR50_INTIICALI1_SHIFT (24u) + +#define INTC_ICDIPTR51_INTIICTMOI1_SHIFT (0u) +#define INTC_ICDIPTR51_INTIICTEI2_SHIFT (8u) +#define INTC_ICDIPTR51_INTIICRI2_SHIFT (16u) +#define INTC_ICDIPTR51_INTIICTI2_SHIFT (24u) + +#define INTC_ICDIPTR52_INTIICSPI2_SHIFT (0u) +#define INTC_ICDIPTR52_INTIICSTI2_SHIFT (8u) +#define INTC_ICDIPTR52_INTIICNAKI2_SHIFT (16u) +#define INTC_ICDIPTR52_INTIICALI2_SHIFT (24u) + +#define INTC_ICDIPTR53_INTIICTMOI2_SHIFT (0u) +#define INTC_ICDIPTR53_INTIICTEI3_SHIFT (8u) +#define INTC_ICDIPTR53_INTIICRI3_SHIFT (16u) +#define INTC_ICDIPTR53_INTIICTI3_SHIFT (24u) + +#define INTC_ICDIPTR54_INTIICSPI3_SHIFT (0u) +#define INTC_ICDIPTR54_INTIICSTI3_SHIFT (8u) +#define INTC_ICDIPTR54_INTIICNAKI3_SHIFT (16u) +#define INTC_ICDIPTR54_INTIICALI3_SHIFT (24u) + +#define INTC_ICDIPTR55_INTIICTMOI3_SHIFT (0u) +#define INTC_ICDIPTR55_BRI0_SHIFT (8u) +#define INTC_ICDIPTR55_ERI0_SHIFT (16u) +#define INTC_ICDIPTR55_RXI0_SHIFT (24u) + +#define INTC_ICDIPTR56_TXI0_SHIFT (0u) +#define INTC_ICDIPTR56_BRI1_SHIFT (8u) +#define INTC_ICDIPTR56_ERI1_SHIFT (16u) +#define INTC_ICDIPTR56_RXI1_SHIFT (24u) + +#define INTC_ICDIPTR57_TXI1_SHIFT (0u) +#define INTC_ICDIPTR57_BRI2_SHIFT (8u) +#define INTC_ICDIPTR57_ERI2_SHIFT (16u) +#define INTC_ICDIPTR57_RXI2_SHIFT (24u) + +#define INTC_ICDIPTR58_TXI2_SHIFT (0u) +#define INTC_ICDIPTR58_BRI3_SHIFT (8u) +#define INTC_ICDIPTR58_ERI3_SHIFT (16u) +#define INTC_ICDIPTR58_RXI3_SHIFT (24u) + +#define INTC_ICDIPTR59_TXI3_SHIFT (0u) +#define INTC_ICDIPTR59_BRI4_SHIFT (8u) +#define INTC_ICDIPTR59_ERI4_SHIFT (16u) +#define INTC_ICDIPTR59_RXI4_SHIFT (24u) + +#define INTC_ICDIPTR60_TXI4_SHIFT (0u) +#define INTC_ICDIPTR60_BRI5_SHIFT (8u) +#define INTC_ICDIPTR60_ERI5_SHIFT (16u) +#define INTC_ICDIPTR60_RXI5_SHIFT (24u) + +#define INTC_ICDIPTR61_TXI5_SHIFT (0u) +#define INTC_ICDIPTR61_BRI6_SHIFT (8u) +#define INTC_ICDIPTR61_ERI6_SHIFT (16u) +#define INTC_ICDIPTR61_RXI6_SHIFT (24u) + +#define INTC_ICDIPTR62_TXI6_SHIFT (0u) +#define INTC_ICDIPTR62_BRI7_SHIFT (8u) +#define INTC_ICDIPTR62_ERI7_SHIFT (16u) +#define INTC_ICDIPTR62_RXI7_SHIFT (24u) + +#define INTC_ICDIPTR63_TXI7_SHIFT (0u) +#define INTC_ICDIPTR63_INTRCANGERR_SHIFT (8u) +#define INTC_ICDIPTR63_INTRCANGRECC_SHIFT (16u) +#define INTC_ICDIPTR63_INTRCAN0REC_SHIFT (24u) + +#define INTC_ICDIPTR64_INTRCAN0ERR_SHIFT (0u) +#define INTC_ICDIPTR64_INTRCAN0TRX_SHIFT (8u) +#define INTC_ICDIPTR64_INTRCAN1REC_SHIFT (16u) +#define INTC_ICDIPTR64_INTRCAN1ERR_SHIFT (24u) + +#define INTC_ICDIPTR65_INTRCAN1TRX_SHIFT (0u) +#define INTC_ICDIPTR65_INTRCAN2REC_SHIFT (8u) +#define INTC_ICDIPTR65_INTRCAN2ERR_SHIFT (16u) +#define INTC_ICDIPTR65_INTRCAN2TRX_SHIFT (24u) + +#define INTC_ICDIPTR66_INTRCAN3REC_SHIFT (0u) +#define INTC_ICDIPTR66_INTRCAN3ERR_SHIFT (8u) +#define INTC_ICDIPTR66_INTRCAN3TRX_SHIFT (16u) +#define INTC_ICDIPTR66_INTRCAN4REC_SHIFT (24u) + +#define INTC_ICDIPTR67_INTRCAN4ERR_SHIFT (0u) +#define INTC_ICDIPTR67_INTRCAN4TRX_SHIFT (8u) +#define INTC_ICDIPTR67_SPEI0_SHIFT (16u) +#define INTC_ICDIPTR67_SPRI0_SHIFT (24u) + +#define INTC_ICDIPTR68_SPTI0_SHIFT (0u) +#define INTC_ICDIPTR68_SPEI1_SHIFT (8u) +#define INTC_ICDIPTR68_SPRI1_SHIFT (16u) +#define INTC_ICDIPTR68_SPTI1_SHIFT (24u) + +#define INTC_ICDIPTR69_SPEI2_SHIFT (0u) +#define INTC_ICDIPTR69_SPRI2_SHIFT (8u) +#define INTC_ICDIPTR69_SPTI2_SHIFT (16u) +#define INTC_ICDIPTR69_SPEI3_SHIFT (24u) + +#define INTC_ICDIPTR70_SPRI3_SHIFT (0u) +#define INTC_ICDIPTR70_SPTI3_SHIFT (8u) +#define INTC_ICDIPTR70_SPEI4_SHIFT (16u) +#define INTC_ICDIPTR70_SPRI4_SHIFT (24u) + +#define INTC_ICDIPTR71_SPTI4_SHIFT (0u) +#define INTC_ICDIPTR71_IEBBTD_SHIFT (8u) +#define INTC_ICDIPTR71_IEBBTERR_SHIFT (16u) +#define INTC_ICDIPTR71_IEBBTSTA_SHIFT (24u) + +#define INTC_ICDIPTR72_IEBBTV_SHIFT (0u) +#define INTC_ICDIPTR72_ISY_SHIFT (8u) +#define INTC_ICDIPTR72_IERR_SHIFT (16u) +#define INTC_ICDIPTR72_ITARG_SHIFT (24u) + +#define INTC_ICDIPTR73_ISEC_SHIFT (0u) +#define INTC_ICDIPTR73_IBUF_SHIFT (8u) +#define INTC_ICDIPTR73_IREADY_SHIFT (16u) +#define INTC_ICDIPTR73_FLSTE_SHIFT (24u) + +#define INTC_ICDIPTR74_FLTENDI_SHIFT (0u) +#define INTC_ICDIPTR74_FLTREQ0I_SHIFT (8u) +#define INTC_ICDIPTR74_FLTREQ1I_SHIFT (16u) +#define INTC_ICDIPTR74_MMC0_SHIFT (24u) + +#define INTC_ICDIPTR75_MMC1_SHIFT (0u) +#define INTC_ICDIPTR75_MMC2_SHIFT (8u) +#define INTC_ICDIPTR75_SDHI0_3_SHIFT (16u) +#define INTC_ICDIPTR75_SDHI0_0_SHIFT (24u) + +#define INTC_ICDIPTR76_SDHI0_1_SHIFT (0u) +#define INTC_ICDIPTR76_SDHI1_3_SHIFT (8u) +#define INTC_ICDIPTR76_SDHI1_0_SHIFT (16u) +#define INTC_ICDIPTR76_SDHI1_1_SHIFT (24u) + +#define INTC_ICDIPTR77_ARM_SHIFT (0u) +#define INTC_ICDIPTR77_PRD_SHIFT (8u) +#define INTC_ICDIPTR77_CUP_SHIFT (16u) +#define INTC_ICDIPTR77_SCUAI0_SHIFT (24u) + +#define INTC_ICDIPTR78_SCUAI1_SHIFT (0u) +#define INTC_ICDIPTR78_SCUFDI0_SHIFT (8u) +#define INTC_ICDIPTR78_SCUFDI1_SHIFT (16u) +#define INTC_ICDIPTR78_SCUFDI2_SHIFT (24u) + +#define INTC_ICDIPTR79_SCUFDI3_SHIFT (0u) +#define INTC_ICDIPTR79_SCUFUI0_SHIFT (8u) +#define INTC_ICDIPTR79_SCUFUI1_SHIFT (16u) +#define INTC_ICDIPTR79_SCUFUI2_SHIFT (24u) + +#define INTC_ICDIPTR80_SCUFUI3_SHIFT (0u) +#define INTC_ICDIPTR80_SCUDVI0_SHIFT (8u) +#define INTC_ICDIPTR80_SCUDVI1_SHIFT (16u) +#define INTC_ICDIPTR80_SCUDVI2_SHIFT (24u) + +#define INTC_ICDIPTR81_SCUDVI3_SHIFT (0u) +#define INTC_ICDIPTR81_MLB_CINT_SHIFT (8u) +#define INTC_ICDIPTR81_MLB_SINT_SHIFT (16u) +#define INTC_ICDIPTR81_DRC0_SHIFT (24u) + +#define INTC_ICDIPTR82_DRC1_SHIFT (0u) +#define INTC_ICDIPTR82_LINI0_INT_T_SHIFT (24u) + +#define INTC_ICDIPTR83_LINI0_INT_R_SHIFT (0u) +#define INTC_ICDIPTR83_LINI0_INT_S_SHIFT (8u) +#define INTC_ICDIPTR83_LINI0_INT_M_SHIFT (16u) +#define INTC_ICDIPTR83_LINI1_INT_T_SHIFT (24u) + +#define INTC_ICDIPTR84_LINI1_INT_R_SHIFT (0u) +#define INTC_ICDIPTR84_LINI1_INT_S_SHIFT (8u) +#define INTC_ICDIPTR84_LINI1_INT_M_SHIFT (16u) + +#define INTC_ICDIPTR86_ERI0_SHIFT (24u) + +#define INTC_ICDIPTR87_RXI0_SHIFT (0u) +#define INTC_ICDIPTR87_TXI0_SHIFT (8u) +#define INTC_ICDIPTR87_TEI0_SHIFT (16u) +#define INTC_ICDIPTR87_ERI1_SHIFT (24u) + +#define INTC_ICDIPTR88_RXI1_SHIFT (0u) +#define INTC_ICDIPTR88_TXI1_SHIFT (8u) +#define INTC_ICDIPTR88_TEI1_SHIFT (16u) +#define INTC_ICDIPTR88_AVBI_DATA_SHIFT (24u) + +#define INTC_ICDIPTR89_AVBI_ERROR_SHIFT (0u) +#define INTC_ICDIPTR89_AVBI_MANAGE_SHIFT (8u) +#define INTC_ICDIPTR89_AVBI_MAC_SHIFT (16u) +#define INTC_ICDIPTR89_ETHERI_SHIFT (24u) + +#define INTC_ICDIPTR91_CEUI_SHIFT (0u) + +#define INTC_ICDIPTR95_H2XMLB_ERRINT_SHIFT (8u) +#define INTC_ICDIPTR95_H2XIC1_ERRINT_SHIFT (16u) +#define INTC_ICDIPTR95_X2HPERI1_ERRINT_SHIFT (24u) + +#define INTC_ICDIPTR96_X2HPERI2_ERRINT_SHIFT (0u) +#define INTC_ICDIPTR96_X2HPERI34_ERRINT_SHIFT (8u) +#define INTC_ICDIPTR96_X2HPERI5_ERRINT_SHIFT (16u) +#define INTC_ICDIPTR96_X2HPERI67_ERRINT_SHIFT (24u) + +#define INTC_ICDIPTR97_X2HDBGR_ERRINT_SHIFT (0u) +#define INTC_ICDIPTR97_X2HBSC_ERRINT_SHIFT (8u) +#define INTC_ICDIPTR97_X2HSPI1_ERRINT_SHIFT (16u) +#define INTC_ICDIPTR97_X2HSPI2_ERRINT_SHIFT (24u) + +#define INTC_ICDIPTR98_PRRI_SHIFT (0u) +#define INTC_ICDIPTR98_IFEI0_SHIFT (8u) +#define INTC_ICDIPTR98_OFFI0_SHIFT (16u) +#define INTC_ICDIPTR98_PFVEI0_SHIFT (24u) + +#define INTC_ICDIPTR99_IFEI1_SHIFT (0u) +#define INTC_ICDIPTR99_OFFI1_SHIFT (8u) +#define INTC_ICDIPTR99_PFVEI1_SHIFT (16u) + +#define INTC_ICDIPTR104_TINT0_SHIFT (0u) +#define INTC_ICDIPTR104_TINT1_SHIFT (8u) +#define INTC_ICDIPTR104_TINT2_SHIFT (16u) +#define INTC_ICDIPTR104_TINT3_SHIFT (24u) + +#define INTC_ICDIPTR105_TINT4_SHIFT (0u) +#define INTC_ICDIPTR105_TINT5_SHIFT (8u) +#define INTC_ICDIPTR105_TINT6_SHIFT (16u) +#define INTC_ICDIPTR105_TINT7_SHIFT (24u) + +#define INTC_ICDIPTR106_TINT8_SHIFT (0u) +#define INTC_ICDIPTR106_TINT9_SHIFT (8u) +#define INTC_ICDIPTR106_TINT10_SHIFT (16u) +#define INTC_ICDIPTR106_TINT11_SHIFT (24u) + +#define INTC_ICDIPTR107_TINT12_SHIFT (0u) +#define INTC_ICDIPTR107_TINT13_SHIFT (8u) +#define INTC_ICDIPTR107_TINT14_SHIFT (16u) +#define INTC_ICDIPTR107_TINT15_SHIFT (24u) + +#define INTC_ICDIPTR108_TINT16_SHIFT (0u) +#define INTC_ICDIPTR108_TINT17_SHIFT (8u) +#define INTC_ICDIPTR108_TINT18_SHIFT (16u) +#define INTC_ICDIPTR108_TINT19_SHIFT (24u) + +#define INTC_ICDIPTR109_TINT20_SHIFT (0u) +#define INTC_ICDIPTR109_TINT21_SHIFT (8u) +#define INTC_ICDIPTR109_TINT22_SHIFT (16u) +#define INTC_ICDIPTR109_TINT23_SHIFT (24u) + +#define INTC_ICDIPTR110_TINT24_SHIFT (0u) +#define INTC_ICDIPTR110_TINT25_SHIFT (8u) +#define INTC_ICDIPTR110_TINT26_SHIFT (16u) +#define INTC_ICDIPTR110_TINT27_SHIFT (24u) + +#define INTC_ICDIPTR111_TINT28_SHIFT (0u) +#define INTC_ICDIPTR111_TINT29_SHIFT (8u) +#define INTC_ICDIPTR111_TINT30_SHIFT (16u) +#define INTC_ICDIPTR111_TINT31_SHIFT (24u) + +#define INTC_ICDIPTR112_TINT32_SHIFT (0u) +#define INTC_ICDIPTR112_TINT33_SHIFT (8u) +#define INTC_ICDIPTR112_TINT34_SHIFT (16u) +#define INTC_ICDIPTR112_TINT35_SHIFT (24u) + +#define INTC_ICDIPTR113_TINT36_SHIFT (0u) +#define INTC_ICDIPTR113_TINT37_SHIFT (8u) +#define INTC_ICDIPTR113_TINT38_SHIFT (16u) +#define INTC_ICDIPTR113_TINT39_SHIFT (24u) + +#define INTC_ICDIPTR114_TINT40_SHIFT (0u) +#define INTC_ICDIPTR114_TINT41_SHIFT (8u) +#define INTC_ICDIPTR114_TINT42_SHIFT (16u) +#define INTC_ICDIPTR114_TINT43_SHIFT (24u) + +#define INTC_ICDIPTR115_TINT44_SHIFT (0u) +#define INTC_ICDIPTR115_TINT45_SHIFT (8u) +#define INTC_ICDIPTR115_TINT46_SHIFT (16u) +#define INTC_ICDIPTR115_TINT47_SHIFT (24u) + +#define INTC_ICDIPTR116_TINT48_SHIFT (0u) +#define INTC_ICDIPTR116_TINT49_SHIFT (8u) +#define INTC_ICDIPTR116_TINT50_SHIFT (16u) +#define INTC_ICDIPTR116_TINT51_SHIFT (24u) + +#define INTC_ICDIPTR117_TINT52_SHIFT (0u) +#define INTC_ICDIPTR117_TINT53_SHIFT (8u) +#define INTC_ICDIPTR117_TINT54_SHIFT (16u) +#define INTC_ICDIPTR117_TINT55_SHIFT (24u) + +#define INTC_ICDIPTR118_TINT56_SHIFT (0u) +#define INTC_ICDIPTR118_TINT57_SHIFT (8u) +#define INTC_ICDIPTR118_TINT58_SHIFT (16u) +#define INTC_ICDIPTR118_TINT59_SHIFT (24u) + +#define INTC_ICDIPTR119_TINT60_SHIFT (0u) +#define INTC_ICDIPTR119_TINT61_SHIFT (8u) +#define INTC_ICDIPTR119_TINT62_SHIFT (16u) +#define INTC_ICDIPTR119_TINT63_SHIFT (24u) + +#define INTC_ICDIPTR120_TINT64_SHIFT (0u) +#define INTC_ICDIPTR120_TINT65_SHIFT (8u) +#define INTC_ICDIPTR120_TINT66_SHIFT (16u) +#define INTC_ICDIPTR120_TINT67_SHIFT (24u) + +#define INTC_ICDIPTR121_TINT68_SHIFT (0u) +#define INTC_ICDIPTR121_TINT69_SHIFT (8u) +#define INTC_ICDIPTR121_TINT70_SHIFT (16u) +#define INTC_ICDIPTR121_TINT71_SHIFT (24u) + +#define INTC_ICDIPTR122_TINT72_SHIFT (0u) +#define INTC_ICDIPTR122_TINT73_SHIFT (8u) +#define INTC_ICDIPTR122_TINT74_SHIFT (16u) +#define INTC_ICDIPTR122_TINT75_SHIFT (24u) + +#define INTC_ICDIPTR123_TINT76_SHIFT (0u) +#define INTC_ICDIPTR123_TINT77_SHIFT (8u) +#define INTC_ICDIPTR123_TINT78_SHIFT (16u) +#define INTC_ICDIPTR123_TINT79_SHIFT (24u) + +#define INTC_ICDIPTR124_TINT80_SHIFT (0u) +#define INTC_ICDIPTR124_TINT81_SHIFT (8u) +#define INTC_ICDIPTR124_TINT82_SHIFT (16u) +#define INTC_ICDIPTR124_TINT83_SHIFT (24u) + +#define INTC_ICDIPTR125_TINT84_SHIFT (0u) +#define INTC_ICDIPTR125_TINT85_SHIFT (8u) +#define INTC_ICDIPTR125_TINT86_SHIFT (16u) +#define INTC_ICDIPTR125_TINT87_SHIFT (24u) + +#define INTC_ICDIPTR126_TINT88_SHIFT (0u) +#define INTC_ICDIPTR126_TINT89_SHIFT (8u) +#define INTC_ICDIPTR126_TINT90_SHIFT (16u) +#define INTC_ICDIPTR126_TINT91_SHIFT (24u) + +#define INTC_ICDIPTR127_TINT92_SHIFT (0u) +#define INTC_ICDIPTR127_TINT93_SHIFT (8u) +#define INTC_ICDIPTR127_TINT94_SHIFT (16u) +#define INTC_ICDIPTR127_TINT95_SHIFT (24u) + +#define INTC_ICDIPTR128_TINT96_SHIFT (0u) +#define INTC_ICDIPTR128_TINT97_SHIFT (8u) +#define INTC_ICDIPTR128_TINT98_SHIFT (16u) +#define INTC_ICDIPTR128_TINT99_SHIFT (24u) + +#define INTC_ICDIPTR129_TINT100_SHIFT (0u) +#define INTC_ICDIPTR129_TINT101_SHIFT (8u) +#define INTC_ICDIPTR129_TINT102_SHIFT (16u) +#define INTC_ICDIPTR129_TINT103_SHIFT (24u) + +#define INTC_ICDIPTR130_TINT104_SHIFT (0u) +#define INTC_ICDIPTR130_TINT105_SHIFT (8u) +#define INTC_ICDIPTR130_TINT106_SHIFT (16u) +#define INTC_ICDIPTR130_TINT107_SHIFT (24u) + +#define INTC_ICDIPTR131_TINT108_SHIFT (0u) +#define INTC_ICDIPTR131_TINT109_SHIFT (8u) +#define INTC_ICDIPTR131_TINT110_SHIFT (16u) +#define INTC_ICDIPTR131_TINT111_SHIFT (24u) + +#define INTC_ICDIPTR132_TINT112_SHIFT (0u) +#define INTC_ICDIPTR132_TINT113_SHIFT (8u) +#define INTC_ICDIPTR132_TINT114_SHIFT (16u) +#define INTC_ICDIPTR132_TINT115_SHIFT (24u) + +#define INTC_ICDIPTR133_TINT116_SHIFT (0u) +#define INTC_ICDIPTR133_TINT117_SHIFT (8u) +#define INTC_ICDIPTR133_TINT118_SHIFT (16u) +#define INTC_ICDIPTR133_TINT119_SHIFT (24u) + +#define INTC_ICDIPTR134_TINT120_SHIFT (0u) +#define INTC_ICDIPTR134_TINT121_SHIFT (8u) +#define INTC_ICDIPTR134_TINT122_SHIFT (16u) +#define INTC_ICDIPTR134_TINT123_SHIFT (24u) + +#define INTC_ICDIPTR135_TINT124_SHIFT (0u) +#define INTC_ICDIPTR135_TINT125_SHIFT (8u) +#define INTC_ICDIPTR135_TINT126_SHIFT (16u) +#define INTC_ICDIPTR135_TINT127_SHIFT (24u) + +#define INTC_ICDIPTR136_TINT128_SHIFT (0u) +#define INTC_ICDIPTR136_TINT129_SHIFT (8u) +#define INTC_ICDIPTR136_TINT130_SHIFT (16u) +#define INTC_ICDIPTR136_TINT131_SHIFT (24u) + +#define INTC_ICDIPTR137_TINT132_SHIFT (0u) +#define INTC_ICDIPTR137_TINT133_SHIFT (8u) +#define INTC_ICDIPTR137_TINT134_SHIFT (16u) +#define INTC_ICDIPTR137_TINT135_SHIFT (24u) + +#define INTC_ICDIPTR138_TINT136_SHIFT (0u) +#define INTC_ICDIPTR138_TINT137_SHIFT (8u) +#define INTC_ICDIPTR138_TINT138_SHIFT (16u) +#define INTC_ICDIPTR138_TINT139_SHIFT (24u) + +#define INTC_ICDIPTR139_TINT140_SHIFT (0u) +#define INTC_ICDIPTR139_TINT141_SHIFT (8u) +#define INTC_ICDIPTR139_TINT142_SHIFT (16u) +#define INTC_ICDIPTR139_TINT143_SHIFT (24u) + +#define INTC_ICDIPTR140_TINT144_SHIFT (0u) +#define INTC_ICDIPTR140_TINT145_SHIFT (8u) +#define INTC_ICDIPTR140_TINT146_SHIFT (16u) +#define INTC_ICDIPTR140_TINT147_SHIFT (24u) + +#define INTC_ICDIPTR141_TINT148_SHIFT (0u) +#define INTC_ICDIPTR141_TINT149_SHIFT (8u) +#define INTC_ICDIPTR141_TINT150_SHIFT (16u) +#define INTC_ICDIPTR141_TINT151_SHIFT (24u) + +#define INTC_ICDIPTR142_TINT152_SHIFT (0u) +#define INTC_ICDIPTR142_TINT153_SHIFT (8u) +#define INTC_ICDIPTR142_TINT154_SHIFT (16u) +#define INTC_ICDIPTR142_TINT155_SHIFT (24u) + +#define INTC_ICDIPTR143_TINT156_SHIFT (0u) +#define INTC_ICDIPTR143_TINT157_SHIFT (8u) +#define INTC_ICDIPTR143_TINT158_SHIFT (16u) +#define INTC_ICDIPTR143_TINT159_SHIFT (24u) + +#define INTC_ICDIPTR144_TINT160_SHIFT (0u) +#define INTC_ICDIPTR144_TINT161_SHIFT (8u) +#define INTC_ICDIPTR144_TINT162_SHIFT (16u) +#define INTC_ICDIPTR144_TINT163_SHIFT (24u) + +#define INTC_ICDIPTR145_TINT164_SHIFT (0u) +#define INTC_ICDIPTR145_TINT165_SHIFT (8u) +#define INTC_ICDIPTR145_TINT166_SHIFT (16u) +#define INTC_ICDIPTR145_TINT167_SHIFT (24u) + +#define INTC_ICDIPTR146_TINT168_SHIFT (0u) +#define INTC_ICDIPTR146_TINT169_SHIFT (8u) +#define INTC_ICDIPTR146_TINT170_SHIFT (16u) + +#define INTC_ICDICFR0_SW0_0_SHIFT (0u) +#define INTC_ICDICFR0_SW0_1_SHIFT (1u) +#define INTC_ICDICFR0_SW1_0_SHIFT (2u) +#define INTC_ICDICFR0_SW1_1_SHIFT (3u) +#define INTC_ICDICFR0_SW2_0_SHIFT (4u) +#define INTC_ICDICFR0_SW2_1_SHIFT (5u) +#define INTC_ICDICFR0_SW3_0_SHIFT (6u) +#define INTC_ICDICFR0_SW3_1_SHIFT (7u) +#define INTC_ICDICFR0_SW4_0_SHIFT (8u) +#define INTC_ICDICFR0_SW4_1_SHIFT (9u) +#define INTC_ICDICFR0_SW5_0_SHIFT (10u) +#define INTC_ICDICFR0_SW5_1_SHIFT (11u) +#define INTC_ICDICFR0_SW6_0_SHIFT (12u) +#define INTC_ICDICFR0_SW6_1_SHIFT (13u) +#define INTC_ICDICFR0_SW7_0_SHIFT (14u) +#define INTC_ICDICFR0_SW7_1_SHIFT (15u) +#define INTC_ICDICFR0_SW8_0_SHIFT (16u) +#define INTC_ICDICFR0_SW8_1_SHIFT (17u) +#define INTC_ICDICFR0_SW9_0_SHIFT (18u) +#define INTC_ICDICFR0_SW9_1_SHIFT (19u) +#define INTC_ICDICFR0_SW10_0_SHIFT (20u) +#define INTC_ICDICFR0_SW10_1_SHIFT (21u) +#define INTC_ICDICFR0_SW11_0_SHIFT (22u) +#define INTC_ICDICFR0_SW11_1_SHIFT (23u) +#define INTC_ICDICFR0_SW12_0_SHIFT (24u) +#define INTC_ICDICFR0_SW12_1_SHIFT (25u) +#define INTC_ICDICFR0_SW13_0_SHIFT (26u) +#define INTC_ICDICFR0_SW13_1_SHIFT (27u) +#define INTC_ICDICFR0_SW14_0_SHIFT (28u) +#define INTC_ICDICFR0_SW14_1_SHIFT (29u) +#define INTC_ICDICFR0_SW15_0_SHIFT (30u) +#define INTC_ICDICFR0_SW15_1_SHIFT (31u) + +#define INTC_ICDICFR1_PMUIRQ0_0_SHIFT (0u) +#define INTC_ICDICFR1_PMUIRQ0_1_SHIFT (1u) +#define INTC_ICDICFR1_COMMRX0_0_SHIFT (2u) +#define INTC_ICDICFR1_COMMRX0_1_SHIFT (3u) +#define INTC_ICDICFR1_COMMTX0_0_SHIFT (4u) +#define INTC_ICDICFR1_COMMTX0_1_SHIFT (5u) +#define INTC_ICDICFR1_CTIIRQ0_0_SHIFT (6u) +#define INTC_ICDICFR1_CTIIRQ0_1_SHIFT (7u) + +#define INTC_ICDICFR2_IRQ0_0_SHIFT (0u) +#define INTC_ICDICFR2_IRQ0_1_SHIFT (1u) +#define INTC_ICDICFR2_IRQ1_0_SHIFT (2u) +#define INTC_ICDICFR2_IRQ1_1_SHIFT (3u) +#define INTC_ICDICFR2_IRQ2_0_SHIFT (4u) +#define INTC_ICDICFR2_IRQ2_1_SHIFT (5u) +#define INTC_ICDICFR2_IRQ3_0_SHIFT (6u) +#define INTC_ICDICFR2_IRQ3_1_SHIFT (7u) +#define INTC_ICDICFR2_IRQ4_0_SHIFT (8u) +#define INTC_ICDICFR2_IRQ4_1_SHIFT (9u) +#define INTC_ICDICFR2_IRQ5_0_SHIFT (10u) +#define INTC_ICDICFR2_IRQ5_1_SHIFT (11u) +#define INTC_ICDICFR2_IRQ6_0_SHIFT (12u) +#define INTC_ICDICFR2_IRQ6_1_SHIFT (13u) +#define INTC_ICDICFR2_IRQ7_0_SHIFT (14u) +#define INTC_ICDICFR2_IRQ7_1_SHIFT (15u) +#define INTC_ICDICFR2_PL310ERR_0_SHIFT (16u) +#define INTC_ICDICFR2_PL310ERR_1_SHIFT (17u) +#define INTC_ICDICFR2_DMAINT0_0_SHIFT (18u) +#define INTC_ICDICFR2_DMAINT0_1_SHIFT (19u) +#define INTC_ICDICFR2_DMAINT1_0_SHIFT (20u) +#define INTC_ICDICFR2_DMAINT1_1_SHIFT (21u) +#define INTC_ICDICFR2_DMAINT2_0_SHIFT (22u) +#define INTC_ICDICFR2_DMAINT2_1_SHIFT (23u) +#define INTC_ICDICFR2_DMAINT3_0_SHIFT (24u) +#define INTC_ICDICFR2_DMAINT3_1_SHIFT (25u) +#define INTC_ICDICFR2_DMAINT4_0_SHIFT (26u) +#define INTC_ICDICFR2_DMAINT4_1_SHIFT (27u) +#define INTC_ICDICFR2_DMAINT5_0_SHIFT (28u) +#define INTC_ICDICFR2_DMAINT5_1_SHIFT (29u) +#define INTC_ICDICFR2_DMAINT6_0_SHIFT (30u) +#define INTC_ICDICFR2_DMAINT6_1_SHIFT (31u) + +#define INTC_ICDICFR3_DMAINT7_0_SHIFT (0u) +#define INTC_ICDICFR3_DMAINT7_1_SHIFT (1u) +#define INTC_ICDICFR3_DMAINT8_0_SHIFT (2u) +#define INTC_ICDICFR3_DMAINT8_1_SHIFT (3u) +#define INTC_ICDICFR3_DMAINT9_0_SHIFT (4u) +#define INTC_ICDICFR3_DMAINT9_1_SHIFT (5u) +#define INTC_ICDICFR3_DMAINT10_0_SHIFT (6u) +#define INTC_ICDICFR3_DMAINT10_1_SHIFT (7u) +#define INTC_ICDICFR3_DMAINT11_0_SHIFT (8u) +#define INTC_ICDICFR3_DMAINT11_1_SHIFT (9u) +#define INTC_ICDICFR3_DMAINT12_0_SHIFT (10u) +#define INTC_ICDICFR3_DMAINT12_1_SHIFT (11u) +#define INTC_ICDICFR3_DMAINT13_0_SHIFT (12u) +#define INTC_ICDICFR3_DMAINT13_1_SHIFT (13u) +#define INTC_ICDICFR3_DMAINT14_0_SHIFT (14u) +#define INTC_ICDICFR3_DMAINT14_1_SHIFT (15u) +#define INTC_ICDICFR3_DMAINT15_0_SHIFT (16u) +#define INTC_ICDICFR3_DMAINT15_1_SHIFT (17u) +#define INTC_ICDICFR3_DMAERR_0_SHIFT (18u) +#define INTC_ICDICFR3_DMAERR_1_SHIFT (19u) + +#define INTC_ICDICFR4_USBI0_0_SHIFT (18u) +#define INTC_ICDICFR4_USBI0_1_SHIFT (19u) +#define INTC_ICDICFR4_USBI1_0_SHIFT (20u) +#define INTC_ICDICFR4_USBI1_1_SHIFT (21u) +#define INTC_ICDICFR4_S0_VI_VSYNC0_0_SHIFT (22u) +#define INTC_ICDICFR4_S0_VI_VSYNC0_1_SHIFT (23u) +#define INTC_ICDICFR4_S0_LO_VSYNC0_0_SHIFT (24u) +#define INTC_ICDICFR4_S0_LO_VSYNC0_1_SHIFT (25u) +#define INTC_ICDICFR4_S0_VSYNCERR0_0_SHIFT (26u) +#define INTC_ICDICFR4_S0_VSYNCERR0_1_SHIFT (27u) +#define INTC_ICDICFR4_GR3_VLINE0_0_SHIFT (28u) +#define INTC_ICDICFR4_GR3_VLINE0_1_SHIFT (29u) +#define INTC_ICDICFR4_S0_VFIELD0_0_SHIFT (30u) +#define INTC_ICDICFR4_S0_VFIELD0_1_SHIFT (31u) + +#define INTC_ICDICFR5_IV1_VBUFERR0_0_SHIFT (0u) +#define INTC_ICDICFR5_IV1_VBUFERR0_1_SHIFT (1u) +#define INTC_ICDICFR5_IV3_VBUFERR0_0_SHIFT (2u) +#define INTC_ICDICFR5_IV3_VBUFERR0_1_SHIFT (3u) +#define INTC_ICDICFR5_IV5_VBUFERR0_0_SHIFT (4u) +#define INTC_ICDICFR5_IV5_VBUFERR0_1_SHIFT (5u) +#define INTC_ICDICFR5_IV6_VBUFERR0_0_SHIFT (6u) +#define INTC_ICDICFR5_IV6_VBUFERR0_1_SHIFT (7u) +#define INTC_ICDICFR5_S0_WLINE0_0_SHIFT (8u) +#define INTC_ICDICFR5_S0_WLINE0_1_SHIFT (9u) +#define INTC_ICDICFR5_S1_VI_VSYNC0_0_SHIFT (10u) +#define INTC_ICDICFR5_S1_VI_VSYNC0_1_SHIFT (11u) +#define INTC_ICDICFR5_S1_LO_VSYNC0_0_SHIFT (12u) +#define INTC_ICDICFR5_S1_LO_VSYNC0_1_SHIFT (13u) +#define INTC_ICDICFR5_S1_VSYNCERR0_0_SHIFT (14u) +#define INTC_ICDICFR5_S1_VSYNCERR0_1_SHIFT (15u) +#define INTC_ICDICFR5_S1_VFIELD0_0_SHIFT (16u) +#define INTC_ICDICFR5_S1_VFIELD0_1_SHIFT (17u) +#define INTC_ICDICFR5_IV2_VBUFERR0_0_SHIFT (18u) +#define INTC_ICDICFR5_IV2_VBUFERR0_1_SHIFT (19u) +#define INTC_ICDICFR5_IV4_VBUFERR0_0_SHIFT (20u) +#define INTC_ICDICFR5_IV4_VBUFERR0_1_SHIFT (21u) +#define INTC_ICDICFR5_S1_WLINE0_0_SHIFT (22u) +#define INTC_ICDICFR5_S1_WLINE0_1_SHIFT (23u) +#define INTC_ICDICFR5_OIR_VI_VSYNC0_0_SHIFT (24u) +#define INTC_ICDICFR5_OIR_VI_VSYNC0_1_SHIFT (25u) +#define INTC_ICDICFR5_OIR_LO_VSYNC0_0_SHIFT (26u) +#define INTC_ICDICFR5_OIR_LO_VSYNC0_1_SHIFT (27u) +#define INTC_ICDICFR5_OIR_VSYNCERR0_0_SHIFT (28u) +#define INTC_ICDICFR5_OIR_VSYNCERR0_1_SHIFT (29u) +#define INTC_ICDICFR5_OIR_VFIELD0_0_SHIFT (30u) +#define INTC_ICDICFR5_OIR_VFIELD0_1_SHIFT (31u) + +#define INTC_ICDICFR6_IV7_VBUFERR0_0_SHIFT (0u) +#define INTC_ICDICFR6_IV7_VBUFERR0_1_SHIFT (1u) +#define INTC_ICDICFR6_IV8_VBUFERR0_0_SHIFT (2u) +#define INTC_ICDICFR6_IV8_VBUFERR0_1_SHIFT (3u) +#define INTC_ICDICFR6_S0_VI_VSYNC1_0_SHIFT (6u) +#define INTC_ICDICFR6_S0_VI_VSYNC1_1_SHIFT (7u) +#define INTC_ICDICFR6_S0_LO_VSYNC1_0_SHIFT (8u) +#define INTC_ICDICFR6_S0_LO_VSYNC1_1_SHIFT (9u) +#define INTC_ICDICFR6_S0_VSYNCERR1_0_SHIFT (10u) +#define INTC_ICDICFR6_S0_VSYNCERR1_1_SHIFT (11u) +#define INTC_ICDICFR6_GR3_VLINE1_0_SHIFT (12u) +#define INTC_ICDICFR6_GR3_VLINE1_1_SHIFT (13u) +#define INTC_ICDICFR6_S0_VFIELD1_0_SHIFT (14u) +#define INTC_ICDICFR6_S0_VFIELD1_1_SHIFT (15u) +#define INTC_ICDICFR6_IV1_VBUFERR1_0_SHIFT (16u) +#define INTC_ICDICFR6_IV1_VBUFERR1_1_SHIFT (17u) +#define INTC_ICDICFR6_IV3_VBUFERR1_0_SHIFT (18u) +#define INTC_ICDICFR6_IV3_VBUFERR1_1_SHIFT (19u) +#define INTC_ICDICFR6_IV5_VBUFERR1_0_SHIFT (20u) +#define INTC_ICDICFR6_IV5_VBUFERR1_1_SHIFT (21u) +#define INTC_ICDICFR6_IV6_VBUFERR1_0_SHIFT (22u) +#define INTC_ICDICFR6_IV6_VBUFERR1_1_SHIFT (23u) +#define INTC_ICDICFR6_S0_WLINE1_0_SHIFT (24u) +#define INTC_ICDICFR6_S0_WLINE1_1_SHIFT (25u) +#define INTC_ICDICFR6_S1_VI_VSYNC1_0_SHIFT (26u) +#define INTC_ICDICFR6_S1_VI_VSYNC1_1_SHIFT (27u) +#define INTC_ICDICFR6_S1_LO_VSYNC1_0_SHIFT (28u) +#define INTC_ICDICFR6_S1_LO_VSYNC1_1_SHIFT (29u) +#define INTC_ICDICFR6_S1_VSYNCERR1_0_SHIFT (30u) +#define INTC_ICDICFR6_S1_VSYNCERR1_1_SHIFT (31u) + +#define INTC_ICDICFR7_S1_VFIELD1_0_SHIFT (0u) +#define INTC_ICDICFR7_S1_VFIELD1_1_SHIFT (1u) +#define INTC_ICDICFR7_IV2_VBUFERR1_0_SHIFT (2u) +#define INTC_ICDICFR7_IV2_VBUFERR1_1_SHIFT (3u) +#define INTC_ICDICFR7_IV4_VBUFERR1_0_SHIFT (4u) +#define INTC_ICDICFR7_IV4_VBUFERR1_1_SHIFT (5u) +#define INTC_ICDICFR7_S1_WLINE1_0_SHIFT (6u) +#define INTC_ICDICFR7_S1_WLINE1_1_SHIFT (7u) +#define INTC_ICDICFR7_OIR_VI_VSYNC1_0_SHIFT (8u) +#define INTC_ICDICFR7_OIR_VI_VSYNC1_1_SHIFT (9u) +#define INTC_ICDICFR7_OIR_LO_VSYNC1_0_SHIFT (10u) +#define INTC_ICDICFR7_OIR_LO_VSYNC1_1_SHIFT (11u) +#define INTC_ICDICFR7_OIR_VLINE1_0_SHIFT (12u) +#define INTC_ICDICFR7_OIR_VLINE1_1_SHIFT (13u) +#define INTC_ICDICFR7_OIR_VFIELD1_0_SHIFT (14u) +#define INTC_ICDICFR7_OIR_VFIELD1_1_SHIFT (15u) +#define INTC_ICDICFR7_IV7_VBUFERR1_0_SHIFT (16u) +#define INTC_ICDICFR7_IV7_VBUFERR1_1_SHIFT (17u) +#define INTC_ICDICFR7_IV8_VBUFERR1_0_SHIFT (18u) +#define INTC_ICDICFR7_IV8_VBUFERR1_1_SHIFT (19u) +#define INTC_ICDICFR7_IMRDI_0_SHIFT (22u) +#define INTC_ICDICFR7_IMRDI_1_SHIFT (23u) +#define INTC_ICDICFR7_IMR2I0_0_SHIFT (24u) +#define INTC_ICDICFR7_IMR2I0_1_SHIFT (25u) +#define INTC_ICDICFR7_IMR2I1_0_SHIFT (26u) +#define INTC_ICDICFR7_IMR2I1_1_SHIFT (27u) +#define INTC_ICDICFR7_JEDI_0_SHIFT (28u) +#define INTC_ICDICFR7_JEDI_1_SHIFT (29u) +#define INTC_ICDICFR7_JDTI_0_SHIFT (30u) +#define INTC_ICDICFR7_JDTI_1_SHIFT (31u) + +#define INTC_ICDICFR8_CMP0_0_SHIFT (0u) +#define INTC_ICDICFR8_CMP0_1_SHIFT (1u) +#define INTC_ICDICFR8_CMP1_0_SHIFT (2u) +#define INTC_ICDICFR8_CMP1_1_SHIFT (3u) +#define INTC_ICDICFR8_INT0_0_SHIFT (4u) +#define INTC_ICDICFR8_INT0_1_SHIFT (5u) +#define INTC_ICDICFR8_INT1_0_SHIFT (6u) +#define INTC_ICDICFR8_INT1_1_SHIFT (7u) +#define INTC_ICDICFR8_INT2_0_SHIFT (8u) +#define INTC_ICDICFR8_INT2_1_SHIFT (9u) +#define INTC_ICDICFR8_INT3_0_SHIFT (10u) +#define INTC_ICDICFR8_INT3_1_SHIFT (11u) +#define INTC_ICDICFR8_OSTM0TINT_0_SHIFT (12u) +#define INTC_ICDICFR8_OSTM0TINT_1_SHIFT (13u) +#define INTC_ICDICFR8_OSTM1TINT_0_SHIFT (14u) +#define INTC_ICDICFR8_OSTM1TINT_1_SHIFT (15u) +#define INTC_ICDICFR8_CMI_0_SHIFT (16u) +#define INTC_ICDICFR8_CMI_1_SHIFT (17u) +#define INTC_ICDICFR8_WTOUT_0_SHIFT (18u) +#define INTC_ICDICFR8_WTOUT_1_SHIFT (19u) +#define INTC_ICDICFR8_ITI_0_SHIFT (20u) +#define INTC_ICDICFR8_ITI_1_SHIFT (21u) +#define INTC_ICDICFR8_TGI0A_0_SHIFT (22u) +#define INTC_ICDICFR8_TGI0A_1_SHIFT (23u) +#define INTC_ICDICFR8_TGI0B_0_SHIFT (24u) +#define INTC_ICDICFR8_TGI0B_1_SHIFT (25u) +#define INTC_ICDICFR8_TGI0C_0_SHIFT (26u) +#define INTC_ICDICFR8_TGI0C_1_SHIFT (27u) +#define INTC_ICDICFR8_TGI0D_0_SHIFT (28u) +#define INTC_ICDICFR8_TGI0D_1_SHIFT (29u) +#define INTC_ICDICFR8_TGI0V_0_SHIFT (30u) +#define INTC_ICDICFR8_TGI0V_1_SHIFT (31u) + +#define INTC_ICDICFR9_TGI0E_0_SHIFT (0u) +#define INTC_ICDICFR9_TGI0E_1_SHIFT (1u) +#define INTC_ICDICFR9_TGI0F_0_SHIFT (2u) +#define INTC_ICDICFR9_TGI0F_1_SHIFT (3u) +#define INTC_ICDICFR9_TGI1A_0_SHIFT (4u) +#define INTC_ICDICFR9_TGI1A_1_SHIFT (5u) +#define INTC_ICDICFR9_TGI1B_0_SHIFT (6u) +#define INTC_ICDICFR9_TGI1B_1_SHIFT (7u) +#define INTC_ICDICFR9_TGI1V_0_SHIFT (8u) +#define INTC_ICDICFR9_TGI1V_1_SHIFT (9u) +#define INTC_ICDICFR9_TGI1U_0_SHIFT (10u) +#define INTC_ICDICFR9_TGI1U_1_SHIFT (11u) +#define INTC_ICDICFR9_TGI2A_0_SHIFT (12u) +#define INTC_ICDICFR9_TGI2A_1_SHIFT (13u) +#define INTC_ICDICFR9_TGI2B_0_SHIFT (14u) +#define INTC_ICDICFR9_TGI2B_1_SHIFT (15u) +#define INTC_ICDICFR9_TGI2V_0_SHIFT (16u) +#define INTC_ICDICFR9_TGI2V_1_SHIFT (17u) +#define INTC_ICDICFR9_TGI2U_0_SHIFT (18u) +#define INTC_ICDICFR9_TGI2U_1_SHIFT (19u) +#define INTC_ICDICFR9_TGI3A_0_SHIFT (20u) +#define INTC_ICDICFR9_TGI3A_1_SHIFT (21u) +#define INTC_ICDICFR9_TGI3B_0_SHIFT (22u) +#define INTC_ICDICFR9_TGI3B_1_SHIFT (23u) +#define INTC_ICDICFR9_TGI3C_0_SHIFT (24u) +#define INTC_ICDICFR9_TGI3C_1_SHIFT (25u) +#define INTC_ICDICFR9_TGI3D_0_SHIFT (26u) +#define INTC_ICDICFR9_TGI3D_1_SHIFT (27u) +#define INTC_ICDICFR9_TGI3V_0_SHIFT (28u) +#define INTC_ICDICFR9_TGI3V_1_SHIFT (29u) +#define INTC_ICDICFR9_TGI4A_0_SHIFT (30u) +#define INTC_ICDICFR9_TGI4A_1_SHIFT (31u) + +#define INTC_ICDICFR10_TGI4B_0_SHIFT (0u) +#define INTC_ICDICFR10_TGI4B_1_SHIFT (1u) +#define INTC_ICDICFR10_TGI4C_0_SHIFT (2u) +#define INTC_ICDICFR10_TGI4C_1_SHIFT (3u) +#define INTC_ICDICFR10_TGI4D_0_SHIFT (4u) +#define INTC_ICDICFR10_TGI4D_1_SHIFT (5u) +#define INTC_ICDICFR10_TGI4V_0_SHIFT (6u) +#define INTC_ICDICFR10_TGI4V_1_SHIFT (7u) +#define INTC_ICDICFR10_CMI1_0_SHIFT (8u) +#define INTC_ICDICFR10_CMI1_1_SHIFT (9u) +#define INTC_ICDICFR10_CMI2_0_SHIFT (10u) +#define INTC_ICDICFR10_CMI2_1_SHIFT (11u) +#define INTC_ICDICFR10_SGDEI0_0_SHIFT (12u) +#define INTC_ICDICFR10_SGDEI0_1_SHIFT (13u) +#define INTC_ICDICFR10_SGDEI1_0_SHIFT (14u) +#define INTC_ICDICFR10_SGDEI1_1_SHIFT (15u) +#define INTC_ICDICFR10_SGDEI2_0_SHIFT (16u) +#define INTC_ICDICFR10_SGDEI2_1_SHIFT (17u) +#define INTC_ICDICFR10_SGDEI3_0_SHIFT (18u) +#define INTC_ICDICFR10_SGDEI3_1_SHIFT (19u) +#define INTC_ICDICFR10_ADI_0_SHIFT (20u) +#define INTC_ICDICFR10_ADI_1_SHIFT (21u) +#define INTC_ICDICFR10_LMTI_0_SHIFT (22u) +#define INTC_ICDICFR10_LMTI_1_SHIFT (23u) +#define INTC_ICDICFR10_SSII0_0_SHIFT (24u) +#define INTC_ICDICFR10_SSII0_1_SHIFT (25u) +#define INTC_ICDICFR10_SSIRXI0_0_SHIFT (26u) +#define INTC_ICDICFR10_SSIRXI0_1_SHIFT (27u) +#define INTC_ICDICFR10_SSITXI0_0_SHIFT (28u) +#define INTC_ICDICFR10_SSITXI0_1_SHIFT (29u) +#define INTC_ICDICFR10_SSII1_0_SHIFT (30u) +#define INTC_ICDICFR10_SSII1_1_SHIFT (31u) + +#define INTC_ICDICFR11_SSIRXI1_0_SHIFT (0u) +#define INTC_ICDICFR11_SSIRXI1_1_SHIFT (1u) +#define INTC_ICDICFR11_SSITXI1_0_SHIFT (2u) +#define INTC_ICDICFR11_SSITXI1_1_SHIFT (3u) +#define INTC_ICDICFR11_SSII2_0_SHIFT (4u) +#define INTC_ICDICFR11_SSII2_1_SHIFT (5u) +#define INTC_ICDICFR11_SSIRTI2_0_SHIFT (6u) +#define INTC_ICDICFR11_SSIRTI2_1_SHIFT (7u) +#define INTC_ICDICFR11_SSII3_0_SHIFT (8u) +#define INTC_ICDICFR11_SSII3_1_SHIFT (9u) +#define INTC_ICDICFR11_SSIRXI3_0_SHIFT (10u) +#define INTC_ICDICFR11_SSIRXI3_1_SHIFT (11u) +#define INTC_ICDICFR11_SSITXI3_0_SHIFT (12u) +#define INTC_ICDICFR11_SSITXI3_1_SHIFT (13u) +#define INTC_ICDICFR11_SSII4_0_SHIFT (14u) +#define INTC_ICDICFR11_SSII4_1_SHIFT (15u) +#define INTC_ICDICFR11_SSIRTI4_0_SHIFT (16u) +#define INTC_ICDICFR11_SSIRTI4_1_SHIFT (17u) +#define INTC_ICDICFR11_SSII5_0_SHIFT (18u) +#define INTC_ICDICFR11_SSII5_1_SHIFT (19u) +#define INTC_ICDICFR11_SSIRXI5_0_SHIFT (20u) +#define INTC_ICDICFR11_SSIRXI5_1_SHIFT (21u) +#define INTC_ICDICFR11_SSITXI5_0_SHIFT (22u) +#define INTC_ICDICFR11_SSITXI5_1_SHIFT (23u) +#define INTC_ICDICFR11_SPDIFI_0_SHIFT (24u) +#define INTC_ICDICFR11_SPDIFI_1_SHIFT (25u) +#define INTC_ICDICFR11_INTIICTEI0_0_SHIFT (26u) +#define INTC_ICDICFR11_INTIICTEI0_1_SHIFT (27u) +#define INTC_ICDICFR11_INTIICRI0_0_SHIFT (28u) +#define INTC_ICDICFR11_INTIICRI0_1_SHIFT (29u) +#define INTC_ICDICFR11_INTIICTI0_0_SHIFT (30u) +#define INTC_ICDICFR11_INTIICTI0_1_SHIFT (31u) + +#define INTC_ICDICFR12_INTIICSPI0_0_SHIFT (0u) +#define INTC_ICDICFR12_INTIICSPI0_1_SHIFT (1u) +#define INTC_ICDICFR12_INTIICSTI0_0_SHIFT (2u) +#define INTC_ICDICFR12_INTIICSTI0_1_SHIFT (3u) +#define INTC_ICDICFR12_INTIICNAKI0_0_SHIFT (4u) +#define INTC_ICDICFR12_INTIICNAKI0_1_SHIFT (5u) +#define INTC_ICDICFR12_INTIICALI0_0_SHIFT (6u) +#define INTC_ICDICFR12_INTIICALI0_1_SHIFT (7u) +#define INTC_ICDICFR12_INTIICTMOI0_0_SHIFT (8u) +#define INTC_ICDICFR12_INTIICTMOI0_1_SHIFT (9u) +#define INTC_ICDICFR12_INTIICTEI1_0_SHIFT (10u) +#define INTC_ICDICFR12_INTIICTEI1_1_SHIFT (11u) +#define INTC_ICDICFR12_INTIICRI1_0_SHIFT (12u) +#define INTC_ICDICFR12_INTIICRI1_1_SHIFT (13u) +#define INTC_ICDICFR12_INTIICTI1_0_SHIFT (14u) +#define INTC_ICDICFR12_INTIICTI1_1_SHIFT (15u) +#define INTC_ICDICFR12_INTIICSPI1_0_SHIFT (16u) +#define INTC_ICDICFR12_INTIICSPI1_1_SHIFT (17u) +#define INTC_ICDICFR12_INTIICSTI1_0_SHIFT (18u) +#define INTC_ICDICFR12_INTIICSTI1_1_SHIFT (19u) +#define INTC_ICDICFR12_INTIICNAKI1_0_SHIFT (20u) +#define INTC_ICDICFR12_INTIICNAKI1_1_SHIFT (21u) +#define INTC_ICDICFR12_INTIICALI1_0_SHIFT (22u) +#define INTC_ICDICFR12_INTIICALI1_1_SHIFT (23u) +#define INTC_ICDICFR12_INTIICTMOI1_0_SHIFT (24u) +#define INTC_ICDICFR12_INTIICTMOI1_1_SHIFT (25u) +#define INTC_ICDICFR12_INTIICTEI2_0_SHIFT (26u) +#define INTC_ICDICFR12_INTIICTEI2_1_SHIFT (27u) +#define INTC_ICDICFR12_INTIICRI2_0_SHIFT (28u) +#define INTC_ICDICFR12_INTIICRI2_1_SHIFT (29u) +#define INTC_ICDICFR12_INTIICTI2_0_SHIFT (30u) +#define INTC_ICDICFR12_INTIICTI2_1_SHIFT (31u) + +#define INTC_ICDICFR13_INTIICSPI2_0_SHIFT (0u) +#define INTC_ICDICFR13_INTIICSPI2_1_SHIFT (1u) +#define INTC_ICDICFR13_INTIICSTI2_0_SHIFT (2u) +#define INTC_ICDICFR13_INTIICSTI2_1_SHIFT (3u) +#define INTC_ICDICFR13_INTIICNAKI2_0_SHIFT (4u) +#define INTC_ICDICFR13_INTIICNAKI2_1_SHIFT (5u) +#define INTC_ICDICFR13_INTIICALI2_0_SHIFT (6u) +#define INTC_ICDICFR13_INTIICALI2_1_SHIFT (7u) +#define INTC_ICDICFR13_INTIICTMOI2_0_SHIFT (8u) +#define INTC_ICDICFR13_INTIICTMOI2_1_SHIFT (9u) +#define INTC_ICDICFR13_INTIICTEI3_0_SHIFT (10u) +#define INTC_ICDICFR13_INTIICTEI3_1_SHIFT (11u) +#define INTC_ICDICFR13_INTIICRI3_0_SHIFT (12u) +#define INTC_ICDICFR13_INTIICRI3_1_SHIFT (13u) +#define INTC_ICDICFR13_INTIICTI3_0_SHIFT (14u) +#define INTC_ICDICFR13_INTIICTI3_1_SHIFT (15u) +#define INTC_ICDICFR13_INTIICSPI3_0_SHIFT (16u) +#define INTC_ICDICFR13_INTIICSPI3_1_SHIFT (17u) +#define INTC_ICDICFR13_INTIICSTI3_0_SHIFT (18u) +#define INTC_ICDICFR13_INTIICSTI3_1_SHIFT (19u) +#define INTC_ICDICFR13_INTIICNAKI3_0_SHIFT (20u) +#define INTC_ICDICFR13_INTIICNAKI3_1_SHIFT (21u) +#define INTC_ICDICFR13_INTIICALI3_0_SHIFT (22u) +#define INTC_ICDICFR13_INTIICALI3_1_SHIFT (23u) +#define INTC_ICDICFR13_INTIICTMOI3_0_SHIFT (24u) +#define INTC_ICDICFR13_INTIICTMOI3_1_SHIFT (25u) +#define INTC_ICDICFR13_BRI0_0_SHIFT (26u) +#define INTC_ICDICFR13_BRI0_1_SHIFT (27u) +#define INTC_ICDICFR13_ERI0_0_SHIFT (28u) +#define INTC_ICDICFR13_ERI0_1_SHIFT (29u) +#define INTC_ICDICFR13_RXI0_0_SHIFT (30u) +#define INTC_ICDICFR13_RXI0_1_SHIFT (31u) + +#define INTC_ICDICFR14_TXI0_0_SHIFT (0u) +#define INTC_ICDICFR14_TXI0_1_SHIFT (1u) +#define INTC_ICDICFR14_BRI1_0_SHIFT (2u) +#define INTC_ICDICFR14_BRI1_1_SHIFT (3u) +#define INTC_ICDICFR14_ERI1_0_SHIFT (4u) +#define INTC_ICDICFR14_ERI1_1_SHIFT (5u) +#define INTC_ICDICFR14_RXI1_0_SHIFT (6u) +#define INTC_ICDICFR14_RXI1_1_SHIFT (7u) +#define INTC_ICDICFR14_TXI1_0_SHIFT (8u) +#define INTC_ICDICFR14_TXI1_1_SHIFT (9u) +#define INTC_ICDICFR14_BRI2_0_SHIFT (10u) +#define INTC_ICDICFR14_BRI2_1_SHIFT (11u) +#define INTC_ICDICFR14_ERI2_0_SHIFT (12u) +#define INTC_ICDICFR14_ERI2_1_SHIFT (13u) +#define INTC_ICDICFR14_RXI2_0_SHIFT (14u) +#define INTC_ICDICFR14_RXI2_1_SHIFT (15u) +#define INTC_ICDICFR14_TXI2_0_SHIFT (16u) +#define INTC_ICDICFR14_TXI2_1_SHIFT (17u) +#define INTC_ICDICFR14_BRI3_0_SHIFT (18u) +#define INTC_ICDICFR14_BRI3_1_SHIFT (19u) +#define INTC_ICDICFR14_ERI3_0_SHIFT (20u) +#define INTC_ICDICFR14_ERI3_1_SHIFT (21u) +#define INTC_ICDICFR14_RXI3_0_SHIFT (22u) +#define INTC_ICDICFR14_RXI3_1_SHIFT (23u) +#define INTC_ICDICFR14_TXI3_0_SHIFT (24u) +#define INTC_ICDICFR14_TXI3_1_SHIFT (25u) +#define INTC_ICDICFR14_BRI4_0_SHIFT (26u) +#define INTC_ICDICFR14_BRI4_1_SHIFT (27u) +#define INTC_ICDICFR14_ERI4_0_SHIFT (28u) +#define INTC_ICDICFR14_ERI4_1_SHIFT (29u) +#define INTC_ICDICFR14_RXI4_0_SHIFT (30u) +#define INTC_ICDICFR14_RXI4_1_SHIFT (31u) + +#define INTC_ICDICFR15_TXI4_0_SHIFT (0u) +#define INTC_ICDICFR15_TXI4_1_SHIFT (1u) +#define INTC_ICDICFR15_BRI5_0_SHIFT (2u) +#define INTC_ICDICFR15_BRI5_1_SHIFT (3u) +#define INTC_ICDICFR15_ERI5_0_SHIFT (4u) +#define INTC_ICDICFR15_ERI5_1_SHIFT (5u) +#define INTC_ICDICFR15_RXI5_0_SHIFT (6u) +#define INTC_ICDICFR15_RXI5_1_SHIFT (7u) +#define INTC_ICDICFR15_TXI5_0_SHIFT (8u) +#define INTC_ICDICFR15_TXI5_1_SHIFT (9u) +#define INTC_ICDICFR15_BRI6_0_SHIFT (10u) +#define INTC_ICDICFR15_BRI6_1_SHIFT (11u) +#define INTC_ICDICFR15_ERI6_0_SHIFT (12u) +#define INTC_ICDICFR15_ERI6_1_SHIFT (13u) +#define INTC_ICDICFR15_RXI6_0_SHIFT (14u) +#define INTC_ICDICFR15_RXI6_1_SHIFT (15u) +#define INTC_ICDICFR15_TXI6_0_SHIFT (16u) +#define INTC_ICDICFR15_TXI6_1_SHIFT (17u) +#define INTC_ICDICFR15_BRI7_0_SHIFT (18u) +#define INTC_ICDICFR15_BRI7_1_SHIFT (19u) +#define INTC_ICDICFR15_ERI7_0_SHIFT (20u) +#define INTC_ICDICFR15_ERI7_1_SHIFT (21u) +#define INTC_ICDICFR15_RXI7_0_SHIFT (22u) +#define INTC_ICDICFR15_RXI7_1_SHIFT (23u) +#define INTC_ICDICFR15_TXI7_0_SHIFT (24u) +#define INTC_ICDICFR15_TXI7_1_SHIFT (25u) +#define INTC_ICDICFR15_INTRCANGERR_0_SHIFT (26u) +#define INTC_ICDICFR15_INTRCANGERR_1_SHIFT (27u) +#define INTC_ICDICFR15_INTRCANGRECC_0_SHIFT (28u) +#define INTC_ICDICFR15_INTRCANGRECC_1_SHIFT (29u) +#define INTC_ICDICFR15_INTRCAN0REC_0_SHIFT (30u) +#define INTC_ICDICFR15_INTRCAN0REC_1_SHIFT (31u) + +#define INTC_ICDICFR16_INTRCAN0ERR_0_SHIFT (0u) +#define INTC_ICDICFR16_INTRCAN0ERR_1_SHIFT (1u) +#define INTC_ICDICFR16_INTRCAN0TRX_0_SHIFT (2u) +#define INTC_ICDICFR16_INTRCAN0TRX_1_SHIFT (3u) +#define INTC_ICDICFR16_INTRCAN1REC_0_SHIFT (4u) +#define INTC_ICDICFR16_INTRCAN1REC_1_SHIFT (5u) +#define INTC_ICDICFR16_INTRCAN1ERR_0_SHIFT (6u) +#define INTC_ICDICFR16_INTRCAN1ERR_1_SHIFT (7u) +#define INTC_ICDICFR16_INTRCAN1TRX_0_SHIFT (8u) +#define INTC_ICDICFR16_INTRCAN1TRX_1_SHIFT (9u) +#define INTC_ICDICFR16_INTRCAN2REC_0_SHIFT (10u) +#define INTC_ICDICFR16_INTRCAN2REC_1_SHIFT (11u) +#define INTC_ICDICFR16_INTRCAN2ERR_0_SHIFT (12u) +#define INTC_ICDICFR16_INTRCAN2ERR_1_SHIFT (13u) +#define INTC_ICDICFR16_INTRCAN2TRX_0_SHIFT (14u) +#define INTC_ICDICFR16_INTRCAN2TRX_1_SHIFT (15u) +#define INTC_ICDICFR16_INTRCAN3REC_0_SHIFT (16u) +#define INTC_ICDICFR16_INTRCAN3REC_1_SHIFT (17u) +#define INTC_ICDICFR16_INTRCAN3ERR_0_SHIFT (18u) +#define INTC_ICDICFR16_INTRCAN3ERR_1_SHIFT (19u) +#define INTC_ICDICFR16_INTRCAN3TRX_0_SHIFT (20u) +#define INTC_ICDICFR16_INTRCAN3TRX_1_SHIFT (21u) +#define INTC_ICDICFR16_INTRCAN4REC_0_SHIFT (22u) +#define INTC_ICDICFR16_INTRCAN4REC_1_SHIFT (23u) +#define INTC_ICDICFR16_INTRCAN4ERR_0_SHIFT (24u) +#define INTC_ICDICFR16_INTRCAN4ERR_1_SHIFT (25u) +#define INTC_ICDICFR16_INTRCAN4TRX_0_SHIFT (26u) +#define INTC_ICDICFR16_INTRCAN4TRX_1_SHIFT (27u) +#define INTC_ICDICFR16_SPEI0_0_SHIFT (28u) +#define INTC_ICDICFR16_SPEI0_1_SHIFT (29u) +#define INTC_ICDICFR16_SPRI0_0_SHIFT (30u) +#define INTC_ICDICFR16_SPRI0_1_SHIFT (31u) + +#define INTC_ICDICFR17_SPTI0_0_SHIFT (0u) +#define INTC_ICDICFR17_SPTI0_1_SHIFT (1u) +#define INTC_ICDICFR17_SPEI1_0_SHIFT (2u) +#define INTC_ICDICFR17_SPEI1_1_SHIFT (3u) +#define INTC_ICDICFR17_SPRI1_0_SHIFT (4u) +#define INTC_ICDICFR17_SPRI1_1_SHIFT (5u) +#define INTC_ICDICFR17_SPTI1_0_SHIFT (6u) +#define INTC_ICDICFR17_SPTI1_1_SHIFT (7u) +#define INTC_ICDICFR17_SPEI2_0_SHIFT (8u) +#define INTC_ICDICFR17_SPEI2_1_SHIFT (9u) +#define INTC_ICDICFR17_SPRI2_0_SHIFT (10u) +#define INTC_ICDICFR17_SPRI2_1_SHIFT (11u) +#define INTC_ICDICFR17_SPTI2_0_SHIFT (12u) +#define INTC_ICDICFR17_SPTI2_1_SHIFT (13u) +#define INTC_ICDICFR17_SPEI3_0_SHIFT (14u) +#define INTC_ICDICFR17_SPEI3_1_SHIFT (15u) +#define INTC_ICDICFR17_SPRI3_0_SHIFT (16u) +#define INTC_ICDICFR17_SPRI3_1_SHIFT (17u) +#define INTC_ICDICFR17_SPTI3_0_SHIFT (18u) +#define INTC_ICDICFR17_SPTI3_1_SHIFT (19u) +#define INTC_ICDICFR17_SPEI4_0_SHIFT (20u) +#define INTC_ICDICFR17_SPEI4_1_SHIFT (21u) +#define INTC_ICDICFR17_SPRI4_0_SHIFT (22u) +#define INTC_ICDICFR17_SPRI4_1_SHIFT (23u) +#define INTC_ICDICFR17_SPTI4_0_SHIFT (24u) +#define INTC_ICDICFR17_SPTI4_1_SHIFT (25u) +#define INTC_ICDICFR17_IEBBTD_0_SHIFT (26u) +#define INTC_ICDICFR17_IEBBTD_1_SHIFT (27u) +#define INTC_ICDICFR17_IEBBTERR_0_SHIFT (28u) +#define INTC_ICDICFR17_IEBBTERR_1_SHIFT (29u) +#define INTC_ICDICFR17_IEBBTSTA_0_SHIFT (30u) +#define INTC_ICDICFR17_IEBBTSTA_1_SHIFT (31u) + +#define INTC_ICDICFR18_IEBBTV_0_SHIFT (0u) +#define INTC_ICDICFR18_IEBBTV_1_SHIFT (1u) +#define INTC_ICDICFR18_ISY_0_SHIFT (2u) +#define INTC_ICDICFR18_ISY_1_SHIFT (3u) +#define INTC_ICDICFR18_IERR_0_SHIFT (4u) +#define INTC_ICDICFR18_IERR_1_SHIFT (5u) +#define INTC_ICDICFR18_ITARG_0_SHIFT (6u) +#define INTC_ICDICFR18_ITARG_1_SHIFT (7u) +#define INTC_ICDICFR18_ISEC_0_SHIFT (8u) +#define INTC_ICDICFR18_ISEC_1_SHIFT (9u) +#define INTC_ICDICFR18_IBUF_0_SHIFT (10u) +#define INTC_ICDICFR18_IBUF_1_SHIFT (11u) +#define INTC_ICDICFR18_IREADY_0_SHIFT (12u) +#define INTC_ICDICFR18_IREADY_1_SHIFT (13u) +#define INTC_ICDICFR18_FLSTE_0_SHIFT (14u) +#define INTC_ICDICFR18_FLSTE_1_SHIFT (15u) +#define INTC_ICDICFR18_FLTENDI_0_SHIFT (16u) +#define INTC_ICDICFR18_FLTENDI_1_SHIFT (17u) +#define INTC_ICDICFR18_FLTREQ0I_0_SHIFT (18u) +#define INTC_ICDICFR18_FLTREQ0I_1_SHIFT (19u) +#define INTC_ICDICFR18_FLTREQ1I_0_SHIFT (20u) +#define INTC_ICDICFR18_FLTREQ1I_1_SHIFT (21u) +#define INTC_ICDICFR18_MMC0_0_SHIFT (22u) +#define INTC_ICDICFR18_MMC0_1_SHIFT (23u) +#define INTC_ICDICFR18_MMC1_0_SHIFT (24u) +#define INTC_ICDICFR18_MMC1_1_SHIFT (25u) +#define INTC_ICDICFR18_MMC2_0_SHIFT (26u) +#define INTC_ICDICFR18_MMC2_1_SHIFT (27u) +#define INTC_ICDICFR18_SDHI0_3_0_SHIFT (28u) +#define INTC_ICDICFR18_SDHI0_3_1_SHIFT (29u) +#define INTC_ICDICFR18_SDHI0_0_0_SHIFT (30u) +#define INTC_ICDICFR18_SDHI0_0_1_SHIFT (31u) + +#define INTC_ICDICFR19_SDHI0_1_0_SHIFT (0u) +#define INTC_ICDICFR19_SDHI0_1_1_SHIFT (1u) +#define INTC_ICDICFR19_SDHI1_3_0_SHIFT (2u) +#define INTC_ICDICFR19_SDHI1_3_1_SHIFT (3u) +#define INTC_ICDICFR19_SDHI1_0_0_SHIFT (4u) +#define INTC_ICDICFR19_SDHI1_0_1_SHIFT (5u) +#define INTC_ICDICFR19_SDHI1_1_0_SHIFT (6u) +#define INTC_ICDICFR19_SDHI1_1_1_SHIFT (7u) +#define INTC_ICDICFR19_ARM_0_SHIFT (8u) +#define INTC_ICDICFR19_ARM_1_SHIFT (9u) +#define INTC_ICDICFR19_PRD_0_SHIFT (10u) +#define INTC_ICDICFR19_PRD_1_SHIFT (11u) +#define INTC_ICDICFR19_CUP_0_SHIFT (12u) +#define INTC_ICDICFR19_CUP_1_SHIFT (13u) +#define INTC_ICDICFR19_SCUAI0_0_SHIFT (14u) +#define INTC_ICDICFR19_SCUAI0_1_SHIFT (15u) +#define INTC_ICDICFR19_SCUAI1_0_SHIFT (16u) +#define INTC_ICDICFR19_SCUAI1_1_SHIFT (17u) +#define INTC_ICDICFR19_SCUFDI0_0_SHIFT (18u) +#define INTC_ICDICFR19_SCUFDI0_1_SHIFT (19u) +#define INTC_ICDICFR19_SCUFDI1_0_SHIFT (20u) +#define INTC_ICDICFR19_SCUFDI1_1_SHIFT (21u) +#define INTC_ICDICFR19_SCUFDI2_0_SHIFT (22u) +#define INTC_ICDICFR19_SCUFDI2_1_SHIFT (23u) +#define INTC_ICDICFR19_SCUFDI3_0_SHIFT (24u) +#define INTC_ICDICFR19_SCUFDI3_1_SHIFT (25u) +#define INTC_ICDICFR19_SCUFUI0_0_SHIFT (26u) +#define INTC_ICDICFR19_SCUFUI0_1_SHIFT (27u) +#define INTC_ICDICFR19_SCUFUI1_0_SHIFT (28u) +#define INTC_ICDICFR19_SCUFUI1_1_SHIFT (29u) +#define INTC_ICDICFR19_SCUFUI2_0_SHIFT (30u) +#define INTC_ICDICFR19_SCUFUI2_1_SHIFT (31u) + +#define INTC_ICDICFR20_SCUFUI3_0_SHIFT (0u) +#define INTC_ICDICFR20_SCUFUI3_1_SHIFT (1u) +#define INTC_ICDICFR20_SCUDVI0_0_SHIFT (2u) +#define INTC_ICDICFR20_SCUDVI0_1_SHIFT (3u) +#define INTC_ICDICFR20_SCUDVI1_0_SHIFT (4u) +#define INTC_ICDICFR20_SCUDVI1_1_SHIFT (5u) +#define INTC_ICDICFR20_SCUDVI2_0_SHIFT (6u) +#define INTC_ICDICFR20_SCUDVI2_1_SHIFT (7u) +#define INTC_ICDICFR20_SCUDVI3_0_SHIFT (8u) +#define INTC_ICDICFR20_SCUDVI3_1_SHIFT (9u) +#define INTC_ICDICFR20_MLB_CINT_0_SHIFT (10u) +#define INTC_ICDICFR20_MLB_CINT_1_SHIFT (11u) +#define INTC_ICDICFR20_MLB_SINT_0_SHIFT (12u) +#define INTC_ICDICFR20_MLB_SINT_1_SHIFT (13u) +#define INTC_ICDICFR20_DRC0_0_SHIFT (14u) +#define INTC_ICDICFR20_DRC0_1_SHIFT (15u) +#define INTC_ICDICFR20_DRC1_0_SHIFT (16u) +#define INTC_ICDICFR20_DRC1_1_SHIFT (17u) +#define INTC_ICDICFR20_LINI0_INT_T_0_SHIFT (22u) +#define INTC_ICDICFR20_LINI0_INT_T_1_SHIFT (23u) +#define INTC_ICDICFR20_LINI0_INT_R_0_SHIFT (24u) +#define INTC_ICDICFR20_LINI0_INT_R_1_SHIFT (25u) +#define INTC_ICDICFR20_LINI0_INT_S_0_SHIFT (26u) +#define INTC_ICDICFR20_LINI0_INT_S_1_SHIFT (27u) +#define INTC_ICDICFR20_LINI0_INT_M_0_SHIFT (28u) +#define INTC_ICDICFR20_LINI0_INT_M_1_SHIFT (29u) +#define INTC_ICDICFR20_LINI1_INT_T_0_SHIFT (30u) +#define INTC_ICDICFR20_LINI1_INT_T_1_SHIFT (31u) + +#define INTC_ICDICFR21_LINI1_INT_R_0_SHIFT (0u) +#define INTC_ICDICFR21_LINI1_INT_R_1_SHIFT (1u) +#define INTC_ICDICFR21_LINI1_INT_S_0_SHIFT (2u) +#define INTC_ICDICFR21_LINI1_INT_S_1_SHIFT (3u) +#define INTC_ICDICFR21_LINI1_INT_M_0_SHIFT (4u) +#define INTC_ICDICFR21_LINI1_INT_M_1_SHIFT (5u) +#define INTC_ICDICFR21_ERI0_0_SHIFT (22u) +#define INTC_ICDICFR21_ERI0_1_SHIFT (23u) +#define INTC_ICDICFR21_RXI0_0_SHIFT (24u) +#define INTC_ICDICFR21_RXI0_1_SHIFT (25u) +#define INTC_ICDICFR21_TXI0_0_SHIFT (26u) +#define INTC_ICDICFR21_TXI0_1_SHIFT (27u) +#define INTC_ICDICFR21_TEI0_0_SHIFT (28u) +#define INTC_ICDICFR21_TEI0_1_SHIFT (29u) +#define INTC_ICDICFR21_ERI1_0_SHIFT (30u) +#define INTC_ICDICFR21_ERI1_1_SHIFT (31u) + +#define INTC_ICDICFR22_RXI1_0_SHIFT (0u) +#define INTC_ICDICFR22_RXI1_1_SHIFT (1u) +#define INTC_ICDICFR22_TXI1_0_SHIFT (2u) +#define INTC_ICDICFR22_TXI1_1_SHIFT (3u) +#define INTC_ICDICFR22_TEI1_0_SHIFT (4u) +#define INTC_ICDICFR22_TEI1_1_SHIFT (5u) +#define INTC_ICDICFR22_AVBI_DATA_0_SHIFT (6u) +#define INTC_ICDICFR22_AVBI_DATA_1_SHIFT (7u) +#define INTC_ICDICFR22_AVBI_ERROR_0_SHIFT (8u) +#define INTC_ICDICFR22_AVBI_ERROR_1_SHIFT (9u) +#define INTC_ICDICFR22_AVBI_MANAGE_0_SHIFT (10u) +#define INTC_ICDICFR22_AVBI_MANAGE_1_SHIFT (11u) +#define INTC_ICDICFR22_AVBI_MAC_0_SHIFT (12u) +#define INTC_ICDICFR22_AVBI_MAC_1_SHIFT (13u) +#define INTC_ICDICFR22_ETHERI_0_SHIFT (14u) +#define INTC_ICDICFR22_ETHERI_1_SHIFT (15u) +#define INTC_ICDICFR22_CEUI_0_SHIFT (24u) +#define INTC_ICDICFR22_CEUI_1_SHIFT (25u) + +#define INTC_ICDICFR23_H2XMLB_ERRINT_0_SHIFT (26u) +#define INTC_ICDICFR23_H2XMLB_ERRINT_1_SHIFT (27u) +#define INTC_ICDICFR23_H2XIC1_ERRINT_0_SHIFT (28u) +#define INTC_ICDICFR23_H2XIC1_ERRINT_1_SHIFT (29u) +#define INTC_ICDICFR23_X2HPERI1_ERRINT_0_SHIFT (30u) +#define INTC_ICDICFR23_X2HPERI1_ERRINT_1_SHIFT (31u) + +#define INTC_ICDICFR24_X2HPERI2_ERRINT_0_SHIFT (0u) +#define INTC_ICDICFR24_X2HPERI2_ERRINT_1_SHIFT (1u) +#define INTC_ICDICFR24_X2HPERI34_ERRINT_0_SHIFT (2u) +#define INTC_ICDICFR24_X2HPERI34_ERRINT_1_SHIFT (3u) +#define INTC_ICDICFR24_X2HPERI5_ERRINT_0_SHIFT (4u) +#define INTC_ICDICFR24_X2HPERI5_ERRINT_1_SHIFT (5u) +#define INTC_ICDICFR24_X2HPERI67_ERRINT_0_SHIFT (6u) +#define INTC_ICDICFR24_X2HPERI67_ERRINT_1_SHIFT (7u) +#define INTC_ICDICFR24_X2HDBGR_ERRINT_0_SHIFT (8u) +#define INTC_ICDICFR24_X2HDBGR_ERRINT_1_SHIFT (9u) +#define INTC_ICDICFR24_X2HBSC_ERRINT_0_SHIFT (10u) +#define INTC_ICDICFR24_X2HBSC_ERRINT_1_SHIFT (11u) +#define INTC_ICDICFR24_X2HSPI1_ERRINT_0_SHIFT (12u) +#define INTC_ICDICFR24_X2HSPI1_ERRINT_1_SHIFT (13u) +#define INTC_ICDICFR24_X2HSPI2_ERRINT_0_SHIFT (14u) +#define INTC_ICDICFR24_X2HSPI2_ERRINT_1_SHIFT (15u) +#define INTC_ICDICFR24_PRRI_0_SHIFT (16u) +#define INTC_ICDICFR24_PRRI_1_SHIFT (17u) +#define INTC_ICDICFR24_IFEI0_0_SHIFT (18u) +#define INTC_ICDICFR24_IFEI0_1_SHIFT (19u) +#define INTC_ICDICFR24_OFFI0_0_SHIFT (20u) +#define INTC_ICDICFR24_OFFI0_1_SHIFT (21u) +#define INTC_ICDICFR24_PFVEI0_0_SHIFT (22u) +#define INTC_ICDICFR24_PFVEI0_1_SHIFT (23u) +#define INTC_ICDICFR24_IFEI1_0_SHIFT (24u) +#define INTC_ICDICFR24_IFEI1_1_SHIFT (25u) +#define INTC_ICDICFR24_OFFI1_0_SHIFT (26u) +#define INTC_ICDICFR24_OFFI1_1_SHIFT (27u) +#define INTC_ICDICFR24_PFVEI1_0_SHIFT (28u) +#define INTC_ICDICFR24_PFVEI1_1_SHIFT (29u) + +#define INTC_ICDICFR26_TINT0_0_SHIFT (0u) +#define INTC_ICDICFR26_TINT0_1_SHIFT (1u) +#define INTC_ICDICFR26_TINT1_0_SHIFT (2u) +#define INTC_ICDICFR26_TINT1_1_SHIFT (3u) +#define INTC_ICDICFR26_TINT2_0_SHIFT (4u) +#define INTC_ICDICFR26_TINT2_1_SHIFT (5u) +#define INTC_ICDICFR26_TINT3_0_SHIFT (6u) +#define INTC_ICDICFR26_TINT3_1_SHIFT (7u) +#define INTC_ICDICFR26_TINT4_0_SHIFT (8u) +#define INTC_ICDICFR26_TINT4_1_SHIFT (9u) +#define INTC_ICDICFR26_TINT5_0_SHIFT (10u) +#define INTC_ICDICFR26_TINT5_1_SHIFT (11u) +#define INTC_ICDICFR26_TINT6_0_SHIFT (12u) +#define INTC_ICDICFR26_TINT6_1_SHIFT (13u) +#define INTC_ICDICFR26_TINT7_0_SHIFT (14u) +#define INTC_ICDICFR26_TINT7_1_SHIFT (15u) +#define INTC_ICDICFR26_TINT8_0_SHIFT (16u) +#define INTC_ICDICFR26_TINT8_1_SHIFT (17u) +#define INTC_ICDICFR26_TINT9_0_SHIFT (18u) +#define INTC_ICDICFR26_TINT9_1_SHIFT (19u) +#define INTC_ICDICFR26_TINT10_0_SHIFT (20u) +#define INTC_ICDICFR26_TINT10_1_SHIFT (21u) +#define INTC_ICDICFR26_TINT11_0_SHIFT (22u) +#define INTC_ICDICFR26_TINT11_1_SHIFT (23u) +#define INTC_ICDICFR26_TINT12_0_SHIFT (24u) +#define INTC_ICDICFR26_TINT12_1_SHIFT (25u) +#define INTC_ICDICFR26_TINT13_0_SHIFT (26u) +#define INTC_ICDICFR26_TINT13_1_SHIFT (27u) +#define INTC_ICDICFR26_TINT14_0_SHIFT (28u) +#define INTC_ICDICFR26_TINT14_1_SHIFT (29u) +#define INTC_ICDICFR26_TINT15_0_SHIFT (30u) +#define INTC_ICDICFR26_TINT15_1_SHIFT (31u) + +#define INTC_ICDICFR27_TINT16_0_SHIFT (0u) +#define INTC_ICDICFR27_TINT16_1_SHIFT (1u) +#define INTC_ICDICFR27_TINT17_0_SHIFT (2u) +#define INTC_ICDICFR27_TINT17_1_SHIFT (3u) +#define INTC_ICDICFR27_TINT18_0_SHIFT (4u) +#define INTC_ICDICFR27_TINT18_1_SHIFT (5u) +#define INTC_ICDICFR27_TINT19_0_SHIFT (6u) +#define INTC_ICDICFR27_TINT19_1_SHIFT (7u) +#define INTC_ICDICFR27_TINT20_0_SHIFT (8u) +#define INTC_ICDICFR27_TINT20_1_SHIFT (9u) +#define INTC_ICDICFR27_TINT21_0_SHIFT (10u) +#define INTC_ICDICFR27_TINT21_1_SHIFT (11u) +#define INTC_ICDICFR27_TINT22_0_SHIFT (12u) +#define INTC_ICDICFR27_TINT22_1_SHIFT (13u) +#define INTC_ICDICFR27_TINT23_0_SHIFT (14u) +#define INTC_ICDICFR27_TINT23_1_SHIFT (15u) +#define INTC_ICDICFR27_TINT24_0_SHIFT (16u) +#define INTC_ICDICFR27_TINT24_1_SHIFT (17u) +#define INTC_ICDICFR27_TINT25_0_SHIFT (18u) +#define INTC_ICDICFR27_TINT25_1_SHIFT (19u) +#define INTC_ICDICFR27_TINT26_0_SHIFT (20u) +#define INTC_ICDICFR27_TINT26_1_SHIFT (21u) +#define INTC_ICDICFR27_TINT27_0_SHIFT (22u) +#define INTC_ICDICFR27_TINT27_1_SHIFT (23u) +#define INTC_ICDICFR27_TINT28_0_SHIFT (24u) +#define INTC_ICDICFR27_TINT28_1_SHIFT (25u) +#define INTC_ICDICFR27_TINT29_0_SHIFT (26u) +#define INTC_ICDICFR27_TINT29_1_SHIFT (27u) +#define INTC_ICDICFR27_TINT30_0_SHIFT (28u) +#define INTC_ICDICFR27_TINT30_1_SHIFT (29u) +#define INTC_ICDICFR27_TINT31_0_SHIFT (30u) +#define INTC_ICDICFR27_TINT31_1_SHIFT (31u) + +#define INTC_ICDICFR28_TINT32_0_SHIFT (0u) +#define INTC_ICDICFR28_TINT32_1_SHIFT (1u) +#define INTC_ICDICFR28_TINT33_0_SHIFT (2u) +#define INTC_ICDICFR28_TINT33_1_SHIFT (3u) +#define INTC_ICDICFR28_TINT34_0_SHIFT (4u) +#define INTC_ICDICFR28_TINT34_1_SHIFT (5u) +#define INTC_ICDICFR28_TINT35_0_SHIFT (6u) +#define INTC_ICDICFR28_TINT35_1_SHIFT (7u) +#define INTC_ICDICFR28_TINT36_0_SHIFT (8u) +#define INTC_ICDICFR28_TINT36_1_SHIFT (9u) +#define INTC_ICDICFR28_TINT37_0_SHIFT (10u) +#define INTC_ICDICFR28_TINT37_1_SHIFT (11u) +#define INTC_ICDICFR28_TINT38_0_SHIFT (12u) +#define INTC_ICDICFR28_TINT38_1_SHIFT (13u) +#define INTC_ICDICFR28_TINT39_0_SHIFT (14u) +#define INTC_ICDICFR28_TINT39_1_SHIFT (15u) +#define INTC_ICDICFR28_TINT40_0_SHIFT (16u) +#define INTC_ICDICFR28_TINT40_1_SHIFT (17u) +#define INTC_ICDICFR28_TINT41_0_SHIFT (18u) +#define INTC_ICDICFR28_TINT41_1_SHIFT (19u) +#define INTC_ICDICFR28_TINT42_0_SHIFT (20u) +#define INTC_ICDICFR28_TINT42_1_SHIFT (21u) +#define INTC_ICDICFR28_TINT43_0_SHIFT (22u) +#define INTC_ICDICFR28_TINT43_1_SHIFT (23u) +#define INTC_ICDICFR28_TINT44_0_SHIFT (24u) +#define INTC_ICDICFR28_TINT44_1_SHIFT (25u) +#define INTC_ICDICFR28_TINT45_0_SHIFT (26u) +#define INTC_ICDICFR28_TINT45_1_SHIFT (27u) +#define INTC_ICDICFR28_TINT46_0_SHIFT (28u) +#define INTC_ICDICFR28_TINT46_1_SHIFT (29u) +#define INTC_ICDICFR28_TINT47_0_SHIFT (30u) +#define INTC_ICDICFR28_TINT47_1_SHIFT (31u) + +#define INTC_ICDICFR29_TINT48_0_SHIFT (0u) +#define INTC_ICDICFR29_TINT48_1_SHIFT (1u) +#define INTC_ICDICFR29_TINT49_0_SHIFT (2u) +#define INTC_ICDICFR29_TINT49_1_SHIFT (3u) +#define INTC_ICDICFR29_TINT50_0_SHIFT (4u) +#define INTC_ICDICFR29_TINT50_1_SHIFT (5u) +#define INTC_ICDICFR29_TINT51_0_SHIFT (6u) +#define INTC_ICDICFR29_TINT51_1_SHIFT (7u) +#define INTC_ICDICFR29_TINT52_0_SHIFT (8u) +#define INTC_ICDICFR29_TINT52_1_SHIFT (9u) +#define INTC_ICDICFR29_TINT53_0_SHIFT (10u) +#define INTC_ICDICFR29_TINT53_1_SHIFT (11u) +#define INTC_ICDICFR29_TINT54_0_SHIFT (12u) +#define INTC_ICDICFR29_TINT54_1_SHIFT (13u) +#define INTC_ICDICFR29_TINT55_0_SHIFT (14u) +#define INTC_ICDICFR29_TINT55_1_SHIFT (15u) +#define INTC_ICDICFR29_TINT56_0_SHIFT (16u) +#define INTC_ICDICFR29_TINT56_1_SHIFT (17u) +#define INTC_ICDICFR29_TINT57_0_SHIFT (18u) +#define INTC_ICDICFR29_TINT57_1_SHIFT (19u) +#define INTC_ICDICFR29_TINT58_0_SHIFT (20u) +#define INTC_ICDICFR29_TINT58_1_SHIFT (21u) +#define INTC_ICDICFR29_TINT59_0_SHIFT (22u) +#define INTC_ICDICFR29_TINT59_1_SHIFT (23u) +#define INTC_ICDICFR29_TINT60_0_SHIFT (24u) +#define INTC_ICDICFR29_TINT60_1_SHIFT (25u) +#define INTC_ICDICFR29_TINT61_0_SHIFT (26u) +#define INTC_ICDICFR29_TINT61_1_SHIFT (27u) +#define INTC_ICDICFR29_TINT62_0_SHIFT (28u) +#define INTC_ICDICFR29_TINT62_1_SHIFT (29u) +#define INTC_ICDICFR29_TINT63_0_SHIFT (30u) +#define INTC_ICDICFR29_TINT63_1_SHIFT (31u) + +#define INTC_ICDICFR30_TINT64_0_SHIFT (0u) +#define INTC_ICDICFR30_TINT64_1_SHIFT (1u) +#define INTC_ICDICFR30_TINT65_0_SHIFT (2u) +#define INTC_ICDICFR30_TINT65_1_SHIFT (3u) +#define INTC_ICDICFR30_TINT66_0_SHIFT (4u) +#define INTC_ICDICFR30_TINT66_1_SHIFT (5u) +#define INTC_ICDICFR30_TINT67_0_SHIFT (6u) +#define INTC_ICDICFR30_TINT67_1_SHIFT (7u) +#define INTC_ICDICFR30_TINT68_0_SHIFT (8u) +#define INTC_ICDICFR30_TINT68_1_SHIFT (9u) +#define INTC_ICDICFR30_TINT69_0_SHIFT (10u) +#define INTC_ICDICFR30_TINT69_1_SHIFT (11u) +#define INTC_ICDICFR30_TINT70_0_SHIFT (12u) +#define INTC_ICDICFR30_TINT70_1_SHIFT (13u) +#define INTC_ICDICFR30_TINT71_0_SHIFT (14u) +#define INTC_ICDICFR30_TINT71_1_SHIFT (15u) +#define INTC_ICDICFR30_TINT72_0_SHIFT (16u) +#define INTC_ICDICFR30_TINT72_1_SHIFT (17u) +#define INTC_ICDICFR30_TINT73_0_SHIFT (18u) +#define INTC_ICDICFR30_TINT73_1_SHIFT (19u) +#define INTC_ICDICFR30_TINT74_0_SHIFT (20u) +#define INTC_ICDICFR30_TINT74_1_SHIFT (21u) +#define INTC_ICDICFR30_TINT75_0_SHIFT (22u) +#define INTC_ICDICFR30_TINT75_1_SHIFT (23u) +#define INTC_ICDICFR30_TINT76_0_SHIFT (24u) +#define INTC_ICDICFR30_TINT76_1_SHIFT (25u) +#define INTC_ICDICFR30_TINT77_0_SHIFT (26u) +#define INTC_ICDICFR30_TINT77_1_SHIFT (27u) +#define INTC_ICDICFR30_TINT78_0_SHIFT (28u) +#define INTC_ICDICFR30_TINT78_1_SHIFT (29u) +#define INTC_ICDICFR30_TINT79_0_SHIFT (30u) +#define INTC_ICDICFR30_TINT79_1_SHIFT (31u) + +#define INTC_ICDICFR31_TINT80_0_SHIFT (0u) +#define INTC_ICDICFR31_TINT80_1_SHIFT (1u) +#define INTC_ICDICFR31_TINT81_0_SHIFT (2u) +#define INTC_ICDICFR31_TINT81_1_SHIFT (3u) +#define INTC_ICDICFR31_TINT82_0_SHIFT (4u) +#define INTC_ICDICFR31_TINT82_1_SHIFT (5u) +#define INTC_ICDICFR31_TINT83_0_SHIFT (6u) +#define INTC_ICDICFR31_TINT83_1_SHIFT (7u) +#define INTC_ICDICFR31_TINT84_0_SHIFT (8u) +#define INTC_ICDICFR31_TINT84_1_SHIFT (9u) +#define INTC_ICDICFR31_TINT85_0_SHIFT (10u) +#define INTC_ICDICFR31_TINT85_1_SHIFT (11u) +#define INTC_ICDICFR31_TINT86_0_SHIFT (12u) +#define INTC_ICDICFR31_TINT86_1_SHIFT (13u) +#define INTC_ICDICFR31_TINT87_0_SHIFT (14u) +#define INTC_ICDICFR31_TINT87_1_SHIFT (15u) +#define INTC_ICDICFR31_TINT88_0_SHIFT (16u) +#define INTC_ICDICFR31_TINT88_1_SHIFT (17u) +#define INTC_ICDICFR31_TINT89_0_SHIFT (18u) +#define INTC_ICDICFR31_TINT89_1_SHIFT (19u) +#define INTC_ICDICFR31_TINT90_0_SHIFT (20u) +#define INTC_ICDICFR31_TINT90_1_SHIFT (21u) +#define INTC_ICDICFR31_TINT91_0_SHIFT (22u) +#define INTC_ICDICFR31_TINT91_1_SHIFT (23u) +#define INTC_ICDICFR31_TINT92_0_SHIFT (24u) +#define INTC_ICDICFR31_TINT92_1_SHIFT (25u) +#define INTC_ICDICFR31_TINT93_0_SHIFT (26u) +#define INTC_ICDICFR31_TINT93_1_SHIFT (27u) +#define INTC_ICDICFR31_TINT94_0_SHIFT (28u) +#define INTC_ICDICFR31_TINT94_1_SHIFT (29u) +#define INTC_ICDICFR31_TINT95_0_SHIFT (30u) +#define INTC_ICDICFR31_TINT95_1_SHIFT (31u) + +#define INTC_ICDICFR32_TINT96_0_SHIFT (0u) +#define INTC_ICDICFR32_TINT96_1_SHIFT (1u) +#define INTC_ICDICFR32_TINT97_0_SHIFT (2u) +#define INTC_ICDICFR32_TINT97_1_SHIFT (3u) +#define INTC_ICDICFR32_TINT98_0_SHIFT (4u) +#define INTC_ICDICFR32_TINT98_1_SHIFT (5u) +#define INTC_ICDICFR32_TINT99_0_SHIFT (6u) +#define INTC_ICDICFR32_TINT99_1_SHIFT (7u) +#define INTC_ICDICFR32_TINT100_0_SHIFT (8u) +#define INTC_ICDICFR32_TINT100_1_SHIFT (9u) +#define INTC_ICDICFR32_TINT101_0_SHIFT (10u) +#define INTC_ICDICFR32_TINT101_1_SHIFT (11u) +#define INTC_ICDICFR32_TINT102_0_SHIFT (12u) +#define INTC_ICDICFR32_TINT102_1_SHIFT (13u) +#define INTC_ICDICFR32_TINT103_0_SHIFT (14u) +#define INTC_ICDICFR32_TINT103_1_SHIFT (15u) +#define INTC_ICDICFR32_TINT104_0_SHIFT (16u) +#define INTC_ICDICFR32_TINT104_1_SHIFT (17u) +#define INTC_ICDICFR32_TINT105_0_SHIFT (18u) +#define INTC_ICDICFR32_TINT105_1_SHIFT (19u) +#define INTC_ICDICFR32_TINT106_0_SHIFT (20u) +#define INTC_ICDICFR32_TINT106_1_SHIFT (21u) +#define INTC_ICDICFR32_TINT107_0_SHIFT (22u) +#define INTC_ICDICFR32_TINT107_1_SHIFT (23u) +#define INTC_ICDICFR32_TINT108_0_SHIFT (24u) +#define INTC_ICDICFR32_TINT108_1_SHIFT (25u) +#define INTC_ICDICFR32_TINT109_0_SHIFT (26u) +#define INTC_ICDICFR32_TINT109_1_SHIFT (27u) +#define INTC_ICDICFR32_TINT110_0_SHIFT (28u) +#define INTC_ICDICFR32_TINT110_1_SHIFT (29u) +#define INTC_ICDICFR32_TINT111_0_SHIFT (30u) +#define INTC_ICDICFR32_TINT111_1_SHIFT (31u) + +#define INTC_ICDICFR33_TINT112_0_SHIFT (0u) +#define INTC_ICDICFR33_TINT112_1_SHIFT (1u) +#define INTC_ICDICFR33_TINT113_0_SHIFT (2u) +#define INTC_ICDICFR33_TINT113_1_SHIFT (3u) +#define INTC_ICDICFR33_TINT114_0_SHIFT (4u) +#define INTC_ICDICFR33_TINT114_1_SHIFT (5u) +#define INTC_ICDICFR33_TINT115_0_SHIFT (6u) +#define INTC_ICDICFR33_TINT115_1_SHIFT (7u) +#define INTC_ICDICFR33_TINT116_0_SHIFT (8u) +#define INTC_ICDICFR33_TINT116_1_SHIFT (9u) +#define INTC_ICDICFR33_TINT117_0_SHIFT (10u) +#define INTC_ICDICFR33_TINT117_1_SHIFT (11u) +#define INTC_ICDICFR33_TINT118_0_SHIFT (12u) +#define INTC_ICDICFR33_TINT118_1_SHIFT (13u) +#define INTC_ICDICFR33_TINT119_0_SHIFT (14u) +#define INTC_ICDICFR33_TINT119_1_SHIFT (15u) +#define INTC_ICDICFR33_TINT120_0_SHIFT (16u) +#define INTC_ICDICFR33_TINT120_1_SHIFT (17u) +#define INTC_ICDICFR33_TINT121_0_SHIFT (18u) +#define INTC_ICDICFR33_TINT121_1_SHIFT (19u) +#define INTC_ICDICFR33_TINT122_0_SHIFT (20u) +#define INTC_ICDICFR33_TINT122_1_SHIFT (21u) +#define INTC_ICDICFR33_TINT123_0_SHIFT (22u) +#define INTC_ICDICFR33_TINT123_1_SHIFT (23u) +#define INTC_ICDICFR33_TINT124_0_SHIFT (24u) +#define INTC_ICDICFR33_TINT124_1_SHIFT (25u) +#define INTC_ICDICFR33_TINT125_0_SHIFT (26u) +#define INTC_ICDICFR33_TINT125_1_SHIFT (27u) +#define INTC_ICDICFR33_TINT126_0_SHIFT (28u) +#define INTC_ICDICFR33_TINT126_1_SHIFT (29u) +#define INTC_ICDICFR33_TINT127_0_SHIFT (30u) +#define INTC_ICDICFR33_TINT127_1_SHIFT (31u) + +#define INTC_ICDICFR34_TINT128_0_SHIFT (0u) +#define INTC_ICDICFR34_TINT128_1_SHIFT (1u) +#define INTC_ICDICFR34_TINT129_0_SHIFT (2u) +#define INTC_ICDICFR34_TINT129_1_SHIFT (3u) +#define INTC_ICDICFR34_TINT130_0_SHIFT (4u) +#define INTC_ICDICFR34_TINT130_1_SHIFT (5u) +#define INTC_ICDICFR34_TINT131_0_SHIFT (6u) +#define INTC_ICDICFR34_TINT131_1_SHIFT (7u) +#define INTC_ICDICFR34_TINT132_0_SHIFT (8u) +#define INTC_ICDICFR34_TINT132_1_SHIFT (9u) +#define INTC_ICDICFR34_TINT133_0_SHIFT (10u) +#define INTC_ICDICFR34_TINT133_1_SHIFT (11u) +#define INTC_ICDICFR34_TINT134_0_SHIFT (12u) +#define INTC_ICDICFR34_TINT134_1_SHIFT (13u) +#define INTC_ICDICFR34_TINT135_0_SHIFT (14u) +#define INTC_ICDICFR34_TINT135_1_SHIFT (15u) +#define INTC_ICDICFR34_TINT136_0_SHIFT (16u) +#define INTC_ICDICFR34_TINT136_1_SHIFT (17u) +#define INTC_ICDICFR34_TINT137_0_SHIFT (18u) +#define INTC_ICDICFR34_TINT137_1_SHIFT (19u) +#define INTC_ICDICFR34_TINT138_0_SHIFT (20u) +#define INTC_ICDICFR34_TINT138_1_SHIFT (21u) +#define INTC_ICDICFR34_TINT139_0_SHIFT (22u) +#define INTC_ICDICFR34_TINT139_1_SHIFT (23u) +#define INTC_ICDICFR34_TINT140_0_SHIFT (24u) +#define INTC_ICDICFR34_TINT140_1_SHIFT (25u) +#define INTC_ICDICFR34_TINT141_0_SHIFT (26u) +#define INTC_ICDICFR34_TINT141_1_SHIFT (27u) +#define INTC_ICDICFR34_TINT142_0_SHIFT (28u) +#define INTC_ICDICFR34_TINT142_1_SHIFT (29u) +#define INTC_ICDICFR34_TINT143_0_SHIFT (30u) +#define INTC_ICDICFR34_TINT143_1_SHIFT (31u) + +#define INTC_ICDICFR35_TINT144_0_SHIFT (0u) +#define INTC_ICDICFR35_TINT144_1_SHIFT (1u) +#define INTC_ICDICFR35_TINT145_0_SHIFT (2u) +#define INTC_ICDICFR35_TINT145_1_SHIFT (3u) +#define INTC_ICDICFR35_TINT146_0_SHIFT (4u) +#define INTC_ICDICFR35_TINT146_1_SHIFT (5u) +#define INTC_ICDICFR35_TINT147_0_SHIFT (6u) +#define INTC_ICDICFR35_TINT147_1_SHIFT (7u) +#define INTC_ICDICFR35_TINT148_0_SHIFT (8u) +#define INTC_ICDICFR35_TINT148_1_SHIFT (9u) +#define INTC_ICDICFR35_TINT149_0_SHIFT (10u) +#define INTC_ICDICFR35_TINT149_1_SHIFT (11u) +#define INTC_ICDICFR35_TINT150_0_SHIFT (12u) +#define INTC_ICDICFR35_TINT150_1_SHIFT (13u) +#define INTC_ICDICFR35_TINT151_0_SHIFT (14u) +#define INTC_ICDICFR35_TINT151_1_SHIFT (15u) +#define INTC_ICDICFR35_TINT152_0_SHIFT (16u) +#define INTC_ICDICFR35_TINT152_1_SHIFT (17u) +#define INTC_ICDICFR35_TINT153_0_SHIFT (18u) +#define INTC_ICDICFR35_TINT153_1_SHIFT (19u) +#define INTC_ICDICFR35_TINT154_0_SHIFT (20u) +#define INTC_ICDICFR35_TINT154_1_SHIFT (21u) +#define INTC_ICDICFR35_TINT155_0_SHIFT (22u) +#define INTC_ICDICFR35_TINT155_1_SHIFT (23u) +#define INTC_ICDICFR35_TINT156_0_SHIFT (24u) +#define INTC_ICDICFR35_TINT156_1_SHIFT (25u) +#define INTC_ICDICFR35_TINT157_0_SHIFT (26u) +#define INTC_ICDICFR35_TINT157_1_SHIFT (27u) +#define INTC_ICDICFR35_TINT158_0_SHIFT (28u) +#define INTC_ICDICFR35_TINT158_1_SHIFT (29u) +#define INTC_ICDICFR35_TINT159_0_SHIFT (30u) +#define INTC_ICDICFR35_TINT159_1_SHIFT (31u) + +#define INTC_ICDICFR36_TINT160_0_SHIFT (0u) +#define INTC_ICDICFR36_TINT160_1_SHIFT (1u) +#define INTC_ICDICFR36_TINT161_0_SHIFT (2u) +#define INTC_ICDICFR36_TINT161_1_SHIFT (3u) +#define INTC_ICDICFR36_TINT162_0_SHIFT (4u) +#define INTC_ICDICFR36_TINT162_1_SHIFT (5u) +#define INTC_ICDICFR36_TINT163_0_SHIFT (6u) +#define INTC_ICDICFR36_TINT163_1_SHIFT (7u) +#define INTC_ICDICFR36_TINT164_0_SHIFT (8u) +#define INTC_ICDICFR36_TINT164_1_SHIFT (9u) +#define INTC_ICDICFR36_TINT165_0_SHIFT (10u) +#define INTC_ICDICFR36_TINT165_1_SHIFT (11u) +#define INTC_ICDICFR36_TINT166_0_SHIFT (12u) +#define INTC_ICDICFR36_TINT166_1_SHIFT (13u) +#define INTC_ICDICFR36_TINT167_0_SHIFT (14u) +#define INTC_ICDICFR36_TINT167_1_SHIFT (15u) +#define INTC_ICDICFR36_TINT168_0_SHIFT (16u) +#define INTC_ICDICFR36_TINT168_1_SHIFT (17u) +#define INTC_ICDICFR36_TINT169_0_SHIFT (18u) +#define INTC_ICDICFR36_TINT169_1_SHIFT (19u) +#define INTC_ICDICFR36_TINT170_0_SHIFT (20u) +#define INTC_ICDICFR36_TINT170_1_SHIFT (21u) + +#define INTC_ICDSGIR_SGIINTID_SHIFT (0u) +#define INTC_ICDSGIR_SATT_SHIFT (15u) +#define INTC_ICDSGIR_CPUTargetList_SHIFT (16u) +#define INTC_ICDSGIR_TargetListFilter_SHIFT (24u) + +#define INTC_ICCICR_EnableS_SHIFT (0u) +#define INTC_ICCICR_EnableNS_SHIFT (1u) +#define INTC_ICCICR_AckCtl_SHIFT (2u) +#define INTC_ICCICR_FIQEn_SHIFT (3u) +#define INTC_ICCICR_SBPR_SHIFT (4u) + +#define INTC_ICCPMR_Priority_SHIFT (0u) + +#define INTC_ICCBPR_Binarypoint_SHIFT (0u) + +#define INTC_ICCIAR_ACKINTID_SHIFT (0u) +#define INTC_ICCIAR_CPUID_SHIFT (10u) + +#define INTC_ICCEOIR_EOIINTID_SHIFT (0u) +#define INTC_ICCEOIR_CPUID_SHIFT (10u) + +#define INTC_ICCRPR_Priority_SHIFT (0u) + +#define INTC_ICCHPIR_PENDINTID_SHIFT (0u) +#define INTC_ICCHPIR_CPUID_SHIFT (10u) + +#define INTC_ICCABPR_Binarypoint_SHIFT (0u) + +#define INTC_ICCIIDR_Implementer_SHIFT (0u) +#define INTC_ICCIIDR_Revision_SHIFT (12u) +#define INTC_ICCIIDR_Architecture_version_SHIFT (16u) +#define INTC_ICCIIDR_ProductID_SHIFT (20u) + +#define INTC_ICR0_NMIF_SHIFT (1u) +#define INTC_ICR0_NMIE_SHIFT (8u) +#define INTC_ICR0_NMIL_SHIFT (15u) + +#define INTC_ICR1_IRQ00S_SHIFT (0u) +#define INTC_ICR1_IRQ01S_SHIFT (1u) +#define INTC_ICR1_IRQ10S_SHIFT (2u) +#define INTC_ICR1_IRQ11S_SHIFT (3u) +#define INTC_ICR1_IRQ20S_SHIFT (4u) +#define INTC_ICR1_IRQ21S_SHIFT (5u) +#define INTC_ICR1_IRQ30S_SHIFT (6u) +#define INTC_ICR1_IRQ31S_SHIFT (7u) +#define INTC_ICR1_IRQ40S_SHIFT (8u) +#define INTC_ICR1_IRQ41S_SHIFT (9u) +#define INTC_ICR1_IRQ50S_SHIFT (10u) +#define INTC_ICR1_IRQ51S_SHIFT (11u) +#define INTC_ICR1_IRQ60S_SHIFT (12u) +#define INTC_ICR1_IRQ61S_SHIFT (13u) +#define INTC_ICR1_IRQ70S_SHIFT (14u) +#define INTC_ICR1_IRQ71S_SHIFT (15u) + +#define INTC_IRQRR_IRQ0F_SHIFT (0u) +#define INTC_IRQRR_IRQ1F_SHIFT (1u) +#define INTC_IRQRR_IRQ2F_SHIFT (2u) +#define INTC_IRQRR_IRQ3F_SHIFT (3u) +#define INTC_IRQRR_IRQ4F_SHIFT (4u) +#define INTC_IRQRR_IRQ5F_SHIFT (5u) +#define INTC_IRQRR_IRQ6F_SHIFT (6u) +#define INTC_IRQRR_IRQ7F_SHIFT (7u) + + +#endif /* INTC_IOBITMASK_H */ + +/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/mtu2_iobitmask.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,462 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : mtu2_iobitmask.h +* $Rev: 1138 $ +* $Date:: 2014-08-08 11:03:56 +0900#$ +* Description : MTU2 register define header +*******************************************************************************/ +#ifndef MTU2_IOBITMASK_H +#define MTU2_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ +#define MTU2_TCR_n_TPSC (0x07u) +#define MTU2_TCR_n_CKEG (0x18u) +#define MTU2_TCR_n_CCLR (0xE0u) + +#define MTU2_TMDR_n_MD (0x0Fu) + +#define MTU2_TIOR_2_IOA (0x0Fu) +#define MTU2_TIOR_2_IOB (0xF0u) + +#define MTU2_TIER_n_TGIEA (0x01u) +#define MTU2_TIER_n_TGIEB (0x02u) +#define MTU2_TIER_n_TCIEV (0x10u) +#define MTU2_TIER_2_TCIEU (0x20u) +#define MTU2_TIER_n_TTGE (0x80u) + +#define MTU2_TSR_n_TGFA (0x01u) +#define MTU2_TSR_n_TGFB (0x02u) +#define MTU2_TSR_n_TCFV (0x10u) +#define MTU2_TSR_2_TCFU (0x20u) +#define MTU2_TSR_2_TCFD (0x80u) + +#define MTU2_TCNT_n_D (0xFFFFu) + +#define MTU2_TGRA_n_D (0xFFFFu) + +#define MTU2_TGRB_n_D (0xFFFFu) + +#define MTU2_TMDR_3_BFA (0x10u) +#define MTU2_TMDR_3_BFB (0x20u) + +#define MTU2_TMDR_4_BFA (0x10u) +#define MTU2_TMDR_4_BFB (0x20u) + +#define MTU2_TIORH_3_IOA (0x0Fu) +#define MTU2_TIORH_3_IOB (0xF0u) + +#define MTU2_TIORL_3_IOC (0x0Fu) +#define MTU2_TIORL_3_IOD (0xF0u) + +#define MTU2_TIORH_4_IOA (0x0Fu) +#define MTU2_TIORH_4_IOB (0xF0u) + +#define MTU2_TIORL_4_IOC (0x0Fu) +#define MTU2_TIORL_4_IOD (0xF0u) + +#define MTU2_TIER_3_TGIEC (0x04u) +#define MTU2_TIER_3_TGIED (0x08u) + +#define MTU2_TIER_4_TGIEC (0x04u) +#define MTU2_TIER_4_TGIED (0x08u) +#define MTU2_TIER_4_TTGE2 (0x40u) + +#define MTU2_TOER_OE3B (0x01u) +#define MTU2_TOER_OE4A (0x02u) +#define MTU2_TOER_OE4B (0x04u) +#define MTU2_TOER_OE3D (0x08u) +#define MTU2_TOER_OE4C (0x10u) +#define MTU2_TOER_OE4D (0x20u) + +#define MTU2_TGCR_UF (0x01u) +#define MTU2_TGCR_VF (0x02u) +#define MTU2_TGCR_WF (0x04u) +#define MTU2_TGCR_FB (0x08u) +#define MTU2_TGCR_P (0x10u) +#define MTU2_TGCR_N (0x20u) +#define MTU2_TGCR_BDC (0x40u) + +#define MTU2_TOCR1_OLSP (0x01u) +#define MTU2_TOCR1_OLSN (0x02u) +#define MTU2_TOCR1_TOCS (0x04u) +#define MTU2_TOCR1_TOCL (0x08u) +#define MTU2_TOCR1_PSYE (0x40u) + +#define MTU2_TOCR2_OLS1P (0x01u) +#define MTU2_TOCR2_OLS1N (0x02u) +#define MTU2_TOCR2_OLS2P (0x04u) +#define MTU2_TOCR2_OLS2N (0x08u) +#define MTU2_TOCR2_OLS3P (0x10u) +#define MTU2_TOCR2_OLS3N (0x20u) +#define MTU2_TOCR2_BF (0xC0u) + +#define MTU2_TCDR_D (0xFFFFu) + +#define MTU2_TDDR_D (0xFFFFu) + +#define MTU2_TCNTS_D (0xFFFFu) + +#define MTU2_TCBR_D (0xFFFFu) + +#define MTU2_TGRC_3_D (0xFFFFu) + +#define MTU2_TGRD_3_D (0xFFFFu) + +#define MTU2_TGRC_4_D (0xFFFFu) + +#define MTU2_TGRD_4_D (0xFFFFu) + +#define MTU2_TSR_3_TGFC (0x04u) +#define MTU2_TSR_3_TGFD (0x08u) +#define MTU2_TSR_3_TCFD (0x80u) + +#define MTU2_TSR_4_TGFC (0x04u) +#define MTU2_TSR_4_TGFD (0x08u) +#define MTU2_TSR_4_TCFD (0x80u) + +#define MTU2_TITCR_4VCOR (0x07u) +#define MTU2_TITCR_T4VEN (0x08u) +#define MTU2_TITCR_3ACOR (0x70u) +#define MTU2_TITCR_T3AEN (0x80u) + +#define MTU2_TITCNT_4VCNT (0x07u) +#define MTU2_TITCNT_3ACNT (0x70u) + +#define MTU2_TBTER_BTE (0x03u) + +#define MTU2_TDER_TDER (0x01u) + +#define MTU2_TOLBR_OLS1P (0x01u) +#define MTU2_TOLBR_OLS1N (0x02u) +#define MTU2_TOLBR_OLS2P (0x04u) +#define MTU2_TOLBR_OLS2N (0x08u) +#define MTU2_TOLBR_OLS3P (0x10u) +#define MTU2_TOLBR_OLS3N (0x20u) + +#define MTU2_TBTM_3_TTSA (0x01u) +#define MTU2_TBTM_3_TTSB (0x02u) + +#define MTU2_TBTM_4_TTSA (0x01u) +#define MTU2_TBTM_4_TTSB (0x02u) + +#define MTU2_TADCR_ITB4VE (0x0001u) +#define MTU2_TADCR_ITB3AE (0x0002u) +#define MTU2_TADCR_ITA4VE (0x0004u) +#define MTU2_TADCR_ITA3AE (0x0008u) +#define MTU2_TADCR_DT4BE (0x0010u) +#define MTU2_TADCR_UT4BE (0x0020u) +#define MTU2_TADCR_DT4AE (0x0040u) +#define MTU2_TADCR_UT4AE (0x0080u) +#define MTU2_TADCR_BF (0xC000u) + +#define MTU2_TADCORA_4_D (0xFFFFu) + +#define MTU2_TADCORB_4_D (0xFFFFu) + +#define MTU2_TADCOBRA_4_D (0xFFFFu) + +#define MTU2_TADCOBRB_4_D (0xFFFFu) + +#define MTU2_TWCR_WRE (0x01u) +#define MTU2_TWCR_CCE (0x80u) + +#define MTU2_TSTR_CST0 (0x01u) +#define MTU2_TSTR_CST1 (0x02u) +#define MTU2_TSTR_CST2 (0x04u) +#define MTU2_TSTR_CST3 (0x40u) +#define MTU2_TSTR_CST4 (0x80u) + +#define MTU2_TSYR_SYNC0 (0x01u) +#define MTU2_TSYR_SYNC1 (0x02u) +#define MTU2_TSYR_SYNC2 (0x04u) +#define MTU2_TSYR_SYNC3 (0x40u) +#define MTU2_TSYR_SYNC4 (0x80u) + +#define MTU2_TRWER_RWE (0x01u) + +#define MTU2_TMDR_0_BFA (0x10u) +#define MTU2_TMDR_0_BFB (0x20u) +#define MTU2_TMDR_0_BFE (0x40u) + +#define MTU2_TIORH_0_IOA (0x0Fu) +#define MTU2_TIORH_0_IOB (0xF0u) + +#define MTU2_TIORL_0_IOC (0x0Fu) +#define MTU2_TIORL_0_IOD (0xF0u) + +#define MTU2_TIER_0_TGIEC (0x04u) +#define MTU2_TIER_0_TGIED (0x08u) + +#define MTU2_TSR_0_TGFC (0x04u) +#define MTU2_TSR_0_TGFD (0x08u) + +#define MTU2_TGRC_0_D (0xFFFFu) + +#define MTU2_TGRD_0_D (0xFFFFu) + +#define MTU2_TGRE_0_D (0xFFFFu) + +#define MTU2_TGRF_0_D (0xFFFFu) + +#define MTU2_TIER2_0_TGIEE (0x01u) +#define MTU2_TIER2_0_TGIEF (0x02u) + +#define MTU2_TSR2_0_TGFE (0x01u) +#define MTU2_TSR2_0_TGFF (0x02u) + +#define MTU2_TBTM_0_TTSA (0x01u) +#define MTU2_TBTM_0_TTSB (0x02u) +#define MTU2_TBTM_0_TTSE (0x04u) + +#define MTU2_TIOR_1_IOA (0x0Fu) +#define MTU2_TIOR_1_IOB (0xF0u) + +#define MTU2_TIER_1_TCIEU (0x20u) + +#define MTU2_TSR_1_TCFU (0x20u) +#define MTU2_TSR_1_TCFD (0x80u) + +#define MTU2_TICCR_I1AE (0x01u) +#define MTU2_TICCR_I1BE (0x02u) +#define MTU2_TICCR_I2AE (0x04u) +#define MTU2_TICCR_I2BE (0x08u) + + +/* ==== Shift values for IO registers ==== */ +#define MTU2_TCR_n_TPSC_SHIFT (0u) +#define MTU2_TCR_n_CKEG_SHIFT (3u) +#define MTU2_TCR_n_CCLR_SHIFT (5u) + +#define MTU2_TMDR_n_MD_SHIFT (0u) + +#define MTU2_TIOR_2_IOA_SHIFT (0u) +#define MTU2_TIOR_2_IOB_SHIFT (4u) + +#define MTU2_TIER_n_TGIEA_SHIFT (0u) +#define MTU2_TIER_n_TGIEB_SHIFT (1u) +#define MTU2_TIER_n_TCIEV_SHIFT (4u) +#define MTU2_TIER_2_TCIEU_SHIFT (5u) +#define MTU2_TIER_n_TTGE_SHIFT (7u) + +#define MTU2_TSR_n_TGFA_SHIFT (0u) +#define MTU2_TSR_n_TGFB_SHIFT (1u) +#define MTU2_TSR_n_TCFV_SHIFT (4u) +#define MTU2_TSR_2_TCFU_SHIFT (5u) +#define MTU2_TSR_2_TCFD_SHIFT (7u) + +#define MTU2_TCNT_n_D_SHIFT (0u) + +#define MTU2_TGRA_n_D_SHIFT (0u) + +#define MTU2_TGRB_n_D_SHIFT (0u) + +#define MTU2_TMDR_3_BFA_SHIFT (4u) +#define MTU2_TMDR_3_BFB_SHIFT (5u) + +#define MTU2_TMDR_4_BFA_SHIFT (4u) +#define MTU2_TMDR_4_BFB_SHIFT (5u) + +#define MTU2_TIORH_3_IOA_SHIFT (0u) +#define MTU2_TIORH_3_IOB_SHIFT (4u) + +#define MTU2_TIORL_3_IOC_SHIFT (0u) +#define MTU2_TIORL_3_IOD_SHIFT (4u) + +#define MTU2_TIORH_4_IOA_SHIFT (0u) +#define MTU2_TIORH_4_IOB_SHIFT (4u) + +#define MTU2_TIORL_4_IOC_SHIFT (0u) +#define MTU2_TIORL_4_IOD_SHIFT (4u) + +#define MTU2_TIER_3_TGIEC_SHIFT (2u) +#define MTU2_TIER_3_TGIED_SHIFT (3u) + +#define MTU2_TIER_4_TGIEC_SHIFT (2u) +#define MTU2_TIER_4_TGIED_SHIFT (3u) +#define MTU2_TIER_4_TTGE2_SHIFT (6u) + +#define MTU2_TOER_OE3B_SHIFT (0u) +#define MTU2_TOER_OE4A_SHIFT (1u) +#define MTU2_TOER_OE4B_SHIFT (2u) +#define MTU2_TOER_OE3D_SHIFT (3u) +#define MTU2_TOER_OE4C_SHIFT (4u) +#define MTU2_TOER_OE4D_SHIFT (5u) + +#define MTU2_TGCR_UF_SHIFT (0u) +#define MTU2_TGCR_VF_SHIFT (1u) +#define MTU2_TGCR_WF_SHIFT (2u) +#define MTU2_TGCR_FB_SHIFT (3u) +#define MTU2_TGCR_P_SHIFT (4u) +#define MTU2_TGCR_N_SHIFT (5u) +#define MTU2_TGCR_BDC_SHIFT (6u) + +#define MTU2_TOCR1_OLSP_SHIFT (0u) +#define MTU2_TOCR1_OLSN_SHIFT (1u) +#define MTU2_TOCR1_TOCS_SHIFT (2u) +#define MTU2_TOCR1_TOCL_SHIFT (3u) +#define MTU2_TOCR1_PSYE_SHIFT (6u) + +#define MTU2_TOCR2_OLS1P_SHIFT (0u) +#define MTU2_TOCR2_OLS1N_SHIFT (1u) +#define MTU2_TOCR2_OLS2P_SHIFT (2u) +#define MTU2_TOCR2_OLS2N_SHIFT (3u) +#define MTU2_TOCR2_OLS3P_SHIFT (4u) +#define MTU2_TOCR2_OLS3N_SHIFT (5u) +#define MTU2_TOCR2_BF_SHIFT (6u) + +#define MTU2_TCDR_D_SHIFT (0u) + +#define MTU2_TDDR_D_SHIFT (0u) + +#define MTU2_TCNTS_D_SHIFT (0u) + +#define MTU2_TCBR_D_SHIFT (0u) + +#define MTU2_TGRC_3_D_SHIFT (0u) + +#define MTU2_TGRD_3_D_SHIFT (0u) + +#define MTU2_TGRC_4_D_SHIFT (0u) + +#define MTU2_TGRD_4_D_SHIFT (0u) + +#define MTU2_TSR_3_TGFC_SHIFT (2u) +#define MTU2_TSR_3_TGFD_SHIFT (3u) +#define MTU2_TSR_3_TCFD_SHIFT (7u) + +#define MTU2_TSR_4_TGFC_SHIFT (2u) +#define MTU2_TSR_4_TGFD_SHIFT (3u) +#define MTU2_TSR_4_TCFD_SHIFT (7u) + +#define MTU2_TITCR_4VCOR_SHIFT (0u) +#define MTU2_TITCR_T4VEN_SHIFT (3u) +#define MTU2_TITCR_3ACOR_SHIFT (4u) +#define MTU2_TITCR_T3AEN_SHIFT (7u) + +#define MTU2_TITCNT_4VCNT_SHIFT (0u) +#define MTU2_TITCNT_3ACNT_SHIFT (4u) + +#define MTU2_TBTER_BTE_SHIFT (0u) + +#define MTU2_TDER_TDER_SHIFT (0u) + +#define MTU2_TOLBR_OLS1P_SHIFT (0u) +#define MTU2_TOLBR_OLS1N_SHIFT (1u) +#define MTU2_TOLBR_OLS2P_SHIFT (2u) +#define MTU2_TOLBR_OLS2N_SHIFT (3u) +#define MTU2_TOLBR_OLS3P_SHIFT (4u) +#define MTU2_TOLBR_OLS3N_SHIFT (5u) + +#define MTU2_TBTM_3_TTSA_SHIFT (0u) +#define MTU2_TBTM_3_TTSB_SHIFT (1u) + +#define MTU2_TBTM_4_TTSA_SHIFT (0u) +#define MTU2_TBTM_4_TTSB_SHIFT (1u) + +#define MTU2_TADCR_ITB4VE_SHIFT (0u) +#define MTU2_TADCR_ITB3AE_SHIFT (1u) +#define MTU2_TADCR_ITA4VE_SHIFT (2u) +#define MTU2_TADCR_ITA3AE_SHIFT (3u) +#define MTU2_TADCR_DT4BE_SHIFT (4u) +#define MTU2_TADCR_UT4BE_SHIFT (5u) +#define MTU2_TADCR_DT4AE_SHIFT (6u) +#define MTU2_TADCR_UT4AE_SHIFT (7u) +#define MTU2_TADCR_BF_SHIFT (14u) + +#define MTU2_TADCORA_4_D_SHIFT (0u) + +#define MTU2_TADCORB_4_D_SHIFT (0u) + +#define MTU2_TADCOBRA_4_D_SHIFT (0u) + +#define MTU2_TADCOBRB_4_D_SHIFT (0u) + +#define MTU2_TWCR_WRE_SHIFT (0u) +#define MTU2_TWCR_CCE_SHIFT (7u) + +#define MTU2_TSTR_CST0_SHIFT (0u) +#define MTU2_TSTR_CST1_SHIFT (1u) +#define MTU2_TSTR_CST2_SHIFT (2u) +#define MTU2_TSTR_CST3_SHIFT (6u) +#define MTU2_TSTR_CST4_SHIFT (7u) + +#define MTU2_TSYR_SYNC0_SHIFT (0u) +#define MTU2_TSYR_SYNC1_SHIFT (1u) +#define MTU2_TSYR_SYNC2_SHIFT (2u) +#define MTU2_TSYR_SYNC3_SHIFT (6u) +#define MTU2_TSYR_SYNC4_SHIFT (7u) + +#define MTU2_TRWER_RWE_SHIFT (0u) + +#define MTU2_TMDR_0_BFA_SHIFT (4u) +#define MTU2_TMDR_0_BFB_SHIFT (5u) +#define MTU2_TMDR_0_BFE_SHIFT (6u) + +#define MTU2_TIORH_0_IOA_SHIFT (0u) +#define MTU2_TIORH_0_IOB_SHIFT (4u) + +#define MTU2_TIORL_0_IOC_SHIFT (0u) +#define MTU2_TIORL_0_IOD_SHIFT (4u) + +#define MTU2_TIER_0_TGIEC_SHIFT (2u) +#define MTU2_TIER_0_TGIED_SHIFT (3u) + +#define MTU2_TSR_0_TGFC_SHIFT (2u) +#define MTU2_TSR_0_TGFD_SHIFT (3u) + +#define MTU2_TGRC_0_D_SHIFT (0u) + +#define MTU2_TGRD_0_D_SHIFT (0u) + +#define MTU2_TGRE_0_D_SHIFT (0u) + +#define MTU2_TGRF_0_D_SHIFT (0u) + +#define MTU2_TIER2_0_TGIEE_SHIFT (0u) +#define MTU2_TIER2_0_TGIEF_SHIFT (1u) + +#define MTU2_TSR2_0_TGFE_SHIFT (0u) +#define MTU2_TSR2_0_TGFF_SHIFT (1u) + +#define MTU2_TBTM_0_TTSA_SHIFT (0u) +#define MTU2_TBTM_0_TTSB_SHIFT (1u) +#define MTU2_TBTM_0_TTSE_SHIFT (2u) + +#define MTU2_TIOR_1_IOA_SHIFT (0u) +#define MTU2_TIOR_1_IOB_SHIFT (4u) + +#define MTU2_TIER_1_TCIEU_SHIFT (5u) + +#define MTU2_TSR_1_TCFU_SHIFT (5u) +#define MTU2_TSR_1_TCFD_SHIFT (7u) + +#define MTU2_TICCR_I1AE_SHIFT (0u) +#define MTU2_TICCR_I1BE_SHIFT (1u) +#define MTU2_TICCR_I2AE_SHIFT (2u) +#define MTU2_TICCR_I2BE_SHIFT (3u) + + +#endif /* MTU2_IOBITMASK_H */ +/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/ostm_iobitmask.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,123 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : ostm_iobitmask.h +* $Rev: 1115 $ +* $Date:: 2014-07-09 15:35:02 +0900#$ +* Description : OSTM register define header +*******************************************************************************/ +#ifndef OSTM_IOBITMASK_H +#define OSTM_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ +/* ---- OSTM0 ---- */ +#define OSTM0_OSTMnCMP_OSTMnCMP (0xFFFFFFFFuL) + +#define OSTM0_OSTMnCNT_OSTMnCNT (0xFFFFFFFFuL) + +#define OSTM0_OSTMnTE_OSTMnTE (0x01u) + +#define OSTM0_OSTMnTS_OSTMnTS (0x01u) + +#define OSTM0_OSTMnTT_OSTMnTT (0x01u) + +#define OSTM0_OSTMnCTL_MD0 (0x00000001uL) +#define OSTM0_OSTMnCTL_MD1 (0x00000002uL) + +/* ---- OSTM1 ---- */ +#define OSTM1_OSTMnCMP_OSTMnCMP (0xFFFFFFFFuL) + +#define OSTM1_OSTMnCNT_OSTMnCNT (0xFFFFFFFFuL) + +#define OSTM1_OSTMnTE_OSTMnTE (0x01u) + +#define OSTM1_OSTMnTS_OSTMnTS (0x01u) + +#define OSTM1_OSTMnTT_OSTMnTT (0x01u) + +#define OSTM1_OSTMnCTL_MD0 (0x00000001uL) +#define OSTM1_OSTMnCTL_MD1 (0x00000002uL) + +/* ---- OSTMn ---- */ +#define OSTMn_OSTMnCMP_OSTMnCMP (0xFFFFFFFFuL) + +#define OSTMn_OSTMnCNT_OSTMnCNT (0xFFFFFFFFuL) + +#define OSTMn_OSTMnTE_OSTMnTE (0x01u) + +#define OSTMn_OSTMnTS_OSTMnTS (0x01u) + +#define OSTMn_OSTMnTT_OSTMnTT (0x01u) + +#define OSTMn_OSTMnCTL_MD0 (0x00000001uL) +#define OSTMn_OSTMnCTL_MD1 (0x00000002uL) + + +/* ==== Shift values for IO registers ==== */ +/* ---- OSTM0 ---- */ +#define OSTM0_OSTMnCMP_OSTMnCMP_SHIFT (0u) + +#define OSTM0_OSTMnCNT_OSTMnCNT_SHIFT (0u) + +#define OSTM0_OSTMnTE_OSTMnTE_SHIFT (0u) + +#define OSTM0_OSTMnTS_OSTMnTS_SHIFT (0u) + +#define OSTM0_OSTMnTT_OSTMnTT_SHIFT (0u) + +#define OSTM0_OSTMnCTL_MD0_SHIFT (0u) +#define OSTM0_OSTMnCTL_MD1_SHIFT (1u) + +/* ---- OSTM1 ---- */ +#define OSTM1_OSTMnCMP_OSTMnCMP_SHIFT (0u) + +#define OSTM1_OSTMnCNT_OSTMnCNT_SHIFT (0u) + +#define OSTM1_OSTMnTE_OSTMnTE_SHIFT (0u) + +#define OSTM1_OSTMnTS_OSTMnTS_SHIFT (0u) + +#define OSTM1_OSTMnTT_OSTMnTT_SHIFT (0u) + +#define OSTM1_OSTMnCTL_MD0_SHIFT (0u) +#define OSTM1_OSTMnCTL_MD1_SHIFT (1u) + +/* ---- OSTMn ---- */ +#define OSTMn_OSTMnCMP_OSTMnCMP_SHIFT (0u) + +#define OSTMn_OSTMnCNT_OSTMnCNT_SHIFT (0u) + +#define OSTMn_OSTMnTE_OSTMnTE_SHIFT (0u) + +#define OSTMn_OSTMnTS_OSTMnTS_SHIFT (0u) + +#define OSTMn_OSTMnTT_OSTMnTT_SHIFT (0u) + +#define OSTMn_OSTMnCTL_MD0_SHIFT (0u) +#define OSTMn_OSTMnCTL_MD1_SHIFT (1u) + + +#endif /* OSTM_IOBITMASK_H */ + +/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/riic_iobitmask.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,231 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : riic_iobitmask.h +* $Rev: 1114 $ +* $Date:: 2014-07-09 14:56:39 +0900#$ +* Description : RIIC register define header +*******************************************************************************/ +#ifndef RIIC_IOBITMASK_H +#define RIIC_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ +#define RIICn_RIICnCR1_SDAI (0x01u) +#define RIICn_RIICnCR1_SCLI (0x02u) +#define RIICn_RIICnCR1_SDAO (0x04u) +#define RIICn_RIICnCR1_SCLO (0x08u) +#define RIICn_RIICnCR1_SOWP (0x10u) +#define RIICn_RIICnCR1_CLO (0x20u) +#define RIICn_RIICnCR1_IICRST (0x40u) +#define RIICn_RIICnCR1_ICE (0x80u) + +#define RIICn_RIICnCR2_ST (0x02u) +#define RIICn_RIICnCR2_RS (0x04u) +#define RIICn_RIICnCR2_SP (0x08u) +#define RIICn_RIICnCR2_TRS (0x20u) +#define RIICn_RIICnCR2_MST (0x40u) +#define RIICn_RIICnCR2_BBSY (0x80u) + +#define RIICn_RIICnMR1_BC (0x07u) +#define RIICn_RIICnMR1_BCWP (0x08u) +#define RIICn_RIICnMR1_CKS (0x70u) +#define RIICn_RIICnMR1_MTWP (0x80u) + +#define RIICn_RIICnMR2_TMOS (0x01u) +#define RIICn_RIICnMR2_TMOL (0x02u) +#define RIICn_RIICnMR2_TMOH (0x04u) +#define RIICn_RIICnMR2_SDDL (0x70u) +#define RIICn_RIICnMR2_DLCS (0x80u) + +#define RIICn_RIICnMR3_NF (0x03u) +#define RIICn_RIICnMR3_ACKBR (0x04u) +#define RIICn_RIICnMR3_ACKBT (0x08u) +#define RIICn_RIICnMR3_ACKWP (0x10u) +#define RIICn_RIICnMR3_RDRFS (0x20u) +#define RIICn_RIICnMR3_WAIT (0x40u) +#define RIICn_RIICnMR3_SMBS (0x80u) + +#define RIICn_RIICnFER_TMOE (0x01u) +#define RIICn_RIICnFER_MALE (0x02u) +#define RIICn_RIICnFER_NALE (0x04u) +#define RIICn_RIICnFER_SALE (0x08u) +#define RIICn_RIICnFER_NACKE (0x10u) +#define RIICn_RIICnFER_NFE (0x20u) +#define RIICn_RIICnFER_SCLE (0x40u) +#define RIICn_RIICnFER_FMPE (0x80u) + +#define RIICn_RIICnSER_SAR0E (0x01u) +#define RIICn_RIICnSER_SAR1E (0x02u) +#define RIICn_RIICnSER_SAR2E (0x04u) +#define RIICn_RIICnSER_GCAE (0x08u) +#define RIICn_RIICnSER_DIDE (0x20u) +#define RIICn_RIICnSER_HOAE (0x80u) + +#define RIICn_RIICnIER_TMOIE (0x01u) +#define RIICn_RIICnIER_ALIE (0x02u) +#define RIICn_RIICnIER_STIE (0x04u) +#define RIICn_RIICnIER_SPIE (0x08u) +#define RIICn_RIICnIER_NAKIE (0x10u) +#define RIICn_RIICnIER_RIE (0x20u) +#define RIICn_RIICnIER_TEIE (0x40u) +#define RIICn_RIICnIER_TIE (0x80u) + +#define RIICn_RIICnSR1_AAS0 (0x01u) +#define RIICn_RIICnSR1_AAS1 (0x02u) +#define RIICn_RIICnSR1_AAS2 (0x04u) +#define RIICn_RIICnSR1_GCA (0x08u) +#define RIICn_RIICnSR1_DID (0x20u) +#define RIICn_RIICnSR1_HOA (0x80u) + +#define RIICn_RIICnSR2_TMOF (0x01u) +#define RIICn_RIICnSR2_AL (0x02u) +#define RIICn_RIICnSR2_START (0x04u) +#define RIICn_RIICnSR2_STOP (0x08u) +#define RIICn_RIICnSR2_NACKF (0x10u) +#define RIICn_RIICnSR2_RDRF (0x20u) +#define RIICn_RIICnSR2_TEND (0x40u) +#define RIICn_RIICnSR2_TDRE (0x80u) + +#define RIICn_RIICnSAR0_SVA0 (0x0001u) +#define RIICn_RIICnSAR0_SVA (0x03FEu) +#define RIICn_RIICnSAR0_FSy (0x8000u) + +#define RIICn_RIICnSAR1_SVA0 (0x0001u) +#define RIICn_RIICnSAR1_SVA (0x03FEu) +#define RIICn_RIICnSAR1_FSy (0x8000u) + +#define RIICn_RIICnSAR2_SVA0 (0x0001u) +#define RIICn_RIICnSAR2_SVA (0x03FEu) +#define RIICn_RIICnSAR2_FSy (0x8000u) + +#define RIICn_RIICnBRL_BRL (0x1Fu) + +#define RIICn_RIICnBRH_BRH (0x1Fu) + +#define RIICn_RIICnDRT_DRT (0xFFu) + +#define RIICn_RIICnDRR_DRR (0xFFu) + + +/* ==== Shift values for IO registers ==== */ +#define RIICn_RIICnCR1_SDAI_SHIFT (0u) +#define RIICn_RIICnCR1_SCLI_SHIFT (1u) +#define RIICn_RIICnCR1_SDAO_SHIFT (2u) +#define RIICn_RIICnCR1_SCLO_SHIFT (3u) +#define RIICn_RIICnCR1_SOWP_SHIFT (4u) +#define RIICn_RIICnCR1_CLO_SHIFT (5u) +#define RIICn_RIICnCR1_IICRST_SHIFT (6u) +#define RIICn_RIICnCR1_ICE_SHIFT (7u) + +#define RIICn_RIICnCR2_ST_SHIFT (1u) +#define RIICn_RIICnCR2_RS_SHIFT (2u) +#define RIICn_RIICnCR2_SP_SHIFT (3u) +#define RIICn_RIICnCR2_TRS_SHIFT (5u) +#define RIICn_RIICnCR2_MST_SHIFT (6u) +#define RIICn_RIICnCR2_BBSY_SHIFT (7u) + +#define RIICn_RIICnMR1_BC_SHIFT (0u) +#define RIICn_RIICnMR1_BCWP_SHIFT (3u) +#define RIICn_RIICnMR1_CKS_SHIFT (4u) +#define RIICn_RIICnMR1_MTWP_SHIFT (7u) + +#define RIICn_RIICnMR2_TMOS_SHIFT (0u) +#define RIICn_RIICnMR2_TMOL_SHIFT (1u) +#define RIICn_RIICnMR2_TMOH_SHIFT (2u) +#define RIICn_RIICnMR2_SDDL_SHIFT (4u) +#define RIICn_RIICnMR2_DLCS_SHIFT (7u) + +#define RIICn_RIICnMR3_NF_SHIFT (0u) +#define RIICn_RIICnMR3_ACKBR_SHIFT (2u) +#define RIICn_RIICnMR3_ACKBT_SHIFT (3u) +#define RIICn_RIICnMR3_ACKWP_SHIFT (4u) +#define RIICn_RIICnMR3_RDRFS_SHIFT (5u) +#define RIICn_RIICnMR3_WAIT_SHIFT (6u) +#define RIICn_RIICnMR3_SMBS_SHIFT (7u) + +#define RIICn_RIICnFER_TMOE_SHIFT (0u) +#define RIICn_RIICnFER_MALE_SHIFT (1u) +#define RIICn_RIICnFER_NALE_SHIFT (2u) +#define RIICn_RIICnFER_SALE_SHIFT (3u) +#define RIICn_RIICnFER_NACKE_SHIFT (4u) +#define RIICn_RIICnFER_NFE_SHIFT (5u) +#define RIICn_RIICnFER_SCLE_SHIFT (6u) +#define RIICn_RIICnFER_FMPE_SHIFT (7u) + +#define RIICn_RIICnSER_SAR0E_SHIFT (0u) +#define RIICn_RIICnSER_SAR1E_SHIFT (1u) +#define RIICn_RIICnSER_SAR2E_SHIFT (2u) +#define RIICn_RIICnSER_GCAE_SHIFT (3u) +#define RIICn_RIICnSER_DIDE_SHIFT (5u) +#define RIICn_RIICnSER_HOAE_SHIFT (7u) + +#define RIICn_RIICnIER_TMOIE_SHIFT (0u) +#define RIICn_RIICnIER_ALIE_SHIFT (1u) +#define RIICn_RIICnIER_STIE_SHIFT (2u) +#define RIICn_RIICnIER_SPIE_SHIFT (3u) +#define RIICn_RIICnIER_NAKIE_SHIFT (4u) +#define RIICn_RIICnIER_RIE_SHIFT (5u) +#define RIICn_RIICnIER_TEIE_SHIFT (6u) +#define RIICn_RIICnIER_TIE_SHIFT (7u) + +#define RIICn_RIICnSR1_AAS0_SHIFT (0u) +#define RIICn_RIICnSR1_AAS1_SHIFT (1u) +#define RIICn_RIICnSR1_AAS2_SHIFT (2u) +#define RIICn_RIICnSR1_GCA_SHIFT (3u) +#define RIICn_RIICnSR1_DID_SHIFT (5u) +#define RIICn_RIICnSR1_HOA_SHIFT (7u) + +#define RIICn_RIICnSR2_TMOF_SHIFT (0u) +#define RIICn_RIICnSR2_AL_SHIFT (1u) +#define RIICn_RIICnSR2_START_SHIFT (2u) +#define RIICn_RIICnSR2_STOP_SHIFT (3u) +#define RIICn_RIICnSR2_NACKF_SHIFT (4u) +#define RIICn_RIICnSR2_RDRF_SHIFT (5u) +#define RIICn_RIICnSR2_TEND_SHIFT (6u) +#define RIICn_RIICnSR2_TDRE_SHIFT (7u) + +#define RIICn_RIICnSAR0_SVA0_SHIFT (0u) +#define RIICn_RIICnSAR0_SVA_SHIFT (1u) +#define RIICn_RIICnSAR0_FSy_SHIFT (15u) + +#define RIICn_RIICnSAR1_SVA0_SHIFT (0u) +#define RIICn_RIICnSAR1_SVA_SHIFT (1u) +#define RIICn_RIICnSAR1_FSy_SHIFT (15u) + +#define RIICn_RIICnSAR2_SVA0_SHIFT (0u) +#define RIICn_RIICnSAR2_SVA_SHIFT (1u) +#define RIICn_RIICnSAR2_FSy_SHIFT (15u) + +#define RIICn_RIICnBRL_BRL_SHIFT (0u) + +#define RIICn_RIICnBRH_BRH_SHIFT (0u) + +#define RIICn_RIICnDRT_DRT_SHIFT (0u) + +#define RIICn_RIICnDRR_DRR_SHIFT (0u) + + +#endif /* RIIC_IOBITMASK_H */ + +/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/rspi_iobitmask.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,215 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : rspi_iobitmask.h +* $Rev: 1114 $ +* $Date:: 2014-07-09 14:56:39 +0900#$ +* Description : Renesas Serial Peripheral Interface register define header +*******************************************************************************/ +#ifndef RSPI_IOBITMASK_H +#define RSPI_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ +#define RSPIn_SPCR_MODFEN (0x04u) +#define RSPIn_SPCR_MSTR (0x08u) +#define RSPIn_SPCR_SPEIE (0x10u) +#define RSPIn_SPCR_SPTIE (0x20u) +#define RSPIn_SPCR_SPE (0x40u) +#define RSPIn_SPCR_SPRIE (0x80u) + +#define RSPIn_SSLP_SSL0P (0x01u) + +#define RSPIn_SPPCR_SPLP (0x01u) +#define RSPIn_SPPCR_MOIFV (0x10u) +#define RSPIn_SPPCR_MOIFE (0x20u) + +#define RSPIn_SPSR_OVRF (0x01u) +#define RSPIn_SPSR_MODF (0x04u) +#define RSPIn_SPSR_SPTEF (0x20u) +#define RSPIn_SPSR_TEND (0x40u) +#define RSPIn_SPSR_SPRF (0x80u) + +#define RSPIn_SPDR_UINT32 (0xFFFFFFFFuL) + +#define RSPIn_SPDR_UINT16 (0xFFFFu) + +#define RSPIn_SPDR_UINT8 (0xFFu) + +#define RSPIn_SPSCR_SPSLN (0x03u) + +#define RSPIn_SPSSR_SPCP (0x03u) + +#define RSPIn_SPBR_SPR (0xFFu) + +#define RSPIn_SPDCR_SPLW (0x60u) +#define RSPIn_SPDCR_TXDMY (0x80u) + +#define RSPIn_SPCKD_SCKDL (0x07u) + +#define RSPIn_SSLND_SLNDL (0x07u) + +#define RSPIn_SPND_SPNDL (0x07u) + +#define RSPIn_SPCMD0_CPHA (0x0001u) +#define RSPIn_SPCMD0_CPOL (0x0002u) +#define RSPIn_SPCMD0_BRDV (0x000Cu) +#define RSPIn_SPCMD0_SSLKP (0x0080u) +#define RSPIn_SPCMD0_SPB (0x0F00u) +#define RSPIn_SPCMD0_LSBF (0x1000u) +#define RSPIn_SPCMD0_SPNDEN (0x2000u) +#define RSPIn_SPCMD0_SLNDEN (0x4000u) +#define RSPIn_SPCMD0_SCKDEN (0x8000u) + +#define RSPIn_SPCMD1_CPHA (0x0001u) +#define RSPIn_SPCMD1_CPOL (0x0002u) +#define RSPIn_SPCMD1_BRDV (0x000Cu) +#define RSPIn_SPCMD1_SSLKP (0x0080u) +#define RSPIn_SPCMD1_SPB (0x0F00u) +#define RSPIn_SPCMD1_LSBF (0x1000u) +#define RSPIn_SPCMD1_SPNDEN (0x2000u) +#define RSPIn_SPCMD1_SLNDEN (0x4000u) +#define RSPIn_SPCMD1_SCKDEN (0x8000u) + +#define RSPIn_SPCMD2_CPHA (0x0001u) +#define RSPIn_SPCMD2_CPOL (0x0002u) +#define RSPIn_SPCMD2_BRDV (0x000Cu) +#define RSPIn_SPCMD2_SSLKP (0x0080u) +#define RSPIn_SPCMD2_SPB (0x0F00u) +#define RSPIn_SPCMD2_LSBF (0x1000u) +#define RSPIn_SPCMD2_SPNDEN (0x2000u) +#define RSPIn_SPCMD2_SLNDEN (0x4000u) +#define RSPIn_SPCMD2_SCKDEN (0x8000u) + +#define RSPIn_SPCMD3_CPHA (0x0001u) +#define RSPIn_SPCMD3_CPOL (0x0002u) +#define RSPIn_SPCMD3_BRDV (0x000Cu) +#define RSPIn_SPCMD3_SSLKP (0x0080u) +#define RSPIn_SPCMD3_SPB (0x0F00u) +#define RSPIn_SPCMD3_LSBF (0x1000u) +#define RSPIn_SPCMD3_SPNDEN (0x2000u) +#define RSPIn_SPCMD3_SLNDEN (0x4000u) +#define RSPIn_SPCMD3_SCKDEN (0x8000u) + +#define RSPIn_SPBFCR_RXTRG (0x07u) +#define RSPIn_SPBFCR_TXTRG (0x30u) +#define RSPIn_SPBFCR_RXRST (0x40u) +#define RSPIn_SPBFCR_TXRST (0x80u) + +#define RSPIn_SPBFDR_R (0x003Fu) +#define RSPIn_SPBFDR_T (0x0F00u) + + +/* ==== Shift values for IO registers ==== */ +#define RSPIn_SPCR_MODFEN_SHIFT (2u) +#define RSPIn_SPCR_MSTR_SHIFT (3u) +#define RSPIn_SPCR_SPEIE_SHIFT (4u) +#define RSPIn_SPCR_SPTIE_SHIFT (5u) +#define RSPIn_SPCR_SPE_SHIFT (6u) +#define RSPIn_SPCR_SPRIE_SHIFT (7u) + +#define RSPIn_SSLP_SSL0P_SHIFT (0u) + +#define RSPIn_SPPCR_SPLP_SHIFT (0u) +#define RSPIn_SPPCR_MOIFV_SHIFT (4u) +#define RSPIn_SPPCR_MOIFE_SHIFT (5u) + +#define RSPIn_SPSR_OVRF_SHIFT (0u) +#define RSPIn_SPSR_MODF_SHIFT (2u) +#define RSPIn_SPSR_SPTEF_SHIFT (5u) +#define RSPIn_SPSR_TEND_SHIFT (6u) +#define RSPIn_SPSR_SPRF_SHIFT (7u) + +#define RSPIn_SPDR_UINT32_SHIFT (0u) + +#define RSPIn_SPDR_UINT16_SHIFT (0u) + +#define RSPIn_SPDR_UINT8_SHIFT (0u) + +#define RSPIn_SPSCR_SPSLN_SHIFT (0u) + +#define RSPIn_SPSSR_SPCP_SHIFT (0u) + +#define RSPIn_SPBR_SPR_SHIFT (0u) + +#define RSPIn_SPDCR_SPLW_SHIFT (5u) +#define RSPIn_SPDCR_TXDMY_SHIFT (7u) + +#define RSPIn_SPCKD_SCKDL_SHIFT (0u) + +#define RSPIn_SSLND_SLNDL_SHIFT (0u) + +#define RSPIn_SPND_SPNDL_SHIFT (0u) + +#define RSPIn_SPCMD0_CPHA_SHIFT (0u) +#define RSPIn_SPCMD0_CPOL_SHIFT (1u) +#define RSPIn_SPCMD0_BRDV_SHIFT (2u) +#define RSPIn_SPCMD0_SSLKP_SHIFT (7u) +#define RSPIn_SPCMD0_SPB_SHIFT (8u) +#define RSPIn_SPCMD0_LSBF_SHIFT (12u) +#define RSPIn_SPCMD0_SPNDEN_SHIFT (13u) +#define RSPIn_SPCMD0_SLNDEN_SHIFT (14u) +#define RSPIn_SPCMD0_SCKDEN_SHIFT (15u) + +#define RSPIn_SPCMD1_CPHA_SHIFT (0u) +#define RSPIn_SPCMD1_CPOL_SHIFT (1u) +#define RSPIn_SPCMD1_BRDV_SHIFT (2u) +#define RSPIn_SPCMD1_SSLKP_SHIFT (7u) +#define RSPIn_SPCMD1_SPB_SHIFT (8u) +#define RSPIn_SPCMD1_LSBF_SHIFT (12u) +#define RSPIn_SPCMD1_SPNDEN_SHIFT (13u) +#define RSPIn_SPCMD1_SLNDEN_SHIFT (14u) +#define RSPIn_SPCMD1_SCKDEN_SHIFT (15u) + +#define RSPIn_SPCMD2_CPHA_SHIFT (0u) +#define RSPIn_SPCMD2_CPOL_SHIFT (1u) +#define RSPIn_SPCMD2_BRDV_SHIFT (2u) +#define RSPIn_SPCMD2_SSLKP_SHIFT (7u) +#define RSPIn_SPCMD2_SPB_SHIFT (8u) +#define RSPIn_SPCMD2_LSBF_SHIFT (12u) +#define RSPIn_SPCMD2_SPNDEN_SHIFT (13u) +#define RSPIn_SPCMD2_SLNDEN_SHIFT (14u) +#define RSPIn_SPCMD2_SCKDEN_SHIFT (15u) + +#define RSPIn_SPCMD3_CPHA_SHIFT (0u) +#define RSPIn_SPCMD3_CPOL_SHIFT (1u) +#define RSPIn_SPCMD3_BRDV_SHIFT (2u) +#define RSPIn_SPCMD3_SSLKP_SHIFT (7u) +#define RSPIn_SPCMD3_SPB_SHIFT (8u) +#define RSPIn_SPCMD3_LSBF_SHIFT (12u) +#define RSPIn_SPCMD3_SPNDEN_SHIFT (13u) +#define RSPIn_SPCMD3_SLNDEN_SHIFT (14u) +#define RSPIn_SPCMD3_SCKDEN_SHIFT (15u) + +#define RSPIn_SPBFCR_RXTRG_SHIFT (0u) +#define RSPIn_SPBFCR_TXTRG_SHIFT (4u) +#define RSPIn_SPBFCR_RXRST_SHIFT (6u) +#define RSPIn_SPBFCR_TXRST_SHIFT (7u) + +#define RSPIn_SPBFDR_R_SHIFT (0u) +#define RSPIn_SPBFDR_T_SHIFT (8u) + + +#endif /* RSPI_IOBITMASK_H */ + +/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/scif_iobitmask.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,1065 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : scif_iobitmask.h +* $Rev: 1115 $ +* $Date:: 2014-07-09 15:35:02 +0900#$ +* Description : SCIF register define header +*******************************************************************************/ +#ifndef SCIF_IOBITMASK_H +#define SCIF_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ +/* ---- SCIF0 ---- */ +#define SCIF0_SCSMR_CKS (0x0003u) +#define SCIF0_SCSMR_STOP (0x0008u) +#define SCIF0_SCSMR_OE (0x0010u) +#define SCIF0_SCSMR_PE (0x0020u) +#define SCIF0_SCSMR_CHR (0x0040u) +#define SCIF0_SCSMR_CA (0x0080u) + +#define SCIF0_SCBRR_D (0xFFu) + +#define SCIF0_SCSCR_CKE (0x0003u) +#define SCIF0_SCSCR_REIE (0x0008u) +#define SCIF0_SCSCR_RE (0x0010u) +#define SCIF0_SCSCR_TE (0x0020u) +#define SCIF0_SCSCR_RIE (0x0040u) +#define SCIF0_SCSCR_TIE (0x0080u) + +#define SCIF0_SCFTDR_D (0xFFu) + +#define SCIF0_SCFSR_DR (0x0001u) +#define SCIF0_SCFSR_RDF (0x0002u) +#define SCIF0_SCFSR_PER (0x0004u) +#define SCIF0_SCFSR_FER (0x0008u) +#define SCIF0_SCFSR_BRK (0x0010u) +#define SCIF0_SCFSR_TDFE (0x0020u) +#define SCIF0_SCFSR_TEND (0x0040u) +#define SCIF0_SCFSR_ER (0x0080u) +#define SCIF0_SCFSR_FERN (0x0F00u) +#define SCIF0_SCFSR_PERN (0xF000u) + +#define SCIF0_SCFRDR_D (0xFFu) + +#define SCIF0_SCFCR_LOOP (0x0001u) +#define SCIF0_SCFCR_RFRST (0x0002u) +#define SCIF0_SCFCR_TFRST (0x0004u) +#define SCIF0_SCFCR_MCE (0x0008u) +#define SCIF0_SCFCR_TTRG (0x0030u) +#define SCIF0_SCFCR_RTRG (0x00C0u) +#define SCIF0_SCFCR_RSTRG (0x0700u) + +#define SCIF0_SCFDR_R (0x001Fu) +#define SCIF0_SCFDR_T (0x1F00u) + +#define SCIF0_SCSPTR_SPB2DT (0x0001u) +#define SCIF0_SCSPTR_SPB2IO (0x0002u) +#define SCIF0_SCSPTR_SCKDT (0x0004u) +#define SCIF0_SCSPTR_SCKIO (0x0008u) +#define SCIF0_SCSPTR_CTSDT (0x0010u) +#define SCIF0_SCSPTR_CTSIO (0x0020u) +#define SCIF0_SCSPTR_RTSDT (0x0040u) +#define SCIF0_SCSPTR_RTSIO (0x0080u) + +#define SCIF0_SCLSR_ORER (0x0001u) + +#define SCIF0_SCEMR_ABCS (0x0001u) +#define SCIF0_SCEMR_BGDM (0x0080u) + +/* ---- SCIF1 ---- */ +#define SCIF1_SCSMR_CKS (0x0003u) +#define SCIF1_SCSMR_STOP (0x0008u) +#define SCIF1_SCSMR_OE (0x0010u) +#define SCIF1_SCSMR_PE (0x0020u) +#define SCIF1_SCSMR_CHR (0x0040u) +#define SCIF1_SCSMR_CA (0x0080u) + +#define SCIF1_SCBRR_D (0xFFu) + +#define SCIF1_SCSCR_CKE (0x0003u) +#define SCIF1_SCSCR_REIE (0x0008u) +#define SCIF1_SCSCR_RE (0x0010u) +#define SCIF1_SCSCR_TE (0x0020u) +#define SCIF1_SCSCR_RIE (0x0040u) +#define SCIF1_SCSCR_TIE (0x0080u) + +#define SCIF1_SCFTDR_D (0xFFu) + +#define SCIF1_SCFSR_DR (0x0001u) +#define SCIF1_SCFSR_RDF (0x0002u) +#define SCIF1_SCFSR_PER (0x0004u) +#define SCIF1_SCFSR_FER (0x0008u) +#define SCIF1_SCFSR_BRK (0x0010u) +#define SCIF1_SCFSR_TDFE (0x0020u) +#define SCIF1_SCFSR_TEND (0x0040u) +#define SCIF1_SCFSR_ER (0x0080u) +#define SCIF1_SCFSR_FERN (0x0F00u) +#define SCIF1_SCFSR_PERN (0xF000u) + +#define SCIF1_SCFRDR_D (0xFFu) + +#define SCIF1_SCFCR_LOOP (0x0001u) +#define SCIF1_SCFCR_RFRST (0x0002u) +#define SCIF1_SCFCR_TFRST (0x0004u) +#define SCIF1_SCFCR_MCE (0x0008u) +#define SCIF1_SCFCR_TTRG (0x0030u) +#define SCIF1_SCFCR_RTRG (0x00C0u) +#define SCIF1_SCFCR_RSTRG (0x0700u) + +#define SCIF1_SCFDR_R (0x001Fu) +#define SCIF1_SCFDR_T (0x1F00u) + +#define SCIF1_SCSPTR_SPB2DT (0x0001u) +#define SCIF1_SCSPTR_SPB2IO (0x0002u) +#define SCIF1_SCSPTR_SCKDT (0x0004u) +#define SCIF1_SCSPTR_SCKIO (0x0008u) +#define SCIF1_SCSPTR_CTSDT (0x0010u) +#define SCIF1_SCSPTR_CTSIO (0x0020u) +#define SCIF1_SCSPTR_RTSDT (0x0040u) +#define SCIF1_SCSPTR_RTSIO (0x0080u) + +#define SCIF1_SCLSR_ORER (0x0001u) + +#define SCIF1_SCEMR_ABCS (0x0001u) +#define SCIF1_SCEMR_BGDM (0x0080u) + +/* ---- SCIF2 ---- */ +#define SCIF2_SCSMR_CKS (0x0003u) +#define SCIF2_SCSMR_STOP (0x0008u) +#define SCIF2_SCSMR_OE (0x0010u) +#define SCIF2_SCSMR_PE (0x0020u) +#define SCIF2_SCSMR_CHR (0x0040u) +#define SCIF2_SCSMR_CA (0x0080u) + +#define SCIF2_SCBRR_D (0xFFu) + +#define SCIF2_SCSCR_CKE (0x0003u) +#define SCIF2_SCSCR_REIE (0x0008u) +#define SCIF2_SCSCR_RE (0x0010u) +#define SCIF2_SCSCR_TE (0x0020u) +#define SCIF2_SCSCR_RIE (0x0040u) +#define SCIF2_SCSCR_TIE (0x0080u) + +#define SCIF2_SCFTDR_D (0xFFu) + +#define SCIF2_SCFSR_DR (0x0001u) +#define SCIF2_SCFSR_RDF (0x0002u) +#define SCIF2_SCFSR_PER (0x0004u) +#define SCIF2_SCFSR_FER (0x0008u) +#define SCIF2_SCFSR_BRK (0x0010u) +#define SCIF2_SCFSR_TDFE (0x0020u) +#define SCIF2_SCFSR_TEND (0x0040u) +#define SCIF2_SCFSR_ER (0x0080u) +#define SCIF2_SCFSR_FERN (0x0F00u) +#define SCIF2_SCFSR_PERN (0xF000u) + +#define SCIF2_SCFRDR_D (0xFFu) + +#define SCIF2_SCFCR_LOOP (0x0001u) +#define SCIF2_SCFCR_RFRST (0x0002u) +#define SCIF2_SCFCR_TFRST (0x0004u) +#define SCIF2_SCFCR_MCE (0x0008u) +#define SCIF2_SCFCR_TTRG (0x0030u) +#define SCIF2_SCFCR_RTRG (0x00C0u) +#define SCIF2_SCFCR_RSTRG (0x0700u) + +#define SCIF2_SCFDR_R (0x001Fu) +#define SCIF2_SCFDR_T (0x1F00u) + +#define SCIF2_SCSPTR_SPB2DT (0x0001u) +#define SCIF2_SCSPTR_SPB2IO (0x0002u) +#define SCIF2_SCSPTR_SCKDT (0x0004u) +#define SCIF2_SCSPTR_SCKIO (0x0008u) +#define SCIF2_SCSPTR_CTSDT (0x0010u) +#define SCIF2_SCSPTR_CTSIO (0x0020u) +#define SCIF2_SCSPTR_RTSDT (0x0040u) +#define SCIF2_SCSPTR_RTSIO (0x0080u) + +#define SCIF2_SCLSR_ORER (0x0001u) + +#define SCIF2_SCEMR_ABCS (0x0001u) +#define SCIF2_SCEMR_BGDM (0x0080u) + +/* ---- SCIF3 ---- */ +#define SCIF3_SCSMR_CKS (0x0003u) +#define SCIF3_SCSMR_STOP (0x0008u) +#define SCIF3_SCSMR_OE (0x0010u) +#define SCIF3_SCSMR_PE (0x0020u) +#define SCIF3_SCSMR_CHR (0x0040u) +#define SCIF3_SCSMR_CA (0x0080u) + +#define SCIF3_SCBRR_D (0xFFu) + +#define SCIF3_SCSCR_CKE (0x0003u) +#define SCIF3_SCSCR_REIE (0x0008u) +#define SCIF3_SCSCR_RE (0x0010u) +#define SCIF3_SCSCR_TE (0x0020u) +#define SCIF3_SCSCR_RIE (0x0040u) +#define SCIF3_SCSCR_TIE (0x0080u) + +#define SCIF3_SCFTDR_D (0xFFu) + +#define SCIF3_SCFSR_DR (0x0001u) +#define SCIF3_SCFSR_RDF (0x0002u) +#define SCIF3_SCFSR_PER (0x0004u) +#define SCIF3_SCFSR_FER (0x0008u) +#define SCIF3_SCFSR_BRK (0x0010u) +#define SCIF3_SCFSR_TDFE (0x0020u) +#define SCIF3_SCFSR_TEND (0x0040u) +#define SCIF3_SCFSR_ER (0x0080u) +#define SCIF3_SCFSR_FERN (0x0F00u) +#define SCIF3_SCFSR_PERN (0xF000u) + +#define SCIF3_SCFRDR_D (0xFFu) + +#define SCIF3_SCFCR_LOOP (0x0001u) +#define SCIF3_SCFCR_RFRST (0x0002u) +#define SCIF3_SCFCR_TFRST (0x0004u) +#define SCIF3_SCFCR_MCE (0x0008u) +#define SCIF3_SCFCR_TTRG (0x0030u) +#define SCIF3_SCFCR_RTRG (0x00C0u) +#define SCIF3_SCFCR_RSTRG (0x0700u) + +#define SCIF3_SCFDR_R (0x001Fu) +#define SCIF3_SCFDR_T (0x1F00u) + +#define SCIF3_SCSPTR_SPB2DT (0x0001u) +#define SCIF3_SCSPTR_SPB2IO (0x0002u) +#define SCIF3_SCSPTR_SCKDT (0x0004u) +#define SCIF3_SCSPTR_SCKIO (0x0008u) +#define SCIF3_SCSPTR_CTSDT (0x0010u) +#define SCIF3_SCSPTR_CTSIO (0x0020u) +#define SCIF3_SCSPTR_RTSDT (0x0040u) +#define SCIF3_SCSPTR_RTSIO (0x0080u) + +#define SCIF3_SCLSR_ORER (0x0001u) + +#define SCIF3_SCEMR_ABCS (0x0001u) +#define SCIF3_SCEMR_BGDM (0x0080u) + +/* ---- SCIF4 ---- */ +#define SCIF4_SCSMR_CKS (0x0003u) +#define SCIF4_SCSMR_STOP (0x0008u) +#define SCIF4_SCSMR_OE (0x0010u) +#define SCIF4_SCSMR_PE (0x0020u) +#define SCIF4_SCSMR_CHR (0x0040u) +#define SCIF4_SCSMR_CA (0x0080u) + +#define SCIF4_SCBRR_D (0xFFu) + +#define SCIF4_SCSCR_CKE (0x0003u) +#define SCIF4_SCSCR_REIE (0x0008u) +#define SCIF4_SCSCR_RE (0x0010u) +#define SCIF4_SCSCR_TE (0x0020u) +#define SCIF4_SCSCR_RIE (0x0040u) +#define SCIF4_SCSCR_TIE (0x0080u) + +#define SCIF4_SCFTDR_D (0xFFu) + +#define SCIF4_SCFSR_DR (0x0001u) +#define SCIF4_SCFSR_RDF (0x0002u) +#define SCIF4_SCFSR_PER (0x0004u) +#define SCIF4_SCFSR_FER (0x0008u) +#define SCIF4_SCFSR_BRK (0x0010u) +#define SCIF4_SCFSR_TDFE (0x0020u) +#define SCIF4_SCFSR_TEND (0x0040u) +#define SCIF4_SCFSR_ER (0x0080u) +#define SCIF4_SCFSR_FERN (0x0F00u) +#define SCIF4_SCFSR_PERN (0xF000u) + +#define SCIF4_SCFRDR_D (0xFFu) + +#define SCIF4_SCFCR_LOOP (0x0001u) +#define SCIF4_SCFCR_RFRST (0x0002u) +#define SCIF4_SCFCR_TFRST (0x0004u) +#define SCIF4_SCFCR_MCE (0x0008u) +#define SCIF4_SCFCR_TTRG (0x0030u) +#define SCIF4_SCFCR_RTRG (0x00C0u) +#define SCIF4_SCFCR_RSTRG (0x0700u) + +#define SCIF4_SCFDR_R (0x001Fu) +#define SCIF4_SCFDR_T (0x1F00u) + +#define SCIF4_SCSPTR_SPB2DT (0x0001u) +#define SCIF4_SCSPTR_SPB2IO (0x0002u) +#define SCIF4_SCSPTR_SCKDT (0x0004u) +#define SCIF4_SCSPTR_SCKIO (0x0008u) +#define SCIF4_SCSPTR_CTSDT (0x0010u) +#define SCIF4_SCSPTR_CTSIO (0x0020u) +#define SCIF4_SCSPTR_RTSDT (0x0040u) +#define SCIF4_SCSPTR_RTSIO (0x0080u) + +#define SCIF4_SCLSR_ORER (0x0001u) + +#define SCIF4_SCEMR_ABCS (0x0001u) +#define SCIF4_SCEMR_BGDM (0x0080u) + +/* ---- SCIF5 ---- */ +#define SCIF5_SCSMR_CKS (0x0003u) +#define SCIF5_SCSMR_STOP (0x0008u) +#define SCIF5_SCSMR_OE (0x0010u) +#define SCIF5_SCSMR_PE (0x0020u) +#define SCIF5_SCSMR_CHR (0x0040u) +#define SCIF5_SCSMR_CA (0x0080u) + +#define SCIF5_SCBRR_D (0xFFu) + +#define SCIF5_SCSCR_CKE (0x0003u) +#define SCIF5_SCSCR_REIE (0x0008u) +#define SCIF5_SCSCR_RE (0x0010u) +#define SCIF5_SCSCR_TE (0x0020u) +#define SCIF5_SCSCR_RIE (0x0040u) +#define SCIF5_SCSCR_TIE (0x0080u) + +#define SCIF5_SCFTDR_D (0xFFu) + +#define SCIF5_SCFSR_DR (0x0001u) +#define SCIF5_SCFSR_RDF (0x0002u) +#define SCIF5_SCFSR_PER (0x0004u) +#define SCIF5_SCFSR_FER (0x0008u) +#define SCIF5_SCFSR_BRK (0x0010u) +#define SCIF5_SCFSR_TDFE (0x0020u) +#define SCIF5_SCFSR_TEND (0x0040u) +#define SCIF5_SCFSR_ER (0x0080u) +#define SCIF5_SCFSR_FERN (0x0F00u) +#define SCIF5_SCFSR_PERN (0xF000u) + +#define SCIF5_SCFRDR_D (0xFFu) + +#define SCIF5_SCFCR_LOOP (0x0001u) +#define SCIF5_SCFCR_RFRST (0x0002u) +#define SCIF5_SCFCR_TFRST (0x0004u) +#define SCIF5_SCFCR_MCE (0x0008u) +#define SCIF5_SCFCR_TTRG (0x0030u) +#define SCIF5_SCFCR_RTRG (0x00C0u) +#define SCIF5_SCFCR_RSTRG (0x0700u) + +#define SCIF5_SCFDR_R (0x001Fu) +#define SCIF5_SCFDR_T (0x1F00u) + +#define SCIF5_SCSPTR_SPB2DT (0x0001u) +#define SCIF5_SCSPTR_SPB2IO (0x0002u) +#define SCIF5_SCSPTR_SCKDT (0x0004u) +#define SCIF5_SCSPTR_SCKIO (0x0008u) +#define SCIF5_SCSPTR_CTSDT (0x0010u) +#define SCIF5_SCSPTR_CTSIO (0x0020u) +#define SCIF5_SCSPTR_RTSDT (0x0040u) +#define SCIF5_SCSPTR_RTSIO (0x0080u) + +#define SCIF5_SCLSR_ORER (0x0001u) + +#define SCIF5_SCEMR_ABCS (0x0001u) +#define SCIF5_SCEMR_BGDM (0x0080u) + +/* ---- SCIF6 ---- */ +#define SCIF6_SCSMR_CKS (0x0003u) +#define SCIF6_SCSMR_STOP (0x0008u) +#define SCIF6_SCSMR_OE (0x0010u) +#define SCIF6_SCSMR_PE (0x0020u) +#define SCIF6_SCSMR_CHR (0x0040u) +#define SCIF6_SCSMR_CA (0x0080u) + +#define SCIF6_SCBRR_D (0xFFu) + +#define SCIF6_SCSCR_CKE (0x0003u) +#define SCIF6_SCSCR_REIE (0x0008u) +#define SCIF6_SCSCR_RE (0x0010u) +#define SCIF6_SCSCR_TE (0x0020u) +#define SCIF6_SCSCR_RIE (0x0040u) +#define SCIF6_SCSCR_TIE (0x0080u) + +#define SCIF6_SCFTDR_D (0xFFu) + +#define SCIF6_SCFSR_DR (0x0001u) +#define SCIF6_SCFSR_RDF (0x0002u) +#define SCIF6_SCFSR_PER (0x0004u) +#define SCIF6_SCFSR_FER (0x0008u) +#define SCIF6_SCFSR_BRK (0x0010u) +#define SCIF6_SCFSR_TDFE (0x0020u) +#define SCIF6_SCFSR_TEND (0x0040u) +#define SCIF6_SCFSR_ER (0x0080u) +#define SCIF6_SCFSR_FERN (0x0F00u) +#define SCIF6_SCFSR_PERN (0xF000u) + +#define SCIF6_SCFRDR_D (0xFFu) + +#define SCIF6_SCFCR_LOOP (0x0001u) +#define SCIF6_SCFCR_RFRST (0x0002u) +#define SCIF6_SCFCR_TFRST (0x0004u) +#define SCIF6_SCFCR_MCE (0x0008u) +#define SCIF6_SCFCR_TTRG (0x0030u) +#define SCIF6_SCFCR_RTRG (0x00C0u) +#define SCIF6_SCFCR_RSTRG (0x0700u) + +#define SCIF6_SCFDR_R (0x001Fu) +#define SCIF6_SCFDR_T (0x1F00u) + +#define SCIF6_SCSPTR_SPB2DT (0x0001u) +#define SCIF6_SCSPTR_SPB2IO (0x0002u) +#define SCIF6_SCSPTR_SCKDT (0x0004u) +#define SCIF6_SCSPTR_SCKIO (0x0008u) +#define SCIF6_SCSPTR_CTSDT (0x0010u) +#define SCIF6_SCSPTR_CTSIO (0x0020u) +#define SCIF6_SCSPTR_RTSDT (0x0040u) +#define SCIF6_SCSPTR_RTSIO (0x0080u) + +#define SCIF6_SCLSR_ORER (0x0001u) + +#define SCIF6_SCEMR_ABCS (0x0001u) +#define SCIF6_SCEMR_BGDM (0x0080u) + +/* ---- SCIF7 ---- */ +#define SCIF7_SCSMR_CKS (0x0003u) +#define SCIF7_SCSMR_STOP (0x0008u) +#define SCIF7_SCSMR_OE (0x0010u) +#define SCIF7_SCSMR_PE (0x0020u) +#define SCIF7_SCSMR_CHR (0x0040u) +#define SCIF7_SCSMR_CA (0x0080u) + +#define SCIF7_SCBRR_D (0xFFu) + +#define SCIF7_SCSCR_CKE (0x0003u) +#define SCIF7_SCSCR_REIE (0x0008u) +#define SCIF7_SCSCR_RE (0x0010u) +#define SCIF7_SCSCR_TE (0x0020u) +#define SCIF7_SCSCR_RIE (0x0040u) +#define SCIF7_SCSCR_TIE (0x0080u) + +#define SCIF7_SCFTDR_D (0xFFu) + +#define SCIF7_SCFSR_DR (0x0001u) +#define SCIF7_SCFSR_RDF (0x0002u) +#define SCIF7_SCFSR_PER (0x0004u) +#define SCIF7_SCFSR_FER (0x0008u) +#define SCIF7_SCFSR_BRK (0x0010u) +#define SCIF7_SCFSR_TDFE (0x0020u) +#define SCIF7_SCFSR_TEND (0x0040u) +#define SCIF7_SCFSR_ER (0x0080u) +#define SCIF7_SCFSR_FERN (0x0F00u) +#define SCIF7_SCFSR_PERN (0xF000u) + +#define SCIF7_SCFRDR_D (0xFFu) + +#define SCIF7_SCFCR_LOOP (0x0001u) +#define SCIF7_SCFCR_RFRST (0x0002u) +#define SCIF7_SCFCR_TFRST (0x0004u) +#define SCIF7_SCFCR_MCE (0x0008u) +#define SCIF7_SCFCR_TTRG (0x0030u) +#define SCIF7_SCFCR_RTRG (0x00C0u) +#define SCIF7_SCFCR_RSTRG (0x0700u) + +#define SCIF7_SCFDR_R (0x001Fu) +#define SCIF7_SCFDR_T (0x1F00u) + +#define SCIF7_SCSPTR_SPB2DT (0x0001u) +#define SCIF7_SCSPTR_SPB2IO (0x0002u) +#define SCIF7_SCSPTR_SCKDT (0x0004u) +#define SCIF7_SCSPTR_SCKIO (0x0008u) +#define SCIF7_SCSPTR_CTSDT (0x0010u) +#define SCIF7_SCSPTR_CTSIO (0x0020u) +#define SCIF7_SCSPTR_RTSDT (0x0040u) +#define SCIF7_SCSPTR_RTSIO (0x0080u) + +#define SCIF7_SCLSR_ORER (0x0001u) + +#define SCIF7_SCEMR_ABCS (0x0001u) +#define SCIF7_SCEMR_BGDM (0x0080u) + +/* ---- SCIFn ---- */ +#define SCIFn_SCSMR_CKS (0x0003u) +#define SCIFn_SCSMR_STOP (0x0008u) +#define SCIFn_SCSMR_OE (0x0010u) +#define SCIFn_SCSMR_PE (0x0020u) +#define SCIFn_SCSMR_CHR (0x0040u) +#define SCIFn_SCSMR_CA (0x0080u) + +#define SCIFn_SCBRR_D (0xFFu) + +#define SCIFn_SCSCR_CKE (0x0003u) +#define SCIFn_SCSCR_REIE (0x0008u) +#define SCIFn_SCSCR_RE (0x0010u) +#define SCIFn_SCSCR_TE (0x0020u) +#define SCIFn_SCSCR_RIE (0x0040u) +#define SCIFn_SCSCR_TIE (0x0080u) + +#define SCIFn_SCFTDR_D (0xFFu) + +#define SCIFn_SCFSR_DR (0x0001u) +#define SCIFn_SCFSR_RDF (0x0002u) +#define SCIFn_SCFSR_PER (0x0004u) +#define SCIFn_SCFSR_FER (0x0008u) +#define SCIFn_SCFSR_BRK (0x0010u) +#define SCIFn_SCFSR_TDFE (0x0020u) +#define SCIFn_SCFSR_TEND (0x0040u) +#define SCIFn_SCFSR_ER (0x0080u) +#define SCIFn_SCFSR_FERN (0x0F00u) +#define SCIFn_SCFSR_PERN (0xF000u) + +#define SCIFn_SCFRDR_D (0xFFu) + +#define SCIFn_SCFCR_LOOP (0x0001u) +#define SCIFn_SCFCR_RFRST (0x0002u) +#define SCIFn_SCFCR_TFRST (0x0004u) +#define SCIFn_SCFCR_MCE (0x0008u) +#define SCIFn_SCFCR_TTRG (0x0030u) +#define SCIFn_SCFCR_RTRG (0x00C0u) +#define SCIFn_SCFCR_RSTRG (0x0700u) + +#define SCIFn_SCFDR_R (0x001Fu) +#define SCIFn_SCFDR_T (0x1F00u) + +#define SCIFn_SCSPTR_SPB2DT (0x0001u) +#define SCIFn_SCSPTR_SPB2IO (0x0002u) +#define SCIFn_SCSPTR_SCKDT (0x0004u) +#define SCIFn_SCSPTR_SCKIO (0x0008u) +#define SCIFn_SCSPTR_CTSDT (0x0010u) +#define SCIFn_SCSPTR_CTSIO (0x0020u) +#define SCIFn_SCSPTR_RTSDT (0x0040u) +#define SCIFn_SCSPTR_RTSIO (0x0080u) + +#define SCIFn_SCLSR_ORER (0x0001u) + +#define SCIFn_SCEMR_ABCS (0x0001u) +#define SCIFn_SCEMR_BGDM (0x0080u) + + +/* ==== Shift values for IO registers ==== */ +/* ---- SCIF0 ---- */ +#define SCIF0_SCSMR_CKS_SHIFT (0u) +#define SCIF0_SCSMR_STOP_SHIFT (3u) +#define SCIF0_SCSMR_OE_SHIFT (4u) +#define SCIF0_SCSMR_PE_SHIFT (5u) +#define SCIF0_SCSMR_CHR_SHIFT (6u) +#define SCIF0_SCSMR_CA_SHIFT (7u) + +#define SCIF0_SCBRR_D_SHIFT (0u) + +#define SCIF0_SCSCR_CKE_SHIFT (0u) +#define SCIF0_SCSCR_REIE_SHIFT (3u) +#define SCIF0_SCSCR_RE_SHIFT (4u) +#define SCIF0_SCSCR_TE_SHIFT (5u) +#define SCIF0_SCSCR_RIE_SHIFT (6u) +#define SCIF0_SCSCR_TIE_SHIFT (7u) + +#define SCIF0_SCFTDR_D_SHIFT (0u) + +#define SCIF0_SCFSR_DR_SHIFT (0u) +#define SCIF0_SCFSR_RDF_SHIFT (1u) +#define SCIF0_SCFSR_PER_SHIFT (2u) +#define SCIF0_SCFSR_FER_SHIFT (3u) +#define SCIF0_SCFSR_BRK_SHIFT (4u) +#define SCIF0_SCFSR_TDFE_SHIFT (5u) +#define SCIF0_SCFSR_TEND_SHIFT (6u) +#define SCIF0_SCFSR_ER_SHIFT (7u) +#define SCIF0_SCFSR_FERN_SHIFT (8u) +#define SCIF0_SCFSR_PERN_SHIFT (12u) + +#define SCIF0_SCFRDR_D_SHIFT (0u) + +#define SCIF0_SCFCR_LOOP_SHIFT (0u) +#define SCIF0_SCFCR_RFRST_SHIFT (1u) +#define SCIF0_SCFCR_TFRST_SHIFT (2u) +#define SCIF0_SCFCR_MCE_SHIFT (3u) +#define SCIF0_SCFCR_TTRG_SHIFT (4u) +#define SCIF0_SCFCR_RTRG_SHIFT (6u) +#define SCIF0_SCFCR_RSTRG_SHIFT (8u) + +#define SCIF0_SCFDR_R_SHIFT (0u) +#define SCIF0_SCFDR_T_SHIFT (8u) + +#define SCIF0_SCSPTR_SPB2DT_SHIFT (0u) +#define SCIF0_SCSPTR_SPB2IO_SHIFT (1u) +#define SCIF0_SCSPTR_SCKDT_SHIFT (2u) +#define SCIF0_SCSPTR_SCKIO_SHIFT (3u) +#define SCIF0_SCSPTR_CTSDT_SHIFT (4u) +#define SCIF0_SCSPTR_CTSIO_SHIFT (5u) +#define SCIF0_SCSPTR_RTSDT_SHIFT (6u) +#define SCIF0_SCSPTR_RTSIO_SHIFT (7u) + +#define SCIF0_SCLSR_ORER_SHIFT (0u) + +#define SCIF0_SCEMR_ABCS_SHIFT (0u) +#define SCIF0_SCEMR_BGDM_SHIFT (7u) + +/* ---- SCIF1 ---- */ +#define SCIF1_SCSMR_CKS_SHIFT (0u) +#define SCIF1_SCSMR_STOP_SHIFT (3u) +#define SCIF1_SCSMR_OE_SHIFT (4u) +#define SCIF1_SCSMR_PE_SHIFT (5u) +#define SCIF1_SCSMR_CHR_SHIFT (6u) +#define SCIF1_SCSMR_CA_SHIFT (7u) + +#define SCIF1_SCBRR_D_SHIFT (0u) + +#define SCIF1_SCSCR_CKE_SHIFT (0u) +#define SCIF1_SCSCR_REIE_SHIFT (3u) +#define SCIF1_SCSCR_RE_SHIFT (4u) +#define SCIF1_SCSCR_TE_SHIFT (5u) +#define SCIF1_SCSCR_RIE_SHIFT (6u) +#define SCIF1_SCSCR_TIE_SHIFT (7u) + +#define SCIF1_SCFTDR_D_SHIFT (0u) + +#define SCIF1_SCFSR_DR_SHIFT (0u) +#define SCIF1_SCFSR_RDF_SHIFT (1u) +#define SCIF1_SCFSR_PER_SHIFT (2u) +#define SCIF1_SCFSR_FER_SHIFT (3u) +#define SCIF1_SCFSR_BRK_SHIFT (4u) +#define SCIF1_SCFSR_TDFE_SHIFT (5u) +#define SCIF1_SCFSR_TEND_SHIFT (6u) +#define SCIF1_SCFSR_ER_SHIFT (7u) +#define SCIF1_SCFSR_FERN_SHIFT (8u) +#define SCIF1_SCFSR_PERN_SHIFT (12u) + +#define SCIF1_SCFRDR_D_SHIFT (0u) + +#define SCIF1_SCFCR_LOOP_SHIFT (0u) +#define SCIF1_SCFCR_RFRST_SHIFT (1u) +#define SCIF1_SCFCR_TFRST_SHIFT (2u) +#define SCIF1_SCFCR_MCE_SHIFT (3u) +#define SCIF1_SCFCR_TTRG_SHIFT (4u) +#define SCIF1_SCFCR_RTRG_SHIFT (6u) +#define SCIF1_SCFCR_RSTRG_SHIFT (8u) + +#define SCIF1_SCFDR_R_SHIFT (0u) +#define SCIF1_SCFDR_T_SHIFT (8u) + +#define SCIF1_SCSPTR_SPB2DT_SHIFT (0u) +#define SCIF1_SCSPTR_SPB2IO_SHIFT (1u) +#define SCIF1_SCSPTR_SCKDT_SHIFT (2u) +#define SCIF1_SCSPTR_SCKIO_SHIFT (3u) +#define SCIF1_SCSPTR_CTSDT_SHIFT (4u) +#define SCIF1_SCSPTR_CTSIO_SHIFT (5u) +#define SCIF1_SCSPTR_RTSDT_SHIFT (6u) +#define SCIF1_SCSPTR_RTSIO_SHIFT (7u) + +#define SCIF1_SCLSR_ORER_SHIFT (0u) + +#define SCIF1_SCEMR_ABCS_SHIFT (0u) +#define SCIF1_SCEMR_BGDM_SHIFT (7u) + +/* ---- SCIF2 ---- */ +#define SCIF2_SCSMR_CKS_SHIFT (0u) +#define SCIF2_SCSMR_STOP_SHIFT (3u) +#define SCIF2_SCSMR_OE_SHIFT (4u) +#define SCIF2_SCSMR_PE_SHIFT (5u) +#define SCIF2_SCSMR_CHR_SHIFT (6u) +#define SCIF2_SCSMR_CA_SHIFT (7u) + +#define SCIF2_SCBRR_D_SHIFT (0u) + +#define SCIF2_SCSCR_CKE_SHIFT (0u) +#define SCIF2_SCSCR_REIE_SHIFT (3u) +#define SCIF2_SCSCR_RE_SHIFT (4u) +#define SCIF2_SCSCR_TE_SHIFT (5u) +#define SCIF2_SCSCR_RIE_SHIFT (6u) +#define SCIF2_SCSCR_TIE_SHIFT (7u) + +#define SCIF2_SCFTDR_D_SHIFT (0u) + +#define SCIF2_SCFSR_DR_SHIFT (0u) +#define SCIF2_SCFSR_RDF_SHIFT (1u) +#define SCIF2_SCFSR_PER_SHIFT (2u) +#define SCIF2_SCFSR_FER_SHIFT (3u) +#define SCIF2_SCFSR_BRK_SHIFT (4u) +#define SCIF2_SCFSR_TDFE_SHIFT (5u) +#define SCIF2_SCFSR_TEND_SHIFT (6u) +#define SCIF2_SCFSR_ER_SHIFT (7u) +#define SCIF2_SCFSR_FERN_SHIFT (8u) +#define SCIF2_SCFSR_PERN_SHIFT (12u) + +#define SCIF2_SCFRDR_D_SHIFT (0u) + +#define SCIF2_SCFCR_LOOP_SHIFT (0u) +#define SCIF2_SCFCR_RFRST_SHIFT (1u) +#define SCIF2_SCFCR_TFRST_SHIFT (2u) +#define SCIF2_SCFCR_MCE_SHIFT (3u) +#define SCIF2_SCFCR_TTRG_SHIFT (4u) +#define SCIF2_SCFCR_RTRG_SHIFT (6u) +#define SCIF2_SCFCR_RSTRG_SHIFT (8u) + +#define SCIF2_SCFDR_R_SHIFT (0u) +#define SCIF2_SCFDR_T_SHIFT (8u) + +#define SCIF2_SCSPTR_SPB2DT_SHIFT (0u) +#define SCIF2_SCSPTR_SPB2IO_SHIFT (1u) +#define SCIF2_SCSPTR_SCKDT_SHIFT (2u) +#define SCIF2_SCSPTR_SCKIO_SHIFT (3u) +#define SCIF2_SCSPTR_CTSDT_SHIFT (4u) +#define SCIF2_SCSPTR_CTSIO_SHIFT (5u) +#define SCIF2_SCSPTR_RTSDT_SHIFT (6u) +#define SCIF2_SCSPTR_RTSIO_SHIFT (7u) + +#define SCIF2_SCLSR_ORER_SHIFT (0u) + +#define SCIF2_SCEMR_ABCS_SHIFT (0u) +#define SCIF2_SCEMR_BGDM_SHIFT (7u) + +/* ---- SCIF3 ---- */ +#define SCIF3_SCSMR_CKS_SHIFT (0u) +#define SCIF3_SCSMR_STOP_SHIFT (3u) +#define SCIF3_SCSMR_OE_SHIFT (4u) +#define SCIF3_SCSMR_PE_SHIFT (5u) +#define SCIF3_SCSMR_CHR_SHIFT (6u) +#define SCIF3_SCSMR_CA_SHIFT (7u) + +#define SCIF3_SCBRR_D_SHIFT (0u) + +#define SCIF3_SCSCR_CKE_SHIFT (0u) +#define SCIF3_SCSCR_REIE_SHIFT (3u) +#define SCIF3_SCSCR_RE_SHIFT (4u) +#define SCIF3_SCSCR_TE_SHIFT (5u) +#define SCIF3_SCSCR_RIE_SHIFT (6u) +#define SCIF3_SCSCR_TIE_SHIFT (7u) + +#define SCIF3_SCFTDR_D_SHIFT (0u) + +#define SCIF3_SCFSR_DR_SHIFT (0u) +#define SCIF3_SCFSR_RDF_SHIFT (1u) +#define SCIF3_SCFSR_PER_SHIFT (2u) +#define SCIF3_SCFSR_FER_SHIFT (3u) +#define SCIF3_SCFSR_BRK_SHIFT (4u) +#define SCIF3_SCFSR_TDFE_SHIFT (5u) +#define SCIF3_SCFSR_TEND_SHIFT (6u) +#define SCIF3_SCFSR_ER_SHIFT (7u) +#define SCIF3_SCFSR_FERN_SHIFT (8u) +#define SCIF3_SCFSR_PERN_SHIFT (12u) + +#define SCIF3_SCFRDR_D_SHIFT (0u) + +#define SCIF3_SCFCR_LOOP_SHIFT (0u) +#define SCIF3_SCFCR_RFRST_SHIFT (1u) +#define SCIF3_SCFCR_TFRST_SHIFT (2u) +#define SCIF3_SCFCR_MCE_SHIFT (3u) +#define SCIF3_SCFCR_TTRG_SHIFT (4u) +#define SCIF3_SCFCR_RTRG_SHIFT (6u) +#define SCIF3_SCFCR_RSTRG_SHIFT (8u) + +#define SCIF3_SCFDR_R_SHIFT (0u) +#define SCIF3_SCFDR_T_SHIFT (8u) + +#define SCIF3_SCSPTR_SPB2DT_SHIFT (0u) +#define SCIF3_SCSPTR_SPB2IO_SHIFT (1u) +#define SCIF3_SCSPTR_SCKDT_SHIFT (2u) +#define SCIF3_SCSPTR_SCKIO_SHIFT (3u) +#define SCIF3_SCSPTR_CTSDT_SHIFT (4u) +#define SCIF3_SCSPTR_CTSIO_SHIFT (5u) +#define SCIF3_SCSPTR_RTSDT_SHIFT (6u) +#define SCIF3_SCSPTR_RTSIO_SHIFT (7u) + +#define SCIF3_SCLSR_ORER_SHIFT (0u) + +#define SCIF3_SCEMR_ABCS_SHIFT (0u) +#define SCIF3_SCEMR_BGDM_SHIFT (7u) + +/* ---- SCIF4 ---- */ +#define SCIF4_SCSMR_CKS_SHIFT (0u) +#define SCIF4_SCSMR_STOP_SHIFT (3u) +#define SCIF4_SCSMR_OE_SHIFT (4u) +#define SCIF4_SCSMR_PE_SHIFT (5u) +#define SCIF4_SCSMR_CHR_SHIFT (6u) +#define SCIF4_SCSMR_CA_SHIFT (7u) + +#define SCIF4_SCBRR_D_SHIFT (0u) + +#define SCIF4_SCSCR_CKE_SHIFT (0u) +#define SCIF4_SCSCR_REIE_SHIFT (3u) +#define SCIF4_SCSCR_RE_SHIFT (4u) +#define SCIF4_SCSCR_TE_SHIFT (5u) +#define SCIF4_SCSCR_RIE_SHIFT (6u) +#define SCIF4_SCSCR_TIE_SHIFT (7u) + +#define SCIF4_SCFTDR_D_SHIFT (0u) + +#define SCIF4_SCFSR_DR_SHIFT (0u) +#define SCIF4_SCFSR_RDF_SHIFT (1u) +#define SCIF4_SCFSR_PER_SHIFT (2u) +#define SCIF4_SCFSR_FER_SHIFT (3u) +#define SCIF4_SCFSR_BRK_SHIFT (4u) +#define SCIF4_SCFSR_TDFE_SHIFT (5u) +#define SCIF4_SCFSR_TEND_SHIFT (6u) +#define SCIF4_SCFSR_ER_SHIFT (7u) +#define SCIF4_SCFSR_FERN_SHIFT (8u) +#define SCIF4_SCFSR_PERN_SHIFT (12u) + +#define SCIF4_SCFRDR_D_SHIFT (0u) + +#define SCIF4_SCFCR_LOOP_SHIFT (0u) +#define SCIF4_SCFCR_RFRST_SHIFT (1u) +#define SCIF4_SCFCR_TFRST_SHIFT (2u) +#define SCIF4_SCFCR_MCE_SHIFT (3u) +#define SCIF4_SCFCR_TTRG_SHIFT (4u) +#define SCIF4_SCFCR_RTRG_SHIFT (6u) +#define SCIF4_SCFCR_RSTRG_SHIFT (8u) + +#define SCIF4_SCFDR_R_SHIFT (0u) +#define SCIF4_SCFDR_T_SHIFT (8u) + +#define SCIF4_SCSPTR_SPB2DT_SHIFT (0u) +#define SCIF4_SCSPTR_SPB2IO_SHIFT (1u) +#define SCIF4_SCSPTR_SCKDT_SHIFT (2u) +#define SCIF4_SCSPTR_SCKIO_SHIFT (3u) +#define SCIF4_SCSPTR_CTSDT_SHIFT (4u) +#define SCIF4_SCSPTR_CTSIO_SHIFT (5u) +#define SCIF4_SCSPTR_RTSDT_SHIFT (6u) +#define SCIF4_SCSPTR_RTSIO_SHIFT (7u) + +#define SCIF4_SCLSR_ORER_SHIFT (0u) + +#define SCIF4_SCEMR_ABCS_SHIFT (0u) +#define SCIF4_SCEMR_BGDM_SHIFT (7u) + +/* ---- SCIF5 ---- */ +#define SCIF5_SCSMR_CKS_SHIFT (0u) +#define SCIF5_SCSMR_STOP_SHIFT (3u) +#define SCIF5_SCSMR_OE_SHIFT (4u) +#define SCIF5_SCSMR_PE_SHIFT (5u) +#define SCIF5_SCSMR_CHR_SHIFT (6u) +#define SCIF5_SCSMR_CA_SHIFT (7u) + +#define SCIF5_SCBRR_D_SHIFT (0u) + +#define SCIF5_SCSCR_CKE_SHIFT (0u) +#define SCIF5_SCSCR_REIE_SHIFT (3u) +#define SCIF5_SCSCR_RE_SHIFT (4u) +#define SCIF5_SCSCR_TE_SHIFT (5u) +#define SCIF5_SCSCR_RIE_SHIFT (6u) +#define SCIF5_SCSCR_TIE_SHIFT (7u) + +#define SCIF5_SCFTDR_D_SHIFT (0u) + +#define SCIF5_SCFSR_DR_SHIFT (0u) +#define SCIF5_SCFSR_RDF_SHIFT (1u) +#define SCIF5_SCFSR_PER_SHIFT (2u) +#define SCIF5_SCFSR_FER_SHIFT (3u) +#define SCIF5_SCFSR_BRK_SHIFT (4u) +#define SCIF5_SCFSR_TDFE_SHIFT (5u) +#define SCIF5_SCFSR_TEND_SHIFT (6u) +#define SCIF5_SCFSR_ER_SHIFT (7u) +#define SCIF5_SCFSR_FERN_SHIFT (8u) +#define SCIF5_SCFSR_PERN_SHIFT (12u) + +#define SCIF5_SCFRDR_D_SHIFT (0u) + +#define SCIF5_SCFCR_LOOP_SHIFT (0u) +#define SCIF5_SCFCR_RFRST_SHIFT (1u) +#define SCIF5_SCFCR_TFRST_SHIFT (2u) +#define SCIF5_SCFCR_MCE_SHIFT (3u) +#define SCIF5_SCFCR_TTRG_SHIFT (4u) +#define SCIF5_SCFCR_RTRG_SHIFT (6u) +#define SCIF5_SCFCR_RSTRG_SHIFT (8u) + +#define SCIF5_SCFDR_R_SHIFT (0u) +#define SCIF5_SCFDR_T_SHIFT (8u) + +#define SCIF5_SCSPTR_SPB2DT_SHIFT (0u) +#define SCIF5_SCSPTR_SPB2IO_SHIFT (1u) +#define SCIF5_SCSPTR_SCKDT_SHIFT (2u) +#define SCIF5_SCSPTR_SCKIO_SHIFT (3u) +#define SCIF5_SCSPTR_CTSDT_SHIFT (4u) +#define SCIF5_SCSPTR_CTSIO_SHIFT (5u) +#define SCIF5_SCSPTR_RTSDT_SHIFT (6u) +#define SCIF5_SCSPTR_RTSIO_SHIFT (7u) + +#define SCIF5_SCLSR_ORER_SHIFT (0u) + +#define SCIF5_SCEMR_ABCS_SHIFT (0u) +#define SCIF5_SCEMR_BGDM_SHIFT (7u) + +/* ---- SCIF6 ---- */ +#define SCIF6_SCSMR_CKS_SHIFT (0u) +#define SCIF6_SCSMR_STOP_SHIFT (3u) +#define SCIF6_SCSMR_OE_SHIFT (4u) +#define SCIF6_SCSMR_PE_SHIFT (5u) +#define SCIF6_SCSMR_CHR_SHIFT (6u) +#define SCIF6_SCSMR_CA_SHIFT (7u) + +#define SCIF6_SCBRR_D_SHIFT (0u) + +#define SCIF6_SCSCR_CKE_SHIFT (0u) +#define SCIF6_SCSCR_REIE_SHIFT (3u) +#define SCIF6_SCSCR_RE_SHIFT (4u) +#define SCIF6_SCSCR_TE_SHIFT (5u) +#define SCIF6_SCSCR_RIE_SHIFT (6u) +#define SCIF6_SCSCR_TIE_SHIFT (7u) + +#define SCIF6_SCFTDR_D_SHIFT (0u) + +#define SCIF6_SCFSR_DR_SHIFT (0u) +#define SCIF6_SCFSR_RDF_SHIFT (1u) +#define SCIF6_SCFSR_PER_SHIFT (2u) +#define SCIF6_SCFSR_FER_SHIFT (3u) +#define SCIF6_SCFSR_BRK_SHIFT (4u) +#define SCIF6_SCFSR_TDFE_SHIFT (5u) +#define SCIF6_SCFSR_TEND_SHIFT (6u) +#define SCIF6_SCFSR_ER_SHIFT (7u) +#define SCIF6_SCFSR_FERN_SHIFT (8u) +#define SCIF6_SCFSR_PERN_SHIFT (12u) + +#define SCIF6_SCFRDR_D_SHIFT (0u) + +#define SCIF6_SCFCR_LOOP_SHIFT (0u) +#define SCIF6_SCFCR_RFRST_SHIFT (1u) +#define SCIF6_SCFCR_TFRST_SHIFT (2u) +#define SCIF6_SCFCR_MCE_SHIFT (3u) +#define SCIF6_SCFCR_TTRG_SHIFT (4u) +#define SCIF6_SCFCR_RTRG_SHIFT (6u) +#define SCIF6_SCFCR_RSTRG_SHIFT (8u) + +#define SCIF6_SCFDR_R_SHIFT (0u) +#define SCIF6_SCFDR_T_SHIFT (8u) + +#define SCIF6_SCSPTR_SPB2DT_SHIFT (0u) +#define SCIF6_SCSPTR_SPB2IO_SHIFT (1u) +#define SCIF6_SCSPTR_SCKDT_SHIFT (2u) +#define SCIF6_SCSPTR_SCKIO_SHIFT (3u) +#define SCIF6_SCSPTR_CTSDT_SHIFT (4u) +#define SCIF6_SCSPTR_CTSIO_SHIFT (5u) +#define SCIF6_SCSPTR_RTSDT_SHIFT (6u) +#define SCIF6_SCSPTR_RTSIO_SHIFT (7u) + +#define SCIF6_SCLSR_ORER_SHIFT (0u) + +#define SCIF6_SCEMR_ABCS_SHIFT (0u) +#define SCIF6_SCEMR_BGDM_SHIFT (7u) + +/* ---- SCIF7 ---- */ +#define SCIF7_SCSMR_CKS_SHIFT (0u) +#define SCIF7_SCSMR_STOP_SHIFT (3u) +#define SCIF7_SCSMR_OE_SHIFT (4u) +#define SCIF7_SCSMR_PE_SHIFT (5u) +#define SCIF7_SCSMR_CHR_SHIFT (6u) +#define SCIF7_SCSMR_CA_SHIFT (7u) + +#define SCIF7_SCBRR_D_SHIFT (0u) + +#define SCIF7_SCSCR_CKE_SHIFT (0u) +#define SCIF7_SCSCR_REIE_SHIFT (3u) +#define SCIF7_SCSCR_RE_SHIFT (4u) +#define SCIF7_SCSCR_TE_SHIFT (5u) +#define SCIF7_SCSCR_RIE_SHIFT (6u) +#define SCIF7_SCSCR_TIE_SHIFT (7u) + +#define SCIF7_SCFTDR_D_SHIFT (0u) + +#define SCIF7_SCFSR_DR_SHIFT (0u) +#define SCIF7_SCFSR_RDF_SHIFT (1u) +#define SCIF7_SCFSR_PER_SHIFT (2u) +#define SCIF7_SCFSR_FER_SHIFT (3u) +#define SCIF7_SCFSR_BRK_SHIFT (4u) +#define SCIF7_SCFSR_TDFE_SHIFT (5u) +#define SCIF7_SCFSR_TEND_SHIFT (6u) +#define SCIF7_SCFSR_ER_SHIFT (7u) +#define SCIF7_SCFSR_FERN_SHIFT (8u) +#define SCIF7_SCFSR_PERN_SHIFT (12u) + +#define SCIF7_SCFRDR_D_SHIFT (0u) + +#define SCIF7_SCFCR_LOOP_SHIFT (0u) +#define SCIF7_SCFCR_RFRST_SHIFT (1u) +#define SCIF7_SCFCR_TFRST_SHIFT (2u) +#define SCIF7_SCFCR_MCE_SHIFT (3u) +#define SCIF7_SCFCR_TTRG_SHIFT (4u) +#define SCIF7_SCFCR_RTRG_SHIFT (6u) +#define SCIF7_SCFCR_RSTRG_SHIFT (8u) + +#define SCIF7_SCFDR_R_SHIFT (0u) +#define SCIF7_SCFDR_T_SHIFT (8u) + +#define SCIF7_SCSPTR_SPB2DT_SHIFT (0u) +#define SCIF7_SCSPTR_SPB2IO_SHIFT (1u) +#define SCIF7_SCSPTR_SCKDT_SHIFT (2u) +#define SCIF7_SCSPTR_SCKIO_SHIFT (3u) +#define SCIF7_SCSPTR_CTSDT_SHIFT (4u) +#define SCIF7_SCSPTR_CTSIO_SHIFT (5u) +#define SCIF7_SCSPTR_RTSDT_SHIFT (6u) +#define SCIF7_SCSPTR_RTSIO_SHIFT (7u) + +#define SCIF7_SCLSR_ORER_SHIFT (0u) + +#define SCIF7_SCEMR_ABCS_SHIFT (0u) +#define SCIF7_SCEMR_BGDM_SHIFT (7u) + +/* ---- SCIFn ---- */ +#define SCIFn_SCSMR_CKS_SHIFT (0u) +#define SCIFn_SCSMR_STOP_SHIFT (3u) +#define SCIFn_SCSMR_OE_SHIFT (4u) +#define SCIFn_SCSMR_PE_SHIFT (5u) +#define SCIFn_SCSMR_CHR_SHIFT (6u) +#define SCIFn_SCSMR_CA_SHIFT (7u) + +#define SCIFn_SCBRR_D_SHIFT (0u) + +#define SCIFn_SCSCR_CKE_SHIFT (0u) +#define SCIFn_SCSCR_REIE_SHIFT (3u) +#define SCIFn_SCSCR_RE_SHIFT (4u) +#define SCIFn_SCSCR_TE_SHIFT (5u) +#define SCIFn_SCSCR_RIE_SHIFT (6u) +#define SCIFn_SCSCR_TIE_SHIFT (7u) + +#define SCIFn_SCFTDR_D_SHIFT (0u) + +#define SCIFn_SCFSR_DR_SHIFT (0u) +#define SCIFn_SCFSR_RDF_SHIFT (1u) +#define SCIFn_SCFSR_PER_SHIFT (2u) +#define SCIFn_SCFSR_FER_SHIFT (3u) +#define SCIFn_SCFSR_BRK_SHIFT (4u) +#define SCIFn_SCFSR_TDFE_SHIFT (5u) +#define SCIFn_SCFSR_TEND_SHIFT (6u) +#define SCIFn_SCFSR_ER_SHIFT (7u) +#define SCIFn_SCFSR_FERN_SHIFT (8u) +#define SCIFn_SCFSR_PERN_SHIFT (12u) + +#define SCIFn_SCFRDR_D_SHIFT (0u) + +#define SCIFn_SCFCR_LOOP_SHIFT (0u) +#define SCIFn_SCFCR_RFRST_SHIFT (1u) +#define SCIFn_SCFCR_TFRST_SHIFT (2u) +#define SCIFn_SCFCR_MCE_SHIFT (3u) +#define SCIFn_SCFCR_TTRG_SHIFT (4u) +#define SCIFn_SCFCR_RTRG_SHIFT (6u) +#define SCIFn_SCFCR_RSTRG_SHIFT (8u) + +#define SCIFn_SCFDR_R_SHIFT (0u) +#define SCIFn_SCFDR_T_SHIFT (8u) + +#define SCIFn_SCSPTR_SPB2DT_SHIFT (0u) +#define SCIFn_SCSPTR_SPB2IO_SHIFT (1u) +#define SCIFn_SCSPTR_SCKDT_SHIFT (2u) +#define SCIFn_SCSPTR_SCKIO_SHIFT (3u) +#define SCIFn_SCSPTR_CTSDT_SHIFT (4u) +#define SCIFn_SCSPTR_CTSIO_SHIFT (5u) +#define SCIFn_SCSPTR_RTSDT_SHIFT (6u) +#define SCIFn_SCSPTR_RTSIO_SHIFT (7u) + +#define SCIFn_SCLSR_ORER_SHIFT (0u) + +#define SCIFn_SCEMR_ABCS_SHIFT (0u) +#define SCIFn_SCEMR_BGDM_SHIFT (7u) + + +#endif /* SCIF_IOBITMASK_H */ + +/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/usb_iobitmask.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,731 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb_iobitmask.h +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Description : USB register define header +*******************************************************************************/ +#ifndef USB_IOBITMASK_H +#define USB_IOBITMASK_H + +/*==============================================*/ +/* SYSCFG */ +/*==============================================*/ +#define USB_SYSCFG_USBE (0x0001u) +#define USB_SYSCFG_UPLLE (0x0002u) +#define USB_SYSCFG_UCKSEL (0x0004u) +/* #define USB_SYSCFG_RESERVED1 (0x0008u) */ +#define USB_SYSCFG_DPRPU (0x0010u) +#define USB_SYSCFG_DRPD (0x0020u) +#define USB_SYSCFG_DCFM (0x0040u) +#define USB_SYSCFG_HSE (0x0080u) +/* #define USB_SYSCFG_RESERVED2 (0xFF00u) */ + +#define USB_SYSCFG_USBE_SHIFT (0) +#define USB_SYSCFG_UPLLE_SHIFT (1) +#define USB_SYSCFG_UCKSEL_SHIFT (2) +/* #define USB_SYSCFG_RESERVED1_SHIFT (3) */ +#define USB_SYSCFG_DPRPU_SHIFT (4) +#define USB_SYSCFG_DRPD_SHIFT (5) +#define USB_SYSCFG_DCFM_SHIFT (6) +#define USB_SYSCFG_HSE_SHIFT (7) +/* #define USB_SYSCFG_RESERVED2_SHIFT (8) */ + +/*==============================================*/ +/* BUSWAIT */ +/*==============================================*/ +#define USB_BUSWAIT_BWAIT (0x003Fu) + +#define USB_BUSWAIT_BWAIT_SHIFT (0) + +/*==============================================*/ +/* SYSSTS0 */ +/*==============================================*/ +#define USB_SYSSTS0_LNST (0x0003u) +#define USB_SYSSTS0_SOFEA (0x0020u) +#define USB_SYSSTS0_HTACT (0x0040u) + +#define USB_SYSSTS0_LNST_SHIFT (0) +#define USB_SYSSTS0_SOFEA_SHIFT (5) +#define USB_SYSSTS0_HTACT_SHIFT (6) + +/*==============================================*/ +/* DVSTCTR0 */ +/*==============================================*/ +#define USB_DVSTCTR0_RHST (0x0007u) +/* #define USB_DVSTCTR0_RESERVED (0x0008u) */ +#define USB_DVSTCTR0_UACT (0x0010u) +#define USB_DVSTCTR0_RESUME (0x0020u) +#define USB_DVSTCTR0_USBRST (0x0040u) +#define USB_DVSTCTR0_RWUPE (0x0080u) +#define USB_DVSTCTR0_WKUP (0x0100u) + +#define USB_DVSTCTR0_RHST_SHIFT (0) +/* #define USB_DVSTCTR0_RESERVED_SHIFT (3) */ +#define USB_DVSTCTR0_UACT_SHIFT (4) +#define USB_DVSTCTR0_RESUME_SHIFT (5) +#define USB_DVSTCTR0_USBRST_SHIFT (6) +#define USB_DVSTCTR0_RWUPE_SHIFT (7) +#define USB_DVSTCTR0_WKUP_SHIFT (8) + +/*==============================================*/ +/* TESTMODE */ +/*==============================================*/ +#define USB_TESTMODE_UTST (0x000Fu) +/* #define USB_TESTMODE_RESERVED (0xFFF0u) */ + +#define USB_TESTMODE_UTST_SHIFT (0) +/* #define USB_TESTMODE_RESERVED_SHIFT (4) */ + +/*==============================================*/ +/* DnFBCFG */ +/*==============================================*/ +/* #define USB_DnFBCFG_RESERVED1 (0x000Fu) */ +#define USB_DnFBCFG_TENDE (0x0010u) +/* #define USB_DnFBCFG_RESERVED2 (0x0FE0u) */ +#define USB_DnFBCFG_DFACC (0x3000u) +/* #define USB_DnFBCFG_RESERVED3 (0xC000u) */ + +/* #define USB_DnFBCFG_RESERVED1_SHIFT (0) */ +#define USB_DnFBCFG_TENDE_SHIFT (4) +/* #define USB_DnFBCFG_RESERVED2_SHIFT (5) */ +#define USB_DnFBCFG_DFACC_SHIFT (12) +/* #define USB_DnFBCFG_RESERVED3_SHIFT (14) */ + +/*==============================================*/ +/* CFIFO */ +/*==============================================*/ +#define USB_CFIFO_FIFOPORT (0xFFFFFFFFuL) + +#define USB_CFIFO_FIFOPORT_SHIFT (0) + +/*==============================================*/ +/* DnFIFO */ +/*==============================================*/ +#define USB_DnFIFO_FIFOPORT (0xFFFFFFFFuL) + +#define USB_DnFIFO_FIFOPORT_SHIFT (0) + +/*==============================================*/ +/* CFIFOSEL */ +/*==============================================*/ +#define USB_CFIFOSEL_CURPIPE (0x000Fu) +/* #define USB_CFIFOSEL_RESERVED1 (0x0010u) */ +#define USB_CFIFOSEL_ISEL_ (0x0020u) +/* #define USB_CFIFOSEL_RESERVED2 (0x00C0u) */ +#define USB_CFIFOSEL_BIGEND (0x0100u) +/* #define USB_CFIFOSEL_RESERVED3 (0x0200u) */ +#define USB_CFIFOSEL_MBW (0x0C00u) +/* #define USB_CFIFOSEL_RESERVED4 (0x3000u) */ +#define USB_CFIFOSEL_REW (0x4000u) +#define USB_CFIFOSEL_RCNT (0x8000u) + +#define USB_CFIFOSEL_CURPIPE_SHIFT (0) +/* #define USB_CFIFOSEL_RESERVED1_SHIFT (4) */ +#define USB_CFIFOSEL_ISEL_SHIFT_ (5) +/* #define USB_CFIFOSEL_RESERVED2_SHIFT (6) */ +#define USB_CFIFOSEL_BIGEND_SHIFT (8) +/* #define USB_CFIFOSEL_RESERVED3_SHIFT (9) */ +#define USB_CFIFOSEL_MBW_SHIFT (10) +/* #define USB_CFIFOSEL_RESERVED4_SHIFT (12) */ +#define USB_CFIFOSEL_REW_SHIFT (14) +#define USB_CFIFOSEL_RCNT_SHIFT (15) + +/*==============================================*/ +/* DnFIFOSEL */ +/*==============================================*/ +#define USB_DnFIFOSEL_CURPIPE (0x000Fu) +/* #define USB_DnFIFOSEL_RESERVED1 (0x00F0u) */ +#define USB_DnFIFOSEL_BIGEND (0x0100u) +/* #define USB_DnFIFOSEL_RESERVED2 (0x0200u) */ +#define USB_DnFIFOSEL_MBW (0x0C00u) +#define USB_DnFIFOSEL_DREQE (0x1000u) +#define USB_DnFIFOSEL_DCLRM (0x2000u) +#define USB_DnFIFOSEL_REW (0x4000u) +#define USB_DnFIFOSEL_RCNT (0x8000u) + +#define USB_DnFIFOSEL_CURPIPE_SHIFT (0) +/* #define USB_DnFIFOSEL_RESERVED1_SHIFT (4) */ +#define USB_DnFIFOSEL_BIGEND_SHIFT (8) +/* #define USB_DnFIFOSEL_RESERVED2_SHIFT (9) */ +#define USB_DnFIFOSEL_MBW_SHIFT (10) +#define USB_DnFIFOSEL_DREQE_SHIFT (12) +#define USB_DnFIFOSEL_DCLRM_SHIFT (13) +#define USB_DnFIFOSEL_REW_SHIFT (14) +#define USB_DnFIFOSEL_RCNT_SHIFT (15) + +/*==============================================*/ +/* CFIFOCTR */ +/*==============================================*/ +#define USB_CFIFOCTR_DTLN (0x0FFFu) +/* #define USB_CFIFOCTR_RESERVED (0x1000u) */ +#define USB_CFIFOCTR_FRDY (0x2000u) +#define USB_CFIFOCTR_BCLR (0x4000u) +#define USB_CFIFOCTR_BVAL (0x8000u) + +#define USB_CFIFOCTR_DTLN_SHIFT (0) +/* #define USB_CFIFOCTR_RESERVED_SHIFT (12) */ +#define USB_CFIFOCTR_FRDY_SHIFT (13) +#define USB_CFIFOCTR_BCLR_SHIFT (14) +#define USB_CFIFOCTR_BVAL_SHIFT (15) + +/*==============================================*/ +/* DnFIFOCTR */ +/*==============================================*/ +#define USB_DnFIFOCTR_DTLN (0x0FFFu) +/* #define USB_DnFIFOCTR_RESERVED (0x1000u) */ +#define USB_DnFIFOCTR_FRDY (0x2000u) +#define USB_DnFIFOCTR_BCLR (0x4000u) +#define USB_DnFIFOCTR_BVAL (0x8000u) + +#define USB_DnFIFOCTR_DTLN_SHIFT (0) +/* #define USB_DnFIFOCTR_RESERVED_SHIFT (12) */ +#define USB_DnFIFOCTR_FRDY_SHIFT (13) +#define USB_DnFIFOCTR_BCLR_SHIFT (14) +#define USB_DnFIFOCTR_BVAL_SHIFT (15) + +/*==============================================*/ +/* INTENB0 */ +/*==============================================*/ +/* #define USB_INTENB0_RESERVED (0x00FFu) */ +#define USB_INTENB0_BRDYE (0x0100u) +#define USB_INTENB0_NRDYE (0x0200u) +#define USB_INTENB0_BEMPE (0x0400u) +#define USB_INTENB0_CTRE (0x0800u) +#define USB_INTENB0_DVSE (0x1000u) +#define USB_INTENB0_SOFE (0x2000u) +#define USB_INTENB0_RSME (0x4000u) +#define USB_INTENB0_VBSE (0x8000u) + +/* #define USB_INTENB0_RESERVED_SHIFT (0) */ +#define USB_INTENB0_BRDYE_SHIFT (8) +#define USB_INTENB0_NRDYE_SHIFT (9) +#define USB_INTENB0_BEMPE_SHIFT (10) +#define USB_INTENB0_CTRE_SHIFT (11) +#define USB_INTENB0_DVSE_SHIFT (12) +#define USB_INTENB0_SOFE_SHIFT (13) +#define USB_INTENB0_RSME_SHIFT (14) +#define USB_INTENB0_VBSE_SHIFT (15) + +/*==============================================*/ +/* INTENB1 */ +/*==============================================*/ +/* #define USB_INTENB1_RESERVED1 (0x000Fu) */ +#define USB_INTENB1_SACKE (0x0010u) +#define USB_INTENB1_SIGNE (0x0020u) +#define USB_INTENB1_EOFERRE (0x0040u) +/* #define USB_INTENB1_RESERVED2 (0x0780u) */ +#define USB_INTENB1_ATTCHE (0x0800u) +#define USB_INTENB1_DTCHE (0x1000u) +/* #define USB_INTENB1_RESERVED3 (0x2000u) */ +#define USB_INTENB1_BCHGE (0x4000u) +/* #define USB_INTENB1_RESERVED4 (0x8000u) */ + +/* #define USB_INTENB1_RESERVED1_SHIFT (0) */ +#define USB_INTENB1_SACKE_SHIFT (4) +#define USB_INTENB1_SIGNE_SHIFT (5) +#define USB_INTENB1_EOFERRE_SHIFT (6) +/* #define USB_INTENB1_RESERVED2_SHIFT (7) */ +#define USB_INTENB1_ATTCHE_SHIFT (11) +#define USB_INTENB1_DTCHE_SHIFT (12) +/* #define USB_INTENB1_RESERVED3_SHIFT (13) */ +#define USB_INTENB1_BCHGE_SHIFT (14) +/* #define USB_INTENB1_RESERVED4_SHIFT (15) */ + +/*==============================================*/ +/* BRDYENB */ +/*==============================================*/ +#define USB_BRDYENB (0xFFFFu) + +#define USB_BRDYENB_SHIFT (0) + +/*==============================================*/ +/* NRDYENB */ +/*==============================================*/ +#define USB_NRDYENB (0xFFFFu) + +#define USB_NRDYENB_SHIFT (0) + +/*==============================================*/ +/* BEMPENB */ +/*==============================================*/ +#define USB_BEMPENB (0xFFFFu) + +#define USB_BEMPENB_SHIFT (0) + +/*==============================================*/ +/* SOFCFG */ +/*==============================================*/ +/* #define USB_SOFCFG_RESERVED1 (0x003Fu) */ +#define USB_SOFCFG_BRDYM (0x0040u) +/* #define USB_SOFCFG_RESERVED2 (0x0080u) */ +#define USB_SOFCFG_TRNENSEL (0x0100u) +/* #define USB_SOFCFG_RESERVED3 (0xFE00u) */ + +/* #define USB_SOFCFG_RESERVED1_SHIFT (0) */ +#define USB_SOFCFG_BRDYM_SHIFT (6) +/* #define USB_SOFCFG_RESERVED2_SHIFT (7) */ +#define USB_SOFCFG_TRNENSEL_SHIFT (8) +/* #define USB_SOFCFG_RESERVED3_SHIFT (9) */ + +/*==============================================*/ +/* INTSTS0 */ +/*==============================================*/ +#define USB_INTSTS0_CTSQ (0x0007u) +#define USB_INTSTS0_VALID (0x0008u) +#define USB_INTSTS0_DVSQ (0x0070u) +#define USB_INTSTS0_VBSTS (0x0080u) +#define USB_INTSTS0_BRDY (0x0100u) +#define USB_INTSTS0_NRDY (0x0200u) +#define USB_INTSTS0_BEMP (0x0400u) +#define USB_INTSTS0_CTRT (0x0800u) +#define USB_INTSTS0_DVST (0x1000u) +#define USB_INTSTS0_SOFR (0x2000u) +#define USB_INTSTS0_RESM (0x4000u) +#define USB_INTSTS0_VBINT (0x8000u) + +#define USB_INTSTS0_CTSQ_SHIFT (0) +#define USB_INTSTS0_VALID_SHIFT (3) +#define USB_INTSTS0_DVSQ_SHIFT (4) +#define USB_INTSTS0_VBSTS_SHIFT (7) +#define USB_INTSTS0_BRDY_SHIFT (8) +#define USB_INTSTS0_NRDY_SHIFT (9) +#define USB_INTSTS0_BEMP_SHIFT (10) +#define USB_INTSTS0_CTRT_SHIFT (11) +#define USB_INTSTS0_DVST_SHIFT (12) +#define USB_INTSTS0_SOFR_SHIFT (13) +#define USB_INTSTS0_RESM_SHIFT (14) +#define USB_INTSTS0_VBINT_SHIFT (15) + +/*==============================================*/ +/* INTSTS1 */ +/*==============================================*/ +/* #define USB_INTSTS1_RESERVED1 (0x000Fu) */ +#define USB_INTSTS1_SACK (0x0010u) +#define USB_INTSTS1_SIGN (0x0020u) +#define USB_INTSTS1_EOFERR (0x0040u) +/* #define USB_INTSTS1_RESERVED2 (0x0780u) */ +#define USB_INTSTS1_ATTCH (0x0800u) +#define USB_INTSTS1_DTCH (0x1000u) +/* #define USB_INTSTS1_RESERVED3 (0x2000u) */ +#define USB_INTSTS1_BCHG (0x4000u) +/* #define USB_INTSTS1_RESERVED4 (0x8000u) */ + +/* #define USB_INTSTS1_RESERVED1_SHIFT (0) */ +#define USB_INTSTS1_SACK_SHIFT (4) +#define USB_INTSTS1_SIGN_SHIFT (5) +#define USB_INTSTS1_EOFERR_SHIFT (6) +/* #define USB_INTSTS1_RESERVED2_SHIFT (7) */ +#define USB_INTSTS1_ATTCH_SHIFT (11) +#define USB_INTSTS1_DTCH_SHIFT (12) +/* #define USB_INTSTS1_RESERVED3_SHIFT (13) */ +#define USB_INTSTS1_BCHG_SHIFT (14) +/* #define USB_INTSTS1_RESERVED4_SHIFT (15) */ + +/*==============================================*/ +/* BRDYSTS */ +/*==============================================*/ +#define USB_BRDYSTS (0xFFFFu) + +#define USB_BRDYSTS_SHIFT (0) + +/*==============================================*/ +/* NRDYSTS */ +/*==============================================*/ +#define USB_NRDYSTS (0xFFFFu) + +#define USB_NRDYSTS_SHIFT (0) + +/*==============================================*/ +/* BEMPSTS */ +/*==============================================*/ +#define USB_BEMPSTS (0xFFFFu) + +#define USB_BEMPSTS_SHIFT (0) + +/*==============================================*/ +/* FRMNUM */ +/*==============================================*/ +#define USB_FRMNUM_FRNM (0x07FFu) +/* #define USB_FRMNUM_RESERVED (0x3800u) */ +#define USB_FRMNUM_CRCE (0x4000u) +#define USB_FRMNUM_OVRN (0x8000u) + +#define USB_FRMNUM_FRNM_SHIFT (0) +/* #define USB_FRMNUM_RESERVED_SHIFT (11) */ +#define USB_FRMNUM_CRCE_SHIFT (14) +#define USB_FRMNUM_OVRN_SHIFT (15) + +/*==============================================*/ +/* UFRMNUM */ +/*==============================================*/ +#define USB_UFRMNUM_UFRNM (0x0007u) +/* #define USB_UFRMNUM_RESERVED (0xFFF8u) */ + +#define USB_UFRMNUM_UFRNM_SHIFT (0) +/* #define USB_UFRMNUM_RESERVED_SHIFT (3) */ + +/*==============================================*/ +/* USBADDR */ +/*==============================================*/ +#define USB_USBADDR_USBADDR (0x007Fu) +/* #define USB_USBADDR_RESERVED (0xFF80u) */ + +#define USB_USBADDR_USBADDR_SHIFT (0) +/* #define USB_USBADDR_RESERVED_SHIFT (7) */ + +/*==============================================*/ +/* USBREQ */ +/*==============================================*/ +#define USB_USBREQ_BMREQUESTTYPE (0x00FFu) +#define USB_USBREQ_BREQUEST (0xFF00u) + +#define USB_USBREQ_BMREQUESTTYPE_SHIFT (0) +#define USB_USBREQ_BREQUEST_SHIFT (8) + +/*==============================================*/ +/* USBVAL */ +/*==============================================*/ +#define USB_USBVAL (0xFFFFu) + +#define USB_USBVAL_SHIFT (0) + +/*==============================================*/ +/* USBINDX */ +/*==============================================*/ +#define USB_USBINDX (0xFFFFu) + +#define USB_USBINDX_SHIFT (0) + +/*==============================================*/ +/* USBLENG */ +/*==============================================*/ +#define USB_USBLENG (0xFFFFu) + +#define USB_USBLENG_SHIFT (0) + +/*==============================================*/ +/* DCPCFG */ +/*==============================================*/ +/* #define USB_DCPCFG_RESERVED1 (0x000Fu) */ +#define USB_DCPCFG_DIR (0x0010u) +/* #define USB_DCPCFG_RESERVED2 (0x0060u) */ +#define USB_DCPCFG_SHTNAK (0x0080u) +#define USB_DCPCFG_CNTMD (0x0100u) +/* #define USB_DCPCFG_RESERVED3 (0xFE00u) */ + +/* #define USB_DCPCFG_RESERVED1_SHIFT (0) */ +#define USB_DCPCFG_DIR_SHIFT (4) +/* #define USB_DCPCFG_RESERVED2_SHIFT (5) */ +#define USB_DCPCFG_SHTNK_SHIFT (7) +#define USB_DCPCFG_CNTMD_SHIFT (8) +/* #define USB_DCPCFG_RESERVED3 (9) */ + +/*==============================================*/ +/* DCPMAXP */ +/*==============================================*/ +#define USB_DCPMAXP_MXPS (0x007Fu) +/* #define USB_DCPMAXP_RESERVED (0x0F80u) */ +#define USB_DCPMAXP_DEVSEL (0xF000u) + +#define USB_DCPMAXP_MXPS_SHIFT (0) +/* #define USB_DCPMAXP_RESERVED_SHIFT (7) */ +#define USB_DCPMAXP_DEVSEL_SHIFT (12) + +/*==============================================*/ +/* DCPCTR */ +/*==============================================*/ +#define USB_DCPCTR_PID (0x0003u) +#define USB_DCPCTR_CCPL (0x0004u) +/* #define USB_DCPCTR_RESERVED1 (0x0008u) */ +#define USB_DCPCTR_PINGE (0x0010u) +#define USB_DCPCTR_PBUSY (0x0020u) +#define USB_DCPCTR_SQMON (0x0040u) +#define USB_DCPCTR_SQSET (0x0080u) +#define USB_DCPCTR_SQCLR (0x0100u) +/* #define USB_DCPCTR_RESERVED2 (0x0600u) */ +#define USB_DCPCTR_SUREQCLR (0x0800u) +#define USB_DCPCTR_CSSTS (0x1000u) +#define USB_DCPCTR_CSCLR (0x2000u) +#define USB_DCPCTR_SUREQ (0x4000u) +#define USB_DCPCTR_BSTS (0x8000u) + +#define USB_DCPCTR_PID_SHIFT (0) +#define USB_DCPCTR_CCPL_SHIFT (2) +/* #define USB_DCPCTR_RESERVED1_SHIFT (3) */ +#define USB_DCPCTR_PINGE_SHIFT (4) +#define USB_DCPCTR_PBUSY_SHIFT (5) +#define USB_DCPCTR_SQMON_SHIFT (6) +#define USB_DCPCTR_SQSET_SHIFT (7) +#define USB_DCPCTR_SQCLR_SHIFT (8) +/* #define USB_DCPCTR_RESERVED2_SHIFT (9) */ +#define USB_DCPCTR_SUREQCLR_SHIFT (11) +#define USB_DCPCTR_CSSTS_SHIFT (12) +#define USB_DCPCTR_CSCLR_SHIFT (13) +#define USB_DCPCTR_SUREQ_SHIFT (14) +#define USB_DCPCTR_BSTS_SHIFT (15) + +/*==============================================*/ +/* PIPESEL */ +/*==============================================*/ +#define USB_PIPESEL_PIPESEL (0x000Fu) +/* #define USB_PIPESEL_RESERVED (0xFFF0u) */ + +#define USB_PIPESEL_PIPESEL_SHIFT (0) +/* #define USB_PIPESEL_RESERVED_SHIFT (4) */ + +/*==============================================*/ +/* PIPECFG */ +/*==============================================*/ +#define USB_PIPECFG_EPNUM (0x000Fu) +#define USB_PIPECFG_DIR (0x0010u) +/* #define USB_PIPECFG_RESERVED1 (0x0060u) */ +#define USB_PIPECFG_SHTNAK (0x0080u) +#define USB_PIPECFG_CNTMD (0x0100u) +#define USB_PIPECFG_DBLB (0x0200u) +#define USB_PIPECFG_BFRE (0x0400u) +/* #define USB_PIPECFG_RESERVED2 (0x3800u) */ +#define USB_PIPECFG_TYPE (0xC000u) + +#define USB_PIPECFG_EPNUM_SHIFT (0) +#define USB_PIPECFG_DIR_SHIFT (4) +/* #define USB_PIPECFG_RESERVED1_SHIFT (5) */ +#define USB_PIPECFG_SHTNAK_SHIFT (7) +#define USB_PIPECFG_CNTMD_SHIFT (8) +#define USB_PIPECFG_DBLB_SHIFT (9) +#define USB_PIPECFG_BFRE_SHIFT (10) +/* #define USB_PIPECFG_RESERVED2_SHIFT (11) */ +#define USB_PIPECFG_TYPE_SHIFT (14) + +/*==============================================*/ +/* PIPEBUF */ +/*==============================================*/ +#define USB_PIPEBUF_BUFNMB (0x00FFu) +/* #define USB_PIPEBUF_RESERVED1 (0x0300u) */ +#define USB_PIPEBUF_BUFSIZE (0x7C00u) +/* #define USB_PIPEBUF_RESERVED2 (0x8000u) */ + +#define USB_PIPEBUF_BUFNMB_SHIFT (0) +/* #define USB_PIPEBUF_RESERVED1_SHIFT (8) */ +#define USB_PIPEBUF_BUFSIZE_SHIFT (10) +/* #define USB_PIPEBUF_RESERVED2_SHIFT (15) */ + +/*==============================================*/ +/* PIPEMAXP */ +/*==============================================*/ +#define USB_PIPEMAXP_MXPS (0x07FFu) +/* #define USB_PIPEMAXP_RESERVED (0x0800u) */ +#define USB_PIPEMAXP_DEVSEL (0xF000u) + +#define USB_PIPEMAXP_MXPS_SHIFT (0) +/* #define USB_PIPEMAXP_RESERVED_SHIFT (11) */ +#define USB_PIPEMAXP_DEVSEL_SHIFT (12) + +/*==============================================*/ +/* PIPEPERI */ +/*==============================================*/ +#define USB_PIPEPERI_IITV (0x0007u) +/* #define USB_PIPEPERI_RESERVED1 (0x0FF8u) */ +#define USB_PIPEPERI_IFIS (0x1000u) +/* #define USB_PIPEPERI_RESERVED2 (0xE000u) */ + +#define USB_PIPEPERI_IITV_SHIFT (0) +/* #define USB_PIPEPERI_RESERVED1_SHIFT (3) */ +#define USB_PIPEPERI_IFIS_SHIFT (12) +/* #define USB_PIPEPERI_RESERVED2_SHIFT (13) */ + +/*==============================================*/ +/* PIPEnCTR_1_5 */ +/*==============================================*/ +#define USB_PIPEnCTR_1_5_PID (0x0003u) +/* #define USB_PIPEnCTR_1_5_RESERVED1 (0x001Cu) */ +#define USB_PIPEnCTR_1_5_PBUSY (0x0020u) +#define USB_PIPEnCTR_1_5_SQMON (0x0040u) +#define USB_PIPEnCTR_1_5_SQSET (0x0080u) +#define USB_PIPEnCTR_1_5_SQCLR (0x0100u) +#define USB_PIPEnCTR_1_5_ACLRM (0x0200u) +#define USB_PIPEnCTR_1_5_ATREPM (0x0400u) +/* #define USB_PIPEnCTR_1_5_RESERVED2 (0x0800u) */ +#define USB_PIPEnCTR_1_5_CSSTS (0x1000u) +#define USB_PIPEnCTR_1_5_CSCLR (0x2000u) +#define USB_PIPEnCTR_1_5_INBUFM (0x4000u) +#define USB_PIPEnCTR_1_5_BSTS (0x8000u) + +#define USB_PIPEnCTR_1_5_PID_SHIFT (0) +/* #define USB_PIPEnCTR_1_5_RESERVED1_SHIFT (2) */ +#define USB_PIPEnCTR_1_5_PBUSY_SHIFT (5) +#define USB_PIPEnCTR_1_5_SQMON_SHIFT (6) +#define USB_PIPEnCTR_1_5_SQSET_SHIFT (7) +#define USB_PIPEnCTR_1_5_SQCLR_SHIFT (8) +#define USB_PIPEnCTR_1_5_ACLRM_SHIFT (9) +#define USB_PIPEnCTR_1_5_ATREPM_SHIFT (10) +/* #define USB_PIPEnCTR_1_5_RESERVED2_SHIFT (11) */ +#define USB_PIPEnCTR_1_5_CSSTS_SHIFT (12) +#define USB_PIPEnCTR_1_5_CSCLR_SHIFT (13) +#define USB_PIPEnCTR_1_5_INBUFM_SHIFT (14) +#define USB_PIPEnCTR_1_5_BSTS_SHIFT (15) + +/*==============================================*/ +/* PIPEnCTR_6_8 */ +/*==============================================*/ +#define USB_PIPEnCTR_6_8_PID (0x0003u) +/* #define USB_PIPEnCTR_6_8_RESERVED1 (0x001Cu) */ +#define USB_PIPEnCTR_6_8_PBUSY (0x0020u) +#define USB_PIPEnCTR_6_8_SQMON (0x0040u) +#define USB_PIPEnCTR_6_8_SQSET (0x0080u) +#define USB_PIPEnCTR_6_8_SQCLR (0x0100u) +#define USB_PIPEnCTR_6_8_ACLRM (0x0200u) +/* #define USB_PIPEnCTR_6_8_RESERVED2 (0x0C00u) */ +#define USB_PIPEnCTR_6_8_CSSTS (0x1000u) +#define USB_PIPEnCTR_6_8_CSCLR (0x2000u) +/* #define USB_PIPEnCTR_6_8_RESERVED3 (0x4000u) */ +#define USB_PIPEnCTR_6_8_BSTS (0x8000u) + +#define USB_PIPEnCTR_6_8_PID_SHIFT (0) +/* #define USB_PIPEnCTR_6_8_RESERVED1_SHIFT (2) */ +#define USB_PIPEnCTR_6_8_PBUSY_SHIFT (5) +#define USB_PIPEnCTR_6_8_SQMON_SHIFT (6) +#define USB_PIPEnCTR_6_8_SQSET_SHIFT (7) +#define USB_PIPEnCTR_6_8_SQCLR_SHIFT (8) +#define USB_PIPEnCTR_6_8_ACLRM_SHIFT (9) +/* #define USB_PIPEnCTR_6_8_RESERVED2_SHIFT (10) */ +#define USB_PIPEnCTR_6_8_CSSTS_SHIFT (12) +#define USB_PIPEnCTR_6_8_CSCLR_SHIFT (13) +/* #define USB_PIPEnCTR_6_8_RESERVED3_SHIFT (14) */ +#define USB_PIPEnCTR_6_8_BSTS_SHIFT (15) + +/*==============================================*/ +/* PIPEnCTR_9 */ +/*==============================================*/ +#define USB_PIPEnCTR_9_PID (0x0003u) +/* #define USB_PIPEnCTR_9_RESERVED1 (0x001Cu) */ +#define USB_PIPEnCTR_9_PBUSY (0x0020u) +#define USB_PIPEnCTR_9_SQMON (0x0040u) +#define USB_PIPEnCTR_9_SQSET (0x0080u) +#define USB_PIPEnCTR_9_SQCLR (0x0100u) +#define USB_PIPEnCTR_9_ACLRM (0x0200u) +#define USB_PIPEnCTR_9_ATREPM (0x0400u) +/* #define USB_PIPEnCTR_9_RESERVED2 (0x0800u) */ +#define USB_PIPEnCTR_9_CSSTS (0x1000u) +#define USB_PIPEnCTR_9_CSCLR (0x2000u) +#define USB_PIPEnCTR_9_INBUFM (0x4000u) +#define USB_PIPEnCTR_9_BSTS (0x8000u) + +#define USB_PIPEnCTR_9_PID_SHIFT (0) +/* #define USB_PIPEnCTR_9_RESERVED1_SHIFT (2) */ +#define USB_PIPEnCTR_9_PBUSY_SHIFT (5) +#define USB_PIPEnCTR_9_SQMON_SHIFT (6) +#define USB_PIPEnCTR_9_SQSET_SHIFT (7) +#define USB_PIPEnCTR_9_SQCLR_SHIFT (8) +#define USB_PIPEnCTR_9_ACLRM_SHIFT (9) +#define USB_PIPEnCTR_9_ATREPM_SHIFT (10) +/* #define USB_PIPEnCTR_9_RESERVED2_SHIFT (11) */ +#define USB_PIPEnCTR_9_CSSTS_SHIFT (12) +#define USB_PIPEnCTR_9_CSCLR_SHIFT (13) +#define USB_PIPEnCTR_9_INBUFM_SHIFT (14) +#define USB_PIPEnCTR_9_BSTS_SHIFT (15) + +/*==============================================*/ +/* PIPEnCTR_A_F */ +/*==============================================*/ +#define USB_PIPEnCTR_A_F_PID (0x0003u) +/* #define USB_PIPEnCTR_A_F_RESERVED1 (0x001Cu) */ +#define USB_PIPEnCTR_A_F_PBUSY (0x0020u) +#define USB_PIPEnCTR_A_F_SQMON (0x0040u) +#define USB_PIPEnCTR_A_F_SQSET (0x0080u) +#define USB_PIPEnCTR_A_F_SQCLR (0x0100u) +#define USB_PIPEnCTR_A_F_ACLRM (0x0200u) +#define USB_PIPEnCTR_A_F_ATREPM (0x0400u) +/* #define USB_PIPEnCTR_A_F_RESERVED2 (0x3800u) */ +#define USB_PIPEnCTR_A_F_INBUFM (0x4000u) +#define USB_PIPEnCTR_A_F_BSTS (0x8000u) + +#define USB_PIPEnCTR_A_F_PID_SHIFT (0) +/* #define USB_PIPEnCTR_A_F_RESERVED1_SHIFT (2) */ +#define USB_PIPEnCTR_A_F_PBUSY_SHIFT (5) +#define USB_PIPEnCTR_A_F_SQMON_SHIFT (6) +#define USB_PIPEnCTR_A_F_SQSET_SHIFT (7) +#define USB_PIPEnCTR_A_F_SQCLR_SHIFT (8) +#define USB_PIPEnCTR_A_F_ACLRM_SHIFT (9) +#define USB_PIPEnCTR_A_F_ATREPM_SHIFT (10) +/* #define USB_PIPEnCTR_A_F_RESERVED2_SHIFT (11) */ +#define USB_PIPEnCTR_A_F_INBUFM_SHIFT (14) +#define USB_PIPEnCTR_A_F_BSTS_SHIFT (15) + +/*==============================================*/ +/* PIPEnTRE */ +/*==============================================*/ +/* #define USB_PIPEnTRE_RESERVED1 (0x00FFu) */ +#define USB_PIPEnTRE_TRCLR (0x0100u) +#define USB_PIPEnTRE_TRENB (0x0200u) +/* #define USB_PIPEnTRE_RESERVED2 (0xFC00u) */ + +/* #define USB_PIPEnTRE_RESERVED1_SHIFT (0) */ +#define USB_PIPEnTRE_TRCLR_SHIFT (8) +#define USB_PIPEnTRE_TRENB_SHIFT (9) +/* #define USB_PIPEnTRE_RESERVED2_SHIFT (10) */ + +/*==============================================*/ +/* PIPEnTRN */ +/*==============================================*/ +#define USB_PIPEnTRN (0xFFFFu) + +#define USB_PIPEnTRN_SHIFT (0) + +/*==============================================*/ +/* DEVADDn */ +/*==============================================*/ +/* #define USB_DEVADDn_RESERVED1 (0x003Fu) */ +#define USB_DEVADDn_USBSPD (0x00C0u) +#define USB_DEVADDn_HUBPORT (0x0700u) +#define USB_DEVADDn_UPPHUB (0x7800u) +/* #define USB_DEVADDn_RESERVED2 (0x8000u) */ + +/* #define USB_DEVADDn_RESERVED1_SHIFT (0) */ +#define USB_DEVADDn_USBSPD_SHIFT (6) +#define USB_DEVADDn_HUBPORT_SHIFT (8) +#define USB_DEVADDn_UPPHUB_SHIFT (11) +/* #define USB_DEVADDn_RESERVED2_SHIFT (15) */ + +/*==============================================*/ +/* SUSPMODE */ +/*==============================================*/ +/* #define USB_SUSPMODE_RESERVED1 (0x3FFFu) */ +#define USB_SUSPMODE_SUSPM (0x4000u) +/* #define USB_SUSPMODE_RESERVED2 (0x8000u) */ + +/* #define USB_SUSPMODE_RESERVED1_SHIFT (0) */ +#define USB_SUSPMODE_SUSPM_SHIFT (14) +/* #define USB_SUSPMODE_RESERVED2_SHIFT (15) */ + +/*==============================================*/ +/* DnFIFOBm */ +/*==============================================*/ +#define USB_DnFIFOBm (0xFFFFu) + +#define USB_DnFIFOBm_SHIFT (0) + +#endif /* USB_IOBITMASK_H */ + +/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,136 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef R7S72100_IODEFINE_H +#define R7S72100_IODEFINE_H +#define IODEFINE_H_VERSION 100 + +enum iodefine_byte_select_t +{ + L = 0, H = 1, + LL= 0, LH = 1, HL = 2, HH = 3 +}; + +/*********************************************************************** + <<< [iodefine_reg32_t] >>> +- Padding : sizeof(iodefine_reg32_t) == 4 +- Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2 +- &UINT8[0]==0, &UINT8[1]==1, &UINT8[2]==2, &UINT8[3]==3 +- Endian : Independent (Same as CPU endian as register endian) +- Bit-Order : Independent +************************************************************************/ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ +union iodefine_reg32_t +{ + volatile uint32_t UINT32; /* 32-bit Access */ + volatile uint16_t UINT16[2]; /* 16-bit Access */ + volatile uint8_t UINT8[4]; /* 8-bit Access */ +}; +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ + +/*********************************************************************** + <<< [iodefine_reg32_16_t] >>> +- Padding : sizeof(iodefine_reg32_16_t) == 4 +- Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2 +- Endian : Independent (Same as CPU endian as register endian) +- Bit-Order : Independent +************************************************************************/ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ +union iodefine_reg32_16_t +{ + volatile uint32_t UINT32; /* 32-bit Access */ + volatile uint16_t UINT16[2]; /* 16-bit Access */ +}; +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ + +/*********************************************************************** + <<< [iodefine_reg16_8_t] >>> +- Padding : sizeof(iodefine_reg16_8_t) == 2 +- Alignment(Offset) : &UINT16==0, &UINT8[0]==0, &UINT8[1]==1 +- Endian : Independent (Same as CPU endian as register endian) +- Bit-Order : Independent +************************************************************************/ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ +union iodefine_reg16_8_t +{ + volatile uint16_t UINT16; /* 16-bit Access */ + volatile uint8_t UINT8[2]; /* 8-bit Access */ +}; +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ + + + + + + +#include "adc_iodefine.h" /* (V1.00a) */ +#include "bsc_iodefine.h" /* (V1.00a) */ +#include "ceu_iodefine.h" /* (V1.00a) */ +#include "cpg_iodefine.h" /* (V1.00a) */ +#include "disc_iodefine.h" /* (V1.00a) */ +#include "dmac_iodefine.h" /* (V1.00a) */ +#include "dvdec_iodefine.h" /* (V1.00a) */ +#include "ether_iodefine.h" /* (V1.00a) */ +#include "flctl_iodefine.h" /* (V1.00a) */ +#include "gpio_iodefine.h" /* (V1.00a) */ +#include "ieb_iodefine.h" /* (V1.00a) */ +#include "inb_iodefine.h" /* (V1.00a) */ +#include "intc_iodefine.h" /* (V1.00a) */ +#include "irda_iodefine.h" /* (V1.00a) */ +#include "jcu_iodefine.h" /* (V1.00a) */ +#include "l2c_iodefine.h" /* (V1.00a) */ +#include "lin_iodefine.h" /* (V1.00a) */ +#include "lvds_iodefine.h" /* (V1.00a) */ +#include "mlb_iodefine.h" /* (V1.00a) */ +#include "mmc_iodefine.h" /* (V1.00a) */ +#include "mtu2_iodefine.h" /* (V1.00a) */ +#include "ostm_iodefine.h" /* (V1.00a) */ +#include "pfv_iodefine.h" /* (V1.00a) */ +#include "pwm_iodefine.h" /* (V1.00a) */ +#include "riic_iodefine.h" /* (V1.00a) */ +#include "romdec_iodefine.h" /* (V1.00a) */ +#include "rscan0_iodefine.h" /* (V1.00a) */ +#include "rspi_iodefine.h" /* (V1.00a) */ +#include "rtc_iodefine.h" /* (V1.00a) */ +#include "scif_iodefine.h" /* (V1.00a) */ +#include "scim_iodefine.h" /* (V1.00a) */ +#include "scux_iodefine.h" /* (V1.00a) */ +#include "sdg_iodefine.h" /* (V1.00a) */ +#include "spdif_iodefine.h" /* (V1.00a) */ +#include "spibsc_iodefine.h" /* (V1.00a) */ +#include "ssif_iodefine.h" /* (V1.00a) */ +#include "usb20_iodefine.h" /* (V1.00a) */ +#include "vdc5_iodefine.h" /* (V1.00a) */ +#include "wdt_iodefine.h" /* (V1.00a) */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/adc_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,98 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : adc_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef ADC_IODEFINE_H +#define ADC_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_adc +{ /* ADC */ + volatile uint16_t ADDRA; /* ADDRA */ + volatile uint16_t ADDRB; /* ADDRB */ + volatile uint16_t ADDRC; /* ADDRC */ + volatile uint16_t ADDRD; /* ADDRD */ + volatile uint16_t ADDRE; /* ADDRE */ + volatile uint16_t ADDRF; /* ADDRF */ + volatile uint16_t ADDRG; /* ADDRG */ + volatile uint16_t ADDRH; /* ADDRH */ + volatile uint8_t dummy32[16]; /* */ + volatile uint16_t ADCMPHA; /* ADCMPHA */ + volatile uint16_t ADCMPLA; /* ADCMPLA */ + volatile uint16_t ADCMPHB; /* ADCMPHB */ + volatile uint16_t ADCMPLB; /* ADCMPLB */ + volatile uint16_t ADCMPHC; /* ADCMPHC */ + volatile uint16_t ADCMPLC; /* ADCMPLC */ + volatile uint16_t ADCMPHD; /* ADCMPHD */ + volatile uint16_t ADCMPLD; /* ADCMPLD */ + volatile uint16_t ADCMPHE; /* ADCMPHE */ + volatile uint16_t ADCMPLE; /* ADCMPLE */ + volatile uint16_t ADCMPHF; /* ADCMPHF */ + volatile uint16_t ADCMPLF; /* ADCMPLF */ + volatile uint16_t ADCMPHG; /* ADCMPHG */ + volatile uint16_t ADCMPLG; /* ADCMPLG */ + volatile uint16_t ADCMPHH; /* ADCMPHH */ + volatile uint16_t ADCMPLH; /* ADCMPLH */ + volatile uint8_t dummy33[32]; /* */ + volatile uint16_t ADCSR; /* ADCSR */ + volatile uint16_t ADCMPER; /* ADCMPER */ + volatile uint16_t ADCMPSR; /* ADCMPSR */ +}; + + +#define ADC (*(struct st_adc *)0xE8005800uL) /* ADC */ + + +#define ADCADDRA ADC.ADDRA +#define ADCADDRB ADC.ADDRB +#define ADCADDRC ADC.ADDRC +#define ADCADDRD ADC.ADDRD +#define ADCADDRE ADC.ADDRE +#define ADCADDRF ADC.ADDRF +#define ADCADDRG ADC.ADDRG +#define ADCADDRH ADC.ADDRH +#define ADCADCMPHA ADC.ADCMPHA +#define ADCADCMPLA ADC.ADCMPLA +#define ADCADCMPHB ADC.ADCMPHB +#define ADCADCMPLB ADC.ADCMPLB +#define ADCADCMPHC ADC.ADCMPHC +#define ADCADCMPLC ADC.ADCMPLC +#define ADCADCMPHD ADC.ADCMPHD +#define ADCADCMPLD ADC.ADCMPLD +#define ADCADCMPHE ADC.ADCMPHE +#define ADCADCMPLE ADC.ADCMPLE +#define ADCADCMPHF ADC.ADCMPHF +#define ADCADCMPLF ADC.ADCMPLF +#define ADCADCMPHG ADC.ADCMPHG +#define ADCADCMPLG ADC.ADCMPLG +#define ADCADCMPHH ADC.ADCMPHH +#define ADCADCMPLH ADC.ADCMPLH +#define ADCADCSR ADC.ADCSR +#define ADCADCMPER ADC.ADCMPER +#define ADCADCMPSR ADC.ADCMPSR +/* <-SEC M1.10.1 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/bsc_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,99 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : bsc_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef BSC_IODEFINE_H +#define BSC_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_bsc +{ /* BSC */ + volatile uint32_t CMNCR; /* CMNCR */ +#define BSC_CSnBCR_COUNT 6 + volatile uint32_t CS0BCR; /* CS0BCR */ + volatile uint32_t CS1BCR; /* CS1BCR */ + volatile uint32_t CS2BCR; /* CS2BCR */ + volatile uint32_t CS3BCR; /* CS3BCR */ + volatile uint32_t CS4BCR; /* CS4BCR */ + volatile uint32_t CS5BCR; /* CS5BCR */ + volatile uint8_t dummy4[12]; /* */ +#define BSC_CSnWCR_COUNT 6 + volatile uint32_t CS0WCR; /* CS0WCR */ + volatile uint32_t CS1WCR; /* CS1WCR */ + volatile uint32_t CS2WCR; /* CS2WCR */ + volatile uint32_t CS3WCR; /* CS3WCR */ + volatile uint32_t CS4WCR; /* CS4WCR */ + volatile uint32_t CS5WCR; /* CS5WCR */ + volatile uint8_t dummy5[12]; /* */ + volatile uint32_t SDCR; /* SDCR */ + volatile uint32_t RTCSR; /* RTCSR */ + volatile uint32_t RTCNT; /* RTCNT */ + volatile uint32_t RTCOR; /* RTCOR */ + volatile uint8_t dummy6[4]; /* */ +#define BSC_TOSCORn_COUNT 6 + volatile uint32_t TOSCOR0; /* TOSCOR0 */ + volatile uint32_t TOSCOR1; /* TOSCOR1 */ + volatile uint32_t TOSCOR2; /* TOSCOR2 */ + volatile uint32_t TOSCOR3; /* TOSCOR3 */ + volatile uint32_t TOSCOR4; /* TOSCOR4 */ + volatile uint32_t TOSCOR5; /* TOSCOR5 */ + volatile uint8_t dummy7[8]; /* */ + volatile uint32_t TOSTR; /* TOSTR */ + volatile uint32_t TOENR; /* TOENR */ +}; + + +#define BSC (*(struct st_bsc *)0x3FFFC000uL) /* BSC */ + + +#define BSCCMNCR BSC.CMNCR +#define BSCCS0BCR BSC.CS0BCR +#define BSCCS1BCR BSC.CS1BCR +#define BSCCS2BCR BSC.CS2BCR +#define BSCCS3BCR BSC.CS3BCR +#define BSCCS4BCR BSC.CS4BCR +#define BSCCS5BCR BSC.CS5BCR +#define BSCCS0WCR BSC.CS0WCR +#define BSCCS1WCR BSC.CS1WCR +#define BSCCS2WCR BSC.CS2WCR +#define BSCCS3WCR BSC.CS3WCR +#define BSCCS4WCR BSC.CS4WCR +#define BSCCS5WCR BSC.CS5WCR +#define BSCSDCR BSC.SDCR +#define BSCRTCSR BSC.RTCSR +#define BSCRTCNT BSC.RTCNT +#define BSCRTCOR BSC.RTCOR +#define BSCTOSCOR0 BSC.TOSCOR0 +#define BSCTOSCOR1 BSC.TOSCOR1 +#define BSCTOSCOR2 BSC.TOSCOR2 +#define BSCTOSCOR3 BSC.TOSCOR3 +#define BSCTOSCOR4 BSC.TOSCOR4 +#define BSCTOSCOR5 BSC.TOSCOR5 +#define BSCTOSTR BSC.TOSTR +#define BSCTOENR BSC.TOENR +/* <-SEC M1.10.1 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/ceu_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,269 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : ceu_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef CEU_IODEFINE_H +#define CEU_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_ceu +{ /* CEU */ +/* start of struct st_ceu_n */ + volatile uint32_t CAPSR; /* CAPSR */ + volatile uint32_t CAPCR; /* CAPCR */ + volatile uint32_t CAMCR; /* CAMCR */ + volatile uint32_t CMCYR; /* CMCYR */ + volatile uint32_t CAMOR_A; /* CAMOR_A */ + volatile uint32_t CAPWR_A; /* CAPWR_A */ + volatile uint32_t CAIFR; /* CAIFR */ + volatile uint8_t dummy305[12]; /* */ + volatile uint32_t CRCNTR; /* CRCNTR */ + volatile uint32_t CRCMPR; /* CRCMPR */ + volatile uint32_t CFLCR_A; /* CFLCR_A */ + volatile uint32_t CFSZR_A; /* CFSZR_A */ + volatile uint32_t CDWDR_A; /* CDWDR_A */ + volatile uint32_t CDAYR_A; /* CDAYR_A */ + volatile uint32_t CDACR_A; /* CDACR_A */ + volatile uint32_t CDBYR_A; /* CDBYR_A */ + volatile uint32_t CDBCR_A; /* CDBCR_A */ + volatile uint32_t CBDSR_A; /* CBDSR_A */ + volatile uint8_t dummy306[12]; /* */ + volatile uint32_t CFWCR; /* CFWCR */ + volatile uint32_t CLFCR_A; /* CLFCR_A */ + volatile uint32_t CDOCR_A; /* CDOCR_A */ + volatile uint8_t dummy307[8]; /* */ + volatile uint32_t CEIER; /* CEIER */ + volatile uint32_t CETCR; /* CETCR */ + volatile uint8_t dummy308[4]; /* */ + volatile uint32_t CSTSR; /* CSTSR */ + volatile uint8_t dummy309[4]; /* */ + volatile uint32_t CDSSR; /* CDSSR */ + volatile uint8_t dummy310[8]; /* */ + volatile uint32_t CDAYR2_A; /* CDAYR2_A */ + volatile uint32_t CDACR2_A; /* CDACR2_A */ + volatile uint32_t CDBYR2_A; /* CDBYR2_A */ + volatile uint32_t CDBCR2_A; /* CDBCR2_A */ +/* end of struct st_ceu_n */ + volatile uint8_t dummy3110[3936]; /* */ +/* start of struct st_ceu_n */ + volatile uint8_t dummy3111[4]; /* */ + volatile uint8_t dummy3112[4]; /* */ + volatile uint8_t dummy3113[4]; /* */ + volatile uint8_t dummy3114[4]; /* */ + volatile uint32_t CAMOR_B; /* CAMOR_B */ + volatile uint32_t CAPWR_B; /* CAPWR_B */ + volatile uint8_t dummy3120[4]; /* */ + volatile uint8_t dummy3121[12]; /* */ + volatile uint8_t dummy3122[4]; /* */ + volatile uint8_t dummy3123[4]; /* */ + volatile uint32_t CFLCR_B; /* CFLCR_B */ + volatile uint32_t CFSZR_B; /* CFSZR_B */ + volatile uint32_t CDWDR_B; /* CDWDR_B */ + volatile uint32_t CDAYR_B; /* CDAYR_B */ + volatile uint32_t CDACR_B; /* CDACR_B */ + volatile uint32_t CDBYR_B; /* CDBYR_B */ + volatile uint32_t CDBCR_B; /* CDBCR_B */ + volatile uint32_t CBDSR_B; /* CBDSR_B */ + volatile uint8_t dummy3130[12]; /* */ + volatile uint8_t dummy3131[4]; /* */ + volatile uint32_t CLFCR_B; /* CLFCR_B */ + volatile uint32_t CDOCR_B; /* CDOCR_B */ + volatile uint8_t dummy3140[8]; /* */ + volatile uint8_t dummy3141[4]; /* */ + volatile uint8_t dummy3142[4]; /* */ + volatile uint8_t dummy3143[4]; /* */ + volatile uint8_t dummy3144[4]; /* */ + volatile uint8_t dummy3145[4]; /* */ + volatile uint8_t dummy3146[4]; /* */ + volatile uint8_t dummy3147[8]; /* */ + volatile uint32_t CDAYR2_B; /* CDAYR2_B */ + volatile uint32_t CDACR2_B; /* CDACR2_B */ + volatile uint32_t CDBYR2_B; /* CDBYR2_B */ + volatile uint32_t CDBCR2_B; /* CDBCR2_B */ +/* end of struct st_ceu_n */ + volatile uint8_t dummy3150[3936]; /* */ +/* start of struct st_ceu_n */ + volatile uint8_t dummy3151[4]; /* */ + volatile uint8_t dummy3152[4]; /* */ + volatile uint8_t dummy3153[4]; /* */ + volatile uint8_t dummy3154[4]; /* */ + volatile uint32_t CAMOR_M; /* CAMOR_M */ + volatile uint32_t CAPWR_M; /* CAPWR_M */ + volatile uint8_t dummy3160[4]; /* */ + volatile uint8_t dummy3161[12]; /* */ + volatile uint8_t dummy3162[4]; /* */ + volatile uint8_t dummy3163[4]; /* */ + volatile uint32_t CFLCR_M; /* CFLCR_M */ + volatile uint32_t CFSZR_M; /* CFSZR_M */ + volatile uint32_t CDWDR_M; /* CDWDR_M */ + volatile uint32_t CDAYR_M; /* CDAYR_M */ + volatile uint32_t CDACR_M; /* CDACR_M */ + volatile uint32_t CDBYR_M; /* CDBYR_M */ + volatile uint32_t CDBCR_M; /* CDBCR_M */ + volatile uint32_t CBDSR_M; /* CBDSR_M */ + volatile uint8_t dummy3170[12]; /* */ + volatile uint8_t dummy3171[4]; /* */ + volatile uint32_t CLFCR_M; /* CLFCR_M */ + volatile uint32_t CDOCR_M; /* CDOCR_M */ + volatile uint8_t dummy3180[8]; /* */ + volatile uint8_t dummy3181[4]; /* */ + volatile uint8_t dummy3182[4]; /* */ + volatile uint8_t dummy3183[4]; /* */ + volatile uint8_t dummy3184[4]; /* */ + volatile uint8_t dummy3185[4]; /* */ + volatile uint8_t dummy3186[4]; /* */ + volatile uint8_t dummy3187[8]; /* */ + volatile uint32_t CDAYR2_M; /* CDAYR2_M */ + volatile uint32_t CDACR2_M; /* CDACR2_M */ + volatile uint32_t CDBYR2_M; /* CDBYR2_M */ + volatile uint32_t CDBCR2_M; /* CDBCR2_M */ +/* end of struct st_ceu_n */ +}; + + +struct st_ceu_n +{ + volatile uint32_t not_common1; /* */ + volatile uint32_t not_common2; /* */ + volatile uint32_t not_common3; /* */ + volatile uint32_t not_common4; /* */ + volatile uint32_t CAMOR; /* CAMOR */ + volatile uint32_t CAPWR; /* CAPWR */ + volatile uint32_t not_common5; /* */ + volatile uint8_t dummy322[12]; /* */ + volatile uint32_t not_common6; /* */ + volatile uint32_t not_common7; /* */ + volatile uint32_t CFLCR; /* CFLCR */ + volatile uint32_t CFSZR; /* CFSZR */ + volatile uint32_t CDWDR; /* CDWDR */ + volatile uint32_t CDAYR; /* CDAYR */ + volatile uint32_t CDACR; /* CDACR */ + volatile uint32_t CDBYR; /* CDBYR */ + volatile uint32_t CDBCR; /* CDBCR */ + volatile uint32_t CBDSR; /* CBDSR */ + volatile uint8_t dummy323[12]; /* */ + volatile uint32_t not_common8; /* */ + volatile uint32_t CLFCR; /* CLFCR */ + volatile uint32_t CDOCR; /* CDOCR */ + volatile uint8_t dummy324[8]; /* */ + volatile uint32_t not_common9; /* */ + volatile uint32_t not_common10; /* */ + volatile uint8_t dummy325[4]; /* */ + volatile uint32_t not_common11; /* */ + volatile uint8_t dummy326[4]; /* */ + volatile uint32_t not_common12; /* */ + volatile uint8_t dummy327[8]; /* */ + volatile uint32_t CDAYR2; /* CDAYR2 */ + volatile uint32_t CDACR2; /* CDACR2 */ + volatile uint32_t CDBYR2; /* CDBYR2 */ + volatile uint32_t CDBCR2; /* CDBCR2 */ +}; + + +#define CEU (*(struct st_ceu *)0xE8210000uL) /* CEU */ + + +/* Start of channnel array defines of CEU */ + +/* Channnel array defines of CEUn */ +/*(Sample) value = CEUn[ channel ]->CAMOR; */ +#define CEUn_COUNT 3 +#define CEUn_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + (volatile struct st_ceu_n*)&CEU_A, \ + (volatile struct st_ceu_n*)&CEU_B, \ + (volatile struct st_ceu_n*)&CEU_M \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define CEU_A (*(struct st_ceu_n *)&CEU.CAPSR) /* CEU_A */ +#define CEU_B (*(struct st_ceu_n *)&CEU.dummy3111) /* CEU_B */ +#define CEU_M (*(struct st_ceu_n *)&CEU.dummy3151) /* CEU_M */ + +/* End of channnel array defines of CEU */ + + +#define CEUCAPSR CEU.CAPSR +#define CEUCAPCR CEU.CAPCR +#define CEUCAMCR CEU.CAMCR +#define CEUCMCYR CEU.CMCYR +#define CEUCAMOR_A CEU.CAMOR_A +#define CEUCAPWR_A CEU.CAPWR_A +#define CEUCAIFR CEU.CAIFR +#define CEUCRCNTR CEU.CRCNTR +#define CEUCRCMPR CEU.CRCMPR +#define CEUCFLCR_A CEU.CFLCR_A +#define CEUCFSZR_A CEU.CFSZR_A +#define CEUCDWDR_A CEU.CDWDR_A +#define CEUCDAYR_A CEU.CDAYR_A +#define CEUCDACR_A CEU.CDACR_A +#define CEUCDBYR_A CEU.CDBYR_A +#define CEUCDBCR_A CEU.CDBCR_A +#define CEUCBDSR_A CEU.CBDSR_A +#define CEUCFWCR CEU.CFWCR +#define CEUCLFCR_A CEU.CLFCR_A +#define CEUCDOCR_A CEU.CDOCR_A +#define CEUCEIER CEU.CEIER +#define CEUCETCR CEU.CETCR +#define CEUCSTSR CEU.CSTSR +#define CEUCDSSR CEU.CDSSR +#define CEUCDAYR2_A CEU.CDAYR2_A +#define CEUCDACR2_A CEU.CDACR2_A +#define CEUCDBYR2_A CEU.CDBYR2_A +#define CEUCDBCR2_A CEU.CDBCR2_A +#define CEUCAMOR_B CEU.CAMOR_B +#define CEUCAPWR_B CEU.CAPWR_B +#define CEUCFLCR_B CEU.CFLCR_B +#define CEUCFSZR_B CEU.CFSZR_B +#define CEUCDWDR_B CEU.CDWDR_B +#define CEUCDAYR_B CEU.CDAYR_B +#define CEUCDACR_B CEU.CDACR_B +#define CEUCDBYR_B CEU.CDBYR_B +#define CEUCDBCR_B CEU.CDBCR_B +#define CEUCBDSR_B CEU.CBDSR_B +#define CEUCLFCR_B CEU.CLFCR_B +#define CEUCDOCR_B CEU.CDOCR_B +#define CEUCDAYR2_B CEU.CDAYR2_B +#define CEUCDACR2_B CEU.CDACR2_B +#define CEUCDBYR2_B CEU.CDBYR2_B +#define CEUCDBCR2_B CEU.CDBCR2_B +#define CEUCAMOR_M CEU.CAMOR_M +#define CEUCAPWR_M CEU.CAPWR_M +#define CEUCFLCR_M CEU.CFLCR_M +#define CEUCFSZR_M CEU.CFSZR_M +#define CEUCDWDR_M CEU.CDWDR_M +#define CEUCDAYR_M CEU.CDAYR_M +#define CEUCDACR_M CEU.CDACR_M +#define CEUCDBYR_M CEU.CDBYR_M +#define CEUCDBCR_M CEU.CDBCR_M +#define CEUCBDSR_M CEU.CBDSR_M +#define CEUCLFCR_M CEU.CLFCR_M +#define CEUCDOCR_M CEU.CDOCR_M +#define CEUCDAYR2_M CEU.CDAYR2_M +#define CEUCDACR2_M CEU.CDACR2_M +#define CEUCDBYR2_M CEU.CDBYR2_M +#define CEUCDBCR2_M CEU.CDBCR2_M +/* <-SEC M1.10.1 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/cpg_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,239 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : cpg_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef CPG_IODEFINE_H +#define CPG_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_cpg +{ /* CPG */ + volatile uint16_t FRQCR; /* FRQCR */ + volatile uint8_t dummy319[2]; /* */ + volatile uint16_t FRQCR2; /* FRQCR2 */ + volatile uint8_t dummy320[2]; /* */ + volatile uint8_t CPUSTS; /* CPUSTS */ + volatile uint8_t dummy321[7]; /* */ + volatile uint8_t STBCR1; /* STBCR1 */ + volatile uint8_t dummy322[3]; /* */ + volatile uint8_t STBCR2; /* STBCR2 */ + volatile uint8_t dummy323[11]; /* */ + volatile uint8_t STBREQ1; /* STBREQ1 */ + volatile uint8_t dummy324[3]; /* */ + volatile uint8_t STBREQ2; /* STBREQ2 */ + volatile uint8_t dummy325[11]; /* */ + volatile uint8_t STBACK1; /* STBACK1 */ + volatile uint8_t dummy326[3]; /* */ + volatile uint8_t STBACK2; /* STBACK2 */ + volatile uint8_t dummy327[955]; /* */ +/* start of struct st_cpg_from_syscr1 */ + volatile uint8_t SYSCR1; /* SYSCR1 */ + volatile uint8_t dummy328[3]; /* */ +/* end of struct st_cpg_from_syscr1 */ +/* start of struct st_cpg_from_syscr1 */ + volatile uint8_t SYSCR2; /* SYSCR2 */ + volatile uint8_t dummy329[3]; /* */ +/* end of struct st_cpg_from_syscr1 */ +/* start of struct st_cpg_from_syscr1 */ + volatile uint8_t SYSCR3; /* SYSCR3 */ + volatile uint8_t dummy3300[3]; /* */ +/* end of struct st_cpg_from_syscr1 */ + volatile uint8_t dummy3301[20]; /* */ +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR3; /* STBCR3 */ + volatile uint8_t dummy331[3]; /* */ +/* end of struct st_cpg_from_stbcr3 */ +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR4; /* STBCR4 */ + volatile uint8_t dummy332[3]; /* */ +/* end of struct st_cpg_from_stbcr3 */ +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR5; /* STBCR5 */ + volatile uint8_t dummy333[3]; /* */ +/* end of struct st_cpg_from_stbcr3 */ +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR6; /* STBCR6 */ + volatile uint8_t dummy334[3]; /* */ +/* end of struct st_cpg_from_stbcr3 */ +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR7; /* STBCR7 */ + volatile uint8_t dummy335[3]; /* */ +/* end of struct st_cpg_from_stbcr3 */ +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR8; /* STBCR8 */ + volatile uint8_t dummy336[3]; /* */ +/* end of struct st_cpg_from_stbcr3 */ +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR9; /* STBCR9 */ + volatile uint8_t dummy337[3]; /* */ +/* end of struct st_cpg_from_stbcr3 */ +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR10; /* STBCR10 */ + volatile uint8_t dummy338[3]; /* */ +/* end of struct st_cpg_from_stbcr3 */ +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR11; /* STBCR11 */ + volatile uint8_t dummy339[3]; /* */ +/* end of struct st_cpg_from_stbcr3 */ +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR12; /* STBCR12 */ + volatile uint8_t dummy3400[3]; /* */ +/* end of struct st_cpg_from_stbcr3 */ + volatile uint8_t dummy3401[24]; /* */ +/* start of struct st_cpg_from_swrstcr1 */ + volatile uint8_t SWRSTCR1; /* SWRSTCR1 */ + volatile uint8_t dummy341[3]; /* */ +/* end of struct st_cpg_from_swrstcr1 */ +/* start of struct st_cpg_from_swrstcr1 */ + volatile uint8_t SWRSTCR2; /* SWRSTCR2 */ + volatile uint8_t dummy342[3]; /* */ +/* end of struct st_cpg_from_swrstcr1 */ +/* start of struct st_cpg_from_swrstcr1 */ + volatile uint8_t SWRSTCR3; /* SWRSTCR3 */ + volatile uint8_t dummy3430[3]; /* */ +/* end of struct st_cpg_from_swrstcr1 */ + volatile uint8_t dummy3431[4]; /* */ + volatile uint8_t STBCR13; /* STBCR13 */ + volatile uint8_t dummy344[70543]; /* */ + volatile uint8_t RRAMKP; /* RRAMKP */ + volatile uint8_t dummy345[1]; /* */ + volatile uint8_t DSCTR; /* DSCTR */ + volatile uint8_t dummy346[1]; /* */ + volatile uint16_t DSSSR; /* DSSSR */ + volatile uint16_t DSESR; /* DSESR */ + volatile uint16_t DSFR; /* DSFR */ + volatile uint8_t dummy347[6]; /* */ + volatile uint8_t XTALCTR; /* XTALCTR */ +}; + + +struct st_cpg_from_syscr1 +{ + volatile uint8_t SYSCR1; /* SYSCR1 */ + volatile uint8_t dummy1[3]; /* */ +}; + + +struct st_cpg_from_stbcr3 +{ + volatile uint8_t STBCR3; /* STBCR3 */ + volatile uint8_t dummy1[3]; /* */ +}; + + +struct st_cpg_from_swrstcr1 +{ + volatile uint8_t SWRSTCR1; /* SWRSTCR1 */ + volatile uint8_t dummy1[3]; /* */ +}; + + +#define CPG (*(struct st_cpg *)0xFCFE0010uL) /* CPG */ + + +/* Start of channnel array defines of CPG */ + +/* Channnel array defines of CPG_FROM_SWRSTCR1_ARRAY */ +/*(Sample) value = CPG_FROM_SWRSTCR1_ARRAY[ channel ]->SWRSTCR1; */ +#define CPG_FROM_SWRSTCR1_ARRAY_COUNT 3 +#define CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &CPG_FROM_SWRSTCR1, &CPG_FROM_SWRSTCR2, &CPG_FROM_SWRSTCR3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define CPG_FROM_SWRSTCR1 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR1) /* CPG_FROM_SWRSTCR1 */ +#define CPG_FROM_SWRSTCR2 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR2) /* CPG_FROM_SWRSTCR2 */ +#define CPG_FROM_SWRSTCR3 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR3) /* CPG_FROM_SWRSTCR3 */ + + +/* Channnel array defines of CPG_FROM_STBCR3_ARRAY */ +/*(Sample) value = CPG_FROM_STBCR3_ARRAY[ channel ]->STBCR3; */ +#define CPG_FROM_STBCR3_ARRAY_COUNT 10 +#define CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &CPG_FROM_STBCR3, &CPG_FROM_STBCR4, &CPG_FROM_STBCR5, &CPG_FROM_STBCR6, &CPG_FROM_STBCR7, &CPG_FROM_STBCR8, &CPG_FROM_STBCR9, &CPG_FROM_STBCR10, \ + &CPG_FROM_STBCR11, &CPG_FROM_STBCR12 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define CPG_FROM_STBCR3 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR3) /* CPG_FROM_STBCR3 */ +#define CPG_FROM_STBCR4 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR4) /* CPG_FROM_STBCR4 */ +#define CPG_FROM_STBCR5 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR5) /* CPG_FROM_STBCR5 */ +#define CPG_FROM_STBCR6 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR6) /* CPG_FROM_STBCR6 */ +#define CPG_FROM_STBCR7 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR7) /* CPG_FROM_STBCR7 */ +#define CPG_FROM_STBCR8 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR8) /* CPG_FROM_STBCR8 */ +#define CPG_FROM_STBCR9 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR9) /* CPG_FROM_STBCR9 */ +#define CPG_FROM_STBCR10 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR10) /* CPG_FROM_STBCR10 */ +#define CPG_FROM_STBCR11 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR11) /* CPG_FROM_STBCR11 */ +#define CPG_FROM_STBCR12 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR12) /* CPG_FROM_STBCR12 */ + + +/* Channnel array defines of CPG_FROM_SYSCR1_ARRAY */ +/*(Sample) value = CPG_FROM_SYSCR1_ARRAY[ channel ]->SYSCR1; */ +#define CPG_FROM_SYSCR1_ARRAY_COUNT 3 +#define CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &CPG_FROM_SYSCR1, &CPG_FROM_SYSCR2, &CPG_FROM_SYSCR3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define CPG_FROM_SYSCR1 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR1) /* CPG_FROM_SYSCR1 */ +#define CPG_FROM_SYSCR2 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR2) /* CPG_FROM_SYSCR2 */ +#define CPG_FROM_SYSCR3 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR3) /* CPG_FROM_SYSCR3 */ + +/* End of channnel array defines of CPG */ + + +#define CPGFRQCR CPG.FRQCR +#define CPGFRQCR2 CPG.FRQCR2 +#define CPGCPUSTS CPG.CPUSTS +#define CPGSTBCR1 CPG.STBCR1 +#define CPGSTBCR2 CPG.STBCR2 +#define CPGSTBREQ1 CPG.STBREQ1 +#define CPGSTBREQ2 CPG.STBREQ2 +#define CPGSTBACK1 CPG.STBACK1 +#define CPGSTBACK2 CPG.STBACK2 +#define CPGSYSCR1 CPG.SYSCR1 +#define CPGSYSCR2 CPG.SYSCR2 +#define CPGSYSCR3 CPG.SYSCR3 +#define CPGSTBCR3 CPG.STBCR3 +#define CPGSTBCR4 CPG.STBCR4 +#define CPGSTBCR5 CPG.STBCR5 +#define CPGSTBCR6 CPG.STBCR6 +#define CPGSTBCR7 CPG.STBCR7 +#define CPGSTBCR8 CPG.STBCR8 +#define CPGSTBCR9 CPG.STBCR9 +#define CPGSTBCR10 CPG.STBCR10 +#define CPGSTBCR11 CPG.STBCR11 +#define CPGSTBCR12 CPG.STBCR12 +#define CPGSWRSTCR1 CPG.SWRSTCR1 +#define CPGSWRSTCR2 CPG.SWRSTCR2 +#define CPGSWRSTCR3 CPG.SWRSTCR3 +#define CPGSTBCR13 CPG.STBCR13 +#define CPGRRAMKP CPG.RRAMKP +#define CPGDSCTR CPG.DSCTR +#define CPGDSSSR CPG.DSSSR +#define CPGDSESR CPG.DSESR +#define CPGDSFR CPG.DSFR +#define CPGXTALCTR CPG.XTALCTR +/* <-SEC M1.10.1 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/disc_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,93 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : disc_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef DISC_IODEFINE_H +#define DISC_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_disc +{ /* DISC */ + volatile uint32_t DOCMCR; /* DOCMCR */ + volatile uint32_t DOCMSTR; /* DOCMSTR */ + volatile uint32_t DOCMCLSTR; /* DOCMCLSTR */ + volatile uint32_t DOCMIENR; /* DOCMIENR */ + volatile uint8_t dummy1[4]; /* */ + volatile uint32_t DOCMPMR; /* DOCMPMR */ + volatile uint32_t DOCMECRCR; /* DOCMECRCR */ + volatile uint32_t DOCMCCRCR; /* DOCMCCRCR */ + volatile uint32_t DOCMSPXR; /* DOCMSPXR */ + volatile uint32_t DOCMSPYR; /* DOCMSPYR */ + volatile uint32_t DOCMSZXR; /* DOCMSZXR */ + volatile uint32_t DOCMSZYR; /* DOCMSZYR */ + volatile uint32_t DOCMCRCIR; /* DOCMCRCIR */ +}; + + +#define DISC0 (*(struct st_disc *)0xFCFFA800uL) /* DISC0 */ +#define DISC1 (*(struct st_disc *)0xFCFFB000uL) /* DISC1 */ + + +/* Start of channnel array defines of DISC */ + +/* Channnel array defines of DISC */ +/*(Sample) value = DISC[ channel ]->DOCMCR; */ +#define DISC_COUNT 2 +#define DISC_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &DISC0, &DISC1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channnel array defines of DISC */ + + +#define DISC0DOCMCR DISC0.DOCMCR +#define DISC0DOCMSTR DISC0.DOCMSTR +#define DISC0DOCMCLSTR DISC0.DOCMCLSTR +#define DISC0DOCMIENR DISC0.DOCMIENR +#define DISC0DOCMPMR DISC0.DOCMPMR +#define DISC0DOCMECRCR DISC0.DOCMECRCR +#define DISC0DOCMCCRCR DISC0.DOCMCCRCR +#define DISC0DOCMSPXR DISC0.DOCMSPXR +#define DISC0DOCMSPYR DISC0.DOCMSPYR +#define DISC0DOCMSZXR DISC0.DOCMSZXR +#define DISC0DOCMSZYR DISC0.DOCMSZYR +#define DISC0DOCMCRCIR DISC0.DOCMCRCIR +#define DISC1DOCMCR DISC1.DOCMCR +#define DISC1DOCMSTR DISC1.DOCMSTR +#define DISC1DOCMCLSTR DISC1.DOCMCLSTR +#define DISC1DOCMIENR DISC1.DOCMIENR +#define DISC1DOCMPMR DISC1.DOCMPMR +#define DISC1DOCMECRCR DISC1.DOCMECRCR +#define DISC1DOCMCCRCR DISC1.DOCMCCRCR +#define DISC1DOCMSPXR DISC1.DOCMSPXR +#define DISC1DOCMSPYR DISC1.DOCMSPYR +#define DISC1DOCMSZXR DISC1.DOCMSZXR +#define DISC1DOCMSZYR DISC1.DOCMSZYR +#define DISC1DOCMCRCIR DISC1.DOCMCRCIR +/* <-SEC M1.10.1 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/dmac_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,733 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : dmac_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef DMAC_IODEFINE_H +#define DMAC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->SEC M1.10.1 : Not magic number */ + +struct st_dmac +{ /* DMAC */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_0; /* N0SA_0 */ + volatile uint32_t N0DA_0; /* N0DA_0 */ + volatile uint32_t N0TB_0; /* N0TB_0 */ + volatile uint32_t N1SA_0; /* N1SA_0 */ + volatile uint32_t N1DA_0; /* N1DA_0 */ + volatile uint32_t N1TB_0; /* N1TB_0 */ + volatile uint32_t CRSA_0; /* CRSA_0 */ + volatile uint32_t CRDA_0; /* CRDA_0 */ + volatile uint32_t CRTB_0; /* CRTB_0 */ + volatile uint32_t CHSTAT_0; /* CHSTAT_0 */ + volatile uint32_t CHCTRL_0; /* CHCTRL_0 */ + volatile uint32_t CHCFG_0; /* CHCFG_0 */ + volatile uint32_t CHITVL_0; /* CHITVL_0 */ + volatile uint32_t CHEXT_0; /* CHEXT_0 */ + volatile uint32_t NXLA_0; /* NXLA_0 */ + volatile uint32_t CRLA_0; /* CRLA_0 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_1; /* N0SA_1 */ + volatile uint32_t N0DA_1; /* N0DA_1 */ + volatile uint32_t N0TB_1; /* N0TB_1 */ + volatile uint32_t N1SA_1; /* N1SA_1 */ + volatile uint32_t N1DA_1; /* N1DA_1 */ + volatile uint32_t N1TB_1; /* N1TB_1 */ + volatile uint32_t CRSA_1; /* CRSA_1 */ + volatile uint32_t CRDA_1; /* CRDA_1 */ + volatile uint32_t CRTB_1; /* CRTB_1 */ + volatile uint32_t CHSTAT_1; /* CHSTAT_1 */ + volatile uint32_t CHCTRL_1; /* CHCTRL_1 */ + volatile uint32_t CHCFG_1; /* CHCFG_1 */ + volatile uint32_t CHITVL_1; /* CHITVL_1 */ + volatile uint32_t CHEXT_1; /* CHEXT_1 */ + volatile uint32_t NXLA_1; /* NXLA_1 */ + volatile uint32_t CRLA_1; /* CRLA_1 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_2; /* N0SA_2 */ + volatile uint32_t N0DA_2; /* N0DA_2 */ + volatile uint32_t N0TB_2; /* N0TB_2 */ + volatile uint32_t N1SA_2; /* N1SA_2 */ + volatile uint32_t N1DA_2; /* N1DA_2 */ + volatile uint32_t N1TB_2; /* N1TB_2 */ + volatile uint32_t CRSA_2; /* CRSA_2 */ + volatile uint32_t CRDA_2; /* CRDA_2 */ + volatile uint32_t CRTB_2; /* CRTB_2 */ + volatile uint32_t CHSTAT_2; /* CHSTAT_2 */ + volatile uint32_t CHCTRL_2; /* CHCTRL_2 */ + volatile uint32_t CHCFG_2; /* CHCFG_2 */ + volatile uint32_t CHITVL_2; /* CHITVL_2 */ + volatile uint32_t CHEXT_2; /* CHEXT_2 */ + volatile uint32_t NXLA_2; /* NXLA_2 */ + volatile uint32_t CRLA_2; /* CRLA_2 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_3; /* N0SA_3 */ + volatile uint32_t N0DA_3; /* N0DA_3 */ + volatile uint32_t N0TB_3; /* N0TB_3 */ + volatile uint32_t N1SA_3; /* N1SA_3 */ + volatile uint32_t N1DA_3; /* N1DA_3 */ + volatile uint32_t N1TB_3; /* N1TB_3 */ + volatile uint32_t CRSA_3; /* CRSA_3 */ + volatile uint32_t CRDA_3; /* CRDA_3 */ + volatile uint32_t CRTB_3; /* CRTB_3 */ + volatile uint32_t CHSTAT_3; /* CHSTAT_3 */ + volatile uint32_t CHCTRL_3; /* CHCTRL_3 */ + volatile uint32_t CHCFG_3; /* CHCFG_3 */ + volatile uint32_t CHITVL_3; /* CHITVL_3 */ + volatile uint32_t CHEXT_3; /* CHEXT_3 */ + volatile uint32_t NXLA_3; /* NXLA_3 */ + volatile uint32_t CRLA_3; /* CRLA_3 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_4; /* N0SA_4 */ + volatile uint32_t N0DA_4; /* N0DA_4 */ + volatile uint32_t N0TB_4; /* N0TB_4 */ + volatile uint32_t N1SA_4; /* N1SA_4 */ + volatile uint32_t N1DA_4; /* N1DA_4 */ + volatile uint32_t N1TB_4; /* N1TB_4 */ + volatile uint32_t CRSA_4; /* CRSA_4 */ + volatile uint32_t CRDA_4; /* CRDA_4 */ + volatile uint32_t CRTB_4; /* CRTB_4 */ + volatile uint32_t CHSTAT_4; /* CHSTAT_4 */ + volatile uint32_t CHCTRL_4; /* CHCTRL_4 */ + volatile uint32_t CHCFG_4; /* CHCFG_4 */ + volatile uint32_t CHITVL_4; /* CHITVL_4 */ + volatile uint32_t CHEXT_4; /* CHEXT_4 */ + volatile uint32_t NXLA_4; /* NXLA_4 */ + volatile uint32_t CRLA_4; /* CRLA_4 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_5; /* N0SA_5 */ + volatile uint32_t N0DA_5; /* N0DA_5 */ + volatile uint32_t N0TB_5; /* N0TB_5 */ + volatile uint32_t N1SA_5; /* N1SA_5 */ + volatile uint32_t N1DA_5; /* N1DA_5 */ + volatile uint32_t N1TB_5; /* N1TB_5 */ + volatile uint32_t CRSA_5; /* CRSA_5 */ + volatile uint32_t CRDA_5; /* CRDA_5 */ + volatile uint32_t CRTB_5; /* CRTB_5 */ + volatile uint32_t CHSTAT_5; /* CHSTAT_5 */ + volatile uint32_t CHCTRL_5; /* CHCTRL_5 */ + volatile uint32_t CHCFG_5; /* CHCFG_5 */ + volatile uint32_t CHITVL_5; /* CHITVL_5 */ + volatile uint32_t CHEXT_5; /* CHEXT_5 */ + volatile uint32_t NXLA_5; /* NXLA_5 */ + volatile uint32_t CRLA_5; /* CRLA_5 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_6; /* N0SA_6 */ + volatile uint32_t N0DA_6; /* N0DA_6 */ + volatile uint32_t N0TB_6; /* N0TB_6 */ + volatile uint32_t N1SA_6; /* N1SA_6 */ + volatile uint32_t N1DA_6; /* N1DA_6 */ + volatile uint32_t N1TB_6; /* N1TB_6 */ + volatile uint32_t CRSA_6; /* CRSA_6 */ + volatile uint32_t CRDA_6; /* CRDA_6 */ + volatile uint32_t CRTB_6; /* CRTB_6 */ + volatile uint32_t CHSTAT_6; /* CHSTAT_6 */ + volatile uint32_t CHCTRL_6; /* CHCTRL_6 */ + volatile uint32_t CHCFG_6; /* CHCFG_6 */ + volatile uint32_t CHITVL_6; /* CHITVL_6 */ + volatile uint32_t CHEXT_6; /* CHEXT_6 */ + volatile uint32_t NXLA_6; /* NXLA_6 */ + volatile uint32_t CRLA_6; /* CRLA_6 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_7; /* N0SA_7 */ + volatile uint32_t N0DA_7; /* N0DA_7 */ + volatile uint32_t N0TB_7; /* N0TB_7 */ + volatile uint32_t N1SA_7; /* N1SA_7 */ + volatile uint32_t N1DA_7; /* N1DA_7 */ + volatile uint32_t N1TB_7; /* N1TB_7 */ + volatile uint32_t CRSA_7; /* CRSA_7 */ + volatile uint32_t CRDA_7; /* CRDA_7 */ + volatile uint32_t CRTB_7; /* CRTB_7 */ + volatile uint32_t CHSTAT_7; /* CHSTAT_7 */ + volatile uint32_t CHCTRL_7; /* CHCTRL_7 */ + volatile uint32_t CHCFG_7; /* CHCFG_7 */ + volatile uint32_t CHITVL_7; /* CHITVL_7 */ + volatile uint32_t CHEXT_7; /* CHEXT_7 */ + volatile uint32_t NXLA_7; /* NXLA_7 */ + volatile uint32_t CRLA_7; /* CRLA_7 */ +/* end of struct st_dmac_n */ + volatile uint8_t dummy187[256]; /* */ +/* start of struct st_dmaccommon_n */ + volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */ + volatile uint8_t dummy188[12]; /* */ + volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */ + volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */ + volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */ + volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */ + volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */ +/* end of struct st_dmaccommon_n */ + volatile uint8_t dummy189[220]; /* */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_8; /* N0SA_8 */ + volatile uint32_t N0DA_8; /* N0DA_8 */ + volatile uint32_t N0TB_8; /* N0TB_8 */ + volatile uint32_t N1SA_8; /* N1SA_8 */ + volatile uint32_t N1DA_8; /* N1DA_8 */ + volatile uint32_t N1TB_8; /* N1TB_8 */ + volatile uint32_t CRSA_8; /* CRSA_8 */ + volatile uint32_t CRDA_8; /* CRDA_8 */ + volatile uint32_t CRTB_8; /* CRTB_8 */ + volatile uint32_t CHSTAT_8; /* CHSTAT_8 */ + volatile uint32_t CHCTRL_8; /* CHCTRL_8 */ + volatile uint32_t CHCFG_8; /* CHCFG_8 */ + volatile uint32_t CHITVL_8; /* CHITVL_8 */ + volatile uint32_t CHEXT_8; /* CHEXT_8 */ + volatile uint32_t NXLA_8; /* NXLA_8 */ + volatile uint32_t CRLA_8; /* CRLA_8 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_9; /* N0SA_9 */ + volatile uint32_t N0DA_9; /* N0DA_9 */ + volatile uint32_t N0TB_9; /* N0TB_9 */ + volatile uint32_t N1SA_9; /* N1SA_9 */ + volatile uint32_t N1DA_9; /* N1DA_9 */ + volatile uint32_t N1TB_9; /* N1TB_9 */ + volatile uint32_t CRSA_9; /* CRSA_9 */ + volatile uint32_t CRDA_9; /* CRDA_9 */ + volatile uint32_t CRTB_9; /* CRTB_9 */ + volatile uint32_t CHSTAT_9; /* CHSTAT_9 */ + volatile uint32_t CHCTRL_9; /* CHCTRL_9 */ + volatile uint32_t CHCFG_9; /* CHCFG_9 */ + volatile uint32_t CHITVL_9; /* CHITVL_9 */ + volatile uint32_t CHEXT_9; /* CHEXT_9 */ + volatile uint32_t NXLA_9; /* NXLA_9 */ + volatile uint32_t CRLA_9; /* CRLA_9 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_10; /* N0SA_10 */ + volatile uint32_t N0DA_10; /* N0DA_10 */ + volatile uint32_t N0TB_10; /* N0TB_10 */ + volatile uint32_t N1SA_10; /* N1SA_10 */ + volatile uint32_t N1DA_10; /* N1DA_10 */ + volatile uint32_t N1TB_10; /* N1TB_10 */ + volatile uint32_t CRSA_10; /* CRSA_10 */ + volatile uint32_t CRDA_10; /* CRDA_10 */ + volatile uint32_t CRTB_10; /* CRTB_10 */ + volatile uint32_t CHSTAT_10; /* CHSTAT_10 */ + volatile uint32_t CHCTRL_10; /* CHCTRL_10 */ + volatile uint32_t CHCFG_10; /* CHCFG_10 */ + volatile uint32_t CHITVL_10; /* CHITVL_10 */ + volatile uint32_t CHEXT_10; /* CHEXT_10 */ + volatile uint32_t NXLA_10; /* NXLA_10 */ + volatile uint32_t CRLA_10; /* CRLA_10 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_11; /* N0SA_11 */ + volatile uint32_t N0DA_11; /* N0DA_11 */ + volatile uint32_t N0TB_11; /* N0TB_11 */ + volatile uint32_t N1SA_11; /* N1SA_11 */ + volatile uint32_t N1DA_11; /* N1DA_11 */ + volatile uint32_t N1TB_11; /* N1TB_11 */ + volatile uint32_t CRSA_11; /* CRSA_11 */ + volatile uint32_t CRDA_11; /* CRDA_11 */ + volatile uint32_t CRTB_11; /* CRTB_11 */ + volatile uint32_t CHSTAT_11; /* CHSTAT_11 */ + volatile uint32_t CHCTRL_11; /* CHCTRL_11 */ + volatile uint32_t CHCFG_11; /* CHCFG_11 */ + volatile uint32_t CHITVL_11; /* CHITVL_11 */ + volatile uint32_t CHEXT_11; /* CHEXT_11 */ + volatile uint32_t NXLA_11; /* NXLA_11 */ + volatile uint32_t CRLA_11; /* CRLA_11 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_12; /* N0SA_12 */ + volatile uint32_t N0DA_12; /* N0DA_12 */ + volatile uint32_t N0TB_12; /* N0TB_12 */ + volatile uint32_t N1SA_12; /* N1SA_12 */ + volatile uint32_t N1DA_12; /* N1DA_12 */ + volatile uint32_t N1TB_12; /* N1TB_12 */ + volatile uint32_t CRSA_12; /* CRSA_12 */ + volatile uint32_t CRDA_12; /* CRDA_12 */ + volatile uint32_t CRTB_12; /* CRTB_12 */ + volatile uint32_t CHSTAT_12; /* CHSTAT_12 */ + volatile uint32_t CHCTRL_12; /* CHCTRL_12 */ + volatile uint32_t CHCFG_12; /* CHCFG_12 */ + volatile uint32_t CHITVL_12; /* CHITVL_12 */ + volatile uint32_t CHEXT_12; /* CHEXT_12 */ + volatile uint32_t NXLA_12; /* NXLA_12 */ + volatile uint32_t CRLA_12; /* CRLA_12 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_13; /* N0SA_13 */ + volatile uint32_t N0DA_13; /* N0DA_13 */ + volatile uint32_t N0TB_13; /* N0TB_13 */ + volatile uint32_t N1SA_13; /* N1SA_13 */ + volatile uint32_t N1DA_13; /* N1DA_13 */ + volatile uint32_t N1TB_13; /* N1TB_13 */ + volatile uint32_t CRSA_13; /* CRSA_13 */ + volatile uint32_t CRDA_13; /* CRDA_13 */ + volatile uint32_t CRTB_13; /* CRTB_13 */ + volatile uint32_t CHSTAT_13; /* CHSTAT_13 */ + volatile uint32_t CHCTRL_13; /* CHCTRL_13 */ + volatile uint32_t CHCFG_13; /* CHCFG_13 */ + volatile uint32_t CHITVL_13; /* CHITVL_13 */ + volatile uint32_t CHEXT_13; /* CHEXT_13 */ + volatile uint32_t NXLA_13; /* NXLA_13 */ + volatile uint32_t CRLA_13; /* CRLA_13 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_14; /* N0SA_14 */ + volatile uint32_t N0DA_14; /* N0DA_14 */ + volatile uint32_t N0TB_14; /* N0TB_14 */ + volatile uint32_t N1SA_14; /* N1SA_14 */ + volatile uint32_t N1DA_14; /* N1DA_14 */ + volatile uint32_t N1TB_14; /* N1TB_14 */ + volatile uint32_t CRSA_14; /* CRSA_14 */ + volatile uint32_t CRDA_14; /* CRDA_14 */ + volatile uint32_t CRTB_14; /* CRTB_14 */ + volatile uint32_t CHSTAT_14; /* CHSTAT_14 */ + volatile uint32_t CHCTRL_14; /* CHCTRL_14 */ + volatile uint32_t CHCFG_14; /* CHCFG_14 */ + volatile uint32_t CHITVL_14; /* CHITVL_14 */ + volatile uint32_t CHEXT_14; /* CHEXT_14 */ + volatile uint32_t NXLA_14; /* NXLA_14 */ + volatile uint32_t CRLA_14; /* CRLA_14 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_15; /* N0SA_15 */ + volatile uint32_t N0DA_15; /* N0DA_15 */ + volatile uint32_t N0TB_15; /* N0TB_15 */ + volatile uint32_t N1SA_15; /* N1SA_15 */ + volatile uint32_t N1DA_15; /* N1DA_15 */ + volatile uint32_t N1TB_15; /* N1TB_15 */ + volatile uint32_t CRSA_15; /* CRSA_15 */ + volatile uint32_t CRDA_15; /* CRDA_15 */ + volatile uint32_t CRTB_15; /* CRTB_15 */ + volatile uint32_t CHSTAT_15; /* CHSTAT_15 */ + volatile uint32_t CHCTRL_15; /* CHCTRL_15 */ + volatile uint32_t CHCFG_15; /* CHCFG_15 */ + volatile uint32_t CHITVL_15; /* CHITVL_15 */ + volatile uint32_t CHEXT_15; /* CHEXT_15 */ + volatile uint32_t NXLA_15; /* NXLA_15 */ + volatile uint32_t CRLA_15; /* CRLA_15 */ +/* end of struct st_dmac_n */ + volatile uint8_t dummy190[256]; /* */ +/* start of struct st_dmaccommon_n */ + volatile uint32_t DCTRL_8_15; /* DCTRL_8_15 */ + volatile uint8_t dummy191[12]; /* */ + volatile uint32_t DSTAT_EN_8_15; /* DSTAT_EN_8_15 */ + volatile uint32_t DSTAT_ER_8_15; /* DSTAT_ER_8_15 */ + volatile uint32_t DSTAT_END_8_15; /* DSTAT_END_8_15 */ + volatile uint32_t DSTAT_TC_8_15; /* DSTAT_TC_8_15 */ + volatile uint32_t DSTAT_SUS_8_15; /* DSTAT_SUS_8_15 */ +/* end of struct st_dmaccommon_n */ + volatile uint8_t dummy192[350095580]; /* */ + volatile uint32_t DMARS0; /* DMARS0 */ + volatile uint32_t DMARS1; /* DMARS1 */ + volatile uint32_t DMARS2; /* DMARS2 */ + volatile uint32_t DMARS3; /* DMARS3 */ + volatile uint32_t DMARS4; /* DMARS4 */ + volatile uint32_t DMARS5; /* DMARS5 */ + volatile uint32_t DMARS6; /* DMARS6 */ + volatile uint32_t DMARS7; /* DMARS7 */ +}; + + +struct st_dmaccommon_n +{ + volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */ + volatile uint8_t dummy1[12]; /* */ + volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */ + volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */ + volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */ + volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */ + volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */ +}; + + +struct st_dmac_n +{ + volatile uint32_t N0SA_n; /* N0SA_n */ + volatile uint32_t N0DA_n; /* N0DA_n */ + volatile uint32_t N0TB_n; /* N0TB_n */ + volatile uint32_t N1SA_n; /* N1SA_n */ + volatile uint32_t N1DA_n; /* N1DA_n */ + volatile uint32_t N1TB_n; /* N1TB_n */ + volatile uint32_t CRSA_n; /* CRSA_n */ + volatile uint32_t CRDA_n; /* CRDA_n */ + volatile uint32_t CRTB_n; /* CRTB_n */ + volatile uint32_t CHSTAT_n; /* CHSTAT_n */ + volatile uint32_t CHCTRL_n; /* CHCTRL_n */ + volatile uint32_t CHCFG_n; /* CHCFG_n */ + volatile uint32_t CHITVL_n; /* CHITVL_n */ + volatile uint32_t CHEXT_n; /* CHEXT_n */ + volatile uint32_t NXLA_n; /* NXLA_n */ + volatile uint32_t CRLA_n; /* CRLA_n */ +}; + + +#define DMAC (*(struct st_dmac *)0xE8200000uL) /* DMAC */ + + +/* Start of channnel array defines of DMAC */ + +/* Channnel array defines of DMACn */ +/*(Sample) value = DMACn[ channel ]->N0SA_n; */ +#define DMACn_COUNT 16 +#define DMACn_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &DMAC0, &DMAC1, &DMAC2, &DMAC3, &DMAC4, &DMAC5, &DMAC6, &DMAC7, \ + &DMAC8, &DMAC9, &DMAC10, &DMAC11, &DMAC12, &DMAC13, &DMAC14, &DMAC15 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define DMAC0 (*(struct st_dmac_n *)&DMAC.N0SA_0) /* DMAC0 */ +#define DMAC1 (*(struct st_dmac_n *)&DMAC.N0SA_1) /* DMAC1 */ +#define DMAC2 (*(struct st_dmac_n *)&DMAC.N0SA_2) /* DMAC2 */ +#define DMAC3 (*(struct st_dmac_n *)&DMAC.N0SA_3) /* DMAC3 */ +#define DMAC4 (*(struct st_dmac_n *)&DMAC.N0SA_4) /* DMAC4 */ +#define DMAC5 (*(struct st_dmac_n *)&DMAC.N0SA_5) /* DMAC5 */ +#define DMAC6 (*(struct st_dmac_n *)&DMAC.N0SA_6) /* DMAC6 */ +#define DMAC7 (*(struct st_dmac_n *)&DMAC.N0SA_7) /* DMAC7 */ +#define DMAC8 (*(struct st_dmac_n *)&DMAC.N0SA_8) /* DMAC8 */ +#define DMAC9 (*(struct st_dmac_n *)&DMAC.N0SA_9) /* DMAC9 */ +#define DMAC10 (*(struct st_dmac_n *)&DMAC.N0SA_10) /* DMAC10 */ +#define DMAC11 (*(struct st_dmac_n *)&DMAC.N0SA_11) /* DMAC11 */ +#define DMAC12 (*(struct st_dmac_n *)&DMAC.N0SA_12) /* DMAC12 */ +#define DMAC13 (*(struct st_dmac_n *)&DMAC.N0SA_13) /* DMAC13 */ +#define DMAC14 (*(struct st_dmac_n *)&DMAC.N0SA_14) /* DMAC14 */ +#define DMAC15 (*(struct st_dmac_n *)&DMAC.N0SA_15) /* DMAC15 */ + + +/* Channnel array defines of DMACnn */ +/*(Sample) value = DMACnn[ channel / 8 ]->DCTRL_0_7; */ +#define DMACnn_COUNT 2 +#define DMACnn_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &DMAC07, &DMAC815 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define DMAC07 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_0_7) /* DMAC07 */ +#define DMAC815 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_8_15) /* DMAC815 */ + + +/* Channnel array defines of DMACmm */ +/*(Sample) value = DMACmm[ channel / 2 ]->DMARS; */ +struct st_dmars_mm +{ + uint32_t DMARS; /* DMARS */ +}; +#define DMACmm_COUNT 8 +#define DMACmm_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &DMAC01, &DMAC23, &DMAC45, &DMAC67, &DMAC89, &DMAC1011, &DMAC1213, &DMAC1415 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define DMAC01 (*(struct st_dmars_mm *)&DMAC.DMARS0) /* DMAC0-1 */ +#define DMAC23 (*(struct st_dmars_mm *)&DMAC.DMARS1) /* DMAC2-3 */ +#define DMAC45 (*(struct st_dmars_mm *)&DMAC.DMARS2) /* DMAC4-5 */ +#define DMAC67 (*(struct st_dmars_mm *)&DMAC.DMARS3) /* DMAC6-7 */ +#define DMAC89 (*(struct st_dmars_mm *)&DMAC.DMARS4) /* DMAC8-9 */ +#define DMAC1011 (*(struct st_dmars_mm *)&DMAC.DMARS5) /* DMAC10-11 */ +#define DMAC1213 (*(struct st_dmars_mm *)&DMAC.DMARS6) /* DMAC12-13 */ +#define DMAC1415 (*(struct st_dmars_mm *)&DMAC.DMARS7) /* DMAC14-15 */ + +/* End of channnel array defines of DMAC */ + + +#define DMACN0SA_0 DMAC.N0SA_0 +#define DMACN0DA_0 DMAC.N0DA_0 +#define DMACN0TB_0 DMAC.N0TB_0 +#define DMACN1SA_0 DMAC.N1SA_0 +#define DMACN1DA_0 DMAC.N1DA_0 +#define DMACN1TB_0 DMAC.N1TB_0 +#define DMACCRSA_0 DMAC.CRSA_0 +#define DMACCRDA_0 DMAC.CRDA_0 +#define DMACCRTB_0 DMAC.CRTB_0 +#define DMACCHSTAT_0 DMAC.CHSTAT_0 +#define DMACCHCTRL_0 DMAC.CHCTRL_0 +#define DMACCHCFG_0 DMAC.CHCFG_0 +#define DMACCHITVL_0 DMAC.CHITVL_0 +#define DMACCHEXT_0 DMAC.CHEXT_0 +#define DMACNXLA_0 DMAC.NXLA_0 +#define DMACCRLA_0 DMAC.CRLA_0 +#define DMACN0SA_1 DMAC.N0SA_1 +#define DMACN0DA_1 DMAC.N0DA_1 +#define DMACN0TB_1 DMAC.N0TB_1 +#define DMACN1SA_1 DMAC.N1SA_1 +#define DMACN1DA_1 DMAC.N1DA_1 +#define DMACN1TB_1 DMAC.N1TB_1 +#define DMACCRSA_1 DMAC.CRSA_1 +#define DMACCRDA_1 DMAC.CRDA_1 +#define DMACCRTB_1 DMAC.CRTB_1 +#define DMACCHSTAT_1 DMAC.CHSTAT_1 +#define DMACCHCTRL_1 DMAC.CHCTRL_1 +#define DMACCHCFG_1 DMAC.CHCFG_1 +#define DMACCHITVL_1 DMAC.CHITVL_1 +#define DMACCHEXT_1 DMAC.CHEXT_1 +#define DMACNXLA_1 DMAC.NXLA_1 +#define DMACCRLA_1 DMAC.CRLA_1 +#define DMACN0SA_2 DMAC.N0SA_2 +#define DMACN0DA_2 DMAC.N0DA_2 +#define DMACN0TB_2 DMAC.N0TB_2 +#define DMACN1SA_2 DMAC.N1SA_2 +#define DMACN1DA_2 DMAC.N1DA_2 +#define DMACN1TB_2 DMAC.N1TB_2 +#define DMACCRSA_2 DMAC.CRSA_2 +#define DMACCRDA_2 DMAC.CRDA_2 +#define DMACCRTB_2 DMAC.CRTB_2 +#define DMACCHSTAT_2 DMAC.CHSTAT_2 +#define DMACCHCTRL_2 DMAC.CHCTRL_2 +#define DMACCHCFG_2 DMAC.CHCFG_2 +#define DMACCHITVL_2 DMAC.CHITVL_2 +#define DMACCHEXT_2 DMAC.CHEXT_2 +#define DMACNXLA_2 DMAC.NXLA_2 +#define DMACCRLA_2 DMAC.CRLA_2 +#define DMACN0SA_3 DMAC.N0SA_3 +#define DMACN0DA_3 DMAC.N0DA_3 +#define DMACN0TB_3 DMAC.N0TB_3 +#define DMACN1SA_3 DMAC.N1SA_3 +#define DMACN1DA_3 DMAC.N1DA_3 +#define DMACN1TB_3 DMAC.N1TB_3 +#define DMACCRSA_3 DMAC.CRSA_3 +#define DMACCRDA_3 DMAC.CRDA_3 +#define DMACCRTB_3 DMAC.CRTB_3 +#define DMACCHSTAT_3 DMAC.CHSTAT_3 +#define DMACCHCTRL_3 DMAC.CHCTRL_3 +#define DMACCHCFG_3 DMAC.CHCFG_3 +#define DMACCHITVL_3 DMAC.CHITVL_3 +#define DMACCHEXT_3 DMAC.CHEXT_3 +#define DMACNXLA_3 DMAC.NXLA_3 +#define DMACCRLA_3 DMAC.CRLA_3 +#define DMACN0SA_4 DMAC.N0SA_4 +#define DMACN0DA_4 DMAC.N0DA_4 +#define DMACN0TB_4 DMAC.N0TB_4 +#define DMACN1SA_4 DMAC.N1SA_4 +#define DMACN1DA_4 DMAC.N1DA_4 +#define DMACN1TB_4 DMAC.N1TB_4 +#define DMACCRSA_4 DMAC.CRSA_4 +#define DMACCRDA_4 DMAC.CRDA_4 +#define DMACCRTB_4 DMAC.CRTB_4 +#define DMACCHSTAT_4 DMAC.CHSTAT_4 +#define DMACCHCTRL_4 DMAC.CHCTRL_4 +#define DMACCHCFG_4 DMAC.CHCFG_4 +#define DMACCHITVL_4 DMAC.CHITVL_4 +#define DMACCHEXT_4 DMAC.CHEXT_4 +#define DMACNXLA_4 DMAC.NXLA_4 +#define DMACCRLA_4 DMAC.CRLA_4 +#define DMACN0SA_5 DMAC.N0SA_5 +#define DMACN0DA_5 DMAC.N0DA_5 +#define DMACN0TB_5 DMAC.N0TB_5 +#define DMACN1SA_5 DMAC.N1SA_5 +#define DMACN1DA_5 DMAC.N1DA_5 +#define DMACN1TB_5 DMAC.N1TB_5 +#define DMACCRSA_5 DMAC.CRSA_5 +#define DMACCRDA_5 DMAC.CRDA_5 +#define DMACCRTB_5 DMAC.CRTB_5 +#define DMACCHSTAT_5 DMAC.CHSTAT_5 +#define DMACCHCTRL_5 DMAC.CHCTRL_5 +#define DMACCHCFG_5 DMAC.CHCFG_5 +#define DMACCHITVL_5 DMAC.CHITVL_5 +#define DMACCHEXT_5 DMAC.CHEXT_5 +#define DMACNXLA_5 DMAC.NXLA_5 +#define DMACCRLA_5 DMAC.CRLA_5 +#define DMACN0SA_6 DMAC.N0SA_6 +#define DMACN0DA_6 DMAC.N0DA_6 +#define DMACN0TB_6 DMAC.N0TB_6 +#define DMACN1SA_6 DMAC.N1SA_6 +#define DMACN1DA_6 DMAC.N1DA_6 +#define DMACN1TB_6 DMAC.N1TB_6 +#define DMACCRSA_6 DMAC.CRSA_6 +#define DMACCRDA_6 DMAC.CRDA_6 +#define DMACCRTB_6 DMAC.CRTB_6 +#define DMACCHSTAT_6 DMAC.CHSTAT_6 +#define DMACCHCTRL_6 DMAC.CHCTRL_6 +#define DMACCHCFG_6 DMAC.CHCFG_6 +#define DMACCHITVL_6 DMAC.CHITVL_6 +#define DMACCHEXT_6 DMAC.CHEXT_6 +#define DMACNXLA_6 DMAC.NXLA_6 +#define DMACCRLA_6 DMAC.CRLA_6 +#define DMACN0SA_7 DMAC.N0SA_7 +#define DMACN0DA_7 DMAC.N0DA_7 +#define DMACN0TB_7 DMAC.N0TB_7 +#define DMACN1SA_7 DMAC.N1SA_7 +#define DMACN1DA_7 DMAC.N1DA_7 +#define DMACN1TB_7 DMAC.N1TB_7 +#define DMACCRSA_7 DMAC.CRSA_7 +#define DMACCRDA_7 DMAC.CRDA_7 +#define DMACCRTB_7 DMAC.CRTB_7 +#define DMACCHSTAT_7 DMAC.CHSTAT_7 +#define DMACCHCTRL_7 DMAC.CHCTRL_7 +#define DMACCHCFG_7 DMAC.CHCFG_7 +#define DMACCHITVL_7 DMAC.CHITVL_7 +#define DMACCHEXT_7 DMAC.CHEXT_7 +#define DMACNXLA_7 DMAC.NXLA_7 +#define DMACCRLA_7 DMAC.CRLA_7 +#define DMACDCTRL_0_7 DMAC.DCTRL_0_7 +#define DMACDSTAT_EN_0_7 DMAC.DSTAT_EN_0_7 +#define DMACDSTAT_ER_0_7 DMAC.DSTAT_ER_0_7 +#define DMACDSTAT_END_0_7 DMAC.DSTAT_END_0_7 +#define DMACDSTAT_TC_0_7 DMAC.DSTAT_TC_0_7 +#define DMACDSTAT_SUS_0_7 DMAC.DSTAT_SUS_0_7 +#define DMACN0SA_8 DMAC.N0SA_8 +#define DMACN0DA_8 DMAC.N0DA_8 +#define DMACN0TB_8 DMAC.N0TB_8 +#define DMACN1SA_8 DMAC.N1SA_8 +#define DMACN1DA_8 DMAC.N1DA_8 +#define DMACN1TB_8 DMAC.N1TB_8 +#define DMACCRSA_8 DMAC.CRSA_8 +#define DMACCRDA_8 DMAC.CRDA_8 +#define DMACCRTB_8 DMAC.CRTB_8 +#define DMACCHSTAT_8 DMAC.CHSTAT_8 +#define DMACCHCTRL_8 DMAC.CHCTRL_8 +#define DMACCHCFG_8 DMAC.CHCFG_8 +#define DMACCHITVL_8 DMAC.CHITVL_8 +#define DMACCHEXT_8 DMAC.CHEXT_8 +#define DMACNXLA_8 DMAC.NXLA_8 +#define DMACCRLA_8 DMAC.CRLA_8 +#define DMACN0SA_9 DMAC.N0SA_9 +#define DMACN0DA_9 DMAC.N0DA_9 +#define DMACN0TB_9 DMAC.N0TB_9 +#define DMACN1SA_9 DMAC.N1SA_9 +#define DMACN1DA_9 DMAC.N1DA_9 +#define DMACN1TB_9 DMAC.N1TB_9 +#define DMACCRSA_9 DMAC.CRSA_9 +#define DMACCRDA_9 DMAC.CRDA_9 +#define DMACCRTB_9 DMAC.CRTB_9 +#define DMACCHSTAT_9 DMAC.CHSTAT_9 +#define DMACCHCTRL_9 DMAC.CHCTRL_9 +#define DMACCHCFG_9 DMAC.CHCFG_9 +#define DMACCHITVL_9 DMAC.CHITVL_9 +#define DMACCHEXT_9 DMAC.CHEXT_9 +#define DMACNXLA_9 DMAC.NXLA_9 +#define DMACCRLA_9 DMAC.CRLA_9 +#define DMACN0SA_10 DMAC.N0SA_10 +#define DMACN0DA_10 DMAC.N0DA_10 +#define DMACN0TB_10 DMAC.N0TB_10 +#define DMACN1SA_10 DMAC.N1SA_10 +#define DMACN1DA_10 DMAC.N1DA_10 +#define DMACN1TB_10 DMAC.N1TB_10 +#define DMACCRSA_10 DMAC.CRSA_10 +#define DMACCRDA_10 DMAC.CRDA_10 +#define DMACCRTB_10 DMAC.CRTB_10 +#define DMACCHSTAT_10 DMAC.CHSTAT_10 +#define DMACCHCTRL_10 DMAC.CHCTRL_10 +#define DMACCHCFG_10 DMAC.CHCFG_10 +#define DMACCHITVL_10 DMAC.CHITVL_10 +#define DMACCHEXT_10 DMAC.CHEXT_10 +#define DMACNXLA_10 DMAC.NXLA_10 +#define DMACCRLA_10 DMAC.CRLA_10 +#define DMACN0SA_11 DMAC.N0SA_11 +#define DMACN0DA_11 DMAC.N0DA_11 +#define DMACN0TB_11 DMAC.N0TB_11 +#define DMACN1SA_11 DMAC.N1SA_11 +#define DMACN1DA_11 DMAC.N1DA_11 +#define DMACN1TB_11 DMAC.N1TB_11 +#define DMACCRSA_11 DMAC.CRSA_11 +#define DMACCRDA_11 DMAC.CRDA_11 +#define DMACCRTB_11 DMAC.CRTB_11 +#define DMACCHSTAT_11 DMAC.CHSTAT_11 +#define DMACCHCTRL_11 DMAC.CHCTRL_11 +#define DMACCHCFG_11 DMAC.CHCFG_11 +#define DMACCHITVL_11 DMAC.CHITVL_11 +#define DMACCHEXT_11 DMAC.CHEXT_11 +#define DMACNXLA_11 DMAC.NXLA_11 +#define DMACCRLA_11 DMAC.CRLA_11 +#define DMACN0SA_12 DMAC.N0SA_12 +#define DMACN0DA_12 DMAC.N0DA_12 +#define DMACN0TB_12 DMAC.N0TB_12 +#define DMACN1SA_12 DMAC.N1SA_12 +#define DMACN1DA_12 DMAC.N1DA_12 +#define DMACN1TB_12 DMAC.N1TB_12 +#define DMACCRSA_12 DMAC.CRSA_12 +#define DMACCRDA_12 DMAC.CRDA_12 +#define DMACCRTB_12 DMAC.CRTB_12 +#define DMACCHSTAT_12 DMAC.CHSTAT_12 +#define DMACCHCTRL_12 DMAC.CHCTRL_12 +#define DMACCHCFG_12 DMAC.CHCFG_12 +#define DMACCHITVL_12 DMAC.CHITVL_12 +#define DMACCHEXT_12 DMAC.CHEXT_12 +#define DMACNXLA_12 DMAC.NXLA_12 +#define DMACCRLA_12 DMAC.CRLA_12 +#define DMACN0SA_13 DMAC.N0SA_13 +#define DMACN0DA_13 DMAC.N0DA_13 +#define DMACN0TB_13 DMAC.N0TB_13 +#define DMACN1SA_13 DMAC.N1SA_13 +#define DMACN1DA_13 DMAC.N1DA_13 +#define DMACN1TB_13 DMAC.N1TB_13 +#define DMACCRSA_13 DMAC.CRSA_13 +#define DMACCRDA_13 DMAC.CRDA_13 +#define DMACCRTB_13 DMAC.CRTB_13 +#define DMACCHSTAT_13 DMAC.CHSTAT_13 +#define DMACCHCTRL_13 DMAC.CHCTRL_13 +#define DMACCHCFG_13 DMAC.CHCFG_13 +#define DMACCHITVL_13 DMAC.CHITVL_13 +#define DMACCHEXT_13 DMAC.CHEXT_13 +#define DMACNXLA_13 DMAC.NXLA_13 +#define DMACCRLA_13 DMAC.CRLA_13 +#define DMACN0SA_14 DMAC.N0SA_14 +#define DMACN0DA_14 DMAC.N0DA_14 +#define DMACN0TB_14 DMAC.N0TB_14 +#define DMACN1SA_14 DMAC.N1SA_14 +#define DMACN1DA_14 DMAC.N1DA_14 +#define DMACN1TB_14 DMAC.N1TB_14 +#define DMACCRSA_14 DMAC.CRSA_14 +#define DMACCRDA_14 DMAC.CRDA_14 +#define DMACCRTB_14 DMAC.CRTB_14 +#define DMACCHSTAT_14 DMAC.CHSTAT_14 +#define DMACCHCTRL_14 DMAC.CHCTRL_14 +#define DMACCHCFG_14 DMAC.CHCFG_14 +#define DMACCHITVL_14 DMAC.CHITVL_14 +#define DMACCHEXT_14 DMAC.CHEXT_14 +#define DMACNXLA_14 DMAC.NXLA_14 +#define DMACCRLA_14 DMAC.CRLA_14 +#define DMACN0SA_15 DMAC.N0SA_15 +#define DMACN0DA_15 DMAC.N0DA_15 +#define DMACN0TB_15 DMAC.N0TB_15 +#define DMACN1SA_15 DMAC.N1SA_15 +#define DMACN1DA_15 DMAC.N1DA_15 +#define DMACN1TB_15 DMAC.N1TB_15 +#define DMACCRSA_15 DMAC.CRSA_15 +#define DMACCRDA_15 DMAC.CRDA_15 +#define DMACCRTB_15 DMAC.CRTB_15 +#define DMACCHSTAT_15 DMAC.CHSTAT_15 +#define DMACCHCTRL_15 DMAC.CHCTRL_15 +#define DMACCHCFG_15 DMAC.CHCFG_15 +#define DMACCHITVL_15 DMAC.CHITVL_15 +#define DMACCHEXT_15 DMAC.CHEXT_15 +#define DMACNXLA_15 DMAC.NXLA_15 +#define DMACCRLA_15 DMAC.CRLA_15 +#define DMACDCTRL_8_15 DMAC.DCTRL_8_15 +#define DMACDSTAT_EN_8_15 DMAC.DSTAT_EN_8_15 +#define DMACDSTAT_ER_8_15 DMAC.DSTAT_ER_8_15 +#define DMACDSTAT_END_8_15 DMAC.DSTAT_END_8_15 +#define DMACDSTAT_TC_8_15 DMAC.DSTAT_TC_8_15 +#define DMACDSTAT_SUS_8_15 DMAC.DSTAT_SUS_8_15 +#define DMACDMARS0 DMAC.DMARS0 +#define DMACDMARS1 DMAC.DMARS1 +#define DMACDMARS2 DMAC.DMARS2 +#define DMACDMARS3 DMAC.DMARS3 +#define DMACDMARS4 DMAC.DMARS4 +#define DMACDMARS5 DMAC.DMARS5 +#define DMACDMARS6 DMAC.DMARS6 +#define DMACDMARS7 DMAC.DMARS7 +/* <-SEC M1.10.1 */ +/* <-QAC 0639 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/dvdec_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,391 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : dvdec_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef DVDEC_IODEFINE_H +#define DVDEC_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_dvdec +{ /* DVDEC */ + volatile uint16_t ADCCR1; /* ADCCR1 */ + volatile uint8_t dummy1[4]; /* */ +#define DVDEC_TGCRn_COUNT 3 + volatile uint16_t TGCR1; /* TGCR1 */ + volatile uint16_t TGCR2; /* TGCR2 */ + volatile uint16_t TGCR3; /* TGCR3 */ + volatile uint8_t dummy2[6]; /* */ +#define DVDEC_SYNSCRn_COUNT 5 + volatile uint16_t SYNSCR1; /* SYNSCR1 */ + volatile uint16_t SYNSCR2; /* SYNSCR2 */ + volatile uint16_t SYNSCR3; /* SYNSCR3 */ + volatile uint16_t SYNSCR4; /* SYNSCR4 */ + volatile uint16_t SYNSCR5; /* SYNSCR5 */ +#define DVDEC_HAFCCRn_COUNT 3 + volatile uint16_t HAFCCR1; /* HAFCCR1 */ + volatile uint16_t HAFCCR2; /* HAFCCR2 */ + volatile uint16_t HAFCCR3; /* HAFCCR3 */ + volatile uint16_t VCDWCR1; /* VCDWCR1 */ + volatile uint8_t dummy3[4]; /* */ +#define DVDEC_DCPCRn_COUNT 8 + volatile uint16_t DCPCR1; /* DCPCR1 */ + volatile uint16_t DCPCR2; /* DCPCR2 */ + volatile uint16_t DCPCR3; /* DCPCR3 */ + volatile uint16_t DCPCR4; /* DCPCR4 */ + volatile uint16_t DCPCR5; /* DCPCR5 */ + volatile uint16_t DCPCR6; /* DCPCR6 */ + volatile uint16_t DCPCR7; /* DCPCR7 */ + volatile uint16_t DCPCR8; /* DCPCR8 */ + volatile uint16_t NSDCR; /* NSDCR */ + volatile uint16_t BTLCR; /* BTLCR */ + volatile uint16_t BTGPCR; /* BTGPCR */ +#define DVDEC_ACCCRn_COUNT 3 + volatile uint16_t ACCCR1; /* ACCCR1 */ + volatile uint16_t ACCCR2; /* ACCCR2 */ + volatile uint16_t ACCCR3; /* ACCCR3 */ + volatile uint16_t TINTCR; /* TINTCR */ + volatile uint16_t YCDCR; /* YCDCR */ +#define DVDEC_AGCCRn_COUNT 2 + volatile uint16_t AGCCR1; /* AGCCR1 */ + volatile uint16_t AGCCR2; /* AGCCR2 */ + volatile uint16_t PKLIMITCR; /* PKLIMITCR */ +#define DVDEC_RGORCRn_COUNT 7 + volatile uint16_t RGORCR1; /* RGORCR1 */ + volatile uint16_t RGORCR2; /* RGORCR2 */ + volatile uint16_t RGORCR3; /* RGORCR3 */ + volatile uint16_t RGORCR4; /* RGORCR4 */ + volatile uint16_t RGORCR5; /* RGORCR5 */ + volatile uint16_t RGORCR6; /* RGORCR6 */ + volatile uint16_t RGORCR7; /* RGORCR7 */ + volatile uint8_t dummy4[24]; /* */ + volatile uint16_t AFCPFCR; /* AFCPFCR */ + volatile uint16_t RUPDCR; /* RUPDCR */ + volatile uint16_t VSYNCSR; /* VSYNCSR */ + volatile uint16_t HSYNCSR; /* HSYNCSR */ +#define DVDEC_DCPSRn_COUNT 2 + volatile uint16_t DCPSR1; /* DCPSR1 */ + volatile uint16_t DCPSR2; /* DCPSR2 */ + volatile uint8_t dummy5[4]; /* */ + volatile uint16_t NSDSR; /* NSDSR */ +#define DVDEC_CROMASRn_COUNT 2 + volatile uint16_t CROMASR1; /* CROMASR1 */ + volatile uint16_t CROMASR2; /* CROMASR2 */ + volatile uint16_t SYNCSSR; /* SYNCSSR */ +#define DVDEC_AGCCSRn_COUNT 2 + volatile uint16_t AGCCSR1; /* AGCCSR1 */ + volatile uint16_t AGCCSR2; /* AGCCSR2 */ + volatile uint8_t dummy6[108]; /* */ +#define DVDEC_YCSCRn_COUNT 7 + volatile uint16_t YCSCR3; /* YCSCR3 */ + volatile uint16_t YCSCR4; /* YCSCR4 */ + volatile uint16_t YCSCR5; /* YCSCR5 */ + volatile uint16_t YCSCR6; /* YCSCR6 */ + volatile uint16_t YCSCR7; /* YCSCR7 */ + volatile uint16_t YCSCR8; /* YCSCR8 */ + volatile uint16_t YCSCR9; /* YCSCR9 */ + volatile uint8_t dummy7[2]; /* */ + volatile uint16_t YCSCR11; /* YCSCR11 */ + volatile uint16_t YCSCR12; /* YCSCR12 */ + volatile uint8_t dummy8[104]; /* */ + volatile uint16_t DCPCR9; /* DCPCR9 */ + volatile uint8_t dummy9[16]; /* */ +#define DVDEC_YCTWA_Fn_COUNT 9 + volatile uint16_t YCTWA_F0; /* YCTWA_F0 */ + volatile uint16_t YCTWA_F1; /* YCTWA_F1 */ + volatile uint16_t YCTWA_F2; /* YCTWA_F2 */ + volatile uint16_t YCTWA_F3; /* YCTWA_F3 */ + volatile uint16_t YCTWA_F4; /* YCTWA_F4 */ + volatile uint16_t YCTWA_F5; /* YCTWA_F5 */ + volatile uint16_t YCTWA_F6; /* YCTWA_F6 */ + volatile uint16_t YCTWA_F7; /* YCTWA_F7 */ + volatile uint16_t YCTWA_F8; /* YCTWA_F8 */ +#define DVDEC_YCTWB_Fn_COUNT 9 + volatile uint16_t YCTWB_F0; /* YCTWB_F0 */ + volatile uint16_t YCTWB_F1; /* YCTWB_F1 */ + volatile uint16_t YCTWB_F2; /* YCTWB_F2 */ + volatile uint16_t YCTWB_F3; /* YCTWB_F3 */ + volatile uint16_t YCTWB_F4; /* YCTWB_F4 */ + volatile uint16_t YCTWB_F5; /* YCTWB_F5 */ + volatile uint16_t YCTWB_F6; /* YCTWB_F6 */ + volatile uint16_t YCTWB_F7; /* YCTWB_F7 */ + volatile uint16_t YCTWB_F8; /* YCTWB_F8 */ +#define DVDEC_YCTNA_Fn_COUNT 9 + volatile uint16_t YCTNA_F0; /* YCTNA_F0 */ + volatile uint16_t YCTNA_F1; /* YCTNA_F1 */ + volatile uint16_t YCTNA_F2; /* YCTNA_F2 */ + volatile uint16_t YCTNA_F3; /* YCTNA_F3 */ + volatile uint16_t YCTNA_F4; /* YCTNA_F4 */ + volatile uint16_t YCTNA_F5; /* YCTNA_F5 */ + volatile uint16_t YCTNA_F6; /* YCTNA_F6 */ + volatile uint16_t YCTNA_F7; /* YCTNA_F7 */ + volatile uint16_t YCTNA_F8; /* YCTNA_F8 */ +#define DVDEC_YCTNB_Fn_COUNT 9 + volatile uint16_t YCTNB_F0; /* YCTNB_F0 */ + volatile uint16_t YCTNB_F1; /* YCTNB_F1 */ + volatile uint16_t YCTNB_F2; /* YCTNB_F2 */ + volatile uint16_t YCTNB_F3; /* YCTNB_F3 */ + volatile uint16_t YCTNB_F4; /* YCTNB_F4 */ + volatile uint16_t YCTNB_F5; /* YCTNB_F5 */ + volatile uint16_t YCTNB_F6; /* YCTNB_F6 */ + volatile uint16_t YCTNB_F7; /* YCTNB_F7 */ + volatile uint16_t YCTNB_F8; /* YCTNB_F8 */ + volatile uint8_t dummy10[38]; /* */ + volatile uint16_t YGAINCR; /* YGAINCR */ + volatile uint16_t CBGAINCR; /* CBGAINCR */ + volatile uint16_t CRGAINCR; /* CRGAINCR */ + volatile uint8_t dummy11[122]; /* */ + volatile uint16_t PGA_UPDATE; /* PGA_UPDATE */ + volatile uint16_t PGACR; /* PGACR */ + volatile uint16_t ADCCR2; /* ADCCR2 */ +}; + + +#define DVDEC1 (*(struct st_dvdec *)0xFCFFA008uL) /* DVDEC1 */ +#define DVDEC0 (*(struct st_dvdec *)0xFCFFB808uL) /* DVDEC0 */ + + +/* Start of channnel array defines of DVDEC */ + +/* Channnel array defines of DVDEC */ +/*(Sample) value = DVDEC[ channel ]->ADCCR1; */ +#define DVDEC_COUNT 2 +#define DVDEC_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &DVDEC0, &DVDEC1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channnel array defines of DVDEC */ + + +#define ADCCR1_1 DVDEC1.ADCCR1 +#define TGCR1_1 DVDEC1.TGCR1 +#define TGCR2_1 DVDEC1.TGCR2 +#define TGCR3_1 DVDEC1.TGCR3 +#define SYNSCR1_1 DVDEC1.SYNSCR1 +#define SYNSCR2_1 DVDEC1.SYNSCR2 +#define SYNSCR3_1 DVDEC1.SYNSCR3 +#define SYNSCR4_1 DVDEC1.SYNSCR4 +#define SYNSCR5_1 DVDEC1.SYNSCR5 +#define HAFCCR1_1 DVDEC1.HAFCCR1 +#define HAFCCR2_1 DVDEC1.HAFCCR2 +#define HAFCCR3_1 DVDEC1.HAFCCR3 +#define VCDWCR1_1 DVDEC1.VCDWCR1 +#define DCPCR1_1 DVDEC1.DCPCR1 +#define DCPCR2_1 DVDEC1.DCPCR2 +#define DCPCR3_1 DVDEC1.DCPCR3 +#define DCPCR4_1 DVDEC1.DCPCR4 +#define DCPCR5_1 DVDEC1.DCPCR5 +#define DCPCR6_1 DVDEC1.DCPCR6 +#define DCPCR7_1 DVDEC1.DCPCR7 +#define DCPCR8_1 DVDEC1.DCPCR8 +#define NSDCR_1 DVDEC1.NSDCR +#define BTLCR_1 DVDEC1.BTLCR +#define BTGPCR_1 DVDEC1.BTGPCR +#define ACCCR1_1 DVDEC1.ACCCR1 +#define ACCCR2_1 DVDEC1.ACCCR2 +#define ACCCR3_1 DVDEC1.ACCCR3 +#define TINTCR_1 DVDEC1.TINTCR +#define YCDCR_1 DVDEC1.YCDCR +#define AGCCR1_1 DVDEC1.AGCCR1 +#define AGCCR2_1 DVDEC1.AGCCR2 +#define PKLIMITCR_1 DVDEC1.PKLIMITCR +#define RGORCR1_1 DVDEC1.RGORCR1 +#define RGORCR2_1 DVDEC1.RGORCR2 +#define RGORCR3_1 DVDEC1.RGORCR3 +#define RGORCR4_1 DVDEC1.RGORCR4 +#define RGORCR5_1 DVDEC1.RGORCR5 +#define RGORCR6_1 DVDEC1.RGORCR6 +#define RGORCR7_1 DVDEC1.RGORCR7 +#define AFCPFCR_1 DVDEC1.AFCPFCR +#define RUPDCR_1 DVDEC1.RUPDCR +#define VSYNCSR_1 DVDEC1.VSYNCSR +#define HSYNCSR_1 DVDEC1.HSYNCSR +#define DCPSR1_1 DVDEC1.DCPSR1 +#define DCPSR2_1 DVDEC1.DCPSR2 +#define NSDSR_1 DVDEC1.NSDSR +#define CROMASR1_1 DVDEC1.CROMASR1 +#define CROMASR2_1 DVDEC1.CROMASR2 +#define SYNCSSR_1 DVDEC1.SYNCSSR +#define AGCCSR1_1 DVDEC1.AGCCSR1 +#define AGCCSR2_1 DVDEC1.AGCCSR2 +#define YCSCR3_1 DVDEC1.YCSCR3 +#define YCSCR4_1 DVDEC1.YCSCR4 +#define YCSCR5_1 DVDEC1.YCSCR5 +#define YCSCR6_1 DVDEC1.YCSCR6 +#define YCSCR7_1 DVDEC1.YCSCR7 +#define YCSCR8_1 DVDEC1.YCSCR8 +#define YCSCR9_1 DVDEC1.YCSCR9 +#define YCSCR11_1 DVDEC1.YCSCR11 +#define YCSCR12_1 DVDEC1.YCSCR12 +#define DCPCR9_1 DVDEC1.DCPCR9 +#define YCTWA_F0_1 DVDEC1.YCTWA_F0 +#define YCTWA_F1_1 DVDEC1.YCTWA_F1 +#define YCTWA_F2_1 DVDEC1.YCTWA_F2 +#define YCTWA_F3_1 DVDEC1.YCTWA_F3 +#define YCTWA_F4_1 DVDEC1.YCTWA_F4 +#define YCTWA_F5_1 DVDEC1.YCTWA_F5 +#define YCTWA_F6_1 DVDEC1.YCTWA_F6 +#define YCTWA_F7_1 DVDEC1.YCTWA_F7 +#define YCTWA_F8_1 DVDEC1.YCTWA_F8 +#define YCTWB_F0_1 DVDEC1.YCTWB_F0 +#define YCTWB_F1_1 DVDEC1.YCTWB_F1 +#define YCTWB_F2_1 DVDEC1.YCTWB_F2 +#define YCTWB_F3_1 DVDEC1.YCTWB_F3 +#define YCTWB_F4_1 DVDEC1.YCTWB_F4 +#define YCTWB_F5_1 DVDEC1.YCTWB_F5 +#define YCTWB_F6_1 DVDEC1.YCTWB_F6 +#define YCTWB_F7_1 DVDEC1.YCTWB_F7 +#define YCTWB_F8_1 DVDEC1.YCTWB_F8 +#define YCTNA_F0_1 DVDEC1.YCTNA_F0 +#define YCTNA_F1_1 DVDEC1.YCTNA_F1 +#define YCTNA_F2_1 DVDEC1.YCTNA_F2 +#define YCTNA_F3_1 DVDEC1.YCTNA_F3 +#define YCTNA_F4_1 DVDEC1.YCTNA_F4 +#define YCTNA_F5_1 DVDEC1.YCTNA_F5 +#define YCTNA_F6_1 DVDEC1.YCTNA_F6 +#define YCTNA_F7_1 DVDEC1.YCTNA_F7 +#define YCTNA_F8_1 DVDEC1.YCTNA_F8 +#define YCTNB_F0_1 DVDEC1.YCTNB_F0 +#define YCTNB_F1_1 DVDEC1.YCTNB_F1 +#define YCTNB_F2_1 DVDEC1.YCTNB_F2 +#define YCTNB_F3_1 DVDEC1.YCTNB_F3 +#define YCTNB_F4_1 DVDEC1.YCTNB_F4 +#define YCTNB_F5_1 DVDEC1.YCTNB_F5 +#define YCTNB_F6_1 DVDEC1.YCTNB_F6 +#define YCTNB_F7_1 DVDEC1.YCTNB_F7 +#define YCTNB_F8_1 DVDEC1.YCTNB_F8 +#define YGAINCR_1 DVDEC1.YGAINCR +#define CBGAINCR_1 DVDEC1.CBGAINCR +#define CRGAINCR_1 DVDEC1.CRGAINCR +#define PGA_UPDATE_1 DVDEC1.PGA_UPDATE +#define PGACR_1 DVDEC1.PGACR +#define ADCCR2_1 DVDEC1.ADCCR2 +#define ADCCR1_0 DVDEC0.ADCCR1 +#define TGCR1_0 DVDEC0.TGCR1 +#define TGCR2_0 DVDEC0.TGCR2 +#define TGCR3_0 DVDEC0.TGCR3 +#define SYNSCR1_0 DVDEC0.SYNSCR1 +#define SYNSCR2_0 DVDEC0.SYNSCR2 +#define SYNSCR3_0 DVDEC0.SYNSCR3 +#define SYNSCR4_0 DVDEC0.SYNSCR4 +#define SYNSCR5_0 DVDEC0.SYNSCR5 +#define HAFCCR1_0 DVDEC0.HAFCCR1 +#define HAFCCR2_0 DVDEC0.HAFCCR2 +#define HAFCCR3_0 DVDEC0.HAFCCR3 +#define VCDWCR1_0 DVDEC0.VCDWCR1 +#define DCPCR1_0 DVDEC0.DCPCR1 +#define DCPCR2_0 DVDEC0.DCPCR2 +#define DCPCR3_0 DVDEC0.DCPCR3 +#define DCPCR4_0 DVDEC0.DCPCR4 +#define DCPCR5_0 DVDEC0.DCPCR5 +#define DCPCR6_0 DVDEC0.DCPCR6 +#define DCPCR7_0 DVDEC0.DCPCR7 +#define DCPCR8_0 DVDEC0.DCPCR8 +#define NSDCR_0 DVDEC0.NSDCR +#define BTLCR_0 DVDEC0.BTLCR +#define BTGPCR_0 DVDEC0.BTGPCR +#define ACCCR1_0 DVDEC0.ACCCR1 +#define ACCCR2_0 DVDEC0.ACCCR2 +#define ACCCR3_0 DVDEC0.ACCCR3 +#define TINTCR_0 DVDEC0.TINTCR +#define YCDCR_0 DVDEC0.YCDCR +#define AGCCR1_0 DVDEC0.AGCCR1 +#define AGCCR2_0 DVDEC0.AGCCR2 +#define PKLIMITCR_0 DVDEC0.PKLIMITCR +#define RGORCR1_0 DVDEC0.RGORCR1 +#define RGORCR2_0 DVDEC0.RGORCR2 +#define RGORCR3_0 DVDEC0.RGORCR3 +#define RGORCR4_0 DVDEC0.RGORCR4 +#define RGORCR5_0 DVDEC0.RGORCR5 +#define RGORCR6_0 DVDEC0.RGORCR6 +#define RGORCR7_0 DVDEC0.RGORCR7 +#define AFCPFCR_0 DVDEC0.AFCPFCR +#define RUPDCR_0 DVDEC0.RUPDCR +#define VSYNCSR_0 DVDEC0.VSYNCSR +#define HSYNCSR_0 DVDEC0.HSYNCSR +#define DCPSR1_0 DVDEC0.DCPSR1 +#define DCPSR2_0 DVDEC0.DCPSR2 +#define NSDSR_0 DVDEC0.NSDSR +#define CROMASR1_0 DVDEC0.CROMASR1 +#define CROMASR2_0 DVDEC0.CROMASR2 +#define SYNCSSR_0 DVDEC0.SYNCSSR +#define AGCCSR1_0 DVDEC0.AGCCSR1 +#define AGCCSR2_0 DVDEC0.AGCCSR2 +#define YCSCR3_0 DVDEC0.YCSCR3 +#define YCSCR4_0 DVDEC0.YCSCR4 +#define YCSCR5_0 DVDEC0.YCSCR5 +#define YCSCR6_0 DVDEC0.YCSCR6 +#define YCSCR7_0 DVDEC0.YCSCR7 +#define YCSCR8_0 DVDEC0.YCSCR8 +#define YCSCR9_0 DVDEC0.YCSCR9 +#define YCSCR11_0 DVDEC0.YCSCR11 +#define YCSCR12_0 DVDEC0.YCSCR12 +#define DCPCR9_0 DVDEC0.DCPCR9 +#define YCTWA_F0_0 DVDEC0.YCTWA_F0 +#define YCTWA_F1_0 DVDEC0.YCTWA_F1 +#define YCTWA_F2_0 DVDEC0.YCTWA_F2 +#define YCTWA_F3_0 DVDEC0.YCTWA_F3 +#define YCTWA_F4_0 DVDEC0.YCTWA_F4 +#define YCTWA_F5_0 DVDEC0.YCTWA_F5 +#define YCTWA_F6_0 DVDEC0.YCTWA_F6 +#define YCTWA_F7_0 DVDEC0.YCTWA_F7 +#define YCTWA_F8_0 DVDEC0.YCTWA_F8 +#define YCTWB_F0_0 DVDEC0.YCTWB_F0 +#define YCTWB_F1_0 DVDEC0.YCTWB_F1 +#define YCTWB_F2_0 DVDEC0.YCTWB_F2 +#define YCTWB_F3_0 DVDEC0.YCTWB_F3 +#define YCTWB_F4_0 DVDEC0.YCTWB_F4 +#define YCTWB_F5_0 DVDEC0.YCTWB_F5 +#define YCTWB_F6_0 DVDEC0.YCTWB_F6 +#define YCTWB_F7_0 DVDEC0.YCTWB_F7 +#define YCTWB_F8_0 DVDEC0.YCTWB_F8 +#define YCTNA_F0_0 DVDEC0.YCTNA_F0 +#define YCTNA_F1_0 DVDEC0.YCTNA_F1 +#define YCTNA_F2_0 DVDEC0.YCTNA_F2 +#define YCTNA_F3_0 DVDEC0.YCTNA_F3 +#define YCTNA_F4_0 DVDEC0.YCTNA_F4 +#define YCTNA_F5_0 DVDEC0.YCTNA_F5 +#define YCTNA_F6_0 DVDEC0.YCTNA_F6 +#define YCTNA_F7_0 DVDEC0.YCTNA_F7 +#define YCTNA_F8_0 DVDEC0.YCTNA_F8 +#define YCTNB_F0_0 DVDEC0.YCTNB_F0 +#define YCTNB_F1_0 DVDEC0.YCTNB_F1 +#define YCTNB_F2_0 DVDEC0.YCTNB_F2 +#define YCTNB_F3_0 DVDEC0.YCTNB_F3 +#define YCTNB_F4_0 DVDEC0.YCTNB_F4 +#define YCTNB_F5_0 DVDEC0.YCTNB_F5 +#define YCTNB_F6_0 DVDEC0.YCTNB_F6 +#define YCTNB_F7_0 DVDEC0.YCTNB_F7 +#define YCTNB_F8_0 DVDEC0.YCTNB_F8 +#define YGAINCR_0 DVDEC0.YGAINCR +#define CBGAINCR_0 DVDEC0.CBGAINCR +#define CRGAINCR_0 DVDEC0.CRGAINCR +#define PGA_UPDATE_0 DVDEC0.PGA_UPDATE +#define PGACR_0 DVDEC0.PGACR +#define ADCCR2_0 DVDEC0.ADCCR2 +/* <-SEC M1.10.1 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/ether_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,427 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : ether_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef ETHER_IODEFINE_H +#define ETHER_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->SEC M1.10.1 : Not magic number */ + +struct st_ether +{ /* ETHER */ + volatile uint32_t EDSR0; /* EDSR0 */ + volatile uint8_t dummy207[12]; /* */ + volatile uint32_t TDLAR0; /* TDLAR0 */ + volatile uint32_t TDFAR0; /* TDFAR0 */ + volatile uint32_t TDFXR0; /* TDFXR0 */ + volatile uint32_t TDFFR0; /* TDFFR0 */ + volatile uint8_t dummy208[16]; /* */ + volatile uint32_t RDLAR0; /* RDLAR0 */ + volatile uint32_t RDFAR0; /* RDFAR0 */ + volatile uint32_t RDFXR0; /* RDFXR0 */ + volatile uint32_t RDFFR0; /* RDFFR0 */ + volatile uint8_t dummy209[960]; /* */ + volatile uint32_t EDMR0; /* EDMR0 */ + volatile uint8_t dummy210[4]; /* */ + volatile uint32_t EDTRR0; /* EDTRR0 */ + volatile uint8_t dummy211[4]; /* */ + volatile uint32_t EDRRR0; /* EDRRR0 */ + volatile uint8_t dummy212[20]; /* */ + volatile uint32_t EESR0; /* EESR0 */ + volatile uint8_t dummy213[4]; /* */ + volatile uint32_t EESIPR0; /* EESIPR0 */ + volatile uint8_t dummy214[4]; /* */ + volatile uint32_t TRSCER0; /* TRSCER0 */ + volatile uint8_t dummy215[4]; /* */ + volatile uint32_t RMFCR0; /* RMFCR0 */ + volatile uint8_t dummy216[4]; /* */ + volatile uint32_t TFTR0; /* TFTR0 */ + volatile uint8_t dummy217[4]; /* */ + volatile uint32_t FDR0; /* FDR0 */ + volatile uint8_t dummy218[4]; /* */ + volatile uint32_t RMCR0; /* RMCR0 */ + volatile uint8_t dummy219[4]; /* */ + volatile uint32_t RPADIR0; /* RPADIR0 */ + volatile uint8_t dummy220[4]; /* */ + volatile uint32_t FCFTR0; /* FCFTR0 */ + volatile uint8_t dummy221[120]; /* */ + volatile uint32_t CSMR; /* CSMR */ + volatile uint32_t CSSBM; /* CSSBM */ + volatile uint32_t CSSMR; /* CSSMR */ + volatile uint8_t dummy222[16]; /* */ + volatile uint32_t ECMR0; /* ECMR0 */ + volatile uint8_t dummy223[4]; /* */ + volatile uint32_t RFLR0; /* RFLR0 */ + volatile uint8_t dummy224[4]; /* */ + volatile uint32_t ECSR0; /* ECSR0 */ + volatile uint8_t dummy225[4]; /* */ + volatile uint32_t ECSIPR0; /* ECSIPR0 */ + volatile uint8_t dummy226[4]; /* */ + volatile uint32_t PIR0; /* PIR0 */ + volatile uint8_t dummy227[48]; /* */ + volatile uint32_t APR0; /* APR0 */ + volatile uint32_t MPR0; /* MPR0 */ + volatile uint32_t PFTCR0; /* PFTCR0 */ + volatile uint32_t PFRCR0; /* PFRCR0 */ + volatile uint32_t TPAUSER0; /* TPAUSER0 */ + volatile uint8_t dummy228[88]; /* */ + volatile uint32_t MAHR0; /* MAHR0 */ + volatile uint8_t dummy229[4]; /* */ + volatile uint32_t MALR0; /* MALR0 */ + volatile uint8_t dummy230[372]; /* */ + volatile uint32_t CEFCR0; /* CEFCR0 */ + volatile uint8_t dummy231[4]; /* */ + volatile uint32_t FRECR0; /* FRECR0 */ + volatile uint8_t dummy232[4]; /* */ + volatile uint32_t TSFRCR0; /* TSFRCR0 */ + volatile uint8_t dummy233[4]; /* */ + volatile uint32_t TLFRCR0; /* TLFRCR0 */ + volatile uint8_t dummy234[4]; /* */ + volatile uint32_t RFCR0; /* RFCR0 */ + volatile uint8_t dummy235[20]; /* */ + volatile uint32_t MAFCR0; /* MAFCR0 */ + volatile uint8_t dummy236[4228]; /* */ + volatile uint32_t ARSTR; /* ARSTR */ + volatile uint32_t TSU_CTRST; /* TSU_CTRST */ + volatile uint8_t dummy237[80]; /* */ + volatile uint32_t TSU_VTAG0; /* TSU_VTAG0 */ + volatile uint8_t dummy238[4]; /* */ + volatile uint32_t TSU_ADSBSY; /* TSU_ADSBSY */ + volatile uint32_t TSU_TEN; /* TSU_TEN */ + volatile uint8_t dummy239[24]; /* */ + volatile uint32_t TXNLCR0; /* TXNLCR0 */ + volatile uint32_t TXALCR0; /* TXALCR0 */ + volatile uint32_t RXNLCR0; /* RXNLCR0 */ + volatile uint32_t RXALCR0; /* RXALCR0 */ + volatile uint8_t dummy240[112]; /* */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH0; /* TSU_ADRH0 */ + volatile uint32_t TSU_ADRL0; /* TSU_ADRL0 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH1; /* TSU_ADRH1 */ + volatile uint32_t TSU_ADRL1; /* TSU_ADRL1 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH2; /* TSU_ADRH2 */ + volatile uint32_t TSU_ADRL2; /* TSU_ADRL2 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH3; /* TSU_ADRH3 */ + volatile uint32_t TSU_ADRL3; /* TSU_ADRL3 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH4; /* TSU_ADRH4 */ + volatile uint32_t TSU_ADRL4; /* TSU_ADRL4 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH5; /* TSU_ADRH5 */ + volatile uint32_t TSU_ADRL5; /* TSU_ADRL5 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH6; /* TSU_ADRH6 */ + volatile uint32_t TSU_ADRL6; /* TSU_ADRL6 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH7; /* TSU_ADRH7 */ + volatile uint32_t TSU_ADRL7; /* TSU_ADRL7 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH8; /* TSU_ADRH8 */ + volatile uint32_t TSU_ADRL8; /* TSU_ADRL8 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH9; /* TSU_ADRH9 */ + volatile uint32_t TSU_ADRL9; /* TSU_ADRL9 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH10; /* TSU_ADRH10 */ + volatile uint32_t TSU_ADRL10; /* TSU_ADRL10 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH11; /* TSU_ADRH11 */ + volatile uint32_t TSU_ADRL11; /* TSU_ADRL11 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH12; /* TSU_ADRH12 */ + volatile uint32_t TSU_ADRL12; /* TSU_ADRL12 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH13; /* TSU_ADRH13 */ + volatile uint32_t TSU_ADRL13; /* TSU_ADRL13 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH14; /* TSU_ADRH14 */ + volatile uint32_t TSU_ADRL14; /* TSU_ADRL14 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH15; /* TSU_ADRH15 */ + volatile uint32_t TSU_ADRL15; /* TSU_ADRL15 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH16; /* TSU_ADRH16 */ + volatile uint32_t TSU_ADRL16; /* TSU_ADRL16 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH17; /* TSU_ADRH17 */ + volatile uint32_t TSU_ADRL17; /* TSU_ADRL17 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH18; /* TSU_ADRH18 */ + volatile uint32_t TSU_ADRL18; /* TSU_ADRL18 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH19; /* TSU_ADRH19 */ + volatile uint32_t TSU_ADRL19; /* TSU_ADRL19 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH20; /* TSU_ADRH20 */ + volatile uint32_t TSU_ADRL20; /* TSU_ADRL20 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH21; /* TSU_ADRH21 */ + volatile uint32_t TSU_ADRL21; /* TSU_ADRL21 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH22; /* TSU_ADRH22 */ + volatile uint32_t TSU_ADRL22; /* TSU_ADRL22 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH23; /* TSU_ADRH23 */ + volatile uint32_t TSU_ADRL23; /* TSU_ADRL23 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH24; /* TSU_ADRH24 */ + volatile uint32_t TSU_ADRL24; /* TSU_ADRL24 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH25; /* TSU_ADRH25 */ + volatile uint32_t TSU_ADRL25; /* TSU_ADRL25 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH26; /* TSU_ADRH26 */ + volatile uint32_t TSU_ADRL26; /* TSU_ADRL26 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH27; /* TSU_ADRH27 */ + volatile uint32_t TSU_ADRL27; /* TSU_ADRL27 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH28; /* TSU_ADRH28 */ + volatile uint32_t TSU_ADRL28; /* TSU_ADRL28 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH29; /* TSU_ADRH29 */ + volatile uint32_t TSU_ADRL29; /* TSU_ADRL29 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH30; /* TSU_ADRH30 */ + volatile uint32_t TSU_ADRL30; /* TSU_ADRL30 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH31; /* TSU_ADRH31 */ + volatile uint32_t TSU_ADRL31; /* TSU_ADRL31 */ +/* end of struct st_ether_from_tsu_adrh0 */ +}; + + +struct st_ether_from_tsu_adrh0 +{ + volatile uint32_t TSU_ADRH0; /* TSU_ADRH0 */ + volatile uint32_t TSU_ADRL0; /* TSU_ADRL0 */ +}; + + +#define ETHER (*(struct st_ether *)0xE8203000uL) /* ETHER */ + + +/* Start of channnel array defines of ETHER */ + +/* Channnel array defines of ETHER_FROM_TSU_ADRH0_ARRAY */ +/*(Sample) value = ETHER_FROM_TSU_ADRH0_ARRAY[ channel ]->TSU_ADRH0; */ +#define ETHER_FROM_TSU_ADRH0_ARRAY_COUNT 32 +#define ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + ÐER_FROM_TSU_ADRH0, ÐER_FROM_TSU_ADRH1, ÐER_FROM_TSU_ADRH2, ÐER_FROM_TSU_ADRH3, ÐER_FROM_TSU_ADRH4, ÐER_FROM_TSU_ADRH5, ÐER_FROM_TSU_ADRH6, ÐER_FROM_TSU_ADRH7, \ + ÐER_FROM_TSU_ADRH8, ÐER_FROM_TSU_ADRH9, ÐER_FROM_TSU_ADRH10, ÐER_FROM_TSU_ADRH11, ÐER_FROM_TSU_ADRH12, ÐER_FROM_TSU_ADRH13, ÐER_FROM_TSU_ADRH14, ÐER_FROM_TSU_ADRH15, \ + ÐER_FROM_TSU_ADRH16, ÐER_FROM_TSU_ADRH17, ÐER_FROM_TSU_ADRH18, ÐER_FROM_TSU_ADRH19, ÐER_FROM_TSU_ADRH20, ÐER_FROM_TSU_ADRH21, ÐER_FROM_TSU_ADRH22, ÐER_FROM_TSU_ADRH23, \ + ÐER_FROM_TSU_ADRH24, ÐER_FROM_TSU_ADRH25, ÐER_FROM_TSU_ADRH26, ÐER_FROM_TSU_ADRH27, ÐER_FROM_TSU_ADRH28, ÐER_FROM_TSU_ADRH29, ÐER_FROM_TSU_ADRH30, ÐER_FROM_TSU_ADRH31 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define ETHER_FROM_TSU_ADRH0 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH0) /* ETHER_FROM_TSU_ADRH0 */ +#define ETHER_FROM_TSU_ADRH1 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH1) /* ETHER_FROM_TSU_ADRH1 */ +#define ETHER_FROM_TSU_ADRH2 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH2) /* ETHER_FROM_TSU_ADRH2 */ +#define ETHER_FROM_TSU_ADRH3 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH3) /* ETHER_FROM_TSU_ADRH3 */ +#define ETHER_FROM_TSU_ADRH4 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH4) /* ETHER_FROM_TSU_ADRH4 */ +#define ETHER_FROM_TSU_ADRH5 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH5) /* ETHER_FROM_TSU_ADRH5 */ +#define ETHER_FROM_TSU_ADRH6 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH6) /* ETHER_FROM_TSU_ADRH6 */ +#define ETHER_FROM_TSU_ADRH7 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH7) /* ETHER_FROM_TSU_ADRH7 */ +#define ETHER_FROM_TSU_ADRH8 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH8) /* ETHER_FROM_TSU_ADRH8 */ +#define ETHER_FROM_TSU_ADRH9 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH9) /* ETHER_FROM_TSU_ADRH9 */ +#define ETHER_FROM_TSU_ADRH10 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH10) /* ETHER_FROM_TSU_ADRH10 */ +#define ETHER_FROM_TSU_ADRH11 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH11) /* ETHER_FROM_TSU_ADRH11 */ +#define ETHER_FROM_TSU_ADRH12 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH12) /* ETHER_FROM_TSU_ADRH12 */ +#define ETHER_FROM_TSU_ADRH13 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH13) /* ETHER_FROM_TSU_ADRH13 */ +#define ETHER_FROM_TSU_ADRH14 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH14) /* ETHER_FROM_TSU_ADRH14 */ +#define ETHER_FROM_TSU_ADRH15 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH15) /* ETHER_FROM_TSU_ADRH15 */ +#define ETHER_FROM_TSU_ADRH16 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH16) /* ETHER_FROM_TSU_ADRH16 */ +#define ETHER_FROM_TSU_ADRH17 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH17) /* ETHER_FROM_TSU_ADRH17 */ +#define ETHER_FROM_TSU_ADRH18 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH18) /* ETHER_FROM_TSU_ADRH18 */ +#define ETHER_FROM_TSU_ADRH19 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH19) /* ETHER_FROM_TSU_ADRH19 */ +#define ETHER_FROM_TSU_ADRH20 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH20) /* ETHER_FROM_TSU_ADRH20 */ +#define ETHER_FROM_TSU_ADRH21 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH21) /* ETHER_FROM_TSU_ADRH21 */ +#define ETHER_FROM_TSU_ADRH22 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH22) /* ETHER_FROM_TSU_ADRH22 */ +#define ETHER_FROM_TSU_ADRH23 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH23) /* ETHER_FROM_TSU_ADRH23 */ +#define ETHER_FROM_TSU_ADRH24 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH24) /* ETHER_FROM_TSU_ADRH24 */ +#define ETHER_FROM_TSU_ADRH25 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH25) /* ETHER_FROM_TSU_ADRH25 */ +#define ETHER_FROM_TSU_ADRH26 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH26) /* ETHER_FROM_TSU_ADRH26 */ +#define ETHER_FROM_TSU_ADRH27 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH27) /* ETHER_FROM_TSU_ADRH27 */ +#define ETHER_FROM_TSU_ADRH28 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH28) /* ETHER_FROM_TSU_ADRH28 */ +#define ETHER_FROM_TSU_ADRH29 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH29) /* ETHER_FROM_TSU_ADRH29 */ +#define ETHER_FROM_TSU_ADRH30 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH30) /* ETHER_FROM_TSU_ADRH30 */ +#define ETHER_FROM_TSU_ADRH31 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH31) /* ETHER_FROM_TSU_ADRH31 */ + +/* End of channnel array defines of ETHER */ + + +#define ETHEREDSR0 ETHER.EDSR0 +#define ETHERTDLAR0 ETHER.TDLAR0 +#define ETHERTDFAR0 ETHER.TDFAR0 +#define ETHERTDFXR0 ETHER.TDFXR0 +#define ETHERTDFFR0 ETHER.TDFFR0 +#define ETHERRDLAR0 ETHER.RDLAR0 +#define ETHERRDFAR0 ETHER.RDFAR0 +#define ETHERRDFXR0 ETHER.RDFXR0 +#define ETHERRDFFR0 ETHER.RDFFR0 +#define ETHEREDMR0 ETHER.EDMR0 +#define ETHEREDTRR0 ETHER.EDTRR0 +#define ETHEREDRRR0 ETHER.EDRRR0 +#define ETHEREESR0 ETHER.EESR0 +#define ETHEREESIPR0 ETHER.EESIPR0 +#define ETHERTRSCER0 ETHER.TRSCER0 +#define ETHERRMFCR0 ETHER.RMFCR0 +#define ETHERTFTR0 ETHER.TFTR0 +#define ETHERFDR0 ETHER.FDR0 +#define ETHERRMCR0 ETHER.RMCR0 +#define ETHERRPADIR0 ETHER.RPADIR0 +#define ETHERFCFTR0 ETHER.FCFTR0 +#define ETHERCSMR ETHER.CSMR +#define ETHERCSSBM ETHER.CSSBM +#define ETHERCSSMR ETHER.CSSMR +#define ETHERECMR0 ETHER.ECMR0 +#define ETHERRFLR0 ETHER.RFLR0 +#define ETHERECSR0 ETHER.ECSR0 +#define ETHERECSIPR0 ETHER.ECSIPR0 +#define ETHERPIR0 ETHER.PIR0 +#define ETHERAPR0 ETHER.APR0 +#define ETHERMPR0 ETHER.MPR0 +#define ETHERPFTCR0 ETHER.PFTCR0 +#define ETHERPFRCR0 ETHER.PFRCR0 +#define ETHERTPAUSER0 ETHER.TPAUSER0 +#define ETHERMAHR0 ETHER.MAHR0 +#define ETHERMALR0 ETHER.MALR0 +#define ETHERCEFCR0 ETHER.CEFCR0 +#define ETHERFRECR0 ETHER.FRECR0 +#define ETHERTSFRCR0 ETHER.TSFRCR0 +#define ETHERTLFRCR0 ETHER.TLFRCR0 +#define ETHERRFCR0 ETHER.RFCR0 +#define ETHERMAFCR0 ETHER.MAFCR0 +#define ETHERARSTR ETHER.ARSTR +#define ETHERTSU_CTRST ETHER.TSU_CTRST +#define ETHERTSU_VTAG0 ETHER.TSU_VTAG0 +#define ETHERTSU_ADSBSY ETHER.TSU_ADSBSY +#define ETHERTSU_TEN ETHER.TSU_TEN +#define ETHERTXNLCR0 ETHER.TXNLCR0 +#define ETHERTXALCR0 ETHER.TXALCR0 +#define ETHERRXNLCR0 ETHER.RXNLCR0 +#define ETHERRXALCR0 ETHER.RXALCR0 +#define ETHERTSU_ADRH0 ETHER.TSU_ADRH0 +#define ETHERTSU_ADRL0 ETHER.TSU_ADRL0 +#define ETHERTSU_ADRH1 ETHER.TSU_ADRH1 +#define ETHERTSU_ADRL1 ETHER.TSU_ADRL1 +#define ETHERTSU_ADRH2 ETHER.TSU_ADRH2 +#define ETHERTSU_ADRL2 ETHER.TSU_ADRL2 +#define ETHERTSU_ADRH3 ETHER.TSU_ADRH3 +#define ETHERTSU_ADRL3 ETHER.TSU_ADRL3 +#define ETHERTSU_ADRH4 ETHER.TSU_ADRH4 +#define ETHERTSU_ADRL4 ETHER.TSU_ADRL4 +#define ETHERTSU_ADRH5 ETHER.TSU_ADRH5 +#define ETHERTSU_ADRL5 ETHER.TSU_ADRL5 +#define ETHERTSU_ADRH6 ETHER.TSU_ADRH6 +#define ETHERTSU_ADRL6 ETHER.TSU_ADRL6 +#define ETHERTSU_ADRH7 ETHER.TSU_ADRH7 +#define ETHERTSU_ADRL7 ETHER.TSU_ADRL7 +#define ETHERTSU_ADRH8 ETHER.TSU_ADRH8 +#define ETHERTSU_ADRL8 ETHER.TSU_ADRL8 +#define ETHERTSU_ADRH9 ETHER.TSU_ADRH9 +#define ETHERTSU_ADRL9 ETHER.TSU_ADRL9 +#define ETHERTSU_ADRH10 ETHER.TSU_ADRH10 +#define ETHERTSU_ADRL10 ETHER.TSU_ADRL10 +#define ETHERTSU_ADRH11 ETHER.TSU_ADRH11 +#define ETHERTSU_ADRL11 ETHER.TSU_ADRL11 +#define ETHERTSU_ADRH12 ETHER.TSU_ADRH12 +#define ETHERTSU_ADRL12 ETHER.TSU_ADRL12 +#define ETHERTSU_ADRH13 ETHER.TSU_ADRH13 +#define ETHERTSU_ADRL13 ETHER.TSU_ADRL13 +#define ETHERTSU_ADRH14 ETHER.TSU_ADRH14 +#define ETHERTSU_ADRL14 ETHER.TSU_ADRL14 +#define ETHERTSU_ADRH15 ETHER.TSU_ADRH15 +#define ETHERTSU_ADRL15 ETHER.TSU_ADRL15 +#define ETHERTSU_ADRH16 ETHER.TSU_ADRH16 +#define ETHERTSU_ADRL16 ETHER.TSU_ADRL16 +#define ETHERTSU_ADRH17 ETHER.TSU_ADRH17 +#define ETHERTSU_ADRL17 ETHER.TSU_ADRL17 +#define ETHERTSU_ADRH18 ETHER.TSU_ADRH18 +#define ETHERTSU_ADRL18 ETHER.TSU_ADRL18 +#define ETHERTSU_ADRH19 ETHER.TSU_ADRH19 +#define ETHERTSU_ADRL19 ETHER.TSU_ADRL19 +#define ETHERTSU_ADRH20 ETHER.TSU_ADRH20 +#define ETHERTSU_ADRL20 ETHER.TSU_ADRL20 +#define ETHERTSU_ADRH21 ETHER.TSU_ADRH21 +#define ETHERTSU_ADRL21 ETHER.TSU_ADRL21 +#define ETHERTSU_ADRH22 ETHER.TSU_ADRH22 +#define ETHERTSU_ADRL22 ETHER.TSU_ADRL22 +#define ETHERTSU_ADRH23 ETHER.TSU_ADRH23 +#define ETHERTSU_ADRL23 ETHER.TSU_ADRL23 +#define ETHERTSU_ADRH24 ETHER.TSU_ADRH24 +#define ETHERTSU_ADRL24 ETHER.TSU_ADRL24 +#define ETHERTSU_ADRH25 ETHER.TSU_ADRH25 +#define ETHERTSU_ADRL25 ETHER.TSU_ADRL25 +#define ETHERTSU_ADRH26 ETHER.TSU_ADRH26 +#define ETHERTSU_ADRL26 ETHER.TSU_ADRL26 +#define ETHERTSU_ADRH27 ETHER.TSU_ADRH27 +#define ETHERTSU_ADRL27 ETHER.TSU_ADRL27 +#define ETHERTSU_ADRH28 ETHER.TSU_ADRH28 +#define ETHERTSU_ADRL28 ETHER.TSU_ADRL28 +#define ETHERTSU_ADRH29 ETHER.TSU_ADRH29 +#define ETHERTSU_ADRL29 ETHER.TSU_ADRL29 +#define ETHERTSU_ADRH30 ETHER.TSU_ADRH30 +#define ETHERTSU_ADRL30 ETHER.TSU_ADRL30 +#define ETHERTSU_ADRH31 ETHER.TSU_ADRH31 +#define ETHERTSU_ADRL31 ETHER.TSU_ADRL31 +/* <-SEC M1.10.1 */ +/* <-QAC 0639 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/flctl_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,72 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : flctl_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef FLCTL_IODEFINE_H +#define FLCTL_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_flctl +{ /* FLCTL */ + volatile uint32_t FLCMNCR; /* FLCMNCR */ + volatile uint32_t FLCMDCR; /* FLCMDCR */ + volatile uint32_t FLCMCDR; /* FLCMCDR */ + volatile uint32_t FLADR; /* FLADR */ + volatile uint32_t FLDATAR; /* FLDATAR */ + volatile uint32_t FLDTCNTR; /* FLDTCNTR */ + volatile uint32_t FLINTDMACR; /* FLINTDMACR */ + volatile uint32_t FLBSYTMR; /* FLBSYTMR */ + volatile uint32_t FLBSYCNT; /* FLBSYCNT */ + volatile uint8_t dummy555[8]; /* */ + volatile uint8_t FLTRCR; /* FLTRCR */ + volatile uint8_t dummy556[15]; /* */ + volatile uint32_t FLADR2; /* FLADR2 */ + volatile uint8_t dummy557[16]; /* */ + volatile uint32_t FLDTFIFO; /* FLDTFIFO */ + volatile uint8_t dummy558[12]; /* */ + volatile uint32_t FLECFIFO; /* FLECFIFO */ +}; + + +#define FLCTL (*(struct st_flctl *)0xFCFF4000uL) /* FLCTL */ + + +#define FLCTLFLCMNCR FLCTL.FLCMNCR +#define FLCTLFLCMDCR FLCTL.FLCMDCR +#define FLCTLFLCMCDR FLCTL.FLCMCDR +#define FLCTLFLADR FLCTL.FLADR +#define FLCTLFLDATAR FLCTL.FLDATAR +#define FLCTLFLDTCNTR FLCTL.FLDTCNTR +#define FLCTLFLINTDMACR FLCTL.FLINTDMACR +#define FLCTLFLBSYTMR FLCTL.FLBSYTMR +#define FLCTLFLBSYCNT FLCTL.FLBSYCNT +#define FLCTLFLTRCR FLCTL.FLTRCR +#define FLCTLFLADR2 FLCTL.FLADR2 +#define FLCTLFLDTFIFO FLCTL.FLDTFIFO +#define FLCTLFLECFIFO FLCTL.FLECFIFO +/* <-SEC M1.10.1 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/gpio_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,1074 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : gpio_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef GPIO_IODEFINE_H +#define GPIO_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->SEC M1.10.1 : Not magic number */ + +struct st_gpio +{ /* GPIO */ +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P1; /* P1 */ + volatile uint8_t dummy348[2]; /* */ +/* end of struct st_gpio_from_p1 */ +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P2; /* P2 */ + volatile uint8_t dummy349[2]; /* */ +/* end of struct st_gpio_from_p1 */ +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P3; /* P3 */ + volatile uint8_t dummy350[2]; /* */ +/* end of struct st_gpio_from_p1 */ +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P4; /* P4 */ + volatile uint8_t dummy351[2]; /* */ +/* end of struct st_gpio_from_p1 */ +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P5; /* P5 */ + volatile uint8_t dummy352[2]; /* */ +/* end of struct st_gpio_from_p1 */ +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P6; /* P6 */ + volatile uint8_t dummy353[2]; /* */ +/* end of struct st_gpio_from_p1 */ +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P7; /* P7 */ + volatile uint8_t dummy354[2]; /* */ +/* end of struct st_gpio_from_p1 */ +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P8; /* P8 */ + volatile uint8_t dummy355[2]; /* */ +/* end of struct st_gpio_from_p1 */ +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P9; /* P9 */ + volatile uint8_t dummy356[2]; /* */ +/* end of struct st_gpio_from_p1 */ +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P10; /* P10 */ + volatile uint8_t dummy357[2]; /* */ +/* end of struct st_gpio_from_p1 */ +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P11; /* P11 */ + volatile uint8_t dummy3580[2]; /* */ +/* end of struct st_gpio_from_p1 */ + volatile uint8_t dummy3581[212]; /* */ +#define GPIO_PSRn_COUNT 11 + volatile uint32_t PSR1; /* PSR1 */ + volatile uint32_t PSR2; /* PSR2 */ + volatile uint32_t PSR3; /* PSR3 */ + volatile uint32_t PSR4; /* PSR4 */ + volatile uint32_t PSR5; /* PSR5 */ + volatile uint32_t PSR6; /* PSR6 */ + volatile uint32_t PSR7; /* PSR7 */ + volatile uint32_t PSR8; /* PSR8 */ + volatile uint32_t PSR9; /* PSR9 */ + volatile uint32_t PSR10; /* PSR10 */ + volatile uint32_t PSR11; /* PSR11 */ + volatile uint8_t dummy359[208]; /* */ +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR0; /* PPR0 */ + volatile uint8_t dummy360[2]; /* */ +/* end of struct st_gpio_from_ppr0 */ +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR1; /* PPR1 */ + volatile uint8_t dummy361[2]; /* */ +/* end of struct st_gpio_from_ppr0 */ +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR2; /* PPR2 */ + volatile uint8_t dummy362[2]; /* */ +/* end of struct st_gpio_from_ppr0 */ +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR3; /* PPR3 */ + volatile uint8_t dummy363[2]; /* */ +/* end of struct st_gpio_from_ppr0 */ +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR4; /* PPR4 */ + volatile uint8_t dummy364[2]; /* */ +/* end of struct st_gpio_from_ppr0 */ +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR5; /* PPR5 */ + volatile uint8_t dummy365[2]; /* */ +/* end of struct st_gpio_from_ppr0 */ +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR6; /* PPR6 */ + volatile uint8_t dummy366[2]; /* */ +/* end of struct st_gpio_from_ppr0 */ +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR7; /* PPR7 */ + volatile uint8_t dummy367[2]; /* */ +/* end of struct st_gpio_from_ppr0 */ +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR8; /* PPR8 */ + volatile uint8_t dummy368[2]; /* */ +/* end of struct st_gpio_from_ppr0 */ +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR9; /* PPR9 */ + volatile uint8_t dummy369[2]; /* */ +/* end of struct st_gpio_from_ppr0 */ +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR10; /* PPR10 */ + volatile uint8_t dummy370[2]; /* */ +/* end of struct st_gpio_from_ppr0 */ +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR11; /* PPR11 */ + volatile uint8_t dummy3710[2]; /* */ +/* end of struct st_gpio_from_ppr0 */ + volatile uint8_t dummy3711[212]; /* */ +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM1; /* PM1 */ + volatile uint8_t dummy372[2]; /* */ +/* end of struct st_gpio_from_pm1 */ +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM2; /* PM2 */ + volatile uint8_t dummy373[2]; /* */ +/* end of struct st_gpio_from_pm1 */ +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM3; /* PM3 */ + volatile uint8_t dummy374[2]; /* */ +/* end of struct st_gpio_from_pm1 */ +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM4; /* PM4 */ + volatile uint8_t dummy375[2]; /* */ +/* end of struct st_gpio_from_pm1 */ +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM5; /* PM5 */ + volatile uint8_t dummy376[2]; /* */ +/* end of struct st_gpio_from_pm1 */ +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM6; /* PM6 */ + volatile uint8_t dummy377[2]; /* */ +/* end of struct st_gpio_from_pm1 */ +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM7; /* PM7 */ + volatile uint8_t dummy378[2]; /* */ +/* end of struct st_gpio_from_pm1 */ +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM8; /* PM8 */ + volatile uint8_t dummy379[2]; /* */ +/* end of struct st_gpio_from_pm1 */ +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM9; /* PM9 */ + volatile uint8_t dummy380[2]; /* */ +/* end of struct st_gpio_from_pm1 */ +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM10; /* PM10 */ + volatile uint8_t dummy381[2]; /* */ +/* end of struct st_gpio_from_pm1 */ +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM11; /* PM11 */ + volatile uint8_t dummy3820[2]; /* */ +/* end of struct st_gpio_from_pm1 */ + volatile uint8_t dummy3821[208]; /* */ +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC0; /* PMC0 */ + volatile uint8_t dummy383[2]; /* */ +/* end of struct st_gpio_from_pmc0 */ +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC1; /* PMC1 */ + volatile uint8_t dummy384[2]; /* */ +/* end of struct st_gpio_from_pmc0 */ +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC2; /* PMC2 */ + volatile uint8_t dummy385[2]; /* */ +/* end of struct st_gpio_from_pmc0 */ +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC3; /* PMC3 */ + volatile uint8_t dummy386[2]; /* */ +/* end of struct st_gpio_from_pmc0 */ +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC4; /* PMC4 */ + volatile uint8_t dummy387[2]; /* */ +/* end of struct st_gpio_from_pmc0 */ +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC5; /* PMC5 */ + volatile uint8_t dummy388[2]; /* */ +/* end of struct st_gpio_from_pmc0 */ +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC6; /* PMC6 */ + volatile uint8_t dummy389[2]; /* */ +/* end of struct st_gpio_from_pmc0 */ +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC7; /* PMC7 */ + volatile uint8_t dummy390[2]; /* */ +/* end of struct st_gpio_from_pmc0 */ +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC8; /* PMC8 */ + volatile uint8_t dummy391[2]; /* */ +/* end of struct st_gpio_from_pmc0 */ +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC9; /* PMC9 */ + volatile uint8_t dummy392[2]; /* */ +/* end of struct st_gpio_from_pmc0 */ +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC10; /* PMC10 */ + volatile uint8_t dummy393[2]; /* */ +/* end of struct st_gpio_from_pmc0 */ +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC11; /* PMC11 */ + volatile uint8_t dummy3940[2]; /* */ +/* end of struct st_gpio_from_pmc0 */ + volatile uint8_t dummy3941[212]; /* */ +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC1; /* PFC1 */ + volatile uint8_t dummy395[2]; /* */ +/* end of struct st_gpio_from_pfc1 */ +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC2; /* PFC2 */ + volatile uint8_t dummy396[2]; /* */ +/* end of struct st_gpio_from_pfc1 */ +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC3; /* PFC3 */ + volatile uint8_t dummy397[2]; /* */ +/* end of struct st_gpio_from_pfc1 */ +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC4; /* PFC4 */ + volatile uint8_t dummy398[2]; /* */ +/* end of struct st_gpio_from_pfc1 */ +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC5; /* PFC5 */ + volatile uint8_t dummy399[2]; /* */ +/* end of struct st_gpio_from_pfc1 */ +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC6; /* PFC6 */ + volatile uint8_t dummy400[2]; /* */ +/* end of struct st_gpio_from_pfc1 */ +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC7; /* PFC7 */ + volatile uint8_t dummy401[2]; /* */ +/* end of struct st_gpio_from_pfc1 */ +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC8; /* PFC8 */ + volatile uint8_t dummy402[2]; /* */ +/* end of struct st_gpio_from_pfc1 */ +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC9; /* PFC9 */ + volatile uint8_t dummy403[2]; /* */ +/* end of struct st_gpio_from_pfc1 */ +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC10; /* PFC10 */ + volatile uint8_t dummy404[2]; /* */ +/* end of struct st_gpio_from_pfc1 */ +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC11; /* PFC11 */ + volatile uint8_t dummy4050[2]; /* */ +/* end of struct st_gpio_from_pfc1 */ + volatile uint8_t dummy4051[212]; /* */ +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE1; /* PFCE1 */ + volatile uint8_t dummy406[2]; /* */ +/* end of struct st_gpio_from_pfce1 */ +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE2; /* PFCE2 */ + volatile uint8_t dummy407[2]; /* */ +/* end of struct st_gpio_from_pfce1 */ +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE3; /* PFCE3 */ + volatile uint8_t dummy408[2]; /* */ +/* end of struct st_gpio_from_pfce1 */ +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE4; /* PFCE4 */ + volatile uint8_t dummy409[2]; /* */ +/* end of struct st_gpio_from_pfce1 */ +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE5; /* PFCE5 */ + volatile uint8_t dummy410[2]; /* */ +/* end of struct st_gpio_from_pfce1 */ +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE6; /* PFCE6 */ + volatile uint8_t dummy411[2]; /* */ +/* end of struct st_gpio_from_pfce1 */ +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE7; /* PFCE7 */ + volatile uint8_t dummy412[2]; /* */ +/* end of struct st_gpio_from_pfce1 */ +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE8; /* PFCE8 */ + volatile uint8_t dummy413[2]; /* */ +/* end of struct st_gpio_from_pfce1 */ +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE9; /* PFCE9 */ + volatile uint8_t dummy414[2]; /* */ +/* end of struct st_gpio_from_pfce1 */ +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE10; /* PFCE10 */ + volatile uint8_t dummy415[2]; /* */ +/* end of struct st_gpio_from_pfce1 */ +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE11; /* PFCE11 */ + volatile uint8_t dummy4160[2]; /* */ +/* end of struct st_gpio_from_pfce1 */ + volatile uint8_t dummy4161[212]; /* */ +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT1; /* PNOT1 */ + volatile uint8_t dummy417[2]; /* */ +/* end of struct st_gpio_from_pnot1 */ +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT2; /* PNOT2 */ + volatile uint8_t dummy418[2]; /* */ +/* end of struct st_gpio_from_pnot1 */ +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT3; /* PNOT3 */ + volatile uint8_t dummy419[2]; /* */ +/* end of struct st_gpio_from_pnot1 */ +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT4; /* PNOT4 */ + volatile uint8_t dummy420[2]; /* */ +/* end of struct st_gpio_from_pnot1 */ +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT5; /* PNOT5 */ + volatile uint8_t dummy421[2]; /* */ +/* end of struct st_gpio_from_pnot1 */ +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT6; /* PNOT6 */ + volatile uint8_t dummy422[2]; /* */ +/* end of struct st_gpio_from_pnot1 */ +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT7; /* PNOT7 */ + volatile uint8_t dummy423[2]; /* */ +/* end of struct st_gpio_from_pnot1 */ +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT8; /* PNOT8 */ + volatile uint8_t dummy424[2]; /* */ +/* end of struct st_gpio_from_pnot1 */ +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT9; /* PNOT9 */ + volatile uint8_t dummy425[2]; /* */ +/* end of struct st_gpio_from_pnot1 */ +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT10; /* PNOT10 */ + volatile uint8_t dummy426[2]; /* */ +/* end of struct st_gpio_from_pnot1 */ +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT11; /* PNOT11 */ + volatile uint8_t dummy4270[2]; /* */ +/* end of struct st_gpio_from_pnot1 */ + volatile uint8_t dummy4271[212]; /* */ +#define GPIO_PMSRn_COUNT 11 + volatile uint32_t PMSR1; /* PMSR1 */ + volatile uint32_t PMSR2; /* PMSR2 */ + volatile uint32_t PMSR3; /* PMSR3 */ + volatile uint32_t PMSR4; /* PMSR4 */ + volatile uint32_t PMSR5; /* PMSR5 */ + volatile uint32_t PMSR6; /* PMSR6 */ + volatile uint32_t PMSR7; /* PMSR7 */ + volatile uint32_t PMSR8; /* PMSR8 */ + volatile uint32_t PMSR9; /* PMSR9 */ + volatile uint32_t PMSR10; /* PMSR10 */ + volatile uint32_t PMSR11; /* PMSR11 */ + volatile uint8_t dummy428[208]; /* */ +#define GPIO_PMCSRn_COUNT 12 + volatile uint32_t PMCSR0; /* PMCSR0 */ + volatile uint32_t PMCSR1; /* PMCSR1 */ + volatile uint32_t PMCSR2; /* PMCSR2 */ + volatile uint32_t PMCSR3; /* PMCSR3 */ + volatile uint32_t PMCSR4; /* PMCSR4 */ + volatile uint32_t PMCSR5; /* PMCSR5 */ + volatile uint32_t PMCSR6; /* PMCSR6 */ + volatile uint32_t PMCSR7; /* PMCSR7 */ + volatile uint32_t PMCSR8; /* PMCSR8 */ + volatile uint32_t PMCSR9; /* PMCSR9 */ + volatile uint32_t PMCSR10; /* PMCSR10 */ + volatile uint32_t PMCSR11; /* PMCSR11 */ + volatile uint8_t dummy429[212]; /* */ +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE1; /* PFCAE1 */ + volatile uint8_t dummy430[2]; /* */ +/* end of struct st_gpio_from_pfcae1 */ +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE2; /* PFCAE2 */ + volatile uint8_t dummy431[2]; /* */ +/* end of struct st_gpio_from_pfcae1 */ +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE3; /* PFCAE3 */ + volatile uint8_t dummy432[2]; /* */ +/* end of struct st_gpio_from_pfcae1 */ +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE4; /* PFCAE4 */ + volatile uint8_t dummy433[2]; /* */ +/* end of struct st_gpio_from_pfcae1 */ +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE5; /* PFCAE5 */ + volatile uint8_t dummy434[2]; /* */ +/* end of struct st_gpio_from_pfcae1 */ +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE6; /* PFCAE6 */ + volatile uint8_t dummy435[2]; /* */ +/* end of struct st_gpio_from_pfcae1 */ +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE7; /* PFCAE7 */ + volatile uint8_t dummy436[2]; /* */ +/* end of struct st_gpio_from_pfcae1 */ +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE8; /* PFCAE8 */ + volatile uint8_t dummy437[2]; /* */ +/* end of struct st_gpio_from_pfcae1 */ +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE9; /* PFCAE9 */ + volatile uint8_t dummy438[2]; /* */ +/* end of struct st_gpio_from_pfcae1 */ +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE10; /* PFCAE10 */ + volatile uint8_t dummy439[2]; /* */ +/* end of struct st_gpio_from_pfcae1 */ +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE11; /* PFCAE11 */ + volatile uint8_t dummy4400[2]; /* */ +/* end of struct st_gpio_from_pfcae1 */ + volatile uint8_t dummy4401[464]; /* */ + volatile uint32_t SNCR; /* SNCR */ + volatile uint8_t dummy441[13308]; /* */ + volatile uint16_t PIBC0; /* PIBC0 */ + volatile uint8_t dummy442[2]; /* */ +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC1; /* PIBC1 */ + volatile uint8_t dummy443[2]; /* */ +/* end of struct st_gpio_from_pibc1 */ +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC2; /* PIBC2 */ + volatile uint8_t dummy444[2]; /* */ +/* end of struct st_gpio_from_pibc1 */ +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC3; /* PIBC3 */ + volatile uint8_t dummy445[2]; /* */ +/* end of struct st_gpio_from_pibc1 */ +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC4; /* PIBC4 */ + volatile uint8_t dummy446[2]; /* */ +/* end of struct st_gpio_from_pibc1 */ +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC5; /* PIBC5 */ + volatile uint8_t dummy447[2]; /* */ +/* end of struct st_gpio_from_pibc1 */ +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC6; /* PIBC6 */ + volatile uint8_t dummy448[2]; /* */ +/* end of struct st_gpio_from_pibc1 */ +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC7; /* PIBC7 */ + volatile uint8_t dummy449[2]; /* */ +/* end of struct st_gpio_from_pibc1 */ +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC8; /* PIBC8 */ + volatile uint8_t dummy450[2]; /* */ +/* end of struct st_gpio_from_pibc1 */ +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC9; /* PIBC9 */ + volatile uint8_t dummy451[2]; /* */ +/* end of struct st_gpio_from_pibc1 */ +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC10; /* PIBC10 */ + volatile uint8_t dummy452[2]; /* */ +/* end of struct st_gpio_from_pibc1 */ +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC11; /* PIBC11 */ + volatile uint8_t dummy4530[2]; /* */ +/* end of struct st_gpio_from_pibc1 */ + volatile uint8_t dummy4531[212]; /* */ +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC1; /* PBDC1 */ + volatile uint8_t dummy454[2]; /* */ +/* end of struct st_gpio_from_pbdc1 */ +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC2; /* PBDC2 */ + volatile uint8_t dummy455[2]; /* */ +/* end of struct st_gpio_from_pbdc1 */ +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC3; /* PBDC3 */ + volatile uint8_t dummy456[2]; /* */ +/* end of struct st_gpio_from_pbdc1 */ +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC4; /* PBDC4 */ + volatile uint8_t dummy457[2]; /* */ +/* end of struct st_gpio_from_pbdc1 */ +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC5; /* PBDC5 */ + volatile uint8_t dummy458[2]; /* */ +/* end of struct st_gpio_from_pbdc1 */ +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC6; /* PBDC6 */ + volatile uint8_t dummy459[2]; /* */ +/* end of struct st_gpio_from_pbdc1 */ +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC7; /* PBDC7 */ + volatile uint8_t dummy460[2]; /* */ +/* end of struct st_gpio_from_pbdc1 */ +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC8; /* PBDC8 */ + volatile uint8_t dummy461[2]; /* */ +/* end of struct st_gpio_from_pbdc1 */ +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC9; /* PBDC9 */ + volatile uint8_t dummy462[2]; /* */ +/* end of struct st_gpio_from_pbdc1 */ +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC10; /* PBDC10 */ + volatile uint8_t dummy463[2]; /* */ +/* end of struct st_gpio_from_pbdc1 */ +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC11; /* PBDC11 */ + volatile uint8_t dummy4640[2]; /* */ +/* end of struct st_gpio_from_pbdc1 */ + volatile uint8_t dummy4641[212]; /* */ +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC1; /* PIPC1 */ + volatile uint8_t dummy465[2]; /* */ +/* end of struct st_gpio_from_pipc1 */ +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC2; /* PIPC2 */ + volatile uint8_t dummy466[2]; /* */ +/* end of struct st_gpio_from_pipc1 */ +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC3; /* PIPC3 */ + volatile uint8_t dummy467[2]; /* */ +/* end of struct st_gpio_from_pipc1 */ +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC4; /* PIPC4 */ + volatile uint8_t dummy468[2]; /* */ +/* end of struct st_gpio_from_pipc1 */ +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC5; /* PIPC5 */ + volatile uint8_t dummy469[2]; /* */ +/* end of struct st_gpio_from_pipc1 */ +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC6; /* PIPC6 */ + volatile uint8_t dummy470[2]; /* */ +/* end of struct st_gpio_from_pipc1 */ +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC7; /* PIPC7 */ + volatile uint8_t dummy471[2]; /* */ +/* end of struct st_gpio_from_pipc1 */ +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC8; /* PIPC8 */ + volatile uint8_t dummy472[2]; /* */ +/* end of struct st_gpio_from_pipc1 */ +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC9; /* PIPC9 */ + volatile uint8_t dummy473[2]; /* */ +/* end of struct st_gpio_from_pipc1 */ +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC10; /* PIPC10 */ + volatile uint8_t dummy474[2]; /* */ +/* end of struct st_gpio_from_pipc1 */ +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC11; /* PIPC11 */ + volatile uint8_t dummy4750[2]; /* */ +/* end of struct st_gpio_from_pipc1 */ + volatile uint8_t dummy4751[2288]; /* */ + volatile uint16_t JPPR0; /* JPPR0 */ + volatile uint8_t dummy476[30]; /* */ + volatile uint16_t JPMC0; /* JPMC0 */ + volatile uint8_t dummy477[78]; /* */ + volatile uint32_t JPMCSR0; /* JPMCSR0 */ + volatile uint8_t dummy478[876]; /* */ + volatile uint16_t JPIBC0; /* JPIBC0 */ +}; + + +struct st_gpio_from_p1 +{ + volatile uint16_t P1; /* P1 */ + volatile uint8_t dummy1[3]; /* */ +}; + + +struct st_gpio_from_ppr0 +{ + volatile uint16_t PPR0; /* PPR0 */ + volatile uint8_t dummy1[2]; /* */ +}; + + +struct st_gpio_from_pm1 +{ + volatile uint16_t PM1; /* PM1 */ + volatile uint8_t dummy1[2]; /* */ +}; + + +struct st_gpio_from_pmc0 +{ + volatile uint16_t PMC0; /* PMC0 */ + volatile uint8_t dummy1[2]; /* */ +}; + + +struct st_gpio_from_pfc1 +{ + volatile uint16_t PFC1; /* PFC1 */ + volatile uint8_t dummy1[2]; /* */ +}; + + +struct st_gpio_from_pfce1 +{ + volatile uint16_t PFCE1; /* PFCE1 */ + volatile uint8_t dummy1[2]; /* */ +}; + + +struct st_gpio_from_pnot1 +{ + volatile uint16_t PNOT1; /* PNOT1 */ + volatile uint8_t dummy1[2]; /* */ +}; + + +struct st_gpio_from_pfcae1 +{ + volatile uint16_t PFCAE1; /* PFCAE1 */ + volatile uint8_t dummy1[2]; /* */ +}; + + +struct st_gpio_from_pibc1 +{ + volatile uint16_t PIBC1; /* PIBC1 */ + volatile uint8_t dummy1[2]; /* */ +}; + + +struct st_gpio_from_pbdc1 +{ + volatile uint16_t PBDC1; /* PBDC1 */ + volatile uint8_t dummy1[2]; /* */ +}; + + +struct st_gpio_from_pipc1 +{ + volatile uint16_t PIPC1; /* PIPC1 */ + volatile uint8_t dummy1[2]; /* */ +}; + + +#define GPIO (*(struct st_gpio *)0xFCFE3004uL) /* GPIO */ + +/* Start of channnel array defines of GPIO */ + +/* Channnel array defines of GPIO_FROM_PIPC1_ARRAY */ +/*(Sample) value = GPIO_FROM_PIPC1_ARRAY[ channel ]->PIPC1; */ +#define GPIO_FROM_PIPC1_ARRAY_COUNT 11 +#define GPIO_FROM_PIPC1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PIPC1, &GPIO_FROM_PIPC2, &GPIO_FROM_PIPC3, &GPIO_FROM_PIPC4, &GPIO_FROM_PIPC5, &GPIO_FROM_PIPC6, &GPIO_FROM_PIPC7, &GPIO_FROM_PIPC8, \ + &GPIO_FROM_PIPC9, &GPIO_FROM_PIPC10, &GPIO_FROM_PIPC11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PIPC1 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC1) /* GPIO_FROM_PIPC1 */ +#define GPIO_FROM_PIPC2 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC2) /* GPIO_FROM_PIPC2 */ +#define GPIO_FROM_PIPC3 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC3) /* GPIO_FROM_PIPC3 */ +#define GPIO_FROM_PIPC4 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC4) /* GPIO_FROM_PIPC4 */ +#define GPIO_FROM_PIPC5 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC5) /* GPIO_FROM_PIPC5 */ +#define GPIO_FROM_PIPC6 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC6) /* GPIO_FROM_PIPC6 */ +#define GPIO_FROM_PIPC7 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC7) /* GPIO_FROM_PIPC7 */ +#define GPIO_FROM_PIPC8 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC8) /* GPIO_FROM_PIPC8 */ +#define GPIO_FROM_PIPC9 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC9) /* GPIO_FROM_PIPC9 */ +#define GPIO_FROM_PIPC10 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC10) /* GPIO_FROM_PIPC10 */ +#define GPIO_FROM_PIPC11 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC11) /* GPIO_FROM_PIPC11 */ + + +/* Channnel array defines of GPIO_FROM_PBDC1_ARRAY */ +/*(Sample) value = GPIO_FROM_PBDC1_ARRAY[ channel ]->PBDC1; */ +#define GPIO_FROM_PBDC1_ARRAY_COUNT 11 +#define GPIO_FROM_PBDC1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PBDC1, &GPIO_FROM_PBDC2, &GPIO_FROM_PBDC3, &GPIO_FROM_PBDC4, &GPIO_FROM_PBDC5, &GPIO_FROM_PBDC6, &GPIO_FROM_PBDC7, &GPIO_FROM_PBDC8, \ + &GPIO_FROM_PBDC9, &GPIO_FROM_PBDC10, &GPIO_FROM_PBDC11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PBDC1 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC1) /* GPIO_FROM_PBDC1 */ +#define GPIO_FROM_PBDC2 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC2) /* GPIO_FROM_PBDC2 */ +#define GPIO_FROM_PBDC3 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC3) /* GPIO_FROM_PBDC3 */ +#define GPIO_FROM_PBDC4 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC4) /* GPIO_FROM_PBDC4 */ +#define GPIO_FROM_PBDC5 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC5) /* GPIO_FROM_PBDC5 */ +#define GPIO_FROM_PBDC6 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC6) /* GPIO_FROM_PBDC6 */ +#define GPIO_FROM_PBDC7 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC7) /* GPIO_FROM_PBDC7 */ +#define GPIO_FROM_PBDC8 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC8) /* GPIO_FROM_PBDC8 */ +#define GPIO_FROM_PBDC9 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC9) /* GPIO_FROM_PBDC9 */ +#define GPIO_FROM_PBDC10 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC10) /* GPIO_FROM_PBDC10 */ +#define GPIO_FROM_PBDC11 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC11) /* GPIO_FROM_PBDC11 */ + + +/* Channnel array defines of GPIO_FROM_PIBC1_ARRAY */ +/*(Sample) value = GPIO_FROM_PIBC1_ARRAY[ channel ]->PIBC1; */ +#define GPIO_FROM_PIBC1_ARRAY_COUNT 11 +#define GPIO_FROM_PIBC1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PIBC1, &GPIO_FROM_PIBC2, &GPIO_FROM_PIBC3, &GPIO_FROM_PIBC4, &GPIO_FROM_PIBC5, &GPIO_FROM_PIBC6, &GPIO_FROM_PIBC7, &GPIO_FROM_PIBC8, \ + &GPIO_FROM_PIBC9, &GPIO_FROM_PIBC10, &GPIO_FROM_PIBC11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PIBC1 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC1) /* GPIO_FROM_PIBC1 */ +#define GPIO_FROM_PIBC2 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC2) /* GPIO_FROM_PIBC2 */ +#define GPIO_FROM_PIBC3 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC3) /* GPIO_FROM_PIBC3 */ +#define GPIO_FROM_PIBC4 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC4) /* GPIO_FROM_PIBC4 */ +#define GPIO_FROM_PIBC5 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC5) /* GPIO_FROM_PIBC5 */ +#define GPIO_FROM_PIBC6 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC6) /* GPIO_FROM_PIBC6 */ +#define GPIO_FROM_PIBC7 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC7) /* GPIO_FROM_PIBC7 */ +#define GPIO_FROM_PIBC8 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC8) /* GPIO_FROM_PIBC8 */ +#define GPIO_FROM_PIBC9 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC9) /* GPIO_FROM_PIBC9 */ +#define GPIO_FROM_PIBC10 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC10) /* GPIO_FROM_PIBC10 */ +#define GPIO_FROM_PIBC11 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC11) /* GPIO_FROM_PIBC11 */ + + +/* Channnel array defines of GPIO_FROM_PFCAE1_ARRAY */ +/*(Sample) value = GPIO_FROM_PFCAE1_ARRAY[ channel ]->PFCAE1; */ +#define GPIO_FROM_PFCAE1_ARRAY_COUNT 11 +#define GPIO_FROM_PFCAE1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PFCAE1, &GPIO_FROM_PFCAE2, &GPIO_FROM_PFCAE3, &GPIO_FROM_PFCAE4, &GPIO_FROM_PFCAE5, &GPIO_FROM_PFCAE6, &GPIO_FROM_PFCAE7, &GPIO_FROM_PFCAE8, \ + &GPIO_FROM_PFCAE9, &GPIO_FROM_PFCAE10, &GPIO_FROM_PFCAE11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PFCAE1 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE1) /* GPIO_FROM_PFCAE1 */ +#define GPIO_FROM_PFCAE2 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE2) /* GPIO_FROM_PFCAE2 */ +#define GPIO_FROM_PFCAE3 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE3) /* GPIO_FROM_PFCAE3 */ +#define GPIO_FROM_PFCAE4 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE4) /* GPIO_FROM_PFCAE4 */ +#define GPIO_FROM_PFCAE5 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE5) /* GPIO_FROM_PFCAE5 */ +#define GPIO_FROM_PFCAE6 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE6) /* GPIO_FROM_PFCAE6 */ +#define GPIO_FROM_PFCAE7 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE7) /* GPIO_FROM_PFCAE7 */ +#define GPIO_FROM_PFCAE8 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE8) /* GPIO_FROM_PFCAE8 */ +#define GPIO_FROM_PFCAE9 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE9) /* GPIO_FROM_PFCAE9 */ +#define GPIO_FROM_PFCAE10 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE10) /* GPIO_FROM_PFCAE10 */ +#define GPIO_FROM_PFCAE11 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE11) /* GPIO_FROM_PFCAE11 */ + + +/* Channnel array defines of GPIO_FROM_PNOT1_ARRAY */ +/*(Sample) value = GPIO_FROM_PNOT1_ARRAY[ channel ]->PNOT1; */ +#define GPIO_FROM_PNOT1_ARRAY_COUNT 11 +#define GPIO_FROM_PNOT1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PNOT1, &GPIO_FROM_PNOT2, &GPIO_FROM_PNOT3, &GPIO_FROM_PNOT4, &GPIO_FROM_PNOT5, &GPIO_FROM_PNOT6, &GPIO_FROM_PNOT7, &GPIO_FROM_PNOT8, \ + &GPIO_FROM_PNOT9, &GPIO_FROM_PNOT10, &GPIO_FROM_PNOT11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PNOT1 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT1) /* GPIO_FROM_PNOT1 */ +#define GPIO_FROM_PNOT2 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT2) /* GPIO_FROM_PNOT2 */ +#define GPIO_FROM_PNOT3 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT3) /* GPIO_FROM_PNOT3 */ +#define GPIO_FROM_PNOT4 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT4) /* GPIO_FROM_PNOT4 */ +#define GPIO_FROM_PNOT5 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT5) /* GPIO_FROM_PNOT5 */ +#define GPIO_FROM_PNOT6 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT6) /* GPIO_FROM_PNOT6 */ +#define GPIO_FROM_PNOT7 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT7) /* GPIO_FROM_PNOT7 */ +#define GPIO_FROM_PNOT8 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT8) /* GPIO_FROM_PNOT8 */ +#define GPIO_FROM_PNOT9 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT9) /* GPIO_FROM_PNOT9 */ +#define GPIO_FROM_PNOT10 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT10) /* GPIO_FROM_PNOT10 */ +#define GPIO_FROM_PNOT11 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT11) /* GPIO_FROM_PNOT11 */ + + +/* Channnel array defines of GPIO_FROM_PFCE1_ARRAY */ +/*(Sample) value = GPIO_FROM_PFCE1_ARRAY[ channel ]->PFCE1; */ +#define GPIO_FROM_PFCE1_ARRAY_COUNT 11 +#define GPIO_FROM_PFCE1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PFCE1, &GPIO_FROM_PFCE2, &GPIO_FROM_PFCE3, &GPIO_FROM_PFCE4, &GPIO_FROM_PFCE5, &GPIO_FROM_PFCE6, &GPIO_FROM_PFCE7, &GPIO_FROM_PFCE8, \ + &GPIO_FROM_PFCE9, &GPIO_FROM_PFCE10, &GPIO_FROM_PFCE11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PFCE1 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE1) /* GPIO_FROM_PFCE1 */ +#define GPIO_FROM_PFCE2 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE2) /* GPIO_FROM_PFCE2 */ +#define GPIO_FROM_PFCE3 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE3) /* GPIO_FROM_PFCE3 */ +#define GPIO_FROM_PFCE4 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE4) /* GPIO_FROM_PFCE4 */ +#define GPIO_FROM_PFCE5 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE5) /* GPIO_FROM_PFCE5 */ +#define GPIO_FROM_PFCE6 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE6) /* GPIO_FROM_PFCE6 */ +#define GPIO_FROM_PFCE7 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE7) /* GPIO_FROM_PFCE7 */ +#define GPIO_FROM_PFCE8 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE8) /* GPIO_FROM_PFCE8 */ +#define GPIO_FROM_PFCE9 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE9) /* GPIO_FROM_PFCE9 */ +#define GPIO_FROM_PFCE10 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE10) /* GPIO_FROM_PFCE10 */ +#define GPIO_FROM_PFCE11 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE11) /* GPIO_FROM_PFCE11 */ + + +/* Channnel array defines of GPIO_FROM_PFC1_ARRAY */ +/*(Sample) value = GPIO_FROM_PFC1_ARRAY[ channel ]->PFC1; */ +#define GPIO_FROM_PFC1_ARRAY_COUNT 11 +#define GPIO_FROM_PFC1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PFC1, &GPIO_FROM_PFC2, &GPIO_FROM_PFC3, &GPIO_FROM_PFC4, &GPIO_FROM_PFC5, &GPIO_FROM_PFC6, &GPIO_FROM_PFC7, &GPIO_FROM_PFC8, \ + &GPIO_FROM_PFC9, &GPIO_FROM_PFC10, &GPIO_FROM_PFC11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PFC1 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC1) /* GPIO_FROM_PFC1 */ +#define GPIO_FROM_PFC2 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC2) /* GPIO_FROM_PFC2 */ +#define GPIO_FROM_PFC3 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC3) /* GPIO_FROM_PFC3 */ +#define GPIO_FROM_PFC4 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC4) /* GPIO_FROM_PFC4 */ +#define GPIO_FROM_PFC5 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC5) /* GPIO_FROM_PFC5 */ +#define GPIO_FROM_PFC6 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC6) /* GPIO_FROM_PFC6 */ +#define GPIO_FROM_PFC7 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC7) /* GPIO_FROM_PFC7 */ +#define GPIO_FROM_PFC8 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC8) /* GPIO_FROM_PFC8 */ +#define GPIO_FROM_PFC9 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC9) /* GPIO_FROM_PFC9 */ +#define GPIO_FROM_PFC10 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC10) /* GPIO_FROM_PFC10 */ +#define GPIO_FROM_PFC11 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC11) /* GPIO_FROM_PFC11 */ + + +/* Channnel array defines of GPIO_FROM_PMC0_ARRAY */ +/*(Sample) value = GPIO_FROM_PMC0_ARRAY[ channel ]->PMC0; */ +#define GPIO_FROM_PMC0_ARRAY_COUNT 12 +#define GPIO_FROM_PMC0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PMC0, &GPIO_FROM_PMC1, &GPIO_FROM_PMC2, &GPIO_FROM_PMC3, &GPIO_FROM_PMC4, &GPIO_FROM_PMC5, &GPIO_FROM_PMC6, &GPIO_FROM_PMC7, \ + &GPIO_FROM_PMC8, &GPIO_FROM_PMC9, &GPIO_FROM_PMC10, &GPIO_FROM_PMC11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PMC0 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC0) /* GPIO_FROM_PMC0 */ +#define GPIO_FROM_PMC1 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC1) /* GPIO_FROM_PMC1 */ +#define GPIO_FROM_PMC2 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC2) /* GPIO_FROM_PMC2 */ +#define GPIO_FROM_PMC3 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC3) /* GPIO_FROM_PMC3 */ +#define GPIO_FROM_PMC4 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC4) /* GPIO_FROM_PMC4 */ +#define GPIO_FROM_PMC5 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC5) /* GPIO_FROM_PMC5 */ +#define GPIO_FROM_PMC6 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC6) /* GPIO_FROM_PMC6 */ +#define GPIO_FROM_PMC7 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC7) /* GPIO_FROM_PMC7 */ +#define GPIO_FROM_PMC8 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC8) /* GPIO_FROM_PMC8 */ +#define GPIO_FROM_PMC9 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC9) /* GPIO_FROM_PMC9 */ +#define GPIO_FROM_PMC10 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC10) /* GPIO_FROM_PMC10 */ +#define GPIO_FROM_PMC11 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC11) /* GPIO_FROM_PMC11 */ + + +/* Channnel array defines of GPIO_FROM_PM1_ARRAY */ +/*(Sample) value = GPIO_FROM_PM1_ARRAY[ channel ]->PM1; */ +#define GPIO_FROM_PM1_ARRAY_COUNT 11 +#define GPIO_FROM_PM1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PM1, &GPIO_FROM_PM2, &GPIO_FROM_PM3, &GPIO_FROM_PM4, &GPIO_FROM_PM5, &GPIO_FROM_PM6, &GPIO_FROM_PM7, &GPIO_FROM_PM8, \ + &GPIO_FROM_PM9, &GPIO_FROM_PM10, &GPIO_FROM_PM11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PM1 (*(struct st_gpio_from_pm1 *)&GPIO.PM1) /* GPIO_FROM_PM1 */ +#define GPIO_FROM_PM2 (*(struct st_gpio_from_pm1 *)&GPIO.PM2) /* GPIO_FROM_PM2 */ +#define GPIO_FROM_PM3 (*(struct st_gpio_from_pm1 *)&GPIO.PM3) /* GPIO_FROM_PM3 */ +#define GPIO_FROM_PM4 (*(struct st_gpio_from_pm1 *)&GPIO.PM4) /* GPIO_FROM_PM4 */ +#define GPIO_FROM_PM5 (*(struct st_gpio_from_pm1 *)&GPIO.PM5) /* GPIO_FROM_PM5 */ +#define GPIO_FROM_PM6 (*(struct st_gpio_from_pm1 *)&GPIO.PM6) /* GPIO_FROM_PM6 */ +#define GPIO_FROM_PM7 (*(struct st_gpio_from_pm1 *)&GPIO.PM7) /* GPIO_FROM_PM7 */ +#define GPIO_FROM_PM8 (*(struct st_gpio_from_pm1 *)&GPIO.PM8) /* GPIO_FROM_PM8 */ +#define GPIO_FROM_PM9 (*(struct st_gpio_from_pm1 *)&GPIO.PM9) /* GPIO_FROM_PM9 */ +#define GPIO_FROM_PM10 (*(struct st_gpio_from_pm1 *)&GPIO.PM10) /* GPIO_FROM_PM10 */ +#define GPIO_FROM_PM11 (*(struct st_gpio_from_pm1 *)&GPIO.PM11) /* GPIO_FROM_PM11 */ + + +/* Channnel array defines of GPIO_FROM_PPR0_ARRAY */ +/*(Sample) value = GPIO_FROM_PPR0_ARRAY[ channel ]->PPR0; */ +#define GPIO_FROM_PPR0_ARRAY_COUNT 12 +#define GPIO_FROM_PPR0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PPR0, &GPIO_FROM_PPR1, &GPIO_FROM_PPR2, &GPIO_FROM_PPR3, &GPIO_FROM_PPR4, &GPIO_FROM_PPR5, &GPIO_FROM_PPR6, &GPIO_FROM_PPR7, \ + &GPIO_FROM_PPR8, &GPIO_FROM_PPR9, &GPIO_FROM_PPR10, &GPIO_FROM_PPR11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PPR0 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR0) /* GPIO_FROM_PPR0 */ +#define GPIO_FROM_PPR1 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR1) /* GPIO_FROM_PPR1 */ +#define GPIO_FROM_PPR2 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR2) /* GPIO_FROM_PPR2 */ +#define GPIO_FROM_PPR3 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR3) /* GPIO_FROM_PPR3 */ +#define GPIO_FROM_PPR4 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR4) /* GPIO_FROM_PPR4 */ +#define GPIO_FROM_PPR5 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR5) /* GPIO_FROM_PPR5 */ +#define GPIO_FROM_PPR6 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR6) /* GPIO_FROM_PPR6 */ +#define GPIO_FROM_PPR7 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR7) /* GPIO_FROM_PPR7 */ +#define GPIO_FROM_PPR8 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR8) /* GPIO_FROM_PPR8 */ +#define GPIO_FROM_PPR9 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR9) /* GPIO_FROM_PPR9 */ +#define GPIO_FROM_PPR10 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR10) /* GPIO_FROM_PPR10 */ +#define GPIO_FROM_PPR11 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR11) /* GPIO_FROM_PPR11 */ + + +/* Channnel array defines of GPIO_FROM_P1_ARRAY */ +/*(Sample) value = GPIO_FROM_P1_ARRAY[ channel ]->P1; */ +#define GPIO_FROM_P1_ARRAY_COUNT 11 +#define GPIO_FROM_P1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_P1, &GPIO_FROM_P2, &GPIO_FROM_P3, &GPIO_FROM_P4, &GPIO_FROM_P5, &GPIO_FROM_P6, &GPIO_FROM_P7, &GPIO_FROM_P8, \ + &GPIO_FROM_P9, &GPIO_FROM_P10, &GPIO_FROM_P11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_P1 (*(struct st_gpio_from_p1 *)&GPIO.P1) /* GPIO_FROM_P1 */ +#define GPIO_FROM_P2 (*(struct st_gpio_from_p1 *)&GPIO.P2) /* GPIO_FROM_P2 */ +#define GPIO_FROM_P3 (*(struct st_gpio_from_p1 *)&GPIO.P3) /* GPIO_FROM_P3 */ +#define GPIO_FROM_P4 (*(struct st_gpio_from_p1 *)&GPIO.P4) /* GPIO_FROM_P4 */ +#define GPIO_FROM_P5 (*(struct st_gpio_from_p1 *)&GPIO.P5) /* GPIO_FROM_P5 */ +#define GPIO_FROM_P6 (*(struct st_gpio_from_p1 *)&GPIO.P6) /* GPIO_FROM_P6 */ +#define GPIO_FROM_P7 (*(struct st_gpio_from_p1 *)&GPIO.P7) /* GPIO_FROM_P7 */ +#define GPIO_FROM_P8 (*(struct st_gpio_from_p1 *)&GPIO.P8) /* GPIO_FROM_P8 */ +#define GPIO_FROM_P9 (*(struct st_gpio_from_p1 *)&GPIO.P9) /* GPIO_FROM_P9 */ +#define GPIO_FROM_P10 (*(struct st_gpio_from_p1 *)&GPIO.P10) /* GPIO_FROM_P10 */ +#define GPIO_FROM_P11 (*(struct st_gpio_from_p1 *)&GPIO.P11) /* GPIO_FROM_P11 */ + +/* End of channnel array defines of GPIO */ + + +#define GPIOP1 GPIO.P1 +#define GPIOP2 GPIO.P2 +#define GPIOP3 GPIO.P3 +#define GPIOP4 GPIO.P4 +#define GPIOP5 GPIO.P5 +#define GPIOP6 GPIO.P6 +#define GPIOP7 GPIO.P7 +#define GPIOP8 GPIO.P8 +#define GPIOP9 GPIO.P9 +#define GPIOP10 GPIO.P10 +#define GPIOP11 GPIO.P11 +#define GPIOPSR1 GPIO.PSR1 +#define GPIOPSR2 GPIO.PSR2 +#define GPIOPSR3 GPIO.PSR3 +#define GPIOPSR4 GPIO.PSR4 +#define GPIOPSR5 GPIO.PSR5 +#define GPIOPSR6 GPIO.PSR6 +#define GPIOPSR7 GPIO.PSR7 +#define GPIOPSR8 GPIO.PSR8 +#define GPIOPSR9 GPIO.PSR9 +#define GPIOPSR10 GPIO.PSR10 +#define GPIOPSR11 GPIO.PSR11 +#define GPIOPPR0 GPIO.PPR0 +#define GPIOPPR1 GPIO.PPR1 +#define GPIOPPR2 GPIO.PPR2 +#define GPIOPPR3 GPIO.PPR3 +#define GPIOPPR4 GPIO.PPR4 +#define GPIOPPR5 GPIO.PPR5 +#define GPIOPPR6 GPIO.PPR6 +#define GPIOPPR7 GPIO.PPR7 +#define GPIOPPR8 GPIO.PPR8 +#define GPIOPPR9 GPIO.PPR9 +#define GPIOPPR10 GPIO.PPR10 +#define GPIOPPR11 GPIO.PPR11 +#define GPIOPM1 GPIO.PM1 +#define GPIOPM2 GPIO.PM2 +#define GPIOPM3 GPIO.PM3 +#define GPIOPM4 GPIO.PM4 +#define GPIOPM5 GPIO.PM5 +#define GPIOPM6 GPIO.PM6 +#define GPIOPM7 GPIO.PM7 +#define GPIOPM8 GPIO.PM8 +#define GPIOPM9 GPIO.PM9 +#define GPIOPM10 GPIO.PM10 +#define GPIOPM11 GPIO.PM11 +#define GPIOPMC0 GPIO.PMC0 +#define GPIOPMC1 GPIO.PMC1 +#define GPIOPMC2 GPIO.PMC2 +#define GPIOPMC3 GPIO.PMC3 +#define GPIOPMC4 GPIO.PMC4 +#define GPIOPMC5 GPIO.PMC5 +#define GPIOPMC6 GPIO.PMC6 +#define GPIOPMC7 GPIO.PMC7 +#define GPIOPMC8 GPIO.PMC8 +#define GPIOPMC9 GPIO.PMC9 +#define GPIOPMC10 GPIO.PMC10 +#define GPIOPMC11 GPIO.PMC11 +#define GPIOPFC1 GPIO.PFC1 +#define GPIOPFC2 GPIO.PFC2 +#define GPIOPFC3 GPIO.PFC3 +#define GPIOPFC4 GPIO.PFC4 +#define GPIOPFC5 GPIO.PFC5 +#define GPIOPFC6 GPIO.PFC6 +#define GPIOPFC7 GPIO.PFC7 +#define GPIOPFC8 GPIO.PFC8 +#define GPIOPFC9 GPIO.PFC9 +#define GPIOPFC10 GPIO.PFC10 +#define GPIOPFC11 GPIO.PFC11 +#define GPIOPFCE1 GPIO.PFCE1 +#define GPIOPFCE2 GPIO.PFCE2 +#define GPIOPFCE3 GPIO.PFCE3 +#define GPIOPFCE4 GPIO.PFCE4 +#define GPIOPFCE5 GPIO.PFCE5 +#define GPIOPFCE6 GPIO.PFCE6 +#define GPIOPFCE7 GPIO.PFCE7 +#define GPIOPFCE8 GPIO.PFCE8 +#define GPIOPFCE9 GPIO.PFCE9 +#define GPIOPFCE10 GPIO.PFCE10 +#define GPIOPFCE11 GPIO.PFCE11 +#define GPIOPNOT1 GPIO.PNOT1 +#define GPIOPNOT2 GPIO.PNOT2 +#define GPIOPNOT3 GPIO.PNOT3 +#define GPIOPNOT4 GPIO.PNOT4 +#define GPIOPNOT5 GPIO.PNOT5 +#define GPIOPNOT6 GPIO.PNOT6 +#define GPIOPNOT7 GPIO.PNOT7 +#define GPIOPNOT8 GPIO.PNOT8 +#define GPIOPNOT9 GPIO.PNOT9 +#define GPIOPNOT10 GPIO.PNOT10 +#define GPIOPNOT11 GPIO.PNOT11 +#define GPIOPMSR1 GPIO.PMSR1 +#define GPIOPMSR2 GPIO.PMSR2 +#define GPIOPMSR3 GPIO.PMSR3 +#define GPIOPMSR4 GPIO.PMSR4 +#define GPIOPMSR5 GPIO.PMSR5 +#define GPIOPMSR6 GPIO.PMSR6 +#define GPIOPMSR7 GPIO.PMSR7 +#define GPIOPMSR8 GPIO.PMSR8 +#define GPIOPMSR9 GPIO.PMSR9 +#define GPIOPMSR10 GPIO.PMSR10 +#define GPIOPMSR11 GPIO.PMSR11 +#define GPIOPMCSR0 GPIO.PMCSR0 +#define GPIOPMCSR1 GPIO.PMCSR1 +#define GPIOPMCSR2 GPIO.PMCSR2 +#define GPIOPMCSR3 GPIO.PMCSR3 +#define GPIOPMCSR4 GPIO.PMCSR4 +#define GPIOPMCSR5 GPIO.PMCSR5 +#define GPIOPMCSR6 GPIO.PMCSR6 +#define GPIOPMCSR7 GPIO.PMCSR7 +#define GPIOPMCSR8 GPIO.PMCSR8 +#define GPIOPMCSR9 GPIO.PMCSR9 +#define GPIOPMCSR10 GPIO.PMCSR10 +#define GPIOPMCSR11 GPIO.PMCSR11 +#define GPIOPFCAE1 GPIO.PFCAE1 +#define GPIOPFCAE2 GPIO.PFCAE2 +#define GPIOPFCAE3 GPIO.PFCAE3 +#define GPIOPFCAE4 GPIO.PFCAE4 +#define GPIOPFCAE5 GPIO.PFCAE5 +#define GPIOPFCAE6 GPIO.PFCAE6 +#define GPIOPFCAE7 GPIO.PFCAE7 +#define GPIOPFCAE8 GPIO.PFCAE8 +#define GPIOPFCAE9 GPIO.PFCAE9 +#define GPIOPFCAE10 GPIO.PFCAE10 +#define GPIOPFCAE11 GPIO.PFCAE11 +#define GPIOSNCR GPIO.SNCR +#define GPIOPIBC0 GPIO.PIBC0 +#define GPIOPIBC1 GPIO.PIBC1 +#define GPIOPIBC2 GPIO.PIBC2 +#define GPIOPIBC3 GPIO.PIBC3 +#define GPIOPIBC4 GPIO.PIBC4 +#define GPIOPIBC5 GPIO.PIBC5 +#define GPIOPIBC6 GPIO.PIBC6 +#define GPIOPIBC7 GPIO.PIBC7 +#define GPIOPIBC8 GPIO.PIBC8 +#define GPIOPIBC9 GPIO.PIBC9 +#define GPIOPIBC10 GPIO.PIBC10 +#define GPIOPIBC11 GPIO.PIBC11 +#define GPIOPBDC1 GPIO.PBDC1 +#define GPIOPBDC2 GPIO.PBDC2 +#define GPIOPBDC3 GPIO.PBDC3 +#define GPIOPBDC4 GPIO.PBDC4 +#define GPIOPBDC5 GPIO.PBDC5 +#define GPIOPBDC6 GPIO.PBDC6 +#define GPIOPBDC7 GPIO.PBDC7 +#define GPIOPBDC8 GPIO.PBDC8 +#define GPIOPBDC9 GPIO.PBDC9 +#define GPIOPBDC10 GPIO.PBDC10 +#define GPIOPBDC11 GPIO.PBDC11 +#define GPIOPIPC1 GPIO.PIPC1 +#define GPIOPIPC2 GPIO.PIPC2 +#define GPIOPIPC3 GPIO.PIPC3 +#define GPIOPIPC4 GPIO.PIPC4 +#define GPIOPIPC5 GPIO.PIPC5 +#define GPIOPIPC6 GPIO.PIPC6 +#define GPIOPIPC7 GPIO.PIPC7 +#define GPIOPIPC8 GPIO.PIPC8 +#define GPIOPIPC9 GPIO.PIPC9 +#define GPIOPIPC10 GPIO.PIPC10 +#define GPIOPIPC11 GPIO.PIPC11 +#define GPIOJPPR0 GPIO.JPPR0 +#define GPIOJPMC0 GPIO.JPMC0 +#define GPIOJPMCSR0 GPIO.JPMCSR0 +#define GPIOJPIBC0 GPIO.JPIBC0 +/* <-SEC M1.10.1 */ +/* <-QAC 0639 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/ieb_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,119 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : ieb_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef IEB_IODEFINE_H +#define IEB_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_ieb +{ /* IEB */ + volatile uint8_t B0BCR; /* B0BCR */ + volatile uint8_t dummy495[3]; /* */ + volatile uint8_t B0PSR; /* B0PSR */ + volatile uint8_t dummy496[3]; /* */ + volatile uint16_t B0UAR; /* B0UAR */ + volatile uint8_t dummy497[2]; /* */ + volatile uint16_t B0SAR; /* B0SAR */ + volatile uint8_t dummy498[2]; /* */ + volatile uint16_t B0PAR; /* B0PAR */ + volatile uint8_t dummy499[2]; /* */ + volatile uint16_t B0RSA; /* B0RSA */ + volatile uint8_t dummy500[2]; /* */ + volatile uint8_t B0CDR; /* B0CDR */ + volatile uint8_t dummy501[3]; /* */ + volatile uint8_t B0TCD; /* B0TCD */ + volatile uint8_t dummy502[3]; /* */ + volatile uint8_t B0RCD; /* B0RCD */ + volatile uint8_t dummy503[3]; /* */ + volatile uint8_t B0DLR; /* B0DLR */ + volatile uint8_t dummy504[3]; /* */ + volatile uint8_t B0TDL; /* B0TDL */ + volatile uint8_t dummy505[3]; /* */ + volatile uint8_t B0RDL; /* B0RDL */ + volatile uint8_t dummy506[3]; /* */ + volatile uint8_t B0CKS; /* B0CKS */ + volatile uint8_t dummy507[3]; /* */ + volatile uint8_t B0TMS; /* B0TMS */ + volatile uint8_t dummy508[3]; /* */ + volatile uint8_t B0PCR; /* B0PCR */ + volatile uint8_t dummy509[3]; /* */ + volatile uint16_t B0BSR; /* B0BSR */ + volatile uint8_t dummy510[2]; /* */ + volatile uint8_t B0SSR; /* B0SSR */ + volatile uint8_t dummy511[3]; /* */ + volatile uint8_t B0USR; /* B0USR */ + volatile uint8_t dummy512[3]; /* */ + volatile uint8_t B0ISR; /* B0ISR */ + volatile uint8_t dummy513[3]; /* */ + volatile uint8_t B0ESR; /* B0ESR */ + volatile uint8_t dummy514[3]; /* */ + volatile uint8_t B0FSR; /* B0FSR */ + volatile uint8_t dummy515[3]; /* */ + volatile uint8_t B0SCR; /* B0SCR */ + volatile uint8_t dummy516[3]; /* */ + volatile uint8_t B0CCR; /* B0CCR */ + volatile uint8_t dummy517[3]; /* */ + volatile uint8_t B0STC0; /* B0STC0 */ + volatile uint8_t dummy518[3]; /* */ + volatile uint8_t B0STC1; /* B0STC1 */ + volatile uint8_t dummy519[3]; /* */ + volatile uint8_t B0DR; /* B0DR */ +}; + + +#define IEB (*(struct st_ieb *)0xFCFEF000uL) /* IEB */ + + +#define IEBB0BCR IEB.B0BCR +#define IEBB0PSR IEB.B0PSR +#define IEBB0UAR IEB.B0UAR +#define IEBB0SAR IEB.B0SAR +#define IEBB0PAR IEB.B0PAR +#define IEBB0RSA IEB.B0RSA +#define IEBB0CDR IEB.B0CDR +#define IEBB0TCD IEB.B0TCD +#define IEBB0RCD IEB.B0RCD +#define IEBB0DLR IEB.B0DLR +#define IEBB0TDL IEB.B0TDL +#define IEBB0RDL IEB.B0RDL +#define IEBB0CKS IEB.B0CKS +#define IEBB0TMS IEB.B0TMS +#define IEBB0PCR IEB.B0PCR +#define IEBB0BSR IEB.B0BSR +#define IEBB0SSR IEB.B0SSR +#define IEBB0USR IEB.B0USR +#define IEBB0ISR IEB.B0ISR +#define IEBB0ESR IEB.B0ESR +#define IEBB0FSR IEB.B0FSR +#define IEBB0SCR IEB.B0SCR +#define IEBB0CCR IEB.B0CCR +#define IEBB0STC0 IEB.B0STC0 +#define IEBB0STC1 IEB.B0STC1 +#define IEBB0DR IEB.B0DR +/* <-SEC M1.10.1 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/inb_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,92 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : inb_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef INB_IODEFINE_H +#define INB_IODEFINE_H + +struct st_inb +{ /* INB */ + volatile uint32_t RMPR; /* RMPR */ +#define INB_AXIBUSCTLn_COUNT 11 + volatile uint32_t AXIBUSCTL0; /* AXIBUSCTL0 */ + volatile uint32_t AXIBUSCTL1; /* AXIBUSCTL1 */ + volatile uint32_t AXIBUSCTL2; /* AXIBUSCTL2 */ + volatile uint32_t AXIBUSCTL3; /* AXIBUSCTL3 */ + volatile uint32_t AXIBUSCTL4; /* AXIBUSCTL4 */ + volatile uint32_t AXIBUSCTL5; /* AXIBUSCTL5 */ + volatile uint32_t AXIBUSCTL6; /* AXIBUSCTL6 */ + volatile uint32_t AXIBUSCTL7; /* AXIBUSCTL7 */ + volatile uint32_t AXIBUSCTL8; /* AXIBUSCTL8 */ + volatile uint32_t AXIBUSCTL9; /* AXIBUSCTL9 */ + volatile uint32_t AXIBUSCTL10; /* AXIBUSCTL10 */ +#define INB_AXIRERRCTLn_COUNT 4 + volatile uint32_t AXIRERRCTL0; /* AXIRERRCTL0 */ + volatile uint32_t AXIRERRCTL1; /* AXIRERRCTL1 */ + volatile uint32_t AXIRERRCTL2; /* AXIRERRCTL2 */ + volatile uint32_t AXIRERRCTL3; /* AXIRERRCTL3 */ +#define INB_AXIRERRSTn_COUNT 4 + volatile uint32_t AXIRERRST0; /* AXIRERRST0 */ + volatile uint32_t AXIRERRST1; /* AXIRERRST1 */ + volatile uint32_t AXIRERRST2; /* AXIRERRST2 */ + volatile uint32_t AXIRERRST3; /* AXIRERRST3 */ +#define INB_AXIRERRCLRn_COUNT 4 + volatile uint32_t AXIRERRCLR0; /* AXIRERRCLR0 */ + volatile uint32_t AXIRERRCLR1; /* AXIRERRCLR1 */ + volatile uint32_t AXIRERRCLR2; /* AXIRERRCLR2 */ + volatile uint32_t AXIRERRCLR3; /* AXIRERRCLR3 */ +}; + + +#define INB (*(struct st_inb *)0xFCFE1A00uL) /* INB */ + + +#define INBRMPR INB.RMPR +#define INBAXIBUSCTL0 INB.AXIBUSCTL0 +#define INBAXIBUSCTL1 INB.AXIBUSCTL1 +#define INBAXIBUSCTL2 INB.AXIBUSCTL2 +#define INBAXIBUSCTL3 INB.AXIBUSCTL3 +#define INBAXIBUSCTL4 INB.AXIBUSCTL4 +#define INBAXIBUSCTL5 INB.AXIBUSCTL5 +#define INBAXIBUSCTL6 INB.AXIBUSCTL6 +#define INBAXIBUSCTL7 INB.AXIBUSCTL7 +#define INBAXIBUSCTL8 INB.AXIBUSCTL8 +#define INBAXIBUSCTL9 INB.AXIBUSCTL9 +#define INBAXIBUSCTL10 INB.AXIBUSCTL10 +#define INBAXIRERRCTL0 INB.AXIRERRCTL0 +#define INBAXIRERRCTL1 INB.AXIRERRCTL1 +#define INBAXIRERRCTL2 INB.AXIRERRCTL2 +#define INBAXIRERRCTL3 INB.AXIRERRCTL3 +#define INBAXIRERRST0 INB.AXIRERRST0 +#define INBAXIRERRST1 INB.AXIRERRST1 +#define INBAXIRERRST2 INB.AXIRERRST2 +#define INBAXIRERRST3 INB.AXIRERRST3 +#define INBAXIRERRCLR0 INB.AXIRERRCLR0 +#define INBAXIRERRCLR1 INB.AXIRERRCLR1 +#define INBAXIRERRCLR2 INB.AXIRERRCLR2 +#define INBAXIRERRCLR3 INB.AXIRERRCLR3 +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/intc_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,1026 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : intc_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef INTC_IODEFINE_H +#define INTC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->SEC M1.10.1 : Not magic number */ + +struct st_intc +{ /* INTC */ + volatile uint32_t ICDDCR; /* ICDDCR */ + volatile uint32_t ICDICTR; /* ICDICTR */ + volatile uint32_t ICDIIDR; /* ICDIIDR */ + volatile uint8_t dummy193[116]; /* */ +#define INTC_ICDISR0_COUNT 19 + volatile uint32_t ICDISR0; /* ICDISR0 */ + volatile uint32_t ICDISR1; /* ICDISR1 */ + volatile uint32_t ICDISR2; /* ICDISR2 */ + volatile uint32_t ICDISR3; /* ICDISR3 */ + volatile uint32_t ICDISR4; /* ICDISR4 */ + volatile uint32_t ICDISR5; /* ICDISR5 */ + volatile uint32_t ICDISR6; /* ICDISR6 */ + volatile uint32_t ICDISR7; /* ICDISR7 */ + volatile uint32_t ICDISR8; /* ICDISR8 */ + volatile uint32_t ICDISR9; /* ICDISR9 */ + volatile uint32_t ICDISR10; /* ICDISR10 */ + volatile uint32_t ICDISR11; /* ICDISR11 */ + volatile uint32_t ICDISR12; /* ICDISR12 */ + volatile uint32_t ICDISR13; /* ICDISR13 */ + volatile uint32_t ICDISR14; /* ICDISR14 */ + volatile uint32_t ICDISR15; /* ICDISR15 */ + volatile uint32_t ICDISR16; /* ICDISR16 */ + volatile uint32_t ICDISR17; /* ICDISR17 */ + volatile uint32_t ICDISR18; /* ICDISR18 */ + volatile uint8_t dummy194[52]; /* */ +#define INTC_ICDISER0_COUNT 19 + volatile uint32_t ICDISER0; /* ICDISER0 */ + volatile uint32_t ICDISER1; /* ICDISER1 */ + volatile uint32_t ICDISER2; /* ICDISER2 */ + volatile uint32_t ICDISER3; /* ICDISER3 */ + volatile uint32_t ICDISER4; /* ICDISER4 */ + volatile uint32_t ICDISER5; /* ICDISER5 */ + volatile uint32_t ICDISER6; /* ICDISER6 */ + volatile uint32_t ICDISER7; /* ICDISER7 */ + volatile uint32_t ICDISER8; /* ICDISER8 */ + volatile uint32_t ICDISER9; /* ICDISER9 */ + volatile uint32_t ICDISER10; /* ICDISER10 */ + volatile uint32_t ICDISER11; /* ICDISER11 */ + volatile uint32_t ICDISER12; /* ICDISER12 */ + volatile uint32_t ICDISER13; /* ICDISER13 */ + volatile uint32_t ICDISER14; /* ICDISER14 */ + volatile uint32_t ICDISER15; /* ICDISER15 */ + volatile uint32_t ICDISER16; /* ICDISER16 */ + volatile uint32_t ICDISER17; /* ICDISER17 */ + volatile uint32_t ICDISER18; /* ICDISER18 */ + volatile uint8_t dummy195[52]; /* */ +#define INTC_ICDICER0_COUNT 19 + volatile uint32_t ICDICER0; /* ICDICER0 */ + volatile uint32_t ICDICER1; /* ICDICER1 */ + volatile uint32_t ICDICER2; /* ICDICER2 */ + volatile uint32_t ICDICER3; /* ICDICER3 */ + volatile uint32_t ICDICER4; /* ICDICER4 */ + volatile uint32_t ICDICER5; /* ICDICER5 */ + volatile uint32_t ICDICER6; /* ICDICER6 */ + volatile uint32_t ICDICER7; /* ICDICER7 */ + volatile uint32_t ICDICER8; /* ICDICER8 */ + volatile uint32_t ICDICER9; /* ICDICER9 */ + volatile uint32_t ICDICER10; /* ICDICER10 */ + volatile uint32_t ICDICER11; /* ICDICER11 */ + volatile uint32_t ICDICER12; /* ICDICER12 */ + volatile uint32_t ICDICER13; /* ICDICER13 */ + volatile uint32_t ICDICER14; /* ICDICER14 */ + volatile uint32_t ICDICER15; /* ICDICER15 */ + volatile uint32_t ICDICER16; /* ICDICER16 */ + volatile uint32_t ICDICER17; /* ICDICER17 */ + volatile uint32_t ICDICER18; /* ICDICER18 */ + volatile uint8_t dummy196[52]; /* */ +#define INTC_ICDISPR0_COUNT 19 + volatile uint32_t ICDISPR0; /* ICDISPR0 */ + volatile uint32_t ICDISPR1; /* ICDISPR1 */ + volatile uint32_t ICDISPR2; /* ICDISPR2 */ + volatile uint32_t ICDISPR3; /* ICDISPR3 */ + volatile uint32_t ICDISPR4; /* ICDISPR4 */ + volatile uint32_t ICDISPR5; /* ICDISPR5 */ + volatile uint32_t ICDISPR6; /* ICDISPR6 */ + volatile uint32_t ICDISPR7; /* ICDISPR7 */ + volatile uint32_t ICDISPR8; /* ICDISPR8 */ + volatile uint32_t ICDISPR9; /* ICDISPR9 */ + volatile uint32_t ICDISPR10; /* ICDISPR10 */ + volatile uint32_t ICDISPR11; /* ICDISPR11 */ + volatile uint32_t ICDISPR12; /* ICDISPR12 */ + volatile uint32_t ICDISPR13; /* ICDISPR13 */ + volatile uint32_t ICDISPR14; /* ICDISPR14 */ + volatile uint32_t ICDISPR15; /* ICDISPR15 */ + volatile uint32_t ICDISPR16; /* ICDISPR16 */ + volatile uint32_t ICDISPR17; /* ICDISPR17 */ + volatile uint32_t ICDISPR18; /* ICDISPR18 */ + volatile uint8_t dummy197[52]; /* */ +#define INTC_ICDICPR0_COUNT 19 + volatile uint32_t ICDICPR0; /* ICDICPR0 */ + volatile uint32_t ICDICPR1; /* ICDICPR1 */ + volatile uint32_t ICDICPR2; /* ICDICPR2 */ + volatile uint32_t ICDICPR3; /* ICDICPR3 */ + volatile uint32_t ICDICPR4; /* ICDICPR4 */ + volatile uint32_t ICDICPR5; /* ICDICPR5 */ + volatile uint32_t ICDICPR6; /* ICDICPR6 */ + volatile uint32_t ICDICPR7; /* ICDICPR7 */ + volatile uint32_t ICDICPR8; /* ICDICPR8 */ + volatile uint32_t ICDICPR9; /* ICDICPR9 */ + volatile uint32_t ICDICPR10; /* ICDICPR10 */ + volatile uint32_t ICDICPR11; /* ICDICPR11 */ + volatile uint32_t ICDICPR12; /* ICDICPR12 */ + volatile uint32_t ICDICPR13; /* ICDICPR13 */ + volatile uint32_t ICDICPR14; /* ICDICPR14 */ + volatile uint32_t ICDICPR15; /* ICDICPR15 */ + volatile uint32_t ICDICPR16; /* ICDICPR16 */ + volatile uint32_t ICDICPR17; /* ICDICPR17 */ + volatile uint32_t ICDICPR18; /* ICDICPR18 */ + volatile uint8_t dummy198[52]; /* */ +#define INTC_ICDABR0_COUNT 19 + volatile uint32_t ICDABR0; /* ICDABR0 */ + volatile uint32_t ICDABR1; /* ICDABR1 */ + volatile uint32_t ICDABR2; /* ICDABR2 */ + volatile uint32_t ICDABR3; /* ICDABR3 */ + volatile uint32_t ICDABR4; /* ICDABR4 */ + volatile uint32_t ICDABR5; /* ICDABR5 */ + volatile uint32_t ICDABR6; /* ICDABR6 */ + volatile uint32_t ICDABR7; /* ICDABR7 */ + volatile uint32_t ICDABR8; /* ICDABR8 */ + volatile uint32_t ICDABR9; /* ICDABR9 */ + volatile uint32_t ICDABR10; /* ICDABR10 */ + volatile uint32_t ICDABR11; /* ICDABR11 */ + volatile uint32_t ICDABR12; /* ICDABR12 */ + volatile uint32_t ICDABR13; /* ICDABR13 */ + volatile uint32_t ICDABR14; /* ICDABR14 */ + volatile uint32_t ICDABR15; /* ICDABR15 */ + volatile uint32_t ICDABR16; /* ICDABR16 */ + volatile uint32_t ICDABR17; /* ICDABR17 */ + volatile uint32_t ICDABR18; /* ICDABR18 */ + volatile uint8_t dummy199[180]; /* */ +#define INTC_ICDIPR0_COUNT 147 + volatile uint32_t ICDIPR0; /* ICDIPR0 */ + volatile uint32_t ICDIPR1; /* ICDIPR1 */ + volatile uint32_t ICDIPR2; /* ICDIPR2 */ + volatile uint32_t ICDIPR3; /* ICDIPR3 */ + volatile uint32_t ICDIPR4; /* ICDIPR4 */ + volatile uint32_t ICDIPR5; /* ICDIPR5 */ + volatile uint32_t ICDIPR6; /* ICDIPR6 */ + volatile uint32_t ICDIPR7; /* ICDIPR7 */ + volatile uint32_t ICDIPR8; /* ICDIPR8 */ + volatile uint32_t ICDIPR9; /* ICDIPR9 */ + volatile uint32_t ICDIPR10; /* ICDIPR10 */ + volatile uint32_t ICDIPR11; /* ICDIPR11 */ + volatile uint32_t ICDIPR12; /* ICDIPR12 */ + volatile uint32_t ICDIPR13; /* ICDIPR13 */ + volatile uint32_t ICDIPR14; /* ICDIPR14 */ + volatile uint32_t ICDIPR15; /* ICDIPR15 */ + volatile uint32_t ICDIPR16; /* ICDIPR16 */ + volatile uint32_t ICDIPR17; /* ICDIPR17 */ + volatile uint32_t ICDIPR18; /* ICDIPR18 */ + volatile uint32_t ICDIPR19; /* ICDIPR19 */ + volatile uint32_t ICDIPR20; /* ICDIPR20 */ + volatile uint32_t ICDIPR21; /* ICDIPR21 */ + volatile uint32_t ICDIPR22; /* ICDIPR22 */ + volatile uint32_t ICDIPR23; /* ICDIPR23 */ + volatile uint32_t ICDIPR24; /* ICDIPR24 */ + volatile uint32_t ICDIPR25; /* ICDIPR25 */ + volatile uint32_t ICDIPR26; /* ICDIPR26 */ + volatile uint32_t ICDIPR27; /* ICDIPR27 */ + volatile uint32_t ICDIPR28; /* ICDIPR28 */ + volatile uint32_t ICDIPR29; /* ICDIPR29 */ + volatile uint32_t ICDIPR30; /* ICDIPR30 */ + volatile uint32_t ICDIPR31; /* ICDIPR31 */ + volatile uint32_t ICDIPR32; /* ICDIPR32 */ + volatile uint32_t ICDIPR33; /* ICDIPR33 */ + volatile uint32_t ICDIPR34; /* ICDIPR34 */ + volatile uint32_t ICDIPR35; /* ICDIPR35 */ + volatile uint32_t ICDIPR36; /* ICDIPR36 */ + volatile uint32_t ICDIPR37; /* ICDIPR37 */ + volatile uint32_t ICDIPR38; /* ICDIPR38 */ + volatile uint32_t ICDIPR39; /* ICDIPR39 */ + volatile uint32_t ICDIPR40; /* ICDIPR40 */ + volatile uint32_t ICDIPR41; /* ICDIPR41 */ + volatile uint32_t ICDIPR42; /* ICDIPR42 */ + volatile uint32_t ICDIPR43; /* ICDIPR43 */ + volatile uint32_t ICDIPR44; /* ICDIPR44 */ + volatile uint32_t ICDIPR45; /* ICDIPR45 */ + volatile uint32_t ICDIPR46; /* ICDIPR46 */ + volatile uint32_t ICDIPR47; /* ICDIPR47 */ + volatile uint32_t ICDIPR48; /* ICDIPR48 */ + volatile uint32_t ICDIPR49; /* ICDIPR49 */ + volatile uint32_t ICDIPR50; /* ICDIPR50 */ + volatile uint32_t ICDIPR51; /* ICDIPR51 */ + volatile uint32_t ICDIPR52; /* ICDIPR52 */ + volatile uint32_t ICDIPR53; /* ICDIPR53 */ + volatile uint32_t ICDIPR54; /* ICDIPR54 */ + volatile uint32_t ICDIPR55; /* ICDIPR55 */ + volatile uint32_t ICDIPR56; /* ICDIPR56 */ + volatile uint32_t ICDIPR57; /* ICDIPR57 */ + volatile uint32_t ICDIPR58; /* ICDIPR58 */ + volatile uint32_t ICDIPR59; /* ICDIPR59 */ + volatile uint32_t ICDIPR60; /* ICDIPR60 */ + volatile uint32_t ICDIPR61; /* ICDIPR61 */ + volatile uint32_t ICDIPR62; /* ICDIPR62 */ + volatile uint32_t ICDIPR63; /* ICDIPR63 */ + volatile uint32_t ICDIPR64; /* ICDIPR64 */ + volatile uint32_t ICDIPR65; /* ICDIPR65 */ + volatile uint32_t ICDIPR66; /* ICDIPR66 */ + volatile uint32_t ICDIPR67; /* ICDIPR67 */ + volatile uint32_t ICDIPR68; /* ICDIPR68 */ + volatile uint32_t ICDIPR69; /* ICDIPR69 */ + volatile uint32_t ICDIPR70; /* ICDIPR70 */ + volatile uint32_t ICDIPR71; /* ICDIPR71 */ + volatile uint32_t ICDIPR72; /* ICDIPR72 */ + volatile uint32_t ICDIPR73; /* ICDIPR73 */ + volatile uint32_t ICDIPR74; /* ICDIPR74 */ + volatile uint32_t ICDIPR75; /* ICDIPR75 */ + volatile uint32_t ICDIPR76; /* ICDIPR76 */ + volatile uint32_t ICDIPR77; /* ICDIPR77 */ + volatile uint32_t ICDIPR78; /* ICDIPR78 */ + volatile uint32_t ICDIPR79; /* ICDIPR79 */ + volatile uint32_t ICDIPR80; /* ICDIPR80 */ + volatile uint32_t ICDIPR81; /* ICDIPR81 */ + volatile uint32_t ICDIPR82; /* ICDIPR82 */ + volatile uint32_t ICDIPR83; /* ICDIPR83 */ + volatile uint32_t ICDIPR84; /* ICDIPR84 */ + volatile uint32_t ICDIPR85; /* ICDIPR85 */ + volatile uint32_t ICDIPR86; /* ICDIPR86 */ + volatile uint32_t ICDIPR87; /* ICDIPR87 */ + volatile uint32_t ICDIPR88; /* ICDIPR88 */ + volatile uint32_t ICDIPR89; /* ICDIPR89 */ + volatile uint32_t ICDIPR90; /* ICDIPR90 */ + volatile uint32_t ICDIPR91; /* ICDIPR91 */ + volatile uint32_t ICDIPR92; /* ICDIPR92 */ + volatile uint32_t ICDIPR93; /* ICDIPR93 */ + volatile uint32_t ICDIPR94; /* ICDIPR94 */ + volatile uint32_t ICDIPR95; /* ICDIPR95 */ + volatile uint32_t ICDIPR96; /* ICDIPR96 */ + volatile uint32_t ICDIPR97; /* ICDIPR97 */ + volatile uint32_t ICDIPR98; /* ICDIPR98 */ + volatile uint32_t ICDIPR99; /* ICDIPR99 */ + volatile uint32_t ICDIPR100; /* ICDIPR100 */ + volatile uint32_t ICDIPR101; /* ICDIPR101 */ + volatile uint32_t ICDIPR102; /* ICDIPR102 */ + volatile uint32_t ICDIPR103; /* ICDIPR103 */ + volatile uint32_t ICDIPR104; /* ICDIPR104 */ + volatile uint32_t ICDIPR105; /* ICDIPR105 */ + volatile uint32_t ICDIPR106; /* ICDIPR106 */ + volatile uint32_t ICDIPR107; /* ICDIPR107 */ + volatile uint32_t ICDIPR108; /* ICDIPR108 */ + volatile uint32_t ICDIPR109; /* ICDIPR109 */ + volatile uint32_t ICDIPR110; /* ICDIPR110 */ + volatile uint32_t ICDIPR111; /* ICDIPR111 */ + volatile uint32_t ICDIPR112; /* ICDIPR112 */ + volatile uint32_t ICDIPR113; /* ICDIPR113 */ + volatile uint32_t ICDIPR114; /* ICDIPR114 */ + volatile uint32_t ICDIPR115; /* ICDIPR115 */ + volatile uint32_t ICDIPR116; /* ICDIPR116 */ + volatile uint32_t ICDIPR117; /* ICDIPR117 */ + volatile uint32_t ICDIPR118; /* ICDIPR118 */ + volatile uint32_t ICDIPR119; /* ICDIPR119 */ + volatile uint32_t ICDIPR120; /* ICDIPR120 */ + volatile uint32_t ICDIPR121; /* ICDIPR121 */ + volatile uint32_t ICDIPR122; /* ICDIPR122 */ + volatile uint32_t ICDIPR123; /* ICDIPR123 */ + volatile uint32_t ICDIPR124; /* ICDIPR124 */ + volatile uint32_t ICDIPR125; /* ICDIPR125 */ + volatile uint32_t ICDIPR126; /* ICDIPR126 */ + volatile uint32_t ICDIPR127; /* ICDIPR127 */ + volatile uint32_t ICDIPR128; /* ICDIPR128 */ + volatile uint32_t ICDIPR129; /* ICDIPR129 */ + volatile uint32_t ICDIPR130; /* ICDIPR130 */ + volatile uint32_t ICDIPR131; /* ICDIPR131 */ + volatile uint32_t ICDIPR132; /* ICDIPR132 */ + volatile uint32_t ICDIPR133; /* ICDIPR133 */ + volatile uint32_t ICDIPR134; /* ICDIPR134 */ + volatile uint32_t ICDIPR135; /* ICDIPR135 */ + volatile uint32_t ICDIPR136; /* ICDIPR136 */ + volatile uint32_t ICDIPR137; /* ICDIPR137 */ + volatile uint32_t ICDIPR138; /* ICDIPR138 */ + volatile uint32_t ICDIPR139; /* ICDIPR139 */ + volatile uint32_t ICDIPR140; /* ICDIPR140 */ + volatile uint32_t ICDIPR141; /* ICDIPR141 */ + volatile uint32_t ICDIPR142; /* ICDIPR142 */ + volatile uint32_t ICDIPR143; /* ICDIPR143 */ + volatile uint32_t ICDIPR144; /* ICDIPR144 */ + volatile uint32_t ICDIPR145; /* ICDIPR145 */ + volatile uint32_t ICDIPR146; /* ICDIPR146 */ + volatile uint8_t dummy200[436]; /* */ +#define INTC_ICDIPTR0_COUNT 147 + volatile uint32_t ICDIPTR0; /* ICDIPTR0 */ + volatile uint32_t ICDIPTR1; /* ICDIPTR1 */ + volatile uint32_t ICDIPTR2; /* ICDIPTR2 */ + volatile uint32_t ICDIPTR3; /* ICDIPTR3 */ + volatile uint32_t ICDIPTR4; /* ICDIPTR4 */ + volatile uint32_t ICDIPTR5; /* ICDIPTR5 */ + volatile uint32_t ICDIPTR6; /* ICDIPTR6 */ + volatile uint32_t ICDIPTR7; /* ICDIPTR7 */ + volatile uint32_t ICDIPTR8; /* ICDIPTR8 */ + volatile uint32_t ICDIPTR9; /* ICDIPTR9 */ + volatile uint32_t ICDIPTR10; /* ICDIPTR10 */ + volatile uint32_t ICDIPTR11; /* ICDIPTR11 */ + volatile uint32_t ICDIPTR12; /* ICDIPTR12 */ + volatile uint32_t ICDIPTR13; /* ICDIPTR13 */ + volatile uint32_t ICDIPTR14; /* ICDIPTR14 */ + volatile uint32_t ICDIPTR15; /* ICDIPTR15 */ + volatile uint32_t ICDIPTR16; /* ICDIPTR16 */ + volatile uint32_t ICDIPTR17; /* ICDIPTR17 */ + volatile uint32_t ICDIPTR18; /* ICDIPTR18 */ + volatile uint32_t ICDIPTR19; /* ICDIPTR19 */ + volatile uint32_t ICDIPTR20; /* ICDIPTR20 */ + volatile uint32_t ICDIPTR21; /* ICDIPTR21 */ + volatile uint32_t ICDIPTR22; /* ICDIPTR22 */ + volatile uint32_t ICDIPTR23; /* ICDIPTR23 */ + volatile uint32_t ICDIPTR24; /* ICDIPTR24 */ + volatile uint32_t ICDIPTR25; /* ICDIPTR25 */ + volatile uint32_t ICDIPTR26; /* ICDIPTR26 */ + volatile uint32_t ICDIPTR27; /* ICDIPTR27 */ + volatile uint32_t ICDIPTR28; /* ICDIPTR28 */ + volatile uint32_t ICDIPTR29; /* ICDIPTR29 */ + volatile uint32_t ICDIPTR30; /* ICDIPTR30 */ + volatile uint32_t ICDIPTR31; /* ICDIPTR31 */ + volatile uint32_t ICDIPTR32; /* ICDIPTR32 */ + volatile uint32_t ICDIPTR33; /* ICDIPTR33 */ + volatile uint32_t ICDIPTR34; /* ICDIPTR34 */ + volatile uint32_t ICDIPTR35; /* ICDIPTR35 */ + volatile uint32_t ICDIPTR36; /* ICDIPTR36 */ + volatile uint32_t ICDIPTR37; /* ICDIPTR37 */ + volatile uint32_t ICDIPTR38; /* ICDIPTR38 */ + volatile uint32_t ICDIPTR39; /* ICDIPTR39 */ + volatile uint32_t ICDIPTR40; /* ICDIPTR40 */ + volatile uint32_t ICDIPTR41; /* ICDIPTR41 */ + volatile uint32_t ICDIPTR42; /* ICDIPTR42 */ + volatile uint32_t ICDIPTR43; /* ICDIPTR43 */ + volatile uint32_t ICDIPTR44; /* ICDIPTR44 */ + volatile uint32_t ICDIPTR45; /* ICDIPTR45 */ + volatile uint32_t ICDIPTR46; /* ICDIPTR46 */ + volatile uint32_t ICDIPTR47; /* ICDIPTR47 */ + volatile uint32_t ICDIPTR48; /* ICDIPTR48 */ + volatile uint32_t ICDIPTR49; /* ICDIPTR49 */ + volatile uint32_t ICDIPTR50; /* ICDIPTR50 */ + volatile uint32_t ICDIPTR51; /* ICDIPTR51 */ + volatile uint32_t ICDIPTR52; /* ICDIPTR52 */ + volatile uint32_t ICDIPTR53; /* ICDIPTR53 */ + volatile uint32_t ICDIPTR54; /* ICDIPTR54 */ + volatile uint32_t ICDIPTR55; /* ICDIPTR55 */ + volatile uint32_t ICDIPTR56; /* ICDIPTR56 */ + volatile uint32_t ICDIPTR57; /* ICDIPTR57 */ + volatile uint32_t ICDIPTR58; /* ICDIPTR58 */ + volatile uint32_t ICDIPTR59; /* ICDIPTR59 */ + volatile uint32_t ICDIPTR60; /* ICDIPTR60 */ + volatile uint32_t ICDIPTR61; /* ICDIPTR61 */ + volatile uint32_t ICDIPTR62; /* ICDIPTR62 */ + volatile uint32_t ICDIPTR63; /* ICDIPTR63 */ + volatile uint32_t ICDIPTR64; /* ICDIPTR64 */ + volatile uint32_t ICDIPTR65; /* ICDIPTR65 */ + volatile uint32_t ICDIPTR66; /* ICDIPTR66 */ + volatile uint32_t ICDIPTR67; /* ICDIPTR67 */ + volatile uint32_t ICDIPTR68; /* ICDIPTR68 */ + volatile uint32_t ICDIPTR69; /* ICDIPTR69 */ + volatile uint32_t ICDIPTR70; /* ICDIPTR70 */ + volatile uint32_t ICDIPTR71; /* ICDIPTR71 */ + volatile uint32_t ICDIPTR72; /* ICDIPTR72 */ + volatile uint32_t ICDIPTR73; /* ICDIPTR73 */ + volatile uint32_t ICDIPTR74; /* ICDIPTR74 */ + volatile uint32_t ICDIPTR75; /* ICDIPTR75 */ + volatile uint32_t ICDIPTR76; /* ICDIPTR76 */ + volatile uint32_t ICDIPTR77; /* ICDIPTR77 */ + volatile uint32_t ICDIPTR78; /* ICDIPTR78 */ + volatile uint32_t ICDIPTR79; /* ICDIPTR79 */ + volatile uint32_t ICDIPTR80; /* ICDIPTR80 */ + volatile uint32_t ICDIPTR81; /* ICDIPTR81 */ + volatile uint32_t ICDIPTR82; /* ICDIPTR82 */ + volatile uint32_t ICDIPTR83; /* ICDIPTR83 */ + volatile uint32_t ICDIPTR84; /* ICDIPTR84 */ + volatile uint32_t ICDIPTR85; /* ICDIPTR85 */ + volatile uint32_t ICDIPTR86; /* ICDIPTR86 */ + volatile uint32_t ICDIPTR87; /* ICDIPTR87 */ + volatile uint32_t ICDIPTR88; /* ICDIPTR88 */ + volatile uint32_t ICDIPTR89; /* ICDIPTR89 */ + volatile uint32_t ICDIPTR90; /* ICDIPTR90 */ + volatile uint32_t ICDIPTR91; /* ICDIPTR91 */ + volatile uint32_t ICDIPTR92; /* ICDIPTR92 */ + volatile uint32_t ICDIPTR93; /* ICDIPTR93 */ + volatile uint32_t ICDIPTR94; /* ICDIPTR94 */ + volatile uint32_t ICDIPTR95; /* ICDIPTR95 */ + volatile uint32_t ICDIPTR96; /* ICDIPTR96 */ + volatile uint32_t ICDIPTR97; /* ICDIPTR97 */ + volatile uint32_t ICDIPTR98; /* ICDIPTR98 */ + volatile uint32_t ICDIPTR99; /* ICDIPTR99 */ + volatile uint32_t ICDIPTR100; /* ICDIPTR100 */ + volatile uint32_t ICDIPTR101; /* ICDIPTR101 */ + volatile uint32_t ICDIPTR102; /* ICDIPTR102 */ + volatile uint32_t ICDIPTR103; /* ICDIPTR103 */ + volatile uint32_t ICDIPTR104; /* ICDIPTR104 */ + volatile uint32_t ICDIPTR105; /* ICDIPTR105 */ + volatile uint32_t ICDIPTR106; /* ICDIPTR106 */ + volatile uint32_t ICDIPTR107; /* ICDIPTR107 */ + volatile uint32_t ICDIPTR108; /* ICDIPTR108 */ + volatile uint32_t ICDIPTR109; /* ICDIPTR109 */ + volatile uint32_t ICDIPTR110; /* ICDIPTR110 */ + volatile uint32_t ICDIPTR111; /* ICDIPTR111 */ + volatile uint32_t ICDIPTR112; /* ICDIPTR112 */ + volatile uint32_t ICDIPTR113; /* ICDIPTR113 */ + volatile uint32_t ICDIPTR114; /* ICDIPTR114 */ + volatile uint32_t ICDIPTR115; /* ICDIPTR115 */ + volatile uint32_t ICDIPTR116; /* ICDIPTR116 */ + volatile uint32_t ICDIPTR117; /* ICDIPTR117 */ + volatile uint32_t ICDIPTR118; /* ICDIPTR118 */ + volatile uint32_t ICDIPTR119; /* ICDIPTR119 */ + volatile uint32_t ICDIPTR120; /* ICDIPTR120 */ + volatile uint32_t ICDIPTR121; /* ICDIPTR121 */ + volatile uint32_t ICDIPTR122; /* ICDIPTR122 */ + volatile uint32_t ICDIPTR123; /* ICDIPTR123 */ + volatile uint32_t ICDIPTR124; /* ICDIPTR124 */ + volatile uint32_t ICDIPTR125; /* ICDIPTR125 */ + volatile uint32_t ICDIPTR126; /* ICDIPTR126 */ + volatile uint32_t ICDIPTR127; /* ICDIPTR127 */ + volatile uint32_t ICDIPTR128; /* ICDIPTR128 */ + volatile uint32_t ICDIPTR129; /* ICDIPTR129 */ + volatile uint32_t ICDIPTR130; /* ICDIPTR130 */ + volatile uint32_t ICDIPTR131; /* ICDIPTR131 */ + volatile uint32_t ICDIPTR132; /* ICDIPTR132 */ + volatile uint32_t ICDIPTR133; /* ICDIPTR133 */ + volatile uint32_t ICDIPTR134; /* ICDIPTR134 */ + volatile uint32_t ICDIPTR135; /* ICDIPTR135 */ + volatile uint32_t ICDIPTR136; /* ICDIPTR136 */ + volatile uint32_t ICDIPTR137; /* ICDIPTR137 */ + volatile uint32_t ICDIPTR138; /* ICDIPTR138 */ + volatile uint32_t ICDIPTR139; /* ICDIPTR139 */ + volatile uint32_t ICDIPTR140; /* ICDIPTR140 */ + volatile uint32_t ICDIPTR141; /* ICDIPTR141 */ + volatile uint32_t ICDIPTR142; /* ICDIPTR142 */ + volatile uint32_t ICDIPTR143; /* ICDIPTR143 */ + volatile uint32_t ICDIPTR144; /* ICDIPTR144 */ + volatile uint32_t ICDIPTR145; /* ICDIPTR145 */ + volatile uint32_t ICDIPTR146; /* ICDIPTR146 */ + volatile uint8_t dummy201[436]; /* */ +#define INTC_ICDICFR0_COUNT 37 + volatile uint32_t ICDICFR0; /* ICDICFR0 */ + volatile uint32_t ICDICFR1; /* ICDICFR1 */ + volatile uint32_t ICDICFR2; /* ICDICFR2 */ + volatile uint32_t ICDICFR3; /* ICDICFR3 */ + volatile uint32_t ICDICFR4; /* ICDICFR4 */ + volatile uint32_t ICDICFR5; /* ICDICFR5 */ + volatile uint32_t ICDICFR6; /* ICDICFR6 */ + volatile uint32_t ICDICFR7; /* ICDICFR7 */ + volatile uint32_t ICDICFR8; /* ICDICFR8 */ + volatile uint32_t ICDICFR9; /* ICDICFR9 */ + volatile uint32_t ICDICFR10; /* ICDICFR10 */ + volatile uint32_t ICDICFR11; /* ICDICFR11 */ + volatile uint32_t ICDICFR12; /* ICDICFR12 */ + volatile uint32_t ICDICFR13; /* ICDICFR13 */ + volatile uint32_t ICDICFR14; /* ICDICFR14 */ + volatile uint32_t ICDICFR15; /* ICDICFR15 */ + volatile uint32_t ICDICFR16; /* ICDICFR16 */ + volatile uint32_t ICDICFR17; /* ICDICFR17 */ + volatile uint32_t ICDICFR18; /* ICDICFR18 */ + volatile uint32_t ICDICFR19; /* ICDICFR19 */ + volatile uint32_t ICDICFR20; /* ICDICFR20 */ + volatile uint32_t ICDICFR21; /* ICDICFR21 */ + volatile uint32_t ICDICFR22; /* ICDICFR22 */ + volatile uint32_t ICDICFR23; /* ICDICFR23 */ + volatile uint32_t ICDICFR24; /* ICDICFR24 */ + volatile uint32_t ICDICFR25; /* ICDICFR25 */ + volatile uint32_t ICDICFR26; /* ICDICFR26 */ + volatile uint32_t ICDICFR27; /* ICDICFR27 */ + volatile uint32_t ICDICFR28; /* ICDICFR28 */ + volatile uint32_t ICDICFR29; /* ICDICFR29 */ + volatile uint32_t ICDICFR30; /* ICDICFR30 */ + volatile uint32_t ICDICFR31; /* ICDICFR31 */ + volatile uint32_t ICDICFR32; /* ICDICFR32 */ + volatile uint32_t ICDICFR33; /* ICDICFR33 */ + volatile uint32_t ICDICFR34; /* ICDICFR34 */ + volatile uint32_t ICDICFR35; /* ICDICFR35 */ + volatile uint32_t ICDICFR36; /* ICDICFR36 */ + volatile uint8_t dummy202[108]; /* */ + volatile uint32_t PPI_STATUS; /* PPI_STATUS */ +#define INTC_SPI_STATUS0_COUNT 17 + volatile uint32_t SPI_STATUS0; /* SPI_STATUS0 */ + volatile uint32_t SPI_STATUS1; /* SPI_STATUS1 */ + volatile uint32_t SPI_STATUS2; /* SPI_STATUS2 */ + volatile uint32_t SPI_STATUS3; /* SPI_STATUS3 */ + volatile uint32_t SPI_STATUS4; /* SPI_STATUS4 */ + volatile uint32_t SPI_STATUS5; /* SPI_STATUS5 */ + volatile uint32_t SPI_STATUS6; /* SPI_STATUS6 */ + volatile uint32_t SPI_STATUS7; /* SPI_STATUS7 */ + volatile uint32_t SPI_STATUS8; /* SPI_STATUS8 */ + volatile uint32_t SPI_STATUS9; /* SPI_STATUS9 */ + volatile uint32_t SPI_STATUS10; /* SPI_STATUS10 */ + volatile uint32_t SPI_STATUS11; /* SPI_STATUS11 */ + volatile uint32_t SPI_STATUS12; /* SPI_STATUS12 */ + volatile uint32_t SPI_STATUS13; /* SPI_STATUS13 */ + volatile uint32_t SPI_STATUS14; /* SPI_STATUS14 */ + volatile uint32_t SPI_STATUS15; /* SPI_STATUS15 */ + volatile uint32_t SPI_STATUS16; /* SPI_STATUS16 */ + volatile uint8_t dummy203[440]; /* */ + volatile uint32_t ICDSGIR; /* ICDSGIR */ + volatile uint8_t dummy204[252]; /* */ + volatile uint32_t ICCICR; /* ICCICR */ + volatile uint32_t ICCPMR; /* ICCPMR */ + volatile uint32_t ICCBPR; /* ICCBPR */ + volatile uint32_t ICCIAR; /* ICCIAR */ + volatile uint32_t ICCEOIR; /* ICCEOIR */ + volatile uint32_t ICCRPR; /* ICCRPR */ + volatile uint32_t ICCHPIR; /* ICCHPIR */ + volatile uint32_t ICCABPR; /* ICCABPR */ + volatile uint8_t dummy205[220]; /* */ + volatile uint32_t ICCIIDR; /* ICCIIDR */ + volatile uint8_t dummy206[350148352]; /* */ + volatile uint16_t ICR0; /* ICR0 */ + volatile uint16_t ICR1; /* ICR1 */ + volatile uint16_t IRQRR; /* IRQRR */ +}; + + +#define INTC (*(struct st_intc *)0xE8201000uL) /* INTC */ + + +#define INTCICDDCR INTC.ICDDCR +#define INTCICDICTR INTC.ICDICTR +#define INTCICDIIDR INTC.ICDIIDR +#define INTCICDISR0 INTC.ICDISR0 +#define INTCICDISR1 INTC.ICDISR1 +#define INTCICDISR2 INTC.ICDISR2 +#define INTCICDISR3 INTC.ICDISR3 +#define INTCICDISR4 INTC.ICDISR4 +#define INTCICDISR5 INTC.ICDISR5 +#define INTCICDISR6 INTC.ICDISR6 +#define INTCICDISR7 INTC.ICDISR7 +#define INTCICDISR8 INTC.ICDISR8 +#define INTCICDISR9 INTC.ICDISR9 +#define INTCICDISR10 INTC.ICDISR10 +#define INTCICDISR11 INTC.ICDISR11 +#define INTCICDISR12 INTC.ICDISR12 +#define INTCICDISR13 INTC.ICDISR13 +#define INTCICDISR14 INTC.ICDISR14 +#define INTCICDISR15 INTC.ICDISR15 +#define INTCICDISR16 INTC.ICDISR16 +#define INTCICDISR17 INTC.ICDISR17 +#define INTCICDISR18 INTC.ICDISR18 +#define INTCICDISER0 INTC.ICDISER0 +#define INTCICDISER1 INTC.ICDISER1 +#define INTCICDISER2 INTC.ICDISER2 +#define INTCICDISER3 INTC.ICDISER3 +#define INTCICDISER4 INTC.ICDISER4 +#define INTCICDISER5 INTC.ICDISER5 +#define INTCICDISER6 INTC.ICDISER6 +#define INTCICDISER7 INTC.ICDISER7 +#define INTCICDISER8 INTC.ICDISER8 +#define INTCICDISER9 INTC.ICDISER9 +#define INTCICDISER10 INTC.ICDISER10 +#define INTCICDISER11 INTC.ICDISER11 +#define INTCICDISER12 INTC.ICDISER12 +#define INTCICDISER13 INTC.ICDISER13 +#define INTCICDISER14 INTC.ICDISER14 +#define INTCICDISER15 INTC.ICDISER15 +#define INTCICDISER16 INTC.ICDISER16 +#define INTCICDISER17 INTC.ICDISER17 +#define INTCICDISER18 INTC.ICDISER18 +#define INTCICDICER0 INTC.ICDICER0 +#define INTCICDICER1 INTC.ICDICER1 +#define INTCICDICER2 INTC.ICDICER2 +#define INTCICDICER3 INTC.ICDICER3 +#define INTCICDICER4 INTC.ICDICER4 +#define INTCICDICER5 INTC.ICDICER5 +#define INTCICDICER6 INTC.ICDICER6 +#define INTCICDICER7 INTC.ICDICER7 +#define INTCICDICER8 INTC.ICDICER8 +#define INTCICDICER9 INTC.ICDICER9 +#define INTCICDICER10 INTC.ICDICER10 +#define INTCICDICER11 INTC.ICDICER11 +#define INTCICDICER12 INTC.ICDICER12 +#define INTCICDICER13 INTC.ICDICER13 +#define INTCICDICER14 INTC.ICDICER14 +#define INTCICDICER15 INTC.ICDICER15 +#define INTCICDICER16 INTC.ICDICER16 +#define INTCICDICER17 INTC.ICDICER17 +#define INTCICDICER18 INTC.ICDICER18 +#define INTCICDISPR0 INTC.ICDISPR0 +#define INTCICDISPR1 INTC.ICDISPR1 +#define INTCICDISPR2 INTC.ICDISPR2 +#define INTCICDISPR3 INTC.ICDISPR3 +#define INTCICDISPR4 INTC.ICDISPR4 +#define INTCICDISPR5 INTC.ICDISPR5 +#define INTCICDISPR6 INTC.ICDISPR6 +#define INTCICDISPR7 INTC.ICDISPR7 +#define INTCICDISPR8 INTC.ICDISPR8 +#define INTCICDISPR9 INTC.ICDISPR9 +#define INTCICDISPR10 INTC.ICDISPR10 +#define INTCICDISPR11 INTC.ICDISPR11 +#define INTCICDISPR12 INTC.ICDISPR12 +#define INTCICDISPR13 INTC.ICDISPR13 +#define INTCICDISPR14 INTC.ICDISPR14 +#define INTCICDISPR15 INTC.ICDISPR15 +#define INTCICDISPR16 INTC.ICDISPR16 +#define INTCICDISPR17 INTC.ICDISPR17 +#define INTCICDISPR18 INTC.ICDISPR18 +#define INTCICDICPR0 INTC.ICDICPR0 +#define INTCICDICPR1 INTC.ICDICPR1 +#define INTCICDICPR2 INTC.ICDICPR2 +#define INTCICDICPR3 INTC.ICDICPR3 +#define INTCICDICPR4 INTC.ICDICPR4 +#define INTCICDICPR5 INTC.ICDICPR5 +#define INTCICDICPR6 INTC.ICDICPR6 +#define INTCICDICPR7 INTC.ICDICPR7 +#define INTCICDICPR8 INTC.ICDICPR8 +#define INTCICDICPR9 INTC.ICDICPR9 +#define INTCICDICPR10 INTC.ICDICPR10 +#define INTCICDICPR11 INTC.ICDICPR11 +#define INTCICDICPR12 INTC.ICDICPR12 +#define INTCICDICPR13 INTC.ICDICPR13 +#define INTCICDICPR14 INTC.ICDICPR14 +#define INTCICDICPR15 INTC.ICDICPR15 +#define INTCICDICPR16 INTC.ICDICPR16 +#define INTCICDICPR17 INTC.ICDICPR17 +#define INTCICDICPR18 INTC.ICDICPR18 +#define INTCICDABR0 INTC.ICDABR0 +#define INTCICDABR1 INTC.ICDABR1 +#define INTCICDABR2 INTC.ICDABR2 +#define INTCICDABR3 INTC.ICDABR3 +#define INTCICDABR4 INTC.ICDABR4 +#define INTCICDABR5 INTC.ICDABR5 +#define INTCICDABR6 INTC.ICDABR6 +#define INTCICDABR7 INTC.ICDABR7 +#define INTCICDABR8 INTC.ICDABR8 +#define INTCICDABR9 INTC.ICDABR9 +#define INTCICDABR10 INTC.ICDABR10 +#define INTCICDABR11 INTC.ICDABR11 +#define INTCICDABR12 INTC.ICDABR12 +#define INTCICDABR13 INTC.ICDABR13 +#define INTCICDABR14 INTC.ICDABR14 +#define INTCICDABR15 INTC.ICDABR15 +#define INTCICDABR16 INTC.ICDABR16 +#define INTCICDABR17 INTC.ICDABR17 +#define INTCICDABR18 INTC.ICDABR18 +#define INTCICDIPR0 INTC.ICDIPR0 +#define INTCICDIPR1 INTC.ICDIPR1 +#define INTCICDIPR2 INTC.ICDIPR2 +#define INTCICDIPR3 INTC.ICDIPR3 +#define INTCICDIPR4 INTC.ICDIPR4 +#define INTCICDIPR5 INTC.ICDIPR5 +#define INTCICDIPR6 INTC.ICDIPR6 +#define INTCICDIPR7 INTC.ICDIPR7 +#define INTCICDIPR8 INTC.ICDIPR8 +#define INTCICDIPR9 INTC.ICDIPR9 +#define INTCICDIPR10 INTC.ICDIPR10 +#define INTCICDIPR11 INTC.ICDIPR11 +#define INTCICDIPR12 INTC.ICDIPR12 +#define INTCICDIPR13 INTC.ICDIPR13 +#define INTCICDIPR14 INTC.ICDIPR14 +#define INTCICDIPR15 INTC.ICDIPR15 +#define INTCICDIPR16 INTC.ICDIPR16 +#define INTCICDIPR17 INTC.ICDIPR17 +#define INTCICDIPR18 INTC.ICDIPR18 +#define INTCICDIPR19 INTC.ICDIPR19 +#define INTCICDIPR20 INTC.ICDIPR20 +#define INTCICDIPR21 INTC.ICDIPR21 +#define INTCICDIPR22 INTC.ICDIPR22 +#define INTCICDIPR23 INTC.ICDIPR23 +#define INTCICDIPR24 INTC.ICDIPR24 +#define INTCICDIPR25 INTC.ICDIPR25 +#define INTCICDIPR26 INTC.ICDIPR26 +#define INTCICDIPR27 INTC.ICDIPR27 +#define INTCICDIPR28 INTC.ICDIPR28 +#define INTCICDIPR29 INTC.ICDIPR29 +#define INTCICDIPR30 INTC.ICDIPR30 +#define INTCICDIPR31 INTC.ICDIPR31 +#define INTCICDIPR32 INTC.ICDIPR32 +#define INTCICDIPR33 INTC.ICDIPR33 +#define INTCICDIPR34 INTC.ICDIPR34 +#define INTCICDIPR35 INTC.ICDIPR35 +#define INTCICDIPR36 INTC.ICDIPR36 +#define INTCICDIPR37 INTC.ICDIPR37 +#define INTCICDIPR38 INTC.ICDIPR38 +#define INTCICDIPR39 INTC.ICDIPR39 +#define INTCICDIPR40 INTC.ICDIPR40 +#define INTCICDIPR41 INTC.ICDIPR41 +#define INTCICDIPR42 INTC.ICDIPR42 +#define INTCICDIPR43 INTC.ICDIPR43 +#define INTCICDIPR44 INTC.ICDIPR44 +#define INTCICDIPR45 INTC.ICDIPR45 +#define INTCICDIPR46 INTC.ICDIPR46 +#define INTCICDIPR47 INTC.ICDIPR47 +#define INTCICDIPR48 INTC.ICDIPR48 +#define INTCICDIPR49 INTC.ICDIPR49 +#define INTCICDIPR50 INTC.ICDIPR50 +#define INTCICDIPR51 INTC.ICDIPR51 +#define INTCICDIPR52 INTC.ICDIPR52 +#define INTCICDIPR53 INTC.ICDIPR53 +#define INTCICDIPR54 INTC.ICDIPR54 +#define INTCICDIPR55 INTC.ICDIPR55 +#define INTCICDIPR56 INTC.ICDIPR56 +#define INTCICDIPR57 INTC.ICDIPR57 +#define INTCICDIPR58 INTC.ICDIPR58 +#define INTCICDIPR59 INTC.ICDIPR59 +#define INTCICDIPR60 INTC.ICDIPR60 +#define INTCICDIPR61 INTC.ICDIPR61 +#define INTCICDIPR62 INTC.ICDIPR62 +#define INTCICDIPR63 INTC.ICDIPR63 +#define INTCICDIPR64 INTC.ICDIPR64 +#define INTCICDIPR65 INTC.ICDIPR65 +#define INTCICDIPR66 INTC.ICDIPR66 +#define INTCICDIPR67 INTC.ICDIPR67 +#define INTCICDIPR68 INTC.ICDIPR68 +#define INTCICDIPR69 INTC.ICDIPR69 +#define INTCICDIPR70 INTC.ICDIPR70 +#define INTCICDIPR71 INTC.ICDIPR71 +#define INTCICDIPR72 INTC.ICDIPR72 +#define INTCICDIPR73 INTC.ICDIPR73 +#define INTCICDIPR74 INTC.ICDIPR74 +#define INTCICDIPR75 INTC.ICDIPR75 +#define INTCICDIPR76 INTC.ICDIPR76 +#define INTCICDIPR77 INTC.ICDIPR77 +#define INTCICDIPR78 INTC.ICDIPR78 +#define INTCICDIPR79 INTC.ICDIPR79 +#define INTCICDIPR80 INTC.ICDIPR80 +#define INTCICDIPR81 INTC.ICDIPR81 +#define INTCICDIPR82 INTC.ICDIPR82 +#define INTCICDIPR83 INTC.ICDIPR83 +#define INTCICDIPR84 INTC.ICDIPR84 +#define INTCICDIPR85 INTC.ICDIPR85 +#define INTCICDIPR86 INTC.ICDIPR86 +#define INTCICDIPR87 INTC.ICDIPR87 +#define INTCICDIPR88 INTC.ICDIPR88 +#define INTCICDIPR89 INTC.ICDIPR89 +#define INTCICDIPR90 INTC.ICDIPR90 +#define INTCICDIPR91 INTC.ICDIPR91 +#define INTCICDIPR92 INTC.ICDIPR92 +#define INTCICDIPR93 INTC.ICDIPR93 +#define INTCICDIPR94 INTC.ICDIPR94 +#define INTCICDIPR95 INTC.ICDIPR95 +#define INTCICDIPR96 INTC.ICDIPR96 +#define INTCICDIPR97 INTC.ICDIPR97 +#define INTCICDIPR98 INTC.ICDIPR98 +#define INTCICDIPR99 INTC.ICDIPR99 +#define INTCICDIPR100 INTC.ICDIPR100 +#define INTCICDIPR101 INTC.ICDIPR101 +#define INTCICDIPR102 INTC.ICDIPR102 +#define INTCICDIPR103 INTC.ICDIPR103 +#define INTCICDIPR104 INTC.ICDIPR104 +#define INTCICDIPR105 INTC.ICDIPR105 +#define INTCICDIPR106 INTC.ICDIPR106 +#define INTCICDIPR107 INTC.ICDIPR107 +#define INTCICDIPR108 INTC.ICDIPR108 +#define INTCICDIPR109 INTC.ICDIPR109 +#define INTCICDIPR110 INTC.ICDIPR110 +#define INTCICDIPR111 INTC.ICDIPR111 +#define INTCICDIPR112 INTC.ICDIPR112 +#define INTCICDIPR113 INTC.ICDIPR113 +#define INTCICDIPR114 INTC.ICDIPR114 +#define INTCICDIPR115 INTC.ICDIPR115 +#define INTCICDIPR116 INTC.ICDIPR116 +#define INTCICDIPR117 INTC.ICDIPR117 +#define INTCICDIPR118 INTC.ICDIPR118 +#define INTCICDIPR119 INTC.ICDIPR119 +#define INTCICDIPR120 INTC.ICDIPR120 +#define INTCICDIPR121 INTC.ICDIPR121 +#define INTCICDIPR122 INTC.ICDIPR122 +#define INTCICDIPR123 INTC.ICDIPR123 +#define INTCICDIPR124 INTC.ICDIPR124 +#define INTCICDIPR125 INTC.ICDIPR125 +#define INTCICDIPR126 INTC.ICDIPR126 +#define INTCICDIPR127 INTC.ICDIPR127 +#define INTCICDIPR128 INTC.ICDIPR128 +#define INTCICDIPR129 INTC.ICDIPR129 +#define INTCICDIPR130 INTC.ICDIPR130 +#define INTCICDIPR131 INTC.ICDIPR131 +#define INTCICDIPR132 INTC.ICDIPR132 +#define INTCICDIPR133 INTC.ICDIPR133 +#define INTCICDIPR134 INTC.ICDIPR134 +#define INTCICDIPR135 INTC.ICDIPR135 +#define INTCICDIPR136 INTC.ICDIPR136 +#define INTCICDIPR137 INTC.ICDIPR137 +#define INTCICDIPR138 INTC.ICDIPR138 +#define INTCICDIPR139 INTC.ICDIPR139 +#define INTCICDIPR140 INTC.ICDIPR140 +#define INTCICDIPR141 INTC.ICDIPR141 +#define INTCICDIPR142 INTC.ICDIPR142 +#define INTCICDIPR143 INTC.ICDIPR143 +#define INTCICDIPR144 INTC.ICDIPR144 +#define INTCICDIPR145 INTC.ICDIPR145 +#define INTCICDIPR146 INTC.ICDIPR146 +#define INTCICDIPTR0 INTC.ICDIPTR0 +#define INTCICDIPTR1 INTC.ICDIPTR1 +#define INTCICDIPTR2 INTC.ICDIPTR2 +#define INTCICDIPTR3 INTC.ICDIPTR3 +#define INTCICDIPTR4 INTC.ICDIPTR4 +#define INTCICDIPTR5 INTC.ICDIPTR5 +#define INTCICDIPTR6 INTC.ICDIPTR6 +#define INTCICDIPTR7 INTC.ICDIPTR7 +#define INTCICDIPTR8 INTC.ICDIPTR8 +#define INTCICDIPTR9 INTC.ICDIPTR9 +#define INTCICDIPTR10 INTC.ICDIPTR10 +#define INTCICDIPTR11 INTC.ICDIPTR11 +#define INTCICDIPTR12 INTC.ICDIPTR12 +#define INTCICDIPTR13 INTC.ICDIPTR13 +#define INTCICDIPTR14 INTC.ICDIPTR14 +#define INTCICDIPTR15 INTC.ICDIPTR15 +#define INTCICDIPTR16 INTC.ICDIPTR16 +#define INTCICDIPTR17 INTC.ICDIPTR17 +#define INTCICDIPTR18 INTC.ICDIPTR18 +#define INTCICDIPTR19 INTC.ICDIPTR19 +#define INTCICDIPTR20 INTC.ICDIPTR20 +#define INTCICDIPTR21 INTC.ICDIPTR21 +#define INTCICDIPTR22 INTC.ICDIPTR22 +#define INTCICDIPTR23 INTC.ICDIPTR23 +#define INTCICDIPTR24 INTC.ICDIPTR24 +#define INTCICDIPTR25 INTC.ICDIPTR25 +#define INTCICDIPTR26 INTC.ICDIPTR26 +#define INTCICDIPTR27 INTC.ICDIPTR27 +#define INTCICDIPTR28 INTC.ICDIPTR28 +#define INTCICDIPTR29 INTC.ICDIPTR29 +#define INTCICDIPTR30 INTC.ICDIPTR30 +#define INTCICDIPTR31 INTC.ICDIPTR31 +#define INTCICDIPTR32 INTC.ICDIPTR32 +#define INTCICDIPTR33 INTC.ICDIPTR33 +#define INTCICDIPTR34 INTC.ICDIPTR34 +#define INTCICDIPTR35 INTC.ICDIPTR35 +#define INTCICDIPTR36 INTC.ICDIPTR36 +#define INTCICDIPTR37 INTC.ICDIPTR37 +#define INTCICDIPTR38 INTC.ICDIPTR38 +#define INTCICDIPTR39 INTC.ICDIPTR39 +#define INTCICDIPTR40 INTC.ICDIPTR40 +#define INTCICDIPTR41 INTC.ICDIPTR41 +#define INTCICDIPTR42 INTC.ICDIPTR42 +#define INTCICDIPTR43 INTC.ICDIPTR43 +#define INTCICDIPTR44 INTC.ICDIPTR44 +#define INTCICDIPTR45 INTC.ICDIPTR45 +#define INTCICDIPTR46 INTC.ICDIPTR46 +#define INTCICDIPTR47 INTC.ICDIPTR47 +#define INTCICDIPTR48 INTC.ICDIPTR48 +#define INTCICDIPTR49 INTC.ICDIPTR49 +#define INTCICDIPTR50 INTC.ICDIPTR50 +#define INTCICDIPTR51 INTC.ICDIPTR51 +#define INTCICDIPTR52 INTC.ICDIPTR52 +#define INTCICDIPTR53 INTC.ICDIPTR53 +#define INTCICDIPTR54 INTC.ICDIPTR54 +#define INTCICDIPTR55 INTC.ICDIPTR55 +#define INTCICDIPTR56 INTC.ICDIPTR56 +#define INTCICDIPTR57 INTC.ICDIPTR57 +#define INTCICDIPTR58 INTC.ICDIPTR58 +#define INTCICDIPTR59 INTC.ICDIPTR59 +#define INTCICDIPTR60 INTC.ICDIPTR60 +#define INTCICDIPTR61 INTC.ICDIPTR61 +#define INTCICDIPTR62 INTC.ICDIPTR62 +#define INTCICDIPTR63 INTC.ICDIPTR63 +#define INTCICDIPTR64 INTC.ICDIPTR64 +#define INTCICDIPTR65 INTC.ICDIPTR65 +#define INTCICDIPTR66 INTC.ICDIPTR66 +#define INTCICDIPTR67 INTC.ICDIPTR67 +#define INTCICDIPTR68 INTC.ICDIPTR68 +#define INTCICDIPTR69 INTC.ICDIPTR69 +#define INTCICDIPTR70 INTC.ICDIPTR70 +#define INTCICDIPTR71 INTC.ICDIPTR71 +#define INTCICDIPTR72 INTC.ICDIPTR72 +#define INTCICDIPTR73 INTC.ICDIPTR73 +#define INTCICDIPTR74 INTC.ICDIPTR74 +#define INTCICDIPTR75 INTC.ICDIPTR75 +#define INTCICDIPTR76 INTC.ICDIPTR76 +#define INTCICDIPTR77 INTC.ICDIPTR77 +#define INTCICDIPTR78 INTC.ICDIPTR78 +#define INTCICDIPTR79 INTC.ICDIPTR79 +#define INTCICDIPTR80 INTC.ICDIPTR80 +#define INTCICDIPTR81 INTC.ICDIPTR81 +#define INTCICDIPTR82 INTC.ICDIPTR82 +#define INTCICDIPTR83 INTC.ICDIPTR83 +#define INTCICDIPTR84 INTC.ICDIPTR84 +#define INTCICDIPTR85 INTC.ICDIPTR85 +#define INTCICDIPTR86 INTC.ICDIPTR86 +#define INTCICDIPTR87 INTC.ICDIPTR87 +#define INTCICDIPTR88 INTC.ICDIPTR88 +#define INTCICDIPTR89 INTC.ICDIPTR89 +#define INTCICDIPTR90 INTC.ICDIPTR90 +#define INTCICDIPTR91 INTC.ICDIPTR91 +#define INTCICDIPTR92 INTC.ICDIPTR92 +#define INTCICDIPTR93 INTC.ICDIPTR93 +#define INTCICDIPTR94 INTC.ICDIPTR94 +#define INTCICDIPTR95 INTC.ICDIPTR95 +#define INTCICDIPTR96 INTC.ICDIPTR96 +#define INTCICDIPTR97 INTC.ICDIPTR97 +#define INTCICDIPTR98 INTC.ICDIPTR98 +#define INTCICDIPTR99 INTC.ICDIPTR99 +#define INTCICDIPTR100 INTC.ICDIPTR100 +#define INTCICDIPTR101 INTC.ICDIPTR101 +#define INTCICDIPTR102 INTC.ICDIPTR102 +#define INTCICDIPTR103 INTC.ICDIPTR103 +#define INTCICDIPTR104 INTC.ICDIPTR104 +#define INTCICDIPTR105 INTC.ICDIPTR105 +#define INTCICDIPTR106 INTC.ICDIPTR106 +#define INTCICDIPTR107 INTC.ICDIPTR107 +#define INTCICDIPTR108 INTC.ICDIPTR108 +#define INTCICDIPTR109 INTC.ICDIPTR109 +#define INTCICDIPTR110 INTC.ICDIPTR110 +#define INTCICDIPTR111 INTC.ICDIPTR111 +#define INTCICDIPTR112 INTC.ICDIPTR112 +#define INTCICDIPTR113 INTC.ICDIPTR113 +#define INTCICDIPTR114 INTC.ICDIPTR114 +#define INTCICDIPTR115 INTC.ICDIPTR115 +#define INTCICDIPTR116 INTC.ICDIPTR116 +#define INTCICDIPTR117 INTC.ICDIPTR117 +#define INTCICDIPTR118 INTC.ICDIPTR118 +#define INTCICDIPTR119 INTC.ICDIPTR119 +#define INTCICDIPTR120 INTC.ICDIPTR120 +#define INTCICDIPTR121 INTC.ICDIPTR121 +#define INTCICDIPTR122 INTC.ICDIPTR122 +#define INTCICDIPTR123 INTC.ICDIPTR123 +#define INTCICDIPTR124 INTC.ICDIPTR124 +#define INTCICDIPTR125 INTC.ICDIPTR125 +#define INTCICDIPTR126 INTC.ICDIPTR126 +#define INTCICDIPTR127 INTC.ICDIPTR127 +#define INTCICDIPTR128 INTC.ICDIPTR128 +#define INTCICDIPTR129 INTC.ICDIPTR129 +#define INTCICDIPTR130 INTC.ICDIPTR130 +#define INTCICDIPTR131 INTC.ICDIPTR131 +#define INTCICDIPTR132 INTC.ICDIPTR132 +#define INTCICDIPTR133 INTC.ICDIPTR133 +#define INTCICDIPTR134 INTC.ICDIPTR134 +#define INTCICDIPTR135 INTC.ICDIPTR135 +#define INTCICDIPTR136 INTC.ICDIPTR136 +#define INTCICDIPTR137 INTC.ICDIPTR137 +#define INTCICDIPTR138 INTC.ICDIPTR138 +#define INTCICDIPTR139 INTC.ICDIPTR139 +#define INTCICDIPTR140 INTC.ICDIPTR140 +#define INTCICDIPTR141 INTC.ICDIPTR141 +#define INTCICDIPTR142 INTC.ICDIPTR142 +#define INTCICDIPTR143 INTC.ICDIPTR143 +#define INTCICDIPTR144 INTC.ICDIPTR144 +#define INTCICDIPTR145 INTC.ICDIPTR145 +#define INTCICDIPTR146 INTC.ICDIPTR146 +#define INTCICDICFR0 INTC.ICDICFR0 +#define INTCICDICFR1 INTC.ICDICFR1 +#define INTCICDICFR2 INTC.ICDICFR2 +#define INTCICDICFR3 INTC.ICDICFR3 +#define INTCICDICFR4 INTC.ICDICFR4 +#define INTCICDICFR5 INTC.ICDICFR5 +#define INTCICDICFR6 INTC.ICDICFR6 +#define INTCICDICFR7 INTC.ICDICFR7 +#define INTCICDICFR8 INTC.ICDICFR8 +#define INTCICDICFR9 INTC.ICDICFR9 +#define INTCICDICFR10 INTC.ICDICFR10 +#define INTCICDICFR11 INTC.ICDICFR11 +#define INTCICDICFR12 INTC.ICDICFR12 +#define INTCICDICFR13 INTC.ICDICFR13 +#define INTCICDICFR14 INTC.ICDICFR14 +#define INTCICDICFR15 INTC.ICDICFR15 +#define INTCICDICFR16 INTC.ICDICFR16 +#define INTCICDICFR17 INTC.ICDICFR17 +#define INTCICDICFR18 INTC.ICDICFR18 +#define INTCICDICFR19 INTC.ICDICFR19 +#define INTCICDICFR20 INTC.ICDICFR20 +#define INTCICDICFR21 INTC.ICDICFR21 +#define INTCICDICFR22 INTC.ICDICFR22 +#define INTCICDICFR23 INTC.ICDICFR23 +#define INTCICDICFR24 INTC.ICDICFR24 +#define INTCICDICFR25 INTC.ICDICFR25 +#define INTCICDICFR26 INTC.ICDICFR26 +#define INTCICDICFR27 INTC.ICDICFR27 +#define INTCICDICFR28 INTC.ICDICFR28 +#define INTCICDICFR29 INTC.ICDICFR29 +#define INTCICDICFR30 INTC.ICDICFR30 +#define INTCICDICFR31 INTC.ICDICFR31 +#define INTCICDICFR32 INTC.ICDICFR32 +#define INTCICDICFR33 INTC.ICDICFR33 +#define INTCICDICFR34 INTC.ICDICFR34 +#define INTCICDICFR35 INTC.ICDICFR35 +#define INTCICDICFR36 INTC.ICDICFR36 +#define INTCPPI_STATUS INTC.PPI_STATUS +#define INTCSPI_STATUS0 INTC.SPI_STATUS0 +#define INTCSPI_STATUS1 INTC.SPI_STATUS1 +#define INTCSPI_STATUS2 INTC.SPI_STATUS2 +#define INTCSPI_STATUS3 INTC.SPI_STATUS3 +#define INTCSPI_STATUS4 INTC.SPI_STATUS4 +#define INTCSPI_STATUS5 INTC.SPI_STATUS5 +#define INTCSPI_STATUS6 INTC.SPI_STATUS6 +#define INTCSPI_STATUS7 INTC.SPI_STATUS7 +#define INTCSPI_STATUS8 INTC.SPI_STATUS8 +#define INTCSPI_STATUS9 INTC.SPI_STATUS9 +#define INTCSPI_STATUS10 INTC.SPI_STATUS10 +#define INTCSPI_STATUS11 INTC.SPI_STATUS11 +#define INTCSPI_STATUS12 INTC.SPI_STATUS12 +#define INTCSPI_STATUS13 INTC.SPI_STATUS13 +#define INTCSPI_STATUS14 INTC.SPI_STATUS14 +#define INTCSPI_STATUS15 INTC.SPI_STATUS15 +#define INTCSPI_STATUS16 INTC.SPI_STATUS16 +#define INTCICDSGIR INTC.ICDSGIR +#define INTCICCICR INTC.ICCICR +#define INTCICCPMR INTC.ICCPMR +#define INTCICCBPR INTC.ICCBPR +#define INTCICCIAR INTC.ICCIAR +#define INTCICCEOIR INTC.ICCEOIR +#define INTCICCRPR INTC.ICCRPR +#define INTCICCHPIR INTC.ICCHPIR +#define INTCICCABPR INTC.ICCABPR +#define INTCICCIIDR INTC.ICCIIDR +#define INTCICR0 INTC.ICR0 +#define INTCICR1 INTC.ICR1 +#define INTCIRQRR INTC.IRQRR +/* <-SEC M1.10.1 */ +/* <-QAC 0639 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/irda_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,42 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : irda_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef IRDA_IODEFINE_H +#define IRDA_IODEFINE_H + +struct st_irda +{ /* IRDA */ + volatile uint8_t IRCR; /* IRCR */ +}; + + +#define IRDA (*(struct st_irda *)0xE8014000uL) /* IRDA */ + + +#define IRDAIRCR IRDA.IRCR +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/jcu_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,169 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : jcu_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef JCU_IODEFINE_H +#define JCU_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_jcu +{ /* JCU */ + volatile uint8_t JCMOD; /* JCMOD */ + volatile uint8_t JCCMD; /* JCCMD */ + volatile uint8_t dummy145[1]; /* */ + volatile uint8_t JCQTN; /* JCQTN */ + volatile uint8_t JCHTN; /* JCHTN */ + volatile uint8_t JCDRIU; /* JCDRIU */ + volatile uint8_t JCDRID; /* JCDRID */ + volatile uint8_t JCVSZU; /* JCVSZU */ + volatile uint8_t JCVSZD; /* JCVSZD */ + volatile uint8_t JCHSZU; /* JCHSZU */ + volatile uint8_t JCHSZD; /* JCHSZD */ + volatile uint8_t JCDTCU; /* JCDTCU */ + volatile uint8_t JCDTCM; /* JCDTCM */ + volatile uint8_t JCDTCD; /* JCDTCD */ + volatile uint8_t JINTE0; /* JINTE0 */ + volatile uint8_t JINTS0; /* JINTS0 */ + volatile uint8_t JCDERR; /* JCDERR */ + volatile uint8_t JCRST; /* JCRST */ + volatile uint8_t dummy146[46]; /* */ + volatile uint32_t JIFECNT; /* JIFECNT */ + volatile uint32_t JIFESA; /* JIFESA */ + volatile uint32_t JIFESOFST; /* JIFESOFST */ + volatile uint32_t JIFEDA; /* JIFEDA */ + volatile uint32_t JIFESLC; /* JIFESLC */ + volatile uint32_t JIFEDDC; /* JIFEDDC */ + volatile uint32_t JIFDCNT; /* JIFDCNT */ + volatile uint32_t JIFDSA; /* JIFDSA */ + volatile uint32_t JIFDDOFST; /* JIFDDOFST */ + volatile uint32_t JIFDDA; /* JIFDDA */ + volatile uint32_t JIFDSDC; /* JIFDSDC */ + volatile uint32_t JIFDDLC; /* JIFDDLC */ + volatile uint32_t JIFDADT; /* JIFDADT */ + volatile uint8_t dummy147[24]; /* */ + volatile uint32_t JINTE1; /* JINTE1 */ + volatile uint32_t JINTS1; /* JINTS1 */ + volatile uint32_t JIFESVSZ; /* JIFESVSZ */ + volatile uint32_t JIFESHSZ; /* JIFESHSZ */ + volatile uint8_t dummy148[100]; /* */ +/* start of struct st_jcu_from_jcqtbl0 */ + volatile uint8_t JCQTBL0; /* JCQTBL0 */ + volatile uint8_t dummy149[63]; /* */ +/* end of struct st_jcu_from_jcqtbl0 */ +/* start of struct st_jcu_from_jcqtbl0 */ + volatile uint8_t JCQTBL1; /* JCQTBL1 */ + volatile uint8_t dummy150[63]; /* */ +/* end of struct st_jcu_from_jcqtbl0 */ +/* start of struct st_jcu_from_jcqtbl0 */ + volatile uint8_t JCQTBL2; /* JCQTBL2 */ + volatile uint8_t dummy151[63]; /* */ +/* end of struct st_jcu_from_jcqtbl0 */ +/* start of struct st_jcu_from_jcqtbl0 */ + volatile uint8_t JCQTBL3; /* JCQTBL3 */ + volatile uint8_t dummy152[63]; /* */ +/* end of struct st_jcu_from_jcqtbl0 */ + volatile uint8_t JCHTBD0; /* JCHTBD0 */ + volatile uint8_t dummy153[31]; /* */ + volatile uint8_t JCHTBA0; /* JCHTBA0 */ + volatile uint8_t dummy154[223]; /* */ + volatile uint8_t JCHTBD1; /* JCHTBD1 */ + volatile uint8_t dummy155[31]; /* */ + volatile uint8_t JCHTBA1; /* JCHTBA1 */ +}; + + +struct st_jcu_from_jcqtbl0 +{ + volatile uint8_t JCQTBL0; /* JCQTBL0 */ + volatile uint8_t dummy1[63]; /* */ +}; + + +#define JCU (*(struct st_jcu *)0xE8017000uL) /* JCU */ + + +/* Start of channnel array defines of JCU */ + +/* Channnel array defines of JCU_JCQTBL0 */ +/*(Sample) value = JCU_JCQTBL0[ channel ]->JCQTBL0; */ +#define JCU_JCQTBL0_COUNT 4 +#define JCU_JCQTBL0_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &JCU_FROM_JCQTBL0, &JCU_FROM_JCQTBL1, &JCU_FROM_JCQTBL2, &JCU_FROM_JCQTBL3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define JCU_FROM_JCQTBL0 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL0) /* JCU_FROM_JCQTBL0 */ +#define JCU_FROM_JCQTBL1 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL1) /* JCU_FROM_JCQTBL1 */ +#define JCU_FROM_JCQTBL2 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL2) /* JCU_FROM_JCQTBL2 */ +#define JCU_FROM_JCQTBL3 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL3) /* JCU_FROM_JCQTBL3 */ + +/* End of channnel array defines of JCU */ + + +#define JCUJCMOD JCU.JCMOD +#define JCUJCCMD JCU.JCCMD +#define JCUJCQTN JCU.JCQTN +#define JCUJCHTN JCU.JCHTN +#define JCUJCDRIU JCU.JCDRIU +#define JCUJCDRID JCU.JCDRID +#define JCUJCVSZU JCU.JCVSZU +#define JCUJCVSZD JCU.JCVSZD +#define JCUJCHSZU JCU.JCHSZU +#define JCUJCHSZD JCU.JCHSZD +#define JCUJCDTCU JCU.JCDTCU +#define JCUJCDTCM JCU.JCDTCM +#define JCUJCDTCD JCU.JCDTCD +#define JCUJINTE0 JCU.JINTE0 +#define JCUJINTS0 JCU.JINTS0 +#define JCUJCDERR JCU.JCDERR +#define JCUJCRST JCU.JCRST +#define JCUJIFECNT JCU.JIFECNT +#define JCUJIFESA JCU.JIFESA +#define JCUJIFESOFST JCU.JIFESOFST +#define JCUJIFEDA JCU.JIFEDA +#define JCUJIFESLC JCU.JIFESLC +#define JCUJIFEDDC JCU.JIFEDDC +#define JCUJIFDCNT JCU.JIFDCNT +#define JCUJIFDSA JCU.JIFDSA +#define JCUJIFDDOFST JCU.JIFDDOFST +#define JCUJIFDDA JCU.JIFDDA +#define JCUJIFDSDC JCU.JIFDSDC +#define JCUJIFDDLC JCU.JIFDDLC +#define JCUJIFDADT JCU.JIFDADT +#define JCUJINTE1 JCU.JINTE1 +#define JCUJINTS1 JCU.JINTS1 +#define JCUJIFESVSZ JCU.JIFESVSZ +#define JCUJIFESHSZ JCU.JIFESHSZ +#define JCUJCQTBL0 JCU.JCQTBL0 +#define JCUJCQTBL1 JCU.JCQTBL1 +#define JCUJCQTBL2 JCU.JCQTBL2 +#define JCUJCQTBL3 JCU.JCQTBL3 +#define JCUJCHTBD0 JCU.JCHTBD0 +#define JCUJCHTBA0 JCU.JCHTBA0 +#define JCUJCHTBD1 JCU.JCHTBD1 +#define JCUJCHTBA1 JCU.JCHTBA1 +/* <-SEC M1.10.1 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/l2c_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,195 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : l2c_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef L2C_IODEFINE_H +#define L2C_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_l2c +{ /* L2C */ + volatile uint32_t REG0_CACHE_ID; /* REG0_CACHE_ID */ + volatile uint32_t REG0_CACHE_TYPE; /* REG0_CACHE_TYPE */ + volatile uint8_t dummy8[248]; /* */ + volatile uint32_t REG1_CONTROL; /* REG1_CONTROL */ + volatile uint32_t REG1_AUX_CONTROL; /* REG1_AUX_CONTROL */ + volatile uint32_t REG1_TAG_RAM_CONTROL; /* REG1_TAG_RAM_CONTROL */ + volatile uint32_t REG1_DATA_RAM_CONTROL; /* REG1_DATA_RAM_CONTROL */ + volatile uint8_t dummy9[240]; /* */ + volatile uint32_t REG2_EV_COUNTER_CTRL; /* REG2_EV_COUNTER_CTRL */ + volatile uint32_t REG2_EV_COUNTER1_CFG; /* REG2_EV_COUNTER1_CFG */ + volatile uint32_t REG2_EV_COUNTER0_CFG; /* REG2_EV_COUNTER0_CFG */ + volatile uint32_t REG2_EV_COUNTER1; /* REG2_EV_COUNTER1 */ + volatile uint32_t REG2_EV_COUNTER0; /* REG2_EV_COUNTER0 */ + volatile uint32_t REG2_INT_MASK; /* REG2_INT_MASK */ + volatile uint32_t REG2_INT_MASK_STATUS; /* REG2_INT_MASK_STATUS */ + volatile uint32_t REG2_INT_RAW_STATUS; /* REG2_INT_RAW_STATUS */ + volatile uint32_t REG2_INT_CLEAR; /* REG2_INT_CLEAR */ + volatile uint8_t dummy10[1292]; /* */ + volatile uint32_t REG7_CACHE_SYNC; /* REG7_CACHE_SYNC */ + volatile uint8_t dummy11[60]; /* */ + volatile uint32_t REG7_INV_PA; /* REG7_INV_PA */ + volatile uint8_t dummy12[8]; /* */ + volatile uint32_t REG7_INV_WAY; /* REG7_INV_WAY */ + volatile uint8_t dummy13[48]; /* */ + volatile uint32_t REG7_CLEAN_PA; /* REG7_CLEAN_PA */ + volatile uint8_t dummy14[4]; /* */ + volatile uint32_t REG7_CLEAN_INDEX; /* REG7_CLEAN_INDEX */ + volatile uint32_t REG7_CLEAN_WAY; /* REG7_CLEAN_WAY */ + volatile uint8_t dummy15[48]; /* */ + volatile uint32_t REG7_CLEAN_INV_PA; /* REG7_CLEAN_INV_PA */ + volatile uint8_t dummy16[4]; /* */ + volatile uint32_t REG7_CLEAN_INV_INDEX; /* REG7_CLEAN_INV_INDEX */ + volatile uint32_t REG7_CLEAN_INV_WAY; /* REG7_CLEAN_INV_WAY */ + volatile uint8_t dummy17[256]; /* */ +/* start of struct st_l2c_from_reg9_d_lockdown0 */ + volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */ + volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */ +/* end of struct st_l2c_from_reg9_d_lockdown0 */ +/* start of struct st_l2c_from_reg9_d_lockdown0 */ + volatile uint32_t REG9_D_LOCKDOWN1; /* REG9_D_LOCKDOWN1 */ + volatile uint32_t REG9_I_LOCKDOWN1; /* REG9_I_LOCKDOWN1 */ +/* end of struct st_l2c_from_reg9_d_lockdown0 */ +/* start of struct st_l2c_from_reg9_d_lockdown0 */ + volatile uint32_t REG9_D_LOCKDOWN2; /* REG9_D_LOCKDOWN2 */ + volatile uint32_t REG9_I_LOCKDOWN2; /* REG9_I_LOCKDOWN2 */ +/* end of struct st_l2c_from_reg9_d_lockdown0 */ +/* start of struct st_l2c_from_reg9_d_lockdown0 */ + volatile uint32_t REG9_D_LOCKDOWN3; /* REG9_D_LOCKDOWN3 */ + volatile uint32_t REG9_I_LOCKDOWN3; /* REG9_I_LOCKDOWN3 */ +/* end of struct st_l2c_from_reg9_d_lockdown0 */ +/* start of struct st_l2c_from_reg9_d_lockdown0 */ + volatile uint32_t REG9_D_LOCKDOWN4; /* REG9_D_LOCKDOWN4 */ + volatile uint32_t REG9_I_LOCKDOWN4; /* REG9_I_LOCKDOWN4 */ +/* end of struct st_l2c_from_reg9_d_lockdown0 */ +/* start of struct st_l2c_from_reg9_d_lockdown0 */ + volatile uint32_t REG9_D_LOCKDOWN5; /* REG9_D_LOCKDOWN5 */ + volatile uint32_t REG9_I_LOCKDOWN5; /* REG9_I_LOCKDOWN5 */ +/* end of struct st_l2c_from_reg9_d_lockdown0 */ +/* start of struct st_l2c_from_reg9_d_lockdown0 */ + volatile uint32_t REG9_D_LOCKDOWN6; /* REG9_D_LOCKDOWN6 */ + volatile uint32_t REG9_I_LOCKDOWN6; /* REG9_I_LOCKDOWN6 */ +/* end of struct st_l2c_from_reg9_d_lockdown0 */ +/* start of struct st_l2c_from_reg9_d_lockdown0 */ + volatile uint32_t REG9_D_LOCKDOWN7; /* REG9_D_LOCKDOWN7 */ + volatile uint32_t REG9_I_LOCKDOWN7; /* REG9_I_LOCKDOWN7 */ +/* end of struct st_l2c_from_reg9_d_lockdown0 */ + volatile uint8_t dummy18[16]; /* */ + volatile uint32_t REG9_LOCK_LINE_EN; /* REG9_LOCK_LINE_EN */ + volatile uint32_t REG9_UNLOCK_WAY; /* REG9_UNLOCK_WAY */ + volatile uint8_t dummy19[680]; /* */ + volatile uint32_t REG12_ADDR_FILTERING_START; /* REG12_ADDR_FILTERING_START */ + volatile uint32_t REG12_ADDR_FILTERING_END; /* REG12_ADDR_FILTERING_END */ + volatile uint8_t dummy20[824]; /* */ + volatile uint32_t REG15_DEBUG_CTRL; /* REG15_DEBUG_CTRL */ + volatile uint8_t dummy21[28]; /* */ + volatile uint32_t REG15_PREFETCH_CTRL; /* REG15_PREFETCH_CTRL */ + volatile uint8_t dummy22[28]; /* */ + volatile uint32_t REG15_POWER_CTRL; /* REG15_POWER_CTRL */ +}; + + +struct st_l2c_from_reg9_d_lockdown0 +{ + volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */ + volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */ +}; + + +#define L2C (*(struct st_l2c *)0x3FFFF000uL) /* L2C */ + + +/* Start of channnel array defines of L2C */ + +/* Channnel array defines of L2C_FROM_REG9_D_LOCKDOWN0_ARRAY */ +/*(Sample) value = L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ channel ]->REG9_D_LOCKDOWN0; */ +#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT 8 +#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &L2C_FROM_REG9_D_LOCKDOWN0, &L2C_FROM_REG9_D_LOCKDOWN1, &L2C_FROM_REG9_D_LOCKDOWN2, &L2C_FROM_REG9_D_LOCKDOWN3, &L2C_FROM_REG9_D_LOCKDOWN4, &L2C_FROM_REG9_D_LOCKDOWN5, &L2C_FROM_REG9_D_LOCKDOWN6, &L2C_FROM_REG9_D_LOCKDOWN7 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define L2C_FROM_REG9_D_LOCKDOWN0 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN0) /* L2C_FROM_REG9_D_LOCKDOWN0 */ +#define L2C_FROM_REG9_D_LOCKDOWN1 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN1) /* L2C_FROM_REG9_D_LOCKDOWN1 */ +#define L2C_FROM_REG9_D_LOCKDOWN2 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN2) /* L2C_FROM_REG9_D_LOCKDOWN2 */ +#define L2C_FROM_REG9_D_LOCKDOWN3 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN3) /* L2C_FROM_REG9_D_LOCKDOWN3 */ +#define L2C_FROM_REG9_D_LOCKDOWN4 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN4) /* L2C_FROM_REG9_D_LOCKDOWN4 */ +#define L2C_FROM_REG9_D_LOCKDOWN5 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN5) /* L2C_FROM_REG9_D_LOCKDOWN5 */ +#define L2C_FROM_REG9_D_LOCKDOWN6 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN6) /* L2C_FROM_REG9_D_LOCKDOWN6 */ +#define L2C_FROM_REG9_D_LOCKDOWN7 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN7) /* L2C_FROM_REG9_D_LOCKDOWN7 */ + +/* End of channnel array defines of L2C */ + + +#define L2CREG0_CACHE_ID L2C.REG0_CACHE_ID +#define L2CREG0_CACHE_TYPE L2C.REG0_CACHE_TYPE +#define L2CREG1_CONTROL L2C.REG1_CONTROL +#define L2CREG1_AUX_CONTROL L2C.REG1_AUX_CONTROL +#define L2CREG1_TAG_RAM_CONTROL L2C.REG1_TAG_RAM_CONTROL +#define L2CREG1_DATA_RAM_CONTROL L2C.REG1_DATA_RAM_CONTROL +#define L2CREG2_EV_COUNTER_CTRL L2C.REG2_EV_COUNTER_CTRL +#define L2CREG2_EV_COUNTER1_CFG L2C.REG2_EV_COUNTER1_CFG +#define L2CREG2_EV_COUNTER0_CFG L2C.REG2_EV_COUNTER0_CFG +#define L2CREG2_EV_COUNTER1 L2C.REG2_EV_COUNTER1 +#define L2CREG2_EV_COUNTER0 L2C.REG2_EV_COUNTER0 +#define L2CREG2_INT_MASK L2C.REG2_INT_MASK +#define L2CREG2_INT_MASK_STATUS L2C.REG2_INT_MASK_STATUS +#define L2CREG2_INT_RAW_STATUS L2C.REG2_INT_RAW_STATUS +#define L2CREG2_INT_CLEAR L2C.REG2_INT_CLEAR +#define L2CREG7_CACHE_SYNC L2C.REG7_CACHE_SYNC +#define L2CREG7_INV_PA L2C.REG7_INV_PA +#define L2CREG7_INV_WAY L2C.REG7_INV_WAY +#define L2CREG7_CLEAN_PA L2C.REG7_CLEAN_PA +#define L2CREG7_CLEAN_INDEX L2C.REG7_CLEAN_INDEX +#define L2CREG7_CLEAN_WAY L2C.REG7_CLEAN_WAY +#define L2CREG7_CLEAN_INV_PA L2C.REG7_CLEAN_INV_PA +#define L2CREG7_CLEAN_INV_INDEX L2C.REG7_CLEAN_INV_INDEX +#define L2CREG7_CLEAN_INV_WAY L2C.REG7_CLEAN_INV_WAY +#define L2CREG9_D_LOCKDOWN0 L2C.REG9_D_LOCKDOWN0 +#define L2CREG9_I_LOCKDOWN0 L2C.REG9_I_LOCKDOWN0 +#define L2CREG9_D_LOCKDOWN1 L2C.REG9_D_LOCKDOWN1 +#define L2CREG9_I_LOCKDOWN1 L2C.REG9_I_LOCKDOWN1 +#define L2CREG9_D_LOCKDOWN2 L2C.REG9_D_LOCKDOWN2 +#define L2CREG9_I_LOCKDOWN2 L2C.REG9_I_LOCKDOWN2 +#define L2CREG9_D_LOCKDOWN3 L2C.REG9_D_LOCKDOWN3 +#define L2CREG9_I_LOCKDOWN3 L2C.REG9_I_LOCKDOWN3 +#define L2CREG9_D_LOCKDOWN4 L2C.REG9_D_LOCKDOWN4 +#define L2CREG9_I_LOCKDOWN4 L2C.REG9_I_LOCKDOWN4 +#define L2CREG9_D_LOCKDOWN5 L2C.REG9_D_LOCKDOWN5 +#define L2CREG9_I_LOCKDOWN5 L2C.REG9_I_LOCKDOWN5 +#define L2CREG9_D_LOCKDOWN6 L2C.REG9_D_LOCKDOWN6 +#define L2CREG9_I_LOCKDOWN6 L2C.REG9_I_LOCKDOWN6 +#define L2CREG9_D_LOCKDOWN7 L2C.REG9_D_LOCKDOWN7 +#define L2CREG9_I_LOCKDOWN7 L2C.REG9_I_LOCKDOWN7 +#define L2CREG9_LOCK_LINE_EN L2C.REG9_LOCK_LINE_EN +#define L2CREG9_UNLOCK_WAY L2C.REG9_UNLOCK_WAY +#define L2CREG12_ADDR_FILTERING_START L2C.REG12_ADDR_FILTERING_START +#define L2CREG12_ADDR_FILTERING_END L2C.REG12_ADDR_FILTERING_END +#define L2CREG15_DEBUG_CTRL L2C.REG15_DEBUG_CTRL +#define L2CREG15_PREFETCH_CTRL L2C.REG15_PREFETCH_CTRL +#define L2CREG15_POWER_CTRL L2C.REG15_POWER_CTRL +/* <-SEC M1.10.1 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/lin_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,174 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : lin_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef LIN_IODEFINE_H +#define LIN_IODEFINE_H +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +struct st_lin +{ /* LIN */ + volatile uint8_t dummy1[1]; /* */ + volatile uint8_t RLN3nLWBR; /* RLN3nLWBR */ + union iodefine_reg16_8_t RLN3nLBRP01; /* RLN3nLBRP01 */ + + volatile uint8_t RLN3nLSTC; /* RLN3nLSTC */ + volatile uint8_t dummy2[3]; /* */ + volatile uint8_t RLN3nLMD; /* RLN3nLMD */ + volatile uint8_t RLN3nLBFC; /* RLN3nLBFC */ + volatile uint8_t RLN3nLSC; /* RLN3nLSC */ + volatile uint8_t RLN3nLWUP; /* RLN3nLWUP */ + volatile uint8_t RLN3nLIE; /* RLN3nLIE */ + volatile uint8_t RLN3nLEDE; /* RLN3nLEDE */ + volatile uint8_t RLN3nLCUC; /* RLN3nLCUC */ + volatile uint8_t dummy3[1]; /* */ + volatile uint8_t RLN3nLTRC; /* RLN3nLTRC */ + volatile uint8_t RLN3nLMST; /* RLN3nLMST */ + volatile uint8_t RLN3nLST; /* RLN3nLST */ + volatile uint8_t RLN3nLEST; /* RLN3nLEST */ + volatile uint8_t RLN3nLDFC; /* RLN3nLDFC */ + volatile uint8_t RLN3nLIDB; /* RLN3nLIDB */ + volatile uint8_t RLN3nLCBR; /* RLN3nLCBR */ + volatile uint8_t RLN3nLUDB0; /* RLN3nLUDB0 */ +#define LIN_LDBn_COUNT 8 + volatile uint8_t RLN3nLDBR1; /* RLN3nLDBR1 */ + volatile uint8_t RLN3nLDBR2; /* RLN3nLDBR2 */ + volatile uint8_t RLN3nLDBR3; /* RLN3nLDBR3 */ + volatile uint8_t RLN3nLDBR4; /* RLN3nLDBR4 */ + volatile uint8_t RLN3nLDBR5; /* RLN3nLDBR5 */ + volatile uint8_t RLN3nLDBR6; /* RLN3nLDBR6 */ + volatile uint8_t RLN3nLDBR7; /* RLN3nLDBR7 */ + volatile uint8_t RLN3nLDBR8; /* RLN3nLDBR8 */ + volatile uint8_t RLN3nLUOER; /* RLN3nLUOER */ + volatile uint8_t RLN3nLUOR1; /* RLN3nLUOR1 */ + volatile uint8_t dummy4[2]; /* */ + union iodefine_reg16_8_t RLN3nLUTDR; /* RLN3nLUTDR */ + union iodefine_reg16_8_t RLN3nLURDR; /* RLN3nLURDR */ + union iodefine_reg16_8_t RLN3nLUWTDR; /* RLN3nLUWTDR */ + +}; + + +#define LIN0 (*(struct st_lin *)0xFCFE9000uL) /* LIN0 */ +#define LIN1 (*(struct st_lin *)0xFCFE9800uL) /* LIN1 */ + + +/* Start of channnel array defines of LIN */ + +/* Channnel array defines of LIN */ +/*(Sample) value = LIN[ channel ]->RLN3nLWBR; */ +#define LIN_COUNT 2 +#define LIN_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &LIN0, &LIN1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channnel array defines of LIN */ + + +#define LIN0RLN30LWBR LIN0.RLN3nLWBR +#define LIN0RLN30LBRP01 LIN0.RLN3nLBRP01.UINT16 +#define LIN0RLN30LBRP0 LIN0.RLN3nLBRP01.UINT8[L] +#define LIN0RLN30LBRP1 LIN0.RLN3nLBRP01.UINT8[H] +#define LIN0RLN30LSTC LIN0.RLN3nLSTC +#define LIN0RLN30LMD LIN0.RLN3nLMD +#define LIN0RLN30LBFC LIN0.RLN3nLBFC +#define LIN0RLN30LSC LIN0.RLN3nLSC +#define LIN0RLN30LWUP LIN0.RLN3nLWUP +#define LIN0RLN30LIE LIN0.RLN3nLIE +#define LIN0RLN30LEDE LIN0.RLN3nLEDE +#define LIN0RLN30LCUC LIN0.RLN3nLCUC +#define LIN0RLN30LTRC LIN0.RLN3nLTRC +#define LIN0RLN30LMST LIN0.RLN3nLMST +#define LIN0RLN30LST LIN0.RLN3nLST +#define LIN0RLN30LEST LIN0.RLN3nLEST +#define LIN0RLN30LDFC LIN0.RLN3nLDFC +#define LIN0RLN30LIDB LIN0.RLN3nLIDB +#define LIN0RLN30LCBR LIN0.RLN3nLCBR +#define LIN0RLN30LUDB0 LIN0.RLN3nLUDB0 +#define LIN0RLN30LDBR1 LIN0.RLN3nLDBR1 +#define LIN0RLN30LDBR2 LIN0.RLN3nLDBR2 +#define LIN0RLN30LDBR3 LIN0.RLN3nLDBR3 +#define LIN0RLN30LDBR4 LIN0.RLN3nLDBR4 +#define LIN0RLN30LDBR5 LIN0.RLN3nLDBR5 +#define LIN0RLN30LDBR6 LIN0.RLN3nLDBR6 +#define LIN0RLN30LDBR7 LIN0.RLN3nLDBR7 +#define LIN0RLN30LDBR8 LIN0.RLN3nLDBR8 +#define LIN0RLN30LUOER LIN0.RLN3nLUOER +#define LIN0RLN30LUOR1 LIN0.RLN3nLUOR1 +#define LIN0RLN30LUTDR LIN0.RLN3nLUTDR.UINT16 +#define LIN0RLN30LUTDRL LIN0.RLN3nLUTDR.UINT8[L] +#define LIN0RLN30LUTDRH LIN0.RLN3nLUTDR.UINT8[H] +#define LIN0RLN30LURDR LIN0.RLN3nLURDR.UINT16 +#define LIN0RLN30LURDRL LIN0.RLN3nLURDR.UINT8[L] +#define LIN0RLN30LURDRH LIN0.RLN3nLURDR.UINT8[H] +#define LIN0RLN30LUWTDR LIN0.RLN3nLUWTDR.UINT16 +#define LIN0RLN30LUWTDRL LIN0.RLN3nLUWTDR.UINT8[L] +#define LIN0RLN30LUWTDRH LIN0.RLN3nLUWTDR.UINT8[H] +#define LIN1RLN31LWBR LIN1.RLN3nLWBR +#define LIN1RLN31LBRP01 LIN1.RLN3nLBRP01.UINT16 +#define LIN1RLN31LBRP0 LIN1.RLN3nLBRP01.UINT8[L] +#define LIN1RLN31LBRP1 LIN1.RLN3nLBRP01.UINT8[H] +#define LIN1RLN31LSTC LIN1.RLN3nLSTC +#define LIN1RLN31LMD LIN1.RLN3nLMD +#define LIN1RLN31LBFC LIN1.RLN3nLBFC +#define LIN1RLN31LSC LIN1.RLN3nLSC +#define LIN1RLN31LWUP LIN1.RLN3nLWUP +#define LIN1RLN31LIE LIN1.RLN3nLIE +#define LIN1RLN31LEDE LIN1.RLN3nLEDE +#define LIN1RLN31LCUC LIN1.RLN3nLCUC +#define LIN1RLN31LTRC LIN1.RLN3nLTRC +#define LIN1RLN31LMST LIN1.RLN3nLMST +#define LIN1RLN31LST LIN1.RLN3nLST +#define LIN1RLN31LEST LIN1.RLN3nLEST +#define LIN1RLN31LDFC LIN1.RLN3nLDFC +#define LIN1RLN31LIDB LIN1.RLN3nLIDB +#define LIN1RLN31LCBR LIN1.RLN3nLCBR +#define LIN1RLN31LUDB0 LIN1.RLN3nLUDB0 +#define LIN1RLN31LDBR1 LIN1.RLN3nLDBR1 +#define LIN1RLN31LDBR2 LIN1.RLN3nLDBR2 +#define LIN1RLN31LDBR3 LIN1.RLN3nLDBR3 +#define LIN1RLN31LDBR4 LIN1.RLN3nLDBR4 +#define LIN1RLN31LDBR5 LIN1.RLN3nLDBR5 +#define LIN1RLN31LDBR6 LIN1.RLN3nLDBR6 +#define LIN1RLN31LDBR7 LIN1.RLN3nLDBR7 +#define LIN1RLN31LDBR8 LIN1.RLN3nLDBR8 +#define LIN1RLN31LUOER LIN1.RLN3nLUOER +#define LIN1RLN31LUOR1 LIN1.RLN3nLUOR1 +#define LIN1RLN31LUTDR LIN1.RLN3nLUTDR.UINT16 +#define LIN1RLN31LUTDRL LIN1.RLN3nLUTDR.UINT8[L] +#define LIN1RLN31LUTDRH LIN1.RLN3nLUTDR.UINT8[H] +#define LIN1RLN31LURDR LIN1.RLN3nLURDR.UINT16 +#define LIN1RLN31LURDRL LIN1.RLN3nLURDR.UINT8[L] +#define LIN1RLN31LURDRH LIN1.RLN3nLURDR.UINT8[H] +#define LIN1RLN31LUWTDR LIN1.RLN3nLUWTDR.UINT16 +#define LIN1RLN31LUWTDRL LIN1.RLN3nLUWTDR.UINT8[L] +#define LIN1RLN31LUWTDRH LIN1.RLN3nLUWTDR.UINT8[H] +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/lvds_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,54 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : lvds_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.01a) +******************************************************************************/ +#ifndef LVDS_IODEFINE_H +#define LVDS_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_lvds +{ /* LVDS */ + volatile uint32_t LVDS_UPDATE; /* LVDS_UPDATE */ + volatile uint32_t LVDSFCL; /* LVDSFCL */ + volatile uint8_t dummy608[24]; /* */ + volatile uint32_t LCLKSELR; /* LCLKSELR */ + volatile uint32_t LPLLSETR; /* LPLLSETR */ + volatile uint8_t dummy609[4]; /* */ + volatile uint32_t LPHYACC; /* LPHYACC */ +}; + + +#define LVDS (*(struct st_lvds *)0xFCFF7A30uL) /* LVDS */ + + +#define LVDSLVDS_UPDATE LVDS.LVDS_UPDATE +#define LVDSLVDSFCL LVDS.LVDSFCL +#define LVDSLCLKSELR LVDS.LCLKSELR +#define LVDSLPLLSETR LVDS.LPLLSETR +#define LVDSLPHYACC LVDS.LPHYACC +/* <-SEC M1.10.1 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/mlb_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,498 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : mlb_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef MLB_IODEFINE_H +#define MLB_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->SEC M1.10.1 : Not magic number */ + +struct st_mlb +{ /* MLB */ + volatile uint32_t DCCR; /* DCCR */ + volatile uint32_t SSCR; /* SSCR */ + volatile uint32_t SDCR; /* SDCR */ + volatile uint32_t SMCR; /* SMCR */ + volatile uint8_t dummy156[12]; /* */ + volatile uint32_t VCCR; /* VCCR */ + volatile uint32_t SBCR; /* SBCR */ + volatile uint32_t ABCR; /* ABCR */ + volatile uint32_t CBCR; /* CBCR */ + volatile uint32_t IBCR; /* IBCR */ + volatile uint32_t CICR; /* CICR */ + volatile uint8_t dummy157[12]; /* */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR0; /* CECR0 */ + volatile uint32_t CSCR0; /* CSCR0 */ + volatile uint32_t CCBCR0; /* CCBCR0 */ + volatile uint32_t CNBCR0; /* CNBCR0 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR1; /* CECR1 */ + volatile uint32_t CSCR1; /* CSCR1 */ + volatile uint32_t CCBCR1; /* CCBCR1 */ + volatile uint32_t CNBCR1; /* CNBCR1 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR2; /* CECR2 */ + volatile uint32_t CSCR2; /* CSCR2 */ + volatile uint32_t CCBCR2; /* CCBCR2 */ + volatile uint32_t CNBCR2; /* CNBCR2 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR3; /* CECR3 */ + volatile uint32_t CSCR3; /* CSCR3 */ + volatile uint32_t CCBCR3; /* CCBCR3 */ + volatile uint32_t CNBCR3; /* CNBCR3 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR4; /* CECR4 */ + volatile uint32_t CSCR4; /* CSCR4 */ + volatile uint32_t CCBCR4; /* CCBCR4 */ + volatile uint32_t CNBCR4; /* CNBCR4 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR5; /* CECR5 */ + volatile uint32_t CSCR5; /* CSCR5 */ + volatile uint32_t CCBCR5; /* CCBCR5 */ + volatile uint32_t CNBCR5; /* CNBCR5 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR6; /* CECR6 */ + volatile uint32_t CSCR6; /* CSCR6 */ + volatile uint32_t CCBCR6; /* CCBCR6 */ + volatile uint32_t CNBCR6; /* CNBCR6 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR7; /* CECR7 */ + volatile uint32_t CSCR7; /* CSCR7 */ + volatile uint32_t CCBCR7; /* CCBCR7 */ + volatile uint32_t CNBCR7; /* CNBCR7 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR8; /* CECR8 */ + volatile uint32_t CSCR8; /* CSCR8 */ + volatile uint32_t CCBCR8; /* CCBCR8 */ + volatile uint32_t CNBCR8; /* CNBCR8 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR9; /* CECR9 */ + volatile uint32_t CSCR9; /* CSCR9 */ + volatile uint32_t CCBCR9; /* CCBCR9 */ + volatile uint32_t CNBCR9; /* CNBCR9 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR10; /* CECR10 */ + volatile uint32_t CSCR10; /* CSCR10 */ + volatile uint32_t CCBCR10; /* CCBCR10 */ + volatile uint32_t CNBCR10; /* CNBCR10 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR11; /* CECR11 */ + volatile uint32_t CSCR11; /* CSCR11 */ + volatile uint32_t CCBCR11; /* CCBCR11 */ + volatile uint32_t CNBCR11; /* CNBCR11 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR12; /* CECR12 */ + volatile uint32_t CSCR12; /* CSCR12 */ + volatile uint32_t CCBCR12; /* CCBCR12 */ + volatile uint32_t CNBCR12; /* CNBCR12 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR13; /* CECR13 */ + volatile uint32_t CSCR13; /* CSCR13 */ + volatile uint32_t CCBCR13; /* CCBCR13 */ + volatile uint32_t CNBCR13; /* CNBCR13 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR14; /* CECR14 */ + volatile uint32_t CSCR14; /* CSCR14 */ + volatile uint32_t CCBCR14; /* CCBCR14 */ + volatile uint32_t CNBCR14; /* CNBCR14 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR15; /* CECR15 */ + volatile uint32_t CSCR15; /* CSCR15 */ + volatile uint32_t CCBCR15; /* CCBCR15 */ + volatile uint32_t CNBCR15; /* CNBCR15 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR16; /* CECR16 */ + volatile uint32_t CSCR16; /* CSCR16 */ + volatile uint32_t CCBCR16; /* CCBCR16 */ + volatile uint32_t CNBCR16; /* CNBCR16 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR17; /* CECR17 */ + volatile uint32_t CSCR17; /* CSCR17 */ + volatile uint32_t CCBCR17; /* CCBCR17 */ + volatile uint32_t CNBCR17; /* CNBCR17 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR18; /* CECR18 */ + volatile uint32_t CSCR18; /* CSCR18 */ + volatile uint32_t CCBCR18; /* CCBCR18 */ + volatile uint32_t CNBCR18; /* CNBCR18 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR19; /* CECR19 */ + volatile uint32_t CSCR19; /* CSCR19 */ + volatile uint32_t CCBCR19; /* CCBCR19 */ + volatile uint32_t CNBCR19; /* CNBCR19 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR20; /* CECR20 */ + volatile uint32_t CSCR20; /* CSCR20 */ + volatile uint32_t CCBCR20; /* CCBCR20 */ + volatile uint32_t CNBCR20; /* CNBCR20 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR21; /* CECR21 */ + volatile uint32_t CSCR21; /* CSCR21 */ + volatile uint32_t CCBCR21; /* CCBCR21 */ + volatile uint32_t CNBCR21; /* CNBCR21 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR22; /* CECR22 */ + volatile uint32_t CSCR22; /* CSCR22 */ + volatile uint32_t CCBCR22; /* CCBCR22 */ + volatile uint32_t CNBCR22; /* CNBCR22 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR23; /* CECR23 */ + volatile uint32_t CSCR23; /* CSCR23 */ + volatile uint32_t CCBCR23; /* CCBCR23 */ + volatile uint32_t CNBCR23; /* CNBCR23 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR24; /* CECR24 */ + volatile uint32_t CSCR24; /* CSCR24 */ + volatile uint32_t CCBCR24; /* CCBCR24 */ + volatile uint32_t CNBCR24; /* CNBCR24 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR25; /* CECR25 */ + volatile uint32_t CSCR25; /* CSCR25 */ + volatile uint32_t CCBCR25; /* CCBCR25 */ + volatile uint32_t CNBCR25; /* CNBCR25 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR26; /* CECR26 */ + volatile uint32_t CSCR26; /* CSCR26 */ + volatile uint32_t CCBCR26; /* CCBCR26 */ + volatile uint32_t CNBCR26; /* CNBCR26 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR27; /* CECR27 */ + volatile uint32_t CSCR27; /* CSCR27 */ + volatile uint32_t CCBCR27; /* CCBCR27 */ + volatile uint32_t CNBCR27; /* CNBCR27 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR28; /* CECR28 */ + volatile uint32_t CSCR28; /* CSCR28 */ + volatile uint32_t CCBCR28; /* CCBCR28 */ + volatile uint32_t CNBCR28; /* CNBCR28 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR29; /* CECR29 */ + volatile uint32_t CSCR29; /* CSCR29 */ + volatile uint32_t CCBCR29; /* CCBCR29 */ + volatile uint32_t CNBCR29; /* CNBCR29 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR30; /* CECR30 */ + volatile uint32_t CSCR30; /* CSCR30 */ + volatile uint32_t CCBCR30; /* CCBCR30 */ + volatile uint32_t CNBCR30; /* CNBCR30 */ +/* end of struct st_mlb_from_cecr0 */ + volatile uint8_t dummy158[80]; /* */ +#define MLB_LCBCR0_COUNT 31 + volatile uint32_t LCBCR0; /* LCBCR0 */ + volatile uint32_t LCBCR1; /* LCBCR1 */ + volatile uint32_t LCBCR2; /* LCBCR2 */ + volatile uint32_t LCBCR3; /* LCBCR3 */ + volatile uint32_t LCBCR4; /* LCBCR4 */ + volatile uint32_t LCBCR5; /* LCBCR5 */ + volatile uint32_t LCBCR6; /* LCBCR6 */ + volatile uint32_t LCBCR7; /* LCBCR7 */ + volatile uint32_t LCBCR8; /* LCBCR8 */ + volatile uint32_t LCBCR9; /* LCBCR9 */ + volatile uint32_t LCBCR10; /* LCBCR10 */ + volatile uint32_t LCBCR11; /* LCBCR11 */ + volatile uint32_t LCBCR12; /* LCBCR12 */ + volatile uint32_t LCBCR13; /* LCBCR13 */ + volatile uint32_t LCBCR14; /* LCBCR14 */ + volatile uint32_t LCBCR15; /* LCBCR15 */ + volatile uint32_t LCBCR16; /* LCBCR16 */ + volatile uint32_t LCBCR17; /* LCBCR17 */ + volatile uint32_t LCBCR18; /* LCBCR18 */ + volatile uint32_t LCBCR19; /* LCBCR19 */ + volatile uint32_t LCBCR20; /* LCBCR20 */ + volatile uint32_t LCBCR21; /* LCBCR21 */ + volatile uint32_t LCBCR22; /* LCBCR22 */ + volatile uint32_t LCBCR23; /* LCBCR23 */ + volatile uint32_t LCBCR24; /* LCBCR24 */ + volatile uint32_t LCBCR25; /* LCBCR25 */ + volatile uint32_t LCBCR26; /* LCBCR26 */ + volatile uint32_t LCBCR27; /* LCBCR27 */ + volatile uint32_t LCBCR28; /* LCBCR28 */ + volatile uint32_t LCBCR29; /* LCBCR29 */ + volatile uint32_t LCBCR30; /* LCBCR30 */ +}; + + +struct st_mlb_from_cecr0 +{ + volatile uint32_t CECR0; /* CECR0 */ + volatile uint32_t CSCR0; /* CSCR0 */ + volatile uint32_t CCBCR0; /* CCBCR0 */ + volatile uint32_t CNBCR0; /* CNBCR0 */ +}; + + +#define MLB (*(struct st_mlb *)0xE8034000uL) /* MLB */ + + +/* Start of channnel array defines of MLB */ + +/* Channnel array defines of MLB_FROM_CECR0_ARRAY */ +/*(Sample) value = MLB_FROM_CECR0_ARRAY[ channel ]->CECR0; */ +#define MLB_FROM_CECR0_ARRAY_COUNT 31 +#define MLB_FROM_CECR0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &MLB_FROM_CECR0, &MLB_FROM_CECR1, &MLB_FROM_CECR2, &MLB_FROM_CECR3, &MLB_FROM_CECR4, &MLB_FROM_CECR5, &MLB_FROM_CECR6, &MLB_FROM_CECR7, \ + &MLB_FROM_CECR8, &MLB_FROM_CECR9, &MLB_FROM_CECR10, &MLB_FROM_CECR11, &MLB_FROM_CECR12, &MLB_FROM_CECR13, &MLB_FROM_CECR14, &MLB_FROM_CECR15, \ + &MLB_FROM_CECR16, &MLB_FROM_CECR17, &MLB_FROM_CECR18, &MLB_FROM_CECR19, &MLB_FROM_CECR20, &MLB_FROM_CECR21, &MLB_FROM_CECR22, &MLB_FROM_CECR23, \ + &MLB_FROM_CECR24, &MLB_FROM_CECR25, &MLB_FROM_CECR26, &MLB_FROM_CECR27, &MLB_FROM_CECR28, &MLB_FROM_CECR29, &MLB_FROM_CECR30 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define MLB_FROM_CECR0 (*(struct st_mlb_from_cecr0 *)&MLB.CECR0) /* MLB_FROM_CECR0 */ +#define MLB_FROM_CECR1 (*(struct st_mlb_from_cecr0 *)&MLB.CECR1) /* MLB_FROM_CECR1 */ +#define MLB_FROM_CECR2 (*(struct st_mlb_from_cecr0 *)&MLB.CECR2) /* MLB_FROM_CECR2 */ +#define MLB_FROM_CECR3 (*(struct st_mlb_from_cecr0 *)&MLB.CECR3) /* MLB_FROM_CECR3 */ +#define MLB_FROM_CECR4 (*(struct st_mlb_from_cecr0 *)&MLB.CECR4) /* MLB_FROM_CECR4 */ +#define MLB_FROM_CECR5 (*(struct st_mlb_from_cecr0 *)&MLB.CECR5) /* MLB_FROM_CECR5 */ +#define MLB_FROM_CECR6 (*(struct st_mlb_from_cecr0 *)&MLB.CECR6) /* MLB_FROM_CECR6 */ +#define MLB_FROM_CECR7 (*(struct st_mlb_from_cecr0 *)&MLB.CECR7) /* MLB_FROM_CECR7 */ +#define MLB_FROM_CECR8 (*(struct st_mlb_from_cecr0 *)&MLB.CECR8) /* MLB_FROM_CECR8 */ +#define MLB_FROM_CECR9 (*(struct st_mlb_from_cecr0 *)&MLB.CECR9) /* MLB_FROM_CECR9 */ +#define MLB_FROM_CECR10 (*(struct st_mlb_from_cecr0 *)&MLB.CECR10) /* MLB_FROM_CECR10 */ +#define MLB_FROM_CECR11 (*(struct st_mlb_from_cecr0 *)&MLB.CECR11) /* MLB_FROM_CECR11 */ +#define MLB_FROM_CECR12 (*(struct st_mlb_from_cecr0 *)&MLB.CECR12) /* MLB_FROM_CECR12 */ +#define MLB_FROM_CECR13 (*(struct st_mlb_from_cecr0 *)&MLB.CECR13) /* MLB_FROM_CECR13 */ +#define MLB_FROM_CECR14 (*(struct st_mlb_from_cecr0 *)&MLB.CECR14) /* MLB_FROM_CECR14 */ +#define MLB_FROM_CECR15 (*(struct st_mlb_from_cecr0 *)&MLB.CECR15) /* MLB_FROM_CECR15 */ +#define MLB_FROM_CECR16 (*(struct st_mlb_from_cecr0 *)&MLB.CECR16) /* MLB_FROM_CECR16 */ +#define MLB_FROM_CECR17 (*(struct st_mlb_from_cecr0 *)&MLB.CECR17) /* MLB_FROM_CECR17 */ +#define MLB_FROM_CECR18 (*(struct st_mlb_from_cecr0 *)&MLB.CECR18) /* MLB_FROM_CECR18 */ +#define MLB_FROM_CECR19 (*(struct st_mlb_from_cecr0 *)&MLB.CECR19) /* MLB_FROM_CECR19 */ +#define MLB_FROM_CECR20 (*(struct st_mlb_from_cecr0 *)&MLB.CECR20) /* MLB_FROM_CECR20 */ +#define MLB_FROM_CECR21 (*(struct st_mlb_from_cecr0 *)&MLB.CECR21) /* MLB_FROM_CECR21 */ +#define MLB_FROM_CECR22 (*(struct st_mlb_from_cecr0 *)&MLB.CECR22) /* MLB_FROM_CECR22 */ +#define MLB_FROM_CECR23 (*(struct st_mlb_from_cecr0 *)&MLB.CECR23) /* MLB_FROM_CECR23 */ +#define MLB_FROM_CECR24 (*(struct st_mlb_from_cecr0 *)&MLB.CECR24) /* MLB_FROM_CECR24 */ +#define MLB_FROM_CECR25 (*(struct st_mlb_from_cecr0 *)&MLB.CECR25) /* MLB_FROM_CECR25 */ +#define MLB_FROM_CECR26 (*(struct st_mlb_from_cecr0 *)&MLB.CECR26) /* MLB_FROM_CECR26 */ +#define MLB_FROM_CECR27 (*(struct st_mlb_from_cecr0 *)&MLB.CECR27) /* MLB_FROM_CECR27 */ +#define MLB_FROM_CECR28 (*(struct st_mlb_from_cecr0 *)&MLB.CECR28) /* MLB_FROM_CECR28 */ +#define MLB_FROM_CECR29 (*(struct st_mlb_from_cecr0 *)&MLB.CECR29) /* MLB_FROM_CECR29 */ +#define MLB_FROM_CECR30 (*(struct st_mlb_from_cecr0 *)&MLB.CECR30) /* MLB_FROM_CECR30 */ + +/* End of channnel array defines of MLB */ + + +#define MLBDCCR MLB.DCCR +#define MLBSSCR MLB.SSCR +#define MLBSDCR MLB.SDCR +#define MLBSMCR MLB.SMCR +#define MLBVCCR MLB.VCCR +#define MLBSBCR MLB.SBCR +#define MLBABCR MLB.ABCR +#define MLBCBCR MLB.CBCR +#define MLBIBCR MLB.IBCR +#define MLBCICR MLB.CICR +#define MLBCECR0 MLB.CECR0 +#define MLBCSCR0 MLB.CSCR0 +#define MLBCCBCR0 MLB.CCBCR0 +#define MLBCNBCR0 MLB.CNBCR0 +#define MLBCECR1 MLB.CECR1 +#define MLBCSCR1 MLB.CSCR1 +#define MLBCCBCR1 MLB.CCBCR1 +#define MLBCNBCR1 MLB.CNBCR1 +#define MLBCECR2 MLB.CECR2 +#define MLBCSCR2 MLB.CSCR2 +#define MLBCCBCR2 MLB.CCBCR2 +#define MLBCNBCR2 MLB.CNBCR2 +#define MLBCECR3 MLB.CECR3 +#define MLBCSCR3 MLB.CSCR3 +#define MLBCCBCR3 MLB.CCBCR3 +#define MLBCNBCR3 MLB.CNBCR3 +#define MLBCECR4 MLB.CECR4 +#define MLBCSCR4 MLB.CSCR4 +#define MLBCCBCR4 MLB.CCBCR4 +#define MLBCNBCR4 MLB.CNBCR4 +#define MLBCECR5 MLB.CECR5 +#define MLBCSCR5 MLB.CSCR5 +#define MLBCCBCR5 MLB.CCBCR5 +#define MLBCNBCR5 MLB.CNBCR5 +#define MLBCECR6 MLB.CECR6 +#define MLBCSCR6 MLB.CSCR6 +#define MLBCCBCR6 MLB.CCBCR6 +#define MLBCNBCR6 MLB.CNBCR6 +#define MLBCECR7 MLB.CECR7 +#define MLBCSCR7 MLB.CSCR7 +#define MLBCCBCR7 MLB.CCBCR7 +#define MLBCNBCR7 MLB.CNBCR7 +#define MLBCECR8 MLB.CECR8 +#define MLBCSCR8 MLB.CSCR8 +#define MLBCCBCR8 MLB.CCBCR8 +#define MLBCNBCR8 MLB.CNBCR8 +#define MLBCECR9 MLB.CECR9 +#define MLBCSCR9 MLB.CSCR9 +#define MLBCCBCR9 MLB.CCBCR9 +#define MLBCNBCR9 MLB.CNBCR9 +#define MLBCECR10 MLB.CECR10 +#define MLBCSCR10 MLB.CSCR10 +#define MLBCCBCR10 MLB.CCBCR10 +#define MLBCNBCR10 MLB.CNBCR10 +#define MLBCECR11 MLB.CECR11 +#define MLBCSCR11 MLB.CSCR11 +#define MLBCCBCR11 MLB.CCBCR11 +#define MLBCNBCR11 MLB.CNBCR11 +#define MLBCECR12 MLB.CECR12 +#define MLBCSCR12 MLB.CSCR12 +#define MLBCCBCR12 MLB.CCBCR12 +#define MLBCNBCR12 MLB.CNBCR12 +#define MLBCECR13 MLB.CECR13 +#define MLBCSCR13 MLB.CSCR13 +#define MLBCCBCR13 MLB.CCBCR13 +#define MLBCNBCR13 MLB.CNBCR13 +#define MLBCECR14 MLB.CECR14 +#define MLBCSCR14 MLB.CSCR14 +#define MLBCCBCR14 MLB.CCBCR14 +#define MLBCNBCR14 MLB.CNBCR14 +#define MLBCECR15 MLB.CECR15 +#define MLBCSCR15 MLB.CSCR15 +#define MLBCCBCR15 MLB.CCBCR15 +#define MLBCNBCR15 MLB.CNBCR15 +#define MLBCECR16 MLB.CECR16 +#define MLBCSCR16 MLB.CSCR16 +#define MLBCCBCR16 MLB.CCBCR16 +#define MLBCNBCR16 MLB.CNBCR16 +#define MLBCECR17 MLB.CECR17 +#define MLBCSCR17 MLB.CSCR17 +#define MLBCCBCR17 MLB.CCBCR17 +#define MLBCNBCR17 MLB.CNBCR17 +#define MLBCECR18 MLB.CECR18 +#define MLBCSCR18 MLB.CSCR18 +#define MLBCCBCR18 MLB.CCBCR18 +#define MLBCNBCR18 MLB.CNBCR18 +#define MLBCECR19 MLB.CECR19 +#define MLBCSCR19 MLB.CSCR19 +#define MLBCCBCR19 MLB.CCBCR19 +#define MLBCNBCR19 MLB.CNBCR19 +#define MLBCECR20 MLB.CECR20 +#define MLBCSCR20 MLB.CSCR20 +#define MLBCCBCR20 MLB.CCBCR20 +#define MLBCNBCR20 MLB.CNBCR20 +#define MLBCECR21 MLB.CECR21 +#define MLBCSCR21 MLB.CSCR21 +#define MLBCCBCR21 MLB.CCBCR21 +#define MLBCNBCR21 MLB.CNBCR21 +#define MLBCECR22 MLB.CECR22 +#define MLBCSCR22 MLB.CSCR22 +#define MLBCCBCR22 MLB.CCBCR22 +#define MLBCNBCR22 MLB.CNBCR22 +#define MLBCECR23 MLB.CECR23 +#define MLBCSCR23 MLB.CSCR23 +#define MLBCCBCR23 MLB.CCBCR23 +#define MLBCNBCR23 MLB.CNBCR23 +#define MLBCECR24 MLB.CECR24 +#define MLBCSCR24 MLB.CSCR24 +#define MLBCCBCR24 MLB.CCBCR24 +#define MLBCNBCR24 MLB.CNBCR24 +#define MLBCECR25 MLB.CECR25 +#define MLBCSCR25 MLB.CSCR25 +#define MLBCCBCR25 MLB.CCBCR25 +#define MLBCNBCR25 MLB.CNBCR25 +#define MLBCECR26 MLB.CECR26 +#define MLBCSCR26 MLB.CSCR26 +#define MLBCCBCR26 MLB.CCBCR26 +#define MLBCNBCR26 MLB.CNBCR26 +#define MLBCECR27 MLB.CECR27 +#define MLBCSCR27 MLB.CSCR27 +#define MLBCCBCR27 MLB.CCBCR27 +#define MLBCNBCR27 MLB.CNBCR27 +#define MLBCECR28 MLB.CECR28 +#define MLBCSCR28 MLB.CSCR28 +#define MLBCCBCR28 MLB.CCBCR28 +#define MLBCNBCR28 MLB.CNBCR28 +#define MLBCECR29 MLB.CECR29 +#define MLBCSCR29 MLB.CSCR29 +#define MLBCCBCR29 MLB.CCBCR29 +#define MLBCNBCR29 MLB.CNBCR29 +#define MLBCECR30 MLB.CECR30 +#define MLBCSCR30 MLB.CSCR30 +#define MLBCCBCR30 MLB.CCBCR30 +#define MLBCNBCR30 MLB.CNBCR30 +#define MLBLCBCR0 MLB.LCBCR0 +#define MLBLCBCR1 MLB.LCBCR1 +#define MLBLCBCR2 MLB.LCBCR2 +#define MLBLCBCR3 MLB.LCBCR3 +#define MLBLCBCR4 MLB.LCBCR4 +#define MLBLCBCR5 MLB.LCBCR5 +#define MLBLCBCR6 MLB.LCBCR6 +#define MLBLCBCR7 MLB.LCBCR7 +#define MLBLCBCR8 MLB.LCBCR8 +#define MLBLCBCR9 MLB.LCBCR9 +#define MLBLCBCR10 MLB.LCBCR10 +#define MLBLCBCR11 MLB.LCBCR11 +#define MLBLCBCR12 MLB.LCBCR12 +#define MLBLCBCR13 MLB.LCBCR13 +#define MLBLCBCR14 MLB.LCBCR14 +#define MLBLCBCR15 MLB.LCBCR15 +#define MLBLCBCR16 MLB.LCBCR16 +#define MLBLCBCR17 MLB.LCBCR17 +#define MLBLCBCR18 MLB.LCBCR18 +#define MLBLCBCR19 MLB.LCBCR19 +#define MLBLCBCR20 MLB.LCBCR20 +#define MLBLCBCR21 MLB.LCBCR21 +#define MLBLCBCR22 MLB.LCBCR22 +#define MLBLCBCR23 MLB.LCBCR23 +#define MLBLCBCR24 MLB.LCBCR24 +#define MLBLCBCR25 MLB.LCBCR25 +#define MLBLCBCR26 MLB.LCBCR26 +#define MLBLCBCR27 MLB.LCBCR27 +#define MLBLCBCR28 MLB.LCBCR28 +#define MLBLCBCR29 MLB.LCBCR29 +#define MLBLCBCR30 MLB.LCBCR30 +/* <-SEC M1.10.1 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/mmc_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,92 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : mmc_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef MMC_IODEFINE_H +#define MMC_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_mmc +{ /* MMC */ + volatile uint16_t CE_CMD_SETH; /* CE_CMD_SETH */ + volatile uint16_t CE_CMD_SETL; /* CE_CMD_SETL */ + volatile uint8_t dummy182[4]; /* */ + volatile uint32_t CE_ARG; /* CE_ARG */ + volatile uint32_t CE_ARG_CMD12; /* CE_ARG_CMD12 */ + volatile uint32_t CE_CMD_CTRL; /* CE_CMD_CTRL */ + volatile uint32_t CE_BLOCK_SET; /* CE_BLOCK_SET */ + volatile uint32_t CE_CLK_CTRL; /* CE_CLK_CTRL */ + volatile uint32_t CE_BUF_ACC; /* CE_BUF_ACC */ +#define MMC_CE_RESPn_COUNT 4 + volatile uint32_t CE_RESP3; /* CE_RESP3 */ + volatile uint32_t CE_RESP2; /* CE_RESP2 */ + volatile uint32_t CE_RESP1; /* CE_RESP1 */ + volatile uint32_t CE_RESP0; /* CE_RESP0 */ + volatile uint32_t CE_RESP_CMD12; /* CE_RESP_CMD12 */ + volatile uint32_t CE_DATA; /* CE_DATA */ + volatile uint8_t dummy183[8]; /* */ + volatile uint32_t CE_INT; /* CE_INT */ + volatile uint32_t CE_INT_EN; /* CE_INT_EN */ + volatile uint32_t CE_HOST_STS1; /* CE_HOST_STS1 */ + volatile uint32_t CE_HOST_STS2; /* CE_HOST_STS2 */ + volatile uint8_t dummy184[12]; /* */ + volatile uint32_t CE_DMA_MODE; /* CE_DMA_MODE */ + volatile uint8_t dummy185[16]; /* */ + volatile uint32_t CE_DETECT; /* CE_DETECT */ + volatile uint32_t CE_ADD_MODE; /* CE_ADD_MODE */ + volatile uint8_t dummy186[4]; /* */ + volatile uint32_t CE_VERSION; /* CE_VERSION */ +}; + + +#define MMC (*(struct st_mmc *)0xE804C800uL) /* MMC */ + + +#define MMCCE_CMD_SETH MMC.CE_CMD_SETH +#define MMCCE_CMD_SETL MMC.CE_CMD_SETL +#define MMCCE_ARG MMC.CE_ARG +#define MMCCE_ARG_CMD12 MMC.CE_ARG_CMD12 +#define MMCCE_CMD_CTRL MMC.CE_CMD_CTRL +#define MMCCE_BLOCK_SET MMC.CE_BLOCK_SET +#define MMCCE_CLK_CTRL MMC.CE_CLK_CTRL +#define MMCCE_BUF_ACC MMC.CE_BUF_ACC +#define MMCCE_RESP3 MMC.CE_RESP3 +#define MMCCE_RESP2 MMC.CE_RESP2 +#define MMCCE_RESP1 MMC.CE_RESP1 +#define MMCCE_RESP0 MMC.CE_RESP0 +#define MMCCE_RESP_CMD12 MMC.CE_RESP_CMD12 +#define MMCCE_DATA MMC.CE_DATA +#define MMCCE_INT MMC.CE_INT +#define MMCCE_INT_EN MMC.CE_INT_EN +#define MMCCE_HOST_STS1 MMC.CE_HOST_STS1 +#define MMCCE_HOST_STS2 MMC.CE_HOST_STS2 +#define MMCCE_DMA_MODE MMC.CE_DMA_MODE +#define MMCCE_DETECT MMC.CE_DETECT +#define MMCCE_ADD_MODE MMC.CE_ADD_MODE +#define MMCCE_VERSION MMC.CE_VERSION +/* <-SEC M1.10.1 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/mtu2_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,217 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : mtu2_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef MTU2_IODEFINE_H +#define MTU2_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_mtu2 +{ /* MTU2 */ + volatile uint8_t TCR_2; /* TCR_2 */ + volatile uint8_t TMDR_2; /* TMDR_2 */ + volatile uint8_t TIOR_2; /* TIOR_2 */ + volatile uint8_t dummy520[1]; /* */ + volatile uint8_t TIER_2; /* TIER_2 */ + volatile uint8_t TSR_2; /* TSR_2 */ + volatile uint16_t TCNT_2; /* TCNT_2 */ + volatile uint16_t TGRA_2; /* TGRA_2 */ + volatile uint16_t TGRB_2; /* TGRB_2 */ + volatile uint8_t dummy521[500]; /* */ + volatile uint8_t TCR_3; /* TCR_3 */ + volatile uint8_t TCR_4; /* TCR_4 */ + volatile uint8_t TMDR_3; /* TMDR_3 */ + volatile uint8_t TMDR_4; /* TMDR_4 */ + volatile uint8_t TIORH_3; /* TIORH_3 */ + volatile uint8_t TIORL_3; /* TIORL_3 */ + volatile uint8_t TIORH_4; /* TIORH_4 */ + volatile uint8_t TIORL_4; /* TIORL_4 */ + volatile uint8_t TIER_3; /* TIER_3 */ + volatile uint8_t TIER_4; /* TIER_4 */ + volatile uint8_t TOER; /* TOER */ + volatile uint8_t dummy522[2]; /* */ + volatile uint8_t TGCR; /* TGCR */ + volatile uint8_t TOCR1; /* TOCR1 */ + volatile uint8_t TOCR2; /* TOCR2 */ + volatile uint16_t TCNT_3; /* TCNT_3 */ + volatile uint16_t TCNT_4; /* TCNT_4 */ + volatile uint16_t TCDR; /* TCDR */ + volatile uint16_t TDDR; /* TDDR */ + volatile uint16_t TGRA_3; /* TGRA_3 */ + volatile uint16_t TGRB_3; /* TGRB_3 */ + volatile uint16_t TGRA_4; /* TGRA_4 */ + volatile uint16_t TGRB_4; /* TGRB_4 */ + volatile uint16_t TCNTS; /* TCNTS */ + volatile uint16_t TCBR; /* TCBR */ + volatile uint16_t TGRC_3; /* TGRC_3 */ + volatile uint16_t TGRD_3; /* TGRD_3 */ + volatile uint16_t TGRC_4; /* TGRC_4 */ + volatile uint16_t TGRD_4; /* TGRD_4 */ + volatile uint8_t TSR_3; /* TSR_3 */ + volatile uint8_t TSR_4; /* TSR_4 */ + volatile uint8_t dummy523[2]; /* */ + volatile uint8_t TITCR; /* TITCR */ + volatile uint8_t TITCNT; /* TITCNT */ + volatile uint8_t TBTER; /* TBTER */ + volatile uint8_t dummy524[1]; /* */ + volatile uint8_t TDER; /* TDER */ + volatile uint8_t dummy525[1]; /* */ + volatile uint8_t TOLBR; /* TOLBR */ + volatile uint8_t dummy526[1]; /* */ + volatile uint8_t TBTM_3; /* TBTM_3 */ + volatile uint8_t TBTM_4; /* TBTM_4 */ + volatile uint8_t dummy527[6]; /* */ + volatile uint16_t TADCR; /* TADCR */ + volatile uint8_t dummy528[2]; /* */ + volatile uint16_t TADCORA_4; /* TADCORA_4 */ + volatile uint16_t TADCORB_4; /* TADCORB_4 */ + volatile uint16_t TADCOBRA_4; /* TADCOBRA_4 */ + volatile uint16_t TADCOBRB_4; /* TADCOBRB_4 */ + volatile uint8_t dummy529[20]; /* */ + volatile uint8_t TWCR; /* TWCR */ + volatile uint8_t dummy530[31]; /* */ + volatile uint8_t TSTR; /* TSTR */ + volatile uint8_t TSYR; /* TSYR */ + volatile uint8_t dummy531[2]; /* */ + volatile uint8_t TRWER; /* TRWER */ + volatile uint8_t dummy532[123]; /* */ + volatile uint8_t TCR_0; /* TCR_0 */ + volatile uint8_t TMDR_0; /* TMDR_0 */ + volatile uint8_t TIORH_0; /* TIORH_0 */ + volatile uint8_t TIORL_0; /* TIORL_0 */ + volatile uint8_t TIER_0; /* TIER_0 */ + volatile uint8_t TSR_0; /* TSR_0 */ + volatile uint16_t TCNT_0; /* TCNT_0 */ + volatile uint16_t TGRA_0; /* TGRA_0 */ + volatile uint16_t TGRB_0; /* TGRB_0 */ + volatile uint16_t TGRC_0; /* TGRC_0 */ + volatile uint16_t TGRD_0; /* TGRD_0 */ + volatile uint8_t dummy533[16]; /* */ + volatile uint16_t TGRE_0; /* TGRE_0 */ + volatile uint16_t TGRF_0; /* TGRF_0 */ + volatile uint8_t TIER2_0; /* TIER2_0 */ + volatile uint8_t TSR2_0; /* TSR2_0 */ + volatile uint8_t TBTM_0; /* TBTM_0 */ + volatile uint8_t dummy534[89]; /* */ + volatile uint8_t TCR_1; /* TCR_1 */ + volatile uint8_t TMDR_1; /* TMDR_1 */ + volatile uint8_t TIOR_1; /* TIOR_1 */ + volatile uint8_t dummy535[1]; /* */ + volatile uint8_t TIER_1; /* TIER_1 */ + volatile uint8_t TSR_1; /* TSR_1 */ + volatile uint16_t TCNT_1; /* TCNT_1 */ + volatile uint16_t TGRA_1; /* TGRA_1 */ + volatile uint16_t TGRB_1; /* TGRB_1 */ + volatile uint8_t dummy536[4]; /* */ + volatile uint8_t TICCR; /* TICCR */ +}; + + +#define MTU2 (*(struct st_mtu2 *)0xFCFF0000uL) /* MTU2 */ + + +#define MTU2TCR_2 MTU2.TCR_2 +#define MTU2TMDR_2 MTU2.TMDR_2 +#define MTU2TIOR_2 MTU2.TIOR_2 +#define MTU2TIER_2 MTU2.TIER_2 +#define MTU2TSR_2 MTU2.TSR_2 +#define MTU2TCNT_2 MTU2.TCNT_2 +#define MTU2TGRA_2 MTU2.TGRA_2 +#define MTU2TGRB_2 MTU2.TGRB_2 +#define MTU2TCR_3 MTU2.TCR_3 +#define MTU2TCR_4 MTU2.TCR_4 +#define MTU2TMDR_3 MTU2.TMDR_3 +#define MTU2TMDR_4 MTU2.TMDR_4 +#define MTU2TIORH_3 MTU2.TIORH_3 +#define MTU2TIORL_3 MTU2.TIORL_3 +#define MTU2TIORH_4 MTU2.TIORH_4 +#define MTU2TIORL_4 MTU2.TIORL_4 +#define MTU2TIER_3 MTU2.TIER_3 +#define MTU2TIER_4 MTU2.TIER_4 +#define MTU2TOER MTU2.TOER +#define MTU2TGCR MTU2.TGCR +#define MTU2TOCR1 MTU2.TOCR1 +#define MTU2TOCR2 MTU2.TOCR2 +#define MTU2TCNT_3 MTU2.TCNT_3 +#define MTU2TCNT_4 MTU2.TCNT_4 +#define MTU2TCDR MTU2.TCDR +#define MTU2TDDR MTU2.TDDR +#define MTU2TGRA_3 MTU2.TGRA_3 +#define MTU2TGRB_3 MTU2.TGRB_3 +#define MTU2TGRA_4 MTU2.TGRA_4 +#define MTU2TGRB_4 MTU2.TGRB_4 +#define MTU2TCNTS MTU2.TCNTS +#define MTU2TCBR MTU2.TCBR +#define MTU2TGRC_3 MTU2.TGRC_3 +#define MTU2TGRD_3 MTU2.TGRD_3 +#define MTU2TGRC_4 MTU2.TGRC_4 +#define MTU2TGRD_4 MTU2.TGRD_4 +#define MTU2TSR_3 MTU2.TSR_3 +#define MTU2TSR_4 MTU2.TSR_4 +#define MTU2TITCR MTU2.TITCR +#define MTU2TITCNT MTU2.TITCNT +#define MTU2TBTER MTU2.TBTER +#define MTU2TDER MTU2.TDER +#define MTU2TOLBR MTU2.TOLBR +#define MTU2TBTM_3 MTU2.TBTM_3 +#define MTU2TBTM_4 MTU2.TBTM_4 +#define MTU2TADCR MTU2.TADCR +#define MTU2TADCORA_4 MTU2.TADCORA_4 +#define MTU2TADCORB_4 MTU2.TADCORB_4 +#define MTU2TADCOBRA_4 MTU2.TADCOBRA_4 +#define MTU2TADCOBRB_4 MTU2.TADCOBRB_4 +#define MTU2TWCR MTU2.TWCR +#define MTU2TSTR MTU2.TSTR +#define MTU2TSYR MTU2.TSYR +#define MTU2TRWER MTU2.TRWER +#define MTU2TCR_0 MTU2.TCR_0 +#define MTU2TMDR_0 MTU2.TMDR_0 +#define MTU2TIORH_0 MTU2.TIORH_0 +#define MTU2TIORL_0 MTU2.TIORL_0 +#define MTU2TIER_0 MTU2.TIER_0 +#define MTU2TSR_0 MTU2.TSR_0 +#define MTU2TCNT_0 MTU2.TCNT_0 +#define MTU2TGRA_0 MTU2.TGRA_0 +#define MTU2TGRB_0 MTU2.TGRB_0 +#define MTU2TGRC_0 MTU2.TGRC_0 +#define MTU2TGRD_0 MTU2.TGRD_0 +#define MTU2TGRE_0 MTU2.TGRE_0 +#define MTU2TGRF_0 MTU2.TGRF_0 +#define MTU2TIER2_0 MTU2.TIER2_0 +#define MTU2TSR2_0 MTU2.TSR2_0 +#define MTU2TBTM_0 MTU2.TBTM_0 +#define MTU2TCR_1 MTU2.TCR_1 +#define MTU2TMDR_1 MTU2.TMDR_1 +#define MTU2TIOR_1 MTU2.TIOR_1 +#define MTU2TIER_1 MTU2.TIER_1 +#define MTU2TSR_1 MTU2.TSR_1 +#define MTU2TCNT_1 MTU2.TCNT_1 +#define MTU2TGRA_1 MTU2.TGRA_1 +#define MTU2TGRB_1 MTU2.TGRB_1 +#define MTU2TICCR MTU2.TICCR +/* <-SEC M1.10.1 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/ostm_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,78 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : ostm_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef OSTM_IODEFINE_H +#define OSTM_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_ostm +{ /* OSTM */ + volatile uint32_t OSTMnCMP; /* OSTMnCMP */ + volatile uint32_t OSTMnCNT; /* OSTMnCNT */ + volatile uint8_t dummy1[8]; /* */ + volatile uint8_t OSTMnTE; /* OSTMnTE */ + volatile uint8_t dummy2[3]; /* */ + volatile uint8_t OSTMnTS; /* OSTMnTS */ + volatile uint8_t dummy3[3]; /* */ + volatile uint8_t OSTMnTT; /* OSTMnTT */ + volatile uint8_t dummy4[7]; /* */ + volatile uint8_t OSTMnCTL; /* OSTMnCTL */ +}; + + +#define OSTM0 (*(struct st_ostm *)0xFCFEC000uL) /* OSTM0 */ +#define OSTM1 (*(struct st_ostm *)0xFCFEC400uL) /* OSTM1 */ + + +/* Start of channnel array defines of OSTM */ + +/* Channnel array defines of OSTM */ +/*(Sample) value = OSTM[ channel ]->OSTMnCMP; */ +#define OSTM_COUNT 2 +#define OSTM_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &OSTM0, &OSTM1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channnel array defines of OSTM */ + + +#define OSTM0CMP OSTM0.OSTMnCMP +#define OSTM0CNT OSTM0.OSTMnCNT +#define OSTM0TE OSTM0.OSTMnTE +#define OSTM0TS OSTM0.OSTMnTS +#define OSTM0TT OSTM0.OSTMnTT +#define OSTM0CTL OSTM0.OSTMnCTL +#define OSTM1CMP OSTM1.OSTMnCMP +#define OSTM1CNT OSTM1.OSTMnCNT +#define OSTM1TE OSTM1.OSTMnTE +#define OSTM1TS OSTM1.OSTMnTS +#define OSTM1TT OSTM1.OSTMnTT +#define OSTM1CTL OSTM1.OSTMnCTL +/* <-SEC M1.10.1 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/pfv_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,150 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : pfv_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef PFV_IODEFINE_H +#define PFV_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_pfv +{ /* PFV */ + volatile uint32_t PFVCR; /* PFVCR */ + volatile uint32_t PFVICR; /* PFVICR */ + volatile uint32_t PFVISR; /* PFVISR */ + volatile uint8_t dummy1[20]; /* */ +#define PFVID_COUNT 8 + volatile uint32_t PFVID0; /* PFVID0 */ + volatile uint32_t PFVID1; /* PFVID1 */ + volatile uint32_t PFVID2; /* PFVID2 */ + volatile uint32_t PFVID3; /* PFVID3 */ + volatile uint32_t PFVID4; /* PFVID4 */ + volatile uint32_t PFVID5; /* PFVID5 */ + volatile uint32_t PFVID6; /* PFVID6 */ + volatile uint32_t PFVID7; /* PFVID7 */ +#define PFVOD_COUNT 8 + volatile uint32_t PFVOD0; /* PFVOD0 */ + volatile uint32_t PFVOD1; /* PFVOD1 */ + volatile uint32_t PFVOD2; /* PFVOD2 */ + volatile uint32_t PFVOD3; /* PFVOD3 */ + volatile uint32_t PFVOD4; /* PFVOD4 */ + volatile uint32_t PFVOD5; /* PFVOD5 */ + volatile uint32_t PFVOD6; /* PFVOD6 */ + volatile uint32_t PFVOD7; /* PFVOD7 */ + volatile uint8_t dummy2[4]; /* */ + volatile uint32_t PFVIFSR; /* PFVIFSR */ + volatile uint32_t PFVOFSR; /* PFVOFSR */ + volatile uint32_t PFVACR; /* PFVACR */ + volatile uint32_t PFV_MTX_MODE; /* PFV_MTX_MODE */ + volatile uint32_t PFV_MTX_YG_ADJ0; /* PFV_MTX_YG_ADJ0 */ + volatile uint32_t PFV_MTX_YG_ADJ1; /* PFV_MTX_YG_ADJ1 */ + volatile uint32_t PFV_MTX_CBB_ADJ0; /* PFV_MTX_CBB_ADJ0 */ + volatile uint32_t PFV_MTX_CBB_ADJ1; /* PFV_MTX_CBB_ADJ1 */ + volatile uint32_t PFV_MTX_CRR_ADJ0; /* PFV_MTX_CRR_ADJ0 */ + volatile uint32_t PFV_MTX_CRR_ADJ1; /* PFV_MTX_CRR_ADJ1 */ + volatile uint32_t PFVSZR; /* PFVSZR */ +}; + + +#define PFV0 (*(struct st_pfv *)0xE8205000uL) /* PFV0 */ +#define PFV1 (*(struct st_pfv *)0xE8205800uL) /* PFV1 */ + + +/* Start of channnel array defines of PFV */ + +/* Channnel array defines of PFV */ +/*(Sample) value = PFV[ channel ]->PFVCR; */ +#define PFV_COUNT 2 +#define PFV_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &PFV0, &PFV1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channnel array defines of PFV */ + + +#define PFV0PFVCR PFV0.PFVCR +#define PFV0PFVICR PFV0.PFVICR +#define PFV0PFVISR PFV0.PFVISR +#define PFV0PFVID0 PFV0.PFVID0 +#define PFV0PFVID1 PFV0.PFVID1 +#define PFV0PFVID2 PFV0.PFVID2 +#define PFV0PFVID3 PFV0.PFVID3 +#define PFV0PFVID4 PFV0.PFVID4 +#define PFV0PFVID5 PFV0.PFVID5 +#define PFV0PFVID6 PFV0.PFVID6 +#define PFV0PFVID7 PFV0.PFVID7 +#define PFV0PFVOD0 PFV0.PFVOD0 +#define PFV0PFVOD1 PFV0.PFVOD1 +#define PFV0PFVOD2 PFV0.PFVOD2 +#define PFV0PFVOD3 PFV0.PFVOD3 +#define PFV0PFVOD4 PFV0.PFVOD4 +#define PFV0PFVOD5 PFV0.PFVOD5 +#define PFV0PFVOD6 PFV0.PFVOD6 +#define PFV0PFVOD7 PFV0.PFVOD7 +#define PFV0PFVIFSR PFV0.PFVIFSR +#define PFV0PFVOFSR PFV0.PFVOFSR +#define PFV0PFVACR PFV0.PFVACR +#define PFV0PFV_MTX_MODE PFV0.PFV_MTX_MODE +#define PFV0PFV_MTX_YG_ADJ0 PFV0.PFV_MTX_YG_ADJ0 +#define PFV0PFV_MTX_YG_ADJ1 PFV0.PFV_MTX_YG_ADJ1 +#define PFV0PFV_MTX_CBB_ADJ0 PFV0.PFV_MTX_CBB_ADJ0 +#define PFV0PFV_MTX_CBB_ADJ1 PFV0.PFV_MTX_CBB_ADJ1 +#define PFV0PFV_MTX_CRR_ADJ0 PFV0.PFV_MTX_CRR_ADJ0 +#define PFV0PFV_MTX_CRR_ADJ1 PFV0.PFV_MTX_CRR_ADJ1 +#define PFV0PFVSZR PFV0.PFVSZR +#define PFV1PFVCR PFV1.PFVCR +#define PFV1PFVICR PFV1.PFVICR +#define PFV1PFVISR PFV1.PFVISR +#define PFV1PFVID0 PFV1.PFVID0 +#define PFV1PFVID1 PFV1.PFVID1 +#define PFV1PFVID2 PFV1.PFVID2 +#define PFV1PFVID3 PFV1.PFVID3 +#define PFV1PFVID4 PFV1.PFVID4 +#define PFV1PFVID5 PFV1.PFVID5 +#define PFV1PFVID6 PFV1.PFVID6 +#define PFV1PFVID7 PFV1.PFVID7 +#define PFV1PFVOD0 PFV1.PFVOD0 +#define PFV1PFVOD1 PFV1.PFVOD1 +#define PFV1PFVOD2 PFV1.PFVOD2 +#define PFV1PFVOD3 PFV1.PFVOD3 +#define PFV1PFVOD4 PFV1.PFVOD4 +#define PFV1PFVOD5 PFV1.PFVOD5 +#define PFV1PFVOD6 PFV1.PFVOD6 +#define PFV1PFVOD7 PFV1.PFVOD7 +#define PFV1PFVIFSR PFV1.PFVIFSR +#define PFV1PFVOFSR PFV1.PFVOFSR +#define PFV1PFVACR PFV1.PFVACR +#define PFV1PFV_MTX_MODE PFV1.PFV_MTX_MODE +#define PFV1PFV_MTX_YG_ADJ0 PFV1.PFV_MTX_YG_ADJ0 +#define PFV1PFV_MTX_YG_ADJ1 PFV1.PFV_MTX_YG_ADJ1 +#define PFV1PFV_MTX_CBB_ADJ0 PFV1.PFV_MTX_CBB_ADJ0 +#define PFV1PFV_MTX_CBB_ADJ1 PFV1.PFV_MTX_CBB_ADJ1 +#define PFV1PFV_MTX_CRR_ADJ0 PFV1.PFV_MTX_CRR_ADJ0 +#define PFV1PFV_MTX_CRR_ADJ1 PFV1.PFV_MTX_CRR_ADJ1 +#define PFV1PFVSZR PFV1.PFVSZR +/* <-SEC M1.10.1 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/pwm_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,135 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : pwm_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef PWM_IODEFINE_H +#define PWM_IODEFINE_H +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +union reg16_8_t +{ + volatile uint16_t UINT16; /* 16-bit Access */ + volatile uint8_t UINT8[2]; /* 8-bit Access */ +}; + +struct st_pwm +{ /* PWM */ + volatile uint8_t dummy559[2]; /* */ + union reg16_8_t PWBTCR; /* PWBTCR */ + + volatile uint8_t dummy560[216]; /* */ + +/* start of struct st_pwm_common */ + union reg16_8_t PWCR_1; /* PWCR_1 */ + + volatile uint8_t dummy561[2]; /* */ + union reg16_8_t PWPR_1; /* PWPR_1 */ + + volatile uint16_t PWCYR_1; /* PWCYR_1 */ + volatile uint16_t PWBFR_1A; /* PWBFR_1A */ + volatile uint16_t PWBFR_1C; /* PWBFR_1C */ + volatile uint16_t PWBFR_1E; /* PWBFR_1E */ + volatile uint16_t PWBFR_1G; /* PWBFR_1G */ +/* end of struct st_pwm_common */ + +/* start of struct st_pwm_common */ + union reg16_8_t PWCR_2; /* PWCR_2 */ + + volatile uint8_t dummy562[2]; /* */ + union reg16_8_t PWPR_2; /* PWPR_2 */ + + volatile uint16_t PWCYR_2; /* PWCYR_2 */ + volatile uint16_t PWBFR_2A; /* PWBFR_2A */ + volatile uint16_t PWBFR_2C; /* PWBFR_2C */ + volatile uint16_t PWBFR_2E; /* PWBFR_2E */ + volatile uint16_t PWBFR_2G; /* PWBFR_2G */ +/* end of struct st_pwm_common */ +}; + + +struct st_pwm_common +{ + union reg16_8_t PWCR_1; /* PWCR_1 */ + + volatile uint8_t dummy572[2]; /* */ + union reg16_8_t PWPR_1; /* PWPR_1 */ + + volatile uint16_t PWCYR_1; /* PWCYR_1 */ + volatile uint16_t PWBFR_1A; /* PWBFR_1A */ + volatile uint16_t PWBFR_1C; /* PWBFR_1C */ + volatile uint16_t PWBFR_1E; /* PWBFR_1E */ + volatile uint16_t PWBFR_1G; /* PWBFR_1G */ +}; + + +#define PWM (*(struct st_pwm *)0xFCFF5004uL) /* PWM */ + + +/* Start of channnel array defines of PWM */ + +/* Channnel array defines of PWMn */ +/*(Sample) value = PWMn[ channel ]->PWCR_1.UINT16; */ +#define PWMn_COUNT 2 +#define PWMn_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &PWM1, &PWM2 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define PWM1 (*(struct st_pwm_common *)&PWM.PWCR_1) /* PWM1 */ +#define PWM2 (*(struct st_pwm_common *)&PWM.PWCR_2) /* PWM2 */ + +/* End of channnel array defines of PWM */ + + +#define PWMPWBTCR PWM.PWBTCR.UINT16 +#define PWMPWBTCR_BYTE_L PWM.PWBTCR.UINT8[0] +#define PWMPWBTCR_BYTE_H PWM.PWBTCR.UINT8[1] +#define PWMPWCR_1 PWM.PWCR_1.UINT16 +#define PWMPWCR_1_BYTE_L PWM.PWCR_1.UINT8[0] +#define PWMPWCR_1_BYTE_H PWM.PWCR_1.UINT8[1] +#define PWMPWPR_1 PWM.PWPR_1.UINT16 +#define PWMPWPR_1_BYTE_L PWM.PWPR_1.UINT8[0] +#define PWMPWPR_1_BYTE_H PWM.PWPR_1.UINT8[1] +#define PWMPWCYR_1 PWM.PWCYR_1 +#define PWMPWBFR_1A PWM.PWBFR_1A +#define PWMPWBFR_1C PWM.PWBFR_1C +#define PWMPWBFR_1E PWM.PWBFR_1E +#define PWMPWBFR_1G PWM.PWBFR_1G +#define PWMPWCR_2 PWM.PWCR_2.UINT16 +#define PWMPWCR_2_BYTE_L PWM.PWCR_2.UINT8[0] +#define PWMPWCR_2_BYTE_H PWM.PWCR_2.UINT8[1] +#define PWMPWPR_2 PWM.PWPR_2.UINT16 +#define PWMPWPR_2_BYTE_L PWM.PWPR_2.UINT8[0] +#define PWMPWPR_2_BYTE_H PWM.PWPR_2.UINT8[1] +#define PWMPWCYR_2 PWM.PWCYR_2 +#define PWMPWBFR_2A PWM.PWBFR_2A +#define PWMPWBFR_2C PWM.PWBFR_2C +#define PWMPWBFR_2E PWM.PWBFR_2E +#define PWMPWBFR_2G PWM.PWBFR_2G +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/riic_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,556 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : riic_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef RIIC_IODEFINE_H +#define RIIC_IODEFINE_H + +#include "reg32_t.h" + +struct st_riic +{ /* RIIC */ +#define RIICnCRm_COUNT 2 + union reg32_t RIICnCR1; /* RIICnCR1 */ + union reg32_t RIICnCR2; /* RIICnCR2 */ +#define RIICnMRm_COUNT 3 + union reg32_t RIICnMR1; /* RIICnMR1 */ + union reg32_t RIICnMR2; /* RIICnMR2 */ + union reg32_t RIICnMR3; /* RIICnMR3 */ + union reg32_t RIICnFER; /* RIICnFER */ + union reg32_t RIICnSER; /* RIICnSER */ + union reg32_t RIICnIER; /* RIICnIER */ +#define RIICnSRm_COUNT 2 + union reg32_t RIICnSR1; /* RIICnSR1 */ + union reg32_t RIICnSR2; /* RIICnSR2 */ +#define RIICnSARm_COUNT 3 + union reg32_t RIICnSAR0; /* RIICnSAR0 */ + union reg32_t RIICnSAR1; /* RIICnSAR1 */ + union reg32_t RIICnSAR2; /* RIICnSAR2 */ + union reg32_t RIICnBRL; /* RIICnBRL */ + union reg32_t RIICnBRH; /* RIICnBRH */ + union reg32_t RIICnDRT; /* RIICnDRT */ + union reg32_t RIICnDRR; /* RIICnDRR */ + +}; + + +#define RIIC0 (*(struct st_riic *)0xFCFEE000uL) /* RIIC0 */ +#define RIIC1 (*(struct st_riic *)0xFCFEE400uL) /* RIIC1 */ +#define RIIC2 (*(struct st_riic *)0xFCFEE800uL) /* RIIC2 */ +#define RIIC3 (*(struct st_riic *)0xFCFEEC00uL) /* RIIC3 */ + + +/* Start of channnel array defines of RIIC */ + +/* Channnel array defines of RIIC */ +/*(Sample) value = RIIC[ channel ]->RIICnCR1.UINT32; */ +#define RIIC_COUNT 4 +#define RIIC_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RIIC0, &RIIC1, &RIIC2, &RIIC3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channnel array defines of RIIC */ + + +#define RIIC0CR1 RIIC0.RIICnCR1.UINT32 +#define RIIC0CR1L RIIC0.RIICnCR1.UINT16[L] +#define RIIC0CR1LL RIIC0.RIICnCR1.UINT8[LL] +#define RIIC0CR1LH RIIC0.RIICnCR1.UINT8[LH] +#define RIIC0CR1H RIIC0.RIICnCR1.UINT16[H] +#define RIIC0CR1HL RIIC0.RIICnCR1.UINT8[HL] +#define RIIC0CR1HH RIIC0.RIICnCR1.UINT8[HH] +#define RIIC0CR2 RIIC0.RIICnCR2.UINT32 +#define RIIC0CR2L RIIC0.RIICnCR2.UINT16[L] +#define RIIC0CR2LL RIIC0.RIICnCR2.UINT8[LL] +#define RIIC0CR2LH RIIC0.RIICnCR2.UINT8[LH] +#define RIIC0CR2H RIIC0.RIICnCR2.UINT16[H] +#define RIIC0CR2HL RIIC0.RIICnCR2.UINT8[HL] +#define RIIC0CR2HH RIIC0.RIICnCR2.UINT8[HH] +#define RIIC0MR1 RIIC0.RIICnMR1.UINT32 +#define RIIC0MR1L RIIC0.RIICnMR1.UINT16[L] +#define RIIC0MR1LL RIIC0.RIICnMR1.UINT8[LL] +#define RIIC0MR1LH RIIC0.RIICnMR1.UINT8[LH] +#define RIIC0MR1H RIIC0.RIICnMR1.UINT16[H] +#define RIIC0MR1HL RIIC0.RIICnMR1.UINT8[HL] +#define RIIC0MR1HH RIIC0.RIICnMR1.UINT8[HH] +#define RIIC0MR2 RIIC0.RIICnMR2.UINT32 +#define RIIC0MR2L RIIC0.RIICnMR2.UINT16[L] +#define RIIC0MR2LL RIIC0.RIICnMR2.UINT8[LL] +#define RIIC0MR2LH RIIC0.RIICnMR2.UINT8[LH] +#define RIIC0MR2H RIIC0.RIICnMR2.UINT16[H] +#define RIIC0MR2HL RIIC0.RIICnMR2.UINT8[HL] +#define RIIC0MR2HH RIIC0.RIICnMR2.UINT8[HH] +#define RIIC0MR3 RIIC0.RIICnMR3.UINT32 +#define RIIC0MR3L RIIC0.RIICnMR3.UINT16[L] +#define RIIC0MR3LL RIIC0.RIICnMR3.UINT8[LL] +#define RIIC0MR3LH RIIC0.RIICnMR3.UINT8[LH] +#define RIIC0MR3H RIIC0.RIICnMR3.UINT16[H] +#define RIIC0MR3HL RIIC0.RIICnMR3.UINT8[HL] +#define RIIC0MR3HH RIIC0.RIICnMR3.UINT8[HH] +#define RIIC0FER RIIC0.RIICnFER.UINT32 +#define RIIC0FERL RIIC0.RIICnFER.UINT16[L] +#define RIIC0FERLL RIIC0.RIICnFER.UINT8[LL] +#define RIIC0FERLH RIIC0.RIICnFER.UINT8[LH] +#define RIIC0FERH RIIC0.RIICnFER.UINT16[H] +#define RIIC0FERHL RIIC0.RIICnFER.UINT8[HL] +#define RIIC0FERHH RIIC0.RIICnFER.UINT8[HH] +#define RIIC0SER RIIC0.RIICnSER.UINT32 +#define RIIC0SERL RIIC0.RIICnSER.UINT16[L] +#define RIIC0SERLL RIIC0.RIICnSER.UINT8[LL] +#define RIIC0SERLH RIIC0.RIICnSER.UINT8[LH] +#define RIIC0SERH RIIC0.RIICnSER.UINT16[H] +#define RIIC0SERHL RIIC0.RIICnSER.UINT8[HL] +#define RIIC0SERHH RIIC0.RIICnSER.UINT8[HH] +#define RIIC0IER RIIC0.RIICnIER.UINT32 +#define RIIC0IERL RIIC0.RIICnIER.UINT16[L] +#define RIIC0IERLL RIIC0.RIICnIER.UINT8[LL] +#define RIIC0IERLH RIIC0.RIICnIER.UINT8[LH] +#define RIIC0IERH RIIC0.RIICnIER.UINT16[H] +#define RIIC0IERHL RIIC0.RIICnIER.UINT8[HL] +#define RIIC0IERHH RIIC0.RIICnIER.UINT8[HH] +#define RIIC0SR1 RIIC0.RIICnSR1.UINT32 +#define RIIC0SR1L RIIC0.RIICnSR1.UINT16[L] +#define RIIC0SR1LL RIIC0.RIICnSR1.UINT8[LL] +#define RIIC0SR1LH RIIC0.RIICnSR1.UINT8[LH] +#define RIIC0SR1H RIIC0.RIICnSR1.UINT16[H] +#define RIIC0SR1HL RIIC0.RIICnSR1.UINT8[HL] +#define RIIC0SR1HH RIIC0.RIICnSR1.UINT8[HH] +#define RIIC0SR2 RIIC0.RIICnSR2.UINT32 +#define RIIC0SR2L RIIC0.RIICnSR2.UINT16[L] +#define RIIC0SR2LL RIIC0.RIICnSR2.UINT8[LL] +#define RIIC0SR2LH RIIC0.RIICnSR2.UINT8[LH] +#define RIIC0SR2H RIIC0.RIICnSR2.UINT16[H] +#define RIIC0SR2HL RIIC0.RIICnSR2.UINT8[HL] +#define RIIC0SR2HH RIIC0.RIICnSR2.UINT8[HH] +#define RIIC0SAR0 RIIC0.RIICnSAR0.UINT32 +#define RIIC0SAR0L RIIC0.RIICnSAR0.UINT16[L] +#define RIIC0SAR0LL RIIC0.RIICnSAR0.UINT8[LL] +#define RIIC0SAR0LH RIIC0.RIICnSAR0.UINT8[LH] +#define RIIC0SAR0H RIIC0.RIICnSAR0.UINT16[H] +#define RIIC0SAR0HL RIIC0.RIICnSAR0.UINT8[HL] +#define RIIC0SAR0HH RIIC0.RIICnSAR0.UINT8[HH] +#define RIIC0SAR1 RIIC0.RIICnSAR1.UINT32 +#define RIIC0SAR1L RIIC0.RIICnSAR1.UINT16[L] +#define RIIC0SAR1LL RIIC0.RIICnSAR1.UINT8[LL] +#define RIIC0SAR1LH RIIC0.RIICnSAR1.UINT8[LH] +#define RIIC0SAR1H RIIC0.RIICnSAR1.UINT16[H] +#define RIIC0SAR1HL RIIC0.RIICnSAR1.UINT8[HL] +#define RIIC0SAR1HH RIIC0.RIICnSAR1.UINT8[HH] +#define RIIC0SAR2 RIIC0.RIICnSAR2.UINT32 +#define RIIC0SAR2L RIIC0.RIICnSAR2.UINT16[L] +#define RIIC0SAR2LL RIIC0.RIICnSAR2.UINT8[LL] +#define RIIC0SAR2LH RIIC0.RIICnSAR2.UINT8[LH] +#define RIIC0SAR2H RIIC0.RIICnSAR2.UINT16[H] +#define RIIC0SAR2HL RIIC0.RIICnSAR2.UINT8[HL] +#define RIIC0SAR2HH RIIC0.RIICnSAR2.UINT8[HH] +#define RIIC0BRL RIIC0.RIICnBRL.UINT32 +#define RIIC0BRLL RIIC0.RIICnBRL.UINT16[L] +#define RIIC0BRLLL RIIC0.RIICnBRL.UINT8[LL] +#define RIIC0BRLLH RIIC0.RIICnBRL.UINT8[LH] +#define RIIC0BRLH RIIC0.RIICnBRL.UINT16[H] +#define RIIC0BRLHL RIIC0.RIICnBRL.UINT8[HL] +#define RIIC0BRLHH RIIC0.RIICnBRL.UINT8[HH] +#define RIIC0BRH RIIC0.RIICnBRH.UINT32 +#define RIIC0BRHL RIIC0.RIICnBRH.UINT16[L] +#define RIIC0BRHLL RIIC0.RIICnBRH.UINT8[LL] +#define RIIC0BRHLH RIIC0.RIICnBRH.UINT8[LH] +#define RIIC0BRHH RIIC0.RIICnBRH.UINT16[H] +#define RIIC0BRHHL RIIC0.RIICnBRH.UINT8[HL] +#define RIIC0BRHHH RIIC0.RIICnBRH.UINT8[HH] +#define RIIC0DRT RIIC0.RIICnDRT.UINT32 +#define RIIC0DRTL RIIC0.RIICnDRT.UINT16[L] +#define RIIC0DRTLL RIIC0.RIICnDRT.UINT8[LL] +#define RIIC0DRTLH RIIC0.RIICnDRT.UINT8[LH] +#define RIIC0DRTH RIIC0.RIICnDRT.UINT16[H] +#define RIIC0DRTHL RIIC0.RIICnDRT.UINT8[HL] +#define RIIC0DRTHH RIIC0.RIICnDRT.UINT8[HH] +#define RIIC0DRR RIIC0.RIICnDRR.UINT32 +#define RIIC0DRRL RIIC0.RIICnDRR.UINT16[L] +#define RIIC0DRRLL RIIC0.RIICnDRR.UINT8[LL] +#define RIIC0DRRLH RIIC0.RIICnDRR.UINT8[LH] +#define RIIC0DRRH RIIC0.RIICnDRR.UINT16[H] +#define RIIC0DRRHL RIIC0.RIICnDRR.UINT8[HL] +#define RIIC0DRRHH RIIC0.RIICnDRR.UINT8[HH] +#define RIIC1CR1 RIIC1.RIICnCR1.UINT32 +#define RIIC1CR1L RIIC1.RIICnCR1.UINT16[L] +#define RIIC1CR1LL RIIC1.RIICnCR1.UINT8[LL] +#define RIIC1CR1LH RIIC1.RIICnCR1.UINT8[LH] +#define RIIC1CR1H RIIC1.RIICnCR1.UINT16[H] +#define RIIC1CR1HL RIIC1.RIICnCR1.UINT8[HL] +#define RIIC1CR1HH RIIC1.RIICnCR1.UINT8[HH] +#define RIIC1CR2 RIIC1.RIICnCR2.UINT32 +#define RIIC1CR2L RIIC1.RIICnCR2.UINT16[L] +#define RIIC1CR2LL RIIC1.RIICnCR2.UINT8[LL] +#define RIIC1CR2LH RIIC1.RIICnCR2.UINT8[LH] +#define RIIC1CR2H RIIC1.RIICnCR2.UINT16[H] +#define RIIC1CR2HL RIIC1.RIICnCR2.UINT8[HL] +#define RIIC1CR2HH RIIC1.RIICnCR2.UINT8[HH] +#define RIIC1MR1 RIIC1.RIICnMR1.UINT32 +#define RIIC1MR1L RIIC1.RIICnMR1.UINT16[L] +#define RIIC1MR1LL RIIC1.RIICnMR1.UINT8[LL] +#define RIIC1MR1LH RIIC1.RIICnMR1.UINT8[LH] +#define RIIC1MR1H RIIC1.RIICnMR1.UINT16[H] +#define RIIC1MR1HL RIIC1.RIICnMR1.UINT8[HL] +#define RIIC1MR1HH RIIC1.RIICnMR1.UINT8[HH] +#define RIIC1MR2 RIIC1.RIICnMR2.UINT32 +#define RIIC1MR2L RIIC1.RIICnMR2.UINT16[L] +#define RIIC1MR2LL RIIC1.RIICnMR2.UINT8[LL] +#define RIIC1MR2LH RIIC1.RIICnMR2.UINT8[LH] +#define RIIC1MR2H RIIC1.RIICnMR2.UINT16[H] +#define RIIC1MR2HL RIIC1.RIICnMR2.UINT8[HL] +#define RIIC1MR2HH RIIC1.RIICnMR2.UINT8[HH] +#define RIIC1MR3 RIIC1.RIICnMR3.UINT32 +#define RIIC1MR3L RIIC1.RIICnMR3.UINT16[L] +#define RIIC1MR3LL RIIC1.RIICnMR3.UINT8[LL] +#define RIIC1MR3LH RIIC1.RIICnMR3.UINT8[LH] +#define RIIC1MR3H RIIC1.RIICnMR3.UINT16[H] +#define RIIC1MR3HL RIIC1.RIICnMR3.UINT8[HL] +#define RIIC1MR3HH RIIC1.RIICnMR3.UINT8[HH] +#define RIIC1FER RIIC1.RIICnFER.UINT32 +#define RIIC1FERL RIIC1.RIICnFER.UINT16[L] +#define RIIC1FERLL RIIC1.RIICnFER.UINT8[LL] +#define RIIC1FERLH RIIC1.RIICnFER.UINT8[LH] +#define RIIC1FERH RIIC1.RIICnFER.UINT16[H] +#define RIIC1FERHL RIIC1.RIICnFER.UINT8[HL] +#define RIIC1FERHH RIIC1.RIICnFER.UINT8[HH] +#define RIIC1SER RIIC1.RIICnSER.UINT32 +#define RIIC1SERL RIIC1.RIICnSER.UINT16[L] +#define RIIC1SERLL RIIC1.RIICnSER.UINT8[LL] +#define RIIC1SERLH RIIC1.RIICnSER.UINT8[LH] +#define RIIC1SERH RIIC1.RIICnSER.UINT16[H] +#define RIIC1SERHL RIIC1.RIICnSER.UINT8[HL] +#define RIIC1SERHH RIIC1.RIICnSER.UINT8[HH] +#define RIIC1IER RIIC1.RIICnIER.UINT32 +#define RIIC1IERL RIIC1.RIICnIER.UINT16[L] +#define RIIC1IERLL RIIC1.RIICnIER.UINT8[LL] +#define RIIC1IERLH RIIC1.RIICnIER.UINT8[LH] +#define RIIC1IERH RIIC1.RIICnIER.UINT16[H] +#define RIIC1IERHL RIIC1.RIICnIER.UINT8[HL] +#define RIIC1IERHH RIIC1.RIICnIER.UINT8[HH] +#define RIIC1SR1 RIIC1.RIICnSR1.UINT32 +#define RIIC1SR1L RIIC1.RIICnSR1.UINT16[L] +#define RIIC1SR1LL RIIC1.RIICnSR1.UINT8[LL] +#define RIIC1SR1LH RIIC1.RIICnSR1.UINT8[LH] +#define RIIC1SR1H RIIC1.RIICnSR1.UINT16[H] +#define RIIC1SR1HL RIIC1.RIICnSR1.UINT8[HL] +#define RIIC1SR1HH RIIC1.RIICnSR1.UINT8[HH] +#define RIIC1SR2 RIIC1.RIICnSR2.UINT32 +#define RIIC1SR2L RIIC1.RIICnSR2.UINT16[L] +#define RIIC1SR2LL RIIC1.RIICnSR2.UINT8[LL] +#define RIIC1SR2LH RIIC1.RIICnSR2.UINT8[LH] +#define RIIC1SR2H RIIC1.RIICnSR2.UINT16[H] +#define RIIC1SR2HL RIIC1.RIICnSR2.UINT8[HL] +#define RIIC1SR2HH RIIC1.RIICnSR2.UINT8[HH] +#define RIIC1SAR0 RIIC1.RIICnSAR0.UINT32 +#define RIIC1SAR0L RIIC1.RIICnSAR0.UINT16[L] +#define RIIC1SAR0LL RIIC1.RIICnSAR0.UINT8[LL] +#define RIIC1SAR0LH RIIC1.RIICnSAR0.UINT8[LH] +#define RIIC1SAR0H RIIC1.RIICnSAR0.UINT16[H] +#define RIIC1SAR0HL RIIC1.RIICnSAR0.UINT8[HL] +#define RIIC1SAR0HH RIIC1.RIICnSAR0.UINT8[HH] +#define RIIC1SAR1 RIIC1.RIICnSAR1.UINT32 +#define RIIC1SAR1L RIIC1.RIICnSAR1.UINT16[L] +#define RIIC1SAR1LL RIIC1.RIICnSAR1.UINT8[LL] +#define RIIC1SAR1LH RIIC1.RIICnSAR1.UINT8[LH] +#define RIIC1SAR1H RIIC1.RIICnSAR1.UINT16[H] +#define RIIC1SAR1HL RIIC1.RIICnSAR1.UINT8[HL] +#define RIIC1SAR1HH RIIC1.RIICnSAR1.UINT8[HH] +#define RIIC1SAR2 RIIC1.RIICnSAR2.UINT32 +#define RIIC1SAR2L RIIC1.RIICnSAR2.UINT16[L] +#define RIIC1SAR2LL RIIC1.RIICnSAR2.UINT8[LL] +#define RIIC1SAR2LH RIIC1.RIICnSAR2.UINT8[LH] +#define RIIC1SAR2H RIIC1.RIICnSAR2.UINT16[H] +#define RIIC1SAR2HL RIIC1.RIICnSAR2.UINT8[HL] +#define RIIC1SAR2HH RIIC1.RIICnSAR2.UINT8[HH] +#define RIIC1BRL RIIC1.RIICnBRL.UINT32 +#define RIIC1BRLL RIIC1.RIICnBRL.UINT16[L] +#define RIIC1BRLLL RIIC1.RIICnBRL.UINT8[LL] +#define RIIC1BRLLH RIIC1.RIICnBRL.UINT8[LH] +#define RIIC1BRLH RIIC1.RIICnBRL.UINT16[H] +#define RIIC1BRLHL RIIC1.RIICnBRL.UINT8[HL] +#define RIIC1BRLHH RIIC1.RIICnBRL.UINT8[HH] +#define RIIC1BRH RIIC1.RIICnBRH.UINT32 +#define RIIC1BRHL RIIC1.RIICnBRH.UINT16[L] +#define RIIC1BRHLL RIIC1.RIICnBRH.UINT8[LL] +#define RIIC1BRHLH RIIC1.RIICnBRH.UINT8[LH] +#define RIIC1BRHH RIIC1.RIICnBRH.UINT16[H] +#define RIIC1BRHHL RIIC1.RIICnBRH.UINT8[HL] +#define RIIC1BRHHH RIIC1.RIICnBRH.UINT8[HH] +#define RIIC1DRT RIIC1.RIICnDRT.UINT32 +#define RIIC1DRTL RIIC1.RIICnDRT.UINT16[L] +#define RIIC1DRTLL RIIC1.RIICnDRT.UINT8[LL] +#define RIIC1DRTLH RIIC1.RIICnDRT.UINT8[LH] +#define RIIC1DRTH RIIC1.RIICnDRT.UINT16[H] +#define RIIC1DRTHL RIIC1.RIICnDRT.UINT8[HL] +#define RIIC1DRTHH RIIC1.RIICnDRT.UINT8[HH] +#define RIIC1DRR RIIC1.RIICnDRR.UINT32 +#define RIIC1DRRL RIIC1.RIICnDRR.UINT16[L] +#define RIIC1DRRLL RIIC1.RIICnDRR.UINT8[LL] +#define RIIC1DRRLH RIIC1.RIICnDRR.UINT8[LH] +#define RIIC1DRRH RIIC1.RIICnDRR.UINT16[H] +#define RIIC1DRRHL RIIC1.RIICnDRR.UINT8[HL] +#define RIIC1DRRHH RIIC1.RIICnDRR.UINT8[HH] +#define RIIC2CR1 RIIC2.RIICnCR1.UINT32 +#define RIIC2CR1L RIIC2.RIICnCR1.UINT16[L] +#define RIIC2CR1LL RIIC2.RIICnCR1.UINT8[LL] +#define RIIC2CR1LH RIIC2.RIICnCR1.UINT8[LH] +#define RIIC2CR1H RIIC2.RIICnCR1.UINT16[H] +#define RIIC2CR1HL RIIC2.RIICnCR1.UINT8[HL] +#define RIIC2CR1HH RIIC2.RIICnCR1.UINT8[HH] +#define RIIC2CR2 RIIC2.RIICnCR2.UINT32 +#define RIIC2CR2L RIIC2.RIICnCR2.UINT16[L] +#define RIIC2CR2LL RIIC2.RIICnCR2.UINT8[LL] +#define RIIC2CR2LH RIIC2.RIICnCR2.UINT8[LH] +#define RIIC2CR2H RIIC2.RIICnCR2.UINT16[H] +#define RIIC2CR2HL RIIC2.RIICnCR2.UINT8[HL] +#define RIIC2CR2HH RIIC2.RIICnCR2.UINT8[HH] +#define RIIC2MR1 RIIC2.RIICnMR1.UINT32 +#define RIIC2MR1L RIIC2.RIICnMR1.UINT16[L] +#define RIIC2MR1LL RIIC2.RIICnMR1.UINT8[LL] +#define RIIC2MR1LH RIIC2.RIICnMR1.UINT8[LH] +#define RIIC2MR1H RIIC2.RIICnMR1.UINT16[H] +#define RIIC2MR1HL RIIC2.RIICnMR1.UINT8[HL] +#define RIIC2MR1HH RIIC2.RIICnMR1.UINT8[HH] +#define RIIC2MR2 RIIC2.RIICnMR2.UINT32 +#define RIIC2MR2L RIIC2.RIICnMR2.UINT16[L] +#define RIIC2MR2LL RIIC2.RIICnMR2.UINT8[LL] +#define RIIC2MR2LH RIIC2.RIICnMR2.UINT8[LH] +#define RIIC2MR2H RIIC2.RIICnMR2.UINT16[H] +#define RIIC2MR2HL RIIC2.RIICnMR2.UINT8[HL] +#define RIIC2MR2HH RIIC2.RIICnMR2.UINT8[HH] +#define RIIC2MR3 RIIC2.RIICnMR3.UINT32 +#define RIIC2MR3L RIIC2.RIICnMR3.UINT16[L] +#define RIIC2MR3LL RIIC2.RIICnMR3.UINT8[LL] +#define RIIC2MR3LH RIIC2.RIICnMR3.UINT8[LH] +#define RIIC2MR3H RIIC2.RIICnMR3.UINT16[H] +#define RIIC2MR3HL RIIC2.RIICnMR3.UINT8[HL] +#define RIIC2MR3HH RIIC2.RIICnMR3.UINT8[HH] +#define RIIC2FER RIIC2.RIICnFER.UINT32 +#define RIIC2FERL RIIC2.RIICnFER.UINT16[L] +#define RIIC2FERLL RIIC2.RIICnFER.UINT8[LL] +#define RIIC2FERLH RIIC2.RIICnFER.UINT8[LH] +#define RIIC2FERH RIIC2.RIICnFER.UINT16[H] +#define RIIC2FERHL RIIC2.RIICnFER.UINT8[HL] +#define RIIC2FERHH RIIC2.RIICnFER.UINT8[HH] +#define RIIC2SER RIIC2.RIICnSER.UINT32 +#define RIIC2SERL RIIC2.RIICnSER.UINT16[L] +#define RIIC2SERLL RIIC2.RIICnSER.UINT8[LL] +#define RIIC2SERLH RIIC2.RIICnSER.UINT8[LH] +#define RIIC2SERH RIIC2.RIICnSER.UINT16[H] +#define RIIC2SERHL RIIC2.RIICnSER.UINT8[HL] +#define RIIC2SERHH RIIC2.RIICnSER.UINT8[HH] +#define RIIC2IER RIIC2.RIICnIER.UINT32 +#define RIIC2IERL RIIC2.RIICnIER.UINT16[L] +#define RIIC2IERLL RIIC2.RIICnIER.UINT8[LL] +#define RIIC2IERLH RIIC2.RIICnIER.UINT8[LH] +#define RIIC2IERH RIIC2.RIICnIER.UINT16[H] +#define RIIC2IERHL RIIC2.RIICnIER.UINT8[HL] +#define RIIC2IERHH RIIC2.RIICnIER.UINT8[HH] +#define RIIC2SR1 RIIC2.RIICnSR1.UINT32 +#define RIIC2SR1L RIIC2.RIICnSR1.UINT16[L] +#define RIIC2SR1LL RIIC2.RIICnSR1.UINT8[LL] +#define RIIC2SR1LH RIIC2.RIICnSR1.UINT8[LH] +#define RIIC2SR1H RIIC2.RIICnSR1.UINT16[H] +#define RIIC2SR1HL RIIC2.RIICnSR1.UINT8[HL] +#define RIIC2SR1HH RIIC2.RIICnSR1.UINT8[HH] +#define RIIC2SR2 RIIC2.RIICnSR2.UINT32 +#define RIIC2SR2L RIIC2.RIICnSR2.UINT16[L] +#define RIIC2SR2LL RIIC2.RIICnSR2.UINT8[LL] +#define RIIC2SR2LH RIIC2.RIICnSR2.UINT8[LH] +#define RIIC2SR2H RIIC2.RIICnSR2.UINT16[H] +#define RIIC2SR2HL RIIC2.RIICnSR2.UINT8[HL] +#define RIIC2SR2HH RIIC2.RIICnSR2.UINT8[HH] +#define RIIC2SAR0 RIIC2.RIICnSAR0.UINT32 +#define RIIC2SAR0L RIIC2.RIICnSAR0.UINT16[L] +#define RIIC2SAR0LL RIIC2.RIICnSAR0.UINT8[LL] +#define RIIC2SAR0LH RIIC2.RIICnSAR0.UINT8[LH] +#define RIIC2SAR0H RIIC2.RIICnSAR0.UINT16[H] +#define RIIC2SAR0HL RIIC2.RIICnSAR0.UINT8[HL] +#define RIIC2SAR0HH RIIC2.RIICnSAR0.UINT8[HH] +#define RIIC2SAR1 RIIC2.RIICnSAR1.UINT32 +#define RIIC2SAR1L RIIC2.RIICnSAR1.UINT16[L] +#define RIIC2SAR1LL RIIC2.RIICnSAR1.UINT8[LL] +#define RIIC2SAR1LH RIIC2.RIICnSAR1.UINT8[LH] +#define RIIC2SAR1H RIIC2.RIICnSAR1.UINT16[H] +#define RIIC2SAR1HL RIIC2.RIICnSAR1.UINT8[HL] +#define RIIC2SAR1HH RIIC2.RIICnSAR1.UINT8[HH] +#define RIIC2SAR2 RIIC2.RIICnSAR2.UINT32 +#define RIIC2SAR2L RIIC2.RIICnSAR2.UINT16[L] +#define RIIC2SAR2LL RIIC2.RIICnSAR2.UINT8[LL] +#define RIIC2SAR2LH RIIC2.RIICnSAR2.UINT8[LH] +#define RIIC2SAR2H RIIC2.RIICnSAR2.UINT16[H] +#define RIIC2SAR2HL RIIC2.RIICnSAR2.UINT8[HL] +#define RIIC2SAR2HH RIIC2.RIICnSAR2.UINT8[HH] +#define RIIC2BRL RIIC2.RIICnBRL.UINT32 +#define RIIC2BRLL RIIC2.RIICnBRL.UINT16[L] +#define RIIC2BRLLL RIIC2.RIICnBRL.UINT8[LL] +#define RIIC2BRLLH RIIC2.RIICnBRL.UINT8[LH] +#define RIIC2BRLH RIIC2.RIICnBRL.UINT16[H] +#define RIIC2BRLHL RIIC2.RIICnBRL.UINT8[HL] +#define RIIC2BRLHH RIIC2.RIICnBRL.UINT8[HH] +#define RIIC2BRH RIIC2.RIICnBRH.UINT32 +#define RIIC2BRHL RIIC2.RIICnBRH.UINT16[L] +#define RIIC2BRHLL RIIC2.RIICnBRH.UINT8[LL] +#define RIIC2BRHLH RIIC2.RIICnBRH.UINT8[LH] +#define RIIC2BRHH RIIC2.RIICnBRH.UINT16[H] +#define RIIC2BRHHL RIIC2.RIICnBRH.UINT8[HL] +#define RIIC2BRHHH RIIC2.RIICnBRH.UINT8[HH] +#define RIIC2DRT RIIC2.RIICnDRT.UINT32 +#define RIIC2DRTL RIIC2.RIICnDRT.UINT16[L] +#define RIIC2DRTLL RIIC2.RIICnDRT.UINT8[LL] +#define RIIC2DRTLH RIIC2.RIICnDRT.UINT8[LH] +#define RIIC2DRTH RIIC2.RIICnDRT.UINT16[H] +#define RIIC2DRTHL RIIC2.RIICnDRT.UINT8[HL] +#define RIIC2DRTHH RIIC2.RIICnDRT.UINT8[HH] +#define RIIC2DRR RIIC2.RIICnDRR.UINT32 +#define RIIC2DRRL RIIC2.RIICnDRR.UINT16[L] +#define RIIC2DRRLL RIIC2.RIICnDRR.UINT8[LL] +#define RIIC2DRRLH RIIC2.RIICnDRR.UINT8[LH] +#define RIIC2DRRH RIIC2.RIICnDRR.UINT16[H] +#define RIIC2DRRHL RIIC2.RIICnDRR.UINT8[HL] +#define RIIC2DRRHH RIIC2.RIICnDRR.UINT8[HH] +#define RIIC3CR1 RIIC3.RIICnCR1.UINT32 +#define RIIC3CR1L RIIC3.RIICnCR1.UINT16[L] +#define RIIC3CR1LL RIIC3.RIICnCR1.UINT8[LL] +#define RIIC3CR1LH RIIC3.RIICnCR1.UINT8[LH] +#define RIIC3CR1H RIIC3.RIICnCR1.UINT16[H] +#define RIIC3CR1HL RIIC3.RIICnCR1.UINT8[HL] +#define RIIC3CR1HH RIIC3.RIICnCR1.UINT8[HH] +#define RIIC3CR2 RIIC3.RIICnCR2.UINT32 +#define RIIC3CR2L RIIC3.RIICnCR2.UINT16[L] +#define RIIC3CR2LL RIIC3.RIICnCR2.UINT8[LL] +#define RIIC3CR2LH RIIC3.RIICnCR2.UINT8[LH] +#define RIIC3CR2H RIIC3.RIICnCR2.UINT16[H] +#define RIIC3CR2HL RIIC3.RIICnCR2.UINT8[HL] +#define RIIC3CR2HH RIIC3.RIICnCR2.UINT8[HH] +#define RIIC3MR1 RIIC3.RIICnMR1.UINT32 +#define RIIC3MR1L RIIC3.RIICnMR1.UINT16[L] +#define RIIC3MR1LL RIIC3.RIICnMR1.UINT8[LL] +#define RIIC3MR1LH RIIC3.RIICnMR1.UINT8[LH] +#define RIIC3MR1H RIIC3.RIICnMR1.UINT16[H] +#define RIIC3MR1HL RIIC3.RIICnMR1.UINT8[HL] +#define RIIC3MR1HH RIIC3.RIICnMR1.UINT8[HH] +#define RIIC3MR2 RIIC3.RIICnMR2.UINT32 +#define RIIC3MR2L RIIC3.RIICnMR2.UINT16[L] +#define RIIC3MR2LL RIIC3.RIICnMR2.UINT8[LL] +#define RIIC3MR2LH RIIC3.RIICnMR2.UINT8[LH] +#define RIIC3MR2H RIIC3.RIICnMR2.UINT16[H] +#define RIIC3MR2HL RIIC3.RIICnMR2.UINT8[HL] +#define RIIC3MR2HH RIIC3.RIICnMR2.UINT8[HH] +#define RIIC3MR3 RIIC3.RIICnMR3.UINT32 +#define RIIC3MR3L RIIC3.RIICnMR3.UINT16[L] +#define RIIC3MR3LL RIIC3.RIICnMR3.UINT8[LL] +#define RIIC3MR3LH RIIC3.RIICnMR3.UINT8[LH] +#define RIIC3MR3H RIIC3.RIICnMR3.UINT16[H] +#define RIIC3MR3HL RIIC3.RIICnMR3.UINT8[HL] +#define RIIC3MR3HH RIIC3.RIICnMR3.UINT8[HH] +#define RIIC3FER RIIC3.RIICnFER.UINT32 +#define RIIC3FERL RIIC3.RIICnFER.UINT16[L] +#define RIIC3FERLL RIIC3.RIICnFER.UINT8[LL] +#define RIIC3FERLH RIIC3.RIICnFER.UINT8[LH] +#define RIIC3FERH RIIC3.RIICnFER.UINT16[H] +#define RIIC3FERHL RIIC3.RIICnFER.UINT8[HL] +#define RIIC3FERHH RIIC3.RIICnFER.UINT8[HH] +#define RIIC3SER RIIC3.RIICnSER.UINT32 +#define RIIC3SERL RIIC3.RIICnSER.UINT16[L] +#define RIIC3SERLL RIIC3.RIICnSER.UINT8[LL] +#define RIIC3SERLH RIIC3.RIICnSER.UINT8[LH] +#define RIIC3SERH RIIC3.RIICnSER.UINT16[H] +#define RIIC3SERHL RIIC3.RIICnSER.UINT8[HL] +#define RIIC3SERHH RIIC3.RIICnSER.UINT8[HH] +#define RIIC3IER RIIC3.RIICnIER.UINT32 +#define RIIC3IERL RIIC3.RIICnIER.UINT16[L] +#define RIIC3IERLL RIIC3.RIICnIER.UINT8[LL] +#define RIIC3IERLH RIIC3.RIICnIER.UINT8[LH] +#define RIIC3IERH RIIC3.RIICnIER.UINT16[H] +#define RIIC3IERHL RIIC3.RIICnIER.UINT8[HL] +#define RIIC3IERHH RIIC3.RIICnIER.UINT8[HH] +#define RIIC3SR1 RIIC3.RIICnSR1.UINT32 +#define RIIC3SR1L RIIC3.RIICnSR1.UINT16[L] +#define RIIC3SR1LL RIIC3.RIICnSR1.UINT8[LL] +#define RIIC3SR1LH RIIC3.RIICnSR1.UINT8[LH] +#define RIIC3SR1H RIIC3.RIICnSR1.UINT16[H] +#define RIIC3SR1HL RIIC3.RIICnSR1.UINT8[HL] +#define RIIC3SR1HH RIIC3.RIICnSR1.UINT8[HH] +#define RIIC3SR2 RIIC3.RIICnSR2.UINT32 +#define RIIC3SR2L RIIC3.RIICnSR2.UINT16[L] +#define RIIC3SR2LL RIIC3.RIICnSR2.UINT8[LL] +#define RIIC3SR2LH RIIC3.RIICnSR2.UINT8[LH] +#define RIIC3SR2H RIIC3.RIICnSR2.UINT16[H] +#define RIIC3SR2HL RIIC3.RIICnSR2.UINT8[HL] +#define RIIC3SR2HH RIIC3.RIICnSR2.UINT8[HH] +#define RIIC3SAR0 RIIC3.RIICnSAR0.UINT32 +#define RIIC3SAR0L RIIC3.RIICnSAR0.UINT16[L] +#define RIIC3SAR0LL RIIC3.RIICnSAR0.UINT8[LL] +#define RIIC3SAR0LH RIIC3.RIICnSAR0.UINT8[LH] +#define RIIC3SAR0H RIIC3.RIICnSAR0.UINT16[H] +#define RIIC3SAR0HL RIIC3.RIICnSAR0.UINT8[HL] +#define RIIC3SAR0HH RIIC3.RIICnSAR0.UINT8[HH] +#define RIIC3SAR1 RIIC3.RIICnSAR1.UINT32 +#define RIIC3SAR1L RIIC3.RIICnSAR1.UINT16[L] +#define RIIC3SAR1LL RIIC3.RIICnSAR1.UINT8[LL] +#define RIIC3SAR1LH RIIC3.RIICnSAR1.UINT8[LH] +#define RIIC3SAR1H RIIC3.RIICnSAR1.UINT16[H] +#define RIIC3SAR1HL RIIC3.RIICnSAR1.UINT8[HL] +#define RIIC3SAR1HH RIIC3.RIICnSAR1.UINT8[HH] +#define RIIC3SAR2 RIIC3.RIICnSAR2.UINT32 +#define RIIC3SAR2L RIIC3.RIICnSAR2.UINT16[L] +#define RIIC3SAR2LL RIIC3.RIICnSAR2.UINT8[LL] +#define RIIC3SAR2LH RIIC3.RIICnSAR2.UINT8[LH] +#define RIIC3SAR2H RIIC3.RIICnSAR2.UINT16[H] +#define RIIC3SAR2HL RIIC3.RIICnSAR2.UINT8[HL] +#define RIIC3SAR2HH RIIC3.RIICnSAR2.UINT8[HH] +#define RIIC3BRL RIIC3.RIICnBRL.UINT32 +#define RIIC3BRLL RIIC3.RIICnBRL.UINT16[L] +#define RIIC3BRLLL RIIC3.RIICnBRL.UINT8[LL] +#define RIIC3BRLLH RIIC3.RIICnBRL.UINT8[LH] +#define RIIC3BRLH RIIC3.RIICnBRL.UINT16[H] +#define RIIC3BRLHL RIIC3.RIICnBRL.UINT8[HL] +#define RIIC3BRLHH RIIC3.RIICnBRL.UINT8[HH] +#define RIIC3BRH RIIC3.RIICnBRH.UINT32 +#define RIIC3BRHL RIIC3.RIICnBRH.UINT16[L] +#define RIIC3BRHLL RIIC3.RIICnBRH.UINT8[LL] +#define RIIC3BRHLH RIIC3.RIICnBRH.UINT8[LH] +#define RIIC3BRHH RIIC3.RIICnBRH.UINT16[H] +#define RIIC3BRHHL RIIC3.RIICnBRH.UINT8[HL] +#define RIIC3BRHHH RIIC3.RIICnBRH.UINT8[HH] +#define RIIC3DRT RIIC3.RIICnDRT.UINT32 +#define RIIC3DRTL RIIC3.RIICnDRT.UINT16[L] +#define RIIC3DRTLL RIIC3.RIICnDRT.UINT8[LL] +#define RIIC3DRTLH RIIC3.RIICnDRT.UINT8[LH] +#define RIIC3DRTH RIIC3.RIICnDRT.UINT16[H] +#define RIIC3DRTHL RIIC3.RIICnDRT.UINT8[HL] +#define RIIC3DRTHH RIIC3.RIICnDRT.UINT8[HH] +#define RIIC3DRR RIIC3.RIICnDRR.UINT32 +#define RIIC3DRRL RIIC3.RIICnDRR.UINT16[L] +#define RIIC3DRRLL RIIC3.RIICnDRR.UINT8[LL] +#define RIIC3DRRLH RIIC3.RIICnDRR.UINT8[LH] +#define RIIC3DRRH RIIC3.RIICnDRR.UINT16[H] +#define RIIC3DRRHL RIIC3.RIICnDRR.UINT8[HL] +#define RIIC3DRRHH RIIC3.RIICnDRR.UINT8[HH] +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/romdec_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,166 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : romdec_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef ROMDEC_IODEFINE_H +#define ROMDEC_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_romdec +{ /* ROMDEC */ + volatile uint8_t CROMEN; /* CROMEN */ + volatile uint8_t CROMSY0; /* CROMSY0 */ +#define ROMDEC_CROMCTL0_COUNT 2 + volatile uint8_t CROMCTL0; /* CROMCTL0 */ + volatile uint8_t CROMCTL1; /* CROMCTL1 */ + volatile uint8_t dummy23[1]; /* */ + volatile uint8_t CROMCTL3; /* CROMCTL3 */ + volatile uint8_t CROMCTL4; /* CROMCTL4 */ + volatile uint8_t CROMCTL5; /* CROMCTL5 */ +#define ROMDEC_CROMST0_COUNT 2 + volatile uint8_t CROMST0; /* CROMST0 */ + volatile uint8_t CROMST1; /* CROMST1 */ + volatile uint8_t dummy24[1]; /* */ + volatile uint8_t CROMST3; /* CROMST3 */ + volatile uint8_t CROMST4; /* CROMST4 */ + volatile uint8_t CROMST5; /* CROMST5 */ + volatile uint8_t CROMST6; /* CROMST6 */ + volatile uint8_t dummy25[5]; /* */ +#define ROMDEC_CBUFST0_COUNT 3 + volatile uint8_t CBUFST0; /* CBUFST0 */ + volatile uint8_t CBUFST1; /* CBUFST1 */ + volatile uint8_t CBUFST2; /* CBUFST2 */ + volatile uint8_t dummy26[1]; /* */ +#define ROMDEC_HEAD00_COUNT 4 + volatile uint8_t HEAD00; /* HEAD00 */ + volatile uint8_t HEAD01; /* HEAD01 */ + volatile uint8_t HEAD02; /* HEAD02 */ + volatile uint8_t HEAD03; /* HEAD03 */ +#define ROMDEC_SHEAD00_COUNT 8 + volatile uint8_t SHEAD00; /* SHEAD00 */ + volatile uint8_t SHEAD01; /* SHEAD01 */ + volatile uint8_t SHEAD02; /* SHEAD02 */ + volatile uint8_t SHEAD03; /* SHEAD03 */ + volatile uint8_t SHEAD04; /* SHEAD04 */ + volatile uint8_t SHEAD05; /* SHEAD05 */ + volatile uint8_t SHEAD06; /* SHEAD06 */ + volatile uint8_t SHEAD07; /* SHEAD07 */ +#define ROMDEC_HEAD20_COUNT 4 + volatile uint8_t HEAD20; /* HEAD20 */ + volatile uint8_t HEAD21; /* HEAD21 */ + volatile uint8_t HEAD22; /* HEAD22 */ + volatile uint8_t HEAD23; /* HEAD23 */ +#define ROMDEC_SHEAD20_COUNT 8 + volatile uint8_t SHEAD20; /* SHEAD20 */ + volatile uint8_t SHEAD21; /* SHEAD21 */ + volatile uint8_t SHEAD22; /* SHEAD22 */ + volatile uint8_t SHEAD23; /* SHEAD23 */ + volatile uint8_t SHEAD24; /* SHEAD24 */ + volatile uint8_t SHEAD25; /* SHEAD25 */ + volatile uint8_t SHEAD26; /* SHEAD26 */ + volatile uint8_t SHEAD27; /* SHEAD27 */ + volatile uint8_t dummy27[16]; /* */ +#define ROMDEC_CBUFCTL0_COUNT 4 + volatile uint8_t CBUFCTL0; /* CBUFCTL0 */ + volatile uint8_t CBUFCTL1; /* CBUFCTL1 */ + volatile uint8_t CBUFCTL2; /* CBUFCTL2 */ + volatile uint8_t CBUFCTL3; /* CBUFCTL3 */ + volatile uint8_t dummy28[1]; /* */ + volatile uint8_t CROMST0M; /* CROMST0M */ + volatile uint8_t dummy29[186]; /* */ + volatile uint8_t ROMDECRST; /* ROMDECRST */ + volatile uint8_t RSTSTAT; /* RSTSTAT */ + volatile uint8_t SSI; /* SSI */ + volatile uint8_t dummy30[5]; /* */ + volatile uint8_t INTHOLD; /* INTHOLD */ + volatile uint8_t INHINT; /* INHINT */ + volatile uint8_t dummy31[246]; /* */ +#define ROMDEC_STRMDIN0_COUNT 2 + volatile uint16_t STRMDIN0; /* STRMDIN0 */ + volatile uint16_t STRMDIN2; /* STRMDIN2 */ + volatile uint16_t STRMDOUT0; /* STRMDOUT0 */ +}; + + +#define ROMDEC (*(struct st_romdec *)0xE8005000uL) /* ROMDEC */ + + +#define ROMDECCROMEN ROMDEC.CROMEN +#define ROMDECCROMSY0 ROMDEC.CROMSY0 +#define ROMDECCROMCTL0 ROMDEC.CROMCTL0 +#define ROMDECCROMCTL1 ROMDEC.CROMCTL1 +#define ROMDECCROMCTL3 ROMDEC.CROMCTL3 +#define ROMDECCROMCTL4 ROMDEC.CROMCTL4 +#define ROMDECCROMCTL5 ROMDEC.CROMCTL5 +#define ROMDECCROMST0 ROMDEC.CROMST0 +#define ROMDECCROMST1 ROMDEC.CROMST1 +#define ROMDECCROMST3 ROMDEC.CROMST3 +#define ROMDECCROMST4 ROMDEC.CROMST4 +#define ROMDECCROMST5 ROMDEC.CROMST5 +#define ROMDECCROMST6 ROMDEC.CROMST6 +#define ROMDECCBUFST0 ROMDEC.CBUFST0 +#define ROMDECCBUFST1 ROMDEC.CBUFST1 +#define ROMDECCBUFST2 ROMDEC.CBUFST2 +#define ROMDECHEAD00 ROMDEC.HEAD00 +#define ROMDECHEAD01 ROMDEC.HEAD01 +#define ROMDECHEAD02 ROMDEC.HEAD02 +#define ROMDECHEAD03 ROMDEC.HEAD03 +#define ROMDECSHEAD00 ROMDEC.SHEAD00 +#define ROMDECSHEAD01 ROMDEC.SHEAD01 +#define ROMDECSHEAD02 ROMDEC.SHEAD02 +#define ROMDECSHEAD03 ROMDEC.SHEAD03 +#define ROMDECSHEAD04 ROMDEC.SHEAD04 +#define ROMDECSHEAD05 ROMDEC.SHEAD05 +#define ROMDECSHEAD06 ROMDEC.SHEAD06 +#define ROMDECSHEAD07 ROMDEC.SHEAD07 +#define ROMDECHEAD20 ROMDEC.HEAD20 +#define ROMDECHEAD21 ROMDEC.HEAD21 +#define ROMDECHEAD22 ROMDEC.HEAD22 +#define ROMDECHEAD23 ROMDEC.HEAD23 +#define ROMDECSHEAD20 ROMDEC.SHEAD20 +#define ROMDECSHEAD21 ROMDEC.SHEAD21 +#define ROMDECSHEAD22 ROMDEC.SHEAD22 +#define ROMDECSHEAD23 ROMDEC.SHEAD23 +#define ROMDECSHEAD24 ROMDEC.SHEAD24 +#define ROMDECSHEAD25 ROMDEC.SHEAD25 +#define ROMDECSHEAD26 ROMDEC.SHEAD26 +#define ROMDECSHEAD27 ROMDEC.SHEAD27 +#define ROMDECCBUFCTL0 ROMDEC.CBUFCTL0 +#define ROMDECCBUFCTL1 ROMDEC.CBUFCTL1 +#define ROMDECCBUFCTL2 ROMDEC.CBUFCTL2 +#define ROMDECCBUFCTL3 ROMDEC.CBUFCTL3 +#define ROMDECCROMST0M ROMDEC.CROMST0M +#define ROMDECROMDECRST ROMDEC.ROMDECRST +#define ROMDECRSTSTAT ROMDEC.RSTSTAT +#define ROMDECSSI ROMDEC.SSI +#define ROMDECINTHOLD ROMDEC.INTHOLD +#define ROMDECINHINT ROMDEC.INHINT +#define ROMDECSTRMDIN0 ROMDEC.STRMDIN0 +#define ROMDECSTRMDIN2 ROMDEC.STRMDIN2 +#define ROMDECSTRMDOUT0 ROMDEC.STRMDOUT0 +/* <-SEC M1.10.1 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/rscan0_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,9038 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : rscan0_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef RSCAN0_IODEFINE_H +#define RSCAN0_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->SEC M1.10.1 : Not magic number */ + +struct st_rscan0 +{ /* RSCAN0 */ +/* start of struct st_rscan_from_rscan0cncfg */ + union iodefine_reg32_t C0CFG; /* C0CFG */ + union iodefine_reg32_t C0CTR; /* C0CTR */ + union iodefine_reg32_t C0STS; /* C0STS */ + union iodefine_reg32_t C0ERFL; /* C0ERFL */ +/* end of struct st_rscan_from_rscan0cncfg */ + +/* start of struct st_rscan_from_rscan0cncfg */ + union iodefine_reg32_t C1CFG; /* C1CFG */ + union iodefine_reg32_t C1CTR; /* C1CTR */ + union iodefine_reg32_t C1STS; /* C1STS */ + union iodefine_reg32_t C1ERFL; /* C1ERFL */ +/* end of struct st_rscan_from_rscan0cncfg */ + +/* start of struct st_rscan_from_rscan0cncfg */ + union iodefine_reg32_t C2CFG; /* C2CFG */ + union iodefine_reg32_t C2CTR; /* C2CTR */ + union iodefine_reg32_t C2STS; /* C2STS */ + union iodefine_reg32_t C2ERFL; /* C2ERFL */ +/* end of struct st_rscan_from_rscan0cncfg */ + +/* start of struct st_rscan_from_rscan0cncfg */ + union iodefine_reg32_t C3CFG; /* C3CFG */ + union iodefine_reg32_t C3CTR; /* C3CTR */ + union iodefine_reg32_t C3STS; /* C3STS */ + union iodefine_reg32_t C3ERFL; /* C3ERFL */ +/* end of struct st_rscan_from_rscan0cncfg */ + +/* start of struct st_rscan_from_rscan0cncfg */ + union iodefine_reg32_t C4CFG; /* C4CFG */ + union iodefine_reg32_t C4CTR; /* C4CTR */ + union iodefine_reg32_t C4STS; /* C4STS */ + union iodefine_reg32_t C4ERFL; /* C4ERFL */ +/* end of struct st_rscan_from_rscan0cncfg */ + + volatile uint8_t dummy159[52]; /* */ + union iodefine_reg32_t GCFG; /* GCFG */ + union iodefine_reg32_t GCTR; /* GCTR */ + union iodefine_reg32_t GSTS; /* GSTS */ + union iodefine_reg32_t GERFL; /* GERFL */ + union iodefine_reg32_16_t GTSC; /* GTSC */ + union iodefine_reg32_t GAFLECTR; /* GAFLECTR */ +#define RSCAN0_GAFLCFG0_COUNT 2 + union iodefine_reg32_t GAFLCFG0; /* GAFLCFG0 */ + union iodefine_reg32_t GAFLCFG1; /* GAFLCFG1 */ + union iodefine_reg32_t RMNB; /* RMNB */ +#define RSCAN0_RMND0_COUNT 3 + union iodefine_reg32_t RMND0; /* RMND0 */ + union iodefine_reg32_t RMND1; /* RMND1 */ + union iodefine_reg32_t RMND2; /* RMND2 */ + + volatile uint8_t dummy160[4]; /* */ +#define RSCAN0_RFCC0_COUNT 8 + union iodefine_reg32_t RFCC0; /* RFCC0 */ + union iodefine_reg32_t RFCC1; /* RFCC1 */ + union iodefine_reg32_t RFCC2; /* RFCC2 */ + union iodefine_reg32_t RFCC3; /* RFCC3 */ + union iodefine_reg32_t RFCC4; /* RFCC4 */ + union iodefine_reg32_t RFCC5; /* RFCC5 */ + union iodefine_reg32_t RFCC6; /* RFCC6 */ + union iodefine_reg32_t RFCC7; /* RFCC7 */ +#define RSCAN0_RFSTS0_COUNT 8 + union iodefine_reg32_t RFSTS0; /* RFSTS0 */ + union iodefine_reg32_t RFSTS1; /* RFSTS1 */ + union iodefine_reg32_t RFSTS2; /* RFSTS2 */ + union iodefine_reg32_t RFSTS3; /* RFSTS3 */ + union iodefine_reg32_t RFSTS4; /* RFSTS4 */ + union iodefine_reg32_t RFSTS5; /* RFSTS5 */ + union iodefine_reg32_t RFSTS6; /* RFSTS6 */ + union iodefine_reg32_t RFSTS7; /* RFSTS7 */ +#define RSCAN0_RFPCTR0_COUNT 8 + union iodefine_reg32_t RFPCTR0; /* RFPCTR0 */ + union iodefine_reg32_t RFPCTR1; /* RFPCTR1 */ + union iodefine_reg32_t RFPCTR2; /* RFPCTR2 */ + union iodefine_reg32_t RFPCTR3; /* RFPCTR3 */ + union iodefine_reg32_t RFPCTR4; /* RFPCTR4 */ + union iodefine_reg32_t RFPCTR5; /* RFPCTR5 */ + union iodefine_reg32_t RFPCTR6; /* RFPCTR6 */ + union iodefine_reg32_t RFPCTR7; /* RFPCTR7 */ +#define RSCAN0_CFCC0_COUNT 15 + union iodefine_reg32_t CFCC0; /* CFCC0 */ + union iodefine_reg32_t CFCC1; /* CFCC1 */ + union iodefine_reg32_t CFCC2; /* CFCC2 */ + union iodefine_reg32_t CFCC3; /* CFCC3 */ + union iodefine_reg32_t CFCC4; /* CFCC4 */ + union iodefine_reg32_t CFCC5; /* CFCC5 */ + union iodefine_reg32_t CFCC6; /* CFCC6 */ + union iodefine_reg32_t CFCC7; /* CFCC7 */ + union iodefine_reg32_t CFCC8; /* CFCC8 */ + union iodefine_reg32_t CFCC9; /* CFCC9 */ + union iodefine_reg32_t CFCC10; /* CFCC10 */ + union iodefine_reg32_t CFCC11; /* CFCC11 */ + union iodefine_reg32_t CFCC12; /* CFCC12 */ + union iodefine_reg32_t CFCC13; /* CFCC13 */ + union iodefine_reg32_t CFCC14; /* CFCC14 */ + + volatile uint8_t dummy161[36]; /* */ +#define RSCAN0_CFSTS0_COUNT 15 + union iodefine_reg32_t CFSTS0; /* CFSTS0 */ + union iodefine_reg32_t CFSTS1; /* CFSTS1 */ + union iodefine_reg32_t CFSTS2; /* CFSTS2 */ + union iodefine_reg32_t CFSTS3; /* CFSTS3 */ + union iodefine_reg32_t CFSTS4; /* CFSTS4 */ + union iodefine_reg32_t CFSTS5; /* CFSTS5 */ + union iodefine_reg32_t CFSTS6; /* CFSTS6 */ + union iodefine_reg32_t CFSTS7; /* CFSTS7 */ + union iodefine_reg32_t CFSTS8; /* CFSTS8 */ + union iodefine_reg32_t CFSTS9; /* CFSTS9 */ + union iodefine_reg32_t CFSTS10; /* CFSTS10 */ + union iodefine_reg32_t CFSTS11; /* CFSTS11 */ + union iodefine_reg32_t CFSTS12; /* CFSTS12 */ + union iodefine_reg32_t CFSTS13; /* CFSTS13 */ + union iodefine_reg32_t CFSTS14; /* CFSTS14 */ + + volatile uint8_t dummy162[36]; /* */ +#define RSCAN0_CFPCTR0_COUNT 15 + union iodefine_reg32_t CFPCTR0; /* CFPCTR0 */ + union iodefine_reg32_t CFPCTR1; /* CFPCTR1 */ + union iodefine_reg32_t CFPCTR2; /* CFPCTR2 */ + union iodefine_reg32_t CFPCTR3; /* CFPCTR3 */ + union iodefine_reg32_t CFPCTR4; /* CFPCTR4 */ + union iodefine_reg32_t CFPCTR5; /* CFPCTR5 */ + union iodefine_reg32_t CFPCTR6; /* CFPCTR6 */ + union iodefine_reg32_t CFPCTR7; /* CFPCTR7 */ + union iodefine_reg32_t CFPCTR8; /* CFPCTR8 */ + union iodefine_reg32_t CFPCTR9; /* CFPCTR9 */ + union iodefine_reg32_t CFPCTR10; /* CFPCTR10 */ + union iodefine_reg32_t CFPCTR11; /* CFPCTR11 */ + union iodefine_reg32_t CFPCTR12; /* CFPCTR12 */ + union iodefine_reg32_t CFPCTR13; /* CFPCTR13 */ + union iodefine_reg32_t CFPCTR14; /* CFPCTR14 */ + + volatile uint8_t dummy163[36]; /* */ + union iodefine_reg32_t FESTS; /* FESTS */ + union iodefine_reg32_t FFSTS; /* FFSTS */ + union iodefine_reg32_t FMSTS; /* FMSTS */ + union iodefine_reg32_t RFISTS; /* RFISTS */ + union iodefine_reg32_t CFRISTS; /* CFRISTS */ + union iodefine_reg32_t CFTISTS; /* CFTISTS */ + +#define RSCAN0_TMC0_COUNT 80 + volatile uint8_t TMC0; /* TMC0 */ + volatile uint8_t TMC1; /* TMC1 */ + volatile uint8_t TMC2; /* TMC2 */ + volatile uint8_t TMC3; /* TMC3 */ + volatile uint8_t TMC4; /* TMC4 */ + volatile uint8_t TMC5; /* TMC5 */ + volatile uint8_t TMC6; /* TMC6 */ + volatile uint8_t TMC7; /* TMC7 */ + volatile uint8_t TMC8; /* TMC8 */ + volatile uint8_t TMC9; /* TMC9 */ + volatile uint8_t TMC10; /* TMC10 */ + volatile uint8_t TMC11; /* TMC11 */ + volatile uint8_t TMC12; /* TMC12 */ + volatile uint8_t TMC13; /* TMC13 */ + volatile uint8_t TMC14; /* TMC14 */ + volatile uint8_t TMC15; /* TMC15 */ + volatile uint8_t TMC16; /* TMC16 */ + volatile uint8_t TMC17; /* TMC17 */ + volatile uint8_t TMC18; /* TMC18 */ + volatile uint8_t TMC19; /* TMC19 */ + volatile uint8_t TMC20; /* TMC20 */ + volatile uint8_t TMC21; /* TMC21 */ + volatile uint8_t TMC22; /* TMC22 */ + volatile uint8_t TMC23; /* TMC23 */ + volatile uint8_t TMC24; /* TMC24 */ + volatile uint8_t TMC25; /* TMC25 */ + volatile uint8_t TMC26; /* TMC26 */ + volatile uint8_t TMC27; /* TMC27 */ + volatile uint8_t TMC28; /* TMC28 */ + volatile uint8_t TMC29; /* TMC29 */ + volatile uint8_t TMC30; /* TMC30 */ + volatile uint8_t TMC31; /* TMC31 */ + volatile uint8_t TMC32; /* TMC32 */ + volatile uint8_t TMC33; /* TMC33 */ + volatile uint8_t TMC34; /* TMC34 */ + volatile uint8_t TMC35; /* TMC35 */ + volatile uint8_t TMC36; /* TMC36 */ + volatile uint8_t TMC37; /* TMC37 */ + volatile uint8_t TMC38; /* TMC38 */ + volatile uint8_t TMC39; /* TMC39 */ + volatile uint8_t TMC40; /* TMC40 */ + volatile uint8_t TMC41; /* TMC41 */ + volatile uint8_t TMC42; /* TMC42 */ + volatile uint8_t TMC43; /* TMC43 */ + volatile uint8_t TMC44; /* TMC44 */ + volatile uint8_t TMC45; /* TMC45 */ + volatile uint8_t TMC46; /* TMC46 */ + volatile uint8_t TMC47; /* TMC47 */ + volatile uint8_t TMC48; /* TMC48 */ + volatile uint8_t TMC49; /* TMC49 */ + volatile uint8_t TMC50; /* TMC50 */ + volatile uint8_t TMC51; /* TMC51 */ + volatile uint8_t TMC52; /* TMC52 */ + volatile uint8_t TMC53; /* TMC53 */ + volatile uint8_t TMC54; /* TMC54 */ + volatile uint8_t TMC55; /* TMC55 */ + volatile uint8_t TMC56; /* TMC56 */ + volatile uint8_t TMC57; /* TMC57 */ + volatile uint8_t TMC58; /* TMC58 */ + volatile uint8_t TMC59; /* TMC59 */ + volatile uint8_t TMC60; /* TMC60 */ + volatile uint8_t TMC61; /* TMC61 */ + volatile uint8_t TMC62; /* TMC62 */ + volatile uint8_t TMC63; /* TMC63 */ + volatile uint8_t TMC64; /* TMC64 */ + volatile uint8_t TMC65; /* TMC65 */ + volatile uint8_t TMC66; /* TMC66 */ + volatile uint8_t TMC67; /* TMC67 */ + volatile uint8_t TMC68; /* TMC68 */ + volatile uint8_t TMC69; /* TMC69 */ + volatile uint8_t TMC70; /* TMC70 */ + volatile uint8_t TMC71; /* TMC71 */ + volatile uint8_t TMC72; /* TMC72 */ + volatile uint8_t TMC73; /* TMC73 */ + volatile uint8_t TMC74; /* TMC74 */ + volatile uint8_t TMC75; /* TMC75 */ + volatile uint8_t TMC76; /* TMC76 */ + volatile uint8_t TMC77; /* TMC77 */ + volatile uint8_t TMC78; /* TMC78 */ + volatile uint8_t TMC79; /* TMC79 */ + volatile uint8_t dummy164[48]; /* */ +#define RSCAN0_TMSTS0_COUNT 80 + volatile uint8_t TMSTS0; /* TMSTS0 */ + volatile uint8_t TMSTS1; /* TMSTS1 */ + volatile uint8_t TMSTS2; /* TMSTS2 */ + volatile uint8_t TMSTS3; /* TMSTS3 */ + volatile uint8_t TMSTS4; /* TMSTS4 */ + volatile uint8_t TMSTS5; /* TMSTS5 */ + volatile uint8_t TMSTS6; /* TMSTS6 */ + volatile uint8_t TMSTS7; /* TMSTS7 */ + volatile uint8_t TMSTS8; /* TMSTS8 */ + volatile uint8_t TMSTS9; /* TMSTS9 */ + volatile uint8_t TMSTS10; /* TMSTS10 */ + volatile uint8_t TMSTS11; /* TMSTS11 */ + volatile uint8_t TMSTS12; /* TMSTS12 */ + volatile uint8_t TMSTS13; /* TMSTS13 */ + volatile uint8_t TMSTS14; /* TMSTS14 */ + volatile uint8_t TMSTS15; /* TMSTS15 */ + volatile uint8_t TMSTS16; /* TMSTS16 */ + volatile uint8_t TMSTS17; /* TMSTS17 */ + volatile uint8_t TMSTS18; /* TMSTS18 */ + volatile uint8_t TMSTS19; /* TMSTS19 */ + volatile uint8_t TMSTS20; /* TMSTS20 */ + volatile uint8_t TMSTS21; /* TMSTS21 */ + volatile uint8_t TMSTS22; /* TMSTS22 */ + volatile uint8_t TMSTS23; /* TMSTS23 */ + volatile uint8_t TMSTS24; /* TMSTS24 */ + volatile uint8_t TMSTS25; /* TMSTS25 */ + volatile uint8_t TMSTS26; /* TMSTS26 */ + volatile uint8_t TMSTS27; /* TMSTS27 */ + volatile uint8_t TMSTS28; /* TMSTS28 */ + volatile uint8_t TMSTS29; /* TMSTS29 */ + volatile uint8_t TMSTS30; /* TMSTS30 */ + volatile uint8_t TMSTS31; /* TMSTS31 */ + volatile uint8_t TMSTS32; /* TMSTS32 */ + volatile uint8_t TMSTS33; /* TMSTS33 */ + volatile uint8_t TMSTS34; /* TMSTS34 */ + volatile uint8_t TMSTS35; /* TMSTS35 */ + volatile uint8_t TMSTS36; /* TMSTS36 */ + volatile uint8_t TMSTS37; /* TMSTS37 */ + volatile uint8_t TMSTS38; /* TMSTS38 */ + volatile uint8_t TMSTS39; /* TMSTS39 */ + volatile uint8_t TMSTS40; /* TMSTS40 */ + volatile uint8_t TMSTS41; /* TMSTS41 */ + volatile uint8_t TMSTS42; /* TMSTS42 */ + volatile uint8_t TMSTS43; /* TMSTS43 */ + volatile uint8_t TMSTS44; /* TMSTS44 */ + volatile uint8_t TMSTS45; /* TMSTS45 */ + volatile uint8_t TMSTS46; /* TMSTS46 */ + volatile uint8_t TMSTS47; /* TMSTS47 */ + volatile uint8_t TMSTS48; /* TMSTS48 */ + volatile uint8_t TMSTS49; /* TMSTS49 */ + volatile uint8_t TMSTS50; /* TMSTS50 */ + volatile uint8_t TMSTS51; /* TMSTS51 */ + volatile uint8_t TMSTS52; /* TMSTS52 */ + volatile uint8_t TMSTS53; /* TMSTS53 */ + volatile uint8_t TMSTS54; /* TMSTS54 */ + volatile uint8_t TMSTS55; /* TMSTS55 */ + volatile uint8_t TMSTS56; /* TMSTS56 */ + volatile uint8_t TMSTS57; /* TMSTS57 */ + volatile uint8_t TMSTS58; /* TMSTS58 */ + volatile uint8_t TMSTS59; /* TMSTS59 */ + volatile uint8_t TMSTS60; /* TMSTS60 */ + volatile uint8_t TMSTS61; /* TMSTS61 */ + volatile uint8_t TMSTS62; /* TMSTS62 */ + volatile uint8_t TMSTS63; /* TMSTS63 */ + volatile uint8_t TMSTS64; /* TMSTS64 */ + volatile uint8_t TMSTS65; /* TMSTS65 */ + volatile uint8_t TMSTS66; /* TMSTS66 */ + volatile uint8_t TMSTS67; /* TMSTS67 */ + volatile uint8_t TMSTS68; /* TMSTS68 */ + volatile uint8_t TMSTS69; /* TMSTS69 */ + volatile uint8_t TMSTS70; /* TMSTS70 */ + volatile uint8_t TMSTS71; /* TMSTS71 */ + volatile uint8_t TMSTS72; /* TMSTS72 */ + volatile uint8_t TMSTS73; /* TMSTS73 */ + volatile uint8_t TMSTS74; /* TMSTS74 */ + volatile uint8_t TMSTS75; /* TMSTS75 */ + volatile uint8_t TMSTS76; /* TMSTS76 */ + volatile uint8_t TMSTS77; /* TMSTS77 */ + volatile uint8_t TMSTS78; /* TMSTS78 */ + volatile uint8_t TMSTS79; /* TMSTS79 */ + volatile uint8_t dummy165[48]; /* */ +#define RSCAN0_TMTRSTS0_COUNT 3 + union iodefine_reg32_t TMTRSTS0; /* TMTRSTS0 */ + union iodefine_reg32_t TMTRSTS1; /* TMTRSTS1 */ + union iodefine_reg32_t TMTRSTS2; /* TMTRSTS2 */ + + volatile uint8_t dummy166[4]; /* */ +#define RSCAN0_TMTARSTS0_COUNT 3 + union iodefine_reg32_t TMTARSTS0; /* TMTARSTS0 */ + union iodefine_reg32_t TMTARSTS1; /* TMTARSTS1 */ + union iodefine_reg32_t TMTARSTS2; /* TMTARSTS2 */ + + volatile uint8_t dummy167[4]; /* */ +#define RSCAN0_TMTCSTS0_COUNT 3 + union iodefine_reg32_t TMTCSTS0; /* TMTCSTS0 */ + union iodefine_reg32_t TMTCSTS1; /* TMTCSTS1 */ + union iodefine_reg32_t TMTCSTS2; /* TMTCSTS2 */ + + volatile uint8_t dummy168[4]; /* */ +#define RSCAN0_TMTASTS0_COUNT 3 + union iodefine_reg32_t TMTASTS0; /* TMTASTS0 */ + union iodefine_reg32_t TMTASTS1; /* TMTASTS1 */ + union iodefine_reg32_t TMTASTS2; /* TMTASTS2 */ + + volatile uint8_t dummy169[4]; /* */ +#define RSCAN0_TMIEC0_COUNT 3 + union iodefine_reg32_t TMIEC0; /* TMIEC0 */ + union iodefine_reg32_t TMIEC1; /* TMIEC1 */ + union iodefine_reg32_t TMIEC2; /* TMIEC2 */ + + volatile uint8_t dummy170[4]; /* */ +#define RSCAN0_TXQCC0_COUNT 5 + union iodefine_reg32_t TXQCC0; /* TXQCC0 */ + union iodefine_reg32_t TXQCC1; /* TXQCC1 */ + union iodefine_reg32_t TXQCC2; /* TXQCC2 */ + union iodefine_reg32_t TXQCC3; /* TXQCC3 */ + union iodefine_reg32_t TXQCC4; /* TXQCC4 */ + + volatile uint8_t dummy171[12]; /* */ +#define RSCAN0_TXQSTS0_COUNT 5 + union iodefine_reg32_t TXQSTS0; /* TXQSTS0 */ + union iodefine_reg32_t TXQSTS1; /* TXQSTS1 */ + union iodefine_reg32_t TXQSTS2; /* TXQSTS2 */ + union iodefine_reg32_t TXQSTS3; /* TXQSTS3 */ + union iodefine_reg32_t TXQSTS4; /* TXQSTS4 */ + + volatile uint8_t dummy172[12]; /* */ +#define RSCAN0_TXQPCTR0_COUNT 5 + union iodefine_reg32_t TXQPCTR0; /* TXQPCTR0 */ + union iodefine_reg32_t TXQPCTR1; /* TXQPCTR1 */ + union iodefine_reg32_t TXQPCTR2; /* TXQPCTR2 */ + union iodefine_reg32_t TXQPCTR3; /* TXQPCTR3 */ + union iodefine_reg32_t TXQPCTR4; /* TXQPCTR4 */ + + volatile uint8_t dummy173[12]; /* */ +#define RSCAN0_THLCC0_COUNT 5 + union iodefine_reg32_t THLCC0; /* THLCC0 */ + union iodefine_reg32_t THLCC1; /* THLCC1 */ + union iodefine_reg32_t THLCC2; /* THLCC2 */ + union iodefine_reg32_t THLCC3; /* THLCC3 */ + union iodefine_reg32_t THLCC4; /* THLCC4 */ + + volatile uint8_t dummy174[12]; /* */ +#define RSCAN0_THLSTS0_COUNT 5 + union iodefine_reg32_t THLSTS0; /* THLSTS0 */ + union iodefine_reg32_t THLSTS1; /* THLSTS1 */ + union iodefine_reg32_t THLSTS2; /* THLSTS2 */ + union iodefine_reg32_t THLSTS3; /* THLSTS3 */ + union iodefine_reg32_t THLSTS4; /* THLSTS4 */ + + volatile uint8_t dummy175[12]; /* */ +#define RSCAN0_THLPCTR0_COUNT 5 + union iodefine_reg32_t THLPCTR0; /* THLPCTR0 */ + union iodefine_reg32_t THLPCTR1; /* THLPCTR1 */ + union iodefine_reg32_t THLPCTR2; /* THLPCTR2 */ + union iodefine_reg32_t THLPCTR3; /* THLPCTR3 */ + union iodefine_reg32_t THLPCTR4; /* THLPCTR4 */ + + volatile uint8_t dummy176[12]; /* */ +#define RSCAN0_GTINTSTS0_COUNT 2 + union iodefine_reg32_t GTINTSTS0; /* GTINTSTS0 */ + union iodefine_reg32_t GTINTSTS1; /* GTINTSTS1 */ + union iodefine_reg32_t GTSTCFG; /* GTSTCFG */ + union iodefine_reg32_t GTSTCTR; /* GTSTCTR */ + + volatile uint8_t dummy177[12]; /* */ + union iodefine_reg32_16_t GLOCKK; /* GLOCKK */ + + volatile uint8_t dummy178[128]; /* */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID0; /* GAFLID0 */ + union iodefine_reg32_t GAFLM0; /* GAFLM0 */ + union iodefine_reg32_t GAFLP00; /* GAFLP00 */ + union iodefine_reg32_t GAFLP10; /* GAFLP10 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID1; /* GAFLID1 */ + union iodefine_reg32_t GAFLM1; /* GAFLM1 */ + union iodefine_reg32_t GAFLP01; /* GAFLP01 */ + union iodefine_reg32_t GAFLP11; /* GAFLP11 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID2; /* GAFLID2 */ + union iodefine_reg32_t GAFLM2; /* GAFLM2 */ + union iodefine_reg32_t GAFLP02; /* GAFLP02 */ + union iodefine_reg32_t GAFLP12; /* GAFLP12 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID3; /* GAFLID3 */ + union iodefine_reg32_t GAFLM3; /* GAFLM3 */ + union iodefine_reg32_t GAFLP03; /* GAFLP03 */ + union iodefine_reg32_t GAFLP13; /* GAFLP13 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID4; /* GAFLID4 */ + union iodefine_reg32_t GAFLM4; /* GAFLM4 */ + union iodefine_reg32_t GAFLP04; /* GAFLP04 */ + union iodefine_reg32_t GAFLP14; /* GAFLP14 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID5; /* GAFLID5 */ + union iodefine_reg32_t GAFLM5; /* GAFLM5 */ + union iodefine_reg32_t GAFLP05; /* GAFLP05 */ + union iodefine_reg32_t GAFLP15; /* GAFLP15 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID6; /* GAFLID6 */ + union iodefine_reg32_t GAFLM6; /* GAFLM6 */ + union iodefine_reg32_t GAFLP06; /* GAFLP06 */ + union iodefine_reg32_t GAFLP16; /* GAFLP16 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID7; /* GAFLID7 */ + union iodefine_reg32_t GAFLM7; /* GAFLM7 */ + union iodefine_reg32_t GAFLP07; /* GAFLP07 */ + union iodefine_reg32_t GAFLP17; /* GAFLP17 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID8; /* GAFLID8 */ + union iodefine_reg32_t GAFLM8; /* GAFLM8 */ + union iodefine_reg32_t GAFLP08; /* GAFLP08 */ + union iodefine_reg32_t GAFLP18; /* GAFLP18 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID9; /* GAFLID9 */ + union iodefine_reg32_t GAFLM9; /* GAFLM9 */ + union iodefine_reg32_t GAFLP09; /* GAFLP09 */ + union iodefine_reg32_t GAFLP19; /* GAFLP19 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID10; /* GAFLID10 */ + union iodefine_reg32_t GAFLM10; /* GAFLM10 */ + union iodefine_reg32_t GAFLP010; /* GAFLP010 */ + union iodefine_reg32_t GAFLP110; /* GAFLP110 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID11; /* GAFLID11 */ + union iodefine_reg32_t GAFLM11; /* GAFLM11 */ + union iodefine_reg32_t GAFLP011; /* GAFLP011 */ + union iodefine_reg32_t GAFLP111; /* GAFLP111 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID12; /* GAFLID12 */ + union iodefine_reg32_t GAFLM12; /* GAFLM12 */ + union iodefine_reg32_t GAFLP012; /* GAFLP012 */ + union iodefine_reg32_t GAFLP112; /* GAFLP112 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID13; /* GAFLID13 */ + union iodefine_reg32_t GAFLM13; /* GAFLM13 */ + union iodefine_reg32_t GAFLP013; /* GAFLP013 */ + union iodefine_reg32_t GAFLP113; /* GAFLP113 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID14; /* GAFLID14 */ + union iodefine_reg32_t GAFLM14; /* GAFLM14 */ + union iodefine_reg32_t GAFLP014; /* GAFLP014 */ + union iodefine_reg32_t GAFLP114; /* GAFLP114 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID15; /* GAFLID15 */ + union iodefine_reg32_t GAFLM15; /* GAFLM15 */ + union iodefine_reg32_t GAFLP015; /* GAFLP015 */ + union iodefine_reg32_t GAFLP115; /* GAFLP115 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID0; /* RMID0 */ + union iodefine_reg32_t RMPTR0; /* RMPTR0 */ + union iodefine_reg32_t RMDF00; /* RMDF00 */ + union iodefine_reg32_t RMDF10; /* RMDF10 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID1; /* RMID1 */ + union iodefine_reg32_t RMPTR1; /* RMPTR1 */ + union iodefine_reg32_t RMDF01; /* RMDF01 */ + union iodefine_reg32_t RMDF11; /* RMDF11 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID2; /* RMID2 */ + union iodefine_reg32_t RMPTR2; /* RMPTR2 */ + union iodefine_reg32_t RMDF02; /* RMDF02 */ + union iodefine_reg32_t RMDF12; /* RMDF12 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID3; /* RMID3 */ + union iodefine_reg32_t RMPTR3; /* RMPTR3 */ + union iodefine_reg32_t RMDF03; /* RMDF03 */ + union iodefine_reg32_t RMDF13; /* RMDF13 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID4; /* RMID4 */ + union iodefine_reg32_t RMPTR4; /* RMPTR4 */ + union iodefine_reg32_t RMDF04; /* RMDF04 */ + union iodefine_reg32_t RMDF14; /* RMDF14 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID5; /* RMID5 */ + union iodefine_reg32_t RMPTR5; /* RMPTR5 */ + union iodefine_reg32_t RMDF05; /* RMDF05 */ + union iodefine_reg32_t RMDF15; /* RMDF15 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID6; /* RMID6 */ + union iodefine_reg32_t RMPTR6; /* RMPTR6 */ + union iodefine_reg32_t RMDF06; /* RMDF06 */ + union iodefine_reg32_t RMDF16; /* RMDF16 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID7; /* RMID7 */ + union iodefine_reg32_t RMPTR7; /* RMPTR7 */ + union iodefine_reg32_t RMDF07; /* RMDF07 */ + union iodefine_reg32_t RMDF17; /* RMDF17 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID8; /* RMID8 */ + union iodefine_reg32_t RMPTR8; /* RMPTR8 */ + union iodefine_reg32_t RMDF08; /* RMDF08 */ + union iodefine_reg32_t RMDF18; /* RMDF18 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID9; /* RMID9 */ + union iodefine_reg32_t RMPTR9; /* RMPTR9 */ + union iodefine_reg32_t RMDF09; /* RMDF09 */ + union iodefine_reg32_t RMDF19; /* RMDF19 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID10; /* RMID10 */ + union iodefine_reg32_t RMPTR10; /* RMPTR10 */ + union iodefine_reg32_t RMDF010; /* RMDF010 */ + union iodefine_reg32_t RMDF110; /* RMDF110 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID11; /* RMID11 */ + union iodefine_reg32_t RMPTR11; /* RMPTR11 */ + union iodefine_reg32_t RMDF011; /* RMDF011 */ + union iodefine_reg32_t RMDF111; /* RMDF111 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID12; /* RMID12 */ + union iodefine_reg32_t RMPTR12; /* RMPTR12 */ + union iodefine_reg32_t RMDF012; /* RMDF012 */ + union iodefine_reg32_t RMDF112; /* RMDF112 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID13; /* RMID13 */ + union iodefine_reg32_t RMPTR13; /* RMPTR13 */ + union iodefine_reg32_t RMDF013; /* RMDF013 */ + union iodefine_reg32_t RMDF113; /* RMDF113 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID14; /* RMID14 */ + union iodefine_reg32_t RMPTR14; /* RMPTR14 */ + union iodefine_reg32_t RMDF014; /* RMDF014 */ + union iodefine_reg32_t RMDF114; /* RMDF114 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID15; /* RMID15 */ + union iodefine_reg32_t RMPTR15; /* RMPTR15 */ + union iodefine_reg32_t RMDF015; /* RMDF015 */ + union iodefine_reg32_t RMDF115; /* RMDF115 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID16; /* RMID16 */ + union iodefine_reg32_t RMPTR16; /* RMPTR16 */ + union iodefine_reg32_t RMDF016; /* RMDF016 */ + union iodefine_reg32_t RMDF116; /* RMDF116 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID17; /* RMID17 */ + union iodefine_reg32_t RMPTR17; /* RMPTR17 */ + union iodefine_reg32_t RMDF017; /* RMDF017 */ + union iodefine_reg32_t RMDF117; /* RMDF117 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID18; /* RMID18 */ + union iodefine_reg32_t RMPTR18; /* RMPTR18 */ + union iodefine_reg32_t RMDF018; /* RMDF018 */ + union iodefine_reg32_t RMDF118; /* RMDF118 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID19; /* RMID19 */ + union iodefine_reg32_t RMPTR19; /* RMPTR19 */ + union iodefine_reg32_t RMDF019; /* RMDF019 */ + union iodefine_reg32_t RMDF119; /* RMDF119 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID20; /* RMID20 */ + union iodefine_reg32_t RMPTR20; /* RMPTR20 */ + union iodefine_reg32_t RMDF020; /* RMDF020 */ + union iodefine_reg32_t RMDF120; /* RMDF120 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID21; /* RMID21 */ + union iodefine_reg32_t RMPTR21; /* RMPTR21 */ + union iodefine_reg32_t RMDF021; /* RMDF021 */ + union iodefine_reg32_t RMDF121; /* RMDF121 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID22; /* RMID22 */ + union iodefine_reg32_t RMPTR22; /* RMPTR22 */ + union iodefine_reg32_t RMDF022; /* RMDF022 */ + union iodefine_reg32_t RMDF122; /* RMDF122 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID23; /* RMID23 */ + union iodefine_reg32_t RMPTR23; /* RMPTR23 */ + union iodefine_reg32_t RMDF023; /* RMDF023 */ + union iodefine_reg32_t RMDF123; /* RMDF123 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID24; /* RMID24 */ + union iodefine_reg32_t RMPTR24; /* RMPTR24 */ + union iodefine_reg32_t RMDF024; /* RMDF024 */ + union iodefine_reg32_t RMDF124; /* RMDF124 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID25; /* RMID25 */ + union iodefine_reg32_t RMPTR25; /* RMPTR25 */ + union iodefine_reg32_t RMDF025; /* RMDF025 */ + union iodefine_reg32_t RMDF125; /* RMDF125 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID26; /* RMID26 */ + union iodefine_reg32_t RMPTR26; /* RMPTR26 */ + union iodefine_reg32_t RMDF026; /* RMDF026 */ + union iodefine_reg32_t RMDF126; /* RMDF126 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID27; /* RMID27 */ + union iodefine_reg32_t RMPTR27; /* RMPTR27 */ + union iodefine_reg32_t RMDF027; /* RMDF027 */ + union iodefine_reg32_t RMDF127; /* RMDF127 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID28; /* RMID28 */ + union iodefine_reg32_t RMPTR28; /* RMPTR28 */ + union iodefine_reg32_t RMDF028; /* RMDF028 */ + union iodefine_reg32_t RMDF128; /* RMDF128 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID29; /* RMID29 */ + union iodefine_reg32_t RMPTR29; /* RMPTR29 */ + union iodefine_reg32_t RMDF029; /* RMDF029 */ + union iodefine_reg32_t RMDF129; /* RMDF129 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID30; /* RMID30 */ + union iodefine_reg32_t RMPTR30; /* RMPTR30 */ + union iodefine_reg32_t RMDF030; /* RMDF030 */ + union iodefine_reg32_t RMDF130; /* RMDF130 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID31; /* RMID31 */ + union iodefine_reg32_t RMPTR31; /* RMPTR31 */ + union iodefine_reg32_t RMDF031; /* RMDF031 */ + union iodefine_reg32_t RMDF131; /* RMDF131 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID32; /* RMID32 */ + union iodefine_reg32_t RMPTR32; /* RMPTR32 */ + union iodefine_reg32_t RMDF032; /* RMDF032 */ + union iodefine_reg32_t RMDF132; /* RMDF132 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID33; /* RMID33 */ + union iodefine_reg32_t RMPTR33; /* RMPTR33 */ + union iodefine_reg32_t RMDF033; /* RMDF033 */ + union iodefine_reg32_t RMDF133; /* RMDF133 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID34; /* RMID34 */ + union iodefine_reg32_t RMPTR34; /* RMPTR34 */ + union iodefine_reg32_t RMDF034; /* RMDF034 */ + union iodefine_reg32_t RMDF134; /* RMDF134 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID35; /* RMID35 */ + union iodefine_reg32_t RMPTR35; /* RMPTR35 */ + union iodefine_reg32_t RMDF035; /* RMDF035 */ + union iodefine_reg32_t RMDF135; /* RMDF135 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID36; /* RMID36 */ + union iodefine_reg32_t RMPTR36; /* RMPTR36 */ + union iodefine_reg32_t RMDF036; /* RMDF036 */ + union iodefine_reg32_t RMDF136; /* RMDF136 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID37; /* RMID37 */ + union iodefine_reg32_t RMPTR37; /* RMPTR37 */ + union iodefine_reg32_t RMDF037; /* RMDF037 */ + union iodefine_reg32_t RMDF137; /* RMDF137 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID38; /* RMID38 */ + union iodefine_reg32_t RMPTR38; /* RMPTR38 */ + union iodefine_reg32_t RMDF038; /* RMDF038 */ + union iodefine_reg32_t RMDF138; /* RMDF138 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID39; /* RMID39 */ + union iodefine_reg32_t RMPTR39; /* RMPTR39 */ + union iodefine_reg32_t RMDF039; /* RMDF039 */ + union iodefine_reg32_t RMDF139; /* RMDF139 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID40; /* RMID40 */ + union iodefine_reg32_t RMPTR40; /* RMPTR40 */ + union iodefine_reg32_t RMDF040; /* RMDF040 */ + union iodefine_reg32_t RMDF140; /* RMDF140 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID41; /* RMID41 */ + union iodefine_reg32_t RMPTR41; /* RMPTR41 */ + union iodefine_reg32_t RMDF041; /* RMDF041 */ + union iodefine_reg32_t RMDF141; /* RMDF141 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID42; /* RMID42 */ + union iodefine_reg32_t RMPTR42; /* RMPTR42 */ + union iodefine_reg32_t RMDF042; /* RMDF042 */ + union iodefine_reg32_t RMDF142; /* RMDF142 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID43; /* RMID43 */ + union iodefine_reg32_t RMPTR43; /* RMPTR43 */ + union iodefine_reg32_t RMDF043; /* RMDF043 */ + union iodefine_reg32_t RMDF143; /* RMDF143 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID44; /* RMID44 */ + union iodefine_reg32_t RMPTR44; /* RMPTR44 */ + union iodefine_reg32_t RMDF044; /* RMDF044 */ + union iodefine_reg32_t RMDF144; /* RMDF144 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID45; /* RMID45 */ + union iodefine_reg32_t RMPTR45; /* RMPTR45 */ + union iodefine_reg32_t RMDF045; /* RMDF045 */ + union iodefine_reg32_t RMDF145; /* RMDF145 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID46; /* RMID46 */ + union iodefine_reg32_t RMPTR46; /* RMPTR46 */ + union iodefine_reg32_t RMDF046; /* RMDF046 */ + union iodefine_reg32_t RMDF146; /* RMDF146 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID47; /* RMID47 */ + union iodefine_reg32_t RMPTR47; /* RMPTR47 */ + union iodefine_reg32_t RMDF047; /* RMDF047 */ + union iodefine_reg32_t RMDF147; /* RMDF147 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID48; /* RMID48 */ + union iodefine_reg32_t RMPTR48; /* RMPTR48 */ + union iodefine_reg32_t RMDF048; /* RMDF048 */ + union iodefine_reg32_t RMDF148; /* RMDF148 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID49; /* RMID49 */ + union iodefine_reg32_t RMPTR49; /* RMPTR49 */ + union iodefine_reg32_t RMDF049; /* RMDF049 */ + union iodefine_reg32_t RMDF149; /* RMDF149 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID50; /* RMID50 */ + union iodefine_reg32_t RMPTR50; /* RMPTR50 */ + union iodefine_reg32_t RMDF050; /* RMDF050 */ + union iodefine_reg32_t RMDF150; /* RMDF150 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID51; /* RMID51 */ + union iodefine_reg32_t RMPTR51; /* RMPTR51 */ + union iodefine_reg32_t RMDF051; /* RMDF051 */ + union iodefine_reg32_t RMDF151; /* RMDF151 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID52; /* RMID52 */ + union iodefine_reg32_t RMPTR52; /* RMPTR52 */ + union iodefine_reg32_t RMDF052; /* RMDF052 */ + union iodefine_reg32_t RMDF152; /* RMDF152 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID53; /* RMID53 */ + union iodefine_reg32_t RMPTR53; /* RMPTR53 */ + union iodefine_reg32_t RMDF053; /* RMDF053 */ + union iodefine_reg32_t RMDF153; /* RMDF153 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID54; /* RMID54 */ + union iodefine_reg32_t RMPTR54; /* RMPTR54 */ + union iodefine_reg32_t RMDF054; /* RMDF054 */ + union iodefine_reg32_t RMDF154; /* RMDF154 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID55; /* RMID55 */ + union iodefine_reg32_t RMPTR55; /* RMPTR55 */ + union iodefine_reg32_t RMDF055; /* RMDF055 */ + union iodefine_reg32_t RMDF155; /* RMDF155 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID56; /* RMID56 */ + union iodefine_reg32_t RMPTR56; /* RMPTR56 */ + union iodefine_reg32_t RMDF056; /* RMDF056 */ + union iodefine_reg32_t RMDF156; /* RMDF156 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID57; /* RMID57 */ + union iodefine_reg32_t RMPTR57; /* RMPTR57 */ + union iodefine_reg32_t RMDF057; /* RMDF057 */ + union iodefine_reg32_t RMDF157; /* RMDF157 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID58; /* RMID58 */ + union iodefine_reg32_t RMPTR58; /* RMPTR58 */ + union iodefine_reg32_t RMDF058; /* RMDF058 */ + union iodefine_reg32_t RMDF158; /* RMDF158 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID59; /* RMID59 */ + union iodefine_reg32_t RMPTR59; /* RMPTR59 */ + union iodefine_reg32_t RMDF059; /* RMDF059 */ + union iodefine_reg32_t RMDF159; /* RMDF159 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID60; /* RMID60 */ + union iodefine_reg32_t RMPTR60; /* RMPTR60 */ + union iodefine_reg32_t RMDF060; /* RMDF060 */ + union iodefine_reg32_t RMDF160; /* RMDF160 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID61; /* RMID61 */ + union iodefine_reg32_t RMPTR61; /* RMPTR61 */ + union iodefine_reg32_t RMDF061; /* RMDF061 */ + union iodefine_reg32_t RMDF161; /* RMDF161 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID62; /* RMID62 */ + union iodefine_reg32_t RMPTR62; /* RMPTR62 */ + union iodefine_reg32_t RMDF062; /* RMDF062 */ + union iodefine_reg32_t RMDF162; /* RMDF162 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID63; /* RMID63 */ + union iodefine_reg32_t RMPTR63; /* RMPTR63 */ + union iodefine_reg32_t RMDF063; /* RMDF063 */ + union iodefine_reg32_t RMDF163; /* RMDF163 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID64; /* RMID64 */ + union iodefine_reg32_t RMPTR64; /* RMPTR64 */ + union iodefine_reg32_t RMDF064; /* RMDF064 */ + union iodefine_reg32_t RMDF164; /* RMDF164 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID65; /* RMID65 */ + union iodefine_reg32_t RMPTR65; /* RMPTR65 */ + union iodefine_reg32_t RMDF065; /* RMDF065 */ + union iodefine_reg32_t RMDF165; /* RMDF165 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID66; /* RMID66 */ + union iodefine_reg32_t RMPTR66; /* RMPTR66 */ + union iodefine_reg32_t RMDF066; /* RMDF066 */ + union iodefine_reg32_t RMDF166; /* RMDF166 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID67; /* RMID67 */ + union iodefine_reg32_t RMPTR67; /* RMPTR67 */ + union iodefine_reg32_t RMDF067; /* RMDF067 */ + union iodefine_reg32_t RMDF167; /* RMDF167 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID68; /* RMID68 */ + union iodefine_reg32_t RMPTR68; /* RMPTR68 */ + union iodefine_reg32_t RMDF068; /* RMDF068 */ + union iodefine_reg32_t RMDF168; /* RMDF168 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID69; /* RMID69 */ + union iodefine_reg32_t RMPTR69; /* RMPTR69 */ + union iodefine_reg32_t RMDF069; /* RMDF069 */ + union iodefine_reg32_t RMDF169; /* RMDF169 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID70; /* RMID70 */ + union iodefine_reg32_t RMPTR70; /* RMPTR70 */ + union iodefine_reg32_t RMDF070; /* RMDF070 */ + union iodefine_reg32_t RMDF170; /* RMDF170 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID71; /* RMID71 */ + union iodefine_reg32_t RMPTR71; /* RMPTR71 */ + union iodefine_reg32_t RMDF071; /* RMDF071 */ + union iodefine_reg32_t RMDF171; /* RMDF171 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID72; /* RMID72 */ + union iodefine_reg32_t RMPTR72; /* RMPTR72 */ + union iodefine_reg32_t RMDF072; /* RMDF072 */ + union iodefine_reg32_t RMDF172; /* RMDF172 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID73; /* RMID73 */ + union iodefine_reg32_t RMPTR73; /* RMPTR73 */ + union iodefine_reg32_t RMDF073; /* RMDF073 */ + union iodefine_reg32_t RMDF173; /* RMDF173 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID74; /* RMID74 */ + union iodefine_reg32_t RMPTR74; /* RMPTR74 */ + union iodefine_reg32_t RMDF074; /* RMDF074 */ + union iodefine_reg32_t RMDF174; /* RMDF174 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID75; /* RMID75 */ + union iodefine_reg32_t RMPTR75; /* RMPTR75 */ + union iodefine_reg32_t RMDF075; /* RMDF075 */ + union iodefine_reg32_t RMDF175; /* RMDF175 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID76; /* RMID76 */ + union iodefine_reg32_t RMPTR76; /* RMPTR76 */ + union iodefine_reg32_t RMDF076; /* RMDF076 */ + union iodefine_reg32_t RMDF176; /* RMDF176 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID77; /* RMID77 */ + union iodefine_reg32_t RMPTR77; /* RMPTR77 */ + union iodefine_reg32_t RMDF077; /* RMDF077 */ + union iodefine_reg32_t RMDF177; /* RMDF177 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID78; /* RMID78 */ + union iodefine_reg32_t RMPTR78; /* RMPTR78 */ + union iodefine_reg32_t RMDF078; /* RMDF078 */ + union iodefine_reg32_t RMDF178; /* RMDF178 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID79; /* RMID79 */ + union iodefine_reg32_t RMPTR79; /* RMPTR79 */ + union iodefine_reg32_t RMDF079; /* RMDF079 */ + union iodefine_reg32_t RMDF179; /* RMDF179 */ +/* end of struct st_rscan_from_rscan0rmidp */ + + volatile uint8_t dummy179[768]; /* */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID0; /* RFID0 */ + union iodefine_reg32_t RFPTR0; /* RFPTR0 */ + union iodefine_reg32_t RFDF00; /* RFDF00 */ + union iodefine_reg32_t RFDF10; /* RFDF10 */ +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID1; /* RFID1 */ + union iodefine_reg32_t RFPTR1; /* RFPTR1 */ + union iodefine_reg32_t RFDF01; /* RFDF01 */ + union iodefine_reg32_t RFDF11; /* RFDF11 */ +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID2; /* RFID2 */ + union iodefine_reg32_t RFPTR2; /* RFPTR2 */ + union iodefine_reg32_t RFDF02; /* RFDF02 */ + union iodefine_reg32_t RFDF12; /* RFDF12 */ +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID3; /* RFID3 */ + union iodefine_reg32_t RFPTR3; /* RFPTR3 */ + union iodefine_reg32_t RFDF03; /* RFDF03 */ + union iodefine_reg32_t RFDF13; /* RFDF13 */ +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID4; /* RFID4 */ + union iodefine_reg32_t RFPTR4; /* RFPTR4 */ + union iodefine_reg32_t RFDF04; /* RFDF04 */ + union iodefine_reg32_t RFDF14; /* RFDF14 */ +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID5; /* RFID5 */ + union iodefine_reg32_t RFPTR5; /* RFPTR5 */ + union iodefine_reg32_t RFDF05; /* RFDF05 */ + union iodefine_reg32_t RFDF15; /* RFDF15 */ +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID6; /* RFID6 */ + union iodefine_reg32_t RFPTR6; /* RFPTR6 */ + union iodefine_reg32_t RFDF06; /* RFDF06 */ + union iodefine_reg32_t RFDF16; /* RFDF16 */ +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID7; /* RFID7 */ + union iodefine_reg32_t RFPTR7; /* RFPTR7 */ + union iodefine_reg32_t RFDF07; /* RFDF07 */ + union iodefine_reg32_t RFDF17; /* RFDF17 */ +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID0; /* CFID0 */ + union iodefine_reg32_t CFPTR0; /* CFPTR0 */ + union iodefine_reg32_t CFDF00; /* CFDF00 */ + union iodefine_reg32_t CFDF10; /* CFDF10 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID1; /* CFID1 */ + union iodefine_reg32_t CFPTR1; /* CFPTR1 */ + union iodefine_reg32_t CFDF01; /* CFDF01 */ + union iodefine_reg32_t CFDF11; /* CFDF11 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID2; /* CFID2 */ + union iodefine_reg32_t CFPTR2; /* CFPTR2 */ + union iodefine_reg32_t CFDF02; /* CFDF02 */ + union iodefine_reg32_t CFDF12; /* CFDF12 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID3; /* CFID3 */ + union iodefine_reg32_t CFPTR3; /* CFPTR3 */ + union iodefine_reg32_t CFDF03; /* CFDF03 */ + union iodefine_reg32_t CFDF13; /* CFDF13 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID4; /* CFID4 */ + union iodefine_reg32_t CFPTR4; /* CFPTR4 */ + union iodefine_reg32_t CFDF04; /* CFDF04 */ + union iodefine_reg32_t CFDF14; /* CFDF14 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID5; /* CFID5 */ + union iodefine_reg32_t CFPTR5; /* CFPTR5 */ + union iodefine_reg32_t CFDF05; /* CFDF05 */ + union iodefine_reg32_t CFDF15; /* CFDF15 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID6; /* CFID6 */ + union iodefine_reg32_t CFPTR6; /* CFPTR6 */ + union iodefine_reg32_t CFDF06; /* CFDF06 */ + union iodefine_reg32_t CFDF16; /* CFDF16 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID7; /* CFID7 */ + union iodefine_reg32_t CFPTR7; /* CFPTR7 */ + union iodefine_reg32_t CFDF07; /* CFDF07 */ + union iodefine_reg32_t CFDF17; /* CFDF17 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID8; /* CFID8 */ + union iodefine_reg32_t CFPTR8; /* CFPTR8 */ + union iodefine_reg32_t CFDF08; /* CFDF08 */ + union iodefine_reg32_t CFDF18; /* CFDF18 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID9; /* CFID9 */ + union iodefine_reg32_t CFPTR9; /* CFPTR9 */ + union iodefine_reg32_t CFDF09; /* CFDF09 */ + union iodefine_reg32_t CFDF19; /* CFDF19 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID10; /* CFID10 */ + union iodefine_reg32_t CFPTR10; /* CFPTR10 */ + union iodefine_reg32_t CFDF010; /* CFDF010 */ + union iodefine_reg32_t CFDF110; /* CFDF110 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID11; /* CFID11 */ + union iodefine_reg32_t CFPTR11; /* CFPTR11 */ + union iodefine_reg32_t CFDF011; /* CFDF011 */ + union iodefine_reg32_t CFDF111; /* CFDF111 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID12; /* CFID12 */ + union iodefine_reg32_t CFPTR12; /* CFPTR12 */ + union iodefine_reg32_t CFDF012; /* CFDF012 */ + union iodefine_reg32_t CFDF112; /* CFDF112 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID13; /* CFID13 */ + union iodefine_reg32_t CFPTR13; /* CFPTR13 */ + union iodefine_reg32_t CFDF013; /* CFDF013 */ + union iodefine_reg32_t CFDF113; /* CFDF113 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID14; /* CFID14 */ + union iodefine_reg32_t CFPTR14; /* CFPTR14 */ + union iodefine_reg32_t CFDF014; /* CFDF014 */ + union iodefine_reg32_t CFDF114; /* CFDF114 */ +/* end of struct st_rscan_from_rscan0cfidm */ + + volatile uint8_t dummy180[144]; /* */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID0; /* TMID0 */ + union iodefine_reg32_t TMPTR0; /* TMPTR0 */ + union iodefine_reg32_t TMDF00; /* TMDF00 */ + union iodefine_reg32_t TMDF10; /* TMDF10 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID1; /* TMID1 */ + union iodefine_reg32_t TMPTR1; /* TMPTR1 */ + union iodefine_reg32_t TMDF01; /* TMDF01 */ + union iodefine_reg32_t TMDF11; /* TMDF11 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID2; /* TMID2 */ + union iodefine_reg32_t TMPTR2; /* TMPTR2 */ + union iodefine_reg32_t TMDF02; /* TMDF02 */ + union iodefine_reg32_t TMDF12; /* TMDF12 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID3; /* TMID3 */ + union iodefine_reg32_t TMPTR3; /* TMPTR3 */ + union iodefine_reg32_t TMDF03; /* TMDF03 */ + union iodefine_reg32_t TMDF13; /* TMDF13 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID4; /* TMID4 */ + union iodefine_reg32_t TMPTR4; /* TMPTR4 */ + union iodefine_reg32_t TMDF04; /* TMDF04 */ + union iodefine_reg32_t TMDF14; /* TMDF14 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID5; /* TMID5 */ + union iodefine_reg32_t TMPTR5; /* TMPTR5 */ + union iodefine_reg32_t TMDF05; /* TMDF05 */ + union iodefine_reg32_t TMDF15; /* TMDF15 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID6; /* TMID6 */ + union iodefine_reg32_t TMPTR6; /* TMPTR6 */ + union iodefine_reg32_t TMDF06; /* TMDF06 */ + union iodefine_reg32_t TMDF16; /* TMDF16 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID7; /* TMID7 */ + union iodefine_reg32_t TMPTR7; /* TMPTR7 */ + union iodefine_reg32_t TMDF07; /* TMDF07 */ + union iodefine_reg32_t TMDF17; /* TMDF17 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID8; /* TMID8 */ + union iodefine_reg32_t TMPTR8; /* TMPTR8 */ + union iodefine_reg32_t TMDF08; /* TMDF08 */ + union iodefine_reg32_t TMDF18; /* TMDF18 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID9; /* TMID9 */ + union iodefine_reg32_t TMPTR9; /* TMPTR9 */ + union iodefine_reg32_t TMDF09; /* TMDF09 */ + union iodefine_reg32_t TMDF19; /* TMDF19 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID10; /* TMID10 */ + union iodefine_reg32_t TMPTR10; /* TMPTR10 */ + union iodefine_reg32_t TMDF010; /* TMDF010 */ + union iodefine_reg32_t TMDF110; /* TMDF110 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID11; /* TMID11 */ + union iodefine_reg32_t TMPTR11; /* TMPTR11 */ + union iodefine_reg32_t TMDF011; /* TMDF011 */ + union iodefine_reg32_t TMDF111; /* TMDF111 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID12; /* TMID12 */ + union iodefine_reg32_t TMPTR12; /* TMPTR12 */ + union iodefine_reg32_t TMDF012; /* TMDF012 */ + union iodefine_reg32_t TMDF112; /* TMDF112 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID13; /* TMID13 */ + union iodefine_reg32_t TMPTR13; /* TMPTR13 */ + union iodefine_reg32_t TMDF013; /* TMDF013 */ + union iodefine_reg32_t TMDF113; /* TMDF113 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID14; /* TMID14 */ + union iodefine_reg32_t TMPTR14; /* TMPTR14 */ + union iodefine_reg32_t TMDF014; /* TMDF014 */ + union iodefine_reg32_t TMDF114; /* TMDF114 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID15; /* TMID15 */ + union iodefine_reg32_t TMPTR15; /* TMPTR15 */ + union iodefine_reg32_t TMDF015; /* TMDF015 */ + union iodefine_reg32_t TMDF115; /* TMDF115 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID16; /* TMID16 */ + union iodefine_reg32_t TMPTR16; /* TMPTR16 */ + union iodefine_reg32_t TMDF016; /* TMDF016 */ + union iodefine_reg32_t TMDF116; /* TMDF116 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID17; /* TMID17 */ + union iodefine_reg32_t TMPTR17; /* TMPTR17 */ + union iodefine_reg32_t TMDF017; /* TMDF017 */ + union iodefine_reg32_t TMDF117; /* TMDF117 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID18; /* TMID18 */ + union iodefine_reg32_t TMPTR18; /* TMPTR18 */ + union iodefine_reg32_t TMDF018; /* TMDF018 */ + union iodefine_reg32_t TMDF118; /* TMDF118 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID19; /* TMID19 */ + union iodefine_reg32_t TMPTR19; /* TMPTR19 */ + union iodefine_reg32_t TMDF019; /* TMDF019 */ + union iodefine_reg32_t TMDF119; /* TMDF119 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID20; /* TMID20 */ + union iodefine_reg32_t TMPTR20; /* TMPTR20 */ + union iodefine_reg32_t TMDF020; /* TMDF020 */ + union iodefine_reg32_t TMDF120; /* TMDF120 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID21; /* TMID21 */ + union iodefine_reg32_t TMPTR21; /* TMPTR21 */ + union iodefine_reg32_t TMDF021; /* TMDF021 */ + union iodefine_reg32_t TMDF121; /* TMDF121 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID22; /* TMID22 */ + union iodefine_reg32_t TMPTR22; /* TMPTR22 */ + union iodefine_reg32_t TMDF022; /* TMDF022 */ + union iodefine_reg32_t TMDF122; /* TMDF122 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID23; /* TMID23 */ + union iodefine_reg32_t TMPTR23; /* TMPTR23 */ + union iodefine_reg32_t TMDF023; /* TMDF023 */ + union iodefine_reg32_t TMDF123; /* TMDF123 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID24; /* TMID24 */ + union iodefine_reg32_t TMPTR24; /* TMPTR24 */ + union iodefine_reg32_t TMDF024; /* TMDF024 */ + union iodefine_reg32_t TMDF124; /* TMDF124 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID25; /* TMID25 */ + union iodefine_reg32_t TMPTR25; /* TMPTR25 */ + union iodefine_reg32_t TMDF025; /* TMDF025 */ + union iodefine_reg32_t TMDF125; /* TMDF125 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID26; /* TMID26 */ + union iodefine_reg32_t TMPTR26; /* TMPTR26 */ + union iodefine_reg32_t TMDF026; /* TMDF026 */ + union iodefine_reg32_t TMDF126; /* TMDF126 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID27; /* TMID27 */ + union iodefine_reg32_t TMPTR27; /* TMPTR27 */ + union iodefine_reg32_t TMDF027; /* TMDF027 */ + union iodefine_reg32_t TMDF127; /* TMDF127 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID28; /* TMID28 */ + union iodefine_reg32_t TMPTR28; /* TMPTR28 */ + union iodefine_reg32_t TMDF028; /* TMDF028 */ + union iodefine_reg32_t TMDF128; /* TMDF128 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID29; /* TMID29 */ + union iodefine_reg32_t TMPTR29; /* TMPTR29 */ + union iodefine_reg32_t TMDF029; /* TMDF029 */ + union iodefine_reg32_t TMDF129; /* TMDF129 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID30; /* TMID30 */ + union iodefine_reg32_t TMPTR30; /* TMPTR30 */ + union iodefine_reg32_t TMDF030; /* TMDF030 */ + union iodefine_reg32_t TMDF130; /* TMDF130 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID31; /* TMID31 */ + union iodefine_reg32_t TMPTR31; /* TMPTR31 */ + union iodefine_reg32_t TMDF031; /* TMDF031 */ + union iodefine_reg32_t TMDF131; /* TMDF131 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID32; /* TMID32 */ + union iodefine_reg32_t TMPTR32; /* TMPTR32 */ + union iodefine_reg32_t TMDF032; /* TMDF032 */ + union iodefine_reg32_t TMDF132; /* TMDF132 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID33; /* TMID33 */ + union iodefine_reg32_t TMPTR33; /* TMPTR33 */ + union iodefine_reg32_t TMDF033; /* TMDF033 */ + union iodefine_reg32_t TMDF133; /* TMDF133 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID34; /* TMID34 */ + union iodefine_reg32_t TMPTR34; /* TMPTR34 */ + union iodefine_reg32_t TMDF034; /* TMDF034 */ + union iodefine_reg32_t TMDF134; /* TMDF134 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID35; /* TMID35 */ + union iodefine_reg32_t TMPTR35; /* TMPTR35 */ + union iodefine_reg32_t TMDF035; /* TMDF035 */ + union iodefine_reg32_t TMDF135; /* TMDF135 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID36; /* TMID36 */ + union iodefine_reg32_t TMPTR36; /* TMPTR36 */ + union iodefine_reg32_t TMDF036; /* TMDF036 */ + union iodefine_reg32_t TMDF136; /* TMDF136 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID37; /* TMID37 */ + union iodefine_reg32_t TMPTR37; /* TMPTR37 */ + union iodefine_reg32_t TMDF037; /* TMDF037 */ + union iodefine_reg32_t TMDF137; /* TMDF137 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID38; /* TMID38 */ + union iodefine_reg32_t TMPTR38; /* TMPTR38 */ + union iodefine_reg32_t TMDF038; /* TMDF038 */ + union iodefine_reg32_t TMDF138; /* TMDF138 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID39; /* TMID39 */ + union iodefine_reg32_t TMPTR39; /* TMPTR39 */ + union iodefine_reg32_t TMDF039; /* TMDF039 */ + union iodefine_reg32_t TMDF139; /* TMDF139 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID40; /* TMID40 */ + union iodefine_reg32_t TMPTR40; /* TMPTR40 */ + union iodefine_reg32_t TMDF040; /* TMDF040 */ + union iodefine_reg32_t TMDF140; /* TMDF140 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID41; /* TMID41 */ + union iodefine_reg32_t TMPTR41; /* TMPTR41 */ + union iodefine_reg32_t TMDF041; /* TMDF041 */ + union iodefine_reg32_t TMDF141; /* TMDF141 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID42; /* TMID42 */ + union iodefine_reg32_t TMPTR42; /* TMPTR42 */ + union iodefine_reg32_t TMDF042; /* TMDF042 */ + union iodefine_reg32_t TMDF142; /* TMDF142 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID43; /* TMID43 */ + union iodefine_reg32_t TMPTR43; /* TMPTR43 */ + union iodefine_reg32_t TMDF043; /* TMDF043 */ + union iodefine_reg32_t TMDF143; /* TMDF143 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID44; /* TMID44 */ + union iodefine_reg32_t TMPTR44; /* TMPTR44 */ + union iodefine_reg32_t TMDF044; /* TMDF044 */ + union iodefine_reg32_t TMDF144; /* TMDF144 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID45; /* TMID45 */ + union iodefine_reg32_t TMPTR45; /* TMPTR45 */ + union iodefine_reg32_t TMDF045; /* TMDF045 */ + union iodefine_reg32_t TMDF145; /* TMDF145 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID46; /* TMID46 */ + union iodefine_reg32_t TMPTR46; /* TMPTR46 */ + union iodefine_reg32_t TMDF046; /* TMDF046 */ + union iodefine_reg32_t TMDF146; /* TMDF146 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID47; /* TMID47 */ + union iodefine_reg32_t TMPTR47; /* TMPTR47 */ + union iodefine_reg32_t TMDF047; /* TMDF047 */ + union iodefine_reg32_t TMDF147; /* TMDF147 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID48; /* TMID48 */ + union iodefine_reg32_t TMPTR48; /* TMPTR48 */ + union iodefine_reg32_t TMDF048; /* TMDF048 */ + union iodefine_reg32_t TMDF148; /* TMDF148 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID49; /* TMID49 */ + union iodefine_reg32_t TMPTR49; /* TMPTR49 */ + union iodefine_reg32_t TMDF049; /* TMDF049 */ + union iodefine_reg32_t TMDF149; /* TMDF149 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID50; /* TMID50 */ + union iodefine_reg32_t TMPTR50; /* TMPTR50 */ + union iodefine_reg32_t TMDF050; /* TMDF050 */ + union iodefine_reg32_t TMDF150; /* TMDF150 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID51; /* TMID51 */ + union iodefine_reg32_t TMPTR51; /* TMPTR51 */ + union iodefine_reg32_t TMDF051; /* TMDF051 */ + union iodefine_reg32_t TMDF151; /* TMDF151 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID52; /* TMID52 */ + union iodefine_reg32_t TMPTR52; /* TMPTR52 */ + union iodefine_reg32_t TMDF052; /* TMDF052 */ + union iodefine_reg32_t TMDF152; /* TMDF152 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID53; /* TMID53 */ + union iodefine_reg32_t TMPTR53; /* TMPTR53 */ + union iodefine_reg32_t TMDF053; /* TMDF053 */ + union iodefine_reg32_t TMDF153; /* TMDF153 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID54; /* TMID54 */ + union iodefine_reg32_t TMPTR54; /* TMPTR54 */ + union iodefine_reg32_t TMDF054; /* TMDF054 */ + union iodefine_reg32_t TMDF154; /* TMDF154 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID55; /* TMID55 */ + union iodefine_reg32_t TMPTR55; /* TMPTR55 */ + union iodefine_reg32_t TMDF055; /* TMDF055 */ + union iodefine_reg32_t TMDF155; /* TMDF155 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID56; /* TMID56 */ + union iodefine_reg32_t TMPTR56; /* TMPTR56 */ + union iodefine_reg32_t TMDF056; /* TMDF056 */ + union iodefine_reg32_t TMDF156; /* TMDF156 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID57; /* TMID57 */ + union iodefine_reg32_t TMPTR57; /* TMPTR57 */ + union iodefine_reg32_t TMDF057; /* TMDF057 */ + union iodefine_reg32_t TMDF157; /* TMDF157 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID58; /* TMID58 */ + union iodefine_reg32_t TMPTR58; /* TMPTR58 */ + union iodefine_reg32_t TMDF058; /* TMDF058 */ + union iodefine_reg32_t TMDF158; /* TMDF158 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID59; /* TMID59 */ + union iodefine_reg32_t TMPTR59; /* TMPTR59 */ + union iodefine_reg32_t TMDF059; /* TMDF059 */ + union iodefine_reg32_t TMDF159; /* TMDF159 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID60; /* TMID60 */ + union iodefine_reg32_t TMPTR60; /* TMPTR60 */ + union iodefine_reg32_t TMDF060; /* TMDF060 */ + union iodefine_reg32_t TMDF160; /* TMDF160 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID61; /* TMID61 */ + union iodefine_reg32_t TMPTR61; /* TMPTR61 */ + union iodefine_reg32_t TMDF061; /* TMDF061 */ + union iodefine_reg32_t TMDF161; /* TMDF161 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID62; /* TMID62 */ + union iodefine_reg32_t TMPTR62; /* TMPTR62 */ + union iodefine_reg32_t TMDF062; /* TMDF062 */ + union iodefine_reg32_t TMDF162; /* TMDF162 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID63; /* TMID63 */ + union iodefine_reg32_t TMPTR63; /* TMPTR63 */ + union iodefine_reg32_t TMDF063; /* TMDF063 */ + union iodefine_reg32_t TMDF163; /* TMDF163 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID64; /* TMID64 */ + union iodefine_reg32_t TMPTR64; /* TMPTR64 */ + union iodefine_reg32_t TMDF064; /* TMDF064 */ + union iodefine_reg32_t TMDF164; /* TMDF164 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID65; /* TMID65 */ + union iodefine_reg32_t TMPTR65; /* TMPTR65 */ + union iodefine_reg32_t TMDF065; /* TMDF065 */ + union iodefine_reg32_t TMDF165; /* TMDF165 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID66; /* TMID66 */ + union iodefine_reg32_t TMPTR66; /* TMPTR66 */ + union iodefine_reg32_t TMDF066; /* TMDF066 */ + union iodefine_reg32_t TMDF166; /* TMDF166 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID67; /* TMID67 */ + union iodefine_reg32_t TMPTR67; /* TMPTR67 */ + union iodefine_reg32_t TMDF067; /* TMDF067 */ + union iodefine_reg32_t TMDF167; /* TMDF167 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID68; /* TMID68 */ + union iodefine_reg32_t TMPTR68; /* TMPTR68 */ + union iodefine_reg32_t TMDF068; /* TMDF068 */ + union iodefine_reg32_t TMDF168; /* TMDF168 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID69; /* TMID69 */ + union iodefine_reg32_t TMPTR69; /* TMPTR69 */ + union iodefine_reg32_t TMDF069; /* TMDF069 */ + union iodefine_reg32_t TMDF169; /* TMDF169 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID70; /* TMID70 */ + union iodefine_reg32_t TMPTR70; /* TMPTR70 */ + union iodefine_reg32_t TMDF070; /* TMDF070 */ + union iodefine_reg32_t TMDF170; /* TMDF170 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID71; /* TMID71 */ + union iodefine_reg32_t TMPTR71; /* TMPTR71 */ + union iodefine_reg32_t TMDF071; /* TMDF071 */ + union iodefine_reg32_t TMDF171; /* TMDF171 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID72; /* TMID72 */ + union iodefine_reg32_t TMPTR72; /* TMPTR72 */ + union iodefine_reg32_t TMDF072; /* TMDF072 */ + union iodefine_reg32_t TMDF172; /* TMDF172 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID73; /* TMID73 */ + union iodefine_reg32_t TMPTR73; /* TMPTR73 */ + union iodefine_reg32_t TMDF073; /* TMDF073 */ + union iodefine_reg32_t TMDF173; /* TMDF173 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID74; /* TMID74 */ + union iodefine_reg32_t TMPTR74; /* TMPTR74 */ + union iodefine_reg32_t TMDF074; /* TMDF074 */ + union iodefine_reg32_t TMDF174; /* TMDF174 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID75; /* TMID75 */ + union iodefine_reg32_t TMPTR75; /* TMPTR75 */ + union iodefine_reg32_t TMDF075; /* TMDF075 */ + union iodefine_reg32_t TMDF175; /* TMDF175 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID76; /* TMID76 */ + union iodefine_reg32_t TMPTR76; /* TMPTR76 */ + union iodefine_reg32_t TMDF076; /* TMDF076 */ + union iodefine_reg32_t TMDF176; /* TMDF176 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID77; /* TMID77 */ + union iodefine_reg32_t TMPTR77; /* TMPTR77 */ + union iodefine_reg32_t TMDF077; /* TMDF077 */ + union iodefine_reg32_t TMDF177; /* TMDF177 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID78; /* TMID78 */ + union iodefine_reg32_t TMPTR78; /* TMPTR78 */ + union iodefine_reg32_t TMDF078; /* TMDF078 */ + union iodefine_reg32_t TMDF178; /* TMDF178 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID79; /* TMID79 */ + union iodefine_reg32_t TMPTR79; /* TMPTR79 */ + union iodefine_reg32_t TMDF079; /* TMDF079 */ + union iodefine_reg32_t TMDF179; /* TMDF179 */ +/* end of struct st_rscan_from_rscan0tmidp */ + + volatile uint8_t dummy181[768]; /* */ +#define RSCAN0_THLACC0_COUNT 5 + union iodefine_reg32_t THLACC0; /* THLACC0 */ + union iodefine_reg32_t THLACC1; /* THLACC1 */ + union iodefine_reg32_t THLACC2; /* THLACC2 */ + union iodefine_reg32_t THLACC3; /* THLACC3 */ + union iodefine_reg32_t THLACC4; /* THLACC4 */ + +}; + + +struct st_rscan_from_rscan0cncfg +{ + union iodefine_reg32_t CnCFG; /* CnCFG */ + union iodefine_reg32_t CnCTR; /* CnCTR */ + union iodefine_reg32_t CnSTS; /* CnSTS */ + union iodefine_reg32_t CnERFL; /* CnERFL */ +}; + + +struct st_rscan_from_rscan0gaflidj +{ + union iodefine_reg32_t GAFLIDj; /* GAFLIDj */ + union iodefine_reg32_t GAFLMj; /* GAFLMj */ + union iodefine_reg32_t GAFLP0j; /* GAFLP0j */ + union iodefine_reg32_t GAFLP1j; /* GAFLP1j */ +}; + + +struct st_rscan_from_rscan0rmidp +{ + union iodefine_reg32_t RMIDp; /* RMIDp */ + union iodefine_reg32_t RMPTRp; /* RMPTRp */ + union iodefine_reg32_t RMDF0p; /* RMDF0p */ + union iodefine_reg32_t RMDF1p; /* RMDF1p */ +}; + + +struct st_rscan_from_rscan0rfidm +{ + union iodefine_reg32_t RFIDm; /* RFIDm */ + union iodefine_reg32_t RFPTRm; /* RFPTRm */ + union iodefine_reg32_t RFDF0m; /* RFDF0m */ + union iodefine_reg32_t RFDF1m; /* RFDF1m */ +}; + + +struct st_rscan_from_rscan0tmidp +{ + union iodefine_reg32_t TMIDp; /* TMIDp */ + union iodefine_reg32_t TMPTRp; /* TMPTRp */ + union iodefine_reg32_t TMDF0p; /* TMDF0p */ + union iodefine_reg32_t TMDF1p; /* TMDF1p */ +}; + + +struct st_rscan_from_rscan0cfidm +{ + union iodefine_reg32_t CFIDm; /* CFIDm */ + union iodefine_reg32_t CFPTRm; /* CFPTRm */ + union iodefine_reg32_t CFDF0m; /* CFDF0m */ + union iodefine_reg32_t CFDF1m; /* CFDF1m */ +}; + + +#define RSCAN0 (*(struct st_rscan0 *)0xE803A000uL) /* RSCAN0 */ + + +/* Start of channnel array defines of RSCAN0 */ + +/* Channnel array defines of RSCAN_FROM_RSCAN0CFIDm */ +/*(Sample) value = RSCAN_FROM_RSCAN0CFIDm[ channel ]->CFIDm.UINT32; */ +#define RSCAN_FROM_RSCAN0CFIDm_COUNT 15 +#define RSCAN_FROM_RSCAN0CFIDm_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSCAN_FROM_RSCAN0CFID0, &RSCAN_FROM_RSCAN0CFID1, &RSCAN_FROM_RSCAN0CFID2, &RSCAN_FROM_RSCAN0CFID3, &RSCAN_FROM_RSCAN0CFID4, &RSCAN_FROM_RSCAN0CFID5, &RSCAN_FROM_RSCAN0CFID6, &RSCAN_FROM_RSCAN0CFID7, \ + &RSCAN_FROM_RSCAN0CFID8, &RSCAN_FROM_RSCAN0CFID9, &RSCAN_FROM_RSCAN0CFID10, &RSCAN_FROM_RSCAN0CFID11, &RSCAN_FROM_RSCAN0CFID12, &RSCAN_FROM_RSCAN0CFID13, &RSCAN_FROM_RSCAN0CFID14 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define RSCAN_FROM_RSCAN0CFID0 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID0) /* RSCAN_FROM_RSCAN0CFID0 */ +#define RSCAN_FROM_RSCAN0CFID1 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID1) /* RSCAN_FROM_RSCAN0CFID1 */ +#define RSCAN_FROM_RSCAN0CFID2 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID2) /* RSCAN_FROM_RSCAN0CFID2 */ +#define RSCAN_FROM_RSCAN0CFID3 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID3) /* RSCAN_FROM_RSCAN0CFID3 */ +#define RSCAN_FROM_RSCAN0CFID4 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID4) /* RSCAN_FROM_RSCAN0CFID4 */ +#define RSCAN_FROM_RSCAN0CFID5 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID5) /* RSCAN_FROM_RSCAN0CFID5 */ +#define RSCAN_FROM_RSCAN0CFID6 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID6) /* RSCAN_FROM_RSCAN0CFID6 */ +#define RSCAN_FROM_RSCAN0CFID7 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID7) /* RSCAN_FROM_RSCAN0CFID7 */ +#define RSCAN_FROM_RSCAN0CFID8 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID8) /* RSCAN_FROM_RSCAN0CFID8 */ +#define RSCAN_FROM_RSCAN0CFID9 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID9) /* RSCAN_FROM_RSCAN0CFID9 */ +#define RSCAN_FROM_RSCAN0CFID10 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID10) /* RSCAN_FROM_RSCAN0CFID10 */ +#define RSCAN_FROM_RSCAN0CFID11 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID11) /* RSCAN_FROM_RSCAN0CFID11 */ +#define RSCAN_FROM_RSCAN0CFID12 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID12) /* RSCAN_FROM_RSCAN0CFID12 */ +#define RSCAN_FROM_RSCAN0CFID13 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID13) /* RSCAN_FROM_RSCAN0CFID13 */ +#define RSCAN_FROM_RSCAN0CFID14 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID14) /* RSCAN_FROM_RSCAN0CFID14 */ + + +/* Channnel array defines of RSCAN_FROM_RSCAN0TMIDp */ +/*(Sample) value = RSCAN_FROM_RSCAN0TMIDp[ channel ]->TMIDp.UINT32; */ +#define RSCAN_FROM_RSCAN0TMIDp_COUNT 80 +#define RSCAN_FROM_RSCAN0TMIDp_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSCAN_FROM_RSCAN0TMID0, &RSCAN_FROM_RSCAN0TMID1, &RSCAN_FROM_RSCAN0TMID2, &RSCAN_FROM_RSCAN0TMID3, &RSCAN_FROM_RSCAN0TMID4, &RSCAN_FROM_RSCAN0TMID5, &RSCAN_FROM_RSCAN0TMID6, &RSCAN_FROM_RSCAN0TMID7, \ + &RSCAN_FROM_RSCAN0TMID8, &RSCAN_FROM_RSCAN0TMID9, &RSCAN_FROM_RSCAN0TMID10, &RSCAN_FROM_RSCAN0TMID11, &RSCAN_FROM_RSCAN0TMID12, &RSCAN_FROM_RSCAN0TMID13, &RSCAN_FROM_RSCAN0TMID14, &RSCAN_FROM_RSCAN0TMID15, \ + &RSCAN_FROM_RSCAN0TMID16, &RSCAN_FROM_RSCAN0TMID17, &RSCAN_FROM_RSCAN0TMID18, &RSCAN_FROM_RSCAN0TMID19, &RSCAN_FROM_RSCAN0TMID20, &RSCAN_FROM_RSCAN0TMID21, &RSCAN_FROM_RSCAN0TMID22, &RSCAN_FROM_RSCAN0TMID23, \ + &RSCAN_FROM_RSCAN0TMID24, &RSCAN_FROM_RSCAN0TMID25, &RSCAN_FROM_RSCAN0TMID26, &RSCAN_FROM_RSCAN0TMID27, &RSCAN_FROM_RSCAN0TMID28, &RSCAN_FROM_RSCAN0TMID29, &RSCAN_FROM_RSCAN0TMID30, &RSCAN_FROM_RSCAN0TMID31, \ + &RSCAN_FROM_RSCAN0TMID32, &RSCAN_FROM_RSCAN0TMID33, &RSCAN_FROM_RSCAN0TMID34, &RSCAN_FROM_RSCAN0TMID35, &RSCAN_FROM_RSCAN0TMID36, &RSCAN_FROM_RSCAN0TMID37, &RSCAN_FROM_RSCAN0TMID38, &RSCAN_FROM_RSCAN0TMID39, \ + &RSCAN_FROM_RSCAN0TMID40, &RSCAN_FROM_RSCAN0TMID41, &RSCAN_FROM_RSCAN0TMID42, &RSCAN_FROM_RSCAN0TMID43, &RSCAN_FROM_RSCAN0TMID44, &RSCAN_FROM_RSCAN0TMID45, &RSCAN_FROM_RSCAN0TMID46, &RSCAN_FROM_RSCAN0TMID47, \ + &RSCAN_FROM_RSCAN0TMID48, &RSCAN_FROM_RSCAN0TMID49, &RSCAN_FROM_RSCAN0TMID50, &RSCAN_FROM_RSCAN0TMID51, &RSCAN_FROM_RSCAN0TMID52, &RSCAN_FROM_RSCAN0TMID53, &RSCAN_FROM_RSCAN0TMID54, &RSCAN_FROM_RSCAN0TMID55, \ + &RSCAN_FROM_RSCAN0TMID56, &RSCAN_FROM_RSCAN0TMID57, &RSCAN_FROM_RSCAN0TMID58, &RSCAN_FROM_RSCAN0TMID59, &RSCAN_FROM_RSCAN0TMID60, &RSCAN_FROM_RSCAN0TMID61, &RSCAN_FROM_RSCAN0TMID62, &RSCAN_FROM_RSCAN0TMID63, \ + &RSCAN_FROM_RSCAN0TMID64, &RSCAN_FROM_RSCAN0TMID65, &RSCAN_FROM_RSCAN0TMID66, &RSCAN_FROM_RSCAN0TMID67, &RSCAN_FROM_RSCAN0TMID68, &RSCAN_FROM_RSCAN0TMID69, &RSCAN_FROM_RSCAN0TMID70, &RSCAN_FROM_RSCAN0TMID71, \ + &RSCAN_FROM_RSCAN0TMID72, &RSCAN_FROM_RSCAN0TMID73, &RSCAN_FROM_RSCAN0TMID74, &RSCAN_FROM_RSCAN0TMID75, &RSCAN_FROM_RSCAN0TMID76, &RSCAN_FROM_RSCAN0TMID77, &RSCAN_FROM_RSCAN0TMID78, &RSCAN_FROM_RSCAN0TMID79 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define RSCAN_FROM_RSCAN0TMID0 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID0) /* RSCAN_FROM_RSCAN0TMID0 */ +#define RSCAN_FROM_RSCAN0TMID1 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID1) /* RSCAN_FROM_RSCAN0TMID1 */ +#define RSCAN_FROM_RSCAN0TMID2 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID2) /* RSCAN_FROM_RSCAN0TMID2 */ +#define RSCAN_FROM_RSCAN0TMID3 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID3) /* RSCAN_FROM_RSCAN0TMID3 */ +#define RSCAN_FROM_RSCAN0TMID4 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID4) /* RSCAN_FROM_RSCAN0TMID4 */ +#define RSCAN_FROM_RSCAN0TMID5 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID5) /* RSCAN_FROM_RSCAN0TMID5 */ +#define RSCAN_FROM_RSCAN0TMID6 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID6) /* RSCAN_FROM_RSCAN0TMID6 */ +#define RSCAN_FROM_RSCAN0TMID7 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID7) /* RSCAN_FROM_RSCAN0TMID7 */ +#define RSCAN_FROM_RSCAN0TMID8 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID8) /* RSCAN_FROM_RSCAN0TMID8 */ +#define RSCAN_FROM_RSCAN0TMID9 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID9) /* RSCAN_FROM_RSCAN0TMID9 */ +#define RSCAN_FROM_RSCAN0TMID10 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID10) /* RSCAN_FROM_RSCAN0TMID10 */ +#define RSCAN_FROM_RSCAN0TMID11 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID11) /* RSCAN_FROM_RSCAN0TMID11 */ +#define RSCAN_FROM_RSCAN0TMID12 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID12) /* RSCAN_FROM_RSCAN0TMID12 */ +#define RSCAN_FROM_RSCAN0TMID13 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID13) /* RSCAN_FROM_RSCAN0TMID13 */ +#define RSCAN_FROM_RSCAN0TMID14 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID14) /* RSCAN_FROM_RSCAN0TMID14 */ +#define RSCAN_FROM_RSCAN0TMID15 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID15) /* RSCAN_FROM_RSCAN0TMID15 */ +#define RSCAN_FROM_RSCAN0TMID16 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID16) /* RSCAN_FROM_RSCAN0TMID16 */ +#define RSCAN_FROM_RSCAN0TMID17 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID17) /* RSCAN_FROM_RSCAN0TMID17 */ +#define RSCAN_FROM_RSCAN0TMID18 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID18) /* RSCAN_FROM_RSCAN0TMID18 */ +#define RSCAN_FROM_RSCAN0TMID19 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID19) /* RSCAN_FROM_RSCAN0TMID19 */ +#define RSCAN_FROM_RSCAN0TMID20 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID20) /* RSCAN_FROM_RSCAN0TMID20 */ +#define RSCAN_FROM_RSCAN0TMID21 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID21) /* RSCAN_FROM_RSCAN0TMID21 */ +#define RSCAN_FROM_RSCAN0TMID22 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID22) /* RSCAN_FROM_RSCAN0TMID22 */ +#define RSCAN_FROM_RSCAN0TMID23 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID23) /* RSCAN_FROM_RSCAN0TMID23 */ +#define RSCAN_FROM_RSCAN0TMID24 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID24) /* RSCAN_FROM_RSCAN0TMID24 */ +#define RSCAN_FROM_RSCAN0TMID25 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID25) /* RSCAN_FROM_RSCAN0TMID25 */ +#define RSCAN_FROM_RSCAN0TMID26 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID26) /* RSCAN_FROM_RSCAN0TMID26 */ +#define RSCAN_FROM_RSCAN0TMID27 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID27) /* RSCAN_FROM_RSCAN0TMID27 */ +#define RSCAN_FROM_RSCAN0TMID28 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID28) /* RSCAN_FROM_RSCAN0TMID28 */ +#define RSCAN_FROM_RSCAN0TMID29 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID29) /* RSCAN_FROM_RSCAN0TMID29 */ +#define RSCAN_FROM_RSCAN0TMID30 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID30) /* RSCAN_FROM_RSCAN0TMID30 */ +#define RSCAN_FROM_RSCAN0TMID31 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID31) /* RSCAN_FROM_RSCAN0TMID31 */ +#define RSCAN_FROM_RSCAN0TMID32 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID32) /* RSCAN_FROM_RSCAN0TMID32 */ +#define RSCAN_FROM_RSCAN0TMID33 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID33) /* RSCAN_FROM_RSCAN0TMID33 */ +#define RSCAN_FROM_RSCAN0TMID34 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID34) /* RSCAN_FROM_RSCAN0TMID34 */ +#define RSCAN_FROM_RSCAN0TMID35 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID35) /* RSCAN_FROM_RSCAN0TMID35 */ +#define RSCAN_FROM_RSCAN0TMID36 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID36) /* RSCAN_FROM_RSCAN0TMID36 */ +#define RSCAN_FROM_RSCAN0TMID37 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID37) /* RSCAN_FROM_RSCAN0TMID37 */ +#define RSCAN_FROM_RSCAN0TMID38 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID38) /* RSCAN_FROM_RSCAN0TMID38 */ +#define RSCAN_FROM_RSCAN0TMID39 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID39) /* RSCAN_FROM_RSCAN0TMID39 */ +#define RSCAN_FROM_RSCAN0TMID40 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID40) /* RSCAN_FROM_RSCAN0TMID40 */ +#define RSCAN_FROM_RSCAN0TMID41 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID41) /* RSCAN_FROM_RSCAN0TMID41 */ +#define RSCAN_FROM_RSCAN0TMID42 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID42) /* RSCAN_FROM_RSCAN0TMID42 */ +#define RSCAN_FROM_RSCAN0TMID43 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID43) /* RSCAN_FROM_RSCAN0TMID43 */ +#define RSCAN_FROM_RSCAN0TMID44 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID44) /* RSCAN_FROM_RSCAN0TMID44 */ +#define RSCAN_FROM_RSCAN0TMID45 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID45) /* RSCAN_FROM_RSCAN0TMID45 */ +#define RSCAN_FROM_RSCAN0TMID46 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID46) /* RSCAN_FROM_RSCAN0TMID46 */ +#define RSCAN_FROM_RSCAN0TMID47 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID47) /* RSCAN_FROM_RSCAN0TMID47 */ +#define RSCAN_FROM_RSCAN0TMID48 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID48) /* RSCAN_FROM_RSCAN0TMID48 */ +#define RSCAN_FROM_RSCAN0TMID49 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID49) /* RSCAN_FROM_RSCAN0TMID49 */ +#define RSCAN_FROM_RSCAN0TMID50 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID50) /* RSCAN_FROM_RSCAN0TMID50 */ +#define RSCAN_FROM_RSCAN0TMID51 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID51) /* RSCAN_FROM_RSCAN0TMID51 */ +#define RSCAN_FROM_RSCAN0TMID52 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID52) /* RSCAN_FROM_RSCAN0TMID52 */ +#define RSCAN_FROM_RSCAN0TMID53 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID53) /* RSCAN_FROM_RSCAN0TMID53 */ +#define RSCAN_FROM_RSCAN0TMID54 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID54) /* RSCAN_FROM_RSCAN0TMID54 */ +#define RSCAN_FROM_RSCAN0TMID55 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID55) /* RSCAN_FROM_RSCAN0TMID55 */ +#define RSCAN_FROM_RSCAN0TMID56 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID56) /* RSCAN_FROM_RSCAN0TMID56 */ +#define RSCAN_FROM_RSCAN0TMID57 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID57) /* RSCAN_FROM_RSCAN0TMID57 */ +#define RSCAN_FROM_RSCAN0TMID58 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID58) /* RSCAN_FROM_RSCAN0TMID58 */ +#define RSCAN_FROM_RSCAN0TMID59 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID59) /* RSCAN_FROM_RSCAN0TMID59 */ +#define RSCAN_FROM_RSCAN0TMID60 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID60) /* RSCAN_FROM_RSCAN0TMID60 */ +#define RSCAN_FROM_RSCAN0TMID61 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID61) /* RSCAN_FROM_RSCAN0TMID61 */ +#define RSCAN_FROM_RSCAN0TMID62 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID62) /* RSCAN_FROM_RSCAN0TMID62 */ +#define RSCAN_FROM_RSCAN0TMID63 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID63) /* RSCAN_FROM_RSCAN0TMID63 */ +#define RSCAN_FROM_RSCAN0TMID64 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID64) /* RSCAN_FROM_RSCAN0TMID64 */ +#define RSCAN_FROM_RSCAN0TMID65 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID65) /* RSCAN_FROM_RSCAN0TMID65 */ +#define RSCAN_FROM_RSCAN0TMID66 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID66) /* RSCAN_FROM_RSCAN0TMID66 */ +#define RSCAN_FROM_RSCAN0TMID67 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID67) /* RSCAN_FROM_RSCAN0TMID67 */ +#define RSCAN_FROM_RSCAN0TMID68 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID68) /* RSCAN_FROM_RSCAN0TMID68 */ +#define RSCAN_FROM_RSCAN0TMID69 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID69) /* RSCAN_FROM_RSCAN0TMID69 */ +#define RSCAN_FROM_RSCAN0TMID70 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID70) /* RSCAN_FROM_RSCAN0TMID70 */ +#define RSCAN_FROM_RSCAN0TMID71 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID71) /* RSCAN_FROM_RSCAN0TMID71 */ +#define RSCAN_FROM_RSCAN0TMID72 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID72) /* RSCAN_FROM_RSCAN0TMID72 */ +#define RSCAN_FROM_RSCAN0TMID73 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID73) /* RSCAN_FROM_RSCAN0TMID73 */ +#define RSCAN_FROM_RSCAN0TMID74 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID74) /* RSCAN_FROM_RSCAN0TMID74 */ +#define RSCAN_FROM_RSCAN0TMID75 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID75) /* RSCAN_FROM_RSCAN0TMID75 */ +#define RSCAN_FROM_RSCAN0TMID76 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID76) /* RSCAN_FROM_RSCAN0TMID76 */ +#define RSCAN_FROM_RSCAN0TMID77 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID77) /* RSCAN_FROM_RSCAN0TMID77 */ +#define RSCAN_FROM_RSCAN0TMID78 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID78) /* RSCAN_FROM_RSCAN0TMID78 */ +#define RSCAN_FROM_RSCAN0TMID79 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID79) /* RSCAN_FROM_RSCAN0TMID79 */ + + +/* Channnel array defines of RSCAN_FROM_RSCAN0RFIDm */ +/*(Sample) value = RSCAN_FROM_RSCAN0RFIDm[ channel ]->RFIDm.UINT32; */ +#define RSCAN_FROM_RSCAN0RFIDm_COUNT 8 +#define RSCAN_FROM_RSCAN0RFIDm_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSCAN_FROM_RSCAN0RFID0, &RSCAN_FROM_RSCAN0RFID1, &RSCAN_FROM_RSCAN0RFID2, &RSCAN_FROM_RSCAN0RFID3, &RSCAN_FROM_RSCAN0RFID4, &RSCAN_FROM_RSCAN0RFID5, &RSCAN_FROM_RSCAN0RFID6, &RSCAN_FROM_RSCAN0RFID7 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define RSCAN_FROM_RSCAN0RFID0 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID0) /* RSCAN_FROM_RSCAN0RFID0 */ +#define RSCAN_FROM_RSCAN0RFID1 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID1) /* RSCAN_FROM_RSCAN0RFID1 */ +#define RSCAN_FROM_RSCAN0RFID2 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID2) /* RSCAN_FROM_RSCAN0RFID2 */ +#define RSCAN_FROM_RSCAN0RFID3 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID3) /* RSCAN_FROM_RSCAN0RFID3 */ +#define RSCAN_FROM_RSCAN0RFID4 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID4) /* RSCAN_FROM_RSCAN0RFID4 */ +#define RSCAN_FROM_RSCAN0RFID5 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID5) /* RSCAN_FROM_RSCAN0RFID5 */ +#define RSCAN_FROM_RSCAN0RFID6 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID6) /* RSCAN_FROM_RSCAN0RFID6 */ +#define RSCAN_FROM_RSCAN0RFID7 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID7) /* RSCAN_FROM_RSCAN0RFID7 */ + + +/* Channnel array defines of RSCAN_FROM_RSCAN0RMIDp */ +/*(Sample) value = RSCAN_FROM_RSCAN0RMIDp[ channel ]->RMIDp.UINT32; */ +#define RSCAN_FROM_RSCAN0RMIDp_COUNT 80 +#define RSCAN_FROM_RSCAN0RMIDp_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSCAN_FROM_RSCAN0RMID0, &RSCAN_FROM_RSCAN0RMID1, &RSCAN_FROM_RSCAN0RMID2, &RSCAN_FROM_RSCAN0RMID3, &RSCAN_FROM_RSCAN0RMID4, &RSCAN_FROM_RSCAN0RMID5, &RSCAN_FROM_RSCAN0RMID6, &RSCAN_FROM_RSCAN0RMID7, \ + &RSCAN_FROM_RSCAN0RMID8, &RSCAN_FROM_RSCAN0RMID9, &RSCAN_FROM_RSCAN0RMID10, &RSCAN_FROM_RSCAN0RMID11, &RSCAN_FROM_RSCAN0RMID12, &RSCAN_FROM_RSCAN0RMID13, &RSCAN_FROM_RSCAN0RMID14, &RSCAN_FROM_RSCAN0RMID15, \ + &RSCAN_FROM_RSCAN0RMID16, &RSCAN_FROM_RSCAN0RMID17, &RSCAN_FROM_RSCAN0RMID18, &RSCAN_FROM_RSCAN0RMID19, &RSCAN_FROM_RSCAN0RMID20, &RSCAN_FROM_RSCAN0RMID21, &RSCAN_FROM_RSCAN0RMID22, &RSCAN_FROM_RSCAN0RMID23, \ + &RSCAN_FROM_RSCAN0RMID24, &RSCAN_FROM_RSCAN0RMID25, &RSCAN_FROM_RSCAN0RMID26, &RSCAN_FROM_RSCAN0RMID27, &RSCAN_FROM_RSCAN0RMID28, &RSCAN_FROM_RSCAN0RMID29, &RSCAN_FROM_RSCAN0RMID30, &RSCAN_FROM_RSCAN0RMID31, \ + &RSCAN_FROM_RSCAN0RMID32, &RSCAN_FROM_RSCAN0RMID33, &RSCAN_FROM_RSCAN0RMID34, &RSCAN_FROM_RSCAN0RMID35, &RSCAN_FROM_RSCAN0RMID36, &RSCAN_FROM_RSCAN0RMID37, &RSCAN_FROM_RSCAN0RMID38, &RSCAN_FROM_RSCAN0RMID39, \ + &RSCAN_FROM_RSCAN0RMID40, &RSCAN_FROM_RSCAN0RMID41, &RSCAN_FROM_RSCAN0RMID42, &RSCAN_FROM_RSCAN0RMID43, &RSCAN_FROM_RSCAN0RMID44, &RSCAN_FROM_RSCAN0RMID45, &RSCAN_FROM_RSCAN0RMID46, &RSCAN_FROM_RSCAN0RMID47, \ + &RSCAN_FROM_RSCAN0RMID48, &RSCAN_FROM_RSCAN0RMID49, &RSCAN_FROM_RSCAN0RMID50, &RSCAN_FROM_RSCAN0RMID51, &RSCAN_FROM_RSCAN0RMID52, &RSCAN_FROM_RSCAN0RMID53, &RSCAN_FROM_RSCAN0RMID54, &RSCAN_FROM_RSCAN0RMID55, \ + &RSCAN_FROM_RSCAN0RMID56, &RSCAN_FROM_RSCAN0RMID57, &RSCAN_FROM_RSCAN0RMID58, &RSCAN_FROM_RSCAN0RMID59, &RSCAN_FROM_RSCAN0RMID60, &RSCAN_FROM_RSCAN0RMID61, &RSCAN_FROM_RSCAN0RMID62, &RSCAN_FROM_RSCAN0RMID63, \ + &RSCAN_FROM_RSCAN0RMID64, &RSCAN_FROM_RSCAN0RMID65, &RSCAN_FROM_RSCAN0RMID66, &RSCAN_FROM_RSCAN0RMID67, &RSCAN_FROM_RSCAN0RMID68, &RSCAN_FROM_RSCAN0RMID69, &RSCAN_FROM_RSCAN0RMID70, &RSCAN_FROM_RSCAN0RMID71, \ + &RSCAN_FROM_RSCAN0RMID72, &RSCAN_FROM_RSCAN0RMID73, &RSCAN_FROM_RSCAN0RMID74, &RSCAN_FROM_RSCAN0RMID75, &RSCAN_FROM_RSCAN0RMID76, &RSCAN_FROM_RSCAN0RMID77, &RSCAN_FROM_RSCAN0RMID78, &RSCAN_FROM_RSCAN0RMID79 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define RSCAN_FROM_RSCAN0RMID0 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID0) /* RSCAN_FROM_RSCAN0RMID0 */ +#define RSCAN_FROM_RSCAN0RMID1 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID1) /* RSCAN_FROM_RSCAN0RMID1 */ +#define RSCAN_FROM_RSCAN0RMID2 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID2) /* RSCAN_FROM_RSCAN0RMID2 */ +#define RSCAN_FROM_RSCAN0RMID3 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID3) /* RSCAN_FROM_RSCAN0RMID3 */ +#define RSCAN_FROM_RSCAN0RMID4 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID4) /* RSCAN_FROM_RSCAN0RMID4 */ +#define RSCAN_FROM_RSCAN0RMID5 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID5) /* RSCAN_FROM_RSCAN0RMID5 */ +#define RSCAN_FROM_RSCAN0RMID6 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID6) /* RSCAN_FROM_RSCAN0RMID6 */ +#define RSCAN_FROM_RSCAN0RMID7 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID7) /* RSCAN_FROM_RSCAN0RMID7 */ +#define RSCAN_FROM_RSCAN0RMID8 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID8) /* RSCAN_FROM_RSCAN0RMID8 */ +#define RSCAN_FROM_RSCAN0RMID9 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID9) /* RSCAN_FROM_RSCAN0RMID9 */ +#define RSCAN_FROM_RSCAN0RMID10 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID10) /* RSCAN_FROM_RSCAN0RMID10 */ +#define RSCAN_FROM_RSCAN0RMID11 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID11) /* RSCAN_FROM_RSCAN0RMID11 */ +#define RSCAN_FROM_RSCAN0RMID12 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID12) /* RSCAN_FROM_RSCAN0RMID12 */ +#define RSCAN_FROM_RSCAN0RMID13 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID13) /* RSCAN_FROM_RSCAN0RMID13 */ +#define RSCAN_FROM_RSCAN0RMID14 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID14) /* RSCAN_FROM_RSCAN0RMID14 */ +#define RSCAN_FROM_RSCAN0RMID15 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID15) /* RSCAN_FROM_RSCAN0RMID15 */ +#define RSCAN_FROM_RSCAN0RMID16 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID16) /* RSCAN_FROM_RSCAN0RMID16 */ +#define RSCAN_FROM_RSCAN0RMID17 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID17) /* RSCAN_FROM_RSCAN0RMID17 */ +#define RSCAN_FROM_RSCAN0RMID18 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID18) /* RSCAN_FROM_RSCAN0RMID18 */ +#define RSCAN_FROM_RSCAN0RMID19 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID19) /* RSCAN_FROM_RSCAN0RMID19 */ +#define RSCAN_FROM_RSCAN0RMID20 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID20) /* RSCAN_FROM_RSCAN0RMID20 */ +#define RSCAN_FROM_RSCAN0RMID21 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID21) /* RSCAN_FROM_RSCAN0RMID21 */ +#define RSCAN_FROM_RSCAN0RMID22 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID22) /* RSCAN_FROM_RSCAN0RMID22 */ +#define RSCAN_FROM_RSCAN0RMID23 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID23) /* RSCAN_FROM_RSCAN0RMID23 */ +#define RSCAN_FROM_RSCAN0RMID24 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID24) /* RSCAN_FROM_RSCAN0RMID24 */ +#define RSCAN_FROM_RSCAN0RMID25 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID25) /* RSCAN_FROM_RSCAN0RMID25 */ +#define RSCAN_FROM_RSCAN0RMID26 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID26) /* RSCAN_FROM_RSCAN0RMID26 */ +#define RSCAN_FROM_RSCAN0RMID27 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID27) /* RSCAN_FROM_RSCAN0RMID27 */ +#define RSCAN_FROM_RSCAN0RMID28 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID28) /* RSCAN_FROM_RSCAN0RMID28 */ +#define RSCAN_FROM_RSCAN0RMID29 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID29) /* RSCAN_FROM_RSCAN0RMID29 */ +#define RSCAN_FROM_RSCAN0RMID30 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID30) /* RSCAN_FROM_RSCAN0RMID30 */ +#define RSCAN_FROM_RSCAN0RMID31 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID31) /* RSCAN_FROM_RSCAN0RMID31 */ +#define RSCAN_FROM_RSCAN0RMID32 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID32) /* RSCAN_FROM_RSCAN0RMID32 */ +#define RSCAN_FROM_RSCAN0RMID33 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID33) /* RSCAN_FROM_RSCAN0RMID33 */ +#define RSCAN_FROM_RSCAN0RMID34 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID34) /* RSCAN_FROM_RSCAN0RMID34 */ +#define RSCAN_FROM_RSCAN0RMID35 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID35) /* RSCAN_FROM_RSCAN0RMID35 */ +#define RSCAN_FROM_RSCAN0RMID36 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID36) /* RSCAN_FROM_RSCAN0RMID36 */ +#define RSCAN_FROM_RSCAN0RMID37 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID37) /* RSCAN_FROM_RSCAN0RMID37 */ +#define RSCAN_FROM_RSCAN0RMID38 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID38) /* RSCAN_FROM_RSCAN0RMID38 */ +#define RSCAN_FROM_RSCAN0RMID39 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID39) /* RSCAN_FROM_RSCAN0RMID39 */ +#define RSCAN_FROM_RSCAN0RMID40 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID40) /* RSCAN_FROM_RSCAN0RMID40 */ +#define RSCAN_FROM_RSCAN0RMID41 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID41) /* RSCAN_FROM_RSCAN0RMID41 */ +#define RSCAN_FROM_RSCAN0RMID42 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID42) /* RSCAN_FROM_RSCAN0RMID42 */ +#define RSCAN_FROM_RSCAN0RMID43 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID43) /* RSCAN_FROM_RSCAN0RMID43 */ +#define RSCAN_FROM_RSCAN0RMID44 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID44) /* RSCAN_FROM_RSCAN0RMID44 */ +#define RSCAN_FROM_RSCAN0RMID45 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID45) /* RSCAN_FROM_RSCAN0RMID45 */ +#define RSCAN_FROM_RSCAN0RMID46 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID46) /* RSCAN_FROM_RSCAN0RMID46 */ +#define RSCAN_FROM_RSCAN0RMID47 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID47) /* RSCAN_FROM_RSCAN0RMID47 */ +#define RSCAN_FROM_RSCAN0RMID48 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID48) /* RSCAN_FROM_RSCAN0RMID48 */ +#define RSCAN_FROM_RSCAN0RMID49 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID49) /* RSCAN_FROM_RSCAN0RMID49 */ +#define RSCAN_FROM_RSCAN0RMID50 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID50) /* RSCAN_FROM_RSCAN0RMID50 */ +#define RSCAN_FROM_RSCAN0RMID51 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID51) /* RSCAN_FROM_RSCAN0RMID51 */ +#define RSCAN_FROM_RSCAN0RMID52 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID52) /* RSCAN_FROM_RSCAN0RMID52 */ +#define RSCAN_FROM_RSCAN0RMID53 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID53) /* RSCAN_FROM_RSCAN0RMID53 */ +#define RSCAN_FROM_RSCAN0RMID54 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID54) /* RSCAN_FROM_RSCAN0RMID54 */ +#define RSCAN_FROM_RSCAN0RMID55 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID55) /* RSCAN_FROM_RSCAN0RMID55 */ +#define RSCAN_FROM_RSCAN0RMID56 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID56) /* RSCAN_FROM_RSCAN0RMID56 */ +#define RSCAN_FROM_RSCAN0RMID57 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID57) /* RSCAN_FROM_RSCAN0RMID57 */ +#define RSCAN_FROM_RSCAN0RMID58 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID58) /* RSCAN_FROM_RSCAN0RMID58 */ +#define RSCAN_FROM_RSCAN0RMID59 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID59) /* RSCAN_FROM_RSCAN0RMID59 */ +#define RSCAN_FROM_RSCAN0RMID60 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID60) /* RSCAN_FROM_RSCAN0RMID60 */ +#define RSCAN_FROM_RSCAN0RMID61 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID61) /* RSCAN_FROM_RSCAN0RMID61 */ +#define RSCAN_FROM_RSCAN0RMID62 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID62) /* RSCAN_FROM_RSCAN0RMID62 */ +#define RSCAN_FROM_RSCAN0RMID63 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID63) /* RSCAN_FROM_RSCAN0RMID63 */ +#define RSCAN_FROM_RSCAN0RMID64 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID64) /* RSCAN_FROM_RSCAN0RMID64 */ +#define RSCAN_FROM_RSCAN0RMID65 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID65) /* RSCAN_FROM_RSCAN0RMID65 */ +#define RSCAN_FROM_RSCAN0RMID66 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID66) /* RSCAN_FROM_RSCAN0RMID66 */ +#define RSCAN_FROM_RSCAN0RMID67 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID67) /* RSCAN_FROM_RSCAN0RMID67 */ +#define RSCAN_FROM_RSCAN0RMID68 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID68) /* RSCAN_FROM_RSCAN0RMID68 */ +#define RSCAN_FROM_RSCAN0RMID69 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID69) /* RSCAN_FROM_RSCAN0RMID69 */ +#define RSCAN_FROM_RSCAN0RMID70 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID70) /* RSCAN_FROM_RSCAN0RMID70 */ +#define RSCAN_FROM_RSCAN0RMID71 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID71) /* RSCAN_FROM_RSCAN0RMID71 */ +#define RSCAN_FROM_RSCAN0RMID72 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID72) /* RSCAN_FROM_RSCAN0RMID72 */ +#define RSCAN_FROM_RSCAN0RMID73 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID73) /* RSCAN_FROM_RSCAN0RMID73 */ +#define RSCAN_FROM_RSCAN0RMID74 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID74) /* RSCAN_FROM_RSCAN0RMID74 */ +#define RSCAN_FROM_RSCAN0RMID75 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID75) /* RSCAN_FROM_RSCAN0RMID75 */ +#define RSCAN_FROM_RSCAN0RMID76 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID76) /* RSCAN_FROM_RSCAN0RMID76 */ +#define RSCAN_FROM_RSCAN0RMID77 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID77) /* RSCAN_FROM_RSCAN0RMID77 */ +#define RSCAN_FROM_RSCAN0RMID78 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID78) /* RSCAN_FROM_RSCAN0RMID78 */ +#define RSCAN_FROM_RSCAN0RMID79 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID79) /* RSCAN_FROM_RSCAN0RMID79 */ + + +/* Channnel array defines of RSCAN_FROM_RSCAN0GAFLIDj */ +/*(Sample) value = RSCAN_FROM_RSCAN0GAFLIDj[ channel ]->GAFLIDj.UINT32; */ +#define RSCAN_FROM_RSCAN0GAFLIDj_COUNT 16 +#define RSCAN_FROM_RSCAN0GAFLIDj_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSCAN_FROM_RSCAN0GAFLID0, &RSCAN_FROM_RSCAN0GAFLID1, &RSCAN_FROM_RSCAN0GAFLID2, &RSCAN_FROM_RSCAN0GAFLID3, &RSCAN_FROM_RSCAN0GAFLID4, &RSCAN_FROM_RSCAN0GAFLID5, &RSCAN_FROM_RSCAN0GAFLID6, &RSCAN_FROM_RSCAN0GAFLID7, \ + &RSCAN_FROM_RSCAN0GAFLID8, &RSCAN_FROM_RSCAN0GAFLID9, &RSCAN_FROM_RSCAN0GAFLID10, &RSCAN_FROM_RSCAN0GAFLID11, &RSCAN_FROM_RSCAN0GAFLID12, &RSCAN_FROM_RSCAN0GAFLID13, &RSCAN_FROM_RSCAN0GAFLID14, &RSCAN_FROM_RSCAN0GAFLID15 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define RSCAN_FROM_RSCAN0GAFLID0 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID0) /* RSCAN_FROM_RSCAN0GAFLID0 */ +#define RSCAN_FROM_RSCAN0GAFLID1 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID1) /* RSCAN_FROM_RSCAN0GAFLID1 */ +#define RSCAN_FROM_RSCAN0GAFLID2 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID2) /* RSCAN_FROM_RSCAN0GAFLID2 */ +#define RSCAN_FROM_RSCAN0GAFLID3 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID3) /* RSCAN_FROM_RSCAN0GAFLID3 */ +#define RSCAN_FROM_RSCAN0GAFLID4 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID4) /* RSCAN_FROM_RSCAN0GAFLID4 */ +#define RSCAN_FROM_RSCAN0GAFLID5 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID5) /* RSCAN_FROM_RSCAN0GAFLID5 */ +#define RSCAN_FROM_RSCAN0GAFLID6 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID6) /* RSCAN_FROM_RSCAN0GAFLID6 */ +#define RSCAN_FROM_RSCAN0GAFLID7 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID7) /* RSCAN_FROM_RSCAN0GAFLID7 */ +#define RSCAN_FROM_RSCAN0GAFLID8 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID8) /* RSCAN_FROM_RSCAN0GAFLID8 */ +#define RSCAN_FROM_RSCAN0GAFLID9 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID9) /* RSCAN_FROM_RSCAN0GAFLID9 */ +#define RSCAN_FROM_RSCAN0GAFLID10 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID10) /* RSCAN_FROM_RSCAN0GAFLID10 */ +#define RSCAN_FROM_RSCAN0GAFLID11 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID11) /* RSCAN_FROM_RSCAN0GAFLID11 */ +#define RSCAN_FROM_RSCAN0GAFLID12 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID12) /* RSCAN_FROM_RSCAN0GAFLID12 */ +#define RSCAN_FROM_RSCAN0GAFLID13 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID13) /* RSCAN_FROM_RSCAN0GAFLID13 */ +#define RSCAN_FROM_RSCAN0GAFLID14 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID14) /* RSCAN_FROM_RSCAN0GAFLID14 */ +#define RSCAN_FROM_RSCAN0GAFLID15 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID15) /* RSCAN_FROM_RSCAN0GAFLID15 */ + + +/* Channnel array defines of RSCAN_FROM_RSCAN0CnCFG */ +/*(Sample) value = RSCAN_FROM_RSCAN0CnCFG[ channel ]->CnCFG.UINT32; */ +#define RSCAN_FROM_RSCAN0CnCFG_COUNT 5 +#define RSCAN_FROM_RSCAN0CnCFG_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSCAN_FROM_RSCAN0C0CFG, &RSCAN_FROM_RSCAN0C1CFG, &RSCAN_FROM_RSCAN0C2CFG, &RSCAN_FROM_RSCAN0C3CFG, &RSCAN_FROM_RSCAN0C4CFG \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define RSCAN_FROM_RSCAN0C0CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C0CFG) /* RSCAN_FROM_RSCAN0C0CFG */ +#define RSCAN_FROM_RSCAN0C1CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C1CFG) /* RSCAN_FROM_RSCAN0C1CFG */ +#define RSCAN_FROM_RSCAN0C2CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C2CFG) /* RSCAN_FROM_RSCAN0C2CFG */ +#define RSCAN_FROM_RSCAN0C3CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C3CFG) /* RSCAN_FROM_RSCAN0C3CFG */ +#define RSCAN_FROM_RSCAN0C4CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C4CFG) /* RSCAN_FROM_RSCAN0C4CFG */ + +/* End of channnel array defines of RSCAN0 */ + + +#define RSCAN0C0CFG RSCAN0.C0CFG.UINT32 +#define RSCAN0C0CFGL RSCAN0.C0CFG.UINT16[L] +#define RSCAN0C0CFGLL RSCAN0.C0CFG.UINT8[LL] +#define RSCAN0C0CFGLH RSCAN0.C0CFG.UINT8[LH] +#define RSCAN0C0CFGH RSCAN0.C0CFG.UINT16[H] +#define RSCAN0C0CFGHL RSCAN0.C0CFG.UINT8[HL] +#define RSCAN0C0CFGHH RSCAN0.C0CFG.UINT8[HH] +#define RSCAN0C0CTR RSCAN0.C0CTR.UINT32 +#define RSCAN0C0CTRL RSCAN0.C0CTR.UINT16[L] +#define RSCAN0C0CTRLL RSCAN0.C0CTR.UINT8[LL] +#define RSCAN0C0CTRLH RSCAN0.C0CTR.UINT8[LH] +#define RSCAN0C0CTRH RSCAN0.C0CTR.UINT16[H] +#define RSCAN0C0CTRHL RSCAN0.C0CTR.UINT8[HL] +#define RSCAN0C0CTRHH RSCAN0.C0CTR.UINT8[HH] +#define RSCAN0C0STS RSCAN0.C0STS.UINT32 +#define RSCAN0C0STSL RSCAN0.C0STS.UINT16[L] +#define RSCAN0C0STSLL RSCAN0.C0STS.UINT8[LL] +#define RSCAN0C0STSLH RSCAN0.C0STS.UINT8[LH] +#define RSCAN0C0STSH RSCAN0.C0STS.UINT16[H] +#define RSCAN0C0STSHL RSCAN0.C0STS.UINT8[HL] +#define RSCAN0C0STSHH RSCAN0.C0STS.UINT8[HH] +#define RSCAN0C0ERFL RSCAN0.C0ERFL.UINT32 +#define RSCAN0C0ERFLL RSCAN0.C0ERFL.UINT16[L] +#define RSCAN0C0ERFLLL RSCAN0.C0ERFL.UINT8[LL] +#define RSCAN0C0ERFLLH RSCAN0.C0ERFL.UINT8[LH] +#define RSCAN0C0ERFLH RSCAN0.C0ERFL.UINT16[H] +#define RSCAN0C0ERFLHL RSCAN0.C0ERFL.UINT8[HL] +#define RSCAN0C0ERFLHH RSCAN0.C0ERFL.UINT8[HH] +#define RSCAN0C1CFG RSCAN0.C1CFG.UINT32 +#define RSCAN0C1CFGL RSCAN0.C1CFG.UINT16[L] +#define RSCAN0C1CFGLL RSCAN0.C1CFG.UINT8[LL] +#define RSCAN0C1CFGLH RSCAN0.C1CFG.UINT8[LH] +#define RSCAN0C1CFGH RSCAN0.C1CFG.UINT16[H] +#define RSCAN0C1CFGHL RSCAN0.C1CFG.UINT8[HL] +#define RSCAN0C1CFGHH RSCAN0.C1CFG.UINT8[HH] +#define RSCAN0C1CTR RSCAN0.C1CTR.UINT32 +#define RSCAN0C1CTRL RSCAN0.C1CTR.UINT16[L] +#define RSCAN0C1CTRLL RSCAN0.C1CTR.UINT8[LL] +#define RSCAN0C1CTRLH RSCAN0.C1CTR.UINT8[LH] +#define RSCAN0C1CTRH RSCAN0.C1CTR.UINT16[H] +#define RSCAN0C1CTRHL RSCAN0.C1CTR.UINT8[HL] +#define RSCAN0C1CTRHH RSCAN0.C1CTR.UINT8[HH] +#define RSCAN0C1STS RSCAN0.C1STS.UINT32 +#define RSCAN0C1STSL RSCAN0.C1STS.UINT16[L] +#define RSCAN0C1STSLL RSCAN0.C1STS.UINT8[LL] +#define RSCAN0C1STSLH RSCAN0.C1STS.UINT8[LH] +#define RSCAN0C1STSH RSCAN0.C1STS.UINT16[H] +#define RSCAN0C1STSHL RSCAN0.C1STS.UINT8[HL] +#define RSCAN0C1STSHH RSCAN0.C1STS.UINT8[HH] +#define RSCAN0C1ERFL RSCAN0.C1ERFL.UINT32 +#define RSCAN0C1ERFLL RSCAN0.C1ERFL.UINT16[L] +#define RSCAN0C1ERFLLL RSCAN0.C1ERFL.UINT8[LL] +#define RSCAN0C1ERFLLH RSCAN0.C1ERFL.UINT8[LH] +#define RSCAN0C1ERFLH RSCAN0.C1ERFL.UINT16[H] +#define RSCAN0C1ERFLHL RSCAN0.C1ERFL.UINT8[HL] +#define RSCAN0C1ERFLHH RSCAN0.C1ERFL.UINT8[HH] +#define RSCAN0C2CFG RSCAN0.C2CFG.UINT32 +#define RSCAN0C2CFGL RSCAN0.C2CFG.UINT16[L] +#define RSCAN0C2CFGLL RSCAN0.C2CFG.UINT8[LL] +#define RSCAN0C2CFGLH RSCAN0.C2CFG.UINT8[LH] +#define RSCAN0C2CFGH RSCAN0.C2CFG.UINT16[H] +#define RSCAN0C2CFGHL RSCAN0.C2CFG.UINT8[HL] +#define RSCAN0C2CFGHH RSCAN0.C2CFG.UINT8[HH] +#define RSCAN0C2CTR RSCAN0.C2CTR.UINT32 +#define RSCAN0C2CTRL RSCAN0.C2CTR.UINT16[L] +#define RSCAN0C2CTRLL RSCAN0.C2CTR.UINT8[LL] +#define RSCAN0C2CTRLH RSCAN0.C2CTR.UINT8[LH] +#define RSCAN0C2CTRH RSCAN0.C2CTR.UINT16[H] +#define RSCAN0C2CTRHL RSCAN0.C2CTR.UINT8[HL] +#define RSCAN0C2CTRHH RSCAN0.C2CTR.UINT8[HH] +#define RSCAN0C2STS RSCAN0.C2STS.UINT32 +#define RSCAN0C2STSL RSCAN0.C2STS.UINT16[L] +#define RSCAN0C2STSLL RSCAN0.C2STS.UINT8[LL] +#define RSCAN0C2STSLH RSCAN0.C2STS.UINT8[LH] +#define RSCAN0C2STSH RSCAN0.C2STS.UINT16[H] +#define RSCAN0C2STSHL RSCAN0.C2STS.UINT8[HL] +#define RSCAN0C2STSHH RSCAN0.C2STS.UINT8[HH] +#define RSCAN0C2ERFL RSCAN0.C2ERFL.UINT32 +#define RSCAN0C2ERFLL RSCAN0.C2ERFL.UINT16[L] +#define RSCAN0C2ERFLLL RSCAN0.C2ERFL.UINT8[LL] +#define RSCAN0C2ERFLLH RSCAN0.C2ERFL.UINT8[LH] +#define RSCAN0C2ERFLH RSCAN0.C2ERFL.UINT16[H] +#define RSCAN0C2ERFLHL RSCAN0.C2ERFL.UINT8[HL] +#define RSCAN0C2ERFLHH RSCAN0.C2ERFL.UINT8[HH] +#define RSCAN0C3CFG RSCAN0.C3CFG.UINT32 +#define RSCAN0C3CFGL RSCAN0.C3CFG.UINT16[L] +#define RSCAN0C3CFGLL RSCAN0.C3CFG.UINT8[LL] +#define RSCAN0C3CFGLH RSCAN0.C3CFG.UINT8[LH] +#define RSCAN0C3CFGH RSCAN0.C3CFG.UINT16[H] +#define RSCAN0C3CFGHL RSCAN0.C3CFG.UINT8[HL] +#define RSCAN0C3CFGHH RSCAN0.C3CFG.UINT8[HH] +#define RSCAN0C3CTR RSCAN0.C3CTR.UINT32 +#define RSCAN0C3CTRL RSCAN0.C3CTR.UINT16[L] +#define RSCAN0C3CTRLL RSCAN0.C3CTR.UINT8[LL] +#define RSCAN0C3CTRLH RSCAN0.C3CTR.UINT8[LH] +#define RSCAN0C3CTRH RSCAN0.C3CTR.UINT16[H] +#define RSCAN0C3CTRHL RSCAN0.C3CTR.UINT8[HL] +#define RSCAN0C3CTRHH RSCAN0.C3CTR.UINT8[HH] +#define RSCAN0C3STS RSCAN0.C3STS.UINT32 +#define RSCAN0C3STSL RSCAN0.C3STS.UINT16[L] +#define RSCAN0C3STSLL RSCAN0.C3STS.UINT8[LL] +#define RSCAN0C3STSLH RSCAN0.C3STS.UINT8[LH] +#define RSCAN0C3STSH RSCAN0.C3STS.UINT16[H] +#define RSCAN0C3STSHL RSCAN0.C3STS.UINT8[HL] +#define RSCAN0C3STSHH RSCAN0.C3STS.UINT8[HH] +#define RSCAN0C3ERFL RSCAN0.C3ERFL.UINT32 +#define RSCAN0C3ERFLL RSCAN0.C3ERFL.UINT16[L] +#define RSCAN0C3ERFLLL RSCAN0.C3ERFL.UINT8[LL] +#define RSCAN0C3ERFLLH RSCAN0.C3ERFL.UINT8[LH] +#define RSCAN0C3ERFLH RSCAN0.C3ERFL.UINT16[H] +#define RSCAN0C3ERFLHL RSCAN0.C3ERFL.UINT8[HL] +#define RSCAN0C3ERFLHH RSCAN0.C3ERFL.UINT8[HH] +#define RSCAN0C4CFG RSCAN0.C4CFG.UINT32 +#define RSCAN0C4CFGL RSCAN0.C4CFG.UINT16[L] +#define RSCAN0C4CFGLL RSCAN0.C4CFG.UINT8[LL] +#define RSCAN0C4CFGLH RSCAN0.C4CFG.UINT8[LH] +#define RSCAN0C4CFGH RSCAN0.C4CFG.UINT16[H] +#define RSCAN0C4CFGHL RSCAN0.C4CFG.UINT8[HL] +#define RSCAN0C4CFGHH RSCAN0.C4CFG.UINT8[HH] +#define RSCAN0C4CTR RSCAN0.C4CTR.UINT32 +#define RSCAN0C4CTRL RSCAN0.C4CTR.UINT16[L] +#define RSCAN0C4CTRLL RSCAN0.C4CTR.UINT8[LL] +#define RSCAN0C4CTRLH RSCAN0.C4CTR.UINT8[LH] +#define RSCAN0C4CTRH RSCAN0.C4CTR.UINT16[H] +#define RSCAN0C4CTRHL RSCAN0.C4CTR.UINT8[HL] +#define RSCAN0C4CTRHH RSCAN0.C4CTR.UINT8[HH] +#define RSCAN0C4STS RSCAN0.C4STS.UINT32 +#define RSCAN0C4STSL RSCAN0.C4STS.UINT16[L] +#define RSCAN0C4STSLL RSCAN0.C4STS.UINT8[LL] +#define RSCAN0C4STSLH RSCAN0.C4STS.UINT8[LH] +#define RSCAN0C4STSH RSCAN0.C4STS.UINT16[H] +#define RSCAN0C4STSHL RSCAN0.C4STS.UINT8[HL] +#define RSCAN0C4STSHH RSCAN0.C4STS.UINT8[HH] +#define RSCAN0C4ERFL RSCAN0.C4ERFL.UINT32 +#define RSCAN0C4ERFLL RSCAN0.C4ERFL.UINT16[L] +#define RSCAN0C4ERFLLL RSCAN0.C4ERFL.UINT8[LL] +#define RSCAN0C4ERFLLH RSCAN0.C4ERFL.UINT8[LH] +#define RSCAN0C4ERFLH RSCAN0.C4ERFL.UINT16[H] +#define RSCAN0C4ERFLHL RSCAN0.C4ERFL.UINT8[HL] +#define RSCAN0C4ERFLHH RSCAN0.C4ERFL.UINT8[HH] +#define RSCAN0GCFG RSCAN0.GCFG.UINT32 +#define RSCAN0GCFGL RSCAN0.GCFG.UINT16[L] +#define RSCAN0GCFGLL RSCAN0.GCFG.UINT8[LL] +#define RSCAN0GCFGLH RSCAN0.GCFG.UINT8[LH] +#define RSCAN0GCFGH RSCAN0.GCFG.UINT16[H] +#define RSCAN0GCFGHL RSCAN0.GCFG.UINT8[HL] +#define RSCAN0GCFGHH RSCAN0.GCFG.UINT8[HH] +#define RSCAN0GCTR RSCAN0.GCTR.UINT32 +#define RSCAN0GCTRL RSCAN0.GCTR.UINT16[L] +#define RSCAN0GCTRLL RSCAN0.GCTR.UINT8[LL] +#define RSCAN0GCTRLH RSCAN0.GCTR.UINT8[LH] +#define RSCAN0GCTRH RSCAN0.GCTR.UINT16[H] +#define RSCAN0GCTRHL RSCAN0.GCTR.UINT8[HL] +#define RSCAN0GCTRHH RSCAN0.GCTR.UINT8[HH] +#define RSCAN0GSTS RSCAN0.GSTS.UINT32 +#define RSCAN0GSTSL RSCAN0.GSTS.UINT16[L] +#define RSCAN0GSTSLL RSCAN0.GSTS.UINT8[LL] +#define RSCAN0GSTSLH RSCAN0.GSTS.UINT8[LH] +#define RSCAN0GSTSH RSCAN0.GSTS.UINT16[H] +#define RSCAN0GSTSHL RSCAN0.GSTS.UINT8[HL] +#define RSCAN0GSTSHH RSCAN0.GSTS.UINT8[HH] +#define RSCAN0GERFL RSCAN0.GERFL.UINT32 +#define RSCAN0GERFLL RSCAN0.GERFL.UINT16[L] +#define RSCAN0GERFLLL RSCAN0.GERFL.UINT8[LL] +#define RSCAN0GERFLLH RSCAN0.GERFL.UINT8[LH] +#define RSCAN0GERFLH RSCAN0.GERFL.UINT16[H] +#define RSCAN0GERFLHL RSCAN0.GERFL.UINT8[HL] +#define RSCAN0GERFLHH RSCAN0.GERFL.UINT8[HH] +#define RSCAN0GTSC RSCAN0.GTSC.UINT32 +#define RSCAN0GTSCL RSCAN0.GTSC.UINT16[L] +#define RSCAN0GTSCH RSCAN0.GTSC.UINT16[H] +#define RSCAN0GAFLECTR RSCAN0.GAFLECTR.UINT32 +#define RSCAN0GAFLECTRL RSCAN0.GAFLECTR.UINT16[L] +#define RSCAN0GAFLECTRLL RSCAN0.GAFLECTR.UINT8[LL] +#define RSCAN0GAFLECTRLH RSCAN0.GAFLECTR.UINT8[LH] +#define RSCAN0GAFLECTRH RSCAN0.GAFLECTR.UINT16[H] +#define RSCAN0GAFLECTRHL RSCAN0.GAFLECTR.UINT8[HL] +#define RSCAN0GAFLECTRHH RSCAN0.GAFLECTR.UINT8[HH] +#define RSCAN0GAFLCFG0 RSCAN0.GAFLCFG0.UINT32 +#define RSCAN0GAFLCFG0L RSCAN0.GAFLCFG0.UINT16[L] +#define RSCAN0GAFLCFG0LL RSCAN0.GAFLCFG0.UINT8[LL] +#define RSCAN0GAFLCFG0LH RSCAN0.GAFLCFG0.UINT8[LH] +#define RSCAN0GAFLCFG0H RSCAN0.GAFLCFG0.UINT16[H] +#define RSCAN0GAFLCFG0HL RSCAN0.GAFLCFG0.UINT8[HL] +#define RSCAN0GAFLCFG0HH RSCAN0.GAFLCFG0.UINT8[HH] +#define RSCAN0GAFLCFG1 RSCAN0.GAFLCFG1.UINT32 +#define RSCAN0GAFLCFG1L RSCAN0.GAFLCFG1.UINT16[L] +#define RSCAN0GAFLCFG1LL RSCAN0.GAFLCFG1.UINT8[LL] +#define RSCAN0GAFLCFG1LH RSCAN0.GAFLCFG1.UINT8[LH] +#define RSCAN0GAFLCFG1H RSCAN0.GAFLCFG1.UINT16[H] +#define RSCAN0GAFLCFG1HL RSCAN0.GAFLCFG1.UINT8[HL] +#define RSCAN0GAFLCFG1HH RSCAN0.GAFLCFG1.UINT8[HH] +#define RSCAN0RMNB RSCAN0.RMNB.UINT32 +#define RSCAN0RMNBL RSCAN0.RMNB.UINT16[L] +#define RSCAN0RMNBLL RSCAN0.RMNB.UINT8[LL] +#define RSCAN0RMNBLH RSCAN0.RMNB.UINT8[LH] +#define RSCAN0RMNBH RSCAN0.RMNB.UINT16[H] +#define RSCAN0RMNBHL RSCAN0.RMNB.UINT8[HL] +#define RSCAN0RMNBHH RSCAN0.RMNB.UINT8[HH] +#define RSCAN0RMND0 RSCAN0.RMND0.UINT32 +#define RSCAN0RMND0L RSCAN0.RMND0.UINT16[L] +#define RSCAN0RMND0LL RSCAN0.RMND0.UINT8[LL] +#define RSCAN0RMND0LH RSCAN0.RMND0.UINT8[LH] +#define RSCAN0RMND0H RSCAN0.RMND0.UINT16[H] +#define RSCAN0RMND0HL RSCAN0.RMND0.UINT8[HL] +#define RSCAN0RMND0HH RSCAN0.RMND0.UINT8[HH] +#define RSCAN0RMND1 RSCAN0.RMND1.UINT32 +#define RSCAN0RMND1L RSCAN0.RMND1.UINT16[L] +#define RSCAN0RMND1LL RSCAN0.RMND1.UINT8[LL] +#define RSCAN0RMND1LH RSCAN0.RMND1.UINT8[LH] +#define RSCAN0RMND1H RSCAN0.RMND1.UINT16[H] +#define RSCAN0RMND1HL RSCAN0.RMND1.UINT8[HL] +#define RSCAN0RMND1HH RSCAN0.RMND1.UINT8[HH] +#define RSCAN0RMND2 RSCAN0.RMND2.UINT32 +#define RSCAN0RMND2L RSCAN0.RMND2.UINT16[L] +#define RSCAN0RMND2LL RSCAN0.RMND2.UINT8[LL] +#define RSCAN0RMND2LH RSCAN0.RMND2.UINT8[LH] +#define RSCAN0RMND2H RSCAN0.RMND2.UINT16[H] +#define RSCAN0RMND2HL RSCAN0.RMND2.UINT8[HL] +#define RSCAN0RMND2HH RSCAN0.RMND2.UINT8[HH] +#define RSCAN0RFCC0 RSCAN0.RFCC0.UINT32 +#define RSCAN0RFCC0L RSCAN0.RFCC0.UINT16[L] +#define RSCAN0RFCC0LL RSCAN0.RFCC0.UINT8[LL] +#define RSCAN0RFCC0LH RSCAN0.RFCC0.UINT8[LH] +#define RSCAN0RFCC0H RSCAN0.RFCC0.UINT16[H] +#define RSCAN0RFCC0HL RSCAN0.RFCC0.UINT8[HL] +#define RSCAN0RFCC0HH RSCAN0.RFCC0.UINT8[HH] +#define RSCAN0RFCC1 RSCAN0.RFCC1.UINT32 +#define RSCAN0RFCC1L RSCAN0.RFCC1.UINT16[L] +#define RSCAN0RFCC1LL RSCAN0.RFCC1.UINT8[LL] +#define RSCAN0RFCC1LH RSCAN0.RFCC1.UINT8[LH] +#define RSCAN0RFCC1H RSCAN0.RFCC1.UINT16[H] +#define RSCAN0RFCC1HL RSCAN0.RFCC1.UINT8[HL] +#define RSCAN0RFCC1HH RSCAN0.RFCC1.UINT8[HH] +#define RSCAN0RFCC2 RSCAN0.RFCC2.UINT32 +#define RSCAN0RFCC2L RSCAN0.RFCC2.UINT16[L] +#define RSCAN0RFCC2LL RSCAN0.RFCC2.UINT8[LL] +#define RSCAN0RFCC2LH RSCAN0.RFCC2.UINT8[LH] +#define RSCAN0RFCC2H RSCAN0.RFCC2.UINT16[H] +#define RSCAN0RFCC2HL RSCAN0.RFCC2.UINT8[HL] +#define RSCAN0RFCC2HH RSCAN0.RFCC2.UINT8[HH] +#define RSCAN0RFCC3 RSCAN0.RFCC3.UINT32 +#define RSCAN0RFCC3L RSCAN0.RFCC3.UINT16[L] +#define RSCAN0RFCC3LL RSCAN0.RFCC3.UINT8[LL] +#define RSCAN0RFCC3LH RSCAN0.RFCC3.UINT8[LH] +#define RSCAN0RFCC3H RSCAN0.RFCC3.UINT16[H] +#define RSCAN0RFCC3HL RSCAN0.RFCC3.UINT8[HL] +#define RSCAN0RFCC3HH RSCAN0.RFCC3.UINT8[HH] +#define RSCAN0RFCC4 RSCAN0.RFCC4.UINT32 +#define RSCAN0RFCC4L RSCAN0.RFCC4.UINT16[L] +#define RSCAN0RFCC4LL RSCAN0.RFCC4.UINT8[LL] +#define RSCAN0RFCC4LH RSCAN0.RFCC4.UINT8[LH] +#define RSCAN0RFCC4H RSCAN0.RFCC4.UINT16[H] +#define RSCAN0RFCC4HL RSCAN0.RFCC4.UINT8[HL] +#define RSCAN0RFCC4HH RSCAN0.RFCC4.UINT8[HH] +#define RSCAN0RFCC5 RSCAN0.RFCC5.UINT32 +#define RSCAN0RFCC5L RSCAN0.RFCC5.UINT16[L] +#define RSCAN0RFCC5LL RSCAN0.RFCC5.UINT8[LL] +#define RSCAN0RFCC5LH RSCAN0.RFCC5.UINT8[LH] +#define RSCAN0RFCC5H RSCAN0.RFCC5.UINT16[H] +#define RSCAN0RFCC5HL RSCAN0.RFCC5.UINT8[HL] +#define RSCAN0RFCC5HH RSCAN0.RFCC5.UINT8[HH] +#define RSCAN0RFCC6 RSCAN0.RFCC6.UINT32 +#define RSCAN0RFCC6L RSCAN0.RFCC6.UINT16[L] +#define RSCAN0RFCC6LL RSCAN0.RFCC6.UINT8[LL] +#define RSCAN0RFCC6LH RSCAN0.RFCC6.UINT8[LH] +#define RSCAN0RFCC6H RSCAN0.RFCC6.UINT16[H] +#define RSCAN0RFCC6HL RSCAN0.RFCC6.UINT8[HL] +#define RSCAN0RFCC6HH RSCAN0.RFCC6.UINT8[HH] +#define RSCAN0RFCC7 RSCAN0.RFCC7.UINT32 +#define RSCAN0RFCC7L RSCAN0.RFCC7.UINT16[L] +#define RSCAN0RFCC7LL RSCAN0.RFCC7.UINT8[LL] +#define RSCAN0RFCC7LH RSCAN0.RFCC7.UINT8[LH] +#define RSCAN0RFCC7H RSCAN0.RFCC7.UINT16[H] +#define RSCAN0RFCC7HL RSCAN0.RFCC7.UINT8[HL] +#define RSCAN0RFCC7HH RSCAN0.RFCC7.UINT8[HH] +#define RSCAN0RFSTS0 RSCAN0.RFSTS0.UINT32 +#define RSCAN0RFSTS0L RSCAN0.RFSTS0.UINT16[L] +#define RSCAN0RFSTS0LL RSCAN0.RFSTS0.UINT8[LL] +#define RSCAN0RFSTS0LH RSCAN0.RFSTS0.UINT8[LH] +#define RSCAN0RFSTS0H RSCAN0.RFSTS0.UINT16[H] +#define RSCAN0RFSTS0HL RSCAN0.RFSTS0.UINT8[HL] +#define RSCAN0RFSTS0HH RSCAN0.RFSTS0.UINT8[HH] +#define RSCAN0RFSTS1 RSCAN0.RFSTS1.UINT32 +#define RSCAN0RFSTS1L RSCAN0.RFSTS1.UINT16[L] +#define RSCAN0RFSTS1LL RSCAN0.RFSTS1.UINT8[LL] +#define RSCAN0RFSTS1LH RSCAN0.RFSTS1.UINT8[LH] +#define RSCAN0RFSTS1H RSCAN0.RFSTS1.UINT16[H] +#define RSCAN0RFSTS1HL RSCAN0.RFSTS1.UINT8[HL] +#define RSCAN0RFSTS1HH RSCAN0.RFSTS1.UINT8[HH] +#define RSCAN0RFSTS2 RSCAN0.RFSTS2.UINT32 +#define RSCAN0RFSTS2L RSCAN0.RFSTS2.UINT16[L] +#define RSCAN0RFSTS2LL RSCAN0.RFSTS2.UINT8[LL] +#define RSCAN0RFSTS2LH RSCAN0.RFSTS2.UINT8[LH] +#define RSCAN0RFSTS2H RSCAN0.RFSTS2.UINT16[H] +#define RSCAN0RFSTS2HL RSCAN0.RFSTS2.UINT8[HL] +#define RSCAN0RFSTS2HH RSCAN0.RFSTS2.UINT8[HH] +#define RSCAN0RFSTS3 RSCAN0.RFSTS3.UINT32 +#define RSCAN0RFSTS3L RSCAN0.RFSTS3.UINT16[L] +#define RSCAN0RFSTS3LL RSCAN0.RFSTS3.UINT8[LL] +#define RSCAN0RFSTS3LH RSCAN0.RFSTS3.UINT8[LH] +#define RSCAN0RFSTS3H RSCAN0.RFSTS3.UINT16[H] +#define RSCAN0RFSTS3HL RSCAN0.RFSTS3.UINT8[HL] +#define RSCAN0RFSTS3HH RSCAN0.RFSTS3.UINT8[HH] +#define RSCAN0RFSTS4 RSCAN0.RFSTS4.UINT32 +#define RSCAN0RFSTS4L RSCAN0.RFSTS4.UINT16[L] +#define RSCAN0RFSTS4LL RSCAN0.RFSTS4.UINT8[LL] +#define RSCAN0RFSTS4LH RSCAN0.RFSTS4.UINT8[LH] +#define RSCAN0RFSTS4H RSCAN0.RFSTS4.UINT16[H] +#define RSCAN0RFSTS4HL RSCAN0.RFSTS4.UINT8[HL] +#define RSCAN0RFSTS4HH RSCAN0.RFSTS4.UINT8[HH] +#define RSCAN0RFSTS5 RSCAN0.RFSTS5.UINT32 +#define RSCAN0RFSTS5L RSCAN0.RFSTS5.UINT16[L] +#define RSCAN0RFSTS5LL RSCAN0.RFSTS5.UINT8[LL] +#define RSCAN0RFSTS5LH RSCAN0.RFSTS5.UINT8[LH] +#define RSCAN0RFSTS5H RSCAN0.RFSTS5.UINT16[H] +#define RSCAN0RFSTS5HL RSCAN0.RFSTS5.UINT8[HL] +#define RSCAN0RFSTS5HH RSCAN0.RFSTS5.UINT8[HH] +#define RSCAN0RFSTS6 RSCAN0.RFSTS6.UINT32 +#define RSCAN0RFSTS6L RSCAN0.RFSTS6.UINT16[L] +#define RSCAN0RFSTS6LL RSCAN0.RFSTS6.UINT8[LL] +#define RSCAN0RFSTS6LH RSCAN0.RFSTS6.UINT8[LH] +#define RSCAN0RFSTS6H RSCAN0.RFSTS6.UINT16[H] +#define RSCAN0RFSTS6HL RSCAN0.RFSTS6.UINT8[HL] +#define RSCAN0RFSTS6HH RSCAN0.RFSTS6.UINT8[HH] +#define RSCAN0RFSTS7 RSCAN0.RFSTS7.UINT32 +#define RSCAN0RFSTS7L RSCAN0.RFSTS7.UINT16[L] +#define RSCAN0RFSTS7LL RSCAN0.RFSTS7.UINT8[LL] +#define RSCAN0RFSTS7LH RSCAN0.RFSTS7.UINT8[LH] +#define RSCAN0RFSTS7H RSCAN0.RFSTS7.UINT16[H] +#define RSCAN0RFSTS7HL RSCAN0.RFSTS7.UINT8[HL] +#define RSCAN0RFSTS7HH RSCAN0.RFSTS7.UINT8[HH] +#define RSCAN0RFPCTR0 RSCAN0.RFPCTR0.UINT32 +#define RSCAN0RFPCTR0L RSCAN0.RFPCTR0.UINT16[L] +#define RSCAN0RFPCTR0LL RSCAN0.RFPCTR0.UINT8[LL] +#define RSCAN0RFPCTR0LH RSCAN0.RFPCTR0.UINT8[LH] +#define RSCAN0RFPCTR0H RSCAN0.RFPCTR0.UINT16[H] +#define RSCAN0RFPCTR0HL RSCAN0.RFPCTR0.UINT8[HL] +#define RSCAN0RFPCTR0HH RSCAN0.RFPCTR0.UINT8[HH] +#define RSCAN0RFPCTR1 RSCAN0.RFPCTR1.UINT32 +#define RSCAN0RFPCTR1L RSCAN0.RFPCTR1.UINT16[L] +#define RSCAN0RFPCTR1LL RSCAN0.RFPCTR1.UINT8[LL] +#define RSCAN0RFPCTR1LH RSCAN0.RFPCTR1.UINT8[LH] +#define RSCAN0RFPCTR1H RSCAN0.RFPCTR1.UINT16[H] +#define RSCAN0RFPCTR1HL RSCAN0.RFPCTR1.UINT8[HL] +#define RSCAN0RFPCTR1HH RSCAN0.RFPCTR1.UINT8[HH] +#define RSCAN0RFPCTR2 RSCAN0.RFPCTR2.UINT32 +#define RSCAN0RFPCTR2L RSCAN0.RFPCTR2.UINT16[L] +#define RSCAN0RFPCTR2LL RSCAN0.RFPCTR2.UINT8[LL] +#define RSCAN0RFPCTR2LH RSCAN0.RFPCTR2.UINT8[LH] +#define RSCAN0RFPCTR2H RSCAN0.RFPCTR2.UINT16[H] +#define RSCAN0RFPCTR2HL RSCAN0.RFPCTR2.UINT8[HL] +#define RSCAN0RFPCTR2HH RSCAN0.RFPCTR2.UINT8[HH] +#define RSCAN0RFPCTR3 RSCAN0.RFPCTR3.UINT32 +#define RSCAN0RFPCTR3L RSCAN0.RFPCTR3.UINT16[L] +#define RSCAN0RFPCTR3LL RSCAN0.RFPCTR3.UINT8[LL] +#define RSCAN0RFPCTR3LH RSCAN0.RFPCTR3.UINT8[LH] +#define RSCAN0RFPCTR3H RSCAN0.RFPCTR3.UINT16[H] +#define RSCAN0RFPCTR3HL RSCAN0.RFPCTR3.UINT8[HL] +#define RSCAN0RFPCTR3HH RSCAN0.RFPCTR3.UINT8[HH] +#define RSCAN0RFPCTR4 RSCAN0.RFPCTR4.UINT32 +#define RSCAN0RFPCTR4L RSCAN0.RFPCTR4.UINT16[L] +#define RSCAN0RFPCTR4LL RSCAN0.RFPCTR4.UINT8[LL] +#define RSCAN0RFPCTR4LH RSCAN0.RFPCTR4.UINT8[LH] +#define RSCAN0RFPCTR4H RSCAN0.RFPCTR4.UINT16[H] +#define RSCAN0RFPCTR4HL RSCAN0.RFPCTR4.UINT8[HL] +#define RSCAN0RFPCTR4HH RSCAN0.RFPCTR4.UINT8[HH] +#define RSCAN0RFPCTR5 RSCAN0.RFPCTR5.UINT32 +#define RSCAN0RFPCTR5L RSCAN0.RFPCTR5.UINT16[L] +#define RSCAN0RFPCTR5LL RSCAN0.RFPCTR5.UINT8[LL] +#define RSCAN0RFPCTR5LH RSCAN0.RFPCTR5.UINT8[LH] +#define RSCAN0RFPCTR5H RSCAN0.RFPCTR5.UINT16[H] +#define RSCAN0RFPCTR5HL RSCAN0.RFPCTR5.UINT8[HL] +#define RSCAN0RFPCTR5HH RSCAN0.RFPCTR5.UINT8[HH] +#define RSCAN0RFPCTR6 RSCAN0.RFPCTR6.UINT32 +#define RSCAN0RFPCTR6L RSCAN0.RFPCTR6.UINT16[L] +#define RSCAN0RFPCTR6LL RSCAN0.RFPCTR6.UINT8[LL] +#define RSCAN0RFPCTR6LH RSCAN0.RFPCTR6.UINT8[LH] +#define RSCAN0RFPCTR6H RSCAN0.RFPCTR6.UINT16[H] +#define RSCAN0RFPCTR6HL RSCAN0.RFPCTR6.UINT8[HL] +#define RSCAN0RFPCTR6HH RSCAN0.RFPCTR6.UINT8[HH] +#define RSCAN0RFPCTR7 RSCAN0.RFPCTR7.UINT32 +#define RSCAN0RFPCTR7L RSCAN0.RFPCTR7.UINT16[L] +#define RSCAN0RFPCTR7LL RSCAN0.RFPCTR7.UINT8[LL] +#define RSCAN0RFPCTR7LH RSCAN0.RFPCTR7.UINT8[LH] +#define RSCAN0RFPCTR7H RSCAN0.RFPCTR7.UINT16[H] +#define RSCAN0RFPCTR7HL RSCAN0.RFPCTR7.UINT8[HL] +#define RSCAN0RFPCTR7HH RSCAN0.RFPCTR7.UINT8[HH] +#define RSCAN0CFCC0 RSCAN0.CFCC0.UINT32 +#define RSCAN0CFCC0L RSCAN0.CFCC0.UINT16[L] +#define RSCAN0CFCC0LL RSCAN0.CFCC0.UINT8[LL] +#define RSCAN0CFCC0LH RSCAN0.CFCC0.UINT8[LH] +#define RSCAN0CFCC0H RSCAN0.CFCC0.UINT16[H] +#define RSCAN0CFCC0HL RSCAN0.CFCC0.UINT8[HL] +#define RSCAN0CFCC0HH RSCAN0.CFCC0.UINT8[HH] +#define RSCAN0CFCC1 RSCAN0.CFCC1.UINT32 +#define RSCAN0CFCC1L RSCAN0.CFCC1.UINT16[L] +#define RSCAN0CFCC1LL RSCAN0.CFCC1.UINT8[LL] +#define RSCAN0CFCC1LH RSCAN0.CFCC1.UINT8[LH] +#define RSCAN0CFCC1H RSCAN0.CFCC1.UINT16[H] +#define RSCAN0CFCC1HL RSCAN0.CFCC1.UINT8[HL] +#define RSCAN0CFCC1HH RSCAN0.CFCC1.UINT8[HH] +#define RSCAN0CFCC2 RSCAN0.CFCC2.UINT32 +#define RSCAN0CFCC2L RSCAN0.CFCC2.UINT16[L] +#define RSCAN0CFCC2LL RSCAN0.CFCC2.UINT8[LL] +#define RSCAN0CFCC2LH RSCAN0.CFCC2.UINT8[LH] +#define RSCAN0CFCC2H RSCAN0.CFCC2.UINT16[H] +#define RSCAN0CFCC2HL RSCAN0.CFCC2.UINT8[HL] +#define RSCAN0CFCC2HH RSCAN0.CFCC2.UINT8[HH] +#define RSCAN0CFCC3 RSCAN0.CFCC3.UINT32 +#define RSCAN0CFCC3L RSCAN0.CFCC3.UINT16[L] +#define RSCAN0CFCC3LL RSCAN0.CFCC3.UINT8[LL] +#define RSCAN0CFCC3LH RSCAN0.CFCC3.UINT8[LH] +#define RSCAN0CFCC3H RSCAN0.CFCC3.UINT16[H] +#define RSCAN0CFCC3HL RSCAN0.CFCC3.UINT8[HL] +#define RSCAN0CFCC3HH RSCAN0.CFCC3.UINT8[HH] +#define RSCAN0CFCC4 RSCAN0.CFCC4.UINT32 +#define RSCAN0CFCC4L RSCAN0.CFCC4.UINT16[L] +#define RSCAN0CFCC4LL RSCAN0.CFCC4.UINT8[LL] +#define RSCAN0CFCC4LH RSCAN0.CFCC4.UINT8[LH] +#define RSCAN0CFCC4H RSCAN0.CFCC4.UINT16[H] +#define RSCAN0CFCC4HL RSCAN0.CFCC4.UINT8[HL] +#define RSCAN0CFCC4HH RSCAN0.CFCC4.UINT8[HH] +#define RSCAN0CFCC5 RSCAN0.CFCC5.UINT32 +#define RSCAN0CFCC5L RSCAN0.CFCC5.UINT16[L] +#define RSCAN0CFCC5LL RSCAN0.CFCC5.UINT8[LL] +#define RSCAN0CFCC5LH RSCAN0.CFCC5.UINT8[LH] +#define RSCAN0CFCC5H RSCAN0.CFCC5.UINT16[H] +#define RSCAN0CFCC5HL RSCAN0.CFCC5.UINT8[HL] +#define RSCAN0CFCC5HH RSCAN0.CFCC5.UINT8[HH] +#define RSCAN0CFCC6 RSCAN0.CFCC6.UINT32 +#define RSCAN0CFCC6L RSCAN0.CFCC6.UINT16[L] +#define RSCAN0CFCC6LL RSCAN0.CFCC6.UINT8[LL] +#define RSCAN0CFCC6LH RSCAN0.CFCC6.UINT8[LH] +#define RSCAN0CFCC6H RSCAN0.CFCC6.UINT16[H] +#define RSCAN0CFCC6HL RSCAN0.CFCC6.UINT8[HL] +#define RSCAN0CFCC6HH RSCAN0.CFCC6.UINT8[HH] +#define RSCAN0CFCC7 RSCAN0.CFCC7.UINT32 +#define RSCAN0CFCC7L RSCAN0.CFCC7.UINT16[L] +#define RSCAN0CFCC7LL RSCAN0.CFCC7.UINT8[LL] +#define RSCAN0CFCC7LH RSCAN0.CFCC7.UINT8[LH] +#define RSCAN0CFCC7H RSCAN0.CFCC7.UINT16[H] +#define RSCAN0CFCC7HL RSCAN0.CFCC7.UINT8[HL] +#define RSCAN0CFCC7HH RSCAN0.CFCC7.UINT8[HH] +#define RSCAN0CFCC8 RSCAN0.CFCC8.UINT32 +#define RSCAN0CFCC8L RSCAN0.CFCC8.UINT16[L] +#define RSCAN0CFCC8LL RSCAN0.CFCC8.UINT8[LL] +#define RSCAN0CFCC8LH RSCAN0.CFCC8.UINT8[LH] +#define RSCAN0CFCC8H RSCAN0.CFCC8.UINT16[H] +#define RSCAN0CFCC8HL RSCAN0.CFCC8.UINT8[HL] +#define RSCAN0CFCC8HH RSCAN0.CFCC8.UINT8[HH] +#define RSCAN0CFCC9 RSCAN0.CFCC9.UINT32 +#define RSCAN0CFCC9L RSCAN0.CFCC9.UINT16[L] +#define RSCAN0CFCC9LL RSCAN0.CFCC9.UINT8[LL] +#define RSCAN0CFCC9LH RSCAN0.CFCC9.UINT8[LH] +#define RSCAN0CFCC9H RSCAN0.CFCC9.UINT16[H] +#define RSCAN0CFCC9HL RSCAN0.CFCC9.UINT8[HL] +#define RSCAN0CFCC9HH RSCAN0.CFCC9.UINT8[HH] +#define RSCAN0CFCC10 RSCAN0.CFCC10.UINT32 +#define RSCAN0CFCC10L RSCAN0.CFCC10.UINT16[L] +#define RSCAN0CFCC10LL RSCAN0.CFCC10.UINT8[LL] +#define RSCAN0CFCC10LH RSCAN0.CFCC10.UINT8[LH] +#define RSCAN0CFCC10H RSCAN0.CFCC10.UINT16[H] +#define RSCAN0CFCC10HL RSCAN0.CFCC10.UINT8[HL] +#define RSCAN0CFCC10HH RSCAN0.CFCC10.UINT8[HH] +#define RSCAN0CFCC11 RSCAN0.CFCC11.UINT32 +#define RSCAN0CFCC11L RSCAN0.CFCC11.UINT16[L] +#define RSCAN0CFCC11LL RSCAN0.CFCC11.UINT8[LL] +#define RSCAN0CFCC11LH RSCAN0.CFCC11.UINT8[LH] +#define RSCAN0CFCC11H RSCAN0.CFCC11.UINT16[H] +#define RSCAN0CFCC11HL RSCAN0.CFCC11.UINT8[HL] +#define RSCAN0CFCC11HH RSCAN0.CFCC11.UINT8[HH] +#define RSCAN0CFCC12 RSCAN0.CFCC12.UINT32 +#define RSCAN0CFCC12L RSCAN0.CFCC12.UINT16[L] +#define RSCAN0CFCC12LL RSCAN0.CFCC12.UINT8[LL] +#define RSCAN0CFCC12LH RSCAN0.CFCC12.UINT8[LH] +#define RSCAN0CFCC12H RSCAN0.CFCC12.UINT16[H] +#define RSCAN0CFCC12HL RSCAN0.CFCC12.UINT8[HL] +#define RSCAN0CFCC12HH RSCAN0.CFCC12.UINT8[HH] +#define RSCAN0CFCC13 RSCAN0.CFCC13.UINT32 +#define RSCAN0CFCC13L RSCAN0.CFCC13.UINT16[L] +#define RSCAN0CFCC13LL RSCAN0.CFCC13.UINT8[LL] +#define RSCAN0CFCC13LH RSCAN0.CFCC13.UINT8[LH] +#define RSCAN0CFCC13H RSCAN0.CFCC13.UINT16[H] +#define RSCAN0CFCC13HL RSCAN0.CFCC13.UINT8[HL] +#define RSCAN0CFCC13HH RSCAN0.CFCC13.UINT8[HH] +#define RSCAN0CFCC14 RSCAN0.CFCC14.UINT32 +#define RSCAN0CFCC14L RSCAN0.CFCC14.UINT16[L] +#define RSCAN0CFCC14LL RSCAN0.CFCC14.UINT8[LL] +#define RSCAN0CFCC14LH RSCAN0.CFCC14.UINT8[LH] +#define RSCAN0CFCC14H RSCAN0.CFCC14.UINT16[H] +#define RSCAN0CFCC14HL RSCAN0.CFCC14.UINT8[HL] +#define RSCAN0CFCC14HH RSCAN0.CFCC14.UINT8[HH] +#define RSCAN0CFSTS0 RSCAN0.CFSTS0.UINT32 +#define RSCAN0CFSTS0L RSCAN0.CFSTS0.UINT16[L] +#define RSCAN0CFSTS0LL RSCAN0.CFSTS0.UINT8[LL] +#define RSCAN0CFSTS0LH RSCAN0.CFSTS0.UINT8[LH] +#define RSCAN0CFSTS0H RSCAN0.CFSTS0.UINT16[H] +#define RSCAN0CFSTS0HL RSCAN0.CFSTS0.UINT8[HL] +#define RSCAN0CFSTS0HH RSCAN0.CFSTS0.UINT8[HH] +#define RSCAN0CFSTS1 RSCAN0.CFSTS1.UINT32 +#define RSCAN0CFSTS1L RSCAN0.CFSTS1.UINT16[L] +#define RSCAN0CFSTS1LL RSCAN0.CFSTS1.UINT8[LL] +#define RSCAN0CFSTS1LH RSCAN0.CFSTS1.UINT8[LH] +#define RSCAN0CFSTS1H RSCAN0.CFSTS1.UINT16[H] +#define RSCAN0CFSTS1HL RSCAN0.CFSTS1.UINT8[HL] +#define RSCAN0CFSTS1HH RSCAN0.CFSTS1.UINT8[HH] +#define RSCAN0CFSTS2 RSCAN0.CFSTS2.UINT32 +#define RSCAN0CFSTS2L RSCAN0.CFSTS2.UINT16[L] +#define RSCAN0CFSTS2LL RSCAN0.CFSTS2.UINT8[LL] +#define RSCAN0CFSTS2LH RSCAN0.CFSTS2.UINT8[LH] +#define RSCAN0CFSTS2H RSCAN0.CFSTS2.UINT16[H] +#define RSCAN0CFSTS2HL RSCAN0.CFSTS2.UINT8[HL] +#define RSCAN0CFSTS2HH RSCAN0.CFSTS2.UINT8[HH] +#define RSCAN0CFSTS3 RSCAN0.CFSTS3.UINT32 +#define RSCAN0CFSTS3L RSCAN0.CFSTS3.UINT16[L] +#define RSCAN0CFSTS3LL RSCAN0.CFSTS3.UINT8[LL] +#define RSCAN0CFSTS3LH RSCAN0.CFSTS3.UINT8[LH] +#define RSCAN0CFSTS3H RSCAN0.CFSTS3.UINT16[H] +#define RSCAN0CFSTS3HL RSCAN0.CFSTS3.UINT8[HL] +#define RSCAN0CFSTS3HH RSCAN0.CFSTS3.UINT8[HH] +#define RSCAN0CFSTS4 RSCAN0.CFSTS4.UINT32 +#define RSCAN0CFSTS4L RSCAN0.CFSTS4.UINT16[L] +#define RSCAN0CFSTS4LL RSCAN0.CFSTS4.UINT8[LL] +#define RSCAN0CFSTS4LH RSCAN0.CFSTS4.UINT8[LH] +#define RSCAN0CFSTS4H RSCAN0.CFSTS4.UINT16[H] +#define RSCAN0CFSTS4HL RSCAN0.CFSTS4.UINT8[HL] +#define RSCAN0CFSTS4HH RSCAN0.CFSTS4.UINT8[HH] +#define RSCAN0CFSTS5 RSCAN0.CFSTS5.UINT32 +#define RSCAN0CFSTS5L RSCAN0.CFSTS5.UINT16[L] +#define RSCAN0CFSTS5LL RSCAN0.CFSTS5.UINT8[LL] +#define RSCAN0CFSTS5LH RSCAN0.CFSTS5.UINT8[LH] +#define RSCAN0CFSTS5H RSCAN0.CFSTS5.UINT16[H] +#define RSCAN0CFSTS5HL RSCAN0.CFSTS5.UINT8[HL] +#define RSCAN0CFSTS5HH RSCAN0.CFSTS5.UINT8[HH] +#define RSCAN0CFSTS6 RSCAN0.CFSTS6.UINT32 +#define RSCAN0CFSTS6L RSCAN0.CFSTS6.UINT16[L] +#define RSCAN0CFSTS6LL RSCAN0.CFSTS6.UINT8[LL] +#define RSCAN0CFSTS6LH RSCAN0.CFSTS6.UINT8[LH] +#define RSCAN0CFSTS6H RSCAN0.CFSTS6.UINT16[H] +#define RSCAN0CFSTS6HL RSCAN0.CFSTS6.UINT8[HL] +#define RSCAN0CFSTS6HH RSCAN0.CFSTS6.UINT8[HH] +#define RSCAN0CFSTS7 RSCAN0.CFSTS7.UINT32 +#define RSCAN0CFSTS7L RSCAN0.CFSTS7.UINT16[L] +#define RSCAN0CFSTS7LL RSCAN0.CFSTS7.UINT8[LL] +#define RSCAN0CFSTS7LH RSCAN0.CFSTS7.UINT8[LH] +#define RSCAN0CFSTS7H RSCAN0.CFSTS7.UINT16[H] +#define RSCAN0CFSTS7HL RSCAN0.CFSTS7.UINT8[HL] +#define RSCAN0CFSTS7HH RSCAN0.CFSTS7.UINT8[HH] +#define RSCAN0CFSTS8 RSCAN0.CFSTS8.UINT32 +#define RSCAN0CFSTS8L RSCAN0.CFSTS8.UINT16[L] +#define RSCAN0CFSTS8LL RSCAN0.CFSTS8.UINT8[LL] +#define RSCAN0CFSTS8LH RSCAN0.CFSTS8.UINT8[LH] +#define RSCAN0CFSTS8H RSCAN0.CFSTS8.UINT16[H] +#define RSCAN0CFSTS8HL RSCAN0.CFSTS8.UINT8[HL] +#define RSCAN0CFSTS8HH RSCAN0.CFSTS8.UINT8[HH] +#define RSCAN0CFSTS9 RSCAN0.CFSTS9.UINT32 +#define RSCAN0CFSTS9L RSCAN0.CFSTS9.UINT16[L] +#define RSCAN0CFSTS9LL RSCAN0.CFSTS9.UINT8[LL] +#define RSCAN0CFSTS9LH RSCAN0.CFSTS9.UINT8[LH] +#define RSCAN0CFSTS9H RSCAN0.CFSTS9.UINT16[H] +#define RSCAN0CFSTS9HL RSCAN0.CFSTS9.UINT8[HL] +#define RSCAN0CFSTS9HH RSCAN0.CFSTS9.UINT8[HH] +#define RSCAN0CFSTS10 RSCAN0.CFSTS10.UINT32 +#define RSCAN0CFSTS10L RSCAN0.CFSTS10.UINT16[L] +#define RSCAN0CFSTS10LL RSCAN0.CFSTS10.UINT8[LL] +#define RSCAN0CFSTS10LH RSCAN0.CFSTS10.UINT8[LH] +#define RSCAN0CFSTS10H RSCAN0.CFSTS10.UINT16[H] +#define RSCAN0CFSTS10HL RSCAN0.CFSTS10.UINT8[HL] +#define RSCAN0CFSTS10HH RSCAN0.CFSTS10.UINT8[HH] +#define RSCAN0CFSTS11 RSCAN0.CFSTS11.UINT32 +#define RSCAN0CFSTS11L RSCAN0.CFSTS11.UINT16[L] +#define RSCAN0CFSTS11LL RSCAN0.CFSTS11.UINT8[LL] +#define RSCAN0CFSTS11LH RSCAN0.CFSTS11.UINT8[LH] +#define RSCAN0CFSTS11H RSCAN0.CFSTS11.UINT16[H] +#define RSCAN0CFSTS11HL RSCAN0.CFSTS11.UINT8[HL] +#define RSCAN0CFSTS11HH RSCAN0.CFSTS11.UINT8[HH] +#define RSCAN0CFSTS12 RSCAN0.CFSTS12.UINT32 +#define RSCAN0CFSTS12L RSCAN0.CFSTS12.UINT16[L] +#define RSCAN0CFSTS12LL RSCAN0.CFSTS12.UINT8[LL] +#define RSCAN0CFSTS12LH RSCAN0.CFSTS12.UINT8[LH] +#define RSCAN0CFSTS12H RSCAN0.CFSTS12.UINT16[H] +#define RSCAN0CFSTS12HL RSCAN0.CFSTS12.UINT8[HL] +#define RSCAN0CFSTS12HH RSCAN0.CFSTS12.UINT8[HH] +#define RSCAN0CFSTS13 RSCAN0.CFSTS13.UINT32 +#define RSCAN0CFSTS13L RSCAN0.CFSTS13.UINT16[L] +#define RSCAN0CFSTS13LL RSCAN0.CFSTS13.UINT8[LL] +#define RSCAN0CFSTS13LH RSCAN0.CFSTS13.UINT8[LH] +#define RSCAN0CFSTS13H RSCAN0.CFSTS13.UINT16[H] +#define RSCAN0CFSTS13HL RSCAN0.CFSTS13.UINT8[HL] +#define RSCAN0CFSTS13HH RSCAN0.CFSTS13.UINT8[HH] +#define RSCAN0CFSTS14 RSCAN0.CFSTS14.UINT32 +#define RSCAN0CFSTS14L RSCAN0.CFSTS14.UINT16[L] +#define RSCAN0CFSTS14LL RSCAN0.CFSTS14.UINT8[LL] +#define RSCAN0CFSTS14LH RSCAN0.CFSTS14.UINT8[LH] +#define RSCAN0CFSTS14H RSCAN0.CFSTS14.UINT16[H] +#define RSCAN0CFSTS14HL RSCAN0.CFSTS14.UINT8[HL] +#define RSCAN0CFSTS14HH RSCAN0.CFSTS14.UINT8[HH] +#define RSCAN0CFPCTR0 RSCAN0.CFPCTR0.UINT32 +#define RSCAN0CFPCTR0L RSCAN0.CFPCTR0.UINT16[L] +#define RSCAN0CFPCTR0LL RSCAN0.CFPCTR0.UINT8[LL] +#define RSCAN0CFPCTR0LH RSCAN0.CFPCTR0.UINT8[LH] +#define RSCAN0CFPCTR0H RSCAN0.CFPCTR0.UINT16[H] +#define RSCAN0CFPCTR0HL RSCAN0.CFPCTR0.UINT8[HL] +#define RSCAN0CFPCTR0HH RSCAN0.CFPCTR0.UINT8[HH] +#define RSCAN0CFPCTR1 RSCAN0.CFPCTR1.UINT32 +#define RSCAN0CFPCTR1L RSCAN0.CFPCTR1.UINT16[L] +#define RSCAN0CFPCTR1LL RSCAN0.CFPCTR1.UINT8[LL] +#define RSCAN0CFPCTR1LH RSCAN0.CFPCTR1.UINT8[LH] +#define RSCAN0CFPCTR1H RSCAN0.CFPCTR1.UINT16[H] +#define RSCAN0CFPCTR1HL RSCAN0.CFPCTR1.UINT8[HL] +#define RSCAN0CFPCTR1HH RSCAN0.CFPCTR1.UINT8[HH] +#define RSCAN0CFPCTR2 RSCAN0.CFPCTR2.UINT32 +#define RSCAN0CFPCTR2L RSCAN0.CFPCTR2.UINT16[L] +#define RSCAN0CFPCTR2LL RSCAN0.CFPCTR2.UINT8[LL] +#define RSCAN0CFPCTR2LH RSCAN0.CFPCTR2.UINT8[LH] +#define RSCAN0CFPCTR2H RSCAN0.CFPCTR2.UINT16[H] +#define RSCAN0CFPCTR2HL RSCAN0.CFPCTR2.UINT8[HL] +#define RSCAN0CFPCTR2HH RSCAN0.CFPCTR2.UINT8[HH] +#define RSCAN0CFPCTR3 RSCAN0.CFPCTR3.UINT32 +#define RSCAN0CFPCTR3L RSCAN0.CFPCTR3.UINT16[L] +#define RSCAN0CFPCTR3LL RSCAN0.CFPCTR3.UINT8[LL] +#define RSCAN0CFPCTR3LH RSCAN0.CFPCTR3.UINT8[LH] +#define RSCAN0CFPCTR3H RSCAN0.CFPCTR3.UINT16[H] +#define RSCAN0CFPCTR3HL RSCAN0.CFPCTR3.UINT8[HL] +#define RSCAN0CFPCTR3HH RSCAN0.CFPCTR3.UINT8[HH] +#define RSCAN0CFPCTR4 RSCAN0.CFPCTR4.UINT32 +#define RSCAN0CFPCTR4L RSCAN0.CFPCTR4.UINT16[L] +#define RSCAN0CFPCTR4LL RSCAN0.CFPCTR4.UINT8[LL] +#define RSCAN0CFPCTR4LH RSCAN0.CFPCTR4.UINT8[LH] +#define RSCAN0CFPCTR4H RSCAN0.CFPCTR4.UINT16[H] +#define RSCAN0CFPCTR4HL RSCAN0.CFPCTR4.UINT8[HL] +#define RSCAN0CFPCTR4HH RSCAN0.CFPCTR4.UINT8[HH] +#define RSCAN0CFPCTR5 RSCAN0.CFPCTR5.UINT32 +#define RSCAN0CFPCTR5L RSCAN0.CFPCTR5.UINT16[L] +#define RSCAN0CFPCTR5LL RSCAN0.CFPCTR5.UINT8[LL] +#define RSCAN0CFPCTR5LH RSCAN0.CFPCTR5.UINT8[LH] +#define RSCAN0CFPCTR5H RSCAN0.CFPCTR5.UINT16[H] +#define RSCAN0CFPCTR5HL RSCAN0.CFPCTR5.UINT8[HL] +#define RSCAN0CFPCTR5HH RSCAN0.CFPCTR5.UINT8[HH] +#define RSCAN0CFPCTR6 RSCAN0.CFPCTR6.UINT32 +#define RSCAN0CFPCTR6L RSCAN0.CFPCTR6.UINT16[L] +#define RSCAN0CFPCTR6LL RSCAN0.CFPCTR6.UINT8[LL] +#define RSCAN0CFPCTR6LH RSCAN0.CFPCTR6.UINT8[LH] +#define RSCAN0CFPCTR6H RSCAN0.CFPCTR6.UINT16[H] +#define RSCAN0CFPCTR6HL RSCAN0.CFPCTR6.UINT8[HL] +#define RSCAN0CFPCTR6HH RSCAN0.CFPCTR6.UINT8[HH] +#define RSCAN0CFPCTR7 RSCAN0.CFPCTR7.UINT32 +#define RSCAN0CFPCTR7L RSCAN0.CFPCTR7.UINT16[L] +#define RSCAN0CFPCTR7LL RSCAN0.CFPCTR7.UINT8[LL] +#define RSCAN0CFPCTR7LH RSCAN0.CFPCTR7.UINT8[LH] +#define RSCAN0CFPCTR7H RSCAN0.CFPCTR7.UINT16[H] +#define RSCAN0CFPCTR7HL RSCAN0.CFPCTR7.UINT8[HL] +#define RSCAN0CFPCTR7HH RSCAN0.CFPCTR7.UINT8[HH] +#define RSCAN0CFPCTR8 RSCAN0.CFPCTR8.UINT32 +#define RSCAN0CFPCTR8L RSCAN0.CFPCTR8.UINT16[L] +#define RSCAN0CFPCTR8LL RSCAN0.CFPCTR8.UINT8[LL] +#define RSCAN0CFPCTR8LH RSCAN0.CFPCTR8.UINT8[LH] +#define RSCAN0CFPCTR8H RSCAN0.CFPCTR8.UINT16[H] +#define RSCAN0CFPCTR8HL RSCAN0.CFPCTR8.UINT8[HL] +#define RSCAN0CFPCTR8HH RSCAN0.CFPCTR8.UINT8[HH] +#define RSCAN0CFPCTR9 RSCAN0.CFPCTR9.UINT32 +#define RSCAN0CFPCTR9L RSCAN0.CFPCTR9.UINT16[L] +#define RSCAN0CFPCTR9LL RSCAN0.CFPCTR9.UINT8[LL] +#define RSCAN0CFPCTR9LH RSCAN0.CFPCTR9.UINT8[LH] +#define RSCAN0CFPCTR9H RSCAN0.CFPCTR9.UINT16[H] +#define RSCAN0CFPCTR9HL RSCAN0.CFPCTR9.UINT8[HL] +#define RSCAN0CFPCTR9HH RSCAN0.CFPCTR9.UINT8[HH] +#define RSCAN0CFPCTR10 RSCAN0.CFPCTR10.UINT32 +#define RSCAN0CFPCTR10L RSCAN0.CFPCTR10.UINT16[L] +#define RSCAN0CFPCTR10LL RSCAN0.CFPCTR10.UINT8[LL] +#define RSCAN0CFPCTR10LH RSCAN0.CFPCTR10.UINT8[LH] +#define RSCAN0CFPCTR10H RSCAN0.CFPCTR10.UINT16[H] +#define RSCAN0CFPCTR10HL RSCAN0.CFPCTR10.UINT8[HL] +#define RSCAN0CFPCTR10HH RSCAN0.CFPCTR10.UINT8[HH] +#define RSCAN0CFPCTR11 RSCAN0.CFPCTR11.UINT32 +#define RSCAN0CFPCTR11L RSCAN0.CFPCTR11.UINT16[L] +#define RSCAN0CFPCTR11LL RSCAN0.CFPCTR11.UINT8[LL] +#define RSCAN0CFPCTR11LH RSCAN0.CFPCTR11.UINT8[LH] +#define RSCAN0CFPCTR11H RSCAN0.CFPCTR11.UINT16[H] +#define RSCAN0CFPCTR11HL RSCAN0.CFPCTR11.UINT8[HL] +#define RSCAN0CFPCTR11HH RSCAN0.CFPCTR11.UINT8[HH] +#define RSCAN0CFPCTR12 RSCAN0.CFPCTR12.UINT32 +#define RSCAN0CFPCTR12L RSCAN0.CFPCTR12.UINT16[L] +#define RSCAN0CFPCTR12LL RSCAN0.CFPCTR12.UINT8[LL] +#define RSCAN0CFPCTR12LH RSCAN0.CFPCTR12.UINT8[LH] +#define RSCAN0CFPCTR12H RSCAN0.CFPCTR12.UINT16[H] +#define RSCAN0CFPCTR12HL RSCAN0.CFPCTR12.UINT8[HL] +#define RSCAN0CFPCTR12HH RSCAN0.CFPCTR12.UINT8[HH] +#define RSCAN0CFPCTR13 RSCAN0.CFPCTR13.UINT32 +#define RSCAN0CFPCTR13L RSCAN0.CFPCTR13.UINT16[L] +#define RSCAN0CFPCTR13LL RSCAN0.CFPCTR13.UINT8[LL] +#define RSCAN0CFPCTR13LH RSCAN0.CFPCTR13.UINT8[LH] +#define RSCAN0CFPCTR13H RSCAN0.CFPCTR13.UINT16[H] +#define RSCAN0CFPCTR13HL RSCAN0.CFPCTR13.UINT8[HL] +#define RSCAN0CFPCTR13HH RSCAN0.CFPCTR13.UINT8[HH] +#define RSCAN0CFPCTR14 RSCAN0.CFPCTR14.UINT32 +#define RSCAN0CFPCTR14L RSCAN0.CFPCTR14.UINT16[L] +#define RSCAN0CFPCTR14LL RSCAN0.CFPCTR14.UINT8[LL] +#define RSCAN0CFPCTR14LH RSCAN0.CFPCTR14.UINT8[LH] +#define RSCAN0CFPCTR14H RSCAN0.CFPCTR14.UINT16[H] +#define RSCAN0CFPCTR14HL RSCAN0.CFPCTR14.UINT8[HL] +#define RSCAN0CFPCTR14HH RSCAN0.CFPCTR14.UINT8[HH] +#define RSCAN0FESTS RSCAN0.FESTS.UINT32 +#define RSCAN0FESTSL RSCAN0.FESTS.UINT16[L] +#define RSCAN0FESTSLL RSCAN0.FESTS.UINT8[LL] +#define RSCAN0FESTSLH RSCAN0.FESTS.UINT8[LH] +#define RSCAN0FESTSH RSCAN0.FESTS.UINT16[H] +#define RSCAN0FESTSHL RSCAN0.FESTS.UINT8[HL] +#define RSCAN0FESTSHH RSCAN0.FESTS.UINT8[HH] +#define RSCAN0FFSTS RSCAN0.FFSTS.UINT32 +#define RSCAN0FFSTSL RSCAN0.FFSTS.UINT16[L] +#define RSCAN0FFSTSLL RSCAN0.FFSTS.UINT8[LL] +#define RSCAN0FFSTSLH RSCAN0.FFSTS.UINT8[LH] +#define RSCAN0FFSTSH RSCAN0.FFSTS.UINT16[H] +#define RSCAN0FFSTSHL RSCAN0.FFSTS.UINT8[HL] +#define RSCAN0FFSTSHH RSCAN0.FFSTS.UINT8[HH] +#define RSCAN0FMSTS RSCAN0.FMSTS.UINT32 +#define RSCAN0FMSTSL RSCAN0.FMSTS.UINT16[L] +#define RSCAN0FMSTSLL RSCAN0.FMSTS.UINT8[LL] +#define RSCAN0FMSTSLH RSCAN0.FMSTS.UINT8[LH] +#define RSCAN0FMSTSH RSCAN0.FMSTS.UINT16[H] +#define RSCAN0FMSTSHL RSCAN0.FMSTS.UINT8[HL] +#define RSCAN0FMSTSHH RSCAN0.FMSTS.UINT8[HH] +#define RSCAN0RFISTS RSCAN0.RFISTS.UINT32 +#define RSCAN0RFISTSL RSCAN0.RFISTS.UINT16[L] +#define RSCAN0RFISTSLL RSCAN0.RFISTS.UINT8[LL] +#define RSCAN0RFISTSLH RSCAN0.RFISTS.UINT8[LH] +#define RSCAN0RFISTSH RSCAN0.RFISTS.UINT16[H] +#define RSCAN0RFISTSHL RSCAN0.RFISTS.UINT8[HL] +#define RSCAN0RFISTSHH RSCAN0.RFISTS.UINT8[HH] +#define RSCAN0CFRISTS RSCAN0.CFRISTS.UINT32 +#define RSCAN0CFRISTSL RSCAN0.CFRISTS.UINT16[L] +#define RSCAN0CFRISTSLL RSCAN0.CFRISTS.UINT8[LL] +#define RSCAN0CFRISTSLH RSCAN0.CFRISTS.UINT8[LH] +#define RSCAN0CFRISTSH RSCAN0.CFRISTS.UINT16[H] +#define RSCAN0CFRISTSHL RSCAN0.CFRISTS.UINT8[HL] +#define RSCAN0CFRISTSHH RSCAN0.CFRISTS.UINT8[HH] +#define RSCAN0CFTISTS RSCAN0.CFTISTS.UINT32 +#define RSCAN0CFTISTSL RSCAN0.CFTISTS.UINT16[L] +#define RSCAN0CFTISTSLL RSCAN0.CFTISTS.UINT8[LL] +#define RSCAN0CFTISTSLH RSCAN0.CFTISTS.UINT8[LH] +#define RSCAN0CFTISTSH RSCAN0.CFTISTS.UINT16[H] +#define RSCAN0CFTISTSHL RSCAN0.CFTISTS.UINT8[HL] +#define RSCAN0CFTISTSHH RSCAN0.CFTISTS.UINT8[HH] +#define RSCAN0TMC0 RSCAN0.TMC0 +#define RSCAN0TMC1 RSCAN0.TMC1 +#define RSCAN0TMC2 RSCAN0.TMC2 +#define RSCAN0TMC3 RSCAN0.TMC3 +#define RSCAN0TMC4 RSCAN0.TMC4 +#define RSCAN0TMC5 RSCAN0.TMC5 +#define RSCAN0TMC6 RSCAN0.TMC6 +#define RSCAN0TMC7 RSCAN0.TMC7 +#define RSCAN0TMC8 RSCAN0.TMC8 +#define RSCAN0TMC9 RSCAN0.TMC9 +#define RSCAN0TMC10 RSCAN0.TMC10 +#define RSCAN0TMC11 RSCAN0.TMC11 +#define RSCAN0TMC12 RSCAN0.TMC12 +#define RSCAN0TMC13 RSCAN0.TMC13 +#define RSCAN0TMC14 RSCAN0.TMC14 +#define RSCAN0TMC15 RSCAN0.TMC15 +#define RSCAN0TMC16 RSCAN0.TMC16 +#define RSCAN0TMC17 RSCAN0.TMC17 +#define RSCAN0TMC18 RSCAN0.TMC18 +#define RSCAN0TMC19 RSCAN0.TMC19 +#define RSCAN0TMC20 RSCAN0.TMC20 +#define RSCAN0TMC21 RSCAN0.TMC21 +#define RSCAN0TMC22 RSCAN0.TMC22 +#define RSCAN0TMC23 RSCAN0.TMC23 +#define RSCAN0TMC24 RSCAN0.TMC24 +#define RSCAN0TMC25 RSCAN0.TMC25 +#define RSCAN0TMC26 RSCAN0.TMC26 +#define RSCAN0TMC27 RSCAN0.TMC27 +#define RSCAN0TMC28 RSCAN0.TMC28 +#define RSCAN0TMC29 RSCAN0.TMC29 +#define RSCAN0TMC30 RSCAN0.TMC30 +#define RSCAN0TMC31 RSCAN0.TMC31 +#define RSCAN0TMC32 RSCAN0.TMC32 +#define RSCAN0TMC33 RSCAN0.TMC33 +#define RSCAN0TMC34 RSCAN0.TMC34 +#define RSCAN0TMC35 RSCAN0.TMC35 +#define RSCAN0TMC36 RSCAN0.TMC36 +#define RSCAN0TMC37 RSCAN0.TMC37 +#define RSCAN0TMC38 RSCAN0.TMC38 +#define RSCAN0TMC39 RSCAN0.TMC39 +#define RSCAN0TMC40 RSCAN0.TMC40 +#define RSCAN0TMC41 RSCAN0.TMC41 +#define RSCAN0TMC42 RSCAN0.TMC42 +#define RSCAN0TMC43 RSCAN0.TMC43 +#define RSCAN0TMC44 RSCAN0.TMC44 +#define RSCAN0TMC45 RSCAN0.TMC45 +#define RSCAN0TMC46 RSCAN0.TMC46 +#define RSCAN0TMC47 RSCAN0.TMC47 +#define RSCAN0TMC48 RSCAN0.TMC48 +#define RSCAN0TMC49 RSCAN0.TMC49 +#define RSCAN0TMC50 RSCAN0.TMC50 +#define RSCAN0TMC51 RSCAN0.TMC51 +#define RSCAN0TMC52 RSCAN0.TMC52 +#define RSCAN0TMC53 RSCAN0.TMC53 +#define RSCAN0TMC54 RSCAN0.TMC54 +#define RSCAN0TMC55 RSCAN0.TMC55 +#define RSCAN0TMC56 RSCAN0.TMC56 +#define RSCAN0TMC57 RSCAN0.TMC57 +#define RSCAN0TMC58 RSCAN0.TMC58 +#define RSCAN0TMC59 RSCAN0.TMC59 +#define RSCAN0TMC60 RSCAN0.TMC60 +#define RSCAN0TMC61 RSCAN0.TMC61 +#define RSCAN0TMC62 RSCAN0.TMC62 +#define RSCAN0TMC63 RSCAN0.TMC63 +#define RSCAN0TMC64 RSCAN0.TMC64 +#define RSCAN0TMC65 RSCAN0.TMC65 +#define RSCAN0TMC66 RSCAN0.TMC66 +#define RSCAN0TMC67 RSCAN0.TMC67 +#define RSCAN0TMC68 RSCAN0.TMC68 +#define RSCAN0TMC69 RSCAN0.TMC69 +#define RSCAN0TMC70 RSCAN0.TMC70 +#define RSCAN0TMC71 RSCAN0.TMC71 +#define RSCAN0TMC72 RSCAN0.TMC72 +#define RSCAN0TMC73 RSCAN0.TMC73 +#define RSCAN0TMC74 RSCAN0.TMC74 +#define RSCAN0TMC75 RSCAN0.TMC75 +#define RSCAN0TMC76 RSCAN0.TMC76 +#define RSCAN0TMC77 RSCAN0.TMC77 +#define RSCAN0TMC78 RSCAN0.TMC78 +#define RSCAN0TMC79 RSCAN0.TMC79 +#define RSCAN0TMSTS0 RSCAN0.TMSTS0 +#define RSCAN0TMSTS1 RSCAN0.TMSTS1 +#define RSCAN0TMSTS2 RSCAN0.TMSTS2 +#define RSCAN0TMSTS3 RSCAN0.TMSTS3 +#define RSCAN0TMSTS4 RSCAN0.TMSTS4 +#define RSCAN0TMSTS5 RSCAN0.TMSTS5 +#define RSCAN0TMSTS6 RSCAN0.TMSTS6 +#define RSCAN0TMSTS7 RSCAN0.TMSTS7 +#define RSCAN0TMSTS8 RSCAN0.TMSTS8 +#define RSCAN0TMSTS9 RSCAN0.TMSTS9 +#define RSCAN0TMSTS10 RSCAN0.TMSTS10 +#define RSCAN0TMSTS11 RSCAN0.TMSTS11 +#define RSCAN0TMSTS12 RSCAN0.TMSTS12 +#define RSCAN0TMSTS13 RSCAN0.TMSTS13 +#define RSCAN0TMSTS14 RSCAN0.TMSTS14 +#define RSCAN0TMSTS15 RSCAN0.TMSTS15 +#define RSCAN0TMSTS16 RSCAN0.TMSTS16 +#define RSCAN0TMSTS17 RSCAN0.TMSTS17 +#define RSCAN0TMSTS18 RSCAN0.TMSTS18 +#define RSCAN0TMSTS19 RSCAN0.TMSTS19 +#define RSCAN0TMSTS20 RSCAN0.TMSTS20 +#define RSCAN0TMSTS21 RSCAN0.TMSTS21 +#define RSCAN0TMSTS22 RSCAN0.TMSTS22 +#define RSCAN0TMSTS23 RSCAN0.TMSTS23 +#define RSCAN0TMSTS24 RSCAN0.TMSTS24 +#define RSCAN0TMSTS25 RSCAN0.TMSTS25 +#define RSCAN0TMSTS26 RSCAN0.TMSTS26 +#define RSCAN0TMSTS27 RSCAN0.TMSTS27 +#define RSCAN0TMSTS28 RSCAN0.TMSTS28 +#define RSCAN0TMSTS29 RSCAN0.TMSTS29 +#define RSCAN0TMSTS30 RSCAN0.TMSTS30 +#define RSCAN0TMSTS31 RSCAN0.TMSTS31 +#define RSCAN0TMSTS32 RSCAN0.TMSTS32 +#define RSCAN0TMSTS33 RSCAN0.TMSTS33 +#define RSCAN0TMSTS34 RSCAN0.TMSTS34 +#define RSCAN0TMSTS35 RSCAN0.TMSTS35 +#define RSCAN0TMSTS36 RSCAN0.TMSTS36 +#define RSCAN0TMSTS37 RSCAN0.TMSTS37 +#define RSCAN0TMSTS38 RSCAN0.TMSTS38 +#define RSCAN0TMSTS39 RSCAN0.TMSTS39 +#define RSCAN0TMSTS40 RSCAN0.TMSTS40 +#define RSCAN0TMSTS41 RSCAN0.TMSTS41 +#define RSCAN0TMSTS42 RSCAN0.TMSTS42 +#define RSCAN0TMSTS43 RSCAN0.TMSTS43 +#define RSCAN0TMSTS44 RSCAN0.TMSTS44 +#define RSCAN0TMSTS45 RSCAN0.TMSTS45 +#define RSCAN0TMSTS46 RSCAN0.TMSTS46 +#define RSCAN0TMSTS47 RSCAN0.TMSTS47 +#define RSCAN0TMSTS48 RSCAN0.TMSTS48 +#define RSCAN0TMSTS49 RSCAN0.TMSTS49 +#define RSCAN0TMSTS50 RSCAN0.TMSTS50 +#define RSCAN0TMSTS51 RSCAN0.TMSTS51 +#define RSCAN0TMSTS52 RSCAN0.TMSTS52 +#define RSCAN0TMSTS53 RSCAN0.TMSTS53 +#define RSCAN0TMSTS54 RSCAN0.TMSTS54 +#define RSCAN0TMSTS55 RSCAN0.TMSTS55 +#define RSCAN0TMSTS56 RSCAN0.TMSTS56 +#define RSCAN0TMSTS57 RSCAN0.TMSTS57 +#define RSCAN0TMSTS58 RSCAN0.TMSTS58 +#define RSCAN0TMSTS59 RSCAN0.TMSTS59 +#define RSCAN0TMSTS60 RSCAN0.TMSTS60 +#define RSCAN0TMSTS61 RSCAN0.TMSTS61 +#define RSCAN0TMSTS62 RSCAN0.TMSTS62 +#define RSCAN0TMSTS63 RSCAN0.TMSTS63 +#define RSCAN0TMSTS64 RSCAN0.TMSTS64 +#define RSCAN0TMSTS65 RSCAN0.TMSTS65 +#define RSCAN0TMSTS66 RSCAN0.TMSTS66 +#define RSCAN0TMSTS67 RSCAN0.TMSTS67 +#define RSCAN0TMSTS68 RSCAN0.TMSTS68 +#define RSCAN0TMSTS69 RSCAN0.TMSTS69 +#define RSCAN0TMSTS70 RSCAN0.TMSTS70 +#define RSCAN0TMSTS71 RSCAN0.TMSTS71 +#define RSCAN0TMSTS72 RSCAN0.TMSTS72 +#define RSCAN0TMSTS73 RSCAN0.TMSTS73 +#define RSCAN0TMSTS74 RSCAN0.TMSTS74 +#define RSCAN0TMSTS75 RSCAN0.TMSTS75 +#define RSCAN0TMSTS76 RSCAN0.TMSTS76 +#define RSCAN0TMSTS77 RSCAN0.TMSTS77 +#define RSCAN0TMSTS78 RSCAN0.TMSTS78 +#define RSCAN0TMSTS79 RSCAN0.TMSTS79 +#define RSCAN0TMTRSTS0 RSCAN0.TMTRSTS0.UINT32 +#define RSCAN0TMTRSTS0L RSCAN0.TMTRSTS0.UINT16[L] +#define RSCAN0TMTRSTS0LL RSCAN0.TMTRSTS0.UINT8[LL] +#define RSCAN0TMTRSTS0LH RSCAN0.TMTRSTS0.UINT8[LH] +#define RSCAN0TMTRSTS0H RSCAN0.TMTRSTS0.UINT16[H] +#define RSCAN0TMTRSTS0HL RSCAN0.TMTRSTS0.UINT8[HL] +#define RSCAN0TMTRSTS0HH RSCAN0.TMTRSTS0.UINT8[HH] +#define RSCAN0TMTRSTS1 RSCAN0.TMTRSTS1.UINT32 +#define RSCAN0TMTRSTS1L RSCAN0.TMTRSTS1.UINT16[L] +#define RSCAN0TMTRSTS1LL RSCAN0.TMTRSTS1.UINT8[LL] +#define RSCAN0TMTRSTS1LH RSCAN0.TMTRSTS1.UINT8[LH] +#define RSCAN0TMTRSTS1H RSCAN0.TMTRSTS1.UINT16[H] +#define RSCAN0TMTRSTS1HL RSCAN0.TMTRSTS1.UINT8[HL] +#define RSCAN0TMTRSTS1HH RSCAN0.TMTRSTS1.UINT8[HH] +#define RSCAN0TMTRSTS2 RSCAN0.TMTRSTS2.UINT32 +#define RSCAN0TMTRSTS2L RSCAN0.TMTRSTS2.UINT16[L] +#define RSCAN0TMTRSTS2LL RSCAN0.TMTRSTS2.UINT8[LL] +#define RSCAN0TMTRSTS2LH RSCAN0.TMTRSTS2.UINT8[LH] +#define RSCAN0TMTRSTS2H RSCAN0.TMTRSTS2.UINT16[H] +#define RSCAN0TMTRSTS2HL RSCAN0.TMTRSTS2.UINT8[HL] +#define RSCAN0TMTRSTS2HH RSCAN0.TMTRSTS2.UINT8[HH] +#define RSCAN0TMTARSTS0 RSCAN0.TMTARSTS0.UINT32 +#define RSCAN0TMTARSTS0L RSCAN0.TMTARSTS0.UINT16[L] +#define RSCAN0TMTARSTS0LL RSCAN0.TMTARSTS0.UINT8[LL] +#define RSCAN0TMTARSTS0LH RSCAN0.TMTARSTS0.UINT8[LH] +#define RSCAN0TMTARSTS0H RSCAN0.TMTARSTS0.UINT16[H] +#define RSCAN0TMTARSTS0HL RSCAN0.TMTARSTS0.UINT8[HL] +#define RSCAN0TMTARSTS0HH RSCAN0.TMTARSTS0.UINT8[HH] +#define RSCAN0TMTARSTS1 RSCAN0.TMTARSTS1.UINT32 +#define RSCAN0TMTARSTS1L RSCAN0.TMTARSTS1.UINT16[L] +#define RSCAN0TMTARSTS1LL RSCAN0.TMTARSTS1.UINT8[LL] +#define RSCAN0TMTARSTS1LH RSCAN0.TMTARSTS1.UINT8[LH] +#define RSCAN0TMTARSTS1H RSCAN0.TMTARSTS1.UINT16[H] +#define RSCAN0TMTARSTS1HL RSCAN0.TMTARSTS1.UINT8[HL] +#define RSCAN0TMTARSTS1HH RSCAN0.TMTARSTS1.UINT8[HH] +#define RSCAN0TMTARSTS2 RSCAN0.TMTARSTS2.UINT32 +#define RSCAN0TMTARSTS2L RSCAN0.TMTARSTS2.UINT16[L] +#define RSCAN0TMTARSTS2LL RSCAN0.TMTARSTS2.UINT8[LL] +#define RSCAN0TMTARSTS2LH RSCAN0.TMTARSTS2.UINT8[LH] +#define RSCAN0TMTARSTS2H RSCAN0.TMTARSTS2.UINT16[H] +#define RSCAN0TMTARSTS2HL RSCAN0.TMTARSTS2.UINT8[HL] +#define RSCAN0TMTARSTS2HH RSCAN0.TMTARSTS2.UINT8[HH] +#define RSCAN0TMTCSTS0 RSCAN0.TMTCSTS0.UINT32 +#define RSCAN0TMTCSTS0L RSCAN0.TMTCSTS0.UINT16[L] +#define RSCAN0TMTCSTS0LL RSCAN0.TMTCSTS0.UINT8[LL] +#define RSCAN0TMTCSTS0LH RSCAN0.TMTCSTS0.UINT8[LH] +#define RSCAN0TMTCSTS0H RSCAN0.TMTCSTS0.UINT16[H] +#define RSCAN0TMTCSTS0HL RSCAN0.TMTCSTS0.UINT8[HL] +#define RSCAN0TMTCSTS0HH RSCAN0.TMTCSTS0.UINT8[HH] +#define RSCAN0TMTCSTS1 RSCAN0.TMTCSTS1.UINT32 +#define RSCAN0TMTCSTS1L RSCAN0.TMTCSTS1.UINT16[L] +#define RSCAN0TMTCSTS1LL RSCAN0.TMTCSTS1.UINT8[LL] +#define RSCAN0TMTCSTS1LH RSCAN0.TMTCSTS1.UINT8[LH] +#define RSCAN0TMTCSTS1H RSCAN0.TMTCSTS1.UINT16[H] +#define RSCAN0TMTCSTS1HL RSCAN0.TMTCSTS1.UINT8[HL] +#define RSCAN0TMTCSTS1HH RSCAN0.TMTCSTS1.UINT8[HH] +#define RSCAN0TMTCSTS2 RSCAN0.TMTCSTS2.UINT32 +#define RSCAN0TMTCSTS2L RSCAN0.TMTCSTS2.UINT16[L] +#define RSCAN0TMTCSTS2LL RSCAN0.TMTCSTS2.UINT8[LL] +#define RSCAN0TMTCSTS2LH RSCAN0.TMTCSTS2.UINT8[LH] +#define RSCAN0TMTCSTS2H RSCAN0.TMTCSTS2.UINT16[H] +#define RSCAN0TMTCSTS2HL RSCAN0.TMTCSTS2.UINT8[HL] +#define RSCAN0TMTCSTS2HH RSCAN0.TMTCSTS2.UINT8[HH] +#define RSCAN0TMTASTS0 RSCAN0.TMTASTS0.UINT32 +#define RSCAN0TMTASTS0L RSCAN0.TMTASTS0.UINT16[L] +#define RSCAN0TMTASTS0LL RSCAN0.TMTASTS0.UINT8[LL] +#define RSCAN0TMTASTS0LH RSCAN0.TMTASTS0.UINT8[LH] +#define RSCAN0TMTASTS0H RSCAN0.TMTASTS0.UINT16[H] +#define RSCAN0TMTASTS0HL RSCAN0.TMTASTS0.UINT8[HL] +#define RSCAN0TMTASTS0HH RSCAN0.TMTASTS0.UINT8[HH] +#define RSCAN0TMTASTS1 RSCAN0.TMTASTS1.UINT32 +#define RSCAN0TMTASTS1L RSCAN0.TMTASTS1.UINT16[L] +#define RSCAN0TMTASTS1LL RSCAN0.TMTASTS1.UINT8[LL] +#define RSCAN0TMTASTS1LH RSCAN0.TMTASTS1.UINT8[LH] +#define RSCAN0TMTASTS1H RSCAN0.TMTASTS1.UINT16[H] +#define RSCAN0TMTASTS1HL RSCAN0.TMTASTS1.UINT8[HL] +#define RSCAN0TMTASTS1HH RSCAN0.TMTASTS1.UINT8[HH] +#define RSCAN0TMTASTS2 RSCAN0.TMTASTS2.UINT32 +#define RSCAN0TMTASTS2L RSCAN0.TMTASTS2.UINT16[L] +#define RSCAN0TMTASTS2LL RSCAN0.TMTASTS2.UINT8[LL] +#define RSCAN0TMTASTS2LH RSCAN0.TMTASTS2.UINT8[LH] +#define RSCAN0TMTASTS2H RSCAN0.TMTASTS2.UINT16[H] +#define RSCAN0TMTASTS2HL RSCAN0.TMTASTS2.UINT8[HL] +#define RSCAN0TMTASTS2HH RSCAN0.TMTASTS2.UINT8[HH] +#define RSCAN0TMIEC0 RSCAN0.TMIEC0.UINT32 +#define RSCAN0TMIEC0L RSCAN0.TMIEC0.UINT16[L] +#define RSCAN0TMIEC0LL RSCAN0.TMIEC0.UINT8[LL] +#define RSCAN0TMIEC0LH RSCAN0.TMIEC0.UINT8[LH] +#define RSCAN0TMIEC0H RSCAN0.TMIEC0.UINT16[H] +#define RSCAN0TMIEC0HL RSCAN0.TMIEC0.UINT8[HL] +#define RSCAN0TMIEC0HH RSCAN0.TMIEC0.UINT8[HH] +#define RSCAN0TMIEC1 RSCAN0.TMIEC1.UINT32 +#define RSCAN0TMIEC1L RSCAN0.TMIEC1.UINT16[L] +#define RSCAN0TMIEC1LL RSCAN0.TMIEC1.UINT8[LL] +#define RSCAN0TMIEC1LH RSCAN0.TMIEC1.UINT8[LH] +#define RSCAN0TMIEC1H RSCAN0.TMIEC1.UINT16[H] +#define RSCAN0TMIEC1HL RSCAN0.TMIEC1.UINT8[HL] +#define RSCAN0TMIEC1HH RSCAN0.TMIEC1.UINT8[HH] +#define RSCAN0TMIEC2 RSCAN0.TMIEC2.UINT32 +#define RSCAN0TMIEC2L RSCAN0.TMIEC2.UINT16[L] +#define RSCAN0TMIEC2LL RSCAN0.TMIEC2.UINT8[LL] +#define RSCAN0TMIEC2LH RSCAN0.TMIEC2.UINT8[LH] +#define RSCAN0TMIEC2H RSCAN0.TMIEC2.UINT16[H] +#define RSCAN0TMIEC2HL RSCAN0.TMIEC2.UINT8[HL] +#define RSCAN0TMIEC2HH RSCAN0.TMIEC2.UINT8[HH] +#define RSCAN0TXQCC0 RSCAN0.TXQCC0.UINT32 +#define RSCAN0TXQCC0L RSCAN0.TXQCC0.UINT16[L] +#define RSCAN0TXQCC0LL RSCAN0.TXQCC0.UINT8[LL] +#define RSCAN0TXQCC0LH RSCAN0.TXQCC0.UINT8[LH] +#define RSCAN0TXQCC0H RSCAN0.TXQCC0.UINT16[H] +#define RSCAN0TXQCC0HL RSCAN0.TXQCC0.UINT8[HL] +#define RSCAN0TXQCC0HH RSCAN0.TXQCC0.UINT8[HH] +#define RSCAN0TXQCC1 RSCAN0.TXQCC1.UINT32 +#define RSCAN0TXQCC1L RSCAN0.TXQCC1.UINT16[L] +#define RSCAN0TXQCC1LL RSCAN0.TXQCC1.UINT8[LL] +#define RSCAN0TXQCC1LH RSCAN0.TXQCC1.UINT8[LH] +#define RSCAN0TXQCC1H RSCAN0.TXQCC1.UINT16[H] +#define RSCAN0TXQCC1HL RSCAN0.TXQCC1.UINT8[HL] +#define RSCAN0TXQCC1HH RSCAN0.TXQCC1.UINT8[HH] +#define RSCAN0TXQCC2 RSCAN0.TXQCC2.UINT32 +#define RSCAN0TXQCC2L RSCAN0.TXQCC2.UINT16[L] +#define RSCAN0TXQCC2LL RSCAN0.TXQCC2.UINT8[LL] +#define RSCAN0TXQCC2LH RSCAN0.TXQCC2.UINT8[LH] +#define RSCAN0TXQCC2H RSCAN0.TXQCC2.UINT16[H] +#define RSCAN0TXQCC2HL RSCAN0.TXQCC2.UINT8[HL] +#define RSCAN0TXQCC2HH RSCAN0.TXQCC2.UINT8[HH] +#define RSCAN0TXQCC3 RSCAN0.TXQCC3.UINT32 +#define RSCAN0TXQCC3L RSCAN0.TXQCC3.UINT16[L] +#define RSCAN0TXQCC3LL RSCAN0.TXQCC3.UINT8[LL] +#define RSCAN0TXQCC3LH RSCAN0.TXQCC3.UINT8[LH] +#define RSCAN0TXQCC3H RSCAN0.TXQCC3.UINT16[H] +#define RSCAN0TXQCC3HL RSCAN0.TXQCC3.UINT8[HL] +#define RSCAN0TXQCC3HH RSCAN0.TXQCC3.UINT8[HH] +#define RSCAN0TXQCC4 RSCAN0.TXQCC4.UINT32 +#define RSCAN0TXQCC4L RSCAN0.TXQCC4.UINT16[L] +#define RSCAN0TXQCC4LL RSCAN0.TXQCC4.UINT8[LL] +#define RSCAN0TXQCC4LH RSCAN0.TXQCC4.UINT8[LH] +#define RSCAN0TXQCC4H RSCAN0.TXQCC4.UINT16[H] +#define RSCAN0TXQCC4HL RSCAN0.TXQCC4.UINT8[HL] +#define RSCAN0TXQCC4HH RSCAN0.TXQCC4.UINT8[HH] +#define RSCAN0TXQSTS0 RSCAN0.TXQSTS0.UINT32 +#define RSCAN0TXQSTS0L RSCAN0.TXQSTS0.UINT16[L] +#define RSCAN0TXQSTS0LL RSCAN0.TXQSTS0.UINT8[LL] +#define RSCAN0TXQSTS0LH RSCAN0.TXQSTS0.UINT8[LH] +#define RSCAN0TXQSTS0H RSCAN0.TXQSTS0.UINT16[H] +#define RSCAN0TXQSTS0HL RSCAN0.TXQSTS0.UINT8[HL] +#define RSCAN0TXQSTS0HH RSCAN0.TXQSTS0.UINT8[HH] +#define RSCAN0TXQSTS1 RSCAN0.TXQSTS1.UINT32 +#define RSCAN0TXQSTS1L RSCAN0.TXQSTS1.UINT16[L] +#define RSCAN0TXQSTS1LL RSCAN0.TXQSTS1.UINT8[LL] +#define RSCAN0TXQSTS1LH RSCAN0.TXQSTS1.UINT8[LH] +#define RSCAN0TXQSTS1H RSCAN0.TXQSTS1.UINT16[H] +#define RSCAN0TXQSTS1HL RSCAN0.TXQSTS1.UINT8[HL] +#define RSCAN0TXQSTS1HH RSCAN0.TXQSTS1.UINT8[HH] +#define RSCAN0TXQSTS2 RSCAN0.TXQSTS2.UINT32 +#define RSCAN0TXQSTS2L RSCAN0.TXQSTS2.UINT16[L] +#define RSCAN0TXQSTS2LL RSCAN0.TXQSTS2.UINT8[LL] +#define RSCAN0TXQSTS2LH RSCAN0.TXQSTS2.UINT8[LH] +#define RSCAN0TXQSTS2H RSCAN0.TXQSTS2.UINT16[H] +#define RSCAN0TXQSTS2HL RSCAN0.TXQSTS2.UINT8[HL] +#define RSCAN0TXQSTS2HH RSCAN0.TXQSTS2.UINT8[HH] +#define RSCAN0TXQSTS3 RSCAN0.TXQSTS3.UINT32 +#define RSCAN0TXQSTS3L RSCAN0.TXQSTS3.UINT16[L] +#define RSCAN0TXQSTS3LL RSCAN0.TXQSTS3.UINT8[LL] +#define RSCAN0TXQSTS3LH RSCAN0.TXQSTS3.UINT8[LH] +#define RSCAN0TXQSTS3H RSCAN0.TXQSTS3.UINT16[H] +#define RSCAN0TXQSTS3HL RSCAN0.TXQSTS3.UINT8[HL] +#define RSCAN0TXQSTS3HH RSCAN0.TXQSTS3.UINT8[HH] +#define RSCAN0TXQSTS4 RSCAN0.TXQSTS4.UINT32 +#define RSCAN0TXQSTS4L RSCAN0.TXQSTS4.UINT16[L] +#define RSCAN0TXQSTS4LL RSCAN0.TXQSTS4.UINT8[LL] +#define RSCAN0TXQSTS4LH RSCAN0.TXQSTS4.UINT8[LH] +#define RSCAN0TXQSTS4H RSCAN0.TXQSTS4.UINT16[H] +#define RSCAN0TXQSTS4HL RSCAN0.TXQSTS4.UINT8[HL] +#define RSCAN0TXQSTS4HH RSCAN0.TXQSTS4.UINT8[HH] +#define RSCAN0TXQPCTR0 RSCAN0.TXQPCTR0.UINT32 +#define RSCAN0TXQPCTR0L RSCAN0.TXQPCTR0.UINT16[L] +#define RSCAN0TXQPCTR0LL RSCAN0.TXQPCTR0.UINT8[LL] +#define RSCAN0TXQPCTR0LH RSCAN0.TXQPCTR0.UINT8[LH] +#define RSCAN0TXQPCTR0H RSCAN0.TXQPCTR0.UINT16[H] +#define RSCAN0TXQPCTR0HL RSCAN0.TXQPCTR0.UINT8[HL] +#define RSCAN0TXQPCTR0HH RSCAN0.TXQPCTR0.UINT8[HH] +#define RSCAN0TXQPCTR1 RSCAN0.TXQPCTR1.UINT32 +#define RSCAN0TXQPCTR1L RSCAN0.TXQPCTR1.UINT16[L] +#define RSCAN0TXQPCTR1LL RSCAN0.TXQPCTR1.UINT8[LL] +#define RSCAN0TXQPCTR1LH RSCAN0.TXQPCTR1.UINT8[LH] +#define RSCAN0TXQPCTR1H RSCAN0.TXQPCTR1.UINT16[H] +#define RSCAN0TXQPCTR1HL RSCAN0.TXQPCTR1.UINT8[HL] +#define RSCAN0TXQPCTR1HH RSCAN0.TXQPCTR1.UINT8[HH] +#define RSCAN0TXQPCTR2 RSCAN0.TXQPCTR2.UINT32 +#define RSCAN0TXQPCTR2L RSCAN0.TXQPCTR2.UINT16[L] +#define RSCAN0TXQPCTR2LL RSCAN0.TXQPCTR2.UINT8[LL] +#define RSCAN0TXQPCTR2LH RSCAN0.TXQPCTR2.UINT8[LH] +#define RSCAN0TXQPCTR2H RSCAN0.TXQPCTR2.UINT16[H] +#define RSCAN0TXQPCTR2HL RSCAN0.TXQPCTR2.UINT8[HL] +#define RSCAN0TXQPCTR2HH RSCAN0.TXQPCTR2.UINT8[HH] +#define RSCAN0TXQPCTR3 RSCAN0.TXQPCTR3.UINT32 +#define RSCAN0TXQPCTR3L RSCAN0.TXQPCTR3.UINT16[L] +#define RSCAN0TXQPCTR3LL RSCAN0.TXQPCTR3.UINT8[LL] +#define RSCAN0TXQPCTR3LH RSCAN0.TXQPCTR3.UINT8[LH] +#define RSCAN0TXQPCTR3H RSCAN0.TXQPCTR3.UINT16[H] +#define RSCAN0TXQPCTR3HL RSCAN0.TXQPCTR3.UINT8[HL] +#define RSCAN0TXQPCTR3HH RSCAN0.TXQPCTR3.UINT8[HH] +#define RSCAN0TXQPCTR4 RSCAN0.TXQPCTR4.UINT32 +#define RSCAN0TXQPCTR4L RSCAN0.TXQPCTR4.UINT16[L] +#define RSCAN0TXQPCTR4LL RSCAN0.TXQPCTR4.UINT8[LL] +#define RSCAN0TXQPCTR4LH RSCAN0.TXQPCTR4.UINT8[LH] +#define RSCAN0TXQPCTR4H RSCAN0.TXQPCTR4.UINT16[H] +#define RSCAN0TXQPCTR4HL RSCAN0.TXQPCTR4.UINT8[HL] +#define RSCAN0TXQPCTR4HH RSCAN0.TXQPCTR4.UINT8[HH] +#define RSCAN0THLCC0 RSCAN0.THLCC0.UINT32 +#define RSCAN0THLCC0L RSCAN0.THLCC0.UINT16[L] +#define RSCAN0THLCC0LL RSCAN0.THLCC0.UINT8[LL] +#define RSCAN0THLCC0LH RSCAN0.THLCC0.UINT8[LH] +#define RSCAN0THLCC0H RSCAN0.THLCC0.UINT16[H] +#define RSCAN0THLCC0HL RSCAN0.THLCC0.UINT8[HL] +#define RSCAN0THLCC0HH RSCAN0.THLCC0.UINT8[HH] +#define RSCAN0THLCC1 RSCAN0.THLCC1.UINT32 +#define RSCAN0THLCC1L RSCAN0.THLCC1.UINT16[L] +#define RSCAN0THLCC1LL RSCAN0.THLCC1.UINT8[LL] +#define RSCAN0THLCC1LH RSCAN0.THLCC1.UINT8[LH] +#define RSCAN0THLCC1H RSCAN0.THLCC1.UINT16[H] +#define RSCAN0THLCC1HL RSCAN0.THLCC1.UINT8[HL] +#define RSCAN0THLCC1HH RSCAN0.THLCC1.UINT8[HH] +#define RSCAN0THLCC2 RSCAN0.THLCC2.UINT32 +#define RSCAN0THLCC2L RSCAN0.THLCC2.UINT16[L] +#define RSCAN0THLCC2LL RSCAN0.THLCC2.UINT8[LL] +#define RSCAN0THLCC2LH RSCAN0.THLCC2.UINT8[LH] +#define RSCAN0THLCC2H RSCAN0.THLCC2.UINT16[H] +#define RSCAN0THLCC2HL RSCAN0.THLCC2.UINT8[HL] +#define RSCAN0THLCC2HH RSCAN0.THLCC2.UINT8[HH] +#define RSCAN0THLCC3 RSCAN0.THLCC3.UINT32 +#define RSCAN0THLCC3L RSCAN0.THLCC3.UINT16[L] +#define RSCAN0THLCC3LL RSCAN0.THLCC3.UINT8[LL] +#define RSCAN0THLCC3LH RSCAN0.THLCC3.UINT8[LH] +#define RSCAN0THLCC3H RSCAN0.THLCC3.UINT16[H] +#define RSCAN0THLCC3HL RSCAN0.THLCC3.UINT8[HL] +#define RSCAN0THLCC3HH RSCAN0.THLCC3.UINT8[HH] +#define RSCAN0THLCC4 RSCAN0.THLCC4.UINT32 +#define RSCAN0THLCC4L RSCAN0.THLCC4.UINT16[L] +#define RSCAN0THLCC4LL RSCAN0.THLCC4.UINT8[LL] +#define RSCAN0THLCC4LH RSCAN0.THLCC4.UINT8[LH] +#define RSCAN0THLCC4H RSCAN0.THLCC4.UINT16[H] +#define RSCAN0THLCC4HL RSCAN0.THLCC4.UINT8[HL] +#define RSCAN0THLCC4HH RSCAN0.THLCC4.UINT8[HH] +#define RSCAN0THLSTS0 RSCAN0.THLSTS0.UINT32 +#define RSCAN0THLSTS0L RSCAN0.THLSTS0.UINT16[L] +#define RSCAN0THLSTS0LL RSCAN0.THLSTS0.UINT8[LL] +#define RSCAN0THLSTS0LH RSCAN0.THLSTS0.UINT8[LH] +#define RSCAN0THLSTS0H RSCAN0.THLSTS0.UINT16[H] +#define RSCAN0THLSTS0HL RSCAN0.THLSTS0.UINT8[HL] +#define RSCAN0THLSTS0HH RSCAN0.THLSTS0.UINT8[HH] +#define RSCAN0THLSTS1 RSCAN0.THLSTS1.UINT32 +#define RSCAN0THLSTS1L RSCAN0.THLSTS1.UINT16[L] +#define RSCAN0THLSTS1LL RSCAN0.THLSTS1.UINT8[LL] +#define RSCAN0THLSTS1LH RSCAN0.THLSTS1.UINT8[LH] +#define RSCAN0THLSTS1H RSCAN0.THLSTS1.UINT16[H] +#define RSCAN0THLSTS1HL RSCAN0.THLSTS1.UINT8[HL] +#define RSCAN0THLSTS1HH RSCAN0.THLSTS1.UINT8[HH] +#define RSCAN0THLSTS2 RSCAN0.THLSTS2.UINT32 +#define RSCAN0THLSTS2L RSCAN0.THLSTS2.UINT16[L] +#define RSCAN0THLSTS2LL RSCAN0.THLSTS2.UINT8[LL] +#define RSCAN0THLSTS2LH RSCAN0.THLSTS2.UINT8[LH] +#define RSCAN0THLSTS2H RSCAN0.THLSTS2.UINT16[H] +#define RSCAN0THLSTS2HL RSCAN0.THLSTS2.UINT8[HL] +#define RSCAN0THLSTS2HH RSCAN0.THLSTS2.UINT8[HH] +#define RSCAN0THLSTS3 RSCAN0.THLSTS3.UINT32 +#define RSCAN0THLSTS3L RSCAN0.THLSTS3.UINT16[L] +#define RSCAN0THLSTS3LL RSCAN0.THLSTS3.UINT8[LL] +#define RSCAN0THLSTS3LH RSCAN0.THLSTS3.UINT8[LH] +#define RSCAN0THLSTS3H RSCAN0.THLSTS3.UINT16[H] +#define RSCAN0THLSTS3HL RSCAN0.THLSTS3.UINT8[HL] +#define RSCAN0THLSTS3HH RSCAN0.THLSTS3.UINT8[HH] +#define RSCAN0THLSTS4 RSCAN0.THLSTS4.UINT32 +#define RSCAN0THLSTS4L RSCAN0.THLSTS4.UINT16[L] +#define RSCAN0THLSTS4LL RSCAN0.THLSTS4.UINT8[LL] +#define RSCAN0THLSTS4LH RSCAN0.THLSTS4.UINT8[LH] +#define RSCAN0THLSTS4H RSCAN0.THLSTS4.UINT16[H] +#define RSCAN0THLSTS4HL RSCAN0.THLSTS4.UINT8[HL] +#define RSCAN0THLSTS4HH RSCAN0.THLSTS4.UINT8[HH] +#define RSCAN0THLPCTR0 RSCAN0.THLPCTR0.UINT32 +#define RSCAN0THLPCTR0L RSCAN0.THLPCTR0.UINT16[L] +#define RSCAN0THLPCTR0LL RSCAN0.THLPCTR0.UINT8[LL] +#define RSCAN0THLPCTR0LH RSCAN0.THLPCTR0.UINT8[LH] +#define RSCAN0THLPCTR0H RSCAN0.THLPCTR0.UINT16[H] +#define RSCAN0THLPCTR0HL RSCAN0.THLPCTR0.UINT8[HL] +#define RSCAN0THLPCTR0HH RSCAN0.THLPCTR0.UINT8[HH] +#define RSCAN0THLPCTR1 RSCAN0.THLPCTR1.UINT32 +#define RSCAN0THLPCTR1L RSCAN0.THLPCTR1.UINT16[L] +#define RSCAN0THLPCTR1LL RSCAN0.THLPCTR1.UINT8[LL] +#define RSCAN0THLPCTR1LH RSCAN0.THLPCTR1.UINT8[LH] +#define RSCAN0THLPCTR1H RSCAN0.THLPCTR1.UINT16[H] +#define RSCAN0THLPCTR1HL RSCAN0.THLPCTR1.UINT8[HL] +#define RSCAN0THLPCTR1HH RSCAN0.THLPCTR1.UINT8[HH] +#define RSCAN0THLPCTR2 RSCAN0.THLPCTR2.UINT32 +#define RSCAN0THLPCTR2L RSCAN0.THLPCTR2.UINT16[L] +#define RSCAN0THLPCTR2LL RSCAN0.THLPCTR2.UINT8[LL] +#define RSCAN0THLPCTR2LH RSCAN0.THLPCTR2.UINT8[LH] +#define RSCAN0THLPCTR2H RSCAN0.THLPCTR2.UINT16[H] +#define RSCAN0THLPCTR2HL RSCAN0.THLPCTR2.UINT8[HL] +#define RSCAN0THLPCTR2HH RSCAN0.THLPCTR2.UINT8[HH] +#define RSCAN0THLPCTR3 RSCAN0.THLPCTR3.UINT32 +#define RSCAN0THLPCTR3L RSCAN0.THLPCTR3.UINT16[L] +#define RSCAN0THLPCTR3LL RSCAN0.THLPCTR3.UINT8[LL] +#define RSCAN0THLPCTR3LH RSCAN0.THLPCTR3.UINT8[LH] +#define RSCAN0THLPCTR3H RSCAN0.THLPCTR3.UINT16[H] +#define RSCAN0THLPCTR3HL RSCAN0.THLPCTR3.UINT8[HL] +#define RSCAN0THLPCTR3HH RSCAN0.THLPCTR3.UINT8[HH] +#define RSCAN0THLPCTR4 RSCAN0.THLPCTR4.UINT32 +#define RSCAN0THLPCTR4L RSCAN0.THLPCTR4.UINT16[L] +#define RSCAN0THLPCTR4LL RSCAN0.THLPCTR4.UINT8[LL] +#define RSCAN0THLPCTR4LH RSCAN0.THLPCTR4.UINT8[LH] +#define RSCAN0THLPCTR4H RSCAN0.THLPCTR4.UINT16[H] +#define RSCAN0THLPCTR4HL RSCAN0.THLPCTR4.UINT8[HL] +#define RSCAN0THLPCTR4HH RSCAN0.THLPCTR4.UINT8[HH] +#define RSCAN0GTINTSTS0 RSCAN0.GTINTSTS0.UINT32 +#define RSCAN0GTINTSTS0L RSCAN0.GTINTSTS0.UINT16[L] +#define RSCAN0GTINTSTS0LL RSCAN0.GTINTSTS0.UINT8[LL] +#define RSCAN0GTINTSTS0LH RSCAN0.GTINTSTS0.UINT8[LH] +#define RSCAN0GTINTSTS0H RSCAN0.GTINTSTS0.UINT16[H] +#define RSCAN0GTINTSTS0HL RSCAN0.GTINTSTS0.UINT8[HL] +#define RSCAN0GTINTSTS0HH RSCAN0.GTINTSTS0.UINT8[HH] +#define RSCAN0GTINTSTS1 RSCAN0.GTINTSTS1.UINT32 +#define RSCAN0GTINTSTS1L RSCAN0.GTINTSTS1.UINT16[L] +#define RSCAN0GTINTSTS1LL RSCAN0.GTINTSTS1.UINT8[LL] +#define RSCAN0GTINTSTS1LH RSCAN0.GTINTSTS1.UINT8[LH] +#define RSCAN0GTINTSTS1H RSCAN0.GTINTSTS1.UINT16[H] +#define RSCAN0GTINTSTS1HL RSCAN0.GTINTSTS1.UINT8[HL] +#define RSCAN0GTINTSTS1HH RSCAN0.GTINTSTS1.UINT8[HH] +#define RSCAN0GTSTCFG RSCAN0.GTSTCFG.UINT32 +#define RSCAN0GTSTCFGL RSCAN0.GTSTCFG.UINT16[L] +#define RSCAN0GTSTCFGLL RSCAN0.GTSTCFG.UINT8[LL] +#define RSCAN0GTSTCFGLH RSCAN0.GTSTCFG.UINT8[LH] +#define RSCAN0GTSTCFGH RSCAN0.GTSTCFG.UINT16[H] +#define RSCAN0GTSTCFGHL RSCAN0.GTSTCFG.UINT8[HL] +#define RSCAN0GTSTCFGHH RSCAN0.GTSTCFG.UINT8[HH] +#define RSCAN0GTSTCTR RSCAN0.GTSTCTR.UINT32 +#define RSCAN0GTSTCTRL RSCAN0.GTSTCTR.UINT16[L] +#define RSCAN0GTSTCTRLL RSCAN0.GTSTCTR.UINT8[LL] +#define RSCAN0GTSTCTRLH RSCAN0.GTSTCTR.UINT8[LH] +#define RSCAN0GTSTCTRH RSCAN0.GTSTCTR.UINT16[H] +#define RSCAN0GTSTCTRHL RSCAN0.GTSTCTR.UINT8[HL] +#define RSCAN0GTSTCTRHH RSCAN0.GTSTCTR.UINT8[HH] +#define RSCAN0GLOCKK RSCAN0.GLOCKK.UINT32 +#define RSCAN0GLOCKKL RSCAN0.GLOCKK.UINT16[L] +#define RSCAN0GLOCKKH RSCAN0.GLOCKK.UINT16[H] +#define RSCAN0GAFLID0 RSCAN0.GAFLID0.UINT32 +#define RSCAN0GAFLID0L RSCAN0.GAFLID0.UINT16[L] +#define RSCAN0GAFLID0LL RSCAN0.GAFLID0.UINT8[LL] +#define RSCAN0GAFLID0LH RSCAN0.GAFLID0.UINT8[LH] +#define RSCAN0GAFLID0H RSCAN0.GAFLID0.UINT16[H] +#define RSCAN0GAFLID0HL RSCAN0.GAFLID0.UINT8[HL] +#define RSCAN0GAFLID0HH RSCAN0.GAFLID0.UINT8[HH] +#define RSCAN0GAFLM0 RSCAN0.GAFLM0.UINT32 +#define RSCAN0GAFLM0L RSCAN0.GAFLM0.UINT16[L] +#define RSCAN0GAFLM0LL RSCAN0.GAFLM0.UINT8[LL] +#define RSCAN0GAFLM0LH RSCAN0.GAFLM0.UINT8[LH] +#define RSCAN0GAFLM0H RSCAN0.GAFLM0.UINT16[H] +#define RSCAN0GAFLM0HL RSCAN0.GAFLM0.UINT8[HL] +#define RSCAN0GAFLM0HH RSCAN0.GAFLM0.UINT8[HH] +#define RSCAN0GAFLP00 RSCAN0.GAFLP00.UINT32 +#define RSCAN0GAFLP00L RSCAN0.GAFLP00.UINT16[L] +#define RSCAN0GAFLP00LL RSCAN0.GAFLP00.UINT8[LL] +#define RSCAN0GAFLP00LH RSCAN0.GAFLP00.UINT8[LH] +#define RSCAN0GAFLP00H RSCAN0.GAFLP00.UINT16[H] +#define RSCAN0GAFLP00HL RSCAN0.GAFLP00.UINT8[HL] +#define RSCAN0GAFLP00HH RSCAN0.GAFLP00.UINT8[HH] +#define RSCAN0GAFLP10 RSCAN0.GAFLP10.UINT32 +#define RSCAN0GAFLP10L RSCAN0.GAFLP10.UINT16[L] +#define RSCAN0GAFLP10LL RSCAN0.GAFLP10.UINT8[LL] +#define RSCAN0GAFLP10LH RSCAN0.GAFLP10.UINT8[LH] +#define RSCAN0GAFLP10H RSCAN0.GAFLP10.UINT16[H] +#define RSCAN0GAFLP10HL RSCAN0.GAFLP10.UINT8[HL] +#define RSCAN0GAFLP10HH RSCAN0.GAFLP10.UINT8[HH] +#define RSCAN0GAFLID1 RSCAN0.GAFLID1.UINT32 +#define RSCAN0GAFLID1L RSCAN0.GAFLID1.UINT16[L] +#define RSCAN0GAFLID1LL RSCAN0.GAFLID1.UINT8[LL] +#define RSCAN0GAFLID1LH RSCAN0.GAFLID1.UINT8[LH] +#define RSCAN0GAFLID1H RSCAN0.GAFLID1.UINT16[H] +#define RSCAN0GAFLID1HL RSCAN0.GAFLID1.UINT8[HL] +#define RSCAN0GAFLID1HH RSCAN0.GAFLID1.UINT8[HH] +#define RSCAN0GAFLM1 RSCAN0.GAFLM1.UINT32 +#define RSCAN0GAFLM1L RSCAN0.GAFLM1.UINT16[L] +#define RSCAN0GAFLM1LL RSCAN0.GAFLM1.UINT8[LL] +#define RSCAN0GAFLM1LH RSCAN0.GAFLM1.UINT8[LH] +#define RSCAN0GAFLM1H RSCAN0.GAFLM1.UINT16[H] +#define RSCAN0GAFLM1HL RSCAN0.GAFLM1.UINT8[HL] +#define RSCAN0GAFLM1HH RSCAN0.GAFLM1.UINT8[HH] +#define RSCAN0GAFLP01 RSCAN0.GAFLP01.UINT32 +#define RSCAN0GAFLP01L RSCAN0.GAFLP01.UINT16[L] +#define RSCAN0GAFLP01LL RSCAN0.GAFLP01.UINT8[LL] +#define RSCAN0GAFLP01LH RSCAN0.GAFLP01.UINT8[LH] +#define RSCAN0GAFLP01H RSCAN0.GAFLP01.UINT16[H] +#define RSCAN0GAFLP01HL RSCAN0.GAFLP01.UINT8[HL] +#define RSCAN0GAFLP01HH RSCAN0.GAFLP01.UINT8[HH] +#define RSCAN0GAFLP11 RSCAN0.GAFLP11.UINT32 +#define RSCAN0GAFLP11L RSCAN0.GAFLP11.UINT16[L] +#define RSCAN0GAFLP11LL RSCAN0.GAFLP11.UINT8[LL] +#define RSCAN0GAFLP11LH RSCAN0.GAFLP11.UINT8[LH] +#define RSCAN0GAFLP11H RSCAN0.GAFLP11.UINT16[H] +#define RSCAN0GAFLP11HL RSCAN0.GAFLP11.UINT8[HL] +#define RSCAN0GAFLP11HH RSCAN0.GAFLP11.UINT8[HH] +#define RSCAN0GAFLID2 RSCAN0.GAFLID2.UINT32 +#define RSCAN0GAFLID2L RSCAN0.GAFLID2.UINT16[L] +#define RSCAN0GAFLID2LL RSCAN0.GAFLID2.UINT8[LL] +#define RSCAN0GAFLID2LH RSCAN0.GAFLID2.UINT8[LH] +#define RSCAN0GAFLID2H RSCAN0.GAFLID2.UINT16[H] +#define RSCAN0GAFLID2HL RSCAN0.GAFLID2.UINT8[HL] +#define RSCAN0GAFLID2HH RSCAN0.GAFLID2.UINT8[HH] +#define RSCAN0GAFLM2 RSCAN0.GAFLM2.UINT32 +#define RSCAN0GAFLM2L RSCAN0.GAFLM2.UINT16[L] +#define RSCAN0GAFLM2LL RSCAN0.GAFLM2.UINT8[LL] +#define RSCAN0GAFLM2LH RSCAN0.GAFLM2.UINT8[LH] +#define RSCAN0GAFLM2H RSCAN0.GAFLM2.UINT16[H] +#define RSCAN0GAFLM2HL RSCAN0.GAFLM2.UINT8[HL] +#define RSCAN0GAFLM2HH RSCAN0.GAFLM2.UINT8[HH] +#define RSCAN0GAFLP02 RSCAN0.GAFLP02.UINT32 +#define RSCAN0GAFLP02L RSCAN0.GAFLP02.UINT16[L] +#define RSCAN0GAFLP02LL RSCAN0.GAFLP02.UINT8[LL] +#define RSCAN0GAFLP02LH RSCAN0.GAFLP02.UINT8[LH] +#define RSCAN0GAFLP02H RSCAN0.GAFLP02.UINT16[H] +#define RSCAN0GAFLP02HL RSCAN0.GAFLP02.UINT8[HL] +#define RSCAN0GAFLP02HH RSCAN0.GAFLP02.UINT8[HH] +#define RSCAN0GAFLP12 RSCAN0.GAFLP12.UINT32 +#define RSCAN0GAFLP12L RSCAN0.GAFLP12.UINT16[L] +#define RSCAN0GAFLP12LL RSCAN0.GAFLP12.UINT8[LL] +#define RSCAN0GAFLP12LH RSCAN0.GAFLP12.UINT8[LH] +#define RSCAN0GAFLP12H RSCAN0.GAFLP12.UINT16[H] +#define RSCAN0GAFLP12HL RSCAN0.GAFLP12.UINT8[HL] +#define RSCAN0GAFLP12HH RSCAN0.GAFLP12.UINT8[HH] +#define RSCAN0GAFLID3 RSCAN0.GAFLID3.UINT32 +#define RSCAN0GAFLID3L RSCAN0.GAFLID3.UINT16[L] +#define RSCAN0GAFLID3LL RSCAN0.GAFLID3.UINT8[LL] +#define RSCAN0GAFLID3LH RSCAN0.GAFLID3.UINT8[LH] +#define RSCAN0GAFLID3H RSCAN0.GAFLID3.UINT16[H] +#define RSCAN0GAFLID3HL RSCAN0.GAFLID3.UINT8[HL] +#define RSCAN0GAFLID3HH RSCAN0.GAFLID3.UINT8[HH] +#define RSCAN0GAFLM3 RSCAN0.GAFLM3.UINT32 +#define RSCAN0GAFLM3L RSCAN0.GAFLM3.UINT16[L] +#define RSCAN0GAFLM3LL RSCAN0.GAFLM3.UINT8[LL] +#define RSCAN0GAFLM3LH RSCAN0.GAFLM3.UINT8[LH] +#define RSCAN0GAFLM3H RSCAN0.GAFLM3.UINT16[H] +#define RSCAN0GAFLM3HL RSCAN0.GAFLM3.UINT8[HL] +#define RSCAN0GAFLM3HH RSCAN0.GAFLM3.UINT8[HH] +#define RSCAN0GAFLP03 RSCAN0.GAFLP03.UINT32 +#define RSCAN0GAFLP03L RSCAN0.GAFLP03.UINT16[L] +#define RSCAN0GAFLP03LL RSCAN0.GAFLP03.UINT8[LL] +#define RSCAN0GAFLP03LH RSCAN0.GAFLP03.UINT8[LH] +#define RSCAN0GAFLP03H RSCAN0.GAFLP03.UINT16[H] +#define RSCAN0GAFLP03HL RSCAN0.GAFLP03.UINT8[HL] +#define RSCAN0GAFLP03HH RSCAN0.GAFLP03.UINT8[HH] +#define RSCAN0GAFLP13 RSCAN0.GAFLP13.UINT32 +#define RSCAN0GAFLP13L RSCAN0.GAFLP13.UINT16[L] +#define RSCAN0GAFLP13LL RSCAN0.GAFLP13.UINT8[LL] +#define RSCAN0GAFLP13LH RSCAN0.GAFLP13.UINT8[LH] +#define RSCAN0GAFLP13H RSCAN0.GAFLP13.UINT16[H] +#define RSCAN0GAFLP13HL RSCAN0.GAFLP13.UINT8[HL] +#define RSCAN0GAFLP13HH RSCAN0.GAFLP13.UINT8[HH] +#define RSCAN0GAFLID4 RSCAN0.GAFLID4.UINT32 +#define RSCAN0GAFLID4L RSCAN0.GAFLID4.UINT16[L] +#define RSCAN0GAFLID4LL RSCAN0.GAFLID4.UINT8[LL] +#define RSCAN0GAFLID4LH RSCAN0.GAFLID4.UINT8[LH] +#define RSCAN0GAFLID4H RSCAN0.GAFLID4.UINT16[H] +#define RSCAN0GAFLID4HL RSCAN0.GAFLID4.UINT8[HL] +#define RSCAN0GAFLID4HH RSCAN0.GAFLID4.UINT8[HH] +#define RSCAN0GAFLM4 RSCAN0.GAFLM4.UINT32 +#define RSCAN0GAFLM4L RSCAN0.GAFLM4.UINT16[L] +#define RSCAN0GAFLM4LL RSCAN0.GAFLM4.UINT8[LL] +#define RSCAN0GAFLM4LH RSCAN0.GAFLM4.UINT8[LH] +#define RSCAN0GAFLM4H RSCAN0.GAFLM4.UINT16[H] +#define RSCAN0GAFLM4HL RSCAN0.GAFLM4.UINT8[HL] +#define RSCAN0GAFLM4HH RSCAN0.GAFLM4.UINT8[HH] +#define RSCAN0GAFLP04 RSCAN0.GAFLP04.UINT32 +#define RSCAN0GAFLP04L RSCAN0.GAFLP04.UINT16[L] +#define RSCAN0GAFLP04LL RSCAN0.GAFLP04.UINT8[LL] +#define RSCAN0GAFLP04LH RSCAN0.GAFLP04.UINT8[LH] +#define RSCAN0GAFLP04H RSCAN0.GAFLP04.UINT16[H] +#define RSCAN0GAFLP04HL RSCAN0.GAFLP04.UINT8[HL] +#define RSCAN0GAFLP04HH RSCAN0.GAFLP04.UINT8[HH] +#define RSCAN0GAFLP14 RSCAN0.GAFLP14.UINT32 +#define RSCAN0GAFLP14L RSCAN0.GAFLP14.UINT16[L] +#define RSCAN0GAFLP14LL RSCAN0.GAFLP14.UINT8[LL] +#define RSCAN0GAFLP14LH RSCAN0.GAFLP14.UINT8[LH] +#define RSCAN0GAFLP14H RSCAN0.GAFLP14.UINT16[H] +#define RSCAN0GAFLP14HL RSCAN0.GAFLP14.UINT8[HL] +#define RSCAN0GAFLP14HH RSCAN0.GAFLP14.UINT8[HH] +#define RSCAN0GAFLID5 RSCAN0.GAFLID5.UINT32 +#define RSCAN0GAFLID5L RSCAN0.GAFLID5.UINT16[L] +#define RSCAN0GAFLID5LL RSCAN0.GAFLID5.UINT8[LL] +#define RSCAN0GAFLID5LH RSCAN0.GAFLID5.UINT8[LH] +#define RSCAN0GAFLID5H RSCAN0.GAFLID5.UINT16[H] +#define RSCAN0GAFLID5HL RSCAN0.GAFLID5.UINT8[HL] +#define RSCAN0GAFLID5HH RSCAN0.GAFLID5.UINT8[HH] +#define RSCAN0GAFLM5 RSCAN0.GAFLM5.UINT32 +#define RSCAN0GAFLM5L RSCAN0.GAFLM5.UINT16[L] +#define RSCAN0GAFLM5LL RSCAN0.GAFLM5.UINT8[LL] +#define RSCAN0GAFLM5LH RSCAN0.GAFLM5.UINT8[LH] +#define RSCAN0GAFLM5H RSCAN0.GAFLM5.UINT16[H] +#define RSCAN0GAFLM5HL RSCAN0.GAFLM5.UINT8[HL] +#define RSCAN0GAFLM5HH RSCAN0.GAFLM5.UINT8[HH] +#define RSCAN0GAFLP05 RSCAN0.GAFLP05.UINT32 +#define RSCAN0GAFLP05L RSCAN0.GAFLP05.UINT16[L] +#define RSCAN0GAFLP05LL RSCAN0.GAFLP05.UINT8[LL] +#define RSCAN0GAFLP05LH RSCAN0.GAFLP05.UINT8[LH] +#define RSCAN0GAFLP05H RSCAN0.GAFLP05.UINT16[H] +#define RSCAN0GAFLP05HL RSCAN0.GAFLP05.UINT8[HL] +#define RSCAN0GAFLP05HH RSCAN0.GAFLP05.UINT8[HH] +#define RSCAN0GAFLP15 RSCAN0.GAFLP15.UINT32 +#define RSCAN0GAFLP15L RSCAN0.GAFLP15.UINT16[L] +#define RSCAN0GAFLP15LL RSCAN0.GAFLP15.UINT8[LL] +#define RSCAN0GAFLP15LH RSCAN0.GAFLP15.UINT8[LH] +#define RSCAN0GAFLP15H RSCAN0.GAFLP15.UINT16[H] +#define RSCAN0GAFLP15HL RSCAN0.GAFLP15.UINT8[HL] +#define RSCAN0GAFLP15HH RSCAN0.GAFLP15.UINT8[HH] +#define RSCAN0GAFLID6 RSCAN0.GAFLID6.UINT32 +#define RSCAN0GAFLID6L RSCAN0.GAFLID6.UINT16[L] +#define RSCAN0GAFLID6LL RSCAN0.GAFLID6.UINT8[LL] +#define RSCAN0GAFLID6LH RSCAN0.GAFLID6.UINT8[LH] +#define RSCAN0GAFLID6H RSCAN0.GAFLID6.UINT16[H] +#define RSCAN0GAFLID6HL RSCAN0.GAFLID6.UINT8[HL] +#define RSCAN0GAFLID6HH RSCAN0.GAFLID6.UINT8[HH] +#define RSCAN0GAFLM6 RSCAN0.GAFLM6.UINT32 +#define RSCAN0GAFLM6L RSCAN0.GAFLM6.UINT16[L] +#define RSCAN0GAFLM6LL RSCAN0.GAFLM6.UINT8[LL] +#define RSCAN0GAFLM6LH RSCAN0.GAFLM6.UINT8[LH] +#define RSCAN0GAFLM6H RSCAN0.GAFLM6.UINT16[H] +#define RSCAN0GAFLM6HL RSCAN0.GAFLM6.UINT8[HL] +#define RSCAN0GAFLM6HH RSCAN0.GAFLM6.UINT8[HH] +#define RSCAN0GAFLP06 RSCAN0.GAFLP06.UINT32 +#define RSCAN0GAFLP06L RSCAN0.GAFLP06.UINT16[L] +#define RSCAN0GAFLP06LL RSCAN0.GAFLP06.UINT8[LL] +#define RSCAN0GAFLP06LH RSCAN0.GAFLP06.UINT8[LH] +#define RSCAN0GAFLP06H RSCAN0.GAFLP06.UINT16[H] +#define RSCAN0GAFLP06HL RSCAN0.GAFLP06.UINT8[HL] +#define RSCAN0GAFLP06HH RSCAN0.GAFLP06.UINT8[HH] +#define RSCAN0GAFLP16 RSCAN0.GAFLP16.UINT32 +#define RSCAN0GAFLP16L RSCAN0.GAFLP16.UINT16[L] +#define RSCAN0GAFLP16LL RSCAN0.GAFLP16.UINT8[LL] +#define RSCAN0GAFLP16LH RSCAN0.GAFLP16.UINT8[LH] +#define RSCAN0GAFLP16H RSCAN0.GAFLP16.UINT16[H] +#define RSCAN0GAFLP16HL RSCAN0.GAFLP16.UINT8[HL] +#define RSCAN0GAFLP16HH RSCAN0.GAFLP16.UINT8[HH] +#define RSCAN0GAFLID7 RSCAN0.GAFLID7.UINT32 +#define RSCAN0GAFLID7L RSCAN0.GAFLID7.UINT16[L] +#define RSCAN0GAFLID7LL RSCAN0.GAFLID7.UINT8[LL] +#define RSCAN0GAFLID7LH RSCAN0.GAFLID7.UINT8[LH] +#define RSCAN0GAFLID7H RSCAN0.GAFLID7.UINT16[H] +#define RSCAN0GAFLID7HL RSCAN0.GAFLID7.UINT8[HL] +#define RSCAN0GAFLID7HH RSCAN0.GAFLID7.UINT8[HH] +#define RSCAN0GAFLM7 RSCAN0.GAFLM7.UINT32 +#define RSCAN0GAFLM7L RSCAN0.GAFLM7.UINT16[L] +#define RSCAN0GAFLM7LL RSCAN0.GAFLM7.UINT8[LL] +#define RSCAN0GAFLM7LH RSCAN0.GAFLM7.UINT8[LH] +#define RSCAN0GAFLM7H RSCAN0.GAFLM7.UINT16[H] +#define RSCAN0GAFLM7HL RSCAN0.GAFLM7.UINT8[HL] +#define RSCAN0GAFLM7HH RSCAN0.GAFLM7.UINT8[HH] +#define RSCAN0GAFLP07 RSCAN0.GAFLP07.UINT32 +#define RSCAN0GAFLP07L RSCAN0.GAFLP07.UINT16[L] +#define RSCAN0GAFLP07LL RSCAN0.GAFLP07.UINT8[LL] +#define RSCAN0GAFLP07LH RSCAN0.GAFLP07.UINT8[LH] +#define RSCAN0GAFLP07H RSCAN0.GAFLP07.UINT16[H] +#define RSCAN0GAFLP07HL RSCAN0.GAFLP07.UINT8[HL] +#define RSCAN0GAFLP07HH RSCAN0.GAFLP07.UINT8[HH] +#define RSCAN0GAFLP17 RSCAN0.GAFLP17.UINT32 +#define RSCAN0GAFLP17L RSCAN0.GAFLP17.UINT16[L] +#define RSCAN0GAFLP17LL RSCAN0.GAFLP17.UINT8[LL] +#define RSCAN0GAFLP17LH RSCAN0.GAFLP17.UINT8[LH] +#define RSCAN0GAFLP17H RSCAN0.GAFLP17.UINT16[H] +#define RSCAN0GAFLP17HL RSCAN0.GAFLP17.UINT8[HL] +#define RSCAN0GAFLP17HH RSCAN0.GAFLP17.UINT8[HH] +#define RSCAN0GAFLID8 RSCAN0.GAFLID8.UINT32 +#define RSCAN0GAFLID8L RSCAN0.GAFLID8.UINT16[L] +#define RSCAN0GAFLID8LL RSCAN0.GAFLID8.UINT8[LL] +#define RSCAN0GAFLID8LH RSCAN0.GAFLID8.UINT8[LH] +#define RSCAN0GAFLID8H RSCAN0.GAFLID8.UINT16[H] +#define RSCAN0GAFLID8HL RSCAN0.GAFLID8.UINT8[HL] +#define RSCAN0GAFLID8HH RSCAN0.GAFLID8.UINT8[HH] +#define RSCAN0GAFLM8 RSCAN0.GAFLM8.UINT32 +#define RSCAN0GAFLM8L RSCAN0.GAFLM8.UINT16[L] +#define RSCAN0GAFLM8LL RSCAN0.GAFLM8.UINT8[LL] +#define RSCAN0GAFLM8LH RSCAN0.GAFLM8.UINT8[LH] +#define RSCAN0GAFLM8H RSCAN0.GAFLM8.UINT16[H] +#define RSCAN0GAFLM8HL RSCAN0.GAFLM8.UINT8[HL] +#define RSCAN0GAFLM8HH RSCAN0.GAFLM8.UINT8[HH] +#define RSCAN0GAFLP08 RSCAN0.GAFLP08.UINT32 +#define RSCAN0GAFLP08L RSCAN0.GAFLP08.UINT16[L] +#define RSCAN0GAFLP08LL RSCAN0.GAFLP08.UINT8[LL] +#define RSCAN0GAFLP08LH RSCAN0.GAFLP08.UINT8[LH] +#define RSCAN0GAFLP08H RSCAN0.GAFLP08.UINT16[H] +#define RSCAN0GAFLP08HL RSCAN0.GAFLP08.UINT8[HL] +#define RSCAN0GAFLP08HH RSCAN0.GAFLP08.UINT8[HH] +#define RSCAN0GAFLP18 RSCAN0.GAFLP18.UINT32 +#define RSCAN0GAFLP18L RSCAN0.GAFLP18.UINT16[L] +#define RSCAN0GAFLP18LL RSCAN0.GAFLP18.UINT8[LL] +#define RSCAN0GAFLP18LH RSCAN0.GAFLP18.UINT8[LH] +#define RSCAN0GAFLP18H RSCAN0.GAFLP18.UINT16[H] +#define RSCAN0GAFLP18HL RSCAN0.GAFLP18.UINT8[HL] +#define RSCAN0GAFLP18HH RSCAN0.GAFLP18.UINT8[HH] +#define RSCAN0GAFLID9 RSCAN0.GAFLID9.UINT32 +#define RSCAN0GAFLID9L RSCAN0.GAFLID9.UINT16[L] +#define RSCAN0GAFLID9LL RSCAN0.GAFLID9.UINT8[LL] +#define RSCAN0GAFLID9LH RSCAN0.GAFLID9.UINT8[LH] +#define RSCAN0GAFLID9H RSCAN0.GAFLID9.UINT16[H] +#define RSCAN0GAFLID9HL RSCAN0.GAFLID9.UINT8[HL] +#define RSCAN0GAFLID9HH RSCAN0.GAFLID9.UINT8[HH] +#define RSCAN0GAFLM9 RSCAN0.GAFLM9.UINT32 +#define RSCAN0GAFLM9L RSCAN0.GAFLM9.UINT16[L] +#define RSCAN0GAFLM9LL RSCAN0.GAFLM9.UINT8[LL] +#define RSCAN0GAFLM9LH RSCAN0.GAFLM9.UINT8[LH] +#define RSCAN0GAFLM9H RSCAN0.GAFLM9.UINT16[H] +#define RSCAN0GAFLM9HL RSCAN0.GAFLM9.UINT8[HL] +#define RSCAN0GAFLM9HH RSCAN0.GAFLM9.UINT8[HH] +#define RSCAN0GAFLP09 RSCAN0.GAFLP09.UINT32 +#define RSCAN0GAFLP09L RSCAN0.GAFLP09.UINT16[L] +#define RSCAN0GAFLP09LL RSCAN0.GAFLP09.UINT8[LL] +#define RSCAN0GAFLP09LH RSCAN0.GAFLP09.UINT8[LH] +#define RSCAN0GAFLP09H RSCAN0.GAFLP09.UINT16[H] +#define RSCAN0GAFLP09HL RSCAN0.GAFLP09.UINT8[HL] +#define RSCAN0GAFLP09HH RSCAN0.GAFLP09.UINT8[HH] +#define RSCAN0GAFLP19 RSCAN0.GAFLP19.UINT32 +#define RSCAN0GAFLP19L RSCAN0.GAFLP19.UINT16[L] +#define RSCAN0GAFLP19LL RSCAN0.GAFLP19.UINT8[LL] +#define RSCAN0GAFLP19LH RSCAN0.GAFLP19.UINT8[LH] +#define RSCAN0GAFLP19H RSCAN0.GAFLP19.UINT16[H] +#define RSCAN0GAFLP19HL RSCAN0.GAFLP19.UINT8[HL] +#define RSCAN0GAFLP19HH RSCAN0.GAFLP19.UINT8[HH] +#define RSCAN0GAFLID10 RSCAN0.GAFLID10.UINT32 +#define RSCAN0GAFLID10L RSCAN0.GAFLID10.UINT16[L] +#define RSCAN0GAFLID10LL RSCAN0.GAFLID10.UINT8[LL] +#define RSCAN0GAFLID10LH RSCAN0.GAFLID10.UINT8[LH] +#define RSCAN0GAFLID10H RSCAN0.GAFLID10.UINT16[H] +#define RSCAN0GAFLID10HL RSCAN0.GAFLID10.UINT8[HL] +#define RSCAN0GAFLID10HH RSCAN0.GAFLID10.UINT8[HH] +#define RSCAN0GAFLM10 RSCAN0.GAFLM10.UINT32 +#define RSCAN0GAFLM10L RSCAN0.GAFLM10.UINT16[L] +#define RSCAN0GAFLM10LL RSCAN0.GAFLM10.UINT8[LL] +#define RSCAN0GAFLM10LH RSCAN0.GAFLM10.UINT8[LH] +#define RSCAN0GAFLM10H RSCAN0.GAFLM10.UINT16[H] +#define RSCAN0GAFLM10HL RSCAN0.GAFLM10.UINT8[HL] +#define RSCAN0GAFLM10HH RSCAN0.GAFLM10.UINT8[HH] +#define RSCAN0GAFLP010 RSCAN0.GAFLP010.UINT32 +#define RSCAN0GAFLP010L RSCAN0.GAFLP010.UINT16[L] +#define RSCAN0GAFLP010LL RSCAN0.GAFLP010.UINT8[LL] +#define RSCAN0GAFLP010LH RSCAN0.GAFLP010.UINT8[LH] +#define RSCAN0GAFLP010H RSCAN0.GAFLP010.UINT16[H] +#define RSCAN0GAFLP010HL RSCAN0.GAFLP010.UINT8[HL] +#define RSCAN0GAFLP010HH RSCAN0.GAFLP010.UINT8[HH] +#define RSCAN0GAFLP110 RSCAN0.GAFLP110.UINT32 +#define RSCAN0GAFLP110L RSCAN0.GAFLP110.UINT16[L] +#define RSCAN0GAFLP110LL RSCAN0.GAFLP110.UINT8[LL] +#define RSCAN0GAFLP110LH RSCAN0.GAFLP110.UINT8[LH] +#define RSCAN0GAFLP110H RSCAN0.GAFLP110.UINT16[H] +#define RSCAN0GAFLP110HL RSCAN0.GAFLP110.UINT8[HL] +#define RSCAN0GAFLP110HH RSCAN0.GAFLP110.UINT8[HH] +#define RSCAN0GAFLID11 RSCAN0.GAFLID11.UINT32 +#define RSCAN0GAFLID11L RSCAN0.GAFLID11.UINT16[L] +#define RSCAN0GAFLID11LL RSCAN0.GAFLID11.UINT8[LL] +#define RSCAN0GAFLID11LH RSCAN0.GAFLID11.UINT8[LH] +#define RSCAN0GAFLID11H RSCAN0.GAFLID11.UINT16[H] +#define RSCAN0GAFLID11HL RSCAN0.GAFLID11.UINT8[HL] +#define RSCAN0GAFLID11HH RSCAN0.GAFLID11.UINT8[HH] +#define RSCAN0GAFLM11 RSCAN0.GAFLM11.UINT32 +#define RSCAN0GAFLM11L RSCAN0.GAFLM11.UINT16[L] +#define RSCAN0GAFLM11LL RSCAN0.GAFLM11.UINT8[LL] +#define RSCAN0GAFLM11LH RSCAN0.GAFLM11.UINT8[LH] +#define RSCAN0GAFLM11H RSCAN0.GAFLM11.UINT16[H] +#define RSCAN0GAFLM11HL RSCAN0.GAFLM11.UINT8[HL] +#define RSCAN0GAFLM11HH RSCAN0.GAFLM11.UINT8[HH] +#define RSCAN0GAFLP011 RSCAN0.GAFLP011.UINT32 +#define RSCAN0GAFLP011L RSCAN0.GAFLP011.UINT16[L] +#define RSCAN0GAFLP011LL RSCAN0.GAFLP011.UINT8[LL] +#define RSCAN0GAFLP011LH RSCAN0.GAFLP011.UINT8[LH] +#define RSCAN0GAFLP011H RSCAN0.GAFLP011.UINT16[H] +#define RSCAN0GAFLP011HL RSCAN0.GAFLP011.UINT8[HL] +#define RSCAN0GAFLP011HH RSCAN0.GAFLP011.UINT8[HH] +#define RSCAN0GAFLP111 RSCAN0.GAFLP111.UINT32 +#define RSCAN0GAFLP111L RSCAN0.GAFLP111.UINT16[L] +#define RSCAN0GAFLP111LL RSCAN0.GAFLP111.UINT8[LL] +#define RSCAN0GAFLP111LH RSCAN0.GAFLP111.UINT8[LH] +#define RSCAN0GAFLP111H RSCAN0.GAFLP111.UINT16[H] +#define RSCAN0GAFLP111HL RSCAN0.GAFLP111.UINT8[HL] +#define RSCAN0GAFLP111HH RSCAN0.GAFLP111.UINT8[HH] +#define RSCAN0GAFLID12 RSCAN0.GAFLID12.UINT32 +#define RSCAN0GAFLID12L RSCAN0.GAFLID12.UINT16[L] +#define RSCAN0GAFLID12LL RSCAN0.GAFLID12.UINT8[LL] +#define RSCAN0GAFLID12LH RSCAN0.GAFLID12.UINT8[LH] +#define RSCAN0GAFLID12H RSCAN0.GAFLID12.UINT16[H] +#define RSCAN0GAFLID12HL RSCAN0.GAFLID12.UINT8[HL] +#define RSCAN0GAFLID12HH RSCAN0.GAFLID12.UINT8[HH] +#define RSCAN0GAFLM12 RSCAN0.GAFLM12.UINT32 +#define RSCAN0GAFLM12L RSCAN0.GAFLM12.UINT16[L] +#define RSCAN0GAFLM12LL RSCAN0.GAFLM12.UINT8[LL] +#define RSCAN0GAFLM12LH RSCAN0.GAFLM12.UINT8[LH] +#define RSCAN0GAFLM12H RSCAN0.GAFLM12.UINT16[H] +#define RSCAN0GAFLM12HL RSCAN0.GAFLM12.UINT8[HL] +#define RSCAN0GAFLM12HH RSCAN0.GAFLM12.UINT8[HH] +#define RSCAN0GAFLP012 RSCAN0.GAFLP012.UINT32 +#define RSCAN0GAFLP012L RSCAN0.GAFLP012.UINT16[L] +#define RSCAN0GAFLP012LL RSCAN0.GAFLP012.UINT8[LL] +#define RSCAN0GAFLP012LH RSCAN0.GAFLP012.UINT8[LH] +#define RSCAN0GAFLP012H RSCAN0.GAFLP012.UINT16[H] +#define RSCAN0GAFLP012HL RSCAN0.GAFLP012.UINT8[HL] +#define RSCAN0GAFLP012HH RSCAN0.GAFLP012.UINT8[HH] +#define RSCAN0GAFLP112 RSCAN0.GAFLP112.UINT32 +#define RSCAN0GAFLP112L RSCAN0.GAFLP112.UINT16[L] +#define RSCAN0GAFLP112LL RSCAN0.GAFLP112.UINT8[LL] +#define RSCAN0GAFLP112LH RSCAN0.GAFLP112.UINT8[LH] +#define RSCAN0GAFLP112H RSCAN0.GAFLP112.UINT16[H] +#define RSCAN0GAFLP112HL RSCAN0.GAFLP112.UINT8[HL] +#define RSCAN0GAFLP112HH RSCAN0.GAFLP112.UINT8[HH] +#define RSCAN0GAFLID13 RSCAN0.GAFLID13.UINT32 +#define RSCAN0GAFLID13L RSCAN0.GAFLID13.UINT16[L] +#define RSCAN0GAFLID13LL RSCAN0.GAFLID13.UINT8[LL] +#define RSCAN0GAFLID13LH RSCAN0.GAFLID13.UINT8[LH] +#define RSCAN0GAFLID13H RSCAN0.GAFLID13.UINT16[H] +#define RSCAN0GAFLID13HL RSCAN0.GAFLID13.UINT8[HL] +#define RSCAN0GAFLID13HH RSCAN0.GAFLID13.UINT8[HH] +#define RSCAN0GAFLM13 RSCAN0.GAFLM13.UINT32 +#define RSCAN0GAFLM13L RSCAN0.GAFLM13.UINT16[L] +#define RSCAN0GAFLM13LL RSCAN0.GAFLM13.UINT8[LL] +#define RSCAN0GAFLM13LH RSCAN0.GAFLM13.UINT8[LH] +#define RSCAN0GAFLM13H RSCAN0.GAFLM13.UINT16[H] +#define RSCAN0GAFLM13HL RSCAN0.GAFLM13.UINT8[HL] +#define RSCAN0GAFLM13HH RSCAN0.GAFLM13.UINT8[HH] +#define RSCAN0GAFLP013 RSCAN0.GAFLP013.UINT32 +#define RSCAN0GAFLP013L RSCAN0.GAFLP013.UINT16[L] +#define RSCAN0GAFLP013LL RSCAN0.GAFLP013.UINT8[LL] +#define RSCAN0GAFLP013LH RSCAN0.GAFLP013.UINT8[LH] +#define RSCAN0GAFLP013H RSCAN0.GAFLP013.UINT16[H] +#define RSCAN0GAFLP013HL RSCAN0.GAFLP013.UINT8[HL] +#define RSCAN0GAFLP013HH RSCAN0.GAFLP013.UINT8[HH] +#define RSCAN0GAFLP113 RSCAN0.GAFLP113.UINT32 +#define RSCAN0GAFLP113L RSCAN0.GAFLP113.UINT16[L] +#define RSCAN0GAFLP113LL RSCAN0.GAFLP113.UINT8[LL] +#define RSCAN0GAFLP113LH RSCAN0.GAFLP113.UINT8[LH] +#define RSCAN0GAFLP113H RSCAN0.GAFLP113.UINT16[H] +#define RSCAN0GAFLP113HL RSCAN0.GAFLP113.UINT8[HL] +#define RSCAN0GAFLP113HH RSCAN0.GAFLP113.UINT8[HH] +#define RSCAN0GAFLID14 RSCAN0.GAFLID14.UINT32 +#define RSCAN0GAFLID14L RSCAN0.GAFLID14.UINT16[L] +#define RSCAN0GAFLID14LL RSCAN0.GAFLID14.UINT8[LL] +#define RSCAN0GAFLID14LH RSCAN0.GAFLID14.UINT8[LH] +#define RSCAN0GAFLID14H RSCAN0.GAFLID14.UINT16[H] +#define RSCAN0GAFLID14HL RSCAN0.GAFLID14.UINT8[HL] +#define RSCAN0GAFLID14HH RSCAN0.GAFLID14.UINT8[HH] +#define RSCAN0GAFLM14 RSCAN0.GAFLM14.UINT32 +#define RSCAN0GAFLM14L RSCAN0.GAFLM14.UINT16[L] +#define RSCAN0GAFLM14LL RSCAN0.GAFLM14.UINT8[LL] +#define RSCAN0GAFLM14LH RSCAN0.GAFLM14.UINT8[LH] +#define RSCAN0GAFLM14H RSCAN0.GAFLM14.UINT16[H] +#define RSCAN0GAFLM14HL RSCAN0.GAFLM14.UINT8[HL] +#define RSCAN0GAFLM14HH RSCAN0.GAFLM14.UINT8[HH] +#define RSCAN0GAFLP014 RSCAN0.GAFLP014.UINT32 +#define RSCAN0GAFLP014L RSCAN0.GAFLP014.UINT16[L] +#define RSCAN0GAFLP014LL RSCAN0.GAFLP014.UINT8[LL] +#define RSCAN0GAFLP014LH RSCAN0.GAFLP014.UINT8[LH] +#define RSCAN0GAFLP014H RSCAN0.GAFLP014.UINT16[H] +#define RSCAN0GAFLP014HL RSCAN0.GAFLP014.UINT8[HL] +#define RSCAN0GAFLP014HH RSCAN0.GAFLP014.UINT8[HH] +#define RSCAN0GAFLP114 RSCAN0.GAFLP114.UINT32 +#define RSCAN0GAFLP114L RSCAN0.GAFLP114.UINT16[L] +#define RSCAN0GAFLP114LL RSCAN0.GAFLP114.UINT8[LL] +#define RSCAN0GAFLP114LH RSCAN0.GAFLP114.UINT8[LH] +#define RSCAN0GAFLP114H RSCAN0.GAFLP114.UINT16[H] +#define RSCAN0GAFLP114HL RSCAN0.GAFLP114.UINT8[HL] +#define RSCAN0GAFLP114HH RSCAN0.GAFLP114.UINT8[HH] +#define RSCAN0GAFLID15 RSCAN0.GAFLID15.UINT32 +#define RSCAN0GAFLID15L RSCAN0.GAFLID15.UINT16[L] +#define RSCAN0GAFLID15LL RSCAN0.GAFLID15.UINT8[LL] +#define RSCAN0GAFLID15LH RSCAN0.GAFLID15.UINT8[LH] +#define RSCAN0GAFLID15H RSCAN0.GAFLID15.UINT16[H] +#define RSCAN0GAFLID15HL RSCAN0.GAFLID15.UINT8[HL] +#define RSCAN0GAFLID15HH RSCAN0.GAFLID15.UINT8[HH] +#define RSCAN0GAFLM15 RSCAN0.GAFLM15.UINT32 +#define RSCAN0GAFLM15L RSCAN0.GAFLM15.UINT16[L] +#define RSCAN0GAFLM15LL RSCAN0.GAFLM15.UINT8[LL] +#define RSCAN0GAFLM15LH RSCAN0.GAFLM15.UINT8[LH] +#define RSCAN0GAFLM15H RSCAN0.GAFLM15.UINT16[H] +#define RSCAN0GAFLM15HL RSCAN0.GAFLM15.UINT8[HL] +#define RSCAN0GAFLM15HH RSCAN0.GAFLM15.UINT8[HH] +#define RSCAN0GAFLP015 RSCAN0.GAFLP015.UINT32 +#define RSCAN0GAFLP015L RSCAN0.GAFLP015.UINT16[L] +#define RSCAN0GAFLP015LL RSCAN0.GAFLP015.UINT8[LL] +#define RSCAN0GAFLP015LH RSCAN0.GAFLP015.UINT8[LH] +#define RSCAN0GAFLP015H RSCAN0.GAFLP015.UINT16[H] +#define RSCAN0GAFLP015HL RSCAN0.GAFLP015.UINT8[HL] +#define RSCAN0GAFLP015HH RSCAN0.GAFLP015.UINT8[HH] +#define RSCAN0GAFLP115 RSCAN0.GAFLP115.UINT32 +#define RSCAN0GAFLP115L RSCAN0.GAFLP115.UINT16[L] +#define RSCAN0GAFLP115LL RSCAN0.GAFLP115.UINT8[LL] +#define RSCAN0GAFLP115LH RSCAN0.GAFLP115.UINT8[LH] +#define RSCAN0GAFLP115H RSCAN0.GAFLP115.UINT16[H] +#define RSCAN0GAFLP115HL RSCAN0.GAFLP115.UINT8[HL] +#define RSCAN0GAFLP115HH RSCAN0.GAFLP115.UINT8[HH] +#define RSCAN0RMID0 RSCAN0.RMID0.UINT32 +#define RSCAN0RMID0L RSCAN0.RMID0.UINT16[L] +#define RSCAN0RMID0LL RSCAN0.RMID0.UINT8[LL] +#define RSCAN0RMID0LH RSCAN0.RMID0.UINT8[LH] +#define RSCAN0RMID0H RSCAN0.RMID0.UINT16[H] +#define RSCAN0RMID0HL RSCAN0.RMID0.UINT8[HL] +#define RSCAN0RMID0HH RSCAN0.RMID0.UINT8[HH] +#define RSCAN0RMPTR0 RSCAN0.RMPTR0.UINT32 +#define RSCAN0RMPTR0L RSCAN0.RMPTR0.UINT16[L] +#define RSCAN0RMPTR0LL RSCAN0.RMPTR0.UINT8[LL] +#define RSCAN0RMPTR0LH RSCAN0.RMPTR0.UINT8[LH] +#define RSCAN0RMPTR0H RSCAN0.RMPTR0.UINT16[H] +#define RSCAN0RMPTR0HL RSCAN0.RMPTR0.UINT8[HL] +#define RSCAN0RMPTR0HH RSCAN0.RMPTR0.UINT8[HH] +#define RSCAN0RMDF00 RSCAN0.RMDF00.UINT32 +#define RSCAN0RMDF00L RSCAN0.RMDF00.UINT16[L] +#define RSCAN0RMDF00LL RSCAN0.RMDF00.UINT8[LL] +#define RSCAN0RMDF00LH RSCAN0.RMDF00.UINT8[LH] +#define RSCAN0RMDF00H RSCAN0.RMDF00.UINT16[H] +#define RSCAN0RMDF00HL RSCAN0.RMDF00.UINT8[HL] +#define RSCAN0RMDF00HH RSCAN0.RMDF00.UINT8[HH] +#define RSCAN0RMDF10 RSCAN0.RMDF10.UINT32 +#define RSCAN0RMDF10L RSCAN0.RMDF10.UINT16[L] +#define RSCAN0RMDF10LL RSCAN0.RMDF10.UINT8[LL] +#define RSCAN0RMDF10LH RSCAN0.RMDF10.UINT8[LH] +#define RSCAN0RMDF10H RSCAN0.RMDF10.UINT16[H] +#define RSCAN0RMDF10HL RSCAN0.RMDF10.UINT8[HL] +#define RSCAN0RMDF10HH RSCAN0.RMDF10.UINT8[HH] +#define RSCAN0RMID1 RSCAN0.RMID1.UINT32 +#define RSCAN0RMID1L RSCAN0.RMID1.UINT16[L] +#define RSCAN0RMID1LL RSCAN0.RMID1.UINT8[LL] +#define RSCAN0RMID1LH RSCAN0.RMID1.UINT8[LH] +#define RSCAN0RMID1H RSCAN0.RMID1.UINT16[H] +#define RSCAN0RMID1HL RSCAN0.RMID1.UINT8[HL] +#define RSCAN0RMID1HH RSCAN0.RMID1.UINT8[HH] +#define RSCAN0RMPTR1 RSCAN0.RMPTR1.UINT32 +#define RSCAN0RMPTR1L RSCAN0.RMPTR1.UINT16[L] +#define RSCAN0RMPTR1LL RSCAN0.RMPTR1.UINT8[LL] +#define RSCAN0RMPTR1LH RSCAN0.RMPTR1.UINT8[LH] +#define RSCAN0RMPTR1H RSCAN0.RMPTR1.UINT16[H] +#define RSCAN0RMPTR1HL RSCAN0.RMPTR1.UINT8[HL] +#define RSCAN0RMPTR1HH RSCAN0.RMPTR1.UINT8[HH] +#define RSCAN0RMDF01 RSCAN0.RMDF01.UINT32 +#define RSCAN0RMDF01L RSCAN0.RMDF01.UINT16[L] +#define RSCAN0RMDF01LL RSCAN0.RMDF01.UINT8[LL] +#define RSCAN0RMDF01LH RSCAN0.RMDF01.UINT8[LH] +#define RSCAN0RMDF01H RSCAN0.RMDF01.UINT16[H] +#define RSCAN0RMDF01HL RSCAN0.RMDF01.UINT8[HL] +#define RSCAN0RMDF01HH RSCAN0.RMDF01.UINT8[HH] +#define RSCAN0RMDF11 RSCAN0.RMDF11.UINT32 +#define RSCAN0RMDF11L RSCAN0.RMDF11.UINT16[L] +#define RSCAN0RMDF11LL RSCAN0.RMDF11.UINT8[LL] +#define RSCAN0RMDF11LH RSCAN0.RMDF11.UINT8[LH] +#define RSCAN0RMDF11H RSCAN0.RMDF11.UINT16[H] +#define RSCAN0RMDF11HL RSCAN0.RMDF11.UINT8[HL] +#define RSCAN0RMDF11HH RSCAN0.RMDF11.UINT8[HH] +#define RSCAN0RMID2 RSCAN0.RMID2.UINT32 +#define RSCAN0RMID2L RSCAN0.RMID2.UINT16[L] +#define RSCAN0RMID2LL RSCAN0.RMID2.UINT8[LL] +#define RSCAN0RMID2LH RSCAN0.RMID2.UINT8[LH] +#define RSCAN0RMID2H RSCAN0.RMID2.UINT16[H] +#define RSCAN0RMID2HL RSCAN0.RMID2.UINT8[HL] +#define RSCAN0RMID2HH RSCAN0.RMID2.UINT8[HH] +#define RSCAN0RMPTR2 RSCAN0.RMPTR2.UINT32 +#define RSCAN0RMPTR2L RSCAN0.RMPTR2.UINT16[L] +#define RSCAN0RMPTR2LL RSCAN0.RMPTR2.UINT8[LL] +#define RSCAN0RMPTR2LH RSCAN0.RMPTR2.UINT8[LH] +#define RSCAN0RMPTR2H RSCAN0.RMPTR2.UINT16[H] +#define RSCAN0RMPTR2HL RSCAN0.RMPTR2.UINT8[HL] +#define RSCAN0RMPTR2HH RSCAN0.RMPTR2.UINT8[HH] +#define RSCAN0RMDF02 RSCAN0.RMDF02.UINT32 +#define RSCAN0RMDF02L RSCAN0.RMDF02.UINT16[L] +#define RSCAN0RMDF02LL RSCAN0.RMDF02.UINT8[LL] +#define RSCAN0RMDF02LH RSCAN0.RMDF02.UINT8[LH] +#define RSCAN0RMDF02H RSCAN0.RMDF02.UINT16[H] +#define RSCAN0RMDF02HL RSCAN0.RMDF02.UINT8[HL] +#define RSCAN0RMDF02HH RSCAN0.RMDF02.UINT8[HH] +#define RSCAN0RMDF12 RSCAN0.RMDF12.UINT32 +#define RSCAN0RMDF12L RSCAN0.RMDF12.UINT16[L] +#define RSCAN0RMDF12LL RSCAN0.RMDF12.UINT8[LL] +#define RSCAN0RMDF12LH RSCAN0.RMDF12.UINT8[LH] +#define RSCAN0RMDF12H RSCAN0.RMDF12.UINT16[H] +#define RSCAN0RMDF12HL RSCAN0.RMDF12.UINT8[HL] +#define RSCAN0RMDF12HH RSCAN0.RMDF12.UINT8[HH] +#define RSCAN0RMID3 RSCAN0.RMID3.UINT32 +#define RSCAN0RMID3L RSCAN0.RMID3.UINT16[L] +#define RSCAN0RMID3LL RSCAN0.RMID3.UINT8[LL] +#define RSCAN0RMID3LH RSCAN0.RMID3.UINT8[LH] +#define RSCAN0RMID3H RSCAN0.RMID3.UINT16[H] +#define RSCAN0RMID3HL RSCAN0.RMID3.UINT8[HL] +#define RSCAN0RMID3HH RSCAN0.RMID3.UINT8[HH] +#define RSCAN0RMPTR3 RSCAN0.RMPTR3.UINT32 +#define RSCAN0RMPTR3L RSCAN0.RMPTR3.UINT16[L] +#define RSCAN0RMPTR3LL RSCAN0.RMPTR3.UINT8[LL] +#define RSCAN0RMPTR3LH RSCAN0.RMPTR3.UINT8[LH] +#define RSCAN0RMPTR3H RSCAN0.RMPTR3.UINT16[H] +#define RSCAN0RMPTR3HL RSCAN0.RMPTR3.UINT8[HL] +#define RSCAN0RMPTR3HH RSCAN0.RMPTR3.UINT8[HH] +#define RSCAN0RMDF03 RSCAN0.RMDF03.UINT32 +#define RSCAN0RMDF03L RSCAN0.RMDF03.UINT16[L] +#define RSCAN0RMDF03LL RSCAN0.RMDF03.UINT8[LL] +#define RSCAN0RMDF03LH RSCAN0.RMDF03.UINT8[LH] +#define RSCAN0RMDF03H RSCAN0.RMDF03.UINT16[H] +#define RSCAN0RMDF03HL RSCAN0.RMDF03.UINT8[HL] +#define RSCAN0RMDF03HH RSCAN0.RMDF03.UINT8[HH] +#define RSCAN0RMDF13 RSCAN0.RMDF13.UINT32 +#define RSCAN0RMDF13L RSCAN0.RMDF13.UINT16[L] +#define RSCAN0RMDF13LL RSCAN0.RMDF13.UINT8[LL] +#define RSCAN0RMDF13LH RSCAN0.RMDF13.UINT8[LH] +#define RSCAN0RMDF13H RSCAN0.RMDF13.UINT16[H] +#define RSCAN0RMDF13HL RSCAN0.RMDF13.UINT8[HL] +#define RSCAN0RMDF13HH RSCAN0.RMDF13.UINT8[HH] +#define RSCAN0RMID4 RSCAN0.RMID4.UINT32 +#define RSCAN0RMID4L RSCAN0.RMID4.UINT16[L] +#define RSCAN0RMID4LL RSCAN0.RMID4.UINT8[LL] +#define RSCAN0RMID4LH RSCAN0.RMID4.UINT8[LH] +#define RSCAN0RMID4H RSCAN0.RMID4.UINT16[H] +#define RSCAN0RMID4HL RSCAN0.RMID4.UINT8[HL] +#define RSCAN0RMID4HH RSCAN0.RMID4.UINT8[HH] +#define RSCAN0RMPTR4 RSCAN0.RMPTR4.UINT32 +#define RSCAN0RMPTR4L RSCAN0.RMPTR4.UINT16[L] +#define RSCAN0RMPTR4LL RSCAN0.RMPTR4.UINT8[LL] +#define RSCAN0RMPTR4LH RSCAN0.RMPTR4.UINT8[LH] +#define RSCAN0RMPTR4H RSCAN0.RMPTR4.UINT16[H] +#define RSCAN0RMPTR4HL RSCAN0.RMPTR4.UINT8[HL] +#define RSCAN0RMPTR4HH RSCAN0.RMPTR4.UINT8[HH] +#define RSCAN0RMDF04 RSCAN0.RMDF04.UINT32 +#define RSCAN0RMDF04L RSCAN0.RMDF04.UINT16[L] +#define RSCAN0RMDF04LL RSCAN0.RMDF04.UINT8[LL] +#define RSCAN0RMDF04LH RSCAN0.RMDF04.UINT8[LH] +#define RSCAN0RMDF04H RSCAN0.RMDF04.UINT16[H] +#define RSCAN0RMDF04HL RSCAN0.RMDF04.UINT8[HL] +#define RSCAN0RMDF04HH RSCAN0.RMDF04.UINT8[HH] +#define RSCAN0RMDF14 RSCAN0.RMDF14.UINT32 +#define RSCAN0RMDF14L RSCAN0.RMDF14.UINT16[L] +#define RSCAN0RMDF14LL RSCAN0.RMDF14.UINT8[LL] +#define RSCAN0RMDF14LH RSCAN0.RMDF14.UINT8[LH] +#define RSCAN0RMDF14H RSCAN0.RMDF14.UINT16[H] +#define RSCAN0RMDF14HL RSCAN0.RMDF14.UINT8[HL] +#define RSCAN0RMDF14HH RSCAN0.RMDF14.UINT8[HH] +#define RSCAN0RMID5 RSCAN0.RMID5.UINT32 +#define RSCAN0RMID5L RSCAN0.RMID5.UINT16[L] +#define RSCAN0RMID5LL RSCAN0.RMID5.UINT8[LL] +#define RSCAN0RMID5LH RSCAN0.RMID5.UINT8[LH] +#define RSCAN0RMID5H RSCAN0.RMID5.UINT16[H] +#define RSCAN0RMID5HL RSCAN0.RMID5.UINT8[HL] +#define RSCAN0RMID5HH RSCAN0.RMID5.UINT8[HH] +#define RSCAN0RMPTR5 RSCAN0.RMPTR5.UINT32 +#define RSCAN0RMPTR5L RSCAN0.RMPTR5.UINT16[L] +#define RSCAN0RMPTR5LL RSCAN0.RMPTR5.UINT8[LL] +#define RSCAN0RMPTR5LH RSCAN0.RMPTR5.UINT8[LH] +#define RSCAN0RMPTR5H RSCAN0.RMPTR5.UINT16[H] +#define RSCAN0RMPTR5HL RSCAN0.RMPTR5.UINT8[HL] +#define RSCAN0RMPTR5HH RSCAN0.RMPTR5.UINT8[HH] +#define RSCAN0RMDF05 RSCAN0.RMDF05.UINT32 +#define RSCAN0RMDF05L RSCAN0.RMDF05.UINT16[L] +#define RSCAN0RMDF05LL RSCAN0.RMDF05.UINT8[LL] +#define RSCAN0RMDF05LH RSCAN0.RMDF05.UINT8[LH] +#define RSCAN0RMDF05H RSCAN0.RMDF05.UINT16[H] +#define RSCAN0RMDF05HL RSCAN0.RMDF05.UINT8[HL] +#define RSCAN0RMDF05HH RSCAN0.RMDF05.UINT8[HH] +#define RSCAN0RMDF15 RSCAN0.RMDF15.UINT32 +#define RSCAN0RMDF15L RSCAN0.RMDF15.UINT16[L] +#define RSCAN0RMDF15LL RSCAN0.RMDF15.UINT8[LL] +#define RSCAN0RMDF15LH RSCAN0.RMDF15.UINT8[LH] +#define RSCAN0RMDF15H RSCAN0.RMDF15.UINT16[H] +#define RSCAN0RMDF15HL RSCAN0.RMDF15.UINT8[HL] +#define RSCAN0RMDF15HH RSCAN0.RMDF15.UINT8[HH] +#define RSCAN0RMID6 RSCAN0.RMID6.UINT32 +#define RSCAN0RMID6L RSCAN0.RMID6.UINT16[L] +#define RSCAN0RMID6LL RSCAN0.RMID6.UINT8[LL] +#define RSCAN0RMID6LH RSCAN0.RMID6.UINT8[LH] +#define RSCAN0RMID6H RSCAN0.RMID6.UINT16[H] +#define RSCAN0RMID6HL RSCAN0.RMID6.UINT8[HL] +#define RSCAN0RMID6HH RSCAN0.RMID6.UINT8[HH] +#define RSCAN0RMPTR6 RSCAN0.RMPTR6.UINT32 +#define RSCAN0RMPTR6L RSCAN0.RMPTR6.UINT16[L] +#define RSCAN0RMPTR6LL RSCAN0.RMPTR6.UINT8[LL] +#define RSCAN0RMPTR6LH RSCAN0.RMPTR6.UINT8[LH] +#define RSCAN0RMPTR6H RSCAN0.RMPTR6.UINT16[H] +#define RSCAN0RMPTR6HL RSCAN0.RMPTR6.UINT8[HL] +#define RSCAN0RMPTR6HH RSCAN0.RMPTR6.UINT8[HH] +#define RSCAN0RMDF06 RSCAN0.RMDF06.UINT32 +#define RSCAN0RMDF06L RSCAN0.RMDF06.UINT16[L] +#define RSCAN0RMDF06LL RSCAN0.RMDF06.UINT8[LL] +#define RSCAN0RMDF06LH RSCAN0.RMDF06.UINT8[LH] +#define RSCAN0RMDF06H RSCAN0.RMDF06.UINT16[H] +#define RSCAN0RMDF06HL RSCAN0.RMDF06.UINT8[HL] +#define RSCAN0RMDF06HH RSCAN0.RMDF06.UINT8[HH] +#define RSCAN0RMDF16 RSCAN0.RMDF16.UINT32 +#define RSCAN0RMDF16L RSCAN0.RMDF16.UINT16[L] +#define RSCAN0RMDF16LL RSCAN0.RMDF16.UINT8[LL] +#define RSCAN0RMDF16LH RSCAN0.RMDF16.UINT8[LH] +#define RSCAN0RMDF16H RSCAN0.RMDF16.UINT16[H] +#define RSCAN0RMDF16HL RSCAN0.RMDF16.UINT8[HL] +#define RSCAN0RMDF16HH RSCAN0.RMDF16.UINT8[HH] +#define RSCAN0RMID7 RSCAN0.RMID7.UINT32 +#define RSCAN0RMID7L RSCAN0.RMID7.UINT16[L] +#define RSCAN0RMID7LL RSCAN0.RMID7.UINT8[LL] +#define RSCAN0RMID7LH RSCAN0.RMID7.UINT8[LH] +#define RSCAN0RMID7H RSCAN0.RMID7.UINT16[H] +#define RSCAN0RMID7HL RSCAN0.RMID7.UINT8[HL] +#define RSCAN0RMID7HH RSCAN0.RMID7.UINT8[HH] +#define RSCAN0RMPTR7 RSCAN0.RMPTR7.UINT32 +#define RSCAN0RMPTR7L RSCAN0.RMPTR7.UINT16[L] +#define RSCAN0RMPTR7LL RSCAN0.RMPTR7.UINT8[LL] +#define RSCAN0RMPTR7LH RSCAN0.RMPTR7.UINT8[LH] +#define RSCAN0RMPTR7H RSCAN0.RMPTR7.UINT16[H] +#define RSCAN0RMPTR7HL RSCAN0.RMPTR7.UINT8[HL] +#define RSCAN0RMPTR7HH RSCAN0.RMPTR7.UINT8[HH] +#define RSCAN0RMDF07 RSCAN0.RMDF07.UINT32 +#define RSCAN0RMDF07L RSCAN0.RMDF07.UINT16[L] +#define RSCAN0RMDF07LL RSCAN0.RMDF07.UINT8[LL] +#define RSCAN0RMDF07LH RSCAN0.RMDF07.UINT8[LH] +#define RSCAN0RMDF07H RSCAN0.RMDF07.UINT16[H] +#define RSCAN0RMDF07HL RSCAN0.RMDF07.UINT8[HL] +#define RSCAN0RMDF07HH RSCAN0.RMDF07.UINT8[HH] +#define RSCAN0RMDF17 RSCAN0.RMDF17.UINT32 +#define RSCAN0RMDF17L RSCAN0.RMDF17.UINT16[L] +#define RSCAN0RMDF17LL RSCAN0.RMDF17.UINT8[LL] +#define RSCAN0RMDF17LH RSCAN0.RMDF17.UINT8[LH] +#define RSCAN0RMDF17H RSCAN0.RMDF17.UINT16[H] +#define RSCAN0RMDF17HL RSCAN0.RMDF17.UINT8[HL] +#define RSCAN0RMDF17HH RSCAN0.RMDF17.UINT8[HH] +#define RSCAN0RMID8 RSCAN0.RMID8.UINT32 +#define RSCAN0RMID8L RSCAN0.RMID8.UINT16[L] +#define RSCAN0RMID8LL RSCAN0.RMID8.UINT8[LL] +#define RSCAN0RMID8LH RSCAN0.RMID8.UINT8[LH] +#define RSCAN0RMID8H RSCAN0.RMID8.UINT16[H] +#define RSCAN0RMID8HL RSCAN0.RMID8.UINT8[HL] +#define RSCAN0RMID8HH RSCAN0.RMID8.UINT8[HH] +#define RSCAN0RMPTR8 RSCAN0.RMPTR8.UINT32 +#define RSCAN0RMPTR8L RSCAN0.RMPTR8.UINT16[L] +#define RSCAN0RMPTR8LL RSCAN0.RMPTR8.UINT8[LL] +#define RSCAN0RMPTR8LH RSCAN0.RMPTR8.UINT8[LH] +#define RSCAN0RMPTR8H RSCAN0.RMPTR8.UINT16[H] +#define RSCAN0RMPTR8HL RSCAN0.RMPTR8.UINT8[HL] +#define RSCAN0RMPTR8HH RSCAN0.RMPTR8.UINT8[HH] +#define RSCAN0RMDF08 RSCAN0.RMDF08.UINT32 +#define RSCAN0RMDF08L RSCAN0.RMDF08.UINT16[L] +#define RSCAN0RMDF08LL RSCAN0.RMDF08.UINT8[LL] +#define RSCAN0RMDF08LH RSCAN0.RMDF08.UINT8[LH] +#define RSCAN0RMDF08H RSCAN0.RMDF08.UINT16[H] +#define RSCAN0RMDF08HL RSCAN0.RMDF08.UINT8[HL] +#define RSCAN0RMDF08HH RSCAN0.RMDF08.UINT8[HH] +#define RSCAN0RMDF18 RSCAN0.RMDF18.UINT32 +#define RSCAN0RMDF18L RSCAN0.RMDF18.UINT16[L] +#define RSCAN0RMDF18LL RSCAN0.RMDF18.UINT8[LL] +#define RSCAN0RMDF18LH RSCAN0.RMDF18.UINT8[LH] +#define RSCAN0RMDF18H RSCAN0.RMDF18.UINT16[H] +#define RSCAN0RMDF18HL RSCAN0.RMDF18.UINT8[HL] +#define RSCAN0RMDF18HH RSCAN0.RMDF18.UINT8[HH] +#define RSCAN0RMID9 RSCAN0.RMID9.UINT32 +#define RSCAN0RMID9L RSCAN0.RMID9.UINT16[L] +#define RSCAN0RMID9LL RSCAN0.RMID9.UINT8[LL] +#define RSCAN0RMID9LH RSCAN0.RMID9.UINT8[LH] +#define RSCAN0RMID9H RSCAN0.RMID9.UINT16[H] +#define RSCAN0RMID9HL RSCAN0.RMID9.UINT8[HL] +#define RSCAN0RMID9HH RSCAN0.RMID9.UINT8[HH] +#define RSCAN0RMPTR9 RSCAN0.RMPTR9.UINT32 +#define RSCAN0RMPTR9L RSCAN0.RMPTR9.UINT16[L] +#define RSCAN0RMPTR9LL RSCAN0.RMPTR9.UINT8[LL] +#define RSCAN0RMPTR9LH RSCAN0.RMPTR9.UINT8[LH] +#define RSCAN0RMPTR9H RSCAN0.RMPTR9.UINT16[H] +#define RSCAN0RMPTR9HL RSCAN0.RMPTR9.UINT8[HL] +#define RSCAN0RMPTR9HH RSCAN0.RMPTR9.UINT8[HH] +#define RSCAN0RMDF09 RSCAN0.RMDF09.UINT32 +#define RSCAN0RMDF09L RSCAN0.RMDF09.UINT16[L] +#define RSCAN0RMDF09LL RSCAN0.RMDF09.UINT8[LL] +#define RSCAN0RMDF09LH RSCAN0.RMDF09.UINT8[LH] +#define RSCAN0RMDF09H RSCAN0.RMDF09.UINT16[H] +#define RSCAN0RMDF09HL RSCAN0.RMDF09.UINT8[HL] +#define RSCAN0RMDF09HH RSCAN0.RMDF09.UINT8[HH] +#define RSCAN0RMDF19 RSCAN0.RMDF19.UINT32 +#define RSCAN0RMDF19L RSCAN0.RMDF19.UINT16[L] +#define RSCAN0RMDF19LL RSCAN0.RMDF19.UINT8[LL] +#define RSCAN0RMDF19LH RSCAN0.RMDF19.UINT8[LH] +#define RSCAN0RMDF19H RSCAN0.RMDF19.UINT16[H] +#define RSCAN0RMDF19HL RSCAN0.RMDF19.UINT8[HL] +#define RSCAN0RMDF19HH RSCAN0.RMDF19.UINT8[HH] +#define RSCAN0RMID10 RSCAN0.RMID10.UINT32 +#define RSCAN0RMID10L RSCAN0.RMID10.UINT16[L] +#define RSCAN0RMID10LL RSCAN0.RMID10.UINT8[LL] +#define RSCAN0RMID10LH RSCAN0.RMID10.UINT8[LH] +#define RSCAN0RMID10H RSCAN0.RMID10.UINT16[H] +#define RSCAN0RMID10HL RSCAN0.RMID10.UINT8[HL] +#define RSCAN0RMID10HH RSCAN0.RMID10.UINT8[HH] +#define RSCAN0RMPTR10 RSCAN0.RMPTR10.UINT32 +#define RSCAN0RMPTR10L RSCAN0.RMPTR10.UINT16[L] +#define RSCAN0RMPTR10LL RSCAN0.RMPTR10.UINT8[LL] +#define RSCAN0RMPTR10LH RSCAN0.RMPTR10.UINT8[LH] +#define RSCAN0RMPTR10H RSCAN0.RMPTR10.UINT16[H] +#define RSCAN0RMPTR10HL RSCAN0.RMPTR10.UINT8[HL] +#define RSCAN0RMPTR10HH RSCAN0.RMPTR10.UINT8[HH] +#define RSCAN0RMDF010 RSCAN0.RMDF010.UINT32 +#define RSCAN0RMDF010L RSCAN0.RMDF010.UINT16[L] +#define RSCAN0RMDF010LL RSCAN0.RMDF010.UINT8[LL] +#define RSCAN0RMDF010LH RSCAN0.RMDF010.UINT8[LH] +#define RSCAN0RMDF010H RSCAN0.RMDF010.UINT16[H] +#define RSCAN0RMDF010HL RSCAN0.RMDF010.UINT8[HL] +#define RSCAN0RMDF010HH RSCAN0.RMDF010.UINT8[HH] +#define RSCAN0RMDF110 RSCAN0.RMDF110.UINT32 +#define RSCAN0RMDF110L RSCAN0.RMDF110.UINT16[L] +#define RSCAN0RMDF110LL RSCAN0.RMDF110.UINT8[LL] +#define RSCAN0RMDF110LH RSCAN0.RMDF110.UINT8[LH] +#define RSCAN0RMDF110H RSCAN0.RMDF110.UINT16[H] +#define RSCAN0RMDF110HL RSCAN0.RMDF110.UINT8[HL] +#define RSCAN0RMDF110HH RSCAN0.RMDF110.UINT8[HH] +#define RSCAN0RMID11 RSCAN0.RMID11.UINT32 +#define RSCAN0RMID11L RSCAN0.RMID11.UINT16[L] +#define RSCAN0RMID11LL RSCAN0.RMID11.UINT8[LL] +#define RSCAN0RMID11LH RSCAN0.RMID11.UINT8[LH] +#define RSCAN0RMID11H RSCAN0.RMID11.UINT16[H] +#define RSCAN0RMID11HL RSCAN0.RMID11.UINT8[HL] +#define RSCAN0RMID11HH RSCAN0.RMID11.UINT8[HH] +#define RSCAN0RMPTR11 RSCAN0.RMPTR11.UINT32 +#define RSCAN0RMPTR11L RSCAN0.RMPTR11.UINT16[L] +#define RSCAN0RMPTR11LL RSCAN0.RMPTR11.UINT8[LL] +#define RSCAN0RMPTR11LH RSCAN0.RMPTR11.UINT8[LH] +#define RSCAN0RMPTR11H RSCAN0.RMPTR11.UINT16[H] +#define RSCAN0RMPTR11HL RSCAN0.RMPTR11.UINT8[HL] +#define RSCAN0RMPTR11HH RSCAN0.RMPTR11.UINT8[HH] +#define RSCAN0RMDF011 RSCAN0.RMDF011.UINT32 +#define RSCAN0RMDF011L RSCAN0.RMDF011.UINT16[L] +#define RSCAN0RMDF011LL RSCAN0.RMDF011.UINT8[LL] +#define RSCAN0RMDF011LH RSCAN0.RMDF011.UINT8[LH] +#define RSCAN0RMDF011H RSCAN0.RMDF011.UINT16[H] +#define RSCAN0RMDF011HL RSCAN0.RMDF011.UINT8[HL] +#define RSCAN0RMDF011HH RSCAN0.RMDF011.UINT8[HH] +#define RSCAN0RMDF111 RSCAN0.RMDF111.UINT32 +#define RSCAN0RMDF111L RSCAN0.RMDF111.UINT16[L] +#define RSCAN0RMDF111LL RSCAN0.RMDF111.UINT8[LL] +#define RSCAN0RMDF111LH RSCAN0.RMDF111.UINT8[LH] +#define RSCAN0RMDF111H RSCAN0.RMDF111.UINT16[H] +#define RSCAN0RMDF111HL RSCAN0.RMDF111.UINT8[HL] +#define RSCAN0RMDF111HH RSCAN0.RMDF111.UINT8[HH] +#define RSCAN0RMID12 RSCAN0.RMID12.UINT32 +#define RSCAN0RMID12L RSCAN0.RMID12.UINT16[L] +#define RSCAN0RMID12LL RSCAN0.RMID12.UINT8[LL] +#define RSCAN0RMID12LH RSCAN0.RMID12.UINT8[LH] +#define RSCAN0RMID12H RSCAN0.RMID12.UINT16[H] +#define RSCAN0RMID12HL RSCAN0.RMID12.UINT8[HL] +#define RSCAN0RMID12HH RSCAN0.RMID12.UINT8[HH] +#define RSCAN0RMPTR12 RSCAN0.RMPTR12.UINT32 +#define RSCAN0RMPTR12L RSCAN0.RMPTR12.UINT16[L] +#define RSCAN0RMPTR12LL RSCAN0.RMPTR12.UINT8[LL] +#define RSCAN0RMPTR12LH RSCAN0.RMPTR12.UINT8[LH] +#define RSCAN0RMPTR12H RSCAN0.RMPTR12.UINT16[H] +#define RSCAN0RMPTR12HL RSCAN0.RMPTR12.UINT8[HL] +#define RSCAN0RMPTR12HH RSCAN0.RMPTR12.UINT8[HH] +#define RSCAN0RMDF012 RSCAN0.RMDF012.UINT32 +#define RSCAN0RMDF012L RSCAN0.RMDF012.UINT16[L] +#define RSCAN0RMDF012LL RSCAN0.RMDF012.UINT8[LL] +#define RSCAN0RMDF012LH RSCAN0.RMDF012.UINT8[LH] +#define RSCAN0RMDF012H RSCAN0.RMDF012.UINT16[H] +#define RSCAN0RMDF012HL RSCAN0.RMDF012.UINT8[HL] +#define RSCAN0RMDF012HH RSCAN0.RMDF012.UINT8[HH] +#define RSCAN0RMDF112 RSCAN0.RMDF112.UINT32 +#define RSCAN0RMDF112L RSCAN0.RMDF112.UINT16[L] +#define RSCAN0RMDF112LL RSCAN0.RMDF112.UINT8[LL] +#define RSCAN0RMDF112LH RSCAN0.RMDF112.UINT8[LH] +#define RSCAN0RMDF112H RSCAN0.RMDF112.UINT16[H] +#define RSCAN0RMDF112HL RSCAN0.RMDF112.UINT8[HL] +#define RSCAN0RMDF112HH RSCAN0.RMDF112.UINT8[HH] +#define RSCAN0RMID13 RSCAN0.RMID13.UINT32 +#define RSCAN0RMID13L RSCAN0.RMID13.UINT16[L] +#define RSCAN0RMID13LL RSCAN0.RMID13.UINT8[LL] +#define RSCAN0RMID13LH RSCAN0.RMID13.UINT8[LH] +#define RSCAN0RMID13H RSCAN0.RMID13.UINT16[H] +#define RSCAN0RMID13HL RSCAN0.RMID13.UINT8[HL] +#define RSCAN0RMID13HH RSCAN0.RMID13.UINT8[HH] +#define RSCAN0RMPTR13 RSCAN0.RMPTR13.UINT32 +#define RSCAN0RMPTR13L RSCAN0.RMPTR13.UINT16[L] +#define RSCAN0RMPTR13LL RSCAN0.RMPTR13.UINT8[LL] +#define RSCAN0RMPTR13LH RSCAN0.RMPTR13.UINT8[LH] +#define RSCAN0RMPTR13H RSCAN0.RMPTR13.UINT16[H] +#define RSCAN0RMPTR13HL RSCAN0.RMPTR13.UINT8[HL] +#define RSCAN0RMPTR13HH RSCAN0.RMPTR13.UINT8[HH] +#define RSCAN0RMDF013 RSCAN0.RMDF013.UINT32 +#define RSCAN0RMDF013L RSCAN0.RMDF013.UINT16[L] +#define RSCAN0RMDF013LL RSCAN0.RMDF013.UINT8[LL] +#define RSCAN0RMDF013LH RSCAN0.RMDF013.UINT8[LH] +#define RSCAN0RMDF013H RSCAN0.RMDF013.UINT16[H] +#define RSCAN0RMDF013HL RSCAN0.RMDF013.UINT8[HL] +#define RSCAN0RMDF013HH RSCAN0.RMDF013.UINT8[HH] +#define RSCAN0RMDF113 RSCAN0.RMDF113.UINT32 +#define RSCAN0RMDF113L RSCAN0.RMDF113.UINT16[L] +#define RSCAN0RMDF113LL RSCAN0.RMDF113.UINT8[LL] +#define RSCAN0RMDF113LH RSCAN0.RMDF113.UINT8[LH] +#define RSCAN0RMDF113H RSCAN0.RMDF113.UINT16[H] +#define RSCAN0RMDF113HL RSCAN0.RMDF113.UINT8[HL] +#define RSCAN0RMDF113HH RSCAN0.RMDF113.UINT8[HH] +#define RSCAN0RMID14 RSCAN0.RMID14.UINT32 +#define RSCAN0RMID14L RSCAN0.RMID14.UINT16[L] +#define RSCAN0RMID14LL RSCAN0.RMID14.UINT8[LL] +#define RSCAN0RMID14LH RSCAN0.RMID14.UINT8[LH] +#define RSCAN0RMID14H RSCAN0.RMID14.UINT16[H] +#define RSCAN0RMID14HL RSCAN0.RMID14.UINT8[HL] +#define RSCAN0RMID14HH RSCAN0.RMID14.UINT8[HH] +#define RSCAN0RMPTR14 RSCAN0.RMPTR14.UINT32 +#define RSCAN0RMPTR14L RSCAN0.RMPTR14.UINT16[L] +#define RSCAN0RMPTR14LL RSCAN0.RMPTR14.UINT8[LL] +#define RSCAN0RMPTR14LH RSCAN0.RMPTR14.UINT8[LH] +#define RSCAN0RMPTR14H RSCAN0.RMPTR14.UINT16[H] +#define RSCAN0RMPTR14HL RSCAN0.RMPTR14.UINT8[HL] +#define RSCAN0RMPTR14HH RSCAN0.RMPTR14.UINT8[HH] +#define RSCAN0RMDF014 RSCAN0.RMDF014.UINT32 +#define RSCAN0RMDF014L RSCAN0.RMDF014.UINT16[L] +#define RSCAN0RMDF014LL RSCAN0.RMDF014.UINT8[LL] +#define RSCAN0RMDF014LH RSCAN0.RMDF014.UINT8[LH] +#define RSCAN0RMDF014H RSCAN0.RMDF014.UINT16[H] +#define RSCAN0RMDF014HL RSCAN0.RMDF014.UINT8[HL] +#define RSCAN0RMDF014HH RSCAN0.RMDF014.UINT8[HH] +#define RSCAN0RMDF114 RSCAN0.RMDF114.UINT32 +#define RSCAN0RMDF114L RSCAN0.RMDF114.UINT16[L] +#define RSCAN0RMDF114LL RSCAN0.RMDF114.UINT8[LL] +#define RSCAN0RMDF114LH RSCAN0.RMDF114.UINT8[LH] +#define RSCAN0RMDF114H RSCAN0.RMDF114.UINT16[H] +#define RSCAN0RMDF114HL RSCAN0.RMDF114.UINT8[HL] +#define RSCAN0RMDF114HH RSCAN0.RMDF114.UINT8[HH] +#define RSCAN0RMID15 RSCAN0.RMID15.UINT32 +#define RSCAN0RMID15L RSCAN0.RMID15.UINT16[L] +#define RSCAN0RMID15LL RSCAN0.RMID15.UINT8[LL] +#define RSCAN0RMID15LH RSCAN0.RMID15.UINT8[LH] +#define RSCAN0RMID15H RSCAN0.RMID15.UINT16[H] +#define RSCAN0RMID15HL RSCAN0.RMID15.UINT8[HL] +#define RSCAN0RMID15HH RSCAN0.RMID15.UINT8[HH] +#define RSCAN0RMPTR15 RSCAN0.RMPTR15.UINT32 +#define RSCAN0RMPTR15L RSCAN0.RMPTR15.UINT16[L] +#define RSCAN0RMPTR15LL RSCAN0.RMPTR15.UINT8[LL] +#define RSCAN0RMPTR15LH RSCAN0.RMPTR15.UINT8[LH] +#define RSCAN0RMPTR15H RSCAN0.RMPTR15.UINT16[H] +#define RSCAN0RMPTR15HL RSCAN0.RMPTR15.UINT8[HL] +#define RSCAN0RMPTR15HH RSCAN0.RMPTR15.UINT8[HH] +#define RSCAN0RMDF015 RSCAN0.RMDF015.UINT32 +#define RSCAN0RMDF015L RSCAN0.RMDF015.UINT16[L] +#define RSCAN0RMDF015LL RSCAN0.RMDF015.UINT8[LL] +#define RSCAN0RMDF015LH RSCAN0.RMDF015.UINT8[LH] +#define RSCAN0RMDF015H RSCAN0.RMDF015.UINT16[H] +#define RSCAN0RMDF015HL RSCAN0.RMDF015.UINT8[HL] +#define RSCAN0RMDF015HH RSCAN0.RMDF015.UINT8[HH] +#define RSCAN0RMDF115 RSCAN0.RMDF115.UINT32 +#define RSCAN0RMDF115L RSCAN0.RMDF115.UINT16[L] +#define RSCAN0RMDF115LL RSCAN0.RMDF115.UINT8[LL] +#define RSCAN0RMDF115LH RSCAN0.RMDF115.UINT8[LH] +#define RSCAN0RMDF115H RSCAN0.RMDF115.UINT16[H] +#define RSCAN0RMDF115HL RSCAN0.RMDF115.UINT8[HL] +#define RSCAN0RMDF115HH RSCAN0.RMDF115.UINT8[HH] +#define RSCAN0RMID16 RSCAN0.RMID16.UINT32 +#define RSCAN0RMID16L RSCAN0.RMID16.UINT16[L] +#define RSCAN0RMID16LL RSCAN0.RMID16.UINT8[LL] +#define RSCAN0RMID16LH RSCAN0.RMID16.UINT8[LH] +#define RSCAN0RMID16H RSCAN0.RMID16.UINT16[H] +#define RSCAN0RMID16HL RSCAN0.RMID16.UINT8[HL] +#define RSCAN0RMID16HH RSCAN0.RMID16.UINT8[HH] +#define RSCAN0RMPTR16 RSCAN0.RMPTR16.UINT32 +#define RSCAN0RMPTR16L RSCAN0.RMPTR16.UINT16[L] +#define RSCAN0RMPTR16LL RSCAN0.RMPTR16.UINT8[LL] +#define RSCAN0RMPTR16LH RSCAN0.RMPTR16.UINT8[LH] +#define RSCAN0RMPTR16H RSCAN0.RMPTR16.UINT16[H] +#define RSCAN0RMPTR16HL RSCAN0.RMPTR16.UINT8[HL] +#define RSCAN0RMPTR16HH RSCAN0.RMPTR16.UINT8[HH] +#define RSCAN0RMDF016 RSCAN0.RMDF016.UINT32 +#define RSCAN0RMDF016L RSCAN0.RMDF016.UINT16[L] +#define RSCAN0RMDF016LL RSCAN0.RMDF016.UINT8[LL] +#define RSCAN0RMDF016LH RSCAN0.RMDF016.UINT8[LH] +#define RSCAN0RMDF016H RSCAN0.RMDF016.UINT16[H] +#define RSCAN0RMDF016HL RSCAN0.RMDF016.UINT8[HL] +#define RSCAN0RMDF016HH RSCAN0.RMDF016.UINT8[HH] +#define RSCAN0RMDF116 RSCAN0.RMDF116.UINT32 +#define RSCAN0RMDF116L RSCAN0.RMDF116.UINT16[L] +#define RSCAN0RMDF116LL RSCAN0.RMDF116.UINT8[LL] +#define RSCAN0RMDF116LH RSCAN0.RMDF116.UINT8[LH] +#define RSCAN0RMDF116H RSCAN0.RMDF116.UINT16[H] +#define RSCAN0RMDF116HL RSCAN0.RMDF116.UINT8[HL] +#define RSCAN0RMDF116HH RSCAN0.RMDF116.UINT8[HH] +#define RSCAN0RMID17 RSCAN0.RMID17.UINT32 +#define RSCAN0RMID17L RSCAN0.RMID17.UINT16[L] +#define RSCAN0RMID17LL RSCAN0.RMID17.UINT8[LL] +#define RSCAN0RMID17LH RSCAN0.RMID17.UINT8[LH] +#define RSCAN0RMID17H RSCAN0.RMID17.UINT16[H] +#define RSCAN0RMID17HL RSCAN0.RMID17.UINT8[HL] +#define RSCAN0RMID17HH RSCAN0.RMID17.UINT8[HH] +#define RSCAN0RMPTR17 RSCAN0.RMPTR17.UINT32 +#define RSCAN0RMPTR17L RSCAN0.RMPTR17.UINT16[L] +#define RSCAN0RMPTR17LL RSCAN0.RMPTR17.UINT8[LL] +#define RSCAN0RMPTR17LH RSCAN0.RMPTR17.UINT8[LH] +#define RSCAN0RMPTR17H RSCAN0.RMPTR17.UINT16[H] +#define RSCAN0RMPTR17HL RSCAN0.RMPTR17.UINT8[HL] +#define RSCAN0RMPTR17HH RSCAN0.RMPTR17.UINT8[HH] +#define RSCAN0RMDF017 RSCAN0.RMDF017.UINT32 +#define RSCAN0RMDF017L RSCAN0.RMDF017.UINT16[L] +#define RSCAN0RMDF017LL RSCAN0.RMDF017.UINT8[LL] +#define RSCAN0RMDF017LH RSCAN0.RMDF017.UINT8[LH] +#define RSCAN0RMDF017H RSCAN0.RMDF017.UINT16[H] +#define RSCAN0RMDF017HL RSCAN0.RMDF017.UINT8[HL] +#define RSCAN0RMDF017HH RSCAN0.RMDF017.UINT8[HH] +#define RSCAN0RMDF117 RSCAN0.RMDF117.UINT32 +#define RSCAN0RMDF117L RSCAN0.RMDF117.UINT16[L] +#define RSCAN0RMDF117LL RSCAN0.RMDF117.UINT8[LL] +#define RSCAN0RMDF117LH RSCAN0.RMDF117.UINT8[LH] +#define RSCAN0RMDF117H RSCAN0.RMDF117.UINT16[H] +#define RSCAN0RMDF117HL RSCAN0.RMDF117.UINT8[HL] +#define RSCAN0RMDF117HH RSCAN0.RMDF117.UINT8[HH] +#define RSCAN0RMID18 RSCAN0.RMID18.UINT32 +#define RSCAN0RMID18L RSCAN0.RMID18.UINT16[L] +#define RSCAN0RMID18LL RSCAN0.RMID18.UINT8[LL] +#define RSCAN0RMID18LH RSCAN0.RMID18.UINT8[LH] +#define RSCAN0RMID18H RSCAN0.RMID18.UINT16[H] +#define RSCAN0RMID18HL RSCAN0.RMID18.UINT8[HL] +#define RSCAN0RMID18HH RSCAN0.RMID18.UINT8[HH] +#define RSCAN0RMPTR18 RSCAN0.RMPTR18.UINT32 +#define RSCAN0RMPTR18L RSCAN0.RMPTR18.UINT16[L] +#define RSCAN0RMPTR18LL RSCAN0.RMPTR18.UINT8[LL] +#define RSCAN0RMPTR18LH RSCAN0.RMPTR18.UINT8[LH] +#define RSCAN0RMPTR18H RSCAN0.RMPTR18.UINT16[H] +#define RSCAN0RMPTR18HL RSCAN0.RMPTR18.UINT8[HL] +#define RSCAN0RMPTR18HH RSCAN0.RMPTR18.UINT8[HH] +#define RSCAN0RMDF018 RSCAN0.RMDF018.UINT32 +#define RSCAN0RMDF018L RSCAN0.RMDF018.UINT16[L] +#define RSCAN0RMDF018LL RSCAN0.RMDF018.UINT8[LL] +#define RSCAN0RMDF018LH RSCAN0.RMDF018.UINT8[LH] +#define RSCAN0RMDF018H RSCAN0.RMDF018.UINT16[H] +#define RSCAN0RMDF018HL RSCAN0.RMDF018.UINT8[HL] +#define RSCAN0RMDF018HH RSCAN0.RMDF018.UINT8[HH] +#define RSCAN0RMDF118 RSCAN0.RMDF118.UINT32 +#define RSCAN0RMDF118L RSCAN0.RMDF118.UINT16[L] +#define RSCAN0RMDF118LL RSCAN0.RMDF118.UINT8[LL] +#define RSCAN0RMDF118LH RSCAN0.RMDF118.UINT8[LH] +#define RSCAN0RMDF118H RSCAN0.RMDF118.UINT16[H] +#define RSCAN0RMDF118HL RSCAN0.RMDF118.UINT8[HL] +#define RSCAN0RMDF118HH RSCAN0.RMDF118.UINT8[HH] +#define RSCAN0RMID19 RSCAN0.RMID19.UINT32 +#define RSCAN0RMID19L RSCAN0.RMID19.UINT16[L] +#define RSCAN0RMID19LL RSCAN0.RMID19.UINT8[LL] +#define RSCAN0RMID19LH RSCAN0.RMID19.UINT8[LH] +#define RSCAN0RMID19H RSCAN0.RMID19.UINT16[H] +#define RSCAN0RMID19HL RSCAN0.RMID19.UINT8[HL] +#define RSCAN0RMID19HH RSCAN0.RMID19.UINT8[HH] +#define RSCAN0RMPTR19 RSCAN0.RMPTR19.UINT32 +#define RSCAN0RMPTR19L RSCAN0.RMPTR19.UINT16[L] +#define RSCAN0RMPTR19LL RSCAN0.RMPTR19.UINT8[LL] +#define RSCAN0RMPTR19LH RSCAN0.RMPTR19.UINT8[LH] +#define RSCAN0RMPTR19H RSCAN0.RMPTR19.UINT16[H] +#define RSCAN0RMPTR19HL RSCAN0.RMPTR19.UINT8[HL] +#define RSCAN0RMPTR19HH RSCAN0.RMPTR19.UINT8[HH] +#define RSCAN0RMDF019 RSCAN0.RMDF019.UINT32 +#define RSCAN0RMDF019L RSCAN0.RMDF019.UINT16[L] +#define RSCAN0RMDF019LL RSCAN0.RMDF019.UINT8[LL] +#define RSCAN0RMDF019LH RSCAN0.RMDF019.UINT8[LH] +#define RSCAN0RMDF019H RSCAN0.RMDF019.UINT16[H] +#define RSCAN0RMDF019HL RSCAN0.RMDF019.UINT8[HL] +#define RSCAN0RMDF019HH RSCAN0.RMDF019.UINT8[HH] +#define RSCAN0RMDF119 RSCAN0.RMDF119.UINT32 +#define RSCAN0RMDF119L RSCAN0.RMDF119.UINT16[L] +#define RSCAN0RMDF119LL RSCAN0.RMDF119.UINT8[LL] +#define RSCAN0RMDF119LH RSCAN0.RMDF119.UINT8[LH] +#define RSCAN0RMDF119H RSCAN0.RMDF119.UINT16[H] +#define RSCAN0RMDF119HL RSCAN0.RMDF119.UINT8[HL] +#define RSCAN0RMDF119HH RSCAN0.RMDF119.UINT8[HH] +#define RSCAN0RMID20 RSCAN0.RMID20.UINT32 +#define RSCAN0RMID20L RSCAN0.RMID20.UINT16[L] +#define RSCAN0RMID20LL RSCAN0.RMID20.UINT8[LL] +#define RSCAN0RMID20LH RSCAN0.RMID20.UINT8[LH] +#define RSCAN0RMID20H RSCAN0.RMID20.UINT16[H] +#define RSCAN0RMID20HL RSCAN0.RMID20.UINT8[HL] +#define RSCAN0RMID20HH RSCAN0.RMID20.UINT8[HH] +#define RSCAN0RMPTR20 RSCAN0.RMPTR20.UINT32 +#define RSCAN0RMPTR20L RSCAN0.RMPTR20.UINT16[L] +#define RSCAN0RMPTR20LL RSCAN0.RMPTR20.UINT8[LL] +#define RSCAN0RMPTR20LH RSCAN0.RMPTR20.UINT8[LH] +#define RSCAN0RMPTR20H RSCAN0.RMPTR20.UINT16[H] +#define RSCAN0RMPTR20HL RSCAN0.RMPTR20.UINT8[HL] +#define RSCAN0RMPTR20HH RSCAN0.RMPTR20.UINT8[HH] +#define RSCAN0RMDF020 RSCAN0.RMDF020.UINT32 +#define RSCAN0RMDF020L RSCAN0.RMDF020.UINT16[L] +#define RSCAN0RMDF020LL RSCAN0.RMDF020.UINT8[LL] +#define RSCAN0RMDF020LH RSCAN0.RMDF020.UINT8[LH] +#define RSCAN0RMDF020H RSCAN0.RMDF020.UINT16[H] +#define RSCAN0RMDF020HL RSCAN0.RMDF020.UINT8[HL] +#define RSCAN0RMDF020HH RSCAN0.RMDF020.UINT8[HH] +#define RSCAN0RMDF120 RSCAN0.RMDF120.UINT32 +#define RSCAN0RMDF120L RSCAN0.RMDF120.UINT16[L] +#define RSCAN0RMDF120LL RSCAN0.RMDF120.UINT8[LL] +#define RSCAN0RMDF120LH RSCAN0.RMDF120.UINT8[LH] +#define RSCAN0RMDF120H RSCAN0.RMDF120.UINT16[H] +#define RSCAN0RMDF120HL RSCAN0.RMDF120.UINT8[HL] +#define RSCAN0RMDF120HH RSCAN0.RMDF120.UINT8[HH] +#define RSCAN0RMID21 RSCAN0.RMID21.UINT32 +#define RSCAN0RMID21L RSCAN0.RMID21.UINT16[L] +#define RSCAN0RMID21LL RSCAN0.RMID21.UINT8[LL] +#define RSCAN0RMID21LH RSCAN0.RMID21.UINT8[LH] +#define RSCAN0RMID21H RSCAN0.RMID21.UINT16[H] +#define RSCAN0RMID21HL RSCAN0.RMID21.UINT8[HL] +#define RSCAN0RMID21HH RSCAN0.RMID21.UINT8[HH] +#define RSCAN0RMPTR21 RSCAN0.RMPTR21.UINT32 +#define RSCAN0RMPTR21L RSCAN0.RMPTR21.UINT16[L] +#define RSCAN0RMPTR21LL RSCAN0.RMPTR21.UINT8[LL] +#define RSCAN0RMPTR21LH RSCAN0.RMPTR21.UINT8[LH] +#define RSCAN0RMPTR21H RSCAN0.RMPTR21.UINT16[H] +#define RSCAN0RMPTR21HL RSCAN0.RMPTR21.UINT8[HL] +#define RSCAN0RMPTR21HH RSCAN0.RMPTR21.UINT8[HH] +#define RSCAN0RMDF021 RSCAN0.RMDF021.UINT32 +#define RSCAN0RMDF021L RSCAN0.RMDF021.UINT16[L] +#define RSCAN0RMDF021LL RSCAN0.RMDF021.UINT8[LL] +#define RSCAN0RMDF021LH RSCAN0.RMDF021.UINT8[LH] +#define RSCAN0RMDF021H RSCAN0.RMDF021.UINT16[H] +#define RSCAN0RMDF021HL RSCAN0.RMDF021.UINT8[HL] +#define RSCAN0RMDF021HH RSCAN0.RMDF021.UINT8[HH] +#define RSCAN0RMDF121 RSCAN0.RMDF121.UINT32 +#define RSCAN0RMDF121L RSCAN0.RMDF121.UINT16[L] +#define RSCAN0RMDF121LL RSCAN0.RMDF121.UINT8[LL] +#define RSCAN0RMDF121LH RSCAN0.RMDF121.UINT8[LH] +#define RSCAN0RMDF121H RSCAN0.RMDF121.UINT16[H] +#define RSCAN0RMDF121HL RSCAN0.RMDF121.UINT8[HL] +#define RSCAN0RMDF121HH RSCAN0.RMDF121.UINT8[HH] +#define RSCAN0RMID22 RSCAN0.RMID22.UINT32 +#define RSCAN0RMID22L RSCAN0.RMID22.UINT16[L] +#define RSCAN0RMID22LL RSCAN0.RMID22.UINT8[LL] +#define RSCAN0RMID22LH RSCAN0.RMID22.UINT8[LH] +#define RSCAN0RMID22H RSCAN0.RMID22.UINT16[H] +#define RSCAN0RMID22HL RSCAN0.RMID22.UINT8[HL] +#define RSCAN0RMID22HH RSCAN0.RMID22.UINT8[HH] +#define RSCAN0RMPTR22 RSCAN0.RMPTR22.UINT32 +#define RSCAN0RMPTR22L RSCAN0.RMPTR22.UINT16[L] +#define RSCAN0RMPTR22LL RSCAN0.RMPTR22.UINT8[LL] +#define RSCAN0RMPTR22LH RSCAN0.RMPTR22.UINT8[LH] +#define RSCAN0RMPTR22H RSCAN0.RMPTR22.UINT16[H] +#define RSCAN0RMPTR22HL RSCAN0.RMPTR22.UINT8[HL] +#define RSCAN0RMPTR22HH RSCAN0.RMPTR22.UINT8[HH] +#define RSCAN0RMDF022 RSCAN0.RMDF022.UINT32 +#define RSCAN0RMDF022L RSCAN0.RMDF022.UINT16[L] +#define RSCAN0RMDF022LL RSCAN0.RMDF022.UINT8[LL] +#define RSCAN0RMDF022LH RSCAN0.RMDF022.UINT8[LH] +#define RSCAN0RMDF022H RSCAN0.RMDF022.UINT16[H] +#define RSCAN0RMDF022HL RSCAN0.RMDF022.UINT8[HL] +#define RSCAN0RMDF022HH RSCAN0.RMDF022.UINT8[HH] +#define RSCAN0RMDF122 RSCAN0.RMDF122.UINT32 +#define RSCAN0RMDF122L RSCAN0.RMDF122.UINT16[L] +#define RSCAN0RMDF122LL RSCAN0.RMDF122.UINT8[LL] +#define RSCAN0RMDF122LH RSCAN0.RMDF122.UINT8[LH] +#define RSCAN0RMDF122H RSCAN0.RMDF122.UINT16[H] +#define RSCAN0RMDF122HL RSCAN0.RMDF122.UINT8[HL] +#define RSCAN0RMDF122HH RSCAN0.RMDF122.UINT8[HH] +#define RSCAN0RMID23 RSCAN0.RMID23.UINT32 +#define RSCAN0RMID23L RSCAN0.RMID23.UINT16[L] +#define RSCAN0RMID23LL RSCAN0.RMID23.UINT8[LL] +#define RSCAN0RMID23LH RSCAN0.RMID23.UINT8[LH] +#define RSCAN0RMID23H RSCAN0.RMID23.UINT16[H] +#define RSCAN0RMID23HL RSCAN0.RMID23.UINT8[HL] +#define RSCAN0RMID23HH RSCAN0.RMID23.UINT8[HH] +#define RSCAN0RMPTR23 RSCAN0.RMPTR23.UINT32 +#define RSCAN0RMPTR23L RSCAN0.RMPTR23.UINT16[L] +#define RSCAN0RMPTR23LL RSCAN0.RMPTR23.UINT8[LL] +#define RSCAN0RMPTR23LH RSCAN0.RMPTR23.UINT8[LH] +#define RSCAN0RMPTR23H RSCAN0.RMPTR23.UINT16[H] +#define RSCAN0RMPTR23HL RSCAN0.RMPTR23.UINT8[HL] +#define RSCAN0RMPTR23HH RSCAN0.RMPTR23.UINT8[HH] +#define RSCAN0RMDF023 RSCAN0.RMDF023.UINT32 +#define RSCAN0RMDF023L RSCAN0.RMDF023.UINT16[L] +#define RSCAN0RMDF023LL RSCAN0.RMDF023.UINT8[LL] +#define RSCAN0RMDF023LH RSCAN0.RMDF023.UINT8[LH] +#define RSCAN0RMDF023H RSCAN0.RMDF023.UINT16[H] +#define RSCAN0RMDF023HL RSCAN0.RMDF023.UINT8[HL] +#define RSCAN0RMDF023HH RSCAN0.RMDF023.UINT8[HH] +#define RSCAN0RMDF123 RSCAN0.RMDF123.UINT32 +#define RSCAN0RMDF123L RSCAN0.RMDF123.UINT16[L] +#define RSCAN0RMDF123LL RSCAN0.RMDF123.UINT8[LL] +#define RSCAN0RMDF123LH RSCAN0.RMDF123.UINT8[LH] +#define RSCAN0RMDF123H RSCAN0.RMDF123.UINT16[H] +#define RSCAN0RMDF123HL RSCAN0.RMDF123.UINT8[HL] +#define RSCAN0RMDF123HH RSCAN0.RMDF123.UINT8[HH] +#define RSCAN0RMID24 RSCAN0.RMID24.UINT32 +#define RSCAN0RMID24L RSCAN0.RMID24.UINT16[L] +#define RSCAN0RMID24LL RSCAN0.RMID24.UINT8[LL] +#define RSCAN0RMID24LH RSCAN0.RMID24.UINT8[LH] +#define RSCAN0RMID24H RSCAN0.RMID24.UINT16[H] +#define RSCAN0RMID24HL RSCAN0.RMID24.UINT8[HL] +#define RSCAN0RMID24HH RSCAN0.RMID24.UINT8[HH] +#define RSCAN0RMPTR24 RSCAN0.RMPTR24.UINT32 +#define RSCAN0RMPTR24L RSCAN0.RMPTR24.UINT16[L] +#define RSCAN0RMPTR24LL RSCAN0.RMPTR24.UINT8[LL] +#define RSCAN0RMPTR24LH RSCAN0.RMPTR24.UINT8[LH] +#define RSCAN0RMPTR24H RSCAN0.RMPTR24.UINT16[H] +#define RSCAN0RMPTR24HL RSCAN0.RMPTR24.UINT8[HL] +#define RSCAN0RMPTR24HH RSCAN0.RMPTR24.UINT8[HH] +#define RSCAN0RMDF024 RSCAN0.RMDF024.UINT32 +#define RSCAN0RMDF024L RSCAN0.RMDF024.UINT16[L] +#define RSCAN0RMDF024LL RSCAN0.RMDF024.UINT8[LL] +#define RSCAN0RMDF024LH RSCAN0.RMDF024.UINT8[LH] +#define RSCAN0RMDF024H RSCAN0.RMDF024.UINT16[H] +#define RSCAN0RMDF024HL RSCAN0.RMDF024.UINT8[HL] +#define RSCAN0RMDF024HH RSCAN0.RMDF024.UINT8[HH] +#define RSCAN0RMDF124 RSCAN0.RMDF124.UINT32 +#define RSCAN0RMDF124L RSCAN0.RMDF124.UINT16[L] +#define RSCAN0RMDF124LL RSCAN0.RMDF124.UINT8[LL] +#define RSCAN0RMDF124LH RSCAN0.RMDF124.UINT8[LH] +#define RSCAN0RMDF124H RSCAN0.RMDF124.UINT16[H] +#define RSCAN0RMDF124HL RSCAN0.RMDF124.UINT8[HL] +#define RSCAN0RMDF124HH RSCAN0.RMDF124.UINT8[HH] +#define RSCAN0RMID25 RSCAN0.RMID25.UINT32 +#define RSCAN0RMID25L RSCAN0.RMID25.UINT16[L] +#define RSCAN0RMID25LL RSCAN0.RMID25.UINT8[LL] +#define RSCAN0RMID25LH RSCAN0.RMID25.UINT8[LH] +#define RSCAN0RMID25H RSCAN0.RMID25.UINT16[H] +#define RSCAN0RMID25HL RSCAN0.RMID25.UINT8[HL] +#define RSCAN0RMID25HH RSCAN0.RMID25.UINT8[HH] +#define RSCAN0RMPTR25 RSCAN0.RMPTR25.UINT32 +#define RSCAN0RMPTR25L RSCAN0.RMPTR25.UINT16[L] +#define RSCAN0RMPTR25LL RSCAN0.RMPTR25.UINT8[LL] +#define RSCAN0RMPTR25LH RSCAN0.RMPTR25.UINT8[LH] +#define RSCAN0RMPTR25H RSCAN0.RMPTR25.UINT16[H] +#define RSCAN0RMPTR25HL RSCAN0.RMPTR25.UINT8[HL] +#define RSCAN0RMPTR25HH RSCAN0.RMPTR25.UINT8[HH] +#define RSCAN0RMDF025 RSCAN0.RMDF025.UINT32 +#define RSCAN0RMDF025L RSCAN0.RMDF025.UINT16[L] +#define RSCAN0RMDF025LL RSCAN0.RMDF025.UINT8[LL] +#define RSCAN0RMDF025LH RSCAN0.RMDF025.UINT8[LH] +#define RSCAN0RMDF025H RSCAN0.RMDF025.UINT16[H] +#define RSCAN0RMDF025HL RSCAN0.RMDF025.UINT8[HL] +#define RSCAN0RMDF025HH RSCAN0.RMDF025.UINT8[HH] +#define RSCAN0RMDF125 RSCAN0.RMDF125.UINT32 +#define RSCAN0RMDF125L RSCAN0.RMDF125.UINT16[L] +#define RSCAN0RMDF125LL RSCAN0.RMDF125.UINT8[LL] +#define RSCAN0RMDF125LH RSCAN0.RMDF125.UINT8[LH] +#define RSCAN0RMDF125H RSCAN0.RMDF125.UINT16[H] +#define RSCAN0RMDF125HL RSCAN0.RMDF125.UINT8[HL] +#define RSCAN0RMDF125HH RSCAN0.RMDF125.UINT8[HH] +#define RSCAN0RMID26 RSCAN0.RMID26.UINT32 +#define RSCAN0RMID26L RSCAN0.RMID26.UINT16[L] +#define RSCAN0RMID26LL RSCAN0.RMID26.UINT8[LL] +#define RSCAN0RMID26LH RSCAN0.RMID26.UINT8[LH] +#define RSCAN0RMID26H RSCAN0.RMID26.UINT16[H] +#define RSCAN0RMID26HL RSCAN0.RMID26.UINT8[HL] +#define RSCAN0RMID26HH RSCAN0.RMID26.UINT8[HH] +#define RSCAN0RMPTR26 RSCAN0.RMPTR26.UINT32 +#define RSCAN0RMPTR26L RSCAN0.RMPTR26.UINT16[L] +#define RSCAN0RMPTR26LL RSCAN0.RMPTR26.UINT8[LL] +#define RSCAN0RMPTR26LH RSCAN0.RMPTR26.UINT8[LH] +#define RSCAN0RMPTR26H RSCAN0.RMPTR26.UINT16[H] +#define RSCAN0RMPTR26HL RSCAN0.RMPTR26.UINT8[HL] +#define RSCAN0RMPTR26HH RSCAN0.RMPTR26.UINT8[HH] +#define RSCAN0RMDF026 RSCAN0.RMDF026.UINT32 +#define RSCAN0RMDF026L RSCAN0.RMDF026.UINT16[L] +#define RSCAN0RMDF026LL RSCAN0.RMDF026.UINT8[LL] +#define RSCAN0RMDF026LH RSCAN0.RMDF026.UINT8[LH] +#define RSCAN0RMDF026H RSCAN0.RMDF026.UINT16[H] +#define RSCAN0RMDF026HL RSCAN0.RMDF026.UINT8[HL] +#define RSCAN0RMDF026HH RSCAN0.RMDF026.UINT8[HH] +#define RSCAN0RMDF126 RSCAN0.RMDF126.UINT32 +#define RSCAN0RMDF126L RSCAN0.RMDF126.UINT16[L] +#define RSCAN0RMDF126LL RSCAN0.RMDF126.UINT8[LL] +#define RSCAN0RMDF126LH RSCAN0.RMDF126.UINT8[LH] +#define RSCAN0RMDF126H RSCAN0.RMDF126.UINT16[H] +#define RSCAN0RMDF126HL RSCAN0.RMDF126.UINT8[HL] +#define RSCAN0RMDF126HH RSCAN0.RMDF126.UINT8[HH] +#define RSCAN0RMID27 RSCAN0.RMID27.UINT32 +#define RSCAN0RMID27L RSCAN0.RMID27.UINT16[L] +#define RSCAN0RMID27LL RSCAN0.RMID27.UINT8[LL] +#define RSCAN0RMID27LH RSCAN0.RMID27.UINT8[LH] +#define RSCAN0RMID27H RSCAN0.RMID27.UINT16[H] +#define RSCAN0RMID27HL RSCAN0.RMID27.UINT8[HL] +#define RSCAN0RMID27HH RSCAN0.RMID27.UINT8[HH] +#define RSCAN0RMPTR27 RSCAN0.RMPTR27.UINT32 +#define RSCAN0RMPTR27L RSCAN0.RMPTR27.UINT16[L] +#define RSCAN0RMPTR27LL RSCAN0.RMPTR27.UINT8[LL] +#define RSCAN0RMPTR27LH RSCAN0.RMPTR27.UINT8[LH] +#define RSCAN0RMPTR27H RSCAN0.RMPTR27.UINT16[H] +#define RSCAN0RMPTR27HL RSCAN0.RMPTR27.UINT8[HL] +#define RSCAN0RMPTR27HH RSCAN0.RMPTR27.UINT8[HH] +#define RSCAN0RMDF027 RSCAN0.RMDF027.UINT32 +#define RSCAN0RMDF027L RSCAN0.RMDF027.UINT16[L] +#define RSCAN0RMDF027LL RSCAN0.RMDF027.UINT8[LL] +#define RSCAN0RMDF027LH RSCAN0.RMDF027.UINT8[LH] +#define RSCAN0RMDF027H RSCAN0.RMDF027.UINT16[H] +#define RSCAN0RMDF027HL RSCAN0.RMDF027.UINT8[HL] +#define RSCAN0RMDF027HH RSCAN0.RMDF027.UINT8[HH] +#define RSCAN0RMDF127 RSCAN0.RMDF127.UINT32 +#define RSCAN0RMDF127L RSCAN0.RMDF127.UINT16[L] +#define RSCAN0RMDF127LL RSCAN0.RMDF127.UINT8[LL] +#define RSCAN0RMDF127LH RSCAN0.RMDF127.UINT8[LH] +#define RSCAN0RMDF127H RSCAN0.RMDF127.UINT16[H] +#define RSCAN0RMDF127HL RSCAN0.RMDF127.UINT8[HL] +#define RSCAN0RMDF127HH RSCAN0.RMDF127.UINT8[HH] +#define RSCAN0RMID28 RSCAN0.RMID28.UINT32 +#define RSCAN0RMID28L RSCAN0.RMID28.UINT16[L] +#define RSCAN0RMID28LL RSCAN0.RMID28.UINT8[LL] +#define RSCAN0RMID28LH RSCAN0.RMID28.UINT8[LH] +#define RSCAN0RMID28H RSCAN0.RMID28.UINT16[H] +#define RSCAN0RMID28HL RSCAN0.RMID28.UINT8[HL] +#define RSCAN0RMID28HH RSCAN0.RMID28.UINT8[HH] +#define RSCAN0RMPTR28 RSCAN0.RMPTR28.UINT32 +#define RSCAN0RMPTR28L RSCAN0.RMPTR28.UINT16[L] +#define RSCAN0RMPTR28LL RSCAN0.RMPTR28.UINT8[LL] +#define RSCAN0RMPTR28LH RSCAN0.RMPTR28.UINT8[LH] +#define RSCAN0RMPTR28H RSCAN0.RMPTR28.UINT16[H] +#define RSCAN0RMPTR28HL RSCAN0.RMPTR28.UINT8[HL] +#define RSCAN0RMPTR28HH RSCAN0.RMPTR28.UINT8[HH] +#define RSCAN0RMDF028 RSCAN0.RMDF028.UINT32 +#define RSCAN0RMDF028L RSCAN0.RMDF028.UINT16[L] +#define RSCAN0RMDF028LL RSCAN0.RMDF028.UINT8[LL] +#define RSCAN0RMDF028LH RSCAN0.RMDF028.UINT8[LH] +#define RSCAN0RMDF028H RSCAN0.RMDF028.UINT16[H] +#define RSCAN0RMDF028HL RSCAN0.RMDF028.UINT8[HL] +#define RSCAN0RMDF028HH RSCAN0.RMDF028.UINT8[HH] +#define RSCAN0RMDF128 RSCAN0.RMDF128.UINT32 +#define RSCAN0RMDF128L RSCAN0.RMDF128.UINT16[L] +#define RSCAN0RMDF128LL RSCAN0.RMDF128.UINT8[LL] +#define RSCAN0RMDF128LH RSCAN0.RMDF128.UINT8[LH] +#define RSCAN0RMDF128H RSCAN0.RMDF128.UINT16[H] +#define RSCAN0RMDF128HL RSCAN0.RMDF128.UINT8[HL] +#define RSCAN0RMDF128HH RSCAN0.RMDF128.UINT8[HH] +#define RSCAN0RMID29 RSCAN0.RMID29.UINT32 +#define RSCAN0RMID29L RSCAN0.RMID29.UINT16[L] +#define RSCAN0RMID29LL RSCAN0.RMID29.UINT8[LL] +#define RSCAN0RMID29LH RSCAN0.RMID29.UINT8[LH] +#define RSCAN0RMID29H RSCAN0.RMID29.UINT16[H] +#define RSCAN0RMID29HL RSCAN0.RMID29.UINT8[HL] +#define RSCAN0RMID29HH RSCAN0.RMID29.UINT8[HH] +#define RSCAN0RMPTR29 RSCAN0.RMPTR29.UINT32 +#define RSCAN0RMPTR29L RSCAN0.RMPTR29.UINT16[L] +#define RSCAN0RMPTR29LL RSCAN0.RMPTR29.UINT8[LL] +#define RSCAN0RMPTR29LH RSCAN0.RMPTR29.UINT8[LH] +#define RSCAN0RMPTR29H RSCAN0.RMPTR29.UINT16[H] +#define RSCAN0RMPTR29HL RSCAN0.RMPTR29.UINT8[HL] +#define RSCAN0RMPTR29HH RSCAN0.RMPTR29.UINT8[HH] +#define RSCAN0RMDF029 RSCAN0.RMDF029.UINT32 +#define RSCAN0RMDF029L RSCAN0.RMDF029.UINT16[L] +#define RSCAN0RMDF029LL RSCAN0.RMDF029.UINT8[LL] +#define RSCAN0RMDF029LH RSCAN0.RMDF029.UINT8[LH] +#define RSCAN0RMDF029H RSCAN0.RMDF029.UINT16[H] +#define RSCAN0RMDF029HL RSCAN0.RMDF029.UINT8[HL] +#define RSCAN0RMDF029HH RSCAN0.RMDF029.UINT8[HH] +#define RSCAN0RMDF129 RSCAN0.RMDF129.UINT32 +#define RSCAN0RMDF129L RSCAN0.RMDF129.UINT16[L] +#define RSCAN0RMDF129LL RSCAN0.RMDF129.UINT8[LL] +#define RSCAN0RMDF129LH RSCAN0.RMDF129.UINT8[LH] +#define RSCAN0RMDF129H RSCAN0.RMDF129.UINT16[H] +#define RSCAN0RMDF129HL RSCAN0.RMDF129.UINT8[HL] +#define RSCAN0RMDF129HH RSCAN0.RMDF129.UINT8[HH] +#define RSCAN0RMID30 RSCAN0.RMID30.UINT32 +#define RSCAN0RMID30L RSCAN0.RMID30.UINT16[L] +#define RSCAN0RMID30LL RSCAN0.RMID30.UINT8[LL] +#define RSCAN0RMID30LH RSCAN0.RMID30.UINT8[LH] +#define RSCAN0RMID30H RSCAN0.RMID30.UINT16[H] +#define RSCAN0RMID30HL RSCAN0.RMID30.UINT8[HL] +#define RSCAN0RMID30HH RSCAN0.RMID30.UINT8[HH] +#define RSCAN0RMPTR30 RSCAN0.RMPTR30.UINT32 +#define RSCAN0RMPTR30L RSCAN0.RMPTR30.UINT16[L] +#define RSCAN0RMPTR30LL RSCAN0.RMPTR30.UINT8[LL] +#define RSCAN0RMPTR30LH RSCAN0.RMPTR30.UINT8[LH] +#define RSCAN0RMPTR30H RSCAN0.RMPTR30.UINT16[H] +#define RSCAN0RMPTR30HL RSCAN0.RMPTR30.UINT8[HL] +#define RSCAN0RMPTR30HH RSCAN0.RMPTR30.UINT8[HH] +#define RSCAN0RMDF030 RSCAN0.RMDF030.UINT32 +#define RSCAN0RMDF030L RSCAN0.RMDF030.UINT16[L] +#define RSCAN0RMDF030LL RSCAN0.RMDF030.UINT8[LL] +#define RSCAN0RMDF030LH RSCAN0.RMDF030.UINT8[LH] +#define RSCAN0RMDF030H RSCAN0.RMDF030.UINT16[H] +#define RSCAN0RMDF030HL RSCAN0.RMDF030.UINT8[HL] +#define RSCAN0RMDF030HH RSCAN0.RMDF030.UINT8[HH] +#define RSCAN0RMDF130 RSCAN0.RMDF130.UINT32 +#define RSCAN0RMDF130L RSCAN0.RMDF130.UINT16[L] +#define RSCAN0RMDF130LL RSCAN0.RMDF130.UINT8[LL] +#define RSCAN0RMDF130LH RSCAN0.RMDF130.UINT8[LH] +#define RSCAN0RMDF130H RSCAN0.RMDF130.UINT16[H] +#define RSCAN0RMDF130HL RSCAN0.RMDF130.UINT8[HL] +#define RSCAN0RMDF130HH RSCAN0.RMDF130.UINT8[HH] +#define RSCAN0RMID31 RSCAN0.RMID31.UINT32 +#define RSCAN0RMID31L RSCAN0.RMID31.UINT16[L] +#define RSCAN0RMID31LL RSCAN0.RMID31.UINT8[LL] +#define RSCAN0RMID31LH RSCAN0.RMID31.UINT8[LH] +#define RSCAN0RMID31H RSCAN0.RMID31.UINT16[H] +#define RSCAN0RMID31HL RSCAN0.RMID31.UINT8[HL] +#define RSCAN0RMID31HH RSCAN0.RMID31.UINT8[HH] +#define RSCAN0RMPTR31 RSCAN0.RMPTR31.UINT32 +#define RSCAN0RMPTR31L RSCAN0.RMPTR31.UINT16[L] +#define RSCAN0RMPTR31LL RSCAN0.RMPTR31.UINT8[LL] +#define RSCAN0RMPTR31LH RSCAN0.RMPTR31.UINT8[LH] +#define RSCAN0RMPTR31H RSCAN0.RMPTR31.UINT16[H] +#define RSCAN0RMPTR31HL RSCAN0.RMPTR31.UINT8[HL] +#define RSCAN0RMPTR31HH RSCAN0.RMPTR31.UINT8[HH] +#define RSCAN0RMDF031 RSCAN0.RMDF031.UINT32 +#define RSCAN0RMDF031L RSCAN0.RMDF031.UINT16[L] +#define RSCAN0RMDF031LL RSCAN0.RMDF031.UINT8[LL] +#define RSCAN0RMDF031LH RSCAN0.RMDF031.UINT8[LH] +#define RSCAN0RMDF031H RSCAN0.RMDF031.UINT16[H] +#define RSCAN0RMDF031HL RSCAN0.RMDF031.UINT8[HL] +#define RSCAN0RMDF031HH RSCAN0.RMDF031.UINT8[HH] +#define RSCAN0RMDF131 RSCAN0.RMDF131.UINT32 +#define RSCAN0RMDF131L RSCAN0.RMDF131.UINT16[L] +#define RSCAN0RMDF131LL RSCAN0.RMDF131.UINT8[LL] +#define RSCAN0RMDF131LH RSCAN0.RMDF131.UINT8[LH] +#define RSCAN0RMDF131H RSCAN0.RMDF131.UINT16[H] +#define RSCAN0RMDF131HL RSCAN0.RMDF131.UINT8[HL] +#define RSCAN0RMDF131HH RSCAN0.RMDF131.UINT8[HH] +#define RSCAN0RMID32 RSCAN0.RMID32.UINT32 +#define RSCAN0RMID32L RSCAN0.RMID32.UINT16[L] +#define RSCAN0RMID32LL RSCAN0.RMID32.UINT8[LL] +#define RSCAN0RMID32LH RSCAN0.RMID32.UINT8[LH] +#define RSCAN0RMID32H RSCAN0.RMID32.UINT16[H] +#define RSCAN0RMID32HL RSCAN0.RMID32.UINT8[HL] +#define RSCAN0RMID32HH RSCAN0.RMID32.UINT8[HH] +#define RSCAN0RMPTR32 RSCAN0.RMPTR32.UINT32 +#define RSCAN0RMPTR32L RSCAN0.RMPTR32.UINT16[L] +#define RSCAN0RMPTR32LL RSCAN0.RMPTR32.UINT8[LL] +#define RSCAN0RMPTR32LH RSCAN0.RMPTR32.UINT8[LH] +#define RSCAN0RMPTR32H RSCAN0.RMPTR32.UINT16[H] +#define RSCAN0RMPTR32HL RSCAN0.RMPTR32.UINT8[HL] +#define RSCAN0RMPTR32HH RSCAN0.RMPTR32.UINT8[HH] +#define RSCAN0RMDF032 RSCAN0.RMDF032.UINT32 +#define RSCAN0RMDF032L RSCAN0.RMDF032.UINT16[L] +#define RSCAN0RMDF032LL RSCAN0.RMDF032.UINT8[LL] +#define RSCAN0RMDF032LH RSCAN0.RMDF032.UINT8[LH] +#define RSCAN0RMDF032H RSCAN0.RMDF032.UINT16[H] +#define RSCAN0RMDF032HL RSCAN0.RMDF032.UINT8[HL] +#define RSCAN0RMDF032HH RSCAN0.RMDF032.UINT8[HH] +#define RSCAN0RMDF132 RSCAN0.RMDF132.UINT32 +#define RSCAN0RMDF132L RSCAN0.RMDF132.UINT16[L] +#define RSCAN0RMDF132LL RSCAN0.RMDF132.UINT8[LL] +#define RSCAN0RMDF132LH RSCAN0.RMDF132.UINT8[LH] +#define RSCAN0RMDF132H RSCAN0.RMDF132.UINT16[H] +#define RSCAN0RMDF132HL RSCAN0.RMDF132.UINT8[HL] +#define RSCAN0RMDF132HH RSCAN0.RMDF132.UINT8[HH] +#define RSCAN0RMID33 RSCAN0.RMID33.UINT32 +#define RSCAN0RMID33L RSCAN0.RMID33.UINT16[L] +#define RSCAN0RMID33LL RSCAN0.RMID33.UINT8[LL] +#define RSCAN0RMID33LH RSCAN0.RMID33.UINT8[LH] +#define RSCAN0RMID33H RSCAN0.RMID33.UINT16[H] +#define RSCAN0RMID33HL RSCAN0.RMID33.UINT8[HL] +#define RSCAN0RMID33HH RSCAN0.RMID33.UINT8[HH] +#define RSCAN0RMPTR33 RSCAN0.RMPTR33.UINT32 +#define RSCAN0RMPTR33L RSCAN0.RMPTR33.UINT16[L] +#define RSCAN0RMPTR33LL RSCAN0.RMPTR33.UINT8[LL] +#define RSCAN0RMPTR33LH RSCAN0.RMPTR33.UINT8[LH] +#define RSCAN0RMPTR33H RSCAN0.RMPTR33.UINT16[H] +#define RSCAN0RMPTR33HL RSCAN0.RMPTR33.UINT8[HL] +#define RSCAN0RMPTR33HH RSCAN0.RMPTR33.UINT8[HH] +#define RSCAN0RMDF033 RSCAN0.RMDF033.UINT32 +#define RSCAN0RMDF033L RSCAN0.RMDF033.UINT16[L] +#define RSCAN0RMDF033LL RSCAN0.RMDF033.UINT8[LL] +#define RSCAN0RMDF033LH RSCAN0.RMDF033.UINT8[LH] +#define RSCAN0RMDF033H RSCAN0.RMDF033.UINT16[H] +#define RSCAN0RMDF033HL RSCAN0.RMDF033.UINT8[HL] +#define RSCAN0RMDF033HH RSCAN0.RMDF033.UINT8[HH] +#define RSCAN0RMDF133 RSCAN0.RMDF133.UINT32 +#define RSCAN0RMDF133L RSCAN0.RMDF133.UINT16[L] +#define RSCAN0RMDF133LL RSCAN0.RMDF133.UINT8[LL] +#define RSCAN0RMDF133LH RSCAN0.RMDF133.UINT8[LH] +#define RSCAN0RMDF133H RSCAN0.RMDF133.UINT16[H] +#define RSCAN0RMDF133HL RSCAN0.RMDF133.UINT8[HL] +#define RSCAN0RMDF133HH RSCAN0.RMDF133.UINT8[HH] +#define RSCAN0RMID34 RSCAN0.RMID34.UINT32 +#define RSCAN0RMID34L RSCAN0.RMID34.UINT16[L] +#define RSCAN0RMID34LL RSCAN0.RMID34.UINT8[LL] +#define RSCAN0RMID34LH RSCAN0.RMID34.UINT8[LH] +#define RSCAN0RMID34H RSCAN0.RMID34.UINT16[H] +#define RSCAN0RMID34HL RSCAN0.RMID34.UINT8[HL] +#define RSCAN0RMID34HH RSCAN0.RMID34.UINT8[HH] +#define RSCAN0RMPTR34 RSCAN0.RMPTR34.UINT32 +#define RSCAN0RMPTR34L RSCAN0.RMPTR34.UINT16[L] +#define RSCAN0RMPTR34LL RSCAN0.RMPTR34.UINT8[LL] +#define RSCAN0RMPTR34LH RSCAN0.RMPTR34.UINT8[LH] +#define RSCAN0RMPTR34H RSCAN0.RMPTR34.UINT16[H] +#define RSCAN0RMPTR34HL RSCAN0.RMPTR34.UINT8[HL] +#define RSCAN0RMPTR34HH RSCAN0.RMPTR34.UINT8[HH] +#define RSCAN0RMDF034 RSCAN0.RMDF034.UINT32 +#define RSCAN0RMDF034L RSCAN0.RMDF034.UINT16[L] +#define RSCAN0RMDF034LL RSCAN0.RMDF034.UINT8[LL] +#define RSCAN0RMDF034LH RSCAN0.RMDF034.UINT8[LH] +#define RSCAN0RMDF034H RSCAN0.RMDF034.UINT16[H] +#define RSCAN0RMDF034HL RSCAN0.RMDF034.UINT8[HL] +#define RSCAN0RMDF034HH RSCAN0.RMDF034.UINT8[HH] +#define RSCAN0RMDF134 RSCAN0.RMDF134.UINT32 +#define RSCAN0RMDF134L RSCAN0.RMDF134.UINT16[L] +#define RSCAN0RMDF134LL RSCAN0.RMDF134.UINT8[LL] +#define RSCAN0RMDF134LH RSCAN0.RMDF134.UINT8[LH] +#define RSCAN0RMDF134H RSCAN0.RMDF134.UINT16[H] +#define RSCAN0RMDF134HL RSCAN0.RMDF134.UINT8[HL] +#define RSCAN0RMDF134HH RSCAN0.RMDF134.UINT8[HH] +#define RSCAN0RMID35 RSCAN0.RMID35.UINT32 +#define RSCAN0RMID35L RSCAN0.RMID35.UINT16[L] +#define RSCAN0RMID35LL RSCAN0.RMID35.UINT8[LL] +#define RSCAN0RMID35LH RSCAN0.RMID35.UINT8[LH] +#define RSCAN0RMID35H RSCAN0.RMID35.UINT16[H] +#define RSCAN0RMID35HL RSCAN0.RMID35.UINT8[HL] +#define RSCAN0RMID35HH RSCAN0.RMID35.UINT8[HH] +#define RSCAN0RMPTR35 RSCAN0.RMPTR35.UINT32 +#define RSCAN0RMPTR35L RSCAN0.RMPTR35.UINT16[L] +#define RSCAN0RMPTR35LL RSCAN0.RMPTR35.UINT8[LL] +#define RSCAN0RMPTR35LH RSCAN0.RMPTR35.UINT8[LH] +#define RSCAN0RMPTR35H RSCAN0.RMPTR35.UINT16[H] +#define RSCAN0RMPTR35HL RSCAN0.RMPTR35.UINT8[HL] +#define RSCAN0RMPTR35HH RSCAN0.RMPTR35.UINT8[HH] +#define RSCAN0RMDF035 RSCAN0.RMDF035.UINT32 +#define RSCAN0RMDF035L RSCAN0.RMDF035.UINT16[L] +#define RSCAN0RMDF035LL RSCAN0.RMDF035.UINT8[LL] +#define RSCAN0RMDF035LH RSCAN0.RMDF035.UINT8[LH] +#define RSCAN0RMDF035H RSCAN0.RMDF035.UINT16[H] +#define RSCAN0RMDF035HL RSCAN0.RMDF035.UINT8[HL] +#define RSCAN0RMDF035HH RSCAN0.RMDF035.UINT8[HH] +#define RSCAN0RMDF135 RSCAN0.RMDF135.UINT32 +#define RSCAN0RMDF135L RSCAN0.RMDF135.UINT16[L] +#define RSCAN0RMDF135LL RSCAN0.RMDF135.UINT8[LL] +#define RSCAN0RMDF135LH RSCAN0.RMDF135.UINT8[LH] +#define RSCAN0RMDF135H RSCAN0.RMDF135.UINT16[H] +#define RSCAN0RMDF135HL RSCAN0.RMDF135.UINT8[HL] +#define RSCAN0RMDF135HH RSCAN0.RMDF135.UINT8[HH] +#define RSCAN0RMID36 RSCAN0.RMID36.UINT32 +#define RSCAN0RMID36L RSCAN0.RMID36.UINT16[L] +#define RSCAN0RMID36LL RSCAN0.RMID36.UINT8[LL] +#define RSCAN0RMID36LH RSCAN0.RMID36.UINT8[LH] +#define RSCAN0RMID36H RSCAN0.RMID36.UINT16[H] +#define RSCAN0RMID36HL RSCAN0.RMID36.UINT8[HL] +#define RSCAN0RMID36HH RSCAN0.RMID36.UINT8[HH] +#define RSCAN0RMPTR36 RSCAN0.RMPTR36.UINT32 +#define RSCAN0RMPTR36L RSCAN0.RMPTR36.UINT16[L] +#define RSCAN0RMPTR36LL RSCAN0.RMPTR36.UINT8[LL] +#define RSCAN0RMPTR36LH RSCAN0.RMPTR36.UINT8[LH] +#define RSCAN0RMPTR36H RSCAN0.RMPTR36.UINT16[H] +#define RSCAN0RMPTR36HL RSCAN0.RMPTR36.UINT8[HL] +#define RSCAN0RMPTR36HH RSCAN0.RMPTR36.UINT8[HH] +#define RSCAN0RMDF036 RSCAN0.RMDF036.UINT32 +#define RSCAN0RMDF036L RSCAN0.RMDF036.UINT16[L] +#define RSCAN0RMDF036LL RSCAN0.RMDF036.UINT8[LL] +#define RSCAN0RMDF036LH RSCAN0.RMDF036.UINT8[LH] +#define RSCAN0RMDF036H RSCAN0.RMDF036.UINT16[H] +#define RSCAN0RMDF036HL RSCAN0.RMDF036.UINT8[HL] +#define RSCAN0RMDF036HH RSCAN0.RMDF036.UINT8[HH] +#define RSCAN0RMDF136 RSCAN0.RMDF136.UINT32 +#define RSCAN0RMDF136L RSCAN0.RMDF136.UINT16[L] +#define RSCAN0RMDF136LL RSCAN0.RMDF136.UINT8[LL] +#define RSCAN0RMDF136LH RSCAN0.RMDF136.UINT8[LH] +#define RSCAN0RMDF136H RSCAN0.RMDF136.UINT16[H] +#define RSCAN0RMDF136HL RSCAN0.RMDF136.UINT8[HL] +#define RSCAN0RMDF136HH RSCAN0.RMDF136.UINT8[HH] +#define RSCAN0RMID37 RSCAN0.RMID37.UINT32 +#define RSCAN0RMID37L RSCAN0.RMID37.UINT16[L] +#define RSCAN0RMID37LL RSCAN0.RMID37.UINT8[LL] +#define RSCAN0RMID37LH RSCAN0.RMID37.UINT8[LH] +#define RSCAN0RMID37H RSCAN0.RMID37.UINT16[H] +#define RSCAN0RMID37HL RSCAN0.RMID37.UINT8[HL] +#define RSCAN0RMID37HH RSCAN0.RMID37.UINT8[HH] +#define RSCAN0RMPTR37 RSCAN0.RMPTR37.UINT32 +#define RSCAN0RMPTR37L RSCAN0.RMPTR37.UINT16[L] +#define RSCAN0RMPTR37LL RSCAN0.RMPTR37.UINT8[LL] +#define RSCAN0RMPTR37LH RSCAN0.RMPTR37.UINT8[LH] +#define RSCAN0RMPTR37H RSCAN0.RMPTR37.UINT16[H] +#define RSCAN0RMPTR37HL RSCAN0.RMPTR37.UINT8[HL] +#define RSCAN0RMPTR37HH RSCAN0.RMPTR37.UINT8[HH] +#define RSCAN0RMDF037 RSCAN0.RMDF037.UINT32 +#define RSCAN0RMDF037L RSCAN0.RMDF037.UINT16[L] +#define RSCAN0RMDF037LL RSCAN0.RMDF037.UINT8[LL] +#define RSCAN0RMDF037LH RSCAN0.RMDF037.UINT8[LH] +#define RSCAN0RMDF037H RSCAN0.RMDF037.UINT16[H] +#define RSCAN0RMDF037HL RSCAN0.RMDF037.UINT8[HL] +#define RSCAN0RMDF037HH RSCAN0.RMDF037.UINT8[HH] +#define RSCAN0RMDF137 RSCAN0.RMDF137.UINT32 +#define RSCAN0RMDF137L RSCAN0.RMDF137.UINT16[L] +#define RSCAN0RMDF137LL RSCAN0.RMDF137.UINT8[LL] +#define RSCAN0RMDF137LH RSCAN0.RMDF137.UINT8[LH] +#define RSCAN0RMDF137H RSCAN0.RMDF137.UINT16[H] +#define RSCAN0RMDF137HL RSCAN0.RMDF137.UINT8[HL] +#define RSCAN0RMDF137HH RSCAN0.RMDF137.UINT8[HH] +#define RSCAN0RMID38 RSCAN0.RMID38.UINT32 +#define RSCAN0RMID38L RSCAN0.RMID38.UINT16[L] +#define RSCAN0RMID38LL RSCAN0.RMID38.UINT8[LL] +#define RSCAN0RMID38LH RSCAN0.RMID38.UINT8[LH] +#define RSCAN0RMID38H RSCAN0.RMID38.UINT16[H] +#define RSCAN0RMID38HL RSCAN0.RMID38.UINT8[HL] +#define RSCAN0RMID38HH RSCAN0.RMID38.UINT8[HH] +#define RSCAN0RMPTR38 RSCAN0.RMPTR38.UINT32 +#define RSCAN0RMPTR38L RSCAN0.RMPTR38.UINT16[L] +#define RSCAN0RMPTR38LL RSCAN0.RMPTR38.UINT8[LL] +#define RSCAN0RMPTR38LH RSCAN0.RMPTR38.UINT8[LH] +#define RSCAN0RMPTR38H RSCAN0.RMPTR38.UINT16[H] +#define RSCAN0RMPTR38HL RSCAN0.RMPTR38.UINT8[HL] +#define RSCAN0RMPTR38HH RSCAN0.RMPTR38.UINT8[HH] +#define RSCAN0RMDF038 RSCAN0.RMDF038.UINT32 +#define RSCAN0RMDF038L RSCAN0.RMDF038.UINT16[L] +#define RSCAN0RMDF038LL RSCAN0.RMDF038.UINT8[LL] +#define RSCAN0RMDF038LH RSCAN0.RMDF038.UINT8[LH] +#define RSCAN0RMDF038H RSCAN0.RMDF038.UINT16[H] +#define RSCAN0RMDF038HL RSCAN0.RMDF038.UINT8[HL] +#define RSCAN0RMDF038HH RSCAN0.RMDF038.UINT8[HH] +#define RSCAN0RMDF138 RSCAN0.RMDF138.UINT32 +#define RSCAN0RMDF138L RSCAN0.RMDF138.UINT16[L] +#define RSCAN0RMDF138LL RSCAN0.RMDF138.UINT8[LL] +#define RSCAN0RMDF138LH RSCAN0.RMDF138.UINT8[LH] +#define RSCAN0RMDF138H RSCAN0.RMDF138.UINT16[H] +#define RSCAN0RMDF138HL RSCAN0.RMDF138.UINT8[HL] +#define RSCAN0RMDF138HH RSCAN0.RMDF138.UINT8[HH] +#define RSCAN0RMID39 RSCAN0.RMID39.UINT32 +#define RSCAN0RMID39L RSCAN0.RMID39.UINT16[L] +#define RSCAN0RMID39LL RSCAN0.RMID39.UINT8[LL] +#define RSCAN0RMID39LH RSCAN0.RMID39.UINT8[LH] +#define RSCAN0RMID39H RSCAN0.RMID39.UINT16[H] +#define RSCAN0RMID39HL RSCAN0.RMID39.UINT8[HL] +#define RSCAN0RMID39HH RSCAN0.RMID39.UINT8[HH] +#define RSCAN0RMPTR39 RSCAN0.RMPTR39.UINT32 +#define RSCAN0RMPTR39L RSCAN0.RMPTR39.UINT16[L] +#define RSCAN0RMPTR39LL RSCAN0.RMPTR39.UINT8[LL] +#define RSCAN0RMPTR39LH RSCAN0.RMPTR39.UINT8[LH] +#define RSCAN0RMPTR39H RSCAN0.RMPTR39.UINT16[H] +#define RSCAN0RMPTR39HL RSCAN0.RMPTR39.UINT8[HL] +#define RSCAN0RMPTR39HH RSCAN0.RMPTR39.UINT8[HH] +#define RSCAN0RMDF039 RSCAN0.RMDF039.UINT32 +#define RSCAN0RMDF039L RSCAN0.RMDF039.UINT16[L] +#define RSCAN0RMDF039LL RSCAN0.RMDF039.UINT8[LL] +#define RSCAN0RMDF039LH RSCAN0.RMDF039.UINT8[LH] +#define RSCAN0RMDF039H RSCAN0.RMDF039.UINT16[H] +#define RSCAN0RMDF039HL RSCAN0.RMDF039.UINT8[HL] +#define RSCAN0RMDF039HH RSCAN0.RMDF039.UINT8[HH] +#define RSCAN0RMDF139 RSCAN0.RMDF139.UINT32 +#define RSCAN0RMDF139L RSCAN0.RMDF139.UINT16[L] +#define RSCAN0RMDF139LL RSCAN0.RMDF139.UINT8[LL] +#define RSCAN0RMDF139LH RSCAN0.RMDF139.UINT8[LH] +#define RSCAN0RMDF139H RSCAN0.RMDF139.UINT16[H] +#define RSCAN0RMDF139HL RSCAN0.RMDF139.UINT8[HL] +#define RSCAN0RMDF139HH RSCAN0.RMDF139.UINT8[HH] +#define RSCAN0RMID40 RSCAN0.RMID40.UINT32 +#define RSCAN0RMID40L RSCAN0.RMID40.UINT16[L] +#define RSCAN0RMID40LL RSCAN0.RMID40.UINT8[LL] +#define RSCAN0RMID40LH RSCAN0.RMID40.UINT8[LH] +#define RSCAN0RMID40H RSCAN0.RMID40.UINT16[H] +#define RSCAN0RMID40HL RSCAN0.RMID40.UINT8[HL] +#define RSCAN0RMID40HH RSCAN0.RMID40.UINT8[HH] +#define RSCAN0RMPTR40 RSCAN0.RMPTR40.UINT32 +#define RSCAN0RMPTR40L RSCAN0.RMPTR40.UINT16[L] +#define RSCAN0RMPTR40LL RSCAN0.RMPTR40.UINT8[LL] +#define RSCAN0RMPTR40LH RSCAN0.RMPTR40.UINT8[LH] +#define RSCAN0RMPTR40H RSCAN0.RMPTR40.UINT16[H] +#define RSCAN0RMPTR40HL RSCAN0.RMPTR40.UINT8[HL] +#define RSCAN0RMPTR40HH RSCAN0.RMPTR40.UINT8[HH] +#define RSCAN0RMDF040 RSCAN0.RMDF040.UINT32 +#define RSCAN0RMDF040L RSCAN0.RMDF040.UINT16[L] +#define RSCAN0RMDF040LL RSCAN0.RMDF040.UINT8[LL] +#define RSCAN0RMDF040LH RSCAN0.RMDF040.UINT8[LH] +#define RSCAN0RMDF040H RSCAN0.RMDF040.UINT16[H] +#define RSCAN0RMDF040HL RSCAN0.RMDF040.UINT8[HL] +#define RSCAN0RMDF040HH RSCAN0.RMDF040.UINT8[HH] +#define RSCAN0RMDF140 RSCAN0.RMDF140.UINT32 +#define RSCAN0RMDF140L RSCAN0.RMDF140.UINT16[L] +#define RSCAN0RMDF140LL RSCAN0.RMDF140.UINT8[LL] +#define RSCAN0RMDF140LH RSCAN0.RMDF140.UINT8[LH] +#define RSCAN0RMDF140H RSCAN0.RMDF140.UINT16[H] +#define RSCAN0RMDF140HL RSCAN0.RMDF140.UINT8[HL] +#define RSCAN0RMDF140HH RSCAN0.RMDF140.UINT8[HH] +#define RSCAN0RMID41 RSCAN0.RMID41.UINT32 +#define RSCAN0RMID41L RSCAN0.RMID41.UINT16[L] +#define RSCAN0RMID41LL RSCAN0.RMID41.UINT8[LL] +#define RSCAN0RMID41LH RSCAN0.RMID41.UINT8[LH] +#define RSCAN0RMID41H RSCAN0.RMID41.UINT16[H] +#define RSCAN0RMID41HL RSCAN0.RMID41.UINT8[HL] +#define RSCAN0RMID41HH RSCAN0.RMID41.UINT8[HH] +#define RSCAN0RMPTR41 RSCAN0.RMPTR41.UINT32 +#define RSCAN0RMPTR41L RSCAN0.RMPTR41.UINT16[L] +#define RSCAN0RMPTR41LL RSCAN0.RMPTR41.UINT8[LL] +#define RSCAN0RMPTR41LH RSCAN0.RMPTR41.UINT8[LH] +#define RSCAN0RMPTR41H RSCAN0.RMPTR41.UINT16[H] +#define RSCAN0RMPTR41HL RSCAN0.RMPTR41.UINT8[HL] +#define RSCAN0RMPTR41HH RSCAN0.RMPTR41.UINT8[HH] +#define RSCAN0RMDF041 RSCAN0.RMDF041.UINT32 +#define RSCAN0RMDF041L RSCAN0.RMDF041.UINT16[L] +#define RSCAN0RMDF041LL RSCAN0.RMDF041.UINT8[LL] +#define RSCAN0RMDF041LH RSCAN0.RMDF041.UINT8[LH] +#define RSCAN0RMDF041H RSCAN0.RMDF041.UINT16[H] +#define RSCAN0RMDF041HL RSCAN0.RMDF041.UINT8[HL] +#define RSCAN0RMDF041HH RSCAN0.RMDF041.UINT8[HH] +#define RSCAN0RMDF141 RSCAN0.RMDF141.UINT32 +#define RSCAN0RMDF141L RSCAN0.RMDF141.UINT16[L] +#define RSCAN0RMDF141LL RSCAN0.RMDF141.UINT8[LL] +#define RSCAN0RMDF141LH RSCAN0.RMDF141.UINT8[LH] +#define RSCAN0RMDF141H RSCAN0.RMDF141.UINT16[H] +#define RSCAN0RMDF141HL RSCAN0.RMDF141.UINT8[HL] +#define RSCAN0RMDF141HH RSCAN0.RMDF141.UINT8[HH] +#define RSCAN0RMID42 RSCAN0.RMID42.UINT32 +#define RSCAN0RMID42L RSCAN0.RMID42.UINT16[L] +#define RSCAN0RMID42LL RSCAN0.RMID42.UINT8[LL] +#define RSCAN0RMID42LH RSCAN0.RMID42.UINT8[LH] +#define RSCAN0RMID42H RSCAN0.RMID42.UINT16[H] +#define RSCAN0RMID42HL RSCAN0.RMID42.UINT8[HL] +#define RSCAN0RMID42HH RSCAN0.RMID42.UINT8[HH] +#define RSCAN0RMPTR42 RSCAN0.RMPTR42.UINT32 +#define RSCAN0RMPTR42L RSCAN0.RMPTR42.UINT16[L] +#define RSCAN0RMPTR42LL RSCAN0.RMPTR42.UINT8[LL] +#define RSCAN0RMPTR42LH RSCAN0.RMPTR42.UINT8[LH] +#define RSCAN0RMPTR42H RSCAN0.RMPTR42.UINT16[H] +#define RSCAN0RMPTR42HL RSCAN0.RMPTR42.UINT8[HL] +#define RSCAN0RMPTR42HH RSCAN0.RMPTR42.UINT8[HH] +#define RSCAN0RMDF042 RSCAN0.RMDF042.UINT32 +#define RSCAN0RMDF042L RSCAN0.RMDF042.UINT16[L] +#define RSCAN0RMDF042LL RSCAN0.RMDF042.UINT8[LL] +#define RSCAN0RMDF042LH RSCAN0.RMDF042.UINT8[LH] +#define RSCAN0RMDF042H RSCAN0.RMDF042.UINT16[H] +#define RSCAN0RMDF042HL RSCAN0.RMDF042.UINT8[HL] +#define RSCAN0RMDF042HH RSCAN0.RMDF042.UINT8[HH] +#define RSCAN0RMDF142 RSCAN0.RMDF142.UINT32 +#define RSCAN0RMDF142L RSCAN0.RMDF142.UINT16[L] +#define RSCAN0RMDF142LL RSCAN0.RMDF142.UINT8[LL] +#define RSCAN0RMDF142LH RSCAN0.RMDF142.UINT8[LH] +#define RSCAN0RMDF142H RSCAN0.RMDF142.UINT16[H] +#define RSCAN0RMDF142HL RSCAN0.RMDF142.UINT8[HL] +#define RSCAN0RMDF142HH RSCAN0.RMDF142.UINT8[HH] +#define RSCAN0RMID43 RSCAN0.RMID43.UINT32 +#define RSCAN0RMID43L RSCAN0.RMID43.UINT16[L] +#define RSCAN0RMID43LL RSCAN0.RMID43.UINT8[LL] +#define RSCAN0RMID43LH RSCAN0.RMID43.UINT8[LH] +#define RSCAN0RMID43H RSCAN0.RMID43.UINT16[H] +#define RSCAN0RMID43HL RSCAN0.RMID43.UINT8[HL] +#define RSCAN0RMID43HH RSCAN0.RMID43.UINT8[HH] +#define RSCAN0RMPTR43 RSCAN0.RMPTR43.UINT32 +#define RSCAN0RMPTR43L RSCAN0.RMPTR43.UINT16[L] +#define RSCAN0RMPTR43LL RSCAN0.RMPTR43.UINT8[LL] +#define RSCAN0RMPTR43LH RSCAN0.RMPTR43.UINT8[LH] +#define RSCAN0RMPTR43H RSCAN0.RMPTR43.UINT16[H] +#define RSCAN0RMPTR43HL RSCAN0.RMPTR43.UINT8[HL] +#define RSCAN0RMPTR43HH RSCAN0.RMPTR43.UINT8[HH] +#define RSCAN0RMDF043 RSCAN0.RMDF043.UINT32 +#define RSCAN0RMDF043L RSCAN0.RMDF043.UINT16[L] +#define RSCAN0RMDF043LL RSCAN0.RMDF043.UINT8[LL] +#define RSCAN0RMDF043LH RSCAN0.RMDF043.UINT8[LH] +#define RSCAN0RMDF043H RSCAN0.RMDF043.UINT16[H] +#define RSCAN0RMDF043HL RSCAN0.RMDF043.UINT8[HL] +#define RSCAN0RMDF043HH RSCAN0.RMDF043.UINT8[HH] +#define RSCAN0RMDF143 RSCAN0.RMDF143.UINT32 +#define RSCAN0RMDF143L RSCAN0.RMDF143.UINT16[L] +#define RSCAN0RMDF143LL RSCAN0.RMDF143.UINT8[LL] +#define RSCAN0RMDF143LH RSCAN0.RMDF143.UINT8[LH] +#define RSCAN0RMDF143H RSCAN0.RMDF143.UINT16[H] +#define RSCAN0RMDF143HL RSCAN0.RMDF143.UINT8[HL] +#define RSCAN0RMDF143HH RSCAN0.RMDF143.UINT8[HH] +#define RSCAN0RMID44 RSCAN0.RMID44.UINT32 +#define RSCAN0RMID44L RSCAN0.RMID44.UINT16[L] +#define RSCAN0RMID44LL RSCAN0.RMID44.UINT8[LL] +#define RSCAN0RMID44LH RSCAN0.RMID44.UINT8[LH] +#define RSCAN0RMID44H RSCAN0.RMID44.UINT16[H] +#define RSCAN0RMID44HL RSCAN0.RMID44.UINT8[HL] +#define RSCAN0RMID44HH RSCAN0.RMID44.UINT8[HH] +#define RSCAN0RMPTR44 RSCAN0.RMPTR44.UINT32 +#define RSCAN0RMPTR44L RSCAN0.RMPTR44.UINT16[L] +#define RSCAN0RMPTR44LL RSCAN0.RMPTR44.UINT8[LL] +#define RSCAN0RMPTR44LH RSCAN0.RMPTR44.UINT8[LH] +#define RSCAN0RMPTR44H RSCAN0.RMPTR44.UINT16[H] +#define RSCAN0RMPTR44HL RSCAN0.RMPTR44.UINT8[HL] +#define RSCAN0RMPTR44HH RSCAN0.RMPTR44.UINT8[HH] +#define RSCAN0RMDF044 RSCAN0.RMDF044.UINT32 +#define RSCAN0RMDF044L RSCAN0.RMDF044.UINT16[L] +#define RSCAN0RMDF044LL RSCAN0.RMDF044.UINT8[LL] +#define RSCAN0RMDF044LH RSCAN0.RMDF044.UINT8[LH] +#define RSCAN0RMDF044H RSCAN0.RMDF044.UINT16[H] +#define RSCAN0RMDF044HL RSCAN0.RMDF044.UINT8[HL] +#define RSCAN0RMDF044HH RSCAN0.RMDF044.UINT8[HH] +#define RSCAN0RMDF144 RSCAN0.RMDF144.UINT32 +#define RSCAN0RMDF144L RSCAN0.RMDF144.UINT16[L] +#define RSCAN0RMDF144LL RSCAN0.RMDF144.UINT8[LL] +#define RSCAN0RMDF144LH RSCAN0.RMDF144.UINT8[LH] +#define RSCAN0RMDF144H RSCAN0.RMDF144.UINT16[H] +#define RSCAN0RMDF144HL RSCAN0.RMDF144.UINT8[HL] +#define RSCAN0RMDF144HH RSCAN0.RMDF144.UINT8[HH] +#define RSCAN0RMID45 RSCAN0.RMID45.UINT32 +#define RSCAN0RMID45L RSCAN0.RMID45.UINT16[L] +#define RSCAN0RMID45LL RSCAN0.RMID45.UINT8[LL] +#define RSCAN0RMID45LH RSCAN0.RMID45.UINT8[LH] +#define RSCAN0RMID45H RSCAN0.RMID45.UINT16[H] +#define RSCAN0RMID45HL RSCAN0.RMID45.UINT8[HL] +#define RSCAN0RMID45HH RSCAN0.RMID45.UINT8[HH] +#define RSCAN0RMPTR45 RSCAN0.RMPTR45.UINT32 +#define RSCAN0RMPTR45L RSCAN0.RMPTR45.UINT16[L] +#define RSCAN0RMPTR45LL RSCAN0.RMPTR45.UINT8[LL] +#define RSCAN0RMPTR45LH RSCAN0.RMPTR45.UINT8[LH] +#define RSCAN0RMPTR45H RSCAN0.RMPTR45.UINT16[H] +#define RSCAN0RMPTR45HL RSCAN0.RMPTR45.UINT8[HL] +#define RSCAN0RMPTR45HH RSCAN0.RMPTR45.UINT8[HH] +#define RSCAN0RMDF045 RSCAN0.RMDF045.UINT32 +#define RSCAN0RMDF045L RSCAN0.RMDF045.UINT16[L] +#define RSCAN0RMDF045LL RSCAN0.RMDF045.UINT8[LL] +#define RSCAN0RMDF045LH RSCAN0.RMDF045.UINT8[LH] +#define RSCAN0RMDF045H RSCAN0.RMDF045.UINT16[H] +#define RSCAN0RMDF045HL RSCAN0.RMDF045.UINT8[HL] +#define RSCAN0RMDF045HH RSCAN0.RMDF045.UINT8[HH] +#define RSCAN0RMDF145 RSCAN0.RMDF145.UINT32 +#define RSCAN0RMDF145L RSCAN0.RMDF145.UINT16[L] +#define RSCAN0RMDF145LL RSCAN0.RMDF145.UINT8[LL] +#define RSCAN0RMDF145LH RSCAN0.RMDF145.UINT8[LH] +#define RSCAN0RMDF145H RSCAN0.RMDF145.UINT16[H] +#define RSCAN0RMDF145HL RSCAN0.RMDF145.UINT8[HL] +#define RSCAN0RMDF145HH RSCAN0.RMDF145.UINT8[HH] +#define RSCAN0RMID46 RSCAN0.RMID46.UINT32 +#define RSCAN0RMID46L RSCAN0.RMID46.UINT16[L] +#define RSCAN0RMID46LL RSCAN0.RMID46.UINT8[LL] +#define RSCAN0RMID46LH RSCAN0.RMID46.UINT8[LH] +#define RSCAN0RMID46H RSCAN0.RMID46.UINT16[H] +#define RSCAN0RMID46HL RSCAN0.RMID46.UINT8[HL] +#define RSCAN0RMID46HH RSCAN0.RMID46.UINT8[HH] +#define RSCAN0RMPTR46 RSCAN0.RMPTR46.UINT32 +#define RSCAN0RMPTR46L RSCAN0.RMPTR46.UINT16[L] +#define RSCAN0RMPTR46LL RSCAN0.RMPTR46.UINT8[LL] +#define RSCAN0RMPTR46LH RSCAN0.RMPTR46.UINT8[LH] +#define RSCAN0RMPTR46H RSCAN0.RMPTR46.UINT16[H] +#define RSCAN0RMPTR46HL RSCAN0.RMPTR46.UINT8[HL] +#define RSCAN0RMPTR46HH RSCAN0.RMPTR46.UINT8[HH] +#define RSCAN0RMDF046 RSCAN0.RMDF046.UINT32 +#define RSCAN0RMDF046L RSCAN0.RMDF046.UINT16[L] +#define RSCAN0RMDF046LL RSCAN0.RMDF046.UINT8[LL] +#define RSCAN0RMDF046LH RSCAN0.RMDF046.UINT8[LH] +#define RSCAN0RMDF046H RSCAN0.RMDF046.UINT16[H] +#define RSCAN0RMDF046HL RSCAN0.RMDF046.UINT8[HL] +#define RSCAN0RMDF046HH RSCAN0.RMDF046.UINT8[HH] +#define RSCAN0RMDF146 RSCAN0.RMDF146.UINT32 +#define RSCAN0RMDF146L RSCAN0.RMDF146.UINT16[L] +#define RSCAN0RMDF146LL RSCAN0.RMDF146.UINT8[LL] +#define RSCAN0RMDF146LH RSCAN0.RMDF146.UINT8[LH] +#define RSCAN0RMDF146H RSCAN0.RMDF146.UINT16[H] +#define RSCAN0RMDF146HL RSCAN0.RMDF146.UINT8[HL] +#define RSCAN0RMDF146HH RSCAN0.RMDF146.UINT8[HH] +#define RSCAN0RMID47 RSCAN0.RMID47.UINT32 +#define RSCAN0RMID47L RSCAN0.RMID47.UINT16[L] +#define RSCAN0RMID47LL RSCAN0.RMID47.UINT8[LL] +#define RSCAN0RMID47LH RSCAN0.RMID47.UINT8[LH] +#define RSCAN0RMID47H RSCAN0.RMID47.UINT16[H] +#define RSCAN0RMID47HL RSCAN0.RMID47.UINT8[HL] +#define RSCAN0RMID47HH RSCAN0.RMID47.UINT8[HH] +#define RSCAN0RMPTR47 RSCAN0.RMPTR47.UINT32 +#define RSCAN0RMPTR47L RSCAN0.RMPTR47.UINT16[L] +#define RSCAN0RMPTR47LL RSCAN0.RMPTR47.UINT8[LL] +#define RSCAN0RMPTR47LH RSCAN0.RMPTR47.UINT8[LH] +#define RSCAN0RMPTR47H RSCAN0.RMPTR47.UINT16[H] +#define RSCAN0RMPTR47HL RSCAN0.RMPTR47.UINT8[HL] +#define RSCAN0RMPTR47HH RSCAN0.RMPTR47.UINT8[HH] +#define RSCAN0RMDF047 RSCAN0.RMDF047.UINT32 +#define RSCAN0RMDF047L RSCAN0.RMDF047.UINT16[L] +#define RSCAN0RMDF047LL RSCAN0.RMDF047.UINT8[LL] +#define RSCAN0RMDF047LH RSCAN0.RMDF047.UINT8[LH] +#define RSCAN0RMDF047H RSCAN0.RMDF047.UINT16[H] +#define RSCAN0RMDF047HL RSCAN0.RMDF047.UINT8[HL] +#define RSCAN0RMDF047HH RSCAN0.RMDF047.UINT8[HH] +#define RSCAN0RMDF147 RSCAN0.RMDF147.UINT32 +#define RSCAN0RMDF147L RSCAN0.RMDF147.UINT16[L] +#define RSCAN0RMDF147LL RSCAN0.RMDF147.UINT8[LL] +#define RSCAN0RMDF147LH RSCAN0.RMDF147.UINT8[LH] +#define RSCAN0RMDF147H RSCAN0.RMDF147.UINT16[H] +#define RSCAN0RMDF147HL RSCAN0.RMDF147.UINT8[HL] +#define RSCAN0RMDF147HH RSCAN0.RMDF147.UINT8[HH] +#define RSCAN0RMID48 RSCAN0.RMID48.UINT32 +#define RSCAN0RMID48L RSCAN0.RMID48.UINT16[L] +#define RSCAN0RMID48LL RSCAN0.RMID48.UINT8[LL] +#define RSCAN0RMID48LH RSCAN0.RMID48.UINT8[LH] +#define RSCAN0RMID48H RSCAN0.RMID48.UINT16[H] +#define RSCAN0RMID48HL RSCAN0.RMID48.UINT8[HL] +#define RSCAN0RMID48HH RSCAN0.RMID48.UINT8[HH] +#define RSCAN0RMPTR48 RSCAN0.RMPTR48.UINT32 +#define RSCAN0RMPTR48L RSCAN0.RMPTR48.UINT16[L] +#define RSCAN0RMPTR48LL RSCAN0.RMPTR48.UINT8[LL] +#define RSCAN0RMPTR48LH RSCAN0.RMPTR48.UINT8[LH] +#define RSCAN0RMPTR48H RSCAN0.RMPTR48.UINT16[H] +#define RSCAN0RMPTR48HL RSCAN0.RMPTR48.UINT8[HL] +#define RSCAN0RMPTR48HH RSCAN0.RMPTR48.UINT8[HH] +#define RSCAN0RMDF048 RSCAN0.RMDF048.UINT32 +#define RSCAN0RMDF048L RSCAN0.RMDF048.UINT16[L] +#define RSCAN0RMDF048LL RSCAN0.RMDF048.UINT8[LL] +#define RSCAN0RMDF048LH RSCAN0.RMDF048.UINT8[LH] +#define RSCAN0RMDF048H RSCAN0.RMDF048.UINT16[H] +#define RSCAN0RMDF048HL RSCAN0.RMDF048.UINT8[HL] +#define RSCAN0RMDF048HH RSCAN0.RMDF048.UINT8[HH] +#define RSCAN0RMDF148 RSCAN0.RMDF148.UINT32 +#define RSCAN0RMDF148L RSCAN0.RMDF148.UINT16[L] +#define RSCAN0RMDF148LL RSCAN0.RMDF148.UINT8[LL] +#define RSCAN0RMDF148LH RSCAN0.RMDF148.UINT8[LH] +#define RSCAN0RMDF148H RSCAN0.RMDF148.UINT16[H] +#define RSCAN0RMDF148HL RSCAN0.RMDF148.UINT8[HL] +#define RSCAN0RMDF148HH RSCAN0.RMDF148.UINT8[HH] +#define RSCAN0RMID49 RSCAN0.RMID49.UINT32 +#define RSCAN0RMID49L RSCAN0.RMID49.UINT16[L] +#define RSCAN0RMID49LL RSCAN0.RMID49.UINT8[LL] +#define RSCAN0RMID49LH RSCAN0.RMID49.UINT8[LH] +#define RSCAN0RMID49H RSCAN0.RMID49.UINT16[H] +#define RSCAN0RMID49HL RSCAN0.RMID49.UINT8[HL] +#define RSCAN0RMID49HH RSCAN0.RMID49.UINT8[HH] +#define RSCAN0RMPTR49 RSCAN0.RMPTR49.UINT32 +#define RSCAN0RMPTR49L RSCAN0.RMPTR49.UINT16[L] +#define RSCAN0RMPTR49LL RSCAN0.RMPTR49.UINT8[LL] +#define RSCAN0RMPTR49LH RSCAN0.RMPTR49.UINT8[LH] +#define RSCAN0RMPTR49H RSCAN0.RMPTR49.UINT16[H] +#define RSCAN0RMPTR49HL RSCAN0.RMPTR49.UINT8[HL] +#define RSCAN0RMPTR49HH RSCAN0.RMPTR49.UINT8[HH] +#define RSCAN0RMDF049 RSCAN0.RMDF049.UINT32 +#define RSCAN0RMDF049L RSCAN0.RMDF049.UINT16[L] +#define RSCAN0RMDF049LL RSCAN0.RMDF049.UINT8[LL] +#define RSCAN0RMDF049LH RSCAN0.RMDF049.UINT8[LH] +#define RSCAN0RMDF049H RSCAN0.RMDF049.UINT16[H] +#define RSCAN0RMDF049HL RSCAN0.RMDF049.UINT8[HL] +#define RSCAN0RMDF049HH RSCAN0.RMDF049.UINT8[HH] +#define RSCAN0RMDF149 RSCAN0.RMDF149.UINT32 +#define RSCAN0RMDF149L RSCAN0.RMDF149.UINT16[L] +#define RSCAN0RMDF149LL RSCAN0.RMDF149.UINT8[LL] +#define RSCAN0RMDF149LH RSCAN0.RMDF149.UINT8[LH] +#define RSCAN0RMDF149H RSCAN0.RMDF149.UINT16[H] +#define RSCAN0RMDF149HL RSCAN0.RMDF149.UINT8[HL] +#define RSCAN0RMDF149HH RSCAN0.RMDF149.UINT8[HH] +#define RSCAN0RMID50 RSCAN0.RMID50.UINT32 +#define RSCAN0RMID50L RSCAN0.RMID50.UINT16[L] +#define RSCAN0RMID50LL RSCAN0.RMID50.UINT8[LL] +#define RSCAN0RMID50LH RSCAN0.RMID50.UINT8[LH] +#define RSCAN0RMID50H RSCAN0.RMID50.UINT16[H] +#define RSCAN0RMID50HL RSCAN0.RMID50.UINT8[HL] +#define RSCAN0RMID50HH RSCAN0.RMID50.UINT8[HH] +#define RSCAN0RMPTR50 RSCAN0.RMPTR50.UINT32 +#define RSCAN0RMPTR50L RSCAN0.RMPTR50.UINT16[L] +#define RSCAN0RMPTR50LL RSCAN0.RMPTR50.UINT8[LL] +#define RSCAN0RMPTR50LH RSCAN0.RMPTR50.UINT8[LH] +#define RSCAN0RMPTR50H RSCAN0.RMPTR50.UINT16[H] +#define RSCAN0RMPTR50HL RSCAN0.RMPTR50.UINT8[HL] +#define RSCAN0RMPTR50HH RSCAN0.RMPTR50.UINT8[HH] +#define RSCAN0RMDF050 RSCAN0.RMDF050.UINT32 +#define RSCAN0RMDF050L RSCAN0.RMDF050.UINT16[L] +#define RSCAN0RMDF050LL RSCAN0.RMDF050.UINT8[LL] +#define RSCAN0RMDF050LH RSCAN0.RMDF050.UINT8[LH] +#define RSCAN0RMDF050H RSCAN0.RMDF050.UINT16[H] +#define RSCAN0RMDF050HL RSCAN0.RMDF050.UINT8[HL] +#define RSCAN0RMDF050HH RSCAN0.RMDF050.UINT8[HH] +#define RSCAN0RMDF150 RSCAN0.RMDF150.UINT32 +#define RSCAN0RMDF150L RSCAN0.RMDF150.UINT16[L] +#define RSCAN0RMDF150LL RSCAN0.RMDF150.UINT8[LL] +#define RSCAN0RMDF150LH RSCAN0.RMDF150.UINT8[LH] +#define RSCAN0RMDF150H RSCAN0.RMDF150.UINT16[H] +#define RSCAN0RMDF150HL RSCAN0.RMDF150.UINT8[HL] +#define RSCAN0RMDF150HH RSCAN0.RMDF150.UINT8[HH] +#define RSCAN0RMID51 RSCAN0.RMID51.UINT32 +#define RSCAN0RMID51L RSCAN0.RMID51.UINT16[L] +#define RSCAN0RMID51LL RSCAN0.RMID51.UINT8[LL] +#define RSCAN0RMID51LH RSCAN0.RMID51.UINT8[LH] +#define RSCAN0RMID51H RSCAN0.RMID51.UINT16[H] +#define RSCAN0RMID51HL RSCAN0.RMID51.UINT8[HL] +#define RSCAN0RMID51HH RSCAN0.RMID51.UINT8[HH] +#define RSCAN0RMPTR51 RSCAN0.RMPTR51.UINT32 +#define RSCAN0RMPTR51L RSCAN0.RMPTR51.UINT16[L] +#define RSCAN0RMPTR51LL RSCAN0.RMPTR51.UINT8[LL] +#define RSCAN0RMPTR51LH RSCAN0.RMPTR51.UINT8[LH] +#define RSCAN0RMPTR51H RSCAN0.RMPTR51.UINT16[H] +#define RSCAN0RMPTR51HL RSCAN0.RMPTR51.UINT8[HL] +#define RSCAN0RMPTR51HH RSCAN0.RMPTR51.UINT8[HH] +#define RSCAN0RMDF051 RSCAN0.RMDF051.UINT32 +#define RSCAN0RMDF051L RSCAN0.RMDF051.UINT16[L] +#define RSCAN0RMDF051LL RSCAN0.RMDF051.UINT8[LL] +#define RSCAN0RMDF051LH RSCAN0.RMDF051.UINT8[LH] +#define RSCAN0RMDF051H RSCAN0.RMDF051.UINT16[H] +#define RSCAN0RMDF051HL RSCAN0.RMDF051.UINT8[HL] +#define RSCAN0RMDF051HH RSCAN0.RMDF051.UINT8[HH] +#define RSCAN0RMDF151 RSCAN0.RMDF151.UINT32 +#define RSCAN0RMDF151L RSCAN0.RMDF151.UINT16[L] +#define RSCAN0RMDF151LL RSCAN0.RMDF151.UINT8[LL] +#define RSCAN0RMDF151LH RSCAN0.RMDF151.UINT8[LH] +#define RSCAN0RMDF151H RSCAN0.RMDF151.UINT16[H] +#define RSCAN0RMDF151HL RSCAN0.RMDF151.UINT8[HL] +#define RSCAN0RMDF151HH RSCAN0.RMDF151.UINT8[HH] +#define RSCAN0RMID52 RSCAN0.RMID52.UINT32 +#define RSCAN0RMID52L RSCAN0.RMID52.UINT16[L] +#define RSCAN0RMID52LL RSCAN0.RMID52.UINT8[LL] +#define RSCAN0RMID52LH RSCAN0.RMID52.UINT8[LH] +#define RSCAN0RMID52H RSCAN0.RMID52.UINT16[H] +#define RSCAN0RMID52HL RSCAN0.RMID52.UINT8[HL] +#define RSCAN0RMID52HH RSCAN0.RMID52.UINT8[HH] +#define RSCAN0RMPTR52 RSCAN0.RMPTR52.UINT32 +#define RSCAN0RMPTR52L RSCAN0.RMPTR52.UINT16[L] +#define RSCAN0RMPTR52LL RSCAN0.RMPTR52.UINT8[LL] +#define RSCAN0RMPTR52LH RSCAN0.RMPTR52.UINT8[LH] +#define RSCAN0RMPTR52H RSCAN0.RMPTR52.UINT16[H] +#define RSCAN0RMPTR52HL RSCAN0.RMPTR52.UINT8[HL] +#define RSCAN0RMPTR52HH RSCAN0.RMPTR52.UINT8[HH] +#define RSCAN0RMDF052 RSCAN0.RMDF052.UINT32 +#define RSCAN0RMDF052L RSCAN0.RMDF052.UINT16[L] +#define RSCAN0RMDF052LL RSCAN0.RMDF052.UINT8[LL] +#define RSCAN0RMDF052LH RSCAN0.RMDF052.UINT8[LH] +#define RSCAN0RMDF052H RSCAN0.RMDF052.UINT16[H] +#define RSCAN0RMDF052HL RSCAN0.RMDF052.UINT8[HL] +#define RSCAN0RMDF052HH RSCAN0.RMDF052.UINT8[HH] +#define RSCAN0RMDF152 RSCAN0.RMDF152.UINT32 +#define RSCAN0RMDF152L RSCAN0.RMDF152.UINT16[L] +#define RSCAN0RMDF152LL RSCAN0.RMDF152.UINT8[LL] +#define RSCAN0RMDF152LH RSCAN0.RMDF152.UINT8[LH] +#define RSCAN0RMDF152H RSCAN0.RMDF152.UINT16[H] +#define RSCAN0RMDF152HL RSCAN0.RMDF152.UINT8[HL] +#define RSCAN0RMDF152HH RSCAN0.RMDF152.UINT8[HH] +#define RSCAN0RMID53 RSCAN0.RMID53.UINT32 +#define RSCAN0RMID53L RSCAN0.RMID53.UINT16[L] +#define RSCAN0RMID53LL RSCAN0.RMID53.UINT8[LL] +#define RSCAN0RMID53LH RSCAN0.RMID53.UINT8[LH] +#define RSCAN0RMID53H RSCAN0.RMID53.UINT16[H] +#define RSCAN0RMID53HL RSCAN0.RMID53.UINT8[HL] +#define RSCAN0RMID53HH RSCAN0.RMID53.UINT8[HH] +#define RSCAN0RMPTR53 RSCAN0.RMPTR53.UINT32 +#define RSCAN0RMPTR53L RSCAN0.RMPTR53.UINT16[L] +#define RSCAN0RMPTR53LL RSCAN0.RMPTR53.UINT8[LL] +#define RSCAN0RMPTR53LH RSCAN0.RMPTR53.UINT8[LH] +#define RSCAN0RMPTR53H RSCAN0.RMPTR53.UINT16[H] +#define RSCAN0RMPTR53HL RSCAN0.RMPTR53.UINT8[HL] +#define RSCAN0RMPTR53HH RSCAN0.RMPTR53.UINT8[HH] +#define RSCAN0RMDF053 RSCAN0.RMDF053.UINT32 +#define RSCAN0RMDF053L RSCAN0.RMDF053.UINT16[L] +#define RSCAN0RMDF053LL RSCAN0.RMDF053.UINT8[LL] +#define RSCAN0RMDF053LH RSCAN0.RMDF053.UINT8[LH] +#define RSCAN0RMDF053H RSCAN0.RMDF053.UINT16[H] +#define RSCAN0RMDF053HL RSCAN0.RMDF053.UINT8[HL] +#define RSCAN0RMDF053HH RSCAN0.RMDF053.UINT8[HH] +#define RSCAN0RMDF153 RSCAN0.RMDF153.UINT32 +#define RSCAN0RMDF153L RSCAN0.RMDF153.UINT16[L] +#define RSCAN0RMDF153LL RSCAN0.RMDF153.UINT8[LL] +#define RSCAN0RMDF153LH RSCAN0.RMDF153.UINT8[LH] +#define RSCAN0RMDF153H RSCAN0.RMDF153.UINT16[H] +#define RSCAN0RMDF153HL RSCAN0.RMDF153.UINT8[HL] +#define RSCAN0RMDF153HH RSCAN0.RMDF153.UINT8[HH] +#define RSCAN0RMID54 RSCAN0.RMID54.UINT32 +#define RSCAN0RMID54L RSCAN0.RMID54.UINT16[L] +#define RSCAN0RMID54LL RSCAN0.RMID54.UINT8[LL] +#define RSCAN0RMID54LH RSCAN0.RMID54.UINT8[LH] +#define RSCAN0RMID54H RSCAN0.RMID54.UINT16[H] +#define RSCAN0RMID54HL RSCAN0.RMID54.UINT8[HL] +#define RSCAN0RMID54HH RSCAN0.RMID54.UINT8[HH] +#define RSCAN0RMPTR54 RSCAN0.RMPTR54.UINT32 +#define RSCAN0RMPTR54L RSCAN0.RMPTR54.UINT16[L] +#define RSCAN0RMPTR54LL RSCAN0.RMPTR54.UINT8[LL] +#define RSCAN0RMPTR54LH RSCAN0.RMPTR54.UINT8[LH] +#define RSCAN0RMPTR54H RSCAN0.RMPTR54.UINT16[H] +#define RSCAN0RMPTR54HL RSCAN0.RMPTR54.UINT8[HL] +#define RSCAN0RMPTR54HH RSCAN0.RMPTR54.UINT8[HH] +#define RSCAN0RMDF054 RSCAN0.RMDF054.UINT32 +#define RSCAN0RMDF054L RSCAN0.RMDF054.UINT16[L] +#define RSCAN0RMDF054LL RSCAN0.RMDF054.UINT8[LL] +#define RSCAN0RMDF054LH RSCAN0.RMDF054.UINT8[LH] +#define RSCAN0RMDF054H RSCAN0.RMDF054.UINT16[H] +#define RSCAN0RMDF054HL RSCAN0.RMDF054.UINT8[HL] +#define RSCAN0RMDF054HH RSCAN0.RMDF054.UINT8[HH] +#define RSCAN0RMDF154 RSCAN0.RMDF154.UINT32 +#define RSCAN0RMDF154L RSCAN0.RMDF154.UINT16[L] +#define RSCAN0RMDF154LL RSCAN0.RMDF154.UINT8[LL] +#define RSCAN0RMDF154LH RSCAN0.RMDF154.UINT8[LH] +#define RSCAN0RMDF154H RSCAN0.RMDF154.UINT16[H] +#define RSCAN0RMDF154HL RSCAN0.RMDF154.UINT8[HL] +#define RSCAN0RMDF154HH RSCAN0.RMDF154.UINT8[HH] +#define RSCAN0RMID55 RSCAN0.RMID55.UINT32 +#define RSCAN0RMID55L RSCAN0.RMID55.UINT16[L] +#define RSCAN0RMID55LL RSCAN0.RMID55.UINT8[LL] +#define RSCAN0RMID55LH RSCAN0.RMID55.UINT8[LH] +#define RSCAN0RMID55H RSCAN0.RMID55.UINT16[H] +#define RSCAN0RMID55HL RSCAN0.RMID55.UINT8[HL] +#define RSCAN0RMID55HH RSCAN0.RMID55.UINT8[HH] +#define RSCAN0RMPTR55 RSCAN0.RMPTR55.UINT32 +#define RSCAN0RMPTR55L RSCAN0.RMPTR55.UINT16[L] +#define RSCAN0RMPTR55LL RSCAN0.RMPTR55.UINT8[LL] +#define RSCAN0RMPTR55LH RSCAN0.RMPTR55.UINT8[LH] +#define RSCAN0RMPTR55H RSCAN0.RMPTR55.UINT16[H] +#define RSCAN0RMPTR55HL RSCAN0.RMPTR55.UINT8[HL] +#define RSCAN0RMPTR55HH RSCAN0.RMPTR55.UINT8[HH] +#define RSCAN0RMDF055 RSCAN0.RMDF055.UINT32 +#define RSCAN0RMDF055L RSCAN0.RMDF055.UINT16[L] +#define RSCAN0RMDF055LL RSCAN0.RMDF055.UINT8[LL] +#define RSCAN0RMDF055LH RSCAN0.RMDF055.UINT8[LH] +#define RSCAN0RMDF055H RSCAN0.RMDF055.UINT16[H] +#define RSCAN0RMDF055HL RSCAN0.RMDF055.UINT8[HL] +#define RSCAN0RMDF055HH RSCAN0.RMDF055.UINT8[HH] +#define RSCAN0RMDF155 RSCAN0.RMDF155.UINT32 +#define RSCAN0RMDF155L RSCAN0.RMDF155.UINT16[L] +#define RSCAN0RMDF155LL RSCAN0.RMDF155.UINT8[LL] +#define RSCAN0RMDF155LH RSCAN0.RMDF155.UINT8[LH] +#define RSCAN0RMDF155H RSCAN0.RMDF155.UINT16[H] +#define RSCAN0RMDF155HL RSCAN0.RMDF155.UINT8[HL] +#define RSCAN0RMDF155HH RSCAN0.RMDF155.UINT8[HH] +#define RSCAN0RMID56 RSCAN0.RMID56.UINT32 +#define RSCAN0RMID56L RSCAN0.RMID56.UINT16[L] +#define RSCAN0RMID56LL RSCAN0.RMID56.UINT8[LL] +#define RSCAN0RMID56LH RSCAN0.RMID56.UINT8[LH] +#define RSCAN0RMID56H RSCAN0.RMID56.UINT16[H] +#define RSCAN0RMID56HL RSCAN0.RMID56.UINT8[HL] +#define RSCAN0RMID56HH RSCAN0.RMID56.UINT8[HH] +#define RSCAN0RMPTR56 RSCAN0.RMPTR56.UINT32 +#define RSCAN0RMPTR56L RSCAN0.RMPTR56.UINT16[L] +#define RSCAN0RMPTR56LL RSCAN0.RMPTR56.UINT8[LL] +#define RSCAN0RMPTR56LH RSCAN0.RMPTR56.UINT8[LH] +#define RSCAN0RMPTR56H RSCAN0.RMPTR56.UINT16[H] +#define RSCAN0RMPTR56HL RSCAN0.RMPTR56.UINT8[HL] +#define RSCAN0RMPTR56HH RSCAN0.RMPTR56.UINT8[HH] +#define RSCAN0RMDF056 RSCAN0.RMDF056.UINT32 +#define RSCAN0RMDF056L RSCAN0.RMDF056.UINT16[L] +#define RSCAN0RMDF056LL RSCAN0.RMDF056.UINT8[LL] +#define RSCAN0RMDF056LH RSCAN0.RMDF056.UINT8[LH] +#define RSCAN0RMDF056H RSCAN0.RMDF056.UINT16[H] +#define RSCAN0RMDF056HL RSCAN0.RMDF056.UINT8[HL] +#define RSCAN0RMDF056HH RSCAN0.RMDF056.UINT8[HH] +#define RSCAN0RMDF156 RSCAN0.RMDF156.UINT32 +#define RSCAN0RMDF156L RSCAN0.RMDF156.UINT16[L] +#define RSCAN0RMDF156LL RSCAN0.RMDF156.UINT8[LL] +#define RSCAN0RMDF156LH RSCAN0.RMDF156.UINT8[LH] +#define RSCAN0RMDF156H RSCAN0.RMDF156.UINT16[H] +#define RSCAN0RMDF156HL RSCAN0.RMDF156.UINT8[HL] +#define RSCAN0RMDF156HH RSCAN0.RMDF156.UINT8[HH] +#define RSCAN0RMID57 RSCAN0.RMID57.UINT32 +#define RSCAN0RMID57L RSCAN0.RMID57.UINT16[L] +#define RSCAN0RMID57LL RSCAN0.RMID57.UINT8[LL] +#define RSCAN0RMID57LH RSCAN0.RMID57.UINT8[LH] +#define RSCAN0RMID57H RSCAN0.RMID57.UINT16[H] +#define RSCAN0RMID57HL RSCAN0.RMID57.UINT8[HL] +#define RSCAN0RMID57HH RSCAN0.RMID57.UINT8[HH] +#define RSCAN0RMPTR57 RSCAN0.RMPTR57.UINT32 +#define RSCAN0RMPTR57L RSCAN0.RMPTR57.UINT16[L] +#define RSCAN0RMPTR57LL RSCAN0.RMPTR57.UINT8[LL] +#define RSCAN0RMPTR57LH RSCAN0.RMPTR57.UINT8[LH] +#define RSCAN0RMPTR57H RSCAN0.RMPTR57.UINT16[H] +#define RSCAN0RMPTR57HL RSCAN0.RMPTR57.UINT8[HL] +#define RSCAN0RMPTR57HH RSCAN0.RMPTR57.UINT8[HH] +#define RSCAN0RMDF057 RSCAN0.RMDF057.UINT32 +#define RSCAN0RMDF057L RSCAN0.RMDF057.UINT16[L] +#define RSCAN0RMDF057LL RSCAN0.RMDF057.UINT8[LL] +#define RSCAN0RMDF057LH RSCAN0.RMDF057.UINT8[LH] +#define RSCAN0RMDF057H RSCAN0.RMDF057.UINT16[H] +#define RSCAN0RMDF057HL RSCAN0.RMDF057.UINT8[HL] +#define RSCAN0RMDF057HH RSCAN0.RMDF057.UINT8[HH] +#define RSCAN0RMDF157 RSCAN0.RMDF157.UINT32 +#define RSCAN0RMDF157L RSCAN0.RMDF157.UINT16[L] +#define RSCAN0RMDF157LL RSCAN0.RMDF157.UINT8[LL] +#define RSCAN0RMDF157LH RSCAN0.RMDF157.UINT8[LH] +#define RSCAN0RMDF157H RSCAN0.RMDF157.UINT16[H] +#define RSCAN0RMDF157HL RSCAN0.RMDF157.UINT8[HL] +#define RSCAN0RMDF157HH RSCAN0.RMDF157.UINT8[HH] +#define RSCAN0RMID58 RSCAN0.RMID58.UINT32 +#define RSCAN0RMID58L RSCAN0.RMID58.UINT16[L] +#define RSCAN0RMID58LL RSCAN0.RMID58.UINT8[LL] +#define RSCAN0RMID58LH RSCAN0.RMID58.UINT8[LH] +#define RSCAN0RMID58H RSCAN0.RMID58.UINT16[H] +#define RSCAN0RMID58HL RSCAN0.RMID58.UINT8[HL] +#define RSCAN0RMID58HH RSCAN0.RMID58.UINT8[HH] +#define RSCAN0RMPTR58 RSCAN0.RMPTR58.UINT32 +#define RSCAN0RMPTR58L RSCAN0.RMPTR58.UINT16[L] +#define RSCAN0RMPTR58LL RSCAN0.RMPTR58.UINT8[LL] +#define RSCAN0RMPTR58LH RSCAN0.RMPTR58.UINT8[LH] +#define RSCAN0RMPTR58H RSCAN0.RMPTR58.UINT16[H] +#define RSCAN0RMPTR58HL RSCAN0.RMPTR58.UINT8[HL] +#define RSCAN0RMPTR58HH RSCAN0.RMPTR58.UINT8[HH] +#define RSCAN0RMDF058 RSCAN0.RMDF058.UINT32 +#define RSCAN0RMDF058L RSCAN0.RMDF058.UINT16[L] +#define RSCAN0RMDF058LL RSCAN0.RMDF058.UINT8[LL] +#define RSCAN0RMDF058LH RSCAN0.RMDF058.UINT8[LH] +#define RSCAN0RMDF058H RSCAN0.RMDF058.UINT16[H] +#define RSCAN0RMDF058HL RSCAN0.RMDF058.UINT8[HL] +#define RSCAN0RMDF058HH RSCAN0.RMDF058.UINT8[HH] +#define RSCAN0RMDF158 RSCAN0.RMDF158.UINT32 +#define RSCAN0RMDF158L RSCAN0.RMDF158.UINT16[L] +#define RSCAN0RMDF158LL RSCAN0.RMDF158.UINT8[LL] +#define RSCAN0RMDF158LH RSCAN0.RMDF158.UINT8[LH] +#define RSCAN0RMDF158H RSCAN0.RMDF158.UINT16[H] +#define RSCAN0RMDF158HL RSCAN0.RMDF158.UINT8[HL] +#define RSCAN0RMDF158HH RSCAN0.RMDF158.UINT8[HH] +#define RSCAN0RMID59 RSCAN0.RMID59.UINT32 +#define RSCAN0RMID59L RSCAN0.RMID59.UINT16[L] +#define RSCAN0RMID59LL RSCAN0.RMID59.UINT8[LL] +#define RSCAN0RMID59LH RSCAN0.RMID59.UINT8[LH] +#define RSCAN0RMID59H RSCAN0.RMID59.UINT16[H] +#define RSCAN0RMID59HL RSCAN0.RMID59.UINT8[HL] +#define RSCAN0RMID59HH RSCAN0.RMID59.UINT8[HH] +#define RSCAN0RMPTR59 RSCAN0.RMPTR59.UINT32 +#define RSCAN0RMPTR59L RSCAN0.RMPTR59.UINT16[L] +#define RSCAN0RMPTR59LL RSCAN0.RMPTR59.UINT8[LL] +#define RSCAN0RMPTR59LH RSCAN0.RMPTR59.UINT8[LH] +#define RSCAN0RMPTR59H RSCAN0.RMPTR59.UINT16[H] +#define RSCAN0RMPTR59HL RSCAN0.RMPTR59.UINT8[HL] +#define RSCAN0RMPTR59HH RSCAN0.RMPTR59.UINT8[HH] +#define RSCAN0RMDF059 RSCAN0.RMDF059.UINT32 +#define RSCAN0RMDF059L RSCAN0.RMDF059.UINT16[L] +#define RSCAN0RMDF059LL RSCAN0.RMDF059.UINT8[LL] +#define RSCAN0RMDF059LH RSCAN0.RMDF059.UINT8[LH] +#define RSCAN0RMDF059H RSCAN0.RMDF059.UINT16[H] +#define RSCAN0RMDF059HL RSCAN0.RMDF059.UINT8[HL] +#define RSCAN0RMDF059HH RSCAN0.RMDF059.UINT8[HH] +#define RSCAN0RMDF159 RSCAN0.RMDF159.UINT32 +#define RSCAN0RMDF159L RSCAN0.RMDF159.UINT16[L] +#define RSCAN0RMDF159LL RSCAN0.RMDF159.UINT8[LL] +#define RSCAN0RMDF159LH RSCAN0.RMDF159.UINT8[LH] +#define RSCAN0RMDF159H RSCAN0.RMDF159.UINT16[H] +#define RSCAN0RMDF159HL RSCAN0.RMDF159.UINT8[HL] +#define RSCAN0RMDF159HH RSCAN0.RMDF159.UINT8[HH] +#define RSCAN0RMID60 RSCAN0.RMID60.UINT32 +#define RSCAN0RMID60L RSCAN0.RMID60.UINT16[L] +#define RSCAN0RMID60LL RSCAN0.RMID60.UINT8[LL] +#define RSCAN0RMID60LH RSCAN0.RMID60.UINT8[LH] +#define RSCAN0RMID60H RSCAN0.RMID60.UINT16[H] +#define RSCAN0RMID60HL RSCAN0.RMID60.UINT8[HL] +#define RSCAN0RMID60HH RSCAN0.RMID60.UINT8[HH] +#define RSCAN0RMPTR60 RSCAN0.RMPTR60.UINT32 +#define RSCAN0RMPTR60L RSCAN0.RMPTR60.UINT16[L] +#define RSCAN0RMPTR60LL RSCAN0.RMPTR60.UINT8[LL] +#define RSCAN0RMPTR60LH RSCAN0.RMPTR60.UINT8[LH] +#define RSCAN0RMPTR60H RSCAN0.RMPTR60.UINT16[H] +#define RSCAN0RMPTR60HL RSCAN0.RMPTR60.UINT8[HL] +#define RSCAN0RMPTR60HH RSCAN0.RMPTR60.UINT8[HH] +#define RSCAN0RMDF060 RSCAN0.RMDF060.UINT32 +#define RSCAN0RMDF060L RSCAN0.RMDF060.UINT16[L] +#define RSCAN0RMDF060LL RSCAN0.RMDF060.UINT8[LL] +#define RSCAN0RMDF060LH RSCAN0.RMDF060.UINT8[LH] +#define RSCAN0RMDF060H RSCAN0.RMDF060.UINT16[H] +#define RSCAN0RMDF060HL RSCAN0.RMDF060.UINT8[HL] +#define RSCAN0RMDF060HH RSCAN0.RMDF060.UINT8[HH] +#define RSCAN0RMDF160 RSCAN0.RMDF160.UINT32 +#define RSCAN0RMDF160L RSCAN0.RMDF160.UINT16[L] +#define RSCAN0RMDF160LL RSCAN0.RMDF160.UINT8[LL] +#define RSCAN0RMDF160LH RSCAN0.RMDF160.UINT8[LH] +#define RSCAN0RMDF160H RSCAN0.RMDF160.UINT16[H] +#define RSCAN0RMDF160HL RSCAN0.RMDF160.UINT8[HL] +#define RSCAN0RMDF160HH RSCAN0.RMDF160.UINT8[HH] +#define RSCAN0RMID61 RSCAN0.RMID61.UINT32 +#define RSCAN0RMID61L RSCAN0.RMID61.UINT16[L] +#define RSCAN0RMID61LL RSCAN0.RMID61.UINT8[LL] +#define RSCAN0RMID61LH RSCAN0.RMID61.UINT8[LH] +#define RSCAN0RMID61H RSCAN0.RMID61.UINT16[H] +#define RSCAN0RMID61HL RSCAN0.RMID61.UINT8[HL] +#define RSCAN0RMID61HH RSCAN0.RMID61.UINT8[HH] +#define RSCAN0RMPTR61 RSCAN0.RMPTR61.UINT32 +#define RSCAN0RMPTR61L RSCAN0.RMPTR61.UINT16[L] +#define RSCAN0RMPTR61LL RSCAN0.RMPTR61.UINT8[LL] +#define RSCAN0RMPTR61LH RSCAN0.RMPTR61.UINT8[LH] +#define RSCAN0RMPTR61H RSCAN0.RMPTR61.UINT16[H] +#define RSCAN0RMPTR61HL RSCAN0.RMPTR61.UINT8[HL] +#define RSCAN0RMPTR61HH RSCAN0.RMPTR61.UINT8[HH] +#define RSCAN0RMDF061 RSCAN0.RMDF061.UINT32 +#define RSCAN0RMDF061L RSCAN0.RMDF061.UINT16[L] +#define RSCAN0RMDF061LL RSCAN0.RMDF061.UINT8[LL] +#define RSCAN0RMDF061LH RSCAN0.RMDF061.UINT8[LH] +#define RSCAN0RMDF061H RSCAN0.RMDF061.UINT16[H] +#define RSCAN0RMDF061HL RSCAN0.RMDF061.UINT8[HL] +#define RSCAN0RMDF061HH RSCAN0.RMDF061.UINT8[HH] +#define RSCAN0RMDF161 RSCAN0.RMDF161.UINT32 +#define RSCAN0RMDF161L RSCAN0.RMDF161.UINT16[L] +#define RSCAN0RMDF161LL RSCAN0.RMDF161.UINT8[LL] +#define RSCAN0RMDF161LH RSCAN0.RMDF161.UINT8[LH] +#define RSCAN0RMDF161H RSCAN0.RMDF161.UINT16[H] +#define RSCAN0RMDF161HL RSCAN0.RMDF161.UINT8[HL] +#define RSCAN0RMDF161HH RSCAN0.RMDF161.UINT8[HH] +#define RSCAN0RMID62 RSCAN0.RMID62.UINT32 +#define RSCAN0RMID62L RSCAN0.RMID62.UINT16[L] +#define RSCAN0RMID62LL RSCAN0.RMID62.UINT8[LL] +#define RSCAN0RMID62LH RSCAN0.RMID62.UINT8[LH] +#define RSCAN0RMID62H RSCAN0.RMID62.UINT16[H] +#define RSCAN0RMID62HL RSCAN0.RMID62.UINT8[HL] +#define RSCAN0RMID62HH RSCAN0.RMID62.UINT8[HH] +#define RSCAN0RMPTR62 RSCAN0.RMPTR62.UINT32 +#define RSCAN0RMPTR62L RSCAN0.RMPTR62.UINT16[L] +#define RSCAN0RMPTR62LL RSCAN0.RMPTR62.UINT8[LL] +#define RSCAN0RMPTR62LH RSCAN0.RMPTR62.UINT8[LH] +#define RSCAN0RMPTR62H RSCAN0.RMPTR62.UINT16[H] +#define RSCAN0RMPTR62HL RSCAN0.RMPTR62.UINT8[HL] +#define RSCAN0RMPTR62HH RSCAN0.RMPTR62.UINT8[HH] +#define RSCAN0RMDF062 RSCAN0.RMDF062.UINT32 +#define RSCAN0RMDF062L RSCAN0.RMDF062.UINT16[L] +#define RSCAN0RMDF062LL RSCAN0.RMDF062.UINT8[LL] +#define RSCAN0RMDF062LH RSCAN0.RMDF062.UINT8[LH] +#define RSCAN0RMDF062H RSCAN0.RMDF062.UINT16[H] +#define RSCAN0RMDF062HL RSCAN0.RMDF062.UINT8[HL] +#define RSCAN0RMDF062HH RSCAN0.RMDF062.UINT8[HH] +#define RSCAN0RMDF162 RSCAN0.RMDF162.UINT32 +#define RSCAN0RMDF162L RSCAN0.RMDF162.UINT16[L] +#define RSCAN0RMDF162LL RSCAN0.RMDF162.UINT8[LL] +#define RSCAN0RMDF162LH RSCAN0.RMDF162.UINT8[LH] +#define RSCAN0RMDF162H RSCAN0.RMDF162.UINT16[H] +#define RSCAN0RMDF162HL RSCAN0.RMDF162.UINT8[HL] +#define RSCAN0RMDF162HH RSCAN0.RMDF162.UINT8[HH] +#define RSCAN0RMID63 RSCAN0.RMID63.UINT32 +#define RSCAN0RMID63L RSCAN0.RMID63.UINT16[L] +#define RSCAN0RMID63LL RSCAN0.RMID63.UINT8[LL] +#define RSCAN0RMID63LH RSCAN0.RMID63.UINT8[LH] +#define RSCAN0RMID63H RSCAN0.RMID63.UINT16[H] +#define RSCAN0RMID63HL RSCAN0.RMID63.UINT8[HL] +#define RSCAN0RMID63HH RSCAN0.RMID63.UINT8[HH] +#define RSCAN0RMPTR63 RSCAN0.RMPTR63.UINT32 +#define RSCAN0RMPTR63L RSCAN0.RMPTR63.UINT16[L] +#define RSCAN0RMPTR63LL RSCAN0.RMPTR63.UINT8[LL] +#define RSCAN0RMPTR63LH RSCAN0.RMPTR63.UINT8[LH] +#define RSCAN0RMPTR63H RSCAN0.RMPTR63.UINT16[H] +#define RSCAN0RMPTR63HL RSCAN0.RMPTR63.UINT8[HL] +#define RSCAN0RMPTR63HH RSCAN0.RMPTR63.UINT8[HH] +#define RSCAN0RMDF063 RSCAN0.RMDF063.UINT32 +#define RSCAN0RMDF063L RSCAN0.RMDF063.UINT16[L] +#define RSCAN0RMDF063LL RSCAN0.RMDF063.UINT8[LL] +#define RSCAN0RMDF063LH RSCAN0.RMDF063.UINT8[LH] +#define RSCAN0RMDF063H RSCAN0.RMDF063.UINT16[H] +#define RSCAN0RMDF063HL RSCAN0.RMDF063.UINT8[HL] +#define RSCAN0RMDF063HH RSCAN0.RMDF063.UINT8[HH] +#define RSCAN0RMDF163 RSCAN0.RMDF163.UINT32 +#define RSCAN0RMDF163L RSCAN0.RMDF163.UINT16[L] +#define RSCAN0RMDF163LL RSCAN0.RMDF163.UINT8[LL] +#define RSCAN0RMDF163LH RSCAN0.RMDF163.UINT8[LH] +#define RSCAN0RMDF163H RSCAN0.RMDF163.UINT16[H] +#define RSCAN0RMDF163HL RSCAN0.RMDF163.UINT8[HL] +#define RSCAN0RMDF163HH RSCAN0.RMDF163.UINT8[HH] +#define RSCAN0RMID64 RSCAN0.RMID64.UINT32 +#define RSCAN0RMID64L RSCAN0.RMID64.UINT16[L] +#define RSCAN0RMID64LL RSCAN0.RMID64.UINT8[LL] +#define RSCAN0RMID64LH RSCAN0.RMID64.UINT8[LH] +#define RSCAN0RMID64H RSCAN0.RMID64.UINT16[H] +#define RSCAN0RMID64HL RSCAN0.RMID64.UINT8[HL] +#define RSCAN0RMID64HH RSCAN0.RMID64.UINT8[HH] +#define RSCAN0RMPTR64 RSCAN0.RMPTR64.UINT32 +#define RSCAN0RMPTR64L RSCAN0.RMPTR64.UINT16[L] +#define RSCAN0RMPTR64LL RSCAN0.RMPTR64.UINT8[LL] +#define RSCAN0RMPTR64LH RSCAN0.RMPTR64.UINT8[LH] +#define RSCAN0RMPTR64H RSCAN0.RMPTR64.UINT16[H] +#define RSCAN0RMPTR64HL RSCAN0.RMPTR64.UINT8[HL] +#define RSCAN0RMPTR64HH RSCAN0.RMPTR64.UINT8[HH] +#define RSCAN0RMDF064 RSCAN0.RMDF064.UINT32 +#define RSCAN0RMDF064L RSCAN0.RMDF064.UINT16[L] +#define RSCAN0RMDF064LL RSCAN0.RMDF064.UINT8[LL] +#define RSCAN0RMDF064LH RSCAN0.RMDF064.UINT8[LH] +#define RSCAN0RMDF064H RSCAN0.RMDF064.UINT16[H] +#define RSCAN0RMDF064HL RSCAN0.RMDF064.UINT8[HL] +#define RSCAN0RMDF064HH RSCAN0.RMDF064.UINT8[HH] +#define RSCAN0RMDF164 RSCAN0.RMDF164.UINT32 +#define RSCAN0RMDF164L RSCAN0.RMDF164.UINT16[L] +#define RSCAN0RMDF164LL RSCAN0.RMDF164.UINT8[LL] +#define RSCAN0RMDF164LH RSCAN0.RMDF164.UINT8[LH] +#define RSCAN0RMDF164H RSCAN0.RMDF164.UINT16[H] +#define RSCAN0RMDF164HL RSCAN0.RMDF164.UINT8[HL] +#define RSCAN0RMDF164HH RSCAN0.RMDF164.UINT8[HH] +#define RSCAN0RMID65 RSCAN0.RMID65.UINT32 +#define RSCAN0RMID65L RSCAN0.RMID65.UINT16[L] +#define RSCAN0RMID65LL RSCAN0.RMID65.UINT8[LL] +#define RSCAN0RMID65LH RSCAN0.RMID65.UINT8[LH] +#define RSCAN0RMID65H RSCAN0.RMID65.UINT16[H] +#define RSCAN0RMID65HL RSCAN0.RMID65.UINT8[HL] +#define RSCAN0RMID65HH RSCAN0.RMID65.UINT8[HH] +#define RSCAN0RMPTR65 RSCAN0.RMPTR65.UINT32 +#define RSCAN0RMPTR65L RSCAN0.RMPTR65.UINT16[L] +#define RSCAN0RMPTR65LL RSCAN0.RMPTR65.UINT8[LL] +#define RSCAN0RMPTR65LH RSCAN0.RMPTR65.UINT8[LH] +#define RSCAN0RMPTR65H RSCAN0.RMPTR65.UINT16[H] +#define RSCAN0RMPTR65HL RSCAN0.RMPTR65.UINT8[HL] +#define RSCAN0RMPTR65HH RSCAN0.RMPTR65.UINT8[HH] +#define RSCAN0RMDF065 RSCAN0.RMDF065.UINT32 +#define RSCAN0RMDF065L RSCAN0.RMDF065.UINT16[L] +#define RSCAN0RMDF065LL RSCAN0.RMDF065.UINT8[LL] +#define RSCAN0RMDF065LH RSCAN0.RMDF065.UINT8[LH] +#define RSCAN0RMDF065H RSCAN0.RMDF065.UINT16[H] +#define RSCAN0RMDF065HL RSCAN0.RMDF065.UINT8[HL] +#define RSCAN0RMDF065HH RSCAN0.RMDF065.UINT8[HH] +#define RSCAN0RMDF165 RSCAN0.RMDF165.UINT32 +#define RSCAN0RMDF165L RSCAN0.RMDF165.UINT16[L] +#define RSCAN0RMDF165LL RSCAN0.RMDF165.UINT8[LL] +#define RSCAN0RMDF165LH RSCAN0.RMDF165.UINT8[LH] +#define RSCAN0RMDF165H RSCAN0.RMDF165.UINT16[H] +#define RSCAN0RMDF165HL RSCAN0.RMDF165.UINT8[HL] +#define RSCAN0RMDF165HH RSCAN0.RMDF165.UINT8[HH] +#define RSCAN0RMID66 RSCAN0.RMID66.UINT32 +#define RSCAN0RMID66L RSCAN0.RMID66.UINT16[L] +#define RSCAN0RMID66LL RSCAN0.RMID66.UINT8[LL] +#define RSCAN0RMID66LH RSCAN0.RMID66.UINT8[LH] +#define RSCAN0RMID66H RSCAN0.RMID66.UINT16[H] +#define RSCAN0RMID66HL RSCAN0.RMID66.UINT8[HL] +#define RSCAN0RMID66HH RSCAN0.RMID66.UINT8[HH] +#define RSCAN0RMPTR66 RSCAN0.RMPTR66.UINT32 +#define RSCAN0RMPTR66L RSCAN0.RMPTR66.UINT16[L] +#define RSCAN0RMPTR66LL RSCAN0.RMPTR66.UINT8[LL] +#define RSCAN0RMPTR66LH RSCAN0.RMPTR66.UINT8[LH] +#define RSCAN0RMPTR66H RSCAN0.RMPTR66.UINT16[H] +#define RSCAN0RMPTR66HL RSCAN0.RMPTR66.UINT8[HL] +#define RSCAN0RMPTR66HH RSCAN0.RMPTR66.UINT8[HH] +#define RSCAN0RMDF066 RSCAN0.RMDF066.UINT32 +#define RSCAN0RMDF066L RSCAN0.RMDF066.UINT16[L] +#define RSCAN0RMDF066LL RSCAN0.RMDF066.UINT8[LL] +#define RSCAN0RMDF066LH RSCAN0.RMDF066.UINT8[LH] +#define RSCAN0RMDF066H RSCAN0.RMDF066.UINT16[H] +#define RSCAN0RMDF066HL RSCAN0.RMDF066.UINT8[HL] +#define RSCAN0RMDF066HH RSCAN0.RMDF066.UINT8[HH] +#define RSCAN0RMDF166 RSCAN0.RMDF166.UINT32 +#define RSCAN0RMDF166L RSCAN0.RMDF166.UINT16[L] +#define RSCAN0RMDF166LL RSCAN0.RMDF166.UINT8[LL] +#define RSCAN0RMDF166LH RSCAN0.RMDF166.UINT8[LH] +#define RSCAN0RMDF166H RSCAN0.RMDF166.UINT16[H] +#define RSCAN0RMDF166HL RSCAN0.RMDF166.UINT8[HL] +#define RSCAN0RMDF166HH RSCAN0.RMDF166.UINT8[HH] +#define RSCAN0RMID67 RSCAN0.RMID67.UINT32 +#define RSCAN0RMID67L RSCAN0.RMID67.UINT16[L] +#define RSCAN0RMID67LL RSCAN0.RMID67.UINT8[LL] +#define RSCAN0RMID67LH RSCAN0.RMID67.UINT8[LH] +#define RSCAN0RMID67H RSCAN0.RMID67.UINT16[H] +#define RSCAN0RMID67HL RSCAN0.RMID67.UINT8[HL] +#define RSCAN0RMID67HH RSCAN0.RMID67.UINT8[HH] +#define RSCAN0RMPTR67 RSCAN0.RMPTR67.UINT32 +#define RSCAN0RMPTR67L RSCAN0.RMPTR67.UINT16[L] +#define RSCAN0RMPTR67LL RSCAN0.RMPTR67.UINT8[LL] +#define RSCAN0RMPTR67LH RSCAN0.RMPTR67.UINT8[LH] +#define RSCAN0RMPTR67H RSCAN0.RMPTR67.UINT16[H] +#define RSCAN0RMPTR67HL RSCAN0.RMPTR67.UINT8[HL] +#define RSCAN0RMPTR67HH RSCAN0.RMPTR67.UINT8[HH] +#define RSCAN0RMDF067 RSCAN0.RMDF067.UINT32 +#define RSCAN0RMDF067L RSCAN0.RMDF067.UINT16[L] +#define RSCAN0RMDF067LL RSCAN0.RMDF067.UINT8[LL] +#define RSCAN0RMDF067LH RSCAN0.RMDF067.UINT8[LH] +#define RSCAN0RMDF067H RSCAN0.RMDF067.UINT16[H] +#define RSCAN0RMDF067HL RSCAN0.RMDF067.UINT8[HL] +#define RSCAN0RMDF067HH RSCAN0.RMDF067.UINT8[HH] +#define RSCAN0RMDF167 RSCAN0.RMDF167.UINT32 +#define RSCAN0RMDF167L RSCAN0.RMDF167.UINT16[L] +#define RSCAN0RMDF167LL RSCAN0.RMDF167.UINT8[LL] +#define RSCAN0RMDF167LH RSCAN0.RMDF167.UINT8[LH] +#define RSCAN0RMDF167H RSCAN0.RMDF167.UINT16[H] +#define RSCAN0RMDF167HL RSCAN0.RMDF167.UINT8[HL] +#define RSCAN0RMDF167HH RSCAN0.RMDF167.UINT8[HH] +#define RSCAN0RMID68 RSCAN0.RMID68.UINT32 +#define RSCAN0RMID68L RSCAN0.RMID68.UINT16[L] +#define RSCAN0RMID68LL RSCAN0.RMID68.UINT8[LL] +#define RSCAN0RMID68LH RSCAN0.RMID68.UINT8[LH] +#define RSCAN0RMID68H RSCAN0.RMID68.UINT16[H] +#define RSCAN0RMID68HL RSCAN0.RMID68.UINT8[HL] +#define RSCAN0RMID68HH RSCAN0.RMID68.UINT8[HH] +#define RSCAN0RMPTR68 RSCAN0.RMPTR68.UINT32 +#define RSCAN0RMPTR68L RSCAN0.RMPTR68.UINT16[L] +#define RSCAN0RMPTR68LL RSCAN0.RMPTR68.UINT8[LL] +#define RSCAN0RMPTR68LH RSCAN0.RMPTR68.UINT8[LH] +#define RSCAN0RMPTR68H RSCAN0.RMPTR68.UINT16[H] +#define RSCAN0RMPTR68HL RSCAN0.RMPTR68.UINT8[HL] +#define RSCAN0RMPTR68HH RSCAN0.RMPTR68.UINT8[HH] +#define RSCAN0RMDF068 RSCAN0.RMDF068.UINT32 +#define RSCAN0RMDF068L RSCAN0.RMDF068.UINT16[L] +#define RSCAN0RMDF068LL RSCAN0.RMDF068.UINT8[LL] +#define RSCAN0RMDF068LH RSCAN0.RMDF068.UINT8[LH] +#define RSCAN0RMDF068H RSCAN0.RMDF068.UINT16[H] +#define RSCAN0RMDF068HL RSCAN0.RMDF068.UINT8[HL] +#define RSCAN0RMDF068HH RSCAN0.RMDF068.UINT8[HH] +#define RSCAN0RMDF168 RSCAN0.RMDF168.UINT32 +#define RSCAN0RMDF168L RSCAN0.RMDF168.UINT16[L] +#define RSCAN0RMDF168LL RSCAN0.RMDF168.UINT8[LL] +#define RSCAN0RMDF168LH RSCAN0.RMDF168.UINT8[LH] +#define RSCAN0RMDF168H RSCAN0.RMDF168.UINT16[H] +#define RSCAN0RMDF168HL RSCAN0.RMDF168.UINT8[HL] +#define RSCAN0RMDF168HH RSCAN0.RMDF168.UINT8[HH] +#define RSCAN0RMID69 RSCAN0.RMID69.UINT32 +#define RSCAN0RMID69L RSCAN0.RMID69.UINT16[L] +#define RSCAN0RMID69LL RSCAN0.RMID69.UINT8[LL] +#define RSCAN0RMID69LH RSCAN0.RMID69.UINT8[LH] +#define RSCAN0RMID69H RSCAN0.RMID69.UINT16[H] +#define RSCAN0RMID69HL RSCAN0.RMID69.UINT8[HL] +#define RSCAN0RMID69HH RSCAN0.RMID69.UINT8[HH] +#define RSCAN0RMPTR69 RSCAN0.RMPTR69.UINT32 +#define RSCAN0RMPTR69L RSCAN0.RMPTR69.UINT16[L] +#define RSCAN0RMPTR69LL RSCAN0.RMPTR69.UINT8[LL] +#define RSCAN0RMPTR69LH RSCAN0.RMPTR69.UINT8[LH] +#define RSCAN0RMPTR69H RSCAN0.RMPTR69.UINT16[H] +#define RSCAN0RMPTR69HL RSCAN0.RMPTR69.UINT8[HL] +#define RSCAN0RMPTR69HH RSCAN0.RMPTR69.UINT8[HH] +#define RSCAN0RMDF069 RSCAN0.RMDF069.UINT32 +#define RSCAN0RMDF069L RSCAN0.RMDF069.UINT16[L] +#define RSCAN0RMDF069LL RSCAN0.RMDF069.UINT8[LL] +#define RSCAN0RMDF069LH RSCAN0.RMDF069.UINT8[LH] +#define RSCAN0RMDF069H RSCAN0.RMDF069.UINT16[H] +#define RSCAN0RMDF069HL RSCAN0.RMDF069.UINT8[HL] +#define RSCAN0RMDF069HH RSCAN0.RMDF069.UINT8[HH] +#define RSCAN0RMDF169 RSCAN0.RMDF169.UINT32 +#define RSCAN0RMDF169L RSCAN0.RMDF169.UINT16[L] +#define RSCAN0RMDF169LL RSCAN0.RMDF169.UINT8[LL] +#define RSCAN0RMDF169LH RSCAN0.RMDF169.UINT8[LH] +#define RSCAN0RMDF169H RSCAN0.RMDF169.UINT16[H] +#define RSCAN0RMDF169HL RSCAN0.RMDF169.UINT8[HL] +#define RSCAN0RMDF169HH RSCAN0.RMDF169.UINT8[HH] +#define RSCAN0RMID70 RSCAN0.RMID70.UINT32 +#define RSCAN0RMID70L RSCAN0.RMID70.UINT16[L] +#define RSCAN0RMID70LL RSCAN0.RMID70.UINT8[LL] +#define RSCAN0RMID70LH RSCAN0.RMID70.UINT8[LH] +#define RSCAN0RMID70H RSCAN0.RMID70.UINT16[H] +#define RSCAN0RMID70HL RSCAN0.RMID70.UINT8[HL] +#define RSCAN0RMID70HH RSCAN0.RMID70.UINT8[HH] +#define RSCAN0RMPTR70 RSCAN0.RMPTR70.UINT32 +#define RSCAN0RMPTR70L RSCAN0.RMPTR70.UINT16[L] +#define RSCAN0RMPTR70LL RSCAN0.RMPTR70.UINT8[LL] +#define RSCAN0RMPTR70LH RSCAN0.RMPTR70.UINT8[LH] +#define RSCAN0RMPTR70H RSCAN0.RMPTR70.UINT16[H] +#define RSCAN0RMPTR70HL RSCAN0.RMPTR70.UINT8[HL] +#define RSCAN0RMPTR70HH RSCAN0.RMPTR70.UINT8[HH] +#define RSCAN0RMDF070 RSCAN0.RMDF070.UINT32 +#define RSCAN0RMDF070L RSCAN0.RMDF070.UINT16[L] +#define RSCAN0RMDF070LL RSCAN0.RMDF070.UINT8[LL] +#define RSCAN0RMDF070LH RSCAN0.RMDF070.UINT8[LH] +#define RSCAN0RMDF070H RSCAN0.RMDF070.UINT16[H] +#define RSCAN0RMDF070HL RSCAN0.RMDF070.UINT8[HL] +#define RSCAN0RMDF070HH RSCAN0.RMDF070.UINT8[HH] +#define RSCAN0RMDF170 RSCAN0.RMDF170.UINT32 +#define RSCAN0RMDF170L RSCAN0.RMDF170.UINT16[L] +#define RSCAN0RMDF170LL RSCAN0.RMDF170.UINT8[LL] +#define RSCAN0RMDF170LH RSCAN0.RMDF170.UINT8[LH] +#define RSCAN0RMDF170H RSCAN0.RMDF170.UINT16[H] +#define RSCAN0RMDF170HL RSCAN0.RMDF170.UINT8[HL] +#define RSCAN0RMDF170HH RSCAN0.RMDF170.UINT8[HH] +#define RSCAN0RMID71 RSCAN0.RMID71.UINT32 +#define RSCAN0RMID71L RSCAN0.RMID71.UINT16[L] +#define RSCAN0RMID71LL RSCAN0.RMID71.UINT8[LL] +#define RSCAN0RMID71LH RSCAN0.RMID71.UINT8[LH] +#define RSCAN0RMID71H RSCAN0.RMID71.UINT16[H] +#define RSCAN0RMID71HL RSCAN0.RMID71.UINT8[HL] +#define RSCAN0RMID71HH RSCAN0.RMID71.UINT8[HH] +#define RSCAN0RMPTR71 RSCAN0.RMPTR71.UINT32 +#define RSCAN0RMPTR71L RSCAN0.RMPTR71.UINT16[L] +#define RSCAN0RMPTR71LL RSCAN0.RMPTR71.UINT8[LL] +#define RSCAN0RMPTR71LH RSCAN0.RMPTR71.UINT8[LH] +#define RSCAN0RMPTR71H RSCAN0.RMPTR71.UINT16[H] +#define RSCAN0RMPTR71HL RSCAN0.RMPTR71.UINT8[HL] +#define RSCAN0RMPTR71HH RSCAN0.RMPTR71.UINT8[HH] +#define RSCAN0RMDF071 RSCAN0.RMDF071.UINT32 +#define RSCAN0RMDF071L RSCAN0.RMDF071.UINT16[L] +#define RSCAN0RMDF071LL RSCAN0.RMDF071.UINT8[LL] +#define RSCAN0RMDF071LH RSCAN0.RMDF071.UINT8[LH] +#define RSCAN0RMDF071H RSCAN0.RMDF071.UINT16[H] +#define RSCAN0RMDF071HL RSCAN0.RMDF071.UINT8[HL] +#define RSCAN0RMDF071HH RSCAN0.RMDF071.UINT8[HH] +#define RSCAN0RMDF171 RSCAN0.RMDF171.UINT32 +#define RSCAN0RMDF171L RSCAN0.RMDF171.UINT16[L] +#define RSCAN0RMDF171LL RSCAN0.RMDF171.UINT8[LL] +#define RSCAN0RMDF171LH RSCAN0.RMDF171.UINT8[LH] +#define RSCAN0RMDF171H RSCAN0.RMDF171.UINT16[H] +#define RSCAN0RMDF171HL RSCAN0.RMDF171.UINT8[HL] +#define RSCAN0RMDF171HH RSCAN0.RMDF171.UINT8[HH] +#define RSCAN0RMID72 RSCAN0.RMID72.UINT32 +#define RSCAN0RMID72L RSCAN0.RMID72.UINT16[L] +#define RSCAN0RMID72LL RSCAN0.RMID72.UINT8[LL] +#define RSCAN0RMID72LH RSCAN0.RMID72.UINT8[LH] +#define RSCAN0RMID72H RSCAN0.RMID72.UINT16[H] +#define RSCAN0RMID72HL RSCAN0.RMID72.UINT8[HL] +#define RSCAN0RMID72HH RSCAN0.RMID72.UINT8[HH] +#define RSCAN0RMPTR72 RSCAN0.RMPTR72.UINT32 +#define RSCAN0RMPTR72L RSCAN0.RMPTR72.UINT16[L] +#define RSCAN0RMPTR72LL RSCAN0.RMPTR72.UINT8[LL] +#define RSCAN0RMPTR72LH RSCAN0.RMPTR72.UINT8[LH] +#define RSCAN0RMPTR72H RSCAN0.RMPTR72.UINT16[H] +#define RSCAN0RMPTR72HL RSCAN0.RMPTR72.UINT8[HL] +#define RSCAN0RMPTR72HH RSCAN0.RMPTR72.UINT8[HH] +#define RSCAN0RMDF072 RSCAN0.RMDF072.UINT32 +#define RSCAN0RMDF072L RSCAN0.RMDF072.UINT16[L] +#define RSCAN0RMDF072LL RSCAN0.RMDF072.UINT8[LL] +#define RSCAN0RMDF072LH RSCAN0.RMDF072.UINT8[LH] +#define RSCAN0RMDF072H RSCAN0.RMDF072.UINT16[H] +#define RSCAN0RMDF072HL RSCAN0.RMDF072.UINT8[HL] +#define RSCAN0RMDF072HH RSCAN0.RMDF072.UINT8[HH] +#define RSCAN0RMDF172 RSCAN0.RMDF172.UINT32 +#define RSCAN0RMDF172L RSCAN0.RMDF172.UINT16[L] +#define RSCAN0RMDF172LL RSCAN0.RMDF172.UINT8[LL] +#define RSCAN0RMDF172LH RSCAN0.RMDF172.UINT8[LH] +#define RSCAN0RMDF172H RSCAN0.RMDF172.UINT16[H] +#define RSCAN0RMDF172HL RSCAN0.RMDF172.UINT8[HL] +#define RSCAN0RMDF172HH RSCAN0.RMDF172.UINT8[HH] +#define RSCAN0RMID73 RSCAN0.RMID73.UINT32 +#define RSCAN0RMID73L RSCAN0.RMID73.UINT16[L] +#define RSCAN0RMID73LL RSCAN0.RMID73.UINT8[LL] +#define RSCAN0RMID73LH RSCAN0.RMID73.UINT8[LH] +#define RSCAN0RMID73H RSCAN0.RMID73.UINT16[H] +#define RSCAN0RMID73HL RSCAN0.RMID73.UINT8[HL] +#define RSCAN0RMID73HH RSCAN0.RMID73.UINT8[HH] +#define RSCAN0RMPTR73 RSCAN0.RMPTR73.UINT32 +#define RSCAN0RMPTR73L RSCAN0.RMPTR73.UINT16[L] +#define RSCAN0RMPTR73LL RSCAN0.RMPTR73.UINT8[LL] +#define RSCAN0RMPTR73LH RSCAN0.RMPTR73.UINT8[LH] +#define RSCAN0RMPTR73H RSCAN0.RMPTR73.UINT16[H] +#define RSCAN0RMPTR73HL RSCAN0.RMPTR73.UINT8[HL] +#define RSCAN0RMPTR73HH RSCAN0.RMPTR73.UINT8[HH] +#define RSCAN0RMDF073 RSCAN0.RMDF073.UINT32 +#define RSCAN0RMDF073L RSCAN0.RMDF073.UINT16[L] +#define RSCAN0RMDF073LL RSCAN0.RMDF073.UINT8[LL] +#define RSCAN0RMDF073LH RSCAN0.RMDF073.UINT8[LH] +#define RSCAN0RMDF073H RSCAN0.RMDF073.UINT16[H] +#define RSCAN0RMDF073HL RSCAN0.RMDF073.UINT8[HL] +#define RSCAN0RMDF073HH RSCAN0.RMDF073.UINT8[HH] +#define RSCAN0RMDF173 RSCAN0.RMDF173.UINT32 +#define RSCAN0RMDF173L RSCAN0.RMDF173.UINT16[L] +#define RSCAN0RMDF173LL RSCAN0.RMDF173.UINT8[LL] +#define RSCAN0RMDF173LH RSCAN0.RMDF173.UINT8[LH] +#define RSCAN0RMDF173H RSCAN0.RMDF173.UINT16[H] +#define RSCAN0RMDF173HL RSCAN0.RMDF173.UINT8[HL] +#define RSCAN0RMDF173HH RSCAN0.RMDF173.UINT8[HH] +#define RSCAN0RMID74 RSCAN0.RMID74.UINT32 +#define RSCAN0RMID74L RSCAN0.RMID74.UINT16[L] +#define RSCAN0RMID74LL RSCAN0.RMID74.UINT8[LL] +#define RSCAN0RMID74LH RSCAN0.RMID74.UINT8[LH] +#define RSCAN0RMID74H RSCAN0.RMID74.UINT16[H] +#define RSCAN0RMID74HL RSCAN0.RMID74.UINT8[HL] +#define RSCAN0RMID74HH RSCAN0.RMID74.UINT8[HH] +#define RSCAN0RMPTR74 RSCAN0.RMPTR74.UINT32 +#define RSCAN0RMPTR74L RSCAN0.RMPTR74.UINT16[L] +#define RSCAN0RMPTR74LL RSCAN0.RMPTR74.UINT8[LL] +#define RSCAN0RMPTR74LH RSCAN0.RMPTR74.UINT8[LH] +#define RSCAN0RMPTR74H RSCAN0.RMPTR74.UINT16[H] +#define RSCAN0RMPTR74HL RSCAN0.RMPTR74.UINT8[HL] +#define RSCAN0RMPTR74HH RSCAN0.RMPTR74.UINT8[HH] +#define RSCAN0RMDF074 RSCAN0.RMDF074.UINT32 +#define RSCAN0RMDF074L RSCAN0.RMDF074.UINT16[L] +#define RSCAN0RMDF074LL RSCAN0.RMDF074.UINT8[LL] +#define RSCAN0RMDF074LH RSCAN0.RMDF074.UINT8[LH] +#define RSCAN0RMDF074H RSCAN0.RMDF074.UINT16[H] +#define RSCAN0RMDF074HL RSCAN0.RMDF074.UINT8[HL] +#define RSCAN0RMDF074HH RSCAN0.RMDF074.UINT8[HH] +#define RSCAN0RMDF174 RSCAN0.RMDF174.UINT32 +#define RSCAN0RMDF174L RSCAN0.RMDF174.UINT16[L] +#define RSCAN0RMDF174LL RSCAN0.RMDF174.UINT8[LL] +#define RSCAN0RMDF174LH RSCAN0.RMDF174.UINT8[LH] +#define RSCAN0RMDF174H RSCAN0.RMDF174.UINT16[H] +#define RSCAN0RMDF174HL RSCAN0.RMDF174.UINT8[HL] +#define RSCAN0RMDF174HH RSCAN0.RMDF174.UINT8[HH] +#define RSCAN0RMID75 RSCAN0.RMID75.UINT32 +#define RSCAN0RMID75L RSCAN0.RMID75.UINT16[L] +#define RSCAN0RMID75LL RSCAN0.RMID75.UINT8[LL] +#define RSCAN0RMID75LH RSCAN0.RMID75.UINT8[LH] +#define RSCAN0RMID75H RSCAN0.RMID75.UINT16[H] +#define RSCAN0RMID75HL RSCAN0.RMID75.UINT8[HL] +#define RSCAN0RMID75HH RSCAN0.RMID75.UINT8[HH] +#define RSCAN0RMPTR75 RSCAN0.RMPTR75.UINT32 +#define RSCAN0RMPTR75L RSCAN0.RMPTR75.UINT16[L] +#define RSCAN0RMPTR75LL RSCAN0.RMPTR75.UINT8[LL] +#define RSCAN0RMPTR75LH RSCAN0.RMPTR75.UINT8[LH] +#define RSCAN0RMPTR75H RSCAN0.RMPTR75.UINT16[H] +#define RSCAN0RMPTR75HL RSCAN0.RMPTR75.UINT8[HL] +#define RSCAN0RMPTR75HH RSCAN0.RMPTR75.UINT8[HH] +#define RSCAN0RMDF075 RSCAN0.RMDF075.UINT32 +#define RSCAN0RMDF075L RSCAN0.RMDF075.UINT16[L] +#define RSCAN0RMDF075LL RSCAN0.RMDF075.UINT8[LL] +#define RSCAN0RMDF075LH RSCAN0.RMDF075.UINT8[LH] +#define RSCAN0RMDF075H RSCAN0.RMDF075.UINT16[H] +#define RSCAN0RMDF075HL RSCAN0.RMDF075.UINT8[HL] +#define RSCAN0RMDF075HH RSCAN0.RMDF075.UINT8[HH] +#define RSCAN0RMDF175 RSCAN0.RMDF175.UINT32 +#define RSCAN0RMDF175L RSCAN0.RMDF175.UINT16[L] +#define RSCAN0RMDF175LL RSCAN0.RMDF175.UINT8[LL] +#define RSCAN0RMDF175LH RSCAN0.RMDF175.UINT8[LH] +#define RSCAN0RMDF175H RSCAN0.RMDF175.UINT16[H] +#define RSCAN0RMDF175HL RSCAN0.RMDF175.UINT8[HL] +#define RSCAN0RMDF175HH RSCAN0.RMDF175.UINT8[HH] +#define RSCAN0RMID76 RSCAN0.RMID76.UINT32 +#define RSCAN0RMID76L RSCAN0.RMID76.UINT16[L] +#define RSCAN0RMID76LL RSCAN0.RMID76.UINT8[LL] +#define RSCAN0RMID76LH RSCAN0.RMID76.UINT8[LH] +#define RSCAN0RMID76H RSCAN0.RMID76.UINT16[H] +#define RSCAN0RMID76HL RSCAN0.RMID76.UINT8[HL] +#define RSCAN0RMID76HH RSCAN0.RMID76.UINT8[HH] +#define RSCAN0RMPTR76 RSCAN0.RMPTR76.UINT32 +#define RSCAN0RMPTR76L RSCAN0.RMPTR76.UINT16[L] +#define RSCAN0RMPTR76LL RSCAN0.RMPTR76.UINT8[LL] +#define RSCAN0RMPTR76LH RSCAN0.RMPTR76.UINT8[LH] +#define RSCAN0RMPTR76H RSCAN0.RMPTR76.UINT16[H] +#define RSCAN0RMPTR76HL RSCAN0.RMPTR76.UINT8[HL] +#define RSCAN0RMPTR76HH RSCAN0.RMPTR76.UINT8[HH] +#define RSCAN0RMDF076 RSCAN0.RMDF076.UINT32 +#define RSCAN0RMDF076L RSCAN0.RMDF076.UINT16[L] +#define RSCAN0RMDF076LL RSCAN0.RMDF076.UINT8[LL] +#define RSCAN0RMDF076LH RSCAN0.RMDF076.UINT8[LH] +#define RSCAN0RMDF076H RSCAN0.RMDF076.UINT16[H] +#define RSCAN0RMDF076HL RSCAN0.RMDF076.UINT8[HL] +#define RSCAN0RMDF076HH RSCAN0.RMDF076.UINT8[HH] +#define RSCAN0RMDF176 RSCAN0.RMDF176.UINT32 +#define RSCAN0RMDF176L RSCAN0.RMDF176.UINT16[L] +#define RSCAN0RMDF176LL RSCAN0.RMDF176.UINT8[LL] +#define RSCAN0RMDF176LH RSCAN0.RMDF176.UINT8[LH] +#define RSCAN0RMDF176H RSCAN0.RMDF176.UINT16[H] +#define RSCAN0RMDF176HL RSCAN0.RMDF176.UINT8[HL] +#define RSCAN0RMDF176HH RSCAN0.RMDF176.UINT8[HH] +#define RSCAN0RMID77 RSCAN0.RMID77.UINT32 +#define RSCAN0RMID77L RSCAN0.RMID77.UINT16[L] +#define RSCAN0RMID77LL RSCAN0.RMID77.UINT8[LL] +#define RSCAN0RMID77LH RSCAN0.RMID77.UINT8[LH] +#define RSCAN0RMID77H RSCAN0.RMID77.UINT16[H] +#define RSCAN0RMID77HL RSCAN0.RMID77.UINT8[HL] +#define RSCAN0RMID77HH RSCAN0.RMID77.UINT8[HH] +#define RSCAN0RMPTR77 RSCAN0.RMPTR77.UINT32 +#define RSCAN0RMPTR77L RSCAN0.RMPTR77.UINT16[L] +#define RSCAN0RMPTR77LL RSCAN0.RMPTR77.UINT8[LL] +#define RSCAN0RMPTR77LH RSCAN0.RMPTR77.UINT8[LH] +#define RSCAN0RMPTR77H RSCAN0.RMPTR77.UINT16[H] +#define RSCAN0RMPTR77HL RSCAN0.RMPTR77.UINT8[HL] +#define RSCAN0RMPTR77HH RSCAN0.RMPTR77.UINT8[HH] +#define RSCAN0RMDF077 RSCAN0.RMDF077.UINT32 +#define RSCAN0RMDF077L RSCAN0.RMDF077.UINT16[L] +#define RSCAN0RMDF077LL RSCAN0.RMDF077.UINT8[LL] +#define RSCAN0RMDF077LH RSCAN0.RMDF077.UINT8[LH] +#define RSCAN0RMDF077H RSCAN0.RMDF077.UINT16[H] +#define RSCAN0RMDF077HL RSCAN0.RMDF077.UINT8[HL] +#define RSCAN0RMDF077HH RSCAN0.RMDF077.UINT8[HH] +#define RSCAN0RMDF177 RSCAN0.RMDF177.UINT32 +#define RSCAN0RMDF177L RSCAN0.RMDF177.UINT16[L] +#define RSCAN0RMDF177LL RSCAN0.RMDF177.UINT8[LL] +#define RSCAN0RMDF177LH RSCAN0.RMDF177.UINT8[LH] +#define RSCAN0RMDF177H RSCAN0.RMDF177.UINT16[H] +#define RSCAN0RMDF177HL RSCAN0.RMDF177.UINT8[HL] +#define RSCAN0RMDF177HH RSCAN0.RMDF177.UINT8[HH] +#define RSCAN0RMID78 RSCAN0.RMID78.UINT32 +#define RSCAN0RMID78L RSCAN0.RMID78.UINT16[L] +#define RSCAN0RMID78LL RSCAN0.RMID78.UINT8[LL] +#define RSCAN0RMID78LH RSCAN0.RMID78.UINT8[LH] +#define RSCAN0RMID78H RSCAN0.RMID78.UINT16[H] +#define RSCAN0RMID78HL RSCAN0.RMID78.UINT8[HL] +#define RSCAN0RMID78HH RSCAN0.RMID78.UINT8[HH] +#define RSCAN0RMPTR78 RSCAN0.RMPTR78.UINT32 +#define RSCAN0RMPTR78L RSCAN0.RMPTR78.UINT16[L] +#define RSCAN0RMPTR78LL RSCAN0.RMPTR78.UINT8[LL] +#define RSCAN0RMPTR78LH RSCAN0.RMPTR78.UINT8[LH] +#define RSCAN0RMPTR78H RSCAN0.RMPTR78.UINT16[H] +#define RSCAN0RMPTR78HL RSCAN0.RMPTR78.UINT8[HL] +#define RSCAN0RMPTR78HH RSCAN0.RMPTR78.UINT8[HH] +#define RSCAN0RMDF078 RSCAN0.RMDF078.UINT32 +#define RSCAN0RMDF078L RSCAN0.RMDF078.UINT16[L] +#define RSCAN0RMDF078LL RSCAN0.RMDF078.UINT8[LL] +#define RSCAN0RMDF078LH RSCAN0.RMDF078.UINT8[LH] +#define RSCAN0RMDF078H RSCAN0.RMDF078.UINT16[H] +#define RSCAN0RMDF078HL RSCAN0.RMDF078.UINT8[HL] +#define RSCAN0RMDF078HH RSCAN0.RMDF078.UINT8[HH] +#define RSCAN0RMDF178 RSCAN0.RMDF178.UINT32 +#define RSCAN0RMDF178L RSCAN0.RMDF178.UINT16[L] +#define RSCAN0RMDF178LL RSCAN0.RMDF178.UINT8[LL] +#define RSCAN0RMDF178LH RSCAN0.RMDF178.UINT8[LH] +#define RSCAN0RMDF178H RSCAN0.RMDF178.UINT16[H] +#define RSCAN0RMDF178HL RSCAN0.RMDF178.UINT8[HL] +#define RSCAN0RMDF178HH RSCAN0.RMDF178.UINT8[HH] +#define RSCAN0RMID79 RSCAN0.RMID79.UINT32 +#define RSCAN0RMID79L RSCAN0.RMID79.UINT16[L] +#define RSCAN0RMID79LL RSCAN0.RMID79.UINT8[LL] +#define RSCAN0RMID79LH RSCAN0.RMID79.UINT8[LH] +#define RSCAN0RMID79H RSCAN0.RMID79.UINT16[H] +#define RSCAN0RMID79HL RSCAN0.RMID79.UINT8[HL] +#define RSCAN0RMID79HH RSCAN0.RMID79.UINT8[HH] +#define RSCAN0RMPTR79 RSCAN0.RMPTR79.UINT32 +#define RSCAN0RMPTR79L RSCAN0.RMPTR79.UINT16[L] +#define RSCAN0RMPTR79LL RSCAN0.RMPTR79.UINT8[LL] +#define RSCAN0RMPTR79LH RSCAN0.RMPTR79.UINT8[LH] +#define RSCAN0RMPTR79H RSCAN0.RMPTR79.UINT16[H] +#define RSCAN0RMPTR79HL RSCAN0.RMPTR79.UINT8[HL] +#define RSCAN0RMPTR79HH RSCAN0.RMPTR79.UINT8[HH] +#define RSCAN0RMDF079 RSCAN0.RMDF079.UINT32 +#define RSCAN0RMDF079L RSCAN0.RMDF079.UINT16[L] +#define RSCAN0RMDF079LL RSCAN0.RMDF079.UINT8[LL] +#define RSCAN0RMDF079LH RSCAN0.RMDF079.UINT8[LH] +#define RSCAN0RMDF079H RSCAN0.RMDF079.UINT16[H] +#define RSCAN0RMDF079HL RSCAN0.RMDF079.UINT8[HL] +#define RSCAN0RMDF079HH RSCAN0.RMDF079.UINT8[HH] +#define RSCAN0RMDF179 RSCAN0.RMDF179.UINT32 +#define RSCAN0RMDF179L RSCAN0.RMDF179.UINT16[L] +#define RSCAN0RMDF179LL RSCAN0.RMDF179.UINT8[LL] +#define RSCAN0RMDF179LH RSCAN0.RMDF179.UINT8[LH] +#define RSCAN0RMDF179H RSCAN0.RMDF179.UINT16[H] +#define RSCAN0RMDF179HL RSCAN0.RMDF179.UINT8[HL] +#define RSCAN0RMDF179HH RSCAN0.RMDF179.UINT8[HH] +#define RSCAN0RFID0 RSCAN0.RFID0.UINT32 +#define RSCAN0RFID0L RSCAN0.RFID0.UINT16[L] +#define RSCAN0RFID0LL RSCAN0.RFID0.UINT8[LL] +#define RSCAN0RFID0LH RSCAN0.RFID0.UINT8[LH] +#define RSCAN0RFID0H RSCAN0.RFID0.UINT16[H] +#define RSCAN0RFID0HL RSCAN0.RFID0.UINT8[HL] +#define RSCAN0RFID0HH RSCAN0.RFID0.UINT8[HH] +#define RSCAN0RFPTR0 RSCAN0.RFPTR0.UINT32 +#define RSCAN0RFPTR0L RSCAN0.RFPTR0.UINT16[L] +#define RSCAN0RFPTR0LL RSCAN0.RFPTR0.UINT8[LL] +#define RSCAN0RFPTR0LH RSCAN0.RFPTR0.UINT8[LH] +#define RSCAN0RFPTR0H RSCAN0.RFPTR0.UINT16[H] +#define RSCAN0RFPTR0HL RSCAN0.RFPTR0.UINT8[HL] +#define RSCAN0RFPTR0HH RSCAN0.RFPTR0.UINT8[HH] +#define RSCAN0RFDF00 RSCAN0.RFDF00.UINT32 +#define RSCAN0RFDF00L RSCAN0.RFDF00.UINT16[L] +#define RSCAN0RFDF00LL RSCAN0.RFDF00.UINT8[LL] +#define RSCAN0RFDF00LH RSCAN0.RFDF00.UINT8[LH] +#define RSCAN0RFDF00H RSCAN0.RFDF00.UINT16[H] +#define RSCAN0RFDF00HL RSCAN0.RFDF00.UINT8[HL] +#define RSCAN0RFDF00HH RSCAN0.RFDF00.UINT8[HH] +#define RSCAN0RFDF10 RSCAN0.RFDF10.UINT32 +#define RSCAN0RFDF10L RSCAN0.RFDF10.UINT16[L] +#define RSCAN0RFDF10LL RSCAN0.RFDF10.UINT8[LL] +#define RSCAN0RFDF10LH RSCAN0.RFDF10.UINT8[LH] +#define RSCAN0RFDF10H RSCAN0.RFDF10.UINT16[H] +#define RSCAN0RFDF10HL RSCAN0.RFDF10.UINT8[HL] +#define RSCAN0RFDF10HH RSCAN0.RFDF10.UINT8[HH] +#define RSCAN0RFID1 RSCAN0.RFID1.UINT32 +#define RSCAN0RFID1L RSCAN0.RFID1.UINT16[L] +#define RSCAN0RFID1LL RSCAN0.RFID1.UINT8[LL] +#define RSCAN0RFID1LH RSCAN0.RFID1.UINT8[LH] +#define RSCAN0RFID1H RSCAN0.RFID1.UINT16[H] +#define RSCAN0RFID1HL RSCAN0.RFID1.UINT8[HL] +#define RSCAN0RFID1HH RSCAN0.RFID1.UINT8[HH] +#define RSCAN0RFPTR1 RSCAN0.RFPTR1.UINT32 +#define RSCAN0RFPTR1L RSCAN0.RFPTR1.UINT16[L] +#define RSCAN0RFPTR1LL RSCAN0.RFPTR1.UINT8[LL] +#define RSCAN0RFPTR1LH RSCAN0.RFPTR1.UINT8[LH] +#define RSCAN0RFPTR1H RSCAN0.RFPTR1.UINT16[H] +#define RSCAN0RFPTR1HL RSCAN0.RFPTR1.UINT8[HL] +#define RSCAN0RFPTR1HH RSCAN0.RFPTR1.UINT8[HH] +#define RSCAN0RFDF01 RSCAN0.RFDF01.UINT32 +#define RSCAN0RFDF01L RSCAN0.RFDF01.UINT16[L] +#define RSCAN0RFDF01LL RSCAN0.RFDF01.UINT8[LL] +#define RSCAN0RFDF01LH RSCAN0.RFDF01.UINT8[LH] +#define RSCAN0RFDF01H RSCAN0.RFDF01.UINT16[H] +#define RSCAN0RFDF01HL RSCAN0.RFDF01.UINT8[HL] +#define RSCAN0RFDF01HH RSCAN0.RFDF01.UINT8[HH] +#define RSCAN0RFDF11 RSCAN0.RFDF11.UINT32 +#define RSCAN0RFDF11L RSCAN0.RFDF11.UINT16[L] +#define RSCAN0RFDF11LL RSCAN0.RFDF11.UINT8[LL] +#define RSCAN0RFDF11LH RSCAN0.RFDF11.UINT8[LH] +#define RSCAN0RFDF11H RSCAN0.RFDF11.UINT16[H] +#define RSCAN0RFDF11HL RSCAN0.RFDF11.UINT8[HL] +#define RSCAN0RFDF11HH RSCAN0.RFDF11.UINT8[HH] +#define RSCAN0RFID2 RSCAN0.RFID2.UINT32 +#define RSCAN0RFID2L RSCAN0.RFID2.UINT16[L] +#define RSCAN0RFID2LL RSCAN0.RFID2.UINT8[LL] +#define RSCAN0RFID2LH RSCAN0.RFID2.UINT8[LH] +#define RSCAN0RFID2H RSCAN0.RFID2.UINT16[H] +#define RSCAN0RFID2HL RSCAN0.RFID2.UINT8[HL] +#define RSCAN0RFID2HH RSCAN0.RFID2.UINT8[HH] +#define RSCAN0RFPTR2 RSCAN0.RFPTR2.UINT32 +#define RSCAN0RFPTR2L RSCAN0.RFPTR2.UINT16[L] +#define RSCAN0RFPTR2LL RSCAN0.RFPTR2.UINT8[LL] +#define RSCAN0RFPTR2LH RSCAN0.RFPTR2.UINT8[LH] +#define RSCAN0RFPTR2H RSCAN0.RFPTR2.UINT16[H] +#define RSCAN0RFPTR2HL RSCAN0.RFPTR2.UINT8[HL] +#define RSCAN0RFPTR2HH RSCAN0.RFPTR2.UINT8[HH] +#define RSCAN0RFDF02 RSCAN0.RFDF02.UINT32 +#define RSCAN0RFDF02L RSCAN0.RFDF02.UINT16[L] +#define RSCAN0RFDF02LL RSCAN0.RFDF02.UINT8[LL] +#define RSCAN0RFDF02LH RSCAN0.RFDF02.UINT8[LH] +#define RSCAN0RFDF02H RSCAN0.RFDF02.UINT16[H] +#define RSCAN0RFDF02HL RSCAN0.RFDF02.UINT8[HL] +#define RSCAN0RFDF02HH RSCAN0.RFDF02.UINT8[HH] +#define RSCAN0RFDF12 RSCAN0.RFDF12.UINT32 +#define RSCAN0RFDF12L RSCAN0.RFDF12.UINT16[L] +#define RSCAN0RFDF12LL RSCAN0.RFDF12.UINT8[LL] +#define RSCAN0RFDF12LH RSCAN0.RFDF12.UINT8[LH] +#define RSCAN0RFDF12H RSCAN0.RFDF12.UINT16[H] +#define RSCAN0RFDF12HL RSCAN0.RFDF12.UINT8[HL] +#define RSCAN0RFDF12HH RSCAN0.RFDF12.UINT8[HH] +#define RSCAN0RFID3 RSCAN0.RFID3.UINT32 +#define RSCAN0RFID3L RSCAN0.RFID3.UINT16[L] +#define RSCAN0RFID3LL RSCAN0.RFID3.UINT8[LL] +#define RSCAN0RFID3LH RSCAN0.RFID3.UINT8[LH] +#define RSCAN0RFID3H RSCAN0.RFID3.UINT16[H] +#define RSCAN0RFID3HL RSCAN0.RFID3.UINT8[HL] +#define RSCAN0RFID3HH RSCAN0.RFID3.UINT8[HH] +#define RSCAN0RFPTR3 RSCAN0.RFPTR3.UINT32 +#define RSCAN0RFPTR3L RSCAN0.RFPTR3.UINT16[L] +#define RSCAN0RFPTR3LL RSCAN0.RFPTR3.UINT8[LL] +#define RSCAN0RFPTR3LH RSCAN0.RFPTR3.UINT8[LH] +#define RSCAN0RFPTR3H RSCAN0.RFPTR3.UINT16[H] +#define RSCAN0RFPTR3HL RSCAN0.RFPTR3.UINT8[HL] +#define RSCAN0RFPTR3HH RSCAN0.RFPTR3.UINT8[HH] +#define RSCAN0RFDF03 RSCAN0.RFDF03.UINT32 +#define RSCAN0RFDF03L RSCAN0.RFDF03.UINT16[L] +#define RSCAN0RFDF03LL RSCAN0.RFDF03.UINT8[LL] +#define RSCAN0RFDF03LH RSCAN0.RFDF03.UINT8[LH] +#define RSCAN0RFDF03H RSCAN0.RFDF03.UINT16[H] +#define RSCAN0RFDF03HL RSCAN0.RFDF03.UINT8[HL] +#define RSCAN0RFDF03HH RSCAN0.RFDF03.UINT8[HH] +#define RSCAN0RFDF13 RSCAN0.RFDF13.UINT32 +#define RSCAN0RFDF13L RSCAN0.RFDF13.UINT16[L] +#define RSCAN0RFDF13LL RSCAN0.RFDF13.UINT8[LL] +#define RSCAN0RFDF13LH RSCAN0.RFDF13.UINT8[LH] +#define RSCAN0RFDF13H RSCAN0.RFDF13.UINT16[H] +#define RSCAN0RFDF13HL RSCAN0.RFDF13.UINT8[HL] +#define RSCAN0RFDF13HH RSCAN0.RFDF13.UINT8[HH] +#define RSCAN0RFID4 RSCAN0.RFID4.UINT32 +#define RSCAN0RFID4L RSCAN0.RFID4.UINT16[L] +#define RSCAN0RFID4LL RSCAN0.RFID4.UINT8[LL] +#define RSCAN0RFID4LH RSCAN0.RFID4.UINT8[LH] +#define RSCAN0RFID4H RSCAN0.RFID4.UINT16[H] +#define RSCAN0RFID4HL RSCAN0.RFID4.UINT8[HL] +#define RSCAN0RFID4HH RSCAN0.RFID4.UINT8[HH] +#define RSCAN0RFPTR4 RSCAN0.RFPTR4.UINT32 +#define RSCAN0RFPTR4L RSCAN0.RFPTR4.UINT16[L] +#define RSCAN0RFPTR4LL RSCAN0.RFPTR4.UINT8[LL] +#define RSCAN0RFPTR4LH RSCAN0.RFPTR4.UINT8[LH] +#define RSCAN0RFPTR4H RSCAN0.RFPTR4.UINT16[H] +#define RSCAN0RFPTR4HL RSCAN0.RFPTR4.UINT8[HL] +#define RSCAN0RFPTR4HH RSCAN0.RFPTR4.UINT8[HH] +#define RSCAN0RFDF04 RSCAN0.RFDF04.UINT32 +#define RSCAN0RFDF04L RSCAN0.RFDF04.UINT16[L] +#define RSCAN0RFDF04LL RSCAN0.RFDF04.UINT8[LL] +#define RSCAN0RFDF04LH RSCAN0.RFDF04.UINT8[LH] +#define RSCAN0RFDF04H RSCAN0.RFDF04.UINT16[H] +#define RSCAN0RFDF04HL RSCAN0.RFDF04.UINT8[HL] +#define RSCAN0RFDF04HH RSCAN0.RFDF04.UINT8[HH] +#define RSCAN0RFDF14 RSCAN0.RFDF14.UINT32 +#define RSCAN0RFDF14L RSCAN0.RFDF14.UINT16[L] +#define RSCAN0RFDF14LL RSCAN0.RFDF14.UINT8[LL] +#define RSCAN0RFDF14LH RSCAN0.RFDF14.UINT8[LH] +#define RSCAN0RFDF14H RSCAN0.RFDF14.UINT16[H] +#define RSCAN0RFDF14HL RSCAN0.RFDF14.UINT8[HL] +#define RSCAN0RFDF14HH RSCAN0.RFDF14.UINT8[HH] +#define RSCAN0RFID5 RSCAN0.RFID5.UINT32 +#define RSCAN0RFID5L RSCAN0.RFID5.UINT16[L] +#define RSCAN0RFID5LL RSCAN0.RFID5.UINT8[LL] +#define RSCAN0RFID5LH RSCAN0.RFID5.UINT8[LH] +#define RSCAN0RFID5H RSCAN0.RFID5.UINT16[H] +#define RSCAN0RFID5HL RSCAN0.RFID5.UINT8[HL] +#define RSCAN0RFID5HH RSCAN0.RFID5.UINT8[HH] +#define RSCAN0RFPTR5 RSCAN0.RFPTR5.UINT32 +#define RSCAN0RFPTR5L RSCAN0.RFPTR5.UINT16[L] +#define RSCAN0RFPTR5LL RSCAN0.RFPTR5.UINT8[LL] +#define RSCAN0RFPTR5LH RSCAN0.RFPTR5.UINT8[LH] +#define RSCAN0RFPTR5H RSCAN0.RFPTR5.UINT16[H] +#define RSCAN0RFPTR5HL RSCAN0.RFPTR5.UINT8[HL] +#define RSCAN0RFPTR5HH RSCAN0.RFPTR5.UINT8[HH] +#define RSCAN0RFDF05 RSCAN0.RFDF05.UINT32 +#define RSCAN0RFDF05L RSCAN0.RFDF05.UINT16[L] +#define RSCAN0RFDF05LL RSCAN0.RFDF05.UINT8[LL] +#define RSCAN0RFDF05LH RSCAN0.RFDF05.UINT8[LH] +#define RSCAN0RFDF05H RSCAN0.RFDF05.UINT16[H] +#define RSCAN0RFDF05HL RSCAN0.RFDF05.UINT8[HL] +#define RSCAN0RFDF05HH RSCAN0.RFDF05.UINT8[HH] +#define RSCAN0RFDF15 RSCAN0.RFDF15.UINT32 +#define RSCAN0RFDF15L RSCAN0.RFDF15.UINT16[L] +#define RSCAN0RFDF15LL RSCAN0.RFDF15.UINT8[LL] +#define RSCAN0RFDF15LH RSCAN0.RFDF15.UINT8[LH] +#define RSCAN0RFDF15H RSCAN0.RFDF15.UINT16[H] +#define RSCAN0RFDF15HL RSCAN0.RFDF15.UINT8[HL] +#define RSCAN0RFDF15HH RSCAN0.RFDF15.UINT8[HH] +#define RSCAN0RFID6 RSCAN0.RFID6.UINT32 +#define RSCAN0RFID6L RSCAN0.RFID6.UINT16[L] +#define RSCAN0RFID6LL RSCAN0.RFID6.UINT8[LL] +#define RSCAN0RFID6LH RSCAN0.RFID6.UINT8[LH] +#define RSCAN0RFID6H RSCAN0.RFID6.UINT16[H] +#define RSCAN0RFID6HL RSCAN0.RFID6.UINT8[HL] +#define RSCAN0RFID6HH RSCAN0.RFID6.UINT8[HH] +#define RSCAN0RFPTR6 RSCAN0.RFPTR6.UINT32 +#define RSCAN0RFPTR6L RSCAN0.RFPTR6.UINT16[L] +#define RSCAN0RFPTR6LL RSCAN0.RFPTR6.UINT8[LL] +#define RSCAN0RFPTR6LH RSCAN0.RFPTR6.UINT8[LH] +#define RSCAN0RFPTR6H RSCAN0.RFPTR6.UINT16[H] +#define RSCAN0RFPTR6HL RSCAN0.RFPTR6.UINT8[HL] +#define RSCAN0RFPTR6HH RSCAN0.RFPTR6.UINT8[HH] +#define RSCAN0RFDF06 RSCAN0.RFDF06.UINT32 +#define RSCAN0RFDF06L RSCAN0.RFDF06.UINT16[L] +#define RSCAN0RFDF06LL RSCAN0.RFDF06.UINT8[LL] +#define RSCAN0RFDF06LH RSCAN0.RFDF06.UINT8[LH] +#define RSCAN0RFDF06H RSCAN0.RFDF06.UINT16[H] +#define RSCAN0RFDF06HL RSCAN0.RFDF06.UINT8[HL] +#define RSCAN0RFDF06HH RSCAN0.RFDF06.UINT8[HH] +#define RSCAN0RFDF16 RSCAN0.RFDF16.UINT32 +#define RSCAN0RFDF16L RSCAN0.RFDF16.UINT16[L] +#define RSCAN0RFDF16LL RSCAN0.RFDF16.UINT8[LL] +#define RSCAN0RFDF16LH RSCAN0.RFDF16.UINT8[LH] +#define RSCAN0RFDF16H RSCAN0.RFDF16.UINT16[H] +#define RSCAN0RFDF16HL RSCAN0.RFDF16.UINT8[HL] +#define RSCAN0RFDF16HH RSCAN0.RFDF16.UINT8[HH] +#define RSCAN0RFID7 RSCAN0.RFID7.UINT32 +#define RSCAN0RFID7L RSCAN0.RFID7.UINT16[L] +#define RSCAN0RFID7LL RSCAN0.RFID7.UINT8[LL] +#define RSCAN0RFID7LH RSCAN0.RFID7.UINT8[LH] +#define RSCAN0RFID7H RSCAN0.RFID7.UINT16[H] +#define RSCAN0RFID7HL RSCAN0.RFID7.UINT8[HL] +#define RSCAN0RFID7HH RSCAN0.RFID7.UINT8[HH] +#define RSCAN0RFPTR7 RSCAN0.RFPTR7.UINT32 +#define RSCAN0RFPTR7L RSCAN0.RFPTR7.UINT16[L] +#define RSCAN0RFPTR7LL RSCAN0.RFPTR7.UINT8[LL] +#define RSCAN0RFPTR7LH RSCAN0.RFPTR7.UINT8[LH] +#define RSCAN0RFPTR7H RSCAN0.RFPTR7.UINT16[H] +#define RSCAN0RFPTR7HL RSCAN0.RFPTR7.UINT8[HL] +#define RSCAN0RFPTR7HH RSCAN0.RFPTR7.UINT8[HH] +#define RSCAN0RFDF07 RSCAN0.RFDF07.UINT32 +#define RSCAN0RFDF07L RSCAN0.RFDF07.UINT16[L] +#define RSCAN0RFDF07LL RSCAN0.RFDF07.UINT8[LL] +#define RSCAN0RFDF07LH RSCAN0.RFDF07.UINT8[LH] +#define RSCAN0RFDF07H RSCAN0.RFDF07.UINT16[H] +#define RSCAN0RFDF07HL RSCAN0.RFDF07.UINT8[HL] +#define RSCAN0RFDF07HH RSCAN0.RFDF07.UINT8[HH] +#define RSCAN0RFDF17 RSCAN0.RFDF17.UINT32 +#define RSCAN0RFDF17L RSCAN0.RFDF17.UINT16[L] +#define RSCAN0RFDF17LL RSCAN0.RFDF17.UINT8[LL] +#define RSCAN0RFDF17LH RSCAN0.RFDF17.UINT8[LH] +#define RSCAN0RFDF17H RSCAN0.RFDF17.UINT16[H] +#define RSCAN0RFDF17HL RSCAN0.RFDF17.UINT8[HL] +#define RSCAN0RFDF17HH RSCAN0.RFDF17.UINT8[HH] +#define RSCAN0CFID0 RSCAN0.CFID0.UINT32 +#define RSCAN0CFID0L RSCAN0.CFID0.UINT16[L] +#define RSCAN0CFID0LL RSCAN0.CFID0.UINT8[LL] +#define RSCAN0CFID0LH RSCAN0.CFID0.UINT8[LH] +#define RSCAN0CFID0H RSCAN0.CFID0.UINT16[H] +#define RSCAN0CFID0HL RSCAN0.CFID0.UINT8[HL] +#define RSCAN0CFID0HH RSCAN0.CFID0.UINT8[HH] +#define RSCAN0CFPTR0 RSCAN0.CFPTR0.UINT32 +#define RSCAN0CFPTR0L RSCAN0.CFPTR0.UINT16[L] +#define RSCAN0CFPTR0LL RSCAN0.CFPTR0.UINT8[LL] +#define RSCAN0CFPTR0LH RSCAN0.CFPTR0.UINT8[LH] +#define RSCAN0CFPTR0H RSCAN0.CFPTR0.UINT16[H] +#define RSCAN0CFPTR0HL RSCAN0.CFPTR0.UINT8[HL] +#define RSCAN0CFPTR0HH RSCAN0.CFPTR0.UINT8[HH] +#define RSCAN0CFDF00 RSCAN0.CFDF00.UINT32 +#define RSCAN0CFDF00L RSCAN0.CFDF00.UINT16[L] +#define RSCAN0CFDF00LL RSCAN0.CFDF00.UINT8[LL] +#define RSCAN0CFDF00LH RSCAN0.CFDF00.UINT8[LH] +#define RSCAN0CFDF00H RSCAN0.CFDF00.UINT16[H] +#define RSCAN0CFDF00HL RSCAN0.CFDF00.UINT8[HL] +#define RSCAN0CFDF00HH RSCAN0.CFDF00.UINT8[HH] +#define RSCAN0CFDF10 RSCAN0.CFDF10.UINT32 +#define RSCAN0CFDF10L RSCAN0.CFDF10.UINT16[L] +#define RSCAN0CFDF10LL RSCAN0.CFDF10.UINT8[LL] +#define RSCAN0CFDF10LH RSCAN0.CFDF10.UINT8[LH] +#define RSCAN0CFDF10H RSCAN0.CFDF10.UINT16[H] +#define RSCAN0CFDF10HL RSCAN0.CFDF10.UINT8[HL] +#define RSCAN0CFDF10HH RSCAN0.CFDF10.UINT8[HH] +#define RSCAN0CFID1 RSCAN0.CFID1.UINT32 +#define RSCAN0CFID1L RSCAN0.CFID1.UINT16[L] +#define RSCAN0CFID1LL RSCAN0.CFID1.UINT8[LL] +#define RSCAN0CFID1LH RSCAN0.CFID1.UINT8[LH] +#define RSCAN0CFID1H RSCAN0.CFID1.UINT16[H] +#define RSCAN0CFID1HL RSCAN0.CFID1.UINT8[HL] +#define RSCAN0CFID1HH RSCAN0.CFID1.UINT8[HH] +#define RSCAN0CFPTR1 RSCAN0.CFPTR1.UINT32 +#define RSCAN0CFPTR1L RSCAN0.CFPTR1.UINT16[L] +#define RSCAN0CFPTR1LL RSCAN0.CFPTR1.UINT8[LL] +#define RSCAN0CFPTR1LH RSCAN0.CFPTR1.UINT8[LH] +#define RSCAN0CFPTR1H RSCAN0.CFPTR1.UINT16[H] +#define RSCAN0CFPTR1HL RSCAN0.CFPTR1.UINT8[HL] +#define RSCAN0CFPTR1HH RSCAN0.CFPTR1.UINT8[HH] +#define RSCAN0CFDF01 RSCAN0.CFDF01.UINT32 +#define RSCAN0CFDF01L RSCAN0.CFDF01.UINT16[L] +#define RSCAN0CFDF01LL RSCAN0.CFDF01.UINT8[LL] +#define RSCAN0CFDF01LH RSCAN0.CFDF01.UINT8[LH] +#define RSCAN0CFDF01H RSCAN0.CFDF01.UINT16[H] +#define RSCAN0CFDF01HL RSCAN0.CFDF01.UINT8[HL] +#define RSCAN0CFDF01HH RSCAN0.CFDF01.UINT8[HH] +#define RSCAN0CFDF11 RSCAN0.CFDF11.UINT32 +#define RSCAN0CFDF11L RSCAN0.CFDF11.UINT16[L] +#define RSCAN0CFDF11LL RSCAN0.CFDF11.UINT8[LL] +#define RSCAN0CFDF11LH RSCAN0.CFDF11.UINT8[LH] +#define RSCAN0CFDF11H RSCAN0.CFDF11.UINT16[H] +#define RSCAN0CFDF11HL RSCAN0.CFDF11.UINT8[HL] +#define RSCAN0CFDF11HH RSCAN0.CFDF11.UINT8[HH] +#define RSCAN0CFID2 RSCAN0.CFID2.UINT32 +#define RSCAN0CFID2L RSCAN0.CFID2.UINT16[L] +#define RSCAN0CFID2LL RSCAN0.CFID2.UINT8[LL] +#define RSCAN0CFID2LH RSCAN0.CFID2.UINT8[LH] +#define RSCAN0CFID2H RSCAN0.CFID2.UINT16[H] +#define RSCAN0CFID2HL RSCAN0.CFID2.UINT8[HL] +#define RSCAN0CFID2HH RSCAN0.CFID2.UINT8[HH] +#define RSCAN0CFPTR2 RSCAN0.CFPTR2.UINT32 +#define RSCAN0CFPTR2L RSCAN0.CFPTR2.UINT16[L] +#define RSCAN0CFPTR2LL RSCAN0.CFPTR2.UINT8[LL] +#define RSCAN0CFPTR2LH RSCAN0.CFPTR2.UINT8[LH] +#define RSCAN0CFPTR2H RSCAN0.CFPTR2.UINT16[H] +#define RSCAN0CFPTR2HL RSCAN0.CFPTR2.UINT8[HL] +#define RSCAN0CFPTR2HH RSCAN0.CFPTR2.UINT8[HH] +#define RSCAN0CFDF02 RSCAN0.CFDF02.UINT32 +#define RSCAN0CFDF02L RSCAN0.CFDF02.UINT16[L] +#define RSCAN0CFDF02LL RSCAN0.CFDF02.UINT8[LL] +#define RSCAN0CFDF02LH RSCAN0.CFDF02.UINT8[LH] +#define RSCAN0CFDF02H RSCAN0.CFDF02.UINT16[H] +#define RSCAN0CFDF02HL RSCAN0.CFDF02.UINT8[HL] +#define RSCAN0CFDF02HH RSCAN0.CFDF02.UINT8[HH] +#define RSCAN0CFDF12 RSCAN0.CFDF12.UINT32 +#define RSCAN0CFDF12L RSCAN0.CFDF12.UINT16[L] +#define RSCAN0CFDF12LL RSCAN0.CFDF12.UINT8[LL] +#define RSCAN0CFDF12LH RSCAN0.CFDF12.UINT8[LH] +#define RSCAN0CFDF12H RSCAN0.CFDF12.UINT16[H] +#define RSCAN0CFDF12HL RSCAN0.CFDF12.UINT8[HL] +#define RSCAN0CFDF12HH RSCAN0.CFDF12.UINT8[HH] +#define RSCAN0CFID3 RSCAN0.CFID3.UINT32 +#define RSCAN0CFID3L RSCAN0.CFID3.UINT16[L] +#define RSCAN0CFID3LL RSCAN0.CFID3.UINT8[LL] +#define RSCAN0CFID3LH RSCAN0.CFID3.UINT8[LH] +#define RSCAN0CFID3H RSCAN0.CFID3.UINT16[H] +#define RSCAN0CFID3HL RSCAN0.CFID3.UINT8[HL] +#define RSCAN0CFID3HH RSCAN0.CFID3.UINT8[HH] +#define RSCAN0CFPTR3 RSCAN0.CFPTR3.UINT32 +#define RSCAN0CFPTR3L RSCAN0.CFPTR3.UINT16[L] +#define RSCAN0CFPTR3LL RSCAN0.CFPTR3.UINT8[LL] +#define RSCAN0CFPTR3LH RSCAN0.CFPTR3.UINT8[LH] +#define RSCAN0CFPTR3H RSCAN0.CFPTR3.UINT16[H] +#define RSCAN0CFPTR3HL RSCAN0.CFPTR3.UINT8[HL] +#define RSCAN0CFPTR3HH RSCAN0.CFPTR3.UINT8[HH] +#define RSCAN0CFDF03 RSCAN0.CFDF03.UINT32 +#define RSCAN0CFDF03L RSCAN0.CFDF03.UINT16[L] +#define RSCAN0CFDF03LL RSCAN0.CFDF03.UINT8[LL] +#define RSCAN0CFDF03LH RSCAN0.CFDF03.UINT8[LH] +#define RSCAN0CFDF03H RSCAN0.CFDF03.UINT16[H] +#define RSCAN0CFDF03HL RSCAN0.CFDF03.UINT8[HL] +#define RSCAN0CFDF03HH RSCAN0.CFDF03.UINT8[HH] +#define RSCAN0CFDF13 RSCAN0.CFDF13.UINT32 +#define RSCAN0CFDF13L RSCAN0.CFDF13.UINT16[L] +#define RSCAN0CFDF13LL RSCAN0.CFDF13.UINT8[LL] +#define RSCAN0CFDF13LH RSCAN0.CFDF13.UINT8[LH] +#define RSCAN0CFDF13H RSCAN0.CFDF13.UINT16[H] +#define RSCAN0CFDF13HL RSCAN0.CFDF13.UINT8[HL] +#define RSCAN0CFDF13HH RSCAN0.CFDF13.UINT8[HH] +#define RSCAN0CFID4 RSCAN0.CFID4.UINT32 +#define RSCAN0CFID4L RSCAN0.CFID4.UINT16[L] +#define RSCAN0CFID4LL RSCAN0.CFID4.UINT8[LL] +#define RSCAN0CFID4LH RSCAN0.CFID4.UINT8[LH] +#define RSCAN0CFID4H RSCAN0.CFID4.UINT16[H] +#define RSCAN0CFID4HL RSCAN0.CFID4.UINT8[HL] +#define RSCAN0CFID4HH RSCAN0.CFID4.UINT8[HH] +#define RSCAN0CFPTR4 RSCAN0.CFPTR4.UINT32 +#define RSCAN0CFPTR4L RSCAN0.CFPTR4.UINT16[L] +#define RSCAN0CFPTR4LL RSCAN0.CFPTR4.UINT8[LL] +#define RSCAN0CFPTR4LH RSCAN0.CFPTR4.UINT8[LH] +#define RSCAN0CFPTR4H RSCAN0.CFPTR4.UINT16[H] +#define RSCAN0CFPTR4HL RSCAN0.CFPTR4.UINT8[HL] +#define RSCAN0CFPTR4HH RSCAN0.CFPTR4.UINT8[HH] +#define RSCAN0CFDF04 RSCAN0.CFDF04.UINT32 +#define RSCAN0CFDF04L RSCAN0.CFDF04.UINT16[L] +#define RSCAN0CFDF04LL RSCAN0.CFDF04.UINT8[LL] +#define RSCAN0CFDF04LH RSCAN0.CFDF04.UINT8[LH] +#define RSCAN0CFDF04H RSCAN0.CFDF04.UINT16[H] +#define RSCAN0CFDF04HL RSCAN0.CFDF04.UINT8[HL] +#define RSCAN0CFDF04HH RSCAN0.CFDF04.UINT8[HH] +#define RSCAN0CFDF14 RSCAN0.CFDF14.UINT32 +#define RSCAN0CFDF14L RSCAN0.CFDF14.UINT16[L] +#define RSCAN0CFDF14LL RSCAN0.CFDF14.UINT8[LL] +#define RSCAN0CFDF14LH RSCAN0.CFDF14.UINT8[LH] +#define RSCAN0CFDF14H RSCAN0.CFDF14.UINT16[H] +#define RSCAN0CFDF14HL RSCAN0.CFDF14.UINT8[HL] +#define RSCAN0CFDF14HH RSCAN0.CFDF14.UINT8[HH] +#define RSCAN0CFID5 RSCAN0.CFID5.UINT32 +#define RSCAN0CFID5L RSCAN0.CFID5.UINT16[L] +#define RSCAN0CFID5LL RSCAN0.CFID5.UINT8[LL] +#define RSCAN0CFID5LH RSCAN0.CFID5.UINT8[LH] +#define RSCAN0CFID5H RSCAN0.CFID5.UINT16[H] +#define RSCAN0CFID5HL RSCAN0.CFID5.UINT8[HL] +#define RSCAN0CFID5HH RSCAN0.CFID5.UINT8[HH] +#define RSCAN0CFPTR5 RSCAN0.CFPTR5.UINT32 +#define RSCAN0CFPTR5L RSCAN0.CFPTR5.UINT16[L] +#define RSCAN0CFPTR5LL RSCAN0.CFPTR5.UINT8[LL] +#define RSCAN0CFPTR5LH RSCAN0.CFPTR5.UINT8[LH] +#define RSCAN0CFPTR5H RSCAN0.CFPTR5.UINT16[H] +#define RSCAN0CFPTR5HL RSCAN0.CFPTR5.UINT8[HL] +#define RSCAN0CFPTR5HH RSCAN0.CFPTR5.UINT8[HH] +#define RSCAN0CFDF05 RSCAN0.CFDF05.UINT32 +#define RSCAN0CFDF05L RSCAN0.CFDF05.UINT16[L] +#define RSCAN0CFDF05LL RSCAN0.CFDF05.UINT8[LL] +#define RSCAN0CFDF05LH RSCAN0.CFDF05.UINT8[LH] +#define RSCAN0CFDF05H RSCAN0.CFDF05.UINT16[H] +#define RSCAN0CFDF05HL RSCAN0.CFDF05.UINT8[HL] +#define RSCAN0CFDF05HH RSCAN0.CFDF05.UINT8[HH] +#define RSCAN0CFDF15 RSCAN0.CFDF15.UINT32 +#define RSCAN0CFDF15L RSCAN0.CFDF15.UINT16[L] +#define RSCAN0CFDF15LL RSCAN0.CFDF15.UINT8[LL] +#define RSCAN0CFDF15LH RSCAN0.CFDF15.UINT8[LH] +#define RSCAN0CFDF15H RSCAN0.CFDF15.UINT16[H] +#define RSCAN0CFDF15HL RSCAN0.CFDF15.UINT8[HL] +#define RSCAN0CFDF15HH RSCAN0.CFDF15.UINT8[HH] +#define RSCAN0CFID6 RSCAN0.CFID6.UINT32 +#define RSCAN0CFID6L RSCAN0.CFID6.UINT16[L] +#define RSCAN0CFID6LL RSCAN0.CFID6.UINT8[LL] +#define RSCAN0CFID6LH RSCAN0.CFID6.UINT8[LH] +#define RSCAN0CFID6H RSCAN0.CFID6.UINT16[H] +#define RSCAN0CFID6HL RSCAN0.CFID6.UINT8[HL] +#define RSCAN0CFID6HH RSCAN0.CFID6.UINT8[HH] +#define RSCAN0CFPTR6 RSCAN0.CFPTR6.UINT32 +#define RSCAN0CFPTR6L RSCAN0.CFPTR6.UINT16[L] +#define RSCAN0CFPTR6LL RSCAN0.CFPTR6.UINT8[LL] +#define RSCAN0CFPTR6LH RSCAN0.CFPTR6.UINT8[LH] +#define RSCAN0CFPTR6H RSCAN0.CFPTR6.UINT16[H] +#define RSCAN0CFPTR6HL RSCAN0.CFPTR6.UINT8[HL] +#define RSCAN0CFPTR6HH RSCAN0.CFPTR6.UINT8[HH] +#define RSCAN0CFDF06 RSCAN0.CFDF06.UINT32 +#define RSCAN0CFDF06L RSCAN0.CFDF06.UINT16[L] +#define RSCAN0CFDF06LL RSCAN0.CFDF06.UINT8[LL] +#define RSCAN0CFDF06LH RSCAN0.CFDF06.UINT8[LH] +#define RSCAN0CFDF06H RSCAN0.CFDF06.UINT16[H] +#define RSCAN0CFDF06HL RSCAN0.CFDF06.UINT8[HL] +#define RSCAN0CFDF06HH RSCAN0.CFDF06.UINT8[HH] +#define RSCAN0CFDF16 RSCAN0.CFDF16.UINT32 +#define RSCAN0CFDF16L RSCAN0.CFDF16.UINT16[L] +#define RSCAN0CFDF16LL RSCAN0.CFDF16.UINT8[LL] +#define RSCAN0CFDF16LH RSCAN0.CFDF16.UINT8[LH] +#define RSCAN0CFDF16H RSCAN0.CFDF16.UINT16[H] +#define RSCAN0CFDF16HL RSCAN0.CFDF16.UINT8[HL] +#define RSCAN0CFDF16HH RSCAN0.CFDF16.UINT8[HH] +#define RSCAN0CFID7 RSCAN0.CFID7.UINT32 +#define RSCAN0CFID7L RSCAN0.CFID7.UINT16[L] +#define RSCAN0CFID7LL RSCAN0.CFID7.UINT8[LL] +#define RSCAN0CFID7LH RSCAN0.CFID7.UINT8[LH] +#define RSCAN0CFID7H RSCAN0.CFID7.UINT16[H] +#define RSCAN0CFID7HL RSCAN0.CFID7.UINT8[HL] +#define RSCAN0CFID7HH RSCAN0.CFID7.UINT8[HH] +#define RSCAN0CFPTR7 RSCAN0.CFPTR7.UINT32 +#define RSCAN0CFPTR7L RSCAN0.CFPTR7.UINT16[L] +#define RSCAN0CFPTR7LL RSCAN0.CFPTR7.UINT8[LL] +#define RSCAN0CFPTR7LH RSCAN0.CFPTR7.UINT8[LH] +#define RSCAN0CFPTR7H RSCAN0.CFPTR7.UINT16[H] +#define RSCAN0CFPTR7HL RSCAN0.CFPTR7.UINT8[HL] +#define RSCAN0CFPTR7HH RSCAN0.CFPTR7.UINT8[HH] +#define RSCAN0CFDF07 RSCAN0.CFDF07.UINT32 +#define RSCAN0CFDF07L RSCAN0.CFDF07.UINT16[L] +#define RSCAN0CFDF07LL RSCAN0.CFDF07.UINT8[LL] +#define RSCAN0CFDF07LH RSCAN0.CFDF07.UINT8[LH] +#define RSCAN0CFDF07H RSCAN0.CFDF07.UINT16[H] +#define RSCAN0CFDF07HL RSCAN0.CFDF07.UINT8[HL] +#define RSCAN0CFDF07HH RSCAN0.CFDF07.UINT8[HH] +#define RSCAN0CFDF17 RSCAN0.CFDF17.UINT32 +#define RSCAN0CFDF17L RSCAN0.CFDF17.UINT16[L] +#define RSCAN0CFDF17LL RSCAN0.CFDF17.UINT8[LL] +#define RSCAN0CFDF17LH RSCAN0.CFDF17.UINT8[LH] +#define RSCAN0CFDF17H RSCAN0.CFDF17.UINT16[H] +#define RSCAN0CFDF17HL RSCAN0.CFDF17.UINT8[HL] +#define RSCAN0CFDF17HH RSCAN0.CFDF17.UINT8[HH] +#define RSCAN0CFID8 RSCAN0.CFID8.UINT32 +#define RSCAN0CFID8L RSCAN0.CFID8.UINT16[L] +#define RSCAN0CFID8LL RSCAN0.CFID8.UINT8[LL] +#define RSCAN0CFID8LH RSCAN0.CFID8.UINT8[LH] +#define RSCAN0CFID8H RSCAN0.CFID8.UINT16[H] +#define RSCAN0CFID8HL RSCAN0.CFID8.UINT8[HL] +#define RSCAN0CFID8HH RSCAN0.CFID8.UINT8[HH] +#define RSCAN0CFPTR8 RSCAN0.CFPTR8.UINT32 +#define RSCAN0CFPTR8L RSCAN0.CFPTR8.UINT16[L] +#define RSCAN0CFPTR8LL RSCAN0.CFPTR8.UINT8[LL] +#define RSCAN0CFPTR8LH RSCAN0.CFPTR8.UINT8[LH] +#define RSCAN0CFPTR8H RSCAN0.CFPTR8.UINT16[H] +#define RSCAN0CFPTR8HL RSCAN0.CFPTR8.UINT8[HL] +#define RSCAN0CFPTR8HH RSCAN0.CFPTR8.UINT8[HH] +#define RSCAN0CFDF08 RSCAN0.CFDF08.UINT32 +#define RSCAN0CFDF08L RSCAN0.CFDF08.UINT16[L] +#define RSCAN0CFDF08LL RSCAN0.CFDF08.UINT8[LL] +#define RSCAN0CFDF08LH RSCAN0.CFDF08.UINT8[LH] +#define RSCAN0CFDF08H RSCAN0.CFDF08.UINT16[H] +#define RSCAN0CFDF08HL RSCAN0.CFDF08.UINT8[HL] +#define RSCAN0CFDF08HH RSCAN0.CFDF08.UINT8[HH] +#define RSCAN0CFDF18 RSCAN0.CFDF18.UINT32 +#define RSCAN0CFDF18L RSCAN0.CFDF18.UINT16[L] +#define RSCAN0CFDF18LL RSCAN0.CFDF18.UINT8[LL] +#define RSCAN0CFDF18LH RSCAN0.CFDF18.UINT8[LH] +#define RSCAN0CFDF18H RSCAN0.CFDF18.UINT16[H] +#define RSCAN0CFDF18HL RSCAN0.CFDF18.UINT8[HL] +#define RSCAN0CFDF18HH RSCAN0.CFDF18.UINT8[HH] +#define RSCAN0CFID9 RSCAN0.CFID9.UINT32 +#define RSCAN0CFID9L RSCAN0.CFID9.UINT16[L] +#define RSCAN0CFID9LL RSCAN0.CFID9.UINT8[LL] +#define RSCAN0CFID9LH RSCAN0.CFID9.UINT8[LH] +#define RSCAN0CFID9H RSCAN0.CFID9.UINT16[H] +#define RSCAN0CFID9HL RSCAN0.CFID9.UINT8[HL] +#define RSCAN0CFID9HH RSCAN0.CFID9.UINT8[HH] +#define RSCAN0CFPTR9 RSCAN0.CFPTR9.UINT32 +#define RSCAN0CFPTR9L RSCAN0.CFPTR9.UINT16[L] +#define RSCAN0CFPTR9LL RSCAN0.CFPTR9.UINT8[LL] +#define RSCAN0CFPTR9LH RSCAN0.CFPTR9.UINT8[LH] +#define RSCAN0CFPTR9H RSCAN0.CFPTR9.UINT16[H] +#define RSCAN0CFPTR9HL RSCAN0.CFPTR9.UINT8[HL] +#define RSCAN0CFPTR9HH RSCAN0.CFPTR9.UINT8[HH] +#define RSCAN0CFDF09 RSCAN0.CFDF09.UINT32 +#define RSCAN0CFDF09L RSCAN0.CFDF09.UINT16[L] +#define RSCAN0CFDF09LL RSCAN0.CFDF09.UINT8[LL] +#define RSCAN0CFDF09LH RSCAN0.CFDF09.UINT8[LH] +#define RSCAN0CFDF09H RSCAN0.CFDF09.UINT16[H] +#define RSCAN0CFDF09HL RSCAN0.CFDF09.UINT8[HL] +#define RSCAN0CFDF09HH RSCAN0.CFDF09.UINT8[HH] +#define RSCAN0CFDF19 RSCAN0.CFDF19.UINT32 +#define RSCAN0CFDF19L RSCAN0.CFDF19.UINT16[L] +#define RSCAN0CFDF19LL RSCAN0.CFDF19.UINT8[LL] +#define RSCAN0CFDF19LH RSCAN0.CFDF19.UINT8[LH] +#define RSCAN0CFDF19H RSCAN0.CFDF19.UINT16[H] +#define RSCAN0CFDF19HL RSCAN0.CFDF19.UINT8[HL] +#define RSCAN0CFDF19HH RSCAN0.CFDF19.UINT8[HH] +#define RSCAN0CFID10 RSCAN0.CFID10.UINT32 +#define RSCAN0CFID10L RSCAN0.CFID10.UINT16[L] +#define RSCAN0CFID10LL RSCAN0.CFID10.UINT8[LL] +#define RSCAN0CFID10LH RSCAN0.CFID10.UINT8[LH] +#define RSCAN0CFID10H RSCAN0.CFID10.UINT16[H] +#define RSCAN0CFID10HL RSCAN0.CFID10.UINT8[HL] +#define RSCAN0CFID10HH RSCAN0.CFID10.UINT8[HH] +#define RSCAN0CFPTR10 RSCAN0.CFPTR10.UINT32 +#define RSCAN0CFPTR10L RSCAN0.CFPTR10.UINT16[L] +#define RSCAN0CFPTR10LL RSCAN0.CFPTR10.UINT8[LL] +#define RSCAN0CFPTR10LH RSCAN0.CFPTR10.UINT8[LH] +#define RSCAN0CFPTR10H RSCAN0.CFPTR10.UINT16[H] +#define RSCAN0CFPTR10HL RSCAN0.CFPTR10.UINT8[HL] +#define RSCAN0CFPTR10HH RSCAN0.CFPTR10.UINT8[HH] +#define RSCAN0CFDF010 RSCAN0.CFDF010.UINT32 +#define RSCAN0CFDF010L RSCAN0.CFDF010.UINT16[L] +#define RSCAN0CFDF010LL RSCAN0.CFDF010.UINT8[LL] +#define RSCAN0CFDF010LH RSCAN0.CFDF010.UINT8[LH] +#define RSCAN0CFDF010H RSCAN0.CFDF010.UINT16[H] +#define RSCAN0CFDF010HL RSCAN0.CFDF010.UINT8[HL] +#define RSCAN0CFDF010HH RSCAN0.CFDF010.UINT8[HH] +#define RSCAN0CFDF110 RSCAN0.CFDF110.UINT32 +#define RSCAN0CFDF110L RSCAN0.CFDF110.UINT16[L] +#define RSCAN0CFDF110LL RSCAN0.CFDF110.UINT8[LL] +#define RSCAN0CFDF110LH RSCAN0.CFDF110.UINT8[LH] +#define RSCAN0CFDF110H RSCAN0.CFDF110.UINT16[H] +#define RSCAN0CFDF110HL RSCAN0.CFDF110.UINT8[HL] +#define RSCAN0CFDF110HH RSCAN0.CFDF110.UINT8[HH] +#define RSCAN0CFID11 RSCAN0.CFID11.UINT32 +#define RSCAN0CFID11L RSCAN0.CFID11.UINT16[L] +#define RSCAN0CFID11LL RSCAN0.CFID11.UINT8[LL] +#define RSCAN0CFID11LH RSCAN0.CFID11.UINT8[LH] +#define RSCAN0CFID11H RSCAN0.CFID11.UINT16[H] +#define RSCAN0CFID11HL RSCAN0.CFID11.UINT8[HL] +#define RSCAN0CFID11HH RSCAN0.CFID11.UINT8[HH] +#define RSCAN0CFPTR11 RSCAN0.CFPTR11.UINT32 +#define RSCAN0CFPTR11L RSCAN0.CFPTR11.UINT16[L] +#define RSCAN0CFPTR11LL RSCAN0.CFPTR11.UINT8[LL] +#define RSCAN0CFPTR11LH RSCAN0.CFPTR11.UINT8[LH] +#define RSCAN0CFPTR11H RSCAN0.CFPTR11.UINT16[H] +#define RSCAN0CFPTR11HL RSCAN0.CFPTR11.UINT8[HL] +#define RSCAN0CFPTR11HH RSCAN0.CFPTR11.UINT8[HH] +#define RSCAN0CFDF011 RSCAN0.CFDF011.UINT32 +#define RSCAN0CFDF011L RSCAN0.CFDF011.UINT16[L] +#define RSCAN0CFDF011LL RSCAN0.CFDF011.UINT8[LL] +#define RSCAN0CFDF011LH RSCAN0.CFDF011.UINT8[LH] +#define RSCAN0CFDF011H RSCAN0.CFDF011.UINT16[H] +#define RSCAN0CFDF011HL RSCAN0.CFDF011.UINT8[HL] +#define RSCAN0CFDF011HH RSCAN0.CFDF011.UINT8[HH] +#define RSCAN0CFDF111 RSCAN0.CFDF111.UINT32 +#define RSCAN0CFDF111L RSCAN0.CFDF111.UINT16[L] +#define RSCAN0CFDF111LL RSCAN0.CFDF111.UINT8[LL] +#define RSCAN0CFDF111LH RSCAN0.CFDF111.UINT8[LH] +#define RSCAN0CFDF111H RSCAN0.CFDF111.UINT16[H] +#define RSCAN0CFDF111HL RSCAN0.CFDF111.UINT8[HL] +#define RSCAN0CFDF111HH RSCAN0.CFDF111.UINT8[HH] +#define RSCAN0CFID12 RSCAN0.CFID12.UINT32 +#define RSCAN0CFID12L RSCAN0.CFID12.UINT16[L] +#define RSCAN0CFID12LL RSCAN0.CFID12.UINT8[LL] +#define RSCAN0CFID12LH RSCAN0.CFID12.UINT8[LH] +#define RSCAN0CFID12H RSCAN0.CFID12.UINT16[H] +#define RSCAN0CFID12HL RSCAN0.CFID12.UINT8[HL] +#define RSCAN0CFID12HH RSCAN0.CFID12.UINT8[HH] +#define RSCAN0CFPTR12 RSCAN0.CFPTR12.UINT32 +#define RSCAN0CFPTR12L RSCAN0.CFPTR12.UINT16[L] +#define RSCAN0CFPTR12LL RSCAN0.CFPTR12.UINT8[LL] +#define RSCAN0CFPTR12LH RSCAN0.CFPTR12.UINT8[LH] +#define RSCAN0CFPTR12H RSCAN0.CFPTR12.UINT16[H] +#define RSCAN0CFPTR12HL RSCAN0.CFPTR12.UINT8[HL] +#define RSCAN0CFPTR12HH RSCAN0.CFPTR12.UINT8[HH] +#define RSCAN0CFDF012 RSCAN0.CFDF012.UINT32 +#define RSCAN0CFDF012L RSCAN0.CFDF012.UINT16[L] +#define RSCAN0CFDF012LL RSCAN0.CFDF012.UINT8[LL] +#define RSCAN0CFDF012LH RSCAN0.CFDF012.UINT8[LH] +#define RSCAN0CFDF012H RSCAN0.CFDF012.UINT16[H] +#define RSCAN0CFDF012HL RSCAN0.CFDF012.UINT8[HL] +#define RSCAN0CFDF012HH RSCAN0.CFDF012.UINT8[HH] +#define RSCAN0CFDF112 RSCAN0.CFDF112.UINT32 +#define RSCAN0CFDF112L RSCAN0.CFDF112.UINT16[L] +#define RSCAN0CFDF112LL RSCAN0.CFDF112.UINT8[LL] +#define RSCAN0CFDF112LH RSCAN0.CFDF112.UINT8[LH] +#define RSCAN0CFDF112H RSCAN0.CFDF112.UINT16[H] +#define RSCAN0CFDF112HL RSCAN0.CFDF112.UINT8[HL] +#define RSCAN0CFDF112HH RSCAN0.CFDF112.UINT8[HH] +#define RSCAN0CFID13 RSCAN0.CFID13.UINT32 +#define RSCAN0CFID13L RSCAN0.CFID13.UINT16[L] +#define RSCAN0CFID13LL RSCAN0.CFID13.UINT8[LL] +#define RSCAN0CFID13LH RSCAN0.CFID13.UINT8[LH] +#define RSCAN0CFID13H RSCAN0.CFID13.UINT16[H] +#define RSCAN0CFID13HL RSCAN0.CFID13.UINT8[HL] +#define RSCAN0CFID13HH RSCAN0.CFID13.UINT8[HH] +#define RSCAN0CFPTR13 RSCAN0.CFPTR13.UINT32 +#define RSCAN0CFPTR13L RSCAN0.CFPTR13.UINT16[L] +#define RSCAN0CFPTR13LL RSCAN0.CFPTR13.UINT8[LL] +#define RSCAN0CFPTR13LH RSCAN0.CFPTR13.UINT8[LH] +#define RSCAN0CFPTR13H RSCAN0.CFPTR13.UINT16[H] +#define RSCAN0CFPTR13HL RSCAN0.CFPTR13.UINT8[HL] +#define RSCAN0CFPTR13HH RSCAN0.CFPTR13.UINT8[HH] +#define RSCAN0CFDF013 RSCAN0.CFDF013.UINT32 +#define RSCAN0CFDF013L RSCAN0.CFDF013.UINT16[L] +#define RSCAN0CFDF013LL RSCAN0.CFDF013.UINT8[LL] +#define RSCAN0CFDF013LH RSCAN0.CFDF013.UINT8[LH] +#define RSCAN0CFDF013H RSCAN0.CFDF013.UINT16[H] +#define RSCAN0CFDF013HL RSCAN0.CFDF013.UINT8[HL] +#define RSCAN0CFDF013HH RSCAN0.CFDF013.UINT8[HH] +#define RSCAN0CFDF113 RSCAN0.CFDF113.UINT32 +#define RSCAN0CFDF113L RSCAN0.CFDF113.UINT16[L] +#define RSCAN0CFDF113LL RSCAN0.CFDF113.UINT8[LL] +#define RSCAN0CFDF113LH RSCAN0.CFDF113.UINT8[LH] +#define RSCAN0CFDF113H RSCAN0.CFDF113.UINT16[H] +#define RSCAN0CFDF113HL RSCAN0.CFDF113.UINT8[HL] +#define RSCAN0CFDF113HH RSCAN0.CFDF113.UINT8[HH] +#define RSCAN0CFID14 RSCAN0.CFID14.UINT32 +#define RSCAN0CFID14L RSCAN0.CFID14.UINT16[L] +#define RSCAN0CFID14LL RSCAN0.CFID14.UINT8[LL] +#define RSCAN0CFID14LH RSCAN0.CFID14.UINT8[LH] +#define RSCAN0CFID14H RSCAN0.CFID14.UINT16[H] +#define RSCAN0CFID14HL RSCAN0.CFID14.UINT8[HL] +#define RSCAN0CFID14HH RSCAN0.CFID14.UINT8[HH] +#define RSCAN0CFPTR14 RSCAN0.CFPTR14.UINT32 +#define RSCAN0CFPTR14L RSCAN0.CFPTR14.UINT16[L] +#define RSCAN0CFPTR14LL RSCAN0.CFPTR14.UINT8[LL] +#define RSCAN0CFPTR14LH RSCAN0.CFPTR14.UINT8[LH] +#define RSCAN0CFPTR14H RSCAN0.CFPTR14.UINT16[H] +#define RSCAN0CFPTR14HL RSCAN0.CFPTR14.UINT8[HL] +#define RSCAN0CFPTR14HH RSCAN0.CFPTR14.UINT8[HH] +#define RSCAN0CFDF014 RSCAN0.CFDF014.UINT32 +#define RSCAN0CFDF014L RSCAN0.CFDF014.UINT16[L] +#define RSCAN0CFDF014LL RSCAN0.CFDF014.UINT8[LL] +#define RSCAN0CFDF014LH RSCAN0.CFDF014.UINT8[LH] +#define RSCAN0CFDF014H RSCAN0.CFDF014.UINT16[H] +#define RSCAN0CFDF014HL RSCAN0.CFDF014.UINT8[HL] +#define RSCAN0CFDF014HH RSCAN0.CFDF014.UINT8[HH] +#define RSCAN0CFDF114 RSCAN0.CFDF114.UINT32 +#define RSCAN0CFDF114L RSCAN0.CFDF114.UINT16[L] +#define RSCAN0CFDF114LL RSCAN0.CFDF114.UINT8[LL] +#define RSCAN0CFDF114LH RSCAN0.CFDF114.UINT8[LH] +#define RSCAN0CFDF114H RSCAN0.CFDF114.UINT16[H] +#define RSCAN0CFDF114HL RSCAN0.CFDF114.UINT8[HL] +#define RSCAN0CFDF114HH RSCAN0.CFDF114.UINT8[HH] +#define RSCAN0TMID0 RSCAN0.TMID0.UINT32 +#define RSCAN0TMID0L RSCAN0.TMID0.UINT16[L] +#define RSCAN0TMID0LL RSCAN0.TMID0.UINT8[LL] +#define RSCAN0TMID0LH RSCAN0.TMID0.UINT8[LH] +#define RSCAN0TMID0H RSCAN0.TMID0.UINT16[H] +#define RSCAN0TMID0HL RSCAN0.TMID0.UINT8[HL] +#define RSCAN0TMID0HH RSCAN0.TMID0.UINT8[HH] +#define RSCAN0TMPTR0 RSCAN0.TMPTR0.UINT32 +#define RSCAN0TMPTR0L RSCAN0.TMPTR0.UINT16[L] +#define RSCAN0TMPTR0LL RSCAN0.TMPTR0.UINT8[LL] +#define RSCAN0TMPTR0LH RSCAN0.TMPTR0.UINT8[LH] +#define RSCAN0TMPTR0H RSCAN0.TMPTR0.UINT16[H] +#define RSCAN0TMPTR0HL RSCAN0.TMPTR0.UINT8[HL] +#define RSCAN0TMPTR0HH RSCAN0.TMPTR0.UINT8[HH] +#define RSCAN0TMDF00 RSCAN0.TMDF00.UINT32 +#define RSCAN0TMDF00L RSCAN0.TMDF00.UINT16[L] +#define RSCAN0TMDF00LL RSCAN0.TMDF00.UINT8[LL] +#define RSCAN0TMDF00LH RSCAN0.TMDF00.UINT8[LH] +#define RSCAN0TMDF00H RSCAN0.TMDF00.UINT16[H] +#define RSCAN0TMDF00HL RSCAN0.TMDF00.UINT8[HL] +#define RSCAN0TMDF00HH RSCAN0.TMDF00.UINT8[HH] +#define RSCAN0TMDF10 RSCAN0.TMDF10.UINT32 +#define RSCAN0TMDF10L RSCAN0.TMDF10.UINT16[L] +#define RSCAN0TMDF10LL RSCAN0.TMDF10.UINT8[LL] +#define RSCAN0TMDF10LH RSCAN0.TMDF10.UINT8[LH] +#define RSCAN0TMDF10H RSCAN0.TMDF10.UINT16[H] +#define RSCAN0TMDF10HL RSCAN0.TMDF10.UINT8[HL] +#define RSCAN0TMDF10HH RSCAN0.TMDF10.UINT8[HH] +#define RSCAN0TMID1 RSCAN0.TMID1.UINT32 +#define RSCAN0TMID1L RSCAN0.TMID1.UINT16[L] +#define RSCAN0TMID1LL RSCAN0.TMID1.UINT8[LL] +#define RSCAN0TMID1LH RSCAN0.TMID1.UINT8[LH] +#define RSCAN0TMID1H RSCAN0.TMID1.UINT16[H] +#define RSCAN0TMID1HL RSCAN0.TMID1.UINT8[HL] +#define RSCAN0TMID1HH RSCAN0.TMID1.UINT8[HH] +#define RSCAN0TMPTR1 RSCAN0.TMPTR1.UINT32 +#define RSCAN0TMPTR1L RSCAN0.TMPTR1.UINT16[L] +#define RSCAN0TMPTR1LL RSCAN0.TMPTR1.UINT8[LL] +#define RSCAN0TMPTR1LH RSCAN0.TMPTR1.UINT8[LH] +#define RSCAN0TMPTR1H RSCAN0.TMPTR1.UINT16[H] +#define RSCAN0TMPTR1HL RSCAN0.TMPTR1.UINT8[HL] +#define RSCAN0TMPTR1HH RSCAN0.TMPTR1.UINT8[HH] +#define RSCAN0TMDF01 RSCAN0.TMDF01.UINT32 +#define RSCAN0TMDF01L RSCAN0.TMDF01.UINT16[L] +#define RSCAN0TMDF01LL RSCAN0.TMDF01.UINT8[LL] +#define RSCAN0TMDF01LH RSCAN0.TMDF01.UINT8[LH] +#define RSCAN0TMDF01H RSCAN0.TMDF01.UINT16[H] +#define RSCAN0TMDF01HL RSCAN0.TMDF01.UINT8[HL] +#define RSCAN0TMDF01HH RSCAN0.TMDF01.UINT8[HH] +#define RSCAN0TMDF11 RSCAN0.TMDF11.UINT32 +#define RSCAN0TMDF11L RSCAN0.TMDF11.UINT16[L] +#define RSCAN0TMDF11LL RSCAN0.TMDF11.UINT8[LL] +#define RSCAN0TMDF11LH RSCAN0.TMDF11.UINT8[LH] +#define RSCAN0TMDF11H RSCAN0.TMDF11.UINT16[H] +#define RSCAN0TMDF11HL RSCAN0.TMDF11.UINT8[HL] +#define RSCAN0TMDF11HH RSCAN0.TMDF11.UINT8[HH] +#define RSCAN0TMID2 RSCAN0.TMID2.UINT32 +#define RSCAN0TMID2L RSCAN0.TMID2.UINT16[L] +#define RSCAN0TMID2LL RSCAN0.TMID2.UINT8[LL] +#define RSCAN0TMID2LH RSCAN0.TMID2.UINT8[LH] +#define RSCAN0TMID2H RSCAN0.TMID2.UINT16[H] +#define RSCAN0TMID2HL RSCAN0.TMID2.UINT8[HL] +#define RSCAN0TMID2HH RSCAN0.TMID2.UINT8[HH] +#define RSCAN0TMPTR2 RSCAN0.TMPTR2.UINT32 +#define RSCAN0TMPTR2L RSCAN0.TMPTR2.UINT16[L] +#define RSCAN0TMPTR2LL RSCAN0.TMPTR2.UINT8[LL] +#define RSCAN0TMPTR2LH RSCAN0.TMPTR2.UINT8[LH] +#define RSCAN0TMPTR2H RSCAN0.TMPTR2.UINT16[H] +#define RSCAN0TMPTR2HL RSCAN0.TMPTR2.UINT8[HL] +#define RSCAN0TMPTR2HH RSCAN0.TMPTR2.UINT8[HH] +#define RSCAN0TMDF02 RSCAN0.TMDF02.UINT32 +#define RSCAN0TMDF02L RSCAN0.TMDF02.UINT16[L] +#define RSCAN0TMDF02LL RSCAN0.TMDF02.UINT8[LL] +#define RSCAN0TMDF02LH RSCAN0.TMDF02.UINT8[LH] +#define RSCAN0TMDF02H RSCAN0.TMDF02.UINT16[H] +#define RSCAN0TMDF02HL RSCAN0.TMDF02.UINT8[HL] +#define RSCAN0TMDF02HH RSCAN0.TMDF02.UINT8[HH] +#define RSCAN0TMDF12 RSCAN0.TMDF12.UINT32 +#define RSCAN0TMDF12L RSCAN0.TMDF12.UINT16[L] +#define RSCAN0TMDF12LL RSCAN0.TMDF12.UINT8[LL] +#define RSCAN0TMDF12LH RSCAN0.TMDF12.UINT8[LH] +#define RSCAN0TMDF12H RSCAN0.TMDF12.UINT16[H] +#define RSCAN0TMDF12HL RSCAN0.TMDF12.UINT8[HL] +#define RSCAN0TMDF12HH RSCAN0.TMDF12.UINT8[HH] +#define RSCAN0TMID3 RSCAN0.TMID3.UINT32 +#define RSCAN0TMID3L RSCAN0.TMID3.UINT16[L] +#define RSCAN0TMID3LL RSCAN0.TMID3.UINT8[LL] +#define RSCAN0TMID3LH RSCAN0.TMID3.UINT8[LH] +#define RSCAN0TMID3H RSCAN0.TMID3.UINT16[H] +#define RSCAN0TMID3HL RSCAN0.TMID3.UINT8[HL] +#define RSCAN0TMID3HH RSCAN0.TMID3.UINT8[HH] +#define RSCAN0TMPTR3 RSCAN0.TMPTR3.UINT32 +#define RSCAN0TMPTR3L RSCAN0.TMPTR3.UINT16[L] +#define RSCAN0TMPTR3LL RSCAN0.TMPTR3.UINT8[LL] +#define RSCAN0TMPTR3LH RSCAN0.TMPTR3.UINT8[LH] +#define RSCAN0TMPTR3H RSCAN0.TMPTR3.UINT16[H] +#define RSCAN0TMPTR3HL RSCAN0.TMPTR3.UINT8[HL] +#define RSCAN0TMPTR3HH RSCAN0.TMPTR3.UINT8[HH] +#define RSCAN0TMDF03 RSCAN0.TMDF03.UINT32 +#define RSCAN0TMDF03L RSCAN0.TMDF03.UINT16[L] +#define RSCAN0TMDF03LL RSCAN0.TMDF03.UINT8[LL] +#define RSCAN0TMDF03LH RSCAN0.TMDF03.UINT8[LH] +#define RSCAN0TMDF03H RSCAN0.TMDF03.UINT16[H] +#define RSCAN0TMDF03HL RSCAN0.TMDF03.UINT8[HL] +#define RSCAN0TMDF03HH RSCAN0.TMDF03.UINT8[HH] +#define RSCAN0TMDF13 RSCAN0.TMDF13.UINT32 +#define RSCAN0TMDF13L RSCAN0.TMDF13.UINT16[L] +#define RSCAN0TMDF13LL RSCAN0.TMDF13.UINT8[LL] +#define RSCAN0TMDF13LH RSCAN0.TMDF13.UINT8[LH] +#define RSCAN0TMDF13H RSCAN0.TMDF13.UINT16[H] +#define RSCAN0TMDF13HL RSCAN0.TMDF13.UINT8[HL] +#define RSCAN0TMDF13HH RSCAN0.TMDF13.UINT8[HH] +#define RSCAN0TMID4 RSCAN0.TMID4.UINT32 +#define RSCAN0TMID4L RSCAN0.TMID4.UINT16[L] +#define RSCAN0TMID4LL RSCAN0.TMID4.UINT8[LL] +#define RSCAN0TMID4LH RSCAN0.TMID4.UINT8[LH] +#define RSCAN0TMID4H RSCAN0.TMID4.UINT16[H] +#define RSCAN0TMID4HL RSCAN0.TMID4.UINT8[HL] +#define RSCAN0TMID4HH RSCAN0.TMID4.UINT8[HH] +#define RSCAN0TMPTR4 RSCAN0.TMPTR4.UINT32 +#define RSCAN0TMPTR4L RSCAN0.TMPTR4.UINT16[L] +#define RSCAN0TMPTR4LL RSCAN0.TMPTR4.UINT8[LL] +#define RSCAN0TMPTR4LH RSCAN0.TMPTR4.UINT8[LH] +#define RSCAN0TMPTR4H RSCAN0.TMPTR4.UINT16[H] +#define RSCAN0TMPTR4HL RSCAN0.TMPTR4.UINT8[HL] +#define RSCAN0TMPTR4HH RSCAN0.TMPTR4.UINT8[HH] +#define RSCAN0TMDF04 RSCAN0.TMDF04.UINT32 +#define RSCAN0TMDF04L RSCAN0.TMDF04.UINT16[L] +#define RSCAN0TMDF04LL RSCAN0.TMDF04.UINT8[LL] +#define RSCAN0TMDF04LH RSCAN0.TMDF04.UINT8[LH] +#define RSCAN0TMDF04H RSCAN0.TMDF04.UINT16[H] +#define RSCAN0TMDF04HL RSCAN0.TMDF04.UINT8[HL] +#define RSCAN0TMDF04HH RSCAN0.TMDF04.UINT8[HH] +#define RSCAN0TMDF14 RSCAN0.TMDF14.UINT32 +#define RSCAN0TMDF14L RSCAN0.TMDF14.UINT16[L] +#define RSCAN0TMDF14LL RSCAN0.TMDF14.UINT8[LL] +#define RSCAN0TMDF14LH RSCAN0.TMDF14.UINT8[LH] +#define RSCAN0TMDF14H RSCAN0.TMDF14.UINT16[H] +#define RSCAN0TMDF14HL RSCAN0.TMDF14.UINT8[HL] +#define RSCAN0TMDF14HH RSCAN0.TMDF14.UINT8[HH] +#define RSCAN0TMID5 RSCAN0.TMID5.UINT32 +#define RSCAN0TMID5L RSCAN0.TMID5.UINT16[L] +#define RSCAN0TMID5LL RSCAN0.TMID5.UINT8[LL] +#define RSCAN0TMID5LH RSCAN0.TMID5.UINT8[LH] +#define RSCAN0TMID5H RSCAN0.TMID5.UINT16[H] +#define RSCAN0TMID5HL RSCAN0.TMID5.UINT8[HL] +#define RSCAN0TMID5HH RSCAN0.TMID5.UINT8[HH] +#define RSCAN0TMPTR5 RSCAN0.TMPTR5.UINT32 +#define RSCAN0TMPTR5L RSCAN0.TMPTR5.UINT16[L] +#define RSCAN0TMPTR5LL RSCAN0.TMPTR5.UINT8[LL] +#define RSCAN0TMPTR5LH RSCAN0.TMPTR5.UINT8[LH] +#define RSCAN0TMPTR5H RSCAN0.TMPTR5.UINT16[H] +#define RSCAN0TMPTR5HL RSCAN0.TMPTR5.UINT8[HL] +#define RSCAN0TMPTR5HH RSCAN0.TMPTR5.UINT8[HH] +#define RSCAN0TMDF05 RSCAN0.TMDF05.UINT32 +#define RSCAN0TMDF05L RSCAN0.TMDF05.UINT16[L] +#define RSCAN0TMDF05LL RSCAN0.TMDF05.UINT8[LL] +#define RSCAN0TMDF05LH RSCAN0.TMDF05.UINT8[LH] +#define RSCAN0TMDF05H RSCAN0.TMDF05.UINT16[H] +#define RSCAN0TMDF05HL RSCAN0.TMDF05.UINT8[HL] +#define RSCAN0TMDF05HH RSCAN0.TMDF05.UINT8[HH] +#define RSCAN0TMDF15 RSCAN0.TMDF15.UINT32 +#define RSCAN0TMDF15L RSCAN0.TMDF15.UINT16[L] +#define RSCAN0TMDF15LL RSCAN0.TMDF15.UINT8[LL] +#define RSCAN0TMDF15LH RSCAN0.TMDF15.UINT8[LH] +#define RSCAN0TMDF15H RSCAN0.TMDF15.UINT16[H] +#define RSCAN0TMDF15HL RSCAN0.TMDF15.UINT8[HL] +#define RSCAN0TMDF15HH RSCAN0.TMDF15.UINT8[HH] +#define RSCAN0TMID6 RSCAN0.TMID6.UINT32 +#define RSCAN0TMID6L RSCAN0.TMID6.UINT16[L] +#define RSCAN0TMID6LL RSCAN0.TMID6.UINT8[LL] +#define RSCAN0TMID6LH RSCAN0.TMID6.UINT8[LH] +#define RSCAN0TMID6H RSCAN0.TMID6.UINT16[H] +#define RSCAN0TMID6HL RSCAN0.TMID6.UINT8[HL] +#define RSCAN0TMID6HH RSCAN0.TMID6.UINT8[HH] +#define RSCAN0TMPTR6 RSCAN0.TMPTR6.UINT32 +#define RSCAN0TMPTR6L RSCAN0.TMPTR6.UINT16[L] +#define RSCAN0TMPTR6LL RSCAN0.TMPTR6.UINT8[LL] +#define RSCAN0TMPTR6LH RSCAN0.TMPTR6.UINT8[LH] +#define RSCAN0TMPTR6H RSCAN0.TMPTR6.UINT16[H] +#define RSCAN0TMPTR6HL RSCAN0.TMPTR6.UINT8[HL] +#define RSCAN0TMPTR6HH RSCAN0.TMPTR6.UINT8[HH] +#define RSCAN0TMDF06 RSCAN0.TMDF06.UINT32 +#define RSCAN0TMDF06L RSCAN0.TMDF06.UINT16[L] +#define RSCAN0TMDF06LL RSCAN0.TMDF06.UINT8[LL] +#define RSCAN0TMDF06LH RSCAN0.TMDF06.UINT8[LH] +#define RSCAN0TMDF06H RSCAN0.TMDF06.UINT16[H] +#define RSCAN0TMDF06HL RSCAN0.TMDF06.UINT8[HL] +#define RSCAN0TMDF06HH RSCAN0.TMDF06.UINT8[HH] +#define RSCAN0TMDF16 RSCAN0.TMDF16.UINT32 +#define RSCAN0TMDF16L RSCAN0.TMDF16.UINT16[L] +#define RSCAN0TMDF16LL RSCAN0.TMDF16.UINT8[LL] +#define RSCAN0TMDF16LH RSCAN0.TMDF16.UINT8[LH] +#define RSCAN0TMDF16H RSCAN0.TMDF16.UINT16[H] +#define RSCAN0TMDF16HL RSCAN0.TMDF16.UINT8[HL] +#define RSCAN0TMDF16HH RSCAN0.TMDF16.UINT8[HH] +#define RSCAN0TMID7 RSCAN0.TMID7.UINT32 +#define RSCAN0TMID7L RSCAN0.TMID7.UINT16[L] +#define RSCAN0TMID7LL RSCAN0.TMID7.UINT8[LL] +#define RSCAN0TMID7LH RSCAN0.TMID7.UINT8[LH] +#define RSCAN0TMID7H RSCAN0.TMID7.UINT16[H] +#define RSCAN0TMID7HL RSCAN0.TMID7.UINT8[HL] +#define RSCAN0TMID7HH RSCAN0.TMID7.UINT8[HH] +#define RSCAN0TMPTR7 RSCAN0.TMPTR7.UINT32 +#define RSCAN0TMPTR7L RSCAN0.TMPTR7.UINT16[L] +#define RSCAN0TMPTR7LL RSCAN0.TMPTR7.UINT8[LL] +#define RSCAN0TMPTR7LH RSCAN0.TMPTR7.UINT8[LH] +#define RSCAN0TMPTR7H RSCAN0.TMPTR7.UINT16[H] +#define RSCAN0TMPTR7HL RSCAN0.TMPTR7.UINT8[HL] +#define RSCAN0TMPTR7HH RSCAN0.TMPTR7.UINT8[HH] +#define RSCAN0TMDF07 RSCAN0.TMDF07.UINT32 +#define RSCAN0TMDF07L RSCAN0.TMDF07.UINT16[L] +#define RSCAN0TMDF07LL RSCAN0.TMDF07.UINT8[LL] +#define RSCAN0TMDF07LH RSCAN0.TMDF07.UINT8[LH] +#define RSCAN0TMDF07H RSCAN0.TMDF07.UINT16[H] +#define RSCAN0TMDF07HL RSCAN0.TMDF07.UINT8[HL] +#define RSCAN0TMDF07HH RSCAN0.TMDF07.UINT8[HH] +#define RSCAN0TMDF17 RSCAN0.TMDF17.UINT32 +#define RSCAN0TMDF17L RSCAN0.TMDF17.UINT16[L] +#define RSCAN0TMDF17LL RSCAN0.TMDF17.UINT8[LL] +#define RSCAN0TMDF17LH RSCAN0.TMDF17.UINT8[LH] +#define RSCAN0TMDF17H RSCAN0.TMDF17.UINT16[H] +#define RSCAN0TMDF17HL RSCAN0.TMDF17.UINT8[HL] +#define RSCAN0TMDF17HH RSCAN0.TMDF17.UINT8[HH] +#define RSCAN0TMID8 RSCAN0.TMID8.UINT32 +#define RSCAN0TMID8L RSCAN0.TMID8.UINT16[L] +#define RSCAN0TMID8LL RSCAN0.TMID8.UINT8[LL] +#define RSCAN0TMID8LH RSCAN0.TMID8.UINT8[LH] +#define RSCAN0TMID8H RSCAN0.TMID8.UINT16[H] +#define RSCAN0TMID8HL RSCAN0.TMID8.UINT8[HL] +#define RSCAN0TMID8HH RSCAN0.TMID8.UINT8[HH] +#define RSCAN0TMPTR8 RSCAN0.TMPTR8.UINT32 +#define RSCAN0TMPTR8L RSCAN0.TMPTR8.UINT16[L] +#define RSCAN0TMPTR8LL RSCAN0.TMPTR8.UINT8[LL] +#define RSCAN0TMPTR8LH RSCAN0.TMPTR8.UINT8[LH] +#define RSCAN0TMPTR8H RSCAN0.TMPTR8.UINT16[H] +#define RSCAN0TMPTR8HL RSCAN0.TMPTR8.UINT8[HL] +#define RSCAN0TMPTR8HH RSCAN0.TMPTR8.UINT8[HH] +#define RSCAN0TMDF08 RSCAN0.TMDF08.UINT32 +#define RSCAN0TMDF08L RSCAN0.TMDF08.UINT16[L] +#define RSCAN0TMDF08LL RSCAN0.TMDF08.UINT8[LL] +#define RSCAN0TMDF08LH RSCAN0.TMDF08.UINT8[LH] +#define RSCAN0TMDF08H RSCAN0.TMDF08.UINT16[H] +#define RSCAN0TMDF08HL RSCAN0.TMDF08.UINT8[HL] +#define RSCAN0TMDF08HH RSCAN0.TMDF08.UINT8[HH] +#define RSCAN0TMDF18 RSCAN0.TMDF18.UINT32 +#define RSCAN0TMDF18L RSCAN0.TMDF18.UINT16[L] +#define RSCAN0TMDF18LL RSCAN0.TMDF18.UINT8[LL] +#define RSCAN0TMDF18LH RSCAN0.TMDF18.UINT8[LH] +#define RSCAN0TMDF18H RSCAN0.TMDF18.UINT16[H] +#define RSCAN0TMDF18HL RSCAN0.TMDF18.UINT8[HL] +#define RSCAN0TMDF18HH RSCAN0.TMDF18.UINT8[HH] +#define RSCAN0TMID9 RSCAN0.TMID9.UINT32 +#define RSCAN0TMID9L RSCAN0.TMID9.UINT16[L] +#define RSCAN0TMID9LL RSCAN0.TMID9.UINT8[LL] +#define RSCAN0TMID9LH RSCAN0.TMID9.UINT8[LH] +#define RSCAN0TMID9H RSCAN0.TMID9.UINT16[H] +#define RSCAN0TMID9HL RSCAN0.TMID9.UINT8[HL] +#define RSCAN0TMID9HH RSCAN0.TMID9.UINT8[HH] +#define RSCAN0TMPTR9 RSCAN0.TMPTR9.UINT32 +#define RSCAN0TMPTR9L RSCAN0.TMPTR9.UINT16[L] +#define RSCAN0TMPTR9LL RSCAN0.TMPTR9.UINT8[LL] +#define RSCAN0TMPTR9LH RSCAN0.TMPTR9.UINT8[LH] +#define RSCAN0TMPTR9H RSCAN0.TMPTR9.UINT16[H] +#define RSCAN0TMPTR9HL RSCAN0.TMPTR9.UINT8[HL] +#define RSCAN0TMPTR9HH RSCAN0.TMPTR9.UINT8[HH] +#define RSCAN0TMDF09 RSCAN0.TMDF09.UINT32 +#define RSCAN0TMDF09L RSCAN0.TMDF09.UINT16[L] +#define RSCAN0TMDF09LL RSCAN0.TMDF09.UINT8[LL] +#define RSCAN0TMDF09LH RSCAN0.TMDF09.UINT8[LH] +#define RSCAN0TMDF09H RSCAN0.TMDF09.UINT16[H] +#define RSCAN0TMDF09HL RSCAN0.TMDF09.UINT8[HL] +#define RSCAN0TMDF09HH RSCAN0.TMDF09.UINT8[HH] +#define RSCAN0TMDF19 RSCAN0.TMDF19.UINT32 +#define RSCAN0TMDF19L RSCAN0.TMDF19.UINT16[L] +#define RSCAN0TMDF19LL RSCAN0.TMDF19.UINT8[LL] +#define RSCAN0TMDF19LH RSCAN0.TMDF19.UINT8[LH] +#define RSCAN0TMDF19H RSCAN0.TMDF19.UINT16[H] +#define RSCAN0TMDF19HL RSCAN0.TMDF19.UINT8[HL] +#define RSCAN0TMDF19HH RSCAN0.TMDF19.UINT8[HH] +#define RSCAN0TMID10 RSCAN0.TMID10.UINT32 +#define RSCAN0TMID10L RSCAN0.TMID10.UINT16[L] +#define RSCAN0TMID10LL RSCAN0.TMID10.UINT8[LL] +#define RSCAN0TMID10LH RSCAN0.TMID10.UINT8[LH] +#define RSCAN0TMID10H RSCAN0.TMID10.UINT16[H] +#define RSCAN0TMID10HL RSCAN0.TMID10.UINT8[HL] +#define RSCAN0TMID10HH RSCAN0.TMID10.UINT8[HH] +#define RSCAN0TMPTR10 RSCAN0.TMPTR10.UINT32 +#define RSCAN0TMPTR10L RSCAN0.TMPTR10.UINT16[L] +#define RSCAN0TMPTR10LL RSCAN0.TMPTR10.UINT8[LL] +#define RSCAN0TMPTR10LH RSCAN0.TMPTR10.UINT8[LH] +#define RSCAN0TMPTR10H RSCAN0.TMPTR10.UINT16[H] +#define RSCAN0TMPTR10HL RSCAN0.TMPTR10.UINT8[HL] +#define RSCAN0TMPTR10HH RSCAN0.TMPTR10.UINT8[HH] +#define RSCAN0TMDF010 RSCAN0.TMDF010.UINT32 +#define RSCAN0TMDF010L RSCAN0.TMDF010.UINT16[L] +#define RSCAN0TMDF010LL RSCAN0.TMDF010.UINT8[LL] +#define RSCAN0TMDF010LH RSCAN0.TMDF010.UINT8[LH] +#define RSCAN0TMDF010H RSCAN0.TMDF010.UINT16[H] +#define RSCAN0TMDF010HL RSCAN0.TMDF010.UINT8[HL] +#define RSCAN0TMDF010HH RSCAN0.TMDF010.UINT8[HH] +#define RSCAN0TMDF110 RSCAN0.TMDF110.UINT32 +#define RSCAN0TMDF110L RSCAN0.TMDF110.UINT16[L] +#define RSCAN0TMDF110LL RSCAN0.TMDF110.UINT8[LL] +#define RSCAN0TMDF110LH RSCAN0.TMDF110.UINT8[LH] +#define RSCAN0TMDF110H RSCAN0.TMDF110.UINT16[H] +#define RSCAN0TMDF110HL RSCAN0.TMDF110.UINT8[HL] +#define RSCAN0TMDF110HH RSCAN0.TMDF110.UINT8[HH] +#define RSCAN0TMID11 RSCAN0.TMID11.UINT32 +#define RSCAN0TMID11L RSCAN0.TMID11.UINT16[L] +#define RSCAN0TMID11LL RSCAN0.TMID11.UINT8[LL] +#define RSCAN0TMID11LH RSCAN0.TMID11.UINT8[LH] +#define RSCAN0TMID11H RSCAN0.TMID11.UINT16[H] +#define RSCAN0TMID11HL RSCAN0.TMID11.UINT8[HL] +#define RSCAN0TMID11HH RSCAN0.TMID11.UINT8[HH] +#define RSCAN0TMPTR11 RSCAN0.TMPTR11.UINT32 +#define RSCAN0TMPTR11L RSCAN0.TMPTR11.UINT16[L] +#define RSCAN0TMPTR11LL RSCAN0.TMPTR11.UINT8[LL] +#define RSCAN0TMPTR11LH RSCAN0.TMPTR11.UINT8[LH] +#define RSCAN0TMPTR11H RSCAN0.TMPTR11.UINT16[H] +#define RSCAN0TMPTR11HL RSCAN0.TMPTR11.UINT8[HL] +#define RSCAN0TMPTR11HH RSCAN0.TMPTR11.UINT8[HH] +#define RSCAN0TMDF011 RSCAN0.TMDF011.UINT32 +#define RSCAN0TMDF011L RSCAN0.TMDF011.UINT16[L] +#define RSCAN0TMDF011LL RSCAN0.TMDF011.UINT8[LL] +#define RSCAN0TMDF011LH RSCAN0.TMDF011.UINT8[LH] +#define RSCAN0TMDF011H RSCAN0.TMDF011.UINT16[H] +#define RSCAN0TMDF011HL RSCAN0.TMDF011.UINT8[HL] +#define RSCAN0TMDF011HH RSCAN0.TMDF011.UINT8[HH] +#define RSCAN0TMDF111 RSCAN0.TMDF111.UINT32 +#define RSCAN0TMDF111L RSCAN0.TMDF111.UINT16[L] +#define RSCAN0TMDF111LL RSCAN0.TMDF111.UINT8[LL] +#define RSCAN0TMDF111LH RSCAN0.TMDF111.UINT8[LH] +#define RSCAN0TMDF111H RSCAN0.TMDF111.UINT16[H] +#define RSCAN0TMDF111HL RSCAN0.TMDF111.UINT8[HL] +#define RSCAN0TMDF111HH RSCAN0.TMDF111.UINT8[HH] +#define RSCAN0TMID12 RSCAN0.TMID12.UINT32 +#define RSCAN0TMID12L RSCAN0.TMID12.UINT16[L] +#define RSCAN0TMID12LL RSCAN0.TMID12.UINT8[LL] +#define RSCAN0TMID12LH RSCAN0.TMID12.UINT8[LH] +#define RSCAN0TMID12H RSCAN0.TMID12.UINT16[H] +#define RSCAN0TMID12HL RSCAN0.TMID12.UINT8[HL] +#define RSCAN0TMID12HH RSCAN0.TMID12.UINT8[HH] +#define RSCAN0TMPTR12 RSCAN0.TMPTR12.UINT32 +#define RSCAN0TMPTR12L RSCAN0.TMPTR12.UINT16[L] +#define RSCAN0TMPTR12LL RSCAN0.TMPTR12.UINT8[LL] +#define RSCAN0TMPTR12LH RSCAN0.TMPTR12.UINT8[LH] +#define RSCAN0TMPTR12H RSCAN0.TMPTR12.UINT16[H] +#define RSCAN0TMPTR12HL RSCAN0.TMPTR12.UINT8[HL] +#define RSCAN0TMPTR12HH RSCAN0.TMPTR12.UINT8[HH] +#define RSCAN0TMDF012 RSCAN0.TMDF012.UINT32 +#define RSCAN0TMDF012L RSCAN0.TMDF012.UINT16[L] +#define RSCAN0TMDF012LL RSCAN0.TMDF012.UINT8[LL] +#define RSCAN0TMDF012LH RSCAN0.TMDF012.UINT8[LH] +#define RSCAN0TMDF012H RSCAN0.TMDF012.UINT16[H] +#define RSCAN0TMDF012HL RSCAN0.TMDF012.UINT8[HL] +#define RSCAN0TMDF012HH RSCAN0.TMDF012.UINT8[HH] +#define RSCAN0TMDF112 RSCAN0.TMDF112.UINT32 +#define RSCAN0TMDF112L RSCAN0.TMDF112.UINT16[L] +#define RSCAN0TMDF112LL RSCAN0.TMDF112.UINT8[LL] +#define RSCAN0TMDF112LH RSCAN0.TMDF112.UINT8[LH] +#define RSCAN0TMDF112H RSCAN0.TMDF112.UINT16[H] +#define RSCAN0TMDF112HL RSCAN0.TMDF112.UINT8[HL] +#define RSCAN0TMDF112HH RSCAN0.TMDF112.UINT8[HH] +#define RSCAN0TMID13 RSCAN0.TMID13.UINT32 +#define RSCAN0TMID13L RSCAN0.TMID13.UINT16[L] +#define RSCAN0TMID13LL RSCAN0.TMID13.UINT8[LL] +#define RSCAN0TMID13LH RSCAN0.TMID13.UINT8[LH] +#define RSCAN0TMID13H RSCAN0.TMID13.UINT16[H] +#define RSCAN0TMID13HL RSCAN0.TMID13.UINT8[HL] +#define RSCAN0TMID13HH RSCAN0.TMID13.UINT8[HH] +#define RSCAN0TMPTR13 RSCAN0.TMPTR13.UINT32 +#define RSCAN0TMPTR13L RSCAN0.TMPTR13.UINT16[L] +#define RSCAN0TMPTR13LL RSCAN0.TMPTR13.UINT8[LL] +#define RSCAN0TMPTR13LH RSCAN0.TMPTR13.UINT8[LH] +#define RSCAN0TMPTR13H RSCAN0.TMPTR13.UINT16[H] +#define RSCAN0TMPTR13HL RSCAN0.TMPTR13.UINT8[HL] +#define RSCAN0TMPTR13HH RSCAN0.TMPTR13.UINT8[HH] +#define RSCAN0TMDF013 RSCAN0.TMDF013.UINT32 +#define RSCAN0TMDF013L RSCAN0.TMDF013.UINT16[L] +#define RSCAN0TMDF013LL RSCAN0.TMDF013.UINT8[LL] +#define RSCAN0TMDF013LH RSCAN0.TMDF013.UINT8[LH] +#define RSCAN0TMDF013H RSCAN0.TMDF013.UINT16[H] +#define RSCAN0TMDF013HL RSCAN0.TMDF013.UINT8[HL] +#define RSCAN0TMDF013HH RSCAN0.TMDF013.UINT8[HH] +#define RSCAN0TMDF113 RSCAN0.TMDF113.UINT32 +#define RSCAN0TMDF113L RSCAN0.TMDF113.UINT16[L] +#define RSCAN0TMDF113LL RSCAN0.TMDF113.UINT8[LL] +#define RSCAN0TMDF113LH RSCAN0.TMDF113.UINT8[LH] +#define RSCAN0TMDF113H RSCAN0.TMDF113.UINT16[H] +#define RSCAN0TMDF113HL RSCAN0.TMDF113.UINT8[HL] +#define RSCAN0TMDF113HH RSCAN0.TMDF113.UINT8[HH] +#define RSCAN0TMID14 RSCAN0.TMID14.UINT32 +#define RSCAN0TMID14L RSCAN0.TMID14.UINT16[L] +#define RSCAN0TMID14LL RSCAN0.TMID14.UINT8[LL] +#define RSCAN0TMID14LH RSCAN0.TMID14.UINT8[LH] +#define RSCAN0TMID14H RSCAN0.TMID14.UINT16[H] +#define RSCAN0TMID14HL RSCAN0.TMID14.UINT8[HL] +#define RSCAN0TMID14HH RSCAN0.TMID14.UINT8[HH] +#define RSCAN0TMPTR14 RSCAN0.TMPTR14.UINT32 +#define RSCAN0TMPTR14L RSCAN0.TMPTR14.UINT16[L] +#define RSCAN0TMPTR14LL RSCAN0.TMPTR14.UINT8[LL] +#define RSCAN0TMPTR14LH RSCAN0.TMPTR14.UINT8[LH] +#define RSCAN0TMPTR14H RSCAN0.TMPTR14.UINT16[H] +#define RSCAN0TMPTR14HL RSCAN0.TMPTR14.UINT8[HL] +#define RSCAN0TMPTR14HH RSCAN0.TMPTR14.UINT8[HH] +#define RSCAN0TMDF014 RSCAN0.TMDF014.UINT32 +#define RSCAN0TMDF014L RSCAN0.TMDF014.UINT16[L] +#define RSCAN0TMDF014LL RSCAN0.TMDF014.UINT8[LL] +#define RSCAN0TMDF014LH RSCAN0.TMDF014.UINT8[LH] +#define RSCAN0TMDF014H RSCAN0.TMDF014.UINT16[H] +#define RSCAN0TMDF014HL RSCAN0.TMDF014.UINT8[HL] +#define RSCAN0TMDF014HH RSCAN0.TMDF014.UINT8[HH] +#define RSCAN0TMDF114 RSCAN0.TMDF114.UINT32 +#define RSCAN0TMDF114L RSCAN0.TMDF114.UINT16[L] +#define RSCAN0TMDF114LL RSCAN0.TMDF114.UINT8[LL] +#define RSCAN0TMDF114LH RSCAN0.TMDF114.UINT8[LH] +#define RSCAN0TMDF114H RSCAN0.TMDF114.UINT16[H] +#define RSCAN0TMDF114HL RSCAN0.TMDF114.UINT8[HL] +#define RSCAN0TMDF114HH RSCAN0.TMDF114.UINT8[HH] +#define RSCAN0TMID15 RSCAN0.TMID15.UINT32 +#define RSCAN0TMID15L RSCAN0.TMID15.UINT16[L] +#define RSCAN0TMID15LL RSCAN0.TMID15.UINT8[LL] +#define RSCAN0TMID15LH RSCAN0.TMID15.UINT8[LH] +#define RSCAN0TMID15H RSCAN0.TMID15.UINT16[H] +#define RSCAN0TMID15HL RSCAN0.TMID15.UINT8[HL] +#define RSCAN0TMID15HH RSCAN0.TMID15.UINT8[HH] +#define RSCAN0TMPTR15 RSCAN0.TMPTR15.UINT32 +#define RSCAN0TMPTR15L RSCAN0.TMPTR15.UINT16[L] +#define RSCAN0TMPTR15LL RSCAN0.TMPTR15.UINT8[LL] +#define RSCAN0TMPTR15LH RSCAN0.TMPTR15.UINT8[LH] +#define RSCAN0TMPTR15H RSCAN0.TMPTR15.UINT16[H] +#define RSCAN0TMPTR15HL RSCAN0.TMPTR15.UINT8[HL] +#define RSCAN0TMPTR15HH RSCAN0.TMPTR15.UINT8[HH] +#define RSCAN0TMDF015 RSCAN0.TMDF015.UINT32 +#define RSCAN0TMDF015L RSCAN0.TMDF015.UINT16[L] +#define RSCAN0TMDF015LL RSCAN0.TMDF015.UINT8[LL] +#define RSCAN0TMDF015LH RSCAN0.TMDF015.UINT8[LH] +#define RSCAN0TMDF015H RSCAN0.TMDF015.UINT16[H] +#define RSCAN0TMDF015HL RSCAN0.TMDF015.UINT8[HL] +#define RSCAN0TMDF015HH RSCAN0.TMDF015.UINT8[HH] +#define RSCAN0TMDF115 RSCAN0.TMDF115.UINT32 +#define RSCAN0TMDF115L RSCAN0.TMDF115.UINT16[L] +#define RSCAN0TMDF115LL RSCAN0.TMDF115.UINT8[LL] +#define RSCAN0TMDF115LH RSCAN0.TMDF115.UINT8[LH] +#define RSCAN0TMDF115H RSCAN0.TMDF115.UINT16[H] +#define RSCAN0TMDF115HL RSCAN0.TMDF115.UINT8[HL] +#define RSCAN0TMDF115HH RSCAN0.TMDF115.UINT8[HH] +#define RSCAN0TMID16 RSCAN0.TMID16.UINT32 +#define RSCAN0TMID16L RSCAN0.TMID16.UINT16[L] +#define RSCAN0TMID16LL RSCAN0.TMID16.UINT8[LL] +#define RSCAN0TMID16LH RSCAN0.TMID16.UINT8[LH] +#define RSCAN0TMID16H RSCAN0.TMID16.UINT16[H] +#define RSCAN0TMID16HL RSCAN0.TMID16.UINT8[HL] +#define RSCAN0TMID16HH RSCAN0.TMID16.UINT8[HH] +#define RSCAN0TMPTR16 RSCAN0.TMPTR16.UINT32 +#define RSCAN0TMPTR16L RSCAN0.TMPTR16.UINT16[L] +#define RSCAN0TMPTR16LL RSCAN0.TMPTR16.UINT8[LL] +#define RSCAN0TMPTR16LH RSCAN0.TMPTR16.UINT8[LH] +#define RSCAN0TMPTR16H RSCAN0.TMPTR16.UINT16[H] +#define RSCAN0TMPTR16HL RSCAN0.TMPTR16.UINT8[HL] +#define RSCAN0TMPTR16HH RSCAN0.TMPTR16.UINT8[HH] +#define RSCAN0TMDF016 RSCAN0.TMDF016.UINT32 +#define RSCAN0TMDF016L RSCAN0.TMDF016.UINT16[L] +#define RSCAN0TMDF016LL RSCAN0.TMDF016.UINT8[LL] +#define RSCAN0TMDF016LH RSCAN0.TMDF016.UINT8[LH] +#define RSCAN0TMDF016H RSCAN0.TMDF016.UINT16[H] +#define RSCAN0TMDF016HL RSCAN0.TMDF016.UINT8[HL] +#define RSCAN0TMDF016HH RSCAN0.TMDF016.UINT8[HH] +#define RSCAN0TMDF116 RSCAN0.TMDF116.UINT32 +#define RSCAN0TMDF116L RSCAN0.TMDF116.UINT16[L] +#define RSCAN0TMDF116LL RSCAN0.TMDF116.UINT8[LL] +#define RSCAN0TMDF116LH RSCAN0.TMDF116.UINT8[LH] +#define RSCAN0TMDF116H RSCAN0.TMDF116.UINT16[H] +#define RSCAN0TMDF116HL RSCAN0.TMDF116.UINT8[HL] +#define RSCAN0TMDF116HH RSCAN0.TMDF116.UINT8[HH] +#define RSCAN0TMID17 RSCAN0.TMID17.UINT32 +#define RSCAN0TMID17L RSCAN0.TMID17.UINT16[L] +#define RSCAN0TMID17LL RSCAN0.TMID17.UINT8[LL] +#define RSCAN0TMID17LH RSCAN0.TMID17.UINT8[LH] +#define RSCAN0TMID17H RSCAN0.TMID17.UINT16[H] +#define RSCAN0TMID17HL RSCAN0.TMID17.UINT8[HL] +#define RSCAN0TMID17HH RSCAN0.TMID17.UINT8[HH] +#define RSCAN0TMPTR17 RSCAN0.TMPTR17.UINT32 +#define RSCAN0TMPTR17L RSCAN0.TMPTR17.UINT16[L] +#define RSCAN0TMPTR17LL RSCAN0.TMPTR17.UINT8[LL] +#define RSCAN0TMPTR17LH RSCAN0.TMPTR17.UINT8[LH] +#define RSCAN0TMPTR17H RSCAN0.TMPTR17.UINT16[H] +#define RSCAN0TMPTR17HL RSCAN0.TMPTR17.UINT8[HL] +#define RSCAN0TMPTR17HH RSCAN0.TMPTR17.UINT8[HH] +#define RSCAN0TMDF017 RSCAN0.TMDF017.UINT32 +#define RSCAN0TMDF017L RSCAN0.TMDF017.UINT16[L] +#define RSCAN0TMDF017LL RSCAN0.TMDF017.UINT8[LL] +#define RSCAN0TMDF017LH RSCAN0.TMDF017.UINT8[LH] +#define RSCAN0TMDF017H RSCAN0.TMDF017.UINT16[H] +#define RSCAN0TMDF017HL RSCAN0.TMDF017.UINT8[HL] +#define RSCAN0TMDF017HH RSCAN0.TMDF017.UINT8[HH] +#define RSCAN0TMDF117 RSCAN0.TMDF117.UINT32 +#define RSCAN0TMDF117L RSCAN0.TMDF117.UINT16[L] +#define RSCAN0TMDF117LL RSCAN0.TMDF117.UINT8[LL] +#define RSCAN0TMDF117LH RSCAN0.TMDF117.UINT8[LH] +#define RSCAN0TMDF117H RSCAN0.TMDF117.UINT16[H] +#define RSCAN0TMDF117HL RSCAN0.TMDF117.UINT8[HL] +#define RSCAN0TMDF117HH RSCAN0.TMDF117.UINT8[HH] +#define RSCAN0TMID18 RSCAN0.TMID18.UINT32 +#define RSCAN0TMID18L RSCAN0.TMID18.UINT16[L] +#define RSCAN0TMID18LL RSCAN0.TMID18.UINT8[LL] +#define RSCAN0TMID18LH RSCAN0.TMID18.UINT8[LH] +#define RSCAN0TMID18H RSCAN0.TMID18.UINT16[H] +#define RSCAN0TMID18HL RSCAN0.TMID18.UINT8[HL] +#define RSCAN0TMID18HH RSCAN0.TMID18.UINT8[HH] +#define RSCAN0TMPTR18 RSCAN0.TMPTR18.UINT32 +#define RSCAN0TMPTR18L RSCAN0.TMPTR18.UINT16[L] +#define RSCAN0TMPTR18LL RSCAN0.TMPTR18.UINT8[LL] +#define RSCAN0TMPTR18LH RSCAN0.TMPTR18.UINT8[LH] +#define RSCAN0TMPTR18H RSCAN0.TMPTR18.UINT16[H] +#define RSCAN0TMPTR18HL RSCAN0.TMPTR18.UINT8[HL] +#define RSCAN0TMPTR18HH RSCAN0.TMPTR18.UINT8[HH] +#define RSCAN0TMDF018 RSCAN0.TMDF018.UINT32 +#define RSCAN0TMDF018L RSCAN0.TMDF018.UINT16[L] +#define RSCAN0TMDF018LL RSCAN0.TMDF018.UINT8[LL] +#define RSCAN0TMDF018LH RSCAN0.TMDF018.UINT8[LH] +#define RSCAN0TMDF018H RSCAN0.TMDF018.UINT16[H] +#define RSCAN0TMDF018HL RSCAN0.TMDF018.UINT8[HL] +#define RSCAN0TMDF018HH RSCAN0.TMDF018.UINT8[HH] +#define RSCAN0TMDF118 RSCAN0.TMDF118.UINT32 +#define RSCAN0TMDF118L RSCAN0.TMDF118.UINT16[L] +#define RSCAN0TMDF118LL RSCAN0.TMDF118.UINT8[LL] +#define RSCAN0TMDF118LH RSCAN0.TMDF118.UINT8[LH] +#define RSCAN0TMDF118H RSCAN0.TMDF118.UINT16[H] +#define RSCAN0TMDF118HL RSCAN0.TMDF118.UINT8[HL] +#define RSCAN0TMDF118HH RSCAN0.TMDF118.UINT8[HH] +#define RSCAN0TMID19 RSCAN0.TMID19.UINT32 +#define RSCAN0TMID19L RSCAN0.TMID19.UINT16[L] +#define RSCAN0TMID19LL RSCAN0.TMID19.UINT8[LL] +#define RSCAN0TMID19LH RSCAN0.TMID19.UINT8[LH] +#define RSCAN0TMID19H RSCAN0.TMID19.UINT16[H] +#define RSCAN0TMID19HL RSCAN0.TMID19.UINT8[HL] +#define RSCAN0TMID19HH RSCAN0.TMID19.UINT8[HH] +#define RSCAN0TMPTR19 RSCAN0.TMPTR19.UINT32 +#define RSCAN0TMPTR19L RSCAN0.TMPTR19.UINT16[L] +#define RSCAN0TMPTR19LL RSCAN0.TMPTR19.UINT8[LL] +#define RSCAN0TMPTR19LH RSCAN0.TMPTR19.UINT8[LH] +#define RSCAN0TMPTR19H RSCAN0.TMPTR19.UINT16[H] +#define RSCAN0TMPTR19HL RSCAN0.TMPTR19.UINT8[HL] +#define RSCAN0TMPTR19HH RSCAN0.TMPTR19.UINT8[HH] +#define RSCAN0TMDF019 RSCAN0.TMDF019.UINT32 +#define RSCAN0TMDF019L RSCAN0.TMDF019.UINT16[L] +#define RSCAN0TMDF019LL RSCAN0.TMDF019.UINT8[LL] +#define RSCAN0TMDF019LH RSCAN0.TMDF019.UINT8[LH] +#define RSCAN0TMDF019H RSCAN0.TMDF019.UINT16[H] +#define RSCAN0TMDF019HL RSCAN0.TMDF019.UINT8[HL] +#define RSCAN0TMDF019HH RSCAN0.TMDF019.UINT8[HH] +#define RSCAN0TMDF119 RSCAN0.TMDF119.UINT32 +#define RSCAN0TMDF119L RSCAN0.TMDF119.UINT16[L] +#define RSCAN0TMDF119LL RSCAN0.TMDF119.UINT8[LL] +#define RSCAN0TMDF119LH RSCAN0.TMDF119.UINT8[LH] +#define RSCAN0TMDF119H RSCAN0.TMDF119.UINT16[H] +#define RSCAN0TMDF119HL RSCAN0.TMDF119.UINT8[HL] +#define RSCAN0TMDF119HH RSCAN0.TMDF119.UINT8[HH] +#define RSCAN0TMID20 RSCAN0.TMID20.UINT32 +#define RSCAN0TMID20L RSCAN0.TMID20.UINT16[L] +#define RSCAN0TMID20LL RSCAN0.TMID20.UINT8[LL] +#define RSCAN0TMID20LH RSCAN0.TMID20.UINT8[LH] +#define RSCAN0TMID20H RSCAN0.TMID20.UINT16[H] +#define RSCAN0TMID20HL RSCAN0.TMID20.UINT8[HL] +#define RSCAN0TMID20HH RSCAN0.TMID20.UINT8[HH] +#define RSCAN0TMPTR20 RSCAN0.TMPTR20.UINT32 +#define RSCAN0TMPTR20L RSCAN0.TMPTR20.UINT16[L] +#define RSCAN0TMPTR20LL RSCAN0.TMPTR20.UINT8[LL] +#define RSCAN0TMPTR20LH RSCAN0.TMPTR20.UINT8[LH] +#define RSCAN0TMPTR20H RSCAN0.TMPTR20.UINT16[H] +#define RSCAN0TMPTR20HL RSCAN0.TMPTR20.UINT8[HL] +#define RSCAN0TMPTR20HH RSCAN0.TMPTR20.UINT8[HH] +#define RSCAN0TMDF020 RSCAN0.TMDF020.UINT32 +#define RSCAN0TMDF020L RSCAN0.TMDF020.UINT16[L] +#define RSCAN0TMDF020LL RSCAN0.TMDF020.UINT8[LL] +#define RSCAN0TMDF020LH RSCAN0.TMDF020.UINT8[LH] +#define RSCAN0TMDF020H RSCAN0.TMDF020.UINT16[H] +#define RSCAN0TMDF020HL RSCAN0.TMDF020.UINT8[HL] +#define RSCAN0TMDF020HH RSCAN0.TMDF020.UINT8[HH] +#define RSCAN0TMDF120 RSCAN0.TMDF120.UINT32 +#define RSCAN0TMDF120L RSCAN0.TMDF120.UINT16[L] +#define RSCAN0TMDF120LL RSCAN0.TMDF120.UINT8[LL] +#define RSCAN0TMDF120LH RSCAN0.TMDF120.UINT8[LH] +#define RSCAN0TMDF120H RSCAN0.TMDF120.UINT16[H] +#define RSCAN0TMDF120HL RSCAN0.TMDF120.UINT8[HL] +#define RSCAN0TMDF120HH RSCAN0.TMDF120.UINT8[HH] +#define RSCAN0TMID21 RSCAN0.TMID21.UINT32 +#define RSCAN0TMID21L RSCAN0.TMID21.UINT16[L] +#define RSCAN0TMID21LL RSCAN0.TMID21.UINT8[LL] +#define RSCAN0TMID21LH RSCAN0.TMID21.UINT8[LH] +#define RSCAN0TMID21H RSCAN0.TMID21.UINT16[H] +#define RSCAN0TMID21HL RSCAN0.TMID21.UINT8[HL] +#define RSCAN0TMID21HH RSCAN0.TMID21.UINT8[HH] +#define RSCAN0TMPTR21 RSCAN0.TMPTR21.UINT32 +#define RSCAN0TMPTR21L RSCAN0.TMPTR21.UINT16[L] +#define RSCAN0TMPTR21LL RSCAN0.TMPTR21.UINT8[LL] +#define RSCAN0TMPTR21LH RSCAN0.TMPTR21.UINT8[LH] +#define RSCAN0TMPTR21H RSCAN0.TMPTR21.UINT16[H] +#define RSCAN0TMPTR21HL RSCAN0.TMPTR21.UINT8[HL] +#define RSCAN0TMPTR21HH RSCAN0.TMPTR21.UINT8[HH] +#define RSCAN0TMDF021 RSCAN0.TMDF021.UINT32 +#define RSCAN0TMDF021L RSCAN0.TMDF021.UINT16[L] +#define RSCAN0TMDF021LL RSCAN0.TMDF021.UINT8[LL] +#define RSCAN0TMDF021LH RSCAN0.TMDF021.UINT8[LH] +#define RSCAN0TMDF021H RSCAN0.TMDF021.UINT16[H] +#define RSCAN0TMDF021HL RSCAN0.TMDF021.UINT8[HL] +#define RSCAN0TMDF021HH RSCAN0.TMDF021.UINT8[HH] +#define RSCAN0TMDF121 RSCAN0.TMDF121.UINT32 +#define RSCAN0TMDF121L RSCAN0.TMDF121.UINT16[L] +#define RSCAN0TMDF121LL RSCAN0.TMDF121.UINT8[LL] +#define RSCAN0TMDF121LH RSCAN0.TMDF121.UINT8[LH] +#define RSCAN0TMDF121H RSCAN0.TMDF121.UINT16[H] +#define RSCAN0TMDF121HL RSCAN0.TMDF121.UINT8[HL] +#define RSCAN0TMDF121HH RSCAN0.TMDF121.UINT8[HH] +#define RSCAN0TMID22 RSCAN0.TMID22.UINT32 +#define RSCAN0TMID22L RSCAN0.TMID22.UINT16[L] +#define RSCAN0TMID22LL RSCAN0.TMID22.UINT8[LL] +#define RSCAN0TMID22LH RSCAN0.TMID22.UINT8[LH] +#define RSCAN0TMID22H RSCAN0.TMID22.UINT16[H] +#define RSCAN0TMID22HL RSCAN0.TMID22.UINT8[HL] +#define RSCAN0TMID22HH RSCAN0.TMID22.UINT8[HH] +#define RSCAN0TMPTR22 RSCAN0.TMPTR22.UINT32 +#define RSCAN0TMPTR22L RSCAN0.TMPTR22.UINT16[L] +#define RSCAN0TMPTR22LL RSCAN0.TMPTR22.UINT8[LL] +#define RSCAN0TMPTR22LH RSCAN0.TMPTR22.UINT8[LH] +#define RSCAN0TMPTR22H RSCAN0.TMPTR22.UINT16[H] +#define RSCAN0TMPTR22HL RSCAN0.TMPTR22.UINT8[HL] +#define RSCAN0TMPTR22HH RSCAN0.TMPTR22.UINT8[HH] +#define RSCAN0TMDF022 RSCAN0.TMDF022.UINT32 +#define RSCAN0TMDF022L RSCAN0.TMDF022.UINT16[L] +#define RSCAN0TMDF022LL RSCAN0.TMDF022.UINT8[LL] +#define RSCAN0TMDF022LH RSCAN0.TMDF022.UINT8[LH] +#define RSCAN0TMDF022H RSCAN0.TMDF022.UINT16[H] +#define RSCAN0TMDF022HL RSCAN0.TMDF022.UINT8[HL] +#define RSCAN0TMDF022HH RSCAN0.TMDF022.UINT8[HH] +#define RSCAN0TMDF122 RSCAN0.TMDF122.UINT32 +#define RSCAN0TMDF122L RSCAN0.TMDF122.UINT16[L] +#define RSCAN0TMDF122LL RSCAN0.TMDF122.UINT8[LL] +#define RSCAN0TMDF122LH RSCAN0.TMDF122.UINT8[LH] +#define RSCAN0TMDF122H RSCAN0.TMDF122.UINT16[H] +#define RSCAN0TMDF122HL RSCAN0.TMDF122.UINT8[HL] +#define RSCAN0TMDF122HH RSCAN0.TMDF122.UINT8[HH] +#define RSCAN0TMID23 RSCAN0.TMID23.UINT32 +#define RSCAN0TMID23L RSCAN0.TMID23.UINT16[L] +#define RSCAN0TMID23LL RSCAN0.TMID23.UINT8[LL] +#define RSCAN0TMID23LH RSCAN0.TMID23.UINT8[LH] +#define RSCAN0TMID23H RSCAN0.TMID23.UINT16[H] +#define RSCAN0TMID23HL RSCAN0.TMID23.UINT8[HL] +#define RSCAN0TMID23HH RSCAN0.TMID23.UINT8[HH] +#define RSCAN0TMPTR23 RSCAN0.TMPTR23.UINT32 +#define RSCAN0TMPTR23L RSCAN0.TMPTR23.UINT16[L] +#define RSCAN0TMPTR23LL RSCAN0.TMPTR23.UINT8[LL] +#define RSCAN0TMPTR23LH RSCAN0.TMPTR23.UINT8[LH] +#define RSCAN0TMPTR23H RSCAN0.TMPTR23.UINT16[H] +#define RSCAN0TMPTR23HL RSCAN0.TMPTR23.UINT8[HL] +#define RSCAN0TMPTR23HH RSCAN0.TMPTR23.UINT8[HH] +#define RSCAN0TMDF023 RSCAN0.TMDF023.UINT32 +#define RSCAN0TMDF023L RSCAN0.TMDF023.UINT16[L] +#define RSCAN0TMDF023LL RSCAN0.TMDF023.UINT8[LL] +#define RSCAN0TMDF023LH RSCAN0.TMDF023.UINT8[LH] +#define RSCAN0TMDF023H RSCAN0.TMDF023.UINT16[H] +#define RSCAN0TMDF023HL RSCAN0.TMDF023.UINT8[HL] +#define RSCAN0TMDF023HH RSCAN0.TMDF023.UINT8[HH] +#define RSCAN0TMDF123 RSCAN0.TMDF123.UINT32 +#define RSCAN0TMDF123L RSCAN0.TMDF123.UINT16[L] +#define RSCAN0TMDF123LL RSCAN0.TMDF123.UINT8[LL] +#define RSCAN0TMDF123LH RSCAN0.TMDF123.UINT8[LH] +#define RSCAN0TMDF123H RSCAN0.TMDF123.UINT16[H] +#define RSCAN0TMDF123HL RSCAN0.TMDF123.UINT8[HL] +#define RSCAN0TMDF123HH RSCAN0.TMDF123.UINT8[HH] +#define RSCAN0TMID24 RSCAN0.TMID24.UINT32 +#define RSCAN0TMID24L RSCAN0.TMID24.UINT16[L] +#define RSCAN0TMID24LL RSCAN0.TMID24.UINT8[LL] +#define RSCAN0TMID24LH RSCAN0.TMID24.UINT8[LH] +#define RSCAN0TMID24H RSCAN0.TMID24.UINT16[H] +#define RSCAN0TMID24HL RSCAN0.TMID24.UINT8[HL] +#define RSCAN0TMID24HH RSCAN0.TMID24.UINT8[HH] +#define RSCAN0TMPTR24 RSCAN0.TMPTR24.UINT32 +#define RSCAN0TMPTR24L RSCAN0.TMPTR24.UINT16[L] +#define RSCAN0TMPTR24LL RSCAN0.TMPTR24.UINT8[LL] +#define RSCAN0TMPTR24LH RSCAN0.TMPTR24.UINT8[LH] +#define RSCAN0TMPTR24H RSCAN0.TMPTR24.UINT16[H] +#define RSCAN0TMPTR24HL RSCAN0.TMPTR24.UINT8[HL] +#define RSCAN0TMPTR24HH RSCAN0.TMPTR24.UINT8[HH] +#define RSCAN0TMDF024 RSCAN0.TMDF024.UINT32 +#define RSCAN0TMDF024L RSCAN0.TMDF024.UINT16[L] +#define RSCAN0TMDF024LL RSCAN0.TMDF024.UINT8[LL] +#define RSCAN0TMDF024LH RSCAN0.TMDF024.UINT8[LH] +#define RSCAN0TMDF024H RSCAN0.TMDF024.UINT16[H] +#define RSCAN0TMDF024HL RSCAN0.TMDF024.UINT8[HL] +#define RSCAN0TMDF024HH RSCAN0.TMDF024.UINT8[HH] +#define RSCAN0TMDF124 RSCAN0.TMDF124.UINT32 +#define RSCAN0TMDF124L RSCAN0.TMDF124.UINT16[L] +#define RSCAN0TMDF124LL RSCAN0.TMDF124.UINT8[LL] +#define RSCAN0TMDF124LH RSCAN0.TMDF124.UINT8[LH] +#define RSCAN0TMDF124H RSCAN0.TMDF124.UINT16[H] +#define RSCAN0TMDF124HL RSCAN0.TMDF124.UINT8[HL] +#define RSCAN0TMDF124HH RSCAN0.TMDF124.UINT8[HH] +#define RSCAN0TMID25 RSCAN0.TMID25.UINT32 +#define RSCAN0TMID25L RSCAN0.TMID25.UINT16[L] +#define RSCAN0TMID25LL RSCAN0.TMID25.UINT8[LL] +#define RSCAN0TMID25LH RSCAN0.TMID25.UINT8[LH] +#define RSCAN0TMID25H RSCAN0.TMID25.UINT16[H] +#define RSCAN0TMID25HL RSCAN0.TMID25.UINT8[HL] +#define RSCAN0TMID25HH RSCAN0.TMID25.UINT8[HH] +#define RSCAN0TMPTR25 RSCAN0.TMPTR25.UINT32 +#define RSCAN0TMPTR25L RSCAN0.TMPTR25.UINT16[L] +#define RSCAN0TMPTR25LL RSCAN0.TMPTR25.UINT8[LL] +#define RSCAN0TMPTR25LH RSCAN0.TMPTR25.UINT8[LH] +#define RSCAN0TMPTR25H RSCAN0.TMPTR25.UINT16[H] +#define RSCAN0TMPTR25HL RSCAN0.TMPTR25.UINT8[HL] +#define RSCAN0TMPTR25HH RSCAN0.TMPTR25.UINT8[HH] +#define RSCAN0TMDF025 RSCAN0.TMDF025.UINT32 +#define RSCAN0TMDF025L RSCAN0.TMDF025.UINT16[L] +#define RSCAN0TMDF025LL RSCAN0.TMDF025.UINT8[LL] +#define RSCAN0TMDF025LH RSCAN0.TMDF025.UINT8[LH] +#define RSCAN0TMDF025H RSCAN0.TMDF025.UINT16[H] +#define RSCAN0TMDF025HL RSCAN0.TMDF025.UINT8[HL] +#define RSCAN0TMDF025HH RSCAN0.TMDF025.UINT8[HH] +#define RSCAN0TMDF125 RSCAN0.TMDF125.UINT32 +#define RSCAN0TMDF125L RSCAN0.TMDF125.UINT16[L] +#define RSCAN0TMDF125LL RSCAN0.TMDF125.UINT8[LL] +#define RSCAN0TMDF125LH RSCAN0.TMDF125.UINT8[LH] +#define RSCAN0TMDF125H RSCAN0.TMDF125.UINT16[H] +#define RSCAN0TMDF125HL RSCAN0.TMDF125.UINT8[HL] +#define RSCAN0TMDF125HH RSCAN0.TMDF125.UINT8[HH] +#define RSCAN0TMID26 RSCAN0.TMID26.UINT32 +#define RSCAN0TMID26L RSCAN0.TMID26.UINT16[L] +#define RSCAN0TMID26LL RSCAN0.TMID26.UINT8[LL] +#define RSCAN0TMID26LH RSCAN0.TMID26.UINT8[LH] +#define RSCAN0TMID26H RSCAN0.TMID26.UINT16[H] +#define RSCAN0TMID26HL RSCAN0.TMID26.UINT8[HL] +#define RSCAN0TMID26HH RSCAN0.TMID26.UINT8[HH] +#define RSCAN0TMPTR26 RSCAN0.TMPTR26.UINT32 +#define RSCAN0TMPTR26L RSCAN0.TMPTR26.UINT16[L] +#define RSCAN0TMPTR26LL RSCAN0.TMPTR26.UINT8[LL] +#define RSCAN0TMPTR26LH RSCAN0.TMPTR26.UINT8[LH] +#define RSCAN0TMPTR26H RSCAN0.TMPTR26.UINT16[H] +#define RSCAN0TMPTR26HL RSCAN0.TMPTR26.UINT8[HL] +#define RSCAN0TMPTR26HH RSCAN0.TMPTR26.UINT8[HH] +#define RSCAN0TMDF026 RSCAN0.TMDF026.UINT32 +#define RSCAN0TMDF026L RSCAN0.TMDF026.UINT16[L] +#define RSCAN0TMDF026LL RSCAN0.TMDF026.UINT8[LL] +#define RSCAN0TMDF026LH RSCAN0.TMDF026.UINT8[LH] +#define RSCAN0TMDF026H RSCAN0.TMDF026.UINT16[H] +#define RSCAN0TMDF026HL RSCAN0.TMDF026.UINT8[HL] +#define RSCAN0TMDF026HH RSCAN0.TMDF026.UINT8[HH] +#define RSCAN0TMDF126 RSCAN0.TMDF126.UINT32 +#define RSCAN0TMDF126L RSCAN0.TMDF126.UINT16[L] +#define RSCAN0TMDF126LL RSCAN0.TMDF126.UINT8[LL] +#define RSCAN0TMDF126LH RSCAN0.TMDF126.UINT8[LH] +#define RSCAN0TMDF126H RSCAN0.TMDF126.UINT16[H] +#define RSCAN0TMDF126HL RSCAN0.TMDF126.UINT8[HL] +#define RSCAN0TMDF126HH RSCAN0.TMDF126.UINT8[HH] +#define RSCAN0TMID27 RSCAN0.TMID27.UINT32 +#define RSCAN0TMID27L RSCAN0.TMID27.UINT16[L] +#define RSCAN0TMID27LL RSCAN0.TMID27.UINT8[LL] +#define RSCAN0TMID27LH RSCAN0.TMID27.UINT8[LH] +#define RSCAN0TMID27H RSCAN0.TMID27.UINT16[H] +#define RSCAN0TMID27HL RSCAN0.TMID27.UINT8[HL] +#define RSCAN0TMID27HH RSCAN0.TMID27.UINT8[HH] +#define RSCAN0TMPTR27 RSCAN0.TMPTR27.UINT32 +#define RSCAN0TMPTR27L RSCAN0.TMPTR27.UINT16[L] +#define RSCAN0TMPTR27LL RSCAN0.TMPTR27.UINT8[LL] +#define RSCAN0TMPTR27LH RSCAN0.TMPTR27.UINT8[LH] +#define RSCAN0TMPTR27H RSCAN0.TMPTR27.UINT16[H] +#define RSCAN0TMPTR27HL RSCAN0.TMPTR27.UINT8[HL] +#define RSCAN0TMPTR27HH RSCAN0.TMPTR27.UINT8[HH] +#define RSCAN0TMDF027 RSCAN0.TMDF027.UINT32 +#define RSCAN0TMDF027L RSCAN0.TMDF027.UINT16[L] +#define RSCAN0TMDF027LL RSCAN0.TMDF027.UINT8[LL] +#define RSCAN0TMDF027LH RSCAN0.TMDF027.UINT8[LH] +#define RSCAN0TMDF027H RSCAN0.TMDF027.UINT16[H] +#define RSCAN0TMDF027HL RSCAN0.TMDF027.UINT8[HL] +#define RSCAN0TMDF027HH RSCAN0.TMDF027.UINT8[HH] +#define RSCAN0TMDF127 RSCAN0.TMDF127.UINT32 +#define RSCAN0TMDF127L RSCAN0.TMDF127.UINT16[L] +#define RSCAN0TMDF127LL RSCAN0.TMDF127.UINT8[LL] +#define RSCAN0TMDF127LH RSCAN0.TMDF127.UINT8[LH] +#define RSCAN0TMDF127H RSCAN0.TMDF127.UINT16[H] +#define RSCAN0TMDF127HL RSCAN0.TMDF127.UINT8[HL] +#define RSCAN0TMDF127HH RSCAN0.TMDF127.UINT8[HH] +#define RSCAN0TMID28 RSCAN0.TMID28.UINT32 +#define RSCAN0TMID28L RSCAN0.TMID28.UINT16[L] +#define RSCAN0TMID28LL RSCAN0.TMID28.UINT8[LL] +#define RSCAN0TMID28LH RSCAN0.TMID28.UINT8[LH] +#define RSCAN0TMID28H RSCAN0.TMID28.UINT16[H] +#define RSCAN0TMID28HL RSCAN0.TMID28.UINT8[HL] +#define RSCAN0TMID28HH RSCAN0.TMID28.UINT8[HH] +#define RSCAN0TMPTR28 RSCAN0.TMPTR28.UINT32 +#define RSCAN0TMPTR28L RSCAN0.TMPTR28.UINT16[L] +#define RSCAN0TMPTR28LL RSCAN0.TMPTR28.UINT8[LL] +#define RSCAN0TMPTR28LH RSCAN0.TMPTR28.UINT8[LH] +#define RSCAN0TMPTR28H RSCAN0.TMPTR28.UINT16[H] +#define RSCAN0TMPTR28HL RSCAN0.TMPTR28.UINT8[HL] +#define RSCAN0TMPTR28HH RSCAN0.TMPTR28.UINT8[HH] +#define RSCAN0TMDF028 RSCAN0.TMDF028.UINT32 +#define RSCAN0TMDF028L RSCAN0.TMDF028.UINT16[L] +#define RSCAN0TMDF028LL RSCAN0.TMDF028.UINT8[LL] +#define RSCAN0TMDF028LH RSCAN0.TMDF028.UINT8[LH] +#define RSCAN0TMDF028H RSCAN0.TMDF028.UINT16[H] +#define RSCAN0TMDF028HL RSCAN0.TMDF028.UINT8[HL] +#define RSCAN0TMDF028HH RSCAN0.TMDF028.UINT8[HH] +#define RSCAN0TMDF128 RSCAN0.TMDF128.UINT32 +#define RSCAN0TMDF128L RSCAN0.TMDF128.UINT16[L] +#define RSCAN0TMDF128LL RSCAN0.TMDF128.UINT8[LL] +#define RSCAN0TMDF128LH RSCAN0.TMDF128.UINT8[LH] +#define RSCAN0TMDF128H RSCAN0.TMDF128.UINT16[H] +#define RSCAN0TMDF128HL RSCAN0.TMDF128.UINT8[HL] +#define RSCAN0TMDF128HH RSCAN0.TMDF128.UINT8[HH] +#define RSCAN0TMID29 RSCAN0.TMID29.UINT32 +#define RSCAN0TMID29L RSCAN0.TMID29.UINT16[L] +#define RSCAN0TMID29LL RSCAN0.TMID29.UINT8[LL] +#define RSCAN0TMID29LH RSCAN0.TMID29.UINT8[LH] +#define RSCAN0TMID29H RSCAN0.TMID29.UINT16[H] +#define RSCAN0TMID29HL RSCAN0.TMID29.UINT8[HL] +#define RSCAN0TMID29HH RSCAN0.TMID29.UINT8[HH] +#define RSCAN0TMPTR29 RSCAN0.TMPTR29.UINT32 +#define RSCAN0TMPTR29L RSCAN0.TMPTR29.UINT16[L] +#define RSCAN0TMPTR29LL RSCAN0.TMPTR29.UINT8[LL] +#define RSCAN0TMPTR29LH RSCAN0.TMPTR29.UINT8[LH] +#define RSCAN0TMPTR29H RSCAN0.TMPTR29.UINT16[H] +#define RSCAN0TMPTR29HL RSCAN0.TMPTR29.UINT8[HL] +#define RSCAN0TMPTR29HH RSCAN0.TMPTR29.UINT8[HH] +#define RSCAN0TMDF029 RSCAN0.TMDF029.UINT32 +#define RSCAN0TMDF029L RSCAN0.TMDF029.UINT16[L] +#define RSCAN0TMDF029LL RSCAN0.TMDF029.UINT8[LL] +#define RSCAN0TMDF029LH RSCAN0.TMDF029.UINT8[LH] +#define RSCAN0TMDF029H RSCAN0.TMDF029.UINT16[H] +#define RSCAN0TMDF029HL RSCAN0.TMDF029.UINT8[HL] +#define RSCAN0TMDF029HH RSCAN0.TMDF029.UINT8[HH] +#define RSCAN0TMDF129 RSCAN0.TMDF129.UINT32 +#define RSCAN0TMDF129L RSCAN0.TMDF129.UINT16[L] +#define RSCAN0TMDF129LL RSCAN0.TMDF129.UINT8[LL] +#define RSCAN0TMDF129LH RSCAN0.TMDF129.UINT8[LH] +#define RSCAN0TMDF129H RSCAN0.TMDF129.UINT16[H] +#define RSCAN0TMDF129HL RSCAN0.TMDF129.UINT8[HL] +#define RSCAN0TMDF129HH RSCAN0.TMDF129.UINT8[HH] +#define RSCAN0TMID30 RSCAN0.TMID30.UINT32 +#define RSCAN0TMID30L RSCAN0.TMID30.UINT16[L] +#define RSCAN0TMID30LL RSCAN0.TMID30.UINT8[LL] +#define RSCAN0TMID30LH RSCAN0.TMID30.UINT8[LH] +#define RSCAN0TMID30H RSCAN0.TMID30.UINT16[H] +#define RSCAN0TMID30HL RSCAN0.TMID30.UINT8[HL] +#define RSCAN0TMID30HH RSCAN0.TMID30.UINT8[HH] +#define RSCAN0TMPTR30 RSCAN0.TMPTR30.UINT32 +#define RSCAN0TMPTR30L RSCAN0.TMPTR30.UINT16[L] +#define RSCAN0TMPTR30LL RSCAN0.TMPTR30.UINT8[LL] +#define RSCAN0TMPTR30LH RSCAN0.TMPTR30.UINT8[LH] +#define RSCAN0TMPTR30H RSCAN0.TMPTR30.UINT16[H] +#define RSCAN0TMPTR30HL RSCAN0.TMPTR30.UINT8[HL] +#define RSCAN0TMPTR30HH RSCAN0.TMPTR30.UINT8[HH] +#define RSCAN0TMDF030 RSCAN0.TMDF030.UINT32 +#define RSCAN0TMDF030L RSCAN0.TMDF030.UINT16[L] +#define RSCAN0TMDF030LL RSCAN0.TMDF030.UINT8[LL] +#define RSCAN0TMDF030LH RSCAN0.TMDF030.UINT8[LH] +#define RSCAN0TMDF030H RSCAN0.TMDF030.UINT16[H] +#define RSCAN0TMDF030HL RSCAN0.TMDF030.UINT8[HL] +#define RSCAN0TMDF030HH RSCAN0.TMDF030.UINT8[HH] +#define RSCAN0TMDF130 RSCAN0.TMDF130.UINT32 +#define RSCAN0TMDF130L RSCAN0.TMDF130.UINT16[L] +#define RSCAN0TMDF130LL RSCAN0.TMDF130.UINT8[LL] +#define RSCAN0TMDF130LH RSCAN0.TMDF130.UINT8[LH] +#define RSCAN0TMDF130H RSCAN0.TMDF130.UINT16[H] +#define RSCAN0TMDF130HL RSCAN0.TMDF130.UINT8[HL] +#define RSCAN0TMDF130HH RSCAN0.TMDF130.UINT8[HH] +#define RSCAN0TMID31 RSCAN0.TMID31.UINT32 +#define RSCAN0TMID31L RSCAN0.TMID31.UINT16[L] +#define RSCAN0TMID31LL RSCAN0.TMID31.UINT8[LL] +#define RSCAN0TMID31LH RSCAN0.TMID31.UINT8[LH] +#define RSCAN0TMID31H RSCAN0.TMID31.UINT16[H] +#define RSCAN0TMID31HL RSCAN0.TMID31.UINT8[HL] +#define RSCAN0TMID31HH RSCAN0.TMID31.UINT8[HH] +#define RSCAN0TMPTR31 RSCAN0.TMPTR31.UINT32 +#define RSCAN0TMPTR31L RSCAN0.TMPTR31.UINT16[L] +#define RSCAN0TMPTR31LL RSCAN0.TMPTR31.UINT8[LL] +#define RSCAN0TMPTR31LH RSCAN0.TMPTR31.UINT8[LH] +#define RSCAN0TMPTR31H RSCAN0.TMPTR31.UINT16[H] +#define RSCAN0TMPTR31HL RSCAN0.TMPTR31.UINT8[HL] +#define RSCAN0TMPTR31HH RSCAN0.TMPTR31.UINT8[HH] +#define RSCAN0TMDF031 RSCAN0.TMDF031.UINT32 +#define RSCAN0TMDF031L RSCAN0.TMDF031.UINT16[L] +#define RSCAN0TMDF031LL RSCAN0.TMDF031.UINT8[LL] +#define RSCAN0TMDF031LH RSCAN0.TMDF031.UINT8[LH] +#define RSCAN0TMDF031H RSCAN0.TMDF031.UINT16[H] +#define RSCAN0TMDF031HL RSCAN0.TMDF031.UINT8[HL] +#define RSCAN0TMDF031HH RSCAN0.TMDF031.UINT8[HH] +#define RSCAN0TMDF131 RSCAN0.TMDF131.UINT32 +#define RSCAN0TMDF131L RSCAN0.TMDF131.UINT16[L] +#define RSCAN0TMDF131LL RSCAN0.TMDF131.UINT8[LL] +#define RSCAN0TMDF131LH RSCAN0.TMDF131.UINT8[LH] +#define RSCAN0TMDF131H RSCAN0.TMDF131.UINT16[H] +#define RSCAN0TMDF131HL RSCAN0.TMDF131.UINT8[HL] +#define RSCAN0TMDF131HH RSCAN0.TMDF131.UINT8[HH] +#define RSCAN0TMID32 RSCAN0.TMID32.UINT32 +#define RSCAN0TMID32L RSCAN0.TMID32.UINT16[L] +#define RSCAN0TMID32LL RSCAN0.TMID32.UINT8[LL] +#define RSCAN0TMID32LH RSCAN0.TMID32.UINT8[LH] +#define RSCAN0TMID32H RSCAN0.TMID32.UINT16[H] +#define RSCAN0TMID32HL RSCAN0.TMID32.UINT8[HL] +#define RSCAN0TMID32HH RSCAN0.TMID32.UINT8[HH] +#define RSCAN0TMPTR32 RSCAN0.TMPTR32.UINT32 +#define RSCAN0TMPTR32L RSCAN0.TMPTR32.UINT16[L] +#define RSCAN0TMPTR32LL RSCAN0.TMPTR32.UINT8[LL] +#define RSCAN0TMPTR32LH RSCAN0.TMPTR32.UINT8[LH] +#define RSCAN0TMPTR32H RSCAN0.TMPTR32.UINT16[H] +#define RSCAN0TMPTR32HL RSCAN0.TMPTR32.UINT8[HL] +#define RSCAN0TMPTR32HH RSCAN0.TMPTR32.UINT8[HH] +#define RSCAN0TMDF032 RSCAN0.TMDF032.UINT32 +#define RSCAN0TMDF032L RSCAN0.TMDF032.UINT16[L] +#define RSCAN0TMDF032LL RSCAN0.TMDF032.UINT8[LL] +#define RSCAN0TMDF032LH RSCAN0.TMDF032.UINT8[LH] +#define RSCAN0TMDF032H RSCAN0.TMDF032.UINT16[H] +#define RSCAN0TMDF032HL RSCAN0.TMDF032.UINT8[HL] +#define RSCAN0TMDF032HH RSCAN0.TMDF032.UINT8[HH] +#define RSCAN0TMDF132 RSCAN0.TMDF132.UINT32 +#define RSCAN0TMDF132L RSCAN0.TMDF132.UINT16[L] +#define RSCAN0TMDF132LL RSCAN0.TMDF132.UINT8[LL] +#define RSCAN0TMDF132LH RSCAN0.TMDF132.UINT8[LH] +#define RSCAN0TMDF132H RSCAN0.TMDF132.UINT16[H] +#define RSCAN0TMDF132HL RSCAN0.TMDF132.UINT8[HL] +#define RSCAN0TMDF132HH RSCAN0.TMDF132.UINT8[HH] +#define RSCAN0TMID33 RSCAN0.TMID33.UINT32 +#define RSCAN0TMID33L RSCAN0.TMID33.UINT16[L] +#define RSCAN0TMID33LL RSCAN0.TMID33.UINT8[LL] +#define RSCAN0TMID33LH RSCAN0.TMID33.UINT8[LH] +#define RSCAN0TMID33H RSCAN0.TMID33.UINT16[H] +#define RSCAN0TMID33HL RSCAN0.TMID33.UINT8[HL] +#define RSCAN0TMID33HH RSCAN0.TMID33.UINT8[HH] +#define RSCAN0TMPTR33 RSCAN0.TMPTR33.UINT32 +#define RSCAN0TMPTR33L RSCAN0.TMPTR33.UINT16[L] +#define RSCAN0TMPTR33LL RSCAN0.TMPTR33.UINT8[LL] +#define RSCAN0TMPTR33LH RSCAN0.TMPTR33.UINT8[LH] +#define RSCAN0TMPTR33H RSCAN0.TMPTR33.UINT16[H] +#define RSCAN0TMPTR33HL RSCAN0.TMPTR33.UINT8[HL] +#define RSCAN0TMPTR33HH RSCAN0.TMPTR33.UINT8[HH] +#define RSCAN0TMDF033 RSCAN0.TMDF033.UINT32 +#define RSCAN0TMDF033L RSCAN0.TMDF033.UINT16[L] +#define RSCAN0TMDF033LL RSCAN0.TMDF033.UINT8[LL] +#define RSCAN0TMDF033LH RSCAN0.TMDF033.UINT8[LH] +#define RSCAN0TMDF033H RSCAN0.TMDF033.UINT16[H] +#define RSCAN0TMDF033HL RSCAN0.TMDF033.UINT8[HL] +#define RSCAN0TMDF033HH RSCAN0.TMDF033.UINT8[HH] +#define RSCAN0TMDF133 RSCAN0.TMDF133.UINT32 +#define RSCAN0TMDF133L RSCAN0.TMDF133.UINT16[L] +#define RSCAN0TMDF133LL RSCAN0.TMDF133.UINT8[LL] +#define RSCAN0TMDF133LH RSCAN0.TMDF133.UINT8[LH] +#define RSCAN0TMDF133H RSCAN0.TMDF133.UINT16[H] +#define RSCAN0TMDF133HL RSCAN0.TMDF133.UINT8[HL] +#define RSCAN0TMDF133HH RSCAN0.TMDF133.UINT8[HH] +#define RSCAN0TMID34 RSCAN0.TMID34.UINT32 +#define RSCAN0TMID34L RSCAN0.TMID34.UINT16[L] +#define RSCAN0TMID34LL RSCAN0.TMID34.UINT8[LL] +#define RSCAN0TMID34LH RSCAN0.TMID34.UINT8[LH] +#define RSCAN0TMID34H RSCAN0.TMID34.UINT16[H] +#define RSCAN0TMID34HL RSCAN0.TMID34.UINT8[HL] +#define RSCAN0TMID34HH RSCAN0.TMID34.UINT8[HH] +#define RSCAN0TMPTR34 RSCAN0.TMPTR34.UINT32 +#define RSCAN0TMPTR34L RSCAN0.TMPTR34.UINT16[L] +#define RSCAN0TMPTR34LL RSCAN0.TMPTR34.UINT8[LL] +#define RSCAN0TMPTR34LH RSCAN0.TMPTR34.UINT8[LH] +#define RSCAN0TMPTR34H RSCAN0.TMPTR34.UINT16[H] +#define RSCAN0TMPTR34HL RSCAN0.TMPTR34.UINT8[HL] +#define RSCAN0TMPTR34HH RSCAN0.TMPTR34.UINT8[HH] +#define RSCAN0TMDF034 RSCAN0.TMDF034.UINT32 +#define RSCAN0TMDF034L RSCAN0.TMDF034.UINT16[L] +#define RSCAN0TMDF034LL RSCAN0.TMDF034.UINT8[LL] +#define RSCAN0TMDF034LH RSCAN0.TMDF034.UINT8[LH] +#define RSCAN0TMDF034H RSCAN0.TMDF034.UINT16[H] +#define RSCAN0TMDF034HL RSCAN0.TMDF034.UINT8[HL] +#define RSCAN0TMDF034HH RSCAN0.TMDF034.UINT8[HH] +#define RSCAN0TMDF134 RSCAN0.TMDF134.UINT32 +#define RSCAN0TMDF134L RSCAN0.TMDF134.UINT16[L] +#define RSCAN0TMDF134LL RSCAN0.TMDF134.UINT8[LL] +#define RSCAN0TMDF134LH RSCAN0.TMDF134.UINT8[LH] +#define RSCAN0TMDF134H RSCAN0.TMDF134.UINT16[H] +#define RSCAN0TMDF134HL RSCAN0.TMDF134.UINT8[HL] +#define RSCAN0TMDF134HH RSCAN0.TMDF134.UINT8[HH] +#define RSCAN0TMID35 RSCAN0.TMID35.UINT32 +#define RSCAN0TMID35L RSCAN0.TMID35.UINT16[L] +#define RSCAN0TMID35LL RSCAN0.TMID35.UINT8[LL] +#define RSCAN0TMID35LH RSCAN0.TMID35.UINT8[LH] +#define RSCAN0TMID35H RSCAN0.TMID35.UINT16[H] +#define RSCAN0TMID35HL RSCAN0.TMID35.UINT8[HL] +#define RSCAN0TMID35HH RSCAN0.TMID35.UINT8[HH] +#define RSCAN0TMPTR35 RSCAN0.TMPTR35.UINT32 +#define RSCAN0TMPTR35L RSCAN0.TMPTR35.UINT16[L] +#define RSCAN0TMPTR35LL RSCAN0.TMPTR35.UINT8[LL] +#define RSCAN0TMPTR35LH RSCAN0.TMPTR35.UINT8[LH] +#define RSCAN0TMPTR35H RSCAN0.TMPTR35.UINT16[H] +#define RSCAN0TMPTR35HL RSCAN0.TMPTR35.UINT8[HL] +#define RSCAN0TMPTR35HH RSCAN0.TMPTR35.UINT8[HH] +#define RSCAN0TMDF035 RSCAN0.TMDF035.UINT32 +#define RSCAN0TMDF035L RSCAN0.TMDF035.UINT16[L] +#define RSCAN0TMDF035LL RSCAN0.TMDF035.UINT8[LL] +#define RSCAN0TMDF035LH RSCAN0.TMDF035.UINT8[LH] +#define RSCAN0TMDF035H RSCAN0.TMDF035.UINT16[H] +#define RSCAN0TMDF035HL RSCAN0.TMDF035.UINT8[HL] +#define RSCAN0TMDF035HH RSCAN0.TMDF035.UINT8[HH] +#define RSCAN0TMDF135 RSCAN0.TMDF135.UINT32 +#define RSCAN0TMDF135L RSCAN0.TMDF135.UINT16[L] +#define RSCAN0TMDF135LL RSCAN0.TMDF135.UINT8[LL] +#define RSCAN0TMDF135LH RSCAN0.TMDF135.UINT8[LH] +#define RSCAN0TMDF135H RSCAN0.TMDF135.UINT16[H] +#define RSCAN0TMDF135HL RSCAN0.TMDF135.UINT8[HL] +#define RSCAN0TMDF135HH RSCAN0.TMDF135.UINT8[HH] +#define RSCAN0TMID36 RSCAN0.TMID36.UINT32 +#define RSCAN0TMID36L RSCAN0.TMID36.UINT16[L] +#define RSCAN0TMID36LL RSCAN0.TMID36.UINT8[LL] +#define RSCAN0TMID36LH RSCAN0.TMID36.UINT8[LH] +#define RSCAN0TMID36H RSCAN0.TMID36.UINT16[H] +#define RSCAN0TMID36HL RSCAN0.TMID36.UINT8[HL] +#define RSCAN0TMID36HH RSCAN0.TMID36.UINT8[HH] +#define RSCAN0TMPTR36 RSCAN0.TMPTR36.UINT32 +#define RSCAN0TMPTR36L RSCAN0.TMPTR36.UINT16[L] +#define RSCAN0TMPTR36LL RSCAN0.TMPTR36.UINT8[LL] +#define RSCAN0TMPTR36LH RSCAN0.TMPTR36.UINT8[LH] +#define RSCAN0TMPTR36H RSCAN0.TMPTR36.UINT16[H] +#define RSCAN0TMPTR36HL RSCAN0.TMPTR36.UINT8[HL] +#define RSCAN0TMPTR36HH RSCAN0.TMPTR36.UINT8[HH] +#define RSCAN0TMDF036 RSCAN0.TMDF036.UINT32 +#define RSCAN0TMDF036L RSCAN0.TMDF036.UINT16[L] +#define RSCAN0TMDF036LL RSCAN0.TMDF036.UINT8[LL] +#define RSCAN0TMDF036LH RSCAN0.TMDF036.UINT8[LH] +#define RSCAN0TMDF036H RSCAN0.TMDF036.UINT16[H] +#define RSCAN0TMDF036HL RSCAN0.TMDF036.UINT8[HL] +#define RSCAN0TMDF036HH RSCAN0.TMDF036.UINT8[HH] +#define RSCAN0TMDF136 RSCAN0.TMDF136.UINT32 +#define RSCAN0TMDF136L RSCAN0.TMDF136.UINT16[L] +#define RSCAN0TMDF136LL RSCAN0.TMDF136.UINT8[LL] +#define RSCAN0TMDF136LH RSCAN0.TMDF136.UINT8[LH] +#define RSCAN0TMDF136H RSCAN0.TMDF136.UINT16[H] +#define RSCAN0TMDF136HL RSCAN0.TMDF136.UINT8[HL] +#define RSCAN0TMDF136HH RSCAN0.TMDF136.UINT8[HH] +#define RSCAN0TMID37 RSCAN0.TMID37.UINT32 +#define RSCAN0TMID37L RSCAN0.TMID37.UINT16[L] +#define RSCAN0TMID37LL RSCAN0.TMID37.UINT8[LL] +#define RSCAN0TMID37LH RSCAN0.TMID37.UINT8[LH] +#define RSCAN0TMID37H RSCAN0.TMID37.UINT16[H] +#define RSCAN0TMID37HL RSCAN0.TMID37.UINT8[HL] +#define RSCAN0TMID37HH RSCAN0.TMID37.UINT8[HH] +#define RSCAN0TMPTR37 RSCAN0.TMPTR37.UINT32 +#define RSCAN0TMPTR37L RSCAN0.TMPTR37.UINT16[L] +#define RSCAN0TMPTR37LL RSCAN0.TMPTR37.UINT8[LL] +#define RSCAN0TMPTR37LH RSCAN0.TMPTR37.UINT8[LH] +#define RSCAN0TMPTR37H RSCAN0.TMPTR37.UINT16[H] +#define RSCAN0TMPTR37HL RSCAN0.TMPTR37.UINT8[HL] +#define RSCAN0TMPTR37HH RSCAN0.TMPTR37.UINT8[HH] +#define RSCAN0TMDF037 RSCAN0.TMDF037.UINT32 +#define RSCAN0TMDF037L RSCAN0.TMDF037.UINT16[L] +#define RSCAN0TMDF037LL RSCAN0.TMDF037.UINT8[LL] +#define RSCAN0TMDF037LH RSCAN0.TMDF037.UINT8[LH] +#define RSCAN0TMDF037H RSCAN0.TMDF037.UINT16[H] +#define RSCAN0TMDF037HL RSCAN0.TMDF037.UINT8[HL] +#define RSCAN0TMDF037HH RSCAN0.TMDF037.UINT8[HH] +#define RSCAN0TMDF137 RSCAN0.TMDF137.UINT32 +#define RSCAN0TMDF137L RSCAN0.TMDF137.UINT16[L] +#define RSCAN0TMDF137LL RSCAN0.TMDF137.UINT8[LL] +#define RSCAN0TMDF137LH RSCAN0.TMDF137.UINT8[LH] +#define RSCAN0TMDF137H RSCAN0.TMDF137.UINT16[H] +#define RSCAN0TMDF137HL RSCAN0.TMDF137.UINT8[HL] +#define RSCAN0TMDF137HH RSCAN0.TMDF137.UINT8[HH] +#define RSCAN0TMID38 RSCAN0.TMID38.UINT32 +#define RSCAN0TMID38L RSCAN0.TMID38.UINT16[L] +#define RSCAN0TMID38LL RSCAN0.TMID38.UINT8[LL] +#define RSCAN0TMID38LH RSCAN0.TMID38.UINT8[LH] +#define RSCAN0TMID38H RSCAN0.TMID38.UINT16[H] +#define RSCAN0TMID38HL RSCAN0.TMID38.UINT8[HL] +#define RSCAN0TMID38HH RSCAN0.TMID38.UINT8[HH] +#define RSCAN0TMPTR38 RSCAN0.TMPTR38.UINT32 +#define RSCAN0TMPTR38L RSCAN0.TMPTR38.UINT16[L] +#define RSCAN0TMPTR38LL RSCAN0.TMPTR38.UINT8[LL] +#define RSCAN0TMPTR38LH RSCAN0.TMPTR38.UINT8[LH] +#define RSCAN0TMPTR38H RSCAN0.TMPTR38.UINT16[H] +#define RSCAN0TMPTR38HL RSCAN0.TMPTR38.UINT8[HL] +#define RSCAN0TMPTR38HH RSCAN0.TMPTR38.UINT8[HH] +#define RSCAN0TMDF038 RSCAN0.TMDF038.UINT32 +#define RSCAN0TMDF038L RSCAN0.TMDF038.UINT16[L] +#define RSCAN0TMDF038LL RSCAN0.TMDF038.UINT8[LL] +#define RSCAN0TMDF038LH RSCAN0.TMDF038.UINT8[LH] +#define RSCAN0TMDF038H RSCAN0.TMDF038.UINT16[H] +#define RSCAN0TMDF038HL RSCAN0.TMDF038.UINT8[HL] +#define RSCAN0TMDF038HH RSCAN0.TMDF038.UINT8[HH] +#define RSCAN0TMDF138 RSCAN0.TMDF138.UINT32 +#define RSCAN0TMDF138L RSCAN0.TMDF138.UINT16[L] +#define RSCAN0TMDF138LL RSCAN0.TMDF138.UINT8[LL] +#define RSCAN0TMDF138LH RSCAN0.TMDF138.UINT8[LH] +#define RSCAN0TMDF138H RSCAN0.TMDF138.UINT16[H] +#define RSCAN0TMDF138HL RSCAN0.TMDF138.UINT8[HL] +#define RSCAN0TMDF138HH RSCAN0.TMDF138.UINT8[HH] +#define RSCAN0TMID39 RSCAN0.TMID39.UINT32 +#define RSCAN0TMID39L RSCAN0.TMID39.UINT16[L] +#define RSCAN0TMID39LL RSCAN0.TMID39.UINT8[LL] +#define RSCAN0TMID39LH RSCAN0.TMID39.UINT8[LH] +#define RSCAN0TMID39H RSCAN0.TMID39.UINT16[H] +#define RSCAN0TMID39HL RSCAN0.TMID39.UINT8[HL] +#define RSCAN0TMID39HH RSCAN0.TMID39.UINT8[HH] +#define RSCAN0TMPTR39 RSCAN0.TMPTR39.UINT32 +#define RSCAN0TMPTR39L RSCAN0.TMPTR39.UINT16[L] +#define RSCAN0TMPTR39LL RSCAN0.TMPTR39.UINT8[LL] +#define RSCAN0TMPTR39LH RSCAN0.TMPTR39.UINT8[LH] +#define RSCAN0TMPTR39H RSCAN0.TMPTR39.UINT16[H] +#define RSCAN0TMPTR39HL RSCAN0.TMPTR39.UINT8[HL] +#define RSCAN0TMPTR39HH RSCAN0.TMPTR39.UINT8[HH] +#define RSCAN0TMDF039 RSCAN0.TMDF039.UINT32 +#define RSCAN0TMDF039L RSCAN0.TMDF039.UINT16[L] +#define RSCAN0TMDF039LL RSCAN0.TMDF039.UINT8[LL] +#define RSCAN0TMDF039LH RSCAN0.TMDF039.UINT8[LH] +#define RSCAN0TMDF039H RSCAN0.TMDF039.UINT16[H] +#define RSCAN0TMDF039HL RSCAN0.TMDF039.UINT8[HL] +#define RSCAN0TMDF039HH RSCAN0.TMDF039.UINT8[HH] +#define RSCAN0TMDF139 RSCAN0.TMDF139.UINT32 +#define RSCAN0TMDF139L RSCAN0.TMDF139.UINT16[L] +#define RSCAN0TMDF139LL RSCAN0.TMDF139.UINT8[LL] +#define RSCAN0TMDF139LH RSCAN0.TMDF139.UINT8[LH] +#define RSCAN0TMDF139H RSCAN0.TMDF139.UINT16[H] +#define RSCAN0TMDF139HL RSCAN0.TMDF139.UINT8[HL] +#define RSCAN0TMDF139HH RSCAN0.TMDF139.UINT8[HH] +#define RSCAN0TMID40 RSCAN0.TMID40.UINT32 +#define RSCAN0TMID40L RSCAN0.TMID40.UINT16[L] +#define RSCAN0TMID40LL RSCAN0.TMID40.UINT8[LL] +#define RSCAN0TMID40LH RSCAN0.TMID40.UINT8[LH] +#define RSCAN0TMID40H RSCAN0.TMID40.UINT16[H] +#define RSCAN0TMID40HL RSCAN0.TMID40.UINT8[HL] +#define RSCAN0TMID40HH RSCAN0.TMID40.UINT8[HH] +#define RSCAN0TMPTR40 RSCAN0.TMPTR40.UINT32 +#define RSCAN0TMPTR40L RSCAN0.TMPTR40.UINT16[L] +#define RSCAN0TMPTR40LL RSCAN0.TMPTR40.UINT8[LL] +#define RSCAN0TMPTR40LH RSCAN0.TMPTR40.UINT8[LH] +#define RSCAN0TMPTR40H RSCAN0.TMPTR40.UINT16[H] +#define RSCAN0TMPTR40HL RSCAN0.TMPTR40.UINT8[HL] +#define RSCAN0TMPTR40HH RSCAN0.TMPTR40.UINT8[HH] +#define RSCAN0TMDF040 RSCAN0.TMDF040.UINT32 +#define RSCAN0TMDF040L RSCAN0.TMDF040.UINT16[L] +#define RSCAN0TMDF040LL RSCAN0.TMDF040.UINT8[LL] +#define RSCAN0TMDF040LH RSCAN0.TMDF040.UINT8[LH] +#define RSCAN0TMDF040H RSCAN0.TMDF040.UINT16[H] +#define RSCAN0TMDF040HL RSCAN0.TMDF040.UINT8[HL] +#define RSCAN0TMDF040HH RSCAN0.TMDF040.UINT8[HH] +#define RSCAN0TMDF140 RSCAN0.TMDF140.UINT32 +#define RSCAN0TMDF140L RSCAN0.TMDF140.UINT16[L] +#define RSCAN0TMDF140LL RSCAN0.TMDF140.UINT8[LL] +#define RSCAN0TMDF140LH RSCAN0.TMDF140.UINT8[LH] +#define RSCAN0TMDF140H RSCAN0.TMDF140.UINT16[H] +#define RSCAN0TMDF140HL RSCAN0.TMDF140.UINT8[HL] +#define RSCAN0TMDF140HH RSCAN0.TMDF140.UINT8[HH] +#define RSCAN0TMID41 RSCAN0.TMID41.UINT32 +#define RSCAN0TMID41L RSCAN0.TMID41.UINT16[L] +#define RSCAN0TMID41LL RSCAN0.TMID41.UINT8[LL] +#define RSCAN0TMID41LH RSCAN0.TMID41.UINT8[LH] +#define RSCAN0TMID41H RSCAN0.TMID41.UINT16[H] +#define RSCAN0TMID41HL RSCAN0.TMID41.UINT8[HL] +#define RSCAN0TMID41HH RSCAN0.TMID41.UINT8[HH] +#define RSCAN0TMPTR41 RSCAN0.TMPTR41.UINT32 +#define RSCAN0TMPTR41L RSCAN0.TMPTR41.UINT16[L] +#define RSCAN0TMPTR41LL RSCAN0.TMPTR41.UINT8[LL] +#define RSCAN0TMPTR41LH RSCAN0.TMPTR41.UINT8[LH] +#define RSCAN0TMPTR41H RSCAN0.TMPTR41.UINT16[H] +#define RSCAN0TMPTR41HL RSCAN0.TMPTR41.UINT8[HL] +#define RSCAN0TMPTR41HH RSCAN0.TMPTR41.UINT8[HH] +#define RSCAN0TMDF041 RSCAN0.TMDF041.UINT32 +#define RSCAN0TMDF041L RSCAN0.TMDF041.UINT16[L] +#define RSCAN0TMDF041LL RSCAN0.TMDF041.UINT8[LL] +#define RSCAN0TMDF041LH RSCAN0.TMDF041.UINT8[LH] +#define RSCAN0TMDF041H RSCAN0.TMDF041.UINT16[H] +#define RSCAN0TMDF041HL RSCAN0.TMDF041.UINT8[HL] +#define RSCAN0TMDF041HH RSCAN0.TMDF041.UINT8[HH] +#define RSCAN0TMDF141 RSCAN0.TMDF141.UINT32 +#define RSCAN0TMDF141L RSCAN0.TMDF141.UINT16[L] +#define RSCAN0TMDF141LL RSCAN0.TMDF141.UINT8[LL] +#define RSCAN0TMDF141LH RSCAN0.TMDF141.UINT8[LH] +#define RSCAN0TMDF141H RSCAN0.TMDF141.UINT16[H] +#define RSCAN0TMDF141HL RSCAN0.TMDF141.UINT8[HL] +#define RSCAN0TMDF141HH RSCAN0.TMDF141.UINT8[HH] +#define RSCAN0TMID42 RSCAN0.TMID42.UINT32 +#define RSCAN0TMID42L RSCAN0.TMID42.UINT16[L] +#define RSCAN0TMID42LL RSCAN0.TMID42.UINT8[LL] +#define RSCAN0TMID42LH RSCAN0.TMID42.UINT8[LH] +#define RSCAN0TMID42H RSCAN0.TMID42.UINT16[H] +#define RSCAN0TMID42HL RSCAN0.TMID42.UINT8[HL] +#define RSCAN0TMID42HH RSCAN0.TMID42.UINT8[HH] +#define RSCAN0TMPTR42 RSCAN0.TMPTR42.UINT32 +#define RSCAN0TMPTR42L RSCAN0.TMPTR42.UINT16[L] +#define RSCAN0TMPTR42LL RSCAN0.TMPTR42.UINT8[LL] +#define RSCAN0TMPTR42LH RSCAN0.TMPTR42.UINT8[LH] +#define RSCAN0TMPTR42H RSCAN0.TMPTR42.UINT16[H] +#define RSCAN0TMPTR42HL RSCAN0.TMPTR42.UINT8[HL] +#define RSCAN0TMPTR42HH RSCAN0.TMPTR42.UINT8[HH] +#define RSCAN0TMDF042 RSCAN0.TMDF042.UINT32 +#define RSCAN0TMDF042L RSCAN0.TMDF042.UINT16[L] +#define RSCAN0TMDF042LL RSCAN0.TMDF042.UINT8[LL] +#define RSCAN0TMDF042LH RSCAN0.TMDF042.UINT8[LH] +#define RSCAN0TMDF042H RSCAN0.TMDF042.UINT16[H] +#define RSCAN0TMDF042HL RSCAN0.TMDF042.UINT8[HL] +#define RSCAN0TMDF042HH RSCAN0.TMDF042.UINT8[HH] +#define RSCAN0TMDF142 RSCAN0.TMDF142.UINT32 +#define RSCAN0TMDF142L RSCAN0.TMDF142.UINT16[L] +#define RSCAN0TMDF142LL RSCAN0.TMDF142.UINT8[LL] +#define RSCAN0TMDF142LH RSCAN0.TMDF142.UINT8[LH] +#define RSCAN0TMDF142H RSCAN0.TMDF142.UINT16[H] +#define RSCAN0TMDF142HL RSCAN0.TMDF142.UINT8[HL] +#define RSCAN0TMDF142HH RSCAN0.TMDF142.UINT8[HH] +#define RSCAN0TMID43 RSCAN0.TMID43.UINT32 +#define RSCAN0TMID43L RSCAN0.TMID43.UINT16[L] +#define RSCAN0TMID43LL RSCAN0.TMID43.UINT8[LL] +#define RSCAN0TMID43LH RSCAN0.TMID43.UINT8[LH] +#define RSCAN0TMID43H RSCAN0.TMID43.UINT16[H] +#define RSCAN0TMID43HL RSCAN0.TMID43.UINT8[HL] +#define RSCAN0TMID43HH RSCAN0.TMID43.UINT8[HH] +#define RSCAN0TMPTR43 RSCAN0.TMPTR43.UINT32 +#define RSCAN0TMPTR43L RSCAN0.TMPTR43.UINT16[L] +#define RSCAN0TMPTR43LL RSCAN0.TMPTR43.UINT8[LL] +#define RSCAN0TMPTR43LH RSCAN0.TMPTR43.UINT8[LH] +#define RSCAN0TMPTR43H RSCAN0.TMPTR43.UINT16[H] +#define RSCAN0TMPTR43HL RSCAN0.TMPTR43.UINT8[HL] +#define RSCAN0TMPTR43HH RSCAN0.TMPTR43.UINT8[HH] +#define RSCAN0TMDF043 RSCAN0.TMDF043.UINT32 +#define RSCAN0TMDF043L RSCAN0.TMDF043.UINT16[L] +#define RSCAN0TMDF043LL RSCAN0.TMDF043.UINT8[LL] +#define RSCAN0TMDF043LH RSCAN0.TMDF043.UINT8[LH] +#define RSCAN0TMDF043H RSCAN0.TMDF043.UINT16[H] +#define RSCAN0TMDF043HL RSCAN0.TMDF043.UINT8[HL] +#define RSCAN0TMDF043HH RSCAN0.TMDF043.UINT8[HH] +#define RSCAN0TMDF143 RSCAN0.TMDF143.UINT32 +#define RSCAN0TMDF143L RSCAN0.TMDF143.UINT16[L] +#define RSCAN0TMDF143LL RSCAN0.TMDF143.UINT8[LL] +#define RSCAN0TMDF143LH RSCAN0.TMDF143.UINT8[LH] +#define RSCAN0TMDF143H RSCAN0.TMDF143.UINT16[H] +#define RSCAN0TMDF143HL RSCAN0.TMDF143.UINT8[HL] +#define RSCAN0TMDF143HH RSCAN0.TMDF143.UINT8[HH] +#define RSCAN0TMID44 RSCAN0.TMID44.UINT32 +#define RSCAN0TMID44L RSCAN0.TMID44.UINT16[L] +#define RSCAN0TMID44LL RSCAN0.TMID44.UINT8[LL] +#define RSCAN0TMID44LH RSCAN0.TMID44.UINT8[LH] +#define RSCAN0TMID44H RSCAN0.TMID44.UINT16[H] +#define RSCAN0TMID44HL RSCAN0.TMID44.UINT8[HL] +#define RSCAN0TMID44HH RSCAN0.TMID44.UINT8[HH] +#define RSCAN0TMPTR44 RSCAN0.TMPTR44.UINT32 +#define RSCAN0TMPTR44L RSCAN0.TMPTR44.UINT16[L] +#define RSCAN0TMPTR44LL RSCAN0.TMPTR44.UINT8[LL] +#define RSCAN0TMPTR44LH RSCAN0.TMPTR44.UINT8[LH] +#define RSCAN0TMPTR44H RSCAN0.TMPTR44.UINT16[H] +#define RSCAN0TMPTR44HL RSCAN0.TMPTR44.UINT8[HL] +#define RSCAN0TMPTR44HH RSCAN0.TMPTR44.UINT8[HH] +#define RSCAN0TMDF044 RSCAN0.TMDF044.UINT32 +#define RSCAN0TMDF044L RSCAN0.TMDF044.UINT16[L] +#define RSCAN0TMDF044LL RSCAN0.TMDF044.UINT8[LL] +#define RSCAN0TMDF044LH RSCAN0.TMDF044.UINT8[LH] +#define RSCAN0TMDF044H RSCAN0.TMDF044.UINT16[H] +#define RSCAN0TMDF044HL RSCAN0.TMDF044.UINT8[HL] +#define RSCAN0TMDF044HH RSCAN0.TMDF044.UINT8[HH] +#define RSCAN0TMDF144 RSCAN0.TMDF144.UINT32 +#define RSCAN0TMDF144L RSCAN0.TMDF144.UINT16[L] +#define RSCAN0TMDF144LL RSCAN0.TMDF144.UINT8[LL] +#define RSCAN0TMDF144LH RSCAN0.TMDF144.UINT8[LH] +#define RSCAN0TMDF144H RSCAN0.TMDF144.UINT16[H] +#define RSCAN0TMDF144HL RSCAN0.TMDF144.UINT8[HL] +#define RSCAN0TMDF144HH RSCAN0.TMDF144.UINT8[HH] +#define RSCAN0TMID45 RSCAN0.TMID45.UINT32 +#define RSCAN0TMID45L RSCAN0.TMID45.UINT16[L] +#define RSCAN0TMID45LL RSCAN0.TMID45.UINT8[LL] +#define RSCAN0TMID45LH RSCAN0.TMID45.UINT8[LH] +#define RSCAN0TMID45H RSCAN0.TMID45.UINT16[H] +#define RSCAN0TMID45HL RSCAN0.TMID45.UINT8[HL] +#define RSCAN0TMID45HH RSCAN0.TMID45.UINT8[HH] +#define RSCAN0TMPTR45 RSCAN0.TMPTR45.UINT32 +#define RSCAN0TMPTR45L RSCAN0.TMPTR45.UINT16[L] +#define RSCAN0TMPTR45LL RSCAN0.TMPTR45.UINT8[LL] +#define RSCAN0TMPTR45LH RSCAN0.TMPTR45.UINT8[LH] +#define RSCAN0TMPTR45H RSCAN0.TMPTR45.UINT16[H] +#define RSCAN0TMPTR45HL RSCAN0.TMPTR45.UINT8[HL] +#define RSCAN0TMPTR45HH RSCAN0.TMPTR45.UINT8[HH] +#define RSCAN0TMDF045 RSCAN0.TMDF045.UINT32 +#define RSCAN0TMDF045L RSCAN0.TMDF045.UINT16[L] +#define RSCAN0TMDF045LL RSCAN0.TMDF045.UINT8[LL] +#define RSCAN0TMDF045LH RSCAN0.TMDF045.UINT8[LH] +#define RSCAN0TMDF045H RSCAN0.TMDF045.UINT16[H] +#define RSCAN0TMDF045HL RSCAN0.TMDF045.UINT8[HL] +#define RSCAN0TMDF045HH RSCAN0.TMDF045.UINT8[HH] +#define RSCAN0TMDF145 RSCAN0.TMDF145.UINT32 +#define RSCAN0TMDF145L RSCAN0.TMDF145.UINT16[L] +#define RSCAN0TMDF145LL RSCAN0.TMDF145.UINT8[LL] +#define RSCAN0TMDF145LH RSCAN0.TMDF145.UINT8[LH] +#define RSCAN0TMDF145H RSCAN0.TMDF145.UINT16[H] +#define RSCAN0TMDF145HL RSCAN0.TMDF145.UINT8[HL] +#define RSCAN0TMDF145HH RSCAN0.TMDF145.UINT8[HH] +#define RSCAN0TMID46 RSCAN0.TMID46.UINT32 +#define RSCAN0TMID46L RSCAN0.TMID46.UINT16[L] +#define RSCAN0TMID46LL RSCAN0.TMID46.UINT8[LL] +#define RSCAN0TMID46LH RSCAN0.TMID46.UINT8[LH] +#define RSCAN0TMID46H RSCAN0.TMID46.UINT16[H] +#define RSCAN0TMID46HL RSCAN0.TMID46.UINT8[HL] +#define RSCAN0TMID46HH RSCAN0.TMID46.UINT8[HH] +#define RSCAN0TMPTR46 RSCAN0.TMPTR46.UINT32 +#define RSCAN0TMPTR46L RSCAN0.TMPTR46.UINT16[L] +#define RSCAN0TMPTR46LL RSCAN0.TMPTR46.UINT8[LL] +#define RSCAN0TMPTR46LH RSCAN0.TMPTR46.UINT8[LH] +#define RSCAN0TMPTR46H RSCAN0.TMPTR46.UINT16[H] +#define RSCAN0TMPTR46HL RSCAN0.TMPTR46.UINT8[HL] +#define RSCAN0TMPTR46HH RSCAN0.TMPTR46.UINT8[HH] +#define RSCAN0TMDF046 RSCAN0.TMDF046.UINT32 +#define RSCAN0TMDF046L RSCAN0.TMDF046.UINT16[L] +#define RSCAN0TMDF046LL RSCAN0.TMDF046.UINT8[LL] +#define RSCAN0TMDF046LH RSCAN0.TMDF046.UINT8[LH] +#define RSCAN0TMDF046H RSCAN0.TMDF046.UINT16[H] +#define RSCAN0TMDF046HL RSCAN0.TMDF046.UINT8[HL] +#define RSCAN0TMDF046HH RSCAN0.TMDF046.UINT8[HH] +#define RSCAN0TMDF146 RSCAN0.TMDF146.UINT32 +#define RSCAN0TMDF146L RSCAN0.TMDF146.UINT16[L] +#define RSCAN0TMDF146LL RSCAN0.TMDF146.UINT8[LL] +#define RSCAN0TMDF146LH RSCAN0.TMDF146.UINT8[LH] +#define RSCAN0TMDF146H RSCAN0.TMDF146.UINT16[H] +#define RSCAN0TMDF146HL RSCAN0.TMDF146.UINT8[HL] +#define RSCAN0TMDF146HH RSCAN0.TMDF146.UINT8[HH] +#define RSCAN0TMID47 RSCAN0.TMID47.UINT32 +#define RSCAN0TMID47L RSCAN0.TMID47.UINT16[L] +#define RSCAN0TMID47LL RSCAN0.TMID47.UINT8[LL] +#define RSCAN0TMID47LH RSCAN0.TMID47.UINT8[LH] +#define RSCAN0TMID47H RSCAN0.TMID47.UINT16[H] +#define RSCAN0TMID47HL RSCAN0.TMID47.UINT8[HL] +#define RSCAN0TMID47HH RSCAN0.TMID47.UINT8[HH] +#define RSCAN0TMPTR47 RSCAN0.TMPTR47.UINT32 +#define RSCAN0TMPTR47L RSCAN0.TMPTR47.UINT16[L] +#define RSCAN0TMPTR47LL RSCAN0.TMPTR47.UINT8[LL] +#define RSCAN0TMPTR47LH RSCAN0.TMPTR47.UINT8[LH] +#define RSCAN0TMPTR47H RSCAN0.TMPTR47.UINT16[H] +#define RSCAN0TMPTR47HL RSCAN0.TMPTR47.UINT8[HL] +#define RSCAN0TMPTR47HH RSCAN0.TMPTR47.UINT8[HH] +#define RSCAN0TMDF047 RSCAN0.TMDF047.UINT32 +#define RSCAN0TMDF047L RSCAN0.TMDF047.UINT16[L] +#define RSCAN0TMDF047LL RSCAN0.TMDF047.UINT8[LL] +#define RSCAN0TMDF047LH RSCAN0.TMDF047.UINT8[LH] +#define RSCAN0TMDF047H RSCAN0.TMDF047.UINT16[H] +#define RSCAN0TMDF047HL RSCAN0.TMDF047.UINT8[HL] +#define RSCAN0TMDF047HH RSCAN0.TMDF047.UINT8[HH] +#define RSCAN0TMDF147 RSCAN0.TMDF147.UINT32 +#define RSCAN0TMDF147L RSCAN0.TMDF147.UINT16[L] +#define RSCAN0TMDF147LL RSCAN0.TMDF147.UINT8[LL] +#define RSCAN0TMDF147LH RSCAN0.TMDF147.UINT8[LH] +#define RSCAN0TMDF147H RSCAN0.TMDF147.UINT16[H] +#define RSCAN0TMDF147HL RSCAN0.TMDF147.UINT8[HL] +#define RSCAN0TMDF147HH RSCAN0.TMDF147.UINT8[HH] +#define RSCAN0TMID48 RSCAN0.TMID48.UINT32 +#define RSCAN0TMID48L RSCAN0.TMID48.UINT16[L] +#define RSCAN0TMID48LL RSCAN0.TMID48.UINT8[LL] +#define RSCAN0TMID48LH RSCAN0.TMID48.UINT8[LH] +#define RSCAN0TMID48H RSCAN0.TMID48.UINT16[H] +#define RSCAN0TMID48HL RSCAN0.TMID48.UINT8[HL] +#define RSCAN0TMID48HH RSCAN0.TMID48.UINT8[HH] +#define RSCAN0TMPTR48 RSCAN0.TMPTR48.UINT32 +#define RSCAN0TMPTR48L RSCAN0.TMPTR48.UINT16[L] +#define RSCAN0TMPTR48LL RSCAN0.TMPTR48.UINT8[LL] +#define RSCAN0TMPTR48LH RSCAN0.TMPTR48.UINT8[LH] +#define RSCAN0TMPTR48H RSCAN0.TMPTR48.UINT16[H] +#define RSCAN0TMPTR48HL RSCAN0.TMPTR48.UINT8[HL] +#define RSCAN0TMPTR48HH RSCAN0.TMPTR48.UINT8[HH] +#define RSCAN0TMDF048 RSCAN0.TMDF048.UINT32 +#define RSCAN0TMDF048L RSCAN0.TMDF048.UINT16[L] +#define RSCAN0TMDF048LL RSCAN0.TMDF048.UINT8[LL] +#define RSCAN0TMDF048LH RSCAN0.TMDF048.UINT8[LH] +#define RSCAN0TMDF048H RSCAN0.TMDF048.UINT16[H] +#define RSCAN0TMDF048HL RSCAN0.TMDF048.UINT8[HL] +#define RSCAN0TMDF048HH RSCAN0.TMDF048.UINT8[HH] +#define RSCAN0TMDF148 RSCAN0.TMDF148.UINT32 +#define RSCAN0TMDF148L RSCAN0.TMDF148.UINT16[L] +#define RSCAN0TMDF148LL RSCAN0.TMDF148.UINT8[LL] +#define RSCAN0TMDF148LH RSCAN0.TMDF148.UINT8[LH] +#define RSCAN0TMDF148H RSCAN0.TMDF148.UINT16[H] +#define RSCAN0TMDF148HL RSCAN0.TMDF148.UINT8[HL] +#define RSCAN0TMDF148HH RSCAN0.TMDF148.UINT8[HH] +#define RSCAN0TMID49 RSCAN0.TMID49.UINT32 +#define RSCAN0TMID49L RSCAN0.TMID49.UINT16[L] +#define RSCAN0TMID49LL RSCAN0.TMID49.UINT8[LL] +#define RSCAN0TMID49LH RSCAN0.TMID49.UINT8[LH] +#define RSCAN0TMID49H RSCAN0.TMID49.UINT16[H] +#define RSCAN0TMID49HL RSCAN0.TMID49.UINT8[HL] +#define RSCAN0TMID49HH RSCAN0.TMID49.UINT8[HH] +#define RSCAN0TMPTR49 RSCAN0.TMPTR49.UINT32 +#define RSCAN0TMPTR49L RSCAN0.TMPTR49.UINT16[L] +#define RSCAN0TMPTR49LL RSCAN0.TMPTR49.UINT8[LL] +#define RSCAN0TMPTR49LH RSCAN0.TMPTR49.UINT8[LH] +#define RSCAN0TMPTR49H RSCAN0.TMPTR49.UINT16[H] +#define RSCAN0TMPTR49HL RSCAN0.TMPTR49.UINT8[HL] +#define RSCAN0TMPTR49HH RSCAN0.TMPTR49.UINT8[HH] +#define RSCAN0TMDF049 RSCAN0.TMDF049.UINT32 +#define RSCAN0TMDF049L RSCAN0.TMDF049.UINT16[L] +#define RSCAN0TMDF049LL RSCAN0.TMDF049.UINT8[LL] +#define RSCAN0TMDF049LH RSCAN0.TMDF049.UINT8[LH] +#define RSCAN0TMDF049H RSCAN0.TMDF049.UINT16[H] +#define RSCAN0TMDF049HL RSCAN0.TMDF049.UINT8[HL] +#define RSCAN0TMDF049HH RSCAN0.TMDF049.UINT8[HH] +#define RSCAN0TMDF149 RSCAN0.TMDF149.UINT32 +#define RSCAN0TMDF149L RSCAN0.TMDF149.UINT16[L] +#define RSCAN0TMDF149LL RSCAN0.TMDF149.UINT8[LL] +#define RSCAN0TMDF149LH RSCAN0.TMDF149.UINT8[LH] +#define RSCAN0TMDF149H RSCAN0.TMDF149.UINT16[H] +#define RSCAN0TMDF149HL RSCAN0.TMDF149.UINT8[HL] +#define RSCAN0TMDF149HH RSCAN0.TMDF149.UINT8[HH] +#define RSCAN0TMID50 RSCAN0.TMID50.UINT32 +#define RSCAN0TMID50L RSCAN0.TMID50.UINT16[L] +#define RSCAN0TMID50LL RSCAN0.TMID50.UINT8[LL] +#define RSCAN0TMID50LH RSCAN0.TMID50.UINT8[LH] +#define RSCAN0TMID50H RSCAN0.TMID50.UINT16[H] +#define RSCAN0TMID50HL RSCAN0.TMID50.UINT8[HL] +#define RSCAN0TMID50HH RSCAN0.TMID50.UINT8[HH] +#define RSCAN0TMPTR50 RSCAN0.TMPTR50.UINT32 +#define RSCAN0TMPTR50L RSCAN0.TMPTR50.UINT16[L] +#define RSCAN0TMPTR50LL RSCAN0.TMPTR50.UINT8[LL] +#define RSCAN0TMPTR50LH RSCAN0.TMPTR50.UINT8[LH] +#define RSCAN0TMPTR50H RSCAN0.TMPTR50.UINT16[H] +#define RSCAN0TMPTR50HL RSCAN0.TMPTR50.UINT8[HL] +#define RSCAN0TMPTR50HH RSCAN0.TMPTR50.UINT8[HH] +#define RSCAN0TMDF050 RSCAN0.TMDF050.UINT32 +#define RSCAN0TMDF050L RSCAN0.TMDF050.UINT16[L] +#define RSCAN0TMDF050LL RSCAN0.TMDF050.UINT8[LL] +#define RSCAN0TMDF050LH RSCAN0.TMDF050.UINT8[LH] +#define RSCAN0TMDF050H RSCAN0.TMDF050.UINT16[H] +#define RSCAN0TMDF050HL RSCAN0.TMDF050.UINT8[HL] +#define RSCAN0TMDF050HH RSCAN0.TMDF050.UINT8[HH] +#define RSCAN0TMDF150 RSCAN0.TMDF150.UINT32 +#define RSCAN0TMDF150L RSCAN0.TMDF150.UINT16[L] +#define RSCAN0TMDF150LL RSCAN0.TMDF150.UINT8[LL] +#define RSCAN0TMDF150LH RSCAN0.TMDF150.UINT8[LH] +#define RSCAN0TMDF150H RSCAN0.TMDF150.UINT16[H] +#define RSCAN0TMDF150HL RSCAN0.TMDF150.UINT8[HL] +#define RSCAN0TMDF150HH RSCAN0.TMDF150.UINT8[HH] +#define RSCAN0TMID51 RSCAN0.TMID51.UINT32 +#define RSCAN0TMID51L RSCAN0.TMID51.UINT16[L] +#define RSCAN0TMID51LL RSCAN0.TMID51.UINT8[LL] +#define RSCAN0TMID51LH RSCAN0.TMID51.UINT8[LH] +#define RSCAN0TMID51H RSCAN0.TMID51.UINT16[H] +#define RSCAN0TMID51HL RSCAN0.TMID51.UINT8[HL] +#define RSCAN0TMID51HH RSCAN0.TMID51.UINT8[HH] +#define RSCAN0TMPTR51 RSCAN0.TMPTR51.UINT32 +#define RSCAN0TMPTR51L RSCAN0.TMPTR51.UINT16[L] +#define RSCAN0TMPTR51LL RSCAN0.TMPTR51.UINT8[LL] +#define RSCAN0TMPTR51LH RSCAN0.TMPTR51.UINT8[LH] +#define RSCAN0TMPTR51H RSCAN0.TMPTR51.UINT16[H] +#define RSCAN0TMPTR51HL RSCAN0.TMPTR51.UINT8[HL] +#define RSCAN0TMPTR51HH RSCAN0.TMPTR51.UINT8[HH] +#define RSCAN0TMDF051 RSCAN0.TMDF051.UINT32 +#define RSCAN0TMDF051L RSCAN0.TMDF051.UINT16[L] +#define RSCAN0TMDF051LL RSCAN0.TMDF051.UINT8[LL] +#define RSCAN0TMDF051LH RSCAN0.TMDF051.UINT8[LH] +#define RSCAN0TMDF051H RSCAN0.TMDF051.UINT16[H] +#define RSCAN0TMDF051HL RSCAN0.TMDF051.UINT8[HL] +#define RSCAN0TMDF051HH RSCAN0.TMDF051.UINT8[HH] +#define RSCAN0TMDF151 RSCAN0.TMDF151.UINT32 +#define RSCAN0TMDF151L RSCAN0.TMDF151.UINT16[L] +#define RSCAN0TMDF151LL RSCAN0.TMDF151.UINT8[LL] +#define RSCAN0TMDF151LH RSCAN0.TMDF151.UINT8[LH] +#define RSCAN0TMDF151H RSCAN0.TMDF151.UINT16[H] +#define RSCAN0TMDF151HL RSCAN0.TMDF151.UINT8[HL] +#define RSCAN0TMDF151HH RSCAN0.TMDF151.UINT8[HH] +#define RSCAN0TMID52 RSCAN0.TMID52.UINT32 +#define RSCAN0TMID52L RSCAN0.TMID52.UINT16[L] +#define RSCAN0TMID52LL RSCAN0.TMID52.UINT8[LL] +#define RSCAN0TMID52LH RSCAN0.TMID52.UINT8[LH] +#define RSCAN0TMID52H RSCAN0.TMID52.UINT16[H] +#define RSCAN0TMID52HL RSCAN0.TMID52.UINT8[HL] +#define RSCAN0TMID52HH RSCAN0.TMID52.UINT8[HH] +#define RSCAN0TMPTR52 RSCAN0.TMPTR52.UINT32 +#define RSCAN0TMPTR52L RSCAN0.TMPTR52.UINT16[L] +#define RSCAN0TMPTR52LL RSCAN0.TMPTR52.UINT8[LL] +#define RSCAN0TMPTR52LH RSCAN0.TMPTR52.UINT8[LH] +#define RSCAN0TMPTR52H RSCAN0.TMPTR52.UINT16[H] +#define RSCAN0TMPTR52HL RSCAN0.TMPTR52.UINT8[HL] +#define RSCAN0TMPTR52HH RSCAN0.TMPTR52.UINT8[HH] +#define RSCAN0TMDF052 RSCAN0.TMDF052.UINT32 +#define RSCAN0TMDF052L RSCAN0.TMDF052.UINT16[L] +#define RSCAN0TMDF052LL RSCAN0.TMDF052.UINT8[LL] +#define RSCAN0TMDF052LH RSCAN0.TMDF052.UINT8[LH] +#define RSCAN0TMDF052H RSCAN0.TMDF052.UINT16[H] +#define RSCAN0TMDF052HL RSCAN0.TMDF052.UINT8[HL] +#define RSCAN0TMDF052HH RSCAN0.TMDF052.UINT8[HH] +#define RSCAN0TMDF152 RSCAN0.TMDF152.UINT32 +#define RSCAN0TMDF152L RSCAN0.TMDF152.UINT16[L] +#define RSCAN0TMDF152LL RSCAN0.TMDF152.UINT8[LL] +#define RSCAN0TMDF152LH RSCAN0.TMDF152.UINT8[LH] +#define RSCAN0TMDF152H RSCAN0.TMDF152.UINT16[H] +#define RSCAN0TMDF152HL RSCAN0.TMDF152.UINT8[HL] +#define RSCAN0TMDF152HH RSCAN0.TMDF152.UINT8[HH] +#define RSCAN0TMID53 RSCAN0.TMID53.UINT32 +#define RSCAN0TMID53L RSCAN0.TMID53.UINT16[L] +#define RSCAN0TMID53LL RSCAN0.TMID53.UINT8[LL] +#define RSCAN0TMID53LH RSCAN0.TMID53.UINT8[LH] +#define RSCAN0TMID53H RSCAN0.TMID53.UINT16[H] +#define RSCAN0TMID53HL RSCAN0.TMID53.UINT8[HL] +#define RSCAN0TMID53HH RSCAN0.TMID53.UINT8[HH] +#define RSCAN0TMPTR53 RSCAN0.TMPTR53.UINT32 +#define RSCAN0TMPTR53L RSCAN0.TMPTR53.UINT16[L] +#define RSCAN0TMPTR53LL RSCAN0.TMPTR53.UINT8[LL] +#define RSCAN0TMPTR53LH RSCAN0.TMPTR53.UINT8[LH] +#define RSCAN0TMPTR53H RSCAN0.TMPTR53.UINT16[H] +#define RSCAN0TMPTR53HL RSCAN0.TMPTR53.UINT8[HL] +#define RSCAN0TMPTR53HH RSCAN0.TMPTR53.UINT8[HH] +#define RSCAN0TMDF053 RSCAN0.TMDF053.UINT32 +#define RSCAN0TMDF053L RSCAN0.TMDF053.UINT16[L] +#define RSCAN0TMDF053LL RSCAN0.TMDF053.UINT8[LL] +#define RSCAN0TMDF053LH RSCAN0.TMDF053.UINT8[LH] +#define RSCAN0TMDF053H RSCAN0.TMDF053.UINT16[H] +#define RSCAN0TMDF053HL RSCAN0.TMDF053.UINT8[HL] +#define RSCAN0TMDF053HH RSCAN0.TMDF053.UINT8[HH] +#define RSCAN0TMDF153 RSCAN0.TMDF153.UINT32 +#define RSCAN0TMDF153L RSCAN0.TMDF153.UINT16[L] +#define RSCAN0TMDF153LL RSCAN0.TMDF153.UINT8[LL] +#define RSCAN0TMDF153LH RSCAN0.TMDF153.UINT8[LH] +#define RSCAN0TMDF153H RSCAN0.TMDF153.UINT16[H] +#define RSCAN0TMDF153HL RSCAN0.TMDF153.UINT8[HL] +#define RSCAN0TMDF153HH RSCAN0.TMDF153.UINT8[HH] +#define RSCAN0TMID54 RSCAN0.TMID54.UINT32 +#define RSCAN0TMID54L RSCAN0.TMID54.UINT16[L] +#define RSCAN0TMID54LL RSCAN0.TMID54.UINT8[LL] +#define RSCAN0TMID54LH RSCAN0.TMID54.UINT8[LH] +#define RSCAN0TMID54H RSCAN0.TMID54.UINT16[H] +#define RSCAN0TMID54HL RSCAN0.TMID54.UINT8[HL] +#define RSCAN0TMID54HH RSCAN0.TMID54.UINT8[HH] +#define RSCAN0TMPTR54 RSCAN0.TMPTR54.UINT32 +#define RSCAN0TMPTR54L RSCAN0.TMPTR54.UINT16[L] +#define RSCAN0TMPTR54LL RSCAN0.TMPTR54.UINT8[LL] +#define RSCAN0TMPTR54LH RSCAN0.TMPTR54.UINT8[LH] +#define RSCAN0TMPTR54H RSCAN0.TMPTR54.UINT16[H] +#define RSCAN0TMPTR54HL RSCAN0.TMPTR54.UINT8[HL] +#define RSCAN0TMPTR54HH RSCAN0.TMPTR54.UINT8[HH] +#define RSCAN0TMDF054 RSCAN0.TMDF054.UINT32 +#define RSCAN0TMDF054L RSCAN0.TMDF054.UINT16[L] +#define RSCAN0TMDF054LL RSCAN0.TMDF054.UINT8[LL] +#define RSCAN0TMDF054LH RSCAN0.TMDF054.UINT8[LH] +#define RSCAN0TMDF054H RSCAN0.TMDF054.UINT16[H] +#define RSCAN0TMDF054HL RSCAN0.TMDF054.UINT8[HL] +#define RSCAN0TMDF054HH RSCAN0.TMDF054.UINT8[HH] +#define RSCAN0TMDF154 RSCAN0.TMDF154.UINT32 +#define RSCAN0TMDF154L RSCAN0.TMDF154.UINT16[L] +#define RSCAN0TMDF154LL RSCAN0.TMDF154.UINT8[LL] +#define RSCAN0TMDF154LH RSCAN0.TMDF154.UINT8[LH] +#define RSCAN0TMDF154H RSCAN0.TMDF154.UINT16[H] +#define RSCAN0TMDF154HL RSCAN0.TMDF154.UINT8[HL] +#define RSCAN0TMDF154HH RSCAN0.TMDF154.UINT8[HH] +#define RSCAN0TMID55 RSCAN0.TMID55.UINT32 +#define RSCAN0TMID55L RSCAN0.TMID55.UINT16[L] +#define RSCAN0TMID55LL RSCAN0.TMID55.UINT8[LL] +#define RSCAN0TMID55LH RSCAN0.TMID55.UINT8[LH] +#define RSCAN0TMID55H RSCAN0.TMID55.UINT16[H] +#define RSCAN0TMID55HL RSCAN0.TMID55.UINT8[HL] +#define RSCAN0TMID55HH RSCAN0.TMID55.UINT8[HH] +#define RSCAN0TMPTR55 RSCAN0.TMPTR55.UINT32 +#define RSCAN0TMPTR55L RSCAN0.TMPTR55.UINT16[L] +#define RSCAN0TMPTR55LL RSCAN0.TMPTR55.UINT8[LL] +#define RSCAN0TMPTR55LH RSCAN0.TMPTR55.UINT8[LH] +#define RSCAN0TMPTR55H RSCAN0.TMPTR55.UINT16[H] +#define RSCAN0TMPTR55HL RSCAN0.TMPTR55.UINT8[HL] +#define RSCAN0TMPTR55HH RSCAN0.TMPTR55.UINT8[HH] +#define RSCAN0TMDF055 RSCAN0.TMDF055.UINT32 +#define RSCAN0TMDF055L RSCAN0.TMDF055.UINT16[L] +#define RSCAN0TMDF055LL RSCAN0.TMDF055.UINT8[LL] +#define RSCAN0TMDF055LH RSCAN0.TMDF055.UINT8[LH] +#define RSCAN0TMDF055H RSCAN0.TMDF055.UINT16[H] +#define RSCAN0TMDF055HL RSCAN0.TMDF055.UINT8[HL] +#define RSCAN0TMDF055HH RSCAN0.TMDF055.UINT8[HH] +#define RSCAN0TMDF155 RSCAN0.TMDF155.UINT32 +#define RSCAN0TMDF155L RSCAN0.TMDF155.UINT16[L] +#define RSCAN0TMDF155LL RSCAN0.TMDF155.UINT8[LL] +#define RSCAN0TMDF155LH RSCAN0.TMDF155.UINT8[LH] +#define RSCAN0TMDF155H RSCAN0.TMDF155.UINT16[H] +#define RSCAN0TMDF155HL RSCAN0.TMDF155.UINT8[HL] +#define RSCAN0TMDF155HH RSCAN0.TMDF155.UINT8[HH] +#define RSCAN0TMID56 RSCAN0.TMID56.UINT32 +#define RSCAN0TMID56L RSCAN0.TMID56.UINT16[L] +#define RSCAN0TMID56LL RSCAN0.TMID56.UINT8[LL] +#define RSCAN0TMID56LH RSCAN0.TMID56.UINT8[LH] +#define RSCAN0TMID56H RSCAN0.TMID56.UINT16[H] +#define RSCAN0TMID56HL RSCAN0.TMID56.UINT8[HL] +#define RSCAN0TMID56HH RSCAN0.TMID56.UINT8[HH] +#define RSCAN0TMPTR56 RSCAN0.TMPTR56.UINT32 +#define RSCAN0TMPTR56L RSCAN0.TMPTR56.UINT16[L] +#define RSCAN0TMPTR56LL RSCAN0.TMPTR56.UINT8[LL] +#define RSCAN0TMPTR56LH RSCAN0.TMPTR56.UINT8[LH] +#define RSCAN0TMPTR56H RSCAN0.TMPTR56.UINT16[H] +#define RSCAN0TMPTR56HL RSCAN0.TMPTR56.UINT8[HL] +#define RSCAN0TMPTR56HH RSCAN0.TMPTR56.UINT8[HH] +#define RSCAN0TMDF056 RSCAN0.TMDF056.UINT32 +#define RSCAN0TMDF056L RSCAN0.TMDF056.UINT16[L] +#define RSCAN0TMDF056LL RSCAN0.TMDF056.UINT8[LL] +#define RSCAN0TMDF056LH RSCAN0.TMDF056.UINT8[LH] +#define RSCAN0TMDF056H RSCAN0.TMDF056.UINT16[H] +#define RSCAN0TMDF056HL RSCAN0.TMDF056.UINT8[HL] +#define RSCAN0TMDF056HH RSCAN0.TMDF056.UINT8[HH] +#define RSCAN0TMDF156 RSCAN0.TMDF156.UINT32 +#define RSCAN0TMDF156L RSCAN0.TMDF156.UINT16[L] +#define RSCAN0TMDF156LL RSCAN0.TMDF156.UINT8[LL] +#define RSCAN0TMDF156LH RSCAN0.TMDF156.UINT8[LH] +#define RSCAN0TMDF156H RSCAN0.TMDF156.UINT16[H] +#define RSCAN0TMDF156HL RSCAN0.TMDF156.UINT8[HL] +#define RSCAN0TMDF156HH RSCAN0.TMDF156.UINT8[HH] +#define RSCAN0TMID57 RSCAN0.TMID57.UINT32 +#define RSCAN0TMID57L RSCAN0.TMID57.UINT16[L] +#define RSCAN0TMID57LL RSCAN0.TMID57.UINT8[LL] +#define RSCAN0TMID57LH RSCAN0.TMID57.UINT8[LH] +#define RSCAN0TMID57H RSCAN0.TMID57.UINT16[H] +#define RSCAN0TMID57HL RSCAN0.TMID57.UINT8[HL] +#define RSCAN0TMID57HH RSCAN0.TMID57.UINT8[HH] +#define RSCAN0TMPTR57 RSCAN0.TMPTR57.UINT32 +#define RSCAN0TMPTR57L RSCAN0.TMPTR57.UINT16[L] +#define RSCAN0TMPTR57LL RSCAN0.TMPTR57.UINT8[LL] +#define RSCAN0TMPTR57LH RSCAN0.TMPTR57.UINT8[LH] +#define RSCAN0TMPTR57H RSCAN0.TMPTR57.UINT16[H] +#define RSCAN0TMPTR57HL RSCAN0.TMPTR57.UINT8[HL] +#define RSCAN0TMPTR57HH RSCAN0.TMPTR57.UINT8[HH] +#define RSCAN0TMDF057 RSCAN0.TMDF057.UINT32 +#define RSCAN0TMDF057L RSCAN0.TMDF057.UINT16[L] +#define RSCAN0TMDF057LL RSCAN0.TMDF057.UINT8[LL] +#define RSCAN0TMDF057LH RSCAN0.TMDF057.UINT8[LH] +#define RSCAN0TMDF057H RSCAN0.TMDF057.UINT16[H] +#define RSCAN0TMDF057HL RSCAN0.TMDF057.UINT8[HL] +#define RSCAN0TMDF057HH RSCAN0.TMDF057.UINT8[HH] +#define RSCAN0TMDF157 RSCAN0.TMDF157.UINT32 +#define RSCAN0TMDF157L RSCAN0.TMDF157.UINT16[L] +#define RSCAN0TMDF157LL RSCAN0.TMDF157.UINT8[LL] +#define RSCAN0TMDF157LH RSCAN0.TMDF157.UINT8[LH] +#define RSCAN0TMDF157H RSCAN0.TMDF157.UINT16[H] +#define RSCAN0TMDF157HL RSCAN0.TMDF157.UINT8[HL] +#define RSCAN0TMDF157HH RSCAN0.TMDF157.UINT8[HH] +#define RSCAN0TMID58 RSCAN0.TMID58.UINT32 +#define RSCAN0TMID58L RSCAN0.TMID58.UINT16[L] +#define RSCAN0TMID58LL RSCAN0.TMID58.UINT8[LL] +#define RSCAN0TMID58LH RSCAN0.TMID58.UINT8[LH] +#define RSCAN0TMID58H RSCAN0.TMID58.UINT16[H] +#define RSCAN0TMID58HL RSCAN0.TMID58.UINT8[HL] +#define RSCAN0TMID58HH RSCAN0.TMID58.UINT8[HH] +#define RSCAN0TMPTR58 RSCAN0.TMPTR58.UINT32 +#define RSCAN0TMPTR58L RSCAN0.TMPTR58.UINT16[L] +#define RSCAN0TMPTR58LL RSCAN0.TMPTR58.UINT8[LL] +#define RSCAN0TMPTR58LH RSCAN0.TMPTR58.UINT8[LH] +#define RSCAN0TMPTR58H RSCAN0.TMPTR58.UINT16[H] +#define RSCAN0TMPTR58HL RSCAN0.TMPTR58.UINT8[HL] +#define RSCAN0TMPTR58HH RSCAN0.TMPTR58.UINT8[HH] +#define RSCAN0TMDF058 RSCAN0.TMDF058.UINT32 +#define RSCAN0TMDF058L RSCAN0.TMDF058.UINT16[L] +#define RSCAN0TMDF058LL RSCAN0.TMDF058.UINT8[LL] +#define RSCAN0TMDF058LH RSCAN0.TMDF058.UINT8[LH] +#define RSCAN0TMDF058H RSCAN0.TMDF058.UINT16[H] +#define RSCAN0TMDF058HL RSCAN0.TMDF058.UINT8[HL] +#define RSCAN0TMDF058HH RSCAN0.TMDF058.UINT8[HH] +#define RSCAN0TMDF158 RSCAN0.TMDF158.UINT32 +#define RSCAN0TMDF158L RSCAN0.TMDF158.UINT16[L] +#define RSCAN0TMDF158LL RSCAN0.TMDF158.UINT8[LL] +#define RSCAN0TMDF158LH RSCAN0.TMDF158.UINT8[LH] +#define RSCAN0TMDF158H RSCAN0.TMDF158.UINT16[H] +#define RSCAN0TMDF158HL RSCAN0.TMDF158.UINT8[HL] +#define RSCAN0TMDF158HH RSCAN0.TMDF158.UINT8[HH] +#define RSCAN0TMID59 RSCAN0.TMID59.UINT32 +#define RSCAN0TMID59L RSCAN0.TMID59.UINT16[L] +#define RSCAN0TMID59LL RSCAN0.TMID59.UINT8[LL] +#define RSCAN0TMID59LH RSCAN0.TMID59.UINT8[LH] +#define RSCAN0TMID59H RSCAN0.TMID59.UINT16[H] +#define RSCAN0TMID59HL RSCAN0.TMID59.UINT8[HL] +#define RSCAN0TMID59HH RSCAN0.TMID59.UINT8[HH] +#define RSCAN0TMPTR59 RSCAN0.TMPTR59.UINT32 +#define RSCAN0TMPTR59L RSCAN0.TMPTR59.UINT16[L] +#define RSCAN0TMPTR59LL RSCAN0.TMPTR59.UINT8[LL] +#define RSCAN0TMPTR59LH RSCAN0.TMPTR59.UINT8[LH] +#define RSCAN0TMPTR59H RSCAN0.TMPTR59.UINT16[H] +#define RSCAN0TMPTR59HL RSCAN0.TMPTR59.UINT8[HL] +#define RSCAN0TMPTR59HH RSCAN0.TMPTR59.UINT8[HH] +#define RSCAN0TMDF059 RSCAN0.TMDF059.UINT32 +#define RSCAN0TMDF059L RSCAN0.TMDF059.UINT16[L] +#define RSCAN0TMDF059LL RSCAN0.TMDF059.UINT8[LL] +#define RSCAN0TMDF059LH RSCAN0.TMDF059.UINT8[LH] +#define RSCAN0TMDF059H RSCAN0.TMDF059.UINT16[H] +#define RSCAN0TMDF059HL RSCAN0.TMDF059.UINT8[HL] +#define RSCAN0TMDF059HH RSCAN0.TMDF059.UINT8[HH] +#define RSCAN0TMDF159 RSCAN0.TMDF159.UINT32 +#define RSCAN0TMDF159L RSCAN0.TMDF159.UINT16[L] +#define RSCAN0TMDF159LL RSCAN0.TMDF159.UINT8[LL] +#define RSCAN0TMDF159LH RSCAN0.TMDF159.UINT8[LH] +#define RSCAN0TMDF159H RSCAN0.TMDF159.UINT16[H] +#define RSCAN0TMDF159HL RSCAN0.TMDF159.UINT8[HL] +#define RSCAN0TMDF159HH RSCAN0.TMDF159.UINT8[HH] +#define RSCAN0TMID60 RSCAN0.TMID60.UINT32 +#define RSCAN0TMID60L RSCAN0.TMID60.UINT16[L] +#define RSCAN0TMID60LL RSCAN0.TMID60.UINT8[LL] +#define RSCAN0TMID60LH RSCAN0.TMID60.UINT8[LH] +#define RSCAN0TMID60H RSCAN0.TMID60.UINT16[H] +#define RSCAN0TMID60HL RSCAN0.TMID60.UINT8[HL] +#define RSCAN0TMID60HH RSCAN0.TMID60.UINT8[HH] +#define RSCAN0TMPTR60 RSCAN0.TMPTR60.UINT32 +#define RSCAN0TMPTR60L RSCAN0.TMPTR60.UINT16[L] +#define RSCAN0TMPTR60LL RSCAN0.TMPTR60.UINT8[LL] +#define RSCAN0TMPTR60LH RSCAN0.TMPTR60.UINT8[LH] +#define RSCAN0TMPTR60H RSCAN0.TMPTR60.UINT16[H] +#define RSCAN0TMPTR60HL RSCAN0.TMPTR60.UINT8[HL] +#define RSCAN0TMPTR60HH RSCAN0.TMPTR60.UINT8[HH] +#define RSCAN0TMDF060 RSCAN0.TMDF060.UINT32 +#define RSCAN0TMDF060L RSCAN0.TMDF060.UINT16[L] +#define RSCAN0TMDF060LL RSCAN0.TMDF060.UINT8[LL] +#define RSCAN0TMDF060LH RSCAN0.TMDF060.UINT8[LH] +#define RSCAN0TMDF060H RSCAN0.TMDF060.UINT16[H] +#define RSCAN0TMDF060HL RSCAN0.TMDF060.UINT8[HL] +#define RSCAN0TMDF060HH RSCAN0.TMDF060.UINT8[HH] +#define RSCAN0TMDF160 RSCAN0.TMDF160.UINT32 +#define RSCAN0TMDF160L RSCAN0.TMDF160.UINT16[L] +#define RSCAN0TMDF160LL RSCAN0.TMDF160.UINT8[LL] +#define RSCAN0TMDF160LH RSCAN0.TMDF160.UINT8[LH] +#define RSCAN0TMDF160H RSCAN0.TMDF160.UINT16[H] +#define RSCAN0TMDF160HL RSCAN0.TMDF160.UINT8[HL] +#define RSCAN0TMDF160HH RSCAN0.TMDF160.UINT8[HH] +#define RSCAN0TMID61 RSCAN0.TMID61.UINT32 +#define RSCAN0TMID61L RSCAN0.TMID61.UINT16[L] +#define RSCAN0TMID61LL RSCAN0.TMID61.UINT8[LL] +#define RSCAN0TMID61LH RSCAN0.TMID61.UINT8[LH] +#define RSCAN0TMID61H RSCAN0.TMID61.UINT16[H] +#define RSCAN0TMID61HL RSCAN0.TMID61.UINT8[HL] +#define RSCAN0TMID61HH RSCAN0.TMID61.UINT8[HH] +#define RSCAN0TMPTR61 RSCAN0.TMPTR61.UINT32 +#define RSCAN0TMPTR61L RSCAN0.TMPTR61.UINT16[L] +#define RSCAN0TMPTR61LL RSCAN0.TMPTR61.UINT8[LL] +#define RSCAN0TMPTR61LH RSCAN0.TMPTR61.UINT8[LH] +#define RSCAN0TMPTR61H RSCAN0.TMPTR61.UINT16[H] +#define RSCAN0TMPTR61HL RSCAN0.TMPTR61.UINT8[HL] +#define RSCAN0TMPTR61HH RSCAN0.TMPTR61.UINT8[HH] +#define RSCAN0TMDF061 RSCAN0.TMDF061.UINT32 +#define RSCAN0TMDF061L RSCAN0.TMDF061.UINT16[L] +#define RSCAN0TMDF061LL RSCAN0.TMDF061.UINT8[LL] +#define RSCAN0TMDF061LH RSCAN0.TMDF061.UINT8[LH] +#define RSCAN0TMDF061H RSCAN0.TMDF061.UINT16[H] +#define RSCAN0TMDF061HL RSCAN0.TMDF061.UINT8[HL] +#define RSCAN0TMDF061HH RSCAN0.TMDF061.UINT8[HH] +#define RSCAN0TMDF161 RSCAN0.TMDF161.UINT32 +#define RSCAN0TMDF161L RSCAN0.TMDF161.UINT16[L] +#define RSCAN0TMDF161LL RSCAN0.TMDF161.UINT8[LL] +#define RSCAN0TMDF161LH RSCAN0.TMDF161.UINT8[LH] +#define RSCAN0TMDF161H RSCAN0.TMDF161.UINT16[H] +#define RSCAN0TMDF161HL RSCAN0.TMDF161.UINT8[HL] +#define RSCAN0TMDF161HH RSCAN0.TMDF161.UINT8[HH] +#define RSCAN0TMID62 RSCAN0.TMID62.UINT32 +#define RSCAN0TMID62L RSCAN0.TMID62.UINT16[L] +#define RSCAN0TMID62LL RSCAN0.TMID62.UINT8[LL] +#define RSCAN0TMID62LH RSCAN0.TMID62.UINT8[LH] +#define RSCAN0TMID62H RSCAN0.TMID62.UINT16[H] +#define RSCAN0TMID62HL RSCAN0.TMID62.UINT8[HL] +#define RSCAN0TMID62HH RSCAN0.TMID62.UINT8[HH] +#define RSCAN0TMPTR62 RSCAN0.TMPTR62.UINT32 +#define RSCAN0TMPTR62L RSCAN0.TMPTR62.UINT16[L] +#define RSCAN0TMPTR62LL RSCAN0.TMPTR62.UINT8[LL] +#define RSCAN0TMPTR62LH RSCAN0.TMPTR62.UINT8[LH] +#define RSCAN0TMPTR62H RSCAN0.TMPTR62.UINT16[H] +#define RSCAN0TMPTR62HL RSCAN0.TMPTR62.UINT8[HL] +#define RSCAN0TMPTR62HH RSCAN0.TMPTR62.UINT8[HH] +#define RSCAN0TMDF062 RSCAN0.TMDF062.UINT32 +#define RSCAN0TMDF062L RSCAN0.TMDF062.UINT16[L] +#define RSCAN0TMDF062LL RSCAN0.TMDF062.UINT8[LL] +#define RSCAN0TMDF062LH RSCAN0.TMDF062.UINT8[LH] +#define RSCAN0TMDF062H RSCAN0.TMDF062.UINT16[H] +#define RSCAN0TMDF062HL RSCAN0.TMDF062.UINT8[HL] +#define RSCAN0TMDF062HH RSCAN0.TMDF062.UINT8[HH] +#define RSCAN0TMDF162 RSCAN0.TMDF162.UINT32 +#define RSCAN0TMDF162L RSCAN0.TMDF162.UINT16[L] +#define RSCAN0TMDF162LL RSCAN0.TMDF162.UINT8[LL] +#define RSCAN0TMDF162LH RSCAN0.TMDF162.UINT8[LH] +#define RSCAN0TMDF162H RSCAN0.TMDF162.UINT16[H] +#define RSCAN0TMDF162HL RSCAN0.TMDF162.UINT8[HL] +#define RSCAN0TMDF162HH RSCAN0.TMDF162.UINT8[HH] +#define RSCAN0TMID63 RSCAN0.TMID63.UINT32 +#define RSCAN0TMID63L RSCAN0.TMID63.UINT16[L] +#define RSCAN0TMID63LL RSCAN0.TMID63.UINT8[LL] +#define RSCAN0TMID63LH RSCAN0.TMID63.UINT8[LH] +#define RSCAN0TMID63H RSCAN0.TMID63.UINT16[H] +#define RSCAN0TMID63HL RSCAN0.TMID63.UINT8[HL] +#define RSCAN0TMID63HH RSCAN0.TMID63.UINT8[HH] +#define RSCAN0TMPTR63 RSCAN0.TMPTR63.UINT32 +#define RSCAN0TMPTR63L RSCAN0.TMPTR63.UINT16[L] +#define RSCAN0TMPTR63LL RSCAN0.TMPTR63.UINT8[LL] +#define RSCAN0TMPTR63LH RSCAN0.TMPTR63.UINT8[LH] +#define RSCAN0TMPTR63H RSCAN0.TMPTR63.UINT16[H] +#define RSCAN0TMPTR63HL RSCAN0.TMPTR63.UINT8[HL] +#define RSCAN0TMPTR63HH RSCAN0.TMPTR63.UINT8[HH] +#define RSCAN0TMDF063 RSCAN0.TMDF063.UINT32 +#define RSCAN0TMDF063L RSCAN0.TMDF063.UINT16[L] +#define RSCAN0TMDF063LL RSCAN0.TMDF063.UINT8[LL] +#define RSCAN0TMDF063LH RSCAN0.TMDF063.UINT8[LH] +#define RSCAN0TMDF063H RSCAN0.TMDF063.UINT16[H] +#define RSCAN0TMDF063HL RSCAN0.TMDF063.UINT8[HL] +#define RSCAN0TMDF063HH RSCAN0.TMDF063.UINT8[HH] +#define RSCAN0TMDF163 RSCAN0.TMDF163.UINT32 +#define RSCAN0TMDF163L RSCAN0.TMDF163.UINT16[L] +#define RSCAN0TMDF163LL RSCAN0.TMDF163.UINT8[LL] +#define RSCAN0TMDF163LH RSCAN0.TMDF163.UINT8[LH] +#define RSCAN0TMDF163H RSCAN0.TMDF163.UINT16[H] +#define RSCAN0TMDF163HL RSCAN0.TMDF163.UINT8[HL] +#define RSCAN0TMDF163HH RSCAN0.TMDF163.UINT8[HH] +#define RSCAN0TMID64 RSCAN0.TMID64.UINT32 +#define RSCAN0TMID64L RSCAN0.TMID64.UINT16[L] +#define RSCAN0TMID64LL RSCAN0.TMID64.UINT8[LL] +#define RSCAN0TMID64LH RSCAN0.TMID64.UINT8[LH] +#define RSCAN0TMID64H RSCAN0.TMID64.UINT16[H] +#define RSCAN0TMID64HL RSCAN0.TMID64.UINT8[HL] +#define RSCAN0TMID64HH RSCAN0.TMID64.UINT8[HH] +#define RSCAN0TMPTR64 RSCAN0.TMPTR64.UINT32 +#define RSCAN0TMPTR64L RSCAN0.TMPTR64.UINT16[L] +#define RSCAN0TMPTR64LL RSCAN0.TMPTR64.UINT8[LL] +#define RSCAN0TMPTR64LH RSCAN0.TMPTR64.UINT8[LH] +#define RSCAN0TMPTR64H RSCAN0.TMPTR64.UINT16[H] +#define RSCAN0TMPTR64HL RSCAN0.TMPTR64.UINT8[HL] +#define RSCAN0TMPTR64HH RSCAN0.TMPTR64.UINT8[HH] +#define RSCAN0TMDF064 RSCAN0.TMDF064.UINT32 +#define RSCAN0TMDF064L RSCAN0.TMDF064.UINT16[L] +#define RSCAN0TMDF064LL RSCAN0.TMDF064.UINT8[LL] +#define RSCAN0TMDF064LH RSCAN0.TMDF064.UINT8[LH] +#define RSCAN0TMDF064H RSCAN0.TMDF064.UINT16[H] +#define RSCAN0TMDF064HL RSCAN0.TMDF064.UINT8[HL] +#define RSCAN0TMDF064HH RSCAN0.TMDF064.UINT8[HH] +#define RSCAN0TMDF164 RSCAN0.TMDF164.UINT32 +#define RSCAN0TMDF164L RSCAN0.TMDF164.UINT16[L] +#define RSCAN0TMDF164LL RSCAN0.TMDF164.UINT8[LL] +#define RSCAN0TMDF164LH RSCAN0.TMDF164.UINT8[LH] +#define RSCAN0TMDF164H RSCAN0.TMDF164.UINT16[H] +#define RSCAN0TMDF164HL RSCAN0.TMDF164.UINT8[HL] +#define RSCAN0TMDF164HH RSCAN0.TMDF164.UINT8[HH] +#define RSCAN0TMID65 RSCAN0.TMID65.UINT32 +#define RSCAN0TMID65L RSCAN0.TMID65.UINT16[L] +#define RSCAN0TMID65LL RSCAN0.TMID65.UINT8[LL] +#define RSCAN0TMID65LH RSCAN0.TMID65.UINT8[LH] +#define RSCAN0TMID65H RSCAN0.TMID65.UINT16[H] +#define RSCAN0TMID65HL RSCAN0.TMID65.UINT8[HL] +#define RSCAN0TMID65HH RSCAN0.TMID65.UINT8[HH] +#define RSCAN0TMPTR65 RSCAN0.TMPTR65.UINT32 +#define RSCAN0TMPTR65L RSCAN0.TMPTR65.UINT16[L] +#define RSCAN0TMPTR65LL RSCAN0.TMPTR65.UINT8[LL] +#define RSCAN0TMPTR65LH RSCAN0.TMPTR65.UINT8[LH] +#define RSCAN0TMPTR65H RSCAN0.TMPTR65.UINT16[H] +#define RSCAN0TMPTR65HL RSCAN0.TMPTR65.UINT8[HL] +#define RSCAN0TMPTR65HH RSCAN0.TMPTR65.UINT8[HH] +#define RSCAN0TMDF065 RSCAN0.TMDF065.UINT32 +#define RSCAN0TMDF065L RSCAN0.TMDF065.UINT16[L] +#define RSCAN0TMDF065LL RSCAN0.TMDF065.UINT8[LL] +#define RSCAN0TMDF065LH RSCAN0.TMDF065.UINT8[LH] +#define RSCAN0TMDF065H RSCAN0.TMDF065.UINT16[H] +#define RSCAN0TMDF065HL RSCAN0.TMDF065.UINT8[HL] +#define RSCAN0TMDF065HH RSCAN0.TMDF065.UINT8[HH] +#define RSCAN0TMDF165 RSCAN0.TMDF165.UINT32 +#define RSCAN0TMDF165L RSCAN0.TMDF165.UINT16[L] +#define RSCAN0TMDF165LL RSCAN0.TMDF165.UINT8[LL] +#define RSCAN0TMDF165LH RSCAN0.TMDF165.UINT8[LH] +#define RSCAN0TMDF165H RSCAN0.TMDF165.UINT16[H] +#define RSCAN0TMDF165HL RSCAN0.TMDF165.UINT8[HL] +#define RSCAN0TMDF165HH RSCAN0.TMDF165.UINT8[HH] +#define RSCAN0TMID66 RSCAN0.TMID66.UINT32 +#define RSCAN0TMID66L RSCAN0.TMID66.UINT16[L] +#define RSCAN0TMID66LL RSCAN0.TMID66.UINT8[LL] +#define RSCAN0TMID66LH RSCAN0.TMID66.UINT8[LH] +#define RSCAN0TMID66H RSCAN0.TMID66.UINT16[H] +#define RSCAN0TMID66HL RSCAN0.TMID66.UINT8[HL] +#define RSCAN0TMID66HH RSCAN0.TMID66.UINT8[HH] +#define RSCAN0TMPTR66 RSCAN0.TMPTR66.UINT32 +#define RSCAN0TMPTR66L RSCAN0.TMPTR66.UINT16[L] +#define RSCAN0TMPTR66LL RSCAN0.TMPTR66.UINT8[LL] +#define RSCAN0TMPTR66LH RSCAN0.TMPTR66.UINT8[LH] +#define RSCAN0TMPTR66H RSCAN0.TMPTR66.UINT16[H] +#define RSCAN0TMPTR66HL RSCAN0.TMPTR66.UINT8[HL] +#define RSCAN0TMPTR66HH RSCAN0.TMPTR66.UINT8[HH] +#define RSCAN0TMDF066 RSCAN0.TMDF066.UINT32 +#define RSCAN0TMDF066L RSCAN0.TMDF066.UINT16[L] +#define RSCAN0TMDF066LL RSCAN0.TMDF066.UINT8[LL] +#define RSCAN0TMDF066LH RSCAN0.TMDF066.UINT8[LH] +#define RSCAN0TMDF066H RSCAN0.TMDF066.UINT16[H] +#define RSCAN0TMDF066HL RSCAN0.TMDF066.UINT8[HL] +#define RSCAN0TMDF066HH RSCAN0.TMDF066.UINT8[HH] +#define RSCAN0TMDF166 RSCAN0.TMDF166.UINT32 +#define RSCAN0TMDF166L RSCAN0.TMDF166.UINT16[L] +#define RSCAN0TMDF166LL RSCAN0.TMDF166.UINT8[LL] +#define RSCAN0TMDF166LH RSCAN0.TMDF166.UINT8[LH] +#define RSCAN0TMDF166H RSCAN0.TMDF166.UINT16[H] +#define RSCAN0TMDF166HL RSCAN0.TMDF166.UINT8[HL] +#define RSCAN0TMDF166HH RSCAN0.TMDF166.UINT8[HH] +#define RSCAN0TMID67 RSCAN0.TMID67.UINT32 +#define RSCAN0TMID67L RSCAN0.TMID67.UINT16[L] +#define RSCAN0TMID67LL RSCAN0.TMID67.UINT8[LL] +#define RSCAN0TMID67LH RSCAN0.TMID67.UINT8[LH] +#define RSCAN0TMID67H RSCAN0.TMID67.UINT16[H] +#define RSCAN0TMID67HL RSCAN0.TMID67.UINT8[HL] +#define RSCAN0TMID67HH RSCAN0.TMID67.UINT8[HH] +#define RSCAN0TMPTR67 RSCAN0.TMPTR67.UINT32 +#define RSCAN0TMPTR67L RSCAN0.TMPTR67.UINT16[L] +#define RSCAN0TMPTR67LL RSCAN0.TMPTR67.UINT8[LL] +#define RSCAN0TMPTR67LH RSCAN0.TMPTR67.UINT8[LH] +#define RSCAN0TMPTR67H RSCAN0.TMPTR67.UINT16[H] +#define RSCAN0TMPTR67HL RSCAN0.TMPTR67.UINT8[HL] +#define RSCAN0TMPTR67HH RSCAN0.TMPTR67.UINT8[HH] +#define RSCAN0TMDF067 RSCAN0.TMDF067.UINT32 +#define RSCAN0TMDF067L RSCAN0.TMDF067.UINT16[L] +#define RSCAN0TMDF067LL RSCAN0.TMDF067.UINT8[LL] +#define RSCAN0TMDF067LH RSCAN0.TMDF067.UINT8[LH] +#define RSCAN0TMDF067H RSCAN0.TMDF067.UINT16[H] +#define RSCAN0TMDF067HL RSCAN0.TMDF067.UINT8[HL] +#define RSCAN0TMDF067HH RSCAN0.TMDF067.UINT8[HH] +#define RSCAN0TMDF167 RSCAN0.TMDF167.UINT32 +#define RSCAN0TMDF167L RSCAN0.TMDF167.UINT16[L] +#define RSCAN0TMDF167LL RSCAN0.TMDF167.UINT8[LL] +#define RSCAN0TMDF167LH RSCAN0.TMDF167.UINT8[LH] +#define RSCAN0TMDF167H RSCAN0.TMDF167.UINT16[H] +#define RSCAN0TMDF167HL RSCAN0.TMDF167.UINT8[HL] +#define RSCAN0TMDF167HH RSCAN0.TMDF167.UINT8[HH] +#define RSCAN0TMID68 RSCAN0.TMID68.UINT32 +#define RSCAN0TMID68L RSCAN0.TMID68.UINT16[L] +#define RSCAN0TMID68LL RSCAN0.TMID68.UINT8[LL] +#define RSCAN0TMID68LH RSCAN0.TMID68.UINT8[LH] +#define RSCAN0TMID68H RSCAN0.TMID68.UINT16[H] +#define RSCAN0TMID68HL RSCAN0.TMID68.UINT8[HL] +#define RSCAN0TMID68HH RSCAN0.TMID68.UINT8[HH] +#define RSCAN0TMPTR68 RSCAN0.TMPTR68.UINT32 +#define RSCAN0TMPTR68L RSCAN0.TMPTR68.UINT16[L] +#define RSCAN0TMPTR68LL RSCAN0.TMPTR68.UINT8[LL] +#define RSCAN0TMPTR68LH RSCAN0.TMPTR68.UINT8[LH] +#define RSCAN0TMPTR68H RSCAN0.TMPTR68.UINT16[H] +#define RSCAN0TMPTR68HL RSCAN0.TMPTR68.UINT8[HL] +#define RSCAN0TMPTR68HH RSCAN0.TMPTR68.UINT8[HH] +#define RSCAN0TMDF068 RSCAN0.TMDF068.UINT32 +#define RSCAN0TMDF068L RSCAN0.TMDF068.UINT16[L] +#define RSCAN0TMDF068LL RSCAN0.TMDF068.UINT8[LL] +#define RSCAN0TMDF068LH RSCAN0.TMDF068.UINT8[LH] +#define RSCAN0TMDF068H RSCAN0.TMDF068.UINT16[H] +#define RSCAN0TMDF068HL RSCAN0.TMDF068.UINT8[HL] +#define RSCAN0TMDF068HH RSCAN0.TMDF068.UINT8[HH] +#define RSCAN0TMDF168 RSCAN0.TMDF168.UINT32 +#define RSCAN0TMDF168L RSCAN0.TMDF168.UINT16[L] +#define RSCAN0TMDF168LL RSCAN0.TMDF168.UINT8[LL] +#define RSCAN0TMDF168LH RSCAN0.TMDF168.UINT8[LH] +#define RSCAN0TMDF168H RSCAN0.TMDF168.UINT16[H] +#define RSCAN0TMDF168HL RSCAN0.TMDF168.UINT8[HL] +#define RSCAN0TMDF168HH RSCAN0.TMDF168.UINT8[HH] +#define RSCAN0TMID69 RSCAN0.TMID69.UINT32 +#define RSCAN0TMID69L RSCAN0.TMID69.UINT16[L] +#define RSCAN0TMID69LL RSCAN0.TMID69.UINT8[LL] +#define RSCAN0TMID69LH RSCAN0.TMID69.UINT8[LH] +#define RSCAN0TMID69H RSCAN0.TMID69.UINT16[H] +#define RSCAN0TMID69HL RSCAN0.TMID69.UINT8[HL] +#define RSCAN0TMID69HH RSCAN0.TMID69.UINT8[HH] +#define RSCAN0TMPTR69 RSCAN0.TMPTR69.UINT32 +#define RSCAN0TMPTR69L RSCAN0.TMPTR69.UINT16[L] +#define RSCAN0TMPTR69LL RSCAN0.TMPTR69.UINT8[LL] +#define RSCAN0TMPTR69LH RSCAN0.TMPTR69.UINT8[LH] +#define RSCAN0TMPTR69H RSCAN0.TMPTR69.UINT16[H] +#define RSCAN0TMPTR69HL RSCAN0.TMPTR69.UINT8[HL] +#define RSCAN0TMPTR69HH RSCAN0.TMPTR69.UINT8[HH] +#define RSCAN0TMDF069 RSCAN0.TMDF069.UINT32 +#define RSCAN0TMDF069L RSCAN0.TMDF069.UINT16[L] +#define RSCAN0TMDF069LL RSCAN0.TMDF069.UINT8[LL] +#define RSCAN0TMDF069LH RSCAN0.TMDF069.UINT8[LH] +#define RSCAN0TMDF069H RSCAN0.TMDF069.UINT16[H] +#define RSCAN0TMDF069HL RSCAN0.TMDF069.UINT8[HL] +#define RSCAN0TMDF069HH RSCAN0.TMDF069.UINT8[HH] +#define RSCAN0TMDF169 RSCAN0.TMDF169.UINT32 +#define RSCAN0TMDF169L RSCAN0.TMDF169.UINT16[L] +#define RSCAN0TMDF169LL RSCAN0.TMDF169.UINT8[LL] +#define RSCAN0TMDF169LH RSCAN0.TMDF169.UINT8[LH] +#define RSCAN0TMDF169H RSCAN0.TMDF169.UINT16[H] +#define RSCAN0TMDF169HL RSCAN0.TMDF169.UINT8[HL] +#define RSCAN0TMDF169HH RSCAN0.TMDF169.UINT8[HH] +#define RSCAN0TMID70 RSCAN0.TMID70.UINT32 +#define RSCAN0TMID70L RSCAN0.TMID70.UINT16[L] +#define RSCAN0TMID70LL RSCAN0.TMID70.UINT8[LL] +#define RSCAN0TMID70LH RSCAN0.TMID70.UINT8[LH] +#define RSCAN0TMID70H RSCAN0.TMID70.UINT16[H] +#define RSCAN0TMID70HL RSCAN0.TMID70.UINT8[HL] +#define RSCAN0TMID70HH RSCAN0.TMID70.UINT8[HH] +#define RSCAN0TMPTR70 RSCAN0.TMPTR70.UINT32 +#define RSCAN0TMPTR70L RSCAN0.TMPTR70.UINT16[L] +#define RSCAN0TMPTR70LL RSCAN0.TMPTR70.UINT8[LL] +#define RSCAN0TMPTR70LH RSCAN0.TMPTR70.UINT8[LH] +#define RSCAN0TMPTR70H RSCAN0.TMPTR70.UINT16[H] +#define RSCAN0TMPTR70HL RSCAN0.TMPTR70.UINT8[HL] +#define RSCAN0TMPTR70HH RSCAN0.TMPTR70.UINT8[HH] +#define RSCAN0TMDF070 RSCAN0.TMDF070.UINT32 +#define RSCAN0TMDF070L RSCAN0.TMDF070.UINT16[L] +#define RSCAN0TMDF070LL RSCAN0.TMDF070.UINT8[LL] +#define RSCAN0TMDF070LH RSCAN0.TMDF070.UINT8[LH] +#define RSCAN0TMDF070H RSCAN0.TMDF070.UINT16[H] +#define RSCAN0TMDF070HL RSCAN0.TMDF070.UINT8[HL] +#define RSCAN0TMDF070HH RSCAN0.TMDF070.UINT8[HH] +#define RSCAN0TMDF170 RSCAN0.TMDF170.UINT32 +#define RSCAN0TMDF170L RSCAN0.TMDF170.UINT16[L] +#define RSCAN0TMDF170LL RSCAN0.TMDF170.UINT8[LL] +#define RSCAN0TMDF170LH RSCAN0.TMDF170.UINT8[LH] +#define RSCAN0TMDF170H RSCAN0.TMDF170.UINT16[H] +#define RSCAN0TMDF170HL RSCAN0.TMDF170.UINT8[HL] +#define RSCAN0TMDF170HH RSCAN0.TMDF170.UINT8[HH] +#define RSCAN0TMID71 RSCAN0.TMID71.UINT32 +#define RSCAN0TMID71L RSCAN0.TMID71.UINT16[L] +#define RSCAN0TMID71LL RSCAN0.TMID71.UINT8[LL] +#define RSCAN0TMID71LH RSCAN0.TMID71.UINT8[LH] +#define RSCAN0TMID71H RSCAN0.TMID71.UINT16[H] +#define RSCAN0TMID71HL RSCAN0.TMID71.UINT8[HL] +#define RSCAN0TMID71HH RSCAN0.TMID71.UINT8[HH] +#define RSCAN0TMPTR71 RSCAN0.TMPTR71.UINT32 +#define RSCAN0TMPTR71L RSCAN0.TMPTR71.UINT16[L] +#define RSCAN0TMPTR71LL RSCAN0.TMPTR71.UINT8[LL] +#define RSCAN0TMPTR71LH RSCAN0.TMPTR71.UINT8[LH] +#define RSCAN0TMPTR71H RSCAN0.TMPTR71.UINT16[H] +#define RSCAN0TMPTR71HL RSCAN0.TMPTR71.UINT8[HL] +#define RSCAN0TMPTR71HH RSCAN0.TMPTR71.UINT8[HH] +#define RSCAN0TMDF071 RSCAN0.TMDF071.UINT32 +#define RSCAN0TMDF071L RSCAN0.TMDF071.UINT16[L] +#define RSCAN0TMDF071LL RSCAN0.TMDF071.UINT8[LL] +#define RSCAN0TMDF071LH RSCAN0.TMDF071.UINT8[LH] +#define RSCAN0TMDF071H RSCAN0.TMDF071.UINT16[H] +#define RSCAN0TMDF071HL RSCAN0.TMDF071.UINT8[HL] +#define RSCAN0TMDF071HH RSCAN0.TMDF071.UINT8[HH] +#define RSCAN0TMDF171 RSCAN0.TMDF171.UINT32 +#define RSCAN0TMDF171L RSCAN0.TMDF171.UINT16[L] +#define RSCAN0TMDF171LL RSCAN0.TMDF171.UINT8[LL] +#define RSCAN0TMDF171LH RSCAN0.TMDF171.UINT8[LH] +#define RSCAN0TMDF171H RSCAN0.TMDF171.UINT16[H] +#define RSCAN0TMDF171HL RSCAN0.TMDF171.UINT8[HL] +#define RSCAN0TMDF171HH RSCAN0.TMDF171.UINT8[HH] +#define RSCAN0TMID72 RSCAN0.TMID72.UINT32 +#define RSCAN0TMID72L RSCAN0.TMID72.UINT16[L] +#define RSCAN0TMID72LL RSCAN0.TMID72.UINT8[LL] +#define RSCAN0TMID72LH RSCAN0.TMID72.UINT8[LH] +#define RSCAN0TMID72H RSCAN0.TMID72.UINT16[H] +#define RSCAN0TMID72HL RSCAN0.TMID72.UINT8[HL] +#define RSCAN0TMID72HH RSCAN0.TMID72.UINT8[HH] +#define RSCAN0TMPTR72 RSCAN0.TMPTR72.UINT32 +#define RSCAN0TMPTR72L RSCAN0.TMPTR72.UINT16[L] +#define RSCAN0TMPTR72LL RSCAN0.TMPTR72.UINT8[LL] +#define RSCAN0TMPTR72LH RSCAN0.TMPTR72.UINT8[LH] +#define RSCAN0TMPTR72H RSCAN0.TMPTR72.UINT16[H] +#define RSCAN0TMPTR72HL RSCAN0.TMPTR72.UINT8[HL] +#define RSCAN0TMPTR72HH RSCAN0.TMPTR72.UINT8[HH] +#define RSCAN0TMDF072 RSCAN0.TMDF072.UINT32 +#define RSCAN0TMDF072L RSCAN0.TMDF072.UINT16[L] +#define RSCAN0TMDF072LL RSCAN0.TMDF072.UINT8[LL] +#define RSCAN0TMDF072LH RSCAN0.TMDF072.UINT8[LH] +#define RSCAN0TMDF072H RSCAN0.TMDF072.UINT16[H] +#define RSCAN0TMDF072HL RSCAN0.TMDF072.UINT8[HL] +#define RSCAN0TMDF072HH RSCAN0.TMDF072.UINT8[HH] +#define RSCAN0TMDF172 RSCAN0.TMDF172.UINT32 +#define RSCAN0TMDF172L RSCAN0.TMDF172.UINT16[L] +#define RSCAN0TMDF172LL RSCAN0.TMDF172.UINT8[LL] +#define RSCAN0TMDF172LH RSCAN0.TMDF172.UINT8[LH] +#define RSCAN0TMDF172H RSCAN0.TMDF172.UINT16[H] +#define RSCAN0TMDF172HL RSCAN0.TMDF172.UINT8[HL] +#define RSCAN0TMDF172HH RSCAN0.TMDF172.UINT8[HH] +#define RSCAN0TMID73 RSCAN0.TMID73.UINT32 +#define RSCAN0TMID73L RSCAN0.TMID73.UINT16[L] +#define RSCAN0TMID73LL RSCAN0.TMID73.UINT8[LL] +#define RSCAN0TMID73LH RSCAN0.TMID73.UINT8[LH] +#define RSCAN0TMID73H RSCAN0.TMID73.UINT16[H] +#define RSCAN0TMID73HL RSCAN0.TMID73.UINT8[HL] +#define RSCAN0TMID73HH RSCAN0.TMID73.UINT8[HH] +#define RSCAN0TMPTR73 RSCAN0.TMPTR73.UINT32 +#define RSCAN0TMPTR73L RSCAN0.TMPTR73.UINT16[L] +#define RSCAN0TMPTR73LL RSCAN0.TMPTR73.UINT8[LL] +#define RSCAN0TMPTR73LH RSCAN0.TMPTR73.UINT8[LH] +#define RSCAN0TMPTR73H RSCAN0.TMPTR73.UINT16[H] +#define RSCAN0TMPTR73HL RSCAN0.TMPTR73.UINT8[HL] +#define RSCAN0TMPTR73HH RSCAN0.TMPTR73.UINT8[HH] +#define RSCAN0TMDF073 RSCAN0.TMDF073.UINT32 +#define RSCAN0TMDF073L RSCAN0.TMDF073.UINT16[L] +#define RSCAN0TMDF073LL RSCAN0.TMDF073.UINT8[LL] +#define RSCAN0TMDF073LH RSCAN0.TMDF073.UINT8[LH] +#define RSCAN0TMDF073H RSCAN0.TMDF073.UINT16[H] +#define RSCAN0TMDF073HL RSCAN0.TMDF073.UINT8[HL] +#define RSCAN0TMDF073HH RSCAN0.TMDF073.UINT8[HH] +#define RSCAN0TMDF173 RSCAN0.TMDF173.UINT32 +#define RSCAN0TMDF173L RSCAN0.TMDF173.UINT16[L] +#define RSCAN0TMDF173LL RSCAN0.TMDF173.UINT8[LL] +#define RSCAN0TMDF173LH RSCAN0.TMDF173.UINT8[LH] +#define RSCAN0TMDF173H RSCAN0.TMDF173.UINT16[H] +#define RSCAN0TMDF173HL RSCAN0.TMDF173.UINT8[HL] +#define RSCAN0TMDF173HH RSCAN0.TMDF173.UINT8[HH] +#define RSCAN0TMID74 RSCAN0.TMID74.UINT32 +#define RSCAN0TMID74L RSCAN0.TMID74.UINT16[L] +#define RSCAN0TMID74LL RSCAN0.TMID74.UINT8[LL] +#define RSCAN0TMID74LH RSCAN0.TMID74.UINT8[LH] +#define RSCAN0TMID74H RSCAN0.TMID74.UINT16[H] +#define RSCAN0TMID74HL RSCAN0.TMID74.UINT8[HL] +#define RSCAN0TMID74HH RSCAN0.TMID74.UINT8[HH] +#define RSCAN0TMPTR74 RSCAN0.TMPTR74.UINT32 +#define RSCAN0TMPTR74L RSCAN0.TMPTR74.UINT16[L] +#define RSCAN0TMPTR74LL RSCAN0.TMPTR74.UINT8[LL] +#define RSCAN0TMPTR74LH RSCAN0.TMPTR74.UINT8[LH] +#define RSCAN0TMPTR74H RSCAN0.TMPTR74.UINT16[H] +#define RSCAN0TMPTR74HL RSCAN0.TMPTR74.UINT8[HL] +#define RSCAN0TMPTR74HH RSCAN0.TMPTR74.UINT8[HH] +#define RSCAN0TMDF074 RSCAN0.TMDF074.UINT32 +#define RSCAN0TMDF074L RSCAN0.TMDF074.UINT16[L] +#define RSCAN0TMDF074LL RSCAN0.TMDF074.UINT8[LL] +#define RSCAN0TMDF074LH RSCAN0.TMDF074.UINT8[LH] +#define RSCAN0TMDF074H RSCAN0.TMDF074.UINT16[H] +#define RSCAN0TMDF074HL RSCAN0.TMDF074.UINT8[HL] +#define RSCAN0TMDF074HH RSCAN0.TMDF074.UINT8[HH] +#define RSCAN0TMDF174 RSCAN0.TMDF174.UINT32 +#define RSCAN0TMDF174L RSCAN0.TMDF174.UINT16[L] +#define RSCAN0TMDF174LL RSCAN0.TMDF174.UINT8[LL] +#define RSCAN0TMDF174LH RSCAN0.TMDF174.UINT8[LH] +#define RSCAN0TMDF174H RSCAN0.TMDF174.UINT16[H] +#define RSCAN0TMDF174HL RSCAN0.TMDF174.UINT8[HL] +#define RSCAN0TMDF174HH RSCAN0.TMDF174.UINT8[HH] +#define RSCAN0TMID75 RSCAN0.TMID75.UINT32 +#define RSCAN0TMID75L RSCAN0.TMID75.UINT16[L] +#define RSCAN0TMID75LL RSCAN0.TMID75.UINT8[LL] +#define RSCAN0TMID75LH RSCAN0.TMID75.UINT8[LH] +#define RSCAN0TMID75H RSCAN0.TMID75.UINT16[H] +#define RSCAN0TMID75HL RSCAN0.TMID75.UINT8[HL] +#define RSCAN0TMID75HH RSCAN0.TMID75.UINT8[HH] +#define RSCAN0TMPTR75 RSCAN0.TMPTR75.UINT32 +#define RSCAN0TMPTR75L RSCAN0.TMPTR75.UINT16[L] +#define RSCAN0TMPTR75LL RSCAN0.TMPTR75.UINT8[LL] +#define RSCAN0TMPTR75LH RSCAN0.TMPTR75.UINT8[LH] +#define RSCAN0TMPTR75H RSCAN0.TMPTR75.UINT16[H] +#define RSCAN0TMPTR75HL RSCAN0.TMPTR75.UINT8[HL] +#define RSCAN0TMPTR75HH RSCAN0.TMPTR75.UINT8[HH] +#define RSCAN0TMDF075 RSCAN0.TMDF075.UINT32 +#define RSCAN0TMDF075L RSCAN0.TMDF075.UINT16[L] +#define RSCAN0TMDF075LL RSCAN0.TMDF075.UINT8[LL] +#define RSCAN0TMDF075LH RSCAN0.TMDF075.UINT8[LH] +#define RSCAN0TMDF075H RSCAN0.TMDF075.UINT16[H] +#define RSCAN0TMDF075HL RSCAN0.TMDF075.UINT8[HL] +#define RSCAN0TMDF075HH RSCAN0.TMDF075.UINT8[HH] +#define RSCAN0TMDF175 RSCAN0.TMDF175.UINT32 +#define RSCAN0TMDF175L RSCAN0.TMDF175.UINT16[L] +#define RSCAN0TMDF175LL RSCAN0.TMDF175.UINT8[LL] +#define RSCAN0TMDF175LH RSCAN0.TMDF175.UINT8[LH] +#define RSCAN0TMDF175H RSCAN0.TMDF175.UINT16[H] +#define RSCAN0TMDF175HL RSCAN0.TMDF175.UINT8[HL] +#define RSCAN0TMDF175HH RSCAN0.TMDF175.UINT8[HH] +#define RSCAN0TMID76 RSCAN0.TMID76.UINT32 +#define RSCAN0TMID76L RSCAN0.TMID76.UINT16[L] +#define RSCAN0TMID76LL RSCAN0.TMID76.UINT8[LL] +#define RSCAN0TMID76LH RSCAN0.TMID76.UINT8[LH] +#define RSCAN0TMID76H RSCAN0.TMID76.UINT16[H] +#define RSCAN0TMID76HL RSCAN0.TMID76.UINT8[HL] +#define RSCAN0TMID76HH RSCAN0.TMID76.UINT8[HH] +#define RSCAN0TMPTR76 RSCAN0.TMPTR76.UINT32 +#define RSCAN0TMPTR76L RSCAN0.TMPTR76.UINT16[L] +#define RSCAN0TMPTR76LL RSCAN0.TMPTR76.UINT8[LL] +#define RSCAN0TMPTR76LH RSCAN0.TMPTR76.UINT8[LH] +#define RSCAN0TMPTR76H RSCAN0.TMPTR76.UINT16[H] +#define RSCAN0TMPTR76HL RSCAN0.TMPTR76.UINT8[HL] +#define RSCAN0TMPTR76HH RSCAN0.TMPTR76.UINT8[HH] +#define RSCAN0TMDF076 RSCAN0.TMDF076.UINT32 +#define RSCAN0TMDF076L RSCAN0.TMDF076.UINT16[L] +#define RSCAN0TMDF076LL RSCAN0.TMDF076.UINT8[LL] +#define RSCAN0TMDF076LH RSCAN0.TMDF076.UINT8[LH] +#define RSCAN0TMDF076H RSCAN0.TMDF076.UINT16[H] +#define RSCAN0TMDF076HL RSCAN0.TMDF076.UINT8[HL] +#define RSCAN0TMDF076HH RSCAN0.TMDF076.UINT8[HH] +#define RSCAN0TMDF176 RSCAN0.TMDF176.UINT32 +#define RSCAN0TMDF176L RSCAN0.TMDF176.UINT16[L] +#define RSCAN0TMDF176LL RSCAN0.TMDF176.UINT8[LL] +#define RSCAN0TMDF176LH RSCAN0.TMDF176.UINT8[LH] +#define RSCAN0TMDF176H RSCAN0.TMDF176.UINT16[H] +#define RSCAN0TMDF176HL RSCAN0.TMDF176.UINT8[HL] +#define RSCAN0TMDF176HH RSCAN0.TMDF176.UINT8[HH] +#define RSCAN0TMID77 RSCAN0.TMID77.UINT32 +#define RSCAN0TMID77L RSCAN0.TMID77.UINT16[L] +#define RSCAN0TMID77LL RSCAN0.TMID77.UINT8[LL] +#define RSCAN0TMID77LH RSCAN0.TMID77.UINT8[LH] +#define RSCAN0TMID77H RSCAN0.TMID77.UINT16[H] +#define RSCAN0TMID77HL RSCAN0.TMID77.UINT8[HL] +#define RSCAN0TMID77HH RSCAN0.TMID77.UINT8[HH] +#define RSCAN0TMPTR77 RSCAN0.TMPTR77.UINT32 +#define RSCAN0TMPTR77L RSCAN0.TMPTR77.UINT16[L] +#define RSCAN0TMPTR77LL RSCAN0.TMPTR77.UINT8[LL] +#define RSCAN0TMPTR77LH RSCAN0.TMPTR77.UINT8[LH] +#define RSCAN0TMPTR77H RSCAN0.TMPTR77.UINT16[H] +#define RSCAN0TMPTR77HL RSCAN0.TMPTR77.UINT8[HL] +#define RSCAN0TMPTR77HH RSCAN0.TMPTR77.UINT8[HH] +#define RSCAN0TMDF077 RSCAN0.TMDF077.UINT32 +#define RSCAN0TMDF077L RSCAN0.TMDF077.UINT16[L] +#define RSCAN0TMDF077LL RSCAN0.TMDF077.UINT8[LL] +#define RSCAN0TMDF077LH RSCAN0.TMDF077.UINT8[LH] +#define RSCAN0TMDF077H RSCAN0.TMDF077.UINT16[H] +#define RSCAN0TMDF077HL RSCAN0.TMDF077.UINT8[HL] +#define RSCAN0TMDF077HH RSCAN0.TMDF077.UINT8[HH] +#define RSCAN0TMDF177 RSCAN0.TMDF177.UINT32 +#define RSCAN0TMDF177L RSCAN0.TMDF177.UINT16[L] +#define RSCAN0TMDF177LL RSCAN0.TMDF177.UINT8[LL] +#define RSCAN0TMDF177LH RSCAN0.TMDF177.UINT8[LH] +#define RSCAN0TMDF177H RSCAN0.TMDF177.UINT16[H] +#define RSCAN0TMDF177HL RSCAN0.TMDF177.UINT8[HL] +#define RSCAN0TMDF177HH RSCAN0.TMDF177.UINT8[HH] +#define RSCAN0TMID78 RSCAN0.TMID78.UINT32 +#define RSCAN0TMID78L RSCAN0.TMID78.UINT16[L] +#define RSCAN0TMID78LL RSCAN0.TMID78.UINT8[LL] +#define RSCAN0TMID78LH RSCAN0.TMID78.UINT8[LH] +#define RSCAN0TMID78H RSCAN0.TMID78.UINT16[H] +#define RSCAN0TMID78HL RSCAN0.TMID78.UINT8[HL] +#define RSCAN0TMID78HH RSCAN0.TMID78.UINT8[HH] +#define RSCAN0TMPTR78 RSCAN0.TMPTR78.UINT32 +#define RSCAN0TMPTR78L RSCAN0.TMPTR78.UINT16[L] +#define RSCAN0TMPTR78LL RSCAN0.TMPTR78.UINT8[LL] +#define RSCAN0TMPTR78LH RSCAN0.TMPTR78.UINT8[LH] +#define RSCAN0TMPTR78H RSCAN0.TMPTR78.UINT16[H] +#define RSCAN0TMPTR78HL RSCAN0.TMPTR78.UINT8[HL] +#define RSCAN0TMPTR78HH RSCAN0.TMPTR78.UINT8[HH] +#define RSCAN0TMDF078 RSCAN0.TMDF078.UINT32 +#define RSCAN0TMDF078L RSCAN0.TMDF078.UINT16[L] +#define RSCAN0TMDF078LL RSCAN0.TMDF078.UINT8[LL] +#define RSCAN0TMDF078LH RSCAN0.TMDF078.UINT8[LH] +#define RSCAN0TMDF078H RSCAN0.TMDF078.UINT16[H] +#define RSCAN0TMDF078HL RSCAN0.TMDF078.UINT8[HL] +#define RSCAN0TMDF078HH RSCAN0.TMDF078.UINT8[HH] +#define RSCAN0TMDF178 RSCAN0.TMDF178.UINT32 +#define RSCAN0TMDF178L RSCAN0.TMDF178.UINT16[L] +#define RSCAN0TMDF178LL RSCAN0.TMDF178.UINT8[LL] +#define RSCAN0TMDF178LH RSCAN0.TMDF178.UINT8[LH] +#define RSCAN0TMDF178H RSCAN0.TMDF178.UINT16[H] +#define RSCAN0TMDF178HL RSCAN0.TMDF178.UINT8[HL] +#define RSCAN0TMDF178HH RSCAN0.TMDF178.UINT8[HH] +#define RSCAN0TMID79 RSCAN0.TMID79.UINT32 +#define RSCAN0TMID79L RSCAN0.TMID79.UINT16[L] +#define RSCAN0TMID79LL RSCAN0.TMID79.UINT8[LL] +#define RSCAN0TMID79LH RSCAN0.TMID79.UINT8[LH] +#define RSCAN0TMID79H RSCAN0.TMID79.UINT16[H] +#define RSCAN0TMID79HL RSCAN0.TMID79.UINT8[HL] +#define RSCAN0TMID79HH RSCAN0.TMID79.UINT8[HH] +#define RSCAN0TMPTR79 RSCAN0.TMPTR79.UINT32 +#define RSCAN0TMPTR79L RSCAN0.TMPTR79.UINT16[L] +#define RSCAN0TMPTR79LL RSCAN0.TMPTR79.UINT8[LL] +#define RSCAN0TMPTR79LH RSCAN0.TMPTR79.UINT8[LH] +#define RSCAN0TMPTR79H RSCAN0.TMPTR79.UINT16[H] +#define RSCAN0TMPTR79HL RSCAN0.TMPTR79.UINT8[HL] +#define RSCAN0TMPTR79HH RSCAN0.TMPTR79.UINT8[HH] +#define RSCAN0TMDF079 RSCAN0.TMDF079.UINT32 +#define RSCAN0TMDF079L RSCAN0.TMDF079.UINT16[L] +#define RSCAN0TMDF079LL RSCAN0.TMDF079.UINT8[LL] +#define RSCAN0TMDF079LH RSCAN0.TMDF079.UINT8[LH] +#define RSCAN0TMDF079H RSCAN0.TMDF079.UINT16[H] +#define RSCAN0TMDF079HL RSCAN0.TMDF079.UINT8[HL] +#define RSCAN0TMDF079HH RSCAN0.TMDF079.UINT8[HH] +#define RSCAN0TMDF179 RSCAN0.TMDF179.UINT32 +#define RSCAN0TMDF179L RSCAN0.TMDF179.UINT16[L] +#define RSCAN0TMDF179LL RSCAN0.TMDF179.UINT8[LL] +#define RSCAN0TMDF179LH RSCAN0.TMDF179.UINT8[LH] +#define RSCAN0TMDF179H RSCAN0.TMDF179.UINT16[H] +#define RSCAN0TMDF179HL RSCAN0.TMDF179.UINT8[HL] +#define RSCAN0TMDF179HH RSCAN0.TMDF179.UINT8[HH] +#define RSCAN0THLACC0 RSCAN0.THLACC0.UINT32 +#define RSCAN0THLACC0L RSCAN0.THLACC0.UINT16[L] +#define RSCAN0THLACC0LL RSCAN0.THLACC0.UINT8[LL] +#define RSCAN0THLACC0LH RSCAN0.THLACC0.UINT8[LH] +#define RSCAN0THLACC0H RSCAN0.THLACC0.UINT16[H] +#define RSCAN0THLACC0HL RSCAN0.THLACC0.UINT8[HL] +#define RSCAN0THLACC0HH RSCAN0.THLACC0.UINT8[HH] +#define RSCAN0THLACC1 RSCAN0.THLACC1.UINT32 +#define RSCAN0THLACC1L RSCAN0.THLACC1.UINT16[L] +#define RSCAN0THLACC1LL RSCAN0.THLACC1.UINT8[LL] +#define RSCAN0THLACC1LH RSCAN0.THLACC1.UINT8[LH] +#define RSCAN0THLACC1H RSCAN0.THLACC1.UINT16[H] +#define RSCAN0THLACC1HL RSCAN0.THLACC1.UINT8[HL] +#define RSCAN0THLACC1HH RSCAN0.THLACC1.UINT8[HH] +#define RSCAN0THLACC2 RSCAN0.THLACC2.UINT32 +#define RSCAN0THLACC2L RSCAN0.THLACC2.UINT16[L] +#define RSCAN0THLACC2LL RSCAN0.THLACC2.UINT8[LL] +#define RSCAN0THLACC2LH RSCAN0.THLACC2.UINT8[LH] +#define RSCAN0THLACC2H RSCAN0.THLACC2.UINT16[H] +#define RSCAN0THLACC2HL RSCAN0.THLACC2.UINT8[HL] +#define RSCAN0THLACC2HH RSCAN0.THLACC2.UINT8[HH] +#define RSCAN0THLACC3 RSCAN0.THLACC3.UINT32 +#define RSCAN0THLACC3L RSCAN0.THLACC3.UINT16[L] +#define RSCAN0THLACC3LL RSCAN0.THLACC3.UINT8[LL] +#define RSCAN0THLACC3LH RSCAN0.THLACC3.UINT8[LH] +#define RSCAN0THLACC3H RSCAN0.THLACC3.UINT16[H] +#define RSCAN0THLACC3HL RSCAN0.THLACC3.UINT8[HL] +#define RSCAN0THLACC3HH RSCAN0.THLACC3.UINT8[HH] +#define RSCAN0THLACC4 RSCAN0.THLACC4.UINT32 +#define RSCAN0THLACC4L RSCAN0.THLACC4.UINT16[L] +#define RSCAN0THLACC4LL RSCAN0.THLACC4.UINT8[LL] +#define RSCAN0THLACC4LH RSCAN0.THLACC4.UINT8[LH] +#define RSCAN0THLACC4H RSCAN0.THLACC4.UINT16[H] +#define RSCAN0THLACC4HL RSCAN0.THLACC4.UINT8[HL] +#define RSCAN0THLACC4HH RSCAN0.THLACC4.UINT8[HH] +/* <-SEC M1.10.1 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/rspi_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,204 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : rspi_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef RSPI_IODEFINE_H +#define RSPI_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +#include "reg32_t.h" + +struct st_rspi +{ /* RSPI */ + volatile uint8_t SPCR; /* SPCR */ + volatile uint8_t SSLP; /* SSLP */ + volatile uint8_t SPPCR; /* SPPCR */ + volatile uint8_t SPSR; /* SPSR */ + union reg32_t SPDR; /* SPDR */ + + volatile uint8_t SPSCR; /* SPSCR */ + volatile uint8_t SPSSR; /* SPSSR */ + volatile uint8_t SPBR; /* SPBR */ + volatile uint8_t SPDCR; /* SPDCR */ + volatile uint8_t SPCKD; /* SPCKD */ + volatile uint8_t SSLND; /* SSLND */ + volatile uint8_t SPND; /* SPND */ + volatile uint8_t dummy1[1]; /* */ +#define SPCMD_COUNT 4 + volatile uint16_t SPCMD0; /* SPCMD0 */ + volatile uint16_t SPCMD1; /* SPCMD1 */ + volatile uint16_t SPCMD2; /* SPCMD2 */ + volatile uint16_t SPCMD3; /* SPCMD3 */ + volatile uint8_t dummy2[8]; /* */ + volatile uint8_t SPBFCR; /* SPBFCR */ + volatile uint8_t dummy3[1]; /* */ + volatile uint16_t SPBFDR; /* SPBFDR */ +}; + + +#define RSPI0 (*(struct st_rspi *)0xE800C800uL) /* RSPI0 */ +#define RSPI1 (*(struct st_rspi *)0xE800D000uL) /* RSPI1 */ +#define RSPI2 (*(struct st_rspi *)0xE800D800uL) /* RSPI2 */ +#define RSPI3 (*(struct st_rspi *)0xE800E000uL) /* RSPI3 */ +#define RSPI4 (*(struct st_rspi *)0xE800E800uL) /* RSPI4 */ + + +/* Start of channnel array defines of RSPI */ + +/* Channnel array defines of RSPI */ +/*(Sample) value = RSPI[ channel ]->SPCR; */ +#define RSPI_COUNT 5 +#define RSPI_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channnel array defines of RSPI */ + + +#define SPCR_0 RSPI0.SPCR +#define SSLP_0 RSPI0.SSLP +#define SPPCR_0 RSPI0.SPPCR +#define SPSR_0 RSPI0.SPSR +#define SPDR_0 RSPI0.SPDR.UINT32 +#define SPDR_0L RSPI0.SPDR.UINT16[L] +#define SPDR_0H RSPI0.SPDR.UINT16[H] +#define SPDR_0LL RSPI0.SPDR.UINT8[LL] +#define SPDR_0LH RSPI0.SPDR.UINT8[LH] +#define SPDR_0HL RSPI0.SPDR.UINT8[HL] +#define SPDR_0HH RSPI0.SPDR.UINT8[HH] +#define SPSCR_0 RSPI0.SPSCR +#define SPSSR_0 RSPI0.SPSSR +#define SPBR_0 RSPI0.SPBR +#define SPDCR_0 RSPI0.SPDCR +#define SPCKD_0 RSPI0.SPCKD +#define SSLND_0 RSPI0.SSLND +#define SPND_0 RSPI0.SPND +#define SPCMD0_0 RSPI0.SPCMD0 +#define SPCMD1_0 RSPI0.SPCMD1 +#define SPCMD2_0 RSPI0.SPCMD2 +#define SPCMD3_0 RSPI0.SPCMD3 +#define SPBFCR_0 RSPI0.SPBFCR +#define SPBFDR_0 RSPI0.SPBFDR +#define SPCR_1 RSPI1.SPCR +#define SSLP_1 RSPI1.SSLP +#define SPPCR_1 RSPI1.SPPCR +#define SPSR_1 RSPI1.SPSR +#define SPDR_1 RSPI1.SPDR.UINT32 +#define SPDR_1L RSPI1.SPDR.UINT16[L] +#define SPDR_1H RSPI1.SPDR.UINT16[H] +#define SPDR_1LL RSPI1.SPDR.UINT8[LL] +#define SPDR_1LH RSPI1.SPDR.UINT8[LH] +#define SPDR_1HL RSPI1.SPDR.UINT8[HL] +#define SPDR_1HH RSPI1.SPDR.UINT8[HH] +#define SPSCR_1 RSPI1.SPSCR +#define SPSSR_1 RSPI1.SPSSR +#define SPBR_1 RSPI1.SPBR +#define SPDCR_1 RSPI1.SPDCR +#define SPCKD_1 RSPI1.SPCKD +#define SSLND_1 RSPI1.SSLND +#define SPND_1 RSPI1.SPND +#define SPCMD0_1 RSPI1.SPCMD0 +#define SPCMD1_1 RSPI1.SPCMD1 +#define SPCMD2_1 RSPI1.SPCMD2 +#define SPCMD3_1 RSPI1.SPCMD3 +#define SPBFCR_1 RSPI1.SPBFCR +#define SPBFDR_1 RSPI1.SPBFDR +#define SPCR_2 RSPI2.SPCR +#define SSLP_2 RSPI2.SSLP +#define SPPCR_2 RSPI2.SPPCR +#define SPSR_2 RSPI2.SPSR +#define SPDR_2 RSPI2.SPDR.UINT32 +#define SPDR_2L RSPI2.SPDR.UINT16[L] +#define SPDR_2H RSPI2.SPDR.UINT16[H] +#define SPDR_2LL RSPI2.SPDR.UINT8[LL] +#define SPDR_2LH RSPI2.SPDR.UINT8[LH] +#define SPDR_2HL RSPI2.SPDR.UINT8[HL] +#define SPDR_2HH RSPI2.SPDR.UINT8[HH] +#define SPSCR_2 RSPI2.SPSCR +#define SPSSR_2 RSPI2.SPSSR +#define SPBR_2 RSPI2.SPBR +#define SPDCR_2 RSPI2.SPDCR +#define SPCKD_2 RSPI2.SPCKD +#define SSLND_2 RSPI2.SSLND +#define SPND_2 RSPI2.SPND +#define SPCMD0_2 RSPI2.SPCMD0 +#define SPCMD1_2 RSPI2.SPCMD1 +#define SPCMD2_2 RSPI2.SPCMD2 +#define SPCMD3_2 RSPI2.SPCMD3 +#define SPBFCR_2 RSPI2.SPBFCR +#define SPBFDR_2 RSPI2.SPBFDR +#define SPCR_3 RSPI3.SPCR +#define SSLP_3 RSPI3.SSLP +#define SPPCR_3 RSPI3.SPPCR +#define SPSR_3 RSPI3.SPSR +#define SPDR_3 RSPI3.SPDR.UINT32 +#define SPDR_3L RSPI3.SPDR.UINT16[L] +#define SPDR_3H RSPI3.SPDR.UINT16[H] +#define SPDR_3LL RSPI3.SPDR.UINT8[LL] +#define SPDR_3LH RSPI3.SPDR.UINT8[LH] +#define SPDR_3HL RSPI3.SPDR.UINT8[HL] +#define SPDR_3HH RSPI3.SPDR.UINT8[HH] +#define SPSCR_3 RSPI3.SPSCR +#define SPSSR_3 RSPI3.SPSSR +#define SPBR_3 RSPI3.SPBR +#define SPDCR_3 RSPI3.SPDCR +#define SPCKD_3 RSPI3.SPCKD +#define SSLND_3 RSPI3.SSLND +#define SPND_3 RSPI3.SPND +#define SPCMD0_3 RSPI3.SPCMD0 +#define SPCMD1_3 RSPI3.SPCMD1 +#define SPCMD2_3 RSPI3.SPCMD2 +#define SPCMD3_3 RSPI3.SPCMD3 +#define SPBFCR_3 RSPI3.SPBFCR +#define SPBFDR_3 RSPI3.SPBFDR +#define SPCR_4 RSPI4.SPCR +#define SSLP_4 RSPI4.SSLP +#define SPPCR_4 RSPI4.SPPCR +#define SPSR_4 RSPI4.SPSR +#define SPDR_4 RSPI4.SPDR.UINT32 +#define SPDR_4L RSPI4.SPDR.UINT16[L] +#define SPDR_4H RSPI4.SPDR.UINT16[H] +#define SPDR_4LL RSPI4.SPDR.UINT8[LL] +#define SPDR_4LH RSPI4.SPDR.UINT8[LH] +#define SPDR_4HL RSPI4.SPDR.UINT8[HL] +#define SPDR_4HH RSPI4.SPDR.UINT8[HH] +#define SPSCR_4 RSPI4.SPSCR +#define SPSSR_4 RSPI4.SPSSR +#define SPBR_4 RSPI4.SPBR +#define SPDCR_4 RSPI4.SPDCR +#define SPCKD_4 RSPI4.SPCKD +#define SSLND_4 RSPI4.SSLND +#define SPND_4 RSPI4.SPND +#define SPCMD0_4 RSPI4.SPCMD0 +#define SPCMD1_4 RSPI4.SPCMD1 +#define SPCMD2_4 RSPI4.SPCMD2 +#define SPCMD3_4 RSPI4.SPCMD3 +#define SPBFCR_4 RSPI4.SPBFCR +#define SPBFDR_4 RSPI4.SPBFDR +/* <-SEC M1.10.1 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/rtc_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,102 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : rtc_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef RTC_IODEFINE_H +#define RTC_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_rtc +{ /* RTC */ + volatile uint8_t R64CNT; /* R64CNT */ + volatile uint8_t dummy537[1]; /* */ + volatile uint8_t RSECCNT; /* RSECCNT */ + volatile uint8_t dummy538[1]; /* */ + volatile uint8_t RMINCNT; /* RMINCNT */ + volatile uint8_t dummy539[1]; /* */ + volatile uint8_t RHRCNT; /* RHRCNT */ + volatile uint8_t dummy540[1]; /* */ + volatile uint8_t RWKCNT; /* RWKCNT */ + volatile uint8_t dummy541[1]; /* */ + volatile uint8_t RDAYCNT; /* RDAYCNT */ + volatile uint8_t dummy542[1]; /* */ + volatile uint8_t RMONCNT; /* RMONCNT */ + volatile uint8_t dummy543[1]; /* */ + volatile uint16_t RYRCNT; /* RYRCNT */ + volatile uint8_t RSECAR; /* RSECAR */ + volatile uint8_t dummy544[1]; /* */ + volatile uint8_t RMINAR; /* RMINAR */ + volatile uint8_t dummy545[1]; /* */ + volatile uint8_t RHRAR; /* RHRAR */ + volatile uint8_t dummy546[1]; /* */ + volatile uint8_t RWKAR; /* RWKAR */ + volatile uint8_t dummy547[1]; /* */ + volatile uint8_t RDAYAR; /* RDAYAR */ + volatile uint8_t dummy548[1]; /* */ + volatile uint8_t RMONAR; /* RMONAR */ + volatile uint8_t dummy549[1]; /* */ + volatile uint8_t RCR1; /* RCR1 */ + volatile uint8_t dummy550[1]; /* */ + volatile uint8_t RCR2; /* RCR2 */ + volatile uint8_t dummy551[1]; /* */ + volatile uint16_t RYRAR; /* RYRAR */ + volatile uint8_t dummy552[2]; /* */ + volatile uint8_t RCR3; /* RCR3 */ + volatile uint8_t dummy553[1]; /* */ + volatile uint8_t RCR5; /* RCR5 */ + volatile uint8_t dummy554[3]; /* */ + volatile uint16_t RFRH; /* RFRH */ + volatile uint16_t RFRL; /* RFRL */ +}; + + +#define RTC (*(struct st_rtc *)0xFCFF1000uL) /* RTC */ + + +#define RTCR64CNT RTC.R64CNT +#define RTCRSECCNT RTC.RSECCNT +#define RTCRMINCNT RTC.RMINCNT +#define RTCRHRCNT RTC.RHRCNT +#define RTCRWKCNT RTC.RWKCNT +#define RTCRDAYCNT RTC.RDAYCNT +#define RTCRMONCNT RTC.RMONCNT +#define RTCRYRCNT RTC.RYRCNT +#define RTCRSECAR RTC.RSECAR +#define RTCRMINAR RTC.RMINAR +#define RTCRHRAR RTC.RHRAR +#define RTCRWKAR RTC.RWKAR +#define RTCRDAYAR RTC.RDAYAR +#define RTCRMONAR RTC.RMONAR +#define RTCRCR1 RTC.RCR1 +#define RTCRCR2 RTC.RCR2 +#define RTCRYRAR RTC.RYRAR +#define RTCRCR3 RTC.RCR3 +#define RTCRCR5 RTC.RCR5 +#define RTCRFRH RTC.RFRH +#define RTCRFRL RTC.RFRL +/* <-SEC M1.10.1 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/scif_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,182 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : scif_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef SCIF_IODEFINE_H +#define SCIF_IODEFINE_H +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->SEC M1.10.1 : Not magic number */ + +struct st_scif +{ /* SCIF */ + volatile uint16_t SCSMR; /* SCSMR */ + volatile uint8_t dummy1[2]; /* */ + volatile uint8_t SCBRR; /* SCBRR */ + volatile uint8_t dummy2[3]; /* */ + volatile uint16_t SCSCR; /* SCSCR */ + volatile uint8_t dummy3[2]; /* */ + volatile uint8_t SCFTDR; /* SCFTDR */ + volatile uint8_t dummy4[3]; /* */ + volatile uint16_t SCFSR; /* SCFSR */ + volatile uint8_t dummy5[2]; /* */ + volatile uint8_t SCFRDR; /* SCFRDR */ + volatile uint8_t dummy6[3]; /* */ + volatile uint16_t SCFCR; /* SCFCR */ + volatile uint8_t dummy7[2]; /* */ + volatile uint16_t SCFDR; /* SCFDR */ + volatile uint8_t dummy8[2]; /* */ + volatile uint16_t SCSPTR; /* SCSPTR */ + volatile uint8_t dummy9[2]; /* */ + volatile uint16_t SCLSR; /* SCLSR */ + volatile uint8_t dummy10[2]; /* */ + volatile uint16_t SCEMR; /* SCEMR */ +}; + + +#define SCIF0 (*(struct st_scif *)0xE8007000uL) /* SCIF0 */ +#define SCIF1 (*(struct st_scif *)0xE8007800uL) /* SCIF1 */ +#define SCIF2 (*(struct st_scif *)0xE8008000uL) /* SCIF2 */ +#define SCIF3 (*(struct st_scif *)0xE8008800uL) /* SCIF3 */ +#define SCIF4 (*(struct st_scif *)0xE8009000uL) /* SCIF4 */ +#define SCIF5 (*(struct st_scif *)0xE8009800uL) /* SCIF5 */ +#define SCIF6 (*(struct st_scif *)0xE800A000uL) /* SCIF6 */ +#define SCIF7 (*(struct st_scif *)0xE800A800uL) /* SCIF7 */ + +#define P_SCIF0 (0xE8007000uL) /* SCIF0 */ +#define P_SCIF1 (0xE8007800uL) /* SCIF1 */ +#define P_SCIF2 (0xE8008000uL) /* SCIF2 */ +#define P_SCIF3 (0xE8008800uL) /* SCIF3 */ +#define P_SCIF4 (0xE8009000uL) /* SCIF4 */ +#define P_SCIF5 (0xE8009800uL) /* SCIF5 */ +#define P_SCIF6 (0xE800A000uL) /* SCIF6 */ +#define P_SCIF7 (0xE800A800uL) /* SCIF7 */ + + +/* Start of channnel array defines of SCIF */ + +/* Channnel array defines of SCIF */ +/*(Sample) value = SCIF[ channel ]->SCSMR; */ +#define SCIF_COUNT 8 +#define SCIF_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCIF0, &SCIF1, &SCIF2, &SCIF3, &SCIF4, &SCIF5, &SCIF6, &SCIF7 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channnel array defines of SCIF */ + + +#define SCSMR_0 SCIF0.SCSMR +#define SCBRR_0 SCIF0.SCBRR +#define SCSCR_0 SCIF0.SCSCR +#define SCFTDR_0 SCIF0.SCFTDR +#define SCFSR_0 SCIF0.SCFSR +#define SCFRDR_0 SCIF0.SCFRDR +#define SCFCR_0 SCIF0.SCFCR +#define SCFDR_0 SCIF0.SCFDR +#define SCSPTR_0 SCIF0.SCSPTR +#define SCLSR_0 SCIF0.SCLSR +#define SCEMR_0 SCIF0.SCEMR +#define SCSMR_1 SCIF1.SCSMR +#define SCBRR_1 SCIF1.SCBRR +#define SCSCR_1 SCIF1.SCSCR +#define SCFTDR_1 SCIF1.SCFTDR +#define SCFSR_1 SCIF1.SCFSR +#define SCFRDR_1 SCIF1.SCFRDR +#define SCFCR_1 SCIF1.SCFCR +#define SCFDR_1 SCIF1.SCFDR +#define SCSPTR_1 SCIF1.SCSPTR +#define SCLSR_1 SCIF1.SCLSR +#define SCEMR_1 SCIF1.SCEMR +#define SCSMR_2 SCIF2.SCSMR +#define SCBRR_2 SCIF2.SCBRR +#define SCSCR_2 SCIF2.SCSCR +#define SCFTDR_2 SCIF2.SCFTDR +#define SCFSR_2 SCIF2.SCFSR +#define SCFRDR_2 SCIF2.SCFRDR +#define SCFCR_2 SCIF2.SCFCR +#define SCFDR_2 SCIF2.SCFDR +#define SCSPTR_2 SCIF2.SCSPTR +#define SCLSR_2 SCIF2.SCLSR +#define SCEMR_2 SCIF2.SCEMR +#define SCSMR_3 SCIF3.SCSMR +#define SCBRR_3 SCIF3.SCBRR +#define SCSCR_3 SCIF3.SCSCR +#define SCFTDR_3 SCIF3.SCFTDR +#define SCFSR_3 SCIF3.SCFSR +#define SCFRDR_3 SCIF3.SCFRDR +#define SCFCR_3 SCIF3.SCFCR +#define SCFDR_3 SCIF3.SCFDR +#define SCSPTR_3 SCIF3.SCSPTR +#define SCLSR_3 SCIF3.SCLSR +#define SCEMR_3 SCIF3.SCEMR +#define SCSMR_4 SCIF4.SCSMR +#define SCBRR_4 SCIF4.SCBRR +#define SCSCR_4 SCIF4.SCSCR +#define SCFTDR_4 SCIF4.SCFTDR +#define SCFSR_4 SCIF4.SCFSR +#define SCFRDR_4 SCIF4.SCFRDR +#define SCFCR_4 SCIF4.SCFCR +#define SCFDR_4 SCIF4.SCFDR +#define SCSPTR_4 SCIF4.SCSPTR +#define SCLSR_4 SCIF4.SCLSR +#define SCEMR_4 SCIF4.SCEMR +#define SCSMR_5 SCIF5.SCSMR +#define SCBRR_5 SCIF5.SCBRR +#define SCSCR_5 SCIF5.SCSCR +#define SCFTDR_5 SCIF5.SCFTDR +#define SCFSR_5 SCIF5.SCFSR +#define SCFRDR_5 SCIF5.SCFRDR +#define SCFCR_5 SCIF5.SCFCR +#define SCFDR_5 SCIF5.SCFDR +#define SCSPTR_5 SCIF5.SCSPTR +#define SCLSR_5 SCIF5.SCLSR +#define SCEMR_5 SCIF5.SCEMR +#define SCSMR_6 SCIF6.SCSMR +#define SCBRR_6 SCIF6.SCBRR +#define SCSCR_6 SCIF6.SCSCR +#define SCFTDR_6 SCIF6.SCFTDR +#define SCFSR_6 SCIF6.SCFSR +#define SCFRDR_6 SCIF6.SCFRDR +#define SCFCR_6 SCIF6.SCFCR +#define SCFDR_6 SCIF6.SCFDR +#define SCSPTR_6 SCIF6.SCSPTR +#define SCLSR_6 SCIF6.SCLSR +#define SCEMR_6 SCIF6.SCEMR +#define SCSMR_7 SCIF7.SCSMR +#define SCBRR_7 SCIF7.SCBRR +#define SCSCR_7 SCIF7.SCSCR +#define SCFTDR_7 SCIF7.SCFTDR +#define SCFSR_7 SCIF7.SCFSR +#define SCFRDR_7 SCIF7.SCFRDR +#define SCFCR_7 SCIF7.SCFCR +#define SCFDR_7 SCIF7.SCFDR +#define SCSPTR_7 SCIF7.SCSPTR +#define SCLSR_7 SCIF7.SCLSR +#define SCEMR_7 SCIF7.SCEMR +/* <-SEC M1.10.1 */ +/* <-QAC 0857 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/scim_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,87 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : scim_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef SCIM_IODEFINE_H +#define SCIM_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_scim +{ /* SCIM */ + volatile uint8_t SMR; /* SMR */ + volatile uint8_t BRR; /* BRR */ + volatile uint8_t SCR; /* SCR */ + volatile uint8_t TDR; /* TDR */ + volatile uint8_t SSR; /* SSR */ + volatile uint8_t RDR; /* RDR */ + volatile uint8_t SCMR; /* SCMR */ + volatile uint8_t SEMR; /* SEMR */ + volatile uint8_t SNFR; /* SNFR */ + volatile uint8_t dummy1[4]; /* */ + volatile uint8_t SECR; /* SECR */ +}; + + +#define SCIM0 (*(struct st_scim *)0xE800B000uL) /* SCIM0 */ +#define SCIM1 (*(struct st_scim *)0xE800B800uL) /* SCIM1 */ + + +/* Start of channnel array defines of SCIM */ + +/* Channnel array defines of SCIM */ +/*(Sample) value = SCIM[ channel ]->SMR; */ +#define SCIM_COUNT 2 +#define SCIM_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCIM0, &SCIM1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channnel array defines of SCIM */ + + +#define SMR0 SCIM0.SMR +#define BRR0 SCIM0.BRR +#define SCR0 SCIM0.SCR +#define TDR0 SCIM0.TDR +#define SSR0 SCIM0.SSR +#define RDR0 SCIM0.RDR +#define SCMR0 SCIM0.SCMR +#define SEMR0 SCIM0.SEMR +#define SNFR0 SCIM0.SNFR +#define SECR0 SCIM0.SECR +#define SMR1 SCIM1.SMR +#define BRR1 SCIM1.BRR +#define SCR1 SCIM1.SCR +#define TDR1 SCIM1.TDR +#define SSR1 SCIM1.SSR +#define RDR1 SCIM1.RDR +#define SCMR1 SCIM1.SCMR +#define SEMR1 SCIM1.SEMR +#define SNFR1 SCIM1.SNFR +#define SECR1 SCIM1.SECR +/* <-SEC M1.10.1 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/scux_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,808 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : scux_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef SCUX_IODEFINE_H +#define SCUX_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->SEC M1.10.1 : Not magic number */ + +struct st_scux +{ /* SCUX */ +/* start of struct st_scux_from_ipcir_ipc0_n */ + volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */ + volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */ + volatile uint8_t dummy259[248]; /* */ +/* end of struct st_scux_from_ipcir_ipc0_n */ +/* start of struct st_scux_from_ipcir_ipc0_n */ + volatile uint32_t IPCIR_IPC0_1; /* IPCIR_IPC0_1 */ + volatile uint32_t IPSLR_IPC0_1; /* IPSLR_IPC0_1 */ + volatile uint8_t dummy260[248]; /* */ +/* end of struct st_scux_from_ipcir_ipc0_n */ +/* start of struct st_scux_from_ipcir_ipc0_n */ + volatile uint32_t IPCIR_IPC0_2; /* IPCIR_IPC0_2 */ + volatile uint32_t IPSLR_IPC0_2; /* IPSLR_IPC0_2 */ + volatile uint8_t dummy261[248]; /* */ +/* end of struct st_scux_from_ipcir_ipc0_n */ +/* start of struct st_scux_from_ipcir_ipc0_n */ + volatile uint32_t IPCIR_IPC0_3; /* IPCIR_IPC0_3 */ + volatile uint32_t IPSLR_IPC0_3; /* IPSLR_IPC0_3 */ + volatile uint8_t dummy262[248]; /* */ +/* end of struct st_scux_from_ipcir_ipc0_n */ +/* start of struct st_scux_from_opcir_opc0_n */ + volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */ + volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */ + volatile uint8_t dummy263[248]; /* */ +/* end of struct st_scux_from_opcir_opc0_n */ +/* start of struct st_scux_from_opcir_opc0_n */ + volatile uint32_t OPCIR_OPC0_1; /* OPCIR_OPC0_1 */ + volatile uint32_t OPSLR_OPC0_1; /* OPSLR_OPC0_1 */ + volatile uint8_t dummy264[248]; /* */ +/* end of struct st_scux_from_opcir_opc0_n */ +/* start of struct st_scux_from_opcir_opc0_n */ + volatile uint32_t OPCIR_OPC0_2; /* OPCIR_OPC0_2 */ + volatile uint32_t OPSLR_OPC0_2; /* OPSLR_OPC0_2 */ + volatile uint8_t dummy265[248]; /* */ +/* end of struct st_scux_from_opcir_opc0_n */ +/* start of struct st_scux_from_opcir_opc0_n */ + volatile uint32_t OPCIR_OPC0_3; /* OPCIR_OPC0_3 */ + volatile uint32_t OPSLR_OPC0_3; /* OPSLR_OPC0_3 */ + volatile uint8_t dummy266[248]; /* */ +/* end of struct st_scux_from_opcir_opc0_n */ +/* start of struct st_scux_from_ffdir_ffd0_n */ + volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */ + volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */ + volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */ + volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */ + volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */ + volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */ + volatile uint8_t dummy267[4]; /* */ + volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */ +/* end of struct st_scux_from_ffdir_ffd0_n */ + volatile uint8_t dummy268[224]; /* */ +/* start of struct st_scux_from_ffdir_ffd0_n */ + volatile uint32_t FFDIR_FFD0_1; /* FFDIR_FFD0_1 */ + volatile uint32_t FDAIR_FFD0_1; /* FDAIR_FFD0_1 */ + volatile uint32_t DRQSR_FFD0_1; /* DRQSR_FFD0_1 */ + volatile uint32_t FFDPR_FFD0_1; /* FFDPR_FFD0_1 */ + volatile uint32_t FFDBR_FFD0_1; /* FFDBR_FFD0_1 */ + volatile uint32_t DEVMR_FFD0_1; /* DEVMR_FFD0_1 */ + volatile uint8_t dummy269[4]; /* */ + volatile uint32_t DEVCR_FFD0_1; /* DEVCR_FFD0_1 */ +/* end of struct st_scux_from_ffdir_ffd0_n */ + volatile uint8_t dummy270[224]; /* */ +/* start of struct st_scux_from_ffdir_ffd0_n */ + volatile uint32_t FFDIR_FFD0_2; /* FFDIR_FFD0_2 */ + volatile uint32_t FDAIR_FFD0_2; /* FDAIR_FFD0_2 */ + volatile uint32_t DRQSR_FFD0_2; /* DRQSR_FFD0_2 */ + volatile uint32_t FFDPR_FFD0_2; /* FFDPR_FFD0_2 */ + volatile uint32_t FFDBR_FFD0_2; /* FFDBR_FFD0_2 */ + volatile uint32_t DEVMR_FFD0_2; /* DEVMR_FFD0_2 */ + volatile uint8_t dummy271[4]; /* */ + volatile uint32_t DEVCR_FFD0_2; /* DEVCR_FFD0_2 */ +/* end of struct st_scux_from_ffdir_ffd0_n */ + volatile uint8_t dummy272[224]; /* */ +/* start of struct st_scux_from_ffdir_ffd0_n */ + volatile uint32_t FFDIR_FFD0_3; /* FFDIR_FFD0_3 */ + volatile uint32_t FDAIR_FFD0_3; /* FDAIR_FFD0_3 */ + volatile uint32_t DRQSR_FFD0_3; /* DRQSR_FFD0_3 */ + volatile uint32_t FFDPR_FFD0_3; /* FFDPR_FFD0_3 */ + volatile uint32_t FFDBR_FFD0_3; /* FFDBR_FFD0_3 */ + volatile uint32_t DEVMR_FFD0_3; /* DEVMR_FFD0_3 */ + volatile uint8_t dummy273[4]; /* */ + volatile uint32_t DEVCR_FFD0_3; /* DEVCR_FFD0_3 */ +/* end of struct st_scux_from_ffdir_ffd0_n */ + volatile uint8_t dummy274[224]; /* */ +/* start of struct st_scux_from_ffuir_ffu0_n */ + volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */ + volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */ + volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */ + volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */ + volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */ + volatile uint8_t dummy275[4]; /* */ + volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */ +/* end of struct st_scux_from_ffuir_ffu0_n */ + volatile uint8_t dummy276[228]; /* */ +/* start of struct st_scux_from_ffuir_ffu0_n */ + volatile uint32_t FFUIR_FFU0_1; /* FFUIR_FFU0_1 */ + volatile uint32_t FUAIR_FFU0_1; /* FUAIR_FFU0_1 */ + volatile uint32_t URQSR_FFU0_1; /* URQSR_FFU0_1 */ + volatile uint32_t FFUPR_FFU0_1; /* FFUPR_FFU0_1 */ + volatile uint32_t UEVMR_FFU0_1; /* UEVMR_FFU0_1 */ + volatile uint8_t dummy277[4]; /* */ + volatile uint32_t UEVCR_FFU0_1; /* UEVCR_FFU0_1 */ +/* end of struct st_scux_from_ffuir_ffu0_n */ + volatile uint8_t dummy278[228]; /* */ +/* start of struct st_scux_from_ffuir_ffu0_n */ + volatile uint32_t FFUIR_FFU0_2; /* FFUIR_FFU0_2 */ + volatile uint32_t FUAIR_FFU0_2; /* FUAIR_FFU0_2 */ + volatile uint32_t URQSR_FFU0_2; /* URQSR_FFU0_2 */ + volatile uint32_t FFUPR_FFU0_2; /* FFUPR_FFU0_2 */ + volatile uint32_t UEVMR_FFU0_2; /* UEVMR_FFU0_2 */ + volatile uint8_t dummy279[4]; /* */ + volatile uint32_t UEVCR_FFU0_2; /* UEVCR_FFU0_2 */ +/* end of struct st_scux_from_ffuir_ffu0_n */ + volatile uint8_t dummy280[228]; /* */ +/* start of struct st_scux_from_ffuir_ffu0_n */ + volatile uint32_t FFUIR_FFU0_3; /* FFUIR_FFU0_3 */ + volatile uint32_t FUAIR_FFU0_3; /* FUAIR_FFU0_3 */ + volatile uint32_t URQSR_FFU0_3; /* URQSR_FFU0_3 */ + volatile uint32_t FFUPR_FFU0_3; /* FFUPR_FFU0_3 */ + volatile uint32_t UEVMR_FFU0_3; /* UEVMR_FFU0_3 */ + volatile uint8_t dummy281[4]; /* */ + volatile uint32_t UEVCR_FFU0_3; /* UEVCR_FFU0_3 */ +/* end of struct st_scux_from_ffuir_ffu0_n */ + volatile uint8_t dummy282[228]; /* */ +/* start of struct st_scux_from_srcir0_2src0_n */ + volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */ + volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */ + volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */ + volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */ + volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */ + volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */ + volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */ + volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */ + volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */ + volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */ + volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */ + volatile uint8_t dummy283[4]; /* */ + volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */ + volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */ + volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */ + volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */ + volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */ + volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */ + volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */ + volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */ + volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */ + volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */ + volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */ + volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */ + volatile uint8_t dummy284[4]; /* */ + volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */ + volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */ +/* end of struct st_scux_from_srcir0_2src0_n */ + volatile uint8_t dummy285[148]; /* */ +/* start of struct st_scux_from_srcir0_2src0_n */ + volatile uint32_t SRCIR0_2SRC0_1; /* SRCIR0_2SRC0_1 */ + volatile uint32_t SADIR0_2SRC0_1; /* SADIR0_2SRC0_1 */ + volatile uint32_t SRCBR0_2SRC0_1; /* SRCBR0_2SRC0_1 */ + volatile uint32_t IFSCR0_2SRC0_1; /* IFSCR0_2SRC0_1 */ + volatile uint32_t IFSVR0_2SRC0_1; /* IFSVR0_2SRC0_1 */ + volatile uint32_t SRCCR0_2SRC0_1; /* SRCCR0_2SRC0_1 */ + volatile uint32_t MNFSR0_2SRC0_1; /* MNFSR0_2SRC0_1 */ + volatile uint32_t BFSSR0_2SRC0_1; /* BFSSR0_2SRC0_1 */ + volatile uint32_t SC2SR0_2SRC0_1; /* SC2SR0_2SRC0_1 */ + volatile uint32_t WATSR0_2SRC0_1; /* WATSR0_2SRC0_1 */ + volatile uint32_t SEVMR0_2SRC0_1; /* SEVMR0_2SRC0_1 */ + volatile uint8_t dummy286[4]; /* */ + volatile uint32_t SEVCR0_2SRC0_1; /* SEVCR0_2SRC0_1 */ + volatile uint32_t SRCIR1_2SRC0_1; /* SRCIR1_2SRC0_1 */ + volatile uint32_t SADIR1_2SRC0_1; /* SADIR1_2SRC0_1 */ + volatile uint32_t SRCBR1_2SRC0_1; /* SRCBR1_2SRC0_1 */ + volatile uint32_t IFSCR1_2SRC0_1; /* IFSCR1_2SRC0_1 */ + volatile uint32_t IFSVR1_2SRC0_1; /* IFSVR1_2SRC0_1 */ + volatile uint32_t SRCCR1_2SRC0_1; /* SRCCR1_2SRC0_1 */ + volatile uint32_t MNFSR1_2SRC0_1; /* MNFSR1_2SRC0_1 */ + volatile uint32_t BFSSR1_2SRC0_1; /* BFSSR1_2SRC0_1 */ + volatile uint32_t SC2SR1_2SRC0_1; /* SC2SR1_2SRC0_1 */ + volatile uint32_t WATSR1_2SRC0_1; /* WATSR1_2SRC0_1 */ + volatile uint32_t SEVMR1_2SRC0_1; /* SEVMR1_2SRC0_1 */ + volatile uint8_t dummy287[4]; /* */ + volatile uint32_t SEVCR1_2SRC0_1; /* SEVCR1_2SRC0_1 */ + volatile uint32_t SRCIRR_2SRC0_1; /* SRCIRR_2SRC0_1 */ +/* end of struct st_scux_from_srcir0_2src0_n */ + volatile uint8_t dummy288[148]; /* */ +/* start of struct st_scux_from_dvuir_dvu0_n */ + volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */ + volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */ + volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */ + volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */ + volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */ + volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */ + volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */ + volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */ + volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */ + volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */ + volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */ + volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */ + volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */ + volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */ + volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */ + volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */ + volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */ + volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */ + volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */ + volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */ + volatile uint8_t dummy289[4]; /* */ + volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */ +/* end of struct st_scux_from_dvuir_dvu0_n */ + volatile uint8_t dummy290[168]; /* */ +/* start of struct st_scux_from_dvuir_dvu0_n */ + volatile uint32_t DVUIR_DVU0_1; /* DVUIR_DVU0_1 */ + volatile uint32_t VADIR_DVU0_1; /* VADIR_DVU0_1 */ + volatile uint32_t DVUBR_DVU0_1; /* DVUBR_DVU0_1 */ + volatile uint32_t DVUCR_DVU0_1; /* DVUCR_DVU0_1 */ + volatile uint32_t ZCMCR_DVU0_1; /* ZCMCR_DVU0_1 */ + volatile uint32_t VRCTR_DVU0_1; /* VRCTR_DVU0_1 */ + volatile uint32_t VRPDR_DVU0_1; /* VRPDR_DVU0_1 */ + volatile uint32_t VRDBR_DVU0_1; /* VRDBR_DVU0_1 */ + volatile uint32_t VRWTR_DVU0_1; /* VRWTR_DVU0_1 */ + volatile uint32_t VOL0R_DVU0_1; /* VOL0R_DVU0_1 */ + volatile uint32_t VOL1R_DVU0_1; /* VOL1R_DVU0_1 */ + volatile uint32_t VOL2R_DVU0_1; /* VOL2R_DVU0_1 */ + volatile uint32_t VOL3R_DVU0_1; /* VOL3R_DVU0_1 */ + volatile uint32_t VOL4R_DVU0_1; /* VOL4R_DVU0_1 */ + volatile uint32_t VOL5R_DVU0_1; /* VOL5R_DVU0_1 */ + volatile uint32_t VOL6R_DVU0_1; /* VOL6R_DVU0_1 */ + volatile uint32_t VOL7R_DVU0_1; /* VOL7R_DVU0_1 */ + volatile uint32_t DVUER_DVU0_1; /* DVUER_DVU0_1 */ + volatile uint32_t DVUSR_DVU0_1; /* DVUSR_DVU0_1 */ + volatile uint32_t VEVMR_DVU0_1; /* VEVMR_DVU0_1 */ + volatile uint8_t dummy291[4]; /* */ + volatile uint32_t VEVCR_DVU0_1; /* VEVCR_DVU0_1 */ +/* end of struct st_scux_from_dvuir_dvu0_n */ + volatile uint8_t dummy292[168]; /* */ +/* start of struct st_scux_from_dvuir_dvu0_n */ + volatile uint32_t DVUIR_DVU0_2; /* DVUIR_DVU0_2 */ + volatile uint32_t VADIR_DVU0_2; /* VADIR_DVU0_2 */ + volatile uint32_t DVUBR_DVU0_2; /* DVUBR_DVU0_2 */ + volatile uint32_t DVUCR_DVU0_2; /* DVUCR_DVU0_2 */ + volatile uint32_t ZCMCR_DVU0_2; /* ZCMCR_DVU0_2 */ + volatile uint32_t VRCTR_DVU0_2; /* VRCTR_DVU0_2 */ + volatile uint32_t VRPDR_DVU0_2; /* VRPDR_DVU0_2 */ + volatile uint32_t VRDBR_DVU0_2; /* VRDBR_DVU0_2 */ + volatile uint32_t VRWTR_DVU0_2; /* VRWTR_DVU0_2 */ + volatile uint32_t VOL0R_DVU0_2; /* VOL0R_DVU0_2 */ + volatile uint32_t VOL1R_DVU0_2; /* VOL1R_DVU0_2 */ + volatile uint32_t VOL2R_DVU0_2; /* VOL2R_DVU0_2 */ + volatile uint32_t VOL3R_DVU0_2; /* VOL3R_DVU0_2 */ + volatile uint32_t VOL4R_DVU0_2; /* VOL4R_DVU0_2 */ + volatile uint32_t VOL5R_DVU0_2; /* VOL5R_DVU0_2 */ + volatile uint32_t VOL6R_DVU0_2; /* VOL6R_DVU0_2 */ + volatile uint32_t VOL7R_DVU0_2; /* VOL7R_DVU0_2 */ + volatile uint32_t DVUER_DVU0_2; /* DVUER_DVU0_2 */ + volatile uint32_t DVUSR_DVU0_2; /* DVUSR_DVU0_2 */ + volatile uint32_t VEVMR_DVU0_2; /* VEVMR_DVU0_2 */ + volatile uint8_t dummy293[4]; /* */ + volatile uint32_t VEVCR_DVU0_2; /* VEVCR_DVU0_2 */ +/* end of struct st_scux_from_dvuir_dvu0_n */ + volatile uint8_t dummy294[168]; /* */ +/* start of struct st_scux_from_dvuir_dvu0_n */ + volatile uint32_t DVUIR_DVU0_3; /* DVUIR_DVU0_3 */ + volatile uint32_t VADIR_DVU0_3; /* VADIR_DVU0_3 */ + volatile uint32_t DVUBR_DVU0_3; /* DVUBR_DVU0_3 */ + volatile uint32_t DVUCR_DVU0_3; /* DVUCR_DVU0_3 */ + volatile uint32_t ZCMCR_DVU0_3; /* ZCMCR_DVU0_3 */ + volatile uint32_t VRCTR_DVU0_3; /* VRCTR_DVU0_3 */ + volatile uint32_t VRPDR_DVU0_3; /* VRPDR_DVU0_3 */ + volatile uint32_t VRDBR_DVU0_3; /* VRDBR_DVU0_3 */ + volatile uint32_t VRWTR_DVU0_3; /* VRWTR_DVU0_3 */ + volatile uint32_t VOL0R_DVU0_3; /* VOL0R_DVU0_3 */ + volatile uint32_t VOL1R_DVU0_3; /* VOL1R_DVU0_3 */ + volatile uint32_t VOL2R_DVU0_3; /* VOL2R_DVU0_3 */ + volatile uint32_t VOL3R_DVU0_3; /* VOL3R_DVU0_3 */ + volatile uint32_t VOL4R_DVU0_3; /* VOL4R_DVU0_3 */ + volatile uint32_t VOL5R_DVU0_3; /* VOL5R_DVU0_3 */ + volatile uint32_t VOL6R_DVU0_3; /* VOL6R_DVU0_3 */ + volatile uint32_t VOL7R_DVU0_3; /* VOL7R_DVU0_3 */ + volatile uint32_t DVUER_DVU0_3; /* DVUER_DVU0_3 */ + volatile uint32_t DVUSR_DVU0_3; /* DVUSR_DVU0_3 */ + volatile uint32_t VEVMR_DVU0_3; /* VEVMR_DVU0_3 */ + volatile uint8_t dummy295[4]; /* */ + volatile uint32_t VEVCR_DVU0_3; /* VEVCR_DVU0_3 */ +/* end of struct st_scux_from_dvuir_dvu0_n */ + volatile uint8_t dummy296[168]; /* */ + volatile uint32_t MIXIR_MIX0_0; /* MIXIR_MIX0_0 */ + volatile uint32_t MADIR_MIX0_0; /* MADIR_MIX0_0 */ + volatile uint32_t MIXBR_MIX0_0; /* MIXBR_MIX0_0 */ + volatile uint32_t MIXMR_MIX0_0; /* MIXMR_MIX0_0 */ + volatile uint32_t MVPDR_MIX0_0; /* MVPDR_MIX0_0 */ + volatile uint32_t MDBAR_MIX0_0; /* MDBAR_MIX0_0 */ + volatile uint32_t MDBBR_MIX0_0; /* MDBBR_MIX0_0 */ + volatile uint32_t MDBCR_MIX0_0; /* MDBCR_MIX0_0 */ + volatile uint32_t MDBDR_MIX0_0; /* MDBDR_MIX0_0 */ + volatile uint32_t MDBER_MIX0_0; /* MDBER_MIX0_0 */ + volatile uint32_t MIXSR_MIX0_0; /* MIXSR_MIX0_0 */ + volatile uint8_t dummy297[212]; /* */ + volatile uint32_t SWRSR_CIM; /* SWRSR_CIM */ + volatile uint32_t DMACR_CIM; /* DMACR_CIM */ +#define SCUX_DMATDn_CIM_COUNT 4 + union iodefine_reg32_16_t DMATD0_CIM; /* DMATD0_CIM */ + union iodefine_reg32_16_t DMATD1_CIM; /* DMATD1_CIM */ + union iodefine_reg32_16_t DMATD2_CIM; /* DMATD2_CIM */ + union iodefine_reg32_16_t DMATD3_CIM; /* DMATD3_CIM */ +#define SCUX_DMATUn_CIM_COUNT 4 + union iodefine_reg32_16_t DMATU0_CIM; /* DMATU0_CIM */ + union iodefine_reg32_16_t DMATU1_CIM; /* DMATU1_CIM */ + union iodefine_reg32_16_t DMATU2_CIM; /* DMATU2_CIM */ + union iodefine_reg32_16_t DMATU3_CIM; /* DMATU3_CIM */ + + volatile uint8_t dummy298[16]; /* */ + volatile uint32_t SSIRSEL_CIM; /* SSIRSEL_CIM */ +#define SCUX_FDTSELn_CIM_COUNT 4 + volatile uint32_t FDTSEL0_CIM; /* FDTSEL0_CIM */ + volatile uint32_t FDTSEL1_CIM; /* FDTSEL1_CIM */ + volatile uint32_t FDTSEL2_CIM; /* FDTSEL2_CIM */ + volatile uint32_t FDTSEL3_CIM; /* FDTSEL3_CIM */ +#define SCUX_FUTSELn_CIM_COUNT 4 + volatile uint32_t FUTSEL0_CIM; /* FUTSEL0_CIM */ + volatile uint32_t FUTSEL1_CIM; /* FUTSEL1_CIM */ + volatile uint32_t FUTSEL2_CIM; /* FUTSEL2_CIM */ + volatile uint32_t FUTSEL3_CIM; /* FUTSEL3_CIM */ + volatile uint32_t SSIPMD_CIM; /* SSIPMD_CIM */ + volatile uint32_t SSICTRL_CIM; /* SSICTRL_CIM */ +#define SCUX_SRCRSELn_CIM_COUNT 4 + volatile uint32_t SRCRSEL0_CIM; /* SRCRSEL0_CIM */ + volatile uint32_t SRCRSEL1_CIM; /* SRCRSEL1_CIM */ + volatile uint32_t SRCRSEL2_CIM; /* SRCRSEL2_CIM */ + volatile uint32_t SRCRSEL3_CIM; /* SRCRSEL3_CIM */ + volatile uint32_t MIXRSEL_CIM; /* MIXRSEL_CIM */ +}; + + +struct st_scux_from_ipcir_ipc0_n +{ + volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */ + volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */ + volatile uint8_t dummy1[248]; /* */ +}; + + +struct st_scux_from_opcir_opc0_n +{ + volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */ + volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */ + volatile uint8_t dummy1[248]; /* */ +}; + + +struct st_scux_from_ffdir_ffd0_n +{ + volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */ + volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */ + volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */ + volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */ + volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */ + volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */ + volatile uint8_t dummy1[4]; /* */ + volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */ +}; + + +struct st_scux_from_ffuir_ffu0_n +{ + volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */ + volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */ + volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */ + volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */ + volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */ + volatile uint8_t dummy1[4]; /* */ + volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */ +}; + + +struct st_scux_from_srcir0_2src0_n +{ + volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */ + volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */ + volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */ + volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */ + volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */ + volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */ + volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */ + volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */ + volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */ + volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */ + volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */ + volatile uint8_t dummy1[4]; /* */ + volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */ + volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */ + volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */ + volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */ + volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */ + volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */ + volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */ + volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */ + volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */ + volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */ + volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */ + volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */ + volatile uint8_t dummy2[4]; /* */ + volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */ + volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */ +}; + + +struct st_scux_from_dvuir_dvu0_n +{ + volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */ + volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */ + volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */ + volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */ + volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */ + volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */ + volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */ + volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */ + volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */ + volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */ + volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */ + volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */ + volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */ + volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */ + volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */ + volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */ + volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */ + volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */ + volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */ + volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */ + volatile uint8_t dummy1[4]; /* */ + volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */ +}; + + +#define SCUX (*(struct st_scux *)0xE8208000uL) /* SCUX */ + + +/* Start of channnel array defines of SCUX */ + +/* Channnel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */ +#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT 4 +#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */ +#define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */ +#define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */ +#define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */ + + +/* Channnel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */ +#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT 2 +#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */ +#define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */ + + +/* Channnel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */ +#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT 4 +#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */ +#define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */ +#define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */ +#define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */ + + +/* Channnel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */ +#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT 4 +#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */ +#define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */ +#define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */ +#define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */ + + +/* Channnel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */ +#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT 4 +#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */ +#define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */ +#define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */ +#define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */ + + +/* Channnel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */ +#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT 4 +#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */ +#define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */ +#define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */ +#define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */ + +/* End of channnel array defines of SCUX */ + + +#define SCUXIPCIR_IPC0_0 SCUX.IPCIR_IPC0_0 +#define SCUXIPSLR_IPC0_0 SCUX.IPSLR_IPC0_0 +#define SCUXIPCIR_IPC0_1 SCUX.IPCIR_IPC0_1 +#define SCUXIPSLR_IPC0_1 SCUX.IPSLR_IPC0_1 +#define SCUXIPCIR_IPC0_2 SCUX.IPCIR_IPC0_2 +#define SCUXIPSLR_IPC0_2 SCUX.IPSLR_IPC0_2 +#define SCUXIPCIR_IPC0_3 SCUX.IPCIR_IPC0_3 +#define SCUXIPSLR_IPC0_3 SCUX.IPSLR_IPC0_3 +#define SCUXOPCIR_OPC0_0 SCUX.OPCIR_OPC0_0 +#define SCUXOPSLR_OPC0_0 SCUX.OPSLR_OPC0_0 +#define SCUXOPCIR_OPC0_1 SCUX.OPCIR_OPC0_1 +#define SCUXOPSLR_OPC0_1 SCUX.OPSLR_OPC0_1 +#define SCUXOPCIR_OPC0_2 SCUX.OPCIR_OPC0_2 +#define SCUXOPSLR_OPC0_2 SCUX.OPSLR_OPC0_2 +#define SCUXOPCIR_OPC0_3 SCUX.OPCIR_OPC0_3 +#define SCUXOPSLR_OPC0_3 SCUX.OPSLR_OPC0_3 +#define SCUXFFDIR_FFD0_0 SCUX.FFDIR_FFD0_0 +#define SCUXFDAIR_FFD0_0 SCUX.FDAIR_FFD0_0 +#define SCUXDRQSR_FFD0_0 SCUX.DRQSR_FFD0_0 +#define SCUXFFDPR_FFD0_0 SCUX.FFDPR_FFD0_0 +#define SCUXFFDBR_FFD0_0 SCUX.FFDBR_FFD0_0 +#define SCUXDEVMR_FFD0_0 SCUX.DEVMR_FFD0_0 +#define SCUXDEVCR_FFD0_0 SCUX.DEVCR_FFD0_0 +#define SCUXFFDIR_FFD0_1 SCUX.FFDIR_FFD0_1 +#define SCUXFDAIR_FFD0_1 SCUX.FDAIR_FFD0_1 +#define SCUXDRQSR_FFD0_1 SCUX.DRQSR_FFD0_1 +#define SCUXFFDPR_FFD0_1 SCUX.FFDPR_FFD0_1 +#define SCUXFFDBR_FFD0_1 SCUX.FFDBR_FFD0_1 +#define SCUXDEVMR_FFD0_1 SCUX.DEVMR_FFD0_1 +#define SCUXDEVCR_FFD0_1 SCUX.DEVCR_FFD0_1 +#define SCUXFFDIR_FFD0_2 SCUX.FFDIR_FFD0_2 +#define SCUXFDAIR_FFD0_2 SCUX.FDAIR_FFD0_2 +#define SCUXDRQSR_FFD0_2 SCUX.DRQSR_FFD0_2 +#define SCUXFFDPR_FFD0_2 SCUX.FFDPR_FFD0_2 +#define SCUXFFDBR_FFD0_2 SCUX.FFDBR_FFD0_2 +#define SCUXDEVMR_FFD0_2 SCUX.DEVMR_FFD0_2 +#define SCUXDEVCR_FFD0_2 SCUX.DEVCR_FFD0_2 +#define SCUXFFDIR_FFD0_3 SCUX.FFDIR_FFD0_3 +#define SCUXFDAIR_FFD0_3 SCUX.FDAIR_FFD0_3 +#define SCUXDRQSR_FFD0_3 SCUX.DRQSR_FFD0_3 +#define SCUXFFDPR_FFD0_3 SCUX.FFDPR_FFD0_3 +#define SCUXFFDBR_FFD0_3 SCUX.FFDBR_FFD0_3 +#define SCUXDEVMR_FFD0_3 SCUX.DEVMR_FFD0_3 +#define SCUXDEVCR_FFD0_3 SCUX.DEVCR_FFD0_3 +#define SCUXFFUIR_FFU0_0 SCUX.FFUIR_FFU0_0 +#define SCUXFUAIR_FFU0_0 SCUX.FUAIR_FFU0_0 +#define SCUXURQSR_FFU0_0 SCUX.URQSR_FFU0_0 +#define SCUXFFUPR_FFU0_0 SCUX.FFUPR_FFU0_0 +#define SCUXUEVMR_FFU0_0 SCUX.UEVMR_FFU0_0 +#define SCUXUEVCR_FFU0_0 SCUX.UEVCR_FFU0_0 +#define SCUXFFUIR_FFU0_1 SCUX.FFUIR_FFU0_1 +#define SCUXFUAIR_FFU0_1 SCUX.FUAIR_FFU0_1 +#define SCUXURQSR_FFU0_1 SCUX.URQSR_FFU0_1 +#define SCUXFFUPR_FFU0_1 SCUX.FFUPR_FFU0_1 +#define SCUXUEVMR_FFU0_1 SCUX.UEVMR_FFU0_1 +#define SCUXUEVCR_FFU0_1 SCUX.UEVCR_FFU0_1 +#define SCUXFFUIR_FFU0_2 SCUX.FFUIR_FFU0_2 +#define SCUXFUAIR_FFU0_2 SCUX.FUAIR_FFU0_2 +#define SCUXURQSR_FFU0_2 SCUX.URQSR_FFU0_2 +#define SCUXFFUPR_FFU0_2 SCUX.FFUPR_FFU0_2 +#define SCUXUEVMR_FFU0_2 SCUX.UEVMR_FFU0_2 +#define SCUXUEVCR_FFU0_2 SCUX.UEVCR_FFU0_2 +#define SCUXFFUIR_FFU0_3 SCUX.FFUIR_FFU0_3 +#define SCUXFUAIR_FFU0_3 SCUX.FUAIR_FFU0_3 +#define SCUXURQSR_FFU0_3 SCUX.URQSR_FFU0_3 +#define SCUXFFUPR_FFU0_3 SCUX.FFUPR_FFU0_3 +#define SCUXUEVMR_FFU0_3 SCUX.UEVMR_FFU0_3 +#define SCUXUEVCR_FFU0_3 SCUX.UEVCR_FFU0_3 +#define SCUXSRCIR0_2SRC0_0 SCUX.SRCIR0_2SRC0_0 +#define SCUXSADIR0_2SRC0_0 SCUX.SADIR0_2SRC0_0 +#define SCUXSRCBR0_2SRC0_0 SCUX.SRCBR0_2SRC0_0 +#define SCUXIFSCR0_2SRC0_0 SCUX.IFSCR0_2SRC0_0 +#define SCUXIFSVR0_2SRC0_0 SCUX.IFSVR0_2SRC0_0 +#define SCUXSRCCR0_2SRC0_0 SCUX.SRCCR0_2SRC0_0 +#define SCUXMNFSR0_2SRC0_0 SCUX.MNFSR0_2SRC0_0 +#define SCUXBFSSR0_2SRC0_0 SCUX.BFSSR0_2SRC0_0 +#define SCUXSC2SR0_2SRC0_0 SCUX.SC2SR0_2SRC0_0 +#define SCUXWATSR0_2SRC0_0 SCUX.WATSR0_2SRC0_0 +#define SCUXSEVMR0_2SRC0_0 SCUX.SEVMR0_2SRC0_0 +#define SCUXSEVCR0_2SRC0_0 SCUX.SEVCR0_2SRC0_0 +#define SCUXSRCIR1_2SRC0_0 SCUX.SRCIR1_2SRC0_0 +#define SCUXSADIR1_2SRC0_0 SCUX.SADIR1_2SRC0_0 +#define SCUXSRCBR1_2SRC0_0 SCUX.SRCBR1_2SRC0_0 +#define SCUXIFSCR1_2SRC0_0 SCUX.IFSCR1_2SRC0_0 +#define SCUXIFSVR1_2SRC0_0 SCUX.IFSVR1_2SRC0_0 +#define SCUXSRCCR1_2SRC0_0 SCUX.SRCCR1_2SRC0_0 +#define SCUXMNFSR1_2SRC0_0 SCUX.MNFSR1_2SRC0_0 +#define SCUXBFSSR1_2SRC0_0 SCUX.BFSSR1_2SRC0_0 +#define SCUXSC2SR1_2SRC0_0 SCUX.SC2SR1_2SRC0_0 +#define SCUXWATSR1_2SRC0_0 SCUX.WATSR1_2SRC0_0 +#define SCUXSEVMR1_2SRC0_0 SCUX.SEVMR1_2SRC0_0 +#define SCUXSEVCR1_2SRC0_0 SCUX.SEVCR1_2SRC0_0 +#define SCUXSRCIRR_2SRC0_0 SCUX.SRCIRR_2SRC0_0 +#define SCUXSRCIR0_2SRC0_1 SCUX.SRCIR0_2SRC0_1 +#define SCUXSADIR0_2SRC0_1 SCUX.SADIR0_2SRC0_1 +#define SCUXSRCBR0_2SRC0_1 SCUX.SRCBR0_2SRC0_1 +#define SCUXIFSCR0_2SRC0_1 SCUX.IFSCR0_2SRC0_1 +#define SCUXIFSVR0_2SRC0_1 SCUX.IFSVR0_2SRC0_1 +#define SCUXSRCCR0_2SRC0_1 SCUX.SRCCR0_2SRC0_1 +#define SCUXMNFSR0_2SRC0_1 SCUX.MNFSR0_2SRC0_1 +#define SCUXBFSSR0_2SRC0_1 SCUX.BFSSR0_2SRC0_1 +#define SCUXSC2SR0_2SRC0_1 SCUX.SC2SR0_2SRC0_1 +#define SCUXWATSR0_2SRC0_1 SCUX.WATSR0_2SRC0_1 +#define SCUXSEVMR0_2SRC0_1 SCUX.SEVMR0_2SRC0_1 +#define SCUXSEVCR0_2SRC0_1 SCUX.SEVCR0_2SRC0_1 +#define SCUXSRCIR1_2SRC0_1 SCUX.SRCIR1_2SRC0_1 +#define SCUXSADIR1_2SRC0_1 SCUX.SADIR1_2SRC0_1 +#define SCUXSRCBR1_2SRC0_1 SCUX.SRCBR1_2SRC0_1 +#define SCUXIFSCR1_2SRC0_1 SCUX.IFSCR1_2SRC0_1 +#define SCUXIFSVR1_2SRC0_1 SCUX.IFSVR1_2SRC0_1 +#define SCUXSRCCR1_2SRC0_1 SCUX.SRCCR1_2SRC0_1 +#define SCUXMNFSR1_2SRC0_1 SCUX.MNFSR1_2SRC0_1 +#define SCUXBFSSR1_2SRC0_1 SCUX.BFSSR1_2SRC0_1 +#define SCUXSC2SR1_2SRC0_1 SCUX.SC2SR1_2SRC0_1 +#define SCUXWATSR1_2SRC0_1 SCUX.WATSR1_2SRC0_1 +#define SCUXSEVMR1_2SRC0_1 SCUX.SEVMR1_2SRC0_1 +#define SCUXSEVCR1_2SRC0_1 SCUX.SEVCR1_2SRC0_1 +#define SCUXSRCIRR_2SRC0_1 SCUX.SRCIRR_2SRC0_1 +#define SCUXDVUIR_DVU0_0 SCUX.DVUIR_DVU0_0 +#define SCUXVADIR_DVU0_0 SCUX.VADIR_DVU0_0 +#define SCUXDVUBR_DVU0_0 SCUX.DVUBR_DVU0_0 +#define SCUXDVUCR_DVU0_0 SCUX.DVUCR_DVU0_0 +#define SCUXZCMCR_DVU0_0 SCUX.ZCMCR_DVU0_0 +#define SCUXVRCTR_DVU0_0 SCUX.VRCTR_DVU0_0 +#define SCUXVRPDR_DVU0_0 SCUX.VRPDR_DVU0_0 +#define SCUXVRDBR_DVU0_0 SCUX.VRDBR_DVU0_0 +#define SCUXVRWTR_DVU0_0 SCUX.VRWTR_DVU0_0 +#define SCUXVOL0R_DVU0_0 SCUX.VOL0R_DVU0_0 +#define SCUXVOL1R_DVU0_0 SCUX.VOL1R_DVU0_0 +#define SCUXVOL2R_DVU0_0 SCUX.VOL2R_DVU0_0 +#define SCUXVOL3R_DVU0_0 SCUX.VOL3R_DVU0_0 +#define SCUXVOL4R_DVU0_0 SCUX.VOL4R_DVU0_0 +#define SCUXVOL5R_DVU0_0 SCUX.VOL5R_DVU0_0 +#define SCUXVOL6R_DVU0_0 SCUX.VOL6R_DVU0_0 +#define SCUXVOL7R_DVU0_0 SCUX.VOL7R_DVU0_0 +#define SCUXDVUER_DVU0_0 SCUX.DVUER_DVU0_0 +#define SCUXDVUSR_DVU0_0 SCUX.DVUSR_DVU0_0 +#define SCUXVEVMR_DVU0_0 SCUX.VEVMR_DVU0_0 +#define SCUXVEVCR_DVU0_0 SCUX.VEVCR_DVU0_0 +#define SCUXDVUIR_DVU0_1 SCUX.DVUIR_DVU0_1 +#define SCUXVADIR_DVU0_1 SCUX.VADIR_DVU0_1 +#define SCUXDVUBR_DVU0_1 SCUX.DVUBR_DVU0_1 +#define SCUXDVUCR_DVU0_1 SCUX.DVUCR_DVU0_1 +#define SCUXZCMCR_DVU0_1 SCUX.ZCMCR_DVU0_1 +#define SCUXVRCTR_DVU0_1 SCUX.VRCTR_DVU0_1 +#define SCUXVRPDR_DVU0_1 SCUX.VRPDR_DVU0_1 +#define SCUXVRDBR_DVU0_1 SCUX.VRDBR_DVU0_1 +#define SCUXVRWTR_DVU0_1 SCUX.VRWTR_DVU0_1 +#define SCUXVOL0R_DVU0_1 SCUX.VOL0R_DVU0_1 +#define SCUXVOL1R_DVU0_1 SCUX.VOL1R_DVU0_1 +#define SCUXVOL2R_DVU0_1 SCUX.VOL2R_DVU0_1 +#define SCUXVOL3R_DVU0_1 SCUX.VOL3R_DVU0_1 +#define SCUXVOL4R_DVU0_1 SCUX.VOL4R_DVU0_1 +#define SCUXVOL5R_DVU0_1 SCUX.VOL5R_DVU0_1 +#define SCUXVOL6R_DVU0_1 SCUX.VOL6R_DVU0_1 +#define SCUXVOL7R_DVU0_1 SCUX.VOL7R_DVU0_1 +#define SCUXDVUER_DVU0_1 SCUX.DVUER_DVU0_1 +#define SCUXDVUSR_DVU0_1 SCUX.DVUSR_DVU0_1 +#define SCUXVEVMR_DVU0_1 SCUX.VEVMR_DVU0_1 +#define SCUXVEVCR_DVU0_1 SCUX.VEVCR_DVU0_1 +#define SCUXDVUIR_DVU0_2 SCUX.DVUIR_DVU0_2 +#define SCUXVADIR_DVU0_2 SCUX.VADIR_DVU0_2 +#define SCUXDVUBR_DVU0_2 SCUX.DVUBR_DVU0_2 +#define SCUXDVUCR_DVU0_2 SCUX.DVUCR_DVU0_2 +#define SCUXZCMCR_DVU0_2 SCUX.ZCMCR_DVU0_2 +#define SCUXVRCTR_DVU0_2 SCUX.VRCTR_DVU0_2 +#define SCUXVRPDR_DVU0_2 SCUX.VRPDR_DVU0_2 +#define SCUXVRDBR_DVU0_2 SCUX.VRDBR_DVU0_2 +#define SCUXVRWTR_DVU0_2 SCUX.VRWTR_DVU0_2 +#define SCUXVOL0R_DVU0_2 SCUX.VOL0R_DVU0_2 +#define SCUXVOL1R_DVU0_2 SCUX.VOL1R_DVU0_2 +#define SCUXVOL2R_DVU0_2 SCUX.VOL2R_DVU0_2 +#define SCUXVOL3R_DVU0_2 SCUX.VOL3R_DVU0_2 +#define SCUXVOL4R_DVU0_2 SCUX.VOL4R_DVU0_2 +#define SCUXVOL5R_DVU0_2 SCUX.VOL5R_DVU0_2 +#define SCUXVOL6R_DVU0_2 SCUX.VOL6R_DVU0_2 +#define SCUXVOL7R_DVU0_2 SCUX.VOL7R_DVU0_2 +#define SCUXDVUER_DVU0_2 SCUX.DVUER_DVU0_2 +#define SCUXDVUSR_DVU0_2 SCUX.DVUSR_DVU0_2 +#define SCUXVEVMR_DVU0_2 SCUX.VEVMR_DVU0_2 +#define SCUXVEVCR_DVU0_2 SCUX.VEVCR_DVU0_2 +#define SCUXDVUIR_DVU0_3 SCUX.DVUIR_DVU0_3 +#define SCUXVADIR_DVU0_3 SCUX.VADIR_DVU0_3 +#define SCUXDVUBR_DVU0_3 SCUX.DVUBR_DVU0_3 +#define SCUXDVUCR_DVU0_3 SCUX.DVUCR_DVU0_3 +#define SCUXZCMCR_DVU0_3 SCUX.ZCMCR_DVU0_3 +#define SCUXVRCTR_DVU0_3 SCUX.VRCTR_DVU0_3 +#define SCUXVRPDR_DVU0_3 SCUX.VRPDR_DVU0_3 +#define SCUXVRDBR_DVU0_3 SCUX.VRDBR_DVU0_3 +#define SCUXVRWTR_DVU0_3 SCUX.VRWTR_DVU0_3 +#define SCUXVOL0R_DVU0_3 SCUX.VOL0R_DVU0_3 +#define SCUXVOL1R_DVU0_3 SCUX.VOL1R_DVU0_3 +#define SCUXVOL2R_DVU0_3 SCUX.VOL2R_DVU0_3 +#define SCUXVOL3R_DVU0_3 SCUX.VOL3R_DVU0_3 +#define SCUXVOL4R_DVU0_3 SCUX.VOL4R_DVU0_3 +#define SCUXVOL5R_DVU0_3 SCUX.VOL5R_DVU0_3 +#define SCUXVOL6R_DVU0_3 SCUX.VOL6R_DVU0_3 +#define SCUXVOL7R_DVU0_3 SCUX.VOL7R_DVU0_3 +#define SCUXDVUER_DVU0_3 SCUX.DVUER_DVU0_3 +#define SCUXDVUSR_DVU0_3 SCUX.DVUSR_DVU0_3 +#define SCUXVEVMR_DVU0_3 SCUX.VEVMR_DVU0_3 +#define SCUXVEVCR_DVU0_3 SCUX.VEVCR_DVU0_3 +#define SCUXMIXIR_MIX0_0 SCUX.MIXIR_MIX0_0 +#define SCUXMADIR_MIX0_0 SCUX.MADIR_MIX0_0 +#define SCUXMIXBR_MIX0_0 SCUX.MIXBR_MIX0_0 +#define SCUXMIXMR_MIX0_0 SCUX.MIXMR_MIX0_0 +#define SCUXMVPDR_MIX0_0 SCUX.MVPDR_MIX0_0 +#define SCUXMDBAR_MIX0_0 SCUX.MDBAR_MIX0_0 +#define SCUXMDBBR_MIX0_0 SCUX.MDBBR_MIX0_0 +#define SCUXMDBCR_MIX0_0 SCUX.MDBCR_MIX0_0 +#define SCUXMDBDR_MIX0_0 SCUX.MDBDR_MIX0_0 +#define SCUXMDBER_MIX0_0 SCUX.MDBER_MIX0_0 +#define SCUXMIXSR_MIX0_0 SCUX.MIXSR_MIX0_0 +#define SCUXSWRSR_CIM SCUX.SWRSR_CIM +#define SCUXDMACR_CIM SCUX.DMACR_CIM +#define SCUXDMATD0_CIM SCUX.DMATD0_CIM.UINT32 +#define SCUXDMATD0_CIML SCUX.DMATD0_CIM.UINT16[L] +#define SCUXDMATD0_CIMH SCUX.DMATD0_CIM.UINT16[H] +#define SCUXDMATD1_CIM SCUX.DMATD1_CIM.UINT32 +#define SCUXDMATD1_CIML SCUX.DMATD1_CIM.UINT16[L] +#define SCUXDMATD1_CIMH SCUX.DMATD1_CIM.UINT16[H] +#define SCUXDMATD2_CIM SCUX.DMATD2_CIM.UINT32 +#define SCUXDMATD2_CIML SCUX.DMATD2_CIM.UINT16[L] +#define SCUXDMATD2_CIMH SCUX.DMATD2_CIM.UINT16[H] +#define SCUXDMATD3_CIM SCUX.DMATD3_CIM.UINT32 +#define SCUXDMATD3_CIML SCUX.DMATD3_CIM.UINT16[L] +#define SCUXDMATD3_CIMH SCUX.DMATD3_CIM.UINT16[H] +#define SCUXDMATU0_CIM SCUX.DMATU0_CIM.UINT32 +#define SCUXDMATU0_CIML SCUX.DMATU0_CIM.UINT16[L] +#define SCUXDMATU0_CIMH SCUX.DMATU0_CIM.UINT16[H] +#define SCUXDMATU1_CIM SCUX.DMATU1_CIM.UINT32 +#define SCUXDMATU1_CIML SCUX.DMATU1_CIM.UINT16[L] +#define SCUXDMATU1_CIMH SCUX.DMATU1_CIM.UINT16[H] +#define SCUXDMATU2_CIM SCUX.DMATU2_CIM.UINT32 +#define SCUXDMATU2_CIML SCUX.DMATU2_CIM.UINT16[L] +#define SCUXDMATU2_CIMH SCUX.DMATU2_CIM.UINT16[H] +#define SCUXDMATU3_CIM SCUX.DMATU3_CIM.UINT32 +#define SCUXDMATU3_CIML SCUX.DMATU3_CIM.UINT16[L] +#define SCUXDMATU3_CIMH SCUX.DMATU3_CIM.UINT16[H] +#define SCUXSSIRSEL_CIM SCUX.SSIRSEL_CIM +#define SCUXFDTSEL0_CIM SCUX.FDTSEL0_CIM +#define SCUXFDTSEL1_CIM SCUX.FDTSEL1_CIM +#define SCUXFDTSEL2_CIM SCUX.FDTSEL2_CIM +#define SCUXFDTSEL3_CIM SCUX.FDTSEL3_CIM +#define SCUXFUTSEL0_CIM SCUX.FUTSEL0_CIM +#define SCUXFUTSEL1_CIM SCUX.FUTSEL1_CIM +#define SCUXFUTSEL2_CIM SCUX.FUTSEL2_CIM +#define SCUXFUTSEL3_CIM SCUX.FUTSEL3_CIM +#define SCUXSSIPMD_CIM SCUX.SSIPMD_CIM +#define SCUXSSICTRL_CIM SCUX.SSICTRL_CIM +#define SCUXSRCRSEL0_CIM SCUX.SRCRSEL0_CIM +#define SCUXSRCRSEL1_CIM SCUX.SRCRSEL1_CIM +#define SCUXSRCRSEL2_CIM SCUX.SRCRSEL2_CIM +#define SCUXSRCRSEL3_CIM SCUX.SRCRSEL3_CIM +#define SCUXMIXRSEL_CIM SCUX.MIXRSEL_CIM +/* <-SEC M1.10.1 */ +/* <-QAC 0639 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/sdg_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,86 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : sdg_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef SDG_IODEFINE_H +#define SDG_IODEFINE_H + +struct st_sdg +{ /* SDG */ + volatile uint8_t SGCR1; /* SGCR1 */ + volatile uint8_t SGCSR; /* SGCSR */ + volatile uint8_t SGCR2; /* SGCR2 */ + volatile uint8_t SGLR; /* SGLR */ + volatile uint8_t SGTFR; /* SGTFR */ + volatile uint8_t SGSFR; /* SGSFR */ +}; + + +#define SDG0 (*(struct st_sdg *)0xFCFF4800uL) /* SDG0 */ +#define SDG1 (*(struct st_sdg *)0xFCFF4A00uL) /* SDG1 */ +#define SDG2 (*(struct st_sdg *)0xFCFF4C00uL) /* SDG2 */ +#define SDG3 (*(struct st_sdg *)0xFCFF4E00uL) /* SDG3 */ + + +/* Start of channnel array defines of SDG */ + +/* Channnel array defines of SDG */ +/*(Sample) value = SDG[ channel ]->SGCR1; */ +#define SDG_COUNT 4 +#define SDG_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SDG0, &SDG1, &SDG2, &SDG3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channnel array defines of SDG */ + + +#define SGCR1_0 SDG0.SGCR1 +#define SGCSR_0 SDG0.SGCSR +#define SGCR2_0 SDG0.SGCR2 +#define SGLR_0 SDG0.SGLR +#define SGTFR_0 SDG0.SGTFR +#define SGSFR_0 SDG0.SGSFR +#define SGCR1_1 SDG1.SGCR1 +#define SGCSR_1 SDG1.SGCSR +#define SGCR2_1 SDG1.SGCR2 +#define SGLR_1 SDG1.SGLR +#define SGTFR_1 SDG1.SGTFR +#define SGSFR_1 SDG1.SGSFR +#define SGCR1_2 SDG2.SGCR1 +#define SGCSR_2 SDG2.SGCSR +#define SGCR2_2 SDG2.SGCR2 +#define SGLR_2 SDG2.SGLR +#define SGTFR_2 SDG2.SGTFR +#define SGSFR_2 SDG2.SGSFR +#define SGCR1_3 SDG3.SGCR1 +#define SGCSR_3 SDG3.SGCSR +#define SGCR2_3 SDG3.SGCR2 +#define SGLR_3 SDG3.SGLR +#define SGTFR_3 SDG3.SGTFR +#define SGSFR_3 SDG3.SGSFR +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/spdif_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,68 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : spdif_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef SPDIF_IODEFINE_H +#define SPDIF_IODEFINE_H + +struct st_spdif +{ /* SPDIF */ + volatile uint32_t TLCA; /* TLCA */ + volatile uint32_t TRCA; /* TRCA */ + volatile uint32_t TLCS; /* TLCS */ + volatile uint32_t TRCS; /* TRCS */ + volatile uint32_t TUI; /* TUI */ + volatile uint32_t RLCA; /* RLCA */ + volatile uint32_t RRCA; /* RRCA */ + volatile uint32_t RLCS; /* RLCS */ + volatile uint32_t RRCS; /* RRCS */ + volatile uint32_t RUI; /* RUI */ + volatile uint32_t CTRL; /* CTRL */ + volatile uint32_t STAT; /* STAT */ + volatile uint32_t TDAD; /* TDAD */ + volatile uint32_t RDAD; /* RDAD */ +}; + + +#define SPDIF (*(struct st_spdif *)0xE8012000uL) /* SPDIF */ + + +#define SPDIFTLCA SPDIF.TLCA +#define SPDIFTRCA SPDIF.TRCA +#define SPDIFTLCS SPDIF.TLCS +#define SPDIFTRCS SPDIF.TRCS +#define SPDIFTUI SPDIF.TUI +#define SPDIFRLCA SPDIF.RLCA +#define SPDIFRRCA SPDIF.RRCA +#define SPDIFRLCS SPDIF.RLCS +#define SPDIFRRCS SPDIF.RRCS +#define SPDIFRUI SPDIF.RUI +#define SPDIFCTRL SPDIF.CTRL +#define SPDIFSTAT SPDIF.STAT +#define SPDIFTDAD SPDIF.TDAD +#define SPDIFRDAD SPDIF.RDAD +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/spibsc_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,173 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : spibsc_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef SPIBSC_IODEFINE_H +#define SPIBSC_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_spibsc +{ /* SPIBSC */ + volatile uint32_t CMNCR; /* CMNCR */ + volatile uint32_t SSLDR; /* SSLDR */ + volatile uint32_t SPBCR; /* SPBCR */ + volatile uint32_t DRCR; /* DRCR */ + volatile uint32_t DRCMR; /* DRCMR */ + volatile uint32_t DREAR; /* DREAR */ + volatile uint32_t DROPR; /* DROPR */ + volatile uint32_t DRENR; /* DRENR */ + volatile uint32_t SMCR; /* SMCR */ + volatile uint32_t SMCMR; /* SMCMR */ + volatile uint32_t SMADR; /* SMADR */ + volatile uint32_t SMOPR; /* SMOPR */ + volatile uint32_t SMENR; /* SMENR */ + volatile uint8_t dummy1[4]; /* */ + union iodefine_reg32_t SMRDR0; /* SMRDR0 */ + union iodefine_reg32_t SMRDR1; /* SMRDR1 */ + union iodefine_reg32_t SMWDR0; /* SMWDR0 */ + union iodefine_reg32_t SMWDR1; /* SMWDR1 */ + + volatile uint32_t CMNSR; /* CMNSR */ + volatile uint8_t dummy2[12]; /* */ + volatile uint32_t DRDMCR; /* DRDMCR */ + volatile uint32_t DRDRENR; /* DRDRENR */ + volatile uint32_t SMDMCR; /* SMDMCR */ + volatile uint32_t SMDRENR; /* SMDRENR */ +}; + + +#define SPIBSC0 (*(struct st_spibsc *)0x3FEFA000uL) /* SPIBSC0 */ +#define SPIBSC1 (*(struct st_spibsc *)0x3FEFB000uL) /* SPIBSC1 */ + + +/* Start of channnel array defines of SPIBSC */ + +/* Channnel array defines of SPIBSC */ +/*(Sample) value = SPIBSC[ channel ]->CMNCR; */ +#define SPIBSC_COUNT 2 +#define SPIBSC_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SPIBSC0, &SPIBSC1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channnel array defines of SPIBSC */ + + +#define CMNCR_0 SPIBSC0.CMNCR +#define SSLDR_0 SPIBSC0.SSLDR +#define SPBCR_0 SPIBSC0.SPBCR +#define DRCR_0 SPIBSC0.DRCR +#define DRCMR_0 SPIBSC0.DRCMR +#define DREAR_0 SPIBSC0.DREAR +#define DROPR_0 SPIBSC0.DROPR +#define DRENR_0 SPIBSC0.DRENR +#define SMCR_0 SPIBSC0.SMCR +#define SMCMR_0 SPIBSC0.SMCMR +#define SMADR_0 SPIBSC0.SMADR +#define SMOPR_0 SPIBSC0.SMOPR +#define SMENR_0 SPIBSC0.SMENR +#define SMRDR0_0 SPIBSC0.SMRDR0.UINT32 +#define SMRDR0_0L SPIBSC0.SMRDR0.UINT16[L] +#define SMRDR0_0H SPIBSC0.SMRDR0.UINT16[H] +#define SMRDR0_0LL SPIBSC0.SMRDR0.UINT8[LL] +#define SMRDR0_0LH SPIBSC0.SMRDR0.UINT8[LH] +#define SMRDR0_0HL SPIBSC0.SMRDR0.UINT8[HL] +#define SMRDR0_0HH SPIBSC0.SMRDR0.UINT8[HH] +#define SMRDR1_0 SPIBSC0.SMRDR1.UINT32 +#define SMRDR1_0L SPIBSC0.SMRDR1.UINT16[L] +#define SMRDR1_0H SPIBSC0.SMRDR1.UINT16[H] +#define SMRDR1_0LL SPIBSC0.SMRDR1.UINT8[LL] +#define SMRDR1_0LH SPIBSC0.SMRDR1.UINT8[LH] +#define SMRDR1_0HL SPIBSC0.SMRDR1.UINT8[HL] +#define SMRDR1_0HH SPIBSC0.SMRDR1.UINT8[HH] +#define SMWDR0_0 SPIBSC0.SMWDR0.UINT32 +#define SMWDR0_0L SPIBSC0.SMWDR0.UINT16[L] +#define SMWDR0_0H SPIBSC0.SMWDR0.UINT16[H] +#define SMWDR0_0LL SPIBSC0.SMWDR0.UINT8[LL] +#define SMWDR0_0LH SPIBSC0.SMWDR0.UINT8[LH] +#define SMWDR0_0HL SPIBSC0.SMWDR0.UINT8[HL] +#define SMWDR0_0HH SPIBSC0.SMWDR0.UINT8[HH] +#define SMWDR1_0 SPIBSC0.SMWDR1.UINT32 +#define SMWDR1_0L SPIBSC0.SMWDR1.UINT16[L] +#define SMWDR1_0H SPIBSC0.SMWDR1.UINT16[H] +#define SMWDR1_0LL SPIBSC0.SMWDR1.UINT8[LL] +#define SMWDR1_0LH SPIBSC0.SMWDR1.UINT8[LH] +#define SMWDR1_0HL SPIBSC0.SMWDR1.UINT8[HL] +#define SMWDR1_0HH SPIBSC0.SMWDR1.UINT8[HH] +#define CMNSR_0 SPIBSC0.CMNSR +#define DRDMCR_0 SPIBSC0.DRDMCR +#define DRDRENR_0 SPIBSC0.DRDRENR +#define SMDMCR_0 SPIBSC0.SMDMCR +#define SMDRENR_0 SPIBSC0.SMDRENR +#define CMNCR_1 SPIBSC1.CMNCR +#define SSLDR_1 SPIBSC1.SSLDR +#define SPBCR_1 SPIBSC1.SPBCR +#define DRCR_1 SPIBSC1.DRCR +#define DRCMR_1 SPIBSC1.DRCMR +#define DREAR_1 SPIBSC1.DREAR +#define DROPR_1 SPIBSC1.DROPR +#define DRENR_1 SPIBSC1.DRENR +#define SMCR_1 SPIBSC1.SMCR +#define SMCMR_1 SPIBSC1.SMCMR +#define SMADR_1 SPIBSC1.SMADR +#define SMOPR_1 SPIBSC1.SMOPR +#define SMENR_1 SPIBSC1.SMENR +#define SMRDR0_1 SPIBSC1.SMRDR0.UINT32 +#define SMRDR0_1L SPIBSC1.SMRDR0.UINT16[L] +#define SMRDR0_1H SPIBSC1.SMRDR0.UINT16[H] +#define SMRDR0_1LL SPIBSC1.SMRDR0.UINT8[LL] +#define SMRDR0_1LH SPIBSC1.SMRDR0.UINT8[LH] +#define SMRDR0_1HL SPIBSC1.SMRDR0.UINT8[HL] +#define SMRDR0_1HH SPIBSC1.SMRDR0.UINT8[HH] +#define SMRDR1_1 SPIBSC1.SMRDR1.UINT32 +#define SMRDR1_1L SPIBSC1.SMRDR1.UINT16[L] +#define SMRDR1_1H SPIBSC1.SMRDR1.UINT16[H] +#define SMRDR1_1LL SPIBSC1.SMRDR1.UINT8[LL] +#define SMRDR1_1LH SPIBSC1.SMRDR1.UINT8[LH] +#define SMRDR1_1HL SPIBSC1.SMRDR1.UINT8[HL] +#define SMRDR1_1HH SPIBSC1.SMRDR1.UINT8[HH] +#define SMWDR0_1 SPIBSC1.SMWDR0.UINT32 +#define SMWDR0_1L SPIBSC1.SMWDR0.UINT16[L] +#define SMWDR0_1H SPIBSC1.SMWDR0.UINT16[H] +#define SMWDR0_1LL SPIBSC1.SMWDR0.UINT8[LL] +#define SMWDR0_1LH SPIBSC1.SMWDR0.UINT8[LH] +#define SMWDR0_1HL SPIBSC1.SMWDR0.UINT8[HL] +#define SMWDR0_1HH SPIBSC1.SMWDR0.UINT8[HH] +#define SMWDR1_1 SPIBSC1.SMWDR1.UINT32 +#define SMWDR1_1L SPIBSC1.SMWDR1.UINT16[L] +#define SMWDR1_1H SPIBSC1.SMWDR1.UINT16[H] +#define SMWDR1_1LL SPIBSC1.SMWDR1.UINT8[LL] +#define SMWDR1_1LH SPIBSC1.SMWDR1.UINT8[LH] +#define SMWDR1_1HL SPIBSC1.SMWDR1.UINT8[HL] +#define SMWDR1_1HH SPIBSC1.SMWDR1.UINT8[HH] +#define CMNSR_1 SPIBSC1.CMNSR +#define DRDMCR_1 SPIBSC1.DRDMCR +#define DRDRENR_1 SPIBSC1.DRDRENR +#define SMDMCR_1 SPIBSC1.SMDMCR +#define SMDRENR_1 SPIBSC1.SMDRENR +/* <-SEC M1.10.1 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/ssif_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,131 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : ssif_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef SSIF_IODEFINE_H +#define SSIF_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_ssif +{ /* SSIF */ + volatile uint32_t SSICR; /* SSICR */ + volatile uint32_t SSISR; /* SSISR */ + volatile uint8_t dummy1[8]; /* */ + volatile uint32_t SSIFCR; /* SSIFCR */ + volatile uint32_t SSIFSR; /* SSIFSR */ + volatile uint32_t SSIFTDR; /* SSIFTDR */ + volatile uint32_t SSIFRDR; /* SSIFRDR */ + volatile uint32_t SSITDMR; /* SSITDMR */ + volatile uint32_t SSIFCCR; /* SSIFCCR */ + volatile uint32_t SSIFCMR; /* SSIFCMR */ + volatile uint32_t SSIFCSR; /* SSIFCSR */ +}; + + +#define SSIF0 (*(struct st_ssif *)0xE820B000uL) /* SSIF0 */ +#define SSIF1 (*(struct st_ssif *)0xE820B800uL) /* SSIF1 */ +#define SSIF2 (*(struct st_ssif *)0xE820C000uL) /* SSIF2 */ +#define SSIF3 (*(struct st_ssif *)0xE820C800uL) /* SSIF3 */ +#define SSIF4 (*(struct st_ssif *)0xE820D000uL) /* SSIF4 */ +#define SSIF5 (*(struct st_ssif *)0xE820D800uL) /* SSIF5 */ + + +/* Start of channnel array defines of SSIF */ + +/* Channnel array defines of SSIF */ +/*(Sample) value = SSIF[ channel ]->SSICR; */ +#define SSIF_COUNT 6 +#define SSIF_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SSIF0, &SSIF1, &SSIF2, &SSIF3, &SSIF4, &SSIF5 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channnel array defines of SSIF */ + + +#define SSICR_0 SSIF0.SSICR +#define SSISR_0 SSIF0.SSISR +#define SSIFCR_0 SSIF0.SSIFCR +#define SSIFSR_0 SSIF0.SSIFSR +#define SSIFTDR_0 SSIF0.SSIFTDR +#define SSIFRDR_0 SSIF0.SSIFRDR +#define SSITDMR_0 SSIF0.SSITDMR +#define SSIFCCR_0 SSIF0.SSIFCCR +#define SSIFCMR_0 SSIF0.SSIFCMR +#define SSIFCSR_0 SSIF0.SSIFCSR +#define SSICR_1 SSIF1.SSICR +#define SSISR_1 SSIF1.SSISR +#define SSIFCR_1 SSIF1.SSIFCR +#define SSIFSR_1 SSIF1.SSIFSR +#define SSIFTDR_1 SSIF1.SSIFTDR +#define SSIFRDR_1 SSIF1.SSIFRDR +#define SSITDMR_1 SSIF1.SSITDMR +#define SSIFCCR_1 SSIF1.SSIFCCR +#define SSIFCMR_1 SSIF1.SSIFCMR +#define SSIFCSR_1 SSIF1.SSIFCSR +#define SSICR_2 SSIF2.SSICR +#define SSISR_2 SSIF2.SSISR +#define SSIFCR_2 SSIF2.SSIFCR +#define SSIFSR_2 SSIF2.SSIFSR +#define SSIFTDR_2 SSIF2.SSIFTDR +#define SSIFRDR_2 SSIF2.SSIFRDR +#define SSITDMR_2 SSIF2.SSITDMR +#define SSIFCCR_2 SSIF2.SSIFCCR +#define SSIFCMR_2 SSIF2.SSIFCMR +#define SSIFCSR_2 SSIF2.SSIFCSR +#define SSICR_3 SSIF3.SSICR +#define SSISR_3 SSIF3.SSISR +#define SSIFCR_3 SSIF3.SSIFCR +#define SSIFSR_3 SSIF3.SSIFSR +#define SSIFTDR_3 SSIF3.SSIFTDR +#define SSIFRDR_3 SSIF3.SSIFRDR +#define SSITDMR_3 SSIF3.SSITDMR +#define SSIFCCR_3 SSIF3.SSIFCCR +#define SSIFCMR_3 SSIF3.SSIFCMR +#define SSIFCSR_3 SSIF3.SSIFCSR +#define SSICR_4 SSIF4.SSICR +#define SSISR_4 SSIF4.SSISR +#define SSIFCR_4 SSIF4.SSIFCR +#define SSIFSR_4 SSIF4.SSIFSR +#define SSIFTDR_4 SSIF4.SSIFTDR +#define SSIFRDR_4 SSIF4.SSIFRDR +#define SSITDMR_4 SSIF4.SSITDMR +#define SSIFCCR_4 SSIF4.SSIFCCR +#define SSIFCMR_4 SSIF4.SSIFCMR +#define SSIFCSR_4 SSIF4.SSIFCSR +#define SSICR_5 SSIF5.SSICR +#define SSISR_5 SSIF5.SSISR +#define SSIFCR_5 SSIF5.SSIFCR +#define SSIFSR_5 SSIF5.SSIFSR +#define SSIFTDR_5 SSIF5.SSIFTDR +#define SSIFRDR_5 SSIF5.SSIFRDR +#define SSITDMR_5 SSIF5.SSITDMR +#define SSIFCCR_5 SSIF5.SSIFCCR +#define SSIFCMR_5 SSIF5.SSIFCMR +#define SSIFCSR_5 SSIF5.SSIFCSR +/* <-SEC M1.10.1 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/usb20_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,546 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb20_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef USB20_IODEFINE_H +#define USB20_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_usb20 +{ /* USB20 */ + volatile uint16_t SYSCFG0; /* SYSCFG0 */ + volatile uint16_t BUSWAIT; /* BUSWAIT */ + volatile uint16_t SYSSTS0; /* SYSSTS0 */ + volatile uint8_t dummy1[2]; /* */ + volatile uint16_t DVSTCTR0; /* DVSTCTR0 */ + volatile uint8_t dummy2[2]; /* */ + volatile uint16_t TESTMODE; /* TESTMODE */ + volatile uint8_t dummy3[2]; /* */ +#define USB20_D0FBCFG_COUNT 2 + volatile uint16_t D0FBCFG; /* D0FBCFG */ + volatile uint16_t D1FBCFG; /* D1FBCFG */ + union iodefine_reg32_t CFIFO; /* CFIFO */ +#define USB20_D0FIFO_COUNT 2 + union iodefine_reg32_t D0FIFO; /* D0FIFO */ + union iodefine_reg32_t D1FIFO; /* D1FIFO */ + + volatile uint16_t CFIFOSEL; /* CFIFOSEL */ + volatile uint16_t CFIFOCTR; /* CFIFOCTR */ + volatile uint8_t dummy4[4]; /* */ +/* start of struct st_usb20_from_d0fifosel */ + volatile uint16_t D0FIFOSEL; /* D0FIFOSEL */ + volatile uint16_t D0FIFOCTR; /* D0FIFOCTR */ +/* end of struct st_usb20_from_d0fifosel */ +/* start of struct st_usb20_from_d0fifosel */ + volatile uint16_t D1FIFOSEL; /* D1FIFOSEL */ + volatile uint16_t D1FIFOCTR; /* D1FIFOCTR */ +/* end of struct st_usb20_from_d0fifosel */ +#define USB20_INTENB0_COUNT 2 + volatile uint16_t INTENB0; /* INTENB0 */ + volatile uint16_t INTENB1; /* INTENB1 */ + volatile uint8_t dummy5[2]; /* */ + volatile uint16_t BRDYENB; /* BRDYENB */ + volatile uint16_t NRDYENB; /* NRDYENB */ + volatile uint16_t BEMPENB; /* BEMPENB */ + volatile uint16_t SOFCFG; /* SOFCFG */ + volatile uint8_t dummy6[2]; /* */ +#define USB20_INTSTS0_COUNT 2 + volatile uint16_t INTSTS0; /* INTSTS0 */ + volatile uint16_t INTSTS1; /* INTSTS1 */ + volatile uint8_t dummy7[2]; /* */ + volatile uint16_t BRDYSTS; /* BRDYSTS */ + volatile uint16_t NRDYSTS; /* NRDYSTS */ + volatile uint16_t BEMPSTS; /* BEMPSTS */ + volatile uint16_t FRMNUM; /* FRMNUM */ + volatile uint16_t UFRMNUM; /* UFRMNUM */ + volatile uint16_t USBADDR; /* USBADDR */ + volatile uint8_t dummy8[2]; /* */ + volatile uint16_t USBREQ; /* USBREQ */ + volatile uint16_t USBVAL; /* USBVAL */ + volatile uint16_t USBINDX; /* USBINDX */ + volatile uint16_t USBLENG; /* USBLENG */ + volatile uint16_t DCPCFG; /* DCPCFG */ + volatile uint16_t DCPMAXP; /* DCPMAXP */ + volatile uint16_t DCPCTR; /* DCPCTR */ + volatile uint8_t dummy9[2]; /* */ + volatile uint16_t PIPESEL; /* PIPESEL */ + volatile uint8_t dummy10[2]; /* */ + volatile uint16_t PIPECFG; /* PIPECFG */ + volatile uint16_t PIPEBUF; /* PIPEBUF */ + volatile uint16_t PIPEMAXP; /* PIPEMAXP */ + volatile uint16_t PIPEPERI; /* PIPEPERI */ +#define USB20_PIPE1CTR_COUNT 0xF + volatile uint16_t PIPE1CTR; /* PIPE1CTR */ + volatile uint16_t PIPE2CTR; /* PIPE2CTR */ + volatile uint16_t PIPE3CTR; /* PIPE3CTR */ + volatile uint16_t PIPE4CTR; /* PIPE4CTR */ + volatile uint16_t PIPE5CTR; /* PIPE5CTR */ + volatile uint16_t PIPE6CTR; /* PIPE6CTR */ + volatile uint16_t PIPE7CTR; /* PIPE7CTR */ + volatile uint16_t PIPE8CTR; /* PIPE8CTR */ + volatile uint16_t PIPE9CTR; /* PIPE9CTR */ + volatile uint16_t PIPEACTR; /* PIPEACTR */ + volatile uint16_t PIPEBCTR; /* PIPEBCTR */ + volatile uint16_t PIPECCTR; /* PIPECCTR */ + volatile uint16_t PIPEDCTR; /* PIPEDCTR */ + volatile uint16_t PIPEECTR; /* PIPEECTR */ + volatile uint16_t PIPEFCTR; /* PIPEFCTR */ + volatile uint8_t dummy11[2]; /* */ +/* start of struct st_usb20_from_pipe1tre */ + volatile uint16_t PIPE1TRE; /* PIPE1TRE */ + volatile uint16_t PIPE1TRN; /* PIPE1TRN */ +/* end of struct st_usb20_from_pipe1tre */ +/* start of struct st_usb20_from_pipe1tre */ + volatile uint16_t PIPE2TRE; /* PIPE2TRE */ + volatile uint16_t PIPE2TRN; /* PIPE2TRN */ +/* end of struct st_usb20_from_pipe1tre */ +/* start of struct st_usb20_from_pipe1tre */ + volatile uint16_t PIPE3TRE; /* PIPE3TRE */ + volatile uint16_t PIPE3TRN; /* PIPE3TRN */ +/* end of struct st_usb20_from_pipe1tre */ +/* start of struct st_usb20_from_pipe1tre */ + volatile uint16_t PIPE4TRE; /* PIPE4TRE */ + volatile uint16_t PIPE4TRN; /* PIPE4TRN */ +/* end of struct st_usb20_from_pipe1tre */ +/* start of struct st_usb20_from_pipe1tre */ + volatile uint16_t PIPE5TRE; /* PIPE5TRE */ + volatile uint16_t PIPE5TRN; /* PIPE5TRN */ +/* end of struct st_usb20_from_pipe1tre */ + volatile uint16_t PIPEBTRE; /* PIPEBTRE */ + volatile uint16_t PIPEBTRN; /* PIPEBTRN */ + volatile uint16_t PIPECTRE; /* PIPECTRE */ + volatile uint16_t PIPECTRN; /* PIPECTRN */ + volatile uint16_t PIPEDTRE; /* PIPEDTRE */ + volatile uint16_t PIPEDTRN; /* PIPEDTRN */ + volatile uint16_t PIPEETRE; /* PIPEETRE */ + volatile uint16_t PIPEETRN; /* PIPEETRN */ + volatile uint16_t PIPEFTRE; /* PIPEFTRE */ + volatile uint16_t PIPEFTRN; /* PIPEFTRN */ + volatile uint16_t PIPE9TRE; /* PIPE9TRE */ + volatile uint16_t PIPE9TRN; /* PIPE9TRN */ + volatile uint16_t PIPEATRE; /* PIPEATRE */ + volatile uint16_t PIPEATRN; /* PIPEATRN */ + volatile uint8_t dummy12[16]; /* */ +#define USB20_DEVADD0_COUNT 0xB + volatile uint16_t DEVADD0; /* DEVADD0 */ + volatile uint16_t DEVADD1; /* DEVADD1 */ + volatile uint16_t DEVADD2; /* DEVADD2 */ + volatile uint16_t DEVADD3; /* DEVADD3 */ + volatile uint16_t DEVADD4; /* DEVADD4 */ + volatile uint16_t DEVADD5; /* DEVADD5 */ + volatile uint16_t DEVADD6; /* DEVADD6 */ + volatile uint16_t DEVADD7; /* DEVADD7 */ + volatile uint16_t DEVADD8; /* DEVADD8 */ + volatile uint16_t DEVADD9; /* DEVADD9 */ + volatile uint16_t DEVADDA; /* DEVADDA */ + volatile uint8_t dummy13[28]; /* */ + volatile uint16_t SUSPMODE; /* SUSPMODE */ + volatile uint8_t dummy14[92]; /* */ +/* start of struct st_usb20_from_dmfifob0 */ + volatile uint32_t D0FIFOB0; /* D0FIFOB0 */ + volatile uint32_t D0FIFOB1; /* D0FIFOB1 */ + volatile uint32_t D0FIFOB2; /* D0FIFOB2 */ + volatile uint32_t D0FIFOB3; /* D0FIFOB3 */ + volatile uint32_t D0FIFOB4; /* D0FIFOB4 */ + volatile uint32_t D0FIFOB5; /* D0FIFOB5 */ + volatile uint32_t D0FIFOB6; /* D0FIFOB6 */ + volatile uint32_t D0FIFOB7; /* D0FIFOB7 */ +/* end of struct st_usb20_from_dmfifob0 */ +/* start of struct st_usb20_from_dmfifob0 */ + volatile uint32_t D1FIFOB0; /* D1FIFOB0 */ + volatile uint32_t D1FIFOB1; /* D1FIFOB1 */ + volatile uint32_t D1FIFOB2; /* D1FIFOB2 */ + volatile uint32_t D1FIFOB3; /* D1FIFOB3 */ + volatile uint32_t D1FIFOB4; /* D1FIFOB4 */ + volatile uint32_t D1FIFOB5; /* D1FIFOB5 */ + volatile uint32_t D1FIFOB6; /* D1FIFOB6 */ + volatile uint32_t D1FIFOB7; /* D1FIFOB7 */ +/* end of struct st_usb20_from_dmfifob0 */ +}; + + +struct st_usb20_from_d0fifosel +{ + volatile uint16_t D0FIFOSEL; /* D0FIFOSEL */ + volatile uint16_t D0FIFOCTR; /* D0FIFOCTR */ +}; + + +struct st_usb20_from_pipe1tre +{ + volatile uint16_t PIPE1TRE; /* PIPE1TRE */ + volatile uint16_t PIPE1TRN; /* PIPE1TRN */ +}; + + +struct st_usb20_from_dmfifob0 +{ +#define USB20_D0FIFOB0_COUNT 0x8 + volatile uint32_t D0FIFOB0; /* D0FIFOB0 */ + volatile uint32_t D0FIFOB1; /* D0FIFOB1 */ + volatile uint32_t D0FIFOB2; /* D0FIFOB2 */ + volatile uint32_t D0FIFOB3; /* D0FIFOB3 */ + volatile uint32_t D0FIFOB4; /* D0FIFOB4 */ + volatile uint32_t D0FIFOB5; /* D0FIFOB5 */ + volatile uint32_t D0FIFOB6; /* D0FIFOB6 */ + volatile uint32_t D0FIFOB7; /* D0FIFOB7 */ +}; + + +#define USB200 (*(struct st_usb20 *)0xE8010000uL) /* USB200 */ +#define USB201 (*(struct st_usb20 *)0xE8207000uL) /* USB201 */ + + +/* Start of channnel array defines of USB20 */ + +/* Channnel array defines of USB20 */ +/*(Sample) value = USB20[ channel ]->SYSCFG0; */ +#define USB20_COUNT 2 +#define USB20_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &USB200, &USB201 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + + + +/* Channnel array defines of USB20_FROM_D0FIFOB0 */ +/*(Sample) value = USB20_FROM_D0FIFOB0[ channel ][ index ]->D0FIFOB0; */ +#define USB20_FROM_D0FIFOB0_COUNT 2 +#define USB20_FROM_D0FIFOB0_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &USB200_FROM_D0FIFOB0, &USB200_FROM_D1FIFOB0 },{ \ + &USB201_FROM_D0FIFOB0, &USB201_FROM_D1FIFOB0 \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define USB200_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D0FIFOB0) /* USB200_FROM_D0FIFOB0 */ +#define USB200_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D1FIFOB0) /* USB200_FROM_D1FIFOB0 */ +#define USB201_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D0FIFOB0) /* USB201_FROM_D0FIFOB0 */ +#define USB201_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D1FIFOB0) /* USB201_FROM_D1FIFOB0 */ + + + + +/* Channnel array defines of USB20_FROM_PIPE1ATRE */ +/*(Sample) value = USB20_FROM_PIPE1ATRE[ channel ][ index ]->PIPE1TRE; */ +#define USB20_FROM_PIPE1ATRE_COUNT 5 +#define USB20_FROM_PIPE1ATRE_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &USB200_FROM_PIPE1TRE, &USB200_FROM_PIPE2TRE, &USB200_FROM_PIPE3TRE, &USB200_FROM_PIPE4TRE, &USB200_FROM_PIPE5TRE },{ \ + &USB201_FROM_PIPE1TRE, &USB201_FROM_PIPE2TRE, &USB201_FROM_PIPE3TRE, &USB201_FROM_PIPE4TRE, &USB201_FROM_PIPE5TRE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define USB200_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE1TRE) /* USB200_FROM_PIPE1TRE */ +#define USB200_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE2TRE) /* USB200_FROM_PIPE2TRE */ +#define USB200_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE3TRE) /* USB200_FROM_PIPE3TRE */ +#define USB200_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE4TRE) /* USB200_FROM_PIPE4TRE */ +#define USB200_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE5TRE) /* USB200_FROM_PIPE5TRE */ +#define USB201_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE1TRE) /* USB201_FROM_PIPE1TRE */ +#define USB201_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE2TRE) /* USB201_FROM_PIPE2TRE */ +#define USB201_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE3TRE) /* USB201_FROM_PIPE3TRE */ +#define USB201_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE4TRE) /* USB201_FROM_PIPE4TRE */ +#define USB201_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE5TRE) /* USB201_FROM_PIPE5TRE */ + + + + +/* Channnel array defines of USB20_FROM_D0FIFOSEL */ +/*(Sample) value = USB20_FROM_D0FIFOSEL[ channel ][ index ]->D0FIFOSEL; */ +#define USB20_FROM_D0FIFOSEL_COUNT 2 +#define USB20_FROM_D0FIFOSEL_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &USB200_FROM_D0FIFOSEL, &USB200_FROM_D1FIFOSEL },{ \ + &USB201_FROM_D0FIFOSEL, &USB201_FROM_D1FIFOSEL \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define USB200_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D0FIFOSEL) /* USB200_FROM_D0FIFOSEL */ +#define USB200_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D1FIFOSEL) /* USB200_FROM_D1FIFOSEL */ +#define USB201_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D0FIFOSEL) /* USB201_FROM_D0FIFOSEL */ +#define USB201_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D1FIFOSEL) /* USB201_FROM_D1FIFOSEL */ + + +/* End of channnel array defines of USB20 */ + + +#define SYSCFG0_0 USB200.SYSCFG0 +#define BUSWAIT_0 USB200.BUSWAIT +#define SYSSTS0_0 USB200.SYSSTS0 +#define DVSTCTR0_0 USB200.DVSTCTR0 +#define TESTMODE_0 USB200.TESTMODE +#define D0FBCFG_0 USB200.D0FBCFG +#define D1FBCFG_0 USB200.D1FBCFG +#define CFIFO_0 USB200.CFIFO.UINT32 +#define CFIFO_0L USB200.CFIFO.UINT16[L] +#define CFIFO_0H USB200.CFIFO.UINT16[H] +#define CFIFO_0LL USB200.CFIFO.UINT8[LL] +#define CFIFO_0LH USB200.CFIFO.UINT8[LH] +#define CFIFO_0HL USB200.CFIFO.UINT8[HL] +#define CFIFO_0HH USB200.CFIFO.UINT8[HH] +#define D0FIFO_0 USB200.D0FIFO.UINT32 +#define D0FIFO_0L USB200.D0FIFO.UINT16[L] +#define D0FIFO_0H USB200.D0FIFO.UINT16[H] +#define D0FIFO_0LL USB200.D0FIFO.UINT8[LL] +#define D0FIFO_0LH USB200.D0FIFO.UINT8[LH] +#define D0FIFO_0HL USB200.D0FIFO.UINT8[HL] +#define D0FIFO_0HH USB200.D0FIFO.UINT8[HH] +#define D1FIFO_0 USB200.D1FIFO.UINT32 +#define D1FIFO_0L USB200.D1FIFO.UINT16[L] +#define D1FIFO_0H USB200.D1FIFO.UINT16[H] +#define D1FIFO_0LL USB200.D1FIFO.UINT8[LL] +#define D1FIFO_0LH USB200.D1FIFO.UINT8[LH] +#define D1FIFO_0HL USB200.D1FIFO.UINT8[HL] +#define D1FIFO_0HH USB200.D1FIFO.UINT8[HH] +#define CFIFOSEL_0 USB200.CFIFOSEL +#define CFIFOCTR_0 USB200.CFIFOCTR +#define D0FIFOSEL_0 USB200.D0FIFOSEL +#define D0FIFOCTR_0 USB200.D0FIFOCTR +#define D1FIFOSEL_0 USB200.D1FIFOSEL +#define D1FIFOCTR_0 USB200.D1FIFOCTR +#define INTENB0_0 USB200.INTENB0 +#define INTENB1_0 USB200.INTENB1 +#define BRDYENB_0 USB200.BRDYENB +#define NRDYENB_0 USB200.NRDYENB +#define BEMPENB_0 USB200.BEMPENB +#define SOFCFG_0 USB200.SOFCFG +#define INTSTS0_0 USB200.INTSTS0 +#define INTSTS1_0 USB200.INTSTS1 +#define BRDYSTS_0 USB200.BRDYSTS +#define NRDYSTS_0 USB200.NRDYSTS +#define BEMPSTS_0 USB200.BEMPSTS +#define FRMNUM_0 USB200.FRMNUM +#define UFRMNUM_0 USB200.UFRMNUM +#define USBADDR_0 USB200.USBADDR +#define USBREQ_0 USB200.USBREQ +#define USBVAL_0 USB200.USBVAL +#define USBINDX_0 USB200.USBINDX +#define USBLENG_0 USB200.USBLENG +#define DCPCFG_0 USB200.DCPCFG +#define DCPMAXP_0 USB200.DCPMAXP +#define DCPCTR_0 USB200.DCPCTR +#define PIPESEL_0 USB200.PIPESEL +#define PIPECFG_0 USB200.PIPECFG +#define PIPEBUF_0 USB200.PIPEBUF +#define PIPEMAXP_0 USB200.PIPEMAXP +#define PIPEPERI_0 USB200.PIPEPERI +#define PIPE1CTR_0 USB200.PIPE1CTR +#define PIPE2CTR_0 USB200.PIPE2CTR +#define PIPE3CTR_0 USB200.PIPE3CTR +#define PIPE4CTR_0 USB200.PIPE4CTR +#define PIPE5CTR_0 USB200.PIPE5CTR +#define PIPE6CTR_0 USB200.PIPE6CTR +#define PIPE7CTR_0 USB200.PIPE7CTR +#define PIPE8CTR_0 USB200.PIPE8CTR +#define PIPE9CTR_0 USB200.PIPE9CTR +#define PIPEACTR_0 USB200.PIPEACTR +#define PIPEBCTR_0 USB200.PIPEBCTR +#define PIPECCTR_0 USB200.PIPECCTR +#define PIPEDCTR_0 USB200.PIPEDCTR +#define PIPEECTR_0 USB200.PIPEECTR +#define PIPEFCTR_0 USB200.PIPEFCTR +#define PIPE1TRE_0 USB200.PIPE1TRE +#define PIPE1TRN_0 USB200.PIPE1TRN +#define PIPE2TRE_0 USB200.PIPE2TRE +#define PIPE2TRN_0 USB200.PIPE2TRN +#define PIPE3TRE_0 USB200.PIPE3TRE +#define PIPE3TRN_0 USB200.PIPE3TRN +#define PIPE4TRE_0 USB200.PIPE4TRE +#define PIPE4TRN_0 USB200.PIPE4TRN +#define PIPE5TRE_0 USB200.PIPE5TRE +#define PIPE5TRN_0 USB200.PIPE5TRN +#define PIPEBTRE_0 USB200.PIPEBTRE +#define PIPEBTRN_0 USB200.PIPEBTRN +#define PIPECTRE_0 USB200.PIPECTRE +#define PIPECTRN_0 USB200.PIPECTRN +#define PIPEDTRE_0 USB200.PIPEDTRE +#define PIPEDTRN_0 USB200.PIPEDTRN +#define PIPEETRE_0 USB200.PIPEETRE +#define PIPEETRN_0 USB200.PIPEETRN +#define PIPEFTRE_0 USB200.PIPEFTRE +#define PIPEFTRN_0 USB200.PIPEFTRN +#define PIPE9TRE_0 USB200.PIPE9TRE +#define PIPE9TRN_0 USB200.PIPE9TRN +#define PIPEATRE_0 USB200.PIPEATRE +#define PIPEATRN_0 USB200.PIPEATRN +#define DEVADD0_0 USB200.DEVADD0 +#define DEVADD1_0 USB200.DEVADD1 +#define DEVADD2_0 USB200.DEVADD2 +#define DEVADD3_0 USB200.DEVADD3 +#define DEVADD4_0 USB200.DEVADD4 +#define DEVADD5_0 USB200.DEVADD5 +#define DEVADD6_0 USB200.DEVADD6 +#define DEVADD7_0 USB200.DEVADD7 +#define DEVADD8_0 USB200.DEVADD8 +#define DEVADD9_0 USB200.DEVADD9 +#define DEVADDA_0 USB200.DEVADDA +#define SUSPMODE_0 USB200.SUSPMODE +#define D0FIFOB0_0 USB200.D0FIFOB0 +#define D0FIFOB1_0 USB200.D0FIFOB1 +#define D0FIFOB2_0 USB200.D0FIFOB2 +#define D0FIFOB3_0 USB200.D0FIFOB3 +#define D0FIFOB4_0 USB200.D0FIFOB4 +#define D0FIFOB5_0 USB200.D0FIFOB5 +#define D0FIFOB6_0 USB200.D0FIFOB6 +#define D0FIFOB7_0 USB200.D0FIFOB7 +#define D1FIFOB0_0 USB200.D1FIFOB0 +#define D1FIFOB1_0 USB200.D1FIFOB1 +#define D1FIFOB2_0 USB200.D1FIFOB2 +#define D1FIFOB3_0 USB200.D1FIFOB3 +#define D1FIFOB4_0 USB200.D1FIFOB4 +#define D1FIFOB5_0 USB200.D1FIFOB5 +#define D1FIFOB6_0 USB200.D1FIFOB6 +#define D1FIFOB7_0 USB200.D1FIFOB7 +#define SYSCFG0_1 USB201.SYSCFG0 +#define BUSWAIT_1 USB201.BUSWAIT +#define SYSSTS0_1 USB201.SYSSTS0 +#define DVSTCTR0_1 USB201.DVSTCTR0 +#define TESTMODE_1 USB201.TESTMODE +#define D0FBCFG_1 USB201.D0FBCFG +#define D1FBCFG_1 USB201.D1FBCFG +#define CFIFO_1 USB201.CFIFO.UINT32 +#define CFIFO_1L USB201.CFIFO.UINT16[L] +#define CFIFO_1H USB201.CFIFO.UINT16[H] +#define CFIFO_1LL USB201.CFIFO.UINT8[LL] +#define CFIFO_1LH USB201.CFIFO.UINT8[LH] +#define CFIFO_1HL USB201.CFIFO.UINT8[HL] +#define CFIFO_1HH USB201.CFIFO.UINT8[HH] +#define D0FIFO_1 USB201.D0FIFO.UINT32 +#define D0FIFO_1L USB201.D0FIFO.UINT16[L] +#define D0FIFO_1H USB201.D0FIFO.UINT16[H] +#define D0FIFO_1LL USB201.D0FIFO.UINT8[LL] +#define D0FIFO_1LH USB201.D0FIFO.UINT8[LH] +#define D0FIFO_1HL USB201.D0FIFO.UINT8[HL] +#define D0FIFO_1HH USB201.D0FIFO.UINT8[HH] +#define D1FIFO_1 USB201.D1FIFO.UINT32 +#define D1FIFO_1L USB201.D1FIFO.UINT16[L] +#define D1FIFO_1H USB201.D1FIFO.UINT16[H] +#define D1FIFO_1LL USB201.D1FIFO.UINT8[LL] +#define D1FIFO_1LH USB201.D1FIFO.UINT8[LH] +#define D1FIFO_1HL USB201.D1FIFO.UINT8[HL] +#define D1FIFO_1HH USB201.D1FIFO.UINT8[HH] +#define CFIFOSEL_1 USB201.CFIFOSEL +#define CFIFOCTR_1 USB201.CFIFOCTR +#define D0FIFOSEL_1 USB201.D0FIFOSEL +#define D0FIFOCTR_1 USB201.D0FIFOCTR +#define D1FIFOSEL_1 USB201.D1FIFOSEL +#define D1FIFOCTR_1 USB201.D1FIFOCTR +#define INTENB0_1 USB201.INTENB0 +#define INTENB1_1 USB201.INTENB1 +#define BRDYENB_1 USB201.BRDYENB +#define NRDYENB_1 USB201.NRDYENB +#define BEMPENB_1 USB201.BEMPENB +#define SOFCFG_1 USB201.SOFCFG +#define INTSTS0_1 USB201.INTSTS0 +#define INTSTS1_1 USB201.INTSTS1 +#define BRDYSTS_1 USB201.BRDYSTS +#define NRDYSTS_1 USB201.NRDYSTS +#define BEMPSTS_1 USB201.BEMPSTS +#define FRMNUM_1 USB201.FRMNUM +#define UFRMNUM_1 USB201.UFRMNUM +#define USBADDR_1 USB201.USBADDR +#define USBREQ_1 USB201.USBREQ +#define USBVAL_1 USB201.USBVAL +#define USBINDX_1 USB201.USBINDX +#define USBLENG_1 USB201.USBLENG +#define DCPCFG_1 USB201.DCPCFG +#define DCPMAXP_1 USB201.DCPMAXP +#define DCPCTR_1 USB201.DCPCTR +#define PIPESEL_1 USB201.PIPESEL +#define PIPECFG_1 USB201.PIPECFG +#define PIPEBUF_1 USB201.PIPEBUF +#define PIPEMAXP_1 USB201.PIPEMAXP +#define PIPEPERI_1 USB201.PIPEPERI +#define PIPE1CTR_1 USB201.PIPE1CTR +#define PIPE2CTR_1 USB201.PIPE2CTR +#define PIPE3CTR_1 USB201.PIPE3CTR +#define PIPE4CTR_1 USB201.PIPE4CTR +#define PIPE5CTR_1 USB201.PIPE5CTR +#define PIPE6CTR_1 USB201.PIPE6CTR +#define PIPE7CTR_1 USB201.PIPE7CTR +#define PIPE8CTR_1 USB201.PIPE8CTR +#define PIPE9CTR_1 USB201.PIPE9CTR +#define PIPEACTR_1 USB201.PIPEACTR +#define PIPEBCTR_1 USB201.PIPEBCTR +#define PIPECCTR_1 USB201.PIPECCTR +#define PIPEDCTR_1 USB201.PIPEDCTR +#define PIPEECTR_1 USB201.PIPEECTR +#define PIPEFCTR_1 USB201.PIPEFCTR +#define PIPE1TRE_1 USB201.PIPE1TRE +#define PIPE1TRN_1 USB201.PIPE1TRN +#define PIPE2TRE_1 USB201.PIPE2TRE +#define PIPE2TRN_1 USB201.PIPE2TRN +#define PIPE3TRE_1 USB201.PIPE3TRE +#define PIPE3TRN_1 USB201.PIPE3TRN +#define PIPE4TRE_1 USB201.PIPE4TRE +#define PIPE4TRN_1 USB201.PIPE4TRN +#define PIPE5TRE_1 USB201.PIPE5TRE +#define PIPE5TRN_1 USB201.PIPE5TRN +#define PIPEBTRE_1 USB201.PIPEBTRE +#define PIPEBTRN_1 USB201.PIPEBTRN +#define PIPECTRE_1 USB201.PIPECTRE +#define PIPECTRN_1 USB201.PIPECTRN +#define PIPEDTRE_1 USB201.PIPEDTRE +#define PIPEDTRN_1 USB201.PIPEDTRN +#define PIPEETRE_1 USB201.PIPEETRE +#define PIPEETRN_1 USB201.PIPEETRN +#define PIPEFTRE_1 USB201.PIPEFTRE +#define PIPEFTRN_1 USB201.PIPEFTRN +#define PIPE9TRE_1 USB201.PIPE9TRE +#define PIPE9TRN_1 USB201.PIPE9TRN +#define PIPEATRE_1 USB201.PIPEATRE +#define PIPEATRN_1 USB201.PIPEATRN +#define DEVADD0_1 USB201.DEVADD0 +#define DEVADD1_1 USB201.DEVADD1 +#define DEVADD2_1 USB201.DEVADD2 +#define DEVADD3_1 USB201.DEVADD3 +#define DEVADD4_1 USB201.DEVADD4 +#define DEVADD5_1 USB201.DEVADD5 +#define DEVADD6_1 USB201.DEVADD6 +#define DEVADD7_1 USB201.DEVADD7 +#define DEVADD8_1 USB201.DEVADD8 +#define DEVADD9_1 USB201.DEVADD9 +#define DEVADDA_1 USB201.DEVADDA +#define SUSPMODE_1 USB201.SUSPMODE +#define D0FIFOB0_1 USB201.D0FIFOB0 +#define D0FIFOB1_1 USB201.D0FIFOB1 +#define D0FIFOB2_1 USB201.D0FIFOB2 +#define D0FIFOB3_1 USB201.D0FIFOB3 +#define D0FIFOB4_1 USB201.D0FIFOB4 +#define D0FIFOB5_1 USB201.D0FIFOB5 +#define D0FIFOB6_1 USB201.D0FIFOB6 +#define D0FIFOB7_1 USB201.D0FIFOB7 +#define D1FIFOB0_1 USB201.D1FIFOB0 +#define D1FIFOB1_1 USB201.D1FIFOB1 +#define D1FIFOB2_1 USB201.D1FIFOB2 +#define D1FIFOB3_1 USB201.D1FIFOB3 +#define D1FIFOB4_1 USB201.D1FIFOB4 +#define D1FIFOB5_1 USB201.D1FIFOB5 +#define D1FIFOB6_1 USB201.D1FIFOB6 +#define D1FIFOB7_1 USB201.D1FIFOB7 +/* <-SEC M1.10.1 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/vdc5_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,1596 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : vdc5_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef VDC5_IODEFINE_H +#define VDC5_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->SEC M1.10.1 : Not magic number */ + +struct st_vdc5 +{ /* VDC5 */ + volatile uint32_t INP_UPDATE; /* INP_UPDATE */ + volatile uint32_t INP_SEL_CNT; /* INP_SEL_CNT */ + volatile uint32_t INP_EXT_SYNC_CNT; /* INP_EXT_SYNC_CNT */ + volatile uint32_t INP_VSYNC_PH_ADJ; /* INP_VSYNC_PH_ADJ */ + volatile uint32_t INP_DLY_ADJ; /* INP_DLY_ADJ */ + volatile uint8_t dummy1[108]; /* */ + volatile uint32_t IMGCNT_UPDATE; /* IMGCNT_UPDATE */ +#define VDC5_IMGCNT_NR_CNT0_COUNT 2 + volatile uint32_t IMGCNT_NR_CNT0; /* IMGCNT_NR_CNT0 */ + volatile uint32_t IMGCNT_NR_CNT1; /* IMGCNT_NR_CNT1 */ + volatile uint8_t dummy2[20]; /* */ + volatile uint32_t IMGCNT_MTX_MODE; /* IMGCNT_MTX_MODE */ + volatile uint32_t IMGCNT_MTX_YG_ADJ0; /* IMGCNT_MTX_YG_ADJ0 */ + volatile uint32_t IMGCNT_MTX_YG_ADJ1; /* IMGCNT_MTX_YG_ADJ1 */ + volatile uint32_t IMGCNT_MTX_CBB_ADJ0; /* IMGCNT_MTX_CBB_ADJ0 */ + volatile uint32_t IMGCNT_MTX_CBB_ADJ1; /* IMGCNT_MTX_CBB_ADJ1 */ + volatile uint32_t IMGCNT_MTX_CRR_ADJ0; /* IMGCNT_MTX_CRR_ADJ0 */ + volatile uint32_t IMGCNT_MTX_CRR_ADJ1; /* IMGCNT_MTX_CRR_ADJ1 */ + volatile uint8_t dummy3[4]; /* */ + volatile uint32_t IMGCNT_DRC_REG; /* IMGCNT_DRC_REG */ + volatile uint8_t dummy4[60]; /* */ +/* start of struct st_vdc5_from_sc0_scl0_update */ + volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */ +#define VDC5_SC0_SCL0_FRC1_COUNT 7 + volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */ + volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */ + volatile uint32_t SC0_SCL0_FRC3; /* SC0_SCL0_FRC3 */ + volatile uint32_t SC0_SCL0_FRC4; /* SC0_SCL0_FRC4 */ + volatile uint32_t SC0_SCL0_FRC5; /* SC0_SCL0_FRC5 */ + volatile uint32_t SC0_SCL0_FRC6; /* SC0_SCL0_FRC6 */ + volatile uint32_t SC0_SCL0_FRC7; /* SC0_SCL0_FRC7 */ + volatile uint8_t dummy5[4]; /* */ + volatile uint32_t SC0_SCL0_FRC9; /* SC0_SCL0_FRC9 */ + volatile uint16_t SC0_SCL0_MON0; /* SC0_SCL0_MON0 */ + volatile uint16_t SC0_SCL0_INT; /* SC0_SCL0_INT */ +#define VDC5_SC0_SCL0_DS1_COUNT 7 + volatile uint32_t SC0_SCL0_DS1; /* SC0_SCL0_DS1 */ + volatile uint32_t SC0_SCL0_DS2; /* SC0_SCL0_DS2 */ + volatile uint32_t SC0_SCL0_DS3; /* SC0_SCL0_DS3 */ + volatile uint32_t SC0_SCL0_DS4; /* SC0_SCL0_DS4 */ + volatile uint32_t SC0_SCL0_DS5; /* SC0_SCL0_DS5 */ + volatile uint32_t SC0_SCL0_DS6; /* SC0_SCL0_DS6 */ + volatile uint32_t SC0_SCL0_DS7; /* SC0_SCL0_DS7 */ +#define VDC5_SC0_SCL0_US1_COUNT 8 + volatile uint32_t SC0_SCL0_US1; /* SC0_SCL0_US1 */ + volatile uint32_t SC0_SCL0_US2; /* SC0_SCL0_US2 */ + volatile uint32_t SC0_SCL0_US3; /* SC0_SCL0_US3 */ + volatile uint32_t SC0_SCL0_US4; /* SC0_SCL0_US4 */ + volatile uint32_t SC0_SCL0_US5; /* SC0_SCL0_US5 */ + volatile uint32_t SC0_SCL0_US6; /* SC0_SCL0_US6 */ + volatile uint32_t SC0_SCL0_US7; /* SC0_SCL0_US7 */ + volatile uint32_t SC0_SCL0_US8; /* SC0_SCL0_US8 */ + volatile uint8_t dummy6[4]; /* */ + volatile uint32_t SC0_SCL0_OVR1; /* SC0_SCL0_OVR1 */ + volatile uint8_t dummy7[16]; /* */ + volatile uint32_t SC0_SCL1_UPDATE; /* SC0_SCL1_UPDATE */ + volatile uint8_t dummy8[4]; /* */ +#define VDC5_SC0_SCL1_WR1_COUNT 4 + volatile uint32_t SC0_SCL1_WR1; /* SC0_SCL1_WR1 */ + volatile uint32_t SC0_SCL1_WR2; /* SC0_SCL1_WR2 */ + volatile uint32_t SC0_SCL1_WR3; /* SC0_SCL1_WR3 */ + volatile uint32_t SC0_SCL1_WR4; /* SC0_SCL1_WR4 */ + volatile uint8_t dummy9[4]; /* */ + volatile uint32_t SC0_SCL1_WR5; /* SC0_SCL1_WR5 */ + volatile uint32_t SC0_SCL1_WR6; /* SC0_SCL1_WR6 */ + volatile uint32_t SC0_SCL1_WR7; /* SC0_SCL1_WR7 */ + volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */ + volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */ + volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */ +/* end of struct st_vdc5_from_sc0_scl0_update */ + volatile uint32_t SC0_SCL1_WR11; /* SC0_SCL1_WR11 */ + volatile uint32_t SC0_SCL1_MON1; /* SC0_SCL1_MON1 */ +/* start of struct st_vdc5_from_sc0_scl1_pbuf0 */ +#define VDC5_SC0_SCL1_PBUF0_COUNT 4 + volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */ + volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */ + volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */ + volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */ + volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */ + volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */ +/* end of struct st_vdc5_from_sc0_scl1_pbuf0 */ + volatile uint8_t dummy10[44]; /* */ +/* start of struct st_vdc5_from_gr0_update */ + volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */ + volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */ +#define VDC5_GR0_FLM1_COUNT 6 + volatile uint32_t GR0_FLM1; /* GR0_FLM1 */ + volatile uint32_t GR0_FLM2; /* GR0_FLM2 */ + volatile uint32_t GR0_FLM3; /* GR0_FLM3 */ + volatile uint32_t GR0_FLM4; /* GR0_FLM4 */ + volatile uint32_t GR0_FLM5; /* GR0_FLM5 */ + volatile uint32_t GR0_FLM6; /* GR0_FLM6 */ +#define VDC5_GR0_AB1_COUNT 3 + volatile uint32_t GR0_AB1; /* GR0_AB1 */ + volatile uint32_t GR0_AB2; /* GR0_AB2 */ + volatile uint32_t GR0_AB3; /* GR0_AB3 */ +/* end of struct st_vdc5_from_gr0_update */ + volatile uint8_t dummy11[12]; /* */ +/* start of struct st_vdc5_from_gr0_ab7 */ + volatile uint32_t GR0_AB7; /* GR0_AB7 */ + volatile uint32_t GR0_AB8; /* GR0_AB8 */ + volatile uint32_t GR0_AB9; /* GR0_AB9 */ + volatile uint32_t GR0_AB10; /* GR0_AB10 */ + volatile uint32_t GR0_AB11; /* GR0_AB11 */ + volatile uint32_t GR0_BASE; /* GR0_BASE */ +/* end of struct st_vdc5_from_gr0_ab7 */ + volatile uint32_t GR0_CLUT; /* GR0_CLUT */ + volatile uint8_t dummy12[44]; /* */ +/* start of struct st_vdc5_from_adj0_update */ + volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */ + volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */ +#define VDC5_ADJ0_ENH_TIM1_COUNT 3 + volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */ + volatile uint32_t ADJ0_ENH_TIM2; /* ADJ0_ENH_TIM2 */ + volatile uint32_t ADJ0_ENH_TIM3; /* ADJ0_ENH_TIM3 */ +#define VDC5_ADJ0_ENH_SHP1_COUNT 6 + volatile uint32_t ADJ0_ENH_SHP1; /* ADJ0_ENH_SHP1 */ + volatile uint32_t ADJ0_ENH_SHP2; /* ADJ0_ENH_SHP2 */ + volatile uint32_t ADJ0_ENH_SHP3; /* ADJ0_ENH_SHP3 */ + volatile uint32_t ADJ0_ENH_SHP4; /* ADJ0_ENH_SHP4 */ + volatile uint32_t ADJ0_ENH_SHP5; /* ADJ0_ENH_SHP5 */ + volatile uint32_t ADJ0_ENH_SHP6; /* ADJ0_ENH_SHP6 */ +#define VDC5_ADJ0_ENH_LTI1_COUNT 2 + volatile uint32_t ADJ0_ENH_LTI1; /* ADJ0_ENH_LTI1 */ + volatile uint32_t ADJ0_ENH_LTI2; /* ADJ0_ENH_LTI2 */ + volatile uint32_t ADJ0_MTX_MODE; /* ADJ0_MTX_MODE */ + volatile uint32_t ADJ0_MTX_YG_ADJ0; /* ADJ0_MTX_YG_ADJ0 */ + volatile uint32_t ADJ0_MTX_YG_ADJ1; /* ADJ0_MTX_YG_ADJ1 */ + volatile uint32_t ADJ0_MTX_CBB_ADJ0; /* ADJ0_MTX_CBB_ADJ0 */ + volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */ + volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */ + volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */ +/* end of struct st_vdc5_from_adj0_update */ + volatile uint8_t dummy13[48]; /* */ +/* start of struct st_vdc5_from_gr0_update */ + volatile uint32_t GR2_UPDATE; /* GR2_UPDATE */ + volatile uint32_t GR2_FLM_RD; /* GR2_FLM_RD */ +#define VDC5_GR2_FLM1_COUNT 6 + volatile uint32_t GR2_FLM1; /* GR2_FLM1 */ + volatile uint32_t GR2_FLM2; /* GR2_FLM2 */ + volatile uint32_t GR2_FLM3; /* GR2_FLM3 */ + volatile uint32_t GR2_FLM4; /* GR2_FLM4 */ + volatile uint32_t GR2_FLM5; /* GR2_FLM5 */ + volatile uint32_t GR2_FLM6; /* GR2_FLM6 */ +#define VDC5_GR2_AB1_COUNT 3 + volatile uint32_t GR2_AB1; /* GR2_AB1 */ + volatile uint32_t GR2_AB2; /* GR2_AB2 */ + volatile uint32_t GR2_AB3; /* GR2_AB3 */ +/* end of struct st_vdc5_from_gr0_update */ + volatile uint32_t GR2_AB4; /* GR2_AB4 */ + volatile uint32_t GR2_AB5; /* GR2_AB5 */ + volatile uint32_t GR2_AB6; /* GR2_AB6 */ +/* start of struct st_vdc5_from_gr0_ab7 */ + volatile uint32_t GR2_AB7; /* GR2_AB7 */ + volatile uint32_t GR2_AB8; /* GR2_AB8 */ + volatile uint32_t GR2_AB9; /* GR2_AB9 */ + volatile uint32_t GR2_AB10; /* GR2_AB10 */ + volatile uint32_t GR2_AB11; /* GR2_AB11 */ + volatile uint32_t GR2_BASE; /* GR2_BASE */ +/* end of struct st_vdc5_from_gr0_ab7 */ + volatile uint32_t GR2_CLUT; /* GR2_CLUT */ + volatile uint32_t GR2_MON; /* GR2_MON */ + volatile uint8_t dummy14[40]; /* */ +/* start of struct st_vdc5_from_gr0_update */ + volatile uint32_t GR3_UPDATE; /* GR3_UPDATE */ + volatile uint32_t GR3_FLM_RD; /* GR3_FLM_RD */ +#define VDC5_GR3_FLM1_COUNT 6 + volatile uint32_t GR3_FLM1; /* GR3_FLM1 */ + volatile uint32_t GR3_FLM2; /* GR3_FLM2 */ + volatile uint32_t GR3_FLM3; /* GR3_FLM3 */ + volatile uint32_t GR3_FLM4; /* GR3_FLM4 */ + volatile uint32_t GR3_FLM5; /* GR3_FLM5 */ + volatile uint32_t GR3_FLM6; /* GR3_FLM6 */ +#define VDC5_GR3_AB1_COUNT 3 + volatile uint32_t GR3_AB1; /* GR3_AB1 */ + volatile uint32_t GR3_AB2; /* GR3_AB2 */ + volatile uint32_t GR3_AB3; /* GR3_AB3 */ +/* end of struct st_vdc5_from_gr0_update */ + volatile uint32_t GR3_AB4; /* GR3_AB4 */ + volatile uint32_t GR3_AB5; /* GR3_AB5 */ + volatile uint32_t GR3_AB6; /* GR3_AB6 */ +/* start of struct st_vdc5_from_gr0_ab7 */ + volatile uint32_t GR3_AB7; /* GR3_AB7 */ + volatile uint32_t GR3_AB8; /* GR3_AB8 */ + volatile uint32_t GR3_AB9; /* GR3_AB9 */ + volatile uint32_t GR3_AB10; /* GR3_AB10 */ + volatile uint32_t GR3_AB11; /* GR3_AB11 */ + volatile uint32_t GR3_BASE; /* GR3_BASE */ +/* end of struct st_vdc5_from_gr0_ab7 */ + volatile uint32_t GR3_CLUT_INT; /* GR3_CLUT_INT */ + volatile uint32_t GR3_MON; /* GR3_MON */ + volatile uint8_t dummy15[40]; /* */ + volatile uint32_t GAM_G_UPDATE; /* GAM_G_UPDATE */ + volatile uint32_t GAM_SW; /* GAM_SW */ +#define VDC5_GAM_G_LUT1_COUNT 16 + volatile uint32_t GAM_G_LUT1; /* GAM_G_LUT1 */ + volatile uint32_t GAM_G_LUT2; /* GAM_G_LUT2 */ + volatile uint32_t GAM_G_LUT3; /* GAM_G_LUT3 */ + volatile uint32_t GAM_G_LUT4; /* GAM_G_LUT4 */ + volatile uint32_t GAM_G_LUT5; /* GAM_G_LUT5 */ + volatile uint32_t GAM_G_LUT6; /* GAM_G_LUT6 */ + volatile uint32_t GAM_G_LUT7; /* GAM_G_LUT7 */ + volatile uint32_t GAM_G_LUT8; /* GAM_G_LUT8 */ + volatile uint32_t GAM_G_LUT9; /* GAM_G_LUT9 */ + volatile uint32_t GAM_G_LUT10; /* GAM_G_LUT10 */ + volatile uint32_t GAM_G_LUT11; /* GAM_G_LUT11 */ + volatile uint32_t GAM_G_LUT12; /* GAM_G_LUT12 */ + volatile uint32_t GAM_G_LUT13; /* GAM_G_LUT13 */ + volatile uint32_t GAM_G_LUT14; /* GAM_G_LUT14 */ + volatile uint32_t GAM_G_LUT15; /* GAM_G_LUT15 */ + volatile uint32_t GAM_G_LUT16; /* GAM_G_LUT16 */ +#define VDC5_GAM_G_AREA1_COUNT 8 + volatile uint32_t GAM_G_AREA1; /* GAM_G_AREA1 */ + volatile uint32_t GAM_G_AREA2; /* GAM_G_AREA2 */ + volatile uint32_t GAM_G_AREA3; /* GAM_G_AREA3 */ + volatile uint32_t GAM_G_AREA4; /* GAM_G_AREA4 */ + volatile uint32_t GAM_G_AREA5; /* GAM_G_AREA5 */ + volatile uint32_t GAM_G_AREA6; /* GAM_G_AREA6 */ + volatile uint32_t GAM_G_AREA7; /* GAM_G_AREA7 */ + volatile uint32_t GAM_G_AREA8; /* GAM_G_AREA8 */ + volatile uint8_t dummy16[24]; /* */ + volatile uint32_t GAM_B_UPDATE; /* GAM_B_UPDATE */ + volatile uint8_t dummy17[4]; /* */ +#define VDC5_GAM_B_LUT1_COUNT 16 + volatile uint32_t GAM_B_LUT1; /* GAM_B_LUT1 */ + volatile uint32_t GAM_B_LUT2; /* GAM_B_LUT2 */ + volatile uint32_t GAM_B_LUT3; /* GAM_B_LUT3 */ + volatile uint32_t GAM_B_LUT4; /* GAM_B_LUT4 */ + volatile uint32_t GAM_B_LUT5; /* GAM_B_LUT5 */ + volatile uint32_t GAM_B_LUT6; /* GAM_B_LUT6 */ + volatile uint32_t GAM_B_LUT7; /* GAM_B_LUT7 */ + volatile uint32_t GAM_B_LUT8; /* GAM_B_LUT8 */ + volatile uint32_t GAM_B_LUT9; /* GAM_B_LUT9 */ + volatile uint32_t GAM_B_LUT10; /* GAM_B_LUT10 */ + volatile uint32_t GAM_B_LUT11; /* GAM_B_LUT11 */ + volatile uint32_t GAM_B_LUT12; /* GAM_B_LUT12 */ + volatile uint32_t GAM_B_LUT13; /* GAM_B_LUT13 */ + volatile uint32_t GAM_B_LUT14; /* GAM_B_LUT14 */ + volatile uint32_t GAM_B_LUT15; /* GAM_B_LUT15 */ + volatile uint32_t GAM_B_LUT16; /* GAM_B_LUT16 */ +#define VDC5_GAM_B_AREA1_COUNT 8 + volatile uint32_t GAM_B_AREA1; /* GAM_B_AREA1 */ + volatile uint32_t GAM_B_AREA2; /* GAM_B_AREA2 */ + volatile uint32_t GAM_B_AREA3; /* GAM_B_AREA3 */ + volatile uint32_t GAM_B_AREA4; /* GAM_B_AREA4 */ + volatile uint32_t GAM_B_AREA5; /* GAM_B_AREA5 */ + volatile uint32_t GAM_B_AREA6; /* GAM_B_AREA6 */ + volatile uint32_t GAM_B_AREA7; /* GAM_B_AREA7 */ + volatile uint32_t GAM_B_AREA8; /* GAM_B_AREA8 */ + volatile uint8_t dummy18[24]; /* */ + volatile uint32_t GAM_R_UPDATE; /* GAM_R_UPDATE */ + volatile uint8_t dummy19[4]; /* */ +#define VDC5_GAM_R_LUT1_COUNT 16 + volatile uint32_t GAM_R_LUT1; /* GAM_R_LUT1 */ + volatile uint32_t GAM_R_LUT2; /* GAM_R_LUT2 */ + volatile uint32_t GAM_R_LUT3; /* GAM_R_LUT3 */ + volatile uint32_t GAM_R_LUT4; /* GAM_R_LUT4 */ + volatile uint32_t GAM_R_LUT5; /* GAM_R_LUT5 */ + volatile uint32_t GAM_R_LUT6; /* GAM_R_LUT6 */ + volatile uint32_t GAM_R_LUT7; /* GAM_R_LUT7 */ + volatile uint32_t GAM_R_LUT8; /* GAM_R_LUT8 */ + volatile uint32_t GAM_R_LUT9; /* GAM_R_LUT9 */ + volatile uint32_t GAM_R_LUT10; /* GAM_R_LUT10 */ + volatile uint32_t GAM_R_LUT11; /* GAM_R_LUT11 */ + volatile uint32_t GAM_R_LUT12; /* GAM_R_LUT12 */ + volatile uint32_t GAM_R_LUT13; /* GAM_R_LUT13 */ + volatile uint32_t GAM_R_LUT14; /* GAM_R_LUT14 */ + volatile uint32_t GAM_R_LUT15; /* GAM_R_LUT15 */ + volatile uint32_t GAM_R_LUT16; /* GAM_R_LUT16 */ +#define VDC5_GAM_R_AREA1_COUNT 8 + volatile uint32_t GAM_R_AREA1; /* GAM_R_AREA1 */ + volatile uint32_t GAM_R_AREA2; /* GAM_R_AREA2 */ + volatile uint32_t GAM_R_AREA3; /* GAM_R_AREA3 */ + volatile uint32_t GAM_R_AREA4; /* GAM_R_AREA4 */ + volatile uint32_t GAM_R_AREA5; /* GAM_R_AREA5 */ + volatile uint32_t GAM_R_AREA6; /* GAM_R_AREA6 */ + volatile uint32_t GAM_R_AREA7; /* GAM_R_AREA7 */ + volatile uint32_t GAM_R_AREA8; /* GAM_R_AREA8 */ + volatile uint8_t dummy20[24]; /* */ + volatile uint32_t TCON_UPDATE; /* TCON_UPDATE */ + volatile uint32_t TCON_TIM; /* TCON_TIM */ +#define VDC5_TCON_TIM_STVA1_COUNT 2 + volatile uint32_t TCON_TIM_STVA1; /* TCON_TIM_STVA1 */ + volatile uint32_t TCON_TIM_STVA2; /* TCON_TIM_STVA2 */ +#define VDC5_TCON_TIM_STVB1_COUNT 2 + volatile uint32_t TCON_TIM_STVB1; /* TCON_TIM_STVB1 */ + volatile uint32_t TCON_TIM_STVB2; /* TCON_TIM_STVB2 */ +#define VDC5_TCON_TIM_STH1_COUNT 2 + volatile uint32_t TCON_TIM_STH1; /* TCON_TIM_STH1 */ + volatile uint32_t TCON_TIM_STH2; /* TCON_TIM_STH2 */ +#define VDC5_TCON_TIM_STB1_COUNT 2 + volatile uint32_t TCON_TIM_STB1; /* TCON_TIM_STB1 */ + volatile uint32_t TCON_TIM_STB2; /* TCON_TIM_STB2 */ +#define VDC5_TCON_TIM_CPV1_COUNT 2 + volatile uint32_t TCON_TIM_CPV1; /* TCON_TIM_CPV1 */ + volatile uint32_t TCON_TIM_CPV2; /* TCON_TIM_CPV2 */ +#define VDC5_TCON_TIM_POLA1_COUNT 2 + volatile uint32_t TCON_TIM_POLA1; /* TCON_TIM_POLA1 */ + volatile uint32_t TCON_TIM_POLA2; /* TCON_TIM_POLA2 */ +#define VDC5_TCON_TIM_POLB1_COUNT 2 + volatile uint32_t TCON_TIM_POLB1; /* TCON_TIM_POLB1 */ + volatile uint32_t TCON_TIM_POLB2; /* TCON_TIM_POLB2 */ + volatile uint32_t TCON_TIM_DE; /* TCON_TIM_DE */ + volatile uint8_t dummy21[60]; /* */ + volatile uint32_t OUT_UPDATE; /* OUT_UPDATE */ + volatile uint32_t OUT_SET; /* OUT_SET */ +#define VDC5_OUT_BRIGHT1_COUNT 2 + volatile uint32_t OUT_BRIGHT1; /* OUT_BRIGHT1 */ + volatile uint32_t OUT_BRIGHT2; /* OUT_BRIGHT2 */ + volatile uint32_t OUT_CONTRAST; /* OUT_CONTRAST */ + volatile uint32_t OUT_PDTHA; /* OUT_PDTHA */ + volatile uint8_t dummy22[12]; /* */ + volatile uint32_t OUT_CLK_PHASE; /* OUT_CLK_PHASE */ + volatile uint8_t dummy23[88]; /* */ +#define VDC5_SYSCNT_INT1_COUNT 6 + volatile uint32_t SYSCNT_INT1; /* SYSCNT_INT1 */ + volatile uint32_t SYSCNT_INT2; /* SYSCNT_INT2 */ + volatile uint32_t SYSCNT_INT3; /* SYSCNT_INT3 */ + volatile uint32_t SYSCNT_INT4; /* SYSCNT_INT4 */ + volatile uint32_t SYSCNT_INT5; /* SYSCNT_INT5 */ + volatile uint32_t SYSCNT_INT6; /* SYSCNT_INT6 */ + volatile uint16_t SYSCNT_PANEL_CLK; /* SYSCNT_PANEL_CLK */ + volatile uint16_t SYSCNT_CLUT; /* SYSCNT_CLUT */ + volatile uint8_t dummy24[356]; /* */ +/* start of struct st_vdc5_from_sc0_scl0_update */ + volatile uint32_t SC1_SCL0_UPDATE; /* SC1_SCL0_UPDATE */ +#define VDC5_SC1_SCL0_FRC1_COUNT 7 + volatile uint32_t SC1_SCL0_FRC1; /* SC1_SCL0_FRC1 */ + volatile uint32_t SC1_SCL0_FRC2; /* SC1_SCL0_FRC2 */ + volatile uint32_t SC1_SCL0_FRC3; /* SC1_SCL0_FRC3 */ + volatile uint32_t SC1_SCL0_FRC4; /* SC1_SCL0_FRC4 */ + volatile uint32_t SC1_SCL0_FRC5; /* SC1_SCL0_FRC5 */ + volatile uint32_t SC1_SCL0_FRC6; /* SC1_SCL0_FRC6 */ + volatile uint32_t SC1_SCL0_FRC7; /* SC1_SCL0_FRC7 */ + volatile uint8_t dummy25[4]; /* */ + volatile uint32_t SC1_SCL0_FRC9; /* SC1_SCL0_FRC9 */ + volatile uint16_t SC1_SCL0_MON0; /* SC1_SCL0_MON0 */ + volatile uint16_t SC1_SCL0_INT; /* SC1_SCL0_INT */ +#define VDC5_SC1_SC1_SCL0_DS1_COUNT 7 + volatile uint32_t SC1_SCL0_DS1; /* SC1_SCL0_DS1 */ + volatile uint32_t SC1_SCL0_DS2; /* SC1_SCL0_DS2 */ + volatile uint32_t SC1_SCL0_DS3; /* SC1_SCL0_DS3 */ + volatile uint32_t SC1_SCL0_DS4; /* SC1_SCL0_DS4 */ + volatile uint32_t SC1_SCL0_DS5; /* SC1_SCL0_DS5 */ + volatile uint32_t SC1_SCL0_DS6; /* SC1_SCL0_DS6 */ + volatile uint32_t SC1_SCL0_DS7; /* SC1_SCL0_DS7 */ +#define VDC5_SC1_SC1_SCL0_US1_COUNT 8 + volatile uint32_t SC1_SCL0_US1; /* SC1_SCL0_US1 */ + volatile uint32_t SC1_SCL0_US2; /* SC1_SCL0_US2 */ + volatile uint32_t SC1_SCL0_US3; /* SC1_SCL0_US3 */ + volatile uint32_t SC1_SCL0_US4; /* SC1_SCL0_US4 */ + volatile uint32_t SC1_SCL0_US5; /* SC1_SCL0_US5 */ + volatile uint32_t SC1_SCL0_US6; /* SC1_SCL0_US6 */ + volatile uint32_t SC1_SCL0_US7; /* SC1_SCL0_US7 */ + volatile uint32_t SC1_SCL0_US8; /* SC1_SCL0_US8 */ + volatile uint8_t dummy26[4]; /* */ + volatile uint32_t SC1_SCL0_OVR1; /* SC1_SCL0_OVR1 */ + volatile uint8_t dummy27[16]; /* */ + volatile uint32_t SC1_SCL1_UPDATE; /* SC1_SCL1_UPDATE */ + volatile uint8_t dummy28[4]; /* */ +#define VDC5_SC1_SCL1_WR1_COUNT 4 + volatile uint32_t SC1_SCL1_WR1; /* SC1_SCL1_WR1 */ + volatile uint32_t SC1_SCL1_WR2; /* SC1_SCL1_WR2 */ + volatile uint32_t SC1_SCL1_WR3; /* SC1_SCL1_WR3 */ + volatile uint32_t SC1_SCL1_WR4; /* SC1_SCL1_WR4 */ + volatile uint8_t dummy29[4]; /* */ + volatile uint32_t SC1_SCL1_WR5; /* SC1_SCL1_WR5 */ + volatile uint32_t SC1_SCL1_WR6; /* SC1_SCL1_WR6 */ + volatile uint32_t SC1_SCL1_WR7; /* SC1_SCL1_WR7 */ + volatile uint32_t SC1_SCL1_WR8; /* SC1_SCL1_WR8 */ + volatile uint32_t SC1_SCL1_WR9; /* SC1_SCL1_WR9 */ + volatile uint32_t SC1_SCL1_WR10; /* SC1_SCL1_WR10 */ +/* end of struct st_vdc5_from_sc0_scl0_update */ + volatile uint32_t SC1_SCL1_WR11; /* SC1_SCL1_WR11 */ + volatile uint32_t SC1_SCL1_MON1; /* SC1_SCL1_MON1 */ +/* start of struct st_vdc5_from_sc0_scl1_pbuf0 */ +#define VDC5_SC1_SCL1_PBUF0_COUNT 4 + volatile uint32_t SC1_SCL1_PBUF0; /* SC1_SCL1_PBUF0 */ + volatile uint32_t SC1_SCL1_PBUF1; /* SC1_SCL1_PBUF1 */ + volatile uint32_t SC1_SCL1_PBUF2; /* SC1_SCL1_PBUF2 */ + volatile uint32_t SC1_SCL1_PBUF3; /* SC1_SCL1_PBUF3 */ + volatile uint32_t SC1_SCL1_PBUF_FLD; /* SC1_SCL1_PBUF_FLD */ + volatile uint32_t SC1_SCL1_PBUF_CNT; /* SC1_SCL1_PBUF_CNT */ +/* end of struct st_vdc5_from_sc0_scl1_pbuf0 */ + volatile uint8_t dummy30[44]; /* */ +/* start of struct st_vdc5_from_gr0_update */ + volatile uint32_t GR1_UPDATE; /* GR1_UPDATE */ + volatile uint32_t GR1_FLM_RD; /* GR1_FLM_RD */ +#define VDC5_GR1_FLM1_COUNT 6 + volatile uint32_t GR1_FLM1; /* GR1_FLM1 */ + volatile uint32_t GR1_FLM2; /* GR1_FLM2 */ + volatile uint32_t GR1_FLM3; /* GR1_FLM3 */ + volatile uint32_t GR1_FLM4; /* GR1_FLM4 */ + volatile uint32_t GR1_FLM5; /* GR1_FLM5 */ + volatile uint32_t GR1_FLM6; /* GR1_FLM6 */ +#define VDC5_GR1_AB1_COUNT 3 + volatile uint32_t GR1_AB1; /* GR1_AB1 */ + volatile uint32_t GR1_AB2; /* GR1_AB2 */ + volatile uint32_t GR1_AB3; /* GR1_AB3 */ +/* end of struct st_vdc5_from_gr0_update */ + volatile uint32_t GR1_AB4; /* GR1_AB4 */ + volatile uint32_t GR1_AB5; /* GR1_AB5 */ + volatile uint32_t GR1_AB6; /* GR1_AB6 */ +/* start of struct st_vdc5_from_gr0_ab7 */ + volatile uint32_t GR1_AB7; /* GR1_AB7 */ + volatile uint32_t GR1_AB8; /* GR1_AB8 */ + volatile uint32_t GR1_AB9; /* GR1_AB9 */ + volatile uint32_t GR1_AB10; /* GR1_AB10 */ + volatile uint32_t GR1_AB11; /* GR1_AB11 */ + volatile uint32_t GR1_BASE; /* GR1_BASE */ +/* end of struct st_vdc5_from_gr0_ab7 */ + volatile uint32_t GR1_CLUT; /* GR1_CLUT */ + volatile uint32_t GR1_MON; /* GR1_MON */ + volatile uint8_t dummy31[40]; /* */ +/* start of struct st_vdc5_from_adj0_update */ + volatile uint32_t ADJ1_UPDATE; /* ADJ1_UPDATE */ + volatile uint32_t ADJ1_BKSTR_SET; /* ADJ1_BKSTR_SET */ +#define VDC5_ADJ1_ENH_TIM1_COUNT 3 + volatile uint32_t ADJ1_ENH_TIM1; /* ADJ1_ENH_TIM1 */ + volatile uint32_t ADJ1_ENH_TIM2; /* ADJ1_ENH_TIM2 */ + volatile uint32_t ADJ1_ENH_TIM3; /* ADJ1_ENH_TIM3 */ +#define VDC5_ADJ1_ENH_SHP1_COUNT 6 + volatile uint32_t ADJ1_ENH_SHP1; /* ADJ1_ENH_SHP1 */ + volatile uint32_t ADJ1_ENH_SHP2; /* ADJ1_ENH_SHP2 */ + volatile uint32_t ADJ1_ENH_SHP3; /* ADJ1_ENH_SHP3 */ + volatile uint32_t ADJ1_ENH_SHP4; /* ADJ1_ENH_SHP4 */ + volatile uint32_t ADJ1_ENH_SHP5; /* ADJ1_ENH_SHP5 */ + volatile uint32_t ADJ1_ENH_SHP6; /* ADJ1_ENH_SHP6 */ +#define VDC5_ADJ1_ENH_LTI1_COUNT 2 + volatile uint32_t ADJ1_ENH_LTI1; /* ADJ1_ENH_LTI1 */ + volatile uint32_t ADJ1_ENH_LTI2; /* ADJ1_ENH_LTI2 */ + volatile uint32_t ADJ1_MTX_MODE; /* ADJ1_MTX_MODE */ + volatile uint32_t ADJ1_MTX_YG_ADJ0; /* ADJ1_MTX_YG_ADJ0 */ + volatile uint32_t ADJ1_MTX_YG_ADJ1; /* ADJ1_MTX_YG_ADJ1 */ + volatile uint32_t ADJ1_MTX_CBB_ADJ0; /* ADJ1_MTX_CBB_ADJ0 */ + volatile uint32_t ADJ1_MTX_CBB_ADJ1; /* ADJ1_MTX_CBB_ADJ1 */ + volatile uint32_t ADJ1_MTX_CRR_ADJ0; /* ADJ1_MTX_CRR_ADJ0 */ + volatile uint32_t ADJ1_MTX_CRR_ADJ1; /* ADJ1_MTX_CRR_ADJ1 */ +/* end of struct st_vdc5_from_adj0_update */ + volatile uint8_t dummy32[48]; /* */ + volatile uint32_t GR_VIN_UPDATE; /* GR_VIN_UPDATE */ + volatile uint8_t dummy33[28]; /* */ +#define VDC5_GR_VIN_AB1_COUNT 7 + volatile uint32_t GR_VIN_AB1; /* GR_VIN_AB1 */ + volatile uint32_t GR_VIN_AB2; /* GR_VIN_AB2 */ + volatile uint32_t GR_VIN_AB3; /* GR_VIN_AB3 */ + volatile uint32_t GR_VIN_AB4; /* GR_VIN_AB4 */ + volatile uint32_t GR_VIN_AB5; /* GR_VIN_AB5 */ + volatile uint32_t GR_VIN_AB6; /* GR_VIN_AB6 */ + volatile uint32_t GR_VIN_AB7; /* GR_VIN_AB7 */ + volatile uint8_t dummy34[16]; /* */ + volatile uint32_t GR_VIN_BASE; /* GR_VIN_BASE */ + volatile uint8_t dummy35[4]; /* */ + volatile uint32_t GR_VIN_MON; /* GR_VIN_MON */ + volatile uint8_t dummy36[40]; /* */ + volatile uint32_t OIR_SCL0_UPDATE; /* OIR_SCL0_UPDATE */ +#define VDC5_OIR_SCL0_FRC1_COUNT 7 + volatile uint32_t OIR_SCL0_FRC1; /* OIR_SCL0_FRC1 */ + volatile uint32_t OIR_SCL0_FRC2; /* OIR_SCL0_FRC2 */ + volatile uint32_t OIR_SCL0_FRC3; /* OIR_SCL0_FRC3 */ + volatile uint32_t OIR_SCL0_FRC4; /* OIR_SCL0_FRC4 */ + volatile uint32_t OIR_SCL0_FRC5; /* OIR_SCL0_FRC5 */ + volatile uint32_t OIR_SCL0_FRC6; /* OIR_SCL0_FRC6 */ + volatile uint32_t OIR_SCL0_FRC7; /* OIR_SCL0_FRC7 */ + volatile uint8_t dummy37[12]; /* */ +#define VDC5_OIR_SCL0_DS1_COUNT 3 + volatile uint32_t OIR_SCL0_DS1; /* OIR_SCL0_DS1 */ + volatile uint32_t OIR_SCL0_DS2; /* OIR_SCL0_DS2 */ + volatile uint32_t OIR_SCL0_DS3; /* OIR_SCL0_DS3 */ + volatile uint8_t dummy38[12]; /* */ + volatile uint32_t OIR_SCL0_DS7; /* OIR_SCL0_DS7 */ + volatile uint32_t OIR_SCL0_US1; /* OIR_SCL0_US1 */ + volatile uint32_t OIR_SCL0_US2; /* OIR_SCL0_US2 */ + volatile uint32_t OIR_SCL0_US3; /* OIR_SCL0_US3 */ + volatile uint8_t dummy39[16]; /* */ + volatile uint32_t OIR_SCL0_US8; /* OIR_SCL0_US8 */ + volatile uint8_t dummy40[4]; /* */ + volatile uint32_t OIR_SCL0_OVR1; /* OIR_SCL0_OVR1 */ + volatile uint8_t dummy41[16]; /* */ + volatile uint32_t OIR_SCL1_UPDATE; /* OIR_SCL1_UPDATE */ + volatile uint8_t dummy42[4]; /* */ +#define VDC5_OIR_SCL1_WR1_COUNT 4 + volatile uint32_t OIR_SCL1_WR1; /* OIR_SCL1_WR1 */ + volatile uint32_t OIR_SCL1_WR2; /* OIR_SCL1_WR2 */ + volatile uint32_t OIR_SCL1_WR3; /* OIR_SCL1_WR3 */ + volatile uint32_t OIR_SCL1_WR4; /* OIR_SCL1_WR4 */ + volatile uint8_t dummy43[4]; /* */ + volatile uint32_t OIR_SCL1_WR5; /* OIR_SCL1_WR5 */ + volatile uint32_t OIR_SCL1_WR6; /* OIR_SCL1_WR6 */ + volatile uint32_t OIR_SCL1_WR7; /* OIR_SCL1_WR7 */ + volatile uint8_t dummy44[88]; /* */ + volatile uint32_t GR_OIR_UPDATE; /* GR_OIR_UPDATE */ + volatile uint32_t GR_OIR_FLM_RD; /* GR_OIR_FLM_RD */ +#define VDC5_GR_OIR_FLM1_COUNT 6 + volatile uint32_t GR_OIR_FLM1; /* GR_OIR_FLM1 */ + volatile uint32_t GR_OIR_FLM2; /* GR_OIR_FLM2 */ + volatile uint32_t GR_OIR_FLM3; /* GR_OIR_FLM3 */ + volatile uint32_t GR_OIR_FLM4; /* GR_OIR_FLM4 */ + volatile uint32_t GR_OIR_FLM5; /* GR_OIR_FLM5 */ + volatile uint32_t GR_OIR_FLM6; /* GR_OIR_FLM6 */ +#define VDC5_GR_OIR_AB1_COUNT 3 + volatile uint32_t GR_OIR_AB1; /* GR_OIR_AB1 */ + volatile uint32_t GR_OIR_AB2; /* GR_OIR_AB2 */ + volatile uint32_t GR_OIR_AB3; /* GR_OIR_AB3 */ + volatile uint8_t dummy45[12]; /* */ + volatile uint32_t GR_OIR_AB7; /* GR_OIR_AB7 */ + volatile uint32_t GR_OIR_AB8; /* GR_OIR_AB8 */ + volatile uint32_t GR_OIR_AB9; /* GR_OIR_AB9 */ + volatile uint32_t GR_OIR_AB10; /* GR_OIR_AB10 */ + volatile uint32_t GR_OIR_AB11; /* GR_OIR_AB11 */ + volatile uint32_t GR_OIR_BASE; /* GR_OIR_BASE */ + volatile uint32_t GR_OIR_CLUT; /* GR_OIR_CLUT */ + volatile uint32_t GR_OIR_MON; /* GR_OIR_MON */ +}; + + +struct st_vdc5_from_gr0_update +{ + volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */ + volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */ + volatile uint32_t GR0_FLM1; /* GR0_FLM1 */ + volatile uint32_t GR0_FLM2; /* GR0_FLM2 */ + volatile uint32_t GR0_FLM3; /* GR0_FLM3 */ + volatile uint32_t GR0_FLM4; /* GR0_FLM4 */ + volatile uint32_t GR0_FLM5; /* GR0_FLM5 */ + volatile uint32_t GR0_FLM6; /* GR0_FLM6 */ + volatile uint32_t GR0_AB1; /* GR0_AB1 */ + volatile uint32_t GR0_AB2; /* GR0_AB2 */ + volatile uint32_t GR0_AB3; /* GR0_AB3 */ +}; + + +struct st_vdc5_from_gr0_ab7 +{ + volatile uint32_t GR0_AB7; /* GR0_AB7 */ + volatile uint32_t GR0_AB8; /* GR0_AB8 */ + volatile uint32_t GR0_AB9; /* GR0_AB9 */ + volatile uint32_t GR0_AB10; /* GR0_AB10 */ + volatile uint32_t GR0_AB11; /* GR0_AB11 */ + volatile uint32_t GR0_BASE; /* GR0_BASE */ +}; + + +struct st_vdc5_from_adj0_update +{ + volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */ + volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */ + volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */ + volatile uint32_t ADJ0_ENH_TIM2; /* ADJ0_ENH_TIM2 */ + volatile uint32_t ADJ0_ENH_TIM3; /* ADJ0_ENH_TIM3 */ + volatile uint32_t ADJ0_ENH_SHP1; /* ADJ0_ENH_SHP1 */ + volatile uint32_t ADJ0_ENH_SHP2; /* ADJ0_ENH_SHP2 */ + volatile uint32_t ADJ0_ENH_SHP3; /* ADJ0_ENH_SHP3 */ + volatile uint32_t ADJ0_ENH_SHP4; /* ADJ0_ENH_SHP4 */ + volatile uint32_t ADJ0_ENH_SHP5; /* ADJ0_ENH_SHP5 */ + volatile uint32_t ADJ0_ENH_SHP6; /* ADJ0_ENH_SHP6 */ + volatile uint32_t ADJ0_ENH_LTI1; /* ADJ0_ENH_LTI1 */ + volatile uint32_t ADJ0_ENH_LTI2; /* ADJ0_ENH_LTI2 */ + volatile uint32_t ADJ0_MTX_MODE; /* ADJ0_MTX_MODE */ + volatile uint32_t ADJ0_MTX_YG_ADJ0; /* ADJ0_MTX_YG_ADJ0 */ + volatile uint32_t ADJ0_MTX_YG_ADJ1; /* ADJ0_MTX_YG_ADJ1 */ + volatile uint32_t ADJ0_MTX_CBB_ADJ0; /* ADJ0_MTX_CBB_ADJ0 */ + volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */ + volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */ + volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */ +}; + + +struct st_vdc5_from_sc0_scl0_update +{ + volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */ + volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */ + volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */ + volatile uint32_t SC0_SCL0_FRC3; /* SC0_SCL0_FRC3 */ + volatile uint32_t SC0_SCL0_FRC4; /* SC0_SCL0_FRC4 */ + volatile uint32_t SC0_SCL0_FRC5; /* SC0_SCL0_FRC5 */ + volatile uint32_t SC0_SCL0_FRC6; /* SC0_SCL0_FRC6 */ + volatile uint32_t SC0_SCL0_FRC7; /* SC0_SCL0_FRC7 */ + volatile uint8_t dummy5[4]; /* */ + volatile uint32_t SC0_SCL0_FRC9; /* SC0_SCL0_FRC9 */ + volatile uint16_t SC0_SCL0_MON0; /* SC0_SCL0_MON0 */ + volatile uint16_t SC0_SCL0_INT; /* SC0_SCL0_INT */ + volatile uint32_t SC0_SCL0_DS1; /* SC0_SCL0_DS1 */ + volatile uint32_t SC0_SCL0_DS2; /* SC0_SCL0_DS2 */ + volatile uint32_t SC0_SCL0_DS3; /* SC0_SCL0_DS3 */ + volatile uint32_t SC0_SCL0_DS4; /* SC0_SCL0_DS4 */ + volatile uint32_t SC0_SCL0_DS5; /* SC0_SCL0_DS5 */ + volatile uint32_t SC0_SCL0_DS6; /* SC0_SCL0_DS6 */ + volatile uint32_t SC0_SCL0_DS7; /* SC0_SCL0_DS7 */ + volatile uint32_t SC0_SCL0_US1; /* SC0_SCL0_US1 */ + volatile uint32_t SC0_SCL0_US2; /* SC0_SCL0_US2 */ + volatile uint32_t SC0_SCL0_US3; /* SC0_SCL0_US3 */ + volatile uint32_t SC0_SCL0_US4; /* SC0_SCL0_US4 */ + volatile uint32_t SC0_SCL0_US5; /* SC0_SCL0_US5 */ + volatile uint32_t SC0_SCL0_US6; /* SC0_SCL0_US6 */ + volatile uint32_t SC0_SCL0_US7; /* SC0_SCL0_US7 */ + volatile uint32_t SC0_SCL0_US8; /* SC0_SCL0_US8 */ + volatile uint8_t dummy6[4]; /* */ + volatile uint32_t SC0_SCL0_OVR1; /* SC0_SCL0_OVR1 */ + volatile uint8_t dummy7[16]; /* */ + volatile uint32_t SC0_SCL1_UPDATE; /* SC0_SCL1_UPDATE */ + volatile uint8_t dummy8[4]; /* */ + volatile uint32_t SC0_SCL1_WR1; /* SC0_SCL1_WR1 */ + volatile uint32_t SC0_SCL1_WR2; /* SC0_SCL1_WR2 */ + volatile uint32_t SC0_SCL1_WR3; /* SC0_SCL1_WR3 */ + volatile uint32_t SC0_SCL1_WR4; /* SC0_SCL1_WR4 */ + volatile uint8_t dummy9[4]; /* */ + volatile uint32_t SC0_SCL1_WR5; /* SC0_SCL1_WR5 */ + volatile uint32_t SC0_SCL1_WR6; /* SC0_SCL1_WR6 */ + volatile uint32_t SC0_SCL1_WR7; /* SC0_SCL1_WR7 */ + volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */ + volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */ + volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */ +}; + + +struct st_vdc5_from_sc0_scl1_pbuf0 +{ + volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */ + volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */ + volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */ + volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */ + volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */ + volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */ +}; + + +#define VDC50 (*(struct st_vdc5 *)0xFCFF7400uL) /* VDC50 */ +#define VDC51 (*(struct st_vdc5 *)0xFCFF9400uL) /* VDC51 */ + + +/* Start of channnel array defines of VDC5 */ + +/* Channnel array defines of VDC5 */ +/*(Sample) value = VDC5[ channel ]->INP_UPDATE; */ +#define VDC5_COUNT 2 +#define VDC5_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &VDC50, &VDC51 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + + + +/* Channnel array defines of VDC5n_FROM_GR2_AB7_ARRAY */ +/*(Sample) value = VDC5n_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ +#define VDC5n_FROM_GR2_AB7_ARRAY_COUNT 2 +#define VDC5n_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 },{ \ + &VDC51_FROM_GR2_AB7, &VDC51_FROM_GR3_AB7 \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */ +#define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */ +#define VDC51_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR2_AB7) /* VDC51_FROM_GR2_AB7 */ +#define VDC51_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR3_AB7) /* VDC51_FROM_GR3_AB7 */ + + + + +/* Channnel array defines of VDC5n_FROM_GR2_UPDATE_ARRAY */ +/*(Sample) value = VDC5n_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ +#define VDC5n_FROM_GR2_UPDATE_ARRAY_COUNT 2 +#define VDC5n_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE },{ \ + &VDC51_FROM_GR2_UPDATE, &VDC51_FROM_GR3_UPDATE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */ +#define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */ +#define VDC51_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR2_UPDATE) /* VDC51_FROM_GR2_UPDATE */ +#define VDC51_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR3_UPDATE) /* VDC51_FROM_GR3_UPDATE */ + + + + +/* Channnel array defines of VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY */ +/*(Sample) value = VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY[ channel ][ index ]->SC0_SCL1_PBUF0; */ +#define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT 2 +#define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_SC0_SCL1_PBUF0, &VDC50_FROM_SC1_SCL1_PBUF0 },{ \ + &VDC51_FROM_SC0_SCL1_PBUF0, &VDC51_FROM_SC1_SCL1_PBUF0 \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC0_SCL1_PBUF0) /* VDC50_FROM_SC0_SCL1_PBUF0 */ +#define VDC50_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC1_SCL1_PBUF0) /* VDC50_FROM_SC1_SCL1_PBUF0 */ +#define VDC51_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC0_SCL1_PBUF0) /* VDC51_FROM_SC0_SCL1_PBUF0 */ +#define VDC51_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC1_SCL1_PBUF0) /* VDC51_FROM_SC1_SCL1_PBUF0 */ + + + + +/* Channnel array defines of VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY */ +/*(Sample) value = VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY[ channel ][ index ]->SC0_SCL0_UPDATE; */ +#define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT 2 +#define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_SC0_SCL0_UPDATE, &VDC50_FROM_SC1_SCL0_UPDATE },{ \ + &VDC51_FROM_SC0_SCL0_UPDATE, &VDC51_FROM_SC1_SCL0_UPDATE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC0_SCL0_UPDATE) /* VDC50_FROM_SC0_SCL0_UPDATE */ +#define VDC50_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC1_SCL0_UPDATE) /* VDC50_FROM_SC1_SCL0_UPDATE */ +#define VDC51_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC0_SCL0_UPDATE) /* VDC51_FROM_SC0_SCL0_UPDATE */ +#define VDC51_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC1_SCL0_UPDATE) /* VDC51_FROM_SC1_SCL0_UPDATE */ + + + + +/* Channnel array defines of VDC5n_FROM_ADJ0_UPDATE_ARRAY */ +/*(Sample) value = VDC5n_FROM_ADJ0_UPDATE_ARRAY[ channel ][ index ]->ADJ0_UPDATE; */ +#define VDC5n_FROM_ADJ0_UPDATE_ARRAY_COUNT 2 +#define VDC5n_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_ADJ0_UPDATE, &VDC50_FROM_ADJ1_UPDATE },{ \ + &VDC51_FROM_ADJ0_UPDATE, &VDC51_FROM_ADJ1_UPDATE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ0_UPDATE) /* VDC50_FROM_ADJ0_UPDATE */ +#define VDC50_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ1_UPDATE) /* VDC50_FROM_ADJ1_UPDATE */ +#define VDC51_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ0_UPDATE) /* VDC51_FROM_ADJ0_UPDATE */ +#define VDC51_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ1_UPDATE) /* VDC51_FROM_ADJ1_UPDATE */ + + + + +/* Channnel array defines of VDC5n_FROM_GR0_AB7_ARRAY */ +/*(Sample) value = VDC5n_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ +#define VDC5n_FROM_GR0_AB7_ARRAY_COUNT 2 +#define VDC5n_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR1_AB7 },{ \ + &VDC51_FROM_GR0_AB7, &VDC51_FROM_GR1_AB7 \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */ +#define VDC50_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR1_AB7) /* VDC50_FROM_GR1_AB7 */ +#define VDC51_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR0_AB7) /* VDC51_FROM_GR0_AB7 */ +#define VDC51_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR1_AB7) /* VDC51_FROM_GR1_AB7 */ + + + + +/* Channnel array defines of VDC5n_FROM_GR0_UPDATE_ARRAY */ +/*(Sample) value = VDC5n_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ +#define VDC5n_FROM_GR0_UPDATE_ARRAY_COUNT 2 +#define VDC5n_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR1_UPDATE },{ \ + &VDC51_FROM_GR0_UPDATE, &VDC51_FROM_GR1_UPDATE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */ +#define VDC50_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR1_UPDATE) /* VDC50_FROM_GR1_UPDATE */ +#define VDC51_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR0_UPDATE) /* VDC51_FROM_GR0_UPDATE */ +#define VDC51_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR1_UPDATE) /* VDC51_FROM_GR1_UPDATE */ + + +/* End of channnel array defines of VDC5 */ + + +#define VDC50INP_UPDATE VDC50.INP_UPDATE +#define VDC50INP_SEL_CNT VDC50.INP_SEL_CNT +#define VDC50INP_EXT_SYNC_CNT VDC50.INP_EXT_SYNC_CNT +#define VDC50INP_VSYNC_PH_ADJ VDC50.INP_VSYNC_PH_ADJ +#define VDC50INP_DLY_ADJ VDC50.INP_DLY_ADJ +#define VDC50IMGCNT_UPDATE VDC50.IMGCNT_UPDATE +#define VDC50IMGCNT_NR_CNT0 VDC50.IMGCNT_NR_CNT0 +#define VDC50IMGCNT_NR_CNT1 VDC50.IMGCNT_NR_CNT1 +#define VDC50IMGCNT_MTX_MODE VDC50.IMGCNT_MTX_MODE +#define VDC50IMGCNT_MTX_YG_ADJ0 VDC50.IMGCNT_MTX_YG_ADJ0 +#define VDC50IMGCNT_MTX_YG_ADJ1 VDC50.IMGCNT_MTX_YG_ADJ1 +#define VDC50IMGCNT_MTX_CBB_ADJ0 VDC50.IMGCNT_MTX_CBB_ADJ0 +#define VDC50IMGCNT_MTX_CBB_ADJ1 VDC50.IMGCNT_MTX_CBB_ADJ1 +#define VDC50IMGCNT_MTX_CRR_ADJ0 VDC50.IMGCNT_MTX_CRR_ADJ0 +#define VDC50IMGCNT_MTX_CRR_ADJ1 VDC50.IMGCNT_MTX_CRR_ADJ1 +#define VDC50IMGCNT_DRC_REG VDC50.IMGCNT_DRC_REG +#define VDC50SC0_SCL0_UPDATE VDC50.SC0_SCL0_UPDATE +#define VDC50SC0_SCL0_FRC1 VDC50.SC0_SCL0_FRC1 +#define VDC50SC0_SCL0_FRC2 VDC50.SC0_SCL0_FRC2 +#define VDC50SC0_SCL0_FRC3 VDC50.SC0_SCL0_FRC3 +#define VDC50SC0_SCL0_FRC4 VDC50.SC0_SCL0_FRC4 +#define VDC50SC0_SCL0_FRC5 VDC50.SC0_SCL0_FRC5 +#define VDC50SC0_SCL0_FRC6 VDC50.SC0_SCL0_FRC6 +#define VDC50SC0_SCL0_FRC7 VDC50.SC0_SCL0_FRC7 +#define VDC50SC0_SCL0_FRC9 VDC50.SC0_SCL0_FRC9 +#define VDC50SC0_SCL0_MON0 VDC50.SC0_SCL0_MON0 +#define VDC50SC0_SCL0_INT VDC50.SC0_SCL0_INT +#define VDC50SC0_SCL0_DS1 VDC50.SC0_SCL0_DS1 +#define VDC50SC0_SCL0_DS2 VDC50.SC0_SCL0_DS2 +#define VDC50SC0_SCL0_DS3 VDC50.SC0_SCL0_DS3 +#define VDC50SC0_SCL0_DS4 VDC50.SC0_SCL0_DS4 +#define VDC50SC0_SCL0_DS5 VDC50.SC0_SCL0_DS5 +#define VDC50SC0_SCL0_DS6 VDC50.SC0_SCL0_DS6 +#define VDC50SC0_SCL0_DS7 VDC50.SC0_SCL0_DS7 +#define VDC50SC0_SCL0_US1 VDC50.SC0_SCL0_US1 +#define VDC50SC0_SCL0_US2 VDC50.SC0_SCL0_US2 +#define VDC50SC0_SCL0_US3 VDC50.SC0_SCL0_US3 +#define VDC50SC0_SCL0_US4 VDC50.SC0_SCL0_US4 +#define VDC50SC0_SCL0_US5 VDC50.SC0_SCL0_US5 +#define VDC50SC0_SCL0_US6 VDC50.SC0_SCL0_US6 +#define VDC50SC0_SCL0_US7 VDC50.SC0_SCL0_US7 +#define VDC50SC0_SCL0_US8 VDC50.SC0_SCL0_US8 +#define VDC50SC0_SCL0_OVR1 VDC50.SC0_SCL0_OVR1 +#define VDC50SC0_SCL1_UPDATE VDC50.SC0_SCL1_UPDATE +#define VDC50SC0_SCL1_WR1 VDC50.SC0_SCL1_WR1 +#define VDC50SC0_SCL1_WR2 VDC50.SC0_SCL1_WR2 +#define VDC50SC0_SCL1_WR3 VDC50.SC0_SCL1_WR3 +#define VDC50SC0_SCL1_WR4 VDC50.SC0_SCL1_WR4 +#define VDC50SC0_SCL1_WR5 VDC50.SC0_SCL1_WR5 +#define VDC50SC0_SCL1_WR6 VDC50.SC0_SCL1_WR6 +#define VDC50SC0_SCL1_WR7 VDC50.SC0_SCL1_WR7 +#define VDC50SC0_SCL1_WR8 VDC50.SC0_SCL1_WR8 +#define VDC50SC0_SCL1_WR9 VDC50.SC0_SCL1_WR9 +#define VDC50SC0_SCL1_WR10 VDC50.SC0_SCL1_WR10 +#define VDC50SC0_SCL1_WR11 VDC50.SC0_SCL1_WR11 +#define VDC50SC0_SCL1_MON1 VDC50.SC0_SCL1_MON1 +#define VDC50SC0_SCL1_PBUF0 VDC50.SC0_SCL1_PBUF0 +#define VDC50SC0_SCL1_PBUF1 VDC50.SC0_SCL1_PBUF1 +#define VDC50SC0_SCL1_PBUF2 VDC50.SC0_SCL1_PBUF2 +#define VDC50SC0_SCL1_PBUF3 VDC50.SC0_SCL1_PBUF3 +#define VDC50SC0_SCL1_PBUF_FLD VDC50.SC0_SCL1_PBUF_FLD +#define VDC50SC0_SCL1_PBUF_CNT VDC50.SC0_SCL1_PBUF_CNT +#define VDC50GR0_UPDATE VDC50.GR0_UPDATE +#define VDC50GR0_FLM_RD VDC50.GR0_FLM_RD +#define VDC50GR0_FLM1 VDC50.GR0_FLM1 +#define VDC50GR0_FLM2 VDC50.GR0_FLM2 +#define VDC50GR0_FLM3 VDC50.GR0_FLM3 +#define VDC50GR0_FLM4 VDC50.GR0_FLM4 +#define VDC50GR0_FLM5 VDC50.GR0_FLM5 +#define VDC50GR0_FLM6 VDC50.GR0_FLM6 +#define VDC50GR0_AB1 VDC50.GR0_AB1 +#define VDC50GR0_AB2 VDC50.GR0_AB2 +#define VDC50GR0_AB3 VDC50.GR0_AB3 +#define VDC50GR0_AB7 VDC50.GR0_AB7 +#define VDC50GR0_AB8 VDC50.GR0_AB8 +#define VDC50GR0_AB9 VDC50.GR0_AB9 +#define VDC50GR0_AB10 VDC50.GR0_AB10 +#define VDC50GR0_AB11 VDC50.GR0_AB11 +#define VDC50GR0_BASE VDC50.GR0_BASE +#define VDC50GR0_CLUT VDC50.GR0_CLUT +#define VDC50ADJ0_UPDATE VDC50.ADJ0_UPDATE +#define VDC50ADJ0_BKSTR_SET VDC50.ADJ0_BKSTR_SET +#define VDC50ADJ0_ENH_TIM1 VDC50.ADJ0_ENH_TIM1 +#define VDC50ADJ0_ENH_TIM2 VDC50.ADJ0_ENH_TIM2 +#define VDC50ADJ0_ENH_TIM3 VDC50.ADJ0_ENH_TIM3 +#define VDC50ADJ0_ENH_SHP1 VDC50.ADJ0_ENH_SHP1 +#define VDC50ADJ0_ENH_SHP2 VDC50.ADJ0_ENH_SHP2 +#define VDC50ADJ0_ENH_SHP3 VDC50.ADJ0_ENH_SHP3 +#define VDC50ADJ0_ENH_SHP4 VDC50.ADJ0_ENH_SHP4 +#define VDC50ADJ0_ENH_SHP5 VDC50.ADJ0_ENH_SHP5 +#define VDC50ADJ0_ENH_SHP6 VDC50.ADJ0_ENH_SHP6 +#define VDC50ADJ0_ENH_LTI1 VDC50.ADJ0_ENH_LTI1 +#define VDC50ADJ0_ENH_LTI2 VDC50.ADJ0_ENH_LTI2 +#define VDC50ADJ0_MTX_MODE VDC50.ADJ0_MTX_MODE +#define VDC50ADJ0_MTX_YG_ADJ0 VDC50.ADJ0_MTX_YG_ADJ0 +#define VDC50ADJ0_MTX_YG_ADJ1 VDC50.ADJ0_MTX_YG_ADJ1 +#define VDC50ADJ0_MTX_CBB_ADJ0 VDC50.ADJ0_MTX_CBB_ADJ0 +#define VDC50ADJ0_MTX_CBB_ADJ1 VDC50.ADJ0_MTX_CBB_ADJ1 +#define VDC50ADJ0_MTX_CRR_ADJ0 VDC50.ADJ0_MTX_CRR_ADJ0 +#define VDC50ADJ0_MTX_CRR_ADJ1 VDC50.ADJ0_MTX_CRR_ADJ1 +#define VDC50GR2_UPDATE VDC50.GR2_UPDATE +#define VDC50GR2_FLM_RD VDC50.GR2_FLM_RD +#define VDC50GR2_FLM1 VDC50.GR2_FLM1 +#define VDC50GR2_FLM2 VDC50.GR2_FLM2 +#define VDC50GR2_FLM3 VDC50.GR2_FLM3 +#define VDC50GR2_FLM4 VDC50.GR2_FLM4 +#define VDC50GR2_FLM5 VDC50.GR2_FLM5 +#define VDC50GR2_FLM6 VDC50.GR2_FLM6 +#define VDC50GR2_AB1 VDC50.GR2_AB1 +#define VDC50GR2_AB2 VDC50.GR2_AB2 +#define VDC50GR2_AB3 VDC50.GR2_AB3 +#define VDC50GR2_AB4 VDC50.GR2_AB4 +#define VDC50GR2_AB5 VDC50.GR2_AB5 +#define VDC50GR2_AB6 VDC50.GR2_AB6 +#define VDC50GR2_AB7 VDC50.GR2_AB7 +#define VDC50GR2_AB8 VDC50.GR2_AB8 +#define VDC50GR2_AB9 VDC50.GR2_AB9 +#define VDC50GR2_AB10 VDC50.GR2_AB10 +#define VDC50GR2_AB11 VDC50.GR2_AB11 +#define VDC50GR2_BASE VDC50.GR2_BASE +#define VDC50GR2_CLUT VDC50.GR2_CLUT +#define VDC50GR2_MON VDC50.GR2_MON +#define VDC50GR3_UPDATE VDC50.GR3_UPDATE +#define VDC50GR3_FLM_RD VDC50.GR3_FLM_RD +#define VDC50GR3_FLM1 VDC50.GR3_FLM1 +#define VDC50GR3_FLM2 VDC50.GR3_FLM2 +#define VDC50GR3_FLM3 VDC50.GR3_FLM3 +#define VDC50GR3_FLM4 VDC50.GR3_FLM4 +#define VDC50GR3_FLM5 VDC50.GR3_FLM5 +#define VDC50GR3_FLM6 VDC50.GR3_FLM6 +#define VDC50GR3_AB1 VDC50.GR3_AB1 +#define VDC50GR3_AB2 VDC50.GR3_AB2 +#define VDC50GR3_AB3 VDC50.GR3_AB3 +#define VDC50GR3_AB4 VDC50.GR3_AB4 +#define VDC50GR3_AB5 VDC50.GR3_AB5 +#define VDC50GR3_AB6 VDC50.GR3_AB6 +#define VDC50GR3_AB7 VDC50.GR3_AB7 +#define VDC50GR3_AB8 VDC50.GR3_AB8 +#define VDC50GR3_AB9 VDC50.GR3_AB9 +#define VDC50GR3_AB10 VDC50.GR3_AB10 +#define VDC50GR3_AB11 VDC50.GR3_AB11 +#define VDC50GR3_BASE VDC50.GR3_BASE +#define VDC50GR3_CLUT_INT VDC50.GR3_CLUT_INT +#define VDC50GR3_MON VDC50.GR3_MON +#define VDC50GAM_G_UPDATE VDC50.GAM_G_UPDATE +#define VDC50GAM_SW VDC50.GAM_SW +#define VDC50GAM_G_LUT1 VDC50.GAM_G_LUT1 +#define VDC50GAM_G_LUT2 VDC50.GAM_G_LUT2 +#define VDC50GAM_G_LUT3 VDC50.GAM_G_LUT3 +#define VDC50GAM_G_LUT4 VDC50.GAM_G_LUT4 +#define VDC50GAM_G_LUT5 VDC50.GAM_G_LUT5 +#define VDC50GAM_G_LUT6 VDC50.GAM_G_LUT6 +#define VDC50GAM_G_LUT7 VDC50.GAM_G_LUT7 +#define VDC50GAM_G_LUT8 VDC50.GAM_G_LUT8 +#define VDC50GAM_G_LUT9 VDC50.GAM_G_LUT9 +#define VDC50GAM_G_LUT10 VDC50.GAM_G_LUT10 +#define VDC50GAM_G_LUT11 VDC50.GAM_G_LUT11 +#define VDC50GAM_G_LUT12 VDC50.GAM_G_LUT12 +#define VDC50GAM_G_LUT13 VDC50.GAM_G_LUT13 +#define VDC50GAM_G_LUT14 VDC50.GAM_G_LUT14 +#define VDC50GAM_G_LUT15 VDC50.GAM_G_LUT15 +#define VDC50GAM_G_LUT16 VDC50.GAM_G_LUT16 +#define VDC50GAM_G_AREA1 VDC50.GAM_G_AREA1 +#define VDC50GAM_G_AREA2 VDC50.GAM_G_AREA2 +#define VDC50GAM_G_AREA3 VDC50.GAM_G_AREA3 +#define VDC50GAM_G_AREA4 VDC50.GAM_G_AREA4 +#define VDC50GAM_G_AREA5 VDC50.GAM_G_AREA5 +#define VDC50GAM_G_AREA6 VDC50.GAM_G_AREA6 +#define VDC50GAM_G_AREA7 VDC50.GAM_G_AREA7 +#define VDC50GAM_G_AREA8 VDC50.GAM_G_AREA8 +#define VDC50GAM_B_UPDATE VDC50.GAM_B_UPDATE +#define VDC50GAM_B_LUT1 VDC50.GAM_B_LUT1 +#define VDC50GAM_B_LUT2 VDC50.GAM_B_LUT2 +#define VDC50GAM_B_LUT3 VDC50.GAM_B_LUT3 +#define VDC50GAM_B_LUT4 VDC50.GAM_B_LUT4 +#define VDC50GAM_B_LUT5 VDC50.GAM_B_LUT5 +#define VDC50GAM_B_LUT6 VDC50.GAM_B_LUT6 +#define VDC50GAM_B_LUT7 VDC50.GAM_B_LUT7 +#define VDC50GAM_B_LUT8 VDC50.GAM_B_LUT8 +#define VDC50GAM_B_LUT9 VDC50.GAM_B_LUT9 +#define VDC50GAM_B_LUT10 VDC50.GAM_B_LUT10 +#define VDC50GAM_B_LUT11 VDC50.GAM_B_LUT11 +#define VDC50GAM_B_LUT12 VDC50.GAM_B_LUT12 +#define VDC50GAM_B_LUT13 VDC50.GAM_B_LUT13 +#define VDC50GAM_B_LUT14 VDC50.GAM_B_LUT14 +#define VDC50GAM_B_LUT15 VDC50.GAM_B_LUT15 +#define VDC50GAM_B_LUT16 VDC50.GAM_B_LUT16 +#define VDC50GAM_B_AREA1 VDC50.GAM_B_AREA1 +#define VDC50GAM_B_AREA2 VDC50.GAM_B_AREA2 +#define VDC50GAM_B_AREA3 VDC50.GAM_B_AREA3 +#define VDC50GAM_B_AREA4 VDC50.GAM_B_AREA4 +#define VDC50GAM_B_AREA5 VDC50.GAM_B_AREA5 +#define VDC50GAM_B_AREA6 VDC50.GAM_B_AREA6 +#define VDC50GAM_B_AREA7 VDC50.GAM_B_AREA7 +#define VDC50GAM_B_AREA8 VDC50.GAM_B_AREA8 +#define VDC50GAM_R_UPDATE VDC50.GAM_R_UPDATE +#define VDC50GAM_R_LUT1 VDC50.GAM_R_LUT1 +#define VDC50GAM_R_LUT2 VDC50.GAM_R_LUT2 +#define VDC50GAM_R_LUT3 VDC50.GAM_R_LUT3 +#define VDC50GAM_R_LUT4 VDC50.GAM_R_LUT4 +#define VDC50GAM_R_LUT5 VDC50.GAM_R_LUT5 +#define VDC50GAM_R_LUT6 VDC50.GAM_R_LUT6 +#define VDC50GAM_R_LUT7 VDC50.GAM_R_LUT7 +#define VDC50GAM_R_LUT8 VDC50.GAM_R_LUT8 +#define VDC50GAM_R_LUT9 VDC50.GAM_R_LUT9 +#define VDC50GAM_R_LUT10 VDC50.GAM_R_LUT10 +#define VDC50GAM_R_LUT11 VDC50.GAM_R_LUT11 +#define VDC50GAM_R_LUT12 VDC50.GAM_R_LUT12 +#define VDC50GAM_R_LUT13 VDC50.GAM_R_LUT13 +#define VDC50GAM_R_LUT14 VDC50.GAM_R_LUT14 +#define VDC50GAM_R_LUT15 VDC50.GAM_R_LUT15 +#define VDC50GAM_R_LUT16 VDC50.GAM_R_LUT16 +#define VDC50GAM_R_AREA1 VDC50.GAM_R_AREA1 +#define VDC50GAM_R_AREA2 VDC50.GAM_R_AREA2 +#define VDC50GAM_R_AREA3 VDC50.GAM_R_AREA3 +#define VDC50GAM_R_AREA4 VDC50.GAM_R_AREA4 +#define VDC50GAM_R_AREA5 VDC50.GAM_R_AREA5 +#define VDC50GAM_R_AREA6 VDC50.GAM_R_AREA6 +#define VDC50GAM_R_AREA7 VDC50.GAM_R_AREA7 +#define VDC50GAM_R_AREA8 VDC50.GAM_R_AREA8 +#define VDC50TCON_UPDATE VDC50.TCON_UPDATE +#define VDC50TCON_TIM VDC50.TCON_TIM +#define VDC50TCON_TIM_STVA1 VDC50.TCON_TIM_STVA1 +#define VDC50TCON_TIM_STVA2 VDC50.TCON_TIM_STVA2 +#define VDC50TCON_TIM_STVB1 VDC50.TCON_TIM_STVB1 +#define VDC50TCON_TIM_STVB2 VDC50.TCON_TIM_STVB2 +#define VDC50TCON_TIM_STH1 VDC50.TCON_TIM_STH1 +#define VDC50TCON_TIM_STH2 VDC50.TCON_TIM_STH2 +#define VDC50TCON_TIM_STB1 VDC50.TCON_TIM_STB1 +#define VDC50TCON_TIM_STB2 VDC50.TCON_TIM_STB2 +#define VDC50TCON_TIM_CPV1 VDC50.TCON_TIM_CPV1 +#define VDC50TCON_TIM_CPV2 VDC50.TCON_TIM_CPV2 +#define VDC50TCON_TIM_POLA1 VDC50.TCON_TIM_POLA1 +#define VDC50TCON_TIM_POLA2 VDC50.TCON_TIM_POLA2 +#define VDC50TCON_TIM_POLB1 VDC50.TCON_TIM_POLB1 +#define VDC50TCON_TIM_POLB2 VDC50.TCON_TIM_POLB2 +#define VDC50TCON_TIM_DE VDC50.TCON_TIM_DE +#define VDC50OUT_UPDATE VDC50.OUT_UPDATE +#define VDC50OUT_SET VDC50.OUT_SET +#define VDC50OUT_BRIGHT1 VDC50.OUT_BRIGHT1 +#define VDC50OUT_BRIGHT2 VDC50.OUT_BRIGHT2 +#define VDC50OUT_CONTRAST VDC50.OUT_CONTRAST +#define VDC50OUT_PDTHA VDC50.OUT_PDTHA +#define VDC50OUT_CLK_PHASE VDC50.OUT_CLK_PHASE +#define VDC50SYSCNT_INT1 VDC50.SYSCNT_INT1 +#define VDC50SYSCNT_INT2 VDC50.SYSCNT_INT2 +#define VDC50SYSCNT_INT3 VDC50.SYSCNT_INT3 +#define VDC50SYSCNT_INT4 VDC50.SYSCNT_INT4 +#define VDC50SYSCNT_INT5 VDC50.SYSCNT_INT5 +#define VDC50SYSCNT_INT6 VDC50.SYSCNT_INT6 +#define VDC50SYSCNT_PANEL_CLK VDC50.SYSCNT_PANEL_CLK +#define VDC50SYSCNT_CLUT VDC50.SYSCNT_CLUT +#define VDC50SC1_SCL0_UPDATE VDC50.SC1_SCL0_UPDATE +#define VDC50SC1_SCL0_FRC1 VDC50.SC1_SCL0_FRC1 +#define VDC50SC1_SCL0_FRC2 VDC50.SC1_SCL0_FRC2 +#define VDC50SC1_SCL0_FRC3 VDC50.SC1_SCL0_FRC3 +#define VDC50SC1_SCL0_FRC4 VDC50.SC1_SCL0_FRC4 +#define VDC50SC1_SCL0_FRC5 VDC50.SC1_SCL0_FRC5 +#define VDC50SC1_SCL0_FRC6 VDC50.SC1_SCL0_FRC6 +#define VDC50SC1_SCL0_FRC7 VDC50.SC1_SCL0_FRC7 +#define VDC50SC1_SCL0_FRC9 VDC50.SC1_SCL0_FRC9 +#define VDC50SC1_SCL0_MON0 VDC50.SC1_SCL0_MON0 +#define VDC50SC1_SCL0_INT VDC50.SC1_SCL0_INT +#define VDC50SC1_SCL0_DS1 VDC50.SC1_SCL0_DS1 +#define VDC50SC1_SCL0_DS2 VDC50.SC1_SCL0_DS2 +#define VDC50SC1_SCL0_DS3 VDC50.SC1_SCL0_DS3 +#define VDC50SC1_SCL0_DS4 VDC50.SC1_SCL0_DS4 +#define VDC50SC1_SCL0_DS5 VDC50.SC1_SCL0_DS5 +#define VDC50SC1_SCL0_DS6 VDC50.SC1_SCL0_DS6 +#define VDC50SC1_SCL0_DS7 VDC50.SC1_SCL0_DS7 +#define VDC50SC1_SCL0_US1 VDC50.SC1_SCL0_US1 +#define VDC50SC1_SCL0_US2 VDC50.SC1_SCL0_US2 +#define VDC50SC1_SCL0_US3 VDC50.SC1_SCL0_US3 +#define VDC50SC1_SCL0_US4 VDC50.SC1_SCL0_US4 +#define VDC50SC1_SCL0_US5 VDC50.SC1_SCL0_US5 +#define VDC50SC1_SCL0_US6 VDC50.SC1_SCL0_US6 +#define VDC50SC1_SCL0_US7 VDC50.SC1_SCL0_US7 +#define VDC50SC1_SCL0_US8 VDC50.SC1_SCL0_US8 +#define VDC50SC1_SCL0_OVR1 VDC50.SC1_SCL0_OVR1 +#define VDC50SC1_SCL1_UPDATE VDC50.SC1_SCL1_UPDATE +#define VDC50SC1_SCL1_WR1 VDC50.SC1_SCL1_WR1 +#define VDC50SC1_SCL1_WR2 VDC50.SC1_SCL1_WR2 +#define VDC50SC1_SCL1_WR3 VDC50.SC1_SCL1_WR3 +#define VDC50SC1_SCL1_WR4 VDC50.SC1_SCL1_WR4 +#define VDC50SC1_SCL1_WR5 VDC50.SC1_SCL1_WR5 +#define VDC50SC1_SCL1_WR6 VDC50.SC1_SCL1_WR6 +#define VDC50SC1_SCL1_WR7 VDC50.SC1_SCL1_WR7 +#define VDC50SC1_SCL1_WR8 VDC50.SC1_SCL1_WR8 +#define VDC50SC1_SCL1_WR9 VDC50.SC1_SCL1_WR9 +#define VDC50SC1_SCL1_WR10 VDC50.SC1_SCL1_WR10 +#define VDC50SC1_SCL1_WR11 VDC50.SC1_SCL1_WR11 +#define VDC50SC1_SCL1_MON1 VDC50.SC1_SCL1_MON1 +#define VDC50SC1_SCL1_PBUF0 VDC50.SC1_SCL1_PBUF0 +#define VDC50SC1_SCL1_PBUF1 VDC50.SC1_SCL1_PBUF1 +#define VDC50SC1_SCL1_PBUF2 VDC50.SC1_SCL1_PBUF2 +#define VDC50SC1_SCL1_PBUF3 VDC50.SC1_SCL1_PBUF3 +#define VDC50SC1_SCL1_PBUF_FLD VDC50.SC1_SCL1_PBUF_FLD +#define VDC50SC1_SCL1_PBUF_CNT VDC50.SC1_SCL1_PBUF_CNT +#define VDC50GR1_UPDATE VDC50.GR1_UPDATE +#define VDC50GR1_FLM_RD VDC50.GR1_FLM_RD +#define VDC50GR1_FLM1 VDC50.GR1_FLM1 +#define VDC50GR1_FLM2 VDC50.GR1_FLM2 +#define VDC50GR1_FLM3 VDC50.GR1_FLM3 +#define VDC50GR1_FLM4 VDC50.GR1_FLM4 +#define VDC50GR1_FLM5 VDC50.GR1_FLM5 +#define VDC50GR1_FLM6 VDC50.GR1_FLM6 +#define VDC50GR1_AB1 VDC50.GR1_AB1 +#define VDC50GR1_AB2 VDC50.GR1_AB2 +#define VDC50GR1_AB3 VDC50.GR1_AB3 +#define VDC50GR1_AB4 VDC50.GR1_AB4 +#define VDC50GR1_AB5 VDC50.GR1_AB5 +#define VDC50GR1_AB6 VDC50.GR1_AB6 +#define VDC50GR1_AB7 VDC50.GR1_AB7 +#define VDC50GR1_AB8 VDC50.GR1_AB8 +#define VDC50GR1_AB9 VDC50.GR1_AB9 +#define VDC50GR1_AB10 VDC50.GR1_AB10 +#define VDC50GR1_AB11 VDC50.GR1_AB11 +#define VDC50GR1_BASE VDC50.GR1_BASE +#define VDC50GR1_CLUT VDC50.GR1_CLUT +#define VDC50GR1_MON VDC50.GR1_MON +#define VDC50ADJ1_UPDATE VDC50.ADJ1_UPDATE +#define VDC50ADJ1_BKSTR_SET VDC50.ADJ1_BKSTR_SET +#define VDC50ADJ1_ENH_TIM1 VDC50.ADJ1_ENH_TIM1 +#define VDC50ADJ1_ENH_TIM2 VDC50.ADJ1_ENH_TIM2 +#define VDC50ADJ1_ENH_TIM3 VDC50.ADJ1_ENH_TIM3 +#define VDC50ADJ1_ENH_SHP1 VDC50.ADJ1_ENH_SHP1 +#define VDC50ADJ1_ENH_SHP2 VDC50.ADJ1_ENH_SHP2 +#define VDC50ADJ1_ENH_SHP3 VDC50.ADJ1_ENH_SHP3 +#define VDC50ADJ1_ENH_SHP4 VDC50.ADJ1_ENH_SHP4 +#define VDC50ADJ1_ENH_SHP5 VDC50.ADJ1_ENH_SHP5 +#define VDC50ADJ1_ENH_SHP6 VDC50.ADJ1_ENH_SHP6 +#define VDC50ADJ1_ENH_LTI1 VDC50.ADJ1_ENH_LTI1 +#define VDC50ADJ1_ENH_LTI2 VDC50.ADJ1_ENH_LTI2 +#define VDC50ADJ1_MTX_MODE VDC50.ADJ1_MTX_MODE +#define VDC50ADJ1_MTX_YG_ADJ0 VDC50.ADJ1_MTX_YG_ADJ0 +#define VDC50ADJ1_MTX_YG_ADJ1 VDC50.ADJ1_MTX_YG_ADJ1 +#define VDC50ADJ1_MTX_CBB_ADJ0 VDC50.ADJ1_MTX_CBB_ADJ0 +#define VDC50ADJ1_MTX_CBB_ADJ1 VDC50.ADJ1_MTX_CBB_ADJ1 +#define VDC50ADJ1_MTX_CRR_ADJ0 VDC50.ADJ1_MTX_CRR_ADJ0 +#define VDC50ADJ1_MTX_CRR_ADJ1 VDC50.ADJ1_MTX_CRR_ADJ1 +#define VDC50GR_VIN_UPDATE VDC50.GR_VIN_UPDATE +#define VDC50GR_VIN_AB1 VDC50.GR_VIN_AB1 +#define VDC50GR_VIN_AB2 VDC50.GR_VIN_AB2 +#define VDC50GR_VIN_AB3 VDC50.GR_VIN_AB3 +#define VDC50GR_VIN_AB4 VDC50.GR_VIN_AB4 +#define VDC50GR_VIN_AB5 VDC50.GR_VIN_AB5 +#define VDC50GR_VIN_AB6 VDC50.GR_VIN_AB6 +#define VDC50GR_VIN_AB7 VDC50.GR_VIN_AB7 +#define VDC50GR_VIN_BASE VDC50.GR_VIN_BASE +#define VDC50GR_VIN_MON VDC50.GR_VIN_MON +#define VDC50OIR_SCL0_UPDATE VDC50.OIR_SCL0_UPDATE +#define VDC50OIR_SCL0_FRC1 VDC50.OIR_SCL0_FRC1 +#define VDC50OIR_SCL0_FRC2 VDC50.OIR_SCL0_FRC2 +#define VDC50OIR_SCL0_FRC3 VDC50.OIR_SCL0_FRC3 +#define VDC50OIR_SCL0_FRC4 VDC50.OIR_SCL0_FRC4 +#define VDC50OIR_SCL0_FRC5 VDC50.OIR_SCL0_FRC5 +#define VDC50OIR_SCL0_FRC6 VDC50.OIR_SCL0_FRC6 +#define VDC50OIR_SCL0_FRC7 VDC50.OIR_SCL0_FRC7 +#define VDC50OIR_SCL0_DS1 VDC50.OIR_SCL0_DS1 +#define VDC50OIR_SCL0_DS2 VDC50.OIR_SCL0_DS2 +#define VDC50OIR_SCL0_DS3 VDC50.OIR_SCL0_DS3 +#define VDC50OIR_SCL0_DS7 VDC50.OIR_SCL0_DS7 +#define VDC50OIR_SCL0_US1 VDC50.OIR_SCL0_US1 +#define VDC50OIR_SCL0_US2 VDC50.OIR_SCL0_US2 +#define VDC50OIR_SCL0_US3 VDC50.OIR_SCL0_US3 +#define VDC50OIR_SCL0_US8 VDC50.OIR_SCL0_US8 +#define VDC50OIR_SCL0_OVR1 VDC50.OIR_SCL0_OVR1 +#define VDC50OIR_SCL1_UPDATE VDC50.OIR_SCL1_UPDATE +#define VDC50OIR_SCL1_WR1 VDC50.OIR_SCL1_WR1 +#define VDC50OIR_SCL1_WR2 VDC50.OIR_SCL1_WR2 +#define VDC50OIR_SCL1_WR3 VDC50.OIR_SCL1_WR3 +#define VDC50OIR_SCL1_WR4 VDC50.OIR_SCL1_WR4 +#define VDC50OIR_SCL1_WR5 VDC50.OIR_SCL1_WR5 +#define VDC50OIR_SCL1_WR6 VDC50.OIR_SCL1_WR6 +#define VDC50OIR_SCL1_WR7 VDC50.OIR_SCL1_WR7 +#define VDC50GR_OIR_UPDATE VDC50.GR_OIR_UPDATE +#define VDC50GR_OIR_FLM_RD VDC50.GR_OIR_FLM_RD +#define VDC50GR_OIR_FLM1 VDC50.GR_OIR_FLM1 +#define VDC50GR_OIR_FLM2 VDC50.GR_OIR_FLM2 +#define VDC50GR_OIR_FLM3 VDC50.GR_OIR_FLM3 +#define VDC50GR_OIR_FLM4 VDC50.GR_OIR_FLM4 +#define VDC50GR_OIR_FLM5 VDC50.GR_OIR_FLM5 +#define VDC50GR_OIR_FLM6 VDC50.GR_OIR_FLM6 +#define VDC50GR_OIR_AB1 VDC50.GR_OIR_AB1 +#define VDC50GR_OIR_AB2 VDC50.GR_OIR_AB2 +#define VDC50GR_OIR_AB3 VDC50.GR_OIR_AB3 +#define VDC50GR_OIR_AB7 VDC50.GR_OIR_AB7 +#define VDC50GR_OIR_AB8 VDC50.GR_OIR_AB8 +#define VDC50GR_OIR_AB9 VDC50.GR_OIR_AB9 +#define VDC50GR_OIR_AB10 VDC50.GR_OIR_AB10 +#define VDC50GR_OIR_AB11 VDC50.GR_OIR_AB11 +#define VDC50GR_OIR_BASE VDC50.GR_OIR_BASE +#define VDC50GR_OIR_CLUT VDC50.GR_OIR_CLUT +#define VDC50GR_OIR_MON VDC50.GR_OIR_MON +#define VDC51INP_UPDATE VDC51.INP_UPDATE +#define VDC51INP_SEL_CNT VDC51.INP_SEL_CNT +#define VDC51INP_EXT_SYNC_CNT VDC51.INP_EXT_SYNC_CNT +#define VDC51INP_VSYNC_PH_ADJ VDC51.INP_VSYNC_PH_ADJ +#define VDC51INP_DLY_ADJ VDC51.INP_DLY_ADJ +#define VDC51IMGCNT_UPDATE VDC51.IMGCNT_UPDATE +#define VDC51IMGCNT_NR_CNT0 VDC51.IMGCNT_NR_CNT0 +#define VDC51IMGCNT_NR_CNT1 VDC51.IMGCNT_NR_CNT1 +#define VDC51IMGCNT_MTX_MODE VDC51.IMGCNT_MTX_MODE +#define VDC51IMGCNT_MTX_YG_ADJ0 VDC51.IMGCNT_MTX_YG_ADJ0 +#define VDC51IMGCNT_MTX_YG_ADJ1 VDC51.IMGCNT_MTX_YG_ADJ1 +#define VDC51IMGCNT_MTX_CBB_ADJ0 VDC51.IMGCNT_MTX_CBB_ADJ0 +#define VDC51IMGCNT_MTX_CBB_ADJ1 VDC51.IMGCNT_MTX_CBB_ADJ1 +#define VDC51IMGCNT_MTX_CRR_ADJ0 VDC51.IMGCNT_MTX_CRR_ADJ0 +#define VDC51IMGCNT_MTX_CRR_ADJ1 VDC51.IMGCNT_MTX_CRR_ADJ1 +#define VDC51IMGCNT_DRC_REG VDC51.IMGCNT_DRC_REG +#define VDC51SC0_SCL0_UPDATE VDC51.SC0_SCL0_UPDATE +#define VDC51SC0_SCL0_FRC1 VDC51.SC0_SCL0_FRC1 +#define VDC51SC0_SCL0_FRC2 VDC51.SC0_SCL0_FRC2 +#define VDC51SC0_SCL0_FRC3 VDC51.SC0_SCL0_FRC3 +#define VDC51SC0_SCL0_FRC4 VDC51.SC0_SCL0_FRC4 +#define VDC51SC0_SCL0_FRC5 VDC51.SC0_SCL0_FRC5 +#define VDC51SC0_SCL0_FRC6 VDC51.SC0_SCL0_FRC6 +#define VDC51SC0_SCL0_FRC7 VDC51.SC0_SCL0_FRC7 +#define VDC51SC0_SCL0_FRC9 VDC51.SC0_SCL0_FRC9 +#define VDC51SC0_SCL0_MON0 VDC51.SC0_SCL0_MON0 +#define VDC51SC0_SCL0_INT VDC51.SC0_SCL0_INT +#define VDC51SC0_SCL0_DS1 VDC51.SC0_SCL0_DS1 +#define VDC51SC0_SCL0_DS2 VDC51.SC0_SCL0_DS2 +#define VDC51SC0_SCL0_DS3 VDC51.SC0_SCL0_DS3 +#define VDC51SC0_SCL0_DS4 VDC51.SC0_SCL0_DS4 +#define VDC51SC0_SCL0_DS5 VDC51.SC0_SCL0_DS5 +#define VDC51SC0_SCL0_DS6 VDC51.SC0_SCL0_DS6 +#define VDC51SC0_SCL0_DS7 VDC51.SC0_SCL0_DS7 +#define VDC51SC0_SCL0_US1 VDC51.SC0_SCL0_US1 +#define VDC51SC0_SCL0_US2 VDC51.SC0_SCL0_US2 +#define VDC51SC0_SCL0_US3 VDC51.SC0_SCL0_US3 +#define VDC51SC0_SCL0_US4 VDC51.SC0_SCL0_US4 +#define VDC51SC0_SCL0_US5 VDC51.SC0_SCL0_US5 +#define VDC51SC0_SCL0_US6 VDC51.SC0_SCL0_US6 +#define VDC51SC0_SCL0_US7 VDC51.SC0_SCL0_US7 +#define VDC51SC0_SCL0_US8 VDC51.SC0_SCL0_US8 +#define VDC51SC0_SCL0_OVR1 VDC51.SC0_SCL0_OVR1 +#define VDC51SC0_SCL1_UPDATE VDC51.SC0_SCL1_UPDATE +#define VDC51SC0_SCL1_WR1 VDC51.SC0_SCL1_WR1 +#define VDC51SC0_SCL1_WR2 VDC51.SC0_SCL1_WR2 +#define VDC51SC0_SCL1_WR3 VDC51.SC0_SCL1_WR3 +#define VDC51SC0_SCL1_WR4 VDC51.SC0_SCL1_WR4 +#define VDC51SC0_SCL1_WR5 VDC51.SC0_SCL1_WR5 +#define VDC51SC0_SCL1_WR6 VDC51.SC0_SCL1_WR6 +#define VDC51SC0_SCL1_WR7 VDC51.SC0_SCL1_WR7 +#define VDC51SC0_SCL1_WR8 VDC51.SC0_SCL1_WR8 +#define VDC51SC0_SCL1_WR9 VDC51.SC0_SCL1_WR9 +#define VDC51SC0_SCL1_WR10 VDC51.SC0_SCL1_WR10 +#define VDC51SC0_SCL1_WR11 VDC51.SC0_SCL1_WR11 +#define VDC51SC0_SCL1_MON1 VDC51.SC0_SCL1_MON1 +#define VDC51SC0_SCL1_PBUF0 VDC51.SC0_SCL1_PBUF0 +#define VDC51SC0_SCL1_PBUF1 VDC51.SC0_SCL1_PBUF1 +#define VDC51SC0_SCL1_PBUF2 VDC51.SC0_SCL1_PBUF2 +#define VDC51SC0_SCL1_PBUF3 VDC51.SC0_SCL1_PBUF3 +#define VDC51SC0_SCL1_PBUF_FLD VDC51.SC0_SCL1_PBUF_FLD +#define VDC51SC0_SCL1_PBUF_CNT VDC51.SC0_SCL1_PBUF_CNT +#define VDC51GR0_UPDATE VDC51.GR0_UPDATE +#define VDC51GR0_FLM_RD VDC51.GR0_FLM_RD +#define VDC51GR0_FLM1 VDC51.GR0_FLM1 +#define VDC51GR0_FLM2 VDC51.GR0_FLM2 +#define VDC51GR0_FLM3 VDC51.GR0_FLM3 +#define VDC51GR0_FLM4 VDC51.GR0_FLM4 +#define VDC51GR0_FLM5 VDC51.GR0_FLM5 +#define VDC51GR0_FLM6 VDC51.GR0_FLM6 +#define VDC51GR0_AB1 VDC51.GR0_AB1 +#define VDC51GR0_AB2 VDC51.GR0_AB2 +#define VDC51GR0_AB3 VDC51.GR0_AB3 +#define VDC51GR0_AB7 VDC51.GR0_AB7 +#define VDC51GR0_AB8 VDC51.GR0_AB8 +#define VDC51GR0_AB9 VDC51.GR0_AB9 +#define VDC51GR0_AB10 VDC51.GR0_AB10 +#define VDC51GR0_AB11 VDC51.GR0_AB11 +#define VDC51GR0_BASE VDC51.GR0_BASE +#define VDC51GR0_CLUT VDC51.GR0_CLUT +#define VDC51ADJ0_UPDATE VDC51.ADJ0_UPDATE +#define VDC51ADJ0_BKSTR_SET VDC51.ADJ0_BKSTR_SET +#define VDC51ADJ0_ENH_TIM1 VDC51.ADJ0_ENH_TIM1 +#define VDC51ADJ0_ENH_TIM2 VDC51.ADJ0_ENH_TIM2 +#define VDC51ADJ0_ENH_TIM3 VDC51.ADJ0_ENH_TIM3 +#define VDC51ADJ0_ENH_SHP1 VDC51.ADJ0_ENH_SHP1 +#define VDC51ADJ0_ENH_SHP2 VDC51.ADJ0_ENH_SHP2 +#define VDC51ADJ0_ENH_SHP3 VDC51.ADJ0_ENH_SHP3 +#define VDC51ADJ0_ENH_SHP4 VDC51.ADJ0_ENH_SHP4 +#define VDC51ADJ0_ENH_SHP5 VDC51.ADJ0_ENH_SHP5 +#define VDC51ADJ0_ENH_SHP6 VDC51.ADJ0_ENH_SHP6 +#define VDC51ADJ0_ENH_LTI1 VDC51.ADJ0_ENH_LTI1 +#define VDC51ADJ0_ENH_LTI2 VDC51.ADJ0_ENH_LTI2 +#define VDC51ADJ0_MTX_MODE VDC51.ADJ0_MTX_MODE +#define VDC51ADJ0_MTX_YG_ADJ0 VDC51.ADJ0_MTX_YG_ADJ0 +#define VDC51ADJ0_MTX_YG_ADJ1 VDC51.ADJ0_MTX_YG_ADJ1 +#define VDC51ADJ0_MTX_CBB_ADJ0 VDC51.ADJ0_MTX_CBB_ADJ0 +#define VDC51ADJ0_MTX_CBB_ADJ1 VDC51.ADJ0_MTX_CBB_ADJ1 +#define VDC51ADJ0_MTX_CRR_ADJ0 VDC51.ADJ0_MTX_CRR_ADJ0 +#define VDC51ADJ0_MTX_CRR_ADJ1 VDC51.ADJ0_MTX_CRR_ADJ1 +#define VDC51GR2_UPDATE VDC51.GR2_UPDATE +#define VDC51GR2_FLM_RD VDC51.GR2_FLM_RD +#define VDC51GR2_FLM1 VDC51.GR2_FLM1 +#define VDC51GR2_FLM2 VDC51.GR2_FLM2 +#define VDC51GR2_FLM3 VDC51.GR2_FLM3 +#define VDC51GR2_FLM4 VDC51.GR2_FLM4 +#define VDC51GR2_FLM5 VDC51.GR2_FLM5 +#define VDC51GR2_FLM6 VDC51.GR2_FLM6 +#define VDC51GR2_AB1 VDC51.GR2_AB1 +#define VDC51GR2_AB2 VDC51.GR2_AB2 +#define VDC51GR2_AB3 VDC51.GR2_AB3 +#define VDC51GR2_AB4 VDC51.GR2_AB4 +#define VDC51GR2_AB5 VDC51.GR2_AB5 +#define VDC51GR2_AB6 VDC51.GR2_AB6 +#define VDC51GR2_AB7 VDC51.GR2_AB7 +#define VDC51GR2_AB8 VDC51.GR2_AB8 +#define VDC51GR2_AB9 VDC51.GR2_AB9 +#define VDC51GR2_AB10 VDC51.GR2_AB10 +#define VDC51GR2_AB11 VDC51.GR2_AB11 +#define VDC51GR2_BASE VDC51.GR2_BASE +#define VDC51GR2_CLUT VDC51.GR2_CLUT +#define VDC51GR2_MON VDC51.GR2_MON +#define VDC51GR3_UPDATE VDC51.GR3_UPDATE +#define VDC51GR3_FLM_RD VDC51.GR3_FLM_RD +#define VDC51GR3_FLM1 VDC51.GR3_FLM1 +#define VDC51GR3_FLM2 VDC51.GR3_FLM2 +#define VDC51GR3_FLM3 VDC51.GR3_FLM3 +#define VDC51GR3_FLM4 VDC51.GR3_FLM4 +#define VDC51GR3_FLM5 VDC51.GR3_FLM5 +#define VDC51GR3_FLM6 VDC51.GR3_FLM6 +#define VDC51GR3_AB1 VDC51.GR3_AB1 +#define VDC51GR3_AB2 VDC51.GR3_AB2 +#define VDC51GR3_AB3 VDC51.GR3_AB3 +#define VDC51GR3_AB4 VDC51.GR3_AB4 +#define VDC51GR3_AB5 VDC51.GR3_AB5 +#define VDC51GR3_AB6 VDC51.GR3_AB6 +#define VDC51GR3_AB7 VDC51.GR3_AB7 +#define VDC51GR3_AB8 VDC51.GR3_AB8 +#define VDC51GR3_AB9 VDC51.GR3_AB9 +#define VDC51GR3_AB10 VDC51.GR3_AB10 +#define VDC51GR3_AB11 VDC51.GR3_AB11 +#define VDC51GR3_BASE VDC51.GR3_BASE +#define VDC51GR3_CLUT_INT VDC51.GR3_CLUT_INT +#define VDC51GR3_MON VDC51.GR3_MON +#define VDC51GAM_G_UPDATE VDC51.GAM_G_UPDATE +#define VDC51GAM_SW VDC51.GAM_SW +#define VDC51GAM_G_LUT1 VDC51.GAM_G_LUT1 +#define VDC51GAM_G_LUT2 VDC51.GAM_G_LUT2 +#define VDC51GAM_G_LUT3 VDC51.GAM_G_LUT3 +#define VDC51GAM_G_LUT4 VDC51.GAM_G_LUT4 +#define VDC51GAM_G_LUT5 VDC51.GAM_G_LUT5 +#define VDC51GAM_G_LUT6 VDC51.GAM_G_LUT6 +#define VDC51GAM_G_LUT7 VDC51.GAM_G_LUT7 +#define VDC51GAM_G_LUT8 VDC51.GAM_G_LUT8 +#define VDC51GAM_G_LUT9 VDC51.GAM_G_LUT9 +#define VDC51GAM_G_LUT10 VDC51.GAM_G_LUT10 +#define VDC51GAM_G_LUT11 VDC51.GAM_G_LUT11 +#define VDC51GAM_G_LUT12 VDC51.GAM_G_LUT12 +#define VDC51GAM_G_LUT13 VDC51.GAM_G_LUT13 +#define VDC51GAM_G_LUT14 VDC51.GAM_G_LUT14 +#define VDC51GAM_G_LUT15 VDC51.GAM_G_LUT15 +#define VDC51GAM_G_LUT16 VDC51.GAM_G_LUT16 +#define VDC51GAM_G_AREA1 VDC51.GAM_G_AREA1 +#define VDC51GAM_G_AREA2 VDC51.GAM_G_AREA2 +#define VDC51GAM_G_AREA3 VDC51.GAM_G_AREA3 +#define VDC51GAM_G_AREA4 VDC51.GAM_G_AREA4 +#define VDC51GAM_G_AREA5 VDC51.GAM_G_AREA5 +#define VDC51GAM_G_AREA6 VDC51.GAM_G_AREA6 +#define VDC51GAM_G_AREA7 VDC51.GAM_G_AREA7 +#define VDC51GAM_G_AREA8 VDC51.GAM_G_AREA8 +#define VDC51GAM_B_UPDATE VDC51.GAM_B_UPDATE +#define VDC51GAM_B_LUT1 VDC51.GAM_B_LUT1 +#define VDC51GAM_B_LUT2 VDC51.GAM_B_LUT2 +#define VDC51GAM_B_LUT3 VDC51.GAM_B_LUT3 +#define VDC51GAM_B_LUT4 VDC51.GAM_B_LUT4 +#define VDC51GAM_B_LUT5 VDC51.GAM_B_LUT5 +#define VDC51GAM_B_LUT6 VDC51.GAM_B_LUT6 +#define VDC51GAM_B_LUT7 VDC51.GAM_B_LUT7 +#define VDC51GAM_B_LUT8 VDC51.GAM_B_LUT8 +#define VDC51GAM_B_LUT9 VDC51.GAM_B_LUT9 +#define VDC51GAM_B_LUT10 VDC51.GAM_B_LUT10 +#define VDC51GAM_B_LUT11 VDC51.GAM_B_LUT11 +#define VDC51GAM_B_LUT12 VDC51.GAM_B_LUT12 +#define VDC51GAM_B_LUT13 VDC51.GAM_B_LUT13 +#define VDC51GAM_B_LUT14 VDC51.GAM_B_LUT14 +#define VDC51GAM_B_LUT15 VDC51.GAM_B_LUT15 +#define VDC51GAM_B_LUT16 VDC51.GAM_B_LUT16 +#define VDC51GAM_B_AREA1 VDC51.GAM_B_AREA1 +#define VDC51GAM_B_AREA2 VDC51.GAM_B_AREA2 +#define VDC51GAM_B_AREA3 VDC51.GAM_B_AREA3 +#define VDC51GAM_B_AREA4 VDC51.GAM_B_AREA4 +#define VDC51GAM_B_AREA5 VDC51.GAM_B_AREA5 +#define VDC51GAM_B_AREA6 VDC51.GAM_B_AREA6 +#define VDC51GAM_B_AREA7 VDC51.GAM_B_AREA7 +#define VDC51GAM_B_AREA8 VDC51.GAM_B_AREA8 +#define VDC51GAM_R_UPDATE VDC51.GAM_R_UPDATE +#define VDC51GAM_R_LUT1 VDC51.GAM_R_LUT1 +#define VDC51GAM_R_LUT2 VDC51.GAM_R_LUT2 +#define VDC51GAM_R_LUT3 VDC51.GAM_R_LUT3 +#define VDC51GAM_R_LUT4 VDC51.GAM_R_LUT4 +#define VDC51GAM_R_LUT5 VDC51.GAM_R_LUT5 +#define VDC51GAM_R_LUT6 VDC51.GAM_R_LUT6 +#define VDC51GAM_R_LUT7 VDC51.GAM_R_LUT7 +#define VDC51GAM_R_LUT8 VDC51.GAM_R_LUT8 +#define VDC51GAM_R_LUT9 VDC51.GAM_R_LUT9 +#define VDC51GAM_R_LUT10 VDC51.GAM_R_LUT10 +#define VDC51GAM_R_LUT11 VDC51.GAM_R_LUT11 +#define VDC51GAM_R_LUT12 VDC51.GAM_R_LUT12 +#define VDC51GAM_R_LUT13 VDC51.GAM_R_LUT13 +#define VDC51GAM_R_LUT14 VDC51.GAM_R_LUT14 +#define VDC51GAM_R_LUT15 VDC51.GAM_R_LUT15 +#define VDC51GAM_R_LUT16 VDC51.GAM_R_LUT16 +#define VDC51GAM_R_AREA1 VDC51.GAM_R_AREA1 +#define VDC51GAM_R_AREA2 VDC51.GAM_R_AREA2 +#define VDC51GAM_R_AREA3 VDC51.GAM_R_AREA3 +#define VDC51GAM_R_AREA4 VDC51.GAM_R_AREA4 +#define VDC51GAM_R_AREA5 VDC51.GAM_R_AREA5 +#define VDC51GAM_R_AREA6 VDC51.GAM_R_AREA6 +#define VDC51GAM_R_AREA7 VDC51.GAM_R_AREA7 +#define VDC51GAM_R_AREA8 VDC51.GAM_R_AREA8 +#define VDC51TCON_UPDATE VDC51.TCON_UPDATE +#define VDC51TCON_TIM VDC51.TCON_TIM +#define VDC51TCON_TIM_STVA1 VDC51.TCON_TIM_STVA1 +#define VDC51TCON_TIM_STVA2 VDC51.TCON_TIM_STVA2 +#define VDC51TCON_TIM_STVB1 VDC51.TCON_TIM_STVB1 +#define VDC51TCON_TIM_STVB2 VDC51.TCON_TIM_STVB2 +#define VDC51TCON_TIM_STH1 VDC51.TCON_TIM_STH1 +#define VDC51TCON_TIM_STH2 VDC51.TCON_TIM_STH2 +#define VDC51TCON_TIM_STB1 VDC51.TCON_TIM_STB1 +#define VDC51TCON_TIM_STB2 VDC51.TCON_TIM_STB2 +#define VDC51TCON_TIM_CPV1 VDC51.TCON_TIM_CPV1 +#define VDC51TCON_TIM_CPV2 VDC51.TCON_TIM_CPV2 +#define VDC51TCON_TIM_POLA1 VDC51.TCON_TIM_POLA1 +#define VDC51TCON_TIM_POLA2 VDC51.TCON_TIM_POLA2 +#define VDC51TCON_TIM_POLB1 VDC51.TCON_TIM_POLB1 +#define VDC51TCON_TIM_POLB2 VDC51.TCON_TIM_POLB2 +#define VDC51TCON_TIM_DE VDC51.TCON_TIM_DE +#define VDC51OUT_UPDATE VDC51.OUT_UPDATE +#define VDC51OUT_SET VDC51.OUT_SET +#define VDC51OUT_BRIGHT1 VDC51.OUT_BRIGHT1 +#define VDC51OUT_BRIGHT2 VDC51.OUT_BRIGHT2 +#define VDC51OUT_CONTRAST VDC51.OUT_CONTRAST +#define VDC51OUT_PDTHA VDC51.OUT_PDTHA +#define VDC51OUT_CLK_PHASE VDC51.OUT_CLK_PHASE +#define VDC51SYSCNT_INT1 VDC51.SYSCNT_INT1 +#define VDC51SYSCNT_INT2 VDC51.SYSCNT_INT2 +#define VDC51SYSCNT_INT3 VDC51.SYSCNT_INT3 +#define VDC51SYSCNT_INT4 VDC51.SYSCNT_INT4 +#define VDC51SYSCNT_INT5 VDC51.SYSCNT_INT5 +#define VDC51SYSCNT_INT6 VDC51.SYSCNT_INT6 +#define VDC51SYSCNT_PANEL_CLK VDC51.SYSCNT_PANEL_CLK +#define VDC51SYSCNT_CLUT VDC51.SYSCNT_CLUT +#define VDC51SC1_SCL0_UPDATE VDC51.SC1_SCL0_UPDATE +#define VDC51SC1_SCL0_FRC1 VDC51.SC1_SCL0_FRC1 +#define VDC51SC1_SCL0_FRC2 VDC51.SC1_SCL0_FRC2 +#define VDC51SC1_SCL0_FRC3 VDC51.SC1_SCL0_FRC3 +#define VDC51SC1_SCL0_FRC4 VDC51.SC1_SCL0_FRC4 +#define VDC51SC1_SCL0_FRC5 VDC51.SC1_SCL0_FRC5 +#define VDC51SC1_SCL0_FRC6 VDC51.SC1_SCL0_FRC6 +#define VDC51SC1_SCL0_FRC7 VDC51.SC1_SCL0_FRC7 +#define VDC51SC1_SCL0_FRC9 VDC51.SC1_SCL0_FRC9 +#define VDC51SC1_SCL0_MON0 VDC51.SC1_SCL0_MON0 +#define VDC51SC1_SCL0_INT VDC51.SC1_SCL0_INT +#define VDC51SC1_SCL0_DS1 VDC51.SC1_SCL0_DS1 +#define VDC51SC1_SCL0_DS2 VDC51.SC1_SCL0_DS2 +#define VDC51SC1_SCL0_DS3 VDC51.SC1_SCL0_DS3 +#define VDC51SC1_SCL0_DS4 VDC51.SC1_SCL0_DS4 +#define VDC51SC1_SCL0_DS5 VDC51.SC1_SCL0_DS5 +#define VDC51SC1_SCL0_DS6 VDC51.SC1_SCL0_DS6 +#define VDC51SC1_SCL0_DS7 VDC51.SC1_SCL0_DS7 +#define VDC51SC1_SCL0_US1 VDC51.SC1_SCL0_US1 +#define VDC51SC1_SCL0_US2 VDC51.SC1_SCL0_US2 +#define VDC51SC1_SCL0_US3 VDC51.SC1_SCL0_US3 +#define VDC51SC1_SCL0_US4 VDC51.SC1_SCL0_US4 +#define VDC51SC1_SCL0_US5 VDC51.SC1_SCL0_US5 +#define VDC51SC1_SCL0_US6 VDC51.SC1_SCL0_US6 +#define VDC51SC1_SCL0_US7 VDC51.SC1_SCL0_US7 +#define VDC51SC1_SCL0_US8 VDC51.SC1_SCL0_US8 +#define VDC51SC1_SCL0_OVR1 VDC51.SC1_SCL0_OVR1 +#define VDC51SC1_SCL1_UPDATE VDC51.SC1_SCL1_UPDATE +#define VDC51SC1_SCL1_WR1 VDC51.SC1_SCL1_WR1 +#define VDC51SC1_SCL1_WR2 VDC51.SC1_SCL1_WR2 +#define VDC51SC1_SCL1_WR3 VDC51.SC1_SCL1_WR3 +#define VDC51SC1_SCL1_WR4 VDC51.SC1_SCL1_WR4 +#define VDC51SC1_SCL1_WR5 VDC51.SC1_SCL1_WR5 +#define VDC51SC1_SCL1_WR6 VDC51.SC1_SCL1_WR6 +#define VDC51SC1_SCL1_WR7 VDC51.SC1_SCL1_WR7 +#define VDC51SC1_SCL1_WR8 VDC51.SC1_SCL1_WR8 +#define VDC51SC1_SCL1_WR9 VDC51.SC1_SCL1_WR9 +#define VDC51SC1_SCL1_WR10 VDC51.SC1_SCL1_WR10 +#define VDC51SC1_SCL1_WR11 VDC51.SC1_SCL1_WR11 +#define VDC51SC1_SCL1_MON1 VDC51.SC1_SCL1_MON1 +#define VDC51SC1_SCL1_PBUF0 VDC51.SC1_SCL1_PBUF0 +#define VDC51SC1_SCL1_PBUF1 VDC51.SC1_SCL1_PBUF1 +#define VDC51SC1_SCL1_PBUF2 VDC51.SC1_SCL1_PBUF2 +#define VDC51SC1_SCL1_PBUF3 VDC51.SC1_SCL1_PBUF3 +#define VDC51SC1_SCL1_PBUF_FLD VDC51.SC1_SCL1_PBUF_FLD +#define VDC51SC1_SCL1_PBUF_CNT VDC51.SC1_SCL1_PBUF_CNT +#define VDC51GR1_UPDATE VDC51.GR1_UPDATE +#define VDC51GR1_FLM_RD VDC51.GR1_FLM_RD +#define VDC51GR1_FLM1 VDC51.GR1_FLM1 +#define VDC51GR1_FLM2 VDC51.GR1_FLM2 +#define VDC51GR1_FLM3 VDC51.GR1_FLM3 +#define VDC51GR1_FLM4 VDC51.GR1_FLM4 +#define VDC51GR1_FLM5 VDC51.GR1_FLM5 +#define VDC51GR1_FLM6 VDC51.GR1_FLM6 +#define VDC51GR1_AB1 VDC51.GR1_AB1 +#define VDC51GR1_AB2 VDC51.GR1_AB2 +#define VDC51GR1_AB3 VDC51.GR1_AB3 +#define VDC51GR1_AB4 VDC51.GR1_AB4 +#define VDC51GR1_AB5 VDC51.GR1_AB5 +#define VDC51GR1_AB6 VDC51.GR1_AB6 +#define VDC51GR1_AB7 VDC51.GR1_AB7 +#define VDC51GR1_AB8 VDC51.GR1_AB8 +#define VDC51GR1_AB9 VDC51.GR1_AB9 +#define VDC51GR1_AB10 VDC51.GR1_AB10 +#define VDC51GR1_AB11 VDC51.GR1_AB11 +#define VDC51GR1_BASE VDC51.GR1_BASE +#define VDC51GR1_CLUT VDC51.GR1_CLUT +#define VDC51GR1_MON VDC51.GR1_MON +#define VDC51ADJ1_UPDATE VDC51.ADJ1_UPDATE +#define VDC51ADJ1_BKSTR_SET VDC51.ADJ1_BKSTR_SET +#define VDC51ADJ1_ENH_TIM1 VDC51.ADJ1_ENH_TIM1 +#define VDC51ADJ1_ENH_TIM2 VDC51.ADJ1_ENH_TIM2 +#define VDC51ADJ1_ENH_TIM3 VDC51.ADJ1_ENH_TIM3 +#define VDC51ADJ1_ENH_SHP1 VDC51.ADJ1_ENH_SHP1 +#define VDC51ADJ1_ENH_SHP2 VDC51.ADJ1_ENH_SHP2 +#define VDC51ADJ1_ENH_SHP3 VDC51.ADJ1_ENH_SHP3 +#define VDC51ADJ1_ENH_SHP4 VDC51.ADJ1_ENH_SHP4 +#define VDC51ADJ1_ENH_SHP5 VDC51.ADJ1_ENH_SHP5 +#define VDC51ADJ1_ENH_SHP6 VDC51.ADJ1_ENH_SHP6 +#define VDC51ADJ1_ENH_LTI1 VDC51.ADJ1_ENH_LTI1 +#define VDC51ADJ1_ENH_LTI2 VDC51.ADJ1_ENH_LTI2 +#define VDC51ADJ1_MTX_MODE VDC51.ADJ1_MTX_MODE +#define VDC51ADJ1_MTX_YG_ADJ0 VDC51.ADJ1_MTX_YG_ADJ0 +#define VDC51ADJ1_MTX_YG_ADJ1 VDC51.ADJ1_MTX_YG_ADJ1 +#define VDC51ADJ1_MTX_CBB_ADJ0 VDC51.ADJ1_MTX_CBB_ADJ0 +#define VDC51ADJ1_MTX_CBB_ADJ1 VDC51.ADJ1_MTX_CBB_ADJ1 +#define VDC51ADJ1_MTX_CRR_ADJ0 VDC51.ADJ1_MTX_CRR_ADJ0 +#define VDC51ADJ1_MTX_CRR_ADJ1 VDC51.ADJ1_MTX_CRR_ADJ1 +#define VDC51GR_VIN_UPDATE VDC51.GR_VIN_UPDATE +#define VDC51GR_VIN_AB1 VDC51.GR_VIN_AB1 +#define VDC51GR_VIN_AB2 VDC51.GR_VIN_AB2 +#define VDC51GR_VIN_AB3 VDC51.GR_VIN_AB3 +#define VDC51GR_VIN_AB4 VDC51.GR_VIN_AB4 +#define VDC51GR_VIN_AB5 VDC51.GR_VIN_AB5 +#define VDC51GR_VIN_AB6 VDC51.GR_VIN_AB6 +#define VDC51GR_VIN_AB7 VDC51.GR_VIN_AB7 +#define VDC51GR_VIN_BASE VDC51.GR_VIN_BASE +#define VDC51GR_VIN_MON VDC51.GR_VIN_MON +#define VDC51OIR_SCL0_UPDATE VDC51.OIR_SCL0_UPDATE +#define VDC51OIR_SCL0_FRC1 VDC51.OIR_SCL0_FRC1 +#define VDC51OIR_SCL0_FRC2 VDC51.OIR_SCL0_FRC2 +#define VDC51OIR_SCL0_FRC3 VDC51.OIR_SCL0_FRC3 +#define VDC51OIR_SCL0_FRC4 VDC51.OIR_SCL0_FRC4 +#define VDC51OIR_SCL0_FRC5 VDC51.OIR_SCL0_FRC5 +#define VDC51OIR_SCL0_FRC6 VDC51.OIR_SCL0_FRC6 +#define VDC51OIR_SCL0_FRC7 VDC51.OIR_SCL0_FRC7 +#define VDC51OIR_SCL0_DS1 VDC51.OIR_SCL0_DS1 +#define VDC51OIR_SCL0_DS2 VDC51.OIR_SCL0_DS2 +#define VDC51OIR_SCL0_DS3 VDC51.OIR_SCL0_DS3 +#define VDC51OIR_SCL0_DS7 VDC51.OIR_SCL0_DS7 +#define VDC51OIR_SCL0_US1 VDC51.OIR_SCL0_US1 +#define VDC51OIR_SCL0_US2 VDC51.OIR_SCL0_US2 +#define VDC51OIR_SCL0_US3 VDC51.OIR_SCL0_US3 +#define VDC51OIR_SCL0_US8 VDC51.OIR_SCL0_US8 +#define VDC51OIR_SCL0_OVR1 VDC51.OIR_SCL0_OVR1 +#define VDC51OIR_SCL1_UPDATE VDC51.OIR_SCL1_UPDATE +#define VDC51OIR_SCL1_WR1 VDC51.OIR_SCL1_WR1 +#define VDC51OIR_SCL1_WR2 VDC51.OIR_SCL1_WR2 +#define VDC51OIR_SCL1_WR3 VDC51.OIR_SCL1_WR3 +#define VDC51OIR_SCL1_WR4 VDC51.OIR_SCL1_WR4 +#define VDC51OIR_SCL1_WR5 VDC51.OIR_SCL1_WR5 +#define VDC51OIR_SCL1_WR6 VDC51.OIR_SCL1_WR6 +#define VDC51OIR_SCL1_WR7 VDC51.OIR_SCL1_WR7 +#define VDC51GR_OIR_UPDATE VDC51.GR_OIR_UPDATE +#define VDC51GR_OIR_FLM_RD VDC51.GR_OIR_FLM_RD +#define VDC51GR_OIR_FLM1 VDC51.GR_OIR_FLM1 +#define VDC51GR_OIR_FLM2 VDC51.GR_OIR_FLM2 +#define VDC51GR_OIR_FLM3 VDC51.GR_OIR_FLM3 +#define VDC51GR_OIR_FLM4 VDC51.GR_OIR_FLM4 +#define VDC51GR_OIR_FLM5 VDC51.GR_OIR_FLM5 +#define VDC51GR_OIR_FLM6 VDC51.GR_OIR_FLM6 +#define VDC51GR_OIR_AB1 VDC51.GR_OIR_AB1 +#define VDC51GR_OIR_AB2 VDC51.GR_OIR_AB2 +#define VDC51GR_OIR_AB3 VDC51.GR_OIR_AB3 +#define VDC51GR_OIR_AB7 VDC51.GR_OIR_AB7 +#define VDC51GR_OIR_AB8 VDC51.GR_OIR_AB8 +#define VDC51GR_OIR_AB9 VDC51.GR_OIR_AB9 +#define VDC51GR_OIR_AB10 VDC51.GR_OIR_AB10 +#define VDC51GR_OIR_AB11 VDC51.GR_OIR_AB11 +#define VDC51GR_OIR_BASE VDC51.GR_OIR_BASE +#define VDC51GR_OIR_CLUT VDC51.GR_OIR_CLUT +#define VDC51GR_OIR_MON VDC51.GR_OIR_MON +/* <-SEC M1.10.1 */ +/* <-QAC 0639 */ +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/wdt_iodefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,46 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : wdt_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef WDT_IODEFINE_H +#define WDT_IODEFINE_H + +struct st_wdt +{ /* WDT */ + volatile uint16_t WTCSR; /* WTCSR */ + volatile uint16_t WTCNT; /* WTCNT */ + volatile uint16_t WRCSR; /* WRCSR */ +}; + + +#define WDT (*(struct st_wdt *)0xFCFE0000uL) /* WDT */ + + +#define WDTWTCSR WDT.WTCSR +#define WDTWTCNT WDT.WTCNT +#define WDTWRCSR WDT.WRCSR +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/reg32_t.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,11 @@ +#ifndef __REG32_T +#define __REG32_T + +union reg32_t { + volatile uint32_t UINT32; + volatile uint16_t UINT16[2]; + volatile uint8_t UINT8[4]; +}; + + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/rza_io_regrw.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,83 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : rza_io_regrw.h +* $Rev: 1135 $ +* $Date:: 2014-08-08 10:11:30 +0900#$ +* Description : Low level register read/write header +*******************************************************************************/ +#ifndef RZA_IO_REGRW_H +#define RZA_IO_REGRW_H + +/****************************************************************************** +Includes <System Includes> , "Project Includes" +******************************************************************************/ +/* ==== includes each bit mask header ==== */ +#include "cpg_iobitmask.h" +#include "intc_iobitmask.h" +#include "bsc_iobitmask.h" +#include "dmac_iobitmask.h" +#include "mtu2_iobitmask.h" +#include "ostm_iobitmask.h" +#include "scif_iobitmask.h" +#include "rspi_iobitmask.h" +#include "riic_iobitmask.h" +#include "usb_iobitmask.h" +#include "gpio_iobitmask.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + + +/****************************************************************************** +Macro definitions +******************************************************************************/ + + +/****************************************************************************** +Variable Externs +******************************************************************************/ + + +/****************************************************************************** +Functions Prototypes +******************************************************************************/ +void RZA_IO_RegWrite_8 (volatile uint8_t * ioreg, uint8_t write_value, uint8_t shift, uint8_t mask); +void RZA_IO_RegWrite_16(volatile uint16_t * ioreg, uint16_t write_value, uint16_t shift, uint16_t mask); +void RZA_IO_RegWrite_32(volatile uint32_t * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask); +uint8_t RZA_IO_RegRead_8 (volatile uint8_t * ioreg, uint8_t shift, uint8_t mask); +uint16_t RZA_IO_RegRead_16 (volatile uint16_t * ioreg, uint16_t shift, uint16_t mask); +uint32_t RZA_IO_RegRead_32 (volatile uint32_t * ioreg, uint32_t shift, uint32_t mask); + +#ifdef __cplusplus +} +#endif + +#endif /* RZA_IO_REGRW_H */ + +/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/mmu_Renesas_RZ_A1.c Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,243 @@ +/**************************************************************************//** + * @file mmu_Renesas_RZ_A1.c + * @brief MMU Startup File for + * mmu_Renesas_RZ_A1 Device Series + * @version V1.01 + * @date 2 Aug 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2011 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#define Renesas_RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */ +#define Renesas_RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */ +#define Renesas_RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */ +#define Renesas_RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */ +// L1 Cache info and restrictions about architecture of the caches (CCSIR register): +// Write-Through support *not* available +// Write-Back support available. +// Read allocation support available. +// Write allocation support available. + +//Note: You should use the Shareable attribute carefully. +//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless the inner cache settings. +//CA9-RTX uses LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. +//Some A9 implementations does not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. + +//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. +//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable. +//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable. + + +//Following MMU configuration is expected +//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag) +//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) +//Domain 0 is always the Client domain +//Descriptors place all memory in domain 0 +//There are no restrictions by privilege level (PL0 can access all memory) + +#include <stdint.h> +#include "VKRZA1H.h" + +//Import symbols from linker +extern uint32_t Image$$VECTORS$$Base; +extern uint32_t Image$$RO_DATA$$Base; +extern uint32_t Image$$RW_DATA$$Base; +extern uint32_t Image$$ZI_DATA$$Base; +#if !defined ( __ICCARM__ ) +extern uint32_t Image$$TTB$$ZI$$Base; +#endif + +#if defined( __CC_ARM ) +#elif defined( __ICCARM__ ) +#else +extern uint32_t Image$$RW_DATA_NC$$Base; +extern uint32_t Image$$ZI_DATA_NC$$Base; +#endif + +extern uint32_t Image$$VECTORS$$Limit; +extern uint32_t Image$$RO_DATA$$Limit; +extern uint32_t Image$$RW_DATA$$Limit; +extern uint32_t Image$$ZI_DATA$$Limit; +#if defined( __CC_ARM ) +#else +extern uint32_t Image$$RW_DATA_NC$$Limit; +extern uint32_t Image$$ZI_DATA_NC$$Limit; +#endif + +#if defined( __ICCARM__ ) +#define VECTORS_SIZE (((uint32_t)Image$$VECTORS$$Limit >> 20) - ((uint32_t)Image$$VECTORS$$Base >> 20) + 1) +#define RO_DATA_SIZE (((uint32_t)Image$$RO_DATA$$Limit >> 20) - ((uint32_t)Image$$RO_DATA$$Base >> 20) + 1) +#define RW_DATA_SIZE (((uint32_t)Image$$RW_DATA$$Limit >> 20) - ((uint32_t)Image$$RW_DATA$$Base >> 20) + 1) +#define ZI_DATA_SIZE (((uint32_t)Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)Image$$ZI_DATA$$Base >> 20) + 1) +#else +#define VECTORS_SIZE (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1) +#define RO_DATA_SIZE (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1) +#define RW_DATA_SIZE (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1) +#define ZI_DATA_SIZE (((uint32_t)&Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA$$Base >> 20) + 1) +#endif + +#if defined( __CC_ARM ) +#else +#define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1) +#define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1) +#endif + +static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 +static uint32_t Sect_Normal_NC; //non-shareable, non-executable, rw, domain 0, base addr 0 +static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 +static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable +static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable +static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0 +static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable + +/* Define global descriptors */ +static uint32_t Page_L1_4k = 0x0; //generic +static uint32_t Page_L1_64k = 0x0; //generic +static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0 +static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0 + +#if defined ( __ICCARM__ ) +__no_init uint32_t Image$$TTB$$ZI$$Base @ ".retram"; +uint32_t Image$$VECTORS$$Base; +uint32_t Image$$RO_DATA$$Base; +uint32_t Image$$RW_DATA$$Base; +uint32_t Image$$ZI_DATA$$Base; + +uint32_t Image$$VECTORS$$Limit; +uint32_t Image$$RO_DATA$$Limit; +uint32_t Image$$RW_DATA$$Limit; +uint32_t Image$$ZI_DATA$$Limit; +#endif + +void create_translation_table(void) +{ + mmu_region_attributes_Type region; +#if defined ( __ICCARM__ ) +#pragma section=".intvec" +#pragma section=".rodata" +#pragma section=".rwdata" +#pragma section=".bss" + + Image$$VECTORS$$Base = (uint32_t) __section_begin(".intvec"); + Image$$VECTORS$$Limit= ((uint32_t)__section_begin(".intvec")+(uint32_t)__section_size(".intvec")); + Image$$RO_DATA$$Base = (uint32_t) __section_begin(".rodata"); + Image$$RO_DATA$$Limit= ((uint32_t)__section_begin(".rodata")+(uint32_t)__section_size(".rodata")); + Image$$RW_DATA$$Base = (uint32_t) __section_begin(".rwdata"); + Image$$RW_DATA$$Limit= ((uint32_t)__section_begin(".rwdata")+(uint32_t)__section_size(".rwdata")); + Image$$ZI_DATA$$Base = (uint32_t) __section_begin(".bss"); + Image$$ZI_DATA$$Limit= ((uint32_t)__section_begin(".bss")+(uint32_t)__section_size(".bss")); +#endif + /* + * Generate descriptors. Refer to VKRZA1H.h to get information about attributes + * + */ + //Create descriptors for Vectors, RO, RW, ZI sections + section_normal(Sect_Normal, region); + section_normal_cod(Sect_Normal_Cod, region); + section_normal_ro(Sect_Normal_RO, region); + section_normal_rw(Sect_Normal_RW, region); + //Create descriptors for peripherals + section_device_ro(Sect_Device_RO, region); + section_device_rw(Sect_Device_RW, region); + section_normal_nc(Sect_Normal_NC, region); + //Create descriptors for 64k pages + page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region); + //Create descriptors for 4k pages + page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region); + + /* + * Define MMU flat-map regions and attributes + * + */ + + //Create 4GB of faulting entries + __TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT); + + // R7S72100 memory map. + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE0 , 64, Sect_Normal_RO); + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE1 , 64, Sect_Normal_RO); + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE0 , 64, Sect_Normal_RW); + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE1 , 64, Sect_Normal_RW); + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA0 , 64, Sect_Normal_RW); + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA1 , 64, Sect_Normal_RW); + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO0 , 64, Sect_Normal_RO); + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO1 , 64, Sect_Normal_RO); + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_BASE , 10, Sect_Normal_RW); + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_MIO_BASE , 1, Sect_Device_RW); + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_BSC_BASE , 1, Sect_Device_RW); + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE0 , 3, Sect_Device_RW); + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE1 , 49, Sect_Device_RW); + +#if defined( __ICCARM__ ) + //Define Image + __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_RO); + __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod); + __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW); + __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$ZI_DATA$$Base, ZI_DATA_SIZE, Sect_Normal_RW); +#else + //Define Image + __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_RO); + __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod); + __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW); + __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, ZI_DATA_SIZE, Sect_Normal_RW); +#endif + +#if defined( __CC_ARM ) + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE, 10, Sect_Normal_NC); +#elif defined ( __ICCARM__ ) + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE, 10, Sect_Normal_NC); + +#else + __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC); + __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC); +#endif + + /* Set location of level 1 page table + ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) + ; 13:7 - 0x0 + ; 6 - IRGN[0] 0x0 (Inner WB WA) + ; 5 - NOS 0x0 (Non-shared) + ; 4:3 - RGN 0x1 (Outer WB WA) + ; 2 - IMP 0x0 (Implementation Defined) + ; 1 - S 0x0 (Non-shared) + ; 0 - IRGN[1] 0x1 (Inner WB WA) */ + __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9); + + /* Set up domain access control register + ; We set domain 0 to Client and all other domains to No Access. + ; All translation table entries specify domain 0 */ + __set_DACR(1); +} + + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/nvic_wrapper.c Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,229 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/**************************************************************************//** +* @file nvic_wrapper.c +* $Rev: $ +* $Date:: $ +* @brief Wrapper between NVIC(for Cortex-M) and GIC(for Cortex-A9) +******************************************************************************/ + +/****************************************************************************** +Includes <System Includes> , "Project Includes" +******************************************************************************/ +#include "VKRZA1H.h" +#include "wdt_iodefine.h" +#include "nvic_wrapper.h" +#include "gic.h" + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Macro definitions +******************************************************************************/ +#define PRIO_BITS (7) /* Set binary point to 0 in gic.c */ +#define WDT_WTCNT_WRITE (0x5A00) +#define WDT_WTCSR_WRITE (0xA500) +#define WDT_WRCSR_WOVF_WRITE (0xA500) +#define WDT_WRCSR_RSTE_WRITE (0x5A00) + +/****************************************************************************** +Imported global variables and functions (from other files) +******************************************************************************/ + +/****************************************************************************** +Exported global variables and functions (to be accessed by other files) +******************************************************************************/ + +/****************************************************************************** +Private global variables and functions +******************************************************************************/ + + + +/* ########################## NVIC functions #################################### */ +void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + GIC_SetBinaryPoint(PriorityGroup); +} + + +uint32_t NVIC_GetPriorityGrouping(void) +{ + return GIC_GetBinaryPoint(0); +} + + +void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + GIC_EnableIRQ(IRQn); +} + + +void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + GIC_DisableIRQ(IRQn); +} + + +uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + uint32_t pending; + + pending = GIC_GetIRQStatus(IRQn); + pending = (pending & 0x00000001); + + return pending; +} + + +void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + GIC_SetPendingIRQ(IRQn); +} + + +void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + GIC_ClearPendingIRQ(IRQn); +} + + +uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + uint32_t active; + + active = GIC_GetIRQStatus(IRQn); + active = ((active >> 1) & 0x00000001); + + return active; +} + + +void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + GIC_SetPriority(IRQn, (priority << 3)); +} + + +uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + uint32_t priority_field; + + priority_field = GIC_GetPriority(IRQn); + priority_field = (priority_field >> 3); + return priority_field; +} + + +uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > PRIO_BITS) ? PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > PRIO_BITS) ? PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + +void NVIC_SystemReset(void) +{ + uint16_t reg; + uint8_t dummy_read; + /* Use Watch Dog Timer to system reset */ + + /* Set WT/IT bit of WTCSR to 1 = Watch Dog */ + /* CLK = 000, 1xP0phi(=33.3333MHz) = 7.7us */ + reg = (WDT_WTCSR_WRITE | 0x0058); + WDTWTCSR = reg; + + /* Clear Count reg */ + reg = (WDT_WTCNT_WRITE | 0x0000); + WDTWTCNT = reg; + + /* Clear WOVF flag */ + dummy_read = WDTWRCSR; + reg = (WDT_WRCSR_WOVF_WRITE | (dummy_read & 0x0000)); + WDTWRCSR = reg; + /* Enable Internal Reset */ + reg = (WDT_WRCSR_RSTE_WRITE | 0x005F); + WDTWRCSR = reg; + + /* Watch Dog start */ + reg = (WDT_WTCSR_WRITE | 0x0078); + WDTWTCSR = reg; + + while(1); /* wait Internal Reset */ +} + +/* ################################## SysTick function ############################################ */ +uint32_t SysTick_Config(uint32_t ticks) +{ + /* Not support this function */ + /* Use mbed Ticker */ + return (1); /* impossible */ +} + + +/* ##################################### Debug In/Output function ########################################### */ +uint32_t ITM_SendChar (uint32_t ch) +{ + /* Not support this function */ + /* Use mbed Serial */ + return (ch); +} + + +int32_t ITM_ReceiveChar (void) { + /* Not support this function */ + /* Use mbed Serial */ + return (-1); /* no character available */ +} + + +int32_t ITM_CheckChar (void) { + /* Not support this function */ + /* Use mbed Serial */ + return (0); /* no character available */ +} +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/nvic_wrapper.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,84 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/**************************************************************************//** +* @file nvic_wrapper.h +* $Rev: $ +* $Date:: $ +* @brief Wrapper between NVIC(for Cortex-M) and GIC(for Cortex-A9) +******************************************************************************/ + +#ifndef NVIC_WRAPPER_H +#define NVIC_WRAPPER_H + + +/****************************************************************************** +Includes <System Includes> , "Project Includes" +******************************************************************************/ +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Macro definitions +******************************************************************************/ + +/****************************************************************************** +Variable Externs +******************************************************************************/ + +/****************************************************************************** +Functions Prototypes +******************************************************************************/ + +/* NVIC functions */ +void NVIC_SetPriorityGrouping(uint32_t PriorityGroup); +uint32_t NVIC_GetPriorityGrouping(void); +void NVIC_EnableIRQ(IRQn_Type IRQn); +void NVIC_DisableIRQ(IRQn_Type IRQn); +uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn); +void NVIC_SetPendingIRQ(IRQn_Type IRQn); +void NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t NVIC_GetActive(IRQn_Type IRQn); +void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority); +uint32_t NVIC_GetPriority(IRQn_Type IRQn); +uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority); +void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); +void NVIC_SystemReset(void); +/* SysTick function */ +uint32_t SysTick_Config(uint32_t ticks); +/* Debug In/Output function */ +uint32_t ITM_SendChar (uint32_t ch); +int32_t ITM_ReceiveChar (void); +int32_t ITM_CheckChar (void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* NVIC_WRAPPER_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/pl310.c Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,128 @@ +/**************************************************************************//** + * @file pl310.c + * @brief Implementation of PL310 PrimeCell Level 2 Cache Controller functions + * @version + * @date 3 December 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2011 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ +#include "VKRZA1H.h" + +//Cache Sync operation +void PL310_Sync(void) +{ + PL310->CACHE_SYNC = 0x0; +} + +//return Cache controller cache ID +int PL310_GetID (void) +{ + return PL310->CACHE_ID; +} + +//return Cache controller cache Type +int PL310_GetType (void) +{ + return PL310->CACHE_TYPE; +} + +//Invalidate all cache by way +void PL310_InvAllByWay (void) +{ + unsigned int assoc; + + if (PL310->AUX_CNT & (1<<16)) + assoc = 16; + else + assoc = 8; + + PL310->INV_WAY = (1 << assoc) - 1; + while(PL310->INV_WAY & ((1 << assoc) - 1)); //poll invalidate + + PL310_Sync(); +} + +//Clean and Invalidate all cache by way +void PL310_CleanInvAllByWay (void) +{ + unsigned int assoc; + + if (PL310->AUX_CNT & (1<<16)) + assoc = 16; + else + assoc = 8; + + PL310->CLEAN_INV_WAY = (1 << assoc) - 1; + while(PL310->CLEAN_INV_WAY & ((1 << assoc) - 1)); //poll invalidate + + PL310_Sync(); +} + +//Enable Cache +void PL310_Enable(void) +{ + PL310->CONTROL = 0; + PL310->INTERRUPT_CLEAR = 0x000001FFuL; + PL310->DEBUG_CONTROL = 0; + PL310->DATA_LOCK_0_WAY = 0; + PL310->CACHE_SYNC = 0; + + PL310->CONTROL = 0x01; + PL310_Sync(); +} +//Disable Cache +void PL310_Disable(void) +{ + PL310->CONTROL = 0x00; + PL310_Sync(); +} + +//Invalidate cache by physical address +void PL310_InvPa (void *pa) +{ + PL310->INV_LINE_PA = (unsigned int)pa; + PL310_Sync(); +} + +//Clean cache by physical address +void PL310_CleanPa (void *pa) +{ + PL310->CLEAN_LINE_PA = (unsigned int)pa; + PL310_Sync(); +} + +//Clean and invalidate cache by physical address +void PL310_CleanInvPa (void *pa) +{ + PL310->CLEAN_INV_LINE_PA = (unsigned int)pa; + PL310_Sync(); +} + +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/pl310.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,114 @@ +/**************************************************************************//** + * @file pl310.h + * @brief Implementation of pl310 functions + * @version + * @date 11 June 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2011 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#ifndef __PL310 +#define __PL310 + +typedef struct +{ + __I uint32_t CACHE_ID; /*!< Offset: 0x0000 Cache ID Register */ + __I uint32_t CACHE_TYPE; /*!< Offset: 0x0004 Cache Type Register */ + uint32_t RESERVED0[0x3e]; + __IO uint32_t CONTROL; /*!< Offset: 0x0100 Control Register */ + __IO uint32_t AUX_CNT; /*!< Offset: 0x0104 Auxiliary Control */ + uint32_t RESERVED1[0x3e]; + __IO uint32_t EVENT_CONTROL; /*!< Offset: 0x0200 Event Counter Control */ + __IO uint32_t EVENT_COUNTER1_CONF; /*!< Offset: 0x0204 Event Counter 1 Configuration */ + __IO uint32_t EVENT_COUNTER0_CONF; /*!< Offset: 0x0208 Event Counter 1 Configuration */ + uint32_t RESERVED2[0x2]; + __IO uint32_t INTERRUPT_MASK; /*!< Offset: 0x0214 Interrupt Mask */ + __I uint32_t MASKED_INT_STATUS; /*!< Offset: 0x0218 Masked Interrupt Status */ + __I uint32_t RAW_INT_STATUS; /*!< Offset: 0x021c Raw Interrupt Status */ + __O uint32_t INTERRUPT_CLEAR; /*!< Offset: 0x0220 Interrupt Clear */ + uint32_t RESERVED3[0x143]; + __IO uint32_t CACHE_SYNC; /*!< Offset: 0x0730 Cache Sync */ + uint32_t RESERVED4[0xf]; + __IO uint32_t INV_LINE_PA; /*!< Offset: 0x0770 Invalidate Line By PA */ + uint32_t RESERVED6[2]; + __IO uint32_t INV_WAY; /*!< Offset: 0x077c Invalidate by Way */ + uint32_t RESERVED5[0xc]; + __IO uint32_t CLEAN_LINE_PA; /*!< Offset: 0x07b0 Clean Line by PA */ + uint32_t RESERVED7[1]; + __IO uint32_t CLEAN_LINE_INDEX_WAY; /*!< Offset: 0x07b8 Clean Line by Index/Way */ + __IO uint32_t CLEAN_WAY; /*!< Offset: 0x07bc Clean by Way */ + uint32_t RESERVED8[0xc]; + __IO uint32_t CLEAN_INV_LINE_PA; /*!< Offset: 0x07f0 Clean and Invalidate Line by PA */ + uint32_t RESERVED9[1]; + __IO uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< Offset: 0x07f8 Clean and Invalidate Line by Index/Way */ + __IO uint32_t CLEAN_INV_WAY; /*!< Offset: 0x07fc Clean and Invalidate by Way */ + uint32_t RESERVED10[0x40]; + __IO uint32_t DATA_LOCK_0_WAY; /*!< Offset: 0x0900 Data Lockdown 0 by Way */ + __IO uint32_t INST_LOCK_0_WAY; /*!< Offset: 0x0904 Instruction Lockdown 0 by Way */ + __IO uint32_t DATA_LOCK_1_WAY; /*!< Offset: 0x0908 Data Lockdown 1 by Way */ + __IO uint32_t INST_LOCK_1_WAY; /*!< Offset: 0x090c Instruction Lockdown 1 by Way */ + __IO uint32_t DATA_LOCK_2_WAY; /*!< Offset: 0x0910 Data Lockdown 2 by Way */ + __IO uint32_t INST_LOCK_2_WAY; /*!< Offset: 0x0914 Instruction Lockdown 2 by Way */ + __IO uint32_t DATA_LOCK_3_WAY; /*!< Offset: 0x0918 Data Lockdown 3 by Way */ + __IO uint32_t INST_LOCK_3_WAY; /*!< Offset: 0x091c Instruction Lockdown 3 by Way */ + __IO uint32_t DATA_LOCK_4_WAY; /*!< Offset: 0x0920 Data Lockdown 4 by Way */ + __IO uint32_t INST_LOCK_4_WAY; /*!< Offset: 0x0924 Instruction Lockdown 4 by Way */ + __IO uint32_t DATA_LOCK_5_WAY; /*!< Offset: 0x0928 Data Lockdown 5 by Way */ + __IO uint32_t INST_LOCK_5_WAY; /*!< Offset: 0x092c Instruction Lockdown 5 by Way */ + __IO uint32_t DATA_LOCK_6_WAY; /*!< Offset: 0x0930 Data Lockdown 5 by Way */ + __IO uint32_t INST_LOCK_6_WAY; /*!< Offset: 0x0934 Instruction Lockdown 5 by Way */ + __IO uint32_t DATA_LOCK_7_WAY; /*!< Offset: 0x0938 Data Lockdown 6 by Way */ + __IO uint32_t INST_LOCK_7_WAY; /*!< Offset: 0x093c Instruction Lockdown 6 by Way */ + uint32_t RESERVED11[0x4]; + __IO uint32_t LOCK_LINE_EN; /*!< Offset: 0x0950 Lockdown by Line Enable */ + __IO uint32_t UNLOCK_ALL_BY_WAY; /*!< Offset: 0x0954 Unlock All Lines by Way */ + uint32_t RESERVED12[0xaa]; + __IO uint32_t ADDRESS_FILTER_START; /*!< Offset: 0x0c00 Address Filtering Start */ + __IO uint32_t ADDRESS_FILTER_END; /*!< Offset: 0x0c04 Address Filtering End */ + uint32_t RESERVED13[0xce]; + __IO uint32_t DEBUG_CONTROL; /*!< Offset: 0x0f40 Debug Control Register */ + +} PL310_TypeDef; + +#define PL310 ((PL310_TypeDef *)Renesas_RZ_A1_PL310_BASE) /*!< PL310 Declaration */ + +extern int PL310_GetID (void); +extern int PL310_GetType (void); +extern void PL310_InvAllByWay (void); +extern void PL310_CleanInvAllByWay(void); +extern void PL310_Enable(void); +extern void PL310_Disable(void); +extern void PL310_InvPa (void *); +extern void PL310_CleanPa (void *); +extern void PL310_CleanInvPa (void *); + +#endif + +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/r_typedefs.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,61 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2013 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : r_typedefs.h +* $Rev: 788 $ +* $Date:: 2014-04-07 18:57:13 +0900#$ +* Description : basic type definition +******************************************************************************/ +#ifndef R_TYPEDEFS_H +#define R_TYPEDEFS_H + +/****************************************************************************** +Includes <System Includes> , "Project Includes" +******************************************************************************/ +#include <stddef.h> +#include <stdbool.h> +#include <stdint.h> + +#if defined(__ARM_NEON__) + +#include <arm_neon.h> + +#else /* __ARM_NEON__ */ + +typedef float float32_t; +typedef double float64_t; + +#endif /* __ARM_NEON__ */ + +/****************************************************************************** +Typedef definitions +******************************************************************************/ +typedef char char_t; +typedef int bool_t; +typedef int int_t; +typedef long double float128_t; +typedef signed long long_t; +typedef unsigned long ulong_t; + +#endif /* R_TYPEDEFS_H */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/rza_io_regrw.c Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,200 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : rza_io_regrw.c +* $Rev: 1121 $ +* $Date:: 2014-08-06 17:09:53 +0900#$ +* Description : Low level register read/write +*******************************************************************************/ + +/****************************************************************************** +Includes <System Includes> , "Project Includes" +******************************************************************************/ +#include "r_typedefs.h" + +#ifdef __CC_ARM +#pragma arm section code = "CODE_IO_REGRW" +#pragma arm section rodata = "CONST_IO_REGRW" +#pragma arm section rwdata = "DATA_IO_REGRW" +#pragma arm section zidata = "BSS_IO_REGRW" +#endif + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + + +/****************************************************************************** +Macro definitions +******************************************************************************/ + + +/****************************************************************************** +Imported global variables and functions (from other files) +******************************************************************************/ + + +/****************************************************************************** +Exported global variables and functions (to be accessed by other files) +******************************************************************************/ + + +/****************************************************************************** +Private global variables and functions +******************************************************************************/ + + +/****************************************************************************** +* Function Name: RZA_IO_RegWrite_8 +* Description : IO register 8-bit write +* Arguments : volatile uint8_t * ioreg : IO register for writing +* : : Use register definition name of the +* : : iodefine.h +* : uint8_t write_value : Write value for the IO register +* : uint8_t shift : The number of left shifts to the +* : : target bit +* : uint8_t mask : Mask value for the IO register +* : : (Target bit : "1") +* Return Value : None +******************************************************************************/ +void RZA_IO_RegWrite_8(volatile uint8_t * ioreg, uint8_t write_value, uint8_t shift, uint8_t mask) +{ + uint8_t reg_value; + + reg_value = *ioreg; /* Read from register */ + reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value */ + *ioreg = reg_value; /* Write to register */ +} + +/****************************************************************************** +* Function Name: RZA_IO_RegWrite_16 +* Description : IO register 16-bit write +* Arguments : volatile uint16_t * ioreg : IO register for writing +* : : Use register definition name of the +* : : iodefine.h +* : uint16_t write_value : Write value for the IO register +* : uint16_t shift : The number of left shifts to the +* : : target bit +* : uint16_t mask : Mask value for the IO register +* : : (Target bit : "1") +* Return Value : None +******************************************************************************/ +void RZA_IO_RegWrite_16(volatile uint16_t * ioreg, uint16_t write_value, uint16_t shift, uint16_t mask) +{ + uint16_t reg_value; + + reg_value = *ioreg; /* Read from register */ + reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value */ + *ioreg = reg_value; /* Write to register */ +} + +/****************************************************************************** +* Function Name: RZA_IO_RegWrite_32 +* Description : IO register 32-bit write +* Arguments : volatile uint32_t * ioreg : IO register for writing +* : : Use register definition name of the +* : : iodefine.h +* : uint32_t write_value : Write value for the IO register +* : uint32_t shift : The number of left shifts to the +* : : target bit +* : uint32_t mask : Mask value for the IO register +* : : (Target bit : "1") +* Return Value : None +******************************************************************************/ +void RZA_IO_RegWrite_32(volatile uint32_t * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask) +{ + uint32_t reg_value; + + reg_value = *ioreg; /* Read from register */ + reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value */ + *ioreg = reg_value; /* Write to register */ +} + +/****************************************************************************** +* Function Name: RZA_IO_RegRead_8 +* Description : IO register 8-bit read +* Arguments : volatile uint8_t * ioreg : IO register for reading +* : : Use register definition name of the +* : : iodefine.h +* : uint8_t shift : The number of right shifts to the +* : : target bit +* : uint8_t mask : Mask bit for the IO register +* : : (Target bit: "1") +* Return Value : uint8_t : Value of the obtained target bit +******************************************************************************/ +uint8_t RZA_IO_RegRead_8(volatile uint8_t * ioreg, uint8_t shift, uint8_t mask) +{ + uint8_t reg_value; + + reg_value = *ioreg; /* Read from register */ + reg_value = (reg_value & mask) >> shift; /* Clear other bit and Bit shift */ + + return reg_value; +} + +/****************************************************************************** +* Function Name: RZA_IO_RegRead_16 +* Description : IO register 16-bit read +* Arguments : volatile uint16_t * ioreg : IO register for reading +* : : Use register definition name of the +* : : iodefine.h +* : uint16_t shift : The number of right shifts to the +* : : target bit +* : uint16_t mask : Mask bit for the IO register +* : : (Target bit: "1") +* Return Value : uint16_t : Value of the obtained target bit +******************************************************************************/ +uint16_t RZA_IO_RegRead_16(volatile uint16_t * ioreg, uint16_t shift, uint16_t mask) +{ + uint16_t reg_value; + + reg_value = *ioreg; /* Read from register */ + reg_value = (reg_value & mask) >> shift; /* Clear other bit and Bit shift */ + + return reg_value; +} + +/****************************************************************************** +* Function Name: RZA_IO_RegRead_32 +* Description : IO register 32-bit read +* Arguments : volatile uint32_t * ioreg : IO register for reading +* : : Use register definition name of the +* : : iodefine.h +* : uint32_t shift : The number of right shifts to the +* : : target bit +* : uint32_t mask : Mask bit for the IO register +* : : (Target bit: "1") +* Return Value : uint32_t : Value of the obtained target bit +******************************************************************************/ +uint32_t RZA_IO_RegRead_32(volatile uint32_t * ioreg, uint32_t shift, uint32_t mask) +{ + uint32_t reg_value; + + reg_value = *ioreg; /* Read from register */ + reg_value = (reg_value & mask) >> shift; /* Clear other bit and Bit shift */ + + return reg_value; +} + + +/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.c Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,485 @@ +/**************************************************************************//** + * @file system_VKRZA1H.c + * @brief CMSIS Device System Source File for + * ARM Cortex-A9 Device Series + * @version V1.00 + * @date 09 January 2015 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2011 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#include <stdint.h> +#include "VKRZA1H.h" +#include "RZ_A1_Init.h" + + +#if defined(__ARMCC_VERSION) +extern void $Super$$main(void); +__asm void FPUEnable(void); +#else +void FPUEnable(void); + +#endif + +uint32_t IRQNestLevel; +unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075 + + +/** + * Initialize the cache. + * + * @param none + * @return none + * + * @brief Initialise caches. Requires PL1, so implemented as an SVC in case threads are USR mode. + */ +#if defined(__ARMCC_VERSION) +#pragma push +#pragma arm + +void InitMemorySubsystem(void) { + + /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before + * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC. + * You are not required to invalidate the main TLB, even though it is recommended for safety + * reasons. This ensures compatibility with future revisions of the processor. */ + + unsigned int l2_id; + + /* Invalidate undefined data */ + __ca9u_inv_tlb_all(); + __v7_inv_icache_all(); + __v7_inv_dcache_all(); + __v7_inv_btac(); + + /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and + * invalidate in order to flush the valid data to the next level cache. + */ + __enable_mmu(); + + /* After MMU is enabled and data has been invalidated, enable caches and BTAC */ + __enable_caches(); + __enable_btac(); + + /* If present, you may also need to Invalidate and Enable L2 cache here */ + l2_id = PL310_GetID(); + if (l2_id) + { + PL310_InvAllByWay(); + PL310_Enable(); + } +} +#pragma pop + +#elif defined(__GNUC__) + +void InitMemorySubsystem(void) { + + /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before + * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC. + * You are not required to invalidate the main TLB, even though it is recommended for safety + * reasons. This ensures compatibility with future revisions of the processor. */ + + unsigned int l2_id; + + /* Invalidate undefined data */ + __ca9u_inv_tlb_all(); + __v7_inv_icache_all(); + __v7_inv_dcache_all(); + __v7_inv_btac(); + + /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and + * invalidate in order to flush the valid data to the next level cache. + */ + __enable_mmu(); + + /* After MMU is enabled and data has been invalidated, enable caches and BTAC */ + __enable_caches(); + __enable_btac(); + + /* If present, you may also need to Invalidate and Enable L2 cache here */ + l2_id = PL310_GetID(); + if (l2_id) + { + PL310_InvAllByWay(); + PL310_Enable(); + } +} +#elif defined ( __ICCARM__ ) + +void InitMemorySubsystem(void) { + + /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before + * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC. + * You are not required to invalidate the main TLB, even though it is recommended for safety + * reasons. This ensures compatibility with future revisions of the processor. */ + + unsigned int l2_id; + + /* Invalidate undefined data */ + __ca9u_inv_tlb_all(); + __v7_inv_icache_all(); + __v7_inv_dcache_all(); + __v7_inv_btac(); + + /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and + * invalidate in order to flush the valid data to the next level cache. + */ + __enable_mmu(); + + /* After MMU is enabled and data has been invalidated, enable caches and BTAC */ + __enable_caches(); + __enable_btac(); + + /* If present, you may also need to Invalidate and Enable L2 cache here */ + l2_id = PL310_GetID(); + if (l2_id) + { + PL310_InvAllByWay(); + PL310_Enable(); + } +} +#else + +#endif + + +IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1]; + +uint32_t IRQCount = sizeof IRQTable / 4; + +uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler) +{ + if (irq < IRQCount) { + IRQTable[irq] = handler; + return 0; + } + else { + return 1; + } +} + +uint32_t InterruptHandlerUnregister (IRQn_Type irq) +{ + if (irq < IRQCount) { + IRQTable[irq] = 0; + return 0; + } + else { + return 1; + } +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + IRQNestLevel = 0; +/* do not use global variables because this function is called before + reaching pre-main. RW section maybe overwritten afterwards. */ + RZ_A1_InitClock(); + RZ_A1_InitBus(); + + //Configure GIC ICDICFR GIC_SetICDICFR() + GIC_Enable(); + __enable_irq(); + +} + + +//Fault Status Register (IFSR/DFSR) definitions +#define FSR_ALIGNMENT_FAULT 0x01 //DFSR only. Fault on first lookup +#define FSR_INSTRUCTION_CACHE_MAINTENANCE 0x04 //DFSR only - async/external +#define FSR_SYNC_EXT_TTB_WALK_FIRST 0x0c //sync/external +#define FSR_SYNC_EXT_TTB_WALK_SECOND 0x0e //sync/external +#define FSR_SYNC_PARITY_TTB_WALK_FIRST 0x1c //sync/external +#define FSR_SYNC_PARITY_TTB_WALK_SECOND 0x1e //sync/external +#define FSR_TRANSLATION_FAULT_FIRST 0x05 //MMU Fault - internal +#define FSR_TRANSLATION_FAULT_SECOND 0x07 //MMU Fault - internal +#define FSR_ACCESS_FLAG_FAULT_FIRST 0x03 //MMU Fault - internal +#define FSR_ACCESS_FLAG_FAULT_SECOND 0x06 //MMU Fault - internal +#define FSR_DOMAIN_FAULT_FIRST 0x09 //MMU Fault - internal +#define FSR_DOMAIN_FAULT_SECOND 0x0b //MMU Fault - internal +#define FSR_PERMISION_FAULT_FIRST 0x0f //MMU Fault - internal +#define FSR_PERMISION_FAULT_SECOND 0x0d //MMU Fault - internal +#define FSR_DEBUG_EVENT 0x02 //internal +#define FSR_SYNC_EXT_ABORT 0x08 //sync/external +#define FSR_TLB_CONFLICT_ABORT 0x10 //sync/external +#define FSR_LOCKDOWN 0x14 //internal +#define FSR_COPROCESSOR_ABORT 0x1a //internal +#define FSR_SYNC_PARITY_ERROR 0x19 //sync/external +#define FSR_ASYNC_EXTERNAL_ABORT 0x16 //DFSR only - async/external +#define FSR_ASYNC_PARITY_ERROR 0x18 //DFSR only - async/external + +void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) { + uint32_t FS = (DFSR & (1 << 10)) >> 6 | (DFSR & 0x0f); //Store Fault Status + + switch(FS) { + //Synchronous parity errors - retry + case FSR_SYNC_PARITY_ERROR: + case FSR_SYNC_PARITY_TTB_WALK_FIRST: + case FSR_SYNC_PARITY_TTB_WALK_SECOND: + return; + + //Your code here. Value in DFAR is invalid for some fault statuses. + case FSR_ALIGNMENT_FAULT: + case FSR_INSTRUCTION_CACHE_MAINTENANCE: + case FSR_SYNC_EXT_TTB_WALK_FIRST: + case FSR_SYNC_EXT_TTB_WALK_SECOND: + case FSR_TRANSLATION_FAULT_FIRST: + case FSR_TRANSLATION_FAULT_SECOND: + case FSR_ACCESS_FLAG_FAULT_FIRST: + case FSR_ACCESS_FLAG_FAULT_SECOND: + case FSR_DOMAIN_FAULT_FIRST: + case FSR_DOMAIN_FAULT_SECOND: + case FSR_PERMISION_FAULT_FIRST: + case FSR_PERMISION_FAULT_SECOND: + case FSR_DEBUG_EVENT: + case FSR_SYNC_EXT_ABORT: + case FSR_TLB_CONFLICT_ABORT: + case FSR_LOCKDOWN: + case FSR_COPROCESSOR_ABORT: + case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid + case FSR_ASYNC_PARITY_ERROR: //DFAR invalid + default: + while(1); + } +} + +void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) { + uint32_t FS = (IFSR & (1 << 10)) >> 6 | (IFSR & 0x0f); //Store Fault Status + + switch(FS) { + //Synchronous parity errors - retry + case FSR_SYNC_PARITY_ERROR: + case FSR_SYNC_PARITY_TTB_WALK_FIRST: + case FSR_SYNC_PARITY_TTB_WALK_SECOND: + return; + + //Your code here. Value in IFAR is invalid for some fault statuses. + case FSR_SYNC_EXT_TTB_WALK_FIRST: + case FSR_SYNC_EXT_TTB_WALK_SECOND: + case FSR_TRANSLATION_FAULT_FIRST: + case FSR_TRANSLATION_FAULT_SECOND: + case FSR_ACCESS_FLAG_FAULT_FIRST: + case FSR_ACCESS_FLAG_FAULT_SECOND: + case FSR_DOMAIN_FAULT_FIRST: + case FSR_DOMAIN_FAULT_SECOND: + case FSR_PERMISION_FAULT_FIRST: + case FSR_PERMISION_FAULT_SECOND: + case FSR_DEBUG_EVENT: //IFAR invalid + case FSR_SYNC_EXT_ABORT: + case FSR_TLB_CONFLICT_ABORT: + case FSR_LOCKDOWN: + case FSR_COPROCESSOR_ABORT: + default: + while(1); + } +} + +//returns amount to decrement lr by +//this will be 0 when we have emulated the instruction and want to execute the next instruction +//this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2) +//this will be 4 when we have performed some maintenance and want to retry the instruction in ARM (state == 4) +uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) { + const unsigned int THUMB = 2; + const unsigned int ARM = 4; + //Lazy VFP/NEON initialisation and switching + + // (ARM ARM section A7.5) VFP data processing instruction? + // (ARM ARM section A7.6) VFP/NEON register load/store instruction? + // (ARM ARM section A7.8) VFP/NEON register data transfer instruction? + // (ARM ARM section A7.9) VFP/NEON 64-bit register data transfer instruction? + if ((state == ARM && ((opcode & 0x0C000000) >> 26 == 0x03)) || + (state == THUMB && ((opcode & 0xEC000000) >> 26 == 0x3B))) { + if (((opcode & 0x00000E00) >> 9) == 5) { + FPUEnable(); + return state; + } + } + + // (ARM ARM section A7.4) NEON data processing instruction? + if ((state == ARM && ((opcode & 0xFE000000) >> 24 == 0xF2)) || + (state == THUMB && ((opcode & 0xEF000000) >> 24 == 0xEF)) || + // (ARM ARM section A7.7) NEON load/store instruction? + (state == ARM && ((opcode >> 24) == 0xF4)) || + (state == THUMB && ((opcode >> 24) == 0xF9))) { + FPUEnable(); + return state; + } + + //Add code here for other Undef cases + while(1); +} + +#if defined(__ARMCC_VERSION) +#pragma push +#pragma arm +//Critical section, called from undef handler, so systick is disabled +__asm void FPUEnable(void) { + ARM + + //Permit access to VFP/NEON, registers by modifying CPACR + MRC p15,0,R1,c1,c0,2 + ORR R1,R1,#0x00F00000 + MCR p15,0,R1,c1,c0,2 + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + ISB + + //Enable VFP/NEON + VMRS R1,FPEXC + ORR R1,R1,#0x40000000 + VMSR FPEXC,R1 + + //Initialise VFP/NEON registers to 0 + MOV R2,#0 + //Initialise D16 registers to 0 + VMOV D0, R2,R2 + VMOV D1, R2,R2 + VMOV D2, R2,R2 + VMOV D3, R2,R2 + VMOV D4, R2,R2 + VMOV D5, R2,R2 + VMOV D6, R2,R2 + VMOV D7, R2,R2 + VMOV D8, R2,R2 + VMOV D9, R2,R2 + VMOV D10,R2,R2 + VMOV D11,R2,R2 + VMOV D12,R2,R2 + VMOV D13,R2,R2 + VMOV D14,R2,R2 + VMOV D15,R2,R2 + //Initialise D32 registers to 0 + VMOV D16,R2,R2 + VMOV D17,R2,R2 + VMOV D18,R2,R2 + VMOV D19,R2,R2 + VMOV D20,R2,R2 + VMOV D21,R2,R2 + VMOV D22,R2,R2 + VMOV D23,R2,R2 + VMOV D24,R2,R2 + VMOV D25,R2,R2 + VMOV D26,R2,R2 + VMOV D27,R2,R2 + VMOV D28,R2,R2 + VMOV D29,R2,R2 + VMOV D30,R2,R2 + VMOV D31,R2,R2 + //Initialise FPSCR to a known state + VMRS R2,FPSCR + LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + AND R2,R2,R3 + VMSR FPSCR,R2 + + BX LR +} +#pragma pop + +#elif defined(__GNUC__) +void FPUEnable(void) { + __asm__ ( + ".ARM;" + + //Permit access to VFP/NEON, registers by modifying CPACR + "MRC p15,0,R1,c1,c0,2;" + "ORR R1,R1,#0x00F00000;" + "MCR p15,0,R1,c1,c0,2;" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + "ISB;" + + //Enable VFP/NEON + "VMRS R1,FPEXC;" + "ORR R1,R1,#0x40000000;" + "VMSR FPEXC,R1;" + + //Initialise VFP/NEON registers to 0 + "MOV R2,#0;" + //Initialise D16 registers to 0 + "VMOV D0, R2,R2;" + "VMOV D1, R2,R2;" + "VMOV D2, R2,R2;" + "VMOV D3, R2,R2;" + "VMOV D4, R2,R2;" + "VMOV D5, R2,R2;" + "VMOV D6, R2,R2;" + "VMOV D7, R2,R2;" + "VMOV D8, R2,R2;" + "VMOV D9, R2,R2;" + "VMOV D10,R2,R2;" + "VMOV D11,R2,R2;" + "VMOV D12,R2,R2;" + "VMOV D13,R2,R2;" + "VMOV D14,R2,R2;" + "VMOV D15,R2,R2;" + //Initialise D32 registers to 0 + "VMOV D16,R2,R2;" + "VMOV D17,R2,R2;" + "VMOV D18,R2,R2;" + "VMOV D19,R2,R2;" + "VMOV D20,R2,R2;" + "VMOV D21,R2,R2;" + "VMOV D22,R2,R2;" + "VMOV D23,R2,R2;" + "VMOV D24,R2,R2;" + "VMOV D25,R2,R2;" + "VMOV D26,R2,R2;" + "VMOV D27,R2,R2;" + "VMOV D28,R2,R2;" + "VMOV D29,R2,R2;" + "VMOV D30,R2,R2;" + "VMOV D31,R2,R2;" + + //Initialise FPSCR to a known state + "VMRS R2,FPSCR;" + "LDR R3,=0x00086060;" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + "AND R2,R2,R3;" + "VMSR FPSCR,R2;" + + //"BX LR;" + : + : + :"r1", "r2", "r3"); + return; +} +#else +#endif +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_VKRZA1H.h + * @brief CMSIS Device System Header File for + * ARMCA9 Device Series + * @version V1.00 + * @date 11 June 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2011 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __SYSTEM_VKRZA1H +#define __SYSTEM_VKRZA1H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void(*IRQHandler)(); +uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler); +uint32_t InterruptHandlerUnregister(IRQn_Type); + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the Systd short int16_t;emCoreClock variable. + */ +extern void SystemInit (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_VKRZA1H */
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/TOOLCHAIN_ARM_MICRO/startup_stm32f302x8.S Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,342 +0,0 @@ -;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** -;* File Name : startup_stm32f302x8.s -; STM32F302x8 Devices vector table for MDK ARM_MICRO toolchain -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Copyright (c) 2014, STMicroelectronics -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of STMicroelectronics nor the names of its contributors -; may be used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; <h> Stack Configuration -; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT __initial_sp - -Stack_Mem SPACE Stack_Size -__initial_sp EQU 0x20004000 ; Top of RAM - - -; <h> Heap Configuration -; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Heap_Size EQU 0x00000400 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 - EXPORT __heap_base - EXPORT __heap_limit - -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit EQU (__initial_sp - Stack_Size) - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_IRQHandler ; ADC1 - DCD USB_HP_CAN1_TX_IRQHandler ; USB Device High Priority or CAN1 TX - DCD USB_LP_CAN1_RX0_IRQHandler ; USB Device Low Priority or CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 - DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 - DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD 0 ; Reserved - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SPI3_IRQHandler ; SPI3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD COMP2_IRQHandler ; COMP2 - DCD COMP4_6_IRQHandler ; COMP4 and COMP6 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD I2C3_EV_IRQHandler ; I2C3 Event - DCD I2C3_ER_IRQHandler ; I2C3 Error - DCD USB_HP_IRQHandler ; USB High Priority remap - DCD USB_LP_IRQHandler ; USB Low Priority remap - DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD FPU_IRQHandler ; FPU - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMPER_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_TS_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT DMA1_Channel5_IRQHandler [WEAK] - EXPORT DMA1_Channel6_IRQHandler [WEAK] - EXPORT DMA1_Channel7_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] - EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT USBWakeUp_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT COMP2_IRQHandler [WEAK] - EXPORT COMP4_6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT USB_HP_IRQHandler [WEAK] - EXPORT USB_LP_IRQHandler [WEAK] - EXPORT USBWakeUp_RMP_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMPER_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_TS_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -DMA1_Channel5_IRQHandler -DMA1_Channel6_IRQHandler -DMA1_Channel7_IRQHandler -ADC1_IRQHandler -USB_HP_CAN1_TX_IRQHandler -USB_LP_CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM15_IRQHandler -TIM1_UP_TIM16_IRQHandler -TIM1_TRG_COM_TIM17_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -USBWakeUp_IRQHandler -SPI3_IRQHandler -TIM6_DAC_IRQHandler -COMP2_IRQHandler -COMP4_6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -USB_HP_IRQHandler -USB_LP_IRQHandler -USBWakeUp_RMP_IRQHandler -FPU_IRQHandler - - B . - - ENDP - - ALIGN - END
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/TOOLCHAIN_ARM_MICRO/stm32f302x8.sct Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,45 +0,0 @@ -; Scatter-Loading Description File -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Copyright (c) 2014, STMicroelectronics -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of STMicroelectronics nor the names of its contributors -; may be used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -; STM32F302R8: 64KB FLASH + 16KB SRAM -LR_IROM1 0x08000000 0x10000 { ; load region size_region - - ER_IROM1 0x08000000 0x10000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - ; 98 vectors (16 core + 82 peripheral) * 4 bytes = 392 bytes to reserve (0x188) - RW_IRAM1 (0x20000000+0x188) (0x4000-0x188) { ; RW data - .ANY (+RW +ZI) - } - -} -
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/TOOLCHAIN_ARM_MICRO/sys.cpp Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,56 +0,0 @@ -/* mbed Microcontroller Library - stackheap - * Setup a fixed single stack/heap memory model, - * between the top of the RW/ZI region and the stackpointer - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rt_misc.h> -#include <stdint.h> - -extern char Image$$RW_IRAM1$$ZI$$Limit[]; - -extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { - uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; - uint32_t sp_limit = __current_sp(); - - zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned - - struct __initial_stackheap r; - r.heap_base = zi_limit; - r.heap_limit = sp_limit; - return r; -} - -#ifdef __cplusplus -} -#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/TOOLCHAIN_ARM_STD/startup_stm32f302x8.S Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,315 +0,0 @@ -;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** -;* File Name : startup_stm32f302x8.s -; STM32F302x8 Devices vector table for MDK ARM_STD toolchain -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Copyright (c) 2014, STMicroelectronics -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of STMicroelectronics nor the names of its contributors -; may be used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -__initial_sp EQU 0x20004000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_IRQHandler ; ADC1 - DCD USB_HP_CAN1_TX_IRQHandler ; USB Device High Priority or CAN1 TX - DCD USB_LP_CAN1_RX0_IRQHandler ; USB Device Low Priority or CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 - DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 - DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD 0 ; Reserved - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SPI3_IRQHandler ; SPI3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD COMP2_IRQHandler ; COMP2 - DCD COMP4_6_IRQHandler ; COMP4 and COMP6 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD I2C3_EV_IRQHandler ; I2C3 Event - DCD I2C3_ER_IRQHandler ; I2C3 Error - DCD USB_HP_IRQHandler ; USB High Priority remap - DCD USB_LP_IRQHandler ; USB Low Priority remap - DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD FPU_IRQHandler ; FPU - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMPER_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_TS_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT DMA1_Channel5_IRQHandler [WEAK] - EXPORT DMA1_Channel6_IRQHandler [WEAK] - EXPORT DMA1_Channel7_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] - EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT USBWakeUp_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT COMP2_IRQHandler [WEAK] - EXPORT COMP4_6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT USB_HP_IRQHandler [WEAK] - EXPORT USB_LP_IRQHandler [WEAK] - EXPORT USBWakeUp_RMP_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMPER_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_TS_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -DMA1_Channel5_IRQHandler -DMA1_Channel6_IRQHandler -DMA1_Channel7_IRQHandler -ADC1_IRQHandler -USB_HP_CAN1_TX_IRQHandler -USB_LP_CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM15_IRQHandler -TIM1_UP_TIM16_IRQHandler -TIM1_TRG_COM_TIM17_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -USBWakeUp_IRQHandler -SPI3_IRQHandler -TIM6_DAC_IRQHandler -COMP2_IRQHandler -COMP4_6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -USB_HP_IRQHandler -USB_LP_IRQHandler -USBWakeUp_RMP_IRQHandler -FPU_IRQHandler - - B . - - ENDP - - ALIGN - END
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/TOOLCHAIN_ARM_STD/stm32f302x8.sct Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,45 +0,0 @@ -; Scatter-Loading Description File -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Copyright (c) 2014, STMicroelectronics -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of STMicroelectronics nor the names of its contributors -; may be used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -; STM32F302R8: 64KB FLASH + 16KB SRAM -LR_IROM1 0x08000000 0x10000 { ; load region size_region - - ER_IROM1 0x08000000 0x10000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - ; 98 vectors (16 core + 82 peripheral) * 4 bytes = 392 bytes to reserve (0x188) - RW_IRAM1 (0x20000000+0x188) (0x4000-0x188) { ; RW data - .ANY (+RW +ZI) - } - -} -
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/TOOLCHAIN_ARM_STD/sys.cpp Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,56 +0,0 @@ -/* mbed Microcontroller Library - stackheap - * Setup a fixed single stack/heap memory model, - * between the top of the RW/ZI region and the stackpointer - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rt_misc.h> -#include <stdint.h> - -extern char Image$$RW_IRAM1$$ZI$$Limit[]; - -extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { - uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; - uint32_t sp_limit = __current_sp(); - - zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned - - struct __initial_stackheap r; - r.heap_base = zi_limit; - r.heap_limit = sp_limit; - return r; -} - -#ifdef __cplusplus -} -#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/TOOLCHAIN_GCC_ARM/STM32F3XX.ld Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,157 +0,0 @@ -/* Linker script for STM32F3xx */ - -/* Linker script to configure memory regions. */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K - CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 8K - RAM (rwx) : ORIGIN = 0x20000188, LENGTH = 40k - 0x188 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - /* KEEP(.ioview) */ - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - _sidata = .; - - .data : AT (__etext) - { - __data_start__ = .; - _sdata = .; - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - _edata = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - _sbss = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - _ebss = .; - } > RAM - - .heap (COPY): - { - __end__ = .; - end = __end__; - *(.heap*) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - _estack = __StackTop; - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} -
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/TOOLCHAIN_GCC_ARM/startup_STM32F30x.S Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,465 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f30x.s - * @author MCD Application Team - * @version V1.0.0 - * @date 04-Spetember-2012 - * @brief STM32F4xx Devices vector table for RIDE7 toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system and the external SRAM mounted on - * STM3230C-EVAL board to be used as data memory (optional, - * to be enabled by user) - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2> - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call the application's entry point.*/ - bl _start - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_STAMP_IRQHandler - .word RTC_WKUP_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_TS_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_2_IRQHandler - .word USB_HP_CAN1_TX_IRQHandler - .word USB_LP_CAN1_RX0_IRQHandler - .word CAN1_RX1_IRQHandler - .word CAN1_SCE_IRQHandler - .word EXTI9_5_IRQHandler - .word TIM1_BRK_TIM15_IRQHandler - .word TIM1_UP_TIM16_IRQHandler - .word TIM1_TRG_COM_TIM17_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTC_Alarm_IRQHandler - .word USBWakeUp_IRQHandler - .word TIM8_BRK_IRQHandler - .word TIM8_UP_IRQHandler - .word TIM8_TRG_COM_IRQHandler - .word TIM8_CC_IRQHandler - .word ADC3_IRQHandler - .word 0 - .word 0 - .word 0 - .word SPI3_IRQHandler - .word UART4_IRQHandler - .word UART5_IRQHandler - .word TIM6_DAC_IRQHandler - .word TIM7_IRQHandler - .word DMA2_Channel1_IRQHandler - .word DMA2_Channel2_IRQHandler - .word DMA2_Channel3_IRQHandler - .word DMA2_Channel4_IRQHandler - .word DMA2_Channel5_IRQHandler - .word ADC4_IRQHandler - .word 0 - .word 0 - .word COMP1_2_3_IRQHandler - .word COMP4_5_6_IRQHandler - .word COMP7_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word USB_HP_IRQHandler - .word USB_LP_IRQHandler - .word USBWakeUp_RMP_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word FPU_IRQHandler - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMPER_STAMP_IRQHandler - .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_TS_IRQHandler - .thumb_set EXTI2_TS_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_2_IRQHandler - .thumb_set ADC1_2_IRQHandler,Default_Handler - - .weak USB_HP_CAN1_TX_IRQHandler - .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler - - .weak USB_LP_CAN1_RX0_IRQHandler - .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM15_IRQHandler - .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM16_IRQHandler - .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM17_IRQHandler - .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak USBWakeUp_IRQHandler - .thumb_set USBWakeUp_IRQHandler,Default_Handler - - .weak TIM8_BRK_IRQHandler - .thumb_set TIM8_BRK_IRQHandler,Default_Handler - - .weak TIM8_UP_IRQHandler - .thumb_set TIM8_UP_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_IRQHandler - .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak ADC3_IRQHandler - .thumb_set ADC3_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Channel1_IRQHandler - .thumb_set DMA2_Channel1_IRQHandler,Default_Handler - - .weak DMA2_Channel2_IRQHandler - .thumb_set DMA2_Channel2_IRQHandler,Default_Handler - - .weak DMA2_Channel3_IRQHandler - .thumb_set DMA2_Channel3_IRQHandler,Default_Handler - - .weak DMA2_Channel4_IRQHandler - .thumb_set DMA2_Channel4_IRQHandler,Default_Handler - - .weak DMA2_Channel5_IRQHandler - .thumb_set DMA2_Channel5_IRQHandler,Default_Handler - - .weak ADC4_IRQHandler - .thumb_set ADC4_IRQHandler,Default_Handler - - .weak COMP1_2_3_IRQHandler - .thumb_set COMP1_2_3_IRQHandler,Default_Handler - - .weak COMP4_5_6_IRQHandler - .thumb_set COMP4_5_6_IRQHandler,Default_Handler - - .weak COMP7_IRQHandler - .thumb_set COMP7_IRQHandler,Default_Handler - - .weak USB_HP_IRQHandler - .thumb_set USB_HP_IRQHandler,Default_Handler - - .weak USB_LP_IRQHandler - .thumb_set USB_LP_IRQHandler,Default_Handler - - .weak USBWakeUp_RMP_IRQHandler - .thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/cmsis.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,38 +0,0 @@ -/* mbed Microcontroller Library - * A generic CMSIS include header - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "stm32f30x.h" -#include "cmsis_nvic.h" - -#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/cmsis_nvic.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,55 +0,0 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "cmsis_nvic.h" - -#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM -#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { - uint32_t *vectors = (uint32_t *)SCB->VTOR; - uint32_t i; - - // Copy and switch to dynamic vectors if the first time called - if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { - uint32_t *old_vectors = vectors; - vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; - for (i=0; i<NVIC_NUM_VECTORS; i++) { - vectors[i] = old_vectors[i]; - } - SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; - } - vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - -uint32_t NVIC_GetVector(IRQn_Type IRQn) { - uint32_t *vectors = (uint32_t*)SCB->VTOR; - return vectors[IRQn + NVIC_USER_IRQ_OFFSET]; -}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/cmsis_nvic.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,55 +0,0 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -// STM32F302R8 -// CORE: 16 vectors (= 64 bytes from 0x00 to 0x3F) -// MCU Peripherals: 82 vectors (= 328 bytes from 0x40 to ...) -// Total: 392 bytes to be reserved in RAM (see scatter file) -#define NVIC_NUM_VECTORS (16 + 82) -#define NVIC_USER_IRQ_OFFSET 16 - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); -uint32_t NVIC_GetVector(IRQn_Type IRQn); - -#ifdef __cplusplus -} -#endif - -#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,7705 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x.h - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File. - * This file contains all the peripheral registers definitions, bits - * definitions and memory mapping for STM32F30x devices. - * - * The file is the unique include file that the application programmer - * is using in the C source code, usually in main.c. This file contains: - * - Configuration section that allows to select: - * - The device used in the target application - * - To use or not the peripherals drivers in application code(i.e. - * code will be based on direct access to peripherals registers - * rather than drivers API), this option is controlled by - * "#define USE_STDPERIPH_DRIVER" - * - To change few application-specific parameters such as the HSE - * crystal frequency - * - Data structures and the address mapping for all peripherals - * - Peripheral registers declarations and bits definition - * - Macros to access peripheral registers hardware - * - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f30x - * @{ - */ - -#ifndef __STM32F30x_H -#define __STM32F30x_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/* Uncomment the line below according to the target STM32 device used in your - application - */ - -#if !defined (STM32F303xC) && !defined (STM32F334x8) && !defined (STM32F303x8) && !defined (STM32F301x8) && !defined (STM32F302x8) -#define STM32F303xC /*!< STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC, STM32F303VB and STM32F303VC Devices */ - /* #define STM32F334x8 */ /*!< STM32F334C4, STM32F334C6, STM32F334C8, STM32F334R4, STM32F334R6 and STM32F334R8 Devices */ - /* #define STM32F302x8 */ /*!< STM32F302K4, STM32F302K6, STM32F302K8, STM32F302C4, STM32F302C6, STM32F302C8, - STM32F302R4, STM32F302R6 and STM32F302R8 Devices */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ - -/* Old STM32F30X definition, maintained for legacy purpose */ -#if defined(STM32F30X) - #define STM32F303xC -#endif /* STM32F30X */ - -#if !defined (STM32F303xC) && !defined (STM32F334x8) && !defined (STM32F302x8) - #error "Please select first the target STM32F30X device used in your application (in stm32f30x.h file)" -#endif - -#if !defined (USE_STDPERIPH_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ -#define USE_STDPERIPH_DRIVER -#endif /* USE_STDPERIPH_DRIVER */ - -/** - * @brief In the following line adjust the value of External High Speed oscillator (HSE) - used in your application - - Tip: To avoid modifying this file each time you need to use different HSE, you - can define the HSE value in your toolchain compiler preprocessor. - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External xtal in Hz */ -#endif /* HSE_VALUE */ - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - Timeout value - */ -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSE start up */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup - Timeout value - */ -#if !defined (HSI_STARTUP_TIMEOUT) - #define HSI_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSI start up */ -#endif /* HSI_STARTUP_TIMEOUT */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)8000000) -#endif /* HSI_VALUE */ /*!< Value of the Internal High Speed oscillator in Hz. - The real value may vary depending on the variations - in voltage and temperature. */ -#if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)40000) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -#if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - - -/** - * @brief STM32F30x Standard Peripherals Library version number V1.1.0 - */ -#define __STM32F30X_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F30X_STDPERIPH_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ -#define __STM32F30X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32F30X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F30X_STDPERIPH_VERSION ( (__STM32F30X_STDPERIPH_VERSION_MAIN << 24)\ - |(__STM32F30X_STDPERIPH_VERSION_SUB1 << 16)\ - |(__STM32F30X_STDPERIPH_VERSION_SUB2 << 8)\ - |(__STM32F30X_STDPERIPH_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ -#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 1 /*!< STM32F30X provide an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32F30X uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< STM32F30X provide an FPU */ - - -/** - * @brief STM32F30X Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum IRQn -{ -/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ -/****** STM32 specific Interrupt Numbers **********************************************************************/ -#ifdef STM32F303xC - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI lines 17, 19 & 20 */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_TS_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ - ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ - TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ - TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */ - TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ - TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ - TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ - DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ - ADC4_IRQn = 61, /*!< ADC4 global Interrupt */ - COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt */ - COMP4_5_6_IRQn = 65, /*!< COMP5, COMP6 and COMP4 global Interrupt */ - COMP7_IRQn = 66, /*!< COMP7 global Interrupt */ - USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */ - USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */ - USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */ - FPU_IRQn = 81 /*!< Floating point Interrupt */ -#endif /* STM32F303xC */ -#ifdef STM32F334x8 - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI lines 17, 19 & 20 */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_TS_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ - ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */ - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupts */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ - TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ - TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error interrupts */ - TIM7_DAC2_IRQn = 55, /*!< TIM7 global and DAC2 underrun error Interrupt */ - COMP2_IRQn = 64, /*!< COMP2 global Interrupt */ - COMP4_6_IRQn = 65, /*!< COMP6 and COMP4 global Interrupt */ - HRTIM1_Master_IRQn = 67, /*!< HRTIM Master Timer global Interrupts */ - HRTIM1_TIMA_IRQn = 68, /*!< HRTIM Timer A global Interrupt */ - HRTIM1_TIMB_IRQn = 69, /*!< HRTIM Timer B global Interrupt */ - HRTIM1_TIMC_IRQn = 70, /*!< HRTIM Timer C global Interrupt */ - HRTIM1_TIMD_IRQn = 71, /*!< HRTIM Timer D global Interrupt */ - HRTIM1_TIME_IRQn = 72, /*!< HRTIM Timer E global Interrupt */ - HRTIM1_FLT_IRQn = 73, /*!< HRTIM Fault global Interrupt */ - FPU_IRQn = 81 /*!< Floating point Interrupt */ -#endif /* STM32F334x8 */ -#ifdef STM32F302x8 - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI lines 20 */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_TS_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ - ADC1_IRQn = 18, /*!< ADC1 Interrupts */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ - TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ - TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - COMP2_IRQn = 64, /*!< COMP2 global Interrupt */ - COMP4_6_IRQn = 65, /*!< COMP5, COMP6 and COMP4 global Interrupt */ - COMP7_IRQn = 66, /*!< COMP7 global Interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 Event Interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */ - USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */ - USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */ - USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */ - FPU_IRQn = 81 /*!< Floating point Interrupt */ -#endif /* STM32F302x8 */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ -#include "system_stm32f30x.h" /* STM32F30x System Header */ -#include <stdint.h> - -/** @addtogroup Exported_types - * @{ - */ -/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef const int32_t sc32; /*!< Read Only */ -typedef const int16_t sc16; /*!< Read Only */ -typedef const int8_t sc8; /*!< Read Only */ - -typedef __IO int32_t vs32; -typedef __IO int16_t vs16; -typedef __IO int8_t vs8; - -typedef __I int32_t vsc32; /*!< Read Only */ -typedef __I int16_t vsc16; /*!< Read Only */ -typedef __I int8_t vsc8; /*!< Read Only */ - -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef const uint32_t uc32; /*!< Read Only */ -typedef const uint16_t uc16; /*!< Read Only */ -typedef const uint8_t uc8; /*!< Read Only */ - -typedef __IO uint32_t vu32; -typedef __IO uint16_t vu16; -typedef __IO uint8_t vu8; - -typedef __I uint32_t vuc32; /*!< Read Only */ -typedef __I uint16_t vuc16; /*!< Read Only */ -typedef __I uint8_t vuc8; /*!< Read Only */ - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -/** - * @} - */ - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ - __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ - __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ - uint32_t RESERVED0; /*!< Reserved, 0x010 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ - uint32_t RESERVED1; /*!< Reserved, 0x01C */ - __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */ - __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */ - __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */ - uint32_t RESERVED2; /*!< Reserved, 0x02C */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ - __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ - uint32_t RESERVED3; /*!< Reserved, 0x044 */ - uint32_t RESERVED4; /*!< Reserved, 0x048 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ - uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ - __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ - __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ - __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ - __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ - uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ - uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ - __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ - __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ - uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ - uint32_t RESERVED9; /*!< Reserved, 0x0AC */ - __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */ - __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */ - -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ - uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual - modes, Address offset: ADC1/3 base address + 0x30A */ -} ADC_Common_TypeDef; - - -/** - * @brief Controller Area Network TxMailBox - */ -typedef struct -{ - __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ - __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ - __IO uint32_t TDLR; /*!< CAN mailbox data low register */ - __IO uint32_t TDHR; /*!< CAN mailbox data high register */ -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ -typedef struct -{ - __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ - __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ - __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ - __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ -typedef struct -{ - __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ - __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ -typedef struct -{ - __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ - __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ - __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ - __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ - __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ - __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ - __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ - __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ - uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ - CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ - uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ - __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ - __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ - uint32_t RESERVED2; /*!< Reserved, 0x208 */ - __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ - uint32_t RESERVED3; /*!< Reserved, 0x210 */ - __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ - uint32_t RESERVED4; /*!< Reserved, 0x218 */ - __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ - CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ -} CAN_TypeDef; - - -/** - * @brief Analog Comparators - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */ -} COMP_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, 0x05 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ - uint32_t RESERVED2; /*!< Reserved, 0x0C */ - __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ - __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */ -} DMA_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ - __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */ - __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */ - __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */ - __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */ - __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */ -}EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ - __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ - __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ - __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */ - uint32_t RESERVED; /*!< Reserved, 0x18 */ - __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */ - __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */ - -} FLASH_TypeDef; - -/** - * @brief Option Bytes Registers - */ -typedef struct -{ - __IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */ - __IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */ - uint16_t RESERVED0; /*!< Reserved, 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */ - __IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */ - __IO uint16_t WRP2; /*!<FLASH option byte write protection 2, Address offset: 0x10 */ - __IO uint16_t WRP3; /*!<FLASH option byte write protection 3, Address offset: 0x12 */ -} OB_TypeDef; - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint16_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - uint16_t RESERVED0; /*!< Reserved, 0x06 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint16_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - uint16_t RESERVED1; /*!< Reserved, 0x12 */ - __IO uint16_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - uint16_t RESERVED2; /*!< Reserved, 0x16 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */ - __IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ - uint16_t RESERVED3; /*!< Reserved, 0x2A */ -}GPIO_TypeDef; - -/** - * @brief High resolution Timer (HRTIM) - */ -/* HRTIM master definition */ -typedef struct -{ - __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */ - __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */ - __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */ - __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */ - __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */ - __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */ - __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */ - __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */ - uint32_t RESERVED0; /*!< Reserved, 0x20 */ - __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */ - __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */ - __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */ -}HRTIM_Master_TypeDef; - -/* HRTIM slave definition */ -typedef struct -{ - __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */ - __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */ - __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */ - __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */ - __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */ - __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */ - __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */ - __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */ - __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */ - __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */ - __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */ - __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */ - __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */ - __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */ - __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */ - __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */ - __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */ - __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */ - __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */ - __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */ - __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */ - __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */ - __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */ - __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */ - __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */ - __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */ - __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */ - uint32_t RESERVED0[5];/*!< Reserved, */ -}HRTIM_Timerx_TypeDef; - -/* HRTIM common register definition */ -typedef struct -{ - __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */ - __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */ - __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */ - __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */ - __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */ - __IO uint32_t DISR; /*!< HRTIM Output disable register, Address offset: 0x18 */ - __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */ - __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */ - __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */ - __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */ - __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */ - __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */ - __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */ - __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */ - __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */ - __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */ - __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */ - __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */ - __IO uint32_t DLLCR; /*!< HRTIM DLL control register, Address offset: 0x4C */ - __IO uint32_t FLTINxR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */ - __IO uint32_t FLTINxR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */ - __IO uint32_t BDMUPDR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */ - __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */ - __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */ - __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */ - __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */ - __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */ - __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */ -}HRTIM_Common_TypeDef; - -/* HRTIM register definition */ -typedef struct { - HRTIM_Master_TypeDef HRTIM_MASTER; - uint32_t RESERVED0[20]; - HRTIM_Timerx_TypeDef HRTIM_TIMERx[5]; - uint32_t RESERVED1[32]; - HRTIM_Common_TypeDef HRTIM_COMMON; -}HRTIM_TypeDef; - -/** - * @brief Operational Amplifier (OPAMP) - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */ -} OPAMP_TypeDef; - - -/** - * @brief System configuration controller - */ - -typedef struct -{ - __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ - __IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */ - __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */ - __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ - __IO uint32_t RESERVED0; /*!< Reserved, 0x1C */ - __IO uint32_t RESERVED1; /*!< Reserved, 0x20 */ - __IO uint32_t RESERVED2; /*!< Reserved, 0x24 */ - __IO uint32_t RESERVED4; /*!< Reserved, 0x28 */ - __IO uint32_t RESERVED5; /*!< Reserved, 0x2C */ - __IO uint32_t RESERVED6; /*!< Reserved, 0x30 */ - __IO uint32_t RESERVED7; /*!< Reserved, 0x34 */ - __IO uint32_t RESERVED8; /*!< Reserved, 0x38 */ - __IO uint32_t RESERVED9; /*!< Reserved, 0x3C */ - __IO uint32_t RESERVED10; /*!< Reserved, 0x40 */ - __IO uint32_t RESERVED11; /*!< Reserved, 0x44 */ - __IO uint32_t RESERVED12; /*!< Reserved, 0x48 */ - __IO uint32_t RESERVED13; /*!< Reserved, 0x4C */ - __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x50 */ -} SYSCFG_TypeDef; - -/** - * @brief Inter-integrated Circuit Interface - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ - __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ - __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ - __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ - __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ - __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ - __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ - __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ - __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ - __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ -}I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ - __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ - __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ -} IWDG_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ - __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ -typedef struct -{ - __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ - __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */ - __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */ - __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */ - __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */ - __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */ - __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */ - __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */ - __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */ - __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */ - __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */ - __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */ - __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */ -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - uint32_t RESERVED0; /*!< Reserved, 0x18 */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ - uint32_t RESERVED7; /*!< Reserved, 0x4C */ - __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ - __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ - __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ - __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ - __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ - __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ - __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ - __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ - __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ - __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ - __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ - __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ - __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ - __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ - __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ - __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ -} RTC_TypeDef; - - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ -} SPI_TypeDef; - -/** - * @brief TIM - */ -typedef struct -{ - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ - __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ - __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ - __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ - __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ - __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */ -} TIM_TypeDef; - - -/** - * @brief Touch Sensing Controller (TSC) - */ -typedef struct -{ - __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ - __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ - __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ - __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ - __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ - __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ - uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ - __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ - uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ - __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ - __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ -} TSC_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ - __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ - __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - uint16_t RESERVED1; /*!< Reserved, 0x0E */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ - __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ - __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ - __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ -} USART_TypeDef; - -/** - * @brief Window WATCHDOG - */ -typedef struct -{ - __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ - __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ -} WWDG_TypeDef; - - -/** @addtogroup Peripheral_memory_map - * @{ - */ - -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ - -#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ - - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000) -#define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000) - -/*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800) -#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400) -#define RTC_BASE (APB1PERIPH_BASE + 0x00002800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000) -#define I2S2ext_BASE (APB1PERIPH_BASE + 0x00003400) -#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00) -#define I2S3ext_BASE (APB1PERIPH_BASE + 0x00004000) -#define USART2_BASE (APB1PERIPH_BASE + 0x00004400) -#define USART3_BASE (APB1PERIPH_BASE + 0x00004800) -#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x00005000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800) -#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400) -#define PWR_BASE (APB1PERIPH_BASE + 0x00007000) -#define DAC1_BASE (APB1PERIPH_BASE + 0x00007400) -#define I2C3_BASE (APB1PERIPH_BASE + 0x00007800) -#define DAC2_BASE (APB1PERIPH_BASE + 0x00009800) -#define DAC_BASE DAC1_BASE - -/*!< APB2 peripherals */ -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000) -#define COMP_BASE (APB2PERIPH_BASE + 0x0000001C) -#define COMP1_BASE (APB2PERIPH_BASE + 0x0000001C) -#define COMP2_BASE (APB2PERIPH_BASE + 0x00000020) -#define COMP3_BASE (APB2PERIPH_BASE + 0x00000024) -#define COMP4_BASE (APB2PERIPH_BASE + 0x00000028) -#define COMP5_BASE (APB2PERIPH_BASE + 0x0000002C) -#define COMP6_BASE (APB2PERIPH_BASE + 0x00000030) -#define COMP7_BASE (APB2PERIPH_BASE + 0x00000034) -#define OPAMP_BASE (APB2PERIPH_BASE + 0x00000038) -#define OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038) -#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003C) -#define OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040) -#define OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044) -#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400) -#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000) -#define TIM8_BASE (APB2PERIPH_BASE + 0x00003400) -#define USART1_BASE (APB2PERIPH_BASE + 0x00003800) -#define TIM15_BASE (APB2PERIPH_BASE + 0x00004000) -#define TIM16_BASE (APB2PERIPH_BASE + 0x00004400) -#define TIM17_BASE (APB2PERIPH_BASE + 0x00004800) -#define HRTIM1_BASE (APB2PERIPH_BASE + 0x00007400) -#define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080) -#define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100) -#define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180) -#define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200) -#define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280) -#define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380) - -/*!< AHB1 peripherals */ -#define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000) -#define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008) -#define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001C) -#define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030) -#define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044) -#define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058) -#define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006C) -#define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400) -#define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408) -#define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041C) -#define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430) -#define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444) -#define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458) -#define RCC_BASE (AHB1PERIPH_BASE + 0x00001000) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000) /*!< Flash registers base address */ -#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ -#define CRC_BASE (AHB1PERIPH_BASE + 0x00003000) -#define TSC_BASE (AHB1PERIPH_BASE + 0x00004000) - -/*!< AHB2 peripherals */ -#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000) -#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400) -#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800) -#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00) -#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000) -#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400) - -/*!< AHB3 peripherals */ -#define ADC1_BASE (AHB3PERIPH_BASE + 0x0000) -#define ADC2_BASE (AHB3PERIPH_BASE + 0x0100) -#define ADC1_2_BASE (AHB3PERIPH_BASE + 0x0300) -#define ADC3_BASE (AHB3PERIPH_BASE + 0x0400) -#define ADC4_BASE (AHB3PERIPH_BASE + 0x0500) -#define ADC3_4_BASE (AHB3PERIPH_BASE + 0x0700) - -#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define I2C3 ((I2C_TypeDef *) I2C3_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC1 ((DAC_TypeDef *) DAC1_BASE) -#define DAC2 ((DAC_TypeDef *) DAC2_BASE) -#define DAC DAC1 -#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) -#define COMP ((COMP_TypeDef *) COMP_BASE) -#define COMP1 ((COMP_TypeDef *) COMP1_BASE) -#define COMP2 ((COMP_TypeDef *) COMP2_BASE) -#define COMP3 ((COMP_TypeDef *) COMP3_BASE) -#define COMP4 ((COMP_TypeDef *) COMP4_BASE) -#define COMP5 ((COMP_TypeDef *) COMP5_BASE) -#define COMP6 ((COMP_TypeDef *) COMP6_BASE) -#define COMP7 ((COMP_TypeDef *) COMP7_BASE) -#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) -#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) -#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) -#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE) -#define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define TIM15 ((TIM_TypeDef *) TIM15_BASE) -#define TIM16 ((TIM_TypeDef *) TIM16_BASE) -#define TIM17 ((TIM_TypeDef *) TIM17_BASE) -#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE) -#define HRTIM1_TIMA ((HRTIM_TIM_TypeDef *) HRTIM1_TIMA_BASE) -#define HRTIM1_TIMB ((HRTIM_TIM_TypeDef *) HRTIM1_TIMB_BASE) -#define HRTIM1_TIMC ((HRTIM_TIM_TypeDef *) HRTIM1_TIMC_BASE) -#define HRTIM1_TIMD ((HRTIM_TIM_TypeDef *) HRTIM1_TIMD_BASE) -#define HRTIM1_TIME ((HRTIM_TIM_TypeDef *) HRTIM1_TIME_BASE) -#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE) -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) -#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) -#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) -#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) -#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define OB ((OB_TypeDef *) OB_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define TSC ((TSC_TypeDef *) TSC_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define ADC4 ((ADC_TypeDef *) ADC4_BASE) -#define ADC1_2 ((ADC_Common_TypeDef *) ADC1_2_BASE) -#define ADC3_4 ((ADC_Common_TypeDef *) ADC3_4_BASE) -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ -/******************************************************************************/ -/* */ -/* High Resolution Timer (HRTIM) */ -/* */ -/******************************************************************************/ -/******************** Master Timer control register ***************************/ -#define HRTIM_MCR_CK_PSC ((uint32_t)0x00000007) /*!< Prescaler mask */ -#define HRTIM_MCR_CK_PSC_0 ((uint32_t)0x00000001) /*!< Prescaler bit 0 */ -#define HRTIM_MCR_CK_PSC_1 ((uint32_t)0x00000002) /*!< Prescaler bit 1 */ -#define HRTIM_MCR_CK_PSC_2 ((uint32_t)0x00000004) /*!< Prescaler bit 2 */ - -#define HRTIM_MCR_CONT ((uint32_t)0x00000008) /*!< Continuous mode */ -#define HRTIM_MCR_RETRIG ((uint32_t)0x00000010) /*!< Rettrigreable mode */ -#define HRTIM_MCR_HALF ((uint32_t)0x00000020) /*!< Half mode */ - -#define HRTIM_MCR_SYNC_IN ((uint32_t)0x00000300) /*!< Synchronization input master */ -#define HRTIM_MCR_SYNC_IN_0 ((uint32_t)0x00000100) /*!< Synchronization input bit 0 */ -#define HRTIM_MCR_SYNC_IN_1 ((uint32_t)0x00000200) /*!< Synchronization input bit 1 */ -#define HRTIM_MCR_SYNCRSTM ((uint32_t)0x00000400) /*!< Synchronization reset master */ -#define HRTIM_MCR_SYNCSTRTM ((uint32_t)0x00000800) /*!< Synchronization start master */ -#define HRTIM_MCR_SYNC_OUT ((uint32_t)0x00003000) /*!< Synchronization output master */ -#define HRTIM_MCR_SYNC_OUT_0 ((uint32_t)0x00001000) /*!< Synchronization output bit 0 */ -#define HRTIM_MCR_SYNC_OUT_1 ((uint32_t)0x00002000) /*!< Synchronization output bit 1 */ -#define HRTIM_MCR_SYNC_SRC ((uint32_t)0x0000C000) /*!< Synchronization source */ -#define HRTIM_MCR_SYNC_SRC_0 ((uint32_t)0x00004000) /*!< Synchronization source bit 0 */ -#define HRTIM_MCR_SYNC_SRC_1 ((uint32_t)0x00008000) /*!< Synchronization source bit 1 */ - -#define HRTIM_MCR_MCEN ((uint32_t)0x00010000) /*!< Master counter enable */ -#define HRTIM_MCR_TACEN ((uint32_t)0x00020000) /*!< Timer A counter enable */ -#define HRTIM_MCR_TBCEN ((uint32_t)0x00040000) /*!< Timer B counter enable */ -#define HRTIM_MCR_TCCEN ((uint32_t)0x00080000) /*!< Timer C counter enable */ -#define HRTIM_MCR_TDCEN ((uint32_t)0x00100000) /*!< Timer D counter enable */ -#define HRTIM_MCR_TECEN ((uint32_t)0x00200000) /*!< Timer E counter enable */ - -#define HRTIM_MCR_DACSYNC ((uint32_t)0x06000000) /*!< DAC synchronization mask */ -#define HRTIM_MCR_DACSYNC_0 ((uint32_t)0x02000000) /*!< DAC synchronization bit 0 */ -#define HRTIM_MCR_DACSYNC_1 ((uint32_t)0x04000000) /*!< DAC synchronization bit 1 */ - -#define HRTIM_MCR_PREEN ((uint32_t)0x08000000) /*!< Master preload enable */ -#define HRTIM_MCR_MREPU ((uint32_t)0x20000000) /*!< Master repetition update */ - -#define HRTIM_MCR_BRSTDMA ((uint32_t)0xC0000000) /*!< Burst DMA update */ -#define HRTIM_MCR_BRSTDMA_0 ((uint32_t)0x40000000) /*!< Burst DMA update bit 0*/ -#define HRTIM_MCR_BRSTDMA_1 ((uint32_t)0x80000000) /*!< Burst DMA update bit 1 */ - -/******************** Master Timer Interrupt status register ******************/ -#define HRTIM_MISR_MCMP1 ((uint32_t)0x00000001) /*!< Master compare 1 interrupt flag */ -#define HRTIM_MISR_MCMP2 ((uint32_t)0x00000002) /*!< Master compare 2 interrupt flag */ -#define HRTIM_MISR_MCMP3 ((uint32_t)0x00000004) /*!< Master compare 3 interrupt flag */ -#define HRTIM_MISR_MCMP4 ((uint32_t)0x00000008) /*!< Master compare 4 interrupt flag */ -#define HRTIM_MISR_MREP ((uint32_t)0x00000010) /*!< Master Repetition interrupt flag */ -#define HRTIM_MISR_SYNC ((uint32_t)0x00000020) /*!< Synchronization input interrupt flag */ -#define HRTIM_MISR_MUPD ((uint32_t)0x00000040) /*!< Master update interrupt flag */ - -/******************** Master Timer Interrupt clear register *******************/ -#define HRTIM_MICR_MCMP1 ((uint32_t)0x00000001) /*!< Master compare 1 interrupt flag clear */ -#define HRTIM_MICR_MCMP2 ((uint32_t)0x00000002) /*!< Master compare 2 interrupt flag clear */ -#define HRTIM_MICR_MCMP3 ((uint32_t)0x00000004) /*!< Master compare 3 interrupt flag clear */ -#define HRTIM_MICR_MCMP4 ((uint32_t)0x00000008) /*!< Master compare 4 interrupt flag clear */ -#define HRTIM_MICR_MREP ((uint32_t)0x00000010) /*!< Master Repetition interrupt flag clear */ -#define HRTIM_MICR_SYNC ((uint32_t)0x00000020) /*!< Synchronization input interrupt flag clear */ -#define HRTIM_MICR_MUPD ((uint32_t)0x00000040) /*!< Master update interrupt flag clear */ - -/******************** Master Timer DMA/Interrupt enable register **************/ -#define HRTIM_MDIER_MCMP1IE ((uint32_t)0x00000001) /*!< Master compare 1 interrupt enable */ -#define HRTIM_MDIER_MCMP2IE ((uint32_t)0x00000002) /*!< Master compare 2 interrupt enable */ -#define HRTIM_MDIER_MCMP3IE ((uint32_t)0x00000004) /*!< Master compare 3 interrupt enable */ -#define HRTIM_MDIER_MCMP4IE ((uint32_t)0x00000008) /*!< Master compare 4 interrupt enable */ -#define HRTIM_MDIER_MREPIE ((uint32_t)0x00000010) /*!< Master Repetition interrupt enable */ -#define HRTIM_MDIER_SYNCIE ((uint32_t)0x00000020) /*!< Synchronization input interrupt enable */ -#define HRTIM_MDIER_MUPDIE ((uint32_t)0x00000040) /*!< Master update interrupt enable */ - -#define HRTIM_MDIER_MCMP1DE ((uint32_t)0x00010000) /*!< Master compare 1 DMA enable */ -#define HRTIM_MDIER_MCMP2DE ((uint32_t)0x00020000) /*!< Master compare 2 DMA enable */ -#define HRTIM_MDIER_MCMP3DE ((uint32_t)0x00040000) /*!< Master compare 3 DMA enable */ -#define HRTIM_MDIER_MCMP4DE ((uint32_t)0x00080000) /*!< Master compare 4 DMA enable */ -#define HRTIM_MDIER_MREPDE ((uint32_t)0x00100000) /*!< Master Repetition DMA enable */ -#define HRTIM_MDIER_SYNCDE ((uint32_t)0x00200000) /*!< Synchronization input DMA enable */ -#define HRTIM_MDIER_MUPDDE ((uint32_t)0x00400000) /*!< Master update DMA enable */ - -/******************* Bit definition for HRTIM_MCNTR register ****************/ -#define HRTIM_MCNTR_MCNTR ((uint32_t)0xFFFFFFFF) /*!<Counter Value */ - -/******************* Bit definition for HRTIM_MPER register *****************/ -#define HRTIM_MPER_MPER ((uint32_t)0xFFFFFFFF) /*!< Period Value */ - -/******************* Bit definition for HRTIM_MREP register *****************/ -#define HRTIM_MREP_MREP ((uint32_t)0xFFFFFFFF) /*!<Repetition Value */ - -/******************* Bit definition for HRTIM_MCMP1R register *****************/ -#define HRTIM_MCMP1R_MCMP1R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */ - -/******************* Bit definition for HRTIM_MCMP2R register *****************/ -#define HRTIM_MCMP1R_MCMP2R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */ - -/******************* Bit definition for HRTIM_MCMP3R register *****************/ -#define HRTIM_MCMP1R_MCMP3R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */ - -/******************* Bit definition for HRTIM_MCMP4R register *****************/ -#define HRTIM_MCMP1R_MCMP4R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */ - -/******************** Slave control register **********************************/ -#define HRTIM_TIMCR_CK_PSC ((uint32_t)0x00000007) /*!< Slave prescaler mask*/ -#define HRTIM_TIMCR_CK_PSC_0 ((uint32_t)0x00000001) /*!< prescaler bit 0 */ -#define HRTIM_TIMCR_CK_PSC_1 ((uint32_t)0x00000002) /*!< prescaler bit 1 */ -#define HRTIM_TIMCR_CK_PSC_2 ((uint32_t)0x00000004) /*!< prescaler bit 2 */ - -#define HRTIM_TIMCR_CONT ((uint32_t)0x00000008) /*!< Slave continuous mode */ -#define HRTIM_TIMCR_RETRIG ((uint32_t)0x00000010) /*!< Slave Retrigreable mode */ -#define HRTIM_TIMCR_HALF ((uint32_t)0x00000020) /*!< Slave Half mode */ -#define HRTIM_TIMCR_PSHPLL ((uint32_t)0x00000040) /*!< Slave push-pull mode */ - -#define HRTIM_TIMCR_SYNCRST ((uint32_t)0x00000400) /*!< Slave synchronization resets */ -#define HRTIM_TIMCR_SYNCSTRT ((uint32_t)0x00000800) /*!< Slave synchronization starts */ - -#define HRTIM_TIMCR_DELCMP2 ((uint32_t)0x00003000) /*!< Slave delayed comparator 2 mode mask */ -#define HRTIM_TIMCR_DELCMP2_0 ((uint32_t)0x00001000) /*!< Slave delayed comparator 2 bit 0 */ -#define HRTIM_TIMCR_DELCMP2_1 ((uint32_t)0x00002000) /*!< Slave delayed comparator 2 bit 1 */ -#define HRTIM_TIMCR_DELCMP4 ((uint32_t)0x0000C000) /*!< Slave delayed comparator 4 mode mask */ -#define HRTIM_TIMCR_DELCMP4_0 ((uint32_t)0x00004000) /*!< Slave delayed comparator 4 bit 0 */ -#define HRTIM_TIMCR_DELCMP4_1 ((uint32_t)0x00008000) /*!< Slave delayed comparator 4 bit 1 */ - -#define HRTIM_TIMCR_TREPU ((uint32_t)0x00020000) /*!< Slave repetition update */ -#define HRTIM_TIMCR_TRSTU ((uint32_t)0x00040000) /*!< Slave reset update */ -#define HRTIM_TIMCR_TAU ((uint32_t)0x00080000) /*!< Slave Timer A update reserved for TIM A */ -#define HRTIM_TIMCR_TBU ((uint32_t)0x00100000) /*!< Slave Timer B update reserved for TIM B */ -#define HRTIM_TIMCR_TCU ((uint32_t)0x00200000) /*!< Slave Timer C update reserved for TIM C */ -#define HRTIM_TIMCR_TDU ((uint32_t)0x00400000) /*!< Slave Timer D update reserved for TIM D */ -#define HRTIM_TIMCR_TEU ((uint32_t)0x00800000) /*!< Slave Timer E update reserved for TIM E */ -#define HRTIM_TIMCR_MSTU ((uint32_t)0x01000000) /*!< Master Update */ - -#define HRTIM_TIMCR_DACSYNC ((uint32_t)0x06000000) /*!< DAC synchronization mask */ -#define HRTIM_TIMCR_DACSYNC_0 ((uint32_t)0x02000000) /*!< DAC synchronization bit 0 */ -#define HRTIM_TIMCR_DACSYNC_1 ((uint32_t)0x04000000) /*!< DAC synchronization bit 1 */ -#define HRTIM_TIMCR_PREEN ((uint32_t)0x08000000) /*!< Slave preload enable */ - -#define HRTIM_TIMCR_UPDGAT ((uint32_t)0xF0000000) /*!< Slave update gating mask */ -#define HRTIM_TIMCR_UPDGAT_0 ((uint32_t)0x10000000) /*!< Update gating bit 0 */ -#define HRTIM_TIMCR_UPDGAT_1 ((uint32_t)0x20000000) /*!< Update gating bit 1 */ -#define HRTIM_TIMCR_UPDGAT_2 ((uint32_t)0x40000000) /*!< Update gating bit 2 */ -#define HRTIM_TIMCR_UPDGAT_3 ((uint32_t)0x80000000) /*!< Update gating bit 3 */ - -/******************** Slave Interrupt status register **************************/ -#define HRTIM_TIMISR_CMP1 ((uint32_t)0x00000001) /*!< Slave compare 1 interrupt flag */ -#define HRTIM_TIMISR_CMP2 ((uint32_t)0x00000002) /*!< Slave compare 2 interrupt flag */ -#define HRTIM_TIMISR_CMP3 ((uint32_t)0x00000004) /*!< Slave compare 3 interrupt flag */ -#define HRTIM_TIMISR_CMP4 ((uint32_t)0x00000008) /*!< Slave compare 4 interrupt flag */ -#define HRTIM_TIMISR_REP ((uint32_t)0x00000010) /*!< Slave repetition interrupt flag */ -#define HRTIM_TIMISR_UPD ((uint32_t)0x00000040) /*!< Slave update interrupt flag */ -#define HRTIM_TIMISR_CPT1 ((uint32_t)0x00000080) /*!< Slave capture 1 interrupt flag */ -#define HRTIM_TIMISR_CPT2 ((uint32_t)0x00000100) /*!< Slave capture 2 interrupt flag */ -#define HRTIM_TIMISR_SET1 ((uint32_t)0x00000200) /*!< Slave output 1 set interrupt flag */ -#define HRTIM_TIMISR_RST1 ((uint32_t)0x00000400) /*!< Slave output 1 reset interrupt flag */ -#define HRTIM_TIMISR_SET2 ((uint32_t)0x00000800) /*!< Slave output 2 set interrupt flag */ -#define HRTIM_TIMISR_RST2 ((uint32_t)0x00001000) /*!< Slave output 2 reset interrupt flag */ -#define HRTIM_TIMISR_RST ((uint32_t)0x00002000) /*!< Slave reset interrupt flag */ -#define HRTIM_TIMISR_DLYPRT ((uint32_t)0x00004000) /*!< Slave output 1 delay protection interrupt flag */ -#define HRTIM_TIMISR_CPPSTAT ((uint32_t)0x00010000) /*!< Slave current push-pull flag */ -#define HRTIM_TIMISR_IPPSTAT ((uint32_t)0x00020000) /*!< Slave idle push-pull flag */ -#define HRTIM_TIMISR_O1STAT ((uint32_t)0x00040000) /*!< Slave output 1 state flag */ -#define HRTIM_TIMISR_O2STAT ((uint32_t)0x00080000) /*!< Slave output 2 state flag */ -#define HRTIM_TIMISR_O1CPY ((uint32_t)0x00100000) /*!< Slave output 1 copy flag */ -#define HRTIM_TIMISR_O2CPY ((uint32_t)0x00200000) /*!< Slave output 2 copy flag */ - -/******************** Slave Interrupt clear register **************************/ -#define HRTIM_TIMICR_CMP1C ((uint32_t)0x00000001) /*!< Slave compare 1 clear flag */ -#define HRTIM_TIMICR_CMP2C ((uint32_t)0x00000002) /*!< Slave compare 2 clear flag */ -#define HRTIM_TIMICR_CMP3C ((uint32_t)0x00000004) /*!< Slave compare 3 clear flag */ -#define HRTIM_TIMICR_CMP4C ((uint32_t)0x00000008) /*!< Slave compare 4 clear flag */ -#define HRTIM_TIMICR_REPC ((uint32_t)0x00000010) /*!< Slave repetition clear flag */ -#define HRTIM_TIMICR_UPDC ((uint32_t)0x00000040) /*!< Slave update clear flag */ -#define HRTIM_TIMICR_CPT1C ((uint32_t)0x00000080) /*!< Slave capture 1 clear flag */ -#define HRTIM_TIMICR_CPT2C ((uint32_t)0x00000100) /*!< Slave capture 2 clear flag */ -#define HRTIM_TIMICR_SET1C ((uint32_t)0x00000200) /*!< Slave output 1 set clear flag */ -#define HRTIM_TIMICR_RST1C ((uint32_t)0x00000400) /*!< Slave output 1 reset clear flag */ -#define HRTIM_TIMICR_SET2C ((uint32_t)0x00000800) /*!< Slave output 2 set clear flag */ -#define HRTIM_TIMICR_RST2C ((uint32_t)0x00001000) /*!< Slave output 2 reset clear flag */ -#define HRTIM_TIMICR_RSTC ((uint32_t)0x00002000) /*!< Slave reset clear flag */ -#define HRTIM_TIMICR_DLYPRT1C ((uint32_t)0x00004000) /*!< Slave output 1 delay protection clear flag */ -#define HRTIM_TIMICR_DLYPRT2C ((uint32_t)0x00008000) /*!< Slave output 2 delay protection clear flag */ - -/******************** Slave DMA/Interrupt enable register *********************/ -#define HRTIM_TIMDIER_CMP1IE ((uint32_t)0x00000001) /*!< Slave compare 1 interrupt enable */ -#define HRTIM_TIMDIER_CMP2IE ((uint32_t)0x00000002) /*!< Slave compare 2 interrupt enable */ -#define HRTIM_TIMDIER_CMP3IE ((uint32_t)0x00000004) /*!< Slave compare 3 interrupt enable */ -#define HRTIM_TIMDIER_CMP4IE ((uint32_t)0x00000008) /*!< Slave compare 4 interrupt enable */ -#define HRTIM_TIMDIER_REPIE ((uint32_t)0x00000010) /*!< Slave repetition interrupt enable */ -#define HRTIM_TIMDIER_UPDIE ((uint32_t)0x00000040) /*!< Slave update interrupt enable */ -#define HRTIM_TIMDIER_CPT1IE ((uint32_t)0x00000080) /*!< Slave capture 1 interrupt enable */ -#define HRTIM_TIMDIER_CPT2IE ((uint32_t)0x00000100) /*!< Slave capture 2 interrupt enable */ -#define HRTIM_TIMDIER_SET1IE ((uint32_t)0x00000200) /*!< Slave output 1 set interrupt enable */ -#define HRTIM_TIMDIER_RST1IE ((uint32_t)0x00000400) /*!< Slave output 1 reset interrupt enable */ -#define HRTIM_TIMDIER_SET2IE ((uint32_t)0x00000800) /*!< Slave output 2 set interrupt enable */ -#define HRTIM_TIMDIER_RST2IE ((uint32_t)0x00001000) /*!< Slave output 2 reset interrupt enable */ -#define HRTIM_TIMDIER_RSTIE ((uint32_t)0x00002000) /*!< Slave reset interrupt enable */ -#define HRTIM_TIMDIER_DLYPRTIE ((uint32_t)0x00004000) /*!< Slave delay protection interrupt enable */ - -#define HRTIM_TIMDIER_CMP1DE ((uint32_t)0x00010000) /*!< Slave compare 1 request enable */ -#define HRTIM_TIMDIER_CMP2DE ((uint32_t)0x00020000) /*!< Slave compare 2 request enable */ -#define HRTIM_TIMDIER_CMP3DE ((uint32_t)0x00040000) /*!< Slave compare 3 request enable */ -#define HRTIM_TIMDIER_CMP4DE ((uint32_t)0x00080000) /*!< Slave compare 4 request enable */ -#define HRTIM_TIMDIER_REPDE ((uint32_t)0x00100000) /*!< Slave repetition request enable */ -#define HRTIM_TIMDIER_UPDDE ((uint32_t)0x00400000) /*!< Slave update request enable */ -#define HRTIM_TIMDIER_CPT1DE ((uint32_t)0x00800000) /*!< Slave capture 1 request enable */ -#define HRTIM_TIMDIER_CPT2DE ((uint32_t)0x01000000) /*!< Slave capture 2 request enable */ -#define HRTIM_TIMDIER_SET1DE ((uint32_t)0x02000000) /*!< Slave output 1 set request enable */ -#define HRTIM_TIMDIER_RST1DE ((uint32_t)0x04000000) /*!< Slave output 1 reset request enable */ -#define HRTIM_TIMDIER_SET2DE ((uint32_t)0x08000000) /*!< Slave output 2 set request enable */ -#define HRTIM_TIMDIER_RST2DE ((uint32_t)0x10000000) /*!< Slave output 2 reset request enable */ -#define HRTIM_TIMDIER_RSTDE ((uint32_t)0x20000000) /*!< Slave reset request enable */ -#define HRTIM_TIMDIER_DLYPRTDE ((uint32_t)0x40000000) /*!< Slave delay protection request enable */ - -/****************** Bit definition for HRTIM_CNTR register ****************/ -#define HRTIM_CNTR_CNTR ((uint32_t)0xFFFFFFFF) /*!< Counter Value */ - -/******************* Bit definition for HRTIM_PER register *****************/ -#define HRTIM_PER_PER ((uint32_t)0xFFFFFFFF) /*!< Period Value */ - -/******************* Bit definition for HRTIM_REP register *****************/ -#define HRTIM_REP_REP ((uint32_t)0xFFFFFFFF) /*!< Repetition Value */ - -/******************* Bit definition for HRTIM_CMP1R register *****************/ -#define HRTIM_CMP1R_CMP1R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */ - -/******************* Bit definition for HRTIM_CMP1CR register *****************/ -#define HRTIM_CMP1CR_CMP1CR ((uint32_t)0xFFFFFFFF) /*!< Compare Value */ - -/******************* Bit definition for HRTIM_CMP2R register *****************/ -#define HRTIM_CMP2R_CMP2R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */ - -/******************* Bit definition for HRTIM_CMP3R register *****************/ -#define HRTIM_CMP3R_CMP3R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */ - -/******************* Bit definition for HRTIM_CMP4R register *****************/ -#define HRTIM_CMP4R_CMP4R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */ - -/******************* Bit definition for HRTIM_CPT1R register ****************/ -#define HRTIM_CPT1R_CPT1R ((uint32_t)0xFFFFFFFF) /*!< Capture Value */ - -/******************* Bit definition for HRTIM_CPT2R register ****************/ -#define HRTIM_CPT2R_CPT2R ((uint32_t)0xFFFFFFFF) /*!< Capture Value */ - -/******************** Bit definition for Slave Deadtime register **************/ -#define HRTIM_DTR_DTR ((uint32_t)0x000001FF) /*!< Dead time rising value */ -#define HRTIM_DTR_DTR_0 ((uint32_t)0x00000001) /*!< Dead time rising bit 0 */ -#define HRTIM_DTR_DTR_1 ((uint32_t)0x00000002) /*!< Dead time rising bit 1 */ -#define HRTIM_DTR_DTR_2 ((uint32_t)0x00000004) /*!< Dead time rising bit 2 */ -#define HRTIM_DTR_DTR_3 ((uint32_t)0x00000008) /*!< Dead time rising bit 3 */ -#define HRTIM_DTR_DTR_4 ((uint32_t)0x00000010) /*!< Dead time rising bit 4 */ -#define HRTIM_DTR_DTR_5 ((uint32_t)0x00000020) /*!< Dead time rising bit 5 */ -#define HRTIM_DTR_DTR_6 ((uint32_t)0x00000040) /*!< Dead time rising bit 6 */ -#define HRTIM_DTR_DTR_7 ((uint32_t)0x00000080) /*!< Dead time rising bit 7 */ -#define HRTIM_DTR_DTR_8 ((uint32_t)0x00000100) /*!< Dead time rising bit 8 */ -#define HRTIM_DTR_SDTR ((uint32_t)0x00000200) /*!< Sign dead time rising value */ -#define HRTIM_DTR_DTPRSC ((uint32_t)0x00001C00) /*!< Dead time prescaler */ -#define HRTIM_DTR_DTPRSC_0 ((uint32_t)0x00000400) /*!< Dead time prescaler bit 0 */ -#define HRTIM_DTR_DTPRSC_1 ((uint32_t)0x00000800) /*!< Dead time prescaler bit 1 */ -#define HRTIM_DTR_DTPRSC_2 ((uint32_t)0x00001000) /*!< Dead time prescaler bit 2 */ -#define HRTIM_DTR_DTRSLK ((uint32_t)0x00004000) /*!< Dead time rising sign lock */ -#define HRTIM_DTR_DTRLK ((uint32_t)0x00008000) /*!< Dead time rising lock */ -#define HRTIM_DTR_DTF ((uint32_t)0x01FF0000) /*!< Dead time falling value */ -#define HRTIM_DTR_DTF_0 ((uint32_t)0x00010000) /*!< Dead time falling bit 0 */ -#define HRTIM_DTR_DTF_1 ((uint32_t)0x00020000) /*!< Dead time falling bit 1 */ -#define HRTIM_DTR_DTF_2 ((uint32_t)0x00040000) /*!< Dead time falling bit 2 */ -#define HRTIM_DTR_DTF_3 ((uint32_t)0x00080000) /*!< Dead time falling bit 3 */ -#define HRTIM_DTR_DTF_4 ((uint32_t)0x00100000) /*!< Dead time falling bit 4 */ -#define HRTIM_DTR_DTF_5 ((uint32_t)0x00200000) /*!< Dead time falling bit 5 */ -#define HRTIM_DTR_DTF_6 ((uint32_t)0x00400000) /*!< Dead time falling bit 6 */ -#define HRTIM_DTR_DTF_7 ((uint32_t)0x00800000) /*!< Dead time falling bit 7 */ -#define HRTIM_DTR_DTF_8 ((uint32_t)0x01000000) /*!< Dead time falling bit 8 */ -#define HRTIM_DTR_SDTF ((uint32_t)0x02000000) /*!< Sign dead time falling value */ -#define HRTIM_DTR_DTFSLK ((uint32_t)0x40000000) /*!< Dead time falling sign lock */ -#define HRTIM_DTR_DTFLK ((uint32_t)0x80000000) /*!< Dead time falling lock */ - -/**** Bit definition for Slave Output 1 set register **************************/ -#define HRTIM_SET1R_SST ((uint32_t)0x00000001) /*!< software set trigger */ -#define HRTIM_SET1R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */ -#define HRTIM_SET1R_PER ((uint32_t)0x00000004) /*!< Timer A period */ -#define HRTIM_SET1R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */ -#define HRTIM_SET1R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */ -#define HRTIM_SET1R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */ -#define HRTIM_SET1R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */ - -#define HRTIM_SET1R_MSTPER ((uint32_t)0x00000080) /*!< Master period */ -#define HRTIM_SET1R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */ -#define HRTIM_SET1R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */ -#define HRTIM_SET1R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */ -#define HRTIM_SET1R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */ - -#define HRTIM_SET1R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */ -#define HRTIM_SET1R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */ -#define HRTIM_SET1R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */ -#define HRTIM_SET1R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */ -#define HRTIM_SET1R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */ -#define HRTIM_SET1R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */ -#define HRTIM_SET1R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */ -#define HRTIM_SET1R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */ -#define HRTIM_SET1R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */ - -#define HRTIM_SET1R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */ -#define HRTIM_SET1R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */ -#define HRTIM_SET1R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */ -#define HRTIM_SET1R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */ -#define HRTIM_SET1R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */ -#define HRTIM_SET1R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */ -#define HRTIM_SET1R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */ -#define HRTIM_SET1R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */ -#define HRTIM_SET1R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */ -#define HRTIM_SET1R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */ - -#define HRTIM_SET1R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */ - -/**** Bit definition for Slave Output 1 reset register ************************/ -#define HRTIM_RST1R_SRT ((uint32_t)0x00000001) /*!< software reset trigger */ -#define HRTIM_RST1R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */ -#define HRTIM_RST1R_PER ((uint32_t)0x00000004) /*!< Timer A period */ -#define HRTIM_RST1R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */ -#define HRTIM_RST1R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */ -#define HRTIM_RST1R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */ -#define HRTIM_RST1R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */ - -#define HRTIM_RST1R_MSTPER ((uint32_t)0x00000080) /*!< Master period */ -#define HRTIM_RST1R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */ -#define HRTIM_RST1R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */ -#define HRTIM_RST1R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */ -#define HRTIM_RST1R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */ - -#define HRTIM_RST1R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */ -#define HRTIM_RST1R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */ -#define HRTIM_RST1R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */ -#define HRTIM_RST1R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */ -#define HRTIM_RST1R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */ -#define HRTIM_RST1R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */ -#define HRTIM_RST1R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */ -#define HRTIM_RST1R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */ -#define HRTIM_RST1R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */ - -#define HRTIM_RST1R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */ -#define HRTIM_RST1R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */ -#define HRTIM_RST1R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */ -#define HRTIM_RST1R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */ -#define HRTIM_RST1R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */ -#define HRTIM_RST1R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */ -#define HRTIM_RST1R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */ -#define HRTIM_RST1R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */ -#define HRTIM_RST1R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */ -#define HRTIM_RST1R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */ - -#define HRTIM_RST1R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */ - - -/**** Bit definition for Slave Output 2 set register **************************/ -#define HRTIM_SET2R_SST ((uint32_t)0x00000001) /*!< software set trigger */ -#define HRTIM_SET2R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */ -#define HRTIM_SET2R_PER ((uint32_t)0x00000004) /*!< Timer A period */ -#define HRTIM_SET2R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */ -#define HRTIM_SET2R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */ -#define HRTIM_SET2R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */ -#define HRTIM_SET2R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */ - -#define HRTIM_SET2R_MSTPER ((uint32_t)0x00000080) /*!< Master period */ -#define HRTIM_SET2R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */ -#define HRTIM_SET2R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */ -#define HRTIM_SET2R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */ -#define HRTIM_SET2R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */ - -#define HRTIM_SET2R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */ -#define HRTIM_SET2R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */ -#define HRTIM_SET2R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */ -#define HRTIM_SET2R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */ -#define HRTIM_SET2R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */ -#define HRTIM_SET2R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */ -#define HRTIM_SET2R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */ -#define HRTIM_SET2R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */ -#define HRTIM_SET2R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */ - -#define HRTIM_SET2R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */ -#define HRTIM_SET2R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */ -#define HRTIM_SET2R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */ -#define HRTIM_SET2R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */ -#define HRTIM_SET2R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */ -#define HRTIM_SET2R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */ -#define HRTIM_SET2R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */ -#define HRTIM_SET2R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */ -#define HRTIM_SET2R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */ -#define HRTIM_SET2R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */ - -#define HRTIM_SET2R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */ - -/**** Bit definition for Slave Output 2 reset register ************************/ -#define HRTIM_RST2R_SRT ((uint32_t)0x00000001) /*!< software reset trigger */ -#define HRTIM_RST2R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */ -#define HRTIM_RST2R_PER ((uint32_t)0x00000004) /*!< Timer A period */ -#define HRTIM_RST2R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */ -#define HRTIM_RST2R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */ -#define HRTIM_RST2R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */ -#define HRTIM_RST2R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */ - -#define HRTIM_RST2R_MSTPER ((uint32_t)0x00000080) /*!< Master period */ -#define HRTIM_RST2R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */ -#define HRTIM_RST2R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */ -#define HRTIM_RST2R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */ -#define HRTIM_RST2R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */ - -#define HRTIM_RST2R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */ -#define HRTIM_RST2R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */ -#define HRTIM_RST2R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */ -#define HRTIM_RST2R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */ -#define HRTIM_RST2R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */ -#define HRTIM_RST2R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */ -#define HRTIM_RST2R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */ -#define HRTIM_RST2R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */ -#define HRTIM_RST2R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */ - -#define HRTIM_RST2R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */ -#define HRTIM_RST2R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */ -#define HRTIM_RST2R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */ -#define HRTIM_RST2R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */ -#define HRTIM_RST2R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */ -#define HRTIM_RST2R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */ -#define HRTIM_RST2R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */ -#define HRTIM_RST2R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */ -#define HRTIM_RST2R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */ -#define HRTIM_RST2R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */ - -#define HRTIM_RST2R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */ - -/**** Bit definition for Slave external event filtering register 1 ***********/ -#define HRTIM_EEFR1_EE1LTCH ((uint32_t)0x00000001) /*!< External Event 1 latch */ -#define HRTIM_EEFR1_EE1FLTR ((uint32_t)0x0000001E) /*!< External Event 1 filter mask */ -#define HRTIM_EEFR1_EE1FLTR_0 ((uint32_t)0x00000002) /*!< External Event 1 bit 0 */ -#define HRTIM_EEFR1_EE1FLTR_1 ((uint32_t)0x00000004) /*!< External Event 1 bit 1*/ -#define HRTIM_EEFR1_EE1FLTR_2 ((uint32_t)0x00000008) /*!< External Event 1 bit 2 */ -#define HRTIM_EEFR1_EE1FLTR_3 ((uint32_t)0x00000010) /*!< External Event 1 bit 3 */ - -#define HRTIM_EEFR1_EE2LTCH ((uint32_t)0x00000040) /*!< External Event 2 latch */ -#define HRTIM_EEFR1_EE2FLTR ((uint32_t)0x00000780) /*!< External Event 2 filter mask */ -#define HRTIM_EEFR1_EE2FLTR_0 ((uint32_t)0x00000080) /*!< External Event 2 bit 0 */ -#define HRTIM_EEFR1_EE2FLTR_1 ((uint32_t)0x00000100) /*!< External Event 2 bit 1*/ -#define HRTIM_EEFR1_EE2FLTR_2 ((uint32_t)0x00000200) /*!< External Event 2 bit 2 */ -#define HRTIM_EEFR1_EE2FLTR_3 ((uint32_t)0x00000400) /*!< External Event 2 bit 3 */ - -#define HRTIM_EEFR1_EE3LTCH ((uint32_t)0x00001000) /*!< External Event 3 latch */ -#define HRTIM_EEFR1_EE3FLTR ((uint32_t)0x0001E000) /*!< External Event 3 filter mask */ -#define HRTIM_EEFR1_EE3FLTR_0 ((uint32_t)0x00002000) /*!< External Event 3 bit 0 */ -#define HRTIM_EEFR1_EE3FLTR_1 ((uint32_t)0x00004000) /*!< External Event 3 bit 1*/ -#define HRTIM_EEFR1_EE3FLTR_2 ((uint32_t)0x00008000) /*!< External Event 3 bit 2 */ -#define HRTIM_EEFR1_EE3FLTR_3 ((uint32_t)0x00010000) /*!< External Event 3 bit 3 */ - -#define HRTIM_EEFR1_EE4LTCH ((uint32_t)0x00040000) /*!< External Event 4 latch */ -#define HRTIM_EEFR1_EE4FLTR ((uint32_t)0x00780000) /*!< External Event 4 filter mask */ -#define HRTIM_EEFR1_EE4FLTR_0 ((uint32_t)0x00080000) /*!< External Event 4 bit 0 */ -#define HRTIM_EEFR1_EE4FLTR_1 ((uint32_t)0x00100000) /*!< External Event 4 bit 1*/ -#define HRTIM_EEFR1_EE4FLTR_2 ((uint32_t)0x00200000) /*!< External Event 4 bit 2 */ -#define HRTIM_EEFR1_EE4FLTR_3 ((uint32_t)0x00400000) /*!< External Event 4 bit 3 */ - -#define HRTIM_EEFR1_EE5LTCH ((uint32_t)0x01000000) /*!< External Event 5 latch */ -#define HRTIM_EEFR1_EE5FLTR ((uint32_t)0x1E000000) /*!< External Event 5 filter mask */ -#define HRTIM_EEFR1_EE5FLTR_0 ((uint32_t)0x02000000) /*!< External Event 5 bit 0 */ -#define HRTIM_EEFR1_EE5FLTR_1 ((uint32_t)0x04000000) /*!< External Event 5 bit 1*/ -#define HRTIM_EEFR1_EE5FLTR_2 ((uint32_t)0x08000000) /*!< External Event 5 bit 2 */ -#define HRTIM_EEFR1_EE5FLTR_3 ((uint32_t)0x10000000) /*!< External Event 5 bit 3 */ - -/**** Bit definition for Slave external event filtering register 2 ***********/ -#define HRTIM_EEFR2_EE6LTCH ((uint32_t)0x00000001) /*!< External Event 6 latch */ -#define HRTIM_EEFR2_EE6FLTR ((uint32_t)0x0000001E) /*!< External Event 6 filter mask */ -#define HRTIM_EEFR2_EE6FLTR_0 ((uint32_t)0x00000002) /*!< External Event 6 bit 0 */ -#define HRTIM_EEFR2_EE6FLTR_1 ((uint32_t)0x00000004) /*!< External Event 6 bit 1*/ -#define HRTIM_EEFR2_EE6FLTR_2 ((uint32_t)0x00000008) /*!< External Event 6 bit 2 */ -#define HRTIM_EEFR2_EE6FLTR_3 ((uint32_t)0x00000010) /*!< External Event 6 bit 3 */ - -#define HRTIM_EEFR2_EE7LTCH ((uint32_t)0x00000040) /*!< External Event 7 latch */ -#define HRTIM_EEFR2_EE7FLTR ((uint32_t)0x00000780) /*!< External Event 7 filter mask */ -#define HRTIM_EEFR2_EE7FLTR_0 ((uint32_t)0x00000080) /*!< External Event 7 bit 0 */ -#define HRTIM_EEFR2_EE7FLTR_1 ((uint32_t)0x00000100) /*!< External Event 7 bit 1*/ -#define HRTIM_EEFR2_EE7FLTR_2 ((uint32_t)0x00000200) /*!< External Event 7 bit 2 */ -#define HRTIM_EEFR2_EE7FLTR_3 ((uint32_t)0x00000400) /*!< External Event 7 bit 3 */ - -#define HRTIM_EEFR2_EE8LTCH ((uint32_t)0x00001000) /*!< External Event 8 latch */ -#define HRTIM_EEFR2_EE8FLTR ((uint32_t)0x0001E000) /*!< External Event 8 filter mask */ -#define HRTIM_EEFR2_EE8FLTR_0 ((uint32_t)0x00002000) /*!< External Event 8 bit 0 */ -#define HRTIM_EEFR2_EE8FLTR_1 ((uint32_t)0x00004000) /*!< External Event 8 bit 1*/ -#define HRTIM_EEFR2_EE8FLTR_2 ((uint32_t)0x00008000) /*!< External Event 8 bit 2 */ -#define HRTIM_EEFR2_EE8FLTR_3 ((uint32_t)0x00010000) /*!< External Event 8 bit 3 */ - -#define HRTIM_EEFR2_EE9LTCH ((uint32_t)0x00040000) /*!< External Event 9 latch */ -#define HRTIM_EEFR2_EE9FLTR ((uint32_t)0x00780000) /*!< External Event 9 filter mask */ -#define HRTIM_EEFR2_EE9FLTR_0 ((uint32_t)0x00080000) /*!< External Event 9 bit 0 */ -#define HRTIM_EEFR2_EE9FLTR_1 ((uint32_t)0x00100000) /*!< External Event 9 bit 1*/ -#define HRTIM_EEFR2_EE9FLTR_2 ((uint32_t)0x00200000) /*!< External Event 9 bit 2 */ -#define HRTIM_EEFR2_EE9FLTR_3 ((uint32_t)0x00400000) /*!< External Event 9 bit 3 */ - -#define HRTIM_EEFR2_EE10LTCH ((uint32_t)0x01000000) /*!< External Event 10 latch */ -#define HRTIM_EEFR2_EE10FLTR ((uint32_t)0x1E000000) /*!< External Event 10 filter mask */ -#define HRTIM_EEFR2_EE10FLTR_0 ((uint32_t)0x02000000) /*!< External Event 10 bit 0 */ -#define HRTIM_EEFR2_EE10FLTR_1 ((uint32_t)0x04000000) /*!< External Event 10 bit 1*/ -#define HRTIM_EEFR2_EE10FLTR_2 ((uint32_t)0x08000000) /*!< External Event 10 bit 2 */ -#define HRTIM_EEFR2_EE10FLTR_3 ((uint32_t)0x10000000) /*!< External Event 10 bit 3 */ - -/**** Bit definition for Slave Timer reset register ***************************/ -#define HRTIM_RSTR_UPDATE ((uint32_t)0x00000002) /*!< Timer update */ -#define HRTIM_RSTR_CMP2 ((uint32_t)0x00000004) /*!< Timer compare2 */ -#define HRTIM_RSTR_CMP4 ((uint32_t)0x00000008) /*!< Timer compare4 */ - -#define HRTIM_RSTR_MSTPER ((uint32_t)0x00000010) /*!< Master period */ -#define HRTIM_RSTR_MSTCMP1 ((uint32_t)0x00000020) /*!< Master compare1 */ -#define HRTIM_RSTR_MSTCMP2 ((uint32_t)0x00000040) /*!< Master compare2 */ -#define HRTIM_RSTR_MSTCMP3 ((uint32_t)0x00000080) /*!< Master compare3 */ -#define HRTIM_RSTR_MSTCMP4 ((uint32_t)0x00000100) /*!< Master compare4 */ - -#define HRTIM_RSTR_EXTEVNT1 ((uint32_t)0x00000200) /*!< External event 1 */ -#define HRTIM_RSTR_EXTEVNT2 ((uint32_t)0x00000400) /*!< External event 2 */ -#define HRTIM_RSTR_EXTEVNT3 ((uint32_t)0x00000800) /*!< External event 3 */ -#define HRTIM_RSTR_EXTEVNT4 ((uint32_t)0x00001000) /*!< External event 4 */ -#define HRTIM_RSTR_EXTEVNT5 ((uint32_t)0x00002000) /*!< External event 5 */ -#define HRTIM_RSTR_EXTEVNT6 ((uint32_t)0x00004000) /*!< External event 6 */ -#define HRTIM_RSTR_EXTEVNT7 ((uint32_t)0x00008000) /*!< External event 7 */ -#define HRTIM_RSTR_EXTEVNT8 ((uint32_t)0x00010000) /*!< External event 8 */ -#define HRTIM_RSTR_EXTEVNT9 ((uint32_t)0x00020000) /*!< External event 9 */ -#define HRTIM_RSTR_EXTEVNT10 ((uint32_t)0x00040000) /*!< External event 10 */ - -#define HRTIM_RSTR_TIMBCMP1 ((uint32_t)0x00080000) /*!< Timer B compare 1 */ -#define HRTIM_RSTR_TIMBCMP2 ((uint32_t)0x00100000) /*!< Timer B compare 2 */ -#define HRTIM_RSTR_TIMBCMP4 ((uint32_t)0x00200000) /*!< Timer B compare 4 */ - -#define HRTIM_RSTR_TIMCCMP1 ((uint32_t)0x00400000) /*!< Timer C compare 1 */ -#define HRTIM_RSTR_TIMCCMP2 ((uint32_t)0x00800000) /*!< Timer C compare 2 */ -#define HRTIM_RSTR_TIMCCMP4 ((uint32_t)0x01000000) /*!< Timer C compare 4 */ - -#define HRTIM_RSTR_TIMDCMP1 ((uint32_t)0x02000000) /*!< Timer D compare 1 */ -#define HRTIM_RSTR_TIMDCMP2 ((uint32_t)0x04000000) /*!< Timer D compare 2 */ -#define HRTIM_RSTR_TIMDCMP4 ((uint32_t)0x08000000) /*!< Timer D compare 4 */ - -#define HRTIM_RSTR_TIMECMP1 ((uint32_t)0x10000000) /*!< Timer E compare 1 */ -#define HRTIM_RSTR_TIMECMP2 ((uint32_t)0x20000000) /*!< Timer E compare 2 */ -#define HRTIM_RSTR_TIMECMP4 ((uint32_t)0x40000000) /*!< Timer E compare 4 */ - -/**** Bit definition for Slave Timer Chopper register *************************/ -#define HRTIM_CHPR_CARFRQ ((uint32_t)0x0000000F) /*!< Timer carrier frequency value */ -#define HRTIM_CHPR_CARFRQ_0 ((uint32_t)0x00000001) /*!< Timer carrier frequency value bit 0 */ -#define HRTIM_CHPR_CARFRQ_1 ((uint32_t)0x00000002) /*!< Timer carrier frequency value bit 1 */ -#define HRTIM_CHPR_CARFRQ_2 ((uint32_t)0x00000004) /*!< Timer carrier frequency value bit 2 */ -#define HRTIM_CHPR_CARFRQ_3 ((uint32_t)0x00000008) /*!< Timer carrier frequency value bit 3 */ - -#define HRTIM_CHPR_CARDTY ((uint32_t)0x00000070) /*!< Timer chopper duty cycle value */ -#define HRTIM_CHPR_CARDTY_0 ((uint32_t)0x00000010) /*!< Timer chopper duty cycle value bit 0 */ -#define HRTIM_CHPR_CARDTY_1 ((uint32_t)0x00000020) /*!< Timer chopper duty cycle value bit 1 */ -#define HRTIM_CHPR_CARDTY_2 ((uint32_t)0x00000040) /*!< Timer chopper duty cycle value bit 2 */ - -#define HRTIM_CHPR_STRPW ((uint32_t)0x00000780) /*!< Timer start pulse width value */ -#define HRTIM_CHPR_STRPW_0 ((uint32_t)0x00000080) /*!< Timer start pulse width value bit 0 */ -#define HRTIM_CHPR_STRPW_1 ((uint32_t)0x00000100) /*!< Timer start pulse width value bit 1 */ -#define HRTIM_CHPR_STRPW_2 ((uint32_t)0x00000200) /*!< Timer start pulse width value bit 2 */ -#define HRTIM_CHPR_STRPW_3 ((uint32_t)0x00000400) /*!< Timer start pulse width value bit 3 */ - -/**** Bit definition for Slave Timer Capture 1 control register ***************/ -#define HRTIM_CPT1CR_SWCPT ((uint32_t)0x00000001) /*!< Software capture */ -#define HRTIM_CPT1CR_UPDCPT ((uint32_t)0x00000002) /*!< Update capture */ -#define HRTIM_CPT1CR_EXEV1CPT ((uint32_t)0x00000004) /*!< External event 1 capture */ -#define HRTIM_CPT1CR_EXEV2CPT ((uint32_t)0x00000008) /*!< External event 2 capture */ -#define HRTIM_CPT1CR_EXEV3CPT ((uint32_t)0x00000010) /*!< External event 3 capture */ -#define HRTIM_CPT1CR_EXEV4CPT ((uint32_t)0x00000020) /*!< External event 4 capture */ -#define HRTIM_CPT1CR_EXEV5CPT ((uint32_t)0x00000040) /*!< External event 5 capture */ -#define HRTIM_CPT1CR_EXEV6CPT ((uint32_t)0x00000080) /*!< External event 6 capture */ -#define HRTIM_CPT1CR_EXEV7CPT ((uint32_t)0x00000100) /*!< External event 7 capture */ -#define HRTIM_CPT1CR_EXEV8CPT ((uint32_t)0x00000200) /*!< External event 8 capture */ -#define HRTIM_CPT1CR_EXEV9CPT ((uint32_t)0x00000400) /*!< External event 9 capture */ -#define HRTIM_CPT1CR_EXEV10CPT ((uint32_t)0x00000800) /*!< External event 10 capture */ - -#define HRTIM_CPT1CR_TA1SET ((uint32_t)0x00001000) /*!< Timer A output 1 set */ -#define HRTIM_CPT1CR_TA1RST ((uint32_t)0x00002000) /*!< Timer A output 1 reset */ -#define HRTIM_CPT1CR_TA1CMP1 ((uint32_t)0x00004000) /*!< Timer A compare 1 */ -#define HRTIM_CPT1CR_TA1CMP2 ((uint32_t)0x00008000) /*!< Timer A compare 2 */ - -#define HRTIM_CPT1CR_TB1SET ((uint32_t)0x00010000) /*!< Timer B output 1 set */ -#define HRTIM_CPT1CR_TB1RST ((uint32_t)0x00020000) /*!< Timer B output 1 reset */ -#define HRTIM_CPT1CR_TB1CMP1 ((uint32_t)0x00040000) /*!< Timer B compare 1 */ -#define HRTIM_CPT1CR_TB1CMP2 ((uint32_t)0x00080000) /*!< Timer B compare 2 */ - -#define HRTIM_CPT1CR_TC1SET ((uint32_t)0x00100000) /*!< Timer C output 1 set */ -#define HRTIM_CPT1CR_TC1RST ((uint32_t)0x00200000) /*!< Timer C output 1 reset */ -#define HRTIM_CPT1CR_TC1CMP1 ((uint32_t)0x00400000) /*!< Timer C compare 1 */ -#define HRTIM_CPT1CR_TC1CMP2 ((uint32_t)0x00800000) /*!< Timer C compare 2 */ - -#define HRTIM_CPT1CR_TD1SET ((uint32_t)0x01000000) /*!< Timer D output 1 set */ -#define HRTIM_CPT1CR_TD1RST ((uint32_t)0x02000000) /*!< Timer D output 1 reset */ -#define HRTIM_CPT1CR_TD1CMP1 ((uint32_t)0x04000000) /*!< Timer D compare 1 */ -#define HRTIM_CPT1CR_TD1CMP2 ((uint32_t)0x08000000) /*!< Timer D compare 2 */ - -#define HRTIM_CPT1CR_TE1SET ((uint32_t)0x10000000) /*!< Timer E output 1 set */ -#define HRTIM_CPT1CR_TE1RST ((uint32_t)0x20000000) /*!< Timer E output 1 reset */ -#define HRTIM_CPT1CR_TE1CMP1 ((uint32_t)0x40000000) /*!< Timer E compare 1 */ -#define HRTIM_CPT1CR_TE1CMP2 ((uint32_t)0x80000000) /*!< Timer E compare 2 */ - -/**** Bit definition for Slave Timer Capture 2 control register ***************/ -#define HRTIM_CPT2CR_SWCPT ((uint32_t)0x00000001) /*!< Software capture */ -#define HRTIM_CPT2CR_UPDCPT ((uint32_t)0x00000002) /*!< Update capture */ -#define HRTIM_CPT2CR_EXEV1CPT ((uint32_t)0x00000004) /*!< External event 1 capture */ -#define HRTIM_CPT2CR_EXEV2CPT ((uint32_t)0x00000008) /*!< External event 2 capture */ -#define HRTIM_CPT2CR_EXEV3CPT ((uint32_t)0x00000010) /*!< External event 3 capture */ -#define HRTIM_CPT2CR_EXEV4CPT ((uint32_t)0x00000020) /*!< External event 4 capture */ -#define HRTIM_CPT2CR_EXEV5CPT ((uint32_t)0x00000040) /*!< External event 5 capture */ -#define HRTIM_CPT2CR_EXEV6CPT ((uint32_t)0x00000080) /*!< External event 6 capture */ -#define HRTIM_CPT2CR_EXEV7CPT ((uint32_t)0x00000100) /*!< External event 7 capture */ -#define HRTIM_CPT2CR_EXEV8CPT ((uint32_t)0x00000200) /*!< External event 8 capture */ -#define HRTIM_CPT2CR_EXEV9CPT ((uint32_t)0x00000400) /*!< External event 9 capture */ -#define HRTIM_CPT2CR_EXEV10CPT ((uint32_t)0x00000800) /*!< External event 10 capture */ - -#define HRTIM_CPT2CR_TA1SET ((uint32_t)0x00001000) /*!< Timer A output 1 set */ -#define HRTIM_CPT2CR_TA1RST ((uint32_t)0x00002000) /*!< Timer A output 1 reset */ -#define HRTIM_CPT2CR_TA1CMP1 ((uint32_t)0x00004000) /*!< Timer A compare 1 */ -#define HRTIM_CPT2CR_TA1CMP2 ((uint32_t)0x00008000) /*!< Timer A compare 2 */ - -#define HRTIM_CPT2CR_TB1SET ((uint32_t)0x00010000) /*!< Timer B output 1 set */ -#define HRTIM_CPT2CR_TB1RST ((uint32_t)0x00020000) /*!< Timer B output 1 reset */ -#define HRTIM_CPT2CR_TB1CMP1 ((uint32_t)0x00040000) /*!< Timer B compare 1 */ -#define HRTIM_CPT2CR_TB1CMP2 ((uint32_t)0x00080000) /*!< Timer B compare 2 */ - -#define HRTIM_CPT2CR_TC1SET ((uint32_t)0x00100000) /*!< Timer C output 1 set */ -#define HRTIM_CPT2CR_TC1RST ((uint32_t)0x00200000) /*!< Timer C output 1 reset */ -#define HRTIM_CPT2CR_TC1CMP1 ((uint32_t)0x00400000) /*!< Timer C compare 1 */ -#define HRTIM_CPT2CR_TC1CMP2 ((uint32_t)0x00800000) /*!< Timer C compare 2 */ - -#define HRTIM_CPT2CR_TD1SET ((uint32_t)0x01000000) /*!< Timer D output 1 set */ -#define HRTIM_CPT2CR_TD1RST ((uint32_t)0x02000000) /*!< Timer D output 1 reset */ -#define HRTIM_CPT2CR_TD1CMP1 ((uint32_t)0x04000000) /*!< Timer D compare 1 */ -#define HRTIM_CPT2CR_TD1CMP2 ((uint32_t)0x08000000) /*!< Timer D compare 2 */ - -#define HRTIM_CPT2CR_TE1SET ((uint32_t)0x10000000) /*!< Timer E output 1 set */ -#define HRTIM_CPT2CR_TE1RST ((uint32_t)0x20000000) /*!< Timer E output 1 reset */ -#define HRTIM_CPT2CR_TE1CMP1 ((uint32_t)0x40000000) /*!< Timer E compare 1 */ -#define HRTIM_CPT2CR_TE1CMP2 ((uint32_t)0x80000000) /*!< Timer E compare 2 */ - -/**** Bit definition for Slave Timer Output register **************************/ -#define HRTIM_OUTR_POL1 ((uint32_t)0x00000002) /*!< Slave output 1 polarity */ -#define HRTIM_OUTR_IDLM1 ((uint32_t)0x00000004) /*!< Slave output 1 idle mode */ -#define HRTIM_OUTR_IDLES1 ((uint32_t)0x00000008) /*!< Slave output 1 idle state */ -#define HRTIM_OUTR_FAULT1 ((uint32_t)0x00000030) /*!< Slave output 1 fault state */ -#define HRTIM_OUTR_FAULT1_0 ((uint32_t)0x00000010) /*!< Slave output 1 fault state bit 0 */ -#define HRTIM_OUTR_FAULT1_1 ((uint32_t)0x00000020) /*!< Slave output 1 fault state bit 1 */ -#define HRTIM_OUTR_CHP1 ((uint32_t)0x00000040) /*!< Slave output 1 chopper enable */ -#define HRTIM_OUTR_DIDL1 ((uint32_t)0x00000080) /*!< Slave output 1 dead time idle */ - -#define HRTIM_OUTR_DTEN ((uint32_t)0x00000100) /*!< Slave output deadtime enable */ -#define HRTIM_OUTR_DLYPRTEN ((uint32_t)0x00000200) /*!< Slave output delay protection enable */ -#define HRTIM_OUTR_DLYPRT ((uint32_t)0x00001C00) /*!< Slave output delay protection */ -#define HRTIM_OUTR_DLYPRT_0 ((uint32_t)0x00000400) /*!< Slave output delay protection bit 0 */ -#define HRTIM_OUTR_DLYPRT_1 ((uint32_t)0x00000800) /*!< Slave output delay protection bit 1 */ -#define HRTIM_OUTR_DLYPRT_2 ((uint32_t)0x00001000) /*!< Slave output delay protection bit 2 */ - -#define HRTIM_OUTR_POL2 ((uint32_t)0x00020000) /*!< Slave output 2 polarity */ -#define HRTIM_OUTR_IDLM2 ((uint32_t)0x00040000) /*!< Slave output 2 idle mode */ -#define HRTIM_OUTR_IDLES2 ((uint32_t)0x00080000) /*!< Slave output 2 idle state */ -#define HRTIM_OUTR_FAULT2 ((uint32_t)0x00300000) /*!< Slave output 2 fault state */ -#define HRTIM_OUTR_FAULT2_0 ((uint32_t)0x00100000) /*!< Slave output 2 fault state bit 0 */ -#define HRTIM_OUTR_FAULT2_1 ((uint32_t)0x00200000) /*!< Slave output 2 fault state bit 1 */ -#define HRTIM_OUTR_CHP2 ((uint32_t)0x00400000) /*!< Slave output 2 chopper enable */ -#define HRTIM_OUTR_DIDL2 ((uint32_t)0x00800000) /*!< Slave output 2 dead time idle */ - -/**** Bit definition for Slave Timer Fault register ***************************/ -#define HRTIM_FLTR_FLT1EN ((uint32_t)0x00000001) /*!< Fault 1 enable */ -#define HRTIM_FLTR_FLT2EN ((uint32_t)0x00000002) /*!< Fault 2 enable */ -#define HRTIM_FLTR_FLT3EN ((uint32_t)0x00000004) /*!< Fault 3 enable */ -#define HRTIM_FLTR_FLT4EN ((uint32_t)0x00000008) /*!< Fault 4 enable */ -#define HRTIM_FLTR_FLT5EN ((uint32_t)0x00000010) /*!< Fault 5 enable */ -#define HRTIM_FLTR_FLTCLK ((uint32_t)0x80000000) /*!< Fault sources lock */ - -/**** Bit definition for Common HRTIM Timer control register 1 ****************/ -#define HRTIM_CR1_MUDIS ((uint32_t)0x00000001) /*!< Master update disable*/ -#define HRTIM_CR1_TAUDIS ((uint32_t)0x00000002) /*!< Timer A update disable*/ -#define HRTIM_CR1_TBUDIS ((uint32_t)0x00000004) /*!< Timer B update disable*/ -#define HRTIM_CR1_TCUDIS ((uint32_t)0x00000008) /*!< Timer C update disable*/ -#define HRTIM_CR1_TDUDIS ((uint32_t)0x00000010) /*!< Timer D update disable*/ -#define HRTIM_CR1_TEUDIS ((uint32_t)0x00000020) /*!< Timer E update disable*/ -#define HRTIM_CR1_ADC1USRC ((uint32_t)0x00070000) /*!< ADC Trigger 1 update source */ -#define HRTIM_CR1_ADC1USRC_0 ((uint32_t)0x00010000) /*!< ADC Trigger 1 update source bit 0 */ -#define HRTIM_CR1_ADC1USRC_1 ((uint32_t)0x00020000) /*!< ADC Trigger 1 update source bit 1 */ -#define HRTIM_CR1_ADC1USRC_2 ((uint32_t)0x00040000) /*!< ADC Trigger 1 update source bit 2 */ -#define HRTIM_CR1_ADC2USRC ((uint32_t)0x00380000) /*!< ADC Trigger 2 update source */ -#define HRTIM_CR1_ADC2USRC_0 ((uint32_t)0x00080000) /*!< ADC Trigger 2 update source bit 0 */ -#define HRTIM_CR1_ADC2USRC_1 ((uint32_t)0x00100000) /*!< ADC Trigger 2 update source bit 1 */ -#define HRTIM_CR1_ADC2USRC_2 ((uint32_t)0x00200000) /*!< ADC Trigger 2 update source bit 2 */ -#define HRTIM_CR1_ADC3USRC ((uint32_t)0x01C00000) /*!< ADC Trigger 3 update source */ -#define HRTIM_CR1_ADC3USRC_0 ((uint32_t)0x00400000) /*!< ADC Trigger 3 update source bit 0 */ -#define HRTIM_CR1_ADC3USRC_1 ((uint32_t)0x00800000) /*!< ADC Trigger 3 update source bit 1 */ -#define HRTIM_CR1_ADC3USRC_2 ((uint32_t)0x01000000) /*!< ADC Trigger 3 update source bit 2 */ -#define HRTIM_CR1_ADC4USRC ((uint32_t)0x0E000000) /*!< ADC Trigger 4 update source */ -#define HRTIM_CR1_ADC4USRC_0 ((uint32_t)0x02000000) /*!< ADC Trigger 4 update source bit 0 */ -#define HRTIM_CR1_ADC4USRC_1 ((uint32_t)0x04000000) /*!< ADC Trigger 4 update source bit 1 */ -#define HRTIM_CR1_ADC4USRC_2 ((uint32_t)0x0800000) /*!< ADC Trigger 4 update source bit 2 */ - -/**** Bit definition for Common HRTIM Timer control register 2 ****************/ -#define HRTIM_CR2_MSWU ((uint32_t)0x00000001) /*!< Master software update */ -#define HRTIM_CR2_TASWU ((uint32_t)0x00000002) /*!< Timer A software update */ -#define HRTIM_CR2_TBSWU ((uint32_t)0x00000004) /*!< Timer B software update */ -#define HRTIM_CR2_TCSWU ((uint32_t)0x00000008) /*!< Timer C software update */ -#define HRTIM_CR2_TDSWU ((uint32_t)0x00000010) /*!< Timer D software update */ -#define HRTIM_CR2_TESWU ((uint32_t)0x00000020) /*!< Timer E software update */ -#define HRTIM_CR2_MRST ((uint32_t)0x00000100) /*!< Master count software reset */ -#define HRTIM_CR2_TARST ((uint32_t)0x00000200) /*!< Timer A count software reset */ -#define HRTIM_CR2_TBRST ((uint32_t)0x00000400) /*!< Timer B count software reset */ -#define HRTIM_CR2_TCRST ((uint32_t)0x00000800) /*!< Timer C count software reset */ -#define HRTIM_CR2_TDRST ((uint32_t)0x00001000) /*!< Timer D count software reset */ -#define HRTIM_CR2_TERST ((uint32_t)0x00002000) /*!< Timer E count software reset */ - -/**** Bit definition for Common HRTIM Timer interrupt status register *********/ -#define HRTIM_ISR_FLT1 ((uint32_t)0x00000001) /*!< Fault 1 interrupt flag */ -#define HRTIM_ISR_FLT2 ((uint32_t)0x00000002) /*!< Fault 2 interrupt flag */ -#define HRTIM_ISR_FLT3 ((uint32_t)0x00000004) /*!< Fault 3 interrupt flag */ -#define HRTIM_ISR_FLT4 ((uint32_t)0x00000008) /*!< Fault 4 interrupt flag */ -#define HRTIM_ISR_FLT5 ((uint32_t)0x00000010) /*!< Fault 5 interrupt flag */ -#define HRTIM_ISR_SYSFLT ((uint32_t)0x00000020) /*!< System Fault interrupt flag */ -#define HRTIM_ISR_DLLRDY ((uint32_t)0x00010000) /*!< DLL ready interrupt flag */ -#define HRTIM_ISR_BMPER ((uint32_t)0x00020000) /*!< Burst mode period interrupt flag */ - -/**** Bit definition for Common HRTIM Timer interrupt clear register **********/ -#define HRTIM_ICR_FLT1C ((uint32_t)0x00000001) /*!< Fault 1 interrupt flag clear */ -#define HRTIM_ICR_FLT2C ((uint32_t)0x00000002) /*!< Fault 2 interrupt flag clear */ -#define HRTIM_ICR_FLT3C ((uint32_t)0x00000004) /*!< Fault 3 interrupt flag clear */ -#define HRTIM_ICR_FLT4C ((uint32_t)0x00000008) /*!< Fault 4 interrupt flag clear */ -#define HRTIM_ICR_FLT5C ((uint32_t)0x00000010) /*!< Fault 5 interrupt flag clear */ -#define HRTIM_ICR_SYSFLTC ((uint32_t)0x00000020) /*!< System Fault interrupt flag clear */ -#define HRTIM_ICR_DLLRDYC ((uint32_t)0x00010000) /*!< DLL ready interrupt flag clear */ -#define HRTIM_ICR_BMPERC ((uint32_t)0x00020000) /*!< Burst mode period interrupt flag clear */ - -/**** Bit definition for Common HRTIM Timer interrupt enable register *********/ -#define HRTIM_IER_FLT1 ((uint32_t)0x00000001) /*!< Fault 1 interrupt enable */ -#define HRTIM_IER_FLT2 ((uint32_t)0x00000002) /*!< Fault 2 interrupt enable */ -#define HRTIM_IER_FLT3 ((uint32_t)0x00000004) /*!< Fault 3 interrupt enable */ -#define HRTIM_IER_FLT4 ((uint32_t)0x00000008) /*!< Fault 4 interrupt enable */ -#define HRTIM_IER_FLT5 ((uint32_t)0x00000010) /*!< Fault 5 interrupt enable */ -#define HRTIM_IER_SYSFLT ((uint32_t)0x00000020) /*!< System Fault interrupt enable */ -#define HRTIM_IER_DLLRDY ((uint32_t)0x00010000) /*!< DLL ready interrupt enable */ -#define HRTIM_IER_BMPER ((uint32_t)0x00020000) /*!< Burst mode period interrupt enable */ - -/**** Bit definition for Common HRTIM Timer output enable register ************/ -#define HRTIM_OENR_TA1OEN ((uint32_t)0x00000001) /*!< Timer A Output 1 enable */ -#define HRTIM_OENR_TA2OEN ((uint32_t)0x00000002) /*!< Timer A Output 2 enable */ -#define HRTIM_OENR_TB1OEN ((uint32_t)0x00000004) /*!< Timer B Output 1 enable */ -#define HRTIM_OENR_TB2OEN ((uint32_t)0x00000008) /*!< Timer B Output 2 enable */ -#define HRTIM_OENR_TC1OEN ((uint32_t)0x00000010) /*!< Timer C Output 1 enable */ -#define HRTIM_OENR_TC2OEN ((uint32_t)0x00000020) /*!< Timer C Output 2 enable */ -#define HRTIM_OENR_TD1OEN ((uint32_t)0x00000040) /*!< Timer D Output 1 enable */ -#define HRTIM_OENR_TD2OEN ((uint32_t)0x00000080) /*!< Timer D Output 2 enable */ -#define HRTIM_OENR_TE1OEN ((uint32_t)0x00000100) /*!< Timer E Output 1 enable */ -#define HRTIM_OENR_TE2OEN ((uint32_t)0x00000200) /*!< Timer E Output 2 enable */ - -/**** Bit definition for Common HRTIM Timer output disable register ***********/ -#define HRTIM_ODISR_TA1ODIS ((uint32_t)0x00000001) /*!< Timer A Output 1 disable */ -#define HRTIM_ODISR_TA2ODIS ((uint32_t)0x00000002) /*!< Timer A Output 2 disable */ -#define HRTIM_ODISR_TB1ODIS ((uint32_t)0x00000004) /*!< Timer B Output 1 disable */ -#define HRTIM_ODISR_TB2ODIS ((uint32_t)0x00000008) /*!< Timer B Output 2 disable */ -#define HRTIM_ODISR_TC1ODIS ((uint32_t)0x00000010) /*!< Timer C Output 1 disable */ -#define HRTIM_ODISR_TC2ODIS ((uint32_t)0x00000020) /*!< Timer C Output 2 disable */ -#define HRTIM_ODISR_TD1ODIS ((uint32_t)0x00000040) /*!< Timer D Output 1 disable */ -#define HRTIM_ODISR_TD2ODIS ((uint32_t)0x00000080) /*!< Timer D Output 2 disable */ -#define HRTIM_ODISR_TE1ODIS ((uint32_t)0x00000100) /*!< Timer E Output 1 disable */ -#define HRTIM_ODISR_TE2ODIS ((uint32_t)0x00000200) /*!< Timer E Output 2 disable */ - -/**** Bit definition for Common HRTIM Timer output disable status register *****/ -#define HRTIM_ODSR_TA1ODS ((uint32_t)0x00000001) /*!< Timer A Output 1 disable status */ -#define HRTIM_ODSR_TA2ODS ((uint32_t)0x00000002) /*!< Timer A Output 2 disable status */ -#define HRTIM_ODSR_TB1ODS ((uint32_t)0x00000004) /*!< Timer B Output 1 disable status */ -#define HRTIM_ODSR_TB2ODS ((uint32_t)0x00000008) /*!< Timer B Output 2 disable status */ -#define HRTIM_ODSR_TC1ODS ((uint32_t)0x00000010) /*!< Timer C Output 1 disable status */ -#define HRTIM_ODSR_TC2ODS ((uint32_t)0x00000020) /*!< Timer C Output 2 disable status */ -#define HRTIM_ODSR_TD1ODS ((uint32_t)0x00000040) /*!< Timer D Output 1 disable status */ -#define HRTIM_ODSR_TD2ODS ((uint32_t)0x00000080) /*!< Timer D Output 2 disable status */ -#define HRTIM_ODSR_TE1ODS ((uint32_t)0x00000100) /*!< Timer E Output 1 disable status */ -#define HRTIM_ODSR_TE2ODS ((uint32_t)0x00000200) /*!< Timer E Output 2 disable status */ - -/**** Bit definition for Common HRTIM Timer Burst mode control register ********/ -#define HRTIM_BMCR_BME ((uint32_t)0x00000001) /*!< Burst mode enable */ -#define HRTIM_BMCR_BMOM ((uint32_t)0x00000002) /*!< Burst mode operating mode */ -#define HRTIM_BMCR_BMCLK ((uint32_t)0x0000003C) /*!< Burst mode clock source */ -#define HRTIM_BMCR_BMCLK_0 ((uint32_t)0x00000004) /*!< Burst mode clock source bit 0 */ -#define HRTIM_BMCR_BMCLK_1 ((uint32_t)0x00000008) /*!< Burst mode clock source bit 1 */ -#define HRTIM_BMCR_BMCLK_2 ((uint32_t)0x00000010) /*!< Burst mode clock source bit 2 */ -#define HRTIM_BMCR_BMCLK_3 ((uint32_t)0x00000020) /*!< Burst mode clock source bit 3 */ -#define HRTIM_BMCR_BMPSC ((uint32_t)0x000003C0) /*!< Burst mode prescaler */ -#define HRTIM_BMCR_BMPSC_0 ((uint32_t)0x00000040) /*!< Burst mode prescaler bit 0 */ -#define HRTIM_BMCR_BMPSC_1 ((uint32_t)0x00000080) /*!< Burst mode prescaler bit 1 */ -#define HRTIM_BMCR_BMPSC_2 ((uint32_t)0x00000100) /*!< Burst mode prescaler bit 2 */ -#define HRTIM_BMCR_BMPSC_3 ((uint32_t)0x00000200) /*!< Burst mode prescaler bit 3 */ -#define HRTIM_BMCR_BMPREN ((uint32_t)0x00000400) /*!< Burst mode Preload bit */ -#define HRTIM_BMCR_MTBM ((uint32_t)0x00010000) /*!< Master Timer Burst mode */ -#define HRTIM_BMCR_TABM ((uint32_t)0x00020000) /*!< Timer A Burst mode */ -#define HRTIM_BMCR_TBBM ((uint32_t)0x00040000) /*!< Timer B Burst mode */ -#define HRTIM_BMCR_TCBM ((uint32_t)0x00080000) /*!< Timer C Burst mode */ -#define HRTIM_BMCR_TDBM ((uint32_t)0x00100000) /*!< Timer D Burst mode */ -#define HRTIM_BMCR_TEBM ((uint32_t)0x00200000) /*!< Timer E Burst mode */ -#define HRTIM_BMCR_BMSTAT ((uint32_t)0x80000000) /*!< Burst mode status */ - -/**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/ -#define HRTIM_BMTRGR_SW ((uint32_t)0x00000001) /*!< Software start */ -#define HRTIM_BMTRGR_MSTRST ((uint32_t)0x00000002) /*!< Master reset */ -#define HRTIM_BMTRGR_MSTREP ((uint32_t)0x00000004) /*!< Master repetition */ -#define HRTIM_BMTRGR_MSTCMP1 ((uint32_t)0x00000008) /*!< Master compare 1 */ -#define HRTIM_BMTRGR_MSTCMP2 ((uint32_t)0x00000010) /*!< Master compare 2 */ -#define HRTIM_BMTRGR_MSTCMP3 ((uint32_t)0x00000020) /*!< Master compare 3 */ -#define HRTIM_BMTRGR_MSTCMP4 ((uint32_t)0x00000040) /*!< Master compare 4 */ -#define HRTIM_BMTRGR_TARST ((uint32_t)0x00000080) /*!< Timer A reset */ -#define HRTIM_BMTRGR_TAREP ((uint32_t)0x00000100) /*!< Timer A repetition */ -#define HRTIM_BMTRGR_TACMP1 ((uint32_t)0x00000200) /*!< Timer A compare 1 */ -#define HRTIM_BMTRGR_TACMP2 ((uint32_t)0x00000400) /*!< Timer A compare 2 */ -#define HRTIM_BMTRGR_TBRST ((uint32_t)0x00000800) /*!< Timer B reset */ -#define HRTIM_BMTRGR_TBREP ((uint32_t)0x00001000) /*!< Timer B repetition */ -#define HRTIM_BMTRGR_TBCMP1 ((uint32_t)0x00002000) /*!< Timer B compare 1 */ -#define HRTIM_BMTRGR_TBCMP2 ((uint32_t)0x00004000) /*!< Timer B compare 2 */ -#define HRTIM_BMTRGR_TCRST ((uint32_t)0x00008000) /*!< Timer C reset */ -#define HRTIM_BMTRGR_TCREP ((uint32_t)0x00010000) /*!< Timer C repetition */ -#define HRTIM_BMTRGR_TCCMP1 ((uint32_t)0x00020000) /*!< Timer C compare 1 */ -#define HRTIM_BMTRGR_TCCMP2 ((uint32_t)0x00040000) /*!< Timer C compare 2 */ -#define HRTIM_BMTRGR_TDRST ((uint32_t)0x00080000) /*!< Timer D reset */ -#define HRTIM_BMTRGR_TDREP ((uint32_t)0x00100000) /*!< Timer D repetition */ -#define HRTIM_BMTRGR_TDCMP1 ((uint32_t)0x00200000) /*!< Timer D compare 1 */ -#define HRTIM_BMTRGR_TDCMP2 ((uint32_t)0x00400000) /*!< Timer D compare 2 */ -#define HRTIM_BMTRGR_TERST ((uint32_t)0x00800000) /*!< Timer E reset */ -#define HRTIM_BMTRGR_TEREP ((uint32_t)0x01000000) /*!< Timer E repetition */ -#define HRTIM_BMTRGR_TECMP1 ((uint32_t)0x02000000) /*!< Timer E compare 1 */ -#define HRTIM_BMTRGR_TECMP2 ((uint32_t)0x04000000) /*!< Timer E compare 2 */ -#define HRTIM_BMTRGR_TAEEV7 ((uint32_t)0x08000000) /*!< Timer A period following External Event7 */ -#define HRTIM_BMTRGR_TDEEV8 ((uint32_t)0x10000000) /*!< Timer D period following External Event8 */ -#define HRTIM_BMTRGR_EEV7 ((uint32_t)0x20000000) /*!< External Event 7 */ -#define HRTIM_BMTRGR_EEV8 ((uint32_t)0x40000000) /*!< External Event 8 */ -#define HRTIM_BMTRGR_OCHPEV ((uint32_t)0x80000000) /*!< on-chip Event */ - -/******************* Bit definition for HRTIM_BMCMPR register ***************/ -#define HRTIM_BMCMPR_BMCMPR ((uint32_t)0x0000FFFF) /*!<!<Burst Compare Value */ - -/******************* Bit definition for HRTIM_BMPER register ****************/ -#define HRTIM_BMPER_BMPER ((uint32_t)0x0000FFFF) /*!<!<Burst period Value */ - -/******************* Bit definition for HRTIM_EECR1 register ****************/ -#define HRTIM_EECR1_EE1SRC ((uint32_t)0x00000003) /*!< External event 1 source */ -#define HRTIM_EECR1_EE1SRC_0 ((uint32_t)0x00000001) /*!< External event 1 source bit 0 */ -#define HRTIM_EECR1_EE1SRC_1 ((uint32_t)0x00000002) /*!< External event 1 source bit 1 */ -#define HRTIM_EECR1_EE1POL ((uint32_t)0x00000004) /*!< External event 1 Polarity */ -#define HRTIM_EECR1_EE1SNS ((uint32_t)0x00000018) /*!< External event 1 sensitivity */ -#define HRTIM_EECR1_EE1SNS_0 ((uint32_t)0x00000008) /*!< External event 1 sensitivity bit 0 */ -#define HRTIM_EECR1_EE1SNS_1 ((uint32_t)0x00000010) /*!< External event 1 sensitivity bit 1 */ -#define HRTIM_EECR1_EE1FAST ((uint32_t)0x00000020) /*!< External event 1 Fast mode */ - -#define HRTIM_EECR1_EE2SRC ((uint32_t)0x000000C0) /*!< External event 2 source */ -#define HRTIM_EECR1_EE2SRC_0 ((uint32_t)0x00000040) /*!< External event 2 source bit 0 */ -#define HRTIM_EECR1_EE2SRC_1 ((uint32_t)0x00000080) /*!< External event 2 source bit 1 */ -#define HRTIM_EECR1_EE2POL ((uint32_t)0x00000100) /*!< External event 2 Polarity */ -#define HRTIM_EECR1_EE2SNS ((uint32_t)0x00000600) /*!< External event 2 sensitivity */ -#define HRTIM_EECR1_EE2SNS_0 ((uint32_t)0x00000200) /*!< External event 2 sensitivity bit 0 */ -#define HRTIM_EECR1_EE2SNS_1 ((uint32_t)0x00000400) /*!< External event 2 sensitivity bit 1 */ -#define HRTIM_EECR1_EE2FAST ((uint32_t)0x00000800) /*!< External event 2 Fast mode */ - -#define HRTIM_EECR1_EE3SRC ((uint32_t)0x00003000) /*!< External event 3 source */ -#define HRTIM_EECR1_EE3SRC_0 ((uint32_t)0x00001000) /*!< External event 3 source bit 0 */ -#define HRTIM_EECR1_EE3SRC_1 ((uint32_t)0x00002000) /*!< External event 3 source bit 1 */ -#define HRTIM_EECR1_EE3POL ((uint32_t)0x00004000) /*!< External event 3 Polarity */ -#define HRTIM_EECR1_EE3SNS ((uint32_t)0x00018000) /*!< External event 3 sensitivity */ -#define HRTIM_EECR1_EE3SNS_0 ((uint32_t)0x00008000) /*!< External event 3 sensitivity bit 0 */ -#define HRTIM_EECR1_EE3SNS_1 ((uint32_t)0x00010000) /*!< External event 3 sensitivity bit 1 */ -#define HRTIM_EECR1_EE3FAST ((uint32_t)0x00020000) /*!< External event 3 Fast mode */ - -#define HRTIM_EECR1_EE4SRC ((uint32_t)0x000C0000) /*!< External event 4 source */ -#define HRTIM_EECR1_EE4SRC_0 ((uint32_t)0x00040000) /*!< External event 4 source bit 0 */ -#define HRTIM_EECR1_EE4SRC_1 ((uint32_t)0x00080000) /*!< External event 4 source bit 1 */ -#define HRTIM_EECR1_EE4POL ((uint32_t)0x00100000) /*!< External event 4 Polarity */ -#define HRTIM_EECR1_EE4SNS ((uint32_t)0x00600000) /*!< External event 4 sensitivity */ -#define HRTIM_EECR1_EE4SNS_0 ((uint32_t)0x00200000) /*!< External event 4 sensitivity bit 0 */ -#define HRTIM_EECR1_EE4SNS_1 ((uint32_t)0x00400000) /*!< External event 4 sensitivity bit 1 */ -#define HRTIM_EECR1_EE4FAST ((uint32_t)0x00800000) /*!< External event 4 Fast mode */ - -#define HRTIM_EECR1_EE5SRC ((uint32_t)0x03000000) /*!< External event 5 source */ -#define HRTIM_EECR1_EE5SRC_0 ((uint32_t)0x01000000) /*!< External event 5 source bit 0 */ -#define HRTIM_EECR1_EE5SRC_1 ((uint32_t)0x02000000) /*!< External event 5 source bit 1 */ -#define HRTIM_EECR1_EE5POL ((uint32_t)0x04000000) /*!< External event 5 Polarity */ -#define HRTIM_EECR1_EE5SNS ((uint32_t)0x18000000) /*!< External event 5 sensitivity */ -#define HRTIM_EECR1_EE5SNS_0 ((uint32_t)0x08000000) /*!< External event 5 sensitivity bit 0 */ -#define HRTIM_EECR1_EE5SNS_1 ((uint32_t)0x10000000) /*!< External event 5 sensitivity bit 1 */ -#define HRTIM_EECR1_EE5FAST ((uint32_t)0x20000000) /*!< External event 5 Fast mode */ - -/******************* Bit definition for HRTIM_EECR2 register ****************/ -#define HRTIM_EECR2_EE6SRC ((uint32_t)0x00000003) /*!< External event 6 source */ -#define HRTIM_EECR2_EE6SRC_0 ((uint32_t)0x00000001) /*!< External event 6 source bit 0 */ -#define HRTIM_EECR2_EE6SRC_1 ((uint32_t)0x00000002) /*!< External event 6 source bit 1 */ -#define HRTIM_EECR2_EE6POL ((uint32_t)0x00000004) /*!< External event 6 Polarity */ -#define HRTIM_EECR2_EE6SNS ((uint32_t)0x00000018) /*!< External event 6 sensitivity */ -#define HRTIM_EECR2_EE6SNS_0 ((uint32_t)0x00000008) /*!< External event 6 sensitivity bit 0 */ -#define HRTIM_EECR2_EE6SNS_1 ((uint32_t)0x00000010) /*!< External event 6 sensitivity bit 1 */ - -#define HRTIM_EECR2_EE7SRC ((uint32_t)0x000000C0) /*!< External event 7 source */ -#define HRTIM_EECR2_EE7SRC_0 ((uint32_t)0x00000040) /*!< External event 7 source bit 0 */ -#define HRTIM_EECR2_EE7SRC_1 ((uint32_t)0x00000080) /*!< External event 7 source bit 1 */ -#define HRTIM_EECR2_EE7POL ((uint32_t)0x00000100) /*!< External event 7 Polarity */ -#define HRTIM_EECR2_EE7SNS ((uint32_t)0x00000600) /*!< External event 7 sensitivity */ -#define HRTIM_EECR2_EE7SNS_0 ((uint32_t)0x00000200) /*!< External event 7 sensitivity bit 0 */ -#define HRTIM_EECR2_EE7SNS_1 ((uint32_t)0x00000400) /*!< External event 7 sensitivity bit 1 */ - -#define HRTIM_EECR2_EE8SRC ((uint32_t)0x00003000) /*!< External event 8 source */ -#define HRTIM_EECR2_EE8SRC_0 ((uint32_t)0x00001000) /*!< External event 8 source bit 0 */ -#define HRTIM_EECR2_EE8SRC_1 ((uint32_t)0x00002000) /*!< External event 8 source bit 1 */ -#define HRTIM_EECR2_EE8POL ((uint32_t)0x00004000) /*!< External event 8 Polarity */ -#define HRTIM_EECR2_EE8SNS ((uint32_t)0x00018000) /*!< External event 8 sensitivity */ -#define HRTIM_EECR2_EE8SNS_0 ((uint32_t)0x00008000) /*!< External event 8 sensitivity bit 0 */ -#define HRTIM_EECR2_EE8SNS_1 ((uint32_t)0x00010000) /*!< External event 8 sensitivity bit 1 */ - -#define HRTIM_EECR2_EE9SRC ((uint32_t)0x000C0000) /*!< External event 9 source */ -#define HRTIM_EECR2_EE9SRC_0 ((uint32_t)0x00040000) /*!< External event 9 source bit 0 */ -#define HRTIM_EECR2_EE9SRC_1 ((uint32_t)0x00080000) /*!< External event 9 source bit 1 */ -#define HRTIM_EECR2_EE9POL ((uint32_t)0x00100000) /*!< External event 9 Polarity */ -#define HRTIM_EECR2_EE9SNS ((uint32_t)0x00600000) /*!< External event 9 sensitivity */ -#define HRTIM_EECR2_EE9SNS_0 ((uint32_t)0x00200000) /*!< External event 9 sensitivity bit 0 */ -#define HRTIM_EECR2_EE9SNS_1 ((uint32_t)0x00400000) /*!< External event 9 sensitivity bit 1 */ - -#define HRTIM_EECR2_EE10SRC ((uint32_t)0x03000000) /*!< External event 10 source */ -#define HRTIM_EECR2_EE10SRC_0 ((uint32_t)0x01000000) /*!< External event 10 source bit 0 */ -#define HRTIM_EECR2_EE10SRC_1 ((uint32_t)0x02000000) /*!< External event 10 source bit 1 */ -#define HRTIM_EECR2_EE10POL ((uint32_t)0x04000000) /*!< External event 10 Polarity */ -#define HRTIM_EECR2_EE10SNS ((uint32_t)0x18000000) /*!< External event 10 sensitivity */ -#define HRTIM_EECR2_EE10SNS_0 ((uint32_t)0x08000000) /*!< External event 10 sensitivity bit 0 */ -#define HRTIM_EECR2_EE10SNS_1 ((uint32_t)0x10000000) /*!< External event 10 sensitivity bit 1 */ - -/******************* Bit definition for HRTIM_EECR3 register ****************/ -#define HRTIM_EECR3_EE6F ((uint32_t)0x0000000F) /*!< External event 6 filter */ -#define HRTIM_EECR3_EE6F_0 ((uint32_t)0x00000001) /*!< External event 6 filter bit 0 */ -#define HRTIM_EECR3_EE6F_1 ((uint32_t)0x00000002) /*!< External event 6 filter bit 1 */ -#define HRTIM_EECR3_EE6F_2 ((uint32_t)0x00000004) /*!< External event 6 filter bit 2 */ -#define HRTIM_EECR3_EE6F_3 ((uint32_t)0x00000008) /*!< External event 6 filter bit 3 */ -#define HRTIM_EECR3_EE7F ((uint32_t)0x000003C0) /*!< External event 7 filter */ -#define HRTIM_EECR3_EE7F_0 ((uint32_t)0x00000040) /*!< External event 7 filter bit 0 */ -#define HRTIM_EECR3_EE7F_1 ((uint32_t)0x00000080) /*!< External event 7 filter bit 1 */ -#define HRTIM_EECR3_EE7F_2 ((uint32_t)0x00000100) /*!< External event 7 filter bit 2 */ -#define HRTIM_EECR3_EE7F_3 ((uint32_t)0x00000200) /*!< External event 7 filter bit 3 */ -#define HRTIM_EECR3_EE8F ((uint32_t)0x0000F000) /*!< External event 8 filter */ -#define HRTIM_EECR3_EE8F_0 ((uint32_t)0x00001000) /*!< External event 8 filter bit 0 */ -#define HRTIM_EECR3_EE8F_1 ((uint32_t)0x00002000) /*!< External event 8 filter bit 1 */ -#define HRTIM_EECR3_EE8F_2 ((uint32_t)0x00004000) /*!< External event 8 filter bit 2 */ -#define HRTIM_EECR3_EE8F_3 ((uint32_t)0x00008000) /*!< External event 8 filter bit 3 */ -#define HRTIM_EECR3_EE9F ((uint32_t)0x003C0000) /*!< External event 9 filter */ -#define HRTIM_EECR3_EE9F_0 ((uint32_t)0x00040000) /*!< External event 9 filter bit 0 */ -#define HRTIM_EECR3_EE9F_1 ((uint32_t)0x00080000) /*!< External event 9 filter bit 1 */ -#define HRTIM_EECR3_EE9F_2 ((uint32_t)0x00100000) /*!< External event 9 filter bit 2 */ -#define HRTIM_EECR3_EE9F_3 ((uint32_t)0x00200000) /*!< External event 9 filter bit 3 */ -#define HRTIM_EECR3_EE10F ((uint32_t)0x0F000000) /*!< External event 10 filter */ -#define HRTIM_EECR3_EE10F_0 ((uint32_t)0x01000000) /*!< External event 10 filter bit 0 */ -#define HRTIM_EECR3_EE10F_1 ((uint32_t)0x02000000) /*!< External event 10 filter bit 1 */ -#define HRTIM_EECR3_EE10F_2 ((uint32_t)0x04000000) /*!< External event 10 filter bit 2 */ -#define HRTIM_EECR3_EE10F_3 ((uint32_t)0x08000000) /*!< External event 10 filter bit 3 */ -#define HRTIM_EECR3_EEVSD ((uint32_t)0xC0000000) /*!< External event sampling clock division */ -#define HRTIM_EECR3_EEVSD_0 ((uint32_t)0x40000000) /*!< External event sampling clock division bit 0 */ -#define HRTIM_EECR3_EEVSD_1 ((uint32_t)0x80000000) /*!< External event sampling clock division bit 1 */ - -/******************* Bit definition for HRTIM_ADC1R register ****************/ -#define HRTIM_ADC1R_AD1MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 1 on master compare 1 */ -#define HRTIM_ADC1R_AD1MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 1 on master compare 2 */ -#define HRTIM_ADC1R_AD1MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 1 on master compare 3 */ -#define HRTIM_ADC1R_AD1MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 1 on master compare 4 */ -#define HRTIM_ADC1R_AD1MPER ((uint32_t)0x00000010) /*!< ADC Trigger 1 on master period */ -#define HRTIM_ADC1R_AD1EEV1 ((uint32_t)0x00000020) /*!< ADC Trigger 1 on external event 1 */ -#define HRTIM_ADC1R_AD1EEV2 ((uint32_t)0x00000040) /*!< ADC Trigger 1 on external event 2 */ -#define HRTIM_ADC1R_AD1EEV3 ((uint32_t)0x00000080) /*!< ADC Trigger 1 on external event 3 */ -#define HRTIM_ADC1R_AD1EEV4 ((uint32_t)0x00000100) /*!< ADC Trigger 1 on external event 4 */ -#define HRTIM_ADC1R_AD1EEV5 ((uint32_t)0x00000200) /*!< ADC Trigger 1 on external event 5 */ -#define HRTIM_ADC1R_AD1TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 1 on Timer A compare 2 */ -#define HRTIM_ADC1R_AD1TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 1 on Timer A compare 3 */ -#define HRTIM_ADC1R_AD1TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 1 on Timer A compare 4 */ -#define HRTIM_ADC1R_AD1TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 1 on Timer A period */ -#define HRTIM_ADC1R_AD1TARST ((uint32_t)0x00004000) /*!< ADC Trigger 1 on Timer A reset */ -#define HRTIM_ADC1R_AD1TBC2 ((uint32_t)0x00008000) /*!< ADC Trigger 1 on Timer B compare 2 */ -#define HRTIM_ADC1R_AD1TBC3 ((uint32_t)0x00010000) /*!< ADC Trigger 1 on Timer B compare 3 */ -#define HRTIM_ADC1R_AD1TBC4 ((uint32_t)0x00020000) /*!< ADC Trigger 1 on Timer B compare 4 */ -#define HRTIM_ADC1R_AD1TBPER ((uint32_t)0x00040000) /*!< ADC Trigger 1 on Timer B period */ -#define HRTIM_ADC1R_AD1TBRST ((uint32_t)0x00080000) /*!< ADC Trigger 1 on Timer B reset */ -#define HRTIM_ADC1R_AD1TCC2 ((uint32_t)0x00100000) /*!< ADC Trigger 1 on Timer C compare 2 */ -#define HRTIM_ADC1R_AD1TCC3 ((uint32_t)0x00200000) /*!< ADC Trigger 1 on Timer C compare 3 */ -#define HRTIM_ADC1R_AD1TCC4 ((uint32_t)0x00400000) /*!< ADC Trigger 1 on Timer C compare 4 */ -#define HRTIM_ADC1R_AD1TCPER ((uint32_t)0x00800000) /*!< ADC Trigger 1 on Timer C period */ -#define HRTIM_ADC1R_AD1TDC2 ((uint32_t)0x01000000) /*!< ADC Trigger 1 on Timer D compare 2 */ -#define HRTIM_ADC1R_AD1TDC3 ((uint32_t)0x02000000) /*!< ADC Trigger 1 on Timer D compare 3 */ -#define HRTIM_ADC1R_AD1TDC4 ((uint32_t)0x04000000) /*!< ADC Trigger 1 on Timer D compare 4 */ -#define HRTIM_ADC1R_AD1TDPER ((uint32_t)0x08000000) /*!< ADC Trigger 1 on Timer D period */ -#define HRTIM_ADC1R_AD1TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 1 on Timer E compare 2 */ -#define HRTIM_ADC1R_AD1TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 1 on Timer E compare 3 */ -#define HRTIM_ADC1R_AD1TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 1 on Timer E compare 4 */ -#define HRTIM_ADC1R_AD1TEPER ((uint32_t)0x80000000) /*!< ADC Trigger 1 on Timer E period */ - -/******************* Bit definition for HRTIM_ADC2R register ****************/ -#define HRTIM_ADC2R_AD2MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 2 on master compare 1 */ -#define HRTIM_ADC2R_AD2MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 2 on master compare 2 */ -#define HRTIM_ADC2R_AD2MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 2 on master compare 3 */ -#define HRTIM_ADC2R_AD2MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 2 on master compare 4 */ -#define HRTIM_ADC2R_AD2MPER ((uint32_t)0x00000010) /*!< ADC Trigger 2 on master period */ -#define HRTIM_ADC2R_AD2EEV6 ((uint32_t)0x00000020) /*!< ADC Trigger 2 on external event 6 */ -#define HRTIM_ADC2R_AD2EEV7 ((uint32_t)0x00000040) /*!< ADC Trigger 2 on external event 7 */ -#define HRTIM_ADC2R_AD2EEV8 ((uint32_t)0x00000080) /*!< ADC Trigger 2 on external event 8 */ -#define HRTIM_ADC2R_AD2EEV9 ((uint32_t)0x00000100) /*!< ADC Trigger 2 on external event 9 */ -#define HRTIM_ADC2R_AD2EEV10 ((uint32_t)0x00000200) /*!< ADC Trigger 2 on external event 10 */ -#define HRTIM_ADC2R_AD2TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 2 on Timer A compare 2 */ -#define HRTIM_ADC2R_AD2TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 2 on Timer A compare 3 */ -#define HRTIM_ADC2R_AD2TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 2 on Timer A compare 4*/ -#define HRTIM_ADC2R_AD2TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 2 on Timer A period */ -#define HRTIM_ADC2R_AD2TBC2 ((uint32_t)0x00004000) /*!< ADC Trigger 2 on Timer B compare 2 */ -#define HRTIM_ADC2R_AD2TBC3 ((uint32_t)0x00008000) /*!< ADC Trigger 2 on Timer B compare 3 */ -#define HRTIM_ADC2R_AD2TBC4 ((uint32_t)0x00010000) /*!< ADC Trigger 2 on Timer B compare 4 */ -#define HRTIM_ADC2R_AD2TBPER ((uint32_t)0x00020000) /*!< ADC Trigger 2 on Timer B period */ -#define HRTIM_ADC2R_AD2TCC2 ((uint32_t)0x00040000) /*!< ADC Trigger 2 on Timer C compare 2 */ -#define HRTIM_ADC2R_AD2TCC3 ((uint32_t)0x00080000) /*!< ADC Trigger 2 on Timer C compare 3 */ -#define HRTIM_ADC2R_AD2TCC4 ((uint32_t)0x00100000) /*!< ADC Trigger 2 on Timer C compare 4 */ -#define HRTIM_ADC2R_AD2TCPER ((uint32_t)0x00200000) /*!< ADC Trigger 2 on Timer C period */ -#define HRTIM_ADC2R_AD2TCRST ((uint32_t)0x00400000) /*!< ADC Trigger 2 on Timer C reset */ -#define HRTIM_ADC2R_AD2TDC2 ((uint32_t)0x00800000) /*!< ADC Trigger 2 on Timer D compare 2 */ -#define HRTIM_ADC2R_AD2TDC3 ((uint32_t)0x01000000) /*!< ADC Trigger 2 on Timer D compare 3 */ -#define HRTIM_ADC2R_AD2TDC4 ((uint32_t)0x02000000) /*!< ADC Trigger 2 on Timer D compare 4*/ -#define HRTIM_ADC2R_AD2TDPER ((uint32_t)0x04000000) /*!< ADC Trigger 2 on Timer D period */ -#define HRTIM_ADC2R_AD2TDRST ((uint32_t)0x08000000) /*!< ADC Trigger 2 on Timer D reset */ -#define HRTIM_ADC2R_AD2TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 2 on Timer E compare 2 */ -#define HRTIM_ADC2R_AD2TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 2 on Timer E compare 3 */ -#define HRTIM_ADC2R_AD2TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 2 on Timer E compare 4 */ -#define HRTIM_ADC2R_AD2TERST ((uint32_t)0x80000000) /*!< ADC Trigger 2 on Timer E reset */ - -/******************* Bit definition for HRTIM_ADC3R register ****************/ -#define HRTIM_ADC3R_AD3MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 3 on master compare 1 */ -#define HRTIM_ADC3R_AD3MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 3 on master compare 2 */ -#define HRTIM_ADC3R_AD3MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 3 on master compare 3 */ -#define HRTIM_ADC3R_AD3MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 3 on master compare 4 */ -#define HRTIM_ADC3R_AD3MPER ((uint32_t)0x00000010) /*!< ADC Trigger 3 on master period */ -#define HRTIM_ADC3R_AD3EEV1 ((uint32_t)0x00000020) /*!< ADC Trigger 3 on external event 1 */ -#define HRTIM_ADC3R_AD3EEV2 ((uint32_t)0x00000040) /*!< ADC Trigger 3 on external event 2 */ -#define HRTIM_ADC3R_AD3EEV3 ((uint32_t)0x00000080) /*!< ADC Trigger 3 on external event 3 */ -#define HRTIM_ADC3R_AD3EEV4 ((uint32_t)0x00000100) /*!< ADC Trigger 3 on external event 4 */ -#define HRTIM_ADC3R_AD3EEV5 ((uint32_t)0x00000200) /*!< ADC Trigger 3 on external event 5 */ -#define HRTIM_ADC3R_AD3TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 3 on Timer A compare 2 */ -#define HRTIM_ADC3R_AD3TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 3 on Timer A compare 3 */ -#define HRTIM_ADC3R_AD3TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 3 on Timer A compare 4 */ -#define HRTIM_ADC3R_AD3TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 3 on Timer A period */ -#define HRTIM_ADC3R_AD3TARST ((uint32_t)0x00004000) /*!< ADC Trigger 3 on Timer A reset */ -#define HRTIM_ADC3R_AD3TBC2 ((uint32_t)0x00008000) /*!< ADC Trigger 3 on Timer B compare 2 */ -#define HRTIM_ADC3R_AD3TBC3 ((uint32_t)0x00010000) /*!< ADC Trigger 3 on Timer B compare 3 */ -#define HRTIM_ADC3R_AD3TBC4 ((uint32_t)0x00020000) /*!< ADC Trigger 3 on Timer B compare 4 */ -#define HRTIM_ADC3R_AD3TBPER ((uint32_t)0x00040000) /*!< ADC Trigger 3 on Timer B period */ -#define HRTIM_ADC3R_AD3TBRST ((uint32_t)0x00080000) /*!< ADC Trigger 3 on Timer B reset */ -#define HRTIM_ADC3R_AD3TCC2 ((uint32_t)0x00100000) /*!< ADC Trigger 3 on Timer C compare 2 */ -#define HRTIM_ADC3R_AD3TCC3 ((uint32_t)0x00200000) /*!< ADC Trigger 3 on Timer C compare 3 */ -#define HRTIM_ADC3R_AD3TCC4 ((uint32_t)0x00400000) /*!< ADC Trigger 3 on Timer C compare 4 */ -#define HRTIM_ADC3R_AD3TCPER ((uint32_t)0x00800000) /*!< ADC Trigger 3 on Timer C period */ -#define HRTIM_ADC3R_AD3TDC2 ((uint32_t)0x01000000) /*!< ADC Trigger 3 on Timer D compare 2 */ -#define HRTIM_ADC3R_AD3TDC3 ((uint32_t)0x02000000) /*!< ADC Trigger 3 on Timer D compare 3 */ -#define HRTIM_ADC3R_AD3TDC4 ((uint32_t)0x04000000) /*!< ADC Trigger 3 on Timer D compare 4 */ -#define HRTIM_ADC3R_AD3TDPER ((uint32_t)0x08000000) /*!< ADC Trigger 3 on Timer D period */ -#define HRTIM_ADC3R_AD3TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 3 on Timer E compare 2 */ -#define HRTIM_ADC3R_AD3TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 3 on Timer E compare 3 */ -#define HRTIM_ADC3R_AD3TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 3 on Timer E compare 4 */ -#define HRTIM_ADC3R_AD3TEPER ((uint32_t)0x80000000) /*!< ADC Trigger 3 on Timer E period */ - -/******************* Bit definition for HRTIM_ADC4R register ****************/ -#define HRTIM_ADC4R_AD4MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 4 on master compare 1 */ -#define HRTIM_ADC4R_AD4MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 4 on master compare 2 */ -#define HRTIM_ADC4R_AD4MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 4 on master compare 3 */ -#define HRTIM_ADC4R_AD4MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 4 on master compare 4 */ -#define HRTIM_ADC4R_AD4MPER ((uint32_t)0x00000010) /*!< ADC Trigger 4 on master period */ -#define HRTIM_ADC4R_AD4EEV6 ((uint32_t)0x00000020) /*!< ADC Trigger 4 on external event 6 */ -#define HRTIM_ADC4R_AD4EEV7 ((uint32_t)0x00000040) /*!< ADC Trigger 4 on external event 7 */ -#define HRTIM_ADC4R_AD4EEV8 ((uint32_t)0x00000080) /*!< ADC Trigger 4 on external event 8 */ -#define HRTIM_ADC4R_AD4EEV9 ((uint32_t)0x00000100) /*!< ADC Trigger 4 on external event 9 */ -#define HRTIM_ADC4R_AD4EEV10 ((uint32_t)0x00000200) /*!< ADC Trigger 4 on external event 10 */ -#define HRTIM_ADC4R_AD4TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 4 on Timer A compare 2 */ -#define HRTIM_ADC4R_AD4TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 4 on Timer A compare 3 */ -#define HRTIM_ADC4R_AD4TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 4 on Timer A compare 4*/ -#define HRTIM_ADC4R_AD4TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 4 on Timer A period */ -#define HRTIM_ADC4R_AD4TBC2 ((uint32_t)0x00004000) /*!< ADC Trigger 4 on Timer B compare 2 */ -#define HRTIM_ADC4R_AD4TBC3 ((uint32_t)0x00008000) /*!< ADC Trigger 4 on Timer B compare 3 */ -#define HRTIM_ADC4R_AD4TBC4 ((uint32_t)0x00010000) /*!< ADC Trigger 4 on Timer B compare 4 */ -#define HRTIM_ADC4R_AD4TBPER ((uint32_t)0x00020000) /*!< ADC Trigger 4 on Timer B period */ -#define HRTIM_ADC4R_AD4TCC2 ((uint32_t)0x00040000) /*!< ADC Trigger 4 on Timer C compare 2 */ -#define HRTIM_ADC4R_AD4TCC3 ((uint32_t)0x00080000) /*!< ADC Trigger 4 on Timer C compare 3 */ -#define HRTIM_ADC4R_AD4TCC4 ((uint32_t)0x00100000) /*!< ADC Trigger 4 on Timer C compare 4 */ -#define HRTIM_ADC4R_AD4TCPER ((uint32_t)0x00200000) /*!< ADC Trigger 4 on Timer C period */ -#define HRTIM_ADC4R_AD4TCRST ((uint32_t)0x00400000) /*!< ADC Trigger 4 on Timer C reset */ -#define HRTIM_ADC4R_AD4TDC2 ((uint32_t)0x00800000) /*!< ADC Trigger 4 on Timer D compare 2 */ -#define HRTIM_ADC4R_AD4TDC3 ((uint32_t)0x01000000) /*!< ADC Trigger 4 on Timer D compare 3 */ -#define HRTIM_ADC4R_AD4TDC4 ((uint32_t)0x02000000) /*!< ADC Trigger 4 on Timer D compare 4*/ -#define HRTIM_ADC4R_AD4TDPER ((uint32_t)0x04000000) /*!< ADC Trigger 4 on Timer D period */ -#define HRTIM_ADC4R_AD4TDRST ((uint32_t)0x08000000) /*!< ADC Trigger 4 on Timer D reset */ -#define HRTIM_ADC4R_AD4TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 4 on Timer E compare 2 */ -#define HRTIM_ADC4R_AD4TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 4 on Timer E compare 3 */ -#define HRTIM_ADC4R_AD4TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 4 on Timer E compare 4 */ -#define HRTIM_ADC4R_AD4TERST ((uint32_t)0x80000000) /*!< ADC Trigger 4 on Timer E reset */ - -/******************* Bit definition for HRTIM_DLLCR register ****************/ -#define HRTIM_DLLCR_CAL ((uint32_t)0x00000001) /*!< DLL calibration start */ -#define HRTIM_DLLCR_CALEN ((uint32_t)0x00000002) /*!< DLL calibration enable */ -#define HRTIM_DLLCR_CALRTE ((uint32_t)0x0000000C) /*!< DLL calibration rate */ -#define HRTIM_DLLCR_CALRTE_0 ((uint32_t)0x00000004) /*!< DLL calibration rate bit 0 */ -#define HRTIM_DLLCR_CALRTE_1 ((uint32_t)0x00000008) /*!< DLL calibration rate bit 1 */ - -/******************* Bit definition for HRTIM_FLTINR1 register ***************/ -#define HRTIM_FLTINR1_FLT1E ((uint32_t)0x00000001) /*!< Fault 1 enable */ -#define HRTIM_FLTINR1_FLT1P ((uint32_t)0x00000002) /*!< Fault 1 polarity */ -#define HRTIM_FLTINR1_FLT1SRC ((uint32_t)0x00000004) /*!< Fault 1 source */ -#define HRTIM_FLTINR1_FLT1F ((uint32_t)0x00000078) /*!< Fault 1 filter */ -#define HRTIM_FLTINR1_FLT1F_0 ((uint32_t)0x00000008) /*!< Fault 1 filter bit 0 */ -#define HRTIM_FLTINR1_FLT1F_1 ((uint32_t)0x00000010) /*!< Fault 1 filter bit 1 */ -#define HRTIM_FLTINR1_FLT1F_2 ((uint32_t)0x00000020) /*!< Fault 1 filter bit 2 */ -#define HRTIM_FLTINR1_FLT1F_3 ((uint32_t)0x00000040) /*!< Fault 1 filter bit 3 */ -#define HRTIM_FLTINR1_FLT1LCK ((uint32_t)0x00000080) /*!< Fault 1 lock */ - -#define HRTIM_FLTINR1_FLT2E ((uint32_t)0x00000100) /*!< Fault 2 enable */ -#define HRTIM_FLTINR1_FLT2P ((uint32_t)0x00000200) /*!< Fault 2 polarity */ -#define HRTIM_FLTINR1_FLT2SRC ((uint32_t)0x00000400) /*!< Fault 2 source */ -#define HRTIM_FLTINR1_FLT2F ((uint32_t)0x00007800) /*!< Fault 2 filter */ -#define HRTIM_FLTINR1_FLT2F_0 ((uint32_t)0x00000800) /*!< Fault 2 filter bit 0 */ -#define HRTIM_FLTINR1_FLT2F_1 ((uint32_t)0x00001000) /*!< Fault 2 filter bit 1 */ -#define HRTIM_FLTINR1_FLT2F_2 ((uint32_t)0x00002000) /*!< Fault 2 filter bit 2 */ -#define HRTIM_FLTINR1_FLT2F_3 ((uint32_t)0x00004000) /*!< Fault 2 filter bit 3 */ -#define HRTIM_FLTINR1_FLT2LCK ((uint32_t)0x00008000) /*!< Fault 2 lock */ - -#define HRTIM_FLTINR1_FLT3E ((uint32_t)0x00010000) /*!< Fault 3 enable */ -#define HRTIM_FLTINR1_FLT3P ((uint32_t)0x00020000) /*!< Fault 3 polarity */ -#define HRTIM_FLTINR1_FLT3SRC ((uint32_t)0x00040000) /*!< Fault 3 source */ -#define HRTIM_FLTINR1_FLT3F ((uint32_t)0x00780000) /*!< Fault 3 filter */ -#define HRTIM_FLTINR1_FLT3F_0 ((uint32_t)0x00080000) /*!< Fault 3 filter bit 0 */ -#define HRTIM_FLTINR1_FLT3F_1 ((uint32_t)0x00100000) /*!< Fault 3 filter bit 1 */ -#define HRTIM_FLTINR1_FLT3F_2 ((uint32_t)0x00200000) /*!< Fault 3 filter bit 2 */ -#define HRTIM_FLTINR1_FLT3F_3 ((uint32_t)0x00400000) /*!< Fault 3 filter bit 3 */ -#define HRTIM_FLTINR1_FLT3LCK ((uint32_t)0x00800000) /*!< Fault 3 lock */ - -#define HRTIM_FLTINR1_FLT4E ((uint32_t)0x01000000) /*!< Fault 4 enable */ -#define HRTIM_FLTINR1_FLT4P ((uint32_t)0x02000000) /*!< Fault 4 polarity */ -#define HRTIM_FLTINR1_FLT4SRC ((uint32_t)0x04000000) /*!< Fault 4 source */ -#define HRTIM_FLTINR1_FLT4F ((uint32_t)0x78000000) /*!< Fault 4 filter */ -#define HRTIM_FLTINR1_FLT4F_0 ((uint32_t)0x08000000) /*!< Fault 4 filter bit 0 */ -#define HRTIM_FLTINR1_FLT4F_1 ((uint32_t)0x10000000) /*!< Fault 4 filter bit 1 */ -#define HRTIM_FLTINR1_FLT4F_2 ((uint32_t)0x20000000) /*!< Fault 4 filter bit 2 */ -#define HRTIM_FLTINR1_FLT4F_3 ((uint32_t)0x40000000) /*!< Fault 4 filter bit 3 */ -#define HRTIM_FLTINR1_FLT4LCK ((uint32_t)0x80000000) /*!< Fault 4 lock */ - -/******************* Bit definition for HRTIM_FLTINR2 register ***************/ -#define HRTIM_FLTINR2_FLT5E ((uint32_t)0x00000001) /*!< Fault 5 enable */ -#define HRTIM_FLTINR2_FLT5P ((uint32_t)0x00000002) /*!< Fault 5 polarity */ -#define HRTIM_FLTINR2_FLT5SRC ((uint32_t)0x00000004) /*!< Fault 5 source */ -#define HRTIM_FLTINR2_FLT5F ((uint32_t)0x00000078) /*!< Fault 5 filter */ -#define HRTIM_FLTINR2_FLT5F_0 ((uint32_t)0x00000008) /*!< Fault 5 filter bit 0 */ -#define HRTIM_FLTINR2_FLT5F_1 ((uint32_t)0x00000010) /*!< Fault 5 filter bit 1 */ -#define HRTIM_FLTINR2_FLT5F_2 ((uint32_t)0x00000020) /*!< Fault 5 filter bit 2 */ -#define HRTIM_FLTINR2_FLT5F_3 ((uint32_t)0x00000040) /*!< Fault 5 filter bit 3 */ -#define HRTIM_FLTINR2_FLT5LCK ((uint32_t)0x00000080) /*!< Fault 5 lock */ -#define HRTIM_FLTINR2_FLTSD ((uint32_t)0x03000000) /*!< Fault sampling clock division */ -#define HRTIM_FLTINR2_FLTSD_0 ((uint32_t)0x01000000) /*!< Fault sampling clock division bit 0 */ -#define HRTIM_FLTINR2_FLTSD_1 ((uint32_t)0x02000000) /*!< Fault sampling clock division bit 1 */ - -/******************* Bit definition for HRTIM_BDMUPR register ***************/ -#define HRTIM_BDMUPR_MCR ((uint32_t)0x00000001) /*!< MCR register update enable */ -#define HRTIM_BDMUPR_MICR ((uint32_t)0x00000002) /*!< MICR register update enable */ -#define HRTIM_BDMUPR_MDIER ((uint32_t)0x00000004) /*!< MDIER register update enable */ -#define HRTIM_BDMUPR_MCNT ((uint32_t)0x00000008) /*!< MCNT register update enable */ -#define HRTIM_BDMUPR_MPER ((uint32_t)0x00000010) /*!< MPER register update enable */ -#define HRTIM_BDMUPR_MREP ((uint32_t)0x00000020) /*!< MREP register update enable */ -#define HRTIM_BDMUPR_MCMP1 ((uint32_t)0x00000040) /*!< MCMP1 register update enable */ -#define HRTIM_BDMUPR_MCMP2 ((uint32_t)0x00000080) /*!< MCMP2 register update enable */ -#define HRTIM_BDMUPR_MCMP3 ((uint32_t)0x00000100) /*!< MCMP3 register update enable */ -#define HRTIM_BDMUPR_MCMP4 ((uint32_t)0x00000200) /*!< MPCMP4 register update enable */ - -/******************* Bit definition for HRTIM_BDTUPR register ***************/ -#define HRTIM_BDTUPR_TIMCR ((uint32_t)0x00000001) /*!< TIMCR register update enable */ -#define HRTIM_BDTUPR_TIMICR ((uint32_t)0x00000002) /*!< TIMICR register update enable */ -#define HRTIM_BDTUPR_TIMDIER ((uint32_t)0x00000004) /*!< TIMDIER register update enable */ -#define HRTIM_BDTUPR_TIMCNT ((uint32_t)0x00000008) /*!< TIMCNT register update enable */ -#define HRTIM_BDTUPR_TIMPER ((uint32_t)0x00000010) /*!< TIMPER register update enable */ -#define HRTIM_BDTUPR_TIMREP ((uint32_t)0x00000020) /*!< TIMREP register update enable */ -#define HRTIM_BDTUPR_TIMCMP1 ((uint32_t)0x00000040) /*!< TIMCMP1 register update enable */ -#define HRTIM_BDTUPR_TIMCMP2 ((uint32_t)0x00000080) /*!< TIMCMP2 register update enable */ -#define HRTIM_BDTUPR_TIMCMP3 ((uint32_t)0x00000100) /*!< TIMCMP3 register update enable */ -#define HRTIM_BDTUPR_TIMCMP4 ((uint32_t)0x00000200) /*!< TIMCMP4 register update enable */ -#define HRTIM_BDTUPR_TIMDTR ((uint32_t)0x00000400) /*!< TIMDTR register update enable */ -#define HRTIM_BDTUPR_TIMSET1R ((uint32_t)0x00000800) /*!< TIMSET1R register update enable */ -#define HRTIM_BDTUPR_TIMRST1R ((uint32_t)0x00001000) /*!< TIMRST1R register update enable */ -#define HRTIM_BDTUPR_TIMSET2R ((uint32_t)0x00002000) /*!< TIMSET2R register update enable */ -#define HRTIM_BDTUPR_TIMRST2R ((uint32_t)0x00004000) /*!< TIMRST2R register update enable */ -#define HRTIM_BDTUPR_TIMEEFR1 ((uint32_t)0x00008000) /*!< TIMEEFR1 register update enable */ -#define HRTIM_BDTUPR_TIMEEFR2 ((uint32_t)0x00010000) /*!< TIMEEFR2 register update enable */ -#define HRTIM_BDTUPR_TIMRSTR ((uint32_t)0x00020000) /*!< TIMRSTR register update enable */ -#define HRTIM_BDTUPR_TIMCHPR ((uint32_t)0x00040000) /*!< TIMCHPR register update enable */ -#define HRTIM_BDTUPR_TIMOUTR ((uint32_t)0x00080000) /*!< TIMOUTR register update enable */ -#define HRTIM_BDTUPR_TIMFLTR ((uint32_t)0x00100000) /*!< TIMFLTR register update enable */ - -/******************* Bit definition for HRTIM_BDMADR register ***************/ -#define HRTIM_BDMADR_BDMADR ((uint32_t)0xFFFFFFFF) /*!< Burst DMA Data register */ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter SAR (ADC) */ -/* */ -/******************************************************************************/ -/******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */ -#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */ -#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion flag */ -#define ADC_ISR_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions flag */ -#define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< ADC overrun flag */ -#define ADC_ISR_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion flag */ -#define ADC_ISR_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions flag */ -#define ADC_ISR_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 flag */ -#define ADC_ISR_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 flag */ -#define ADC_ISR_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 flag */ -#define ADC_ISR_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow flag */ - -/******************** Bit definition for ADC_IER register ********************/ -#define ADC_IER_RDY ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) interrupt source */ -#define ADC_IER_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling interrupt source */ -#define ADC_IER_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion interrupt source */ -#define ADC_IER_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions interrupt source */ -#define ADC_IER_OVR ((uint32_t)0x00000010) /*!< ADC overrun interrupt source */ -#define ADC_IER_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion interrupt source */ -#define ADC_IER_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions interrupt source */ -#define ADC_IER_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 interrupt source */ -#define ADC_IER_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 interrupt source */ -#define ADC_IER_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 interrupt source */ -#define ADC_IER_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow interrupt source */ - -/******************** Bit definition for ADC_CR register ********************/ -#define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC Enable control */ -#define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC Disable command */ -#define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC Start of Regular conversion */ -#define ADC_CR_JADSTART ((uint32_t)0x00000008) /*!< ADC Start of injected conversion */ -#define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC Stop of Regular conversion */ -#define ADC_CR_JADSTP ((uint32_t)0x00000020) /*!< ADC Stop of injected conversion */ -#define ADC_CR_ADVREGEN ((uint32_t)0x30000000) /*!< ADC Voltage regulator Enable */ -#define ADC_CR_ADVREGEN_0 ((uint32_t)0x10000000) /*!< ADC ADVREGEN bit 0 */ -#define ADC_CR_ADVREGEN_1 ((uint32_t)0x20000000) /*!< ADC ADVREGEN bit 1 */ -#define ADC_CR_ADCALDIF ((uint32_t)0x40000000) /*!< ADC Differential Mode for calibration */ -#define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC Calibration */ - -/******************** Bit definition for ADC_CFGR register ********************/ -#define ADC_CFGR_DMAEN ((uint32_t)0x00000001) /*!< ADC DMA Enable */ -#define ADC_CFGR_DMACFG ((uint32_t)0x00000002) /*!< ADC DMA configuration */ - -#define ADC_CFGR_RES ((uint32_t)0x00000018) /*!< ADC Data resolution */ -#define ADC_CFGR_RES_0 ((uint32_t)0x00000008) /*!< ADC RES bit 0 */ -#define ADC_CFGR_RES_1 ((uint32_t)0x00000010) /*!< ADC RES bit 1 */ - -#define ADC_CFGR_ALIGN ((uint32_t)0x00000020) /*!< ADC Data Alignment */ - -#define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0) /*!< ADC External trigger selection for regular group */ -#define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) /*!< ADC EXTSEL bit 0 */ -#define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) /*!< ADC EXTSEL bit 1 */ -#define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) /*!< ADC EXTSEL bit 2 */ -#define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) /*!< ADC EXTSEL bit 3 */ - -#define ADC_CFGR_EXTEN ((uint32_t)0x00000C00) /*!< ADC External trigger enable and polarity selection for regular channels */ -#define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400) /*!< ADC EXTEN bit 0 */ -#define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800) /*!< ADC EXTEN bit 1 */ - -#define ADC_CFGR_OVRMOD ((uint32_t)0x00001000) /*!< ADC overrun mode */ -#define ADC_CFGR_CONT ((uint32_t)0x00002000) /*!< ADC Single/continuous conversion mode for regular conversion */ -#define ADC_CFGR_AUTDLY ((uint32_t)0x00004000) /*!< ADC Delayed conversion mode */ -#define ADC_CFGR_DISCEN ((uint32_t)0x00010000) /*!< ADC Discontinuous mode for regular channels */ - -#define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000) /*!< ADC Discontinuous mode channel count */ -#define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) /*!< ADC DISCNUM bit 0 */ -#define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) /*!< ADC DISCNUM bit 1 */ -#define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) /*!< ADC DISCNUM bit 2 */ - -#define ADC_CFGR_JDISCEN ((uint32_t)0x00100000) /*!< ADC Discontinuous mode on injected channels */ -#define ADC_CFGR_JQM ((uint32_t)0x00200000) /*!< ADC JSQR Queue mode */ -#define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000) /*!< Enable the watchdog 1 on a single channel or on all channels */ -#define ADC_CFGR_AWD1EN ((uint32_t)0x00800000) /*!< ADC Analog watchdog 1 enable on regular Channels */ -#define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000) /*!< ADC Analog watchdog 1 enable on injected Channels */ -#define ADC_CFGR_JAUTO ((uint32_t)0x02000000) /*!< ADC Automatic injected group conversion */ - -#define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000) /*!< ADC Analog watchdog 1 Channel selection */ -#define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000) /*!< ADC AWD1CH bit 0 */ -#define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000) /*!< ADC AWD1CH bit 1 */ -#define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000) /*!< ADC AWD1CH bit 2 */ -#define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000) /*!< ADC AWD1CH bit 3 */ -#define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000) /*!< ADC AWD1CH bit 4 */ - -/******************** Bit definition for ADC_SMPR1 register ********************/ -#define ADC_SMPR1_SMP0 ((uint32_t)0x00000007) /*!< ADC Channel 0 Sampling time selection */ -#define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001) /*!< ADC SMP0 bit 0 */ -#define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002) /*!< ADC SMP0 bit 1 */ -#define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004) /*!< ADC SMP0 bit 2 */ - -#define ADC_SMPR1_SMP1 ((uint32_t)0x00000038) /*!< ADC Channel 1 Sampling time selection */ -#define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008) /*!< ADC SMP1 bit 0 */ -#define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010) /*!< ADC SMP1 bit 1 */ -#define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020) /*!< ADC SMP1 bit 2 */ - -#define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0) /*!< ADC Channel 2 Sampling time selection */ -#define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040) /*!< ADC SMP2 bit 0 */ -#define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080) /*!< ADC SMP2 bit 1 */ -#define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100) /*!< ADC SMP2 bit 2 */ - -#define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00) /*!< ADC Channel 3 Sampling time selection */ -#define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200) /*!< ADC SMP3 bit 0 */ -#define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400) /*!< ADC SMP3 bit 1 */ -#define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800) /*!< ADC SMP3 bit 2 */ - -#define ADC_SMPR1_SMP4 ((uint32_t)0x00007000) /*!< ADC Channel 4 Sampling time selection */ -#define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000) /*!< ADC SMP4 bit 0 */ -#define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000) /*!< ADC SMP4 bit 1 */ -#define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000) /*!< ADC SMP4 bit 2 */ - -#define ADC_SMPR1_SMP5 ((uint32_t)0x00038000) /*!< ADC Channel 5 Sampling time selection */ -#define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000) /*!< ADC SMP5 bit 0 */ -#define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000) /*!< ADC SMP5 bit 1 */ -#define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000) /*!< ADC SMP5 bit 2 */ - -#define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000) /*!< ADC Channel 6 Sampling time selection */ -#define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000) /*!< ADC SMP6 bit 0 */ -#define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000) /*!< ADC SMP6 bit 1 */ -#define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000) /*!< ADC SMP6 bit 2 */ - -#define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000) /*!< ADC Channel 7 Sampling time selection */ -#define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000) /*!< ADC SMP7 bit 0 */ -#define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000) /*!< ADC SMP7 bit 1 */ -#define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000) /*!< ADC SMP7 bit 2 */ - -#define ADC_SMPR1_SMP8 ((uint32_t)0x07000000) /*!< ADC Channel 8 Sampling time selection */ -#define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000) /*!< ADC SMP8 bit 0 */ -#define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000) /*!< ADC SMP8 bit 1 */ -#define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000) /*!< ADC SMP8 bit 2 */ - -#define ADC_SMPR1_SMP9 ((uint32_t)0x38000000) /*!< ADC Channel 9 Sampling time selection */ -#define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000) /*!< ADC SMP9 bit 0 */ -#define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000) /*!< ADC SMP9 bit 1 */ -#define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000) /*!< ADC SMP9 bit 2 */ - -/******************** Bit definition for ADC_SMPR2 register ********************/ -#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< ADC Channel 10 Sampling time selection */ -#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< ADC SMP10 bit 0 */ -#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< ADC SMP10 bit 1 */ -#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< ADC SMP10 bit 2 */ - -#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< ADC Channel 11 Sampling time selection */ -#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< ADC SMP11 bit 0 */ -#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< ADC SMP11 bit 1 */ -#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< ADC SMP11 bit 2 */ - -#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< ADC Channel 12 Sampling time selection */ -#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< ADC SMP12 bit 0 */ -#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< ADC SMP12 bit 1 */ -#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< ADC SMP12 bit 2 */ - -#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< ADC Channel 13 Sampling time selection */ -#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< ADC SMP13 bit 0 */ -#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< ADC SMP13 bit 1 */ -#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< ADC SMP13 bit 2 */ - -#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< ADC Channel 14 Sampling time selection */ -#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< ADC SMP14 bit 0 */ -#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< ADC SMP14 bit 1 */ -#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< ADC SMP14 bit 2 */ - -#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< ADC Channel 15 Sampling time selection */ -#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< ADC SMP15 bit 0 */ -#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< ADC SMP15 bit 1 */ -#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< ADC SMP15 bit 2 */ - -#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< ADC Channel 16 Sampling time selection */ -#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< ADC SMP16 bit 0 */ -#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< ADC SMP16 bit 1 */ -#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< ADC SMP16 bit 2 */ - -#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< ADC Channel 17 Sampling time selection */ -#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< ADC SMP17 bit 0 */ -#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< ADC SMP17 bit 1 */ -#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< ADC SMP17 bit 2 */ - -#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< ADC Channel 18 Sampling time selection */ -#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< ADC SMP18 bit 0 */ -#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< ADC SMP18 bit 1 */ -#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< ADC SMP18 bit 2 */ - -/******************** Bit definition for ADC_TR1 register ********************/ -#define ADC_TR1_LT1 ((uint32_t)0x00000FFF) /*!< ADC Analog watchdog 1 lower threshold */ -#define ADC_TR1_LT1_0 ((uint32_t)0x00000001) /*!< ADC LT1 bit 0 */ -#define ADC_TR1_LT1_1 ((uint32_t)0x00000002) /*!< ADC LT1 bit 1 */ -#define ADC_TR1_LT1_2 ((uint32_t)0x00000004) /*!< ADC LT1 bit 2 */ -#define ADC_TR1_LT1_3 ((uint32_t)0x00000008) /*!< ADC LT1 bit 3 */ -#define ADC_TR1_LT1_4 ((uint32_t)0x00000010) /*!< ADC LT1 bit 4 */ -#define ADC_TR1_LT1_5 ((uint32_t)0x00000020) /*!< ADC LT1 bit 5 */ -#define ADC_TR1_LT1_6 ((uint32_t)0x00000040) /*!< ADC LT1 bit 6 */ -#define ADC_TR1_LT1_7 ((uint32_t)0x00000080) /*!< ADC LT1 bit 7 */ -#define ADC_TR1_LT1_8 ((uint32_t)0x00000100) /*!< ADC LT1 bit 8 */ -#define ADC_TR1_LT1_9 ((uint32_t)0x00000200) /*!< ADC LT1 bit 9 */ -#define ADC_TR1_LT1_10 ((uint32_t)0x00000400) /*!< ADC LT1 bit 10 */ -#define ADC_TR1_LT1_11 ((uint32_t)0x00000800) /*!< ADC LT1 bit 11 */ - -#define ADC_TR1_HT1 ((uint32_t)0x0FFF0000) /*!< ADC Analog watchdog 1 higher threshold */ -#define ADC_TR1_HT1_0 ((uint32_t)0x00010000) /*!< ADC HT1 bit 0 */ -#define ADC_TR1_HT1_1 ((uint32_t)0x00020000) /*!< ADC HT1 bit 1 */ -#define ADC_TR1_HT1_2 ((uint32_t)0x00040000) /*!< ADC HT1 bit 2 */ -#define ADC_TR1_HT1_3 ((uint32_t)0x00080000) /*!< ADC HT1 bit 3 */ -#define ADC_TR1_HT1_4 ((uint32_t)0x00100000) /*!< ADC HT1 bit 4 */ -#define ADC_TR1_HT1_5 ((uint32_t)0x00200000) /*!< ADC HT1 bit 5 */ -#define ADC_TR1_HT1_6 ((uint32_t)0x00400000) /*!< ADC HT1 bit 6 */ -#define ADC_TR1_HT1_7 ((uint32_t)0x00800000) /*!< ADC HT1 bit 7 */ -#define ADC_TR1_HT1_8 ((uint32_t)0x01000000) /*!< ADC HT1 bit 8 */ -#define ADC_TR1_HT1_9 ((uint32_t)0x02000000) /*!< ADC HT1 bit 9 */ -#define ADC_TR1_HT1_10 ((uint32_t)0x04000000) /*!< ADC HT1 bit 10 */ -#define ADC_TR1_HT1_11 ((uint32_t)0x08000000) /*!< ADC HT1 bit 11 */ - -/******************** Bit definition for ADC_TR2 register ********************/ -#define ADC_TR2_LT2 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 2 lower threshold */ -#define ADC_TR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ -#define ADC_TR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ -#define ADC_TR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ -#define ADC_TR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ -#define ADC_TR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ -#define ADC_TR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ -#define ADC_TR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ -#define ADC_TR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ - -#define ADC_TR2_HT2 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 2 higher threshold */ -#define ADC_TR2_HT2_0 ((uint32_t)0x00010000) /*!< ADC HT2 bit 0 */ -#define ADC_TR2_HT2_1 ((uint32_t)0x00020000) /*!< ADC HT2 bit 1 */ -#define ADC_TR2_HT2_2 ((uint32_t)0x00040000) /*!< ADC HT2 bit 2 */ -#define ADC_TR2_HT2_3 ((uint32_t)0x00080000) /*!< ADC HT2 bit 3 */ -#define ADC_TR2_HT2_4 ((uint32_t)0x00100000) /*!< ADC HT2 bit 4 */ -#define ADC_TR2_HT2_5 ((uint32_t)0x00200000) /*!< ADC HT2 bit 5 */ -#define ADC_TR2_HT2_6 ((uint32_t)0x00400000) /*!< ADC HT2 bit 6 */ -#define ADC_TR2_HT2_7 ((uint32_t)0x00800000) /*!< ADC HT2 bit 7 */ - -/******************** Bit definition for ADC_TR3 register ********************/ -#define ADC_TR3_LT3 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 3 lower threshold */ -#define ADC_TR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ -#define ADC_TR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ -#define ADC_TR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ -#define ADC_TR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ -#define ADC_TR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ -#define ADC_TR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ -#define ADC_TR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ -#define ADC_TR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ - -#define ADC_TR3_HT3 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 3 higher threshold */ -#define ADC_TR3_HT3_0 ((uint32_t)0x00010000) /*!< ADC HT3 bit 0 */ -#define ADC_TR3_HT3_1 ((uint32_t)0x00020000) /*!< ADC HT3 bit 1 */ -#define ADC_TR3_HT3_2 ((uint32_t)0x00040000) /*!< ADC HT3 bit 2 */ -#define ADC_TR3_HT3_3 ((uint32_t)0x00080000) /*!< ADC HT3 bit 3 */ -#define ADC_TR3_HT3_4 ((uint32_t)0x00100000) /*!< ADC HT3 bit 4 */ -#define ADC_TR3_HT3_5 ((uint32_t)0x00200000) /*!< ADC HT3 bit 5 */ -#define ADC_TR3_HT3_6 ((uint32_t)0x00400000) /*!< ADC HT3 bit 6 */ -#define ADC_TR3_HT3_7 ((uint32_t)0x00800000) /*!< ADC HT3 bit 7 */ - -/******************** Bit definition for ADC_SQR1 register ********************/ -#define ADC_SQR1_L ((uint32_t)0x0000000F) /*!< ADC regular channel sequence length */ -#define ADC_SQR1_L_0 ((uint32_t)0x00000001) /*!< ADC L bit 0 */ -#define ADC_SQR1_L_1 ((uint32_t)0x00000002) /*!< ADC L bit 1 */ -#define ADC_SQR1_L_2 ((uint32_t)0x00000004) /*!< ADC L bit 2 */ -#define ADC_SQR1_L_3 ((uint32_t)0x00000008) /*!< ADC L bit 3 */ - -#define ADC_SQR1_SQ1 ((uint32_t)0x000007C0) /*!< ADC 1st conversion in regular sequence */ -#define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040) /*!< ADC SQ1 bit 0 */ -#define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080) /*!< ADC SQ1 bit 1 */ -#define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100) /*!< ADC SQ1 bit 2 */ -#define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200) /*!< ADC SQ1 bit 3 */ -#define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400) /*!< ADC SQ1 bit 4 */ - -#define ADC_SQR1_SQ2 ((uint32_t)0x0001F000) /*!< ADC 2nd conversion in regular sequence */ -#define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000) /*!< ADC SQ2 bit 0 */ -#define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000) /*!< ADC SQ2 bit 1 */ -#define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000) /*!< ADC SQ2 bit 2 */ -#define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000) /*!< ADC SQ2 bit 3 */ -#define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000) /*!< ADC SQ2 bit 4 */ - -#define ADC_SQR1_SQ3 ((uint32_t)0x007C0000) /*!< ADC 3rd conversion in regular sequence */ -#define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000) /*!< ADC SQ3 bit 0 */ -#define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000) /*!< ADC SQ3 bit 1 */ -#define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000) /*!< ADC SQ3 bit 2 */ -#define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000) /*!< ADC SQ3 bit 3 */ -#define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000) /*!< ADC SQ3 bit 4 */ - -#define ADC_SQR1_SQ4 ((uint32_t)0x1F000000) /*!< ADC 4th conversion in regular sequence */ -#define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000) /*!< ADC SQ4 bit 0 */ -#define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000) /*!< ADC SQ4 bit 1 */ -#define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000) /*!< ADC SQ4 bit 2 */ -#define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000) /*!< ADC SQ4 bit 3 */ -#define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000) /*!< ADC SQ4 bit 4 */ - -/******************** Bit definition for ADC_SQR2 register ********************/ -#define ADC_SQR2_SQ5 ((uint32_t)0x0000001F) /*!< ADC 5th conversion in regular sequence */ -#define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001) /*!< ADC SQ5 bit 0 */ -#define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002) /*!< ADC SQ5 bit 1 */ -#define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004) /*!< ADC SQ5 bit 2 */ -#define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008) /*!< ADC SQ5 bit 3 */ -#define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010) /*!< ADC SQ5 bit 4 */ - -#define ADC_SQR2_SQ6 ((uint32_t)0x000007C0) /*!< ADC 6th conversion in regular sequence */ -#define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040) /*!< ADC SQ6 bit 0 */ -#define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080) /*!< ADC SQ6 bit 1 */ -#define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100) /*!< ADC SQ6 bit 2 */ -#define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200) /*!< ADC SQ6 bit 3 */ -#define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400) /*!< ADC SQ6 bit 4 */ - -#define ADC_SQR2_SQ7 ((uint32_t)0x0001F000) /*!< ADC 7th conversion in regular sequence */ -#define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000) /*!< ADC SQ7 bit 0 */ -#define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000) /*!< ADC SQ7 bit 1 */ -#define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000) /*!< ADC SQ7 bit 2 */ -#define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000) /*!< ADC SQ7 bit 3 */ -#define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000) /*!< ADC SQ7 bit 4 */ - -#define ADC_SQR2_SQ8 ((uint32_t)0x007C0000) /*!< ADC 8th conversion in regular sequence */ -#define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000) /*!< ADC SQ8 bit 0 */ -#define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000) /*!< ADC SQ8 bit 1 */ -#define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000) /*!< ADC SQ8 bit 2 */ -#define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000) /*!< ADC SQ8 bit 3 */ -#define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000) /*!< ADC SQ8 bit 4 */ - -#define ADC_SQR2_SQ9 ((uint32_t)0x1F000000) /*!< ADC 9th conversion in regular sequence */ -#define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000) /*!< ADC SQ9 bit 0 */ -#define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000) /*!< ADC SQ9 bit 1 */ -#define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000) /*!< ADC SQ9 bit 2 */ -#define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000) /*!< ADC SQ9 bit 3 */ -#define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000) /*!< ADC SQ9 bit 4 */ - -/******************** Bit definition for ADC_SQR3 register ********************/ -#define ADC_SQR3_SQ10 ((uint32_t)0x0000001F) /*!< ADC 10th conversion in regular sequence */ -#define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001) /*!< ADC SQ10 bit 0 */ -#define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002) /*!< ADC SQ10 bit 1 */ -#define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004) /*!< ADC SQ10 bit 2 */ -#define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008) /*!< ADC SQ10 bit 3 */ -#define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010) /*!< ADC SQ10 bit 4 */ - -#define ADC_SQR3_SQ11 ((uint32_t)0x000007C0) /*!< ADC 11th conversion in regular sequence */ -#define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040) /*!< ADC SQ11 bit 0 */ -#define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080) /*!< ADC SQ11 bit 1 */ -#define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100) /*!< ADC SQ11 bit 2 */ -#define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200) /*!< ADC SQ11 bit 3 */ -#define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400) /*!< ADC SQ11 bit 4 */ - -#define ADC_SQR3_SQ12 ((uint32_t)0x0001F000) /*!< ADC 12th conversion in regular sequence */ -#define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000) /*!< ADC SQ12 bit 0 */ -#define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000) /*!< ADC SQ12 bit 1 */ -#define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000) /*!< ADC SQ12 bit 2 */ -#define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000) /*!< ADC SQ12 bit 3 */ -#define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000) /*!< ADC SQ12 bit 4 */ - -#define ADC_SQR3_SQ13 ((uint32_t)0x007C0000) /*!< ADC 13th conversion in regular sequence */ -#define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000) /*!< ADC SQ13 bit 0 */ -#define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000) /*!< ADC SQ13 bit 1 */ -#define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000) /*!< ADC SQ13 bit 2 */ -#define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000) /*!< ADC SQ13 bit 3 */ -#define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000) /*!< ADC SQ13 bit 4 */ - -#define ADC_SQR3_SQ14 ((uint32_t)0x1F000000) /*!< ADC 14th conversion in regular sequence */ -#define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000) /*!< ADC SQ14 bit 0 */ -#define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000) /*!< ADC SQ14 bit 1 */ -#define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000) /*!< ADC SQ14 bit 2 */ -#define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000) /*!< ADC SQ14 bit 3 */ -#define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000) /*!< ADC SQ14 bit 4 */ - -/******************** Bit definition for ADC_SQR4 register ********************/ -#define ADC_SQR4_SQ15 ((uint32_t)0x0000001F) /*!< ADC 15th conversion in regular sequence */ -#define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001) /*!< ADC SQ15 bit 0 */ -#define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002) /*!< ADC SQ15 bit 1 */ -#define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004) /*!< ADC SQ15 bit 2 */ -#define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008) /*!< ADC SQ15 bit 3 */ -#define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010) /*!< ADC SQ105 bit 4 */ - -#define ADC_SQR4_SQ16 ((uint32_t)0x000007C0) /*!< ADC 16th conversion in regular sequence */ -#define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040) /*!< ADC SQ16 bit 0 */ -#define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080) /*!< ADC SQ16 bit 1 */ -#define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100) /*!< ADC SQ16 bit 2 */ -#define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200) /*!< ADC SQ16 bit 3 */ -#define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400) /*!< ADC SQ16 bit 4 */ - -/* these defines are maintained for legacy purpose */ -#define ADC_SQR3_SQ15 ADC_SQR4_SQ15 /*!< ADC 15th conversion in regular sequence */ -#define ADC_SQR3_SQ15_0 ADC_SQR4_SQ15_0 /*!< ADC SQ15 bit 0 */ -#define ADC_SQR3_SQ15_1 ADC_SQR4_SQ15_1 /*!< ADC SQ15 bit 1 */ -#define ADC_SQR3_SQ15_2 ADC_SQR4_SQ15_2 /*!< ADC SQ15 bit 2 */ -#define ADC_SQR3_SQ15_3 ADC_SQR4_SQ15_3 /*!< ADC SQ15 bit 3 */ -#define ADC_SQR3_SQ15_4 ADC_SQR4_SQ15_4 /*!< ADC SQ105 bit 4 */ - -#define ADC_SQR3_SQ16 ADC_SQR4_SQ16 /*!< ADC 16th conversion in regular sequence */ -#define ADC_SQR3_SQ16_0 ADC_SQR4_SQ16_0 /*!< ADC SQ16 bit 0 */ -#define ADC_SQR3_SQ16_1 ADC_SQR4_SQ16_1 /*!< ADC SQ16 bit 1 */ -#define ADC_SQR3_SQ16_2 ADC_SQR4_SQ16_2 /*!< ADC SQ16 bit 2 */ -#define ADC_SQR3_SQ16_3 ADC_SQR4_SQ16_3 /*!< ADC SQ16 bit 3 */ -#define ADC_SQR3_SQ16_4 ADC_SQR4_SQ16_4 /*!< ADC SQ16 bit 4 */ -/******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_RDATA ((uint32_t)0x0000FFFF) /*!< ADC regular Data converted */ -#define ADC_DR_RDATA_0 ((uint32_t)0x00000001) /*!< ADC RDATA bit 0 */ -#define ADC_DR_RDATA_1 ((uint32_t)0x00000002) /*!< ADC RDATA bit 1 */ -#define ADC_DR_RDATA_2 ((uint32_t)0x00000004) /*!< ADC RDATA bit 2 */ -#define ADC_DR_RDATA_3 ((uint32_t)0x00000008) /*!< ADC RDATA bit 3 */ -#define ADC_DR_RDATA_4 ((uint32_t)0x00000010) /*!< ADC RDATA bit 4 */ -#define ADC_DR_RDATA_5 ((uint32_t)0x00000020) /*!< ADC RDATA bit 5 */ -#define ADC_DR_RDATA_6 ((uint32_t)0x00000040) /*!< ADC RDATA bit 6 */ -#define ADC_DR_RDATA_7 ((uint32_t)0x00000080) /*!< ADC RDATA bit 7 */ -#define ADC_DR_RDATA_8 ((uint32_t)0x00000100) /*!< ADC RDATA bit 8 */ -#define ADC_DR_RDATA_9 ((uint32_t)0x00000200) /*!< ADC RDATA bit 9 */ -#define ADC_DR_RDATA_10 ((uint32_t)0x00000400) /*!< ADC RDATA bit 10 */ -#define ADC_DR_RDATA_11 ((uint32_t)0x00000800) /*!< ADC RDATA bit 11 */ -#define ADC_DR_RDATA_12 ((uint32_t)0x00001000) /*!< ADC RDATA bit 12 */ -#define ADC_DR_RDATA_13 ((uint32_t)0x00002000) /*!< ADC RDATA bit 13 */ -#define ADC_DR_RDATA_14 ((uint32_t)0x00004000) /*!< ADC RDATA bit 14 */ -#define ADC_DR_RDATA_15 ((uint32_t)0x00008000) /*!< ADC RDATA bit 15 */ - -/******************** Bit definition for ADC_JSQR register ********************/ -#define ADC_JSQR_JL ((uint32_t)0x00000003) /*!< ADC injected channel sequence length */ -#define ADC_JSQR_JL_0 ((uint32_t)0x00000001) /*!< ADC JL bit 0 */ -#define ADC_JSQR_JL_1 ((uint32_t)0x00000002) /*!< ADC JL bit 1 */ - -#define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003C) /*!< ADC external trigger selection for injected group */ -#define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004) /*!< ADC JEXTSEL bit 0 */ -#define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008) /*!< ADC JEXTSEL bit 1 */ -#define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010) /*!< ADC JEXTSEL bit 2 */ -#define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020) /*!< ADC JEXTSEL bit 3 */ - -#define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0) /*!< ADC external trigger enable and polarity selection for injected channels */ -#define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040) /*!< ADC JEXTEN bit 0 */ -#define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080) /*!< ADC JEXTEN bit 1 */ - -#define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00) /*!< ADC 1st conversion in injected sequence */ -#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100) /*!< ADC JSQ1 bit 0 */ -#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200) /*!< ADC JSQ1 bit 1 */ -#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400) /*!< ADC JSQ1 bit 2 */ -#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800) /*!< ADC JSQ1 bit 3 */ -#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000) /*!< ADC JSQ1 bit 4 */ - -#define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000) /*!< ADC 2nd conversion in injected sequence */ -#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000) /*!< ADC JSQ2 bit 0 */ -#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000) /*!< ADC JSQ2 bit 1 */ -#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000) /*!< ADC JSQ2 bit 2 */ -#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000) /*!< ADC JSQ2 bit 3 */ -#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000) /*!< ADC JSQ2 bit 4 */ - -#define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000) /*!< ADC 3rd conversion in injected sequence */ -#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000) /*!< ADC JSQ3 bit 0 */ -#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000) /*!< ADC JSQ3 bit 1 */ -#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000) /*!< ADC JSQ3 bit 2 */ -#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000) /*!< ADC JSQ3 bit 3 */ -#define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000) /*!< ADC JSQ3 bit 4 */ - -#define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000) /*!< ADC 4th conversion in injected sequence */ -#define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000) /*!< ADC JSQ4 bit 0 */ -#define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000) /*!< ADC JSQ4 bit 1 */ -#define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000) /*!< ADC JSQ4 bit 2 */ -#define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000) /*!< ADC JSQ4 bit 3 */ -#define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000) /*!< ADC JSQ4 bit 4 */ - -/******************** Bit definition for ADC_OFR1 register ********************/ -#define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFF) /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ -#define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001) /*!< ADC OFFSET1 bit 0 */ -#define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002) /*!< ADC OFFSET1 bit 1 */ -#define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004) /*!< ADC OFFSET1 bit 2 */ -#define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008) /*!< ADC OFFSET1 bit 3 */ -#define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010) /*!< ADC OFFSET1 bit 4 */ -#define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020) /*!< ADC OFFSET1 bit 5 */ -#define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040) /*!< ADC OFFSET1 bit 6 */ -#define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080) /*!< ADC OFFSET1 bit 7 */ -#define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100) /*!< ADC OFFSET1 bit 8 */ -#define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200) /*!< ADC OFFSET1 bit 9 */ -#define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) /*!< ADC OFFSET1 bit 10 */ -#define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) /*!< ADC OFFSET1 bit 11 */ - -#define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 1 */ -#define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET1_CH bit 0 */ -#define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET1_CH bit 1 */ -#define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET1_CH bit 2 */ -#define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET1_CH bit 3 */ -#define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET1_CH bit 4 */ - -#define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) /*!< ADC offset 1 enable */ - -/******************** Bit definition for ADC_OFR2 register ********************/ -#define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFF) /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ -#define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001) /*!< ADC OFFSET2 bit 0 */ -#define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002) /*!< ADC OFFSET2 bit 1 */ -#define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004) /*!< ADC OFFSET2 bit 2 */ -#define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008) /*!< ADC OFFSET2 bit 3 */ -#define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010) /*!< ADC OFFSET2 bit 4 */ -#define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020) /*!< ADC OFFSET2 bit 5 */ -#define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040) /*!< ADC OFFSET2 bit 6 */ -#define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080) /*!< ADC OFFSET2 bit 7 */ -#define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100) /*!< ADC OFFSET2 bit 8 */ -#define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200) /*!< ADC OFFSET2 bit 9 */ -#define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) /*!< ADC OFFSET2 bit 10 */ -#define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) /*!< ADC OFFSET2 bit 11 */ - -#define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 2 */ -#define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET2_CH bit 0 */ -#define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET2_CH bit 1 */ -#define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET2_CH bit 2 */ -#define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET2_CH bit 3 */ -#define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET2_CH bit 4 */ - -#define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) /*!< ADC offset 2 enable */ - -/******************** Bit definition for ADC_OFR3 register ********************/ -#define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFF) /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ -#define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001) /*!< ADC OFFSET3 bit 0 */ -#define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002) /*!< ADC OFFSET3 bit 1 */ -#define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004) /*!< ADC OFFSET3 bit 2 */ -#define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008) /*!< ADC OFFSET3 bit 3 */ -#define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010) /*!< ADC OFFSET3 bit 4 */ -#define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020) /*!< ADC OFFSET3 bit 5 */ -#define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040) /*!< ADC OFFSET3 bit 6 */ -#define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080) /*!< ADC OFFSET3 bit 7 */ -#define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100) /*!< ADC OFFSET3 bit 8 */ -#define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200) /*!< ADC OFFSET3 bit 9 */ -#define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) /*!< ADC OFFSET3 bit 10 */ -#define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) /*!< ADC OFFSET3 bit 11 */ - -#define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 3 */ -#define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET3_CH bit 0 */ -#define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET3_CH bit 1 */ -#define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET3_CH bit 2 */ -#define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET3_CH bit 3 */ -#define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET3_CH bit 4 */ - -#define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) /*!< ADC offset 3 enable */ - -/******************** Bit definition for ADC_OFR4 register ********************/ -#define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFF) /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ -#define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001) /*!< ADC OFFSET4 bit 0 */ -#define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002) /*!< ADC OFFSET4 bit 1 */ -#define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004) /*!< ADC OFFSET4 bit 2 */ -#define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008) /*!< ADC OFFSET4 bit 3 */ -#define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010) /*!< ADC OFFSET4 bit 4 */ -#define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020) /*!< ADC OFFSET4 bit 5 */ -#define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040) /*!< ADC OFFSET4 bit 6 */ -#define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080) /*!< ADC OFFSET4 bit 7 */ -#define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100) /*!< ADC OFFSET4 bit 8 */ -#define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200) /*!< ADC OFFSET4 bit 9 */ -#define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) /*!< ADC OFFSET4 bit 10 */ -#define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) /*!< ADC OFFSET4 bit 11 */ - -#define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 4 */ -#define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET4_CH bit 0 */ -#define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET4_CH bit 1 */ -#define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET4_CH bit 2 */ -#define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET4_CH bit 3 */ -#define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET4_CH bit 4 */ - -#define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) /*!< ADC offset 4 enable */ - -/******************** Bit definition for ADC_JDR1 register ********************/ -#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */ -#define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */ -#define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */ -#define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */ -#define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */ -#define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */ -#define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */ -#define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */ -#define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */ -#define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */ -#define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */ -#define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */ -#define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */ -#define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */ -#define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */ -#define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */ -#define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */ - -/******************** Bit definition for ADC_JDR2 register ********************/ -#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */ -#define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */ -#define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */ -#define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */ -#define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */ -#define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */ -#define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */ -#define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */ -#define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */ -#define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */ -#define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */ -#define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */ -#define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */ -#define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */ -#define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */ -#define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */ -#define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */ - -/******************** Bit definition for ADC_JDR3 register ********************/ -#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */ -#define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */ -#define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */ -#define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */ -#define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */ -#define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */ -#define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */ -#define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */ -#define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */ -#define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */ -#define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */ -#define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */ -#define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */ -#define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */ -#define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */ -#define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */ -#define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */ - -/******************** Bit definition for ADC_JDR4 register ********************/ -#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */ -#define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */ -#define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */ -#define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */ -#define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */ -#define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */ -#define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */ -#define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */ -#define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */ -#define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */ -#define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */ -#define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */ -#define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */ -#define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */ -#define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */ -#define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */ -#define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */ - -/******************** Bit definition for ADC_AWD2CR register ********************/ -#define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */ -#define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000002) /*!< ADC AWD2CH bit 0 */ -#define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000004) /*!< ADC AWD2CH bit 1 */ -#define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000008) /*!< ADC AWD2CH bit 2 */ -#define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000010) /*!< ADC AWD2CH bit 3 */ -#define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000020) /*!< ADC AWD2CH bit 4 */ -#define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000040) /*!< ADC AWD2CH bit 5 */ -#define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000080) /*!< ADC AWD2CH bit 6 */ -#define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000100) /*!< ADC AWD2CH bit 7 */ -#define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000200) /*!< ADC AWD2CH bit 8 */ -#define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000400) /*!< ADC AWD2CH bit 9 */ -#define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000800) /*!< ADC AWD2CH bit 10 */ -#define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00001000) /*!< ADC AWD2CH bit 11 */ -#define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00002000) /*!< ADC AWD2CH bit 12 */ -#define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00004000) /*!< ADC AWD2CH bit 13 */ -#define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00008000) /*!< ADC AWD2CH bit 14 */ -#define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00010000) /*!< ADC AWD2CH bit 15 */ -#define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00020000) /*!< ADC AWD2CH bit 16 */ -#define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00030000) /*!< ADC AWD2CH bit 17 */ - -/******************** Bit definition for ADC_AWD3CR register ********************/ -#define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */ -#define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000002) /*!< ADC AWD3CH bit 0 */ -#define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000004) /*!< ADC AWD3CH bit 1 */ -#define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000008) /*!< ADC AWD3CH bit 2 */ -#define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000010) /*!< ADC AWD3CH bit 3 */ -#define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000020) /*!< ADC AWD3CH bit 4 */ -#define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000040) /*!< ADC AWD3CH bit 5 */ -#define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000080) /*!< ADC AWD3CH bit 6 */ -#define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000100) /*!< ADC AWD3CH bit 7 */ -#define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000200) /*!< ADC AWD3CH bit 8 */ -#define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000400) /*!< ADC AWD3CH bit 9 */ -#define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000800) /*!< ADC AWD3CH bit 10 */ -#define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00001000) /*!< ADC AWD3CH bit 11 */ -#define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00002000) /*!< ADC AWD3CH bit 12 */ -#define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00004000) /*!< ADC AWD3CH bit 13 */ -#define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00008000) /*!< ADC AWD3CH bit 14 */ -#define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00010000) /*!< ADC AWD3CH bit 15 */ -#define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00020000) /*!< ADC AWD3CH bit 16 */ -#define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00030000) /*!< ADC AWD3CH bit 17 */ - -/******************** Bit definition for ADC_DIFSEL register ********************/ -#define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFE) /*!< ADC differential modes for channels 1 to 18 */ -#define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) /*!< ADC DIFSEL bit 0 */ -#define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) /*!< ADC DIFSEL bit 1 */ -#define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) /*!< ADC DIFSEL bit 2 */ -#define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) /*!< ADC DIFSEL bit 3 */ -#define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) /*!< ADC DIFSEL bit 4 */ -#define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) /*!< ADC DIFSEL bit 5 */ -#define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) /*!< ADC DIFSEL bit 6 */ -#define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) /*!< ADC DIFSEL bit 7 */ -#define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) /*!< ADC DIFSEL bit 8 */ -#define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) /*!< ADC DIFSEL bit 9 */ -#define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /*!< ADC DIFSEL bit 10 */ -#define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /*!< ADC DIFSEL bit 11 */ -#define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /*!< ADC DIFSEL bit 12 */ -#define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /*!< ADC DIFSEL bit 13 */ -#define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /*!< ADC DIFSEL bit 14 */ -#define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /*!< ADC DIFSEL bit 15 */ -#define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /*!< ADC DIFSEL bit 16 */ -#define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00030000) /*!< ADC DIFSEL bit 17 */ - -/******************** Bit definition for ADC_CALFACT register ********************/ -#define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007F) /*!< ADC calibration factors in single-ended mode */ -#define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) /*!< ADC CALFACT_S bit 0 */ -#define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) /*!< ADC CALFACT_S bit 1 */ -#define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) /*!< ADC CALFACT_S bit 2 */ -#define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) /*!< ADC CALFACT_S bit 3 */ -#define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) /*!< ADC CALFACT_S bit 4 */ -#define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) /*!< ADC CALFACT_S bit 5 */ -#define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) /*!< ADC CALFACT_S bit 6 */ -#define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000) /*!< ADC calibration factors in differential mode */ -#define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) /*!< ADC CALFACT_D bit 0 */ -#define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) /*!< ADC CALFACT_D bit 1 */ -#define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) /*!< ADC CALFACT_D bit 2 */ -#define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) /*!< ADC CALFACT_D bit 3 */ -#define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) /*!< ADC CALFACT_D bit 4 */ -#define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) /*!< ADC CALFACT_D bit 5 */ -#define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) /*!< ADC CALFACT_D bit 6 */ - -/************************* ADC Common registers *****************************/ -/******************** Bit definition for ADC12_CSR register ********************/ -#define ADC12_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */ -#define ADC12_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */ -#define ADC12_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */ -#define ADC12_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */ -#define ADC12_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */ -#define ADC12_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */ -#define ADC12_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */ -#define ADC12_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */ -#define ADC12_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */ -#define ADC12_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */ -#define ADC12_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */ -#define ADC12_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */ -#define ADC12_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */ -#define ADC12_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */ -#define ADC12_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */ -#define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */ -#define ADC12_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */ -#define ADC12_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */ -#define ADC12_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */ -#define ADC12_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */ -#define ADC12_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */ -#define ADC12_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */ - -/******************** Bit definition for ADC34_CSR register ********************/ -#define ADC34_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */ -#define ADC34_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */ -#define ADC34_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */ -#define ADC34_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */ -#define ADC34_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */ -#define ADC34_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */ -#define ADC34_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */ -#define ADC34_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */ -#define ADC34_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */ -#define ADC34_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */ -#define ADC34_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */ -#define ADC34_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */ -#define ADC34_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */ -#define ADC34_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */ -#define ADC34_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */ -#define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */ -#define ADC34_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */ -#define ADC34_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */ -#define ADC34_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */ -#define ADC34_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */ -#define ADC34_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */ -#define ADC34_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */ - -/******************** Bit definition for ADC_CCR register ********************/ -#define ADC12_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */ -#define ADC12_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */ -#define ADC12_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */ -#define ADC12_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */ -#define ADC12_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */ -#define ADC12_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */ -#define ADC12_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */ -#define ADC12_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */ -#define ADC12_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */ -#define ADC12_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */ -#define ADC12_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */ -#define ADC12_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */ -#define ADC12_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */ -#define ADC12_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */ -#define ADC12_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */ -#define ADC12_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */ -#define ADC12_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */ -#define ADC12_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */ -#define ADC12_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */ -#define ADC12_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */ -#define ADC12_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */ - -/******************** Bit definition for ADC_CCR register ********************/ -#define ADC34_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */ -#define ADC34_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */ -#define ADC34_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */ -#define ADC34_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */ -#define ADC34_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */ -#define ADC34_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */ - -#define ADC34_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */ -#define ADC34_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */ -#define ADC34_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */ -#define ADC34_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */ -#define ADC34_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */ - -#define ADC34_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */ -#define ADC34_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */ -#define ADC34_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */ -#define ADC34_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */ - -#define ADC34_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */ -#define ADC34_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */ -#define ADC34_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */ - -#define ADC34_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */ - -/******************** Bit definition for ADC_CDR register ********************/ -#define ADC12_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */ -#define ADC12_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */ -#define ADC12_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */ -#define ADC12_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */ -#define ADC12_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */ -#define ADC12_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */ -#define ADC12_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */ -#define ADC12_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */ -#define ADC12_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */ -#define ADC12_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */ -#define ADC12_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */ -#define ADC12_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */ -#define ADC12_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */ -#define ADC12_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */ -#define ADC12_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */ -#define ADC12_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */ -#define ADC12_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */ - -#define ADC12_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */ -#define ADC12_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */ -#define ADC12_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */ -#define ADC12_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */ -#define ADC12_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */ -#define ADC12_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */ -#define ADC12_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */ -#define ADC12_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */ -#define ADC12_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */ -#define ADC12_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */ -#define ADC12_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */ -#define ADC12_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */ -#define ADC12_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */ -#define ADC12_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */ -#define ADC12_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */ -#define ADC12_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */ -#define ADC12_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */ - -/******************** Bit definition for ADC_CDR register ********************/ -#define ADC34_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */ -#define ADC34_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */ -#define ADC34_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */ -#define ADC34_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */ -#define ADC34_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */ -#define ADC34_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */ -#define ADC34_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */ -#define ADC34_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */ -#define ADC34_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */ -#define ADC34_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */ -#define ADC34_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */ -#define ADC34_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */ -#define ADC34_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */ -#define ADC34_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */ -#define ADC34_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */ -#define ADC34_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */ -#define ADC34_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */ - -#define ADC34_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */ -#define ADC34_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */ -#define ADC34_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */ -#define ADC34_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */ -#define ADC34_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */ -#define ADC34_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */ -#define ADC34_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */ -#define ADC34_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */ -#define ADC34_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */ -#define ADC34_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */ -#define ADC34_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */ -#define ADC34_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */ -#define ADC34_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */ -#define ADC34_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */ -#define ADC34_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */ -#define ADC34_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */ -#define ADC34_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */ - -/******************************************************************************/ -/* */ -/* Analog Comparators (COMP) */ -/* */ -/******************************************************************************/ -/********************** Bit definition for COMP1_CSR register ***************/ -#define COMP1_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */ -#define COMP1_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */ -#define COMP1_CSR_COMP1MODE ((uint32_t)0x0000000C) /*!< COMP1 power mode */ -#define COMP1_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */ -#define COMP1_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */ -#define COMP1_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */ -#define COMP1_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */ -#define COMP1_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */ -#define COMP1_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */ -#define COMP1_CSR_COMP1NONINSEL ((uint32_t)0x00000080) /*!< COMP1 non inverting input select */ -#define COMP1_CSR_COMP1OUTSEL ((uint32_t)0x00003C00) /*!< COMP1 output select */ -#define COMP1_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP1 output select bit 0 */ -#define COMP1_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP1 output select bit 1 */ -#define COMP1_CSR_COMP1OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP1 output select bit 2 */ -#define COMP1_CSR_COMP1OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP1 output select bit 3 */ -#define COMP1_CSR_COMP1POL ((uint32_t)0x00008000) /*!< COMP1 output polarity */ -#define COMP1_CSR_COMP1HYST ((uint32_t)0x00030000) /*!< COMP1 hysteresis */ -#define COMP1_CSR_COMP1HYST_0 ((uint32_t)0x00010000) /*!< COMP1 hysteresis bit 0 */ -#define COMP1_CSR_COMP1HYST_1 ((uint32_t)0x00020000) /*!< COMP1 hysteresis bit 1 */ -#define COMP1_CSR_COMP1BLANKING ((uint32_t)0x000C0000) /*!< COMP1 blanking */ -#define COMP1_CSR_COMP1BLANKING_0 ((uint32_t)0x00040000) /*!< COMP1 blanking bit 0 */ -#define COMP1_CSR_COMP1BLANKING_1 ((uint32_t)0x00080000) /*!< COMP1 blanking bit 1 */ -#define COMP1_CSR_COMP1BLANKING_2 ((uint32_t)0x00100000) /*!< COMP1 blanking bit 2 */ -#define COMP1_CSR_COMP1OUT ((uint32_t)0x40000000) /*!< COMP1 output level */ -#define COMP1_CSR_COMP1LOCK ((uint32_t)0x80000000) /*!< COMP1 lock */ - -/********************** Bit definition for COMP2_CSR register ***************/ -#define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */ -#define COMP2_CSR_COMP2MODE ((uint32_t)0x0000000C) /*!< COMP2 power mode */ -#define COMP2_CSR_COMP2MODE_0 ((uint32_t)0x00000004) /*!< COMP2 power mode bit 0 */ -#define COMP2_CSR_COMP2MODE_1 ((uint32_t)0x00000008) /*!< COMP2 power mode bit 1 */ -#define COMP2_CSR_COMP2INSEL ((uint32_t)0x00000070) /*!< COMP2 inverting input select */ -#define COMP2_CSR_COMP2INSEL_0 ((uint32_t)0x00000010) /*!< COMP2 inverting input select bit 0 */ -#define COMP2_CSR_COMP2INSEL_1 ((uint32_t)0x00000020) /*!< COMP2 inverting input select bit 1 */ -#define COMP2_CSR_COMP2INSEL_2 ((uint32_t)0x00000040) /*!< COMP2 inverting input select bit 2 */ -#define COMP2_CSR_COMP2NONINSEL ((uint32_t)0x00000080) /*!< COMP2 non inverting input select */ -#define COMP2_CSR_COMP2WNDWEN ((uint32_t)0x00000200) /*!< COMP2 window mode enable */ -#define COMP2_CSR_COMP2OUTSEL ((uint32_t)0x00003C00) /*!< COMP2 output select */ -#define COMP2_CSR_COMP2OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP2 output select bit 0 */ -#define COMP2_CSR_COMP2OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP2 output select bit 1 */ -#define COMP2_CSR_COMP2OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP2 output select bit 2 */ -#define COMP2_CSR_COMP2OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP2 output select bit 3 */ -#define COMP2_CSR_COMP2POL ((uint32_t)0x00008000) /*!< COMP2 output polarity */ -#define COMP2_CSR_COMP2HYST ((uint32_t)0x00030000) /*!< COMP2 hysteresis */ -#define COMP2_CSR_COMP2HYST_0 ((uint32_t)0x00010000) /*!< COMP2 hysteresis bit 0 */ -#define COMP2_CSR_COMP2HYST_1 ((uint32_t)0x00020000) /*!< COMP2 hysteresis bit 1 */ -#define COMP2_CSR_COMP2BLANKING ((uint32_t)0x000C0000) /*!< COMP2 blanking */ -#define COMP2_CSR_COMP2BLANKING_0 ((uint32_t)0x00040000) /*!< COMP2 blanking bit 0 */ -#define COMP2_CSR_COMP2BLANKING_1 ((uint32_t)0x00080000) /*!< COMP2 blanking bit 1 */ -#define COMP2_CSR_COMP2BLANKING_2 ((uint32_t)0x00100000) /*!< COMP2 blanking bit 2 */ -#define COMP2_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */ -#define COMP2_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */ - -/********************** Bit definition for COMP3_CSR register ***************/ -#define COMP3_CSR_COMP3EN ((uint32_t)0x00000001) /*!< COMP3 enable */ -#define COMP3_CSR_COMP3MODE ((uint32_t)0x0000000C) /*!< COMP3 power mode */ -#define COMP3_CSR_COMP3MODE_0 ((uint32_t)0x00000004) /*!< COMP3 power mode bit 0 */ -#define COMP3_CSR_COMP3MODE_1 ((uint32_t)0x00000008) /*!< COMP3 power mode bit 1 */ -#define COMP3_CSR_COMP3INSEL ((uint32_t)0x00000070) /*!< COMP3 inverting input select */ -#define COMP3_CSR_COMP3INSEL_0 ((uint32_t)0x00000010) /*!< COMP3 inverting input select bit 0 */ -#define COMP3_CSR_COMP3INSEL_1 ((uint32_t)0x00000020) /*!< COMP3 inverting input select bit 1 */ -#define COMP3_CSR_COMP3INSEL_2 ((uint32_t)0x00000040) /*!< COMP3 inverting input select bit 2 */ -#define COMP3_CSR_COMP3NONINSEL ((uint32_t)0x00000080) /*!< COMP3 non inverting input select */ -#define COMP3_CSR_COMP3OUTSEL ((uint32_t)0x00003C00) /*!< COMP3 output select */ -#define COMP3_CSR_COMP3OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP3 output select bit 0 */ -#define COMP3_CSR_COMP3OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP3 output select bit 1 */ -#define COMP3_CSR_COMP3OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP3 output select bit 2 */ -#define COMP3_CSR_COMP3OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP3 output select bit 3 */ -#define COMP3_CSR_COMP3POL ((uint32_t)0x00008000) /*!< COMP3 output polarity */ -#define COMP3_CSR_COMP3HYST ((uint32_t)0x00030000) /*!< COMP3 hysteresis */ -#define COMP3_CSR_COMP3HYST_0 ((uint32_t)0x00010000) /*!< COMP3 hysteresis bit 0 */ -#define COMP3_CSR_COMP3HYST_1 ((uint32_t)0x00020000) /*!< COMP3 hysteresis bit 1 */ -#define COMP3_CSR_COMP3BLANKING ((uint32_t)0x000C0000) /*!< COMP3 blanking */ -#define COMP3_CSR_COMP3BLANKING_0 ((uint32_t)0x00040000) /*!< COMP3 blanking bit 0 */ -#define COMP3_CSR_COMP3BLANKING_1 ((uint32_t)0x00080000) /*!< COMP3 blanking bit 1 */ -#define COMP3_CSR_COMP3BLANKING_2 ((uint32_t)0x00100000) /*!< COMP3 blanking bit 2 */ -#define COMP3_CSR_COMP3OUT ((uint32_t)0x40000000) /*!< COMP3 output level */ -#define COMP3_CSR_COMP3LOCK ((uint32_t)0x80000000) /*!< COMP3 lock */ - -/********************** Bit definition for COMP4_CSR register ***************/ -#define COMP4_CSR_COMP4EN ((uint32_t)0x00000001) /*!< COMP4 enable */ -#define COMP4_CSR_COMP4MODE ((uint32_t)0x0000000C) /*!< COMP4 power mode */ -#define COMP4_CSR_COMP4MODE_0 ((uint32_t)0x00000004) /*!< COMP4 power mode bit 0 */ -#define COMP4_CSR_COMP4MODE_1 ((uint32_t)0x00000008) /*!< COMP4 power mode bit 1 */ -#define COMP4_CSR_COMP4INSEL ((uint32_t)0x00000070) /*!< COMP4 inverting input select */ -#define COMP4_CSR_COMP4INSEL_0 ((uint32_t)0x00000010) /*!< COMP4 inverting input select bit 0 */ -#define COMP4_CSR_COMP4INSEL_1 ((uint32_t)0x00000020) /*!< COMP4 inverting input select bit 1 */ -#define COMP4_CSR_COMP4INSEL_2 ((uint32_t)0x00000040) /*!< COMP4 inverting input select bit 2 */ -#define COMP4_CSR_COMP4NONINSEL ((uint32_t)0x00000080) /*!< COMP4 non inverting input select */ -#define COMP4_CSR_COMP4WNDWEN ((uint32_t)0x00000200) /*!< COMP4 window mode enable */ -#define COMP4_CSR_COMP4OUTSEL ((uint32_t)0x00003C00) /*!< COMP4 output select */ -#define COMP4_CSR_COMP4OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP4 output select bit 0 */ -#define COMP4_CSR_COMP4OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP4 output select bit 1 */ -#define COMP4_CSR_COMP4OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP4 output select bit 2 */ -#define COMP4_CSR_COMP4OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP4 output select bit 3 */ -#define COMP4_CSR_COMP4POL ((uint32_t)0x00008000) /*!< COMP4 output polarity */ -#define COMP4_CSR_COMP4HYST ((uint32_t)0x00030000) /*!< COMP4 hysteresis */ -#define COMP4_CSR_COMP4HYST_0 ((uint32_t)0x00010000) /*!< COMP4 hysteresis bit 0 */ -#define COMP4_CSR_COMP4HYST_1 ((uint32_t)0x00020000) /*!< COMP4 hysteresis bit 1 */ -#define COMP4_CSR_COMP4BLANKING ((uint32_t)0x000C0000) /*!< COMP4 blanking */ -#define COMP4_CSR_COMP4BLANKING_0 ((uint32_t)0x00040000) /*!< COMP4 blanking bit 0 */ -#define COMP4_CSR_COMP4BLANKING_1 ((uint32_t)0x00080000) /*!< COMP4 blanking bit 1 */ -#define COMP4_CSR_COMP4BLANKING_2 ((uint32_t)0x00100000) /*!< COMP4 blanking bit 2 */ -#define COMP4_CSR_COMP4OUT ((uint32_t)0x40000000) /*!< COMP4 output level */ -#define COMP4_CSR_COMP4LOCK ((uint32_t)0x80000000) /*!< COMP4 lock */ - -/********************** Bit definition for COMP5_CSR register ***************/ -#define COMP5_CSR_COMP5EN ((uint32_t)0x00000001) /*!< COMP5 enable */ -#define COMP5_CSR_COMP5MODE ((uint32_t)0x0000000C) /*!< COMP5 power mode */ -#define COMP5_CSR_COMP5MODE_0 ((uint32_t)0x00000004) /*!< COMP5 power mode bit 0 */ -#define COMP5_CSR_COMP5MODE_1 ((uint32_t)0x00000008) /*!< COMP5 power mode bit 1 */ -#define COMP5_CSR_COMP5INSEL ((uint32_t)0x00000070) /*!< COMP5 inverting input select */ -#define COMP5_CSR_COMP5INSEL_0 ((uint32_t)0x00000010) /*!< COMP5 inverting input select bit 0 */ -#define COMP5_CSR_COMP5INSEL_1 ((uint32_t)0x00000020) /*!< COMP5 inverting input select bit 1 */ -#define COMP5_CSR_COMP5INSEL_2 ((uint32_t)0x00000040) /*!< COMP5 inverting input select bit 2 */ -#define COMP5_CSR_COMP5NONINSEL ((uint32_t)0x00000080) /*!< COMP5 non inverting input select */ -#define COMP5_CSR_COMP5OUTSEL ((uint32_t)0x00003C00) /*!< COMP5 output select */ -#define COMP5_CSR_COMP5OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP5 output select bit 0 */ -#define COMP5_CSR_COMP5OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP5 output select bit 1 */ -#define COMP5_CSR_COMP5OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP5 output select bit 2 */ -#define COMP5_CSR_COMP5OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP5 output select bit 3 */ -#define COMP5_CSR_COMP5POL ((uint32_t)0x00008000) /*!< COMP5 output polarity */ -#define COMP5_CSR_COMP5HYST ((uint32_t)0x00030000) /*!< COMP5 hysteresis */ -#define COMP5_CSR_COMP5HYST_0 ((uint32_t)0x00010000) /*!< COMP5 hysteresis bit 0 */ -#define COMP5_CSR_COMP5HYST_1 ((uint32_t)0x00020000) /*!< COMP5 hysteresis bit 1 */ -#define COMP5_CSR_COMP5BLANKING ((uint32_t)0x000C0000) /*!< COMP5 blanking */ -#define COMP5_CSR_COMP5BLANKING_0 ((uint32_t)0x00040000) /*!< COMP5 blanking bit 0 */ -#define COMP5_CSR_COMP5BLANKING_1 ((uint32_t)0x00080000) /*!< COMP5 blanking bit 1 */ -#define COMP5_CSR_COMP5BLANKING_2 ((uint32_t)0x00100000) /*!< COMP5 blanking bit 2 */ -#define COMP5_CSR_COMP5OUT ((uint32_t)0x40000000) /*!< COMP5 output level */ -#define COMP5_CSR_COMP5LOCK ((uint32_t)0x80000000) /*!< COMP5 lock */ - -/********************** Bit definition for COMP6_CSR register ***************/ -#define COMP6_CSR_COMP6EN ((uint32_t)0x00000001) /*!< COMP6 enable */ -#define COMP6_CSR_COMP6MODE ((uint32_t)0x0000000C) /*!< COMP6 power mode */ -#define COMP6_CSR_COMP6MODE_0 ((uint32_t)0x00000004) /*!< COMP6 power mode bit 0 */ -#define COMP6_CSR_COMP6MODE_1 ((uint32_t)0x00000008) /*!< COMP6 power mode bit 1 */ -#define COMP6_CSR_COMP6INSEL ((uint32_t)0x00000070) /*!< COMP6 inverting input select */ -#define COMP6_CSR_COMP6INSEL_0 ((uint32_t)0x00000010) /*!< COMP6 inverting input select bit 0 */ -#define COMP6_CSR_COMP6INSEL_1 ((uint32_t)0x00000020) /*!< COMP6 inverting input select bit 1 */ -#define COMP6_CSR_COMP6INSEL_2 ((uint32_t)0x00000040) /*!< COMP6 inverting input select bit 2 */ -#define COMP6_CSR_COMP6NONINSEL ((uint32_t)0x00000080) /*!< COMP6 non inverting input select */ -#define COMP6_CSR_COMP6WNDWEN ((uint32_t)0x00000200) /*!< COMP6 window mode enable */ -#define COMP6_CSR_COMP6OUTSEL ((uint32_t)0x00003C00) /*!< COMP6 output select */ -#define COMP6_CSR_COMP6OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP6 output select bit 0 */ -#define COMP6_CSR_COMP6OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP6 output select bit 1 */ -#define COMP6_CSR_COMP6OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP6 output select bit 2 */ -#define COMP6_CSR_COMP6OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP6 output select bit 3 */ -#define COMP6_CSR_COMP6POL ((uint32_t)0x00008000) /*!< COMP6 output polarity */ -#define COMP6_CSR_COMP6HYST ((uint32_t)0x00030000) /*!< COMP6 hysteresis */ -#define COMP6_CSR_COMP6HYST_0 ((uint32_t)0x00010000) /*!< COMP6 hysteresis bit 0 */ -#define COMP6_CSR_COMP6HYST_1 ((uint32_t)0x00020000) /*!< COMP6 hysteresis bit 1 */ -#define COMP6_CSR_COMP6BLANKING ((uint32_t)0x000C0000) /*!< COMP6 blanking */ -#define COMP6_CSR_COMP6BLANKING_0 ((uint32_t)0x00040000) /*!< COMP6 blanking bit 0 */ -#define COMP6_CSR_COMP6BLANKING_1 ((uint32_t)0x00080000) /*!< COMP6 blanking bit 1 */ -#define COMP6_CSR_COMP6BLANKING_2 ((uint32_t)0x00100000) /*!< COMP6 blanking bit 2 */ -#define COMP6_CSR_COMP6OUT ((uint32_t)0x40000000) /*!< COMP6 output level */ -#define COMP6_CSR_COMP6LOCK ((uint32_t)0x80000000) /*!< COMP6 lock */ - -/********************** Bit definition for COMP7_CSR register ***************/ -#define COMP7_CSR_COMP7EN ((uint32_t)0x00000001) /*!< COMP7 enable */ -#define COMP7_CSR_COMP7MODE ((uint32_t)0x0000000C) /*!< COMP7 power mode */ -#define COMP7_CSR_COMP7MODE_0 ((uint32_t)0x00000004) /*!< COMP7 power mode bit 0 */ -#define COMP7_CSR_COMP7MODE_1 ((uint32_t)0x00000008) /*!< COMP7 power mode bit 1 */ -#define COMP7_CSR_COMP7INSEL ((uint32_t)0x00000070) /*!< COMP7 inverting input select */ -#define COMP7_CSR_COMP7INSEL_0 ((uint32_t)0x00000010) /*!< COMP7 inverting input select bit 0 */ -#define COMP7_CSR_COMP7INSEL_1 ((uint32_t)0x00000020) /*!< COMP7 inverting input select bit 1 */ -#define COMP7_CSR_COMP7INSEL_2 ((uint32_t)0x00000040) /*!< COMP7 inverting input select bit 2 */ -#define COMP7_CSR_COMP7NONINSEL ((uint32_t)0x00000080) /*!< COMP7 non inverting input select */ -#define COMP7_CSR_COMP7OUTSEL ((uint32_t)0x00003C00) /*!< COMP7 output select */ -#define COMP7_CSR_COMP7OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP7 output select bit 0 */ -#define COMP7_CSR_COMP7OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP7 output select bit 1 */ -#define COMP7_CSR_COMP7OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP7 output select bit 2 */ -#define COMP7_CSR_COMP7OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP7 output select bit 3 */ -#define COMP7_CSR_COMP7POL ((uint32_t)0x00008000) /*!< COMP7 output polarity */ -#define COMP7_CSR_COMP7HYST ((uint32_t)0x00030000) /*!< COMP7 hysteresis */ -#define COMP7_CSR_COMP7HYST_0 ((uint32_t)0x00010000) /*!< COMP7 hysteresis bit 0 */ -#define COMP7_CSR_COMP7HYST_1 ((uint32_t)0x00020000) /*!< COMP7 hysteresis bit 1 */ -#define COMP7_CSR_COMP7BLANKING ((uint32_t)0x000C0000) /*!< COMP7 blanking */ -#define COMP7_CSR_COMP7BLANKING_0 ((uint32_t)0x00040000) /*!< COMP7 blanking bit 0 */ -#define COMP7_CSR_COMP7BLANKING_1 ((uint32_t)0x00080000) /*!< COMP7 blanking bit 1 */ -#define COMP7_CSR_COMP7BLANKING_2 ((uint32_t)0x00100000) /*!< COMP7 blanking bit 2 */ -#define COMP7_CSR_COMP7OUT ((uint32_t)0x40000000) /*!< COMP7 output level */ -#define COMP7_CSR_COMP7LOCK ((uint32_t)0x80000000) /*!< COMP7 lock */ - -/********************** Bit definition for COMP_CSR register ****************/ -#define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */ -#define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */ -#define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */ -#define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */ -#define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */ -#define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /*!< COMPx inverting input select */ -#define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */ -#define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */ -#define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */ -#define COMP_CSR_COMPxNONINSEL ((uint32_t)0x00000080) /*!< COMPx non inverting input select */ -#define COMP_CSR_COMPxWNDWEN ((uint32_t)0x00000200) /*!< COMPx window mode enable */ -#define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00003C00) /*!< COMPx output select */ -#define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000400) /*!< COMPx output select bit 0 */ -#define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000800) /*!< COMPx output select bit 1 */ -#define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00001000) /*!< COMPx output select bit 2 */ -#define COMP_CSR_COMPxOUTSEL_3 ((uint32_t)0x00002000) /*!< COMPx output select bit 3 */ -#define COMP_CSR_COMPxPOL ((uint32_t)0x00008000) /*!< COMPx output polarity */ -#define COMP_CSR_COMPxHYST ((uint32_t)0x00030000) /*!< COMPx hysteresis */ -#define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00010000) /*!< COMPx hysteresis bit 0 */ -#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00020000) /*!< COMPx hysteresis bit 1 */ -#define COMP_CSR_COMPxBLANKING ((uint32_t)0x000C0000) /*!< COMPx blanking */ -#define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */ -#define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */ -#define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */ -#define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /*!< COMPx inverting input select bit 3 */ -#define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /*!< COMPx output level */ -#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */ - -/******************************************************************************/ -/* */ -/* Operational Amplifier (OPAMP) */ -/* */ -/******************************************************************************/ -/********************* Bit definition for OPAMP1_CSR register ***************/ -#define OPAMP1_CSR_OPAMP1EN ((uint32_t)0x00000001) /*!< OPAMP1 enable */ -#define OPAMP1_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */ -#define OPAMP1_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */ -#define OPAMP1_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define OPAMP1_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */ -#define OPAMP1_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */ -#define OPAMP1_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define OPAMP1_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define OPAMP1_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */ -#define OPAMP1_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */ -#define OPAMP1_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */ -#define OPAMP1_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define OPAMP1_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define OPAMP1_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */ -#define OPAMP1_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */ -#define OPAMP1_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define OPAMP1_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define OPAMP1_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */ -#define OPAMP1_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define OPAMP1_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */ -#define OPAMP1_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */ -#define OPAMP1_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */ -#define OPAMP1_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */ -#define OPAMP1_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */ -#define OPAMP1_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */ -#define OPAMP1_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */ -#define OPAMP1_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP output status flag */ -#define OPAMP1_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */ - -/********************* Bit definition for OPAMP2_CSR register ***************/ -#define OPAMP2_CSR_OPAMP2EN ((uint32_t)0x00000001) /*!< OPAMP2 enable */ -#define OPAMP2_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */ -#define OPAMP2_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */ -#define OPAMP2_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define OPAMP2_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */ -#define OPAMP2_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */ -#define OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define OPAMP2_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */ -#define OPAMP2_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */ -#define OPAMP2_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */ -#define OPAMP2_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define OPAMP2_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define OPAMP2_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */ -#define OPAMP2_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */ -#define OPAMP2_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define OPAMP2_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define OPAMP2_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */ -#define OPAMP2_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define OPAMP2_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */ -#define OPAMP2_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */ -#define OPAMP2_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */ -#define OPAMP2_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */ -#define OPAMP2_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */ -#define OPAMP2_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */ -#define OPAMP2_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */ -#define OPAMP2_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP output status flag */ -#define OPAMP2_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */ - -/********************* Bit definition for OPAMP3_CSR register ***************/ -#define OPAMP3_CSR_OPAMP3EN ((uint32_t)0x00000001) /*!< OPAMP3 enable */ -#define OPAMP3_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */ -#define OPAMP3_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */ -#define OPAMP3_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define OPAMP3_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */ -#define OPAMP3_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */ -#define OPAMP3_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define OPAMP3_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define OPAMP3_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */ -#define OPAMP3_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */ -#define OPAMP3_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */ -#define OPAMP3_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define OPAMP3_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define OPAMP3_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */ -#define OPAMP3_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */ -#define OPAMP3_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define OPAMP3_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define OPAMP3_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */ -#define OPAMP3_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define OPAMP3_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */ -#define OPAMP3_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */ -#define OPAMP3_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */ -#define OPAMP3_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */ -#define OPAMP3_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */ -#define OPAMP3_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */ -#define OPAMP3_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */ -#define OPAMP3_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP output status flag */ -#define OPAMP3_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */ - -/********************* Bit definition for OPAMP4_CSR register ***************/ -#define OPAMP4_CSR_OPAMP4EN ((uint32_t)0x00000001) /*!< OPAMP4 enable */ -#define OPAMP4_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */ -#define OPAMP4_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */ -#define OPAMP4_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define OPAMP4_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */ -#define OPAMP4_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */ -#define OPAMP4_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define OPAMP4_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define OPAMP4_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */ -#define OPAMP4_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */ -#define OPAMP4_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */ -#define OPAMP4_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define OPAMP4_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define OPAMP4_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */ -#define OPAMP4_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */ -#define OPAMP4_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define OPAMP4_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define OPAMP4_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */ -#define OPAMP4_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define OPAMP4_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */ -#define OPAMP4_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */ -#define OPAMP4_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */ -#define OPAMP4_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */ -#define OPAMP4_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */ -#define OPAMP4_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */ -#define OPAMP4_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */ -#define OPAMP4_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP output status flag */ -#define OPAMP4_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */ - -/********************* Bit definition for OPAMPx_CSR register ***************/ -#define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001) /*!< OPAMP enable */ -#define OPAMP_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */ -#define OPAMP_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */ -#define OPAMP_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define OPAMP_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */ -#define OPAMP_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */ -#define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define OPAMP_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */ -#define OPAMP_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */ -#define OPAMP_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */ -#define OPAMP_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define OPAMP_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define OPAMP_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */ -#define OPAMP_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */ -#define OPAMP_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define OPAMP_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define OPAMP_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */ -#define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */ -#define OPAMP_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */ -#define OPAMP_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */ -#define OPAMP_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */ -#define OPAMP_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */ -#define OPAMP_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */ -#define OPAMP_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */ -#define OPAMP_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP output status flag */ -#define OPAMP_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */ - - -/******************************************************************************/ -/* */ -/* Controller Area Network (CAN ) */ -/* */ -/******************************************************************************/ -/*!<CAN control and status registers */ -/******************* Bit definition for CAN_MCR register ********************/ -#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */ -#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */ -#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */ -#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */ -#define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */ -#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */ -#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */ -#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */ -#define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */ - -/******************* Bit definition for CAN_MSR register ********************/ -#define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */ -#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */ -#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */ -#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */ -#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */ -#define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */ -#define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */ -#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */ -#define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */ - -/******************* Bit definition for CAN_TSR register ********************/ -#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */ -#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */ -#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */ -#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */ -#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */ -#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */ -#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */ -#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */ -#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */ -#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */ -#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */ -#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */ -#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */ -#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */ -#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */ -#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */ - -#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */ -#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */ -#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */ -#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */ - -#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */ -#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */ -#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */ -#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */ - -/******************* Bit definition for CAN_RF0R register *******************/ -#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */ -#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */ -#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */ -#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */ - -/******************* Bit definition for CAN_RF1R register *******************/ -#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */ -#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */ -#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */ -#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */ - -/******************** Bit definition for CAN_IER register *******************/ -#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */ -#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */ -#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */ -#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */ -#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */ -#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */ -#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */ -#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */ -#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */ -#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */ -#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */ -#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */ -#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */ -#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */ - -/******************** Bit definition for CAN_ESR register *******************/ -#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */ -#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */ -#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */ - -#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */ -#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */ -#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */ -#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */ - -#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */ -#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */ - -/******************* Bit definition for CAN_BTR register ********************/ -#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */ -#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */ -#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */ -#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */ -#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */ -#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */ - -/*!<Mailbox registers */ -/****************** Bit definition for CAN_TI0R register ********************/ -#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ -#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ -#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ -#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ -#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ - -/****************** Bit definition for CAN_TDT0R register *******************/ -#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ -#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ -#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ - -/****************** Bit definition for CAN_TDL0R register *******************/ -#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ -#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ -#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ -#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ - -/****************** Bit definition for CAN_TDH0R register *******************/ -#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ -#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ -#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ -#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ - -/******************* Bit definition for CAN_TI1R register *******************/ -#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ -#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ -#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ -#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ -#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_TDT1R register ******************/ -#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ -#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ -#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ - -/******************* Bit definition for CAN_TDL1R register ******************/ -#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ -#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ -#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ -#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ - -/******************* Bit definition for CAN_TDH1R register ******************/ -#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ -#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ -#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ -#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ - -/******************* Bit definition for CAN_TI2R register *******************/ -#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ -#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ -#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ -#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */ -#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_TDT2R register ******************/ -#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ -#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ -#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ - -/******************* Bit definition for CAN_TDL2R register ******************/ -#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ -#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ -#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ -#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ - -/******************* Bit definition for CAN_TDH2R register ******************/ -#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ -#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ -#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ -#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ - -/******************* Bit definition for CAN_RI0R register *******************/ -#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ -#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ -#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ -#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_RDT0R register ******************/ -#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ -#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */ -#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ - -/******************* Bit definition for CAN_RDL0R register ******************/ -#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ -#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ -#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ -#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ - -/******************* Bit definition for CAN_RDH0R register ******************/ -#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ -#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ -#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ -#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ - -/******************* Bit definition for CAN_RI1R register *******************/ -#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ -#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ -#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */ -#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_RDT1R register ******************/ -#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ -#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */ -#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ - -/******************* Bit definition for CAN_RDL1R register ******************/ -#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ -#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ -#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ -#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ - -/******************* Bit definition for CAN_RDH1R register ******************/ -#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ -#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ -#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ -#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ - -/*!<CAN filter registers */ -/******************* Bit definition for CAN_FMR register ********************/ -#define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */ - -/******************* Bit definition for CAN_FM1R register *******************/ -#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */ -#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */ -#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */ -#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */ -#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */ -#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */ -#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */ -#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */ -#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */ -#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */ -#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */ -#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */ -#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */ -#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */ -#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */ - -/******************* Bit definition for CAN_FS1R register *******************/ -#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */ -#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */ -#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */ -#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */ -#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */ -#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */ -#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */ -#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */ -#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */ -#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */ -#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */ -#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */ -#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */ -#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */ -#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */ - -/****************** Bit definition for CAN_FFA1R register *******************/ -#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */ -#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */ -#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */ -#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */ -#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */ -#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */ -#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */ -#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */ -#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */ -#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */ -#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */ -#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */ -#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */ -#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */ -#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */ - -/******************* Bit definition for CAN_FA1R register *******************/ -#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */ -#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */ -#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */ -#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */ -#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */ -#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */ -#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */ -#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */ -#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */ -#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */ -#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */ -#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */ -#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */ -#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */ -#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */ - -/******************* Bit definition for CAN_F0R1 register *******************/ -#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F1R1 register *******************/ -#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F2R1 register *******************/ -#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F3R1 register *******************/ -#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F4R1 register *******************/ -#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F5R1 register *******************/ -#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F6R1 register *******************/ -#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F7R1 register *******************/ -#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F8R1 register *******************/ -#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F9R1 register *******************/ -#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F10R1 register ******************/ -#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F11R1 register ******************/ -#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F12R1 register ******************/ -#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F13R1 register ******************/ -#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F0R2 register *******************/ -#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F1R2 register *******************/ -#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F2R2 register *******************/ -#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F3R2 register *******************/ -#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F4R2 register *******************/ -#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F5R2 register *******************/ -#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F6R2 register *******************/ -#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F7R2 register *******************/ -#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F8R2 register *******************/ -#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F9R2 register *******************/ -#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F10R2 register ******************/ -#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F11R2 register ******************/ -#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F12R2 register ******************/ -#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F13R2 register ******************/ -#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************************************************************************/ -/* */ -/* CRC calculation unit (CRC) */ -/* */ -/******************************************************************************/ -/******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ - -/******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ - -/******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */ -#define CRC_CR_POLSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */ -#define CRC_CR_POLSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */ -#define CRC_CR_POLSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */ -#define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */ -#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */ - -/******************* Bit definition for CRC_INIT register *******************/ -#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */ - -/******************* Bit definition for CRC_POL register ********************/ -#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */ -/******************************************************************************/ -/* */ -/* Digital to Analog Converter (DAC) */ -/* */ -/******************************************************************************/ -/******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */ -#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */ -#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */ - -#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ -#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ -#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */ -#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */ -#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */ -#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */ - -#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ -#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */ -#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */ -#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */ - -#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ -#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */ - -/***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */ -#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */ - -/***************** Bit definition for DAC_DHR12R1 register ******************/ -#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12L1 register ******************/ -#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DHR8R1 register ******************/ -#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12R2 register ******************/ -#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!< DAC channel2 12-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12L2 register ******************/ -#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!< DAC channel2 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DHR8R2 register ******************/ -#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!< DAC channel2 8-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12RD register ******************/ -#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ -#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12LD register ******************/ -#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ -#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DHR8RD register ******************/ -#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */ -#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!< DAC channel2 8-bit Right aligned data */ - -/******************* Bit definition for DAC_DOR1 register *******************/ -#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */ - -/******************* Bit definition for DAC_DOR2 register *******************/ -#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!< DAC channel2 data output */ - -/******************** Bit definition for DAC_SR register ********************/ -#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */ -#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */ - -/******************************************************************************/ -/* */ -/* Debug MCU (DBGMCU) */ -/* */ -/******************************************************************************/ -/******************** Bit definition for DBGMCU_IDCODE register *************/ -#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) -#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) - -/******************** Bit definition for DBGMCU_CR register *****************/ -#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) -#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) -#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) -#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) - -#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) -#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */ -#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */ - -/******************** Bit definition for DBGMCU_APB1_FZ register ************/ -#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) -#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) -#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) -#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) -#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) -#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) -#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) -#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) -#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) -#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) -#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000) - -/******************** Bit definition for DBGMCU_APB2_FZ register ************/ -#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001) -#define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002) -#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00000004) -#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00000008) -#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00000010) - -/******************************************************************************/ -/* */ -/* DMA Controller (DMA) */ -/* */ -/******************************************************************************/ -/******************* Bit definition for DMA_ISR register ********************/ -#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ -#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ -#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ -#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ -#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ -#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ -#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ -#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ -#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ -#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ -#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ -#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ -#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ -#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ -#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ -#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ -#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ -#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ -#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ -#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ -#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ -#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ -#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ -#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ -#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ -#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ -#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ -#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ - -/******************* Bit definition for DMA_IFCR register *******************/ -#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ -#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ -#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ -#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ -#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ -#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ -#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ -#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ -#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ -#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ -#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ -#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ -#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ -#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ -#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ -#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ -#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ -#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ -#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ -#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ -#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ -#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ -#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ -#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ -#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ -#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ -#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ -#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ - -/******************* Bit definition for DMA_CCR register ********************/ -#define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */ -#define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */ -#define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */ -#define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */ -#define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */ -#define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */ - -#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -#define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/ -#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - -#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */ - -/****************** Bit definition for DMA_CNDTR register *******************/ -#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */ - -/****************** Bit definition for DMA_CPAR register ********************/ -#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ - -/****************** Bit definition for DMA_CMAR register ********************/ -#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ - -/******************************************************************************/ -/* */ -/* External Interrupt/Event Controller (EXTI) */ -/* */ -/******************************************************************************/ -/******************* Bit definition for EXTI_IMR register *******************/ -#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ -#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ -#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ -#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ -#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ -#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ -#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ -#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ -#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ -#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ -#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ -#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ -#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ -#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ -#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ -#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ -#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ -#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ -#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ -#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ -#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */ -#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */ -#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */ -#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */ -#define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */ -#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */ -#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */ -#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */ -#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */ - -/******************* Bit definition for EXTI_EMR register *******************/ -#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ -#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ -#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ -#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ -#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ -#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ -#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ -#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ -#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ -#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ -#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ -#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ -#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ -#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ -#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ -#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ -#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ -#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ -#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ -#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ -#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */ -#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */ -#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */ -#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */ -#define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */ -#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */ -#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */ -#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */ -#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */ - -/****************** Bit definition for EXTI_RTSR register *******************/ -#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ -#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ -#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ -#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ -#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ -#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ -#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ -#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ -#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ -#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ -#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ -#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ -#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ -#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ -#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ -#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ -#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ -#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ -#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ -#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */ -#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */ -#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */ -#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */ -#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */ -#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */ -#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */ -#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */ -#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */ - -/****************** Bit definition for EXTI_FTSR register *******************/ -#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ -#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ -#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ -#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ -#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ -#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ -#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ -#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ -#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ -#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ -#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ -#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ -#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ -#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ -#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ -#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ -#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ -#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ -#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ -#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */ -#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */ -#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */ -#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */ -#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */ -#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */ -#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */ -#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */ -#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */ - -/****************** Bit definition for EXTI_SWIER register ******************/ -#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ -#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ -#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ -#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ -#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ -#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ -#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ -#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ -#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ -#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ -#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ -#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ -#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ -#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ -#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ -#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ -#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ -#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ -#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ -#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ -#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */ -#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */ -#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */ -#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */ -#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */ -#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */ -#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */ -#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */ -#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */ - -/******************* Bit definition for EXTI_PR register ********************/ -#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ -#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ -#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ -#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ -#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ -#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ -#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ -#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ -#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ -#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ -#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ -#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ -#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ -#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ -#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ -#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ -#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ -#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ -#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ -#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ -#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */ -#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */ -#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */ -#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */ -#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */ -#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */ -#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */ -#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */ -#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */ - -/******************************************************************************/ -/* */ -/* FLASH */ -/* */ -/******************************************************************************/ -/******************* Bit definition for FLASH_ACR register ******************/ -#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!< LATENCY[2:0] bits (Latency) */ -#define FLASH_ACR_LATENCY_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define FLASH_ACR_LATENCY_1 ((uint8_t)0x02) /*!< Bit 1 */ - -#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!< Flash Half Cycle Access Enable */ -#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!< Prefetch Buffer Enable */ -#define FLASH_ACR_PRFTBS ((uint8_t)0x20) - -/****************** Bit definition for FLASH_KEYR register ******************/ -#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */ - -#define RDP_KEY ((uint16_t)0x00A5) /*!< RDP Key */ -#define FLASH_KEY1 ((uint32_t)0x45670123) /*!< FPEC Key1 */ -#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< FPEC Key2 */ - -/***************** Bit definition for FLASH_OPTKEYR register ****************/ -#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ - -#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */ -#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */ - -/****************** Bit definition for FLASH_SR register *******************/ -#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */ -#define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */ -#define FLASH_SR_WRPERR ((uint32_t)0x00000010) /*!< Write Protection Error */ -#define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */ - -/******************* Bit definition for FLASH_CR register *******************/ -#define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */ -#define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */ -#define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */ -#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */ -#define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */ -#define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */ -#define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */ -#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */ -#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */ -#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */ -#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< OptionBytes Loader Launch */ - -/******************* Bit definition for FLASH_AR register *******************/ -#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ - -/****************** Bit definition for FLASH_OBR register *******************/ -#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */ -#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */ -#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */ - -#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */ -#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */ -#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */ -#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */ - -/****************** Bit definition for FLASH_WRPR register ******************/ -#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ - -/*----------------------------------------------------------------------------*/ - -/****************** Bit definition for OB_RDP register **********************/ -#define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */ -#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */ - -/****************** Bit definition for OB_USER register *********************/ -#define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */ -#define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */ - -/****************** Bit definition for FLASH_WRP0 register ******************/ -#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ -#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRP1 register ******************/ -#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ -#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRP2 register ******************/ -#define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ -#define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRP3 register ******************/ -#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ -#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ -/******************************************************************************/ -/* */ -/* General Purpose I/O (GPIO) */ -/* */ -/******************************************************************************/ -/******************* Bit definition for GPIO_MODER register *****************/ -#define GPIO_MODER_MODER0 ((uint32_t)0x00000003) -#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001) -#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002) -#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C) -#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004) -#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008) -#define GPIO_MODER_MODER2 ((uint32_t)0x00000030) -#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010) -#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020) -#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0) -#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040) -#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080) -#define GPIO_MODER_MODER4 ((uint32_t)0x00000300) -#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100) -#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200) -#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00) -#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400) -#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800) -#define GPIO_MODER_MODER6 ((uint32_t)0x00003000) -#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000) -#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000) -#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000) -#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000) -#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000) -#define GPIO_MODER_MODER8 ((uint32_t)0x00030000) -#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000) -#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000) -#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000) -#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000) -#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000) -#define GPIO_MODER_MODER10 ((uint32_t)0x00300000) -#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000) -#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000) -#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000) -#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000) -#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000) -#define GPIO_MODER_MODER12 ((uint32_t)0x03000000) -#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000) -#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000) -#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000) -#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000) -#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000) -#define GPIO_MODER_MODER14 ((uint32_t)0x30000000) -#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000) -#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000) -#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000) -#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000) -#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000) - - -/****************** Bit definition for GPIO_OTYPER register *****************/ -#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001) -#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002) -#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004) -#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008) -#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010) -#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020) -#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040) -#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080) -#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100) -#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200) -#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400) -#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800) -#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000) -#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000) -#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000) -#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000) - - -/**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003) -#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001) -#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002) -#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C) -#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004) -#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008) -#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030) -#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010) -#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020) -#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0) -#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040) -#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080) -#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300) -#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100) -#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200) -#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00) -#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400) -#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800) -#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000) -#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000) -#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000) -#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000) -#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000) -#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000) -#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000) -#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000) -#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000) -#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000) -#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000) -#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000) -#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000) -#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000) -#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000) -#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000) -#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000) -#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000) -#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000) -#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000) -#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000) -#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000) -#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000) -#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000) -#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000) -#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000) -#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000) -#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000) -#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000) -#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000) - -/******************* Bit definition for GPIO_PUPDR register ******************/ -#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003) -#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001) -#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002) -#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C) -#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004) -#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008) -#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030) -#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010) -#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020) -#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0) -#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040) -#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080) -#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300) -#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100) -#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200) -#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00) -#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400) -#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800) -#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000) -#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000) -#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000) -#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000) -#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000) -#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000) -#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000) -#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000) -#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000) -#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000) -#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000) -#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000) -#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000) -#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000) -#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000) -#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000) -#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000) -#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000) -#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000) -#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000) -#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000) -#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000) -#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000) -#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000) -#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000) -#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000) -#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000) -#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000) -#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000) -#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000) - -/******************* Bit definition for GPIO_IDR register *******************/ -#define GPIO_IDR_0 ((uint32_t)0x00000001) -#define GPIO_IDR_1 ((uint32_t)0x00000002) -#define GPIO_IDR_2 ((uint32_t)0x00000004) -#define GPIO_IDR_3 ((uint32_t)0x00000008) -#define GPIO_IDR_4 ((uint32_t)0x00000010) -#define GPIO_IDR_5 ((uint32_t)0x00000020) -#define GPIO_IDR_6 ((uint32_t)0x00000040) -#define GPIO_IDR_7 ((uint32_t)0x00000080) -#define GPIO_IDR_8 ((uint32_t)0x00000100) -#define GPIO_IDR_9 ((uint32_t)0x00000200) -#define GPIO_IDR_10 ((uint32_t)0x00000400) -#define GPIO_IDR_11 ((uint32_t)0x00000800) -#define GPIO_IDR_12 ((uint32_t)0x00001000) -#define GPIO_IDR_13 ((uint32_t)0x00002000) -#define GPIO_IDR_14 ((uint32_t)0x00004000) -#define GPIO_IDR_15 ((uint32_t)0x00008000) - -/****************** Bit definition for GPIO_ODR register ********************/ -#define GPIO_ODR_0 ((uint32_t)0x00000001) -#define GPIO_ODR_1 ((uint32_t)0x00000002) -#define GPIO_ODR_2 ((uint32_t)0x00000004) -#define GPIO_ODR_3 ((uint32_t)0x00000008) -#define GPIO_ODR_4 ((uint32_t)0x00000010) -#define GPIO_ODR_5 ((uint32_t)0x00000020) -#define GPIO_ODR_6 ((uint32_t)0x00000040) -#define GPIO_ODR_7 ((uint32_t)0x00000080) -#define GPIO_ODR_8 ((uint32_t)0x00000100) -#define GPIO_ODR_9 ((uint32_t)0x00000200) -#define GPIO_ODR_10 ((uint32_t)0x00000400) -#define GPIO_ODR_11 ((uint32_t)0x00000800) -#define GPIO_ODR_12 ((uint32_t)0x00001000) -#define GPIO_ODR_13 ((uint32_t)0x00002000) -#define GPIO_ODR_14 ((uint32_t)0x00004000) -#define GPIO_ODR_15 ((uint32_t)0x00008000) - -/****************** Bit definition for GPIO_BSRR register ********************/ -#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001) -#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002) -#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004) -#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008) -#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010) -#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020) -#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040) -#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080) -#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100) -#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200) -#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400) -#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800) -#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000) -#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000) -#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000) -#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000) -#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000) -#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000) -#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000) -#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000) -#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000) -#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000) -#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000) -#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000) -#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000) -#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000) -#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000) -#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000) -#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000) -#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000) -#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000) -#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000) - -/****************** Bit definition for GPIO_LCKR register ********************/ -#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) -#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) -#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) -#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) -#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) -#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) -#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) -#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) -#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) -#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) -#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) -#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) -#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) -#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) -#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) -#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) -#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) - -/****************** Bit definition for GPIO_AFRL register ********************/ -#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F) -#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0) -#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00) -#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000) -#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000) -#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000) -#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000) -#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000) - -/****************** Bit definition for GPIO_AFRH register ********************/ -#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F) -#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0) -#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00) -#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000) -#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000) -#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000) -#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000) -#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000) - -/****************** Bit definition for GPIO_BRR register *********************/ -#define GPIO_BRR_BR_0 ((uint32_t)0x00000001) -#define GPIO_BRR_BR_1 ((uint32_t)0x00000002) -#define GPIO_BRR_BR_2 ((uint32_t)0x00000004) -#define GPIO_BRR_BR_3 ((uint32_t)0x00000008) -#define GPIO_BRR_BR_4 ((uint32_t)0x00000010) -#define GPIO_BRR_BR_5 ((uint32_t)0x00000020) -#define GPIO_BRR_BR_6 ((uint32_t)0x00000040) -#define GPIO_BRR_BR_7 ((uint32_t)0x00000080) -#define GPIO_BRR_BR_8 ((uint32_t)0x00000100) -#define GPIO_BRR_BR_9 ((uint32_t)0x00000200) -#define GPIO_BRR_BR_10 ((uint32_t)0x00000400) -#define GPIO_BRR_BR_11 ((uint32_t)0x00000800) -#define GPIO_BRR_BR_12 ((uint32_t)0x00001000) -#define GPIO_BRR_BR_13 ((uint32_t)0x00002000) -#define GPIO_BRR_BR_14 ((uint32_t)0x00004000) -#define GPIO_BRR_BR_15 ((uint32_t)0x00008000) - -/******************************************************************************/ -/* */ -/* Inter-integrated Circuit Interface (I2C) */ -/* */ -/******************************************************************************/ -/******************* Bit definition for I2C_CR1 register *******************/ -#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */ -#define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */ -#define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */ -#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */ -#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */ -#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */ -#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */ -#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */ -#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */ -#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */ -#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */ -#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */ -#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */ -#define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */ -#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */ -#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */ -#define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */ -#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */ -#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */ -#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */ -#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */ - -/****************** Bit definition for I2C_CR2 register ********************/ -#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */ -#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */ -#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */ -#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */ -#define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */ -#define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */ -#define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */ -#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */ -#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */ -#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */ -#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */ - -/******************* Bit definition for I2C_OAR1 register ******************/ -#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */ -#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */ -#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */ - -/******************* Bit definition for I2C_OAR2 register *******************/ -#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */ -#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */ -#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */ - -/******************* Bit definition for I2C_TIMINGR register *****************/ -#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */ -#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */ -#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */ -#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */ -#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */ - -/******************* Bit definition for I2C_TIMEOUTR register *****************/ -#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */ -#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */ -#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */ -#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/ -#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */ - -/****************** Bit definition for I2C_ISR register *********************/ -#define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */ -#define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */ -#define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */ -#define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/ -#define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */ -#define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */ -#define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */ -#define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */ -#define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */ -#define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */ -#define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */ -#define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */ -#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */ -#define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */ -#define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */ -#define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */ -#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */ - -/****************** Bit definition for I2C_ICR register *********************/ -#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */ -#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */ -#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */ -#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */ -#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */ -#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */ -#define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */ -#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */ -#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */ - -/****************** Bit definition for I2C_PECR register ********************/ -#define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */ - -/****************** Bit definition for I2C_RXDR register *********************/ -#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */ - -/****************** Bit definition for I2C_TXDR register *********************/ -#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */ - - -/******************************************************************************/ -/* */ -/* Independent WATCHDOG (IWDG) */ -/* */ -/******************************************************************************/ -/******************* Bit definition for IWDG_KR register ********************/ -#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */ - -/******************* Bit definition for IWDG_PR register ********************/ -#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */ -#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */ - -/******************* Bit definition for IWDG_RLR register *******************/ -#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */ - -/******************* Bit definition for IWDG_SR register ********************/ -#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */ -#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */ -#define IWDG_SR_WVU ((uint8_t)0x04) /*!< Watchdog counter window value update */ - -/******************* Bit definition for IWDG_KR register ********************/ -#define IWDG_WINR_WIN ((uint16_t)0x0FFF) /*!< Watchdog counter window value */ - -/******************************************************************************/ -/* */ -/* Power Control */ -/* */ -/******************************************************************************/ -/******************** Bit definition for PWR_CR register ********************/ -#define PWR_CR_LPSDSR ((uint16_t)0x0001) /*!< Low-power deepsleep/sleep/low power run */ -#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ -#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ -#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ -#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ - -#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ -#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ -#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ - -/*!< PVD level configuration */ -#define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /*!< PVD level 0 */ -#define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /*!< PVD level 1 */ -#define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /*!< PVD level 2 */ -#define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /*!< PVD level 3 */ -#define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /*!< PVD level 4 */ -#define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /*!< PVD level 5 */ -#define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /*!< PVD level 6 */ -#define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /*!< PVD level 7 */ - -#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ - -/******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ -#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ -#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ -#define PWR_CSR_VREFINTRDYF ((uint16_t)0x0008) /*!< Internal voltage reference (VREFINT) ready flag */ - -#define PWR_CSR_EWUP1 ((uint16_t)0x0100) /*!< Enable WKUP pin 1 */ -#define PWR_CSR_EWUP2 ((uint16_t)0x0200) /*!< Enable WKUP pin 2 */ -#define PWR_CSR_EWUP3 ((uint16_t)0x0400) /*!< Enable WKUP pin 3 */ - -/******************************************************************************/ -/* */ -/* Reset and Clock Control */ -/* */ -/******************************************************************************/ -/******************** Bit definition for RCC_CR register ********************/ -#define RCC_CR_HSION ((uint32_t)0x00000001) -#define RCC_CR_HSIRDY ((uint32_t)0x00000002) - -#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) -#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */ -#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */ -#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */ -#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */ -#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */ - -#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) -#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */ -#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */ -#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */ -#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */ -#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */ -#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */ -#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */ -#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */ - -#define RCC_CR_HSEON ((uint32_t)0x00010000) -#define RCC_CR_HSERDY ((uint32_t)0x00020000) -#define RCC_CR_HSEBYP ((uint32_t)0x00040000) -#define RCC_CR_CSSON ((uint32_t)0x00080000) - -#define RCC_CR_PLLON ((uint32_t)0x01000000) -#define RCC_CR_PLLRDY ((uint32_t)0x02000000) - -/******************** Bit definition for RCC_CFGR register ******************/ -/*!< SW configuration */ -#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ -#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ -#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ -#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ - -/*!< SWS configuration */ -#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ -#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ - -/*!< HPRE configuration */ -#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ -#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ -#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ -#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ -#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ -#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ -#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ -#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ -#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ -#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ - -/*!< PPRE1 configuration */ -#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ -#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - -#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ - -/*!< PPRE2 configuration */ -#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ -#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ -#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ -#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ - -#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ - -#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ - -#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ - -/*!< PLLMUL configuration */ -#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ -#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ -#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ - -#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ -#define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ - -#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ -#define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ - -#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ -#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ -#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ -#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ -#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ -#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ -#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ -#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ -#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ -#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ -#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ -#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ -#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ -#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ -#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ - -/*!< USB configuration */ -#define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB prescaler */ - -/*!< I2S configuration */ -#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000) /*!< I2S external clock source selection */ - -/*!< MCO configuration */ -#define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ -#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ -#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */ -#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */ -#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ -#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ -#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ -#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ - -#define RCC_CFGR_MCOF ((uint32_t)0x10000000) /*!< Microcontroller Clock Output Flag */ - -#define RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) /*!< MCO prescaler */ -#define RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */ -#define RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */ -#define RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */ -#define RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */ -#define RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */ -#define RCC_CFGR_MCO_PRE_32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 */ -#define RCC_CFGR_MCO_PRE_64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */ -#define RCC_CFGR_MCO_PRE_128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */ - -#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */ - -/********************* Bit definition for RCC_CIR register ********************/ -#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ -#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ -#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ -#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ -#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ -#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ -#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ -#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ -#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ -#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ -#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ -#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ -#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ -#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ -#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ -#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ -#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ - -/****************** Bit definition for RCC_APB2RSTR register *****************/ -#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG reset */ -#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000200) /*!< TIM1 reset */ -#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */ -#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000200) /*!< TIM8 reset */ -#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ -#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 reset */ -#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 reset */ -#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 reset */ -#define RCC_APB2RSTR_HRTIM1RST ((uint32_t)0x20000000) /*!< HRTIM1 reset */ - -/****************** Bit definition for RCC_APB1RSTR register ******************/ -#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ -#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ -#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ -#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ -#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ -#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ -#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 reset */ -#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI3 reset */ -#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ -#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */ -#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ -#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ -#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ -#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ -#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */ -#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN reset */ -#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR reset */ -#define RCC_APB1RSTR_DAC1RST ((uint32_t)0x20000000) /*!< DAC 1 reset */ -#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x40000000) /*!< I2C 3 reset */ -#define RCC_APB1RSTR_DAC2RST ((uint32_t)0x04000000) /*!< DAC 2 reset */ -#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DAC1RST /*!< DAC reset */ - -/****************** Bit definition for RCC_AHBENR register ******************/ -#define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */ -#define RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) /*!< DMA2 clock enable */ -#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */ -#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */ -#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */ -#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */ -#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */ -#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */ -#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */ -#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */ -#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */ -#define RCC_AHBENR_TSEN ((uint32_t)0x01000000) /*!< TS clock enable */ -#define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */ -#define RCC_AHBENR_ADC34EN ((uint32_t)0x20000000) /*!< ADC1/ ADC2 clock enable */ - -/***************** Bit definition for RCC_APB2ENR register ******************/ -#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */ -#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */ -#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */ -#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 clock enable */ -#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ -#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */ -#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */ -#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */ -#define RCC_APB2ENR_HRTIM1 ((uint32_t)0x20000000) /*!< HRTIM1 clock enable */ - -/****************** Bit definition for RCC_APB1ENR register ******************/ -#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */ -#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ -#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ -#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ -#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ -#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ -#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */ -#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI3 clock enable */ -#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ -#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ -#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ -#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ -#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ -#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ -#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */ -#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN clock enable */ -#define RCC_APB1ENR_DAC2EN ((uint32_t)0x04000000) /*!< DAC 2 clock enable */ -#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */ -#define RCC_APB1ENR_DAC1EN ((uint32_t)0x20000000) /*!< DAC clock enable */ -#define RCC_APB1ENR_I2C3EN ((uint32_t)0x40000000) /*!< I2C 3 clock enable */ -#define RCC_APB1ENR_DACEN RCC_APB1ENR_DAC1EN - -/******************** Bit definition for RCC_BDCR register ******************/ -#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ -#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ -#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ - -#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */ -#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */ - - -#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ -#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -/*!< RTC configuration */ -#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ -#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */ - -#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ -#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ - -/******************** Bit definition for RCC_CSR register *******************/ -#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ -#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ -#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ -#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */ -#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ -#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ -#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ -#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ -#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ -#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ - -/******************* Bit definition for RCC_AHBRSTR register ****************/ -#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA reset */ -#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB reset */ -#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC reset */ -#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00010000) /*!< GPIOD reset */ -#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00040000) /*!< GPIOF reset */ -#define RCC_AHBRSTR_TSRST ((uint32_t)0x00100000) /*!< TS reset */ -#define RCC_AHBRSTR_ADC12RST ((uint32_t)0x01000000) /*!< ADC1 & ADC2 reset */ -#define RCC_AHBRSTR_ADC34RST ((uint32_t)0x02000000) /*!< ADC3 & ADC4 reset */ - -/******************* Bit definition for RCC_CFGR2 register ******************/ -/*!< PREDIV1 configuration */ -#define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ -#define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ -#define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ -#define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ -#define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ -#define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ -#define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ -#define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ -#define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ -#define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ -#define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ -#define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ -#define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ -#define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ -#define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ -#define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ -#define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ - -/*!< ADCPRE12 configuration */ -#define RCC_CFGR2_ADCPRE12 ((uint32_t)0x000001F0) /*!< ADCPRE12[8:4] bits */ -#define RCC_CFGR2_ADCPRE12_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define RCC_CFGR2_ADCPRE12_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define RCC_CFGR2_ADCPRE12_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define RCC_CFGR2_ADCPRE12_3 ((uint32_t)0x00000080) /*!< Bit 3 */ -#define RCC_CFGR2_ADCPRE12_4 ((uint32_t)0x00000100) /*!< Bit 4 */ - -#define RCC_CFGR2_ADCPRE12_NO ((uint32_t)0x00000000) /*!< ADC12 clock disabled, ADC12 can use AHB clock */ -#define RCC_CFGR2_ADCPRE12_DIV1 ((uint32_t)0x00000100) /*!< ADC12 PLL clock divided by 1 */ -#define RCC_CFGR2_ADCPRE12_DIV2 ((uint32_t)0x00000110) /*!< ADC12 PLL clock divided by 2 */ -#define RCC_CFGR2_ADCPRE12_DIV4 ((uint32_t)0x00000120) /*!< ADC12 PLL clock divided by 4 */ -#define RCC_CFGR2_ADCPRE12_DIV6 ((uint32_t)0x00000130) /*!< ADC12 PLL clock divided by 6 */ -#define RCC_CFGR2_ADCPRE12_DIV8 ((uint32_t)0x00000140) /*!< ADC12 PLL clock divided by 8 */ -#define RCC_CFGR2_ADCPRE12_DIV10 ((uint32_t)0x00000150) /*!< ADC12 PLL clock divided by 10 */ -#define RCC_CFGR2_ADCPRE12_DIV12 ((uint32_t)0x00000160) /*!< ADC12 PLL clock divided by 12 */ -#define RCC_CFGR2_ADCPRE12_DIV16 ((uint32_t)0x00000170) /*!< ADC12 PLL clock divided by 16 */ -#define RCC_CFGR2_ADCPRE12_DIV32 ((uint32_t)0x00000180) /*!< ADC12 PLL clock divided by 32 */ -#define RCC_CFGR2_ADCPRE12_DIV64 ((uint32_t)0x00000190) /*!< ADC12 PLL clock divided by 64 */ -#define RCC_CFGR2_ADCPRE12_DIV128 ((uint32_t)0x000001A0) /*!< ADC12 PLL clock divided by 128 */ -#define RCC_CFGR2_ADCPRE12_DIV256 ((uint32_t)0x000001B0) /*!< ADC12 PLL clock divided by 256 */ - -/*!< ADCPRE34 configuration */ -#define RCC_CFGR2_ADCPRE34 ((uint32_t)0x00003E00) /*!< ADCPRE34[13:5] bits */ -#define RCC_CFGR2_ADCPRE34_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define RCC_CFGR2_ADCPRE34_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define RCC_CFGR2_ADCPRE34_2 ((uint32_t)0x00000800) /*!< Bit 2 */ -#define RCC_CFGR2_ADCPRE34_3 ((uint32_t)0x00001000) /*!< Bit 3 */ -#define RCC_CFGR2_ADCPRE34_4 ((uint32_t)0x00002000) /*!< Bit 4 */ - -#define RCC_CFGR2_ADCPRE34_NO ((uint32_t)0x00000000) /*!< ADC34 clock disabled, ADC34 can use AHB clock */ -#define RCC_CFGR2_ADCPRE34_DIV1 ((uint32_t)0x00002000) /*!< ADC34 PLL clock divided by 1 */ -#define RCC_CFGR2_ADCPRE34_DIV2 ((uint32_t)0x00002200) /*!< ADC34 PLL clock divided by 2 */ -#define RCC_CFGR2_ADCPRE34_DIV4 ((uint32_t)0x00002400) /*!< ADC34 PLL clock divided by 4 */ -#define RCC_CFGR2_ADCPRE34_DIV6 ((uint32_t)0x00002600) /*!< ADC34 PLL clock divided by 6 */ -#define RCC_CFGR2_ADCPRE34_DIV8 ((uint32_t)0x00002800) /*!< ADC34 PLL clock divided by 8 */ -#define RCC_CFGR2_ADCPRE34_DIV10 ((uint32_t)0x00002A00) /*!< ADC34 PLL clock divided by 10 */ -#define RCC_CFGR2_ADCPRE34_DIV12 ((uint32_t)0x00002C00) /*!< ADC34 PLL clock divided by 12 */ -#define RCC_CFGR2_ADCPRE34_DIV16 ((uint32_t)0x00002E00) /*!< ADC34 PLL clock divided by 16 */ -#define RCC_CFGR2_ADCPRE34_DIV32 ((uint32_t)0x00003000) /*!< ADC34 PLL clock divided by 32 */ -#define RCC_CFGR2_ADCPRE34_DIV64 ((uint32_t)0x00003200) /*!< ADC34 PLL clock divided by 64 */ -#define RCC_CFGR2_ADCPRE34_DIV128 ((uint32_t)0x00003400) /*!< ADC34 PLL clock divided by 128 */ -#define RCC_CFGR2_ADCPRE34_DIV256 ((uint32_t)0x00003600) /*!< ADC34 PLL clock divided by 256 */ - -/******************* Bit definition for RCC_CFGR3 register ******************/ -#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */ -#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define RCC_CFGR3_I2CSW ((uint32_t)0x00000070) /*!< I2CSW bits */ -#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */ -#define RCC_CFGR3_I2C2SW ((uint32_t)0x00000020) /*!< I2C2SW bits */ -#define RCC_CFGR3_I2C3SW ((uint32_t)0x00000040) /*!< I2C3SW bits */ - -#define RCC_CFGR3_TIMSW ((uint32_t)0x00002F00) /*!< TIMSW bits */ -#define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */ -#define RCC_CFGR3_TIM8SW ((uint32_t)0x00000200) /*!< TIM8SW bits */ -#define RCC_CFGR3_TIM15SW ((uint32_t)0x00000400) /*!< TIM15SW bits */ -#define RCC_CFGR3_TIM16SW ((uint32_t)0x00000800) /*!< TIM16SW bits */ -#define RCC_CFGR3_TIM17SW ((uint32_t)0x00002000) /*!< TIM17SW bits */ - -#define RCC_CFGR3_HRTIM1SW ((uint32_t)0x00001000) /*!< HRTIM1SW bits */ - -#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */ -#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */ - -#define RCC_CFGR3_USART3SW ((uint32_t)0x000C0000) /*!< USART3SW[1:0] bits */ -#define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */ - -#define RCC_CFGR3_UART4SW ((uint32_t)0x00300000) /*!< UART4SW[1:0] bits */ -#define RCC_CFGR3_UART4SW_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define RCC_CFGR3_UART4SW_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -#define RCC_CFGR3_UART5SW ((uint32_t)0x00C00000) /*!< UART5SW[1:0] bits */ -#define RCC_CFGR3_UART5SW_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define RCC_CFGR3_UART5SW_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -/******************************************************************************/ -/* */ -/* Real-Time Clock (RTC) */ -/* */ -/******************************************************************************/ -/******************** Bits definition for RTC_TR register *******************/ -#define RTC_TR_PM ((uint32_t)0x00400000) -#define RTC_TR_HT ((uint32_t)0x00300000) -#define RTC_TR_HT_0 ((uint32_t)0x00100000) -#define RTC_TR_HT_1 ((uint32_t)0x00200000) -#define RTC_TR_HU ((uint32_t)0x000F0000) -#define RTC_TR_HU_0 ((uint32_t)0x00010000) -#define RTC_TR_HU_1 ((uint32_t)0x00020000) -#define RTC_TR_HU_2 ((uint32_t)0x00040000) -#define RTC_TR_HU_3 ((uint32_t)0x00080000) -#define RTC_TR_MNT ((uint32_t)0x00007000) -#define RTC_TR_MNT_0 ((uint32_t)0x00001000) -#define RTC_TR_MNT_1 ((uint32_t)0x00002000) -#define RTC_TR_MNT_2 ((uint32_t)0x00004000) -#define RTC_TR_MNU ((uint32_t)0x00000F00) -#define RTC_TR_MNU_0 ((uint32_t)0x00000100) -#define RTC_TR_MNU_1 ((uint32_t)0x00000200) -#define RTC_TR_MNU_2 ((uint32_t)0x00000400) -#define RTC_TR_MNU_3 ((uint32_t)0x00000800) -#define RTC_TR_ST ((uint32_t)0x00000070) -#define RTC_TR_ST_0 ((uint32_t)0x00000010) -#define RTC_TR_ST_1 ((uint32_t)0x00000020) -#define RTC_TR_ST_2 ((uint32_t)0x00000040) -#define RTC_TR_SU ((uint32_t)0x0000000F) -#define RTC_TR_SU_0 ((uint32_t)0x00000001) -#define RTC_TR_SU_1 ((uint32_t)0x00000002) -#define RTC_TR_SU_2 ((uint32_t)0x00000004) -#define RTC_TR_SU_3 ((uint32_t)0x00000008) - -/******************** Bits definition for RTC_DR register *******************/ -#define RTC_DR_YT ((uint32_t)0x00F00000) -#define RTC_DR_YT_0 ((uint32_t)0x00100000) -#define RTC_DR_YT_1 ((uint32_t)0x00200000) -#define RTC_DR_YT_2 ((uint32_t)0x00400000) -#define RTC_DR_YT_3 ((uint32_t)0x00800000) -#define RTC_DR_YU ((uint32_t)0x000F0000) -#define RTC_DR_YU_0 ((uint32_t)0x00010000) -#define RTC_DR_YU_1 ((uint32_t)0x00020000) -#define RTC_DR_YU_2 ((uint32_t)0x00040000) -#define RTC_DR_YU_3 ((uint32_t)0x00080000) -#define RTC_DR_WDU ((uint32_t)0x0000E000) -#define RTC_DR_WDU_0 ((uint32_t)0x00002000) -#define RTC_DR_WDU_1 ((uint32_t)0x00004000) -#define RTC_DR_WDU_2 ((uint32_t)0x00008000) -#define RTC_DR_MT ((uint32_t)0x00001000) -#define RTC_DR_MU ((uint32_t)0x00000F00) -#define RTC_DR_MU_0 ((uint32_t)0x00000100) -#define RTC_DR_MU_1 ((uint32_t)0x00000200) -#define RTC_DR_MU_2 ((uint32_t)0x00000400) -#define RTC_DR_MU_3 ((uint32_t)0x00000800) -#define RTC_DR_DT ((uint32_t)0x00000030) -#define RTC_DR_DT_0 ((uint32_t)0x00000010) -#define RTC_DR_DT_1 ((uint32_t)0x00000020) -#define RTC_DR_DU ((uint32_t)0x0000000F) -#define RTC_DR_DU_0 ((uint32_t)0x00000001) -#define RTC_DR_DU_1 ((uint32_t)0x00000002) -#define RTC_DR_DU_2 ((uint32_t)0x00000004) -#define RTC_DR_DU_3 ((uint32_t)0x00000008) - -/******************** Bits definition for RTC_CR register *******************/ -#define RTC_CR_COE ((uint32_t)0x00800000) -#define RTC_CR_OSEL ((uint32_t)0x00600000) -#define RTC_CR_OSEL_0 ((uint32_t)0x00200000) -#define RTC_CR_OSEL_1 ((uint32_t)0x00400000) -#define RTC_CR_POL ((uint32_t)0x00100000) -#define RTC_CR_COSEL ((uint32_t)0x00080000) -#define RTC_CR_BCK ((uint32_t)0x00040000) -#define RTC_CR_SUB1H ((uint32_t)0x00020000) -#define RTC_CR_ADD1H ((uint32_t)0x00010000) -#define RTC_CR_TSIE ((uint32_t)0x00008000) -#define RTC_CR_WUTIE ((uint32_t)0x00004000) -#define RTC_CR_ALRBIE ((uint32_t)0x00002000) -#define RTC_CR_ALRAIE ((uint32_t)0x00001000) -#define RTC_CR_TSE ((uint32_t)0x00000800) -#define RTC_CR_WUTE ((uint32_t)0x00000400) -#define RTC_CR_ALRBE ((uint32_t)0x00000200) -#define RTC_CR_ALRAE ((uint32_t)0x00000100) -#define RTC_CR_FMT ((uint32_t)0x00000040) -#define RTC_CR_BYPSHAD ((uint32_t)0x00000020) -#define RTC_CR_REFCKON ((uint32_t)0x00000010) -#define RTC_CR_TSEDGE ((uint32_t)0x00000008) -#define RTC_CR_WUCKSEL ((uint32_t)0x00000007) -#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) -#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) -#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) - -/******************** Bits definition for RTC_ISR register ******************/ -#define RTC_ISR_RECALPF ((uint32_t)0x00010000) -#define RTC_ISR_TAMP3F ((uint32_t)0x00008000) -#define RTC_ISR_TAMP2F ((uint32_t)0x00004000) -#define RTC_ISR_TAMP1F ((uint32_t)0x00002000) -#define RTC_ISR_TSOVF ((uint32_t)0x00001000) -#define RTC_ISR_TSF ((uint32_t)0x00000800) -#define RTC_ISR_WUTF ((uint32_t)0x00000400) -#define RTC_ISR_ALRBF ((uint32_t)0x00000200) -#define RTC_ISR_ALRAF ((uint32_t)0x00000100) -#define RTC_ISR_INIT ((uint32_t)0x00000080) -#define RTC_ISR_INITF ((uint32_t)0x00000040) -#define RTC_ISR_RSF ((uint32_t)0x00000020) -#define RTC_ISR_INITS ((uint32_t)0x00000010) -#define RTC_ISR_SHPF ((uint32_t)0x00000008) -#define RTC_ISR_WUTWF ((uint32_t)0x00000004) -#define RTC_ISR_ALRBWF ((uint32_t)0x00000002) -#define RTC_ISR_ALRAWF ((uint32_t)0x00000001) - -/******************** Bits definition for RTC_PRER register *****************/ -#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) -#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF) - -/******************** Bits definition for RTC_WUTR register *****************/ -#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF) - -/******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) -#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) -#define RTC_ALRMAR_DT ((uint32_t)0x30000000) -#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) -#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) -#define RTC_ALRMAR_DU ((uint32_t)0x0F000000) -#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) -#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) -#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) -#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) -#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) -#define RTC_ALRMAR_PM ((uint32_t)0x00400000) -#define RTC_ALRMAR_HT ((uint32_t)0x00300000) -#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) -#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) -#define RTC_ALRMAR_HU ((uint32_t)0x000F0000) -#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) -#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) -#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) -#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) -#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) -#define RTC_ALRMAR_MNT ((uint32_t)0x00007000) -#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) -#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) -#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) -#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00) -#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) -#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) -#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) -#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) -#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) -#define RTC_ALRMAR_ST ((uint32_t)0x00000070) -#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) -#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) -#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) -#define RTC_ALRMAR_SU ((uint32_t)0x0000000F) -#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) -#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) -#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) -#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) - -/******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000) -#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000) -#define RTC_ALRMBR_DT ((uint32_t)0x30000000) -#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000) -#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000) -#define RTC_ALRMBR_DU ((uint32_t)0x0F000000) -#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000) -#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000) -#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000) -#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000) -#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000) -#define RTC_ALRMBR_PM ((uint32_t)0x00400000) -#define RTC_ALRMBR_HT ((uint32_t)0x00300000) -#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000) -#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000) -#define RTC_ALRMBR_HU ((uint32_t)0x000F0000) -#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000) -#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000) -#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000) -#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000) -#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000) -#define RTC_ALRMBR_MNT ((uint32_t)0x00007000) -#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000) -#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000) -#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000) -#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00) -#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100) -#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200) -#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400) -#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800) -#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080) -#define RTC_ALRMBR_ST ((uint32_t)0x00000070) -#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010) -#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020) -#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040) -#define RTC_ALRMBR_SU ((uint32_t)0x0000000F) -#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001) -#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002) -#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004) -#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008) - -/******************** Bits definition for RTC_WPR register ******************/ -#define RTC_WPR_KEY ((uint32_t)0x000000FF) - -/******************** Bits definition for RTC_SSR register ******************/ -#define RTC_SSR_SS ((uint32_t)0x0000FFFF) - -/******************** Bits definition for RTC_SHIFTR register ***************/ -#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) -#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) - -/******************** Bits definition for RTC_TSTR register *****************/ -#define RTC_TSTR_PM ((uint32_t)0x00400000) -#define RTC_TSTR_HT ((uint32_t)0x00300000) -#define RTC_TSTR_HT_0 ((uint32_t)0x00100000) -#define RTC_TSTR_HT_1 ((uint32_t)0x00200000) -#define RTC_TSTR_HU ((uint32_t)0x000F0000) -#define RTC_TSTR_HU_0 ((uint32_t)0x00010000) -#define RTC_TSTR_HU_1 ((uint32_t)0x00020000) -#define RTC_TSTR_HU_2 ((uint32_t)0x00040000) -#define RTC_TSTR_HU_3 ((uint32_t)0x00080000) -#define RTC_TSTR_MNT ((uint32_t)0x00007000) -#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000) -#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000) -#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000) -#define RTC_TSTR_MNU ((uint32_t)0x00000F00) -#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100) -#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200) -#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400) -#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800) -#define RTC_TSTR_ST ((uint32_t)0x00000070) -#define RTC_TSTR_ST_0 ((uint32_t)0x00000010) -#define RTC_TSTR_ST_1 ((uint32_t)0x00000020) -#define RTC_TSTR_ST_2 ((uint32_t)0x00000040) -#define RTC_TSTR_SU ((uint32_t)0x0000000F) -#define RTC_TSTR_SU_0 ((uint32_t)0x00000001) -#define RTC_TSTR_SU_1 ((uint32_t)0x00000002) -#define RTC_TSTR_SU_2 ((uint32_t)0x00000004) -#define RTC_TSTR_SU_3 ((uint32_t)0x00000008) - -/******************** Bits definition for RTC_TSDR register *****************/ -#define RTC_TSDR_WDU ((uint32_t)0x0000E000) -#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000) -#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000) -#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000) -#define RTC_TSDR_MT ((uint32_t)0x00001000) -#define RTC_TSDR_MU ((uint32_t)0x00000F00) -#define RTC_TSDR_MU_0 ((uint32_t)0x00000100) -#define RTC_TSDR_MU_1 ((uint32_t)0x00000200) -#define RTC_TSDR_MU_2 ((uint32_t)0x00000400) -#define RTC_TSDR_MU_3 ((uint32_t)0x00000800) -#define RTC_TSDR_DT ((uint32_t)0x00000030) -#define RTC_TSDR_DT_0 ((uint32_t)0x00000010) -#define RTC_TSDR_DT_1 ((uint32_t)0x00000020) -#define RTC_TSDR_DU ((uint32_t)0x0000000F) -#define RTC_TSDR_DU_0 ((uint32_t)0x00000001) -#define RTC_TSDR_DU_1 ((uint32_t)0x00000002) -#define RTC_TSDR_DU_2 ((uint32_t)0x00000004) -#define RTC_TSDR_DU_3 ((uint32_t)0x00000008) - -/******************** Bits definition for RTC_TSSSR register ****************/ -#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF) - -/******************** Bits definition for RTC_CAL register *****************/ -#define RTC_CALR_CALP ((uint32_t)0x00008000) -#define RTC_CALR_CALW8 ((uint32_t)0x00004000) -#define RTC_CALR_CALW16 ((uint32_t)0x00002000) -#define RTC_CALR_CALM ((uint32_t)0x000001FF) -#define RTC_CALR_CALM_0 ((uint32_t)0x00000001) -#define RTC_CALR_CALM_1 ((uint32_t)0x00000002) -#define RTC_CALR_CALM_2 ((uint32_t)0x00000004) -#define RTC_CALR_CALM_3 ((uint32_t)0x00000008) -#define RTC_CALR_CALM_4 ((uint32_t)0x00000010) -#define RTC_CALR_CALM_5 ((uint32_t)0x00000020) -#define RTC_CALR_CALM_6 ((uint32_t)0x00000040) -#define RTC_CALR_CALM_7 ((uint32_t)0x00000080) -#define RTC_CALR_CALM_8 ((uint32_t)0x00000100) - -/******************** Bits definition for RTC_TAFCR register ****************/ -#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000) -#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000) -#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000) -#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000) -#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000) -#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800) -#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800) -#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000) -#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700) -#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100) -#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200) -#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400) -#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080) -#define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040) -#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020) -#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010) -#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008) -#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004) -#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002) -#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001) - -/******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000) -#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000) -#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000) -#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000) -#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000) -#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF) - -/******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000) -#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000) -#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000) -#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000) -#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000) -#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF) - -/******************** Bits definition for RTC_BKP0R register ****************/ -#define RTC_BKP0R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP1R register ****************/ -#define RTC_BKP1R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP2R register ****************/ -#define RTC_BKP2R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP3R register ****************/ -#define RTC_BKP3R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP4R register ****************/ -#define RTC_BKP4R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP5R register ****************/ -#define RTC_BKP5R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP6R register ****************/ -#define RTC_BKP6R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP7R register ****************/ -#define RTC_BKP7R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP8R register ****************/ -#define RTC_BKP8R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP9R register ****************/ -#define RTC_BKP9R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP10R register ***************/ -#define RTC_BKP10R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP11R register ***************/ -#define RTC_BKP11R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP12R register ***************/ -#define RTC_BKP12R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP13R register ***************/ -#define RTC_BKP13R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP14R register ***************/ -#define RTC_BKP14R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP15R register ***************/ -#define RTC_BKP15R ((uint32_t)0xFFFFFFFF) - -/******************************************************************************/ -/* */ -/* Serial Peripheral Interface (SPI) */ -/* */ -/******************************************************************************/ -/******************* Bit definition for SPI_CR1 register ********************/ -#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */ -#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */ -#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */ - -#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */ -#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */ -#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */ -#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */ - -#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */ -#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */ -#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */ -#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */ -#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */ -#define SPI_CR1_CRCL ((uint16_t)0x0800) /*!< CRC Length */ -#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */ -#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */ -#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */ -#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */ - -/******************* Bit definition for SPI_CR2 register ********************/ -#define SPI_CR2_RXDMAEN ((uint16_t)0x0001) /*!< Rx Buffer DMA Enable */ -#define SPI_CR2_TXDMAEN ((uint16_t)0x0002) /*!< Tx Buffer DMA Enable */ -#define SPI_CR2_SSOE ((uint16_t)0x0004) /*!< SS Output Enable */ -#define SPI_CR2_NSSP ((uint16_t)0x0008) /*!< NSS pulse management Enable */ -#define SPI_CR2_FRF ((uint16_t)0x0010) /*!< Frame Format Enable */ -#define SPI_CR2_ERRIE ((uint16_t)0x0020) /*!< Error Interrupt Enable */ -#define SPI_CR2_RXNEIE ((uint16_t)0x0040) /*!< RX buffer Not Empty Interrupt Enable */ -#define SPI_CR2_TXEIE ((uint16_t)0x0080) /*!< Tx buffer Empty Interrupt Enable */ - -#define SPI_CR2_DS ((uint16_t)0x0F00) /*!< DS[3:0] Data Size */ -#define SPI_CR2_DS_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define SPI_CR2_DS_1 ((uint16_t)0x0200) /*!< Bit 1 */ -#define SPI_CR2_DS_2 ((uint16_t)0x0400) /*!< Bit 2 */ -#define SPI_CR2_DS_3 ((uint16_t)0x0800) /*!< Bit 3 */ - -#define SPI_CR2_FRXTH ((uint16_t)0x1000) /*!< FIFO reception Threshold */ -#define SPI_CR2_LDMARX ((uint16_t)0x2000) /*!< Last DMA transfer for reception */ -#define SPI_CR2_LDMATX ((uint16_t)0x4000) /*!< Last DMA transfer for transmission */ - -/******************** Bit definition for SPI_SR register ********************/ -#define SPI_SR_RXNE ((uint16_t)0x0001) /*!< Receive buffer Not Empty */ -#define SPI_SR_TXE ((uint16_t)0x0002) /*!< Transmit buffer Empty */ -#define SPI_SR_CRCERR ((uint16_t)0x0010) /*!< CRC Error flag */ -#define SPI_SR_MODF ((uint16_t)0x0020) /*!< Mode fault */ -#define SPI_SR_OVR ((uint16_t)0x0040) /*!< Overrun flag */ -#define SPI_SR_BSY ((uint16_t)0x0080) /*!< Busy flag */ -#define SPI_SR_FRE ((uint16_t)0x0100) /*!< TI frame format error */ -#define SPI_SR_FRLVL ((uint16_t)0x0600) /*!< FIFO Reception Level */ -#define SPI_SR_FRLVL_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define SPI_SR_FRLVL_1 ((uint16_t)0x0400) /*!< Bit 1 */ -#define SPI_SR_FTLVL ((uint16_t)0x1800) /*!< FIFO Transmission Level */ -#define SPI_SR_FTLVL_0 ((uint16_t)0x0800) /*!< Bit 0 */ -#define SPI_SR_FTLVL_1 ((uint16_t)0x1000) /*!< Bit 1 */ - -/******************** Bit definition for SPI_DR register ********************/ -#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */ - -/******************* Bit definition for SPI_CRCPR register ******************/ -#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */ - -/****************** Bit definition for SPI_RXCRCR register ******************/ -#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */ - -/****************** Bit definition for SPI_TXCRCR register ******************/ -#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */ - -/****************** Bit definition for SPI_I2SCFGR register *****************/ -#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */ - -#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */ -#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */ -#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */ - -#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */ - -#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */ -#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */ -#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */ - -#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */ - -#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */ -#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */ -#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */ - -#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */ -#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */ - -/****************** Bit definition for SPI_I2SPR register *******************/ -#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */ -#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */ -#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */ - -/******************************************************************************/ -/* */ -/* System Configuration(SYSCFG) */ -/* */ -/******************************************************************************/ -/***************** Bit definition for SYSCFG_CFGR1 register *****************/ -#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */ -#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define SYSCFG_CFGR1_USB_IT_RMP ((uint32_t)0x00000020) /*!< USB interrupt remap */ -#define SYSCFG_CFGR1_TIM1_ITR3_RMP ((uint32_t)0x00000040) /*!< Timer 1 ITR3 selection */ -#define SYSCFG_CFGR1_DAC1_TRIG1_RMP ((uint32_t)0x00000080) /*!< DAC1 Trigger1 remap */ -#define SYSCFG_CFGR1_ADC24_DMA_RMP ((uint32_t)0x00000100) /*!< ADC2 and ADC4 DMA remap */ -#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */ -#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */ -#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */ -#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 CH2 DMA remap */ -#define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP ((uint32_t)0x00008000) /*!< DAC2 CH1 DMA remap */ -#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */ -#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */ -#define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */ -#define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */ -#define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000) /*!< I2C1 Fast mode plus */ -#define SYSCFG_CFGR1_I2C2_FMP ((uint32_t)0x00200000) /*!< I2C2 Fast mode plus */ -#define SYSCFG_CFGR1_ENCODER_MODE ((uint32_t)0x00C00000) /*!< Encoder Mode */ -#define SYSCFG_CFGR1_ENCODER_MODE_0 ((uint32_t)0x00400000) /*!< Encoder Mode 0 */ -#define SYSCFG_CFGR1_ENCODER_MODE_1 ((uint32_t)0x00800000) /*!< Encoder Mode 1 */ -#define SYSCFG_CFGR1_FPU_IE ((uint32_t)0xFC000000) /*!< Floating Point Unit Interrupt Enable */ -#define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000) /*!< Floating Point Unit Interrupt Enable 0 */ -#define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000) /*!< Floating Point Unit Interrupt Enable 1 */ -#define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000) /*!< Floating Point Unit Interrupt Enable 2 */ -#define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000) /*!< Floating Point Unit Interrupt Enable 3 */ -#define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000) /*!< Floating Point Unit Interrupt Enable 4 */ -#define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000) /*!< Floating Point Unit Interrupt Enable 5 */ -#define SYSCFG_CFGR1_DAC_TRIG_RMP SYSCFG_CFGR1_DAC1_TRIG1_RMP /*!< Old define maintained for legacy purpose */ -#define SYSCFG_CFGR1_TIM6DAC1 SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP /*!< Old define maintained for legacy purpose */ -#define SYSCFG_CFGR1_TIM7DAC2 SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP /*!< Old define maintained for legacy purpose */ -/***************** Bit definition for SYSCFG_RCR register *******************/ -#define SYSCFG_RCR_PAGE0 ((uint32_t)0x00000001) /*!< ICODE SRAM Write protection page 0 */ -#define SYSCFG_RCR_PAGE1 ((uint32_t)0x00000002) /*!< ICODE SRAM Write protection page 1 */ -#define SYSCFG_RCR_PAGE2 ((uint32_t)0x00000004) /*!< ICODE SRAM Write protection page 2 */ -#define SYSCFG_RCR_PAGE3 ((uint32_t)0x00000008) /*!< ICODE SRAM Write protection page 3 */ -#define SYSCFG_RCR_PAGE4 ((uint32_t)0x00000010) /*!< ICODE SRAM Write protection page 4 */ -#define SYSCFG_RCR_PAGE5 ((uint32_t)0x00000020) /*!< ICODE SRAM Write protection page 5 */ -#define SYSCFG_RCR_PAGE6 ((uint32_t)0x00000040) /*!< ICODE SRAM Write protection page 6 */ -#define SYSCFG_RCR_PAGE7 ((uint32_t)0x00000080) /*!< ICODE SRAM Write protection page 7 */ - -/***************** Bit definition for SYSCFG_EXTICR1 register ***************/ -#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ -#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ -#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ -#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ - -/** - * @brief EXTI0 configuration - */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ - -/** - * @brief EXTI1 configuration - */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ - -/** - * @brief EXTI2 configuration - */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ - -/** - * @brief EXTI3 configuration - */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ - -/***************** Bit definition for SYSCFG_EXTICR2 register ***************/ -#define SYSCFG_EXTIRCR_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ -#define SYSCFG_EXTIRCR_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ -#define SYSCFG_EXTIRCR_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ -#define SYSCFG_EXTIRCR_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ - -/** - * @brief EXTI4 configuration - */ -#define SYSCFG_EXTIRCR_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ -#define SYSCFG_EXTIRCR_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ -#define SYSCFG_EXTIRCR_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ -#define SYSCFG_EXTIRCR_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ -#define SYSCFG_EXTIRCR_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ -#define SYSCFG_EXTIRCR_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ - -/** - * @brief EXTI5 configuration - */ -#define SYSCFG_EXTIRCR_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ -#define SYSCFG_EXTIRCR_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ -#define SYSCFG_EXTIRCR_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ -#define SYSCFG_EXTIRCR_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ -#define SYSCFG_EXTIRCR_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ -#define SYSCFG_EXTIRCR_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ - -/** - * @brief EXTI6 configuration - */ -#define SYSCFG_EXTIRCR_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ -#define SYSCFG_EXTIRCR_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ -#define SYSCFG_EXTIRCR_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ -#define SYSCFG_EXTIRCR_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ -#define SYSCFG_EXTIRCR_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ -#define SYSCFG_EXTIRCR_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ - -/** - * @brief EXTI7 configuration - */ -#define SYSCFG_EXTIRCR_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ -#define SYSCFG_EXTIRCR_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ -#define SYSCFG_EXTIRCR_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ -#define SYSCFG_EXTIRCR_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ -#define SYSCFG_EXTIRCR_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ - -/***************** Bit definition for SYSCFG_EXTICR3 register ***************/ -#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ -#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ -#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ -#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ - -/** - * @brief EXTI8 configuration - */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ - -/** - * @brief EXTI9 configuration - */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ - -/** - * @brief EXTI10 configuration - */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ - -/** - * @brief EXTI11 configuration - */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ - -/***************** Bit definition for SYSCFG_EXTICR4 register *****************/ -#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ -#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ -#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ -#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ - -/** - * @brief EXTI12 configuration - */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ - -/** - * @brief EXTI13 configuration - */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ - -/** - * @brief EXTI14 configuration - */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ - -/** - * @brief EXTI15 configuration - */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ - -/***************** Bit definition for SYSCFG_CFGR2 register *****************/ -#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */ -#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17 */ -#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMER1/8/15/16/17 */ -#define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the address parity check on RAM */ -#define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */ - -/***************** Bit definition for SYSCFG_CFGR3 register *****************/ -#define SYSCFG_CFGR3_SPI1_RX_DMA_RMP ((uint32_t)0x00000003) /*!< SPI1 RX DMA remap */ -#define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_0 ((uint32_t)0x00000001) /*!< SPI1 RX DMA remap bit 0 */ -#define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_1 ((uint32_t)0x00000002) /*!< SPI1 RX DMA remap bit 1 */ -#define SYSCFG_CFGR3_SPI1_TX_DMA_RMP ((uint32_t)0x0000000C) /*!< SPI1 TX DMA remap */ -#define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_0 ((uint32_t)0x00000004) /*!< SPI1 TX DMA remap bit 0 */ -#define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_1 ((uint32_t)0x00000008) /*!< SPI1 TX DMA remap bit 1 */ -#define SYSCFG_CFGR3_I2C1_RX_DMA_RMP ((uint32_t)0x00000030) /*!< I2C1 RX DMA remap */ -#define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_0 ((uint32_t)0x00000010) /*!< I2C1 RX DMA remap bit 0 */ -#define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_1 ((uint32_t)0x00000020) /*!< I2C1 RX DMA remap bit 1 */ -#define SYSCFG_CFGR3_I2C1_TX_DMA_RMP ((uint32_t)0x000000C0) /*!< I2C1 RX DMA remap */ -#define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_0 ((uint32_t)0x00000040) /*!< I2C1 TX DMA remap bit 0 */ -#define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_1 ((uint32_t)0x00000080) /*!< I2C1 TX DMA remap bit 1 */ -#define SYSCFG_CFGR3_ADC2_DMA_RMP ((uint32_t)0x00000300) /*!< ADC2 DMA remap */ -#define SYSCFG_CFGR3_ADC2_DMA_RMP_0 ((uint32_t)0x00000100) /*!< ADC2 DMA remap bit 0 */ -#define SYSCFG_CFGR3_ADC2_DMA_RMP_1 ((uint32_t)0x00000200) /*!< ADC2 DMA remap bit 1 */ -#define SYSCFG_CFGR3_DAC1_TRG3_RMP ((uint32_t)0x00010000) /*!< DAC1 TRG3 remap */ -#define SYSCFG_CFGR3_DAC1_TRG5_RMP ((uint32_t)0x00020000) /*!< DAC1 TRG5 remap */ - -/******************************************************************************/ -/* */ -/* TIM */ -/* */ -/******************************************************************************/ -/******************* Bit definition for TIM_CR1 register ********************/ -#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */ -#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */ -#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */ -#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */ -#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */ - -#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */ -#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */ -#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */ - -#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */ - -#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */ -#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */ -#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */ - -#define TIM_CR1_UIFREMAP ((uint16_t)0x0800) /*!<Update interrupt flag remap */ - -/******************* Bit definition for TIM_CR2 register ********************/ -#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */ -#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */ -#define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */ - -#define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */ -#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */ -#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */ -#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */ - -#define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */ -#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */ -#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */ -#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */ -#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */ -#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */ -#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */ -#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */ -#define TIM_CR2_OIS5 ((uint32_t)0x00010000) /*!<Output Idle state 4 (OC4 output) */ -#define TIM_CR2_OIS6 ((uint32_t)0x00020000) /*!<Output Idle state 4 (OC4 output) */ - -#define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /*!<MMS[2:0] bits (Master Mode Selection) */ -#define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */ -#define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */ -#define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */ -#define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /*!<Bit 2 */ - -/******************* Bit definition for TIM_SMCR register *******************/ -#define TIM_SMCR_SMS ((uint32_t)0x00010007) /*!<SMS[2:0] bits (Slave mode selection) */ -#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */ -#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */ -#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */ -#define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /*!<Bit 3 */ - -#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */ - -#define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */ -#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */ -#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */ -#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */ - -#define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */ - -#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */ -#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */ -#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */ -#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */ -#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */ - -#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */ -#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */ -#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */ - -#define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */ -#define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */ - -/******************* Bit definition for TIM_DIER register *******************/ -#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */ -#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */ -#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */ -#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */ -#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */ -#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */ -#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */ -#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */ -#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */ -#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */ -#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */ -#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */ -#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */ -#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */ -#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */ - -/******************** Bit definition for TIM_SR register ********************/ -#define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */ -#define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */ -#define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */ -#define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */ -#define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */ -#define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */ -#define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */ -#define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */ -#define TIM_SR_B2IF ((uint32_t)0x00000100) /*!<Break2 interrupt Flag */ -#define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Over capture Flag */ -#define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Over capture Flag */ -#define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Over capture Flag */ -#define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Over capture Flag */ -#define TIM_SR_CC5IF ((uint32_t)0x00010000) /*!<Capture/Compare 5 interrupt Flag */ -#define TIM_SR_CC6IF ((uint32_t)0x00020000) /*!<Capture/Compare 6 interrupt Flag */ - - -/******************* Bit definition for TIM_EGR register ********************/ -#define TIM_EGR_UG ((uint16_t)0x0001) /*!<Update Generation */ -#define TIM_EGR_CC1G ((uint16_t)0x0002) /*!<Capture/Compare 1 Generation */ -#define TIM_EGR_CC2G ((uint16_t)0x0004) /*!<Capture/Compare 2 Generation */ -#define TIM_EGR_CC3G ((uint16_t)0x0008) /*!<Capture/Compare 3 Generation */ -#define TIM_EGR_CC4G ((uint16_t)0x0010) /*!<Capture/Compare 4 Generation */ -#define TIM_EGR_COMG ((uint16_t)0x0020) /*!<Capture/Compare Control Update Generation */ -#define TIM_EGR_TG ((uint16_t)0x0040) /*!<Trigger Generation */ -#define TIM_EGR_BG ((uint16_t)0x0080) /*!<Break Generation */ -#define TIM_EGR_B2G ((uint16_t)0x0100) /*!<Break Generation */ - - -/****************** Bit definition for TIM_CCMR1 register *******************/ -#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ -#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */ -#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */ - -#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */ -#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */ - -#define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ -#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */ -#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */ -#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */ -#define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /*!<Bit 3 */ - -#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */ - -#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ -#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */ -#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */ - -#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */ -#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */ - -#define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ -#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */ -#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */ -#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */ -#define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /*!<Bit 3 */ - -#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */ - -/*----------------------------------------------------------------------------*/ - -#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ -#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */ -#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */ - -#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ -#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */ -#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */ -#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */ -#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */ - -#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ -#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */ -#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */ - -#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ -#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */ -#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */ -#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */ -#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */ - -/****************** Bit definition for TIM_CCMR2 register *******************/ -#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ -#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */ -#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */ - -#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */ -#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */ - -#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ -#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */ -#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */ -#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */ -#define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /*!<Bit 3 */ - -#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */ - -#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ -#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */ -#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */ - -#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */ -#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */ - -#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ -#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */ -#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */ -#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */ -#define TIM_CCMR2_OC4M_3 ((uint32_t)0x00100000) /*!<Bit 3 */ - -#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */ - -/*----------------------------------------------------------------------------*/ - -#define TIM_CCMR2_IC3PSC ((uint16_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ -#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x00000004) /*!<Bit 0 */ -#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x00000008) /*!<Bit 1 */ - -#define TIM_CCMR2_IC3F ((uint16_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ -#define TIM_CCMR2_IC3F_0 ((uint16_t)0x00000010) /*!<Bit 0 */ -#define TIM_CCMR2_IC3F_1 ((uint16_t)0x00000020) /*!<Bit 1 */ -#define TIM_CCMR2_IC3F_2 ((uint16_t)0x00000040) /*!<Bit 2 */ -#define TIM_CCMR2_IC3F_3 ((uint16_t)0x00000080) /*!<Bit 3 */ - -#define TIM_CCMR2_IC4PSC ((uint16_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ -#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x00000400) /*!<Bit 0 */ -#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x00000800) /*!<Bit 1 */ - -#define TIM_CCMR2_IC4F ((uint16_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ -#define TIM_CCMR2_IC4F_0 ((uint16_t)0x00001000) /*!<Bit 0 */ -#define TIM_CCMR2_IC4F_1 ((uint16_t)0x00002000) /*!<Bit 1 */ -#define TIM_CCMR2_IC4F_2 ((uint16_t)0x00004000) /*!<Bit 2 */ -#define TIM_CCMR2_IC4F_3 ((uint16_t)0x00008000) /*!<Bit 3 */ - -/******************* Bit definition for TIM_CCER register *******************/ -#define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */ -#define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */ -#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */ -#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */ -#define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */ -#define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */ -#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */ -#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */ -#define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */ -#define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */ -#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */ -#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */ -#define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */ -#define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */ -#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */ -#define TIM_CCER_CC5E ((uint32_t)0x00010000) /*!<Capture/Compare 5 output enable */ -#define TIM_CCER_CC5P ((uint32_t)0x00020000) /*!<Capture/Compare 5 output Polarity */ -#define TIM_CCER_CC6E ((uint32_t)0x00100000) /*!<Capture/Compare 6 output enable */ -#define TIM_CCER_CC6P ((uint32_t)0x00200000) /*!<Capture/Compare 6 output Polarity */ -/******************* Bit definition for TIM_CNT register ********************/ -#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */ -#define TIM_CNT_UIFCPY ((uint32_t)0x80000000) /*!<Update interrupt flag copy */ -/******************* Bit definition for TIM_PSC register ********************/ -#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */ - -/******************* Bit definition for TIM_ARR register ********************/ -#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */ - -/******************* Bit definition for TIM_RCR register ********************/ -#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */ - -/******************* Bit definition for TIM_CCR1 register *******************/ -#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */ - -/******************* Bit definition for TIM_CCR2 register *******************/ -#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */ - -/******************* Bit definition for TIM_CCR3 register *******************/ -#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */ - -/******************* Bit definition for TIM_CCR4 register *******************/ -#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */ - -/******************* Bit definition for TIM_CCR5 register *******************/ -#define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /*!<Capture/Compare 5 Value */ -#define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /*!<Group Channel 5 and Channel 1 */ -#define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /*!<Group Channel 5 and Channel 2 */ -#define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /*!<Group Channel 5 and Channel 3 */ - -/******************* Bit definition for TIM_CCR6 register *******************/ -#define TIM_CCR6_CCR6 ((uint16_t)0xFFFF) /*!<Capture/Compare 6 Value */ - -/******************* Bit definition for TIM_BDTR register *******************/ -#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ -#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */ -#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */ -#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */ -#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */ -#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */ -#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */ -#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */ -#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */ - -#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */ -#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */ -#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */ - -#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */ -#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */ -#define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable for Break1 */ -#define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity for Break1 */ -#define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */ -#define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */ - -#define TIM_BDTR_BKF ((uint32_t)0x000F0000) /*!<Break Filter for Break1 */ -#define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /*!<Break Filter for Break2 */ - -#define TIM_BDTR_BK2E ((uint32_t)0x01000000) /*!<Break enable for Break2 */ -#define TIM_BDTR_BK2P ((uint32_t)0x02000000) /*!<Break Polarity for Break2 */ - -/******************* Bit definition for TIM_DCR register ********************/ -#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */ -#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */ -#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */ -#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */ -#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */ -#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */ - -#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */ -#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */ -#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */ -#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */ -#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */ -#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */ - -/******************* Bit definition for TIM_DMAR register *******************/ -#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */ - -/******************* Bit definition for TIM16_OR register *********************/ -#define TIM16_OR_TI1_RMP ((uint16_t)0x00C0) /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */ -#define TIM16_OR_TI1_RMP_0 ((uint16_t)0x0040) /*!<Bit 0 */ -#define TIM16_OR_TI1_RMP_1 ((uint16_t)0x0080) /*!<Bit 1 */ - -/******************* Bit definition for TIM1_OR register *********************/ -#define TIM1_OR_ETR_RMP ((uint16_t)0x000F) /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */ -#define TIM1_OR_ETR_RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */ -#define TIM1_OR_ETR_RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */ -#define TIM1_OR_ETR_RMP_2 ((uint16_t)0x0004) /*!<Bit 2 */ -#define TIM1_OR_ETR_RMP_3 ((uint16_t)0x0008) /*!<Bit 3 */ - -/******************* Bit definition for TIM8_OR register *********************/ -#define TIM8_OR_ETR_RMP ((uint16_t)0x000F) /*!<ETR_RMP[3:0] bits (TIM8 ETR remap) */ -#define TIM8_OR_ETR_RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */ -#define TIM8_OR_ETR_RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */ -#define TIM8_OR_ETR_RMP_2 ((uint16_t)0x0004) /*!<Bit 2 */ -#define TIM8_OR_ETR_RMP_3 ((uint16_t)0x0008) /*!<Bit 3 */ - -/****************** Bit definition for TIM_CCMR3 register *******************/ -#define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */ -#define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */ - -#define TIM_CCMR3_OC5M ((uint32_t)0x00000070) /*!<OC5M[2:0] bits (Output Compare 5 Mode) */ -#define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /*!<Bit 0 */ -#define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /*!<Bit 1 */ -#define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /*!<Bit 2 */ -#define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /*!<Bit 3 */ - -#define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /*!<Output Compare 5 Clear Enable */ - -#define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */ -#define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */ - -#define TIM_CCMR3_OC6M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ -#define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /*!<Bit 0 */ -#define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /*!<Bit 1 */ -#define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /*!<Bit 2 */ -#define TIM_CCMR3_OC6M_3 ((uint32_t)0x00100000) /*!<Bit 3 */ - -#define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */ - -/******************************************************************************/ -/* */ -/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ -/* */ -/******************************************************************************/ -/****************** Bit definition for USART_CR1 register *******************/ -#define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */ -#define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */ -#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */ -#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */ -#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */ -#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */ -#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */ -#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */ -#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */ -#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */ -#define USART_CR1_M ((uint32_t)0x00001000) /*!< Word length */ -#define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */ -#define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */ -#define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */ -#define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */ -#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */ -#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */ -#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */ -#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */ -#define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */ -#define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */ - -/****************** Bit definition for USART_CR2 register *******************/ -#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */ -#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */ -#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */ -#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */ -#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */ -#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */ -#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */ -#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */ -#define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */ -#define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */ -#define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */ -#define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */ -#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */ -#define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/ -#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */ -#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */ -#define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */ - -/****************** Bit definition for USART_CR3 register *******************/ -#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */ -#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */ -#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */ -#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */ -#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */ -#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */ -#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */ -#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */ -#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */ -#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */ -#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */ -#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */ -#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */ -#define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */ -#define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */ -#define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */ -#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */ -#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */ -#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */ -#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */ -#define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */ -#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */ - -/****************** Bit definition for USART_BRR register *******************/ -#define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /*!< Fraction of USARTDIV */ -#define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */ - -/****************** Bit definition for USART_GTPR register ******************/ -#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */ -#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< GT[7:0] bits (Guard time value) */ - - -/******************* Bit definition for USART_RTOR register *****************/ -#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */ -#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */ - -/******************* Bit definition for USART_RQR register ******************/ -#define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud Rate Request */ -#define USART_RQR_SBKRQ ((uint16_t)0x0002) /*!< Send Break Request */ -#define USART_RQR_MMRQ ((uint16_t)0x0004) /*!< Mute Mode Request */ -#define USART_RQR_RXFRQ ((uint16_t)0x0008) /*!< Receive Data flush Request */ -#define USART_RQR_TXFRQ ((uint16_t)0x0010) /*!< Transmit data flush Request */ - -/******************* Bit definition for USART_ISR register ******************/ -#define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */ -#define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */ -#define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */ -#define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */ -#define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */ -#define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */ -#define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */ -#define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */ -#define USART_ISR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */ -#define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */ -#define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */ -#define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */ -#define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */ -#define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */ -#define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */ -#define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */ -#define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */ -#define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */ -#define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */ -#define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */ -#define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */ -#define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */ - -/******************* Bit definition for USART_ICR register ******************/ -#define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */ -#define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */ -#define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */ -#define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */ -#define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */ -#define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */ -#define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */ -#define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */ -#define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */ -#define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */ -#define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */ -#define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */ - -/******************* Bit definition for USART_RDR register ******************/ -#define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */ - -/******************* Bit definition for USART_TDR register ******************/ -#define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */ - -/******************************************************************************/ -/* */ -/* Window WATCHDOG */ -/* */ -/******************************************************************************/ -/******************* Bit definition for WWDG_CR register ********************/ -#define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */ -#define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */ -#define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */ -#define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */ -#define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */ -#define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */ -#define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */ -#define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */ - -#define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */ - -/******************* Bit definition for WWDG_CFR register *******************/ -#define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */ -#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */ -#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */ -#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */ -#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */ -#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */ -#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */ -#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */ - -#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */ -#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */ -#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */ - -#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */ - -/******************* Bit definition for WWDG_SR register ********************/ -#define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */ - -/** - * @} - */ - - /** - * @} - */ - -#ifdef USE_STDPERIPH_DRIVER - #include "stm32f30x_conf.h" -#endif /*!< USE_STDPERIPH_DRIVER */ - -/** @addtogroup Exported_macro - * @{ - */ - -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32F30x_H */ - -/** - * @} - */ - - /** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_adc.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2411 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_adc.c - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Convertor (ADC) peripheral: - * + Initialization and Configuration - * + Analog Watchdog configuration - * + Temperature Sensor, Vbat & Vrefint (Internal Reference Voltage) management - * + Regular Channels Configuration - * + Regular Channels DMA Configuration - * + Injected channels Configuration - * + Interrupts and flags management - * + Dual mode configuration - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) select the ADC clock using the function RCC_ADCCLKConfig() - (#) Enable the ADC interface clock using RCC_AHBPeriphClockCmd(); - (#) ADC pins configuration - (++) Enable the clock for the ADC GPIOs using the following function: - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE); - (++) Configure these ADC pins in analog mode using GPIO_Init(); - (#) Configure the ADC conversion resolution, data alignment, external - trigger and edge, sequencer lenght and Enable/Disable the continuous mode - using the ADC_Init() function. - (#) Activate the ADC peripheral using ADC_Cmd() function. - - *** ADC channels group configuration *** - ======================================== - [..] - (+) To configure the ADC channels features, use ADC_Init(), ADC_InjectedInit() - and/or ADC_RegularChannelConfig() functions. - (+) To activate the continuous mode, use the ADC_ContinuousModeCmd() - function. - (+) To activate the Discontinuous mode, use the ADC_DiscModeCmd() functions. - (+) To activate the overrun mode, use the ADC_OverrunModeCmd() functions. - (+) To activate the calibration mode, use the ADC_StartCalibration() functions. - (+) To read the ADC converted values, use the ADC_GetConversionValue() - function. - - *** DMA for ADC channels features configuration *** - =================================================== - [..] - (+) To enable the DMA mode for ADC channels group, use the ADC_DMACmd() function. - (+) To configure the DMA transfer request, use ADC_DMAConfig() function. - - @endverbatim - * - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x_adc.h" -#include "stm32f30x_rcc.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @defgroup ADC - * @brief ADC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* CFGR register Mask */ -#define CFGR_CLEAR_Mask ((uint32_t)0xFDFFC007) - -/* JSQR register Mask */ -#define JSQR_CLEAR_Mask ((uint32_t)0x00000000) - -/* ADC ADON mask */ -#define CCR_CLEAR_MASK ((uint32_t)0xFFFC10E0) - -/* ADC JDRx registers offset */ -#define JDR_Offset ((uint8_t)0x80) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup ADC_Private_Functions - * @{ - */ - -/** @defgroup ADC_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This section provides functions allowing to: - (#) Initialize and configure the ADC injected and/or regular channels and dual mode. - (#) Management of the calibration process - (#) ADC Power-on Power-off - (#) Single ended or differential mode - (#) Enabling the queue of context and the auto delay mode - (#) The number of ADC conversions that will be done using the sequencer for regular - channel group - (#) Enable or disable the ADC peripheral - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the ADCx peripheral registers to their default reset values. - * @param ADCx: where x can be 1, 2,3 or 4 to select the ADC peripheral. - * @retval None - */ -void ADC_DeInit(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - - if((ADCx == ADC1) || (ADCx == ADC2)) - { - /* Enable ADC1/ADC2 reset state */ - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ADC12, ENABLE); - /* Release ADC1/ADC2 from reset state */ - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ADC12, DISABLE); - } - else if((ADCx == ADC3) || (ADCx == ADC4)) - { - /* Enable ADC3/ADC4 reset state */ - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ADC34, ENABLE); - /* Release ADC3/ADC4 from reset state */ - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ADC34, DISABLE); - } -} -/** - * @brief Initializes the ADCx peripheral according to the specified parameters - * in the ADC_InitStruct. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains - * the configuration information for the specified ADC peripheral. - * @retval None - */ -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) -{ - uint32_t tmpreg1 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CONVMODE(ADC_InitStruct->ADC_ContinuousConvMode)); - assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); - assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConvEvent)); - assert_param(IS_EXTERNALTRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigEventEdge)); - assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); - assert_param(IS_ADC_OVRUNMODE(ADC_InitStruct->ADC_OverrunMode)); - assert_param(IS_ADC_AUTOINJECMODE(ADC_InitStruct->ADC_AutoInjMode)); - assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfRegChannel)); - - /*---------------------------- ADCx CFGR Configuration -----------------*/ - /* Get the ADCx CFGR value */ - tmpreg1 = ADCx->CFGR; - /* Clear SCAN bit */ - tmpreg1 &= CFGR_CLEAR_Mask; - /* Configure ADCx: scan conversion mode */ - /* Set SCAN bit according to ADC_ScanConvMode value */ - tmpreg1 |= (uint32_t)ADC_InitStruct->ADC_ContinuousConvMode | - ADC_InitStruct->ADC_Resolution| - ADC_InitStruct->ADC_ExternalTrigConvEvent| - ADC_InitStruct->ADC_ExternalTrigEventEdge| - ADC_InitStruct->ADC_DataAlign| - ADC_InitStruct->ADC_OverrunMode| - ADC_InitStruct->ADC_AutoInjMode; - - /* Write to ADCx CFGR */ - ADCx->CFGR = tmpreg1; - - /*---------------------------- ADCx SQR1 Configuration -----------------*/ - /* Get the ADCx SQR1 value */ - tmpreg1 = ADCx->SQR1; - /* Clear L bits */ - tmpreg1 &= ~(uint32_t)(ADC_SQR1_L); - /* Configure ADCx: regular channel sequence length */ - /* Set L bits according to ADC_NbrOfRegChannel value */ - tmpreg1 |= (uint32_t) (ADC_InitStruct->ADC_NbrOfRegChannel - 1); - /* Write to ADCx SQR1 */ - ADCx->SQR1 = tmpreg1; - -} - -/** - * @brief Fills each ADC_InitStruct member with its default value. - * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized. - * @retval None - */ -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) -{ - /* Reset ADC init structure parameters values */ - ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; - ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b; - ADC_InitStruct->ADC_ExternalTrigConvEvent = ADC_ExternalTrigConvEvent_0; - ADC_InitStruct->ADC_ExternalTrigEventEdge = ADC_ExternalTrigEventEdge_None; - ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; - ADC_InitStruct->ADC_OverrunMode = DISABLE; - ADC_InitStruct->ADC_AutoInjMode = DISABLE; - ADC_InitStruct->ADC_NbrOfRegChannel = 1; -} - -/** - * @brief Initializes the ADCx peripheral according to the specified parameters - * in the ADC_InitStruct. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param ADC_InjectInitStruct: pointer to an ADC_InjecInitTypeDef structure that contains - * the configuration information for the specified ADC injected channel. - * @retval None - */ -void ADC_InjectedInit(ADC_TypeDef* ADCx, ADC_InjectedInitTypeDef* ADC_InjectedInitStruct) -{ - uint32_t tmpreg1 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_InjectedInitStruct->ADC_ExternalTrigInjecConvEvent)); - assert_param(IS_EXTERNALTRIGINJ_EDGE(ADC_InjectedInitStruct->ADC_ExternalTrigInjecEventEdge)); - assert_param(IS_ADC_INJECTED_LENGTH(ADC_InjectedInitStruct->ADC_NbrOfInjecChannel)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedInitStruct->ADC_InjecSequence1)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedInitStruct->ADC_InjecSequence2)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedInitStruct->ADC_InjecSequence3)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedInitStruct->ADC_InjecSequence4)); - - /*---------------------------- ADCx JSQR Configuration -----------------*/ - /* Get the ADCx JSQR value */ - tmpreg1 = ADCx->JSQR; - /* Clear L bits */ - tmpreg1 &= JSQR_CLEAR_Mask; - /* Configure ADCx: Injected channel sequence length, external trigger, - external trigger edge and sequences - */ - tmpreg1 = (uint32_t) ((ADC_InjectedInitStruct->ADC_NbrOfInjecChannel - (uint8_t)1) | - ADC_InjectedInitStruct->ADC_ExternalTrigInjecConvEvent | - ADC_InjectedInitStruct->ADC_ExternalTrigInjecEventEdge | - (uint32_t)((ADC_InjectedInitStruct->ADC_InjecSequence1) << 8) | - (uint32_t)((ADC_InjectedInitStruct->ADC_InjecSequence2) << 14) | - (uint32_t)((ADC_InjectedInitStruct->ADC_InjecSequence3) << 20) | - (uint32_t)((ADC_InjectedInitStruct->ADC_InjecSequence4) << 26)); - /* Write to ADCx SQR1 */ - ADCx->JSQR = tmpreg1; -} - -/** - * @brief Fills each ADC_InjectedInitStruct member with its default value. - * @param ADC_InjectedInitStruct : pointer to an ADC_InjectedInitTypeDef structure which will be initialized. - * @retval None - */ -void ADC_InjectedStructInit(ADC_InjectedInitTypeDef* ADC_InjectedInitStruct) -{ - ADC_InjectedInitStruct->ADC_ExternalTrigInjecConvEvent = ADC_ExternalTrigInjecConvEvent_0; - ADC_InjectedInitStruct->ADC_ExternalTrigInjecEventEdge = ADC_ExternalTrigInjecEventEdge_None; - ADC_InjectedInitStruct->ADC_NbrOfInjecChannel = 1; - ADC_InjectedInitStruct->ADC_InjecSequence1 = ADC_InjectedChannel_1; - ADC_InjectedInitStruct->ADC_InjecSequence2 = ADC_InjectedChannel_1; - ADC_InjectedInitStruct->ADC_InjecSequence3 = ADC_InjectedChannel_1; - ADC_InjectedInitStruct->ADC_InjecSequence4 = ADC_InjectedChannel_1; -} - -/** - * @brief Initializes the ADCs peripherals according to the specified parameters - * in the ADC_CommonInitStruct. - * @param ADCx: where x can be 1 or 4 to select the ADC peripheral. - * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure - * that contains the configuration information for All ADCs peripherals. - * @retval None - */ -void ADC_CommonInit(ADC_TypeDef* ADCx, ADC_CommonInitTypeDef* ADC_CommonInitStruct) -{ - uint32_t tmpreg1 = 0; - /* Check the parameters */ - assert_param(IS_ADC_MODE(ADC_CommonInitStruct->ADC_Mode)); - assert_param(IS_ADC_CLOCKMODE(ADC_CommonInitStruct->ADC_Clock)); - assert_param(IS_ADC_DMA_MODE(ADC_CommonInitStruct->ADC_DMAMode)); - assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode)); - assert_param(IS_ADC_TWOSAMPLING_DELAY(ADC_CommonInitStruct->ADC_TwoSamplingDelay)); - - if((ADCx == ADC1) || (ADCx == ADC2)) - { - /* Get the ADC CCR value */ - tmpreg1 = ADC1_2->CCR; - - /* Clear MULTI, DELAY, DMA and ADCPRE bits */ - tmpreg1 &= CCR_CLEAR_MASK; - } - else - { - /* Get the ADC CCR value */ - tmpreg1 = ADC3_4->CCR; - - /* Clear MULTI, DELAY, DMA and ADCPRE bits */ - tmpreg1 &= CCR_CLEAR_MASK; - } - /*---------------------------- ADC CCR Configuration -----------------*/ - /* Configure ADCx: Multi mode, Delay between two sampling time, ADC clock, DMA mode - and DMA access mode for dual mode */ - /* Set MULTI bits according to ADC_Mode value */ - /* Set CKMODE bits according to ADC_Clock value */ - /* Set MDMA bits according to ADC_DMAAccessMode value */ - /* Set DMACFG bits according to ADC_DMAMode value */ - /* Set DELAY bits according to ADC_TwoSamplingDelay value */ - tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode | - ADC_CommonInitStruct->ADC_Clock | - ADC_CommonInitStruct->ADC_DMAAccessMode | - (uint32_t)(ADC_CommonInitStruct->ADC_DMAMode << 12) | - (uint32_t)((uint32_t)ADC_CommonInitStruct->ADC_TwoSamplingDelay << 8)); - - if((ADCx == ADC1) || (ADCx == ADC2)) - { - /* Write to ADC CCR */ - ADC1_2->CCR = tmpreg1; - } - else - { - /* Write to ADC CCR */ - ADC3_4->CCR = tmpreg1; - } -} - -/** - * @brief Fills each ADC_CommonInitStruct member with its default value. - * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure - * which will be initialized. - * @retval None - */ -void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) -{ - /* Initialize the ADC_Mode member */ - ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent; - - /* initialize the ADC_Clock member */ - ADC_CommonInitStruct->ADC_Clock = ADC_Clock_AsynClkMode; - - /* Initialize the ADC_DMAAccessMode member */ - ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled; - - /* Initialize the ADC_DMAMode member */ - ADC_CommonInitStruct->ADC_DMAMode = ADC_DMAMode_OneShot; - - /* Initialize the ADC_TwoSamplingDelay member */ - ADC_CommonInitStruct->ADC_TwoSamplingDelay = 0; - -} - -/** - * @brief Enables or disables the specified ADC peripheral. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param NewState: new state of the ADCx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the ADEN bit */ - ADCx->CR |= ADC_CR_ADEN; - } - else - { - /* Disable the selected ADC peripheral: Set the ADDIS bit */ - ADCx->CR |= ADC_CR_ADDIS; - } -} - -/** - * @brief Starts the selected ADC calibration process. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @retval None - */ -void ADC_StartCalibration(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Set the ADCAL bit */ - ADCx->CR |= ADC_CR_ADCAL; -} - -/** - * @brief Returns the ADCx calibration value. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @retval None - */ -uint32_t ADC_GetCalibrationValue(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Return the selected ADC calibration value */ - return (uint32_t)ADCx->CALFACT; -} - -/** - * @brief Sets the ADCx calibration register. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @retval None - */ -void ADC_SetCalibrationValue(ADC_TypeDef* ADCx, uint32_t ADC_Calibration) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Set the ADC calibration register value */ - ADCx->CALFACT = ADC_Calibration; -} - -/** - * @brief Select the ADC calibration mode. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param ADC_CalibrationMode: the ADC calibration mode. - * This parameter can be one of the following values: - * @arg ADC_CalibrationMode_Single: to select the calibration for single channel - * @arg ADC_CalibrationMode_Differential: to select the calibration for differential channel - * @retval None - */ -void ADC_SelectCalibrationMode(ADC_TypeDef* ADCx, uint32_t ADC_CalibrationMode) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CALIBRATION_MODE(ADC_CalibrationMode)); - /* Set or Reset the ADCALDIF bit */ - ADCx->CR &= (~ADC_CR_ADCALDIF); - ADCx->CR |= ADC_CalibrationMode; - -} - -/** - * @brief Gets the selected ADC calibration status. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @retval The new state of ADC calibration (SET or RESET). - */ -FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Check the status of CAL bit */ - if ((ADCx->CR & ADC_CR_ADCAL) != (uint32_t)RESET) - { - /* CAL bit is set: calibration on going */ - bitstatus = SET; - } - else - { - /* CAL bit is reset: end of calibration */ - bitstatus = RESET; - } - /* Return the CAL bit status */ - return bitstatus; -} - -/** - * @brief ADC Disable Command. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @retval None - */ -void ADC_DisableCmd(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Set the ADDIS bit */ - ADCx->CR |= ADC_CR_ADDIS; -} - - -/** - * @brief Gets the selected ADC disable command Status. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @retval The new state of ADC ADC disable command (SET or RESET). - */ -FlagStatus ADC_GetDisableCmdStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Check the status of ADDIS bit */ - if ((ADCx->CR & ADC_CR_ADDIS) != (uint32_t)RESET) - { - /* ADDIS bit is set */ - bitstatus = SET; - } - else - { - /* ADDIS bit is reset */ - bitstatus = RESET; - } - /* Return the ADDIS bit status */ - return bitstatus; -} - -/** - * @brief Enables or disables the specified ADC Voltage Regulator. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param NewState: new state of the ADCx Voltage Regulator. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_VoltageRegulatorCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* set the intermediate state before moving the ADC voltage regulator - from enable state to disable state or from disable state to enable state */ - ADCx->CR &= ~(ADC_CR_ADVREGEN); - - if (NewState != DISABLE) - { - /* Set the ADVREGEN bit 0 */ - ADCx->CR |= ADC_CR_ADVREGEN_0; - } - else - { - /* Set the ADVREGEN bit 1 */ - ADCx->CR |=ADC_CR_ADVREGEN_1; - } -} - -/** - * @brief Selectes the differential mode for a specific channel - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure for the analog watchdog. - * This parameter can be one of the following values: - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @note : Channel 15, 16 and 17 are fixed to single-ended inputs mode. - * @retval None - */ -void ADC_SelectDifferentialMode(ADC_TypeDef* ADCx, uint8_t ADC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_DIFFCHANNEL(ADC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the DIFSEL bit */ - ADCx->DIFSEL |= (uint32_t)(1 << ADC_Channel ); - } - else - { - /* Reset the DIFSEL bit */ - ADCx->DIFSEL &= ~(uint32_t)(1 << ADC_Channel); - } -} - -/** - * @brief Selects the Queue Of Context Mode for injected channels. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param NewState: new state of the Queue Of Context Mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_SelectQueueOfContextMode(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the JQM bit */ - ADCx->CFGR |= (uint32_t)(ADC_CFGR_JQM ); - } - else - { - /* Reset the JQM bit */ - ADCx->CFGR &= ~(uint32_t)(ADC_CFGR_JQM); - } -} - -/** - * @brief Selects the ADC Delayed Conversion Mode. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param NewState: new state of the ADC Delayed Conversion Mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_AutoDelayCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the AUTDLY bit */ - ADCx->CFGR |= (uint32_t)(ADC_CFGR_AUTDLY ); - } - else - { - /* Reset the AUTDLY bit */ - ADCx->CFGR &= ~(uint32_t)(ADC_CFGR_AUTDLY); - } -} - -/** - * @} - */ - -/** @defgroup ADC_Group2 Analog Watchdog configuration functions - * @brief Analog Watchdog configuration functions - * -@verbatim - =============================================================================== - ##### Analog Watchdog configuration functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure the 3 Analog Watchdogs - (AWDG1, AWDG2 and AWDG3) in the ADC. - - [..] A typical configuration Analog Watchdog is done following these steps : - (#) The ADC guarded channel(s) is (are) selected using the functions: - (++) ADC_AnalogWatchdog1SingleChannelConfig(). - (++) ADC_AnalogWatchdog2SingleChannelConfig(). - (++) ADC_AnalogWatchdog3SingleChannelConfig(). - - (#) The Analog watchdog lower and higher threshold are configured using the functions: - (++) ADC_AnalogWatchdog1ThresholdsConfig(). - (++) ADC_AnalogWatchdog2ThresholdsConfig(). - (++) ADC_AnalogWatchdog3ThresholdsConfig(). - - (#) The Analog watchdog is enabled and configured to enable the check, on one - or more channels, using the function: - (++) ADC_AnalogWatchdogCmd(). - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the analog watchdog on single/all regular - * or injected channels - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. - * This parameter can be one of the following values: - * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel - * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel - * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel - * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel - * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel - * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels - * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog - * @retval None - */ -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); - /* Get the old register value */ - tmpreg = ADCx->CFGR; - /* Clear AWDEN, AWDENJ and AWDSGL bits */ - tmpreg &= ~(uint32_t)(ADC_CFGR_AWD1SGL|ADC_CFGR_AWD1EN|ADC_CFGR_JAWD1EN); - /* Set the analog watchdog enable mode */ - tmpreg |= ADC_AnalogWatchdog; - /* Store the new register value */ - ADCx->CFGR = tmpreg; -} - -/** - * @brief Configures the high and low thresholds of the analog watchdog1. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param HighThreshold: the ADC analog watchdog High threshold value. - * This parameter must be a 12bit value. - * @param LowThreshold: the ADC analog watchdog Low threshold value. - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_THRESHOLD(HighThreshold)); - assert_param(IS_ADC_THRESHOLD(LowThreshold)); - /* Set the ADCx high threshold */ - ADCx->TR1 &= ~(uint32_t)ADC_TR1_HT1; - ADCx->TR1 |= (uint32_t)((uint32_t)HighThreshold << 16); - - /* Set the ADCx low threshold */ - ADCx->TR1 &= ~(uint32_t)ADC_TR1_LT1; - ADCx->TR1 |= LowThreshold; -} - -/** - * @brief Configures the high and low thresholds of the analog watchdog2. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param HighThreshold: the ADC analog watchdog High threshold value. - * This parameter must be a 8bit value. - * @param LowThreshold: the ADC analog watchdog Low threshold value. - * This parameter must be a 8bit value. - * @retval None - */ -void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold, - uint8_t LowThreshold) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Set the ADCx high threshold */ - ADCx->TR2 &= ~(uint32_t)ADC_TR2_HT2; - ADCx->TR2 |= (uint32_t)((uint32_t)HighThreshold << 16); - - /* Set the ADCx low threshold */ - ADCx->TR2 &= ~(uint32_t)ADC_TR2_LT2; - ADCx->TR2 |= LowThreshold; -} - -/** - * @brief Configures the high and low thresholds of the analog watchdog3. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param HighThreshold: the ADC analog watchdog High threshold value. - * This parameter must be a 8bit value. - * @param LowThreshold: the ADC analog watchdog Low threshold value. - * This parameter must be a 8bit value. - * @retval None - */ -void ADC_AnalogWatchdog3ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold, - uint8_t LowThreshold) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Set the ADCx high threshold */ - ADCx->TR3 &= ~(uint32_t)ADC_TR3_HT3; - ADCx->TR3 |= (uint32_t)((uint32_t)HighThreshold << 16); - - /* Set the ADCx low threshold */ - ADCx->TR3 &= ~(uint32_t)ADC_TR3_LT3; - ADCx->TR3 |= LowThreshold; -} - -/** - * @brief Configures the analog watchdog 2 guarded single channel - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure for the analog watchdog. - * This parameter can be one of the following values: - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @retval None - */ -void ADC_AnalogWatchdog1SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - /* Get the old register value */ - tmpreg = ADCx->CFGR; - /* Clear the Analog watchdog channel select bits */ - tmpreg &= ~(uint32_t)ADC_CFGR_AWD1CH; - /* Set the Analog watchdog channel */ - tmpreg |= (uint32_t)((uint32_t)ADC_Channel << 26); - /* Store the new register value */ - ADCx->CFGR = tmpreg; -} - -/** - * @brief Configures the analog watchdog 2 guarded single channel - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure for the analog watchdog. - * This parameter can be one of the following values: - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @retval None - */ -void ADC_AnalogWatchdog2SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - /* Get the old register value */ - tmpreg = ADCx->AWD2CR; - /* Clear the Analog watchdog channel select bits */ - tmpreg &= ~(uint32_t)ADC_AWD2CR_AWD2CH; - /* Set the Analog watchdog channel */ - tmpreg |= (uint32_t)1 << (ADC_Channel); - /* Store the new register value */ - ADCx->AWD2CR |= tmpreg; -} - -/** - * @brief Configures the analog watchdog 3 guarded single channel - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure for the analog watchdog. - * This parameter can be one of the following values: - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @retval None - */ -void ADC_AnalogWatchdog3SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - /* Get the old register value */ - tmpreg = ADCx->AWD3CR; - /* Clear the Analog watchdog channel select bits */ - tmpreg &= ~(uint32_t)ADC_AWD3CR_AWD3CH; - /* Set the Analog watchdog channel */ - tmpreg |= (uint32_t)1 << (ADC_Channel); - /* Store the new register value */ - ADCx->AWD3CR |= tmpreg; -} - -/** - * @} - */ - -/** @defgroup ADC_Group3 Temperature Sensor - Vrefint (Internal Reference Voltage) and VBAT management functions - * @brief Vbat, Temperature Sensor & Vrefint (Internal Reference Voltage) management function - * -@verbatim - ==================================================================================================== - ##### Temperature Sensor - Vrefint (Internal Reference Voltage) and VBAT management functions ##### - ==================================================================================================== - - [..] This section provides a function allowing to enable/ disable the internal - connections between the ADC and the Vbat/2, Temperature Sensor and the Vrefint source. - - [..] A typical configuration to get the Temperature sensor and Vrefint channels - voltages is done following these steps : - (#) Enable the internal connection of Vbat/2, Temperature sensor and Vrefint sources - with the ADC channels using: - (++) ADC_TempSensorCmd() - (++) ADC_VrefintCmd() - (++) ADC_VbatCmd() - - (#) select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint and/or ADC_Channel_Vbat using - (++) ADC_RegularChannelConfig() or - (++) ADC_InjectedInit() functions - - (#) Get the voltage values, using: - (++) ADC_GetConversionValue() or - (++) ADC_GetInjectedConversionValue(). - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the temperature sensor channel. - * @param ADCx: where x can be 1 to select the ADC peripheral. - * @param NewState: new state of the temperature sensor. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_TempSensorCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the temperature sensor channel*/ - ADC1_2->CCR |= ADC12_CCR_TSEN; - } - else - { - /* Disable the temperature sensor channel*/ - ADC1_2->CCR &= ~(uint32_t)ADC12_CCR_TSEN; - } -} - -/** - * @brief Enables or disables the Vrefint channel. - * @param ADCx: where x can be 1 or 4 to select the ADC peripheral. - * @param NewState: new state of the Vrefint. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_VrefintCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if((ADCx == ADC1) || (ADCx == ADC2)) - { - if (NewState != DISABLE) - { - /* Enable the Vrefint channel*/ - ADC1_2->CCR |= ADC12_CCR_VREFEN; - } - else - { - /* Disable the Vrefint channel*/ - ADC1_2->CCR &= ~(uint32_t)ADC12_CCR_VREFEN; - } - } - else - { - if (NewState != DISABLE) - { - /* Enable the Vrefint channel*/ - ADC3_4->CCR |= ADC34_CCR_VREFEN; - } - else - { - /* Disable the Vrefint channel*/ - ADC3_4->CCR &= ~(uint32_t)ADC34_CCR_VREFEN; - } - } -} - -/** - * @brief Enables or disables the Vbat channel. - * @param ADCx: where x can be 1 to select the ADC peripheral. - * @param NewState: new state of the Vbat. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_VbatCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Vbat channel*/ - ADC1_2->CCR |= ADC12_CCR_VBATEN; - } - else - { - /* Disable the Vbat channel*/ - ADC1_2->CCR &= ~(uint32_t)ADC12_CCR_VBATEN; - } -} - -/** - * @} - */ - -/** @defgroup ADC_Group4 Regular Channels Configuration functions - * @brief Regular Channels Configuration functions - * -@verbatim - =============================================================================== - ##### Channels Configuration functions ##### - =============================================================================== - - [..] This section provides functions allowing to manage the ADC regular channels. - - [..] To configure a regular sequence of channels use: - (#) ADC_RegularChannelConfig() - this fuction allows: - (++) Configure the rank in the regular group sequencer for each channel - (++) Configure the sampling time for each channel - - (#) ADC_RegularChannelSequencerLengthConfig() to set the length of the regular sequencer - - [..] The regular trigger is configured using the following functions: - (#) ADC_SelectExternalTrigger() - (#) ADC_ExternalTriggerPolarityConfig() - - [..] The start and the stop conversion are controlled by: - (#) ADC_StartConversion() - (#) ADC_StopConversion() - - [..] - (@)Please Note that the following features for regular channels are configurated - using the ADC_Init() function : - (++) continuous mode activation - (++) Resolution - (++) Data Alignement - (++) Overrun Mode. - - [..] Get the conversion data: This subsection provides an important function in - the ADC peripheral since it returns the converted data of the current - regular channel. When the Conversion value is read, the EOC Flag is - automatically cleared. - - [..] To configure the discontinous mode, the following functions should be used: - (#) ADC_DiscModeChannelCountConfig() to configure the number of discontinuous channel to be converted. - (#) ADC_DiscModeCmd() to enable the discontinuous mode. - - [..] To configure and enable/disable the Channel offset use the functions: - (++) ADC_SetChannelOffset1() - (++) ADC_SetChannelOffset2() - (++) ADC_SetChannelOffset3() - (++) ADC_SetChannelOffset4() - (++) ADC_ChannelOffset1Cmd() - (++) ADC_ChannelOffset2Cmd() - (++) ADC_ChannelOffset3Cmd() - (++) ADC_ChannelOffset4Cmd() - -@endverbatim - * @{ - */ - -/** - * @brief Configures for the selected ADC regular channel its corresponding - * rank in the sequencer and its sample time. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16. - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles - * @arg ADC_SampleTime_2Cycles5: Sample time equal to 2.5 cycles - * @arg ADC_SampleTime_4Cycles5: Sample time equal to 4.5 cycles - * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles - * @arg ADC_SampleTime_19Cycles5: Sample time equal to 19.5 cycles - * @arg ADC_SampleTime_61Cycles5: Sample time equal to 61.5 cycles - * @arg ADC_SampleTime_181Cycles5: Sample time equal to 181.5 cycles - * @arg ADC_SampleTime_601Cycles5: Sample time equal to 601.5 cycles - * @retval None - */ -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - - /* Regular sequence configuration */ - /* For Rank 1 to 4 */ - if (Rank < 5) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR1; - /* Calculate the mask to clear */ - tmpreg2 = 0x1F << (6 * (Rank )); - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)(ADC_Channel) << (6 * (Rank)); - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SQR1 = tmpreg1; - } - /* For Rank 5 to 9 */ - else if (Rank < 10) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR2; - /* Calculate the mask to clear */ - tmpreg2 = ADC_SQR2_SQ5 << (6 * (Rank - 5)); - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)(ADC_Channel) << (6 * (Rank - 5)); - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SQR2 = tmpreg1; - } - /* For Rank 10 to 14 */ - else if (Rank < 15) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR3; - /* Calculate the mask to clear */ - tmpreg2 = ADC_SQR3_SQ10 << (6 * (Rank - 10)); - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)(ADC_Channel) << (6 * (Rank - 10)); - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SQR3 = tmpreg1; - } - else - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR4; - /* Calculate the mask to clear */ - tmpreg2 = ADC_SQR3_SQ15 << (6 * (Rank - 15)); - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)(ADC_Channel) << (6 * (Rank - 15)); - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SQR4 = tmpreg1; - } - - /* Channel sampling configuration */ - /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ - if (ADC_Channel > ADC_Channel_9) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR2; - /* Calculate the mask to clear */ - tmpreg2 = ADC_SMPR2_SMP10 << (3 * (ADC_Channel - 10)); - /* Clear the old channel sample time */ - ADCx->SMPR2 &= ~tmpreg2; - /* Calculate the mask to set */ - ADCx->SMPR2 |= (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR1; - /* Calculate the mask to clear */ - tmpreg2 = ADC_SMPR1_SMP1 << (3 * (ADC_Channel - 1)); - /* Clear the old channel sample time */ - ADCx->SMPR1 &= ~tmpreg2; - /* Calculate the mask to set */ - ADCx->SMPR1 |= (uint32_t)ADC_SampleTime << (3 * (ADC_Channel)); - } -} - -/** - * @brief Sets the ADC regular channel sequence lenght. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param SequenceLength: The Regular sequence length. This parameter must be between 1 to 16. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_RegularChannelSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t SequencerLength) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Configure the ADC sequence lenght */ - ADCx->SQR1 &= ~(uint32_t)ADC_SQR1_L; - ADCx->SQR1 |= (uint32_t)(SequencerLength - 1); -} - -/** - * @brief External Trigger Enable and Polarity Selection for regular channels. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param ADC_ExternalTrigConvEvent: ADC external Trigger source. - * This parameter can be one of the following values: - * @arg ADC_ExternalTrigger_Event0: External trigger event 0 - * @arg ADC_ExternalTrigger_Event1: External trigger event 1 - * @arg ADC_ExternalTrigger_Event2: External trigger event 2 - * @arg ADC_ExternalTrigger_Event3: External trigger event 3 - * @arg ADC_ExternalTrigger_Event4: External trigger event 4 - * @arg ADC_ExternalTrigger_Event5: External trigger event 5 - * @arg ADC_ExternalTrigger_Event6: External trigger event 6 - * @arg ADC_ExternalTrigger_Event7: External trigger event 7 - * @arg ADC_ExternalTrigger_Event8: External trigger event 8 - * @arg ADC_ExternalTrigger_Event9: External trigger event 9 - * @arg ADC_ExternalTrigger_Event10: External trigger event 10 - * @arg ADC_ExternalTrigger_Event11: External trigger event 11 - * @arg ADC_ExternalTrigger_Event12: External trigger event 12 - * @arg ADC_ExternalTrigger_Event13: External trigger event 13 - * @arg ADC_ExternalTrigger_Event14: External trigger event 14 - * @arg ADC_ExternalTrigger_Event15: External trigger event 15 - * @param ADC_ExternalTrigEventEdge: ADC external Trigger Polarity. - * This parameter can be one of the following values: - * @arg ADC_ExternalTrigEventEdge_OFF: Hardware trigger detection disabled - * (conversions can be launched by software) - * @arg ADC_ExternalTrigEventEdge_RisingEdge: Hardware trigger detection on the rising edge - * @arg ADC_ExternalTrigEventEdge_FallingEdge: Hardware trigger detection on the falling edge - * @arg ADC_ExternalTrigEventEdge_BothEdge: Hardware trigger detection on both the rising and falling edges - * @retval None - */ -void ADC_ExternalTriggerConfig(ADC_TypeDef* ADCx, uint16_t ADC_ExternalTrigConvEvent, uint16_t ADC_ExternalTrigEventEdge) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_EXT_TRIG(ADC_ExternalTrigConvEvent)); - assert_param(IS_EXTERNALTRIG_EDGE(ADC_ExternalTrigEventEdge)); - - /* Disable the selected ADC conversion on external event */ - ADCx->CFGR &= ~(ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL); - ADCx->CFGR |= (uint32_t)(ADC_ExternalTrigEventEdge | ADC_ExternalTrigConvEvent); -} - -/** - * @brief Enables or disables the selected ADC start conversion . - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @retval None - */ -void ADC_StartConversion(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Set the ADSTART bit */ - ADCx->CR |= ADC_CR_ADSTART; -} - -/** - * @brief Gets the selected ADC start conversion Status. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @retval The new state of ADC start conversion (SET or RESET). - */ -FlagStatus ADC_GetStartConversionStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Check the status of ADSTART bit */ - if ((ADCx->CR & ADC_CR_ADSTART) != (uint32_t)RESET) - { - /* ADSTART bit is set */ - bitstatus = SET; - } - else - { - /* ADSTART bit is reset */ - bitstatus = RESET; - } - /* Return the ADSTART bit status */ - return bitstatus; -} - -/** - * @brief Stops the selected ADC ongoing conversion. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @retval None - */ -void ADC_StopConversion(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Set the ADSTP bit */ - ADCx->CR |= ADC_CR_ADSTP; -} - - -/** - * @brief Configures the discontinuous mode for the selected ADC regular - * group channel. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param Number: specifies the discontinuous mode regular channel - * count value. This number must be between 1 and 8. - * @retval None - */ -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); - /* Get the old register value */ - tmpreg1 = ADCx->CFGR; - /* Clear the old discontinuous mode channel count */ - tmpreg1 &= ~(uint32_t)(ADC_CFGR_DISCNUM); - /* Set the discontinuous mode channel count */ - tmpreg2 = Number - 1; - tmpreg1 |= tmpreg2 << 17; - /* Store the new register value */ - ADCx->CFGR = tmpreg1; -} - -/** - * @brief Enables or disables the discontinuous mode on regular group - * channel for the specified ADC - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param NewState: new state of the selected ADC discontinuous mode - * on regular group channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC regular discontinuous mode */ - ADCx->CFGR |= ADC_CFGR_DISCEN; - } - else - { - /* Disable the selected ADC regular discontinuous mode */ - ADCx->CFGR &= ~(uint32_t)(ADC_CFGR_DISCEN); - } -} - -/** - * @brief Returns the last ADCx conversion result data for regular channel. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @retval The Data conversion value. - */ -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Return the selected ADC conversion value */ - return (uint16_t) ADCx->DR; -} - -/** - * @brief Returns the last ADC1, ADC2, ADC3 and ADC4 regular conversions results - * data in the selected dual mode. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @retval The Data conversion value. - * @note In dual mode, the value returned by this function is as following - * Data[15:0] : these bits contain the regular data of the Master ADC. - * Data[31:16]: these bits contain the regular data of the Slave ADC. - */ -uint32_t ADC_GetDualModeConversionValue(ADC_TypeDef* ADCx) -{ - uint32_t tmpreg1 = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - if((ADCx == ADC1) || (ADCx== ADC2)) - { - /* Get the dual mode conversion value */ - tmpreg1 = ADC1_2->CDR; - } - else - { - /* Get the dual mode conversion value */ - tmpreg1 = ADC3_4->CDR; - } - /* Return the dual mode conversion value */ - return (uint32_t) tmpreg1; -} - -/** - * @brief Set the ADC channels conversion value offset1 - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @param Offset: the offset value for the selected ADC Channel - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_SetChannelOffset1(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_OFFSET(Offset)); - - /* Select the Channel */ - ADCx->OFR1 &= ~ (uint32_t) ADC_OFR1_OFFSET1_CH; - ADCx->OFR1 |= (uint32_t)((uint32_t)ADC_Channel << 26); - - /* Set the data offset */ - ADCx->OFR1 &= ~ (uint32_t) ADC_OFR1_OFFSET1; - ADCx->OFR1 |= (uint32_t)Offset; -} - -/** - * @brief Set the ADC channels conversion value offset2 - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @param Offset: the offset value for the selected ADC Channel - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_SetChannelOffset2(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_OFFSET(Offset)); - - /* Select the Channel */ - ADCx->OFR2 &= ~ (uint32_t) ADC_OFR2_OFFSET2_CH; - ADCx->OFR2 |= (uint32_t)((uint32_t)ADC_Channel << 26); - - /* Set the data offset */ - ADCx->OFR2 &= ~ (uint32_t) ADC_OFR2_OFFSET2; - ADCx->OFR2 |= (uint32_t)Offset; -} - -/** - * @brief Set the ADC channels conversion value offset3 - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @param Offset: the offset value for the selected ADC Channel - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_SetChannelOffset3(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_OFFSET(Offset)); - - /* Select the Channel */ - ADCx->OFR3 &= ~ (uint32_t) ADC_OFR3_OFFSET3_CH; - ADCx->OFR3 |= (uint32_t)((uint32_t)ADC_Channel << 26); - - /* Set the data offset */ - ADCx->OFR3 &= ~ (uint32_t) ADC_OFR3_OFFSET3; - ADCx->OFR3 |= (uint32_t)Offset; -} - -/** - * @brief Set the ADC channels conversion value offset4 - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @param Offset: the offset value for the selected ADC Channel - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_SetChannelOffset4(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_OFFSET(Offset)); - - /* Select the Channel */ - ADCx->OFR4 &= ~ (uint32_t) ADC_OFR4_OFFSET4_CH; - ADCx->OFR4 |= (uint32_t)((uint32_t)ADC_Channel << 26); - - /* Set the data offset */ - ADCx->OFR4 &= ~ (uint32_t) ADC_OFR4_OFFSET4; - ADCx->OFR4 |= (uint32_t)Offset; -} - -/** - * @brief Enables or disables the Offset1. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param NewState: new state of the ADCx offset1. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ChannelOffset1Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the OFFSET1_EN bit */ - ADCx->OFR1 |= ADC_OFR1_OFFSET1_EN; - } - else - { - /* Reset the OFFSET1_EN bit */ - ADCx->OFR1 &= ~(ADC_OFR1_OFFSET1_EN); - } -} - -/** - * @brief Enables or disables the Offset2. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param NewState: new state of the ADCx offset2. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ChannelOffset2Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the OFFSET1_EN bit */ - ADCx->OFR2 |= ADC_OFR2_OFFSET2_EN; - } - else - { - /* Reset the OFFSET1_EN bit */ - ADCx->OFR2 &= ~(ADC_OFR2_OFFSET2_EN); - } -} - -/** - * @brief Enables or disables the Offset3. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param NewState: new state of the ADCx offset3. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ChannelOffset3Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the OFFSET1_EN bit */ - ADCx->OFR3 |= ADC_OFR3_OFFSET3_EN; - } - else - { - /* Reset the OFFSET1_EN bit */ - ADCx->OFR3 &= ~(ADC_OFR3_OFFSET3_EN); - } -} - -/** - * @brief Enables or disables the Offset4. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param NewState: new state of the ADCx offset4. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ChannelOffset4Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the OFFSET1_EN bit */ - ADCx->OFR4 |= ADC_OFR4_OFFSET4_EN; - } - else - { - /* Reset the OFFSET1_EN bit */ - ADCx->OFR4 &= ~(ADC_OFR4_OFFSET4_EN); - } -} - -/** - * @} - */ - -/** @defgroup ADC_Group5 Regular Channels DMA Configuration functions - * @brief Regular Channels DMA Configuration functions - * -@verbatim - =============================================================================== - ##### Regular Channels DMA Configuration functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure the DMA for ADC regular - channels. Since converted regular channel values are stored into a unique data register, - it is useful to use DMA for conversion of more than one regular channel. This - avoids the loss of the data already stored in the ADC Data register. - - (#) ADC_DMACmd() function is used to enable the ADC DMA mode, after each - conversion of a regular channel, a DMA request is generated. - (#) ADC_DMAConfig() function is used to select between the one shot DMA mode - or the circular DMA mode - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified ADC DMA request. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param NewState: new state of the selected ADC DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_DMA_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request */ - ADCx->CFGR |= ADC_CFGR_DMAEN; - } - else - { - /* Disable the selected ADC DMA request */ - ADCx->CFGR &= ~(uint32_t)ADC_CFGR_DMAEN; - } -} - -/** - * @brief Configure ADC DMA mode. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param ADC_DMAMode: select the ADC DMA mode. - * This parameter can be one of the following values: - * @arg ADC_DMAMode_OneShot: ADC DMA Oneshot mode - * @arg ADC_DMAMode_Circular: ADC DMA circular mode - * @retval None - */ -void ADC_DMAConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMAMode) -{ - /* Check the parameters */ - assert_param(IS_ADC_DMA_PERIPH(ADCx)); - assert_param(IS_ADC_DMA_MODE(ADC_DMAMode)); - - /* Set or reset the DMACFG bit */ - ADCx->CFGR &= ~(uint32_t)ADC_CFGR_DMACFG; - ADCx->CFGR |= ADC_DMAMode; -} - -/** - * @} - */ - -/** @defgroup ADC_Group6 Injected channels Configuration functions - * @brief Injected channels Configuration functions - * -@verbatim - =============================================================================== - ##### Injected channels Configuration functions ##### - =============================================================================== - - [..] This section provide functions allowing to manage the ADC Injected channels, - it is composed of : - - (#) Configuration functions for Injected channels sample time - (#) Functions to start and stop the injected conversion - (#) unction to select the discontinuous mode - (#) Function to get the Specified Injected channel conversion data: This subsection - provides an important function in the ADC peripheral since it returns the - converted data of the specific injected channel. - -@endverbatim - * @{ - */ - -/** - * @brief Configures for the selected ADC injected channel its corresponding - * sample time. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: ADC Channel1 selected - * @arg ADC_InjectedChannel_2: ADC Channel2 selected - * @arg ADC_InjectedChannel_3: ADC Channel3 selected - * @arg ADC_InjectedChannel_4: ADC Channel4 selected - * @arg ADC_InjectedChannel_5: ADC Channel5 selected - * @arg ADC_InjectedChannel_6: ADC Channel6 selected - * @arg ADC_InjectedChannel_7: ADC Channel7 selected - * @arg ADC_InjectedChannel_8: ADC Channel8 selected - * @arg ADC_InjectedChannel_9: ADC Channel9 selected - * @arg ADC_InjectedChannel_10: ADC Channel10 selected - * @arg ADC_InjectedChannel_11: ADC Channel11 selected - * @arg ADC_InjectedChannel_12: ADC Channel12 selected - * @arg ADC_InjectedChannel_13: ADC Channel13 selected - * @arg ADC_InjectedChannel_14: ADC Channel14 selected - * @arg ADC_InjectedChannel_15: ADC Channel15 selected - * @arg ADC_InjectedChannel_16: ADC Channel16 selected - * @arg ADC_InjectedChannel_17: ADC Channel17 selected - * @arg ADC_InjectedChannel_18: ADC Channel18 selected - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles - * @arg ADC_SampleTime_2Cycles5: Sample time equal to 2.5 cycles - * @arg ADC_SampleTime_4Cycles5: Sample time equal to 4.5 cycles - * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles - * @arg ADC_SampleTime_19Cycles5: Sample time equal to 19.5 cycles - * @arg ADC_SampleTime_61Cycles5: Sample time equal to 61.5 cycles - * @arg ADC_SampleTime_181Cycles5: Sample time equal to 181.5 cycles - * @arg ADC_SampleTime_601Cycles5: Sample time equal to 601.5 cycles - * @retval None - */ -void ADC_InjectedChannelSampleTimeConfig(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - - /* Channel sampling configuration */ - /* if ADC_InjectedChannel_10 ... ADC_InjectedChannel_18 is selected */ - if (ADC_InjectedChannel > ADC_InjectedChannel_9) - { - /* Calculate the mask to clear */ - tmpreg1 = ADC_SMPR2_SMP10 << (3 * (ADC_InjectedChannel - 10)); - /* Clear the old channel sample time */ - ADCx->SMPR2 &= ~tmpreg1; - /* Calculate the mask to set */ - ADCx->SMPR2 |= (uint32_t)ADC_SampleTime << (3 * (ADC_InjectedChannel - 10)); - - } - else /* ADC_InjectedChannel include in ADC_InjectedChannel_[0..9] */ - { - /* Calculate the mask to clear */ - tmpreg1 = ADC_SMPR1_SMP1 << (3 * (ADC_InjectedChannel - 1)); - /* Clear the old channel sample time */ - ADCx->SMPR1 &= ~tmpreg1; - /* Calculate the mask to set */ - ADCx->SMPR1 |= (uint32_t)ADC_SampleTime << (3 * (ADC_InjectedChannel)); - } -} - -/** - * @brief Enables or disables the selected ADC start of the injected - * channels conversion. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param NewState: new state of the selected ADC software start injected conversion. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_StartInjectedConversion(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Enable the selected ADC conversion for injected group on external event and start the selected - ADC injected conversion */ - ADCx->CR |= ADC_CR_JADSTART; -} - -/** - * @brief Stops the selected ADC ongoing injected conversion. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @retval None - */ -void ADC_StopInjectedConversion(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Set the JADSTP bit */ - ADCx->CR |= ADC_CR_JADSTP; -} - -/** - * @brief Gets the selected ADC Software start injected conversion Status. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @retval The new state of ADC start injected conversion (SET or RESET). - */ -FlagStatus ADC_GetStartInjectedConversionStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Check the status of JADSTART bit */ - if ((ADCx->CR & ADC_CR_JADSTART) != (uint32_t)RESET) - { - /* JADSTART bit is set */ - bitstatus = SET; - } - else - { - /* JADSTART bit is reset */ - bitstatus = RESET; - } - /* Return the JADSTART bit status */ - return bitstatus; -} - -/** - * @brief Enables or disables the selected ADC automatic injected group - * conversion after regular one. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param NewState: new state of the selected ADC auto injected conversion - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC automatic injected group conversion */ - ADCx->CFGR |= ADC_CFGR_JAUTO; - } - else - { - /* Disable the selected ADC automatic injected group conversion */ - ADCx->CFGR &= ~ADC_CFGR_JAUTO; - } -} - -/** - * @brief Enables or disables the discontinuous mode for injected group - * channel for the specified ADC - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param NewState: new state of the selected ADC discontinuous mode - * on injected group channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC injected discontinuous mode */ - ADCx->CFGR |= ADC_CFGR_JDISCEN; - } - else - { - /* Disable the selected ADC injected discontinuous mode */ - ADCx->CFGR &= ~ADC_CFGR_JDISCEN; - } -} - -/** - * @brief Returns the ADC injected channel conversion result - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param ADC_InjectedSequence: the converted ADC injected sequence. - * This parameter can be one of the following values: - * @arg ADC_InjectedSequence_1: Injected Sequence1 selected - * @arg ADC_InjectedSequence_2: Injected Sequence2 selected - * @arg ADC_InjectedSequence_3: Injected Sequence3 selected - * @arg ADC_InjectedSequence_4: Injected Sequence4 selected - * @retval The Data conversion value. - */ -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedSequence) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_SEQUENCE(ADC_InjectedSequence)); - - tmp = (uint32_t)ADCx; - tmp += ((ADC_InjectedSequence - 1 )<< 2) + JDR_Offset; - - /* Returns the selected injected channel conversion data value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} - -/** - * @} - */ - -/** @defgroup ADC_Group7 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure the ADC Interrupts, get - the status and clear flags and Interrupts pending bits. - - [..] The ADC provide 11 Interrupts sources and 11 Flags which can be divided into 3 groups: - - (#) Flags and Interrupts for ADC regular channels - (##)Flags - (+) ADC_FLAG_RDY: ADC Ready flag - (+) ADC_FLAG_EOSMP: ADC End of Sampling flag - (+) ADC_FLAG_EOC: ADC End of Regular Conversion flag. - (+) ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag - (+) ADC_FLAG_OVR: ADC overrun flag - - (##) Interrupts - (+) ADC_IT_RDY: ADC Ready interrupt source - (+) ADC_IT_EOSMP: ADC End of Sampling interrupt source - (+) ADC_IT_EOC: ADC End of Regular Conversion interrupt source - (+) ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt - (+) ADC_IT_OVR: ADC overrun interrupt source - - - (#) Flags and Interrupts for ADC regular channels - (##)Flags - (+) ADC_FLAG_JEOC: ADC Ready flag - (+) ADC_FLAG_JEOS: ADC End of Sampling flag - (+) ADC_FLAG_JQOVF: ADC End of Regular Conversion flag. - - (##) Interrupts - (+) ADC_IT_JEOC: ADC End of Injected Conversion interrupt source - (+) ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source - (+) ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source - - (#) General Flags and Interrupts for the ADC - (##)Flags - (+) ADC_FLAG_AWD1: ADC Analog watchdog 1 flag - (+) ADC_FLAG_AWD2: ADC Analog watchdog 2 flag - (+) ADC_FLAG_AWD3: ADC Analog watchdog 3 flag - - (##)Flags - (+) ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source - (+) ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source - (+) ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source - - (#) Flags for ADC dual mode - (##)Flags for Master - (+) ADC_FLAG_MSTRDY: ADC master Ready (ADRDY) flag - (+) ADC_FLAG_MSTEOSMP: ADC master End of Sampling flag - (+) ADC_FLAG_MSTEOC: ADC master End of Regular Conversion flag - (+) ADC_FLAG_MSTEOS: ADC master End of Regular sequence of Conversions flag - (+) ADC_FLAG_MSTOVR: ADC master overrun flag - (+) ADC_FLAG_MSTJEOC: ADC master End of Injected Conversion flag - (+) ADC_FLAG_MSTJEOS: ADC master End of Injected sequence of Conversions flag - (+) ADC_FLAG_MSTAWD1: ADC master Analog watchdog 1 flag - (+) ADC_FLAG_MSTAWD2: ADC master Analog watchdog 2 flag - (+) ADC_FLAG_MSTAWD3: ADC master Analog watchdog 3 flag - (+) ADC_FLAG_MSTJQOVF: ADC master Injected Context Queue Overflow flag - - (##) Flags for Slave - (+) ADC_FLAG_SLVRDY: ADC slave Ready (ADRDY) flag - (+) ADC_FLAG_SLVEOSMP: ADC slave End of Sampling flag - (+) ADC_FLAG_SLVEOC: ADC slave End of Regular Conversion flag - (+) ADC_FLAG_SLVEOS: ADC slave End of Regular sequence of Conversions flag - (+) ADC_FLAG_SLVOVR: ADC slave overrun flag - (+) ADC_FLAG_SLVJEOC: ADC slave End of Injected Conversion flag - (+) ADC_FLAG_SLVJEOS: ADC slave End of Injected sequence of Conversions flag - (+) ADC_FLAG_SLVAWD1: ADC slave Analog watchdog 1 flag - (+) ADC_FLAG_SLVAWD2: ADC slave Analog watchdog 2 flag - (+) ADC_FLAG_SLVAWD3: ADC slave Analog watchdog 3 flag - (+) ADC_FLAG_SLVJQOVF: ADC slave Injected Context Queue Overflow flag - - The user should identify which mode will be used in his application to manage - the ADC controller events: Polling mode or Interrupt mode. - - In the Polling Mode it is advised to use the following functions: - - ADC_GetFlagStatus() : to check if flags events occur. - - ADC_ClearFlag() : to clear the flags events. - - In the Interrupt Mode it is advised to use the following functions: - - ADC_ITConfig() : to enable or disable the interrupt source. - - ADC_GetITStatus() : to check if Interrupt occurs. - - ADC_ClearITPendingBit() : to clear the Interrupt pending Bit - (corresponding Flag). -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified ADC interrupts. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source - * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source - * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source - * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source - * @arg ADC_IT_OVR: ADC overrun interrupt source - * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source - * @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source - * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source - * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source - * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source - * @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source - * @param NewState: new state of the specified ADC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_ADC_IT(ADC_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC interrupts */ - ADCx->IER |= ADC_IT; - } - else - { - /* Disable the selected ADC interrupts */ - ADCx->IER &= (~(uint32_t)ADC_IT); - } -} - -/** - * @brief Checks whether the specified ADC flag is set or not. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param ADC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg ADC_FLAG_RDY: ADC Ready (ADRDY) flag - * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag - * @arg ADC_FLAG_EOC: ADC End of Regular Conversion flag - * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag - * @arg ADC_FLAG_OVR: ADC overrun flag - * @arg ADC_FLAG_JEOC: ADC End of Injected Conversion flag - * @arg ADC_FLAG_JEOS: ADC End of Injected sequence of Conversions flag - * @arg ADC_FLAG_AWD1: ADC Analog watchdog 1 flag - * @arg ADC_FLAG_AWD2: ADC Analog watchdog 2 flag - * @arg ADC_FLAG_AWD3: ADC Analog watchdog 3 flag - * @arg ADC_FLAG_JQOVF: ADC Injected Context Queue Overflow flag - * @retval The new state of ADC_FLAG (SET or RESET). - */ -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); - - /* Check the status of the specified ADC flag */ - if ((ADCx->ISR & ADC_FLAG) != (uint32_t)RESET) - { - /* ADC_FLAG is set */ - bitstatus = SET; - } - else - { - /* ADC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the ADC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's pending flags. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param ADC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg ADC_FLAG_RDY: ADC Ready (ADRDY) flag - * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag - * @arg ADC_FLAG_EOC: ADC End of Regular Conversion flag - * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag - * @arg ADC_FLAG_OVR: ADC overrun flag - * @arg ADC_FLAG_JEOC: ADC End of Injected Conversion flag - * @arg ADC_FLAG_JEOS: ADC End of Injected sequence of Conversions flag - * @arg ADC_FLAG_AWD1: ADC Analog watchdog 1 flag - * @arg ADC_FLAG_AWD2: ADC Analog watchdog 2 flag - * @arg ADC_FLAG_AWD3: ADC Analog watchdog 3 flag - * @arg ADC_FLAG_JQOVF: ADC Injected Context Queue Overflow flag - * @retval None - */ -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); - /* Clear the selected ADC flags */ - ADCx->ISR = (uint32_t)ADC_FLAG; -} - -/** - * @brief Checks whether the specified ADC flag is set or not. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param ADC_FLAG: specifies the master or slave flag to check. - * This parameter can be one of the following values: - * @arg ADC_FLAG_MSTRDY: ADC master Ready (ADRDY) flag - * @arg ADC_FLAG_MSTEOSMP: ADC master End of Sampling flag - * @arg ADC_FLAG_MSTEOC: ADC master End of Regular Conversion flag - * @arg ADC_FLAG_MSTEOS: ADC master End of Regular sequence of Conversions flag - * @arg ADC_FLAG_MSTOVR: ADC master overrun flag - * @arg ADC_FLAG_MSTJEOC: ADC master End of Injected Conversion flag - * @arg ADC_FLAG_MSTJEOS: ADC master End of Injected sequence of Conversions flag - * @arg ADC_FLAG_MSTAWD1: ADC master Analog watchdog 1 flag - * @arg ADC_FLAG_MSTAWD2: ADC master Analog watchdog 2 flag - * @arg ADC_FLAG_MSTAWD3: ADC master Analog watchdog 3 flag - * @arg ADC_FLAG_MSTJQOVF: ADC master Injected Context Queue Overflow flag - * @arg ADC_FLAG_SLVRDY: ADC slave Ready (ADRDY) flag - * @arg ADC_FLAG_SLVEOSMP: ADC slave End of Sampling flag - * @arg ADC_FLAG_SLVEOC: ADC slave End of Regular Conversion flag - * @arg ADC_FLAG_SLVEOS: ADC slave End of Regular sequence of Conversions flag - * @arg ADC_FLAG_SLVOVR: ADC slave overrun flag - * @arg ADC_FLAG_SLVJEOC: ADC slave End of Injected Conversion flag - * @arg ADC_FLAG_SLVJEOS: ADC slave End of Injected sequence of Conversions flag - * @arg ADC_FLAG_SLVAWD1: ADC slave Analog watchdog 1 flag - * @arg ADC_FLAG_SLVAWD2: ADC slave Analog watchdog 2 flag - * @arg ADC_FLAG_SLVAWD3: ADC slave Analog watchdog 3 flag - * @arg ADC_FLAG_SLVJQOVF: ADC slave Injected Context Queue Overflow flag - * @retval The new state of ADC_FLAG (SET or RESET). - */ -FlagStatus ADC_GetCommonFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG) -{ - uint32_t tmpreg1 = 0; - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_GET_COMMONFLAG(ADC_FLAG)); - - if((ADCx == ADC1) || (ADCx == ADC2)) - { - tmpreg1 = ADC1_2->CSR; - } - else - { - tmpreg1 = ADC3_4->CSR; - } - /* Check the status of the specified ADC flag */ - if ((tmpreg1 & ADC_FLAG) != (uint32_t)RESET) - { - /* ADC_FLAG is set */ - bitstatus = SET; - } - else - { - /* ADC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the ADC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's pending flags. - * @param ADCx: where x can be 1, 2, 3 or 4 to select the ADC peripheral. - * @param ADC_FLAG: specifies the master or slave flag to clear. - * This parameter can be one of the following values: - * @arg ADC_FLAG_MSTRDY: ADC master Ready (ADRDY) flag - * @arg ADC_FLAG_MSTEOSMP: ADC master End of Sampling flag - * @arg ADC_FLAG_MSTEOC: ADC master End of Regular Conversion flag - * @arg ADC_FLAG_MSTEOS: ADC master End of Regular sequence of Conversions flag - * @arg ADC_FLAG_MSTOVR: ADC master overrun flag - * @arg ADC_FLAG_MSTJEOC: ADC master End of Injected Conversion flag - * @arg ADC_FLAG_MSTJEOS: ADC master End of Injected sequence of Conversions flag - * @arg ADC_FLAG_MSTAWD1: ADC master Analog watchdog 1 flag - * @arg ADC_FLAG_MSTAWD2: ADC master Analog watchdog 2 flag - * @arg ADC_FLAG_MSTAWD3: ADC master Analog watchdog 3 flag - * @arg ADC_FLAG_MSTJQOVF: ADC master Injected Context Queue Overflow flag - * @arg ADC_FLAG_SLVRDY: ADC slave Ready (ADRDY) flag - * @arg ADC_FLAG_SLVEOSMP: ADC slave End of Sampling flag - * @arg ADC_FLAG_SLVEOC: ADC slave End of Regular Conversion flag - * @arg ADC_FLAG_SLVEOS: ADC slave End of Regular sequence of Conversions flag - * @arg ADC_FLAG_SLVOVR: ADC slave overrun flag - * @arg ADC_FLAG_SLVJEOC: ADC slave End of Injected Conversion flag - * @arg ADC_FLAG_SLVJEOS: ADC slave End of Injected sequence of Conversions flag - * @arg ADC_FLAG_SLVAWD1: ADC slave Analog watchdog 1 flag - * @arg ADC_FLAG_SLVAWD2: ADC slave Analog watchdog 2 flag - * @arg ADC_FLAG_SLVAWD3: ADC slave Analog watchdog 3 flag - * @arg ADC_FLAG_SLVJQOVF: ADC slave Injected Context Queue Overflow flag - * @retval None - */ -void ADC_ClearCommonFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CLEAR_COMMONFLAG(ADC_FLAG)); - - if((ADCx == ADC1) || (ADCx == ADC2)) - { - /* Clear the selected ADC flags */ - ADC1_2->CSR |= (uint32_t)ADC_FLAG; - } - else - { - /* Clear the selected ADC flags */ - ADC3_4->CSR |= (uint32_t)ADC_FLAG; - } -} - -/** - * @brief Checks whether the specified ADC interrupt has occurred or not. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt source to check. - * This parameter can be one of the following values: - * @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source - * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source - * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source - * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source - * @arg ADC_IT_OVR: ADC overrun interrupt source - * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source - * @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source - * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source - * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source - * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source - * @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source - * @retval The new state of ADC_IT (SET or RESET). - */ -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itstatus = 0x0, itenable = 0x0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_GET_IT(ADC_IT)); - - itstatus = ADCx->ISR & ADC_IT; - - itenable = ADCx->IER & ADC_IT; - if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the ADCx's interrupt pending bits. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source - * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source - * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source - * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source - * @arg ADC_IT_OVR: ADC overrun interrupt source - * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source - * @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source - * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source - * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source - * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source - * @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source - * @retval None - */ -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_IT(ADC_IT)); - /* Clear the selected ADC interrupt pending bit */ - ADCx->ISR = (uint32_t)ADC_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_adc.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,830 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_adc.h - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file contains all the functions prototypes for the ADC firmware - * library. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F30x_ADC_H -#define __STM32F30x_ADC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief ADC Init structure definition - */ -typedef struct -{ - - uint32_t ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in - Continuous or Single mode. - This parameter can be set to ENABLE or DISABLE. */ - uint32_t ADC_Resolution; /*!< Configures the ADC resolution. - This parameter can be a value of @ref ADC_resolution */ - uint32_t ADC_ExternalTrigConvEvent; /*!< Defines the external trigger used to start the analog - to digital conversion of regular channels. This parameter - can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ - uint32_t ADC_ExternalTrigEventEdge; /*!< Select the external trigger edge and enable the trigger of a regular group. - This parameter can be a value of - @ref ADC_external_trigger_edge_for_regular_channels_conversion */ - uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. - This parameter can be a value of @ref ADC_data_align */ - uint32_t ADC_OverrunMode; /*!< Specifies the way data overrun are managed. - This parameter can be set to ENABLE or DISABLE. */ - uint32_t ADC_AutoInjMode; /*!< Enable/disable automatic injected group conversion after - regular group conversion. - This parameter can be set to ENABLE or DISABLE. */ - uint8_t ADC_NbrOfRegChannel; /*!< Specifies the number of ADC channels that will be converted - using the sequencer for regular channel group. - This parameter must range from 1 to 16. */ -}ADC_InitTypeDef; - -/** - * @} - */ -/** - * @brief ADC Init structure definition - */ -typedef struct -{ - - uint32_t ADC_ExternalTrigInjecConvEvent; /*!< Defines the external trigger used to start the analog - to digital conversion of injected channels. This parameter - can be a value of @ref ADC_external_trigger_sources_for_Injected_channels_conversion */ - uint32_t ADC_ExternalTrigInjecEventEdge; /*!< Select the external trigger edge and enable the trigger of an injected group. - This parameter can be a value of - @ref ADC_external_trigger_edge_for_Injected_channels_conversion */ - uint8_t ADC_NbrOfInjecChannel; /*!< Specifies the number of ADC channels that will be converted - using the sequencer for injected channel group. - This parameter must range from 1 to 4. */ - uint32_t ADC_InjecSequence1; - uint32_t ADC_InjecSequence2; - uint32_t ADC_InjecSequence3; - uint32_t ADC_InjecSequence4; -}ADC_InjectedInitTypeDef; - -/** - * @} - */ -typedef struct -{ - uint32_t ADC_Mode; /*!< Configures the ADC to operate in - independent or multi mode. - This parameter can be a value of @ref ADC_mode */ - uint32_t ADC_Clock; /*!< Select the clock of the ADC. The clock is common for both master - and slave ADCs. - This parameter can be a value of @ref ADC_Clock */ - uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode. - This parameter can be a value of - @ref ADC_Direct_memory_access_mode_for_multi_mode */ - uint32_t ADC_DMAMode; /*!< Configures the DMA mode for ADC. - This parameter can be a value of @ref ADC_DMA_Mode_definition */ - uint8_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. - This parameter can be a value between 0x0 and 0xF */ - -}ADC_CommonInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Constants - * @{ - */ - -#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ - ((PERIPH) == ADC2) || \ - ((PERIPH) == ADC3) || \ - ((PERIPH) == ADC4)) - -#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ - ((PERIPH) == ADC2) || \ - ((PERIPH) == ADC3) || \ - ((PERIPH) == ADC4)) - -/** @defgroup ADC_ContinuousConvMode - * @{ - */ -#define ADC_ContinuousConvMode_Enable ((uint32_t)0x00002000) /*!< ADC continuous conversion mode enable */ -#define ADC_ContinuousConvMode_Disable ((uint32_t)0x00000000) /*!< ADC continuous conversion mode disable */ -#define IS_ADC_CONVMODE(MODE) (((MODE) == ADC_ContinuousConvMode_Enable) || \ - ((MODE) == ADC_ContinuousConvMode_Disable)) -/** - * @} - */ -/** @defgroup ADC_OverunMode - * @{ - */ -#define ADC_OverrunMode_Enable ((uint32_t)0x00001000) /*!< ADC Overrun Mode enable */ -#define ADC_OverrunMode_Disable ((uint32_t)0x00000000) /*!< ADC Overrun Mode disable */ -#define IS_ADC_OVRUNMODE(MODE) (((MODE) == ADC_OverrunMode_Enable) || \ - ((MODE) == ADC_OverrunMode_Disable)) -/** - * @} - */ -/** @defgroup ADC_AutoInjecMode - * @{ - */ -#define ADC_AutoInjec_Enable ((uint32_t)0x02000000) /*!< ADC Auto injected Mode enable */ -#define ADC_AutoInjec_Disable ((uint32_t)0x00000000) /*!< ADC Auto injected Mode disable */ -#define IS_ADC_AUTOINJECMODE(MODE) (((MODE) == ADC_AutoInjec_Enable) || \ - ((MODE) == ADC_AutoInjec_Disable)) -/** - * @} - */ -/** @defgroup ADC_resolution - * @{ - */ -#define ADC_Resolution_12b ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */ -#define ADC_Resolution_10b ((uint32_t)0x00000008) /*!< ADC 10-bit resolution */ -#define ADC_Resolution_8b ((uint32_t)0x00000010) /*!< ADC 8-bit resolution */ -#define ADC_Resolution_6b ((uint32_t)0x00000018) /*!< ADC 6-bit resolution */ -#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \ - ((RESOLUTION) == ADC_Resolution_10b) || \ - ((RESOLUTION) == ADC_Resolution_8b) || \ - ((RESOLUTION) == ADC_Resolution_6b)) - -/** - * @} - */ - - -/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion - * @{ - */ -#define ADC_ExternalTrigEventEdge_None ((uint16_t)0x0000) /*!< ADC No external trigger for regular conversion */ -#define ADC_ExternalTrigEventEdge_RisingEdge ((uint16_t)0x0400) /*!< ADC external trigger rising edge for regular conversion */ -#define ADC_ExternalTrigEventEdge_FallingEdge ((uint16_t)0x0800) /*!< ADC ADC external trigger falling edge for regular conversion */ -#define ADC_ExternalTrigEventEdge_BothEdge ((uint16_t)0x0C00) /*!< ADC ADC external trigger both edges for regular conversion */ - -#define IS_EXTERNALTRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigEventEdge_None) || \ - ((EDGE) == ADC_ExternalTrigEventEdge_RisingEdge) || \ - ((EDGE) == ADC_ExternalTrigEventEdge_FallingEdge) || \ - ((EDGE) == ADC_ExternalTrigEventEdge_BothEdge)) - -/** - * @} - */ - -/** @defgroup ADC_external_trigger_edge_for_Injected_channels_conversion - * @{ - */ -#define ADC_ExternalTrigInjecEventEdge_None ((uint16_t)0x0000) /*!< ADC No external trigger for regular conversion */ -#define ADC_ExternalTrigInjecEventEdge_RisingEdge ((uint16_t)0x0040) /*!< ADC external trigger rising edge for injected conversion */ -#define ADC_ExternalTrigInjecEventEdge_FallingEdge ((uint16_t)0x0080) /*!< ADC external trigger falling edge for injected conversion */ -#define ADC_ExternalTrigInjecEventEdge_BothEdge ((uint16_t)0x00C0) /*!< ADC external trigger both edges for injected conversion */ - -#define IS_EXTERNALTRIGINJ_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecEventEdge_None) || \ - ((EDGE) == ADC_ExternalTrigInjecEventEdge_RisingEdge) || \ - ((EDGE) == ADC_ExternalTrigInjecEventEdge_FallingEdge) || \ - ((EDGE) == ADC_ExternalTrigInjecEventEdge_BothEdge)) - -/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion - * @{ - */ -#define ADC_ExternalTrigConvEvent_0 ((uint16_t)0x0000) /*!< ADC external trigger event 0 */ -#define ADC_ExternalTrigConvEvent_1 ((uint16_t)0x0040) /*!< ADC external trigger event 1 */ -#define ADC_ExternalTrigConvEvent_2 ((uint16_t)0x0080) /*!< ADC external trigger event 2 */ -#define ADC_ExternalTrigConvEvent_3 ((uint16_t)0x00C0) /*!< ADC external trigger event 3 */ -#define ADC_ExternalTrigConvEvent_4 ((uint16_t)0x0100) /*!< ADC external trigger event 4 */ -#define ADC_ExternalTrigConvEvent_5 ((uint16_t)0x0140) /*!< ADC external trigger event 5 */ -#define ADC_ExternalTrigConvEvent_6 ((uint16_t)0x0180) /*!< ADC external trigger event 6 */ -#define ADC_ExternalTrigConvEvent_7 ((uint16_t)0x01C0) /*!< ADC external trigger event 7 */ -#define ADC_ExternalTrigConvEvent_8 ((uint16_t)0x0200) /*!< ADC external trigger event 8 */ -#define ADC_ExternalTrigConvEvent_9 ((uint16_t)0x0240) /*!< ADC external trigger event 9 */ -#define ADC_ExternalTrigConvEvent_10 ((uint16_t)0x0280) /*!< ADC external trigger event 10 */ -#define ADC_ExternalTrigConvEvent_11 ((uint16_t)0x02C0) /*!< ADC external trigger event 11 */ -#define ADC_ExternalTrigConvEvent_12 ((uint16_t)0x0300) /*!< ADC external trigger event 12 */ -#define ADC_ExternalTrigConvEvent_13 ((uint16_t)0x0340) /*!< ADC external trigger event 13 */ -#define ADC_ExternalTrigConvEvent_14 ((uint16_t)0x0380) /*!< ADC external trigger event 14 */ -#define ADC_ExternalTrigConvEvent_15 ((uint16_t)0x03C0) /*!< ADC external trigger event 15 */ - -#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConvEvent_0) || \ - ((REGTRIG) == ADC_ExternalTrigConvEvent_1) || \ - ((REGTRIG) == ADC_ExternalTrigConvEvent_2) || \ - ((REGTRIG) == ADC_ExternalTrigConvEvent_3) || \ - ((REGTRIG) == ADC_ExternalTrigConvEvent_4) || \ - ((REGTRIG) == ADC_ExternalTrigConvEvent_5) || \ - ((REGTRIG) == ADC_ExternalTrigConvEvent_6) || \ - ((REGTRIG) == ADC_ExternalTrigConvEvent_7) || \ - ((REGTRIG) == ADC_ExternalTrigConvEvent_8) || \ - ((REGTRIG) == ADC_ExternalTrigConvEvent_9) || \ - ((REGTRIG) == ADC_ExternalTrigConvEvent_10) || \ - ((REGTRIG) == ADC_ExternalTrigConvEvent_11) || \ - ((REGTRIG) == ADC_ExternalTrigConvEvent_12) || \ - ((REGTRIG) == ADC_ExternalTrigConvEvent_13) || \ - ((REGTRIG) == ADC_ExternalTrigConvEvent_14) || \ - ((REGTRIG) == ADC_ExternalTrigConvEvent_15)) - -/** - * @} - */ - -/** @defgroup ADC_external_trigger_sources_for_Injected_channels_conversion - * @{ - */ - -#define ADC_ExternalTrigInjecConvEvent_0 ((uint16_t)0x0000) /*!< ADC external trigger for injected conversion event 0 */ -#define ADC_ExternalTrigInjecConvEvent_1 ((uint16_t)0x0004) /*!< ADC external trigger for injected conversion event 1 */ -#define ADC_ExternalTrigInjecConvEvent_2 ((uint16_t)0x0008) /*!< ADC external trigger for injected conversion event 2 */ -#define ADC_ExternalTrigInjecConvEvent_3 ((uint16_t)0x000C) /*!< ADC external trigger for injected conversion event 3 */ -#define ADC_ExternalTrigInjecConvEvent_4 ((uint16_t)0x0010) /*!< ADC external trigger for injected conversion event 4 */ -#define ADC_ExternalTrigInjecConvEvent_5 ((uint16_t)0x0014) /*!< ADC external trigger for injected conversion event 5 */ -#define ADC_ExternalTrigInjecConvEvent_6 ((uint16_t)0x0018) /*!< ADC external trigger for injected conversion event 6 */ -#define ADC_ExternalTrigInjecConvEvent_7 ((uint16_t)0x001C) /*!< ADC external trigger for injected conversion event 7 */ -#define ADC_ExternalTrigInjecConvEvent_8 ((uint16_t)0x0020) /*!< ADC external trigger for injected conversion event 8 */ -#define ADC_ExternalTrigInjecConvEvent_9 ((uint16_t)0x0024) /*!< ADC external trigger for injected conversion event 9 */ -#define ADC_ExternalTrigInjecConvEvent_10 ((uint16_t)0x0028) /*!< ADC external trigger for injected conversion event 10 */ -#define ADC_ExternalTrigInjecConvEvent_11 ((uint16_t)0x002C) /*!< ADC external trigger for injected conversion event 11 */ -#define ADC_ExternalTrigInjecConvEvent_12 ((uint16_t)0x0030) /*!< ADC external trigger for injected conversion event 12 */ -#define ADC_ExternalTrigInjecConvEvent_13 ((uint16_t)0x0034) /*!< ADC external trigger for injected conversion event 13 */ -#define ADC_ExternalTrigInjecConvEvent_14 ((uint16_t)0x0038) /*!< ADC external trigger for injected conversion event 14 */ -#define ADC_ExternalTrigInjecConvEvent_15 ((uint16_t)0x003C) /*!< ADC external trigger for injected conversion event 15 */ - -#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConvEvent_0) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_1) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_2) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_3) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_5) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_6) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_7) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_8) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_9) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_10) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_11) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_12) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_13) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_14) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_15)) -/** - * @} - */ -/** @defgroup ADC_data_align - * @{ - */ - -#define ADC_DataAlign_Right ((uint32_t)0x00000000) /*!< ADC Data alignment right */ -#define ADC_DataAlign_Left ((uint32_t)0x00000020) /*!< ADC Data alignment left */ -#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ - ((ALIGN) == ADC_DataAlign_Left)) -/** - * @} - */ - -/** @defgroup ADC_channels - * @{ - */ - -#define ADC_Channel_1 ((uint8_t)0x01) /*!< ADC Channel 1 */ -#define ADC_Channel_2 ((uint8_t)0x02) /*!< ADC Channel 2 */ -#define ADC_Channel_3 ((uint8_t)0x03) /*!< ADC Channel 3 */ -#define ADC_Channel_4 ((uint8_t)0x04) /*!< ADC Channel 4 */ -#define ADC_Channel_5 ((uint8_t)0x05) /*!< ADC Channel 5 */ -#define ADC_Channel_6 ((uint8_t)0x06) /*!< ADC Channel 6 */ -#define ADC_Channel_7 ((uint8_t)0x07) /*!< ADC Channel 7 */ -#define ADC_Channel_8 ((uint8_t)0x08) /*!< ADC Channel 8 */ -#define ADC_Channel_9 ((uint8_t)0x09) /*!< ADC Channel 9 */ -#define ADC_Channel_10 ((uint8_t)0x0A) /*!< ADC Channel 10 */ -#define ADC_Channel_11 ((uint8_t)0x0B) /*!< ADC Channel 11 */ -#define ADC_Channel_12 ((uint8_t)0x0C) /*!< ADC Channel 12 */ -#define ADC_Channel_13 ((uint8_t)0x0D) /*!< ADC Channel 13 */ -#define ADC_Channel_14 ((uint8_t)0x0E) /*!< ADC Channel 14 */ -#define ADC_Channel_15 ((uint8_t)0x0F) /*!< ADC Channel 15 */ -#define ADC_Channel_16 ((uint8_t)0x10) /*!< ADC Channel 16 */ -#define ADC_Channel_17 ((uint8_t)0x11) /*!< ADC Channel 17 */ -#define ADC_Channel_18 ((uint8_t)0x12) /*!< ADC Channel 18 */ - -#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) -#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_18) -#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_17) - -#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_1) || \ - ((CHANNEL) == ADC_Channel_2) || \ - ((CHANNEL) == ADC_Channel_3) || \ - ((CHANNEL) == ADC_Channel_4) || \ - ((CHANNEL) == ADC_Channel_5) || \ - ((CHANNEL) == ADC_Channel_6) || \ - ((CHANNEL) == ADC_Channel_7) || \ - ((CHANNEL) == ADC_Channel_8) || \ - ((CHANNEL) == ADC_Channel_9) || \ - ((CHANNEL) == ADC_Channel_10) || \ - ((CHANNEL) == ADC_Channel_11) || \ - ((CHANNEL) == ADC_Channel_12) || \ - ((CHANNEL) == ADC_Channel_13) || \ - ((CHANNEL) == ADC_Channel_14) || \ - ((CHANNEL) == ADC_Channel_15) || \ - ((CHANNEL) == ADC_Channel_16) || \ - ((CHANNEL) == ADC_Channel_17) || \ - ((CHANNEL) == ADC_Channel_18)) -#define IS_ADC_DIFFCHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_1) || \ - ((CHANNEL) == ADC_Channel_2) || \ - ((CHANNEL) == ADC_Channel_3) || \ - ((CHANNEL) == ADC_Channel_4) || \ - ((CHANNEL) == ADC_Channel_5) || \ - ((CHANNEL) == ADC_Channel_6) || \ - ((CHANNEL) == ADC_Channel_7) || \ - ((CHANNEL) == ADC_Channel_8) || \ - ((CHANNEL) == ADC_Channel_9) || \ - ((CHANNEL) == ADC_Channel_10) || \ - ((CHANNEL) == ADC_Channel_11) || \ - ((CHANNEL) == ADC_Channel_12) || \ - ((CHANNEL) == ADC_Channel_13) || \ - ((CHANNEL) == ADC_Channel_14)) -/** - * @} - */ - -/** @defgroup ADC_mode - * @{ - */ -#define ADC_Mode_Independent ((uint32_t)0x00000000) /*!< ADC independent mode */ -#define ADC_Mode_CombRegSimulInjSimul ((uint32_t)0x00000001) /*!< ADC multi ADC mode: Combined Regular simultaneous injected simultaneous mode */ -#define ADC_Mode_CombRegSimulAltTrig ((uint32_t)0x00000002) /*!< ADC multi ADC mode: Combined Regular simultaneous Alternate trigger mode */ -#define ADC_Mode_InjSimul ((uint32_t)0x00000005) /*!< ADC multi ADC mode: Injected simultaneous mode */ -#define ADC_Mode_RegSimul ((uint32_t)0x00000006) /*!< ADC multi ADC mode: Regular simultaneous mode */ -#define ADC_Mode_Interleave ((uint32_t)0x00000007) /*!< ADC multi ADC mode: Interleave mode */ -#define ADC_Mode_AltTrig ((uint32_t)0x00000009) /*!< ADC multi ADC mode: Alternate Trigger mode */ - -#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ - ((MODE) == ADC_Mode_CombRegSimulInjSimul) || \ - ((MODE) == ADC_Mode_CombRegSimulAltTrig) || \ - ((MODE) == ADC_Mode_InjSimul) || \ - ((MODE) == ADC_Mode_RegSimul) || \ - ((MODE) == ADC_Mode_Interleave) || \ - ((MODE) == ADC_Mode_AltTrig)) - -/** - * @} - */ - -/** @defgroup ADC_Clock - * @{ - */ -#define ADC_Clock_AsynClkMode ((uint32_t)0x00000000) /*!< ADC Asynchronous clock mode */ -#define ADC_Clock_SynClkModeDiv1 ((uint32_t)0x00010000) /*!< Synchronous clock mode divided by 1 */ -#define ADC_Clock_SynClkModeDiv2 ((uint32_t)0x00020000) /*!< Synchronous clock mode divided by 2 */ -#define ADC_Clock_SynClkModeDiv4 ((uint32_t)0x00030000) /*!< Synchronous clock mode divided by 4 */ -#define IS_ADC_CLOCKMODE(CLOCK) (((CLOCK) == ADC_Clock_AsynClkMode) ||\ - ((CLOCK) == ADC_Clock_SynClkModeDiv1) ||\ - ((CLOCK) == ADC_Clock_SynClkModeDiv2)||\ - ((CLOCK) == ADC_Clock_SynClkModeDiv4)) -/** - * @} - */ -/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode - * @{ - */ -#define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /*!< DMA mode disabled */ -#define ADC_DMAAccessMode_1 ((uint32_t)0x00008000) /*!< DMA mode enabled for 12 and 10-bit resolution (6 bit) */ -#define ADC_DMAAccessMode_2 ((uint32_t)0x0000C000) /*!< DMA mode enabled for 8 and 6-bit resolution (8bit) */ -#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \ - ((MODE) == ADC_DMAAccessMode_1) || \ - ((MODE) == ADC_DMAAccessMode_2)) - -/** - * @} - */ -/** @defgroup ADC_sampling_time - * @{ - */ - -#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) /*!< ADC sampling time 1.5 cycle */ -#define ADC_SampleTime_2Cycles5 ((uint8_t)0x01) /*!< ADC sampling time 2.5 cycles */ -#define ADC_SampleTime_4Cycles5 ((uint8_t)0x02) /*!< ADC sampling time 4.5 cycles */ -#define ADC_SampleTime_7Cycles5 ((uint8_t)0x03) /*!< ADC sampling time 7.5 cycles */ -#define ADC_SampleTime_19Cycles5 ((uint8_t)0x04) /*!< ADC sampling time 19.5 cycles */ -#define ADC_SampleTime_61Cycles5 ((uint8_t)0x05) /*!< ADC sampling time 61.5 cycles */ -#define ADC_SampleTime_181Cycles5 ((uint8_t)0x06) /*!< ADC sampling time 181.5 cycles */ -#define ADC_SampleTime_601Cycles5 ((uint8_t)0x07) /*!< ADC sampling time 601.5 cycles */ -#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \ - ((TIME) == ADC_SampleTime_2Cycles5) || \ - ((TIME) == ADC_SampleTime_4Cycles5) || \ - ((TIME) == ADC_SampleTime_7Cycles5) || \ - ((TIME) == ADC_SampleTime_19Cycles5) || \ - ((TIME) == ADC_SampleTime_61Cycles5) || \ - ((TIME) == ADC_SampleTime_181Cycles5) || \ - ((TIME) == ADC_SampleTime_601Cycles5)) -/** - * @} - */ - -/** @defgroup ADC_injected_Channel_selection - * @{ - */ - -#define ADC_InjectedChannel_1 ADC_Channel_1 /*!< ADC Injected channel 1 */ -#define ADC_InjectedChannel_2 ADC_Channel_2 /*!< ADC Injected channel 2 */ -#define ADC_InjectedChannel_3 ADC_Channel_3 /*!< ADC Injected channel 3 */ -#define ADC_InjectedChannel_4 ADC_Channel_4 /*!< ADC Injected channel 4 */ -#define ADC_InjectedChannel_5 ADC_Channel_5 /*!< ADC Injected channel 5 */ -#define ADC_InjectedChannel_6 ADC_Channel_6 /*!< ADC Injected channel 6 */ -#define ADC_InjectedChannel_7 ADC_Channel_7 /*!< ADC Injected channel 7 */ -#define ADC_InjectedChannel_8 ADC_Channel_8 /*!< ADC Injected channel 8 */ -#define ADC_InjectedChannel_9 ADC_Channel_9 /*!< ADC Injected channel 9 */ -#define ADC_InjectedChannel_10 ADC_Channel_10 /*!< ADC Injected channel 10 */ -#define ADC_InjectedChannel_11 ADC_Channel_11 /*!< ADC Injected channel 11 */ -#define ADC_InjectedChannel_12 ADC_Channel_12 /*!< ADC Injected channel 12 */ -#define ADC_InjectedChannel_13 ADC_Channel_13 /*!< ADC Injected channel 13 */ -#define ADC_InjectedChannel_14 ADC_Channel_14 /*!< ADC Injected channel 14 */ -#define ADC_InjectedChannel_15 ADC_Channel_15 /*!< ADC Injected channel 15 */ -#define ADC_InjectedChannel_16 ADC_Channel_16 /*!< ADC Injected channel 16 */ -#define ADC_InjectedChannel_17 ADC_Channel_17 /*!< ADC Injected channel 17 */ -#define ADC_InjectedChannel_18 ADC_Channel_18 /*!< ADC Injected channel 18 */ - -#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ - ((CHANNEL) == ADC_InjectedChannel_2) || \ - ((CHANNEL) == ADC_InjectedChannel_3) || \ - ((CHANNEL) == ADC_InjectedChannel_4) ||\ - ((CHANNEL) == ADC_InjectedChannel_5) ||\ - ((CHANNEL) == ADC_InjectedChannel_6) ||\ - ((CHANNEL) == ADC_InjectedChannel_7) ||\ - ((CHANNEL) == ADC_InjectedChannel_8) ||\ - ((CHANNEL) == ADC_InjectedChannel_9) ||\ - ((CHANNEL) == ADC_InjectedChannel_10) ||\ - ((CHANNEL) == ADC_InjectedChannel_11) ||\ - ((CHANNEL) == ADC_InjectedChannel_12) ||\ - ((CHANNEL) == ADC_InjectedChannel_13) ||\ - ((CHANNEL) == ADC_InjectedChannel_14) ||\ - ((CHANNEL) == ADC_InjectedChannel_15) ||\ - ((CHANNEL) == ADC_InjectedChannel_16) ||\ - ((CHANNEL) == ADC_InjectedChannel_17) ||\ - ((CHANNEL) == ADC_InjectedChannel_18)) -/** - * @} - */ - -/** @defgroup ADC_injected_Sequence_selection - * @{ - */ - -#define ADC_InjectedSequence_1 ADC_Channel_1 /*!< ADC Injected sequence 1 */ -#define ADC_InjectedSequence_2 ADC_Channel_2 /*!< ADC Injected sequence 2 */ -#define ADC_InjectedSequence_3 ADC_Channel_3 /*!< ADC Injected sequence 3 */ -#define ADC_InjectedSequence_4 ADC_Channel_4 /*!< ADC Injected sequence 4 */ -#define IS_ADC_INJECTED_SEQUENCE(SEQUENCE) (((SEQUENCE) == ADC_InjectedSequence_1) || \ - ((SEQUENCE) == ADC_InjectedSequence_2) || \ - ((SEQUENCE) == ADC_InjectedSequence_3) || \ - ((SEQUENCE) == ADC_InjectedSequence_4)) -/** - * @} - */ - -/** @defgroup ADC_analog_watchdog_selection - * @{ - */ - -#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00C00000) /*!< ADC Analog watchdog single regular mode */ -#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x01400000) /*!< ADC Analog watchdog single injected mode */ -#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x01C00000) /*!< ADC Analog watchdog single regular or injected mode */ -#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) /*!< ADC Analog watchdog all regular mode */ -#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x01000000) /*!< ADC Analog watchdog all injected mode */ -#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x01800000) /*!< ADC Analog watchdog all regular and all injected mode */ -#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) /*!< ADC Analog watchdog off */ - -#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_None)) -/** - * @} - */ - -/** @defgroup ADC_Calibration_Mode_definition - * @{ - */ -#define ADC_CalibrationMode_Single ((uint32_t)0x00000000) /*!< ADC Calibration for single ended channel */ -#define ADC_CalibrationMode_Differential ((uint32_t)0x40000000) /*!< ADC Calibration for differential channel */ - -#define IS_ADC_CALIBRATION_MODE(MODE) (((MODE) == ADC_CalibrationMode_Single) ||((MODE) == ADC_CalibrationMode_Differential)) - -/** - * @} - */ - -/** @defgroup ADC_DMA_Mode_definition - * @{ - */ -#define ADC_DMAMode_OneShot ((uint32_t)0x00000000) /*!< ADC DMA Oneshot mode */ -#define ADC_DMAMode_Circular ((uint32_t)0x00000002) /*!< ADC DMA circular mode */ - -#define IS_ADC_DMA_MODE(MODE) (((MODE) == ADC_DMAMode_OneShot) || ((MODE) == ADC_DMAMode_Circular)) -/** - * @} - */ - -/** @defgroup ADC_interrupts_definition - * @{ - */ - -#define ADC_IT_RDY ((uint16_t)0x0001) /*!< ADC Ready (ADRDY) interrupt source */ -#define ADC_IT_EOSMP ((uint16_t)0x0002) /*!< ADC End of Sampling interrupt source */ -#define ADC_IT_EOC ((uint16_t)0x0004) /*!< ADC End of Regular Conversion interrupt source */ -#define ADC_IT_EOS ((uint16_t)0x0008) /*!< ADC End of Regular sequence of Conversions interrupt source */ -#define ADC_IT_OVR ((uint16_t)0x0010) /*!< ADC overrun interrupt source */ -#define ADC_IT_JEOC ((uint16_t)0x0020) /*!< ADC End of Injected Conversion interrupt source */ -#define ADC_IT_JEOS ((uint16_t)0x0040) /*!< ADC End of Injected sequence of Conversions interrupt source */ -#define ADC_IT_AWD1 ((uint16_t)0x0080) /*!< ADC Analog watchdog 1 interrupt source */ -#define ADC_IT_AWD2 ((uint16_t)0x0100) /*!< ADC Analog watchdog 2 interrupt source */ -#define ADC_IT_AWD3 ((uint16_t)0x0200) /*!< ADC Analog watchdog 3 interrupt source */ -#define ADC_IT_JQOVF ((uint16_t)0x0400) /*!< ADC Injected Context Queue Overflow interrupt source */ - - -#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF800) == 0x0000) && ((IT) != 0x0000)) - -#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_RDY) || ((IT) == ADC_IT_EOSMP) || \ - ((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_EOS) || \ - ((IT) == ADC_IT_OVR) || ((IT) == ADC_IT_EOS) || \ - ((IT) == ADC_IT_JEOS) || ((IT) == ADC_IT_AWD1) || \ - ((IT) == ADC_IT_AWD2) || ((IT) == ADC_IT_AWD3) || \ - ((IT) == ADC_IT_JQOVF)) -/** - * @} - */ - -/** @defgroup ADC_flags_definition - * @{ - */ - -#define ADC_FLAG_RDY ((uint16_t)0x0001) /*!< ADC Ready (ADRDY) flag */ -#define ADC_FLAG_EOSMP ((uint16_t)0x0002) /*!< ADC End of Sampling flag */ -#define ADC_FLAG_EOC ((uint16_t)0x0004) /*!< ADC End of Regular Conversion flag */ -#define ADC_FLAG_EOS ((uint16_t)0x0008) /*!< ADC End of Regular sequence of Conversions flag */ -#define ADC_FLAG_OVR ((uint16_t)0x0010) /*!< ADC overrun flag */ -#define ADC_FLAG_JEOC ((uint16_t)0x0020) /*!< ADC End of Injected Conversion flag */ -#define ADC_FLAG_JEOS ((uint16_t)0x0040) /*!< ADC End of Injected sequence of Conversions flag */ -#define ADC_FLAG_AWD1 ((uint16_t)0x0080) /*!< ADC Analog watchdog 1 flag */ -#define ADC_FLAG_AWD2 ((uint16_t)0x0100) /*!< ADC Analog watchdog 2 flag */ -#define ADC_FLAG_AWD3 ((uint16_t)0x0200) /*!< ADC Analog watchdog 3 flag */ -#define ADC_FLAG_JQOVF ((uint16_t)0x0400) /*!< ADC Injected Context Queue Overflow flag */ - -#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xF800) == 0x0000) && ((FLAG) != 0x0000)) -#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_RDY) || ((FLAG) == ADC_FLAG_EOSMP) || \ - ((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_EOS) || \ - ((FLAG) == ADC_FLAG_OVR) || ((FLAG) == ADC_FLAG_JEOC) || \ - ((FLAG) == ADC_FLAG_JEOS) || ((FLAG) == ADC_FLAG_AWD1) || \ - ((FLAG) == ADC_FLAG_AWD2) || ((FLAG) == ADC_FLAG_AWD3) || \ - ((FLAG) == ADC_FLAG_JQOVF)) -/** - * @} - */ - -/** @defgroup ADC_Common_flags_definition - * @{ - */ - -#define ADC_FLAG_MSTRDY ((uint32_t)0x00000001) /*!< ADC Master Ready (ADRDY) flag */ -#define ADC_FLAG_MSTEOSMP ((uint32_t)0x00000002) /*!< ADC Master End of Sampling flag */ -#define ADC_FLAG_MSTEOC ((uint32_t)0x00000004) /*!< ADC Master End of Regular Conversion flag */ -#define ADC_FLAG_MSTEOS ((uint32_t)0x00000008) /*!< ADC Master End of Regular sequence of Conversions flag */ -#define ADC_FLAG_MSTOVR ((uint32_t)0x00000010) /*!< ADC Master overrun flag */ -#define ADC_FLAG_MSTJEOC ((uint32_t)0x00000020) /*!< ADC Master End of Injected Conversion flag */ -#define ADC_FLAG_MSTJEOS ((uint32_t)0x00000040) /*!< ADC Master End of Injected sequence of Conversions flag */ -#define ADC_FLAG_MSTAWD1 ((uint32_t)0x00000080) /*!< ADC Master Analog watchdog 1 flag */ -#define ADC_FLAG_MSTAWD2 ((uint32_t)0x00000100) /*!< ADC Master Analog watchdog 2 flag */ -#define ADC_FLAG_MSTAWD3 ((uint32_t)0x00000200) /*!< ADC Master Analog watchdog 3 flag */ -#define ADC_FLAG_MSTJQOVF ((uint32_t)0x00000400) /*!< ADC Master Injected Context Queue Overflow flag */ - -#define ADC_FLAG_SLVRDY ((uint32_t)0x00010000) /*!< ADC Slave Ready (ADRDY) flag */ -#define ADC_FLAG_SLVEOSMP ((uint32_t)0x00020000) /*!< ADC Slave End of Sampling flag */ -#define ADC_FLAG_SLVEOC ((uint32_t)0x00040000) /*!< ADC Slave End of Regular Conversion flag */ -#define ADC_FLAG_SLVEOS ((uint32_t)0x00080000) /*!< ADC Slave End of Regular sequence of Conversions flag */ -#define ADC_FLAG_SLVOVR ((uint32_t)0x00100000) /*!< ADC Slave overrun flag */ -#define ADC_FLAG_SLVJEOC ((uint32_t)0x00200000) /*!< ADC Slave End of Injected Conversion flag */ -#define ADC_FLAG_SLVJEOS ((uint32_t)0x00400000) /*!< ADC Slave End of Injected sequence of Conversions flag */ -#define ADC_FLAG_SLVAWD1 ((uint32_t)0x00800000) /*!< ADC Slave Analog watchdog 1 flag */ -#define ADC_FLAG_SLVAWD2 ((uint32_t)0x01000000) /*!< ADC Slave Analog watchdog 2 flag */ -#define ADC_FLAG_SLVAWD3 ((uint32_t)0x02000000) /*!< ADC Slave Analog watchdog 3 flag */ -#define ADC_FLAG_SLVJQOVF ((uint32_t)0x04000000) /*!< ADC Slave Injected Context Queue Overflow flag */ - -#define IS_ADC_CLEAR_COMMONFLAG(FLAG) ((((FLAG) & (uint32_t)0xF800F800) == 0x0000) && ((FLAG) != 0x00000000)) -#define IS_ADC_GET_COMMONFLAG(FLAG) (((FLAG) == ADC_FLAG_MSTRDY) || ((FLAG) == ADC_FLAG_MSTEOSMP) || \ - ((FLAG) == ADC_FLAG_MSTEOC) || ((FLAG) == ADC_FLAG_MSTEOS) || \ - ((FLAG) == ADC_FLAG_MSTOVR) || ((FLAG) == ADC_FLAG_MSTEOS) || \ - ((FLAG) == ADC_FLAG_MSTJEOS) || ((FLAG) == ADC_FLAG_MSTAWD1) || \ - ((FLAG) == ADC_FLAG_MSTAWD2) || ((FLAG) == ADC_FLAG_MSTAWD3) || \ - ((FLAG) == ADC_FLAG_MSTJQOVF) || \ - ((FLAG) == ADC_FLAG_SLVRDY) || ((FLAG) == ADC_FLAG_SLVEOSMP) || \ - ((FLAG) == ADC_FLAG_SLVEOC) || ((FLAG) == ADC_FLAG_SLVEOS) || \ - ((FLAG) == ADC_FLAG_SLVOVR) || ((FLAG) == ADC_FLAG_SLVEOS) || \ - ((FLAG) == ADC_FLAG_SLVJEOS) || ((FLAG) == ADC_FLAG_SLVAWD1) || \ - ((FLAG) == ADC_FLAG_SLVAWD2) || ((FLAG) == ADC_FLAG_SLVAWD3) || \ - ((FLAG) == ADC_FLAG_SLVJQOVF)) -/** - * @} - */ - -/** @defgroup ADC_thresholds - * @{ - */ - -#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) - -/** - * @} - */ - -/** @defgroup ADC_injected_offset - * @{ - */ - -#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) - -/** - * @} - */ - -/** @defgroup ADC_injected_length - * @{ - */ - -#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) - -/** - * @} - */ - - -/** @defgroup ADC_regular_length - * @{ - */ - -#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) -/** - * @} - */ - -/** @defgroup ADC_regular_discontinuous_mode_number - * @{ - */ - -#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) - -/** - * @} - */ - -/** @defgroup ADC_two_sampling_delay_number - * @{ - */ -#define IS_ADC_TWOSAMPLING_DELAY(DELAY) (((DELAY) <= 0xF)) - -/** - * @} - */ -/** - * @} - */ - - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the ADC configuration to the default reset state *****/ -void ADC_DeInit(ADC_TypeDef* ADCx); - -/* Initialization and Configuration functions *********************************/ -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); -void ADC_InjectedInit(ADC_TypeDef* ADCx, ADC_InjectedInitTypeDef* ADC_InjectedInitStruct); -void ADC_InjectedStructInit(ADC_InjectedInitTypeDef* ADC_InjectedInitStruct); -void ADC_CommonInit(ADC_TypeDef* ADCx, ADC_CommonInitTypeDef* ADC_CommonInitStruct); -void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); - -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_StartCalibration(ADC_TypeDef* ADCx); -uint32_t ADC_GetCalibrationValue(ADC_TypeDef* ADCx); -void ADC_SetCalibrationValue(ADC_TypeDef* ADCx, uint32_t ADC_Calibration); -void ADC_SelectCalibrationMode(ADC_TypeDef* ADCx, uint32_t ADC_CalibrationMode); -FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); -void ADC_DisableCmd(ADC_TypeDef* ADCx); -FlagStatus ADC_GetDisableCmdStatus(ADC_TypeDef* ADCx); -void ADC_VoltageRegulatorCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_SelectDifferentialMode(ADC_TypeDef* ADCx, uint8_t ADC_Channel, FunctionalState NewState); -void ADC_SelectQueueOfContextMode(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_AutoDelayCmd(ADC_TypeDef* ADCx, FunctionalState NewState); - -/* Analog Watchdog configuration functions ************************************/ -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); -void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); -void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold, uint8_t LowThreshold); -void ADC_AnalogWatchdog3ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold, uint8_t LowThreshold); -void ADC_AnalogWatchdog1SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); -void ADC_AnalogWatchdog2SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); -void ADC_AnalogWatchdog3SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); - -/* Temperature Sensor, Vrefint and Vbat management function */ -void ADC_TempSensorCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_VrefintCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_VbatCmd(ADC_TypeDef* ADCx, FunctionalState NewState); - -/* Channels Configuration functions ***********************************/ -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_RegularChannelSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t SequencerLength); -void ADC_ExternalTriggerConfig(ADC_TypeDef* ADCx, uint16_t ADC_ExternalTrigConvEvent, uint16_t ADC_ExternalTrigEventEdge); - -void ADC_StartConversion(ADC_TypeDef* ADCx); -FlagStatus ADC_GetStartConversionStatus(ADC_TypeDef* ADCx); -void ADC_StopConversion(ADC_TypeDef* ADCx); -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); -uint32_t ADC_GetDualModeConversionValue(ADC_TypeDef* ADCx); - -void ADC_SetChannelOffset1(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset); -void ADC_SetChannelOffset2(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset); -void ADC_SetChannelOffset3(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset); -void ADC_SetChannelOffset4(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset); - -void ADC_ChannelOffset1Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_ChannelOffset2Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_ChannelOffset3Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_ChannelOffset4Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); - -/* Regular Channels DMA Configuration functions *******************************/ -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_DMAConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMAMode); - -/* Injected channels Configuration functions **********************************/ -void ADC_InjectedChannelSampleTimeConfig(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint8_t ADC_SampleTime); -void ADC_StartInjectedConversion(ADC_TypeDef* ADCx); -FlagStatus ADC_GetStartInjectedConversionStatus(ADC_TypeDef* ADCx); -void ADC_StopInjectedConversion(ADC_TypeDef* ADCx); -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); - -/* ADC Dual Modes Configuration functions *************************************/ -FlagStatus ADC_GetCommonFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG); -void ADC_ClearCommonFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG); - -/* Interrupts and flags management functions **********************************/ -void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState); -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG); -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG); -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT); -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F30x_ADC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_can.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1639 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_can.c - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Controller area network (CAN) peripheral: - * + Initialization and Configuration - * + CAN Frames Transmission - * + CAN Frames Reception - * + Operation modes switch - * + Error management - * + Interrupts and flags - * - @verbatim - - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable the CAN controller interface clock using - RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); - (#) CAN pins configuration: - (++) Enable the clock for the CAN GPIOs using the following function: - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE); - (++) Connect the involved CAN pins to AF9 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx); - (++) Configure these CAN pins in alternate function mode by calling - the function GPIO_Init(); - (#) Initialise and configure the CAN using CAN_Init() and - CAN_FilterInit() functions. - (#) Transmit the desired CAN frame using CAN_Transmit() function. - (#) Check the transmission of a CAN frame using CAN_TransmitStatus() function. - (#) Cancel the transmission of a CAN frame using CAN_CancelTransmit() function. - (#) Receive a CAN frame using CAN_Recieve() function. - (#) Release the receive FIFOs using CAN_FIFORelease() function. - (#) Return the number of pending received frames using CAN_MessagePending() function. - (#) To control CAN events you can use one of the following two methods: - (++) Check on CAN flags using the CAN_GetFlagStatus() function. - (++) Use CAN interrupts through the function CAN_ITConfig() at initialization - phase and CAN_GetITStatus() function into interrupt routines to check - if the event has occurred or not. - After checking on a flag you should clear it using CAN_ClearFlag() - function. And after checking on an interrupt event you should clear it - using CAN_ClearITPendingBit() function. - - @endverbatim - * - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x_can.h" -#include "stm32f30x_rcc.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @defgroup CAN - * @brief CAN driver modules - * @{ - */ -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* CAN Master Control Register bits */ -#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */ - -/* CAN Mailbox Transmit Request */ -#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ - -/* CAN Filter Master Register bits */ -#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ - -/* Time out for INAK bit */ -#define INAK_TIMEOUT ((uint32_t)0x00FFFFFF) -/* Time out for SLAK bit */ -#define SLAK_TIMEOUT ((uint32_t)0x00FFFFFF) - -/* Flags in TSR register */ -#define CAN_FLAGS_TSR ((uint32_t)0x08000000) -/* Flags in RF1R register */ -#define CAN_FLAGS_RF1R ((uint32_t)0x04000000) -/* Flags in RF0R register */ -#define CAN_FLAGS_RF0R ((uint32_t)0x02000000) -/* Flags in MSR register */ -#define CAN_FLAGS_MSR ((uint32_t)0x01000000) -/* Flags in ESR register */ -#define CAN_FLAGS_ESR ((uint32_t)0x00F00000) - -/* Mailboxes definition */ -#define CAN_TXMAILBOX_0 ((uint8_t)0x00) -#define CAN_TXMAILBOX_1 ((uint8_t)0x01) -#define CAN_TXMAILBOX_2 ((uint8_t)0x02) - -#define CAN_MODE_MASK ((uint32_t) 0x00000003) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); - -/** @defgroup CAN_Private_Functions - * @{ - */ - -/** @defgroup CAN_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the CAN peripherals : Prescaler, operating mode, the maximum - number of time quanta to perform resynchronization, the number of time - quanta in Bit Segment 1 and 2 and many other modes. - (+) Configure the CAN reception filter. - (+) Select the start bank filter for slave CAN. - (+) Enable or disable the Debug Freeze mode for CAN. - (+) Enable or disable the CAN Time Trigger Operation communication mode. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the CAN peripheral registers to their default reset values. - * @param CANx: where x can be 1 to select the CAN1 peripheral. - * @retval None. - */ -void CAN_DeInit(CAN_TypeDef* CANx) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Enable CAN1 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); - /* Release CAN1 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); -} - -/** - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_InitStruct. - * @param CANx: where x can be 1 to select the CAN1 peripheral. - * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains - * the configuration information for the CAN peripheral. - * @retval Constant indicates initialization succeed which will be - * CAN_InitStatus_Failed or CAN_InitStatus_Success. - */ -uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) -{ - uint8_t InitStatus = CAN_InitStatus_Failed; - __IO uint32_t wait_ack = 0x00000000; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); - assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); - assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); - assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); - assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); - assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); - - /* Exit from sleep mode */ - CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP); - - /* Request initialisation */ - CANx->MCR |= CAN_MCR_INRQ ; - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - /* Check acknowledge */ - if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - /* Set the time triggered communication mode */ - if (CAN_InitStruct->CAN_TTCM == ENABLE) - { - CANx->MCR |= CAN_MCR_TTCM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM; - } - - /* Set the automatic bus-off management */ - if (CAN_InitStruct->CAN_ABOM == ENABLE) - { - CANx->MCR |= CAN_MCR_ABOM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM; - } - - /* Set the automatic wake-up mode */ - if (CAN_InitStruct->CAN_AWUM == ENABLE) - { - CANx->MCR |= CAN_MCR_AWUM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM; - } - - /* Set the no automatic retransmission */ - if (CAN_InitStruct->CAN_NART == ENABLE) - { - CANx->MCR |= CAN_MCR_NART; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_NART; - } - - /* Set the receive FIFO locked mode */ - if (CAN_InitStruct->CAN_RFLM == ENABLE) - { - CANx->MCR |= CAN_MCR_RFLM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM; - } - - /* Set the transmit FIFO priority */ - if (CAN_InitStruct->CAN_TXFP == ENABLE) - { - CANx->MCR |= CAN_MCR_TXFP; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP; - } - - /* Set the bit timing register */ - CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \ - ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \ - ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \ - ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \ - ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); - - /* Request leave initialisation */ - CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ; - - /* Wait the acknowledge */ - wait_ack = 0; - - while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - /* ...and check acknowledged */ - if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - InitStatus = CAN_InitStatus_Success ; - } - } - - /* At this step, return the status of initialization */ - return InitStatus; -} - -/** - * @brief Configures the CAN reception filter according to the specified - * parameters in the CAN_FilterInitStruct. - * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that - * contains the configuration information. - * @retval None - */ -void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) -{ - uint32_t filter_number_bit_pos = 0; - /* Check the parameters */ - assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); - assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); - assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); - assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); - assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); - - filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; - - /* Initialisation mode for the filter */ - CAN1->FMR |= FMR_FINIT; - - /* Filter Deactivation */ - CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos; - - /* Filter Scale */ - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) - { - /* 16-bit scale for the filter */ - CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos; - - /* First 16-bit identifier and First 16-bit mask */ - /* Or First 16-bit identifier and Second 16-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - - /* Second 16-bit identifier and Second 16-bit mask */ - /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); - } - - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) - { - /* 32-bit scale for the filter */ - CAN1->FS1R |= filter_number_bit_pos; - /* 32-bit identifier or First 32-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - /* 32-bit mask or Second 32-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); - } - - /* Filter Mode */ - if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) - { - /*Id/Mask mode for the filter*/ - CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos; - } - else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ - { - /*Identifier list mode for the filter*/ - CAN1->FM1R |= (uint32_t)filter_number_bit_pos; - } - - /* Filter FIFO assignment */ - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) - { - /* FIFO 0 assignation for the filter */ - CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos; - } - - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) - { - /* FIFO 1 assignation for the filter */ - CAN1->FFA1R |= (uint32_t)filter_number_bit_pos; - } - - /* Filter activation */ - if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) - { - CAN1->FA1R |= filter_number_bit_pos; - } - - /* Leave the initialisation mode for the filter */ - CAN1->FMR &= ~FMR_FINIT; -} - -/** - * @brief Fills each CAN_InitStruct member with its default value. - * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized. - * @retval None - */ -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) -{ - /* Reset CAN init structure parameters values */ - - /* Initialize the time triggered communication mode */ - CAN_InitStruct->CAN_TTCM = DISABLE; - - /* Initialize the automatic bus-off management */ - CAN_InitStruct->CAN_ABOM = DISABLE; - - /* Initialize the automatic wake-up mode */ - CAN_InitStruct->CAN_AWUM = DISABLE; - - /* Initialize the no automatic retransmission */ - CAN_InitStruct->CAN_NART = DISABLE; - - /* Initialize the receive FIFO locked mode */ - CAN_InitStruct->CAN_RFLM = DISABLE; - - /* Initialize the transmit FIFO priority */ - CAN_InitStruct->CAN_TXFP = DISABLE; - - /* Initialize the CAN_Mode member */ - CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; - - /* Initialize the CAN_SJW member */ - CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; - - /* Initialize the CAN_BS1 member */ - CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; - - /* Initialize the CAN_BS2 member */ - CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; - - /* Initialize the CAN_Prescaler member */ - CAN_InitStruct->CAN_Prescaler = 1; -} - -/** - * @brief Select the start bank filter for slave CAN. - * @param CAN_BankNumber: Select the start slave bank filter from 1..27. - * @retval None - */ -void CAN_SlaveStartBank(uint8_t CAN_BankNumber) -{ - /* Check the parameters */ - assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); - - /* Enter Initialisation mode for the filter */ - CAN1->FMR |= FMR_FINIT; - - /* Select the start slave bank */ - CAN1->FMR &= (uint32_t)0xFFFFC0F1 ; - CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8; - - /* Leave Initialisation mode for the filter */ - CAN1->FMR &= ~FMR_FINIT; -} - -/** - * @brief Enables or disables the DBG Freeze for CAN. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param NewState: new state of the CAN peripheral. - * This parameter can be: ENABLE (CAN reception/transmission is frozen - * during debug. Reception FIFOs can still be accessed/controlled normally) - * or DISABLE (CAN is working during debug). - * @retval None - */ -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Debug Freeze */ - CANx->MCR |= MCR_DBF; - } - else - { - /* Disable Debug Freeze */ - CANx->MCR &= ~MCR_DBF; - } -} - -/** - * @brief Enables or disables the CAN Time TriggerOperation communication mode. - * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be - * sent over the CAN bus. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param NewState: Mode new state. This parameter can be: ENABLE or DISABLE. - * When enabled, Time stamp (TIME[15:0]) value is sent in the last two - * data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8] - * in data byte 7. - * @retval None - */ -void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the TTCM mode */ - CANx->MCR |= CAN_MCR_TTCM; - - /* Set TGT bits */ - CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT); - CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT); - CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT); - } - else - { - /* Disable the TTCM mode */ - CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM); - - /* Reset TGT bits */ - CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT); - CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT); - CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT); - } -} -/** - * @} - */ - - -/** @defgroup CAN_Group2 CAN Frames Transmission functions - * @brief CAN Frames Transmission functions - * -@verbatim - =============================================================================== - ##### CAN Frames Transmission functions ##### - =============================================================================== - [..] This section provides functions allowing to - (+) Initiate and transmit a CAN frame message (if there is an empty mailbox). - (+) Check the transmission status of a CAN Frame. - (+) Cancel a transmit request. - -@endverbatim - * @{ - */ - -/** - * @brief Initiates and transmits a CAN frame message. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data. - * @retval The number of the mailbox that is used for transmission or - * CAN_TxStatus_NoMailBox if there is no empty mailbox. - */ -uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) -{ - uint8_t transmit_mailbox = 0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); - assert_param(IS_CAN_RTR(TxMessage->RTR)); - assert_param(IS_CAN_DLC(TxMessage->DLC)); - - /* Select one empty transmit mailbox */ - if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) - { - transmit_mailbox = 0; - } - else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmit_mailbox = 1; - } - else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) - { - transmit_mailbox = 2; - } - else - { - transmit_mailbox = CAN_TxStatus_NoMailBox; - } - - if (transmit_mailbox != CAN_TxStatus_NoMailBox) - { - /* Set up the Id */ - CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; - if (TxMessage->IDE == CAN_Id_Standard) - { - assert_param(IS_CAN_STDID(TxMessage->StdId)); - CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \ - TxMessage->RTR); - } - else - { - assert_param(IS_CAN_EXTID(TxMessage->ExtId)); - CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \ - TxMessage->IDE | \ - TxMessage->RTR); - } - - /* Set up the DLC */ - TxMessage->DLC &= (uint8_t)0x0000000F; - CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0; - CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC; - - /* Set up the data field */ - CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | - ((uint32_t)TxMessage->Data[2] << 16) | - ((uint32_t)TxMessage->Data[1] << 8) | - ((uint32_t)TxMessage->Data[0])); - CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | - ((uint32_t)TxMessage->Data[6] << 16) | - ((uint32_t)TxMessage->Data[5] << 8) | - ((uint32_t)TxMessage->Data[4])); - /* Request transmission */ - CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ; - } - return transmit_mailbox; -} - -/** - * @brief Checks the transmission status of a CAN Frame. - * @param CANx: where x can be 1 to select the CAN1 peripheral. - * @param TransmitMailbox: the number of the mailbox that is used for transmission. - * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, - * CAN_TxStatus_Failed in an other case. - */ -uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) -{ - uint32_t state = 0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); - - switch (TransmitMailbox) - { - case (CAN_TXMAILBOX_0): - state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0); - break; - case (CAN_TXMAILBOX_1): - state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1); - break; - case (CAN_TXMAILBOX_2): - state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2); - break; - default: - state = CAN_TxStatus_Failed; - break; - } - switch (state) - { - /* transmit pending */ - case (0x0): state = CAN_TxStatus_Pending; - break; - /* transmit failed */ - case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed; - break; - case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed; - break; - case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed; - break; - /* transmit succeeded */ - case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok; - break; - case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok; - break; - case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok; - break; - default: state = CAN_TxStatus_Failed; - break; - } - return (uint8_t) state; -} - -/** - * @brief Cancels a transmit request. - * @param CANx: where x can be 1 to select the CAN1 peripheral. - * @param Mailbox: Mailbox number. - * @retval None - */ -void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); - /* abort transmission */ - switch (Mailbox) - { - case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0; - break; - case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1; - break; - case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2; - break; - default: - break; - } -} -/** - * @} - */ - - -/** @defgroup CAN_Group3 CAN Frames Reception functions - * @brief CAN Frames Reception functions - * -@verbatim - =============================================================================== - ##### CAN Frames Reception functions ##### - =============================================================================== - [..] This section provides functions allowing to - (+) Receive a correct CAN frame. - (+) Release a specified receive FIFO (2 FIFOs are available). - (+) Return the number of the pending received CAN frames. - -@endverbatim - * @{ - */ - -/** - * @brief Receives a correct CAN frame. - * @param CANx: where x can be 1 to select the CAN1 peripheral. - * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @param RxMessage: pointer to a structure receive frame which contains CAN Id, - * CAN DLC, CAN data and FMI number. - * @retval None - */ -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - /* Get the Id */ - RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; - if (RxMessage->IDE == CAN_Id_Standard) - { - RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); - } - else - { - RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); - } - - RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FMI */ - RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); - /* Get the data field */ - RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; - RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); - RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); - RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); - RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; - RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); - RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); - RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); - /* Release the FIFO */ - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - CANx->RF0R |= CAN_RF0R_RFOM0; - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - CANx->RF1R |= CAN_RF1R_RFOM1; - } -} - -/** - * @brief Releases the specified receive FIFO. - * @param CANx: where x can be 1 to select the CAN1 peripheral. - * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. - * @retval None - */ -void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - CANx->RF0R |= CAN_RF0R_RFOM0; - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - CANx->RF1R |= CAN_RF1R_RFOM1; - } -} - -/** - * @brief Returns the number of pending received messages. - * @param CANx: where x can be 1 to select the CAN1 peripheral. - * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval NbMessage : which is the number of pending message. - */ -uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - uint8_t message_pending=0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - if (FIFONumber == CAN_FIFO0) - { - message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03); - } - else if (FIFONumber == CAN_FIFO1) - { - message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03); - } - else - { - message_pending = 0; - } - return message_pending; -} -/** - * @} - */ - - -/** @defgroup CAN_Group4 CAN Operation modes functions - * @brief CAN Operation modes functions - * -@verbatim - =============================================================================== - ##### CAN Operation modes functions ##### - =============================================================================== - [..] This section provides functions allowing to select the CAN Operation modes: - (+) sleep mode. - (+) normal mode. - (+) initialization mode. - -@endverbatim - * @{ - */ - - -/** - * @brief Selects the CAN Operation mode. - * @param CAN_OperatingMode: CAN Operating Mode. - * This parameter can be one of @ref CAN_OperatingMode_TypeDef enumeration. - * @retval status of the requested mode which can be: - * - CAN_ModeStatus_Failed: CAN failed entering the specific mode - * - CAN_ModeStatus_Success: CAN Succeed entering the specific mode - */ -uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode) -{ - uint8_t status = CAN_ModeStatus_Failed; - - /* Timeout for INAK or also for SLAK bits*/ - uint32_t timeout = INAK_TIMEOUT; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode)); - - if (CAN_OperatingMode == CAN_OperatingMode_Initialization) - { - /* Request initialisation */ - CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else if (CAN_OperatingMode == CAN_OperatingMode_Normal) - { - /* Request leave initialisation and sleep mode and enter Normal mode */ - CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ)); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != 0) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) - { - /* Request Sleep mode */ - CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else - { - status = CAN_ModeStatus_Failed; - } - - return (uint8_t) status; -} - -/** - * @brief Enters the Sleep (low power) mode. - * @param CANx: where x can be 1 to select the CAN1 peripheral. - * @retval CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed otherwise. - */ -uint8_t CAN_Sleep(CAN_TypeDef* CANx) -{ - uint8_t sleepstatus = CAN_Sleep_Failed; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Request Sleep mode */ - CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - - /* Sleep mode status */ - if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK) - { - /* Sleep mode not entered */ - sleepstatus = CAN_Sleep_Ok; - } - /* return sleep mode status */ - return (uint8_t)sleepstatus; -} - -/** - * @brief Wakes up the CAN peripheral from sleep mode . - * @param CANx: where x can be 1 to select the CAN1 peripheral. - * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed otherwise. - */ -uint8_t CAN_WakeUp(CAN_TypeDef* CANx) -{ - uint32_t wait_slak = SLAK_TIMEOUT; - uint8_t wakeupstatus = CAN_WakeUp_Failed; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Wake up request */ - CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP; - - /* Sleep mode status */ - while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00)) - { - wait_slak--; - } - if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK) - { - /* wake up done : Sleep mode exited */ - wakeupstatus = CAN_WakeUp_Ok; - } - /* return wakeup status */ - return (uint8_t)wakeupstatus; -} -/** - * @} - */ - - -/** @defgroup CAN_Group5 CAN Bus Error management functions - * @brief CAN Bus Error management functions - * -@verbatim - =============================================================================== - ##### CAN Bus Error management functions ##### - =============================================================================== - [..] This section provides functions allowing to - (+) Return the CANx's last error code (LEC). - (+) Return the CANx Receive Error Counter (REC). - (+) Return the LSB of the 9-bit CANx Transmit Error Counter(TEC). - [..] - (@) If TEC is greater than 255, The CAN is in bus-off state. - (@) If REC or TEC are greater than 96, an Error warning flag occurs. - (@) If REC or TEC are greater than 127, an Error Passive Flag occurs. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the CANx's last error code (LEC). - * @param CANx: where x can be 1 to select the CAN1 peripheral. - * @retval Error code: - * - CAN_ERRORCODE_NoErr: No Error - * - CAN_ERRORCODE_StuffErr: Stuff Error - * - CAN_ERRORCODE_FormErr: Form Error - * - CAN_ERRORCODE_ACKErr : Acknowledgment Error - * - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error - * - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error - * - CAN_ERRORCODE_CRCErr: CRC Error - * - CAN_ERRORCODE_SoftwareSetErr: Software Set Error - */ -uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx) -{ - uint8_t errorcode=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the error code*/ - errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC); - - /* Return the error code*/ - return errorcode; -} - -/** - * @brief Returns the CANx Receive Error Counter (REC). - * @note In case of an error during reception, this counter is incremented - * by 1 or by 8 depending on the error condition as defined by the CAN - * standard. After every successful reception, the counter is - * decremented by 1 or reset to 120 if its value was higher than 128. - * When the counter value exceeds 127, the CAN controller enters the - * error passive state. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval CAN Receive Error Counter. - */ -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx) -{ - uint8_t counter=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the Receive Error Counter*/ - counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24); - - /* Return the Receive Error Counter*/ - return counter; -} - - -/** - * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval LSB of the 9-bit CAN Transmit Error Counter. - */ -uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) -{ - uint8_t counter=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ - counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16); - - /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ - return counter; -} -/** - * @} - */ - -/** @defgroup CAN_Group6 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - [..] This section provides functions allowing to configure the CAN Interrupts - and to get the status and clear flags and Interrupts pending bits. - [..] The CAN provides 14 Interrupts sources and 15 Flags: - - *** Flags *** - ============= - [..] The 15 flags can be divided on 4 groups: - (+) Transmit Flags: - (++) CAN_FLAG_RQCP0. - (++) CAN_FLAG_RQCP1. - (++) CAN_FLAG_RQCP2: Request completed MailBoxes 0, 1 and 2 Flags - Set when when the last request (transmit or abort) has - been performed. - (+) Receive Flags: - (++) CAN_FLAG_FMP0. - (++) CAN_FLAG_FMP1: FIFO 0 and 1 Message Pending Flags; - Set to signal that messages are pending in the receive FIFO. - These Flags are cleared only by hardware. - (++) CAN_FLAG_FF0. - (++) CAN_FLAG_FF1: FIFO 0 and 1 Full Flags; - Set when three messages are stored in the selected FIFO. - (++) CAN_FLAG_FOV0. - (++) CAN_FLAG_FOV1: FIFO 0 and 1 Overrun Flags; - Set when a new message has been received and passed the filter - while the FIFO was full. - (+) Operating Mode Flags: - (++) CAN_FLAG_WKU: Wake up Flag; - Set to signal that a SOF bit has been detected while the CAN - hardware was in Sleep mode. - (++) CAN_FLAG_SLAK: Sleep acknowledge Flag; - Set to signal that the CAN has entered Sleep Mode. - (+) Error Flags: - (++) CAN_FLAG_EWG: Error Warning Flag; - Set when the warning limit has been reached (Receive Error Counter - or Transmit Error Counter greater than 96). - This Flag is cleared only by hardware. - (++) CAN_FLAG_EPV: Error Passive Flag; - Set when the Error Passive limit has been reached (Receive Error - Counter or Transmit Error Counter greater than 127). - This Flag is cleared only by hardware. - (++) CAN_FLAG_BOF: Bus-Off Flag; - Set when CAN enters the bus-off state. The bus-off state is - entered on TEC overflow, greater than 255. - This Flag is cleared only by hardware. - (++) CAN_FLAG_LEC: Last error code Flag; - Set If a message has been transferred (reception or transmission) - with error, and the error code is hold. - - *** Interrupts *** - ================== - [..] The 14 interrupts can be divided on 4 groups: - (+) Transmit interrupt: - (++) CAN_IT_TME: Transmit mailbox empty Interrupt; - If enabled, this interrupt source is pending when no transmit - request are pending for Tx mailboxes. - (+) Receive Interrupts: - (++) CAN_IT_FMP0. - (++) CAN_IT_FMP1: FIFO 0 and FIFO1 message pending Interrupts; - If enabled, these interrupt sources are pending when messages - are pending in the receive FIFO. - The corresponding interrupt pending bits are cleared only by hardware. - (++) CAN_IT_FF0. - (++) CAN_IT_FF1: FIFO 0 and FIFO1 full Interrupts; - If enabled, these interrupt sources are pending when three messages - are stored in the selected FIFO. - (++) CAN_IT_FOV0. - (++) CAN_IT_FOV1: FIFO 0 and FIFO1 overrun Interrupts; - If enabled, these interrupt sources are pending when a new message - has been received and passed the filter while the FIFO was full. - (+) Operating Mode Interrupts: - (++) CAN_IT_WKU: Wake-up Interrupt; - If enabled, this interrupt source is pending when a SOF bit has - been detected while the CAN hardware was in Sleep mode. - (++) CAN_IT_SLK: Sleep acknowledge Interrupt: - If enabled, this interrupt source is pending when the CAN has - entered Sleep Mode. - (+) Error Interrupts: - (++) CAN_IT_EWG: Error warning Interrupt; - If enabled, this interrupt source is pending when the warning limit - has been reached (Receive Error Counter or Transmit Error Counter=96). - (++) CAN_IT_EPV: Error passive Interrupt; - If enabled, this interrupt source is pending when the Error Passive - limit has been reached (Receive Error Counter or Transmit Error Counter>127). - (++) CAN_IT_BOF: Bus-off Interrupt; - If enabled, this interrupt source is pending when CAN enters - the bus-off state. The bus-off state is entered on TEC overflow, - greater than 255. - This Flag is cleared only by hardware. - (++) CAN_IT_LEC: Last error code Interrupt; - If enabled, this interrupt source is pending when a message has - been transferred (reception or transmission) with error and the - error code is hold. - (++) CAN_IT_ERR: Error Interrupt; - If enabled, this interrupt source is pending when an error condition - is pending. - [..] Managing the CAN controller events: - The user should identify which mode will be used in his application to manage - the CAN controller events: Polling mode or Interrupt mode. - (+) In the Polling Mode it is advised to use the following functions: - (++) CAN_GetFlagStatus() : to check if flags events occur. - (++) CAN_ClearFlag() : to clear the flags events. - (+) In the Interrupt Mode it is advised to use the following functions: - (++) CAN_ITConfig() : to enable or disable the interrupt source. - (++) CAN_GetITStatus() : to check if Interrupt occurs. - (++) CAN_ClearITPendingBit() : to clear the Interrupt pending Bit - (corresponding Flag). - This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts - pending bits since there are cleared only by hardware. - -@endverbatim - * @{ - */ -/** - * @brief Enables or disables the specified CANx interrupts. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg CAN_IT_TME: Transmit mailbox empty Interrupt - * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt - * @arg CAN_IT_FF0: FIFO 0 full Interrupt - * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt - * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt - * @arg CAN_IT_FF1: FIFO 1 full Interrupt - * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt - * @arg CAN_IT_WKU: Wake-up Interrupt - * @arg CAN_IT_SLK: Sleep acknowledge Interrupt - * @arg CAN_IT_EWG: Error warning Interrupt - * @arg CAN_IT_EPV: Error passive Interrupt - * @arg CAN_IT_BOF: Bus-off Interrupt - * @arg CAN_IT_LEC: Last error code Interrupt - * @arg CAN_IT_ERR: Error Interrupt - * @param NewState: new state of the CAN interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IT(CAN_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected CANx interrupt */ - CANx->IER |= CAN_IT; - } - else - { - /* Disable the selected CANx interrupt */ - CANx->IER &= ~CAN_IT; - } -} -/** - * @brief Checks whether the specified CAN flag is set or not. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag - * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag - * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_EWG: Error Warning Flag - * @arg CAN_FLAG_EPV: Error Passive Flag - * @arg CAN_FLAG_BOF: Bus-Off Flag - * @arg CAN_FLAG_LEC: Last error code Flag - * @retval The new state of CAN_FLAG (SET or RESET). - */ -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_GET_FLAG(CAN_FLAG)); - - - if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */ - { - /* Check the status of the specified CAN flag */ - if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - /* Return the CAN_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the CAN's pending flags. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_FLAG: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag - * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag - * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_LEC: Last error code Flag - * @retval None - */ -void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - uint32_t flagtmp=0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG)); - - if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */ - { - /* Clear the selected CAN flags */ - CANx->ESR = (uint32_t)RESET; - } - else /* MSR or TSR or RF0R or RF1R */ - { - flagtmp = CAN_FLAG & 0x000FFFFF; - - if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET) - { - /* Receive Flags */ - CANx->RF0R = (uint32_t)(flagtmp); - } - else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET) - { - /* Receive Flags */ - CANx->RF1R = (uint32_t)(flagtmp); - } - else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET) - { - /* Transmit Flags */ - CANx->TSR = (uint32_t)(flagtmp); - } - else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */ - { - /* Operating mode Flags */ - CANx->MSR = (uint32_t)(flagtmp); - } - } -} - -/** - * @brief Checks whether the specified CANx interrupt has occurred or not. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the CAN interrupt source to check. - * This parameter can be one of the following values: - * @arg CAN_IT_TME: Transmit mailbox empty Interrupt - * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt - * @arg CAN_IT_FF0: FIFO 0 full Interrupt - * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt - * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt - * @arg CAN_IT_FF1: FIFO 1 full Interrupt - * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt - * @arg CAN_IT_WKU: Wake-up Interrupt - * @arg CAN_IT_SLK: Sleep acknowledge Interrupt - * @arg CAN_IT_EWG: Error warning Interrupt - * @arg CAN_IT_EPV: Error passive Interrupt - * @arg CAN_IT_BOF: Bus-off Interrupt - * @arg CAN_IT_LEC: Last error code Interrupt - * @arg CAN_IT_ERR: Error Interrupt - * @retval The current state of CAN_IT (SET or RESET). - */ -ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - ITStatus itstatus = RESET; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IT(CAN_IT)); - - /* check the interrupt enable bit */ - if((CANx->IER & CAN_IT) != RESET) - { - /* in case the Interrupt is enabled, .... */ - switch (CAN_IT) - { - case CAN_IT_TME: - /* Check CAN_TSR_RQCPx bits */ - itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2); - break; - case CAN_IT_FMP0: - /* Check CAN_RF0R_FMP0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0); - break; - case CAN_IT_FF0: - /* Check CAN_RF0R_FULL0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0); - break; - case CAN_IT_FOV0: - /* Check CAN_RF0R_FOVR0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0); - break; - case CAN_IT_FMP1: - /* Check CAN_RF1R_FMP1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1); - break; - case CAN_IT_FF1: - /* Check CAN_RF1R_FULL1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1); - break; - case CAN_IT_FOV1: - /* Check CAN_RF1R_FOVR1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1); - break; - case CAN_IT_WKU: - /* Check CAN_MSR_WKUI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI); - break; - case CAN_IT_SLK: - /* Check CAN_MSR_SLAKI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI); - break; - case CAN_IT_EWG: - /* Check CAN_ESR_EWGF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF); - break; - case CAN_IT_EPV: - /* Check CAN_ESR_EPVF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF); - break; - case CAN_IT_BOF: - /* Check CAN_ESR_BOFF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF); - break; - case CAN_IT_LEC: - /* Check CAN_ESR_LEC bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC); - break; - case CAN_IT_ERR: - /* Check CAN_MSR_ERRI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); - break; - default: - /* in case of error, return RESET */ - itstatus = RESET; - break; - } - } - else - { - /* in case the Interrupt is not enabled, return RESET */ - itstatus = RESET; - } - - /* Return the CAN_IT status */ - return itstatus; -} - -/** - * @brief Clears the CANx's interrupt pending bits. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg CAN_IT_TME: Transmit mailbox empty Interrupt - * @arg CAN_IT_FF0: FIFO 0 full Interrupt - * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt - * @arg CAN_IT_FF1: FIFO 1 full Interrupt - * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt - * @arg CAN_IT_WKU: Wake-up Interrupt - * @arg CAN_IT_SLK: Sleep acknowledge Interrupt - * @arg CAN_IT_EWG: Error warning Interrupt - * @arg CAN_IT_EPV: Error passive Interrupt - * @arg CAN_IT_BOF: Bus-off Interrupt - * @arg CAN_IT_LEC: Last error code Interrupt - * @arg CAN_IT_ERR: Error Interrupt - * @retval None - */ -void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_CLEAR_IT(CAN_IT)); - - switch (CAN_IT) - { - case CAN_IT_TME: - /* Clear CAN_TSR_RQCPx (rc_w1)*/ - CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2; - break; - case CAN_IT_FF0: - /* Clear CAN_RF0R_FULL0 (rc_w1)*/ - CANx->RF0R = CAN_RF0R_FULL0; - break; - case CAN_IT_FOV0: - /* Clear CAN_RF0R_FOVR0 (rc_w1)*/ - CANx->RF0R = CAN_RF0R_FOVR0; - break; - case CAN_IT_FF1: - /* Clear CAN_RF1R_FULL1 (rc_w1)*/ - CANx->RF1R = CAN_RF1R_FULL1; - break; - case CAN_IT_FOV1: - /* Clear CAN_RF1R_FOVR1 (rc_w1)*/ - CANx->RF1R = CAN_RF1R_FOVR1; - break; - case CAN_IT_WKU: - /* Clear CAN_MSR_WKUI (rc_w1)*/ - CANx->MSR = CAN_MSR_WKUI; - break; - case CAN_IT_SLK: - /* Clear CAN_MSR_SLAKI (rc_w1)*/ - CANx->MSR = CAN_MSR_SLAKI; - break; - case CAN_IT_EWG: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ - break; - case CAN_IT_EPV: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ - break; - case CAN_IT_BOF: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ - break; - case CAN_IT_LEC: - /* Clear LEC bits */ - CANx->ESR = RESET; - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - break; - case CAN_IT_ERR: - /*Clear LEC bits */ - CANx->ESR = RESET; - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note BOFF, EPVF and EWGF Flags are cleared by hardware depending on the CAN Bus status*/ - break; - default: - break; - } -} - /** - * @} - */ - -/** - * @brief Checks whether the CAN interrupt has occurred or not. - * @param CAN_Reg: specifies the CAN interrupt register to check. - * @param It_Bit: specifies the interrupt source bit to check. - * @retval The new state of the CAN Interrupt (SET or RESET). - */ -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) -{ - ITStatus pendingbitstatus = RESET; - - if ((CAN_Reg & It_Bit) != (uint32_t)RESET) - { - /* CAN_IT is set */ - pendingbitstatus = SET; - } - else - { - /* CAN_IT is reset */ - pendingbitstatus = RESET; - } - return pendingbitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_can.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,653 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_can.h - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file contains all the functions prototypes for the CAN firmware - * library. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F30x_CAN_H -#define __STM32F30x_CAN_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CAN - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1)) - -/** - * @brief CAN init structure definition - */ -typedef struct -{ - uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. - It ranges from 1 to 1024. */ - - uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. - This parameter can be a value of @ref CAN_operating_mode */ - - uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta - the CAN hardware is allowed to lengthen or - shorten a bit to perform resynchronization. - This parameter can be a value of @ref CAN_synchronisation_jump_width */ - - uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit - Segment 1. This parameter can be a value of - @ref CAN_time_quantum_in_bit_segment_1 */ - - uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ - - FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_NART; /*!< Enable or disable the non-automatic retransmission mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. - This parameter can be set either to ENABLE or DISABLE. */ -} CAN_InitTypeDef; - -/** - * @brief CAN filter init structure definition - */ -typedef struct -{ - uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit - configuration, first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit - configuration, second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, - according to the mode (MSBs for a 32-bit configuration, - first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, - according to the mode (LSBs for a 32-bit configuration, - second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. - This parameter can be a value of @ref CAN_filter_FIFO */ - - uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ - - uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. - This parameter can be a value of @ref CAN_filter_mode */ - - uint8_t CAN_FilterScale; /*!< Specifies the filter scale. - This parameter can be a value of @ref CAN_filter_scale */ - - FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. - This parameter can be set either to ENABLE or DISABLE. */ -} CAN_FilterInitTypeDef; - -/** - * @brief CAN Tx message structure definition - */ -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /*!< Specifies the type of identifier for the message that - will be transmitted. This parameter can be a value - of @ref CAN_identifier_type */ - - uint8_t RTR; /*!< Specifies the type of frame for the message that will - be transmitted. This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /*!< Specifies the length of the frame that will be - transmitted. This parameter can be a value between - 0 to 8 */ - - uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 - to 0xFF. */ -} CanTxMsg; - -/** - * @brief CAN Rx message structure definition - */ -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /*!< Specifies the type of identifier for the message that - will be received. This parameter can be a value of - @ref CAN_identifier_type */ - - uint8_t RTR; /*!< Specifies the type of frame for the received message. - This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /*!< Specifies the length of the frame that will be received. - This parameter can be a value between 0 to 8 */ - - uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to - 0xFF. */ - - uint8_t FMI; /*!< Specifies the index of the filter the message stored in - the mailbox passes through. This parameter can be a - value between 0 to 0xFF */ -} CanRxMsg; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CAN_Exported_Constants - * @{ - */ - -/** @defgroup CAN_InitStatus - * @{ - */ - -#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ -#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */ - - -/* Legacy defines */ -#define CANINITFAILED CAN_InitStatus_Failed -#define CANINITOK CAN_InitStatus_Success -/** - * @} - */ - -/** @defgroup CAN_operating_mode - * @{ - */ - -#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ -#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ -#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ -#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ - -#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \ - ((MODE) == CAN_Mode_LoopBack)|| \ - ((MODE) == CAN_Mode_Silent) || \ - ((MODE) == CAN_Mode_Silent_LoopBack)) -/** - * @} - */ - - - /** - * @defgroup CAN_operating_mode - * @{ - */ -#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */ -#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */ -#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */ - - -#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\ - ((MODE) == CAN_OperatingMode_Normal)|| \ - ((MODE) == CAN_OperatingMode_Sleep)) -/** - * @} - */ - -/** - * @defgroup CAN_operating_mode_status - * @{ - */ - -#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ -#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */ -/** - * @} - */ - -/** @defgroup CAN_synchronisation_jump_width - * @{ - */ -#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ - -#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ - ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_1 - * @{ - */ -#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ -#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ -#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ -#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ -#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ -#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ -#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ -#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ -#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ -#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ -#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ -#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ -#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ - -#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_2 - * @{ - */ -#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ -#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ -#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ -#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ -#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ - -#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) -/** - * @} - */ - -/** @defgroup CAN_clock_prescaler - * @{ - */ -#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) -/** - * @} - */ - -/** @defgroup CAN_filter_number - * @{ - */ -#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) -/** - * @} - */ - -/** @defgroup CAN_filter_mode - * @{ - */ -#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */ -#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ - -#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ - ((MODE) == CAN_FilterMode_IdList)) -/** - * @} - */ - -/** @defgroup CAN_filter_scale - * @{ - */ -#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ -#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ - -#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ - ((SCALE) == CAN_FilterScale_32bit)) -/** - * @} - */ - -/** @defgroup CAN_filter_FIFO - * @{ - */ -#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ -#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ -#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ - ((FIFO) == CAN_FilterFIFO1)) - -/* Legacy defines */ -#define CAN_FilterFIFO0 CAN_Filter_FIFO0 -#define CAN_FilterFIFO1 CAN_Filter_FIFO1 -/** - * @} - */ - -/** @defgroup CAN_Start_bank_filter_for_slave_CAN - * @{ - */ -#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) -/** - * @} - */ - -/** @defgroup CAN_Tx - * @{ - */ -#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) -#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) -#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) -#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) -/** - * @} - */ - -/** @defgroup CAN_identifier_type - * @{ - */ -#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */ -#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */ -#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \ - ((IDTYPE) == CAN_Id_Extended)) - -/* Legacy defines */ -#define CAN_ID_STD CAN_Id_Standard -#define CAN_ID_EXT CAN_Id_Extended -/** - * @} - */ - -/** @defgroup CAN_remote_transmission_request - * @{ - */ -#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */ -#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */ -#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote)) - -/* Legacy defines */ -#define CAN_RTR_DATA CAN_RTR_Data -#define CAN_RTR_REMOTE CAN_RTR_Remote -/** - * @} - */ - -/** @defgroup CAN_transmit_constants - * @{ - */ -#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */ -#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ -#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ -#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide - an empty mailbox */ -/* Legacy defines */ -#define CANTXFAILED CAN_TxStatus_Failed -#define CANTXOK CAN_TxStatus_Ok -#define CANTXPENDING CAN_TxStatus_Pending -#define CAN_NO_MB CAN_TxStatus_NoMailBox -/** - * @} - */ - -/** @defgroup CAN_receive_FIFO_number_constants - * @{ - */ -#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ -#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ - -#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) -/** - * @} - */ - -/** @defgroup CAN_sleep_constants - * @{ - */ -#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ -#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ - -/* Legacy defines */ -#define CANSLEEPFAILED CAN_Sleep_Failed -#define CANSLEEPOK CAN_Sleep_Ok -/** - * @} - */ - -/** @defgroup CAN_wake_up_constants - * @{ - */ -#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ -#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ - -/* Legacy defines */ -#define CANWAKEUPFAILED CAN_WakeUp_Failed -#define CANWAKEUPOK CAN_WakeUp_Ok -/** - * @} - */ - -/** - * @defgroup CAN_Error_Code_constants - * @{ - */ -#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */ -#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ -#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */ -#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ -#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ -#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ -#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ -#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */ -/** - * @} - */ - -/** @defgroup CAN_flags - * @{ - */ -/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() - and CAN_ClearFlag() functions. */ -/* If the flag is 0x1XXXXXXX, it means that it can only be used with - CAN_GetFlagStatus() function. */ - -/* Transmit Flags */ -#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ -#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ -#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ - -/* Receive Flags */ -#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */ -#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */ -#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */ -#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */ -#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */ -#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */ - -/* Operating Mode Flags */ -#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ -#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ -/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. - In this case the SLAK bit can be polled.*/ - -/* Error Flags */ -#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */ -#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */ -#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ -#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ - -#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \ - ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \ - ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \ - ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \ - ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \ - ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \ - ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \ - ((FLAG) == CAN_FLAG_SLAK )) - -#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \ - ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \ - ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\ - ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \ - ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK)) -/** - * @} - */ - - -/** @defgroup CAN_interrupts - * @{ - */ -#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ - -/* Receive Interrupts */ -#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/ -#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/ -#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/ -#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/ -#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/ -#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/ - -/* Operating Mode Interrupts */ -#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ -#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ - -/* Error Interrupts */ -#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ -#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ -#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ -#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ -#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ - -/* Flags named as Interrupts : kept only for FW compatibility */ -#define CAN_IT_RQCP0 CAN_IT_TME -#define CAN_IT_RQCP1 CAN_IT_TME -#define CAN_IT_RQCP2 CAN_IT_TME - - -#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ - ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ - ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) - -#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ - ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the CAN configuration to the default reset state *****/ -void CAN_DeInit(CAN_TypeDef* CANx); - -/* Initialization and Configuration functions *********************************/ -uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); -void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); -void CAN_SlaveStartBank(uint8_t CAN_BankNumber); -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); -void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); - -/* CAN Frames Transmission functions ******************************************/ -uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); -uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); -void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); - -/* CAN Frames Reception functions *********************************************/ -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); -void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); -uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); - -/* Operation modes functions **************************************************/ -uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); -uint8_t CAN_Sleep(CAN_TypeDef* CANx); -uint8_t CAN_WakeUp(CAN_TypeDef* CANx); - -/* CAN Bus Error management functions *****************************************/ -uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); -uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); - -/* Interrupts and flags management functions **********************************/ -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); -void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); -ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); -void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F30x_CAN_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_comp.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,514 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_comp.c - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the 7 analog comparators (COMP1, COMP2...COMP7) peripheral: - * + Comparators configuration - * + Window mode control - * - @verbatim - - ============================================================================== - ##### COMP Peripheral features ##### - ============================================================================== - [..] - The device integrates 7 analog comparators COMP1, COMP2...COMP7: - (#) The non inverting input and inverting input can be set to GPIO pins - as shown in table1. COMP Inputs below. - - (#) The COMP output is internally is available using COMP_GetOutputLevel() - and can be set on GPIO pins. Refer to table 2. COMP Outputs below. - - (#) The COMP output can be redirected to embedded timers (TIM1, TIM2, TIM3...) - Refer to table 3. COMP Outputs redirection to embedded timers below. - - (#) The comparators COMP1 and COMP2, COMP3 and COMP4, COMP5 and COMP6 can be combined in window - mode and only COMP1, COMP3 and COMP5 non inverting input can be used as non-inverting input. - - (#) The seven comparators have interrupt capability with wake-up - from Sleep and Stop modes (through the EXTI controller): - (++) COMP1 is internally connected to EXTI Line 21 - (++) COMP2 is internally connected to EXTI Line 22 - (++) COMP3 is internally connected to EXTI Line 29 - (++) COMP4 is internally connected to EXTI Line 30 - (++) COMP5 is internally connected to EXTI Line 31 - (++) COMP6 is internally connected to EXTI Line 32 - (++) COMP7 is internally connected to EXTI Line 33 - - [..] Table 1. COMP Inputs - +------------------------------------------------------------------------------------------+ - | | | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 | - |-----------------|----------------|---------------|---------------------------------------| - | | 1/4 VREFINT | OK | OK | OK | OK | OK | OK | OK | - | | 1/2 VREFINT | OK | OK | OK | OK | OK | OK | OK | - | | 3/4 VREFINT | OK | OK | OK | OK | OK | OK | OK | - | Inverting Input | VREFINT | OK | OK | OK | OK | OK | OK | OK | - | | DAC1 OUT1(PA4) | OK | OK | OK | OK | OK | OK | OK | - | | DAC1 OUT2(PA5) | OK | OK | OK | OK | OK | OK | OK | - | | IO1 | PA0 | PA2 | PD15 | PE8 | PD13 | PD10 | PC0 | - | | IO2 | --- | --- | PB12 | PB2 | PB10 | PB15 | --- | - | | DAC2 OUT1(PA6) | --- | OK | --- | OK | --- | OK | --- | - |-----------------|----------------|-------|-------|-------|-------|-------|-------|-------| - | Non Inverting | IO1 | PA1 | PA7 | PB14 | PB0 | PD12 | PD11 | PA0 | - | Input | IO2 | --- | PA3 | PD14 | PE7 | PB13 | PB11 | PC1 | - +------------------------------------------------------------------------------------------+ - - [..] Table 2. COMP Outputs - +-------------------------------------------------------+ - | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 | - |-------|-------|-------|-------|-------|-------|-------| - | PA0 | PA2 | PB1 | PC8 | PC7 | PA10 | PC2 | - | PF4 | PA7 | --- | PA8 | PA9 | PC6 | --- | - | PA6 | PA12 | --- | --- | --- | --- | --- | - | PA11 | PB9 | --- | --- | --- | --- | --- | - | PB8 | --- | --- | --- | --- | --- | --- | - +-------------------------------------------------------+ - - [..] Table 3. COMP Outputs redirection to embedded timers - +----------------------------------------------------------------------------------------------------------------------+ - | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 | - |----------------|----------------|----------------|----------------|----------------|----------------|----------------| - | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | - | | | | | | | | - | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | - | | | | | | | | - | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | - | | | | | | | | - | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | - | | | | | | | | - | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | - | + | + | + | + | + | + | + | - | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | - | | | | | | | | - | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM1 OCREFCLR | - | | | | | | | | - | TIM1 IC1 | TIM1 IC1 | TIM2 OCREFCLR | TIM3 IC3 | TIM2 IC1 | TIM2 IC2 | TIM8 OCREFCLR | - | | | | | | | | - | TIM2 IC4 | TIM2 IC4 | TIM3 IC2 | TIM3 OCREFCLR | TIM3 OCREFCLR | TIM2 OCREFCLR | TIM2 IC3 | - | | | | | | | | - | TIM2 OCREFCLR | TIM2 OCREFCLR | TIM4 IC1 | TIM4 IC2 | TIM4 IC3 | TIM16 OCREFCLR| TIM1 IC2 | - | | | | | | | | - | TIM3 IC1 | TIM3 IC1 | TIM15 IC1 | TIM15 OCREFCLR| TIM16 BKIN | TIM16 IC1 | TIM17 OCREFCLR| - | | | | | | | | - | TIM3 OCREFCLR | TIM3 OCREFCLR | TIM15 BKIN | TIM15 IC2 | TIM17 IC1 | TIM4 IC4 | TIM17 BKIN | - +----------------------------------------------------------------------------------------------------------------------+ - - [..] Table 4. COMP Outputs blanking sources - +----------------------------------------------------------------------------------------------------------------------+ - | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 | - |----------------|----------------|----------------|----------------|----------------|----------------|----------------| - | TIM1 OC5 | TIM1 OC5 | TIM1 OC5 | TIM3 OC4 | TIM3 OC3 | TIM2 OC4 | TIM1 OC5 | - | | | | | | | | - | TIM2 OC3 | TIM2 OC3 | -------- | TIM8 OC5 | TIM8 OC5 | TIM8 OC5 | TIM8 OC5 | - | | | | | | | | - | TIM3 OC3 | TIM3 OC3 | TIM2 OC4 | TIM15 OC1 | TIM8 BKIN | TIM15 OC2 | TIM15 OC2 | - | | | | | | | | - +----------------------------------------------------------------------------------------------------------------------+ - - - ##### How to use this driver ##### - ============================================================================== - [..] - This driver provides functions to configure and program the Comparators - of all STM32F30x devices. - - To use the comparator, perform the following steps: - - (#) Enable the SYSCFG APB clock to get write access to comparator - register using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - - (#) Configure the comparator input in analog mode using GPIO_Init() - - (#) Configure the comparator output in alternate function mode - using GPIO_Init() and use GPIO_PinAFConfig() function to map the - comparator output to the GPIO pin - - (#) Configure the comparator using COMP_Init() function: - (++) Select the inverting input - (++) Select the non-inverting input - (++) Select the output polarity - (++) Select the output redirection - (++) Select the hysteresis level - (++) Select the power mode - - (#) Enable the comparator using COMP_Cmd() function - - (#) If required enable the COMP interrupt by configuring and enabling - EXTI line in Interrupt mode and selecting the desired sensitivity - level using EXTI_Init() function. After that enable the comparator - interrupt vector using NVIC_Init() function. - - @endverbatim - * - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x_comp.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @defgroup COMP - * @brief COMP driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* CSR register Mask */ -#define COMP_CSR_CLEAR_MASK ((uint32_t)0x00000003) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup COMP_Private_Functions - * @{ - */ - -/** @defgroup COMP_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes COMP peripheral registers to their default reset values. - * @note Deinitialization can't be performed if the COMP configuration is locked. - * To unlock the configuration, perform a system reset. - * @param COMP_Selection: the selected comparator. - * This parameter can be COMP_Selection_COMPx where x can be 1 to 7 - * to select the COMP peripheral. - * @param None - * @retval None - */ -void COMP_DeInit(uint32_t COMP_Selection) -{ - /*!< Set COMP_CSR register to reset value */ - *(__IO uint32_t *) (COMP_BASE + COMP_Selection) = ((uint32_t)0x00000000); -} - -/** - * @brief Initializes the COMP peripheral according to the specified parameters - * in COMP_InitStruct - * @note If the selected comparator is locked, initialization can't be performed. - * To unlock the configuration, perform a system reset. - * @note By default, PA1 is selected as COMP1 non inverting input. - * To use PA4 as COMP1 non inverting input call COMP_SwitchCmd() after COMP_Init() - * @param COMP_Selection: the selected comparator. - * This parameter can be COMP_Selection_COMPx where x can be 1 to 7 - * to select the COMP peripheral. - * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains - * the configuration information for the specified COMP peripheral. - * - COMP_InvertingInput specifies the inverting input of COMP - * - COMP_NonInvertingInput specifies the non inverting input of COMP - * - COMP_Output connect COMP output to selected timer - * input (Input capture / Output Compare Reference Clear / Break Input) - * - COMP_BlankingSrce specifies the blanking source of COMP - * - COMP_OutputPol select output polarity - * - COMP_Hysteresis configures COMP hysteresis value - * - COMP_Mode configures COMP power mode - * @retval None - */ -void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_COMP_ALL_PERIPH(COMP_Selection)); - assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput)); - assert_param(IS_COMP_NONINVERTING_INPUT(COMP_InitStruct->COMP_NonInvertingInput)); - assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_Output)); - assert_param(IS_COMP_BLANKING_SOURCE(COMP_InitStruct->COMP_BlankingSrce)); - assert_param(IS_COMP_OUTPUT_POL(COMP_InitStruct->COMP_OutputPol)); - assert_param(IS_COMP_HYSTERESIS(COMP_InitStruct->COMP_Hysteresis)); - assert_param(IS_COMP_MODE(COMP_InitStruct->COMP_Mode)); - - /*!< Get the COMPx_CSR register value */ - tmpreg = *(__IO uint32_t *) (COMP_BASE + COMP_Selection); - - /*!< Clear the COMP1SW1, COMPxINSEL, COMPxOUTSEL, COMPxPOL, COMPxHYST and COMPxMODE bits */ - tmpreg &= (uint32_t) (COMP_CSR_CLEAR_MASK); - - /*!< Configure COMP: inverting input, output redirection, hysteresis value and power mode */ - /*!< Set COMPxINSEL bits according to COMP_InitStruct->COMP_InvertingInput value */ - /*!< Set COMPxNONINSEL bits according to COMP_InitStruct->COMP_NonInvertingInput value */ - /*!< Set COMPxBLANKING bits according to COMP_InitStruct->COMP_BlankingSrce value */ - /*!< Set COMPxOUTSEL bits according to COMP_InitStruct->COMP_Output value */ - /*!< Set COMPxPOL bit according to COMP_InitStruct->COMP_OutputPol value */ - /*!< Set COMPxHYST bits according to COMP_InitStruct->COMP_Hysteresis value */ - /*!< Set COMPxMODE bits according to COMP_InitStruct->COMP_Mode value */ - tmpreg |= (uint32_t)(COMP_InitStruct->COMP_InvertingInput | COMP_InitStruct->COMP_NonInvertingInput | - COMP_InitStruct->COMP_Output | COMP_InitStruct->COMP_OutputPol | COMP_InitStruct->COMP_BlankingSrce | - COMP_InitStruct->COMP_Hysteresis | COMP_InitStruct->COMP_Mode); - - /*!< Write to COMPx_CSR register */ - *(__IO uint32_t *) (COMP_BASE + COMP_Selection) = tmpreg; -} - -/** - * @brief Fills each COMP_InitStruct member with its default value. - * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct) -{ - COMP_InitStruct->COMP_InvertingInput = COMP_InvertingInput_1_4VREFINT; - COMP_InitStruct->COMP_NonInvertingInput = COMP_NonInvertingInput_IO1; - COMP_InitStruct->COMP_Output = COMP_Output_None; - COMP_InitStruct->COMP_BlankingSrce = COMP_BlankingSrce_None; - COMP_InitStruct->COMP_OutputPol = COMP_OutputPol_NonInverted; - COMP_InitStruct->COMP_Hysteresis = COMP_Hysteresis_No; - COMP_InitStruct->COMP_Mode = COMP_Mode_UltraLowPower; -} - -/** - * @brief Enable or disable the COMP peripheral. - * @note If the selected comparator is locked, enable/disable can't be performed. - * To unlock the configuration, perform a system reset. - * @param COMP_Selection: the selected comparator. - * This parameter can be COMP_Selection_COMPx where x can be 1 to 7 - * to select the COMP peripheral. - * @param NewState: new state of the COMP peripheral. - * This parameter can be: ENABLE or DISABLE. - * When enabled, the comparator compares the non inverting input with - * the inverting input and the comparison result is available - * on comparator output. - * When disabled, the comparator doesn't perform comparison and the - * output level is low. - * @retval None - */ -void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_COMP_ALL_PERIPH(COMP_Selection)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected COMPx peripheral */ - *(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) (COMP_CSR_COMPxEN); - } - else - { - /* Disable the selected COMP peripheral */ - *(__IO uint32_t *) (COMP_BASE + COMP_Selection) &= (uint32_t)(~COMP_CSR_COMPxEN); - } -} - -/** - * @brief Close or Open the SW1 switch. - * @note If the COMP1 is locked, Close/Open the SW1 switch can't be performed. - * To unlock the configuration, perform a system reset. - * @note This switch is solely intended to redirect signals onto high - * impedance input, such as COMP1 non-inverting input (highly resistive switch) - * @param NewState: New state of the analog switch. - * This parameter can be - * ENABLE so the SW1 is closed; PA1 is connected to PA4 - * or DISABLE so the SW1 switch is open; PA1 is disconnected from PA4 - * @retval None - */ -void COMP_SwitchCmd(uint32_t COMP_Selection, FunctionalState NewState) -{ - /* Check the parameter */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Close SW1 switch */ - *(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) (COMP_CSR_COMP1SW1); - } - else - { - /* Open SW1 switch */ - *(__IO uint32_t *) (COMP_BASE + COMP_Selection) &= (uint32_t)(~COMP_CSR_COMP1SW1); - } -} - -/** - * @brief Return the output level (high or low) of the selected comparator. - * The output level depends on the selected polarity. - * If the polarity is not inverted: - * - Comparator output is low when the non-inverting input is at a lower - * voltage than the inverting input - * - Comparator output is high when the non-inverting input is at a higher - * voltage than the inverting input - * If the polarity is inverted: - * - Comparator output is high when the non-inverting input is at a lower - * voltage than the inverting input - * - Comparator output is low when the non-inverting input is at a higher - * voltage than the inverting input - * @param COMP_Selection: the selected comparator. - * This parameter can be COMP_Selection_COMPx where x can be 1 to 7 - * to select the COMP peripheral. - * @retval Returns the selected comparator output level: low or high. - * - */ -uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection) -{ - uint32_t compout = 0x0; - - /* Check the parameters */ - assert_param(IS_COMP_ALL_PERIPH(COMP_Selection)); - - /* Check if selected comparator output is high */ - if ((*(__IO uint32_t *) (COMP_BASE + COMP_Selection) & (COMP_CSR_COMPxOUT)) != 0) - { - compout = COMP_OutputLevel_High; - } - else - { - compout = COMP_OutputLevel_Low; - } - - /* Return the comparator output level */ - return (uint32_t)(compout); -} - -/** - * @} - */ - -/** @defgroup COMP_Group2 Window mode control function - * @brief Window mode control function - * -@verbatim - =============================================================================== - ##### Window mode control function ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the window mode. - * Window mode for comparators makes use of two comparators: - * COMP1 and COM2, COMP3 and COMP4, COMP5 and COMP6. - * In window mode, COMPx and COMPx-1 (where x can be 2, 4 or 6) - * non inverting inputs are connected together and only COMPx-1 non - * inverting input can be used. - * e.g When window mode enabled for COMP4, COMP3 non inverting input (PB14 or PD14) - * is to be used. - * @note If the COMPx is locked, ENABLE/DISABLE the window mode can't be performed. - * To unlock the configuration, perform a system reset. - * @param COMP_Selection: the selected comparator. - * This parameter can be COMP_Selection_COMPx where x can be 2, 4 or 6 - * to select the COMP peripheral. - * param NewState: new state of the window mode. - * This parameter can be ENABLE or DISABLE. - * When enbaled, COMPx and COMPx-1 non inverting inputs are connected together. - * When disabled, COMPx and COMPx-1 non inverting inputs are disconnected. - * @retval None - */ -void COMP_WindowCmd(uint32_t COMP_Selection, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_COMP_WINDOW(COMP_Selection)); - - if (NewState != DISABLE) - { - /* Enable the window mode */ - *(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) COMP_CSR_COMPxWNDWEN; - } - else - { - /* Disable the window mode */ - *(__IO uint32_t *) (COMP_BASE + COMP_Selection) &= (uint32_t)(~COMP_CSR_COMPxWNDWEN); - } -} - -/** - * @} - */ - -/** @defgroup COMP_Group3 COMP configuration locking function - * @brief COMP1, COMP2,...COMP7 configuration locking function - * COMP1, COMP2,...COMP7 configuration can be locked each separately. - * Unlocking is performed by system reset. - * -@verbatim - =============================================================================== - ##### Configuration Lock function ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Lock the selected comparator (COMP1/COMP2) configuration. - * @note Locking the configuration means that all control bits are read-only. - * To unlock the comparator configuration, perform a system reset. - * @param COMP_Selection: the selected comparator. - * This parameter can be COMP_Selection_COMPx where x can be 1 to 7 - * to select the COMP peripheral. - * @retval None - */ -void COMP_LockConfig(uint32_t COMP_Selection) -{ - /* Check the parameter */ - assert_param(IS_COMP_ALL_PERIPH(COMP_Selection)); - - /* Set the lock bit corresponding to selected comparator */ - *(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) (COMP_CSR_COMPxLOCK); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_comp.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,436 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_comp.h - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file contains all the functions prototypes for the COMP firmware - * library. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F30x_COMP_H -#define __STM32F30x_COMP_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup COMP - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief COMP Init structure definition - */ - -typedef struct -{ - - uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator. - This parameter can be a value of @ref COMP_InvertingInput */ - - uint32_t COMP_NonInvertingInput; /*!< Selects the non inverting input of the comparator. - This parameter can be a value of @ref COMP_NonInvertingInput */ - - uint32_t COMP_Output; /*!< Selects the output redirection of the comparator. - This parameter can be a value of @ref COMP_Output */ - - uint32_t COMP_BlankingSrce; /*!< Selects the output blanking source of the comparator. - This parameter can be a value of @ref COMP_BlankingSrce */ - - uint32_t COMP_OutputPol; /*!< Selects the output polarity of the comparator. - This parameter can be a value of @ref COMP_OutputPoloarity */ - - uint32_t COMP_Hysteresis; /*!< Selects the hysteresis voltage of the comparator. - This parameter can be a value of @ref COMP_Hysteresis */ - - uint32_t COMP_Mode; /*!< Selects the operating mode of the comparator - and allows to adjust the speed/consumption. - This parameter can be a value of @ref COMP_Mode */ -}COMP_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup COMP_Exported_Constants - * @{ - */ - -/** @defgroup COMP_Selection - * @{ - */ - -#define COMP_Selection_COMP1 ((uint32_t)0x00000000) /*!< COMP1 Selection */ -#define COMP_Selection_COMP2 ((uint32_t)0x00000004) /*!< COMP2 Selection */ -#define COMP_Selection_COMP3 ((uint32_t)0x00000008) /*!< COMP3 Selection */ -#define COMP_Selection_COMP4 ((uint32_t)0x0000000C) /*!< COMP4 Selection */ -#define COMP_Selection_COMP5 ((uint32_t)0x00000010) /*!< COMP5 Selection */ -#define COMP_Selection_COMP6 ((uint32_t)0x00000014) /*!< COMP6 Selection */ -#define COMP_Selection_COMP7 ((uint32_t)0x00000018) /*!< COMP7 Selection */ - -#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \ - ((PERIPH) == COMP_Selection_COMP2) || \ - ((PERIPH) == COMP_Selection_COMP3) || \ - ((PERIPH) == COMP_Selection_COMP4) || \ - ((PERIPH) == COMP_Selection_COMP5) || \ - ((PERIPH) == COMP_Selection_COMP6) || \ - ((PERIPH) == COMP_Selection_COMP7)) - -/** - * @} - */ - -/** @defgroup COMP_InvertingInput - * @{ - */ - -#define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */ -#define COMP_InvertingInput_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */ -#define COMP_InvertingInput_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */ -#define COMP_InvertingInput_VREFINT ((uint32_t)0x00000030) /*!< VREFINT connected to comparator inverting input */ -#define COMP_InvertingInput_DAC1OUT1 COMP_CSR_COMPxINSEL_2 /*!< DAC1_OUT1 (PA4) connected to comparator inverting input */ -#define COMP_InvertingInput_DAC1OUT2 ((uint32_t)0x00000050) /*!< DAC1_OUT2 (PA5) connected to comparator inverting input */ - -#define COMP_InvertingInput_IO1 ((uint32_t)0x00000060) /*!< I/O1 (PA0 for COMP1, PA2 for COMP2, PD15 for COMP3, - PE8 for COMP4, PD13 for COMP5, PD10 for COMP6, - PC0 for COMP7) connected to comparator inverting input */ - -#define COMP_InvertingInput_IO2 COMP_CSR_COMPxINSEL /*!< I/O2 (PB12 for COMP3, PB2 for COMP4, PB10 for COMP5, - PB15 for COMP6) connected to comparator inverting input */ - -#define COMP_InvertingInput_DAC2OUT1 COMP_CSR_COMPxINSEL_3 /*!< DAC2_OUT1 (PA6) connected to comparator inverting input */ - -#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_1_4VREFINT) || \ - ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \ - ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \ - ((INPUT) == COMP_InvertingInput_VREFINT) || \ - ((INPUT) == COMP_InvertingInput_DAC1OUT1) || \ - ((INPUT) == COMP_InvertingInput_DAC1OUT2) || \ - ((INPUT) == COMP_InvertingInput_IO1) || \ - ((INPUT) == COMP_InvertingInput_IO2) || \ - ((INPUT) == COMP_InvertingInput_DAC2OUT1)) -/** - * @} - */ - -/** @defgroup COMP_NonInvertingInput - * @{ - */ - -#define COMP_NonInvertingInput_IO1 ((uint32_t)0x00000000) /*!< I/O1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3, - PB0 for COMP4, PD12 for COMP5, PD11 for COMP6, - PA0 for COMP7) connected to comparator non inverting input */ - -#define COMP_NonInvertingInput_IO2 COMP_CSR_COMPxNONINSEL /*!< I/O2 (PA3 for COMP2, PD14 for COMP3, PE7 for COMP4, PB13 for COMP5, - PB11 for COMP6, PC1 for COMP7) connected to comparator non inverting input */ - -#define IS_COMP_NONINVERTING_INPUT(INPUT) (((INPUT) == COMP_NonInvertingInput_IO1) || \ - ((INPUT) == COMP_NonInvertingInput_IO2)) -/** - * @} - */ - -/** @defgroup COMP_Output - * @{ - */ - -#define COMP_Output_None ((uint32_t)0x00000000) /*!< COMP output isn't connected to other peripherals */ - -/* Output Redirection common for all comparators COMP1...COMP7 */ -#define COMP_Output_TIM1BKIN COMP_CSR_COMPxOUTSEL_0 /*!< COMP output connected to TIM1 Break Input (BKIN) */ -#define COMP_Output_TIM1BKIN2 ((uint32_t)0x00000800) /*!< COMP output connected to TIM1 Break Input 2 (BKIN2) */ -#define COMP_Output_TIM8BKIN ((uint32_t)0x00000C00) /*!< COMP output connected to TIM8 Break Input (BKIN) */ -#define COMP_Output_TIM8BKIN2 ((uint32_t)0x00001000) /*!< COMP output connected to TIM8 Break Input 2 (BKIN2) */ -#define COMP_Output_TIM1BKIN2_TIM8BKIN2 ((uint32_t)0x00001400) /*!< COMP output connected to TIM1 Break Input 2 and TIM8 Break Input 2 */ - -/* Output Redirection common for COMP1 and COMP2 */ -#define COMP_Output_TIM1OCREFCLR ((uint32_t)0x00001800) /*!< COMP output connected to TIM1 OCREF Clear */ -#define COMP_Output_TIM1IC1 ((uint32_t)0x00001C00) /*!< COMP output connected to TIM1 Input Capture 1 */ -#define COMP_Output_TIM2IC4 ((uint32_t)0x00002000) /*!< COMP output connected to TIM2 Input Capture 4 */ -#define COMP_Output_TIM2OCREFCLR ((uint32_t)0x00002400) /*!< COMP output connected to TIM2 OCREF Clear */ -#define COMP_Output_TIM3IC1 ((uint32_t)0x00002800) /*!< COMP output connected to TIM3 Input Capture 1 */ -#define COMP_Output_TIM3OCREFCLR ((uint32_t)0x00002C00) /*!< COMP output connected to TIM3 OCREF Clear */ - -/* Output Redirection specific to COMP2 */ -#define COMP_Output_HRTIM1_FLT6 ((uint32_t)0x00003000) /*!< COMP output connected to HRTIM1 FLT6 */ -#define COMP_Output_HRTIM1_EE1_2 ((uint32_t)0x00003400) /*!< COMP output connected to HRTIM1 EE1_2*/ -#define COMP_Output_HRTIM1_EE6_2 ((uint32_t)0x00003800) /*!< COMP output connected to HRTIM1 EE6_2 */ - -/* Output Redirection specific to COMP3 */ -#define COMP_Output_TIM4IC1 ((uint32_t)0x00001C00) /*!< COMP output connected to TIM4 Input Capture 1 */ -#define COMP_Output_TIM3IC2 ((uint32_t)0x00002000) /*!< COMP output connected to TIM3 Input Capture 2 */ -#define COMP_Output_TIM15IC1 ((uint32_t)0x00002800) /*!< COMP output connected to TIM15 Input Capture 1 */ -#define COMP_Output_TIM15BKIN ((uint32_t)0x00002C00) /*!< COMP output connected to TIM15 Break Input (BKIN) */ - -/* Output Redirection specific to COMP4 */ -#define COMP_Output_TIM3IC3 ((uint32_t)0x00001800) /*!< COMP output connected to TIM3 Input Capture 3 */ -#define COMP_Output_TIM8OCREFCLR ((uint32_t)0x00001C00) /*!< COMP output connected to TIM8 OCREF Clear */ -#define COMP_Output_TIM15IC2 ((uint32_t)0x00002000) /*!< COMP output connected to TIM15 Input Capture 2 */ -#define COMP_Output_TIM4IC2 ((uint32_t)0x00002400) /*!< COMP output connected to TIM4 Input Capture 2 */ -#define COMP_Output_TIM15OCREFCLR ((uint32_t)0x00002800) /*!< COMP output connected to TIM15 OCREF Clear */ - -#define COMP_Output_HRTIM1_FLT7 ((uint32_t)0x00003000) /*!< COMP output connected to HRTIM1 FLT7 */ -#define COMP_Output_HRTIM1_EE2_2 ((uint32_t)0x00003400) /*!< COMP output connected to HRTIM1 EE2_2*/ -#define COMP_Output_HRTIM1_EE7_2 ((uint32_t)0x00003800) /*!< COMP output connected to HRTIM1 EE7_2 */ - -/* Output Redirection specific to COMP5 */ -#define COMP_Output_TIM2IC1 ((uint32_t)0x00001800) /*!< COMP output connected to TIM2 Input Capture 1 */ -#define COMP_Output_TIM17IC1 ((uint32_t)0x00002000) /*!< COMP output connected to TIM17 Input Capture 1 */ -#define COMP_Output_TIM4IC3 ((uint32_t)0x00002400) /*!< COMP output connected to TIM4 Input Capture 3 */ -#define COMP_Output_TIM16BKIN ((uint32_t)0x00002800) /*!< COMP output connected to TIM16 Break Input (BKIN) */ - -/* Output Redirection specific to COMP6 */ -#define COMP_Output_TIM2IC2 ((uint32_t)0x00001800) /*!< COMP output connected to TIM2 Input Capture 2 */ -#define COMP_Output_COMP6TIM2OCREFCLR ((uint32_t)0x00002000) /*!< COMP output connected to TIM2 OCREF Clear */ -#define COMP_Output_TIM16OCREFCLR ((uint32_t)0x00002400) /*!< COMP output connected to TIM16 OCREF Clear */ -#define COMP_Output_TIM16IC1 ((uint32_t)0x00002800) /*!< COMP output connected to TIM16 Input Capture 1 */ -#define COMP_Output_TIM4IC4 ((uint32_t)0x00002C00) /*!< COMP output connected to TIM4 Input Capture 4 */ - -#define COMP_Output_HRTIM1_FLT8 ((uint32_t)0x00003000) /*!< COMP output connected to HRTIM1 FLT8 */ -#define COMP_Output_HRTIM1_EE3_2 ((uint32_t)0x00003400) /*!< COMP output connected to HRTIM1 EE3_2*/ -#define COMP_Output_HRTIM1_EE8_2 ((uint32_t)0x00003800) /*!< COMP output connected to HRTIM1 EE8_2 */ - -/* Output Redirection specific to COMP7 */ -#define COMP_Output_TIM2IC3 ((uint32_t)0x00002000) /*!< COMP output connected to TIM2 Input Capture 3 */ -#define COMP_Output_TIM1IC2 ((uint32_t)0x00002400) /*!< COMP output connected to TIM1 Input Capture 2 */ -#define COMP_Output_TIM17OCREFCLR ((uint32_t)0x00002800) /*!< COMP output connected to TIM16 OCREF Clear */ -#define COMP_Output_TIM17BKIN ((uint32_t)0x00002C00) /*!< COMP output connected to TIM16 Break Input (BKIN) */ - -#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_Output_None) || \ - ((OUTPUT) == COMP_Output_TIM1BKIN) || \ - ((OUTPUT) == COMP_Output_TIM1IC1) || \ - ((OUTPUT) == COMP_Output_TIM1OCREFCLR) || \ - ((OUTPUT) == COMP_Output_TIM2IC4) || \ - ((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \ - ((OUTPUT) == COMP_Output_COMP6TIM2OCREFCLR) || \ - ((OUTPUT) == COMP_Output_TIM3IC1) || \ - ((OUTPUT) == COMP_Output_TIM3OCREFCLR) || \ - ((OUTPUT) == COMP_Output_TIM8BKIN) || \ - ((OUTPUT) == COMP_Output_TIM1BKIN2) || \ - ((OUTPUT) == COMP_Output_TIM8BKIN2) || \ - ((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \ - ((OUTPUT) == COMP_Output_TIM1BKIN2_TIM8BKIN2) || \ - ((OUTPUT) == COMP_Output_TIM3IC2) || \ - ((OUTPUT) == COMP_Output_TIM4IC1) || \ - ((OUTPUT) == COMP_Output_TIM15IC1) || \ - ((OUTPUT) == COMP_Output_TIM15BKIN) || \ - ((OUTPUT) == COMP_Output_TIM8OCREFCLR) || \ - ((OUTPUT) == COMP_Output_TIM3IC3) || \ - ((OUTPUT) == COMP_Output_TIM4IC1) || \ - ((OUTPUT) == COMP_Output_TIM15IC1) || \ - ((OUTPUT) == COMP_Output_TIM2IC1) || \ - ((OUTPUT) == COMP_Output_TIM4IC3) || \ - ((OUTPUT) == COMP_Output_TIM16BKIN) || \ - ((OUTPUT) == COMP_Output_TIM17IC1) || \ - ((OUTPUT) == COMP_Output_TIM2IC2) || \ - ((OUTPUT) == COMP_Output_TIM16IC1) || \ - ((OUTPUT) == COMP_Output_TIM4IC4) || \ - ((OUTPUT) == COMP_Output_TIM16OCREFCLR) || \ - ((OUTPUT) == COMP_Output_TIM2IC3) || \ - ((OUTPUT) == COMP_Output_TIM1IC2) || \ - ((OUTPUT) == COMP_Output_TIM17BKIN) || \ - ((OUTPUT) == COMP_Output_TIM17OCREFCLR) || \ - ((OUTPUT) == COMP_Output_HRTIM1_FLT6) || \ - ((OUTPUT) == COMP_Output_HRTIM1_EE1_2) || \ - ((OUTPUT) == COMP_Output_HRTIM1_EE6_2) || \ - ((OUTPUT) == COMP_Output_HRTIM1_FLT7) || \ - ((OUTPUT) == COMP_Output_HRTIM1_EE2_2) || \ - ((OUTPUT) == COMP_Output_HRTIM1_EE7_2) || \ - ((OUTPUT) == COMP_Output_HRTIM1_FLT8) || \ - ((OUTPUT) == COMP_Output_HRTIM1_EE3_2) || \ - ((OUTPUT) == COMP_Output_HRTIM1_EE8_2)) - -/** - * @} - */ - -/** @defgroup COMP_BlankingSrce - * @{ - */ - -/* No blanking source can be selected for all comparators */ -#define COMP_BlankingSrce_None ((uint32_t)0x00000000) /*!< No blanking source */ - -/* Blanking source common for COMP1, COMP2, COMP3 and COMP7 */ -#define COMP_BlankingSrce_TIM1OC5 COMP_CSR_COMPxBLANKING_0 /*!< TIM1 OC5 selected as blanking source for compartor */ - -/* Blanking source common for COMP1 and COMP2 */ -#define COMP_BlankingSrce_TIM2OC3 COMP_CSR_COMPxBLANKING_1 /*!< TIM2 OC5 selected as blanking source for compartor */ - -/* Blanking source common for COMP1, COMP2 and COMP5 */ -#define COMP_BlankingSrce_TIM3OC3 ((uint32_t)0x000C0000) /*!< TIM2 OC3 selected as blanking source for compartor */ - -/* Blanking source common for COMP3 and COMP6 */ -#define COMP_BlankingSrce_TIM2OC4 ((uint32_t)0x000C0000) /*!< TIM2 OC4 selected as blanking source for compartor */ - -/* Blanking source common for COMP4, COMP5, COMP6 and COMP7 */ -#define COMP_BlankingSrce_TIM8OC5 COMP_CSR_COMPxBLANKING_1 /*!< TIM8 OC5 selected as blanking source for compartor */ - -/* Blanking source for COMP4 */ -#define COMP_BlankingSrce_TIM3OC4 COMP_CSR_COMPxBLANKING_0 /*!< TIM3 OC4 selected as blanking source for compartor */ -#define COMP_BlankingSrce_TIM15OC1 ((uint32_t)0x000C0000) /*!< TIM15 OC1 selected as blanking source for compartor */ - -/* Blanking source common for COMP6 and COMP7 */ -#define COMP_BlankingSrce_TIM15OC2 COMP_CSR_COMPxBLANKING_2 /*!< TIM15 OC2 selected as blanking source for compartor */ - -#define IS_COMP_BLANKING_SOURCE(SOURCE) (((SOURCE) == COMP_BlankingSrce_None) || \ - ((SOURCE) == COMP_BlankingSrce_TIM1OC5) || \ - ((SOURCE) == COMP_BlankingSrce_TIM2OC3) || \ - ((SOURCE) == COMP_BlankingSrce_TIM3OC3) || \ - ((SOURCE) == COMP_BlankingSrce_TIM2OC4) || \ - ((SOURCE) == COMP_BlankingSrce_TIM8OC5) || \ - ((SOURCE) == COMP_BlankingSrce_TIM3OC4) || \ - ((SOURCE) == COMP_BlankingSrce_TIM15OC1) || \ - ((SOURCE) == COMP_BlankingSrce_TIM15OC2)) -/** - * @} - */ - -/** @defgroup COMP_OutputPoloarity - * @{ - */ -#define COMP_OutputPol_NonInverted ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */ -#define COMP_OutputPol_Inverted COMP_CSR_COMPxPOL /*!< COMP output on GPIO is inverted */ - -#define IS_COMP_OUTPUT_POL(POL) (((POL) == COMP_OutputPol_NonInverted) || \ - ((POL) == COMP_OutputPol_Inverted)) - -/** - * @} - */ - -/** @defgroup COMP_Hysteresis - * @{ - */ -/* Please refer to the electrical characteristics in the device datasheet for - the hysteresis level */ -#define COMP_Hysteresis_No 0x00000000 /*!< No hysteresis */ -#define COMP_Hysteresis_Low COMP_CSR_COMPxHYST_0 /*!< Hysteresis level low */ -#define COMP_Hysteresis_Medium COMP_CSR_COMPxHYST_1 /*!< Hysteresis level medium */ -#define COMP_Hysteresis_High COMP_CSR_COMPxHYST /*!< Hysteresis level high */ - -#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_Hysteresis_No) || \ - ((HYSTERESIS) == COMP_Hysteresis_Low) || \ - ((HYSTERESIS) == COMP_Hysteresis_Medium) || \ - ((HYSTERESIS) == COMP_Hysteresis_High)) -/** - * @} - */ - -/** @defgroup COMP_Mode - * @{ - */ -/* Please refer to the electrical characteristics in the device datasheet for - the power consumption values */ -#define COMP_Mode_HighSpeed 0x00000000 /*!< High Speed */ -#define COMP_Mode_MediumSpeed COMP_CSR_COMPxMODE_0 /*!< Medium Speed */ -#define COMP_Mode_LowPower COMP_CSR_COMPxMODE_1 /*!< Low power mode */ -#define COMP_Mode_UltraLowPower COMP_CSR_COMPxMODE /*!< Ultra-low power mode */ - -#define IS_COMP_MODE(MODE) (((MODE) == COMP_Mode_UltraLowPower) || \ - ((MODE) == COMP_Mode_LowPower) || \ - ((MODE) == COMP_Mode_MediumSpeed) || \ - ((MODE) == COMP_Mode_HighSpeed)) -/** - * @} - */ - -/** @defgroup COMP_OutputLevel - * @{ - */ -/* When output polarity is not inverted, comparator output is high when - the non-inverting input is at a higher voltage than the inverting input */ -#define COMP_OutputLevel_High COMP_CSR_COMPxOUT -/* When output polarity is not inverted, comparator output is low when - the non-inverting input is at a lower voltage than the inverting input*/ -#define COMP_OutputLevel_Low ((uint32_t)0x00000000) - -/** - * @} - */ - -/** @defgroup COMP_WindowMode - * @{ - */ -#define IS_COMP_WINDOW(WINDOW) (((WINDOW) == COMP_Selection_COMP2) || \ - ((WINDOW) == COMP_Selection_COMP4) || \ - ((WINDOW) == COMP_Selection_COMP6)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the COMP configuration to the default reset state ****/ -void COMP_DeInit(uint32_t COMP_Selection); - -/* Initialization and Configuration functions *********************************/ -void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct); -void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct); -void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState); -void COMP_SwitchCmd(uint32_t COMP_Selection, FunctionalState NewState); -uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection); - -/* Window mode control function ***********************************************/ -void COMP_WindowCmd(uint32_t COMP_Selection, FunctionalState NewState); - -/* COMP configuration locking function ****************************************/ -void COMP_LockConfig(uint32_t COMP_Selection); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F30x_COMP_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_conf.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,94 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_conf.h - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief Library configuration file. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F30X_CONF_H -#define __STM32F30X_CONF_H - - -/* Includes ------------------------------------------------------------------*/ -/* Comment the line below to disable peripheral header file inclusion */ -#include "stm32f30x_adc.h" -#include "stm32f30x_can.h" -#include "stm32f30x_crc.h" -#include "stm32f30x_comp.h" -#include "stm32f30x_dac.h" -#include "stm32f30x_dbgmcu.h" -#include "stm32f30x_dma.h" -#include "stm32f30x_exti.h" -#include "stm32f30x_flash.h" -#include "stm32f30x_gpio.h" -#include "stm32f30x_hrtim.h" -#include "stm32f30x_syscfg.h" -#include "stm32f30x_i2c.h" -#include "stm32f30x_iwdg.h" -#include "stm32f30x_opamp.h" -#include "stm32f30x_pwr.h" -#include "stm32f30x_rcc.h" -#include "stm32f30x_rtc.h" -#include "stm32f30x_spi.h" -#include "stm32f30x_tim.h" -#include "stm32f30x_usart.h" -#include "stm32f30x_wwdg.h" -#include "stm32f30x_misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Uncomment the line below to expanse the "assert_param" macro in the - Standard Peripheral Library drivers code */ -/* #define USE_FULL_ASSERT 1 */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT - -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function which reports - * the name of the source file and the source line number of the call - * that failed. If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0) -#endif /* USE_FULL_ASSERT */ - -#endif /* __STM32F30X_CONF_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_crc.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,364 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_crc.c - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of CRC computation unit peripheral: - * + Configuration of the CRC computation unit - * + CRC computation of one/many 32-bit data - * + CRC Independent register (IDR) access - * - @verbatim - - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable CRC AHB clock using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_CRC, ENABLE) - function. - (#) Select the polynomial size: 7-bit, 8-bit, 16-bit or 32-bit. - (#) Set the polynomial coefficients using CRC_SetPolynomial(); - (#) If required, select the reverse operation on input data - using CRC_ReverseInputDataSelect(); - (#) If required, enable the reverse operation on output data - using CRC_ReverseOutputDataCmd(Enable); - (#) If required, set the initialization remainder value using - CRC_SetInitRegister(); - (#) use CRC_CalcCRC() function to compute the CRC of a 32-bit data - or use CRC_CalcBlockCRC() function to compute the CRC if a 32-bit - data buffer. - - @endverbatim - - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x_crc.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRC - * @brief CRC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup CRC_Private_Functions - * @{ - */ - -/** @defgroup CRC_Group1 Configuration of the CRC computation unit functions - * @brief Configuration of the CRC computation unit functions - * -@verbatim - =============================================================================== - ##### CRC configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes CRC peripheral registers to their default reset values. - * @param None - * @retval None - */ -void CRC_DeInit(void) -{ - /* Set DR register to reset value */ - CRC->DR = 0xFFFFFFFF; - /* Set the POL register to the reset value: 0x04C11DB7 */ - CRC->POL = 0x04C11DB7; - /* Reset IDR register */ - CRC->IDR = 0x00; - /* Set INIT register to reset value */ - CRC->INIT = 0xFFFFFFFF; - /* Reset the CRC calculation unit */ - CRC->CR = CRC_CR_RESET; -} - -/** - * @brief Resets the CRC calculation unit and sets INIT register content in DR register. - * @param None - * @retval None - */ -void CRC_ResetDR(void) -{ - /* Reset CRC generator */ - CRC->CR |= CRC_CR_RESET; -} - -/** - * @brief Selects the polynomial size. - * @param CRC_PolSize: Specifies the polynomial size. - * This parameter can be: - * @arg CRC_PolSize_7: 7-bit polynomial for CRC calculation - * @arg CRC_PolSize_8: 8-bit polynomial for CRC calculation - * @arg CRC_PolSize_16: 16-bit polynomial for CRC calculation - * @arg CRC_PolSize_32: 32-bit polynomial for CRC calculation - * @retval None - */ -void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize) -{ - uint32_t tmpcr = 0; - - /* Check the parameter */ - assert_param(IS_CRC_POL_SIZE(CRC_PolSize)); - - /* Get CR register value */ - tmpcr = CRC->CR; - - /* Reset POL_SIZE bits */ - tmpcr &= (uint32_t)~((uint32_t)CRC_CR_POLSIZE); - /* Set the polynomial size */ - tmpcr |= (uint32_t)CRC_PolSize; - - /* Write to CR register */ - CRC->CR = (uint32_t)tmpcr; -} - -/** - * @brief Selects the reverse operation to be performed on input data. - * @param CRC_ReverseInputData: Specifies the reverse operation on input data. - * This parameter can be: - * @arg CRC_ReverseInputData_No: No reverse operation is performed - * @arg CRC_ReverseInputData_8bits: reverse operation performed on 8 bits - * @arg CRC_ReverseInputData_16bits: reverse operation performed on 16 bits - * @arg CRC_ReverseInputData_32bits: reverse operation performed on 32 bits - * @retval None - */ -void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData) -{ - uint32_t tmpcr = 0; - - /* Check the parameter */ - assert_param(IS_CRC_REVERSE_INPUT_DATA(CRC_ReverseInputData)); - - /* Get CR register value */ - tmpcr = CRC->CR; - - /* Reset REV_IN bits */ - tmpcr &= (uint32_t)~((uint32_t)CRC_CR_REV_IN); - /* Set the reverse operation */ - tmpcr |= (uint32_t)CRC_ReverseInputData; - - /* Write to CR register */ - CRC->CR = (uint32_t)tmpcr; -} - -/** - * @brief Enables or disable the reverse operation on output data. - * The reverse operation on output data is performed on 32-bit. - * @param NewState: new state of the reverse operation on output data. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CRC_ReverseOutputDataCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable reverse operation on output data */ - CRC->CR |= CRC_CR_REV_OUT; - } - else - { - /* Disable reverse operation on output data */ - CRC->CR &= (uint32_t)~((uint32_t)CRC_CR_REV_OUT); - } -} - -/** - * @brief Initializes the INIT register. - * @note After resetting CRC calculation unit, CRC_InitValue is stored in DR register - * @param CRC_InitValue: Programmable initial CRC value - * @retval None - */ -void CRC_SetInitRegister(uint32_t CRC_InitValue) -{ - CRC->INIT = CRC_InitValue; -} - -/** - * @brief Initializes the polynomail coefficients. - * @param CRC_Pol: Polynomial to be used for CRC calculation. - * @retval None - */ -void CRC_SetPolynomial(uint32_t CRC_Pol) -{ - CRC->POL = CRC_Pol; -} - -/** - * @} - */ - -/** @defgroup CRC_Group2 CRC computation of one/many 32-bit data functions - * @brief CRC computation of one/many 32-bit data functions - * -@verbatim - =============================================================================== - ##### CRC computation functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Computes the 32-bit CRC of a given data word(32-bit). - * @param CRC_Data: data word(32-bit) to compute its CRC - * @retval 32-bit CRC - */ -uint32_t CRC_CalcCRC(uint32_t CRC_Data) -{ - CRC->DR = CRC_Data; - - return (CRC->DR); -} - -/** - * @brief Computes the 16-bit CRC of a given 16-bit data. - * @param CRC_Data: data half-word(16-bit) to compute its CRC - * @retval 16-bit CRC - */ -uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data) -{ - *(uint16_t*)(CRC_BASE) = (uint16_t) CRC_Data; - - return (CRC->DR); -} - -/** - * @brief Computes the 8-bit CRC of a given 8-bit data. - * @param CRC_Data: 8-bit data to compute its CRC - * @retval 8-bit CRC - */ -uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data) -{ - *(uint8_t*)(CRC_BASE) = (uint8_t) CRC_Data; - - return (CRC->DR); -} - -/** - * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). - * @param pBuffer: pointer to the buffer containing the data to be computed - * @param BufferLength: length of the buffer to be computed - * @retval 32-bit CRC - */ -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) -{ - uint32_t index = 0; - - for(index = 0; index < BufferLength; index++) - { - CRC->DR = pBuffer[index]; - } - return (CRC->DR); -} - -/** - * @brief Returns the current CRC value. - * @param None - * @retval 32-bit CRC - */ -uint32_t CRC_GetCRC(void) -{ - return (CRC->DR); -} - -/** - * @} - */ - -/** @defgroup CRC_Group3 CRC Independent Register (IDR) access functions - * @brief CRC Independent Register (IDR) access (write/read) functions - * -@verbatim - =============================================================================== - ##### CRC Independent Register (IDR) access functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Stores an 8-bit data in the Independent Data(ID) register. - * @param CRC_IDValue: 8-bit value to be stored in the ID register - * @retval None - */ -void CRC_SetIDRegister(uint8_t CRC_IDValue) -{ - CRC->IDR = CRC_IDValue; -} - -/** - * @brief Returns the 8-bit data stored in the Independent Data(ID) register - * @param None - * @retval 8-bit value of the ID register - */ -uint8_t CRC_GetIDRegister(void) -{ - return (CRC->IDR); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_crc.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,131 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_crc.h - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file contains all the functions prototypes for the CRC firmware - * library. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F30x_CRC_H -#define __STM32F30x_CRC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/*!< Includes ----------------------------------------------------------------*/ -#include "stm32f30x.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CRC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CRC_ReverseInputData - * @{ - */ -#define CRC_ReverseInputData_No ((uint32_t)0x00000000) /*!< No reverse operation of Input Data */ -#define CRC_ReverseInputData_8bits CRC_CR_REV_IN_0 /*!< Reverse operation of Input Data on 8 bits */ -#define CRC_ReverseInputData_16bits CRC_CR_REV_IN_1 /*!< Reverse operation of Input Data on 16 bits */ -#define CRC_ReverseInputData_32bits CRC_CR_REV_IN /*!< Reverse operation of Input Data on 32 bits */ - -#define IS_CRC_REVERSE_INPUT_DATA(DATA) (((DATA) == CRC_ReverseInputData_No) || \ - ((DATA) == CRC_ReverseInputData_8bits) || \ - ((DATA) == CRC_ReverseInputData_16bits) || \ - ((DATA) == CRC_ReverseInputData_32bits)) - -/** - * @} - */ - -/** @defgroup CRC_PolynomialSize - * @{ - */ -#define CRC_PolSize_7 CRC_CR_POLSIZE /*!< 7-bit polynomial for CRC calculation */ -#define CRC_PolSize_8 CRC_CR_POLSIZE_1 /*!< 8-bit polynomial for CRC calculation */ -#define CRC_PolSize_16 CRC_CR_POLSIZE_0 /*!< 16-bit polynomial for CRC calculation */ -#define CRC_PolSize_32 ((uint32_t)0x00000000)/*!< 32-bit polynomial for CRC calculation */ - -#define IS_CRC_POL_SIZE(SIZE) (((SIZE) == CRC_PolSize_7) || \ - ((SIZE) == CRC_PolSize_8) || \ - ((SIZE) == CRC_PolSize_16) || \ - ((SIZE) == CRC_PolSize_32)) - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -/* Configuration of the CRC computation unit **********************************/ -void CRC_DeInit(void); -void CRC_ResetDR(void); -void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize); -void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData); -void CRC_ReverseOutputDataCmd(FunctionalState NewState); -void CRC_SetInitRegister(uint32_t CRC_InitValue); -void CRC_SetPolynomial(uint32_t CRC_Pol); - -/* CRC computation ************************************************************/ -uint32_t CRC_CalcCRC(uint32_t CRC_Data); -uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data); -uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data); -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); -uint32_t CRC_GetCRC(void); - -/* Independent register (IDR) access (write/read) *****************************/ -void CRC_SetIDRegister(uint8_t CRC_IDValue); -uint8_t CRC_GetIDRegister(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F30x_CRC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_dac.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,764 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_dac.c - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Digital-to-Analog Converter (DAC) peripheral: - * + DAC channels configuration: trigger, output buffer, data format - * + DMA management - * + Interrupts and flags management - * - @verbatim - - =============================================================================== - ##### DAC Peripheral features ##### - =============================================================================== - [..] The device integrates two 12-bit Digital Analog Converters that can - be used independently or simultaneously (dual mode): - (#) DAC1 integrates two DAC channels: - (++) DAC1 channel 1 with DAC1_OUT1 as output - (++) DAC1 channel 2 with DAC1_OUT2 as output - (++) The two channels can be used independently or simultaneously (dual mode) - - (#) DAC2 integrates only one channel DAC2 channel 1 with DAC2_OUT1 as output - - [..] Digital to Analog conversion can be non-triggered using DAC_Trigger_None - and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register using - DAC_SetChannel1Data()/DAC_SetChannel2Data. - - [..] Digital to Analog conversion can be triggered by: - (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9. - The used pin (GPIOx_Pin9) must be configured in input mode. - - (#) Timers TRGO: TIM2, TIM8/TIM3, TIM4, TIM6, TIM7, and TIM15 - (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...) - The timer TRGO event should be selected using TIM_SelectOutputTrigger() - (++) To trigger DAC conversions by TIM3 instead of TIM8 follow - this sequence: - (+++) Enable SYSCFG APB clock by calling - RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - (+++) Select DAC_Trigger_T3_TRGO when calling DAC_Init() - (+++) Remap the DAC trigger from TIM8 to TIM3 by calling - SYSCFG_TriggerRemapConfig(SYSCFG_TriggerRemap_DACTIM3, ENABLE) - (#) Software using DAC_Trigger_Software - - [..] Each DAC channel integrates an output buffer that can be used to - reduce the output impedance, and to drive external loads directly - without having to add an external operational amplifier. - To enable, the output buffer use - DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable; - - [..] Refer to the device datasheet for more details about output impedance - value with and without output buffer. - - [..] Both DAC channels can be used to generate: - (+) Noise wave using DAC_WaveGeneration_Noise - (+) Triangle wave using DAC_WaveGeneration_Triangle - - [..] Wave generation can be disabled using DAC_WaveGeneration_None - - [..] The DAC data format can be: - (+) 8-bit right alignment using DAC_Align_8b_R - (+) 12-bit left alignment using DAC_Align_12b_L - (+) 12-bit right alignment using DAC_Align_12b_R - - [..] The analog output voltage on each DAC channel pin is determined - by the following equation: - (+) DAC_OUTx = VREF+ * DOR / 4095 with DOR is the Data Output Register. - VREF+ is the input voltage reference (refer to the device datasheet) - e.g. To set DAC_OUT1 to 0.7V, use DAC_SetChannel1Data(DAC_Align_12b_R, 868); - Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V - - [..] A DMA1 request can be generated when an external trigger (but not - a software trigger) occurs if DMA1 requests are enabled using - DAC_DMACmd() - DMA1 requests are mapped as following: - (+) DAC channel1 is mapped on DMA1 channel3 which must be already - configured - (+) DAC channel2 is mapped on DMA1 channel4 which must be already - configured - - ##### How to use this driver ##### - =============================================================================== - [..] - (+) Enable DAC APB1 clock to get write access to DAC registers - using RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE) - - (+) Configure DACx_OUTy (DAC1_OUT1: PA4, DAC1_OUT2: PA5, DAC2_OUT1: PA6) - in analog mode. - - (+) Configure the DAC channel using DAC_Init() - - (+) Enable the DAC channel using DAC_Cmd() - - @endverbatim - - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x_dac.h" -#include "stm32f30x_rcc.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @defgroup DAC - * @brief DAC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* CR register Mask */ -#define CR_CLEAR_MASK ((uint32_t)0x00000FFE) - -/* DAC Dual Channels SWTRIG masks */ -#define DUAL_SWTRIG_SET ((uint32_t)0x00000003) -#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) - -/* DHR registers offsets */ -#define DHR12R1_OFFSET ((uint32_t)0x00000008) -#define DHR12R2_OFFSET ((uint32_t)0x00000014) -#define DHR12RD_OFFSET ((uint32_t)0x00000020) - -/* DOR register offset */ -#define DOR_OFFSET ((uint32_t)0x0000002C) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DAC_Private_Functions - * @{ - */ - -/** @defgroup DAC_Group1 DAC channels configuration - * @brief DAC channels configuration: trigger, output buffer, data format - * -@verbatim - =============================================================================== - ##### DAC channels configuration: trigger, output buffer, data format ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the DAC peripheral registers to their default reset values. - * @param DACx: where x can be 1 or 2 to select the DAC peripheral. - * @retval None - */ -void DAC_DeInit(DAC_TypeDef* DACx) -{ - /* Check the parameters */ - assert_param(IS_DAC_ALL_PERIPH(DACx)); - - if (DACx == DAC1) - { - /* Enable DAC1 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC1, ENABLE); - /* Release DAC1 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC1, DISABLE); - } - else - { - /* Enable DAC2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC2, ENABLE); - /* Release DAC2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC2, DISABLE); - } -} - -/** - * @brief Initializes the DAC peripheral according to the specified - * parameters in the DAC_InitStruct. - * @param DACx: where x can be 1 or 2 to select the DAC peripheral. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that - * contains the configuration information for the specified DAC channel. - * @retval None - */ -void DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - - /* Check the DAC parameters */ - assert_param(IS_DAC_ALL_PERIPH(DACx)); - assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); - assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); - assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); - assert_param(IS_DAC_BUFFER_SWITCH_STATE(DAC_InitStruct->DAC_Buffer_Switch)); - -/*---------------------------- DAC CR Configuration --------------------------*/ - /* Get the DAC CR value */ - tmpreg1 = DACx->CR; - /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ - tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); - /* Configure for the selected DAC channel: buffer output, trigger, wave generation, - mask/amplitude for wave generation */ - - /* Set TSELx and TENx bits according to DAC_Trigger value */ - /* Set WAVEx bits according to DAC_WaveGeneration value */ - /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ - /* Set BOFFx OUTENx bit according to DAC_Buffer_Switch value */ - tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_Buffer_Switch); - - /* Calculate CR register value depending on DAC_Channel */ - tmpreg1 |= tmpreg2 << DAC_Channel; - /* Write to DAC CR */ - DACx->CR = tmpreg1; -} - -/** - * @brief Fills each DAC_InitStruct member with its default value. - * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) -{ -/*--------------- Reset DAC init structure parameters values -----------------*/ - /* Initialize the DAC_Trigger member */ - DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; - /* Initialize the DAC_WaveGeneration member */ - DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; - /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; - /* Initialize the DAC_Buffer_Switch member */ - DAC_InitStruct->DAC_Buffer_Switch = DAC_BufferSwitch_Enable; -} - -/** - * @brief Enables or disables the specified DAC channel. - * @param DACx: where x can be 1 or 2 to select the DAC peripheral. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the DAC channel. - * This parameter can be: ENABLE or DISABLE. - * @note When the DAC channel is enabled the trigger source can no more - * be modified. - * @retval None - */ -void DAC_Cmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_ALL_PERIPH(DACx)); - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC channel */ - DACx->CR |= (DAC_CR_EN1 << DAC_Channel); - } - else - { - /* Disable the selected DAC channel */ - DACx->CR &= (~(DAC_CR_EN1 << DAC_Channel)); - } -} - -/** - * @brief Enables or disables the selected DAC channel software trigger. - * @param DACx: where x can be 1 or 2 to select the DAC peripheral. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel software trigger. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_SoftwareTriggerCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_ALL_PERIPH(DACx)); - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable software trigger for the selected DAC channel */ - DACx->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); - } - else - { - /* Disable software trigger for the selected DAC channel */ - DACx->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); - } -} - -/** - * @brief Enables or disables simultaneously the two DAC channels software - * triggers. - * @param DACx: where x can be 1 to select the DAC1 peripheral. - * @note Dual trigger is not applicable for DAC2 (DAC2 integrates one channel). - * @param NewState: new state of the DAC channels software triggers. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_DualSoftwareTriggerCmd(DAC_TypeDef* DACx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_LIST1_PERIPH(DACx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable software trigger for both DAC channels */ - DACx->SWTRIGR |= DUAL_SWTRIG_SET; - } - else - { - /* Disable software trigger for both DAC channels */ - DACx->SWTRIGR &= DUAL_SWTRIG_RESET; - } -} - -/** - * @brief Enables or disables the selected DAC channel wave generation. - * @param DACx: where x can be 1 to select the DAC1 peripheral. - * @note Wave generation is not available in DAC2. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_Wave: Specifies the wave type to enable or disable. - * This parameter can be one of the following values: - * @arg DAC_Wave_Noise: noise wave generation - * @arg DAC_Wave_Triangle: triangle wave generation - * @param NewState: new state of the selected DAC channel wave generation. - * This parameter can be: ENABLE or DISABLE. - * @note - * @retval None - */ -void DAC_WaveGenerationCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_LIST1_PERIPH(DACx)); - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_WAVE(DAC_Wave)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected wave generation for the selected DAC channel */ - DACx->CR |= DAC_Wave << DAC_Channel; - } - else - { - /* Disable the selected wave generation for the selected DAC channel */ - DACx->CR &= ~(DAC_Wave << DAC_Channel); - } -} - -/** - * @brief Set the specified data holding register value for DAC channel1. - * @param DACx: where x can be 1 or 2 to select the DAC peripheral. - * @param DAC_Align: Specifies the data alignment for DAC channel1. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data: Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel1Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALL_PERIPH(DACx)); - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DACx; - tmp += DHR12R1_OFFSET + DAC_Align; - - /* Set the DAC channel1 selected data holding register */ - *(__IO uint32_t *) tmp = Data; -} - -/** - * @brief Set the specified data holding register value for DAC channel2. - * @param DACx: where x can be 1 to select the DAC peripheral. - * @note This function is available only for DAC1. - * @param DAC_Align: Specifies the data alignment for DAC channel2. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data : Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel2Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_LIST1_PERIPH(DACx)); - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DACx; - tmp += DHR12R2_OFFSET + DAC_Align; - - /* Set the DAC channel2 selected data holding register */ - *(__IO uint32_t *)tmp = Data; -} - -/** - * @brief Set the specified data holding register value for dual channel DAC. - * @param DACx: where x can be 1 to select the DAC peripheral. - * @note This function isn't applicable for DAC2. - * @param DAC_Align: Specifies the data alignment for dual channel DAC. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data2: Data for DAC Channel2 to be loaded in the selected data - * holding register. - * @param Data1: Data for DAC Channel1 to be loaded in the selected data - * holding register. - * @note In dual mode, a unique register access is required to write in both - * DAC channels at the same time. - * @retval None - */ -void DAC_SetDualChannelData(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) -{ - uint32_t data = 0, tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_LIST1_PERIPH(DACx)); - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data1)); - assert_param(IS_DAC_DATA(Data2)); - - /* Calculate and set dual DAC data holding register value */ - if (DAC_Align == DAC_Align_8b_R) - { - data = ((uint32_t)Data2 << 8) | Data1; - } - else - { - data = ((uint32_t)Data2 << 16) | Data1; - } - - tmp = (uint32_t)DACx; - tmp += DHR12RD_OFFSET + DAC_Align; - - /* Set the dual DAC selected data holding register */ - *(__IO uint32_t *)tmp = data; -} - -/** - * @brief Returns the last data output value of the selected DAC channel. - * @param DACx: where x can be 1 or 2 to select the DAC peripheral. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @retval The selected DAC channel data output value. - */ -uint16_t DAC_GetDataOutputValue(DAC_TypeDef* DACx, uint32_t DAC_Channel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALL_PERIPH(DACx)); - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - - tmp = (uint32_t) DACx; - tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); - - /* Returns the DAC channel data output register value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} - -/** - * @} - */ - -/** @defgroup DAC_Group2 DMA management functions - * @brief DMA management functions - * -@verbatim - =============================================================================== - ##### DMA management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified DAC channel DMA request. - * When enabled DMA1 is generated when an external trigger (EXTI Line9, - * TIM2, TIM4, TIM6, TIM7 or TIM9 but not a software trigger) occurs - * @param DACx: where x can be 1 or 2 to select the DAC peripheral. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel DMA request. - * This parameter can be: ENABLE or DISABLE. - * @note The DAC channel1 (channel2) is mapped on DMA1 channel3 (channel4) which - * must be already configured. - * @retval None - */ -void DAC_DMACmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_ALL_PERIPH(DACx)); - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC channel DMA request */ - DACx->CR |= (DAC_CR_DMAEN1 << DAC_Channel); - } - else - { - /* Disable the selected DAC channel DMA request */ - DACx->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel)); - } -} - -/** - * @} - */ - -/** @defgroup DAC_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified DAC interrupts. - * @param DACx: where x can be 1 or 2 to select the DAC peripheral. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @note The DMA underrun occurs when a second external trigger arrives before - * the acknowledgement for the first external trigger is received (first request). - * @param NewState: new state of the specified DAC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_ITConfig(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_ALL_PERIPH(DACx)); - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_DAC_IT(DAC_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC interrupts */ - DACx->CR |= (DAC_IT << DAC_Channel); - } - else - { - /* Disable the selected DAC interrupts */ - DACx->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); - } -} - -/** - * @brief Checks whether the specified DAC flag is set or not. - * @param DACx: where x can be 1 or 2 to select the DAC peripheral. - * @param DAC_Channel: thee selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_FLAG: specifies the flag to check. - * This parameter can be: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @note The DMA underrun occurs when a second external trigger arrives before - * the acknowledgement for the first external trigger is received (first request). - * @retval The new state of DAC_FLAG (SET or RESET). - */ -FlagStatus DAC_GetFlagStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_DAC_ALL_PERIPH(DACx)); - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Check the status of the specified DAC flag */ - if ((DACx->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) - { - /* DAC_FLAG is set */ - bitstatus = SET; - } - else - { - /* DAC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the DAC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channel's pending flags. - * @param DACx: where x can be 1 or 2 to select the DAC peripheral. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_FLAG: specifies the flag to clear. - * This parameter can be: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @retval None - */ -void DAC_ClearFlag(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DAC_ALL_PERIPH(DACx)); - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Clear the selected DAC flags */ - DACx->SR = (DAC_FLAG << DAC_Channel); -} - -/** - * @brief Checks whether the specified DAC interrupt has occurred or not. - * @param DACx: where x can be 1 or 2 to select the DAC peripheral. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt source to check. - * This parameter can be: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @note The DMA underrun occurs when a second external trigger arrives before - * the acknowledgement for the first external trigger is received (first request). - * @retval The new state of DAC_IT (SET or RESET). - */ -ITStatus DAC_GetITStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALL_PERIPH(DACx)); - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Get the DAC_IT enable bit status */ - enablestatus = (DACx->CR & (DAC_IT << DAC_Channel)) ; - - /* Check the status of the specified DAC interrupt */ - if (((DACx->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) - { - /* DAC_IT is set */ - bitstatus = SET; - } - else - { - /* DAC_IT is reset */ - bitstatus = RESET; - } - /* Return the DAC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channel's interrupt pending bits. - * @param DACx: where x can be 1 or 2 to select the DAC peripheral. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt pending bit to clear. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @retval None - */ -void DAC_ClearITPendingBit(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT) -{ - /* Check the parameters */ - assert_param(IS_DAC_ALL_PERIPH(DACx)); - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Clear the selected DAC interrupt pending bits */ - DACx->SR = (DAC_IT << DAC_Channel); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_dac.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,332 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_dac.h - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file contains all the functions prototypes for the DAC firmware - * library. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F30x_DAC_H -#define __STM32F30x_DAC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DAC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -#define DAC_CR_DMAUDRIE ((uint32_t)0x00002000) /*!< DAC channel DMA underrun interrupt enable */ - -/** - * @brief DAC Init structure definition - */ - -typedef struct -{ - uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. - This parameter can be a value of @ref DAC_trigger_selection */ - - uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves - are generated, or whether no wave is generated. - This parameter can be a value of @ref DAC_wave_generation */ - - uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or - the maximum amplitude triangle generation for the DAC channel. - This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ - - uint32_t DAC_Buffer_Switch; /*!< Specifies whether the DAC channel output buffer is enabled or disabled or - the DAC channel output switch is enabled or disabled. - This parameter can be a value of @ref DAC_buffer_switch */ -}DAC_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DAC_Exported_Constants - * @{ - */ - -#define IS_DAC_ALL_PERIPH(PERIPH) (((PERIPH) == DAC1) || \ - ((PERIPH) == DAC2)) - -#define IS_DAC_LIST1_PERIPH(PERIPH) (((PERIPH) == DAC1)) - -/** @defgroup DAC_trigger_selection - * @{ - */ - -#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */ -#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM3 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */ -#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC1 channel1/2 */ -#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */ -#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */ -#define DAC_Trigger_HRTIM1_DACTRG1 ((uint32_t)0x0000001C) /*!< HRTIM1 DACTRG1 selected as external conversion trigger for DAC1 channel1/2 */ -#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */ -#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_HRTIM1_DACTRG2 ((uint32_t)0x0000002C) /*!< HRTIM1 DACTRG2 selected as external conversion trigger for DAC1 channel1/2 */ -#define DAC_Trigger_HRTIM1_DACTRG3 ((uint32_t)0x0000002C) /*!< HRTIM1 DACTRG3 selected as external conversion trigger for DAC2 channel1 */ -#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC1/2 channel1/2 */ -#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC1/2 channel1/2 */ - -#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ - ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T3_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T15_TRGO) || \ - ((TRIGGER) == DAC_Trigger_HRTIM1_DACTRG1)|| \ - ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ - ((TRIGGER) == DAC_Trigger_HRTIM1_DACTRG2)|| \ - ((TRIGGER) == DAC_Trigger_HRTIM1_DACTRG3)|| \ - ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ - ((TRIGGER) == DAC_Trigger_Software)) - -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_WaveGeneration_None ((uint32_t)0x00000000) -#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) -#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) - -#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ - ((WAVE) == DAC_WaveGeneration_Noise) || \ - ((WAVE) == DAC_WaveGeneration_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_lfsrunmask_triangleamplitude - * @{ - */ - -#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ -#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ -#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ -#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ -#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ -#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ -#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ -#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ -#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ -#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ -#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ -#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ -#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ -#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ - -#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ - ((VALUE) == DAC_TriangleAmplitude_1) || \ - ((VALUE) == DAC_TriangleAmplitude_3) || \ - ((VALUE) == DAC_TriangleAmplitude_7) || \ - ((VALUE) == DAC_TriangleAmplitude_15) || \ - ((VALUE) == DAC_TriangleAmplitude_31) || \ - ((VALUE) == DAC_TriangleAmplitude_63) || \ - ((VALUE) == DAC_TriangleAmplitude_127) || \ - ((VALUE) == DAC_TriangleAmplitude_255) || \ - ((VALUE) == DAC_TriangleAmplitude_511) || \ - ((VALUE) == DAC_TriangleAmplitude_1023) || \ - ((VALUE) == DAC_TriangleAmplitude_2047) || \ - ((VALUE) == DAC_TriangleAmplitude_4095)) -/** - * @} - */ - -/** @defgroup DAC_buffer_switch - * @{ - */ - -#define DAC_BufferSwitch_Disable ((uint32_t)0x00000000) -#define DAC_BufferSwitch_Enable ((uint32_t)0x00000002) - -#define IS_DAC_BUFFER_SWITCH_STATE(STATE) (((STATE) == DAC_BufferSwitch_Enable) || \ - ((STATE) == DAC_BufferSwitch_Disable)) -/** - * @} - */ - -/** @defgroup DAC_Channel_selection - * @{ - */ -#define DAC_Channel_1 ((uint32_t)0x00000000) -#define DAC_Channel_2 ((uint32_t)0x00000010) - -#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ - ((CHANNEL) == DAC_Channel_2)) -/** - * @} - */ - -/** @defgroup DAC_data_alignement - * @{ - */ - -#define DAC_Align_12b_R ((uint32_t)0x00000000) -#define DAC_Align_12b_L ((uint32_t)0x00000004) -#define DAC_Align_8b_R ((uint32_t)0x00000008) - -#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ - ((ALIGN) == DAC_Align_12b_L) || \ - ((ALIGN) == DAC_Align_8b_R)) -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_Wave_Noise ((uint32_t)0x00000040) -#define DAC_Wave_Triangle ((uint32_t)0x00000080) - -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ - ((WAVE) == DAC_Wave_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_data - * @{ - */ - -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) -/** - * @} - */ - -/** @defgroup DAC_interrupts_definition - * @{ - */ -#define DAC_IT_DMAUDR ((uint32_t)0x00002000) -#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) - -/** - * @} - */ - -/** @defgroup DAC_flags_definition - * @{ - */ - -#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) -#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the DAC configuration to the default reset state *****/ -void DAC_DeInit(DAC_TypeDef* DACx); - -/* DAC channels configuration: trigger, output buffer, data format functions */ -void DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); -void DAC_Cmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState); -void DAC_SoftwareTriggerCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState); -void DAC_DualSoftwareTriggerCmd(DAC_TypeDef* DACx, FunctionalState NewState); -void DAC_WaveGenerationCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); -void DAC_SetChannel1Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data); -void DAC_SetChannel2Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data); -void DAC_SetDualChannelData(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); -uint16_t DAC_GetDataOutputValue(DAC_TypeDef* DACx, uint32_t DAC_Channel); - -/* DMA management functions ***************************************************/ -void DAC_DMACmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void DAC_ITConfig(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); -FlagStatus DAC_GetFlagStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG); -void DAC_ClearFlag(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG); -ITStatus DAC_GetITStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT); -void DAC_ClearITPendingBit(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F30x_DAC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_dbgmcu.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,223 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_dbgmcu.c - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Debug MCU (DBGMCU) peripheral: - * + Device and Revision ID management - * + Peripherals Configuration - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x_dbgmcu.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @defgroup DBGMCU - * @brief DBGMCU driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DBGMCU_Private_Functions - * @{ - */ - -/** @defgroup DBGMCU_Group1 Device and Revision ID management functions - * @brief Device and Revision ID management functions - * -@verbatim - ============================================================================== - ##### Device and Revision ID management functions ##### - ============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Returns the device revision identifier. - * @param None - * @retval Device revision identifier - */ -uint32_t DBGMCU_GetREVID(void) -{ - return(DBGMCU->IDCODE >> 16); -} - -/** - * @brief Returns the device identifier. - * @param None - * @retval Device identifier - */ -uint32_t DBGMCU_GetDEVID(void) -{ - return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); -} - -/** - * @} - */ - -/** @defgroup DBGMCU_Group2 Peripherals Configuration functions - * @brief Peripherals Configuration - * -@verbatim - ============================================================================== - ##### Peripherals Configuration functions ##### - ============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures low power mode behavior when the MCU is in Debug mode. - * @param DBGMCU_Periph: specifies the low power mode. - * This parameter can be any combination of the following values: - * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode. - * @arg DBGMCU_STOP: Keep debugger connection during STOP mode. - * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode. - * @param NewState: new state of the specified low power mode in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - DBGMCU->CR |= DBGMCU_Periph; - } - else - { - DBGMCU->CR &= ~DBGMCU_Periph; - } -} - -/** - * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode. - * @param DBGMCU_Periph: specifies the APB1 peripheral. - * This parameter can be any combination of the following values: - * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted. - * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted. - * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted. - * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted. - * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted. - * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter are stopped when - * Core is halted. - * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted. - * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted. - * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when - * Core is halted. - * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when - * Core is halted. - * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted. - * @param NewState: new state of the specified APB1 peripheral in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - DBGMCU->APB1FZ |= DBGMCU_Periph; - } - else - { - DBGMCU->APB1FZ &= ~DBGMCU_Periph; - } -} - -/** - * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode. - * @param DBGMCU_Periph: specifies the APB2 peripheral. - * This parameter can be any combination of the following values: - * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted. - * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted. - * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted. - * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted. - * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted. - * @param NewState: new state of the specified APB2 peripheral in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - DBGMCU->APB2FZ |= DBGMCU_Periph; - } - else - { - DBGMCU->APB2FZ &= ~DBGMCU_Periph; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_dbgmcu.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,118 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_dbgmcu.h - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file contains all the functions prototypes for the DBGMCU firmware library. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F30x_DBGMCU_H -#define __STM32F30x_DBGMCU_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DBGMCU - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DBGMCU_Exported_Constants - * @{ - */ -#define DBGMCU_SLEEP ((uint32_t)0x00000001) -#define DBGMCU_STOP ((uint32_t)0x00000002) -#define DBGMCU_STANDBY ((uint32_t)0x00000004) -#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00)) - -#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001) -#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002) -#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004) -#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010) -#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020) -#define DBGMCU_RTC_STOP ((uint32_t)0x00000400) -#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800) -#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000) -#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) -#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) -#define DBGMCU_CAN1_STOP ((uint32_t)0x02000000) - -#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFD9FE3C8) == 0x00) && ((PERIPH) != 0x00)) - -#define DBGMCU_TIM1_STOP ((uint32_t)0x00000001) -#define DBGMCU_TIM8_STOP ((uint32_t)0x00000002) -#define DBGMCU_TIM15_STOP ((uint32_t)0x00000004) -#define DBGMCU_TIM16_STOP ((uint32_t)0x00000008) -#define DBGMCU_TIM17_STOP ((uint32_t)0x00000010) -#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFE0) == 0x00) && ((PERIPH) != 0x00)) - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/* Device and Revision ID management functions ********************************/ -uint32_t DBGMCU_GetREVID(void); -uint32_t DBGMCU_GetDEVID(void); - -/* Peripherals Configuration functions ****************************************/ -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); -void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); -void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F30x_DBGMCU_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_dma.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,876 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_dma.c - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Direct Memory Access controller (DMA): - * + Initialization and Configuration - * + Data Counter - * + Interrupts and flags management - * - @verbatim - - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable The DMA controller clock using - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1 or - using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE) function for DMA2. - (#) Enable and configure the peripheral to be connected to the DMA channel - (except for internal SRAM / FLASH memories: no initialization is necessary). - (#) For a given Channel, program the Source and Destination addresses, - the transfer Direction, the Buffer Size, the Peripheral and Memory - Incrementation mode and Data Size, the Circular or Normal mode, - the channel transfer Priority and the Memory-to-Memory transfer - mode (if needed) using the DMA_Init() function. - (#) Enable the NVIC and the corresponding interrupt(s) using the function - DMA_ITConfig() if you need to use DMA interrupts. - (#) Enable the DMA channel using the DMA_Cmd() function. - (#) Activate the needed channel Request using PPP_DMACmd() function for - any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) - The function allowing this operation is provided in each PPP peripheral - driver (ie. SPI_DMACmd for SPI peripheral). - (#) Optionally, you can configure the number of data to be transferred - when the channel is disabled (ie. after each Transfer Complete event - or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter(). - And you can get the number of remaining data to be transferred using - the function DMA_GetCurrDataCounter() at run time (when the DMA channel is - enabled and running). - (#) To control DMA events you can use one of the following two methods: - (##) Check on DMA channel flags using the function DMA_GetFlagStatus(). - (##) Use DMA interrupts through the function DMA_ITConfig() at initialization - phase and DMA_GetITStatus() function into interrupt routines in - communication phase. - After checking on a flag you should clear it using DMA_ClearFlag() - function. And after checking on an interrupt event you should - clear it using DMA_ClearITPendingBit() function. - - @endverbatim - - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x_dma.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @defgroup DMA - * @brief DMA driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F) /* DMA Channel config registers Masks */ -#define FLAG_Mask ((uint32_t)0x10000000) /* DMA2 FLAG mask */ - - -/* DMA1 Channelx interrupt pending bit masks */ -#define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) -#define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) -#define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) -#define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) -#define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) -#define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6)) -#define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7)) - -/* DMA2 Channelx interrupt pending bit masks */ -#define DMA2_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) -#define DMA2_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) -#define DMA2_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) -#define DMA2_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) -#define DMA2_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DMA_Private_Functions - * @{ - */ - -/** @defgroup DMA_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This subsection provides functions allowing to initialize the DMA channel - source and destination addresses, incrementation and data sizes, transfer - direction, buffer size, circular/normal mode selection, memory-to-memory - mode selection and channel priority value. - [..] The DMA_Init() function follows the DMA configuration procedures as described - in reference manual (RM00316). - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the DMAy Channelx registers to their default reset - * values. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @retval None - */ -void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - - /* Disable the selected DMAy Channelx */ - DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN); - - /* Reset DMAy Channelx control register */ - DMAy_Channelx->CCR = 0; - - /* Reset DMAy Channelx remaining bytes register */ - DMAy_Channelx->CNDTR = 0; - - /* Reset DMAy Channelx peripheral address register */ - DMAy_Channelx->CPAR = 0; - - /* Reset DMAy Channelx memory address register */ - DMAy_Channelx->CMAR = 0; - - if (DMAy_Channelx == DMA1_Channel1) - { - /* Reset interrupt pending bits for DMA1 Channel1 */ - DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK; - } - else if (DMAy_Channelx == DMA1_Channel2) - { - /* Reset interrupt pending bits for DMA1 Channel2 */ - DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK; - } - else if (DMAy_Channelx == DMA1_Channel3) - { - /* Reset interrupt pending bits for DMA1 Channel3 */ - DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK; - } - else if (DMAy_Channelx == DMA1_Channel4) - { - /* Reset interrupt pending bits for DMA1 Channel4 */ - DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK; - } - else if (DMAy_Channelx == DMA1_Channel5) - { - /* Reset interrupt pending bits for DMA1 Channel5 */ - DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK; - } - else if (DMAy_Channelx == DMA1_Channel6) - { - /* Reset interrupt pending bits for DMA1 Channel6 */ - DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK; - } - else if (DMAy_Channelx == DMA1_Channel7) - { - /* Reset interrupt pending bits for DMA1 Channel7 */ - DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK; - } - else if (DMAy_Channelx == DMA2_Channel1) - { - /* Reset interrupt pending bits for DMA2 Channel1 */ - DMA2->IFCR |= DMA2_CHANNEL1_IT_MASK; - } - else if (DMAy_Channelx == DMA2_Channel2) - { - /* Reset interrupt pending bits for DMA2 Channel2 */ - DMA2->IFCR |= DMA2_CHANNEL2_IT_MASK; - } - else if (DMAy_Channelx == DMA2_Channel3) - { - /* Reset interrupt pending bits for DMA2 Channel3 */ - DMA2->IFCR |= DMA2_CHANNEL3_IT_MASK; - } - else if (DMAy_Channelx == DMA2_Channel4) - { - /* Reset interrupt pending bits for DMA2 Channel4 */ - DMA2->IFCR |= DMA2_CHANNEL4_IT_MASK; - } - else - { - if (DMAy_Channelx == DMA2_Channel5) - { - /* Reset interrupt pending bits for DMA2 Channel5 */ - DMA2->IFCR |= DMA2_CHANNEL5_IT_MASK; - } - } -} - -/** - * @brief Initializes the DMAy Channelx according to the specified parameters - * in the DMA_InitStruct. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval None - */ -void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); - assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); - assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); - assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); - assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); - assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); - assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); - assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); - -/*--------------------------- DMAy Channelx CCR Configuration ----------------*/ - /* Get the DMAy_Channelx CCR value */ - tmpreg = DMAy_Channelx->CCR; - - /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ - tmpreg &= CCR_CLEAR_MASK; - - /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ - /* Set DIR bit according to DMA_DIR value */ - /* Set CIRC bit according to DMA_Mode value */ - /* Set PINC bit according to DMA_PeripheralInc value */ - /* Set MINC bit according to DMA_MemoryInc value */ - /* Set PSIZE bits according to DMA_PeripheralDataSize value */ - /* Set MSIZE bits according to DMA_MemoryDataSize value */ - /* Set PL bits according to DMA_Priority value */ - /* Set the MEM2MEM bit according to DMA_M2M value */ - tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | - DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | - DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | - DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; - - /* Write to DMAy Channelx CCR */ - DMAy_Channelx->CCR = tmpreg; - -/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/ - /* Write to DMAy Channelx CNDTR */ - DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; - -/*--------------------------- DMAy Channelx CPAR Configuration ---------------*/ - /* Write to DMAy Channelx CPAR */ - DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; - -/*--------------------------- DMAy Channelx CMAR Configuration ---------------*/ - /* Write to DMAy Channelx CMAR */ - DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; -} - -/** - * @brief Fills each DMA_InitStruct member with its default value. - * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) -{ -/*-------------- Reset DMA init structure parameters values ------------------*/ - /* Initialize the DMA_PeripheralBaseAddr member */ - DMA_InitStruct->DMA_PeripheralBaseAddr = 0; - /* Initialize the DMA_MemoryBaseAddr member */ - DMA_InitStruct->DMA_MemoryBaseAddr = 0; - /* Initialize the DMA_DIR member */ - DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; - /* Initialize the DMA_BufferSize member */ - DMA_InitStruct->DMA_BufferSize = 0; - /* Initialize the DMA_PeripheralInc member */ - DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; - /* Initialize the DMA_MemoryInc member */ - DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; - /* Initialize the DMA_PeripheralDataSize member */ - DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - /* Initialize the DMA_MemoryDataSize member */ - DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - /* Initialize the DMA_Mode member */ - DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; - /* Initialize the DMA_Priority member */ - DMA_InitStruct->DMA_Priority = DMA_Priority_Low; - /* Initialize the DMA_M2M member */ - DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; -} - -/** - * @brief Enables or disables the specified DMAy Channelx. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @param NewState: new state of the DMAy Channelx. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DMAy Channelx */ - DMAy_Channelx->CCR |= DMA_CCR_EN; - } - else - { - /* Disable the selected DMAy Channelx */ - DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN); - } -} - -/** - * @} - */ - -/** @defgroup DMA_Group2 Data Counter functions - * @brief Data Counter functions - * -@verbatim - =============================================================================== - ##### Data Counter functions ##### - =============================================================================== - [..] This subsection provides function allowing to configure and read the buffer - size (number of data to be transferred).The DMA data counter can be written - only when the DMA channel is disabled (ie. after transfer complete event). - [..] The following function can be used to write the Channel data counter value: - (+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber). - [..] - (@) It is advised to use this function rather than DMA_Init() in situations - where only the Data buffer needs to be reloaded. - [..] The DMA data counter can be read to indicate the number of remaining transfers - for the relative DMA channel. This counter is decremented at the end of each - data transfer and when the transfer is complete: - (+) If Normal mode is selected: the counter is set to 0. - (+) If Circular mode is selected: the counter is reloaded with the initial - value(configured before enabling the DMA channel). - [..] The following function can be used to read the Channel data counter value: - (+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx). - -@endverbatim - * @{ - */ - -/** - * @brief Sets the number of data units in the current DMAy Channelx transfer. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @param DataNumber: The number of data units in the current DMAy Channelx - * transfer. - * @note This function can only be used when the DMAy_Channelx is disabled. - * @retval None. - */ -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - -/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/ - /* Write to DMAy Channelx CNDTR */ - DMAy_Channelx->CNDTR = DataNumber; -} - -/** - * @brief Returns the number of remaining data units in the current - * DMAy Channelx transfer. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @retval The number of remaining data units in the current DMAy Channelx - * transfer. - */ -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - /* Return the number of remaining data units for DMAy Channelx */ - return ((uint16_t)(DMAy_Channelx->CNDTR)); -} - -/** - * @} - */ - -/** @defgroup DMA_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - [..] This subsection provides functions allowing to configure the DMA Interrupt - sources and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to manage - the DMA controller events: Polling mode or Interrupt mode. - - *** Polling Mode *** - ==================== - [..] Each DMA channel can be managed through 4 event Flags (y : DMA Controller - number, x : DMA channel number): - (#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred. - (#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred. - (#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred. - (#) DMAy_FLAG_GLx : to indicate that at least one of the events described - above occurred. - [..] - (@) Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the - same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx). - [..] In this Mode it is advised to use the following functions: - (+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG); - (+) void DMA_ClearFlag(uint32_t DMA_FLAG); - - *** Interrupt Mode *** - ====================== - [..] Each DMA channel can be managed through 4 Interrupts: - (+) Interrupt Source - (##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete - event. - (##) DMA_IT_HT: specifies the interrupt source for the Half-transfer Complete - event. - (##) DMA_IT_TE: specifies the interrupt source for the transfer errors event. - (##) DMA_IT_GL: to indicate that at least one of the interrupts described - above occurred. - -@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of - the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE). - [..] In this Mode it is advised to use the following functions: - (+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); - (+) ITStatus DMA_GetITStatus(uint32_t DMA_IT); - (+) void DMA_ClearITPendingBit(uint32_t DMA_IT); - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified DMAy Channelx interrupts. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @param DMA_IT: specifies the DMA interrupts sources to be enabled - * or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @param NewState: new state of the specified DMA interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - assert_param(IS_DMA_CONFIG_IT(DMA_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DMA interrupts */ - DMAy_Channelx->CCR |= DMA_IT; - } - else - { - /* Disable the selected DMA interrupts */ - DMAy_Channelx->CCR &= ~DMA_IT; - } -} - -/** - * @brief Checks whether the specified DMAy Channelx flag is set or not. - * @param DMAy_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. - * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. - * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. - * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. - * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. - * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. - * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. - * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. - * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. - * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. - * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. - * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. - * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. - * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. - * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. - * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. - * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. - * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. - * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. - * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. - * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. - * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. - * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. - * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. - * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. - * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. - * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. - * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. - * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. - * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. - * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. - * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. - * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. - * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. - * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. - * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. - * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. - * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. - * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. - * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. - * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. - * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. - * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. - * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. - * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. - * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. - * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. - * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. - * - * @note - * The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags - * relative to the same channel is set (Transfer Complete, Half-transfer - * Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or - * DMAy_FLAG_TEx). - * - * @retval The new state of DMAy_FLAG (SET or RESET). - */ -FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_GET_FLAG(DMAy_FLAG)); - - /* Calculate the used DMAy */ - if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) - { - /* Get DMA2 ISR register value */ - tmpreg = DMA2->ISR ; - } - else - { - /* Get DMA1 ISR register value */ - tmpreg = DMA1->ISR ; - } - - /* Check the status of the specified DMAy flag */ - if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET) - { - /* DMAy_FLAG is set */ - bitstatus = SET; - } - else - { - /* DMAy_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the DMAy_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Channelx's pending flags. - * @param DMAy_FLAG: specifies the flag to clear. - * This parameter can be any combination (for the same DMA) of the following values: - * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. - * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. - * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. - * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. - * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. - * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. - * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. - * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. - * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. - * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. - * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. - * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. - * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. - * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. - * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. - * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. - * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. - * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. - * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. - * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. - * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. - * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. - * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. - * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. - * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. - * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. - * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. - * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. - * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. - * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. - * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. - * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. - * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. - * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. - * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. - * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. - * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. - * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. - * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. - * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. - * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. - * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. - * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. - * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. - * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. - * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. - * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. - * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. - * - * @note - * Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags - * relative to the same channel (Transfer Complete, Half-transfer Complete and - * Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx). - * - * @retval None - */ -void DMA_ClearFlag(uint32_t DMAy_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG)); - -/* Calculate the used DMAy */ - if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) - { - /* Clear the selected DMAy flags */ - DMA2->IFCR = DMAy_FLAG; - } - else - { - /* Clear the selected DMAy flags */ - DMA1->IFCR = DMAy_FLAG; - } -} - -/** - * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not. - * @param DMAy_IT: specifies the DMAy interrupt source to check. - * This parameter can be one of the following values: - * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. - * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. - * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. - * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. - * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. - * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. - * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. - * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. - * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. - * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. - * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. - * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. - * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. - * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. - * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. - * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. - * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. - * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. - * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. - * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. - * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. - * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. - * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. - * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. - * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. - * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. - * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. - * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. - * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. - * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. - * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. - * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. - * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. - * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. - * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. - * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. - * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. - * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. - * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. - * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. - * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. - * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. - * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. - * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. - * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. - * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. - * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. - * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. - * - * @note - * The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other - * interrupts relative to the same channel is set (Transfer Complete, - * Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx, - * DMAy_IT_HTx or DMAy_IT_TEx). - * - * @retval The new state of DMAy_IT (SET or RESET). - */ -ITStatus DMA_GetITStatus(uint32_t DMAy_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_GET_IT(DMAy_IT)); - - /* Calculate the used DMA */ - if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) - { - /* Get DMA2 ISR register value */ - tmpreg = DMA2->ISR; - } - else - { - /* Get DMA1 ISR register value */ - tmpreg = DMA1->ISR; - } - - /* Check the status of the specified DMAy interrupt */ - if ((tmpreg & DMAy_IT) != (uint32_t)RESET) - { - /* DMAy_IT is set */ - bitstatus = SET; - } - else - { - /* DMAy_IT is reset */ - bitstatus = RESET; - } - /* Return the DMAy_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Channelx's interrupt pending bits. - * @param DMAy_IT: specifies the DMAy interrupt pending bit to clear. - * This parameter can be any combination (for the same DMA) of the following values: - * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. - * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. - * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. - * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. - * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. - * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. - * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. - * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. - * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. - * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. - * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. - * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. - * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. - * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. - * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. - * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. - * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. - * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. - * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. - * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. - * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. - * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. - * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. - * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. - * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. - * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. - * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. - * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. - * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. - * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. - * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. - * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. - * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. - * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. - * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. - * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. - * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. - * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. - * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. - * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. - * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. - * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. - * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. - * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. - * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. - * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. - * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. - * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. - * - * @note - * Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other - * interrupts relative to the same channel (Transfer Complete, Half-transfer - * Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and - * DMAy_IT_TEx). - * - * @retval None - */ -void DMA_ClearITPendingBit(uint32_t DMAy_IT) -{ - /* Check the parameters */ - assert_param(IS_DMA_CLEAR_IT(DMAy_IT)); - - /* Calculate the used DMAy */ - if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) - { - /* Clear the selected DMAy interrupt pending bits */ - DMA2->IFCR = DMAy_IT; - } - else - { - /* Clear the selected DMAy interrupt pending bits */ - DMA1->IFCR = DMAy_IT; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_dma.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,446 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_dma.h - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file contains all the functions prototypes for the DMA firmware - * library. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F30x_DMA_H -#define __STM32F30x_DMA_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief DMA Init structures definition - */ -typedef struct -{ - uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ - - uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ - - uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. - This parameter can be a value of @ref DMA_data_transfer_direction */ - - uint16_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. - The data unit is equal to the configuration set in DMA_PeripheralDataSize - or DMA_MemoryDataSize members depending in the transfer direction. */ - - uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. - This parameter can be a value of @ref DMA_peripheral_incremented_mode */ - - uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. - This parameter can be a value of @ref DMA_memory_incremented_mode */ - - uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_peripheral_data_size */ - - uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. - This parameter can be a value of @ref DMA_memory_data_size */ - - uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. - This parameter can be a value of @ref DMA_circular_normal_mode - @note: The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Channel */ - - uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. - This parameter can be a value of @ref DMA_priority_level */ - - uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. - This parameter can be a value of @ref DMA_memory_to_memory */ -}DMA_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Constants - * @{ - */ - -#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ - ((PERIPH) == DMA1_Channel2) || \ - ((PERIPH) == DMA1_Channel3) || \ - ((PERIPH) == DMA1_Channel4) || \ - ((PERIPH) == DMA1_Channel5) || \ - ((PERIPH) == DMA1_Channel6) || \ - ((PERIPH) == DMA1_Channel7) || \ - ((PERIPH) == DMA2_Channel1) || \ - ((PERIPH) == DMA2_Channel2) || \ - ((PERIPH) == DMA2_Channel3) || \ - ((PERIPH) == DMA2_Channel4) || \ - ((PERIPH) == DMA2_Channel5)) - -/** @defgroup DMA_data_transfer_direction - * @{ - */ - -#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) -#define DMA_DIR_PeripheralDST DMA_CCR_DIR - -#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \ - ((DIR) == DMA_DIR_PeripheralDST)) -/** - * @} - */ - - -/** @defgroup DMA_peripheral_incremented_mode - * @{ - */ - -#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) -#define DMA_PeripheralInc_Enable DMA_CCR_PINC - -#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \ - ((STATE) == DMA_PeripheralInc_Enable)) -/** - * @} - */ - -/** @defgroup DMA_memory_incremented_mode - * @{ - */ - -#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) -#define DMA_MemoryInc_Enable DMA_CCR_MINC - -#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \ - ((STATE) == DMA_MemoryInc_Enable)) -/** - * @} - */ - -/** @defgroup DMA_peripheral_data_size - * @{ - */ - -#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) -#define DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0 -#define DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1 - -#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ - ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ - ((SIZE) == DMA_PeripheralDataSize_Word)) -/** - * @} - */ - -/** @defgroup DMA_memory_data_size - * @{ - */ - -#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) -#define DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0 -#define DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1 - -#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ - ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ - ((SIZE) == DMA_MemoryDataSize_Word)) -/** - * @} - */ - -/** @defgroup DMA_circular_normal_mode - * @{ - */ - -#define DMA_Mode_Normal ((uint32_t)0x00000000) -#define DMA_Mode_Circular DMA_CCR_CIRC - -#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular)) -/** - * @} - */ - -/** @defgroup DMA_priority_level - * @{ - */ - -#define DMA_Priority_VeryHigh DMA_CCR_PL -#define DMA_Priority_High DMA_CCR_PL_1 -#define DMA_Priority_Medium DMA_CCR_PL_0 -#define DMA_Priority_Low ((uint32_t)0x00000000) - -#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ - ((PRIORITY) == DMA_Priority_High) || \ - ((PRIORITY) == DMA_Priority_Medium) || \ - ((PRIORITY) == DMA_Priority_Low)) -/** - * @} - */ - -/** @defgroup DMA_memory_to_memory - * @{ - */ - -#define DMA_M2M_Disable ((uint32_t)0x00000000) -#define DMA_M2M_Enable DMA_CCR_MEM2MEM - -#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable)) - -/** - * @} - */ - -/** @defgroup DMA_interrupts_definition - * @{ - */ - -#define DMA_IT_TC ((uint32_t)0x00000002) -#define DMA_IT_HT ((uint32_t)0x00000004) -#define DMA_IT_TE ((uint32_t)0x00000008) -#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) - -#define DMA1_IT_GL1 ((uint32_t)0x00000001) -#define DMA1_IT_TC1 ((uint32_t)0x00000002) -#define DMA1_IT_HT1 ((uint32_t)0x00000004) -#define DMA1_IT_TE1 ((uint32_t)0x00000008) -#define DMA1_IT_GL2 ((uint32_t)0x00000010) -#define DMA1_IT_TC2 ((uint32_t)0x00000020) -#define DMA1_IT_HT2 ((uint32_t)0x00000040) -#define DMA1_IT_TE2 ((uint32_t)0x00000080) -#define DMA1_IT_GL3 ((uint32_t)0x00000100) -#define DMA1_IT_TC3 ((uint32_t)0x00000200) -#define DMA1_IT_HT3 ((uint32_t)0x00000400) -#define DMA1_IT_TE3 ((uint32_t)0x00000800) -#define DMA1_IT_GL4 ((uint32_t)0x00001000) -#define DMA1_IT_TC4 ((uint32_t)0x00002000) -#define DMA1_IT_HT4 ((uint32_t)0x00004000) -#define DMA1_IT_TE4 ((uint32_t)0x00008000) -#define DMA1_IT_GL5 ((uint32_t)0x00010000) -#define DMA1_IT_TC5 ((uint32_t)0x00020000) -#define DMA1_IT_HT5 ((uint32_t)0x00040000) -#define DMA1_IT_TE5 ((uint32_t)0x00080000) -#define DMA1_IT_GL6 ((uint32_t)0x00100000) -#define DMA1_IT_TC6 ((uint32_t)0x00200000) -#define DMA1_IT_HT6 ((uint32_t)0x00400000) -#define DMA1_IT_TE6 ((uint32_t)0x00800000) -#define DMA1_IT_GL7 ((uint32_t)0x01000000) -#define DMA1_IT_TC7 ((uint32_t)0x02000000) -#define DMA1_IT_HT7 ((uint32_t)0x04000000) -#define DMA1_IT_TE7 ((uint32_t)0x08000000) - -#define DMA2_IT_GL1 ((uint32_t)0x10000001) -#define DMA2_IT_TC1 ((uint32_t)0x10000002) -#define DMA2_IT_HT1 ((uint32_t)0x10000004) -#define DMA2_IT_TE1 ((uint32_t)0x10000008) -#define DMA2_IT_GL2 ((uint32_t)0x10000010) -#define DMA2_IT_TC2 ((uint32_t)0x10000020) -#define DMA2_IT_HT2 ((uint32_t)0x10000040) -#define DMA2_IT_TE2 ((uint32_t)0x10000080) -#define DMA2_IT_GL3 ((uint32_t)0x10000100) -#define DMA2_IT_TC3 ((uint32_t)0x10000200) -#define DMA2_IT_HT3 ((uint32_t)0x10000400) -#define DMA2_IT_TE3 ((uint32_t)0x10000800) -#define DMA2_IT_GL4 ((uint32_t)0x10001000) -#define DMA2_IT_TC4 ((uint32_t)0x10002000) -#define DMA2_IT_HT4 ((uint32_t)0x10004000) -#define DMA2_IT_TE4 ((uint32_t)0x10008000) -#define DMA2_IT_GL5 ((uint32_t)0x10010000) -#define DMA2_IT_TC5 ((uint32_t)0x10020000) -#define DMA2_IT_HT5 ((uint32_t)0x10040000) -#define DMA2_IT_TE5 ((uint32_t)0x10080000) - -#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) - -#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ - ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ - ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ - ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ - ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ - ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ - ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ - ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ - ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ - ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ - ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ - ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ - ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ - ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ - ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \ - ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \ - ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \ - ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \ - ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \ - ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \ - ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \ - ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \ - ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \ - ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) - -/** - * @} - */ - -/** @defgroup DMA_flags_definition - * @{ - */ - -#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) -#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) -#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) -#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) -#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) -#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) -#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) -#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) -#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) -#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) -#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) -#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) -#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) -#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) -#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) -#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) -#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) -#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) -#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) -#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) -#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) -#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) -#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) -#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) -#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) -#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) -#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) -#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) - -#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) -#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) -#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) -#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) -#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) -#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) -#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) -#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) -#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) -#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) -#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) -#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) -#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) -#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) -#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) -#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) -#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) -#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) -#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) -#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) - -#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) - -#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ - ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ - ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ - ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ - ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ - ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ - ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ - ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ - ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ - ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ - ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ - ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ - ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ - ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \ - ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \ - ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \ - ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \ - ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \ - ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \ - ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \ - ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \ - ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \ - ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \ - ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the DMA configuration to the default reset state ******/ -void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); - -/* Initialization and Configuration functions *********************************/ -void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); -void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); - -/* Data Counter functions******************************************************/ -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); - -/* Interrupts and flags management functions **********************************/ -void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); -FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); -void DMA_ClearFlag(uint32_t DMAy_FLAG); -ITStatus DMA_GetITStatus(uint32_t DMAy_IT); -void DMA_ClearITPendingBit(uint32_t DMAy_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F30x_DMA_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_exti.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,359 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_exti.c - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the EXTI peripheral: - * + Initialization and Configuration - * + Interrupts and flags management - * - @verbatim - =============================================================================== - ##### EXTI features ##### - =============================================================================== - [..] External interrupt/event lines are mapped as following: - (#) All available GPIO pins are connected to the 16 external - interrupt/event lines from EXTI0 to EXTI15. - (#) EXTI line 16 is connected to the PVD output - (#) EXTI line 17 is connected to the RTC Alarm event - (#) EXTI line 18 is connected to USB Device wakeup event - (#) EXTI line 19 is connected to the RTC Tamper and TimeStamp events - (#) EXTI line 20 is connected to the RTC wakeup event - (#) EXTI line 21 is connected to the Comparator 1 wakeup event - (#) EXTI line 22 is connected to the Comparator 2 wakeup event - (#) EXTI line 23 is connected to the I2C1 wakeup event - (#) EXTI line 24 is connected to the I2C2 wakeup event - (#) EXTI line 25 is connected to the USART1 wakeup event - (#) EXTI line 26 is connected to the USART2 wakeup event - (#) EXTI line 27 is reserved - (#) EXTI line 28 is connected to the USART3 wakeup event - (#) EXTI line 29 is connected to the Comparator 3 event - (#) EXTI line 30 is connected to the Comparator 4 event - (#) EXTI line 31 is connected to the Comparator 5 event - (#) EXTI line 32 is connected to the Comparator 6 event - (#) EXTI line 33 is connected to the Comparator 7 event - (#) EXTI line 34 is connected for thr UART4 wakeup event - (#) EXTI line 35 is connected for the UART5 wakeup event - - ##### How to use this driver ##### - =============================================================================== - [..] In order to use an I/O pin as an external interrupt source, - follow steps below: - (#) Configure the I/O in input mode using GPIO_Init(). - (#) Select the input source pin for the EXTI line using - SYSCFG_EXTILineConfig(). - (#) Select the mode(interrupt, event) and configure the trigger - selection (Rising, falling or both) using EXTI_Init(). For the - internal interrupt, the trigger selection is not needed - (the active edge is always the rising one). - (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init(). - (#) Optionally, you can generate a software interrupt using the function - EXTI_GenerateSWInterrupt(). - [..] - (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx - registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - - @endverbatim - - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x_exti.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @defgroup EXTI - * @brief EXTI driver modules - * @{ - */ - - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup EXTI_Private_Functions - * @{ - */ - -/** @defgroup EXTI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the EXTI peripheral registers to their default reset - * values. - * @param None - * @retval None - */ -void EXTI_DeInit(void) -{ - EXTI->IMR = 0x1F800000; - EXTI->EMR = 0x00000000; - EXTI->RTSR = 0x00000000; - EXTI->FTSR = 0x00000000; - EXTI->SWIER = 0x00000000; - EXTI->PR = 0xE07FFFFF; - EXTI->IMR2 = 0x0000000C; - EXTI->EMR2 = 0x00000000; - EXTI->RTSR2 = 0x00000000; - EXTI->FTSR2 = 0x00000000; - EXTI->SWIER2 = 0x00000000; - EXTI->PR2 = 0x00000003; -} - -/** - * @brief Initializes the EXTI peripheral according to the specified - * parameters in the EXTI_InitStruct. - * EXTI_Line specifies the EXTI line (EXTI0....EXTI35). - * EXTI_Mode specifies which EXTI line is used as interrupt or an event. - * EXTI_Trigger selects the trigger. When the trigger occurs, interrupt - * pending bit will be set. - * EXTI_LineCmd controls (Enable/Disable) the EXTI line. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure that - * contains the configuration information for the EXTI peripheral. - * @retval None - */ - - -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); - assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); - assert_param(IS_EXTI_LINE_ALL(EXTI_InitStruct->EXTI_Line)); - assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); - - tmp = (uint32_t)EXTI_BASE; - - if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) - { - /* Clear EXTI line configuration */ - *(__IO uint32_t *) (((uint32_t) &(EXTI->IMR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F)); - *(__IO uint32_t *) (((uint32_t) &(EXTI->EMR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F)); - - tmp += EXTI_InitStruct->EXTI_Mode + (((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20); - - *(__IO uint32_t *) tmp |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F)); - - tmp = (uint32_t)EXTI_BASE; - - /* Clear Rising Falling edge configuration */ - *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F)); - *(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F)); - - /* Select the trigger for the selected interrupts */ - if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) - { - /* Rising Falling edge */ - *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F)); - *(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F)); - } - else - { - tmp += EXTI_InitStruct->EXTI_Trigger + (((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20); - - *(__IO uint32_t *) tmp |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F)); - } - } - - else - { - tmp += EXTI_InitStruct->EXTI_Mode + (((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20); - - /* Disable the selected external lines */ - *(__IO uint32_t *) tmp &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F)); - } - -} - -/** - * @brief Fills each EXTI_InitStruct member with its reset value. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) -{ - EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; - EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Rising_Falling; - EXTI_InitStruct->EXTI_LineCmd = DISABLE; -} - -/** - * @brief Generates a Software interrupt on selected EXTI line. - * @param EXTI_Line: specifies the EXTI line on which the software interrupt - * will be generated. - * This parameter can be any combination of EXTI_Linex where x can be (0..20). - * @retval None - */ -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE_EXT(EXTI_Line)); - - *(__IO uint32_t *) (((uint32_t) &(EXTI->SWIER)) + ((EXTI_Line) >> 5 ) * 0x20) |= (uint32_t)(1 << (EXTI_Line & 0x1F)); - -} - -/** - * @} - */ - -/** @defgroup EXTI_Group2 Interrupts and flags management functions - * @brief EXTI Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - [..] - This section provides functions allowing to configure the EXTI Interrupts - sources and check or clear the flags or pending bits status. - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified EXTI line flag is set or not. - * @param EXTI_Line: specifies the EXTI line flag to check. - * This parameter can be any combination of EXTI_Linex where x can be (0..20). - * @retval The new state of EXTI_Line (SET or RESET). - */ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - if ((*(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20)& (uint32_t)(1 << (EXTI_Line & 0x1F))) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the EXTI's line pending flags. - * @param EXTI_Line: specifies the EXTI lines flags to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..20). - * @retval None - */ -void EXTI_ClearFlag(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE_EXT(EXTI_Line)); - - *(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20) = (1 << (EXTI_Line & 0x1F)); -} - -/** - * @brief Checks whether the specified EXTI line is asserted or not. - * @param EXTI_Line: specifies the EXTI line to check. - * This parameter can be any combination of EXTI_Linex where x can be (0..20). - * @retval The new state of EXTI_Line (SET or RESET). - */ -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - if ((*(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20)& (uint32_t)(1 << (EXTI_Line & 0x1F))) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; - -} - -/** - * @brief Clears the EXTI's line pending bits. - * @param EXTI_Line: specifies the EXTI lines to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..20). - * @retval None - */ -void EXTI_ClearITPendingBit(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE_EXT(EXTI_Line)); - - *(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20) = (1 << (EXTI_Line & 0x1F)); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_exti.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,244 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_exti.h - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file contains all the functions prototypes for the EXTI - * firmware library. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F30x_EXTI_H -#define __STM32F30x_EXTI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup EXTI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief EXTI mode enumeration - */ - -typedef enum -{ - EXTI_Mode_Interrupt = 0x00, - EXTI_Mode_Event = 0x04 -}EXTIMode_TypeDef; - -#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) - -/** - * @brief EXTI Trigger enumeration - */ - -typedef enum -{ - EXTI_Trigger_Rising = 0x08, - EXTI_Trigger_Falling = 0x0C, - EXTI_Trigger_Rising_Falling = 0x10 -}EXTITrigger_TypeDef; - -#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ - ((TRIGGER) == EXTI_Trigger_Falling) || \ - ((TRIGGER) == EXTI_Trigger_Rising_Falling)) -/** - * @brief EXTI Init Structure definition - */ - -typedef struct -{ - uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. - This parameter can be any combination of @ref EXTI_Lines */ - - EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTITrigger_TypeDef */ - - FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ -}EXTI_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup EXTI_Exported_Constants - * @{ - */ -/** @defgroup EXTI_Lines - * @{ - */ - -#define EXTI_Line0 ((uint32_t)0x00) /*!< External interrupt line 0 */ -#define EXTI_Line1 ((uint32_t)0x01) /*!< External interrupt line 1 */ -#define EXTI_Line2 ((uint32_t)0x02) /*!< External interrupt line 2 */ -#define EXTI_Line3 ((uint32_t)0x03) /*!< External interrupt line 3 */ -#define EXTI_Line4 ((uint32_t)0x04) /*!< External interrupt line 4 */ -#define EXTI_Line5 ((uint32_t)0x05) /*!< External interrupt line 5 */ -#define EXTI_Line6 ((uint32_t)0x06) /*!< External interrupt line 6 */ -#define EXTI_Line7 ((uint32_t)0x07) /*!< External interrupt line 7 */ -#define EXTI_Line8 ((uint32_t)0x08) /*!< External interrupt line 8 */ -#define EXTI_Line9 ((uint32_t)0x09) /*!< External interrupt line 9 */ -#define EXTI_Line10 ((uint32_t)0x0A) /*!< External interrupt line 10 */ -#define EXTI_Line11 ((uint32_t)0x0B) /*!< External interrupt line 11 */ -#define EXTI_Line12 ((uint32_t)0x0C) /*!< External interrupt line 12 */ -#define EXTI_Line13 ((uint32_t)0x0D) /*!< External interrupt line 13 */ -#define EXTI_Line14 ((uint32_t)0x0E) /*!< External interrupt line 14 */ -#define EXTI_Line15 ((uint32_t)0x0F) /*!< External interrupt line 15 */ -#define EXTI_Line16 ((uint32_t)0x10) /*!< External interrupt line 16 - Connected to the PVD Output */ -#define EXTI_Line17 ((uint32_t)0x11) /*!< Internal interrupt line 17 - Connected to the RTC Alarm - event */ -#define EXTI_Line18 ((uint32_t)0x12) /*!< Internal interrupt line 18 - Connected to the USB Device - Wakeup from suspend event */ -#define EXTI_Line19 ((uint32_t)0x13) /*!< Internal interrupt line 19 - Connected to the RTC Tamper - and Time Stamp events */ -#define EXTI_Line20 ((uint32_t)0x14) /*!< Internal interrupt line 20 - Connected to the RTC wakeup - event */ -#define EXTI_Line21 ((uint32_t)0x15) /*!< Internal interrupt line 21 - Connected to the Comparator 1 - event */ -#define EXTI_Line22 ((uint32_t)0x16) /*!< Internal interrupt line 22 - Connected to the Comparator 2 - event */ -#define EXTI_Line23 ((uint32_t)0x17) /*!< Internal interrupt line 23 - Connected to the I2C1 wakeup - event */ -#define EXTI_Line24 ((uint32_t)0x18) /*!< Internal interrupt line 24 - Connected to the I2C2 wakeup - event */ -#define EXTI_Line25 ((uint32_t)0x19) /*!< Internal interrupt line 25 - Connected to the USART1 wakeup - event */ -#define EXTI_Line26 ((uint32_t)0x1A) /*!< Internal interrupt line 26 - Connected to the USART2 wakeup - event */ -#define EXTI_Line27 ((uint32_t)0x1B) /*!< Internal interrupt line 27 - reserved */ -#define EXTI_Line28 ((uint32_t)0x1C) /*!< Internal interrupt line 28 - Connected to the USART3 wakeup - event */ -#define EXTI_Line29 ((uint32_t)0x1D) /*!< Internal interrupt line 29 - Connected to the Comparator 3 - event */ -#define EXTI_Line30 ((uint32_t)0x1E) /*!< Internal interrupt line 30 - Connected to the Comparator 4 - event */ -#define EXTI_Line31 ((uint32_t)0x1F) /*!< Internal interrupt line 31 - Connected to the Comparator 5 - event */ -#define EXTI_Line32 ((uint32_t)0x20) /*!< Internal interrupt line 32 - Connected to the Comparator 6 - event */ -#define EXTI_Line33 ((uint32_t)0x21) /*!< Internal interrupt line 33 - Connected to the Comparator 7 - event */ -#define EXTI_Line34 ((uint32_t)0x22) /*!< Internal interrupt line 34 - Connected to the USART4 wakeup - event */ -#define EXTI_Line35 ((uint32_t)0x23) /*!< Internal interrupt line 35 - Connected to the USART5 wakeup - event */ - -#define IS_EXTI_LINE_ALL(LINE) ((LINE) <= 0x23) -#define IS_EXTI_LINE_EXT(LINE) (((LINE) <= 0x16) || (((LINE) == EXTI_Line29) || ((LINE) == EXTI_Line30) || \ - ((LINE) == EXTI_Line31) || ((LINE) == EXTI_Line32) || ((LINE) == EXTI_Line33))) - -#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ - ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ - ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ - ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ - ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ - ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ - ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ - ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ - ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ - ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \ - ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \ - ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line29) || \ - ((LINE) == EXTI_Line30) || ((LINE) == EXTI_Line31) || \ - ((LINE) == EXTI_Line32) || ((LINE) == EXTI_Line33)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -/* Function used to set the EXTI configuration to the default reset state *****/ -void EXTI_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); - -/* Interrupts and flags management functions **********************************/ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); -void EXTI_ClearFlag(uint32_t EXTI_Line); -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); -void EXTI_ClearITPendingBit(uint32_t EXTI_Line); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F30x_EXTI_H */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_flash.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1180 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_flash.c - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the FLASH peripheral: - * + FLASH Interface configuration - * + FLASH Memory Programming - * + Option Bytes Programming - * + Interrupts and flags management - * - @verbatim - - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] This driver provides functions to configure and program the FLASH - memory of all STM32F30x devices. These functions are split in 4 groups: - (#) FLASH Interface configuration functions: this group includes the - management of following features: - (++) Set the latency. - (++) Enable/Disable the Half Cycle Access. - (++) Enable/Disable the prefetch buffer. - (#) FLASH Memory Programming functions: this group includes all needed - functions to erase and program the main memory: - (++) Lock and Unlock the FLASH interface. - (++) Erase function: Erase page, erase all pages. - (++) Program functions: Half Word and Word write. - (#) FLASH Option Bytes Programming functions: this group includes all - needed functions to manage the Option Bytes: - (++) Lock and Unlock the Flash Option bytes. - (++) Launch the Option Bytes loader - (++) Erase the Option Bytes - (++) Set/Reset the write protection - (++) Set the Read protection Level - (++) Program the user option Bytes - (++) Set/Reset the BOOT1 bit - (++) Enable/Disable the VDDA Analog Monitoring - (++) Enable/Disable the SRAM parity - (++) Get the user option bytes - (++) Get the Write protection - (++) Get the read protection status - (#) FLASH Interrupts and flags management functions: this group includes - all needed functions to: - (++) Enable/Disable the FLASH interrupt sources. - (++) Get flags status. - (++) Clear flags. - (++) Get FLASH operation status. - (++) Wait for last FLASH operation. - - @endverbatim - - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x_flash.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @defgroup FLASH - * @brief FLASH driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* FLASH Mask */ -#define RDPRT_MASK ((uint32_t)0x00000002) -#define WRP01_MASK ((uint32_t)0x0000FFFF) -#define WRP23_MASK ((uint32_t)0xFFFF0000) -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup FLASH_Private_Functions - * @{ - */ - -/** @defgroup FLASH_Group1 FLASH Interface configuration functions - * @brief FLASH Interface configuration functions - * - -@verbatim - =============================================================================== - ##### FLASH Interface configuration functions ##### - =============================================================================== - [..] This group includes the following functions: - (+) void FLASH_SetLatency(uint32_t FLASH_Latency); - (+) void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess); - (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState); - [..] The unlock sequence is not needed for these functions. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the code latency value. - * @param FLASH_Latency: specifies the FLASH Latency value. - * This parameter can be one of the following values: - * @arg FLASH_Latency_0: FLASH Zero Latency cycle - * @arg FLASH_Latency_1: FLASH One Latency cycle - * @arg FLASH_Latency_2: FLASH Two Latency cycles - * @retval None - */ -void FLASH_SetLatency(uint32_t FLASH_Latency) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_LATENCY(FLASH_Latency)); - - /* Read the ACR register */ - tmpreg = FLASH->ACR; - - /* Sets the Latency value */ - tmpreg &= (uint32_t) (~((uint32_t)FLASH_ACR_LATENCY)); - tmpreg |= FLASH_Latency; - - /* Write the ACR register */ - FLASH->ACR = tmpreg; -} - -/** - * @brief Enables or disables the Half cycle flash access. - * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode. - * This parameter can be one of the following values: - * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable - * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable - * @retval None - */ -void FLASH_HalfCycleAccessCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - FLASH->ACR |= FLASH_ACR_HLFCYA; - } - else - { - FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_HLFCYA)); - } -} - -/** - * @brief Enables or disables the Prefetch Buffer. - * @param NewState: new state of the Prefetch Buffer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_PrefetchBufferCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - FLASH->ACR |= FLASH_ACR_PRFTBE; - } - else - { - FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_PRFTBE)); - } -} - -/** - * @} - */ - -/** @defgroup FLASH_Group2 FLASH Memory Programming functions - * @brief FLASH Memory Programming functions - * -@verbatim - =============================================================================== - ##### FLASH Memory Programming functions ##### - =============================================================================== - [..] This group includes the following functions: - (+) void FLASH_Unlock(void); - (+) void FLASH_Lock(void); - (+) FLASH_Status FLASH_ErasePage(uint32_t Page_Address); - (+) FLASH_Status FLASH_EraseAllPages(void); - (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); - (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); - [..] Any operation of erase or program should follow these steps: - (#) Call the FLASH_Unlock() function to enable the FLASH control register - program memory access. - (#) Call the desired function to erase page or program data. - (#) Call the FLASH_Lock() function to disable the FLASH control register - access (recommended to protect the FLASH memory against possible - unwanted operation). - -@endverbatim - * @{ - */ - -/** - * @brief Unlocks the FLASH control register access - * @param None - * @retval None - */ -void FLASH_Unlock(void) -{ - if((FLASH->CR & FLASH_CR_LOCK) != RESET) - { - /* Authorize the FLASH Registers access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; - } -} - -/** - * @brief Locks the FLASH control register access - * @param None - * @retval None - */ -void FLASH_Lock(void) -{ - /* Set the LOCK Bit to lock the FLASH Registers access */ - FLASH->CR |= FLASH_CR_LOCK; -} - -/** - * @brief Erases a specified page in program memory. - * @note To correctly run this function, the FLASH_Unlock() function - * must be called before. - * @note Call the FLASH_Lock() to disable the flash memory access - * (recommended to protect the FLASH memory against possible unwanted operation) - * @param Page_Address: The page address in program memory to be erased. - * @note A Page is erased in the Program memory only if the address to load - * is the start address of a page (multiple of 1024 bytes). - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ErasePage(uint32_t Page_Address) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_PROGRAM_ADDRESS(Page_Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the previous operation is completed, proceed to erase the page */ - FLASH->CR |= FLASH_CR_PER; - FLASH->AR = Page_Address; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - /* Disable the PER Bit */ - FLASH->CR &= ~FLASH_CR_PER; - } - - /* Return the Erase Status */ - return status; -} - -/** - * @brief Erases all FLASH pages. - * @note To correctly run this function, the FLASH_Unlock() function - * must be called before. - * all the FLASH_Lock() to disable the flash memory access - * (recommended to protect the FLASH memory against possible unwanted operation) - * @param None - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseAllPages(void) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all pages */ - FLASH->CR |= FLASH_CR_MER; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - /* Disable the MER Bit */ - FLASH->CR &= ~FLASH_CR_MER; - } - - /* Return the Erase Status */ - return status; -} - -/** - * @brief Programs a word at a specified address. - * @note To correctly run this function, the FLASH_Unlock() function - * must be called before. - * Call the FLASH_Lock() to disable the flash memory access - * (recommended to protect the FLASH memory against possible unwanted operation) - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the previous operation is completed, proceed to program the new first - half word */ - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint16_t*)Address = (uint16_t)Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the previous operation is completed, proceed to program the new second - half word */ - tmp = Address + 2; - - *(__IO uint16_t*) tmp = Data >> 16; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - /* Disable the PG Bit */ - FLASH->CR &= ~FLASH_CR_PG; - } - else - { - /* Disable the PG Bit */ - FLASH->CR &= ~FLASH_CR_PG; - } - } - - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a half word at a specified address. - * @note To correctly run this function, the FLASH_Unlock() function - * must be called before. - * Call the FLASH_Lock() to disable the flash memory access - * (recommended to protect the FLASH memory against possible unwanted operation) - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the previous operation is completed, proceed to program the new data */ - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint16_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - /* Disable the PG Bit */ - FLASH->CR &= ~FLASH_CR_PG; - } - - /* Return the Program Status */ - return status; -} - -/** - * @} - */ - -/** @defgroup FLASH_Group3 Option Bytes Programming functions - * @brief Option Bytes Programming functions - * -@verbatim - =============================================================================== - ##### Option Bytes Programming functions ##### - =============================================================================== - [..] This group includes the following functions: - (+) void FLASH_OB_Unlock(void); - (+) void FLASH_OB_Lock(void); - (+) void FLASH_OB_Erase(void); - (+) FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); - (+) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP); - (+) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); - (+) FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1); - (+) FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG); - (+) FLASH_Status FLASH_OB_SRMParityConfig(uint8_t OB_SRAM_Parity); - (+) FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER); - (+) FLASH_Status FLASH_OB_Launch(void); - (+) uint32_t FLASH_OB_GetUser(void); - (+) uint8_t FLASH_OB_GetWRP(void); - (+) uint8_t FLASH_OB_GetRDP(void); - [..] Any operation of erase or program should follow these steps: - (#) Call the FLASH_OB_Unlock() function to enable the FLASH option control - register access. - (#) Call one or several functions to program the desired Option Bytes: - (++) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); - => to Enable/Disable the desired sector write protection. - (++) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the - desired read Protection Level. - (++) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); - => to configure the user Option Bytes. - (++) FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1); - => to set the boot1 mode - (++) FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG); - => to Enable/Disable the VDDA monotoring. - (++) FLASH_Status FLASH_OB_SRMParityConfig(uint8_t OB_SRAM_Parity); - => to Enable/Disable the SRAM Parity check. - (++) FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER); - => to write all user option bytes: OB_IWDG, OB_STOP, OB_STDBY, - OB_BOOT1, OB_VDDA_ANALOG and OB_VDD_SD12. - (#) Once all needed Option Bytes to be programmed are correctly written, - call the FLASH_OB_Launch() function to launch the Option Bytes - programming process. - (#@) When changing the IWDG mode from HW to SW or from SW to HW, a system - reset is needed to make the change effective. - (#) Call the FLASH_OB_Lock() function to disable the FLASH option control - register access (recommended to protect the Option Bytes against - possible unwanted operations). - -@endverbatim - * @{ - */ - -/** - * @brief Unlocks the option bytes block access. - * @param None - * @retval None - */ -void FLASH_OB_Unlock(void) -{ - if((FLASH->CR & FLASH_CR_OPTWRE) == RESET) - { - /* Unlocking the option bytes block access */ - FLASH->OPTKEYR = FLASH_OPTKEY1; - FLASH->OPTKEYR = FLASH_OPTKEY2; - } -} - -/** - * @brief Locks the option bytes block access. - * @param None - * @retval None - */ -void FLASH_OB_Lock(void) -{ - /* Set the OPTWREN Bit to lock the option bytes block access */ - FLASH->CR &= ~FLASH_CR_OPTWRE; -} - -/** - * @brief Launch the option byte loading. - * @param None - * @retval None - */ -void FLASH_OB_Launch(void) -{ - /* Set the OBL_Launch bit to launch the option byte loading */ - FLASH->CR |= FLASH_CR_OBL_LAUNCH; -} - -/** - * @brief Erases the FLASH option bytes. - * @note This functions erases all option bytes except the Read protection (RDP). - * @param None - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_OB_Erase(void) -{ - uint16_t rdptmp = OB_RDP_Level_0; - - FLASH_Status status = FLASH_COMPLETE; - - /* Get the actual read protection Option Byte value */ - if(FLASH_OB_GetRDP() != RESET) - { - rdptmp = 0x00; - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the previous operation is completed, proceed to erase the option bytes */ - FLASH->CR |= FLASH_CR_OPTER; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the erase operation is completed, disable the OPTER Bit */ - FLASH->CR &= ~FLASH_CR_OPTER; - - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - /* Restore the last read protection Option Byte value */ - OB->RDP = (uint16_t)rdptmp; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - else - { - if (status != FLASH_TIMEOUT) - { - /* Disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - } - /* Return the erase status */ - return status; -} - -/** - * @brief Write protects the desired pages - * @note To correctly run this function, the FLASH_OB_Unlock() function - * must be called before. - * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes - * (recommended to protect the FLASH memory against possible unwanted operation) - * @param OB_WRP: specifies the address of the pages to be write protected. - * This parameter can be: - * @arg value between OB_WRP_Pages0to35 and OB_WRP_Pages60to63 - * @arg OB_WRP_AllPages - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP) -{ - uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF; - - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_WRP(OB_WRP)); - - OB_WRP = (uint32_t)(~OB_WRP); - WRP0_Data = (uint16_t)(OB_WRP & OB_WRP0_WRP0); - WRP1_Data = (uint16_t)((OB_WRP & OB_WRP0_nWRP0) >> 8); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - FLASH->CR |= FLASH_CR_OPTPG; - - if(WRP0_Data != 0xFF) - { - OB->WRP0 = WRP0_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - } - if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF)) - { - OB->WRP1 = WRP1_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - } - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - /* Return the write protection operation Status */ - return status; -} - -/** - * @brief Enables or disables the read out protection. - * @note To correctly run this function, the FLASH_OB_Unlock() function - * must be called before. - * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes - * (recommended to protect the FLASH memory against possible unwanted operation) - * @param FLASH_ReadProtection_Level: specifies the read protection level. - * This parameter can be: - * @arg OB_RDP_Level_0: No protection - * @arg OB_RDP_Level_1: Read protection of the memory - * @arg OB_RDP_Level_2: Chip protection - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_RDP(OB_RDP)); - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - FLASH->CR |= FLASH_CR_OPTER; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the erase operation is completed, disable the OPTER Bit */ - FLASH->CR &= ~FLASH_CR_OPTER; - - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - OB->RDP = OB_RDP; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - else - { - if(status != FLASH_TIMEOUT) - { - /* Disable the OPTER Bit */ - FLASH->CR &= ~FLASH_CR_OPTER; - } - } - } - /* Return the protection operation Status */ - return status; -} - -/** - * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @param OB_IWDG: Selects the IWDG mode - * This parameter can be one of the following values: - * @arg OB_IWDG_SW: Software IWDG selected - * @arg OB_IWDG_HW: Hardware IWDG selected - * @param OB_STOP: Reset event when entering STOP mode. - * This parameter can be one of the following values: - * @arg OB_STOP_NoRST: No reset generated when entering in STOP - * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param OB_STDBY: Reset event when entering Standby mode. - * This parameter can be one of the following values: - * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY - * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); - assert_param(IS_OB_STOP_SOURCE(OB_STOP)); - assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); - - /* Authorize the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - OB->USER = (uint8_t)((uint8_t)(OB_IWDG | OB_STOP) | (uint8_t)(OB_STDBY |0xF8)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - /* Return the Option Byte program Status */ - return status; -} - -/** - * @brief Sets or resets the BOOT1. - * @param OB_BOOT1: Set or Reset the BOOT1. - * This parameter can be one of the following values: - * @arg OB_BOOT1_RESET: BOOT1 Reset - * @arg OB_BOOT1_SET: BOOT1 Set - * @retval None - */ -FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_BOOT1(OB_BOOT1)); - - /* Authorize the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - OB->USER = OB_BOOT1|0xEF; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - /* Return the Option Byte program Status */ - return status; -} - -/** - * @brief Sets or resets the analogue monitoring on VDDA Power source. - * @param OB_VDDA_ANALOG: Selects the analog monitoring on VDDA Power source. - * This parameter can be one of the following values: - * @arg OB_VDDA_ANALOG_ON: Analog monitoring on VDDA Power source ON - * @arg OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source OFF - * @retval None - */ -FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_VDDA_ANALOG(OB_VDDA_ANALOG)); - - /* Authorize the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - OB->USER = OB_VDDA_ANALOG |0xDF; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - /* Return the Option Byte program Status */ - return status; -} - -/** - * @brief Sets or resets the SRAM partiy. - * @param OB_SRAM_Parity: Set or Reset the SRAM partiy enable bit. - * This parameter can be one of the following values: - * @arg OB_SRAM_PARITY_SET: Set SRAM partiy. - * @arg OB_SRAM_PARITY_RESET: Reset SRAM partiy. - * @retval None - */ -FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_SRAM_PARITY(OB_SRAM_Parity)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - OB->USER = OB_SRAM_Parity | 0xBF; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - /* Return the Option Byte program Status */ - return status; -} - -/** - * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY/ BOOT1 and OB_VDDA_ANALOG. - * @note To correctly run this function, the FLASH_OB_Unlock() function - * must be called before. - * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes - * (recommended to protect the FLASH memory against possible unwanted operation) - * @param OB_USER: Selects all user option bytes - * This parameter is a combination of the following values: - * @arg OB_IWDG_SW / OB_IWDG_HW: Software / Hardware WDG selected - * @arg OB_STOP_NoRST / OB_STOP_RST: No reset / Reset generated when entering in STOP - * @arg OB_STDBY_NoRST / OB_STDBY_RST: No reset / Reset generated when entering in STANDBY - * @arg OB_BOOT1_RESET / OB_BOOT1_SET: BOOT1 Reset / Set - * @arg OB_VDDA_ANALOG_ON / OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source ON / OFF - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Authorize the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - OB->USER = OB_USER | 0x88; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - /* Return the Option Byte program Status */ - return status; - -} - -/** - * @brief Programs a half word at a specified Option Byte Data address. - * @note To correctly run this function, the FLASH_OB_Unlock() function - * must be called before. - * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes - * (recommended to protect the FLASH memory against possible unwanted operation) - * @param Address: specifies the address to be programmed. - * This parameter can be 0x1FFFF804 or 0x1FFFF806. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Check the parameters */ - assert_param(IS_OB_DATA_ADDRESS(Address)); - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* Enables the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - *(__IO uint16_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* If the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - /* Return the Option Byte Data Program Status */ - return status; -} - -/** - * @brief Returns the FLASH User Option Bytes values. - * @param None - * @retval The FLASH User Option Bytes . - */ -uint8_t FLASH_OB_GetUser(void) -{ - /* Return the User Option Byte */ - return (uint8_t)(FLASH->OBR >> 8); -} - -/** - * @brief Returns the FLASH Write Protection Option Bytes value. - * @param None - * @retval The FLASH Write Protection Option Bytes value - */ -uint32_t FLASH_OB_GetWRP(void) -{ - /* Return the FLASH write protection Register value */ - return (uint32_t)(FLASH->WRPR); -} - -/** - * @brief Checks whether the FLASH Read out Protection Status is set or not. - * @param None - * @retval FLASH ReadOut Protection Status(SET or RESET) - */ -FlagStatus FLASH_OB_GetRDP(void) -{ - FlagStatus readstatus = RESET; - - if ((uint8_t)(FLASH->OBR & (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2)) != RESET) - { - readstatus = SET; - } - else - { - readstatus = RESET; - } - return readstatus; -} - -/** - * @} - */ - -/** @defgroup FLASH_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified FLASH interrupts. - * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or - * disabled. - * This parameter can be any combination of the following values: - * @arg FLASH_IT_EOP: FLASH end of programming Interrupt - * @arg FLASH_IT_ERR: FLASH Error Interrupt - * @retval None - */ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FLASH_IT(FLASH_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - /* Enable the interrupt sources */ - FLASH->CR |= FLASH_IT; - } - else - { - /* Disable the interrupt sources */ - FLASH->CR &= ~(uint32_t)FLASH_IT; - } -} - -/** - * @brief Checks whether the specified FLASH flag is set or not. - * @param FLASH_FLAG: specifies the FLASH flag to check. - * This parameter can be one of the following values: - * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag - * @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_EOP: FLASH End of Programming flag - * @retval The new state of FLASH_FLAG (SET or RESET). - */ -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)); - - if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the new state of FLASH_FLAG (SET or RESET) */ - return bitstatus; -} - -/** - * @brief Clears the FLASH's pending flags. - * @param FLASH_FLAG: specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_EOP: FLASH End of Programming flag - * @retval None - */ -void FLASH_ClearFlag(uint32_t FLASH_FLAG) -{ - /* Check the parameters */ - assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)); - - /* Clear the flags */ - FLASH->SR = FLASH_FLAG; -} - -/** - * @brief Returns the FLASH Status. - * @param None - * @retval FLASH Status: The returned value can be: - * FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_GetStatus(void) -{ - FLASH_Status FLASHstatus = FLASH_COMPLETE; - - if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) - { - FLASHstatus = FLASH_BUSY; - } - else - { - if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00) - { - FLASHstatus = FLASH_ERROR_WRP; - } - else - { - if((FLASH->SR & (uint32_t)(FLASH_SR_PGERR)) != (uint32_t)0x00) - { - FLASHstatus = FLASH_ERROR_PROGRAM; - } - else - { - FLASHstatus = FLASH_COMPLETE; - } - } - } - /* Return the FLASH Status */ - return FLASHstatus; -} - -/** - * @brief Waits for a FLASH operation to complete or a TIMEOUT to occur. - * @param Timeout: FLASH programming Timeout - * @retval FLASH Status: The returned value can be: FLASH_BUSY, - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check for the FLASH Status */ - status = FLASH_GetStatus(); - - /* Wait for a FLASH operation to complete or a TIMEOUT to occur */ - while((status == FLASH_BUSY) && (Timeout != 0x00)) - { - status = FLASH_GetStatus(); - Timeout--; - } - - if(Timeout == 0x00 ) - { - status = FLASH_TIMEOUT; - } - /* Return the operation status */ - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_flash.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,339 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_flash.h - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file contains all the functions prototypes for the FLASH - * firmware library. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F30x_FLASH_H -#define __STM32F30x_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** - * @brief FLASH Status - */ -typedef enum -{ - FLASH_BUSY = 1, - FLASH_ERROR_WRP, - FLASH_ERROR_PROGRAM, - FLASH_COMPLETE, - FLASH_TIMEOUT -}FLASH_Status; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup FLASH_Exported_Constants - * @{ - */ - -/** @defgroup Flash_Latency - * @{ - */ -#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */ -#define FLASH_Latency_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */ -#define FLASH_Latency_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */ - -#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ - ((LATENCY) == FLASH_Latency_1) || \ - ((LATENCY) == FLASH_Latency_2)) -/** - * @} - */ - -/** @defgroup FLASH_Interrupts - * @{ - */ - -#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of programming interrupt source */ -#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error interrupt source */ -#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) -/** - * @} - */ -/** @defgroup FLASH_Address - * @{ - */ - -#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF)) - -/** - * @} - */ - -/** @defgroup FLASH_OB_DATA_ADDRESS - * @{ - */ -#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) - -/** - * @} - */ - -/** @defgroup Option_Bytes_Write_Protection - * @{ - */ - -#define OB_WRP_Pages0to1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */ -#define OB_WRP_Pages2to3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */ -#define OB_WRP_Pages4to5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */ -#define OB_WRP_Pages6to7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */ -#define OB_WRP_Pages8to9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */ -#define OB_WRP_Pages10to11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */ -#define OB_WRP_Pages12to13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */ -#define OB_WRP_Pages14to15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */ -#define OB_WRP_Pages16to17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */ -#define OB_WRP_Pages18to19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */ -#define OB_WRP_Pages20to21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */ -#define OB_WRP_Pages22to23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */ -#define OB_WRP_Pages24to25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */ -#define OB_WRP_Pages26to27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */ -#define OB_WRP_Pages28to29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */ -#define OB_WRP_Pages30to31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */ -#define OB_WRP_Pages32to33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */ -#define OB_WRP_Pages34to35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */ -#define OB_WRP_Pages36to37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */ -#define OB_WRP_Pages38to39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */ -#define OB_WRP_Pages40to41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */ -#define OB_WRP_Pages42to43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */ -#define OB_WRP_Pages44to45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */ -#define OB_WRP_Pages46to47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */ -#define OB_WRP_Pages48to49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */ -#define OB_WRP_Pages50to51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */ -#define OB_WRP_Pages52to53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */ -#define OB_WRP_Pages54to55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */ -#define OB_WRP_Pages56to57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */ -#define OB_WRP_Pages58to59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */ -#define OB_WRP_Pages60to61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */ -#define OB_WRP_Pages62to127 ((uint32_t)0x80000000) /* Write protection of page 62 to 127 */ - -#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */ - -#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000)) - -/** - * @} - */ - -/** @defgroup Option_Bytes_Read_Protection - * @{ - */ - -/** - * @brief Read Protection Level - */ -#define OB_RDP_Level_0 ((uint8_t)0xAA) -#define OB_RDP_Level_1 ((uint8_t)0xBB) -/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2 - it's no more possible to go back to level 1 or 0 */ - -#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\ - ((LEVEL) == OB_RDP_Level_1))/*||\ - ((LEVEL) == OB_RDP_Level_2))*/ -/** - * @} - */ - -/** @defgroup Option_Bytes_IWatchdog - * @{ - */ - -#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */ -#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ -#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) - -/** - * @} - */ - -/** @defgroup Option_Bytes_nRST_STOP - * @{ - */ - -#define OB_STOP_NoRST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ -#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) - -/** - * @} - */ - -/** @defgroup Option_Bytes_nRST_STDBY - * @{ - */ - -#define OB_STDBY_NoRST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ -#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) - -/** - * @} - */ -/** @defgroup Option_Bytes_BOOT1 - * @{ - */ - -#define OB_BOOT1_RESET ((uint8_t)0x00) /*!< BOOT1 Reset */ -#define OB_BOOT1_SET ((uint8_t)0x10) /*!< BOOT1 Set */ -#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET)) - -/** - * @} - */ -/** @defgroup Option_Bytes_VDDA_Analog_Monitoring - * @{ - */ - -#define OB_VDDA_ANALOG_ON ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source ON */ -#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */ - -#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF)) - -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_SRAM_Parity_Enable - * @{ - */ - -#define OB_SRAM_PARITY_SET ((uint8_t)0x00) /*!< SRAM parity enable Set */ -#define OB_SRAM_PARITY_RESET ((uint8_t)0x40) /*!< SRAM parity enable reset */ - -#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET)) - -/** - * @} - */ - -/** @defgroup FLASH_Flags - * @{ - */ - -#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ -#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */ -#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */ - -#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCB) == 0x00000000) && ((FLAG) != 0x00000000)) - -#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PGERR) || \ - ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP)) -/** - * @} - */ -/** @defgroup Timeout_definition - * @{ - */ -#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x000B0000) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* FLASH Interface configuration functions ************************************/ -void FLASH_SetLatency(uint32_t FLASH_Latency); -void FLASH_HalfCycleAccessCmd(FunctionalState NewState); -void FLASH_PrefetchBufferCmd(FunctionalState NewState); - -/* FLASH Memory Programming functions *****************************************/ -void FLASH_Unlock(void); -void FLASH_Lock(void); -FLASH_Status FLASH_ErasePage(uint32_t Page_Address); -FLASH_Status FLASH_EraseAllPages(void); -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); - -/* Option Bytes Programming functions *****************************************/ -void FLASH_OB_Unlock(void); -void FLASH_OB_Lock(void); -void FLASH_OB_Launch(void); -FLASH_Status FLASH_OB_Erase(void); -FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP); -FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP); -FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); -FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1); -FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG); -FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity); -FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER); -FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); -uint8_t FLASH_OB_GetUser(void); -uint32_t FLASH_OB_GetWRP(void); -FlagStatus FLASH_OB_GetRDP(void); - -/* Interrupts and flags management functions **********************************/ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); -void FLASH_ClearFlag(uint32_t FLASH_FLAG); -FLASH_Status FLASH_GetStatus(void); -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F30x_FLASH_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_gpio.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,545 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_gpio.c - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the GPIO peripheral: - * + Initialization and Configuration functions - * + GPIO Read and Write functions - * + GPIO Alternate functions configuration functions - * - * @verbatim - - - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd() - (#) Configure the GPIO pin(s) using GPIO_Init() - Four possible configuration are available for each pin: - (++) Input: Floating, Pull-up, Pull-down. - (++) Output: Push-Pull (Pull-up, Pull-down or no Pull), - Open Drain (Pull-up, Pull-down or no Pull). - In output mode, the speed is configurable: Low, Medium, Fast or High. - (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull), - Open Drain (Pull-up, Pull-down or no Pull). - (++) Analog: required mode when a pin is to be used as ADC channel, - DAC output or comparator input. - (#) Peripherals alternate function: - (++) For ADC, DAC and comparators, configure the desired pin in - analog mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN - (++) For other peripherals (TIM, USART...): - (+++) Connect the pin to the desired peripherals' Alternate - Function (AF) using GPIO_PinAFConfig() function. - (+++) Configure the desired pin in alternate function mode using - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - (+++) Select the type, pull-up/pull-down and output speed via - GPIO_PuPd, GPIO_OType and GPIO_Speed members. - (+++) Call GPIO_Init() function. - (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit() - (#) To set/reset the level of a pin configured in output mode use - GPIO_SetBits()/GPIO_ResetBits() - (#) During and just after reset, the alternate functions are not active - and the GPIO pins are configured in input floating mode (except JTAG pins). - (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as - general-purpose (PC14 and PC15, respectively) when the LSE - oscillator is off. The LSE has priority over the GPIO function. - (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose - (PF0 and PF1 respectively) when the HSE oscillator is off. The HSE has - the priority over the GPIO function. - - @endverbatim - - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x_gpio.h" -#include "stm32f30x_rcc.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @defgroup GPIO - * @brief GPIO driver modules - * @{ - */ - - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup GPIO_Private_Functions - * @{ - */ - -/** @defgroup GPIO_Group1 Initialization and Configuration - * @brief Initialization and Configuration - * -@verbatim - =============================================================================== - ##### Initialization and Configuration ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the GPIOx peripheral registers to their default reset - * values. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @retval None - */ -void GPIO_DeInit(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - if(GPIOx == GPIOA) - { - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE); - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE); - } - else if(GPIOx == GPIOB) - { - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE); - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE); - } - else if(GPIOx == GPIOC) - { - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE); - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE); - } - else if(GPIOx == GPIOD) - { - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE); - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE); - } - else if(GPIOx == GPIOE) - { - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE); - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE); - } - else - { - if(GPIOx == GPIOF) - { - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, ENABLE); - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, DISABLE); - } - } -} - -/** - * @brief Initializes the GPIOx peripheral according to the specified - * parameters in the GPIO_InitStruct. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that - * contains the configuration information for the specified GPIO - * peripheral. - * @note GPIO_Pin: selects the pin to be configured: - * GPIO_Pin_0->GPIO_Pin_15 for GPIOA, GPIOB, GPIOC, GPIOD and GPIOE; - * GPIO_Pin_0->GPIO_Pin_2, GPIO_Pin_4, GPIO_Pin_6, GPIO_Pin_9 - * and GPIO_Pin_10 for GPIOF. - * @retval None - */ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) -{ - uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00; - uint32_t tmpreg = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); - assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); - assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); - - /*-------------------------- Configure the port pins -----------------------*/ - /*-- GPIO Mode Configuration --*/ - for (pinpos = 0x00; pinpos < 0x10; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - - /* Get the port pins position */ - currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - - if (currentpin == pos) - { - if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF)) - { - /* Check Speed mode parameters */ - assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); - - /* Speed mode configuration */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2)); - GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2)); - - /* Check Output mode parameters */ - assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType)); - - /* Output mode configuration */ - GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)); - GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos)); - } - - GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2)); - - GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2)); - - /* Use temporary variable to update PUPDR register configuration, to avoid - unexpected transition in the GPIO pin configuration. */ - tmpreg = GPIOx->PUPDR; - tmpreg &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2)); - tmpreg |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2)); - GPIOx->PUPDR = tmpreg; - } - } -} - -/** - * @brief Fills each GPIO_InitStruct member with its default value. - * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) -{ - /* Reset GPIO init structure parameters values */ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStruct->GPIO_OType = GPIO_OType_PP; - GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL; -} - -/** - * @brief Locks GPIO Pins configuration registers. - * The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, - * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. - * @note The configuration of the locked GPIO pins can no longer be modified - * until the next reset. - * @param GPIOx: where x can be (A or B or D) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint32_t tmp = 0x00010000; - - /* Check the parameters */ - assert_param(IS_GPIO_LIST_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - tmp |= GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Reset LCKK bit */ - GPIOx->LCKR = GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Read LCKK bit */ - tmp = GPIOx->LCKR; - /* Read LCKK bit */ - tmp = GPIOx->LCKR; -} - -/** - * @} - */ - -/** @defgroup GPIO_Group2 GPIO Read and Write - * @brief GPIO Read and Write - * -@verbatim - =============================================================================== - ##### GPIO Read and Write ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to read. - * @note This parameter can be GPIO_Pin_x where x can be : - * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE; - * (0..2, 4, 6, 9..10) for GPIOF. - * @retval The input port pin value. - */ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @retval The input port pin value. - */ -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->IDR); -} - -/** - * @brief Reads the specified output data port bit. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @param GPIO_Pin: Specifies the port bit to read. - * @note This parameter can be GPIO_Pin_x where x can be : - * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE; - * (0..2, 4, 6, 9..10) for GPIOF. - * @retval The output port pin value. - */ -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO output data port. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @retval GPIO output data port value. - */ -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->ODR); -} - -/** - * @brief Sets the selected data port bits. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bits to be written. - * @note This parameter can be GPIO_Pin_x where x can be : - * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE; - * (0..2, 4, 6, 9..10) for GPIOF. - * @retval None - */ -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BSRR = GPIO_Pin; -} - -/** - * @brief Clears the selected data port bits. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bits to be written. - * @note This parameter can be GPIO_Pin_x where x can be : - * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE; - * (0..2, 4, 6, 9..10) for GPIOF. - * @retval None - */ -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BRR = GPIO_Pin; -} - -/** - * @brief Sets or clears the selected data port bit. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. - * @note This parameter can be GPIO_Pin_x where x can be : - * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE; - * (0..2, 4, 6, 9..10) for GPIOF. - * @param BitVal: specifies the value to be written to the selected bit. - * This parameter can be one of the BitAction enumeration values: - * @arg Bit_RESET: to clear the port pin - * @arg Bit_SET: to set the port pin - * @retval None - */ -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_BIT_ACTION(BitVal)); - - if (BitVal != Bit_RESET) - { - GPIOx->BSRR = GPIO_Pin; - } - else - { - GPIOx->BRR = GPIO_Pin ; - } -} - -/** - * @brief Writes data to the specified GPIO data port. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @param PortVal: specifies the value to be written to the port output data - * register. - * @retval None - */ -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - GPIOx->ODR = PortVal; -} - -/** - * @} - */ - -/** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions - * @brief GPIO Alternate functions configuration functions - * -@verbatim - =============================================================================== - ##### GPIO Alternate functions configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Writes data to the specified GPIO data port. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @param GPIO_PinSource: specifies the pin for the Alternate function. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * @param GPIO_AF: selects the pin to be used as Alternate function. - * This parameter can be one of the following value: - * @arg GPIO_AF_0: JTCK-SWCLK, JTDI, JTDO/TRACESW0, JTMS-SWDAT, MCO, NJTRST, - * TRACED, TRACECK. - * @arg GPIO_AF_1: OUT, TIM2, TIM15, TIM16, TIM17. - * @arg GPIO_AF_2: COMP1_OUT, TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16. - * @arg GPIO_AF_3: COMP7_OUT, TIM8, TIM15, Touch, HRTIM. - * @arg GPIO_AF_4: I2C1, I2C2, TIM1, TIM8, TIM16, TIM17. - * @arg GPIO_AF_5: IR_OUT, I2S2, I2S3, SPI1, SPI2, TIM8, USART4, USART5 - * @arg GPIO_AF_6: IR_OUT, I2S2, I2S3, SPI2, SPI3, TIM1, TIM8 - * @arg GPIO_AF_7: AOP2_OUT, CAN, COMP3_OUT, COMP5_OUT, COMP6_OUT, USART1, - * USART2, USART3. - * @arg GPIO_AF_8: COMP1_OUT, COMP2_OUT, COMP3_OUT, COMP4_OUT, COMP5_OUT, - * COMP6_OUT. - * @arg GPIO_AF_9: AOP4_OUT, CAN, TIM1, TIM8, TIM15. - * @arg GPIO_AF_10: AOP1_OUT, AOP3_OUT, TIM2, TIM3, TIM4, TIM8, TIM17. - * @arg GPIO_AF_11: TIM1, TIM8. - * @arg GPIO_AF_12: TIM1, HRTIM. - * @arg GPIO_AF_13: HRTIM, AOP2_OUT. - * @arg GPIO_AF_14: USBDM, USBDP. - * @arg GPIO_AF_15: OUT. - * @note The pin should already been configured in Alternate Function mode(AF) - * using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - * @note Refer to the Alternate function mapping table in the device datasheet - * for the detailed mapping of the system and peripherals alternate - * function I/O pins. - * @retval None - */ -void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF) -{ - uint32_t temp = 0x00; - uint32_t temp_2 = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); - assert_param(IS_GPIO_AF(GPIO_AF)); - - temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)); - GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)); - temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp; - GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_gpio.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,410 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_gpio.h - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file contains all the functions prototypes for the GPIO - * firmware library. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F30x_GPIO_H -#define __STM32F30x_GPIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ - ((PERIPH) == GPIOB) || \ - ((PERIPH) == GPIOC) || \ - ((PERIPH) == GPIOD) || \ - ((PERIPH) == GPIOE) || \ - ((PERIPH) == GPIOF)) - -#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ - ((PERIPH) == GPIOB) || \ - ((PERIPH) == GPIOD)) -/** @defgroup Configuration_Mode_enumeration - * @{ - */ -typedef enum -{ - GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */ - GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */ - GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */ - GPIO_Mode_AN = 0x03 /*!< GPIO Analog In/Out Mode */ -}GPIOMode_TypeDef; - -#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \ - ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN)) -/** - * @} - */ - -/** @defgroup Output_type_enumeration - * @{ - */ -typedef enum -{ - GPIO_OType_PP = 0x00, - GPIO_OType_OD = 0x01 -}GPIOOType_TypeDef; - -#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD)) - -/** - * @} - */ - -/** @defgroup Output_Maximum_frequency_enumeration - * @{ - */ -typedef enum -{ - GPIO_Speed_Level_1 = 0x01, /*!< Fast Speed */ - GPIO_Speed_Level_2 = 0x02, /*!< Meduim Speed */ - GPIO_Speed_Level_3 = 0x03 /*!< High Speed */ -}GPIOSpeed_TypeDef; - -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2) || \ - ((SPEED) == GPIO_Speed_Level_3)) -/** - * @} - */ - -/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration - * @{ - */ -typedef enum -{ - GPIO_PuPd_NOPULL = 0x00, - GPIO_PuPd_UP = 0x01, - GPIO_PuPd_DOWN = 0x02 -}GPIOPuPd_TypeDef; - -#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \ - ((PUPD) == GPIO_PuPd_DOWN)) -/** - * @} - */ - -/** @defgroup Bit_SET_and_Bit_RESET_enumeration - * @{ - */ -typedef enum -{ - Bit_RESET = 0, - Bit_SET -}BitAction; - -#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) -/** - * @} - */ - -/** - * @brief GPIO Init structure definition - */ -typedef struct -{ - uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIOMode_TypeDef */ - - GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIOSpeed_TypeDef */ - - GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins. - This parameter can be a value of @ref GPIOOType_TypeDef */ - - GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins. - This parameter can be a value of @ref GPIOPuPd_TypeDef */ -}GPIO_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Constants - * @{ - */ - -/** @defgroup GPIO_pins_define - * @{ - */ -#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ -#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ -#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ -#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ -#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ -#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ -#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ -#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ -#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ -#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ -#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ -#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ -#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ -#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ -#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ -#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ -#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ - -#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00) - -#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ - ((PIN) == GPIO_Pin_1) || \ - ((PIN) == GPIO_Pin_2) || \ - ((PIN) == GPIO_Pin_3) || \ - ((PIN) == GPIO_Pin_4) || \ - ((PIN) == GPIO_Pin_5) || \ - ((PIN) == GPIO_Pin_6) || \ - ((PIN) == GPIO_Pin_7) || \ - ((PIN) == GPIO_Pin_8) || \ - ((PIN) == GPIO_Pin_9) || \ - ((PIN) == GPIO_Pin_10) || \ - ((PIN) == GPIO_Pin_11) || \ - ((PIN) == GPIO_Pin_12) || \ - ((PIN) == GPIO_Pin_13) || \ - ((PIN) == GPIO_Pin_14) || \ - ((PIN) == GPIO_Pin_15)) - -/** - * @} - */ - -/** @defgroup GPIO_Pin_sources - * @{ - */ -#define GPIO_PinSource0 ((uint8_t)0x00) -#define GPIO_PinSource1 ((uint8_t)0x01) -#define GPIO_PinSource2 ((uint8_t)0x02) -#define GPIO_PinSource3 ((uint8_t)0x03) -#define GPIO_PinSource4 ((uint8_t)0x04) -#define GPIO_PinSource5 ((uint8_t)0x05) -#define GPIO_PinSource6 ((uint8_t)0x06) -#define GPIO_PinSource7 ((uint8_t)0x07) -#define GPIO_PinSource8 ((uint8_t)0x08) -#define GPIO_PinSource9 ((uint8_t)0x09) -#define GPIO_PinSource10 ((uint8_t)0x0A) -#define GPIO_PinSource11 ((uint8_t)0x0B) -#define GPIO_PinSource12 ((uint8_t)0x0C) -#define GPIO_PinSource13 ((uint8_t)0x0D) -#define GPIO_PinSource14 ((uint8_t)0x0E) -#define GPIO_PinSource15 ((uint8_t)0x0F) - -#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ - ((PINSOURCE) == GPIO_PinSource1) || \ - ((PINSOURCE) == GPIO_PinSource2) || \ - ((PINSOURCE) == GPIO_PinSource3) || \ - ((PINSOURCE) == GPIO_PinSource4) || \ - ((PINSOURCE) == GPIO_PinSource5) || \ - ((PINSOURCE) == GPIO_PinSource6) || \ - ((PINSOURCE) == GPIO_PinSource7) || \ - ((PINSOURCE) == GPIO_PinSource8) || \ - ((PINSOURCE) == GPIO_PinSource9) || \ - ((PINSOURCE) == GPIO_PinSource10) || \ - ((PINSOURCE) == GPIO_PinSource11) || \ - ((PINSOURCE) == GPIO_PinSource12) || \ - ((PINSOURCE) == GPIO_PinSource13) || \ - ((PINSOURCE) == GPIO_PinSource14) || \ - ((PINSOURCE) == GPIO_PinSource15)) -/** - * @} - */ - -/** @defgroup GPIO_Alternate_function_selection_define - * @{ - */ - -/** - * @brief AF 0 selection - */ -#define GPIO_AF_0 ((uint8_t)0x00) /* JTCK-SWCLK, JTDI, JTDO/TRACESW0, JTMS-SWDAT, - MCO, NJTRST, TRACED, TRACECK */ -/** - * @brief AF 1 selection - */ -#define GPIO_AF_1 ((uint8_t)0x01) /* OUT, TIM2, TIM15, TIM16, TIM17 */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF_2 ((uint8_t)0x02) /* COMP1_OUT, TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16 */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF_3 ((uint8_t)0x03) /* COMP7_OUT, TIM8, TIM15, Touch, HRTIM1 */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF_4 ((uint8_t)0x04) /* I2C1, I2C2, TIM1, TIM8, TIM16, TIM17 */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF_5 ((uint8_t)0x05) /* IR_OUT, I2S2, I2S3, SPI1, SPI2, TIM8, USART4, USART5 */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF_6 ((uint8_t)0x06) /* IR_OUT, I2S2, I2S3, SPI2, SPI3, TIM1, TIM8 */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF_7 ((uint8_t)0x07) /* AOP2_OUT, CAN, COMP3_OUT, COMP5_OUT, COMP6_OUT, - USART1, USART2, USART3 */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF_8 ((uint8_t)0x08) /* COMP1_OUT, COMP2_OUT, COMP3_OUT, COMP4_OUT, - COMP5_OUT, COMP6_OUT */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF_9 ((uint8_t)0x09) /* AOP4_OUT, CAN, TIM1, TIM8, TIM15 */ - -/** - * @brief AF 10 selection - */ -#define GPIO_AF_10 ((uint8_t)0x0A) /* AOP1_OUT, AOP3_OUT, TIM2, TIM3, TIM4, TIM8, TIM17 */ - -/** - * @brief AF 11 selection - */ -#define GPIO_AF_11 ((uint8_t)0x0B) /* TIM1, TIM8 */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF_12 ((uint8_t)0x0C) /* TIM1, HRTIM1 */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF_13 ((uint8_t)0x0D) /* HRTIM1, AOP2_OUT */ - -/** - * @brief AF 14 selection - */ -#define GPIO_AF_14 ((uint8_t)0x0E) /* USBDM, USBDP */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF_15 ((uint8_t)0x0F) /* OUT */ - -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_0)||((AF) == GPIO_AF_1)||\ - ((AF) == GPIO_AF_2)||((AF) == GPIO_AF_3)||\ - ((AF) == GPIO_AF_4)||((AF) == GPIO_AF_5)||\ - ((AF) == GPIO_AF_6)||((AF) == GPIO_AF_7)||\ - ((AF) == GPIO_AF_8)||((AF) == GPIO_AF_9)||\ - ((AF) == GPIO_AF_10)||((AF) == GPIO_AF_11)||\ - ((AF) == GPIO_AF_12)||((AF) == GPIO_AF_13)||\ - ((AF) == GPIO_AF_14)||((AF) == GPIO_AF_15)) - -/** - * @} - */ - -/** @defgroup GPIO_Speed_Legacy - * @{ - */ - -#define GPIO_Speed_10MHz GPIO_Speed_Level_1 /*!< Fast Speed:10MHz */ -#define GPIO_Speed_2MHz GPIO_Speed_Level_2 /*!< Medium Speed:2MHz */ -#define GPIO_Speed_50MHz GPIO_Speed_Level_3 /*!< High Speed:50MHz */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -/* Function used to set the GPIO configuration to the default reset state *****/ -void GPIO_DeInit(GPIO_TypeDef* GPIOx); - -/* Initialization and Configuration functions *********************************/ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); - -/* GPIO Read and Write functions **********************************************/ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); - -/* GPIO Alternate functions configuration functions ***************************/ -void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F30x_GPIO_H */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_hrtim.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,3968 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_hrtim.c - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief HRTIMx module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the HRTIMx peripheral: - * + Initialization/de-initialization methods - * + I/O operation methods - * + Peripheral Control methods - * - @verbatim -================================================================================ - ##### <HRTIM specific features> ##### -================================================================================ - - [..] < HRTIM introduction: - (#) The high-resolution timer can generate up to 10 digital signals with - highly accurate timings. - It is primarily intended to drive power conversion systems such as - switch mode power supplies or lighting systems, - but can be of general purpose usage, whenever a very fine timing - resolution is expected. - - (#) Its modular architecture allows to generate either independent or - coupled waveforms. - The wave-shape is defined by self-contained timings - (using counters and compare units) and a broad range of external events, - such as analog or digital feedbacks and synchronisation signals. - This allows to produce a large variety of control signal (PWM, phase-shifted, - constant Ton,...) and address most of conversion topologies. - - (#) For control and monitoring purposes, the timer has also timing measure - capabilities and links to built-in ADC and DAC converters. - Last, it features light-load management mode and is able to handle - various fault schemes for safe shut-down purposes. - - - ##### How to use this driver ##### -================================================================================ - [..] This driver provides functions to configure and program the HRTIM - of all stm32f33x devices. - These functions are split in 9 groups: - - (#) HRTIM Simple TimeBase management: this group includes all needed functions - to configure the HRTIM Timebase unit: - (++) Initializes the HRTIMx timer in simple time base mode - (++) Start/Stop the time base generation - (++) Deinitialize the HRTIM peripheral - - - (#) HRTIM simple Output Compare management: this group includes all needed - functions to configure the Compare unit used in Output compare mode: - (++) Initializes the HRTIMx timer time base unit - (++) Configure the compare unit in in simple Output Compare mode - (++) Start/Stop the Output compare generation - - (#) HRTIM simple PWM management: this group includes all needed - functions to configure the Compare unit used in PWM mode: - (++) Initializes the HRTIMx timer time base unit - (++) Configure the compare unit in in simple PWM mode - (++) Start/Stop the PWM generation - - (#) HRTIM simple Capture management: this group includes all needed - functions to configure the Capture unit used in Capture mode: - (++) Initializes the HRTIMx timer time base unit - (++) Configure the compare unit in in simple Capture mode - (++) Start/Stop the Capture mode - - (#) HRTIM simple One Pulse management: this group includes all needed - functions to configure the Capture unit and Compare unit used in One Pulse mode: - (++) Initializes the HRTIMx timer time base unit - (++) Configure the compare unit and the capture unit in in simple One Pulse mode - (++) Start/Stop the One Pulse mode generation - - (#) HRTIM Waveform management: this group includes all needed - functions to configure the HRTIM possible waveform mode: - (++) Initializes the HRTIMx timer Master time base unit - (++) Initializes the HRTIMx timer Slaves time base unit - (++) Configures the HRTIMx timer Compare unit - (++) Configures the HRTIMx Slave timer Capture unit - (++) Configures the HRTIMx timer Output unit - (++) Configures the HRTIMx timer DeadTime / Chopper / Burst features - (++) Configures the HRTIMx timer Fault / External event features - (++) Configures the HRTIMx timer Synchronization features: Internal/External connection, DACs,... - (++) Configures the HRTIMx timer Synchronization features: ADCs Triggers - (++) HRTIMx timer Outputs Start/Stop - (++) Start/Stop the HRTIMx Timer counters - - (#) HRTIM interrupts, DMA and flags management - (++) Enable/Disable interrupt sources - (++) Get flags status - (++) Clear flags/ Pending bits - (++) Enable/Disable DMA requests - (++) Configure DMA burst mode - - (#) TIM specific interface management, this group includes all - needed functions to use the specific TIM interface: - (++) HRTIMx timer DLL calibration - - @endverbatim - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x_hrtim.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @defgroup HRTIM - * @brief HRTIM driver module - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\ - HRTIM_FLTR_FLT2EN |\ - HRTIM_FLTR_FLT3EN |\ - HRTIM_FLTR_FLT4EN | \ - HRTIM_FLTR_FLT5EN) - -#define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER |\ - HRTIM_TIMUPDATETRIGGER_TIMER_A |\ - HRTIM_TIMUPDATETRIGGER_TIMER_B |\ - HRTIM_TIMUPDATETRIGGER_TIMER_C |\ - HRTIM_TIMUPDATETRIGGER_TIMER_D |\ - HRTIM_TIMUPDATETRIGGER_TIMER_E) - -#define HRTIM_TIM_OFFSET (uint32_t)0x00000080 -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -static uint32_t TimerIdxToTimerId[] = -{ - HRTIM_TIMERID_TIMER_A, - HRTIM_TIMERID_TIMER_B, - HRTIM_TIMERID_TIMER_C, - HRTIM_TIMERID_TIMER_D, - HRTIM_TIMERID_TIMER_E, - HRTIM_TIMERID_MASTER, -}; - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -static void HRTIM_MasterBase_Config(HRTIM_TypeDef* HRTIMx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruc); -static void HRTIM_TimingUnitBase_Config(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct); -static void HRTIM_MasterWaveform_Config(HRTIM_TypeDef * HRTIMx, HRTIM_TimerInitTypeDef * TimerInit); -static void HRTIM_TimingUnitWaveform_Config(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - HRTIM_TimerInitTypeDef * TimerInit); -static void HRTIM_CompareUnitConfig(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t CompareUnit, - HRTIM_CompareCfgTypeDef * CompareCfg); -static void HRTIM_CaptureUnitConfig(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t CaptureUnit, - uint32_t Event); -static void HRTIM_OutputConfig(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t Output, - HRTIM_OutputCfgTypeDef * OutputCfg); -static void HRTIM_ExternalEventConfig(HRTIM_TypeDef * HRTIMx, - uint32_t Event, - HRTIM_EventCfgTypeDef * EventCfg); -static void HRTIM_TIM_ResetConfig(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t Event); - /** @defgroup HRTIM_Private_Functions - * @{ - */ - -/** @defgroup HRTIM_Group1 Initialization/de-initialization methods - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization/de-initialization methods ##### - =============================================================================== - [..] This section provides functions allowing to: - (+)Initializes timer in basic time base mode - (+)Initializes timer in basic OC mode - (+)Initializes timer in basic PWM mode - (+)Initializes timer in basic Capture mode - (+)Initializes timer in One Pulse mode - (+)Initializes a timer operating in waveform mode - (+)De-initializes the HRTIMx timer - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the HRTIMx timer in basic time base mode - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 for master timer - * @arg 0x1 to 0x5 for timers A to E - * @note The time-base unit initialization parameters specify: - * The timer counter operating mode (continuous, one shot) - * The timer clock prescaler - * The timer period - * The timer repetition counter. - * @retval None - */ -void HRTIM_SimpleBase_Init(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct) -{ - /* Check the parameters */ - assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode)); - - if (TimerIdx == HRTIM_TIMERINDEX_MASTER) - { - /* Configure master timer */ - HRTIM_MasterBase_Config(HRTIMx, HRTIM_BaseInitStruct); - } - else - { - /* Configure timing unit */ - HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct); - } -} - -/** - * @brief De-initializes a timer operating in all mode - * @param HRTIMx: pointer to HRTIMx peripheral - * @retval None - */ -void HRTIM_DeInit(HRTIM_TypeDef* HRTIMx) -{ - /* Check the parameters */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_HRTIM1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_HRTIM1, DISABLE); - } - -/** - * @brief Initializes the HRTIMx timer in basic output compare mode - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x1 to 0x5 for timers A to E - * @note Initializes the time-base unit of the timer and prepare it to - * operate in output compare mode - * @retval None - */ -void HRTIM_SimpleOC_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct) -{ - /* Check the parameters */ - assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode)); - - /* Configure timing unit */ - HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct); -} - -/** - * @brief Initializes the HRTIMx timer in basic PWM mode - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x1 to 0x5 for timers A to E - * @note Initializes the time-base unit of the timer and prepare it to - * operate in capture mode - * @retval None - */ -void HRTIM_SimplePWM_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct) -{ - /* Check the parameters */ - assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode)); - - /* Configure timing unit */ - HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct); -} - -/** - * @brief Initializes a timer operating in basic capture mode - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x1 to 0x5 for timers A to E - * @retval None - */ -void HRTIM_SimpleCapture_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct) -{ - /* Check the parameters */ - assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode)); - - /* Configure timing unit */ - HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct); -} - -/** - * @brief Initializes the HRTIMx timer in basic one pulse mode - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x1 to 0x5 for timers A to E - * @note Initializes the time-base unit of the timer and prepare it to - * operate in one pulse mode. In this mode the counter operates - * in single shot mode (retriggerable or not) - * @retval None - */ -void HRTIM_SimpleOnePulse_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct) -{ - /* Check the parameters */ - assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode)); - - /* Configure timing unit */ - HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct); -} - -/** - * @brief Initializes a timer operating in waveform mode - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 for master timer - * @arg 0x1 to 0x5 for timers A to E - * @param pTimerInit: pointer to the timer initialization data structure - * @retval None - */ -void HRTIM_Waveform_Init(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct, - HRTIM_TimerInitTypeDef* HRTIM_TimerInitStruct) -{ - /* Check the parameters */ - assert_param(IS_HRTIM_HALFMODE(HRTIM_TimerInitStruct->HalfModeEnable)); - assert_param(IS_HRTIM_SYNCSTART(HRTIM_TimerInitStruct->StartOnSync)); - assert_param(IS_HRTIM_SYNCRESET(HRTIM_TimerInitStruct->ResetOnSync)); - assert_param(IS_HRTIM_DACSYNC(HRTIM_TimerInitStruct->DACSynchro)); - assert_param(IS_HRTIM_PRELOAD(HRTIM_TimerInitStruct->PreloadEnable)); - assert_param(IS_HRTIM_TIMERBURSTMODE(HRTIM_TimerInitStruct->BurstMode)); - assert_param(IS_HRTIM_UPDATEONREPETITION(HRTIM_TimerInitStruct->RepetitionUpdate)); - - if (TimerIdx == HRTIM_TIMERINDEX_MASTER) - { - /* Check parameters */ - assert_param(IS_HRTIM_UPDATEGATING_MASTER(HRTIM_TimerInitStruct->UpdateGating)); - - /* Configure master timer */ - HRTIM_MasterBase_Config(HRTIMx, HRTIM_BaseInitStruct); - HRTIM_MasterWaveform_Config(HRTIMx, HRTIM_TimerInitStruct); - } - else - { - /* Check parameters */ - assert_param(IS_HRTIM_UPDATEGATING_TIM(HRTIM_TimerInitStruct->UpdateGating)); - - /* Configure timing unit */ - HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct); - HRTIM_TimingUnitWaveform_Config(HRTIMx, TimerIdx, HRTIM_TimerInitStruct); - } -} - -/** - * @} - */ - -/** @defgroup HRTIM_Group2 I/O operation methods - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### IO operation methods ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the HRTIMx data - transfers. - (+) Starts the DLL calibration. - (+) Starts / stops the counter of a timer operating in basic time base mode - (+) Starts / stops the output compare signal generation on the designed timer output - (+) Starts / stops the PWM output signal generation on the designed timer output - (+) Enables / disables a basic capture on the designed capture unit - -@endverbatim - * @{ - */ - -/** - * @brief Starts the DLL calibration - * @param HRTIMx: pointer to HRTIMx peripheral - * @param CalibrationRate: DLL calibration period - * This parameter can be one of the following values: - * @arg HRTIM_CALIBRATIONRATE_7300: 7.3 ms - * @arg HRTIM_CALIBRATIONRATE_910: 910 us - * @arg HRTIM_CALIBRATIONRATE_114: 114 us - * @arg HRTIM_CALIBRATIONRATE_14: 14 us - * @retval None - */ -void HRTIM_DLLCalibrationStart(HRTIM_TypeDef * HRTIMx, uint32_t CalibrationRate) -{ - uint32_t HRTIM_dllcr; - - /* Check the parameters */ - assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate)); - - /* Configure DLL Calibration */ - HRTIM_dllcr = (HRTIMx->HRTIM_COMMON).DLLCR; - - /* Set the Calibration rate */ - HRTIM_dllcr &= ~(HRTIM_DLLCR_CALRTE); - HRTIM_dllcr |= CalibrationRate; - - /* Start DLL calibration */ - HRTIM_dllcr |= HRTIM_DLLCR_CAL; - - /* Update HRTIMx register */ - (HRTIMx->HRTIM_COMMON).DLLCR = HRTIM_dllcr; - -} -/** - * @brief Starts the counter of a timer operating in basic time base mode - * @param HRTIMx: pointer to HRTIM peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x5 for master timer - * @arg 0x0 to 0x4 for timers A to E - * @retval None - */ -void HRTIM_SimpleBaseStart(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx) -{ - /* Check the parameters */ - assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - - /* Enable the timer counter */ - __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]); -} - -/** - * @brief Stops the counter of a timer operating in basic time base mode - * @param HRTIMx: pointer to HRTIM peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x5 for master timer - * @arg 0x0 to 0x4 for timers A to E - * @retval None - */ -void HRTIM_SimpleBaseStop(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx) -{ - /* Check the parameters */ - assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - - /* Disable the timer counter */ - __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]); -} - -/** - * @brief Starts the output compare signal generation on the designed timer output - * @param HRTIMx: pointer to HRTIM peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param OCChannel: Timer output - * This parameter can be one of the following values: - * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 - * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 - * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 - * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 - * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 - * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 - * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 - * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 - * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 - * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 - * @retval None - */ -void HRTIM_SimpleOCStart(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t OCChannel) -{ - /* Check the parameters */ - assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); - - /* Enable the timer output */ - (HRTIMx->HRTIM_COMMON).OENR |= OCChannel; - - /* Enable the timer counter */ - __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]); - -} - -/** - * @brief Stops the output compare signal generation on the designed timer output - * @param HRTIMx: pointer to HRTIM peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param OCChannel: Timer output - * This parameter can be one of the following values: - * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 - * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 - * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 - * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 - * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 - * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 - * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 - * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 - * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 - * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 - * @retval None - */ -void HRTIM_SimpleOCStop(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t OCChannel) -{ - /* Check the parameters */ - assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); - - /* Disable the timer output */ - HRTIMx->HRTIM_COMMON.DISR |= OCChannel; - - /* Disable the timer counter */ - __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]); -} - -/** - * @brief Starts the PWM output signal generation on the designed timer output - * @param HRTIMx: pointer to HRTIM peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param PWMChannel: Timer output - * This parameter can be one of the following values: - * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 - * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 - * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 - * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 - * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 - * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 - * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 - * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 - * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 - * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 - * @retval None - */ -void HRTIM_SimplePWMStart(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t PWMChannel) -{ - /* Check the parameters */ - assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); - - /* Enable the timer output */ - HRTIMx->HRTIM_COMMON.OENR |= PWMChannel; - - /* Enable the timer counter */ - __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]); -} - -/** - * @brief Stops the PWM output signal generation on the designed timer output - * @param HRTIMx: pointer to HRTIM peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param PWMChannel: Timer output - * This parameter can be one of the following values: - * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 - * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 - * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 - * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 - * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 - * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 - * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 - * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 - * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 - * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 - * @retval None - */ -void HRTIM_SimplePWMStop(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t PWMChannel) -{ - /* Check the parameters */ - assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); - - /* Disable the timer output */ - HRTIMx->HRTIM_COMMON.DISR |= PWMChannel; - - /* Disable the timer counter */ - __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]); -} - -/** - * @brief Enables a basic capture on the designed capture unit - * @param HRTIMx: pointer to HRTIM peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param CaptureChannel: Timer output - * This parameter can be one of the following values: - * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1 - * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 - * @retval None - * @note The external event triggering the capture is available for all timing - * units. It can be used directly and is active as soon as the timing - * unit counter is enabled. - */ -void HRTIM_SimpleCaptureStart(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t CaptureChannel) -{ - /* Enable the timer counter */ - __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]); - -} - -/** - * @brief Disables a basic capture on the designed capture unit - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param CaptureChannel: Timer output - * This parameter can be one of the following values: - * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1 - * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 - * @retval None - */ -void HRTIM_SimpleCaptureStop(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t CaptureChannel) -{ - /* Check the parameters */ - assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); - assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); - - /* Set the capture unit trigger */ - switch (CaptureChannel) - { - case HRTIM_CAPTUREUNIT_1: - { - HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE; - } - break; - case HRTIM_CAPTUREUNIT_2: - { - HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE; - } - break; - default: - break; - } - - /* Disable the timer counter */ - if ((HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) && - (HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE)) - { - __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]); - } - -} - -/** - * @brief Enables the basic one pulse signal generation on the designed output - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param OnePulseChannel: Timer output - * This parameter can be one of the following values: - * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 - * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 - * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 - * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 - * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 - * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 - * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 - * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 - * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 - * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 - * @retval None - */ -void HRTIM_SimpleOnePulseStart(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t OnePulseChannel) -{ - /* Check the parameters */ - assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel)); - - /* Enable the timer output */ - HRTIMx->HRTIM_COMMON.OENR |= OnePulseChannel; - - /* Enable the timer counter */ - __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]); -} - -/** - * @brief Disables the basic one pulse signal generation on the designed output - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param OnePulseChannel: Timer output - * This parameter can be one of the following values: - * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 - * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 - * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 - * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 - * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 - * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 - * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 - * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 - * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 - * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 - * @retval None - */ -void HRTIM_SimpleOnePulseStop(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t OnePulseChannel) -{ - /* Check the parameters */ - assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel)); - - /* Disable the timer output */ - HRTIMx->HRTIM_COMMON.DISR |= OnePulseChannel; - - /* Disable the timer counter */ - __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]); -} - -/** - * @brief Starts the counter of the designated timer(s) operating in waveform mode - * Timers can be combined (ORed) to allow for simultaneous counter start - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimersToStart: Timer counter(s) to start - * This parameter can be any combination of the following values: - * @arg HRTIM_TIMERID_MASTER - * @arg HRTIM_TIMERID_TIMER_A - * @arg HRTIM_TIMERID_TIMER_B - * @arg HRTIM_TIMERID_TIMER_C - * @arg HRTIM_TIMERID_TIMER_D - * @arg HRTIM_TIMERID_TIMER_E - * @retval None - */ -void HRTIM_WaveformCounterStart(HRTIM_TypeDef * HRTIMx, - uint32_t TimersToStart) -{ - /* Enable timer(s) counter */ - HRTIMx->HRTIM_MASTER.MCR |= TimersToStart; -} - -/** - * @brief Stops the counter of the designated timer(s) operating in waveform mode - * Timers can be combined (ORed) to allow for simultaneous counter stop - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimersToStop: Timer counter(s) to stop - * This parameter can be any combination of the following values: - * @arg HRTIM_TIMER_MASTER - * @arg HRTIM_TIMER_A - * @arg HRTIM_TIMER_B - * @arg HRTIM_TIMER_C - * @arg HRTIM_TIMER_D - * @arg HRTIM_TIMER_E - * @retval None - */ -void HRTIM_WaveformCounterStop(HRTIM_TypeDef * HRTIMx, - uint32_t TimersToStop) -{ - /* Disable timer(s) counter */ - HRTIMx->HRTIM_MASTER.MCR &= ~TimersToStop; -} - -/** - * @brief Enables the generation of the waveform signal on the designated output(s) - * Outputs can be combined (ORed) to allow for simultaneous output enabling - * @param HRTIMx: pointer to HRTIMx peripheral - * @param OutputsToStart: Timer output(s) to enable - * This parameter can be any combination of the following values: - * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 - * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 - * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 - * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 - * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 - * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 - * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 - * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 - * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 - * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 - * @retval None - */ -void HRTIM_WaveformOutputStart(HRTIM_TypeDef * HRTIMx, - uint32_t OutputsToStart) -{ - /* Enable the HRTIM outputs */ - HRTIMx->HRTIM_COMMON.OENR = OutputsToStart; -} - -/** - * @brief Disables the generation of the waveform signal on the designated output(s) - * Outputs can be combined (ORed) to allow for simultaneous output disabling - * @param HRTIMx: pointer to HRTIMx peripheral - * @param OutputsToStop: Timer output(s) to disable - * This parameter can be any combination of the following values: - * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 - * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 - * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 - * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 - * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 - * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 - * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 - * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 - * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 - * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 - * @retval None - */ -void HRTIM_WaveformOutputStop(HRTIM_TypeDef * HRTIMx, - uint32_t OutputsToStop) -{ - /* Disable the HRTIM outputs */ - HRTIMx->HRTIM_COMMON.DISR = OutputsToStop; -} - -/** - * @brief Enables or disables the Master and slaves interrupt request - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param HRTIM_IT: specifies the HRTIM interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt source - * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt source - * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt Interrupt source - * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 Interrupt source - * @arg HRTIM_MASTER_IT_MREP: Master Repetition Interrupt source - * @arg HRTIM_MASTER_IT_SYNC: Synchronization input Interrupt source - * @arg HRTIM_MASTER_IT_MUPD: Master update Interrupt source - * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 Interrupt source - * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 Interrupt source - * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 Interrupt source - * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 Interrupt source - * @arg HRTIM_TIM_IT_REP: Timer repetition Interrupt source - * @arg HRTIM_TIM_IT_UPD: Timer update Interrupt source - * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 Interrupt source - * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 Interrupt source - * @arg HRTIM_TIM_IT_SET1: Timer output 1 set Interrupt source - * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset Interrupt source - * @arg HRTIM_TIM_IT_SET2: Timer output 2 set Interrupt source - * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset Interrupt source - * @arg HRTIM_TIM_IT_RST: Timer reset Interrupt source - * @arg HRTIM_TIM_IT_DLYPRT1: Timer delay protection Interrupt source - * @param NewState: new state of the TIM interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void HRTIM_ITConfig(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT, FunctionalState NewState) -{ - if(TimerIdx != HRTIM_TIMERINDEX_MASTER) - { - if(NewState != DISABLE) - { - HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER |= HRTIM_IT; - } - else - { - HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER &= ~HRTIM_IT; - } - } - else - { - if(NewState != DISABLE) - { - HRTIMx->HRTIM_MASTER.MDIER |= HRTIM_IT; - } - else - { - HRTIMx->HRTIM_MASTER.MDIER &= ~HRTIM_IT; - } - } -} - -/** - * @brief Enables or disables the common interrupt request - * @param HRTIMx: pointer to HRTIMx peripheral - * @param HRTIM_IT: specifies the HRTIM interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg HRTIM_IT_FLT1: Fault 1 interrupt source - * @arg HRTIM_IT_FLT2: Fault 2 interrupt source - * @arg HRTIM_IT_FLT3: Fault 3 interrupt Interrupt source - * @arg HRTIM_IT_FLT4: Fault 4 Interrupt source - * @arg HRTIM_IT_FLT5: Fault 5 Interrupt source - * @arg HRTIM_IT_SYSFLT: System Fault Interrupt source - * @arg HRTIM_IT_DLLRDY: DLL ready Interrupt source - * @arg HRTIM_IT_BMPER: Burst mode period Interrupt source - * @param NewState: new state of the TIM interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void HRTIM_ITCommonConfig(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT, FunctionalState NewState) -{ - if(NewState != DISABLE) - { - HRTIMx->HRTIM_COMMON.IER |= HRTIM_CommonIT; - } - else - { - HRTIMx->HRTIM_COMMON.IER &= ~HRTIM_CommonIT; - } -} - -/** - * @brief Clears the Master and slaves interrupt flags - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param HRTIM_FLAG: specifies the HRTIM flags sources to be cleared. - * This parameter can be any combination of the following values: - * @arg HRTIM_MASTER_FLAG_MCMP1: Master compare 1 interrupt flag - * @arg HRTIM_MASTER_FLAG_MCMP2: Master compare 2 interrupt flag - * @arg HRTIM_MASTER_FLAG_MCMP3: Master compare 3 interrupt Interrupt flag - * @arg HRTIM_MASTER_FLAG_MCMP4: Master compare 4 Interrupt flag - * @arg HRTIM_MASTER_FLAG_MREP: Master Repetition Interrupt flag - * @arg HRTIM_MASTER_FLAG_SYNC: Synchronization input Interrupt flag - * @arg HRTIM_MASTER_FLAG_MUPD: Master update Interrupt flag - * @arg HRTIM_TIM_FLAG_CMP1: Timer compare 1 Interrupt flag - * @arg HRTIM_TIM_FLAG_CMP2: Timer compare 2 Interrupt flag - * @arg HRTIM_TIM_FLAG_CMP3: Timer compare 3 Interrupt flag - * @arg HRTIM_TIM_FLAG_CMP4: Timer compare 4 Interrupt flag - * @arg HRTIM_TIM_FLAG_REP: Timer repetition Interrupt flag - * @arg HRTIM_TIM_FLAG_UPD: Timer update Interrupt flag - * @arg HRTIM_TIM_FLAG_CPT1: Timer capture 1 Interrupt flag - * @arg HRTIM_TIM_FLAG_CPT2: Timer capture 2 Interrupt flag - * @arg HRTIM_TIM_FLAG_SET1: Timer output 1 set Interrupt flag - * @arg HRTIM_TIM_FLAG_RST1: Timer output 1 reset Interrupt flag - * @arg HRTIM_TIM_FLAG_SET2: Timer output 2 set Interrupt flag - * @arg HRTIM_TIM_FLAG_RST2: Timer output 2 reset Interrupt flag - * @arg HRTIM_TIM_FLAG_RST: Timer reset Interrupt flag - * @arg HRTIM_TIM_FLAG_DLYPRT1: Timer delay protection Interrupt flag - * @retval None - */ -void HRTIM_ClearFlag(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG) -{ - if(TimerIdx != HRTIM_TIMERINDEX_MASTER) - { - HRTIMx->HRTIM_MASTER.MICR |= HRTIM_FLAG; - } - else - { - HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxICR |= HRTIM_FLAG; - } -} - -/** - * @brief Clears the common interrupt flags - * @param HRTIMx: pointer to HRTIMx peripheral - * @param HRTIM_FLAG: specifies the HRTIM flags to be cleared. - * This parameter can be any combination of the following values: - * @arg HRTIM_FLAG_FLT1: Fault 1 interrupt flag - * @arg HRTIM_FLAG_FLT2: Fault 2 interrupt flag - * @arg HRTIM_FLAG_FLT3: Fault 3 interrupt Interrupt flag - * @arg HRTIM_FLAG_FLT4: Fault 4 Interrupt flag - * @arg HRTIM_FLAG_FLT5: Fault 5 Interrupt flag - * @arg HRTIM_FLAG_SYSFLT: System Fault Interrupt flag - * @arg HRTIM_FLAG_DLLRDY: DLL ready Interrupt flag - * @arg HRTIM_FLAG_BMPER: Burst mode period Interrupt flag - * @retval None - */ -void HRTIM_ClearCommonFlag(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG) -{ - HRTIMx->HRTIM_COMMON.ICR |= HRTIM_CommonFLAG; -} - -/** - * @brief Clears the Master and slaves interrupt request pending bits - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param HRTIM_IT: specifies the HRTIM interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt source - * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt source - * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt Interrupt source - * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 Interrupt source - * @arg HRTIM_MASTER_IT_MREP: Master Repetition Interrupt source - * @arg HRTIM_MASTER_IT_SYNC: Synchronization input Interrupt source - * @arg HRTIM_MASTER_IT_MUPD: Master update Interrupt source - * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 Interrupt source - * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 Interrupt source - * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 Interrupt source - * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 Interrupt source - * @arg HRTIM_TIM_IT_REP: Timer repetition Interrupt source - * @arg HRTIM_TIM_IT_UPD: Timer update Interrupt source - * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 Interrupt source - * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 Interrupt source - * @arg HRTIM_TIM_IT_SET1: Timer output 1 set Interrupt source - * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset Interrupt source - * @arg HRTIM_TIM_IT_SET2: Timer output 2 set Interrupt source - * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset Interrupt source - * @arg HRTIM_TIM_IT_RST: Timer reset Interrupt source - * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection Interrupt source - * @retval None - */ -void HRTIM_ClearITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT) -{ - if(TimerIdx != HRTIM_TIMERINDEX_MASTER) - { - HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxICR |= HRTIM_IT; - } - else - { - HRTIMx->HRTIM_MASTER.MICR |= HRTIM_IT; - } -} - -/** - * @brief Clears the common interrupt pending bits - * @param HRTIMx: pointer to HRTIMx peripheral - * @param HRTIM_IT: specifies the HRTIM interrupts sources to be cleared. - * This parameter can be any combination of the following values: - * @arg HRTIM_IT_FLT1: Fault 1 interrupt source - * @arg HRTIM_IT_FLT2: Fault 2 interrupt source - * @arg HRTIM_IT_FLT3: Fault 3 interrupt Interrupt source - * @arg HRTIM_IT_FLT4: Fault 4 Interrupt source - * @arg HRTIM_IT_FLT5: Fault 5 Interrupt source - * @arg HRTIM_IT_SYSFLT: System Fault Interrupt source - * @arg HRTIM_IT_DLLRDY: DLL ready Interrupt source - * @arg HRTIM_IT_BMPER: Burst mode period Interrupt source - * @retval None - */ -void HRTIM_ClearCommonITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT) -{ - HRTIMx->HRTIM_COMMON.ICR |= HRTIM_CommonIT; -} - - -/** - * @brief Checks whether the specified HRTIM flag is set or not. - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param HRTIM_FLAG: specifies the HRTIM flags to check. - * This parameter can be any combination of the following values: - * @arg HRTIM_MASTER_FLAG_MCMP1: Master compare 1 interrupt flag - * @arg HRTIM_MASTER_FLAG_MCMP2: Master compare 2 interrupt flag - * @arg HRTIM_MASTER_FLAG_MCMP3: Master compare 3 interrupt Interrupt flag - * @arg HRTIM_MASTER_FLAG_MCMP4: Master compare 4 Interrupt flag - * @arg HRTIM_MASTER_FLAG_MREP: Master Repetition Interrupt flag - * @arg HRTIM_MASTER_FLAG_SYNC: Synchronization input Interrupt flag - * @arg HRTIM_MASTER_FLAG_MUPD: Master update Interrupt flag - * @arg HRTIM_TIM_FLAG_CMP1: Timer compare 1 Interrupt flag - * @arg HRTIM_TIM_FLAG_CMP2: Timer compare 2 Interrupt flag - * @arg HRTIM_TIM_FLAG_CMP3: Timer compare 3 Interrupt flag - * @arg HRTIM_TIM_FLAG_CMP4: Timer compare 4 Interrupt flag - * @arg HRTIM_TIM_FLAG_REP: Timer repetition Interrupt flag - * @arg HRTIM_TIM_FLAG_UPD: Timer update Interrupt flag - * @arg HRTIM_TIM_FLAG_CPT1: Timer capture 1 Interrupt flag - * @arg HRTIM_TIM_FLAG_CPT2: Timer capture 2 Interrupt flag - * @arg HRTIM_TIM_FLAG_SET1: Timer output 1 set Interrupt flag - * @arg HRTIM_TIM_FLAG_RST1: Timer output 1 reset Interrupt flag - * @arg HRTIM_TIM_FLAG_SET2: Timer output 2 set Interrupt flag - * @arg HRTIM_TIM_FLAG_RST2: Timer output 2 reset Interrupt flag - * @arg HRTIM_TIM_FLAG_RST: Timer reset Interrupt flag - * @arg HRTIM_TIM_FLAG_DLYPRT: Timer delay protection Interrupt flag - * @retval The new state of HRTIM_FLAG (SET or RESET). - */ -FlagStatus HRTIM_GetFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG) -{ - FlagStatus bitstatus = RESET; - - if(TimerIdx != HRTIM_TIMERINDEX_MASTER) - { - if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_FLAG) != RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - if ((HRTIMx->HRTIM_MASTER.MISR & HRTIM_FLAG) != RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - return bitstatus; -} - -/** - * @brief Checks whether the specified HRTIM common flag is set or not. - * @param HRTIMx: pointer to HRTIMx peripheral - * @param HRTIM_FLAG: specifies the HRTIM flags to check. - * This parameter can be any combination of the following values: - * @arg HRTIM_FLAG_FLT1: Fault 1 interrupt flag - * @arg HRTIM_FLAG_FLT2: Fault 2 interrupt flag - * @arg HRTIM_FLAG_FLT3: Fault 3 interrupt Interrupt flag - * @arg HRTIM_FLAG_FLT4: Fault 4 Interrupt flag - * @arg HRTIM_FLAG_FLT5: Fault 5 Interrupt flag - * @arg HRTIM_FLAG_SYSFLT: System Fault Interrupt flag - * @arg HRTIM_FLAG_DLLRDY: DLL ready Interrupt flag - * @arg HRTIM_FLAG_BMPER: Burst mode period Interrupt flag - * @retval The new state of HRTIM_FLAG (SET or RESET). - */ -FlagStatus HRTIM_GetCommonFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG) -{ - FlagStatus bitstatus = RESET; - - if((HRTIMx->HRTIM_COMMON.ISR & HRTIM_CommonFLAG) != RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Checks whether the specified HRTIM interrupt has occurred or not. - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param HRTIM_IT: specifies the HRTIM flags sources to be cleared. - * This parameter can be any combination of the following values: - * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt - * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt - * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt Interrupt - * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 Interrupt - * @arg HRTIM_MASTER_IT_MREP: Master Repetition Interrupt - * @arg HRTIM_MASTER_IT_SYNC: Synchronization input Interrupt - * @arg HRTIM_MASTER_IT_MUPD: Master update Interrupt - * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 Interrupt - * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 Interrupt - * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 Interrupt - * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 Interrupt - * @arg HRTIM_TIM_IT_REP: Timer repetition Interrupt - * @arg HRTIM_TIM_IT_UPD: Timer update Interrupt - * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 Interrupt - * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 Interrupt - * @arg HRTIM_TIM_IT_SET1: Timer output 1 set Interrupt - * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset Interrupt - * @arg HRTIM_TIM_IT_SET2: Timer output 2 set Interrupt - * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset Interrupt - * @arg HRTIM_TIM_IT_RST: Timer reset Interrupt - * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection Interrupt - * @retval The new state of the HRTIM_IT(SET or RESET). - */ -ITStatus HRTIM_GetITStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itstatus = 0x0, itenable = 0x0; - - if(TimerIdx != HRTIM_TIMERINDEX_MASTER) - { - itstatus = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_IT; - - itenable = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER & HRTIM_IT; - if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - itstatus = HRTIMx->HRTIM_MASTER.MISR & HRTIM_IT; - - itenable = HRTIMx->HRTIM_MASTER.MDIER & HRTIM_IT; - if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - return bitstatus; -} - -/** - * @brief Checks whether the specified HRTIM common interrupt has occurred or not. - * @param HRTIMx: pointer to HRTIMx peripheral - * @param HRTIM_IT: specifies the HRTIM interrupt source to check. - * This parameter can be any combination of the following values: - * @arg HRTIM_IT_FLT1: Fault 1 interrupt - * @arg HRTIM_IT_FLT2: Fault 2 interrupt - * @arg HRTIM_IT_FLT3: Fault 3 interrupt Interrupt - * @arg HRTIM_IT_FLT4: Fault 4 Interrupt - * @arg HRTIM_IT_FLT5: Fault 5 Interrupt - * @arg HRTIM_IT_SYSFLT: System Fault Interrupt - * @arg HRTIM_IT_DLLRDY: DLL ready Interrupt flag - * @arg HRTIM_IT_BMPER: Burst mode period Interrupt - * @retval The new state of HRTIM_FLAG (SET or RESET). - */ -ITStatus HRTIM_GetCommonITStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT) -{ - ITStatus bitstatus = RESET; - uint16_t itstatus = 0x0, itenable = 0x0; - - itstatus = HRTIMx->HRTIM_COMMON.ISR & HRTIM_CommonIT; - itenable = HRTIMx->HRTIM_COMMON.IER & HRTIM_CommonIT; - - if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/** - * @brief Enables or disables the HRTIMx's DMA Requests. - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param HRTIM_DMA: specifies the DMA Request sources. - * This parameter can be any combination of the following values: - * @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA request source - * @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA request source - * @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA request source - * @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA request source - * @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA request source - * @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA request source - * @arg HRTIM_MASTER_DMA_MUPD:Master update DMA request source - * @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA request source - * @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA request source - * @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA request source - * @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA request source - * @arg HRTIM_TIM_DMA_REP: Timer repetition DMA request source - * @arg HRTIM_TIM_DMA_UPD: Timer update DMA request source - * @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA request source - * @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA request source - * @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA request source - * @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA request source - * @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA request source - * @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA request source - * @arg HRTIM_TIM_DMA_RST: Timer reset DMA request source - * @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA request source - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void HRTIM_DMACmd(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_DMA, FunctionalState NewState) -{ - if(TimerIdx != HRTIM_TIMERINDEX_MASTER) - { - if(NewState != DISABLE) - { - HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER |= HRTIM_DMA; - } - else - { - HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER &= ~HRTIM_DMA; - } - } - else - { - if(NewState != DISABLE) - { - HRTIMx->HRTIM_MASTER.MDIER |= HRTIM_DMA; - } - else - { - HRTIMx->HRTIM_MASTER.MDIER &= ~HRTIM_DMA; - } - } -} - -/** - * @} - */ - -/** @defgroup HRTIM_Group3 Peripheral Control methods - * @brief management functions - * -@verbatim - =============================================================================== - ##### Peripheral Control methods ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the HRTIMx data - transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Configures an output in basic output compare mode - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param OCChannel: Timer output - * This parameter can be one of the following values: - * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 - * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 - * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 - * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 - * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 - * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 - * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 - * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 - * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 - * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 - * @param pBasicOCChannelCfg: pointer to the basic output compare output configuration structure - * @note When the timer operates in basic output compare mode: - * Output 1 is implicitely controled by the compare unit 1 - * Output 2 is implicitely controled by the compare unit 2 - * Output Set/Reset crossbar is set according to the selected output compare mode: - * Toggle: SETxyR = RSTxyR = CMPy - * Active: SETxyR = CMPy, RSTxyR = 0 - * Inactive: SETxy =0, RSTxy = CMPy - * @retval None - */ -void HRTIM_SimpleOCChannelConfig(HRTIM_TypeDef * HRTIM_, - uint32_t TimerIdx, - uint32_t OCChannel, - HRTIM_BasicOCChannelCfgTypeDef* pBasicOCChannelCfg) -{ - uint32_t CompareUnit = HRTIM_COMPAREUNIT_1; - HRTIM_CompareCfgTypeDef CompareCfg; - HRTIM_OutputCfgTypeDef OutputCfg; - - /* Check parameters */ - assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); - assert_param(IS_HRTIM_BASICOCMODE(pBasicOCChannelCfg->Mode)); - assert_param(IS_HRTIM_OUTPUTPOLARITY(pBasicOCChannelCfg->Polarity)); - assert_param(IS_HRTIM_OUTPUTIDLESTATE(pBasicOCChannelCfg->IdleState)); - - /* Configure timer compare unit */ - switch (OCChannel) - { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: - { - CompareUnit = HRTIM_COMPAREUNIT_1; - } - break; - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: - { - CompareUnit = HRTIM_COMPAREUNIT_2; - } - break; - default: - break; - } - - CompareCfg.CompareValue = pBasicOCChannelCfg->Pulse; - CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR; - CompareCfg.AutoDelayedTimeout = 0; - - HRTIM_CompareUnitConfig(HRTIM_, - TimerIdx, - CompareUnit, - &CompareCfg); - - /* Configure timer output */ - OutputCfg.Polarity = pBasicOCChannelCfg->Polarity; - OutputCfg.IdleState = pBasicOCChannelCfg->IdleState; - OutputCfg.FaultState = HRTIM_OUTPUTFAULTSTATE_NONE; - OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE; - OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED; - OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR; - - switch (pBasicOCChannelCfg->Mode) - { - case HRTIM_BASICOCMODE_TOGGLE: - { - if (CompareUnit == HRTIM_COMPAREUNIT_1) - { - OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1; - } - else - { - OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2; - } - OutputCfg.ResetSource = OutputCfg.SetSource; - } - break; - case HRTIM_BASICOCMODE_ACTIVE: - { - if (CompareUnit == HRTIM_COMPAREUNIT_1) - { - OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1; - } - else - { - OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2; - } - OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE; - } - break; - case HRTIM_BASICOCMODE_INACTIVE: - { - if (CompareUnit == HRTIM_COMPAREUNIT_1) - { - OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1; - } - else - { - OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP2; - } - OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE; - } - break; - default: - break; - } - - HRTIM_OutputConfig(HRTIM_, TimerIdx, OCChannel, &OutputCfg); -} - -/** - * @brief Configures an output in basic PWM mode - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param PWMChannel: Timer output - * This parameter can be one of the following values: - * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 - * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 - * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 - * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 - * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 - * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 - * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 - * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 - * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 - * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 - * @param pBasicPWMChannelCfg: pointer to the basic PWM output configuration structure - * @note When the timer operates in basic PWM output mode: - * Output 1 is implicitly controled by the compare unit 1 - * Output 2 is implicitly controled by the compare unit 2 - * Output Set/Reset crossbar is set as follows: - * Output 1: SETx1R = CMP1, RSTx1R = PER - * Output 2: SETx2R = CMP2, RST2R = PER - * @retval None - */ -void HRTIM_SimplePWMChannelConfig(HRTIM_TypeDef * HRTIM_, - uint32_t TimerIdx, - uint32_t PWMChannel, - HRTIM_BasicPWMChannelCfgTypeDef* pBasicPWMChannelCfg) -{ - uint32_t CompareUnit = HRTIM_COMPAREUNIT_1; - HRTIM_CompareCfgTypeDef CompareCfg; - HRTIM_OutputCfgTypeDef OutputCfg; - - /* Check parameters */ - assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); - assert_param(IS_HRTIM_OUTPUTPOLARITY(pBasicPWMChannelCfg->Polarity)); - assert_param(IS_HRTIM_OUTPUTIDLESTATE(pBasicPWMChannelCfg->IdleState)); - - /* Configure timer compare unit */ - switch (PWMChannel) - { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: - { - CompareUnit = HRTIM_COMPAREUNIT_1; - } - break; - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: - { - CompareUnit = HRTIM_COMPAREUNIT_2; - } - break; - default: - break; - } - - CompareCfg.CompareValue = pBasicPWMChannelCfg->Pulse; - CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR; - CompareCfg.AutoDelayedTimeout = 0; - - HRTIM_CompareUnitConfig(HRTIM_, - TimerIdx, - CompareUnit, - &CompareCfg); - - /* Configure timer output */ - OutputCfg.Polarity = pBasicPWMChannelCfg->Polarity; - OutputCfg.IdleState = pBasicPWMChannelCfg->IdleState; - OutputCfg.FaultState = HRTIM_OUTPUTFAULTSTATE_NONE; - OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE; - OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED; - OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR; - - if (CompareUnit == HRTIM_COMPAREUNIT_1) - { - OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1; - } - else - { - OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2; - } - OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER; - - HRTIM_OutputConfig(HRTIM_, TimerIdx, PWMChannel, &OutputCfg); -} - -/** - * @brief Configures a basic capture - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param CaptureChannel: Capture unit - * This parameter can be one of the following values: - * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1 - * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 - * @param pBasicCaptureChannelCfg: pointer to the basic capture configuration structure - * @note When the timer operates in basic capture mode the capture is triggered - * by the designated external event and GPIO input is implicitly used as event source. - * The cature can be triggered by a rising edge, a falling edge or both - * edges on event channel. - * @retval None - */ -void HRTIM_SimpleCaptureChannelConfig(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t CaptureChannel, - HRTIM_BasicCaptureChannelCfgTypeDef* pBasicCaptureChannelCfg) -{ - HRTIM_EventCfgTypeDef EventCfg; - - /* Check parameters */ - assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); - assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); - assert_param(IS_HRTIM_EVENT(pBasicCaptureChannelCfg->Event)); - assert_param(IS_HRTIM_EVENTPOLARITY(pBasicCaptureChannelCfg->EventPolarity)); - assert_param(IS_HRTIM_EVENTSENSITIVITY(pBasicCaptureChannelCfg->EventSensitivity)); - assert_param(IS_HRTIM_EVENTFILTER(pBasicCaptureChannelCfg->EventFilter)); - - /* Configure external event channel */ - EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE; - EventCfg.Filter = pBasicCaptureChannelCfg->EventFilter; - EventCfg.Polarity = pBasicCaptureChannelCfg->EventPolarity; - EventCfg.Sensitivity = pBasicCaptureChannelCfg->EventSensitivity; - EventCfg.Source = HRTIM_EVENTSRC_1; - - HRTIM_ExternalEventConfig(HRTIMx, - pBasicCaptureChannelCfg->Event, - &EventCfg); - - /* Memorize capture trigger (will be configured when the capture is started */ - HRTIM_CaptureUnitConfig(HRTIMx, - TimerIdx, - CaptureChannel, - pBasicCaptureChannelCfg->Event); -} - -/** - * @brief Configures an output basic one pulse mode - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param OnePulseChannel: Timer output - * This parameter can be one of the following values: - * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 - * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 - * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 - * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 - * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 - * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 - * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 - * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 - * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 - * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 - * @param pBasicOnePulseChannelCfg: pointer to the basic one pulse output configuration structure - * @note When the timer operates in basic one pulse mode: - * the timer counter is implicitly started by the reset event, - * the reset of the timer counter is triggered by the designated external event - * GPIO input is implicitly used as event source, - * Output 1 is implicitly controled by the compare unit 1, - * Output 2 is implicitly controled by the compare unit 2. - * Output Set/Reset crossbar is set as follows: - * Output 1: SETx1R = CMP1, RSTx1R = PER - * Output 2: SETx2R = CMP2, RST2R = PER - * The counter mode should be HRTIM_MODE_SINGLESHOT_RETRIGGERABLE - * @retval None - */ -void HRTIM_SimpleOnePulseChannelConfig(HRTIM_TypeDef * HRTIM_, - uint32_t TimerIdx, - uint32_t OnePulseChannel, - HRTIM_BasicOnePulseChannelCfgTypeDef* pBasicOnePulseChannelCfg) -{ - uint32_t CompareUnit = HRTIM_COMPAREUNIT_1; - HRTIM_CompareCfgTypeDef CompareCfg; - HRTIM_OutputCfgTypeDef OutputCfg; - HRTIM_EventCfgTypeDef EventCfg; - - /* Check parameters */ - assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel)); - assert_param(IS_HRTIM_OUTPUTPOLARITY(pBasicOnePulseChannelCfg->OutputPolarity)); - assert_param(IS_HRTIM_OUTPUTIDLESTATE(pBasicOnePulseChannelCfg->OutputIdleState)); - assert_param(IS_HRTIM_EVENT(pBasicOnePulseChannelCfg->Event)); - assert_param(IS_HRTIM_EVENTPOLARITY(pBasicOnePulseChannelCfg->EventPolarity)); - assert_param(IS_HRTIM_EVENTSENSITIVITY(pBasicOnePulseChannelCfg->EventSensitivity)); - assert_param(IS_HRTIM_EVENTFILTER(pBasicOnePulseChannelCfg->EventFilter)); - - /* Configure timer compare unit */ - switch (OnePulseChannel) - { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: - { - CompareUnit = HRTIM_COMPAREUNIT_1; - } - break; - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: - { - CompareUnit = HRTIM_COMPAREUNIT_2; - } - break; - default: - break; - } - - CompareCfg.CompareValue = pBasicOnePulseChannelCfg->Pulse; - CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR; - CompareCfg.AutoDelayedTimeout = 0; - - HRTIM_CompareUnitConfig(HRTIM_, - TimerIdx, - CompareUnit, - &CompareCfg); - - /* Configure timer output */ - OutputCfg.Polarity = pBasicOnePulseChannelCfg->OutputPolarity; - OutputCfg.IdleState = pBasicOnePulseChannelCfg->OutputIdleState; - OutputCfg.FaultState = HRTIM_OUTPUTFAULTSTATE_NONE; - OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE; - OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED; - OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR; - - if (CompareUnit == HRTIM_COMPAREUNIT_1) - { - OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1; - } - else - { - OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2; - } - OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER; - - HRTIM_OutputConfig(HRTIM_, - TimerIdx, - OnePulseChannel, - &OutputCfg); - - /* Configure external event channel */ - EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE; - EventCfg.Filter = pBasicOnePulseChannelCfg->EventFilter; - EventCfg.Polarity = pBasicOnePulseChannelCfg->EventPolarity; - EventCfg.Sensitivity = pBasicOnePulseChannelCfg->EventSensitivity; - EventCfg.Source = HRTIM_EVENTSRC_1; - - HRTIM_ExternalEventConfig(HRTIM_, - pBasicOnePulseChannelCfg->Event, - &EventCfg); - - /* Configure the timer reset register */ - HRTIM_TIM_ResetConfig(HRTIM_, - TimerIdx, - pBasicOnePulseChannelCfg->Event); -} - -/** - * @brief Configures the general behavior of a timer operating in waveform mode - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param pTimerCfg: pointer to the timer configuration structure - * @note When the timer operates in waveform mode, all the features supported by - * the HRTIMx are available without any limitation. - * @retval None - */ -void HRTIM_WaveformTimerConfig(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - HRTIM_TimerCfgTypeDef * pTimerCfg) -{ - uint32_t HRTIM_timcr; - uint32_t HRTIM_timfltr; - uint32_t HRTIM_timoutr; - uint32_t HRTIM_timrstr; - - /* Check parameters */ - assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); - assert_param(IS_HRTIM_TIMPUSHPULLMODE(pTimerCfg->PushPull)); - assert_param(IS_HRTIM_TIMFAULTENABLE(pTimerCfg->FaultEnable)); - assert_param(IS_HRTIM_TIMFAULTLOCK(pTimerCfg->FaultLock)); - assert_param(IS_HRTIM_TIMDEADTIMEINSERTION(pTimerCfg->DeadTimeInsertion)); - assert_param(IS_HRTIM_TIMDELAYEDPROTECTION(pTimerCfg->DelayedProtectionMode)); - assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger)); - assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger)); - assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate)); - - /* Configure timing unit (Timer A to Timer E) */ - HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR; - HRTIM_timfltr = HRTIMx->HRTIM_TIMERx[TimerIdx].FLTxR; - HRTIM_timoutr = HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR; - HRTIM_timrstr = HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR; - - /* Set the push-pull mode */ - HRTIM_timcr &= ~(HRTIM_TIMCR_PSHPLL); - HRTIM_timcr |= pTimerCfg->PushPull; - - /* Enable/Disable registers update on timer counter reset */ - HRTIM_timcr &= ~(HRTIM_TIMCR_TRSTU); - HRTIM_timcr |= pTimerCfg->ResetUpdate; - - /* Set the timer update trigger */ - HRTIM_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER); - HRTIM_timcr |= pTimerCfg->UpdateTrigger; - - /* Enable/Disable the fault channel at timer level */ - HRTIM_timfltr &= ~(HRTIM_FLTR_FLTxEN); - HRTIM_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN); - - /* Lock/Unlock fault sources at timer level */ - HRTIM_timfltr &= ~(HRTIM_FLTR_FLTCLK); - HRTIM_timfltr |= pTimerCfg->FaultLock; - - /* Enable/Disable dead time insertion at timer level */ - HRTIM_timoutr &= ~(HRTIM_OUTR_DTEN); - HRTIM_timoutr |= pTimerCfg->DeadTimeInsertion; - - /* Enable/Disable delayed protection at timer level */ - HRTIM_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN); - HRTIM_timoutr |= pTimerCfg->DelayedProtectionMode; - - /* Set the timer counter reset trigger */ - HRTIM_timrstr = pTimerCfg->ResetTrigger; - - /* Update the HRTIMx registers */ - HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr; - HRTIMx->HRTIM_TIMERx[TimerIdx].FLTxR = HRTIM_timfltr; - HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR = HRTIM_timoutr; - HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_timrstr; - } - -/** - * @brief Configures the compare unit of a timer operating in waveform mode - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * 0xFF for master timer - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param CompareUnit: Compare unit to configure - * This parameter can be one of the following values: - * @arg HRTIM_COMPAREUNIT_1: Compare unit 1 - * @arg HRTIM_COMPAREUNIT_2: Compare unit 2 - * @arg HRTIM_COMPAREUNIT_3: Compare unit 3 - * @arg HRTIM_COMPAREUNIT_4: Compare unit 4 - * @param pCompareCfg: pointer to the compare unit configuration structure - * @note When auto delayed mode is required for compare unit 2 or compare unit 4, - * application has to configure separately the capture unit. Capture unit - * to configure in that case depends on the compare unit auto delayed mode - * is applied to (see below): - * Auto delayed on output compare 2: capture unit 1 must be configured - * Auto delayed on output compare 4: capture unit 2 must be configured - * @retval None - */ - void HRTIM_WaveformCompareConfig(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t CompareUnit, - HRTIM_CompareCfgTypeDef* pCompareCfg) -{ - uint32_t HRTIM_timcr; - - /* Check parameters */ - assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); - assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode)); - - /* Configure the compare unit */ - switch (CompareUnit) - { - case HRTIM_COMPAREUNIT_1: - { - /* Set the compare value */ - HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->CompareValue; - } - break; - case HRTIM_COMPAREUNIT_2: - { - /* Set the compare value */ - HRTIMx->HRTIM_TIMERx[TimerIdx].CMP2xR = pCompareCfg->CompareValue; - - if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR) - { - /* Configure auto-delayed mode */ - HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR; - HRTIM_timcr &= ~HRTIM_TIMCR_DELCMP2; - HRTIM_timcr |= pCompareCfg->AutoDelayedMode; - HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr; - - /* Set the compare value for timeout compare unit (if any) */ - if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) - { - HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout; - } - else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3) - { - HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout; - } - } - } - break; - case HRTIM_COMPAREUNIT_3: - { - /* Set the compare value */ - HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->CompareValue; - } - break; - case HRTIM_COMPAREUNIT_4: - { - /* Set the compare value */ - HRTIMx->HRTIM_TIMERx[TimerIdx].CMP4xR = pCompareCfg->CompareValue; - - if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR) - { - /* Configure auto-delayed mode */ - HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR; - HRTIM_timcr &= ~HRTIM_TIMCR_DELCMP4; - HRTIM_timcr |= (pCompareCfg->AutoDelayedMode << 2); - HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr; - - /* Set the compare value for timeout compare unit (if any) */ - if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) - { - HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout; - } - else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3) - { - HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout; - } - } - } - break; - default: - break; - } -} - -/** - * @brief Sets the HRTIMx Master Comparex Register value - * @param HRTIMx: pointer to HRTIMx peripheral - * @param CompareUnit: Compare unit to configure - * This parameter can be one of the following values: - * @arg HRTIM_COMPAREUNIT_1: Compare unit 1 - * @arg HRTIM_COMPAREUNIT_2: Compare unit 2 - * @arg HRTIM_COMPAREUNIT_3: Compare unit 3 - * @arg HRTIM_COMPAREUNIT_4: Compare unit 4 - * @param Compare: specifies the Comparex register new value - * @retval None - */ -void HRTIM_MasterSetCompare(HRTIM_TypeDef * HRTIMx, - uint32_t CompareUnit, - uint32_t Compare) -{ - /* Check parameters */ - assert_param(IS_HRTIM_COMPAREUNIT(CompareUnit)); - - /* Configure the compare unit */ - switch (CompareUnit) - { - case HRTIM_COMPAREUNIT_1: - { - /* Set the compare value */ - HRTIMx->HRTIM_MASTER.MCMP1R = Compare; - } - break; - case HRTIM_COMPAREUNIT_2: - { - /* Set the compare value */ - HRTIMx->HRTIM_MASTER.MCMP2R = Compare; - } - break; - case HRTIM_COMPAREUNIT_3: - { - /* Set the compare value */ - HRTIMx->HRTIM_MASTER.MCMP3R = Compare; - } - break; - case HRTIM_COMPAREUNIT_4: - { - /* Set the compare value */ - HRTIMx->HRTIM_MASTER.MCMP4R = Compare; - } - break; - default: - break; - } -} -/** - * @brief Configures the capture unit of a timer operating in waveform mode - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param CaptureChannel: Capture unit to configure - * This parameter can be one of the following values: - * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1 - * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 - * @param pCaptureCfg: pointer to the compare unit configuration structure - * @retval None - */ -void HRTIM_WaveformCaptureConfig(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t CaptureUnit, - HRTIM_CaptureCfgTypeDef* pCaptureCfg) -{ - /* Configure the capture unit */ - switch (CaptureUnit) - { - case HRTIM_CAPTUREUNIT_1: - { - HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR = pCaptureCfg->Trigger; - } - break; - case HRTIM_CAPTUREUNIT_2: - { - HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR = pCaptureCfg->Trigger; - } - break; - default: - break; - } -} - -/** - * @brief Configures the output of a timer operating in waveform mode - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param Output: Timer output - * This parameter can be one of the following values: - * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 - * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 - * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 - * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 - * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 - * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 - * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 - * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 - * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 - * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 - * @param pOutputCfg: pointer to the timer output configuration structure - * @retval None - */ -void HRTIM_WaveformOutputConfig(HRTIM_TypeDef * HRTIM_, - uint32_t TimerIdx, - uint32_t Output, - HRTIM_OutputCfgTypeDef * pOutputCfg) -{ - /* Check parameters */ - assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output)); - assert_param(IS_HRTIM_OUTPUTPOLARITY(pOutputCfg->Polarity)); - assert_param(IS_HRTIM_OUTPUTIDLESTATE(pOutputCfg->IdleState)); - assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode)); - assert_param(IS_HRTIM_OUTPUTFAULTSTATE(pOutputCfg->FaultState)); - assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable)); - assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed)); - - /* Configure the timer output */ - HRTIM_OutputConfig(HRTIM_, TimerIdx, Output, pOutputCfg); -} - -/** - * @brief Configures the event filtering capabilities of a timer (blanking, windowing) - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param Event: external event for which timer event filtering must be configured - * This parameter can be one of the following values: - * @arg HRTIM_EVENT_1: External event 1 - * @arg HRTIM_EVENT_2: External event 2 - * @arg HRTIM_EVENT_3: External event 3 - * @arg HRTIM_EVENT_4: External event 4 - * @arg HRTIM_EVENT_5: External event 5 - * @arg HRTIM_EVENT_6: External event 6 - * @arg HRTIM_EVENT_7: External event 7 - * @arg HRTIM_EVENT_8: External event 8 - * @arg HRTIM_EVENT_9: External event 9 - * @arg HRTIM_EVENT_10: External event 10 - * @param pTimerEventFilteringCfg: pointer to the timer event filtering configuration structure - * @retval None - */ -void HRTIM_TimerEventFilteringConfig(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t Event, - HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg) -{ - uint32_t HRTIM_eefr; - - /* Check parameters */ - assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); - assert_param(IS_HRTIM_EVENT(Event)); - assert_param(IS_HRTIM_TIMEVENTFILTER(pTimerEventFilteringCfg->Filter)); - assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch)); - - /* Configure timer event filtering capabilities */ - switch (Event) - { - case HRTIM_TIMEVENTFILTER_NONE: - { - HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = 0; - HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = 0; - } - break; - case HRTIM_EVENT_1: - { - HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1; - HRTIM_eefr &= ~(HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH); - HRTIM_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch); - HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr; - } - break; - case HRTIM_EVENT_2: - { - HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1; - HRTIM_eefr &= ~(HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH); - HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6); - HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr; - } - break; - case HRTIM_EVENT_3: - { - HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1; - HRTIM_eefr &= ~(HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH); - HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12); - HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr; - } - break; - case HRTIM_EVENT_4: - { - HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1; - HRTIM_eefr &= ~(HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH); - HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18); - HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr; - } - break; - case HRTIM_EVENT_5: - { - HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1; - HRTIM_eefr &= ~(HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH); - HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24); - HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr; - } - break; - case HRTIM_EVENT_6: - { - HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2; - HRTIM_eefr &= ~(HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH); - HRTIM_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch); - HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr; - } - break; - case HRTIM_EVENT_7: - { - HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2; - HRTIM_eefr &= ~(HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH); - HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6); - HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr; - } - break; - case HRTIM_EVENT_8: - { - HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2; - HRTIM_eefr &= ~(HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH); - HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12); - HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr; - } - break; - case HRTIM_EVENT_9: - { - HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2; - HRTIM_eefr &= ~(HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH); - HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18); - HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr; - } - break; - case HRTIM_EVENT_10: - { - HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2; - HRTIM_eefr &= ~(HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH); - HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24); - HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr; - } - break; - default: - break; - } -} - -/** - * @brief Configures the dead time insertion feature for a timer - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param pDeadTimeCfg: pointer to the dead time insertion configuration structure - * @retval None - */ -void HRTIM_DeadTimeConfig(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg) -{ - uint32_t HRTIM_dtr; - - /* Check parameters */ - assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); - assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGN(pDeadTimeCfg->RisingSign)); - assert_param(IS_HRTIM_TIMDEADTIME_RISINGLOCK(pDeadTimeCfg->RisingLock)); - assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock)); - assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign)); - assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock)); - assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock)); - - HRTIM_dtr = HRTIMx->HRTIM_TIMERx[TimerIdx].DTxR; - - /* Clear timer dead times configuration */ - HRTIM_dtr &= ~(HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC | - HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_SDTF | - HRTIM_DTR_SDTR | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK); - - /* Set timer dead times configuration */ - HRTIM_dtr |= (pDeadTimeCfg->Prescaler << 10); - HRTIM_dtr |= pDeadTimeCfg->RisingValue; - HRTIM_dtr |= pDeadTimeCfg->RisingSign; - HRTIM_dtr |= pDeadTimeCfg->RisingSignLock; - HRTIM_dtr |= pDeadTimeCfg->RisingLock; - HRTIM_dtr |= (pDeadTimeCfg->FallingValue << 16); - HRTIM_dtr |= pDeadTimeCfg->FallingSign; - HRTIM_dtr |= pDeadTimeCfg->FallingSignLock; - HRTIM_dtr |= pDeadTimeCfg->FallingLock; - - /* Update the HRTIMx registers */ - HRTIMx->HRTIM_TIMERx[TimerIdx].DTxR = HRTIM_dtr; -} - -/** - * @brief Configures the chopper mode feature for a timer - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param pChopperModeCfg: pointer to the chopper mode configuration structure - * @retval None - */ -void HRTIM_ChopperModeConfig(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg) -{ - uint32_t HRTIM_chpr; - - /* Check parameters */ - assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); - - HRTIM_chpr = HRTIMx->HRTIM_TIMERx[TimerIdx].CHPxR; - - /* Clear timer chopper mode configuration */ - HRTIM_chpr &= ~(HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | HRTIM_CHPR_STRPW); - - /* Set timer chopper mode configuration */ - HRTIM_chpr |= pChopperModeCfg->CarrierFreq; - HRTIM_chpr |= (pChopperModeCfg->DutyCycle << 4); - HRTIM_chpr |= (pChopperModeCfg->StartPulse << 7); - - /* Update the HRTIMx registers */ - HRTIMx->HRTIM_TIMERx[TimerIdx].CHPxR = HRTIM_chpr; -} - -/** - * @brief Configures the burst DMA controller for a timer - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x5 for master timer - * @arg 0x0 to 0x4 for timers A to E - * @param RegistersToUpdate: registers to be written by DMA - * This parameter can be any combination of the following values: - * @arg HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR - * @arg HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR - * @arg HRTIM_BURSTDMA_DIER: HRTIM_MDIER or HRTIM_TIMxDIER - * @arg HRTIM_BURSTDMA_CNT: HRTIM_MCNT or HRTIM_TIMxCNT - * @arg HRTIM_BURSTDMA_PER: HRTIM_MPER or HRTIM_TIMxPER - * @arg HRTIM_BURSTDMA_REP: HRTIM_MREP or HRTIM_TIMxREP - * @arg HRTIM_BURSTDMA_CMP1: HRTIM_MCMP1 or HRTIM_TIMxCMP1 - * @arg HRTIM_BURSTDMA_CMP2: HRTIM_MCMP2 or HRTIM_TIMxCMP2 - * @arg HRTIM_BURSTDMA_CMP3: HRTIM_MCMP3 or HRTIM_TIMxCMP3 - * @arg HRTIM_BURSTDMA_CMP4: HRTIM_MCMP4 or HRTIM_TIMxCMP4 - * @arg HRTIM_BURSTDMA_DTR: HRTIM_TIMxDTR - * @arg HRTIM_BURSTDMA_SET1R: HRTIM_TIMxSET1R - * @arg HRTIM_BURSTDMA_RST1R: HRTIM_TIMxRST1R - * @arg HRTIM_BURSTDMA_SET2R: HRTIM_TIMxSET2R - * @arg HRTIM_BURSTDMA_RST2R: HRTIM_TIMxRST2R - * @arg HRTIM_BURSTDMA_EEFR1: HRTIM_TIMxEEFR1 - * @arg HRTIM_BURSTDMA_EEFR2: HRTIM_TIMxEEFR2 - * @arg HRTIM_BURSTDMA_RSTR: HRTIM_TIMxRSTR - * @arg HRTIM_BURSTDMA_CHPR: HRTIM_TIMxCHPR - * @arg HRTIM_BURSTDMA_OUTR: HRTIM_TIMxOUTR - * @arg HRTIM_BURSTDMA_FLTR: HRTIM_TIMxFLTR - * @retval None - */ -void HRTIM_BurstDMAConfig(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t RegistersToUpdate) -{ - /* Check parameters */ - assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate)); - - /* Set the burst DMA timer update register */ - switch (TimerIdx) - { - case HRTIM_TIMERINDEX_TIMER_A: - { - HRTIMx->HRTIM_COMMON.BDTAUPR = RegistersToUpdate; - } - break; - case HRTIM_TIMERINDEX_TIMER_B: - { - HRTIMx->HRTIM_COMMON.BDTBUPR = RegistersToUpdate; - } - break; - case HRTIM_TIMERINDEX_TIMER_C: - { - HRTIMx->HRTIM_COMMON.BDTCUPR = RegistersToUpdate; - } - break; - case HRTIM_TIMERINDEX_TIMER_D: - { - HRTIMx->HRTIM_COMMON.BDTDUPR = RegistersToUpdate; - } - break; - case HRTIM_TIMERINDEX_TIMER_E: - { - HRTIMx->HRTIM_COMMON.BDTEUPR = RegistersToUpdate; - } - break; - case HRTIM_TIMERINDEX_MASTER: - { - HRTIMx->HRTIM_COMMON.BDMUPDR = RegistersToUpdate; - } - break; - default: - break; - } -} - -/** - * @brief Configures the external input/output synchronization of the HRTIMx - * @param HRTIMx: pointer to HRTIMx peripheral - * @param pSynchroCfg: pointer to the input/output synchronization configuration structure - * @retval None - */ -void HRTIM_SynchronizationConfig(HRTIM_TypeDef *HRTIMx, HRTIM_SynchroCfgTypeDef * pSynchroCfg) -{ - uint32_t HRTIM_mcr; - - /* Check parameters */ - assert_param(IS_HRTIM_SYNCINPUTSOURCE(pSynchroCfg->SyncInputSource)); - assert_param(IS_HRTIM_SYNCOUTPUTSOURCE(pSynchroCfg->SyncOutputSource)); - assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(pSynchroCfg->SyncOutputPolarity)); - - HRTIM_mcr = HRTIMx->HRTIM_MASTER.MCR; - - /* Set the synchronization input source */ - HRTIM_mcr &= ~(HRTIM_MCR_SYNC_IN); - HRTIM_mcr |= pSynchroCfg->SyncInputSource; - - /* Set the event to be sent on the synchronization output */ - HRTIM_mcr &= ~(HRTIM_MCR_SYNC_SRC); - HRTIM_mcr |= pSynchroCfg->SyncOutputSource; - - /* Set the polarity of the synchronization output */ - HRTIM_mcr &= ~(HRTIM_MCR_SYNC_OUT); - HRTIM_mcr |= pSynchroCfg->SyncOutputPolarity; - - /* Update the HRTIMx registers */ - HRTIMx->HRTIM_MASTER.MCR = HRTIM_mcr; -} - -/** - * @brief Configures the burst mode feature of the HRTIMx - * @param HRTIMx: pointer to HRTIMx peripheral - * @param pBurstModeCfg: pointer to the burst mode configuration structure - * @retval None - */ -void HRTIM_BurstModeConfig(HRTIM_TypeDef * HRTIMx, - HRTIM_BurstModeCfgTypeDef* pBurstModeCfg) -{ - uint32_t HRTIM_bmcr; - - /* Check parameters */ - assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode)); - assert_param(IS_HRTIM_BURSTMODECLOCKSOURCE(pBurstModeCfg->ClockSource)); - assert_param(IS_HRTIM_HRTIM_BURSTMODEPRESCALER(pBurstModeCfg->Prescaler)); - assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable)); - - HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR; - - /* Set the burst mode operating mode */ - HRTIM_bmcr &= ~(HRTIM_BMCR_BMOM); - HRTIM_bmcr |= pBurstModeCfg->Mode; - - /* Set the burst mode clock source */ - HRTIM_bmcr &= ~(HRTIM_BMCR_BMCLK); - HRTIM_bmcr |= pBurstModeCfg->ClockSource; - - /* Set the burst mode prescaler */ - HRTIM_bmcr &= ~(HRTIM_BMCR_BMPSC); - HRTIM_bmcr |= pBurstModeCfg->Prescaler; - - /* Enable/disable burst mode registers preload */ - HRTIM_bmcr &= ~(HRTIM_BMCR_BMPREN); - HRTIM_bmcr |= pBurstModeCfg->PreloadEnable; - - /* Set the burst mode trigger */ - HRTIMx->HRTIM_COMMON.BMTRGR = pBurstModeCfg->Trigger; - - /* Set the burst mode compare value */ - HRTIMx->HRTIM_COMMON.BMCMPR = pBurstModeCfg->IdleDuration; - - /* Set the burst mode period */ - HRTIMx->HRTIM_COMMON.BMPER = pBurstModeCfg->Period; - - /* Update the HRTIMx registers */ - HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr; -} - -/** - * @brief Configures the conditioning of an external event - * @param HRTIMx: pointer to HRTIMx peripheral - * @param Event: external event to configure - * This parameter can be one of the following values: - * @arg HRTIM_EVENT_1: External event 1 - * @arg HRTIM_EVENT_2: External event 2 - * @arg HRTIM_EVENT_3: External event 3 - * @arg HRTIM_EVENT_4: External event 4 - * @arg HRTIM_EVENT_5: External event 5 - * @arg HRTIM_EVENT_6: External event 6 - * @arg HRTIM_EVENT_7: External event 7 - * @arg HRTIM_EVENT_8: External event 8 - * @arg HRTIM_EVENT_9: External event 9 - * @arg HRTIM_EVENT_10: External event 10 - * @param pEventCfg: pointer to the event conditioning configuration structure - * @retval None - */ -void HRTIM_EventConfig(HRTIM_TypeDef * HRTIMx, - uint32_t Event, - HRTIM_EventCfgTypeDef* pEventCfg) -{ - /* Check parameters */ - assert_param(IS_HRTIM_EVENTSRC(pEventCfg->Source)); - assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Polarity)); - assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity)); - assert_param(IS_HRTIM_EVENTFASTMODE(pEventCfg->FastMode)); - assert_param(IS_HRTIM_EVENTFILTER(pEventCfg->Filter)); - - /* Configure the event channel */ - HRTIM_ExternalEventConfig(HRTIMx, Event, pEventCfg); - -} - -/** - * @brief Configures the external event conditioning block prescaler - * @param HRTIMx: pointer to HRTIMx peripheral - * @param Prescaler: Prescaler value - * This parameter can be one of the following values: - * @arg HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIMx - * @arg HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIMx / 2 - * @arg HRTIM_EVENTPRESCALER_DIV4: fEEVS=fHRTIMx / 4 - * @arg HRTIM_EVENTPRESCALER_DIV8: fEEVS=fHRTIMx / 8 - * @retval None - */ -void HRTIM_EventPrescalerConfig(HRTIM_TypeDef * HRTIMx, - uint32_t Prescaler) -{ - uint32_t HRTIM_eecr3; - - /* Check parameters */ - assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler)); - - /* Set the external event prescaler */ - HRTIM_eecr3 = HRTIMx->HRTIM_COMMON.EECR3; - HRTIM_eecr3 &= ~(HRTIM_EECR3_EEVSD); - HRTIM_eecr3 |= Prescaler; - - /* Update the HRTIMx registers */ - HRTIMx->HRTIM_COMMON.EECR3 = HRTIM_eecr3; -} - -/** - * @brief Configures the conditioning of fault input - * @param HRTIMx: pointer to HRTIMx peripheral - * @param Fault: fault input to configure - * This parameter can be one of the following values: - * @arg HRTIM_FAULT_1: Fault input 1 - * @arg HRTIM_FAULT_2: Fault input 2 - * @arg HRTIM_FAULT_3: Fault input 3 - * @arg HRTIM_FAULT_4: Fault input 4 - * @arg HRTIM_FAULT_5: Fault input 5 - * @param pFaultCfg: pointer to the fault conditioning configuration structure - * @retval None - */ -void HRTIM_FaultConfig(HRTIM_TypeDef * HRTIMx, - HRTIM_FaultCfgTypeDef* pFaultCfg, - uint32_t Fault) -{ - uint32_t HRTIM_fltinr1; - uint32_t HRTIM_fltinr2; - - /* Check parameters */ - assert_param(IS_HRTIM_FAULT(Fault)); - assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source)); - assert_param(IS_HRTIM_FAULTPOLARITY(pFaultCfg->Polarity)); - assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter)); - assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock)); - - /* Configure fault channel */ - HRTIM_fltinr1 = HRTIMx->HRTIM_COMMON.FLTINxR1; - HRTIM_fltinr2 = HRTIMx->HRTIM_COMMON.FLTINxR2; - - switch (Fault) - { - case HRTIM_FAULT_1: - { - HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK); - HRTIM_fltinr1 |= pFaultCfg->Polarity; - HRTIM_fltinr1 |= pFaultCfg->Source; - HRTIM_fltinr1 |= pFaultCfg->Filter; - HRTIM_fltinr1 |= pFaultCfg->Lock; - } - break; - case HRTIM_FAULT_2: - { - HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK); - HRTIM_fltinr1 |= (pFaultCfg->Polarity << 8); - HRTIM_fltinr1 |= (pFaultCfg->Source << 8); - HRTIM_fltinr1 |= (pFaultCfg->Filter << 8); - HRTIM_fltinr1 |= (pFaultCfg->Lock << 8); - } - break; - case HRTIM_FAULT_3: - { - HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK); - HRTIM_fltinr1 |= (pFaultCfg->Polarity << 16); - HRTIM_fltinr1 |= (pFaultCfg->Source << 16); - HRTIM_fltinr1 |= (pFaultCfg->Filter << 16); - HRTIM_fltinr1 |= (pFaultCfg->Lock << 16); - } - break; - case HRTIM_FAULT_4: - { - HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK); - HRTIM_fltinr1 |= (pFaultCfg->Polarity << 24); - HRTIM_fltinr1 |= (pFaultCfg->Source << 24); - HRTIM_fltinr1 |= (pFaultCfg->Filter << 24); - HRTIM_fltinr1 |= (pFaultCfg->Lock << 24); - } - break; - case HRTIM_FAULT_5: - { - HRTIM_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK); - HRTIM_fltinr2 |= pFaultCfg->Polarity; - HRTIM_fltinr2 |= pFaultCfg->Source; - HRTIM_fltinr2 |= pFaultCfg->Filter; - HRTIM_fltinr2 |= pFaultCfg->Lock; - } - break; - default: - break; - } - - /* Update the HRTIMx registers */ - HRTIMx->HRTIM_COMMON.FLTINxR1 = HRTIM_fltinr1; - HRTIMx->HRTIM_COMMON.FLTINxR2 = HRTIM_fltinr2; -} - -/** - * @brief Configures the fault conditioning block prescaler - * @param HRTIMx: pointer to HRTIMx peripheral - * @param Prescaler: Prescaler value - * This parameter can be one of the following values: - * @arg HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIMx - * @arg HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIMx / 2 - * @arg HRTIM_FAULTPRESCALER_DIV4: fFLTS=fHRTIMx / 4 - * @arg HRTIM_FAULTPRESCALER_DIV8: fFLTS=fHRTIMx / 8 - * @retval None - */ -void HRTIM_FaultPrescalerConfig(HRTIM_TypeDef * HRTIMx, - uint32_t Prescaler) -{ - uint32_t HRTIM_fltinr2; - - /* Check parameters */ - assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler)); - - /* Set the external event prescaler */ - HRTIM_fltinr2 = HRTIMx->HRTIM_COMMON.FLTINxR2; - HRTIM_fltinr2 &= ~(HRTIM_FLTINR2_FLTSD); - HRTIM_fltinr2 |= Prescaler; - - /* Update the HRTIMx registers */ - HRTIMx->HRTIM_COMMON.FLTINxR2 = HRTIM_fltinr2; -} - -/** - * @brief Enables or disables the HRTIMx Fault mode. - * @param HRTIMx: pointer to HRTIMx peripheral - * @param Fault: fault input to configure - * This parameter can be one of the following values: - * @arg HRTIM_FAULT_1: Fault input 1 - * @arg HRTIM_FAULT_2: Fault input 2 - * @arg HRTIM_FAULT_3: Fault input 3 - * @arg HRTIM_FAULT_4: Fault input 4 - * @arg HRTIM_FAULT_5: Fault input 5 - * @param Enable: Fault mode controller enabling - * This parameter can be one of the following values: - * @arg HRTIM_FAULT_ENABLED: Fault mode enabled - * @arg HRTIM_FAULT_DISABLED: Fault mode disabled - * @retval None - */ -void HRTIM_FaultModeCtl(HRTIM_TypeDef * HRTIMx, uint32_t Fault, uint32_t Enable) -{ - uint32_t HRTIM_fltinr1; - uint32_t HRTIM_fltinr2; - - /* Check parameters */ - assert_param(IS_HRTIM_FAULT(Fault)); - assert_param(IS_HRTIM_FAULTCTL(Enable)); - - /* Configure fault channel */ - HRTIM_fltinr1 = HRTIMx->HRTIM_COMMON.FLTINxR1; - HRTIM_fltinr2 = HRTIMx->HRTIM_COMMON.FLTINxR2; - - switch (Fault) - { - case HRTIM_FAULT_1: - { - HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT1E; - HRTIM_fltinr1 |= Enable; - } - break; - case HRTIM_FAULT_2: - { - HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT2E; - HRTIM_fltinr1 |= (Enable<< 8); - } - break; - case HRTIM_FAULT_3: - { - HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT3E; - HRTIM_fltinr1 |= (Enable << 16); - } - break; - case HRTIM_FAULT_4: - { - HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT4E; - HRTIM_fltinr1 |= (Enable << 24); - } - break; - case HRTIM_FAULT_5: - { - HRTIM_fltinr2 &= ~HRTIM_FLTINR2_FLT5E; - HRTIM_fltinr2 |= Enable; - } - break; - default: - break; - } - - /* Update the HRTIMx registers */ - HRTIMx->HRTIM_COMMON.FLTINxR1 = HRTIM_fltinr1; - HRTIMx->HRTIM_COMMON.FLTINxR2 = HRTIM_fltinr2; -} - -/** - * @brief Configures both the ADC trigger register update source and the ADC - * trigger source. - * @param HRTIMx: pointer to HRTIMx peripheral - * @param ADC trigger: ADC trigger to configure - * This parameter can be one of the following values: - * @arg HRTIM_ADCTRIGGER_1: ADC trigger 1 - * @arg HRTIM_ADCTRIGGER_2: ADC trigger 2 - * @arg HRTIM_ADCTRIGGER_3: ADC trigger 3 - * @arg HRTIM_ADCTRIGGER_4: ADC trigger 4 - * @param pADCTriggerCfg: pointer to the ADC trigger configuration structure - * @retval None - */ -void HRTIM_ADCTriggerConfig(HRTIM_TypeDef * HRTIMx, - uint32_t ADCTrigger, - HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg) -{ - uint32_t HRTIM_cr1; - - /* Check parameters */ - assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger)); - assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource)); - - /* Set the ADC trigger update source */ - HRTIM_cr1 = HRTIMx->HRTIM_COMMON.CR1; - - switch (ADCTrigger) - { - case HRTIM_ADCTRIGGER_1: - { - HRTIM_cr1 &= ~(HRTIM_CR1_ADC1USRC); - HRTIM_cr1 |= pADCTriggerCfg->UpdateSource; - - /* Set the ADC trigger 1 source */ - HRTIMx->HRTIM_COMMON.ADC1R = pADCTriggerCfg->Trigger; - } - break; - case HRTIM_ADCTRIGGER_2: - { - HRTIM_cr1 &= ~(HRTIM_CR1_ADC2USRC); - HRTIM_cr1 |= (pADCTriggerCfg->UpdateSource << 3); - - /* Set the ADC trigger 2 source */ - HRTIMx->HRTIM_COMMON.ADC2R = pADCTriggerCfg->Trigger; - } - break; - case HRTIM_ADCTRIGGER_3: - { - HRTIM_cr1 &= ~(HRTIM_CR1_ADC3USRC); - HRTIM_cr1 |= (pADCTriggerCfg->UpdateSource << 6); - - /* Set the ADC trigger 3 source */ - HRTIMx->HRTIM_COMMON.ADC3R = pADCTriggerCfg->Trigger; - } - case HRTIM_ADCTRIGGER_4: - { - HRTIM_cr1 &= ~(HRTIM_CR1_ADC4USRC); - HRTIM_cr1 |= (pADCTriggerCfg->UpdateSource << 9); - - /* Set the ADC trigger 4 source */ - HRTIMx->HRTIM_COMMON.ADC4R = pADCTriggerCfg->Trigger; - } - break; - default: - break; - } - - /* Update the HRTIMx registers */ - HRTIMx->HRTIM_COMMON.CR1 = HRTIM_cr1; -} - - -/** - * @brief Enables or disables the HRTIMx burst mode controller. - * @param HRTIMx: pointer to HRTIMx peripheral - * @param Enable: Burst mode controller enabling - * This parameter can be one of the following values: - * @arg HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled - * @arg HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled - * @retval None - */ -void HRTIM_BurstModeCtl(HRTIM_TypeDef * HRTIMx, uint32_t Enable) -{ - uint32_t HRTIM_bmcr; - - /* Check parameters */ - assert_param(IS_HRTIM_BURSTMODECTL(Enable)); - - /* Enable/Disable the burst mode controller */ - HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR; - HRTIM_bmcr &= ~(HRTIM_BMCR_BME); - HRTIM_bmcr |= Enable; - - /* Update the HRTIMx registers */ - HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr; -} - -/** - * @brief Triggers a software capture on the designed capture unit - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param CaptureUnit: Capture unit to trig - * This parameter can be one of the following values: - * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1 - * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 - * @retval None - * @note The 'software capture' bit in the capure configuration register is - * automatically reset by hardware - */ -void HRTIM_SoftwareCapture(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t CaptureUnit) -{ - /* Check parameters */ - assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); - assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit)); - - /* Force a software capture on concerned capture unit */ - switch (CaptureUnit) - { - case HRTIM_CAPTUREUNIT_1: - { - HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR |= HRTIM_CPT1CR_SWCPT; - } - break; - case HRTIM_CAPTUREUNIT_2: - { - HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR |= HRTIM_CPT2CR_SWCPT; - } - break; - default: - break; - } -} - -/** - * @brief Triggers the update of the registers of one or several timers - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimersToUpdate: timers concerned with the software register update - * This parameter can be any combination of the following values: - * @arg HRTIM_TIMERUPDATE_MASTER - * @arg HRTIM_TIMERUPDATE_A - * @arg HRTIM_TIMERUPDATE_B - * @arg HRTIM_TIMERUPDATE_C - * @arg HRTIM_TIMERUPDATE_D - * @arg HRTIM_TIMERUPDATE_E - * @retval None - * @note The 'software update' bits in the HRTIMx control register 2 register are - * automatically reset by hardware - */ -void HRTIM_SoftwareUpdate(HRTIM_TypeDef * HRTIMx, - uint32_t TimersToUpdate) -{ - /* Check parameters */ - assert_param(IS_HRTIM_TIMERUPDATE(TimersToUpdate)); - - /* Force timer(s) registers update */ - HRTIMx->HRTIM_COMMON.CR2 |= TimersToUpdate; - -} - -/** - * @brief Triggers the reset of one or several timers - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimersToUpdate: timers concerned with the software counter reset - * This parameter can be any combination of the following values: - * @arg HRTIM_TIMER_MASTER - * @arg HRTIM_TIMER_A - * @arg HRTIM_TIMER_B - * @arg HRTIM_TIMER_C - * @arg HRTIM_TIMER_D - * @arg HRTIM_TIMER_E - * @retval None - * @note The 'software reset' bits in the HRTIMx control register 2 are - * automatically reset by hardware - */ -void HRTIM_SoftwareReset(HRTIM_TypeDef * HRTIMx, - uint32_t TimersToReset) -{ - /* Check parameters */ - assert_param(IS_HRTIM_TIMERRESET(TimersToReset)); - - /* Force timer(s) registers update */ - HRTIMx->HRTIM_COMMON.CR2 |= TimersToReset; - -} - -/** - * @brief Forces the timer output to its active or inactive state - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param Output: Timer output - * This parameter can be one of the following values: - * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 - * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 - * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 - * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 - * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 - * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 - * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 - * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 - * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 - * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 - * @param OutputLevel: indicates whether the output is forced to its active or inactive state - * This parameter can be one of the following values: - * @arg HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active state - * @arg HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive state - * @retval None - * @note The 'software set/reset trigger' bit in the output set/reset registers - * is automatically reset by hardware - */ -void HRTIM_WaveformSetOutputLevel(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t Output, - uint32_t OutputLevel) -{ - /* Check parameters */ - assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output)); - assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel)); - - /* Force timer output level */ - switch (Output) - { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: - { - if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE) - { - /* Force output to its active state */ - HRTIMx->HRTIM_TIMERx[TimerIdx].SETx1R |= HRTIM_SET1R_SST; - } - else - { - /* Force output to its inactive state */ - HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx1R |= HRTIM_RST1R_SRT; - } - } - break; - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: - { - if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE) - { - /* Force output to its active state */ - HRTIMx->HRTIM_TIMERx[TimerIdx].SETx2R |= HRTIM_SET2R_SST; - } - else - { - /* Force output to its inactive state */ - HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx2R |= HRTIM_RST2R_SRT; - } - } - break; - default: - break; - } -} - - -/** - * @} - */ - -/** @defgroup HRTIM_Group4 Peripheral State methods - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State methods ##### - =============================================================================== - [..] - This subsection permit to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Returns actual value of the capture register of the designated capture unit - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param CaptureUnit: Capture unit to trig - * This parameter can be one of the following values: - * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1 - * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 - * @retval Captured value - */ -uint32_t HRTIM_GetCapturedValue(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t CaptureUnit) -{ - uint32_t captured_value = 0; - - /* Check parameters */ - assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); - assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit)); - - /* Read captured value */ - switch (CaptureUnit) - { - case HRTIM_CAPTUREUNIT_1: - { - captured_value = HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xR; - } - break; - case HRTIM_CAPTUREUNIT_2: - { - captured_value = HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xR; - } - break; - default: - break; - } - - return captured_value; -} - -/** - * @brief Returns actual level (active or inactive) of the designated output - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param Output: Timer output - * This parameter can be one of the following values: - * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 - * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 - * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 - * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 - * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 - * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 - * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 - * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 - * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 - * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 - * @retval Output level - * @note Returned output level is taken before the output stage (chopper, - * polarity). - */ -uint32_t HRTIM_WaveformGetOutputLevel(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t Output) -{ - uint32_t output_level = HRTIM_OUTPUTLEVEL_INACTIVE; - - /* Check parameters */ - assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output)); - - /* Read the output level */ - switch (Output) - { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: - { - if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != RESET) - { - output_level = HRTIM_OUTPUTLEVEL_ACTIVE; - } - else - { - output_level = HRTIM_OUTPUTLEVEL_INACTIVE; - } - } - break; - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: - { - if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != RESET) - { - output_level = HRTIM_OUTPUTLEVEL_ACTIVE; - } - else - { - output_level = HRTIM_OUTPUTLEVEL_INACTIVE; - } - } - break; - default: - break; - } - - return output_level; -} - -/** - * @brief Returns actual state (RUN, IDLE, FAULT) of the designated output - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param Output: Timer output - * This parameter can be one of the following values: - * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 - * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 - * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 - * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 - * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 - * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 - * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 - * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 - * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 - * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 - * @retval Output state - */ -uint32_t HRTIM_WaveformGetOutputState(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t Output) -{ - uint32_t output_bit = 0; - uint32_t output_state = HRTIM_OUTPUTSTATE_IDLE; - - /* Check parameters */ - assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output)); - - /* Set output state according to output control status and output disable status */ - switch (Output) - { - case HRTIM_OUTPUT_TA1: - { - output_bit = HRTIM_OENR_TA1OEN; - } - break; - case HRTIM_OUTPUT_TA2: - { - output_bit = HRTIM_OENR_TA2OEN; - } - break; - case HRTIM_OUTPUT_TB1: - { - output_bit = HRTIM_OENR_TB1OEN; - } - break; - case HRTIM_OUTPUT_TB2: - { - output_bit = HRTIM_OENR_TB2OEN; - } - break; - case HRTIM_OUTPUT_TC1: - { - output_bit = HRTIM_OENR_TC1OEN; - } - break; - case HRTIM_OUTPUT_TC2: - { - output_bit = HRTIM_OENR_TC2OEN; - } - break; - case HRTIM_OUTPUT_TD1: - { - output_bit = HRTIM_OENR_TD1OEN; - } - break; - case HRTIM_OUTPUT_TD2: - { - output_bit = HRTIM_OENR_TD2OEN; - } - break; - case HRTIM_OUTPUT_TE1: - { - output_bit = HRTIM_OENR_TE1OEN; - } - break; - case HRTIM_OUTPUT_TE2: - { - output_bit = HRTIM_OENR_TE2OEN; - } - break; - default: - break; - } - - if ((HRTIMx->HRTIM_COMMON.OENR & output_bit) != RESET) - { - /* Output is enabled: output in RUN state (whatever ouput disable status is)*/ - output_state = HRTIM_OUTPUTSTATE_RUN; - } - else - { - if ((HRTIMx->HRTIM_COMMON.ODSR & output_bit) != RESET) - { - /* Output is disabled: output in FAULT state */ - output_state = HRTIM_OUTPUTSTATE_FAULT; - } - else - { - /* Output is disabled: output in IDLE state */ - output_state = HRTIM_OUTPUTSTATE_IDLE; - } - } - - return(output_state); -} - -/** - * @brief Returns the level (active or inactive) of the designated output - * when the delayed protection was triggered - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @param Output: Timer output - * This parameter can be one of the following values: - * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 - * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 - * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 - * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 - * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 - * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 - * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 - * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 - * @arg HRTIM_OUTPUT_TD1: Timer E - Output 1 - * @arg HRTIM_OUTPUT_TD2: Timer E - Output 2 - * @retval Delayed protection status - */ -uint32_t HRTIM_GetDelayedProtectionStatus(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t Output) -{ - uint32_t delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE; - - /* Check parameters */ - assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output)); - - /* Read the delayed protection status */ - switch (Output) - { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: - { - if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != RESET) - { - /* Output 1 was active when the delayed idle protection was triggered */ - delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE; - } - else - { - /* Output 1 was inactive when the delayed idle protection was triggered */ - delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE; - } - } - break; - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: - { - if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != RESET) - { - /* Output 2 was active when the delayed idle protection was triggered */ - delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE; - } - else - { - /* Output 2 was inactive when the delayed idle protection was triggered */ - delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE; - } - } - break; - default: - break; - } - - return delayed_protection_status; -} - -/** - * @brief Returns the actual status (active or inactive) of the burst mode controller - * @param HRTIMx: pointer to HRTIMx peripheral - * @retval Burst mode controller status - */ -uint32_t HRTIM_GetBurstStatus(HRTIM_TypeDef * HRTIMx) -{ - uint32_t burst_mode_status; - - /* Read burst mode status */ - burst_mode_status = (HRTIMx->HRTIM_COMMON.BMCR & HRTIM_BMCR_BMSTAT); - - return burst_mode_status; -} - -/** - * @brief Indicates on which output the signal is currently active (when the - * push pull mode is enabled) - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @retval Burst mode controller status - */ -uint32_t HRTIM_GetCurrentPushPullStatus(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx) -{ - uint32_t current_pushpull_status; - - /* Check the parameters */ - assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); - - /* Read current push pull status */ - current_pushpull_status = (HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT); - - return current_pushpull_status; -} - - -/** - * @brief Indicates on which output the signal was applied, in push-pull mode - balanced fault mode or delayed idle mode, when the protection was triggered - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * This parameter can be one of the following values: - * @arg 0x0 to 0x4 for timers A to E - * @retval Idle Push Pull Status - */ -uint32_t HRTIM_GetIdlePushPullStatus(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx) -{ - uint32_t idle_pushpull_status; - - /* Check the parameters */ - assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); - - /* Read current push pull status */ - idle_pushpull_status = (HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT); - - return idle_pushpull_status; -} - -/** - * @brief Configures the master timer time base - * @param HRTIMx: pointer to HRTIMx peripheral - * @retval None - */ -void HRTIM_MasterBase_Config(HRTIM_TypeDef * HRTIMx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct) -{ - /* Set the prescaler ratio */ - HRTIMx->HRTIM_MASTER.MCR &= (uint32_t) ~(HRTIM_MCR_CK_PSC); - HRTIMx->HRTIM_MASTER.MCR |= (uint32_t)HRTIM_BaseInitStruct->PrescalerRatio; - - /* Set the operating mode */ - HRTIMx->HRTIM_MASTER.MCR &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG); - HRTIMx->HRTIM_MASTER.MCR |= (uint32_t)HRTIM_BaseInitStruct->Mode; - - /* Update the HRTIMx registers */ - HRTIMx->HRTIM_MASTER.MPER = HRTIM_BaseInitStruct->Period; - HRTIMx->HRTIM_MASTER.MREP = HRTIM_BaseInitStruct->RepetitionCounter; -} - -/** - * @brief Configures timing unit (timer A to timer E) time base - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * @retval None - */ -void HRTIM_TimingUnitBase_Config(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct) -{ - /* Set the prescaler ratio */ - HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC); - HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR |= (uint32_t)HRTIM_BaseInitStruct->PrescalerRatio; - - /* Set the operating mode */ - HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG); - HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR |= (uint32_t)HRTIM_BaseInitStruct->Mode; - - /* Update the HRTIMx registers */ - HRTIMx->HRTIM_TIMERx[TimerIdx].PERxR = HRTIM_BaseInitStruct->Period; - HRTIMx->HRTIM_TIMERx[TimerIdx].REPxR = HRTIM_BaseInitStruct->RepetitionCounter; -} - -/** - * @brief Configures the master timer in waveform mode - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * @param pTimerInit: pointer to the timer initialization data structure - * @retval None - */ -void HRTIM_MasterWaveform_Config(HRTIM_TypeDef * HRTIMx, - HRTIM_TimerInitTypeDef * pTimerInit) -{ - uint32_t HRTIM_mcr; - uint32_t HRTIM_bmcr; - - /* Configure master timer */ - HRTIM_mcr = HRTIMx->HRTIM_MASTER.MCR; - HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR; - - /* Enable/Disable the half mode */ - HRTIM_mcr &= ~(HRTIM_MCR_HALF); - HRTIM_mcr |= pTimerInit->HalfModeEnable; - - /* Enable/Disable the timer start upon synchronization event reception */ - HRTIM_mcr &= ~(HRTIM_MCR_SYNCSTRTM); - HRTIM_mcr |= pTimerInit->StartOnSync; - - /* Enable/Disable the timer reset upon synchronization event reception */ - HRTIM_mcr &= ~(HRTIM_MCR_SYNCRSTM); - HRTIM_mcr |= pTimerInit->ResetOnSync; - - /* Enable/Disable the DAC synchronization event generation */ - HRTIM_mcr &= ~(HRTIM_MCR_DACSYNC); - HRTIM_mcr |= pTimerInit->DACSynchro; - - /* Enable/Disable preload mechanism for timer registers */ - HRTIM_mcr &= ~(HRTIM_MCR_PREEN); - HRTIM_mcr |= pTimerInit->PreloadEnable; - - /* Master timer registers update handling */ - HRTIM_mcr &= ~(HRTIM_MCR_BRSTDMA); - HRTIM_mcr |= (pTimerInit->UpdateGating << 2); - - /* Enable/Disable registers update on repetition */ - HRTIM_mcr &= ~(HRTIM_MCR_MREPU); - HRTIM_mcr |= pTimerInit->RepetitionUpdate; - - /* Set the timer burst mode */ - HRTIM_bmcr &= ~(HRTIM_BMCR_MTBM); - HRTIM_bmcr |= pTimerInit->BurstMode; - - /* Update the HRTIMx registers */ - HRTIMx->HRTIM_MASTER.MCR = HRTIM_mcr; - HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr; - -} - -/** - * @brief Configures timing unit (timer A to timer E) in waveform mode - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * @param pTimerInit: pointer to the timer initialization data structure - * @retval None - */ -void HRTIM_TimingUnitWaveform_Config(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - HRTIM_TimerInitTypeDef * pTimerInit) -{ - uint32_t HRTIM_timcr; - uint32_t HRTIM_bmcr; - - /* Configure timing unit */ - HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR; - HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR; - - /* Enable/Disable the half mode */ - HRTIM_timcr &= ~(HRTIM_TIMCR_HALF); - HRTIM_timcr |= pTimerInit->HalfModeEnable; - - /* Enable/Disable the timer start upon synchronization event reception */ - HRTIM_timcr &= ~(HRTIM_TIMCR_SYNCSTRT); - HRTIM_timcr |= pTimerInit->StartOnSync; - - /* Enable/Disable the timer reset upon synchronization event reception */ - HRTIM_timcr &= ~(HRTIM_TIMCR_SYNCRST); - HRTIM_timcr |= pTimerInit->ResetOnSync; - - /* Enable/Disable the DAC synchronization event generation */ - HRTIM_timcr &= ~(HRTIM_TIMCR_DACSYNC); - HRTIM_timcr |= pTimerInit->DACSynchro; - - /* Enable/Disable preload mechanism for timer registers */ - HRTIM_timcr &= ~(HRTIM_TIMCR_PREEN); - HRTIM_timcr |= pTimerInit->PreloadEnable; - - /* Timing unit registers update handling */ - HRTIM_timcr &= ~(HRTIM_TIMCR_UPDGAT); - HRTIM_timcr |= pTimerInit->UpdateGating; - - /* Enable/Disable registers update on repetition */ - HRTIM_timcr &= ~(HRTIM_TIMCR_TREPU); - if (pTimerInit->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED) - { - HRTIM_timcr |= HRTIM_TIMCR_TREPU; - } - - /* Set the timer burst mode */ - switch (TimerIdx) - { - case HRTIM_TIMERINDEX_TIMER_A: - { - HRTIM_bmcr &= ~(HRTIM_BMCR_TABM); - HRTIM_bmcr |= ( pTimerInit->BurstMode << 1); - } - break; - case HRTIM_TIMERINDEX_TIMER_B: - { - HRTIM_bmcr &= ~(HRTIM_BMCR_TBBM); - HRTIM_bmcr |= ( pTimerInit->BurstMode << 2); - } - break; - case HRTIM_TIMERINDEX_TIMER_C: - { - HRTIM_bmcr &= ~(HRTIM_BMCR_TCBM); - HRTIM_bmcr |= ( pTimerInit->BurstMode << 3); - } - break; - case HRTIM_TIMERINDEX_TIMER_D: - { - HRTIM_bmcr &= ~(HRTIM_BMCR_TDBM); - HRTIM_bmcr |= ( pTimerInit->BurstMode << 4); - } - break; - case HRTIM_TIMERINDEX_TIMER_E: - { - HRTIM_bmcr &= ~(HRTIM_BMCR_TEBM); - HRTIM_bmcr |= ( pTimerInit->BurstMode << 5); - } - break; - default: - break; - } - - /* Update the HRTIMx registers */ - HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr; - HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr; -} - -/** - * @brief Configures a compare unit - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * @param CompareUnit: Compare unit identifier - * @param pCompareCfg: pointer to the compare unit configuration data structure - * @retval None - */ -void HRTIM_CompareUnitConfig(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t CompareUnit, - HRTIM_CompareCfgTypeDef * pCompareCfg) -{ - if (TimerIdx == HRTIM_TIMERINDEX_MASTER) - { - /* Configure the compare unit of the master timer */ - switch (CompareUnit) - { - case HRTIM_COMPAREUNIT_1: - { - HRTIMx->HRTIM_MASTER.MCMP1R = pCompareCfg->CompareValue; - } - break; - case HRTIM_COMPAREUNIT_2: - { - HRTIMx->HRTIM_MASTER.MCMP2R = pCompareCfg->CompareValue; - } - break; - case HRTIM_COMPAREUNIT_3: - { - HRTIMx->HRTIM_MASTER.MCMP3R = pCompareCfg->CompareValue; - } - break; - case HRTIM_COMPAREUNIT_4: - { - HRTIMx->HRTIM_MASTER.MCMP4R = pCompareCfg->CompareValue; - } - break; - default: - break; - } - } - else - { - /* Configure the compare unit of the timing unit */ - switch (CompareUnit) - { - case HRTIM_COMPAREUNIT_1: - { - HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->CompareValue; - } - break; - case HRTIM_COMPAREUNIT_2: - { - HRTIMx->HRTIM_TIMERx[TimerIdx].CMP2xR = pCompareCfg->CompareValue; - } - break; - case HRTIM_COMPAREUNIT_3: - { - HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->CompareValue; - } - break; - case HRTIM_COMPAREUNIT_4: - { - HRTIMx->HRTIM_TIMERx[TimerIdx].CMP4xR = pCompareCfg->CompareValue; - } - break; - default: - break; - } - } -} - -/** - * @brief Configures a capture unit - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * @param CaptureUnit: Capture unit identifier - * @param pCaptureCfg: pointer to the compare unit configuration data structure - * @retval None - */ -void HRTIM_CaptureUnitConfig(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t CaptureUnit, - uint32_t Event) -{ - uint32_t CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1; - - switch (Event) - { - case HRTIM_EVENT_1: - { - CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1; - } - break; - case HRTIM_EVENT_2: - { - CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2; - } - break; - case HRTIM_EVENT_3: - { - CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3; - } - break; - case HRTIM_EVENT_4: - { - CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4; - } - break; - case HRTIM_EVENT_5: - { - CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5; - } - break; - case HRTIM_EVENT_6: - { - CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6; - } - break; - case HRTIM_EVENT_7: - { - CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7; - } - break; - case HRTIM_EVENT_8: - { - CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8; - } - break; - case HRTIM_EVENT_9: - { - CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9; - } - break; - case HRTIM_EVENT_10: - { - CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10; - } - break; - default: - break; - - } - switch (CaptureUnit) - { - case HRTIM_CAPTUREUNIT_1: - { - HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR = CaptureTrigger; - } - break; - case HRTIM_CAPTUREUNIT_2: - { - HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR = CaptureTrigger; - } - break; - default: - break; - } -} - -/** - * @brief Configures the output of a timing unit - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * @param Output: timing unit output identifier - * @param pOutputCfg: pointer to the output configuration data structure - * @retval None - */ -void HRTIM_OutputConfig(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t Output, - HRTIM_OutputCfgTypeDef * pOutputCfg) -{ - uint32_t HRTIM_outr; - uint32_t shift = 0; - - HRTIM_outr = HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR; - - switch (Output) - { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: - { - /* Set the output set/reset crossbar */ - HRTIMx->HRTIM_TIMERx[TimerIdx].SETx1R = pOutputCfg->SetSource; - HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx1R = pOutputCfg->ResetSource; - - shift = 0; - } - break; - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: - { - /* Set the output set/reset crossbar */ - HRTIMx->HRTIM_TIMERx[TimerIdx].SETx2R = pOutputCfg->SetSource; - HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx2R = pOutputCfg->ResetSource; - - shift = 16; - } - break; - default: - break; - } - - /* Clear output config */ - HRTIM_outr &= ~((HRTIM_OUTR_POL1 | - HRTIM_OUTR_IDLM1 | - HRTIM_OUTR_IDLES1| - HRTIM_OUTR_FAULT1| - HRTIM_OUTR_CHP1 | - HRTIM_OUTR_DIDL1) << shift); - - /* Set the polarity */ - HRTIM_outr |= (pOutputCfg->Polarity << shift); - - /* Set the IDLE mode */ - HRTIM_outr |= (pOutputCfg->IdleMode << shift); - - /* Set the IDLE state */ - HRTIM_outr |= (pOutputCfg->IdleState << shift); - - /* Set the FAULT state */ - HRTIM_outr |= (pOutputCfg->FaultState << shift); - - /* Set the chopper mode */ - HRTIM_outr |= (pOutputCfg->ChopperModeEnable << shift); - - /* Set the burst mode entry mode */ - HRTIM_outr |= (pOutputCfg->BurstModeEntryDelayed << shift); - - /* Update HRTIMx register */ - HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR = HRTIM_outr; -} - -/** - * @brief Configures an external event channel - * @param HRTIMx: pointer to HRTIMx peripheral - * @param Event: Event channel identifier - * @param pEventCfg: pointer to the event channel configuration data structure - * @retval None - */ -static void HRTIM_ExternalEventConfig(HRTIM_TypeDef * HRTIMx, - uint32_t Event, - HRTIM_EventCfgTypeDef *pEventCfg) -{ - uint32_t hrtim_eecr1; - uint32_t hrtim_eecr2; - uint32_t hrtim_eecr3; - - /* Configure external event channel */ - hrtim_eecr1 = HRTIMx->HRTIM_COMMON.EECR1; - hrtim_eecr2 = HRTIMx->HRTIM_COMMON.EECR2; - hrtim_eecr3 = HRTIMx->HRTIM_COMMON.EECR3; - - switch (Event) - { - case HRTIM_EVENT_1: - { - hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST); - hrtim_eecr1 |= pEventCfg->Source; - hrtim_eecr1 |= pEventCfg->Polarity; - hrtim_eecr1 |= pEventCfg->Sensitivity; - /* Update the HRTIM registers (all bit fields but EE1FAST bit) */ - HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1; - /* Update the HRTIM registers (EE1FAST bit) */ - hrtim_eecr1 |= pEventCfg->FastMode; - HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1; - } - break; - case HRTIM_EVENT_2: - { - hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST); - hrtim_eecr1 |= (pEventCfg->Source << 6); - hrtim_eecr1 |= (pEventCfg->Polarity << 6); - hrtim_eecr1 |= (pEventCfg->Sensitivity << 6); - /* Update the HRTIM registers (all bit fields but EE2FAST bit) */ - HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1; - /* Update the HRTIM registers (EE2FAST bit) */ - hrtim_eecr1 |= (pEventCfg->FastMode << 6); - HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1; - } - break; - case HRTIM_EVENT_3: - { - hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST); - hrtim_eecr1 |= (pEventCfg->Source << 12); - hrtim_eecr1 |= (pEventCfg->Polarity << 12); - hrtim_eecr1 |= (pEventCfg->Sensitivity << 12); - /* Update the HRTIM registers (all bit fields but EE3FAST bit) */ - HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1; - /* Update the HRTIM registers (EE3FAST bit) */ - hrtim_eecr1 |= (pEventCfg->FastMode << 12); - HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1; - } - break; - case HRTIM_EVENT_4: - { - hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST); - hrtim_eecr1 |= (pEventCfg->Source << 18); - hrtim_eecr1 |= (pEventCfg->Polarity << 18); - hrtim_eecr1 |= (pEventCfg->Sensitivity << 18); - /* Update the HRTIM registers (all bit fields but EE4FAST bit) */ - HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1; - /* Update the HRTIM registers (EE4FAST bit) */ - hrtim_eecr1 |= (pEventCfg->FastMode << 18); - HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1; - } - break; - case HRTIM_EVENT_5: - { - hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST); - hrtim_eecr1 |= (pEventCfg->Source << 24); - hrtim_eecr1 |= (pEventCfg->Polarity << 24); - hrtim_eecr1 |= (pEventCfg->Sensitivity << 24); - /* Update the HRTIM registers (all bit fields but EE5FAST bit) */ - HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1; - /* Update the HRTIM registers (EE5FAST bit) */ - hrtim_eecr1 |= (pEventCfg->FastMode << 24); - HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1; - } - break; - case HRTIM_EVENT_6: - { - hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS); - hrtim_eecr2 |= pEventCfg->Source; - hrtim_eecr2 |= pEventCfg->Polarity; - hrtim_eecr2 |= pEventCfg->Sensitivity; - hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F); - hrtim_eecr3 |= pEventCfg->Filter; - /* Update the HRTIM registers */ - HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2; - HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3; - } - break; - case HRTIM_EVENT_7: - { - hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS); - hrtim_eecr2 |= (pEventCfg->Source << 6); - hrtim_eecr2 |= (pEventCfg->Polarity << 6); - hrtim_eecr2 |= (pEventCfg->Sensitivity << 6); - hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F); - hrtim_eecr3 |= (pEventCfg->Filter << 6); - /* Update the HRTIM registers */ - HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2; - HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3; - } - break; - case HRTIM_EVENT_8: - { - hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS); - hrtim_eecr2 |= (pEventCfg->Source << 12); - hrtim_eecr2 |= (pEventCfg->Polarity << 12); - hrtim_eecr2 |= (pEventCfg->Sensitivity << 12); - hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F); - hrtim_eecr3 |= (pEventCfg->Filter << 12); - /* Update the HRTIM registers */ - HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2; - HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3; - } - break; - case HRTIM_EVENT_9: - { - hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS); - hrtim_eecr2 |= (pEventCfg->Source << 18); - hrtim_eecr2 |= (pEventCfg->Polarity << 18); - hrtim_eecr2 |= (pEventCfg->Sensitivity << 18); - hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F); - hrtim_eecr3 |= (pEventCfg->Filter << 18); - /* Update the HRTIM registers */ - HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2; - HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3; - } - break; - case HRTIM_EVENT_10: - { - hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS); - hrtim_eecr2 |= (pEventCfg->Source << 24); - hrtim_eecr2 |= (pEventCfg->Polarity << 24); - hrtim_eecr2 |= (pEventCfg->Sensitivity << 24); - hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F); - hrtim_eecr3 |= (pEventCfg->Filter << 24); - /* Update the HRTIM registers */ - HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2; - HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3; - } - break; - default: - break; - } -} - -/** - * @brief Configures the timer counter reset - * @param HRTIMx: pointer to HRTIMx peripheral - * @param TimerIdx: Timer index - * @param Event: Event channel identifier - * @retval None - */ -void HRTIM_TIM_ResetConfig(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t Event) -{ - switch (Event) - { - case HRTIM_EVENT_1: - { - HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1; - } - break; - case HRTIM_EVENT_2: - { - HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2; - } - break; - case HRTIM_EVENT_3: - { - HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3; - } - break; - case HRTIM_EVENT_4: - { - HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4; - } - break; - case HRTIM_EVENT_5: - { - HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5; - } - break; - case HRTIM_EVENT_6: - { - HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6; - } - break; - case HRTIM_EVENT_7: - { - HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7; - } - break; - case HRTIM_EVENT_8: - { - HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8; - } - break; - case HRTIM_EVENT_9: - { - HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9; - } - break; - case HRTIM_EVENT_10: - { - HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10; - } - break; - default: - break; - } -} -/** - * @} - */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - -
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_hrtim.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2723 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_hrtim.h - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file contains all the functions prototypes for the HRTIM firmware - * library. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F30x_HRTIM_H -#define __STM32F30x_HRTIM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief HRTIM Configuration Structure definition - Time base related parameters - */ -typedef struct -{ - uint32_t Period; /*!< Specifies the timer period - The period value must be above 3 periods of the fHRTIM clock. - Maximum value is = 0xFFDF */ - uint32_t RepetitionCounter; /*!< Specifies the timer repetition period - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ - uint32_t PrescalerRatio; /*!< Specifies the timer clock prescaler ratio. - This parameter can be any value of @ref HRTIM_PrescalerRatio */ - uint32_t Mode; /*!< Specifies the counter operating mode - This parameter can be any value of @ref HRTIM_Mode */ -} HRTIM_BaseInitTypeDef; -/** - * @brief Waveform mode initialization parameters definition - */ -typedef struct { - uint32_t HalfModeEnable; /*!< Specifies whether or not half mode is enabled - This parameter can be a combination of @ref HRTIM_HalfModeEnable */ - uint32_t StartOnSync; /*!< Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled) - This parameter can be a combination of @ref HRTIM_StartOnSyncInputEvent */ - uint32_t ResetOnSync; /*!< Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled) - This parameter can be a combination of @ref HRTIM_ResetOnSyncInputEvent */ - uint32_t DACSynchro; /*!< Indicates whether or not the a DAC synchronization event is generated - This parameter can be any value of @ref HRTIM_DACSynchronization */ - uint32_t PreloadEnable; /*!< Specifies whether or not register preload is enabled - This parameter can be a combination of @ref HRTIM_RegisterPreloadEnable */ - uint32_t UpdateGating; /*!< Specifies how the update occurs with respect to a burst DMA transaction or - update enable inputs (Slave timers only) - This parameter can be any value of @ref HRTIM_UpdateGating */ - uint32_t BurstMode; /*!< Specifies how the timer behaves during a burst mode operation - This parameter can be a combination of @ref HRTIM_TimerBurstMode */ - uint32_t RepetitionUpdate; /*!< Specifies whether or not registers update is triggered by the repetition event - This parameter can be a combination of @ref HRTIM_TimerRepetitionUpdate */ -} HRTIM_TimerInitTypeDef; - -/** - * @brief Basic output compare mode configuration definition - */ -typedef struct { - uint32_t Mode; /*!< Specifies the output compare mode (toggle, active, inactive) - This parameter can be a combination of @ref HRTIM_BasicOCMode */ - uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register. - The compare value must be above or equal to 3 periods of the fHRTIM clock */ - uint32_t Polarity; /*!< Specifies the output polarity - This parameter can be any value of @ref HRTIM_Output_Polarity */ - uint32_t IdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state - This parameter can be any value of @ref HRTIM_OutputIDLEState */ -} HRTIM_BasicOCChannelCfgTypeDef; - -/** - * @brief Basic PWM output mode configuration definition - */ -typedef struct { - uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register. - The compare value must be above or equal to 3 periods of the fHRTIM clock */ - uint32_t Polarity; /*!< Specifies the output polarity - This parameter can be any value of @ref HRTIM_OutputPolarity */ - uint32_t IdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state - This parameter can be any value of @ref HRTIM_OutputIDLEState */ -} HRTIM_BasicPWMChannelCfgTypeDef; - -/** - * @brief Basic capture mode configuration definition - */ -typedef struct { - uint32_t CaptureUnit; /*!< Specifies the external event Channel - This parameter can be any 'EEVx' value of @ref HRTIM_CaptureUnit */ - uint32_t Event; /*!< Specifies the external event triggering the capture - This parameter can be any 'EEVx' value of @ref HRTIM_ExternalEventChannels */ - uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity) - This parameter can be a value of @ref HRTIM_ExternalEventPolarity */ - uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event - This parameter can be a value of @ref HRTIM_ExternalEventSensitivity */ - uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter - This parameter can be a value of @ref HRTIM_ExternalEventFilter */ -} HRTIM_BasicCaptureChannelCfgTypeDef; - -/** - * @brief Basic One Pulse mode configuration definition - */ -typedef struct { - uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register. - The compare value must be above or equal to 3 periods of the fHRTIM clock */ - uint32_t OutputPolarity; /*!< Specifies the output polarity - This parameter can be any value of @ref HRTIM_Output_Polarity */ - uint32_t OutputIdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state - This parameter can be any value of @ref HRTIM_Output_IDLE_State */ - uint32_t Event; /*!< Specifies the external event triggering the pulse generation - This parameter can be any 'EEVx' value of @ref HRTIM_Capture_Unit_Trigger */ - uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity) - This parameter can be a value of @ref HRTIM_ExternalEventPolarity */ - uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event - This parameter can be a value of @ref HRTIM_ExternalEventSensitivity */ - uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter - This parameter can be a value of @ref HRTIM_ExternalEventFilter */ -} HRTIM_BasicOnePulseChannelCfgTypeDef; - -/** - * @brief Timer configuration definition - */ -typedef struct { - uint32_t PushPull; /*!< Specifies whether or not the push-pull mode is enabled - This parameter can be a value of @ref HRTIM_TimerPushPullMode */ - uint32_t FaultEnable; /*!< Specifies which fault channels are enabled for the timer - This parameter can be a combination of @ref HRTIM_TimerFaultEnabling */ - uint32_t FaultLock; /*!< Specifies whether or not fault enabling status is write protected - This parameter can be a value of @ref HRTIM_TimerFaultLock */ - uint32_t DeadTimeInsertion; /*!< Specifies whether or not dead time insertion is enabled for the timer - This parameter can be a value of @ref HRTIM_TimerDeadtimeInsertion */ - uint32_t DelayedProtectionMode; /*!< Specifies the delayed protection mode - This parameter can be a value of @ref HRTIM_TimerDelayedProtectionMode */ - uint32_t UpdateTrigger; /*!< Specifies source(s) triggering the timer registers update - This parameter can be a combination of @ref HRTIM_TimerUpdateTrigger */ - uint32_t ResetTrigger; /*!< Specifies source(s) triggering the timer counter reset - This parameter can be a combination of @ref HRTIM_TimerResetTrigger */ - uint32_t ResetUpdate; /*!< Specifies whether or not registers update is triggered when the timer counter is reset - This parameter can be a combination of @ref HRTIM_TimerResetUpdate */ -} HRTIM_TimerCfgTypeDef; - -/** - * @brief Compare unit configuration definition - */ -typedef struct { - uint32_t CompareValue; /*!< Specifies the compare value of the timer compare unit - the minimum value must be greater than or equal to 3 periods of the fHRTIM clock - the maximum value must be less than or equal to 0xFFFF - 1 periods of the fHRTIM clock */ - uint32_t AutoDelayedMode; /*!< Specifies the auto delayed mode for compare unit 2 or 4 - This parameter can be a value of @ref HRTIM_CompareUnitAutoDelayedMode */ - uint32_t AutoDelayedTimeout; /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected - CompareValue + AutoDelayedTimeout must be less than 0xFFFF */ -} HRTIM_CompareCfgTypeDef; - -/** - * @brief Capture unit configuration definition - */ -typedef struct { - uint32_t Trigger; /*!< Specifies source(s) triggering the capture - This parameter can be a combination of @ref HRTIM_CaptureUnitTrigger */ -} HRTIM_CaptureCfgTypeDef; - -/** - * @brief Output configuration definition - */ -typedef struct { - uint32_t Polarity; /*!< Specifies the output polarity - This parameter can be any value of @ref HRTIM_Output_Polarity */ - uint32_t SetSource; /*!< Specifies the event(s) transitioning the output from its inactive level to its active level - This parameter can be any value of @ref HRTIM_OutputSetSource */ - uint32_t ResetSource; /*!< Specifies the event(s) transitioning the output from its active level to its inactive level - This parameter can be any value of @ref HRTIM_OutputResetSource */ - uint32_t IdleMode; /*!< Specifies whether or not the output is affected by a burst mode operation - This parameter can be any value of @ref HRTIM_OutputIdleMode */ - uint32_t IdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state - This parameter can be any value of @ref HRTIM_OutputIDLEState */ - uint32_t FaultState; /*!< Specifies whether the output level is active or inactive when in FAULT state - This parameter can be any value of @ref HRTIM_OutputFAULTState */ - uint32_t ChopperModeEnable; /*!< Indicates whether or not the chopper mode is enabled - This parameter can be any value of @ref HRTIM_OutputChopperModeEnable */ - uint32_t BurstModeEntryDelayed; /* !<Indicates whether or not deadtime is inserted when entering the IDLE state - during a burst mode operation - This parameters can be any value of @ref HRTIM_OutputBurstModeEntryDelayed */ -} HRTIM_OutputCfgTypeDef; - -/** - * @brief External event filtering in timing units configuration definition - */ -typedef struct { - uint32_t Filter; /*!< Specifies the type of event filtering within the timing unit - This parameter can be a value of @ref HRTIM_TimerExternalEventFilter */ - uint32_t Latch; /*!< Specifies whether or not the signal is latched - This parameter can be a value of @ref HRTIM_TimerExternalEventLatch */ -} HRTIM_TimerEventFilteringCfgTypeDef; - -/** - * @brief Dead time feature configuration definition - */ -typedef struct { - uint32_t Prescaler; /*!< Specifies the Deadtime Prescaler - This parameter can be a number between 0x0 and = 0x7 */ - uint32_t RisingValue; /*!< Specifies the Deadtime following a rising edge - This parameter can be a number between 0x0 and 0xFF */ - uint32_t RisingSign; /*!< Specifies whether the deadtime is positive or negative on rising edge - This parameter can be a value of @ref HRTIM_DeadtimeRisingSign */ - uint32_t RisingLock; /*!< Specifies whether or not deadtime rising settings (value and sign) are write protected - This parameter can be a value of @ref HRTIM_DeadtimeRisingLock */ - uint32_t RisingSignLock; /*!< Specifies whether or not deadtime rising sign is write protected - This parameter can be a value of @ref HRTIM_DeadtimeRisingSignLock */ - uint32_t FallingValue; /*!< Specifies the Deadtime following a falling edge - This parameter can be a number between 0x0 and 0xFF */ - uint32_t FallingSign; /*!< Specifies whether the deadtime is positive or negative on falling edge - This parameter can be a value of @ref HRTIM_DeadtimeFallingSign */ - uint32_t FallingLock; /*!< Specifies whether or not deadtime falling settings (value and sign) are write protected - This parameter can be a value of @ref HRTIM_DeadtimeFallingLock */ - uint32_t FallingSignLock; /*!< Specifies whether or not deadtime falling sign is write protected - This parameter can be a value of @ref HRTIM_DeadtimeFallingSignLock */ -} HRTIM_DeadTimeCfgTypeDef; - -/** - * @brief Chopper mode configuration definition - */ -typedef struct { - uint32_t CarrierFreq; /*!< Specifies the Timer carrier frequency value. - This parameter can be a value between 0 and 0xF */ - uint32_t DutyCycle; /*!< Specifies the Timer chopper duty cycle value. - This parameter can be a value between 0 and 0x7 */ - uint32_t StartPulse; /*!< Specifies the Timer pulse width value. - This parameter can be a value between 0 and 0xF */ -} HRTIM_ChopperModeCfgTypeDef; - -/** - * @brief Master synchronization configuration definition - */ -typedef struct { - uint32_t SyncInputSource; /*!< Specifies the external synchronization input source - This parameter can be a value of @ref HRTIM_SynchronizationInputSource */ - uint32_t SyncOutputSource; /*!< Specifies the source and event to be sent on the external synchronization outputs - This parameter can be a value of @ref HRTIM_SynchronizationOutputSource */ - uint32_t SyncOutputPolarity; /*!< Specifies the conditioning of the event to be sent on the external synchronization outputs - This parameter can be a value of @ref HRTIM_SynchronizationOutputPolarity */ -} HRTIM_SynchroCfgTypeDef; - -/** - * @brief External event channel configuration definition - */ -typedef struct { - uint32_t Source; /*!< Identifies the source of the external event - This parameter can be a value of @ref HRTIM_ExternalEventSources */ - uint32_t Polarity; /*!< Specifies the polarity of the external event (in case of level sensitivity) - This parameter can be a value of @ref HRTIM_ExternalEventPolarity */ - uint32_t Sensitivity; /*!< Specifies the sensitivity of the external event - This parameter can be a value of @ref HRTIM_ExternalEventSensitivity */ - uint32_t Filter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter - This parameter can be a value of @ref HRTIM_ExternalEventFilter */ - uint32_t FastMode; /*!< Indicates whether or not low latency mode is enabled for the external event - This parameter can be a value of @ref HRTIM_ExternalEventFastMode */ -} HRTIM_EventCfgTypeDef; - -/** - * @brief Fault channel configuration definition - */ -typedef struct { - uint32_t Source; /*!< Identifies the source of the fault - This parameter can be a value of @ref HRTIM_FaultSources */ - uint32_t Polarity; /*!< Specifies the polarity of the fault event - This parameter can be a value of @ref HRTIM_FaultPolarity */ - uint32_t Filter; /*!< Defines the frequency used to sample the Fault input and the length of the digital filter - This parameter can be a value of @ref HRTIM_FaultFilter */ - uint32_t Lock; /*!< Indicates whether or not fault programming bits are write protected - This parameter can be a value of @ref HRTIM_FaultLock */ -} HRTIM_FaultCfgTypeDef; - -/** - * @brief Burst mode configuration definition - */ -typedef struct { - uint32_t Mode; /*!< Specifies the burst mode operating mode - This parameter can be a value of @ref HRTIM_BurstModeOperatingMode */ - uint32_t ClockSource; /*!< Specifies the burst mode clock source - This parameter can be a value of @ref HRTIM_BurstModeClockSource */ - uint32_t Prescaler; /*!< Specifies the burst mode prescaler - This parameter can be a value of @ref HRTIM_BurstModePrescaler */ - uint32_t PreloadEnable; /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER) - This parameter can be a combination of @ref HRTIM_BurstModeRegisterPreloadEnable */ - uint32_t Trigger; /*!< Specifies the event(s) triggering the burst operation - This parameter can be a combination of @ref HRTIM_BurstModeTrigger */ - uint32_t IdleDuration; /*!< Specifies number of periods during which the selected timers are in idle state - This parameter can be a number between 0x0 and 0xFFFF */ - uint32_t Period; /*!< Specifies burst mode repetition period - This parameter can be a number between 0x1 and 0xFFFF */ -} HRTIM_BurstModeCfgTypeDef; - -/** - * @brief ADC trigger configuration definition - */ -typedef struct { - uint32_t UpdateSource; /*!< Specifies the ADC trigger update source - This parameter can be a combination of @ref HRTIM_ADCTriggerUpdateSource */ - uint32_t Trigger; /*!< Specifies the event(s) triggering the ADC conversion - This parameter can be a combination of @ref HRTIM_ADCTriggerEvent */ -} HRTIM_ADCTriggerCfgTypeDef; - - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup HRTIM_Exported_Constants - * @{ - */ - -/** @defgroup HRTIM_TimerIndex - * @{ - * @brief Constants defining the timer indexes - */ -#define HRTIM_TIMERINDEX_TIMER_A (uint32_t)0x0 /*!< Index associated to timer A */ -#define HRTIM_TIMERINDEX_TIMER_B (uint32_t)0x1 /*!< Index associated to timer B */ -#define HRTIM_TIMERINDEX_TIMER_C (uint32_t)0x2 /*!< Index associated to timer C */ -#define HRTIM_TIMERINDEX_TIMER_D (uint32_t)0x3 /*!< Index associated to timer D */ -#define HRTIM_TIMERINDEX_TIMER_E (uint32_t)0x4 /*!< Index associated to timer E */ -#define HRTIM_TIMERINDEX_MASTER (uint32_t)0x5 /*!< Index associated to master timer */ -#define HRTIM_COMMONINDEX (uint32_t)0x6 /*!< Index associated to Common space */ - -#define IS_HRTIM_TIMERINDEX(TIMERINDEX)\ - (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) - -#define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\ - (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) -/** - * @} - */ - -/** @defgroup HRTIM_TimerIdentifier - * @{ - * @brief Constants defining timer identifiers - */ -#define HRTIM_TIMERID_MASTER (HRTIM_MCR_MCEN) /*!< Master identifier*/ -#define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN) /*!< Timer A identifier */ -#define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN) /*!< Timer B identifier */ -#define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN) /*!< Timer C identifier */ -#define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN) /*!< Timer D identifier */ -#define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN) /*!< Timer E identifier */ - -#define IS_HRTIM_TIMERID(TIMERID)\ - (((TIMERID) == HRTIM_TIMERID_MASTER) || \ - ((TIMERID) == HRTIM_TIMERID_TIMER_A) || \ - ((TIMERID) == HRTIM_TIMERID_TIMER_B) || \ - ((TIMERID) == HRTIM_TIMERID_TIMER_C) || \ - ((TIMERID) == HRTIM_TIMERID_TIMER_D) || \ - ((TIMERID) == HRTIM_TIMERID_TIMER_E)) -/** - * @} - */ - -/** @defgroup HRTIM_CompareUnit - * @{ - * @brief Constants defining compare unit identifiers - */ -#define HRTIM_COMPAREUNIT_1 (uint32_t)0x00000001 /*!< Compare unit 1 identifier */ -#define HRTIM_COMPAREUNIT_2 (uint32_t)0x00000002 /*!< Compare unit 2 identifier */ -#define HRTIM_COMPAREUNIT_3 (uint32_t)0x00000004 /*!< Compare unit 3 identifier */ -#define HRTIM_COMPAREUNIT_4 (uint32_t)0x00000008 /*!< Compare unit 4 identifier */ - -#define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\ - (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \ - ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \ - ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \ - ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4)) - /** - * @} - */ - -/** @defgroup HRTIM_CaptureUnit - * @{ - * @brief Constants defining capture unit identifiers - */ -#define HRTIM_CAPTUREUNIT_1 (uint32_t)0x00000001 /*!< Capture unit 1 identifier */ -#define HRTIM_CAPTUREUNIT_2 (uint32_t)0x00000002 /*!< Capture unit 2 identifier */ - -#define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\ - (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \ - ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2)) -/** - * @} - */ - -/** @defgroup HRTIM_TimerOutput - * @{ - * @brief Constants defining timer output identifiers - */ -#define HRTIM_OUTPUT_TA1 (uint32_t)0x00000001 /*!< Timer A - Ouput 1 identifier */ -#define HRTIM_OUTPUT_TA2 (uint32_t)0x00000002 /*!< Timer A - Ouput 2 identifier */ -#define HRTIM_OUTPUT_TB1 (uint32_t)0x00000004 /*!< Timer B - Ouput 1 identifier */ -#define HRTIM_OUTPUT_TB2 (uint32_t)0x00000008 /*!< Timer B - Ouput 2 identifier */ -#define HRTIM_OUTPUT_TC1 (uint32_t)0x00000010 /*!< Timer C - Ouput 1 identifier */ -#define HRTIM_OUTPUT_TC2 (uint32_t)0x00000020 /*!< Timer C - Ouput 2 identifier */ -#define HRTIM_OUTPUT_TD1 (uint32_t)0x00000040 /*!< Timer D - Ouput 1 identifier */ -#define HRTIM_OUTPUT_TD2 (uint32_t)0x00000080 /*!< Timer D - Ouput 2 identifier */ -#define HRTIM_OUTPUT_TE1 (uint32_t)0x00000100 /*!< Timer E - Ouput 1 identifier */ -#define HRTIM_OUTPUT_TE2 (uint32_t)0x00000200 /*!< Timer E - Ouput 2 identifier */ - -#define IS_HRTIM_OUTPUT(OUTPUT)\ - (((OUTPUT) == HRTIM_OUTPUT_TA1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TA2) || \ - ((OUTPUT) == HRTIM_OUTPUT_TB1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TB2) || \ - ((OUTPUT) == HRTIM_OUTPUT_TC1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TC2) || \ - ((OUTPUT) == HRTIM_OUTPUT_TD1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TD2) || \ - ((OUTPUT) == HRTIM_OUTPUT_TE1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TE2)) - -#define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\ - ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ - (((OUTPUT) == HRTIM_OUTPUT_TA1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TA2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ - (((OUTPUT) == HRTIM_OUTPUT_TB1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TB2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ - (((OUTPUT) == HRTIM_OUTPUT_TC1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TC2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ - (((OUTPUT) == HRTIM_OUTPUT_TD1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TD2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ - (((OUTPUT) == HRTIM_OUTPUT_TE1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TE2)))) -/** - * @} - */ - -/** @defgroup HRTIM_ADCTrigger - * @{ - * @brief Constants defining ADC triggers identifiers - */ -#define HRTIM_ADCTRIGGER_1 (uint32_t)0x00000001 /*!< ADC trigger 1 identifier */ -#define HRTIM_ADCTRIGGER_2 (uint32_t)0x00000002 /*!< ADC trigger 1 identifier */ -#define HRTIM_ADCTRIGGER_3 (uint32_t)0x00000004 /*!< ADC trigger 1 identifier */ -#define HRTIM_ADCTRIGGER_4 (uint32_t)0x00000008 /*!< ADC trigger 1 identifier */ - -#define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\ - (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4)) -/** - * @} - */ - -/** @defgroup HRTIM_ExternalEventChannels - * @{ - * @brief Constants defining external event channel identifiers - */ -#define HRTIM_EVENT_NONE ((uint32_t)0x00000000) /*!< Undefined event channel */ -#define HRTIM_EVENT_1 ((uint32_t)0x00000001) /*!< External event channel 1 identifier */ -#define HRTIM_EVENT_2 ((uint32_t)0x00000002) /*!< External event channel 2 identifier */ -#define HRTIM_EVENT_3 ((uint32_t)0x00000004) /*!< External event channel 3 identifier */ -#define HRTIM_EVENT_4 ((uint32_t)0x00000008) /*!< External event channel 4 identifier */ -#define HRTIM_EVENT_5 ((uint32_t)0x00000010) /*!< External event channel 5 identifier */ -#define HRTIM_EVENT_6 ((uint32_t)0x00000020) /*!< External event channel 6 identifier */ -#define HRTIM_EVENT_7 ((uint32_t)0x00000040) /*!< External event channel 7 identifier */ -#define HRTIM_EVENT_8 ((uint32_t)0x00000080) /*!< External event channel 8 identifier */ -#define HRTIM_EVENT_9 ((uint32_t)0x00000100) /*!< External event channel 9 identifier */ -#define HRTIM_EVENT_10 ((uint32_t)0x00000200) /*!< External event channel 10 identifier */ - -#define IS_HRTIM_EVENT(EVENT)\ - (((EVENT) == HRTIM_EVENT_1) || \ - ((EVENT) == HRTIM_EVENT_2) || \ - ((EVENT) == HRTIM_EVENT_3) || \ - ((EVENT) == HRTIM_EVENT_4) || \ - ((EVENT) == HRTIM_EVENT_5) || \ - ((EVENT) == HRTIM_EVENT_6) || \ - ((EVENT) == HRTIM_EVENT_7) || \ - ((EVENT) == HRTIM_EVENT_8) || \ - ((EVENT) == HRTIM_EVENT_9) || \ - ((EVENT) == HRTIM_EVENT_10)) -/** - * @} - */ - -/** @defgroup HRTIM_FaultChannel - * @{ - * @brief Constants defining fault channel identifiers - */ -#define HRTIM_FAULT_1 ((uint32_t)0x01) /*!< Fault channel 1 identifier */ -#define HRTIM_FAULT_2 ((uint32_t)0x02) /*!< Fault channel 2 identifier */ -#define HRTIM_FAULT_3 ((uint32_t)0x04) /*!< Fault channel 3 identifier */ -#define HRTIM_FAULT_4 ((uint32_t)0x08) /*!< Fault channel 4 identifier */ -#define HRTIM_FAULT_5 ((uint32_t)0x10) /*!< Fault channel 5 identifier */ - -#define IS_HRTIM_FAULT(FAULT)\ - (((FAULT) == HRTIM_FAULT_1) || \ - ((FAULT) == HRTIM_FAULT_2) || \ - ((FAULT) == HRTIM_FAULT_3) || \ - ((FAULT) == HRTIM_FAULT_4) || \ - ((FAULT) == HRTIM_FAULT_5)) -/** - * @} - */ - - - /** @defgroup HRTIM_PrescalerRatio - * @{ - * @brief Constants defining timer high-resolution clock prescaler ratio. - */ -#define HRTIM_PRESCALERRATIO_MUL32 ((uint32_t)0x00000000) /*!< fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */ -#define HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001) /*!< fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */ -#define HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002) /*!< fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */ -#define HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003) /*!< fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */ -#define HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004) /*!< fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */ -#define HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005) /*!< fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */ -#define HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006) /*!< fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */ -#define HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007) /*!< fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */ - -#define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\ - (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4)) -/** - * @} - */ - -/** @defgroup HRTIM_Mode - * @{ - * @brief Constants defining timer counter operating mode. - */ -#define HRTIM_MODE_CONTINOUS ((uint32_t)0x00000008) /*!< The timer operates in continuous (free-running) mode */ -#define HRTIM_MODE_SINGLESHOT ((uint32_t)0x00000000) /*!< The timer operates in non retriggerable single-shot mode */ -#define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE ((uint32_t)0x00000010) /*!< The timer operates in retriggerable single-shot mode */ - -#define IS_HRTIM_MODE(MODE)\ - (((MODE) == HRTIM_MODE_CONTINOUS) || \ - ((MODE) == HRTIM_MODE_SINGLESHOT) || \ - ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) - -#define IS_HRTIM_MODE_ONEPULSE(MODE)\ - (((MODE) == HRTIM_MODE_SINGLESHOT) || \ - ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) - -/** - * @} - */ - -/** @defgroup HRTIM_HalfModeEnable - * @{ - * @brief Constants defining half mode enabling status. - */ -#define HRTIM_HALFMODE_DISABLED ((uint32_t)0x00000000) /*!< Half mode is disabled */ -#define HRTIM_HALFMODE_ENABLED ((uint32_t)0x00000020) /*!< Half mode is enabled */ - -#define IS_HRTIM_HALFMODE(HALFMODE)\ - (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \ - ((HALFMODE) == HRTIM_HALFMODE_ENABLED)) -/** - * @} - */ - -/** @defgroup HRTIM_StartOnSyncInputEvent - * @{ - * @brief Constants defining the timer behavior following the synchronization event - */ -#define HRTIM_SYNCSTART_DISABLED ((uint32_t)0x00000000) /*!< Synchronization input event has effect on the timer */ -#define HRTIM_SYNCSTART_ENABLED (HRTIM_MCR_SYNCSTRTM) /*!< Synchronization input event starts the timer */ - -#define IS_HRTIM_SYNCSTART(SYNCSTART)\ - (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \ - ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED)) -/** - * @} - */ - -/** @defgroup HRTIM_ResetOnSyncInputEvent - * @{ - * @brief Constants defining the timer behavior following the synchronization event - */ -#define HRTIM_SYNCRESET_DISABLED ((uint32_t)0x00000000) /*!< Synchronization input event has effect on the timer */ -#define HRTIM_SYNCRESET_ENABLED (HRTIM_MCR_SYNCRSTM) /*!< Synchronization input event resets the timer */ - -#define IS_HRTIM_SYNCRESET(SYNCRESET)\ - (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \ - ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED)) -/** - * @} - */ - -/** @defgroup HRTIM_DACSynchronization - * @{ - * @brief Constants defining on which output the DAC synchronization event is sent - */ -#define HRTIM_DACSYNC_NONE (uint32_t)0x00000000 /*!< No DAC synchronization event generated */ -#define HRTIM_DACSYNC_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */ -#define HRTIM_DACSYNC_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */ -#define HRTIM_DACSYNC_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC update generated on DACTrigOut3 output upon timer update */ - -#define IS_HRTIM_DACSYNC(DACSYNC)\ - (((DACSYNC) == HRTIM_DACSYNC_NONE) || \ - ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \ - ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \ - ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3)) -/** - * @} - */ - -/** @defgroup HRTIM_RegisterPreloadEnable - * @{ - * @brief Constants defining whether a write access into a preloadable - * register is done into the active or the preload register. - */ -#define HRTIM_PRELOAD_DISABLED ((uint32_t)0x00000000) /*!< Preload disabled: the write access is directly done into the active register */ -#define HRTIM_PRELOAD_ENABLED (HRTIM_MCR_PREEN) /*!< Preload enabled: the write access is done into the preload register */ - -#define IS_HRTIM_PRELOAD(PRELOAD)\ - (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \ - ((PRELOAD) == HRTIM_PRELOAD_ENABLED)) -/** - * @} - */ - -/** @defgroup HRTIM_UpdateGating - * @{ - * @brief Constants defining how the update occurs relatively to the burst DMA - * transaction and the external update request on update enable inputs 1 to 3. - */ -#define HRTIM_UPDATEGATING_INDEPENDENT (uint32_t)0x00000000 /*!< Update done independently from the DMA burst transfer completion */ -#define HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */ -#define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/ -#define HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 */ -#define HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 */ -#define HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 */ -#define HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1 */ -#define HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 */ -#define HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 */ - -#define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\ - (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE)) - -#define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\ - (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE)) -/** - * @} - */ - -/** @defgroup HRTIM_TimerBurstMode - * @{ - * @brief Constants defining how the timer behaves during a burst - mode operation. - */ -#define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /*!< Timer counter clock is maintained and the timer operates normally */ -#define HRTIM_TIMERBURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */ - -#define IS_HRTIM_TIMERBURSTMODE(TIMERBURSTMODE) \ - (((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \ - ((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER)) -/** - * @} - */ - -/** @defgroup HRTIM_TimerRepetitionUpdate - * @{ - * @brief Constants defining whether registers are updated when the timer - * repetition period is completed (either due to roll-over or - * reset events) - */ -#define HRTIM_UPDATEONREPETITION_DISABLED (uint32_t)0x00000000 /*!< Update on repetition disabled */ -#define HRTIM_UPDATEONREPETITION_ENABLED (HRTIM_MCR_MREPU) /*!< Update on repetition enabled */ - -#define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \ - (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \ - ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED)) -/** - * @} - */ - - -/** @defgroup HRTIM_TimerPushPullMode - * @{ - * @brief Constants defining whether or not the push-pull mode is enabled for - * a timer. - */ -#define HRTIM_TIMPUSHPULLMODE_DISABLED ((uint32_t)0x00000000) /*!< Push-Pull mode disabled */ -#define HRTIM_TIMPUSHPULLMODE_ENABLED ((uint32_t)HRTIM_TIMCR_PSHPLL) /*!< Push-Pull mode enabled */ - -#define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\ - (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \ - ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED)) -/** - * @} - */ - -/** @defgroup HRTIM_TimerFaultEnabling - * @{ - * @brief Constants defining whether a faut channel is enabled for a timer - */ -#define HRTIM_TIMFAULTENABLE_NONE (uint32_t)0x00000000 /*!< No fault enabled */ -#define HRTIM_TIMFAULTENABLE_FAULT1 (HRTIM_FLTR_FLT1EN) /*!< Fault 1 enabled */ -#define HRTIM_TIMFAULTENABLE_FAULT2 (HRTIM_FLTR_FLT2EN) /*!< Fault 2 enabled */ -#define HRTIM_TIMFAULTENABLE_FAULT3 (HRTIM_FLTR_FLT3EN) /*!< Fault 3 enabled */ -#define HRTIM_TIMFAULTENABLE_FAULT4 (HRTIM_FLTR_FLT4EN) /*!< Fault 4 enabled */ -#define HRTIM_TIMFAULTENABLE_FAULT5 (HRTIM_FLTR_FLT5EN) /*!< Fault 5 enabled */ - -#define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0) == 0x00000000) - -/** - * @} - */ - -/** @defgroup HRTIM_TimerFaultLock - * @{ - * @brief Constants defining whether or not fault enabling bits are write - * protected for a timer - */ -#define HRTIM_TIMFAULTLOCK_READWRITE ((uint32_t)0x00000000) /*!< Timer fault enabling bits are read/write */ -#define HRTIM_TIMFAULTLOCK_READONLY (HRTIM_FLTR_FLTCLK) /*!< Timer fault enabling bits are read only */ - -#define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\ - (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \ - ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY)) -/** - * @} - */ - -/** @defgroup HRTIM_TimerDeadtimeInsertion - * @{ - * @brief Constants defining whether or not fault the dead time insertion - * feature is enabled for a timer - */ -#define HRTIM_TIMDEADTIMEINSERTION_DISABLED ((uint32_t)0x00000000) /*!< Output 1 and output 2 signals are independent */ -#define HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN /*!< Deadtime is inserted between output 1 and output 2 */ - -#define IS_HRTIM_TIMDEADTIMEINSERTION(TIMDEADTIMEINSERTION)\ - (((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \ - ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)) -/** - * @} - */ - -/** @defgroup HRTIM_TimerDelayedProtectionMode - * @{ - * @brief Constants defining all possible delayed protection modes - * for a timer. Also define the source and outputs on which the delayed - * protection schemes are applied - */ -#define HRTIM_TIMDELAYEDPROTECTION_DISABLED ((uint32_t)0x00000000) /*!< No action */ -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 (HRTIM_OUTR_DLYPRTEN) /*!< Output 1 delayed Idle on external Event 6 or 8 */ -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Output 2 delayed Idle on external Event 6 or 8 */ -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Output 1 and output 2 delayed Idle on external Event 6 or 8 */ -#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Balanced Idle on external Event 6 or 8 */ -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Output 1 delayed Idle on external Event 7 or 9 */ -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Output 2 delayed Idle on external Event 7 or 9 */ -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Output 1 and output2 delayed Idle on external Event 7 or 9 */ -#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Balanced Idle on external Event 7 or 9 */ - -#define IS_HRTIM_TIMDELAYEDPROTECTION(TIMDELAYEDPROTECTION)\ - (((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DISABLED) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79)) -/** - * @} - */ - -/** @defgroup HRTIM_TimerUpdateTrigger - * @{ - * @brief Constants defining whether the registers update is done synchronously - * with any other timer or master update - */ -#define HRTIM_TIMUPDATETRIGGER_NONE (uint32_t)0x00000000 /*!< Register update is disabled */ -#define HRTIM_TIMUPDATETRIGGER_MASTER (HRTIM_TIMCR_MSTU) /*!< Register update is triggered by the master timer update */ -#define HRTIM_TIMUPDATETRIGGER_TIMER_A (HRTIM_TIMCR_TAU) /*!< Register update is triggered by the timer A update */ -#define HRTIM_TIMUPDATETRIGGER_TIMER_B (HRTIM_TIMCR_TBU) /*!< Register update is triggered by the timer B update */ -#define HRTIM_TIMUPDATETRIGGER_TIMER_C (HRTIM_TIMCR_TCU) /*!< Register update is triggered by the timer C update*/ -#define HRTIM_TIMUPDATETRIGGER_TIMER_D (HRTIM_TIMCR_TDU) /*!< Register update is triggered by the timer D update */ -#define HRTIM_TIMUPDATETRIGGER_TIMER_E (HRTIM_TIMCR_TEU) /*!< Register update is triggered by the timer E update */ - -#define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFF) == 0x00000000) -/** - * @} - */ - -/** @defgroup HRTIM_TimerResetTrigger - * @{ - * @brief Constants defining the events that can be selected to trigger the reset - * of the timer counter - */ -#define HRTIM_TIMRESETTRIGGER_NONE (uint32_t)0x00000000 /*!< No counter reset trigger */ -#define HRTIM_TIMRESETTRIGGER_UPDATE (HRTIM_RSTR_UPDATE) /*!< The timer counter is reset upon update event */ -#define HRTIM_TIMRESETTRIGGER_CMP2 (HRTIM_RSTR_CMP2) /*!< The timer counter is reset upon Timer Compare 2 event */ -#define HRTIM_TIMRESETTRIGGER_CMP4 (HRTIM_RSTR_CMP4) /*!< The timer counter is reset upon Timer Compare 4 event */ -#define HRTIM_TIMRESETTRIGGER_MASTER_PER (HRTIM_RSTR_MSTPER) /*!< The timer counter is reset upon master timer period event */ -#define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1) /*!< The timer counter is reset upon master timer Compare 1 event */ -#define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2) /*!< The timer counter is reset upon master timer Compare 2 event */ -#define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3) /*!< The timer counter is reset upon master timer Compare 3 event */ -#define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4) /*!< The timer counter is reset upon master timer Compare 4 event */ -#define HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1) /*!< The timer counter is reset upon external event 1 */ -#define HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2) /*!< The timer counter is reset upon external event 2 */ -#define HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3) /*!< The timer counter is reset upon external event 3 */ -#define HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4) /*!< The timer counter is reset upon external event 4 */ -#define HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5) /*!< The timer counter is reset upon external event 5 */ -#define HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6) /*!< The timer counter is reset upon external event 6 */ -#define HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7) /*!< The timer counter is reset upon external event 7 */ -#define HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8) /*!< The timer counter is reset upon external event 8 */ -#define HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9) /*!< The timer counter is reset upon external event 9 */ -#define HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10) /*!< The timer counter is reset upon external event 10 */ -#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */ -#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */ -#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */ -#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */ -#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */ -#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */ -#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */ -#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */ -#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */ -#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1) /*!< The timer counter is reset upon other timer Compare 1 event */ -#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2) /*!< The timer counter is reset upon other timer Compare 2 event */ -#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4) /*!< The timer counter is reset upon other timer Compare 4 event */ - -#define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x800000001) == 0x00000000) - -/** - * @} - */ - -/** @defgroup HRTIM_TimerResetUpdate - * @{ - * @brief Constants defining whether the register are updated upon Timerx - * counter reset or rollover to 0 after reaching the period value - * in continuous mode - */ -#define HRTIM_TIMUPDATEONRESET_DISABLED (uint32_t)0x00000000 /*!< Update by timer x reset / rollover disabled */ -#define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU) /*!< Update by timer x reset / rollover enabled */ - -#define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \ - (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \ - ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED)) -/** - * @} - */ - -/** @defgroup HRTIM_CompareUnitAutoDelayedMode - * @{ - * @brief Constants defining whether the compare register is behaving in - * regular mode (compare match issued as soon as counter equal compare), - * or in auto-delayed mode - */ -#define HRTIM_AUTODELAYEDMODE_REGULAR ((uint32_t)0x00000000) /*!< standard compare mode */ -#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occured */ -#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */ -#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */ - -#define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\ - (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)) - -/* Auto delayed mode is only available for compare units 2 and 4 */ -#define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \ - ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) && \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)) \ - || \ - (((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \ - (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \ - || \ - (((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) && \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)) \ - || \ - (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \ - (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)))) -/** - * @} - */ - -/** @defgroup HRTIM_BasicOCMode - * @{ - * @brief Constants defining the behavior of the output signal when the timer - operates in basic output compare mode - */ -#define HRTIM_BASICOCMODE_TOGGLE ((uint32_t)0x00000001) /*!< Output toggles when the timer counter reaches the compare value */ -#define HRTIM_BASICOCMODE_INACTIVE ((uint32_t)0x00000002) /*!< Output forced to active level when the timer counter reaches the compare value */ -#define HRTIM_BASICOCMODE_ACTIVE ((uint32_t)0x00000003) /*!< Output forced to inactive level when the timer counter reaches the compare value */ - -#define IS_HRTIM_BASICOCMODE(BASICOCMODE)\ - (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \ - ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \ - ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE)) -/** - * @} - */ - -/** @defgroup HRTIM_OutputPolarity - * @{ - * @brief Constants defining the polarity of a timer output - */ -#define HRTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000) /*!< Output is active HIGH */ -#define HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1) /*!< Output is active LOW */ - -#define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\ - (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \ - ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW)) -/** - * @} - */ - -/** @defgroup HRTIM_OutputSetSource - * @{ - * @brief Constants defining the events that can be selected to configure the - * set crossbar of a timer output - */ -#define HRTIM_OUTPUTSET_NONE (uint32_t)0x00000000 /*!< Reset the output set crossbar */ -#define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces the output to its active state */ -#define HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces the output to its active state */ -#define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its active state */ -#define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its active state */ -#define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its active state */ -#define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ -#define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces the output to its active state */ -#define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces the output to its active state */ -#define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces the output to its active state */ -#define HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces the output to its active state */ -#define HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces the output to its active state */ -#define HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces the output to its active state */ -#define HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces the output to its active state */ -#define HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces the output to its active state */ -#define HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces the output to its active state */ -#define HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces the output to its active state */ -#define HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces the output to its active state */ - -#define IS_HRTIM_OUTPUTSET(OUTPUTSET)\ - (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE)) -/** - * @} - */ - -/** @defgroup HRTIM_OutputResetSource - * @{ - * @brief Constants defining the events that can be selected to configure the - * set crossbar of a timer output - */ -#define HRTIM_OUTPUTRESET_NONE (uint32_t)0x00000000 /*!< Reset the output reset crossbar */ -#define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */ - -#define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\ - (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE)) -/** - * @} - */ - -/** @defgroup HRTIM_OutputIdleMode - * @{ - * @brief Constants defining whether or not the timer output transition to its - IDLE state when burst mode is entered - */ -#define HRTIM_OUTPUTIDLEMODE_NONE (uint32_t)0x00000000 /*!< The output is not affected by the burst mode operation */ -#define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */ - -#define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\ - (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \ - ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE)) - /** - * @} - */ - -/** @defgroup HRTIM_OutputIDLEState - * @{ - * @brief Constants defining the IDLE state of a timer output - */ -#define HRTIM_OUTPUTIDLESTATE_INACTIVE (uint32_t)0x00000000 /*!< Output at inactive level when in IDLE state */ -#define HRTIM_OUTPUTIDLESTATE_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */ - -#define IS_HRTIM_OUTPUTIDLESTATE(OUTPUTIDLESTATE)\ - (((OUTPUTIDLESTATE) == HRTIM_OUTPUTIDLESTATE_INACTIVE) || \ - ((OUTPUTIDLESTATE) == HRTIM_OUTPUTIDLESTATE_ACTIVE)) -/** - * @} - */ - -/** @defgroup HRTIM_OutputFAULTState - * @{ - * @brief Constants defining the FAULT state of a timer output - */ -#define HRTIM_OUTPUTFAULTSTATE_NONE (uint32_t)0x00000000 /*!< The output is not affected by the fault input */ -#define HRTIM_OUTPUTFAULTSTATE_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */ -#define HRTIM_OUTPUTFAULTSTATE_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */ -#define HRTIM_OUTPUTFAULTSTATE_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */ - -#define IS_HRTIM_OUTPUTFAULTSTATE(OUTPUTFAULTSTATE)\ - (((OUTPUTFAULTSTATE) == HRTIM_OUTPUTFAULTSTATE_NONE) || \ - ((OUTPUTFAULTSTATE) == HRTIM_OUTPUTFAULTSTATE_ACTIVE) || \ - ((OUTPUTFAULTSTATE) == HRTIM_OUTPUTFAULTSTATE_INACTIVE) || \ - ((OUTPUTFAULTSTATE) == HRTIM_OUTPUTFAULTSTATE_HIGHZ)) -/** - * @} - */ - -/** @defgroup HRTIM_OutputChopperModeEnable - * @{ - * @brief Constants defining whether or not chopper mode is enabled for a timer - output - */ -#define HRTIM_OUTPUTCHOPPERMODE_DISABLED (uint32_t)0x00000000 /*!< The output is not affected by the fault input */ -#define HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output at active level when in FAULT state */ - -#define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\ - (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \ - ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED)) -/** - * @} - */ - -/** @defgroup HRTIM_OutputBurstModeEntryDelayed - * @{ - * @brief Constants defining the idle mode entry is delayed by forcing a - deadtime insertion before switching the outputs to their idle state - */ -#define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR (uint32_t)0x00000000 /*!< The programmed Idle state is applied immediately to the Output */ -#define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1) /*!< Deadtime is inserted on output before entering the idle mode */ - -#define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\ - (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \ - ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED)) -/** - * @} - */ - -/** @defgroup HRTIM_CaptureUnitTrigger - * @{ - * @brief Constants defining the events that can be selected to trigger the - * capture of the timing unit counter - */ -#define HRTIM_CAPTURETRIGGER_NONE (uint32_t)0x00000000 /*!< Capture trigger is disabled */ -#define HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT) /*!< The update event triggers the Capture */ -#define HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT) /*!< The External event 1 triggers the Capture */ -#define HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT) /*!< The External event 2 triggers the Capture */ -#define HRTIM_CAPTURETRIGGER_EEV_3 (HRTIM_CPT1CR_EXEV3CPT) /*!< The External event 3 triggers the Capture */ -#define HRTIM_CAPTURETRIGGER_EEV_4 (HRTIM_CPT1CR_EXEV4CPT) /*!< The External event 4 triggers the Capture */ -#define HRTIM_CAPTURETRIGGER_EEV_5 (HRTIM_CPT1CR_EXEV5CPT) /*!< The External event 5 triggers the Capture */ -#define HRTIM_CAPTURETRIGGER_EEV_6 (HRTIM_CPT1CR_EXEV6CPT) /*!< The External event 6 triggers the Capture */ -#define HRTIM_CAPTURETRIGGER_EEV_7 (HRTIM_CPT1CR_EXEV7CPT) /*!< The External event 7 triggers the Capture */ -#define HRTIM_CAPTURETRIGGER_EEV_8 (HRTIM_CPT1CR_EXEV8CPT) /*!< The External event 8 triggers the Capture */ -#define HRTIM_CAPTURETRIGGER_EEV_9 (HRTIM_CPT1CR_EXEV9CPT) /*!< The External event 9 triggers the Capture */ -#define HRTIM_CAPTURETRIGGER_EEV_10 (HRTIM_CPT1CR_EXEV10CPT) /*!< The External event 10 triggers the Capture */ -#define HRTIM_CAPTURETRIGGER_TA1_SET (HRTIM_CPT1CR_TA1SET) /*!< Capture is triggered by TA1 output inactive to active transition */ -#define HRTIM_CAPTURETRIGGER_TA1_RESET (HRTIM_CPT1CR_TA1RST) /*!< Capture is triggered by TA1 output active to inactive transition */ -#define HRTIM_CAPTURETRIGGER_TIMERA_CMP1 (HRTIM_CPT1CR_TA1CMP1) /*!< Timer A Compare 1 triggers Capture */ -#define HRTIM_CAPTURETRIGGER_TIMERA_CMP2 (HRTIM_CPT1CR_TA1CMP2) /*!< Timer A Compare 2 triggers Capture */ -#define HRTIM_CAPTURETRIGGER_TB1_SET (HRTIM_CPT1CR_TB1SET) /*!< Capture is triggered by TB1 output inactive to active transition */ -#define HRTIM_CAPTURETRIGGER_TB1_RESET (HRTIM_CPT1CR_TB1RST) /*!< Capture is triggered by TB1 output active to inactive transition */ -#define HRTIM_CAPTURETRIGGER_TIMERB_CMP1 (HRTIM_CPT1CR_TB1CMP1) /*!< Timer B Compare 1 triggers Capture */ -#define HRTIM_CAPTURETRIGGER_TIMERB_CMP2 (HRTIM_CPT1CR_TB1CMP2) /*!< Timer B Compare 2 triggers Capture */ -#define HRTIM_CAPTURETRIGGER_TC1_SET (HRTIM_CPT1CR_TC1SET) /*!< Capture is triggered by TC1 output inactive to active transition */ -#define HRTIM_CAPTURETRIGGER_TC1_RESET (HRTIM_CPT1CR_TC1RST) /*!< Capture is triggered by TC1 output active to inactive transition */ -#define HRTIM_CAPTURETRIGGER_TIMERC_CMP1 (HRTIM_CPT1CR_TC1CMP1) /*!< Timer C Compare 1 triggers Capture */ -#define HRTIM_CAPTURETRIGGER_TIMERC_CMP2 (HRTIM_CPT1CR_TC1CMP2) /*!< Timer C Compare 2 triggers Capture */ -#define HRTIM_CAPTURETRIGGER_TD1_SET (HRTIM_CPT1CR_TD1SET) /*!< Capture is triggered by TD1 output inactive to active transition */ -#define HRTIM_CAPTURETRIGGER_TD1_RESET (HRTIM_CPT1CR_TD1RST) /*!< Capture is triggered by TD1 output active to inactive transition */ -#define HRTIM_CAPTURETRIGGER_TIMERD_CMP1 (HRTIM_CPT1CR_TD1CMP1) /*!< Timer D Compare 1 triggers Capture */ -#define HRTIM_CAPTURETRIGGER_TIMERD_CMP2 (HRTIM_CPT1CR_TD1CMP2) /*!< Timer D Compare 2 triggers Capture */ -#define HRTIM_CAPTURETRIGGER_TE1_SET (HRTIM_CPT1CR_TE1SET) /*!< Capture is triggered by TE1 output inactive to active transition */ -#define HRTIM_CAPTURETRIGGER_TE1_RESET (HRTIM_CPT1CR_TE1RST) /*!< Capture is triggered by TE1 output active to inactive transition */ -#define HRTIM_CAPTURETRIGGER_TIMERE_CMP1 (HRTIM_CPT1CR_TE1CMP1) /*!< Timer E Compare 1 triggers Capture */ -#define HRTIM_CAPTURETRIGGER_TIMERE_CMP2 (HRTIM_CPT1CR_TE1CMP2) /*!< Timer E Compare 2 triggers Capture */ - -#define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))) -/** - * @} - */ - -/** @defgroup HRTIM_TimerExternalEventFilter - * @{ - * @brief Constants defining the event filtering applied to external events - * by a timer - */ -#define HRTIM_TIMEVENTFILTER_NONE (0x00000000) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1 */ -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2 */ -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3 */ -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4 */ -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */ -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */ -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */ -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */ -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */ -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */ -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */ -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */ -#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2 */ -#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3 */ -#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */ - -#define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\ - (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM)) -/** - * @} - */ - -/** @defgroup HRTIM_TimerExternalEventLatch - * @{ - * @brief Constants defining whether or not the external event is - * memorized (latched) and generated as soon as the blanking period - * is completed or the window ends - */ -#define HRTIM_TIMEVENTLATCH_DISABLED ((uint32_t)0x00000000) /*!< Event is ignored if it happens during a blank, or passed through during a window */ -#define HRTIM_TIMEVENTLATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event 1 is latched and delayed till the end of the blanking or windowing period */ /*!< Blanking from counter reset/roll-over to Compare 1 */ - -#define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\ - (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \ - ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED)) -/** - * @} - */ - -/** @defgroup HRTIM_DeadtimeRisingSign - * @{ - * @brief Constants defining whether the deadtime is positive or negative - * (overlapping signal) on rising edge - */ -#define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE ((uint32_t)0x00000000) /*!< Positive deadtime on rising edge */ -#define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative deadtime on rising edge */ - -#define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\ - (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \ - ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE)) -/** - * @} - */ - -/** @defgroup HRTIM_DeadtimeRisingLock - * @{ - * @brief Constants defining whether or not the deadtime (rising sign and - * value) is write protected - */ -#define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime rising value and sign is writable */ -#define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK) /*!< Deadtime rising value and sign is read-only */ - -#define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\ - (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \ - ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY)) -/** - * @} - */ - -/** @defgroup HRTIM_DeadtimeRisingSignLock - * @{ - * @brief Constants defining whether or not the deadtime rising sign is write - * protected - */ -#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime rising sign is writable */ -#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK) /*!< Deadtime rising sign is read-only */ - -#define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\ - (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \ - ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY)) -/** - * @} - */ - -/** @defgroup HRTIM_DeadtimeFallingSign - * @{ - * @brief Constants defining whether the deadtime is positive or negative - * (overlapping signal) on falling edge - */ -#define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE ((uint32_t)0x00000000) /*!< Positive deadtime on falling edge */ -#define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative deadtime on falling edge */ - -#define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\ - (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \ - ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE)) -/** - * @} - */ - -/** @defgroup HRTIM_DeadtimeFallingLock - * @{ - * @brief Constants defining whether or not the deadtime (falling sign and - * value) is write protected - */ -#define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime falling value and sign is writable */ -#define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK) /*!< Deadtime falling value and sign is read-only */ - -#define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\ - (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \ - ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY)) -/** - * @} - */ - -/** @defgroup HRTIM_DeadtimeFallingSignLock - * @{ - * @brief Constants defining whether or not the deadtime falling sign is write - * protected - */ -#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime falling sign is writable */ -#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK) /*!< Deadtime falling sign is read-only */ - -#define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\ - (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \ - ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY)) -/** - * @} - */ - -/** @defgroup HRTIM_SynchronizationInputSource - * @{ - * @brief Constants defining defining the synchronization input source - */ -#define HRTIM_SYNCINPUTSOURCE_NONE (uint32_t)0x00000000 /*!< disabled. HRTIM is not synchronized and runs in standalone mode */ -#define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1 /*!< The HRTIM is synchronized with the on-chip timer */ -#define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */ - -#define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\ - (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \ - ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \ - ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT)) -/** - * @} - */ - -/** @defgroup HRTIM_SynchronizationOutputSource - * @{ - * @brief Constants defining the source and event to be sent on the - * synchronization outputs - */ -#define HRTIM_SYNCOUTPUTSOURCE_MASTER_START (uint32_t)0x00000000 /*!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon master timer start event */ -#define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon master timer compare 1 event*/ -#define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon timer A start or reset events */ -#define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon timer A compare 1 event */ - -#define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\ - (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \ - ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \ - ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \ - ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1)) -/** - * @} - */ - -/** @defgroup HRTIM_SynchronizationOutputPolarity - * @{ - * @brief Constants defining the routing and conditioning of the synchronization output event - */ -#define HRTIM_SYNCOUTPUTPOLARITY_NONE (uint32_t)0x00000000 /*!< Synchronization output event is disabled */ -#define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_0) /*!< Positive pulse on SCOUT output (16x fHRTIM clock cycles) */ -#define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< Positive pulse on SCOUT output (16x fHRTIM clock cycles) */ - -#define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\ - (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \ - ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \ - ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE)) -/** - * @} - */ - -/** @defgroup HRTIM_ExternalEventSources - * @{ - * @brief Constants defining available sources associated to external events - */ -#define HRTIM_EVENTSRC_1 ((uint32_t)0x00000000) /*!< External event source 1 */ -#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 */ -#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 */ -#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 */ - -#define IS_HRTIM_EVENTSRC(EVENTSRC)\ - (((EVENTSRC) == HRTIM_EVENTSRC_1) || \ - ((EVENTSRC) == HRTIM_EVENTSRC_2) || \ - ((EVENTSRC) == HRTIM_EVENTSRC_3) || \ - ((EVENTSRC) == HRTIM_EVENTSRC_4)) -/** - * @} - */ - -/** @defgroup HRTIM_ExternalEventPolarity - * @{ - * @brief Constants defining the polarity of an external event - */ -#define HRTIM_EVENTPOLARITY_HIGH ((uint32_t)0x00000000) /*!< External event is active high */ -#define HRTIM_EVENTPOLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */ - -#define IS_HRTIM_EVENTPOLARITY(EVENTPOLARITY)\ - (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \ - ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW)) -/** - * @} - */ - -/** @defgroup HRTIM_ExternalEventSensitivity - * @{ - * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive) - * of an external event - */ -#define HRTIM_EVENTSENSITIVITY_LEVEL ((uint32_t)0x00000000) /*!< External event is active on level */ -#define HRTIM_EVENTSENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */ -#define HRTIM_EVENTSENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */ -#define HRTIM_EVENTSENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */ - -#define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\ - (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)) -/** - * @} - */ - -/** @defgroup HRTIM_ExternalEventFastMode - * @{ - * @brief Constants defining whether or not an external event is programmed in - fast mode - */ -#define HRTIM_EVENTFASTMODE_DISABLE ((uint32_t)0x00000000) /*!< External Event is acting asynchronously on outputs (low latency mode) */ -#define HRTIM_EVENTFASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */ - -#define IS_HRTIM_EVENTFASTMODE(EVENTFASTMODE)\ - (((EVENTFASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \ - ((EVENTFASTMODE) == HRTIM_EVENTFASTMODE_DISABLE)) - -#define IS_HRTIM_FASTMODE_AVAILABLE(EVENT)\ - (((EVENT) == HRTIM_EVENT_1) || \ - ((EVENT) == HRTIM_EVENT_2) || \ - ((EVENT) == HRTIM_EVENT_3) || \ - ((EVENT) == HRTIM_EVENT_4) || \ - ((EVENT) == HRTIM_EVENT_5)) -/** - * @} - */ - -/** @defgroup HRTIM_ExternalEventFilter - * @{ - * @brief Constants defining the frequency used to sample an external event 6 - * input and the length (N) of the digital filter applied - */ -#define HRTIM_EVENTFILTER_NONE ((uint32_t)0x00000000) /*!< Filter disabled */ -#define HRTIM_EVENTFILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=2 */ -#define HRTIM_EVENTFILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fHRTIM, N=4 */ -#define HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=8 */ -#define HRTIM_EVENTFILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/2, N=6 */ -#define HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/2, N=8 */ -#define HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/4, N=6 */ -#define HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/4, N=8 */ -#define HRTIM_EVENTFILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING= fEEVS/8, N=6 */ -#define HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/8, N=8 */ -#define HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/16, N=5 */ -#define HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/16, N=6 */ -#define HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/16, N=8 */ -#define HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32, N=5 */ -#define HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/32, N=6 */ -#define HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32, N=8 */ - -#define IS_HRTIM_EVENTFILTER(EVENTFILTER)\ - (((EVENTFILTER) == HRTIM_EVENTFILTER_NONE) || \ - ((EVENTFILTER) == HRTIM_EVENTFILTER_1) || \ - ((EVENTFILTER) == HRTIM_EVENTFILTER_2) || \ - ((EVENTFILTER) == HRTIM_EVENTFILTER_3) || \ - ((EVENTFILTER) == HRTIM_EVENTFILTER_4) || \ - ((EVENTFILTER) == HRTIM_EVENTFILTER_5) || \ - ((EVENTFILTER) == HRTIM_EVENTFILTER_6) || \ - ((EVENTFILTER) == HRTIM_EVENTFILTER_7) || \ - ((EVENTFILTER) == HRTIM_EVENTFILTER_8) || \ - ((EVENTFILTER) == HRTIM_EVENTFILTER_9) || \ - ((EVENTFILTER) == HRTIM_EVENTFILTER_10) || \ - ((EVENTFILTER) == HRTIM_EVENTFILTER_11) || \ - ((EVENTFILTER) == HRTIM_EVENTFILTER_12) || \ - ((EVENTFILTER) == HRTIM_EVENTFILTER_13) || \ - ((EVENTFILTER) == HRTIM_EVENTFILTER_14) || \ - ((EVENTFILTER) == HRTIM_EVENTFILTER_15)) -/** - * @} - */ - -/** @defgroup HRTIM_ ExternalEventPrescaler - * @{ - * @brief Constants defining division ratio between the timer clock frequency - * fHRTIM) and the external event signal sampling clock (fEEVS) - * used by the digital filters - */ -#define HRTIM_EVENTPRESCALER_DIV1 ((uint32_t)0x00000000) /*!< fEEVS=fHRTIM */ -#define HRTIM_EVENTPRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 2 */ -#define HRTIM_EVENTPRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS=fHRTIM / 4 */ -#define HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 8 */ - -#define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\ - (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \ - ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \ - ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \ - ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8)) -/** - * @} - */ - -/** @defgroup HRTIM_FaultSources - * @{ - * @brief Constants defining whether a faults is be triggered by any external - * or internal fault source - */ -#define HRTIM_FAULTSOURCE_DIGITALINPUT ((uint32_t)0x00000000) /*!< Fault input is FLT input pin */ -#define HRTIM_FAULTSOURCE_INTERNAL (HRTIM_FLTINR1_FLT1SRC) /*!< Fault input is FLT_Int signal (e.g. internal comparator) */ - - -#define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\ - (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \ - ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL)) -/** - * @} - */ - -/** @defgroup HRTIM_FaultPolarity - * @{ - * @brief Constants defining the polarity of a fault event - */ -#define HRTIM_FAULTPOLARITY_LOW ((uint32_t)0x00000000) /*!< Fault input is active low */ -#define HRTIM_FAULTPOLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */ - -#define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\ - (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \ - ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH)) -/** - * @} - */ - -/** @defgroup HRTIM_FaultFilter - * @{ - * @ brief Constants defining the frequency used to sample the fault input and - * the length (N) of the digital filter applied - */ -#define HRTIM_FAULTFILTER_NONE ((uint32_t)0x00000000) /*!< Filter disabled */ -#define HRTIM_FAULTFILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2 */ -#define HRTIM_FAULTFILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4 */ -#define HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8 */ -#define HRTIM_FAULTFILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2, N=6 */ -#define HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2, N=8 */ -#define HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4, N=6 */ -#define HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4, N=8 */ -#define HRTIM_FAULTFILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8, N=6 */ -#define HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8, N=8 */ -#define HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16, N=5 */ -#define HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16, N=6 */ -#define HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16, N=8 */ -#define HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=5 */ -#define HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32, N=6 */ -#define HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=8 */ - -#define IS_HRTIM_FAULTFILTER(FAULTFILTER)\ - (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_15)) -/** - * @} - */ - -/** @defgroup HRTIM_FaultLock - * @{ - * @brief Constants defining whether or not the fault programming bits are - write protected - */ -#define HRTIM_FAULTLOCK_READWRITE ((uint32_t)0x00000000) /*!< Fault settings bits are read/write */ -#define HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK) /*!< Fault settings bits are read only */ - -#define IS_HRTIM_FAULTLOCK(FAULTLOCK)\ - (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \ - ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY)) -/** - * @} - */ - -/** @defgroup HRTIM_ExternalFaultPrescaler - * @{ - * @brief Constants defining the division ratio between the timer clock - * frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used - * by the digital filters. - */ -#define HRTIM_FAULTPRESCALER_DIV1 ((uint32_t)0x00000000) /*!< fFLTS=fHRTIM */ -#define HRTIM_FAULTPRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 2 */ -#define HRTIM_FAULTPRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS=fHRTIM / 4 */ -#define HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 8 */ - -#define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\ - (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \ - ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \ - ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \ - ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8)) -/** - * @} - */ - -/** @defgroup HRTIM_BurstModeOperatingmode - * @{ - * @brief Constants defining if the burst mode is entered once or if it is - * continuously operating - */ -#define HRTIM_BURSTMODE_SINGLESHOT ((uint32_t)0x00000000) /*!< Burst mode operates in single shot mode */ -#define HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */ - -#define IS_HRTIM_BURSTMODE(BURSTMODE)\ - (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \ - ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS)) -/** - * @} - */ - -/** @defgroup HRTIM_BurstModeClockSource - * @{ - * @brief Constants defining the clock source for the burst mode counter - */ -#define HRTIM_BURSTMODECLOCKSOURCE_MASTER ((uint32_t)0x00000000) /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */ -#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */ -#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */ -#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */ -#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */ -#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */ -#define HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_1 (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */ -#define HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_2 (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */ -#define HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_3 (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */ -#define HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_4 (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 4 (BMClk[4]), acting as a burst mode counter clock */ -#define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */ - -#define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\ - (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_1) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_2) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_3) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_4) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM)) -/** - * @} - */ - -/** @defgroup HRTIM_BurstModePrescaler - * @{ - * @brief Constants defining the prescaling ratio of the fHRTIM clock - * for the burst mode controller - */ -#define HRTIM_BURSTMODEPRESCALER_DIV1 ((uint32_t)0x00000000) /*!< fBRST = fHRTIM */ -#define HRTIM_BURSTMODEPRESCALER_DIV2 (HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/2 */ -#define HRTIM_BURSTMODEPRESCALER_DIV4 (HRTIM_BMCR_BMPSC_1) /*!< fBRST = fHRTIM/4 */ -#define HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPSC_1 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/8 */ -#define HRTIM_BURSTMODEPRESCALER_DIV16 (HRTIM_BMCR_BMPSC_2) /*!< fBRST = fHRTIM/16 */ -#define HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/32 */ -#define HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_1) /*!< fBRST = fHRTIM/64 */ -#define HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_1 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/128 */ -#define HRTIM_BURSTMODEPRESCALER_DIV256 (HRTIM_BMCR_BMPSC_3) /*!< fBRST = fHRTIM/256 */ -#define HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/512 */ -#define HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_1) /*!< fBRST = fHRTIM/1024 */ -#define HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_1 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/2048*/ -#define HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_2) /*!< fBRST = fHRTIM/4096 */ -#define HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/8192 */ -#define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_1) /*!< fBRST = fHRTIM/16384 */ -#define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_1 | HRTIM_BMCR_BMPSC_0) /*!< fBRST = fHRTIM/32768 */ - -#define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\ - (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768)) -/** - * @} - */ - -/** @defgroup HRTIM_BurstModeRegisterPreloadEnable - * @{ - * @brief Constants defining whether or not burst mode registers preload - mechanism is enabled, i.e. a write access into a preloadable register - (HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register - */ -#define HRIM_BURSTMODEPRELOAD_DISABLED ((uint32_t)0x00000000) /*!< Preload disabled: the write access is directly done into active registers */ -#define HRIM_BURSTMODEPRELOAD_ENABLED (HRTIM_BMCR_BMPREN) /*!< Preload enabled: the write access is done into preload registers */ - -#define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\ - (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \ - ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED)) -/** - * @} - */ - -/** @defgroup HRTIM_BurstModeTrigger - * @{ - * @brief Constants defining the events that can be used tor trig the burst - * mode operation - */ -#define HRTIM_BURSTMODETRIGGER_SOFTWARE (uint32_t)0x00000000 /*!< Software trigger */ -#define HRTIM_BURSTMODETRIGGER_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master reset */ -#define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master repetition */ -#define HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master compare 1 */ -#define HRTIM_BURSTMODETRIGGER_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master compare 2 */ -#define HRTIM_BURSTMODETRIGGER_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master compare 3 */ -#define HRTIM_BURSTMODETRIGGER_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master compare 4 */ -#define HRTIM_BURSTMODETRIGGER_TIMERA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset */ -#define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition */ -#define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 */ -#define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 */ -#define HRTIM_BURSTMODETRIGGER_TIMERB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset */ -#define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition */ -#define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 */ -#define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 */ -#define HRTIM_BURSTMODETRIGGER_TIMERC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C reset */ -#define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition */ -#define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 */ -#define HRTIM_BURSTMODETRIGGER_TIMERC_CMP2 (HRTIM_BMTRGR_TCCMP2) /*!< Timer C compare 2 */ -#define HRTIM_BURSTMODETRIGGER_TIMERD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset */ -#define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition */ -#define HRTIM_BURSTMODETRIGGER_TIMERD_CMP1 (HRTIM_BMTRGR_TDCMP1) /*!< Timer D compare 1 */ -#define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 */ -#define HRTIM_BURSTMODETRIGGER_TIMERE_RESET (HRTIM_BMTRGR_TERST) /*!< Timer E reset */ -#define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition */ -#define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 */ -#define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 */ -#define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following External Event 7 */ -#define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following External Event 8 */ -#define HRTIM_BURSTMODETRIGGER_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External Event 7 */ -#define HRTIM_BURSTMODETRIGGER_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External Event 8 */ -#define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< On-chip Event */ - -#define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\ - (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP)) -/** - * @} - */ - -/** @defgroup HRTIM_ADCTriggerUpdateSource - * @{ - * @brief constants defining the source triggering the update of the - HRTIM_ADCxR register (transfer from preload to active register). - */ -#define HRTIM_ADCTRIGGERUPDATE_MASTER (uint32_t)0x00000000 /*!< Master timer */ -#define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /*!< Timer A */ -#define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /*!< Timer B */ -#define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< Timer C */ -#define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /*!< Timer D */ -#define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< Timer E */ - -#define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\ - (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E)) -/** - * @} - */ - -/** @defgroup HRTIM_ADCTriggerEvent - * @{ - * @brief constants defining the events triggering ADC conversion. - * HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3 - * HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4 - */ -#define HRTIM_ADCTRIGGEREVENT13_NONE (uint32_t)0x00000000 /*!< No ADC trigger event */ -#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1) /*!< ADC Trigger on master compare 1 */ -#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2) /*!< ADC Trigger on master compare 2 */ -#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3) /*!< ADC Trigger on master compare 3 */ -#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4) /*!< ADC Trigger on master compare 4 */ -#define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD (HRTIM_ADC1R_AD1MPER) /*!< ADC Trigger on master period */ -#define HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1) /*!< ADC Trigger on external event 1 */ -#define HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2) /*!< ADC Trigger on external event 2 */ -#define HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3) /*!< ADC Trigger on external event 3 */ -#define HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4) /*!< ADC Trigger on external event 4 */ -#define HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5) /*!< ADC Trigger on external event 5 */ -#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2 (HRTIM_ADC1R_AD1TAC2) /*!< ADC Trigger on Timer A compare 2 */ -#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3) /*!< ADC Trigger on Timer A compare 3 */ -#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4) /*!< ADC Trigger on Timer A compare 4 */ -#define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD (HRTIM_ADC1R_AD1TAPER) /*!< ADC Trigger on Timer A period */ -#define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET (HRTIM_ADC1R_AD1TARST) /*!< ADC Trigger on Timer A reset */ -#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2 (HRTIM_ADC1R_AD1TBC2) /*!< ADC Trigger on Timer B compare 2 */ -#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3) /*!< ADC Trigger on Timer B compare 3 */ -#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4) /*!< ADC Trigger on Timer B compare 4 */ -#define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD (HRTIM_ADC1R_AD1TBPER) /*!< ADC Trigger on Timer B period */ -#define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET (HRTIM_ADC1R_AD1TBRST) /*!< ADC Trigger on Timer B reset */ -#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2 (HRTIM_ADC1R_AD1TCC2) /*!< ADC Trigger on Timer C compare 2 */ -#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3) /*!< ADC Trigger on Timer C compare 3 */ -#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4) /*!< ADC Trigger on Timer C compare 4 */ -#define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD (HRTIM_ADC1R_AD1TCPER) /*!< ADC Trigger on Timer C period */ -#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2 (HRTIM_ADC1R_AD1TDC2) /*!< ADC Trigger on Timer D compare 2 */ -#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3) /*!< ADC Trigger on Timer D compare 3 */ -#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4) /*!< ADC Trigger on Timer D compare 4 */ -#define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD (HRTIM_ADC1R_AD1TDPER) /*!< ADC Trigger on Timer D period */ -#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2 (HRTIM_ADC1R_AD1TEC2) /*!< ADC Trigger on Timer E compare 2 */ -#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3) /*!< ADC Trigger on Timer E compare 3 */ -#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4) /*!< ADC Trigger on Timer E compare 4 */ -#define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD (HRTIM_ADC1R_AD1TEPER) /*!< ADC Trigger on Timer E period */ - -#define HRTIM_ADCTRIGGEREVENT24_NONE (uint32_t)0x00000000 /*!< No ADC trigger event */ -#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1) /*!< ADC Trigger on master compare 1 */ -#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2) /*!< ADC Trigger on master compare 2 */ -#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3) /*!< ADC Trigger on master compare 3 */ -#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4) /*!< ADC Trigger on master compare 4 */ -#define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD (HRTIM_ADC2R_AD2MPER) /*!< ADC Trigger on master period */ -#define HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6) /*!< ADC Trigger on external event 6 */ -#define HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7) /*!< ADC Trigger on external event 7 */ -#define HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8) /*!< ADC Trigger on external event 8 */ -#define HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9) /*!< ADC Trigger on external event 9 */ -#define HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10) /*!< ADC Trigger on external event 10 */ -#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2) /*!< ADC Trigger on Timer A compare 2 */ -#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3 (HRTIM_ADC2R_AD2TAC3) /*!< ADC Trigger on Timer A compare 3 */ -#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4) /*!< ADC Trigger on Timer A compare 4 */ -#define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD (HRTIM_ADC2R_AD2TAPER) /*!< ADC Trigger on Timer A period */ -#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2) /*!< ADC Trigger on Timer B compare 2 */ -#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3 (HRTIM_ADC2R_AD2TBC3) /*!< ADC Trigger on Timer B compare 3 */ -#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4) /*!< ADC Trigger on Timer B compare 4 */ -#define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD (HRTIM_ADC2R_AD2TBPER) /*!< ADC Trigger on Timer B period */ -#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2) /*!< ADC Trigger on Timer C compare 2 */ -#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3 (HRTIM_ADC2R_AD2TCC3) /*!< ADC Trigger on Timer C compare 3 */ -#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4) /*!< ADC Trigger on Timer C compare 4 */ -#define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD (HRTIM_ADC2R_AD2TCPER) /*!< ADC Trigger on Timer C period */ -#define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET (HRTIM_ADC2R_AD2TCRST) /*!< ADC Trigger on Timer C reset */ -#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2) /*!< ADC Trigger on Timer D compare 2 */ -#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3 (HRTIM_ADC2R_AD2TDC3) /*!< ADC Trigger on Timer D compare 3 */ -#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4) /*!< ADC Trigger on Timer D compare 4 */ -#define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD (HRTIM_ADC2R_AD2TDPER) /*!< ADC Trigger on Timer D period */ -#define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET (HRTIM_ADC2R_AD2TDRST) /*!< ADC Trigger on Timer D reset */ -#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2) /*!< ADC Trigger on Timer E compare 2 */ -#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3) /*!< ADC Trigger on Timer E compare 3 */ -#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4) /*!< ADC Trigger on Timer E compare 4 */ -#define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST) /*!< ADC Trigger on Timer E reset */ - -/** - * @} - */ - -/** @defgroup HRTIM_DLLCalibrationRate - * @{ - * @brief Constants defining the DLL calibration periods (in micro seconds) - */ - -#define HRTIM_CALIBRATIONRATE_7300 (uint32_t)0x00000000 /*!< 1048576 * tHRTIM (7.3 ms) */ -#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) /*!< 131072 * tHRTIM (910 µs) */ -#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) /*!< 131072 * tHRTIM (910 µs) */ -#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) /*!< 131072 * tHRTIM (910 µs) */ - -#define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\ - (((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14)) -/** - * @} - */ - -/** @defgroup HRTIM_BurstDMARegistersUpdate - * @{ - * @brief Constants defining the registers that can be written during a burst - * DMA operation - */ -#define HRTIM_BURSTDMA_NONE (uint32_t)0x00000000 /*!< No register is updated by Burst DMA accesses */ -#define HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR) /*!< MCR or TIMxCR register is updated by Burst DMA accesses */ -#define HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR) /*!< MICR or TIMxICR register is updated by Burst DMA accesses */ -#define HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER) /*!< MDIER or TIMxDIER register is updated by Burst DMA accesses */ -#define HRTIM_BURSTDMA_CNT (HRTIM_BDTUPR_TIMCNT) /*!< MCNTR or CNTxCR register is updated by Burst DMA accesses */ -#define HRTIM_BURSTDMA_PER (HRTIM_BDTUPR_TIMPER) /*!< MPER or PERxR register is updated by Burst DMA accesses */ -#define HRTIM_BURSTDMA_REP (HRTIM_BDTUPR_TIMREP) /*!< MREPR or REPxR register is updated by Burst DMA accesses */ -#define HRTIM_BURSTDMA_CMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< MCMP1R or CMP1xR register is updated by Burst DMA accesses */ -#define HRTIM_BURSTDMA_CMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< MCMP2R or CMP2xR register is updated by Burst DMA accesses */ -#define HRTIM_BURSTDMA_CMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< MCMP3R or CMP3xR register is updated by Burst DMA accesses */ -#define HRTIM_BURSTDMA_CMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< MCMP4R or CMP4xR register is updated by Burst DMA accesses */ -#define HRTIM_BURSTDMA_DTR (HRTIM_BDTUPR_TIMDTR) /*!< TDxR register is updated by Burst DMA accesses */ -#define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */ -#define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */ -#define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */ -#define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */ -#define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */ -#define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */ -#define HRTIM_BURSTDMA_RSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */ -#define HRTIM_BURSTDMA_CHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */ -#define HRTIM_BURSTDMA_OUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */ -#define HRTIM_BURSTDMA_FLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */ - -#define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \ - ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFFC000) == 0x00000000)) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000) == 0x00000000))) -/** - * @} - */ - -/** @defgroup HRTIM_BursttModeControl - * @{ - * @brief Constants used to enable or disable the burst mode controller - */ -#define HRTIM_BURSTMODECTL_DISABLED (uint32_t)0x00000000 /*!< Burst mode disabled */ -#define HRTIM_BURSTMODECTL_ENABLED (HRTIM_BMCR_BME) /*!< Burst mode enabled */ - -#define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\ - (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \ - ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED)) -/** - * @} - */ - -/** @defgroup HRTIM_FaultModeControl - * @{ - * @brief Constants used to enable or disable the Fault mode - */ -#define HRTIM_FAULT_DISABLED (uint32_t)0x00000000 /*!< Fault mode disabled */ -#define HRTIM_FAULT_ENABLED (HRTIM_FLTINR1_FLT1E) /*!< Fault mode enabled */ - -#define IS_HRTIM_FAULTCTL(FAULTCTL)\ - (((FAULTCTL) == HRTIM_FAULT_DISABLED) || \ - ((FAULTCTL) == HRTIM_FAULT_ENABLED)) -/** - * @} - */ - -/** @defgroup HRTIM_SoftwareTimerUpdate - * @{ - * @brief Constants used to force timer registers update - */ -#define HRTIM_TIMERUPDATE_MASTER (HRTIM_CR2_MSWU) /*!< Forces an immediate transfer from the preload to the active register in the master timer */ -#define HRTIM_TIMERUPDATE_A (HRTIM_CR2_TASWU) /*!< Forces an immediate transfer from the preload to the active register in the timer A */ -#define HRTIM_TIMERUPDATE_B (HRTIM_CR2_TBSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer B */ -#define HRTIM_TIMERUPDATE_C (HRTIM_CR2_TCSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer C */ -#define HRTIM_TIMERUPDATE_D (HRTIM_CR2_TDSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer D */ -#define HRTIM_TIMERUPDATE_E (HRTIM_CR2_TESWU) /*!< Forces an immediate transfer from the preload to the active register in the timer E */ - -#define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0) == 0x00000000) -/** - * @} - */ - -/** @defgroup HRTIM_SoftwareTimerReset - * @{ - * @brief Constants used to force timer counter reset - */ -#define HRTIM_TIMERRESET_MASTER (HRTIM_CR2_MRST) /*!< Resets the master timer counter */ -#define HRTIM_TIMERRESET_A (HRTIM_CR2_TARST) /*!< Resets the timer A counter */ -#define HRTIM_TIMERRESET_B (HRTIM_CR2_TBRST) /*!< Resets the timer B counter */ -#define HRTIM_TIMERRESET_C (HRTIM_CR2_TCRST) /*!< Resets the timer C counter */ -#define HRTIM_TIMERRESET_D (HRTIM_CR2_TDRST) /*!< Resets the timer D counter */ -#define HRTIM_TIMERRESET_E (HRTIM_CR2_TERST) /*!< Resets the timer E counter */ - -#define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FF) == 0x00000000) -/** - * @} - */ - -/** @defgroup HRTIM_OutputLevel - * @{ - * @brief Constants defining the level of a timer output - */ -#define HRTIM_OUTPUTLEVEL_ACTIVE (uint32_t)0x00000001 /*!< Forces the output to its active state */ -#define HRTIM_OUTPUTLEVEL_INACTIVE (uint32_t)0x00000002 /*!< Forces the output to its inactive state */ - -#define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\ - (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \ - ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE)) -/** - * @} - */ - -/** @defgroup HRTIM_OutputState - * @{ - * @brief Constants defining the state of a timer output - */ -#define HRTIM_OUTPUTSTATE_IDLE (uint32_t)0x00000001 /*!< Main operating mode, where the output can take the active or - inactive level as programmed in the crossbar unit */ -#define HRTIM_OUTPUTSTATE_RUN (uint32_t)0x00000002 /*!< Default operating state (e.g. after an HRTIM reset, when the - outputs are disabled by software or during a burst mode operation */ -#define HRTIM_OUTPUTSTATE_FAULT (uint32_t)0x00000003 /*!< Safety state, entered in case of a shut-down request on - FAULTx inputs */ -/** - * @} - */ - -/** @defgroup HRTIM_BurstModeStatus - * @{ - * @brief Constants defining the operating state of the burst mode controller - */ -#define HRTIM_BURSTMODESTATUS_NORMAL (uint32_t) 0x00000000 /*!< Normal operation */ -#define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT) /*!< Burst operation on-going */ -/** - * @} - */ - -/** @defgroup HRTIM_CurrentPushPullStatus - * @{ - * @brief Constants defining on which output the signal is currently applied - * in push-pull mode - */ -#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 (uint32_t) 0x00000000 /*!< Signal applied on output 1 and output 2 forced inactive */ -#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */ -/** - * @} - */ - -/** @defgroup HRTIM_IdlePushPullStatus - * @{ - * @brief Constants defining on which output the signal was applied, in - * push-pull mode balanced fault mode or delayed idle mode, when the - * protection was triggered - */ -#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 (uint32_t) 0x00000000 /*!< Protection occurred when the output 1 was active and output 2 forced inactive */ -#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */ -/** - * @} - */ - -/** @defgroup HRTIM_CommonInterrupt - * @{ - */ -#define HRTIM_IT_FLT1 HRTIM_ISR_FLT1 /*!< Fault 1 interrupt flag */ -#define HRTIM_IT_FLT2 HRTIM_ISR_FLT2 /*!< Fault 2 interrupt flag */ -#define HRTIM_IT_FLT3 HRTIM_ISR_FLT3 /*!< Fault 3 interrupt flag */ -#define HRTIM_IT_FLT4 HRTIM_ISR_FLT4 /*!< Fault 4 interrupt flag */ -#define HRTIM_IT_FLT5 HRTIM_ISR_FLT5 /*!< Fault 5 interrupt flag */ -#define HRTIM_IT_SYSFLT HRTIM_ISR_SYSFLT /*!< System Fault interrupt flag */ -#define HRTIM_IT_DLLRDY HRTIM_ISR_DLLRDY /*!< DLL ready interrupt flag */ -#define HRTIM_IT_BMPER HRTIM_ISR_BMPER /*!< Burst mode period interrupt flag */ - -#define IS_HRTIM_IT(IT)\ - (((IT) == HRTIM_ISR_FLT1) || \ - ((IT) == HRTIM_ISR_FLT2) || \ - ((IT) == HRTIM_ISR_FLT3) || \ - ((IT) == HRTIM_ISR_FLT4) || \ - ((IT) == HRTIM_ISR_FLT5) || \ - ((IT) == HRTIM_ISR_SYSFLT) || \ - ((IT) == HRTIM_ISR_DLLRDY) || \ - ((IT) == HRTIM_ISR_BMPER)) -/** - * @} - */ - -/** @defgroup HRTIM_MasterInterrupt - * @{ - */ -#define HRTIM_MASTER_IT_MCMP1 HRTIM_MDIER_MCMP1IE /*!< Master compare 1 interrupt flag */ -#define HRTIM_MASTER_IT_MCMP2 HRTIM_MDIER_MCMP2IE /*!< Master compare 2 interrupt flag */ -#define HRTIM_MASTER_IT_MCMP3 HRTIM_MDIER_MCMP3IE /*!< Master compare 3 interrupt flag */ -#define HRTIM_MASTER_IT_MCMP4 HRTIM_MDIER_MCMP4IE /*!< Master compare 4 interrupt flag */ -#define HRTIM_MASTER_IT_MREP HRTIM_MDIER_MREPIE /*!< Master Repetition interrupt flag */ -#define HRTIM_MASTER_IT_SYNC HRTIM_MDIER_SYNCIE /*!< Synchronization input interrupt flag */ -#define HRTIM_MASTER_IT_MUPD HRTIM_MDIER_MUPDIE /*!< Master update interrupt flag */ - -#define IS_HRTIM_MASTER_IT(IT)\ - (((IT) == HRTIM_MDIER_MCMP1IE) || \ - ((IT) == HRTIM_MDIER_MCMP2IE) || \ - ((IT) == HRTIM_MDIER_MCMP3IE) || \ - ((IT) == HRTIM_MDIER_MCMP4IE) || \ - ((IT) == HRTIM_MDIER_MREPIE) || \ - ((IT) == HRTIM_MDIER_SYNCIE) || \ - ((IT) == HRTIM_MDIER_MUPDIE)) - -/** @defgroup HRTIM_MasterFlag - * @{ - */ -#define HRTIM_MASTER_FLAG_MCMP1 HRTIM_MISR_MCMP1 /*!< Master compare 1 interrupt flag */ -#define HRTIM_MASTER_FLAG_MCMP2 HRTIM_MISR_MCMP2 /*!< Master compare 2 interrupt flag */ -#define HRTIM_MASTER_FLAG_MCMP3 HRTIM_MISR_MCMP3 /*!< Master compare 3 interrupt flag */ -#define HRTIM_MASTER_FLAG_MCMP4 HRTIM_MISR_MCMP4 /*!< Master compare 4 interrupt flag */ -#define HRTIM_MASTER_FLAG_MREP HRTIM_MISR_MREP /*!< Master Repetition interrupt flag */ -#define HRTIM_MASTER_FLAG_SYNC HRTIM_MISR_SYNC /*!< Synchronization input interrupt flag */ -#define HRTIM_MASTER_FLAG_MUPD HRTIM_MISR_MUPD /*!< Master update interrupt flag */ - -#define IS_HRTIM_MASTER_FLAG(FLAG)\ - (((FLAG) == HRTIM_MISR_MCMP1) || \ - ((FLAG) == HRTIM_MISR_MCMP2) || \ - ((FLAG) == HRTIM_MISR_MCMP3) || \ - ((FLAG) == HRTIM_MISR_MCMP4) || \ - ((FLAG) == HRTIM_MISR_MREP) || \ - ((FLAG) == HRTIM_MISR_SYNC) || \ - ((FLAG) == HRTIM_MISR_MUPD)) -/** - * @} - */ - -/** @defgroup HRTIM_TimingUnitInterrupt - * @{ - */ -#define HRTIM_TIM_IT_CMP1 HRTIM_TIMDIER_CMP1IE /*!< Timer compare 1 interrupt flag */ -#define HRTIM_TIM_IT_CMP2 HRTIM_TIMDIER_CMP2IE /*!< Timer compare 2 interrupt flag */ -#define HRTIM_TIM_IT_CMP3 HRTIM_TIMDIER_CMP3IE /*!< Timer compare 3 interrupt flag */ -#define HRTIM_TIM_IT_CMP4 HRTIM_TIMDIER_CMP4IE /*!< Timer compare 4 interrupt flag */ -#define HRTIM_TIM_IT_REP HRTIM_TIMDIER_REPIE /*!< Timer repetition interrupt flag */ -#define HRTIM_TIM_IT_UPD HRTIM_TIMDIER_UPDIE /*!< Timer update interrupt flag */ -#define HRTIM_TIM_IT_CPT1 HRTIM_TIMDIER_CPT1IE /*!< Timer capture 1 interrupt flag */ -#define HRTIM_TIM_IT_CPT2 HRTIM_TIMDIER_CPT2IE /*!< Timer capture 2 interrupt flag */ -#define HRTIM_TIM_IT_SET1 HRTIM_TIMDIER_SET1IE /*!< Timer output 1 set interrupt flag */ -#define HRTIM_TIM_IT_RST1 HRTIM_TIMDIER_RST1IE /*!< Timer output 1 reset interrupt flag */ -#define HRTIM_TIM_IT_SET2 HRTIM_TIMDIER_SET2IE /*!< Timer output 2 set interrupt flag */ -#define HRTIM_TIM_IT_RST2 HRTIM_TIMDIER_RST2IE /*!< Timer output 2 reset interrupt flag */ -#define HRTIM_TIM_IT_RST HRTIM_TIMDIER_RSTIE /*!< Timer reset interrupt flag */ -#define HRTIM_TIM_IT_DLYPRT HRTIM_TIMDIER_DLYPRT1IE /*!< Timer delay protection interrupt flag */ - -#define IS_HRTIM_TIM_IT(IT)\ - (((IT) == HRTIM_TIMDIER_CMP1IE) || \ - ((IT) == HRTIM_TIMDIER_CMP2IE) || \ - ((IT) == HRTIM_TIMDIER_CMP3IE) || \ - ((IT) == HRTIM_TIMDIER_CMP4IE) || \ - ((IT) == HRTIM_TIMDIER_REPIE) || \ - ((IT) == HRTIM_TIMDIER_UPDIE) || \ - ((IT) == HRTIM_TIMDIER_CPT1IE) || \ - ((IT) == HRTIM_TIMDIER_CPT2IE) || \ - ((IT) == HRTIM_TIMDIER_SET1IE) || \ - ((IT) == HRTIM_TIMDIER_RST1IE) || \ - ((IT) == HRTIM_TIMDIER_SET2IE) || \ - ((IT) == HRTIM_TIMDIER_RST2IE) || \ - ((IT) == HRTIM_TIMDIER_RSTIE) || \ - ((IT) == HRTIM_TIMDIER_DLYPRTIE)) - -/** - * @} - */ - -/** @defgroup HRTIM_TimingUnitFlag - * @{ - */ -#define HRTIM_TIM_FLAG_CMP1 HRTIM_TIMISR_CMP1 /*!< Timer compare 1 interrupt flag */ -#define HRTIM_TIM_FLAG_CMP2 HRTIM_TIMISR_CMP2 /*!< Timer compare 2 interrupt flag */ -#define HRTIM_TIM_FLAG_CMP3 HRTIM_TIMISR_CMP3 /*!< Timer compare 3 interrupt flag */ -#define HRTIM_TIM_FLAG_CMP4 HRTIM_TIMISR_CMP4 /*!< Timer compare 4 interrupt flag */ -#define HRTIM_TIM_FLAG_REP HRTIM_TIMISR_REP /*!< Timer repetition interrupt flag */ -#define HRTIM_TIM_FLAG_UPD HRTIM_TIMISR_UPD /*!< Timer update interrupt flag */ -#define HRTIM_TIM_FLAG_CPT1 HRTIM_TIMISR_CPT1 /*!< Timer capture 1 interrupt flag */ -#define HRTIM_TIM_FLAG_CPT2 HRTIM_TIMISR_CPT2 /*!< Timer capture 2 interrupt flag */ -#define HRTIM_TIM_FLAG_SET1 HRTIM_TIMISR_SET1 /*!< Timer output 1 set interrupt flag */ -#define HRTIM_TIM_FLAG_RST1 HRTIM_TIMISR_RST1 /*!< Timer output 1 reset interrupt flag */ -#define HRTIM_TIM_FLAG_SET2 HRTIM_TIMISR_SET2 /*!< Timer output 2 set interrupt flag */ -#define HRTIM_TIM_FLAG_RST2 HRTIM_TIMISR_RST2 /*!< Timer output 2 reset interrupt flag */ -#define HRTIM_TIM_FLAG_RST HRTIM_TIMDIER_RSTIE /*!< Timer reset interrupt flag */ -#define HRTIM_TIM_FLAG_DLYPRT1 HRTIM_TIMISR_DLYPRT /*!< Timer delay protection interrupt flag */ - -#define IS_HRTIM_TIM_FLAG(FLAG)\ - (((FLAG) == HRTIM_TIM_FLAG_CMP1) || \ - ((FLAG) == HRTIM_TIM_FLAG_CMP2) || \ - ((FLAG) == HRTIM_TIM_FLAG_CMP3) || \ - ((FLAG) == HRTIM_TIM_FLAG_CMP4) || \ - ((FLAG) == HRTIM_TIM_FLAG_REP) || \ - ((FLAG) == HRTIM_TIM_FLAG_UPD) || \ - ((FLAG) == HRTIM_TIM_FLAG_CPT1) || \ - ((FLAG) == HRTIM_TIM_FLAG_CPT2) || \ - ((FLAG) == HRTIM_TIM_FLAG_SET1) || \ - ((FLAG) == HRTIM_TIM_FLAG_RST1) || \ - ((FLAG) == HRTIM_TIM_FLAG_SET2) || \ - ((FLAG) == HRTIM_TIM_FLAG_RST2) || \ - ((FLAG) == HRTIM_TIM_FLAG_RST) || \ - ((FLAG) == HRTIM_TIM_FLAG_DLYPRT1)) - -/** - * @} - */ - -/** @defgroup HRTIM_MasterDMARequest - * @{ - */ -#define HRTIM_MASTER_DMA_MCMP1 HRTIM_MDIER_MCMP1DE /*!< Master compare 1 DMA request flag */ -#define HRTIM_MASTER_DMA_MCMP2 HRTIM_MDIER_MCMP2DE /*!< Master compare 2 DMA request flag */ -#define HRTIM_MASTER_DMA_MCMP3 HRTIM_MDIER_MCMP3DE /*!< Master compare 3 DMA request flag */ -#define HRTIM_MASTER_DMA_MCMP4 HRTIM_MDIER_MCMP4DE /*!< Master compare 4 DMA request flag */ -#define HRTIM_MASTER_DMA_MREP HRTIM_MDIER_MREPDE /*!< Master Repetition DMA request flag */ -#define HRTIM_MASTER_DMA_SYNC HRTIM_MDIER_SYNCDE /*!< Synchronization input DMA request flag */ -#define HRTIM_MASTER_DMA_MUPD HRTIM_MDIER_MUPDDE /*!< Master update DMA request flag */ - -#define IS_HRTIM_MASTER_DMA(DMA)\ - (((DMA) == HRTIM_MDIER_MCMP1DE) || \ - ((DMA) == HRTIM_MDIER_MCMP2DE) || \ - ((DMA) == HRTIM_MDIER_MCMP3DE) || \ - ((DMA) == HRTIM_MDIER_MCMP4DE) || \ - ((DMA) == HRTIM_MDIER_MREPDE) || \ - ((DMA) == HRTIM_MDIER_SYNCDE) || \ - ((DMA) == HRTIM_MDIER_MUPDDE)) -/** - * @} - */ - -/** @defgroup HRTIM_TimingUnitDMARequest - * @{ - */ -#define HRTIM_TIM_DMA_CMP1 HRTIM_TIMDIER_CMP1DE /*!< Timer compare 1 interrupt flag */ -#define HRTIM_TIM_DMA_CMP2 HRTIM_TIMDIER_CMP2DE /*!< Timer compare 2 interrupt flag */ -#define HRTIM_TIM_DMA_CMP3 HRTIM_TIMDIER_CMP3DE /*!< Timer compare 3 interrupt flag */ -#define HRTIM_TIM_DMA_CMP4 HRTIM_TIMDIER_CMP4DE /*!< Timer compare 4 interrupt flag */ -#define HRTIM_TIM_DMA_REP HRTIM_TIMDIER_REPDE /*!< Timer repetition interrupt flag */ -#define HRTIM_TIM_DMA_UPD HRTIM_TIMDIER_UPDDE /*!< Timer update interrupt flag */ -#define HRTIM_TIM_DMA_CPT1 HRTIM_TIMDIER_CPT1DE /*!< Timer capture 1 interrupt flag */ -#define HRTIM_TIM_DMA_CPT2 HRTIM_TIMDIER_CPT2DE /*!< Timer capture 2 interrupt flag */ -#define HRTIM_TIM_DMA_SET1 HRTIM_TIMDIER_SET1DE /*!< Timer output 1 set interrupt flag */ -#define HRTIM_TIM_DMA_RST1 HRTIM_TIMDIER_RST1DE /*!< Timer output 1 reset interrupt flag */ -#define HRTIM_TIM_DMA_SET2 HRTIM_TIMDIER_SET2DE /*!< Timer output 2 set interrupt flag */ -#define HRTIM_TIM_DMA_RST2 HRTIM_TIMDIER_RST2DE /*!< Timer output 2 reset interrupt flag */ -#define HRTIM_TIM_DMA_RST HRTIM_TIMDIER_RSTDE /*!< Timer reset interrupt flag */ -#define HRTIM_TIM_DMA_DLYPRT HRTIM_TIMDIER_DLYPRTDE /*!< Timer delay protection interrupt flag */ - -#define IS_HRTIM_TIM_DMA(DMA)\ - (((DMA) == HRTIM_TIMDIER_CMP1DE) || \ - ((DMA) == HRTIM_TIMDIER_CMP2DE) || \ - ((DMA) == HRTIM_TIMDIER_CMP3DE) || \ - ((DMA) == HRTIM_TIMDIER_CMP4DE) || \ - ((DMA) == HRTIM_TIMDIER_REPDE) || \ - ((DMA) == HRTIM_TIMDIER_UPDDE) || \ - ((DMA) == HRTIM_TIMDIER_CPT1DE) || \ - ((DMA) == HRTIM_TIMDIER_CPT2DE) || \ - ((DMA) == HRTIM_TIMDIER_SET1DE) || \ - ((DMA) == HRTIM_TIMDIER_RST1DE) || \ - ((DMA) == HRTIM_TIMDIER_SET2DE) || \ - ((DMA) == HRTIM_TIMDIER_RST2DE) || \ - ((DMA) == HRTIM_TIMDIER_RSTDE) || \ - ((DMA) == HRTIM_TIMDIER_DLYPRTDE)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup HRTIM_Instancedefinition - * @{ - */ -#define IS_HRTIM_INSTANCE(INSTANCE) (INSTANCE) == HRTIM1) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - - -/** @brief Enables or disables the timer counter(s) - * @param __HANDLE__: specifies the HRTIM Handle. - * @param __TIMERS__: timersto enable/disable - * This parameter can be any combinations of the following values: - * @arg HRTIM_TIMERID_MASTER: Master timer identifier - * @arg HRTIM_TIMERID_TIMER_A: Timer A identifier - * @arg HRTIM_TIMERID_TIMER_B: Timer B identifier - * @arg HRTIM_TIMERID_TIMER_C: Timer C identifier - * @arg HRTIM_TIMERID_TIMER_D: Timer D identifier - * @arg HRTIM_TIMERID_TIMER_E: Timer E identifier - * @retval None - */ -#define __HRTIM_ENABLE(__HANDLE__, __TIMERS__) ((__HANDLE__)->HRTIM_MASTER.MCR |= (__TIMERS__)) - -/* The counter of a timing unit is disabled only if all the timer outputs */ -/* are disabled and no capture is configured */ -#define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN) -#define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN) -#define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN) -#define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN) -#define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN) -#define __HRTIM_DISABLE(__HANDLE__, __TIMERS__)\ - do {\ - if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\ - {\ - ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_MASTER);\ - }\ - if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\ - {\ - if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TAOEN_MASK) == RESET)\ - {\ - ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_A);\ - }\ - }\ - if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\ - {\ - if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TBOEN_MASK) == RESET)\ - {\ - ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_B);\ - }\ - }\ - if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\ - {\ - if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TCOEN_MASK) == RESET)\ - {\ - ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_C);\ - }\ - }\ - if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\ - {\ - if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TDOEN_MASK) == RESET)\ - {\ - ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_D);\ - }\ - }\ - if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\ - {\ - if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TEOEN_MASK) == RESET)\ - {\ - ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_E);\ - }\ - }\ - } while(0) - -/* Exported functions --------------------------------------------------------*/ - -/* Simple time base related functions *****************************************/ -void HRTIM_SimpleBase_Init(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct); - -void HRTIM_DeInit(HRTIM_TypeDef* HRTIMx); - -void HRTIM_SimpleBaseStart(HRTIM_TypeDef *hrtim, uint32_t TimerIdx); -void HRTIM_SimpleBaseStop(HRTIM_TypeDef *hrtim, uint32_t TimerIdx); - -/* Simple output compare related functions ************************************/ -void HRTIM_SimpleOC_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct); - -void HRTIM_SimpleOCChannelConfig(HRTIM_TypeDef *hrtim, - uint32_t TimerIdx, - uint32_t OCChannel, - HRTIM_BasicOCChannelCfgTypeDef* pBasicOCChannelCfg); - -void HRTIM_SimpleOCStart(HRTIM_TypeDef *hrtim, - uint32_t TimerIdx, - uint32_t OCChannel); -void HRTIM_SimpleOCStop(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t OCChannel); -/* Simple PWM output related functions ****************************************/ -void HRTIM_SimplePWM_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct); - -void HRTIM_SimplePWMChannelConfig(HRTIM_TypeDef *hrtim, - uint32_t TimerIdx, - uint32_t PWMChannel, - HRTIM_BasicPWMChannelCfgTypeDef* pBasicPWMChannelCfg); - -void HRTIM_SimplePWMStart(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t PWMChannel); -void HRTIM_SimplePWMStop(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t PWMChannel); -/* Simple capture related functions *******************************************/ -void HRTIM_SimpleCapture_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct); - -void HRTIM_SimpleCaptureChannelConfig(HRTIM_TypeDef *hrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel, - HRTIM_BasicCaptureChannelCfgTypeDef* pBasicCaptureChannelCfg); - -void HRTIM_SimpleCaptureStart(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t CaptureChannel); -void HRTIM_SimpleCaptureStop(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t CaptureChannel); -/* SImple one pulse related functions *****************************************/ -void HRTIM_SimpleOnePulse_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct); - -void HRTIM_SimpleOnePulseChannelConfig(HRTIM_TypeDef *hrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel, - HRTIM_BasicOnePulseChannelCfgTypeDef* pBasicOnePulseChannelCfg); - -void HRTIM_SimpleOnePulseStart(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - uint32_t OnePulseChannel); -void HRTIM_SimpleOnePulseStop(HRTIM_TypeDef * HRTIM_, - uint32_t TimerIdx, - uint32_t OnePulseChannel); -/* Waveform related functions *************************************************/ -void HRTIM_Waveform_Init(HRTIM_TypeDef * HRTIMx, - uint32_t TimerIdx, - HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct, - HRTIM_TimerInitTypeDef* HRTIM_TimerInitStruct); - -void HRTIM_WaveformTimerConfig(HRTIM_TypeDef *hrtim, - uint32_t TimerIdx, - HRTIM_TimerCfgTypeDef * HRTIM_TimerCfgStruct); - -void HRTIM_WaveformCompareConfig(HRTIM_TypeDef *hrtim, - uint32_t TimerIdx, - uint32_t CompareUnit, - HRTIM_CompareCfgTypeDef* pCompareCfg); - -void HRTIM_MasterSetCompare(HRTIM_TypeDef * HRTIMx, - uint32_t CompareUnit, - uint32_t Compare); -void HRTIM_WaveformCaptureConfig(HRTIM_TypeDef *hrtim, - uint32_t TimerIdx, - uint32_t CaptureUnit, - HRTIM_CaptureCfgTypeDef* pCaptureCfg); - -void HRTIM_WaveformOuputConfig(HRTIM_TypeDef *hrtim, - uint32_t TimerIdx, - uint32_t Output, - HRTIM_OutputCfgTypeDef * pOutputCfg); - -void HRTIM_TimerEventFilteringConfig(HRTIM_TypeDef *hrtim, - uint32_t TimerIdx, - uint32_t Event, - HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg); - -void HRTIM_DeadTimeConfig(HRTIM_TypeDef *hrtim, - uint32_t TimerIdx, - HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg); - -void HRTIM_ChopperModeConfig(HRTIM_TypeDef *hrtim, - uint32_t TimerIdx, - HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg); - -void HRTIM_BurstDMAConfig(HRTIM_TypeDef *hrtim, - uint32_t TimerIdx, - uint32_t RegistersToUpdate); - -void HRTIM_SynchronizationConfig(HRTIM_TypeDef *HRTIMx, - HRTIM_SynchroCfgTypeDef * pSynchroCfg); - -void HRTIM_BurstModeConfig(HRTIM_TypeDef *hrtim, - HRTIM_BurstModeCfgTypeDef* pBurstModeCfg); - -void HRTIM_EventConfig(HRTIM_TypeDef *hrtim, - uint32_t Event, - HRTIM_EventCfgTypeDef* pEventCfg); - -void HRTIM_EventPrescalerConfig(HRTIM_TypeDef *hrtim, - uint32_t Prescaler); - -void HRTIM_FaultConfig(HRTIM_TypeDef *hrtim, - HRTIM_FaultCfgTypeDef* pFaultCfg, - uint32_t Fault); - -void HRTIM_FaultPrescalerConfig(HRTIM_TypeDef *hrtim, - uint32_t Prescaler); -void HRTIM_FaultModeCtl(HRTIM_TypeDef * HRTIMx, uint32_t Fault, uint32_t Enable); - -void HRTIM_ADCTriggerConfig(HRTIM_TypeDef *hrtim, - uint32_t ADCTrigger, - HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg); - -void HRTIM_WaveformCounterStart(HRTIM_TypeDef *hrtim, - uint32_t TimersToStart); - -void HRTIM_WaveformCounterStop(HRTIM_TypeDef *hrtim, - uint32_t TimersToStop); - -void HRTIM_WaveformOutputStart(HRTIM_TypeDef *hrtim, - uint32_t OuputsToStart); -void HRTIM_WaveformOutputStop(HRTIM_TypeDef * HRTIM_, - uint32_t OuputsToStop); - -void HRTIM_DLLCalibrationStart(HRTIM_TypeDef *hrtim, - uint32_t CalibrationRate); - -/* Interrupt/flags and DMA management */ -void HRTIM_ITConfig(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_TIM_IT, FunctionalState NewState); -void HRTIM_ITCommonConfig(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT, FunctionalState NewState); - -void HRTIM_ClearFlag(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG); -void HRTIM_ClearCommonFlag(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG); - -void HRTIM_ClearITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT); -void HRTIM_ClearCommonITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT); - -FlagStatus HRTIM_GetFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG); -FlagStatus HRTIM_GetCommonFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG); - -ITStatus HRTIM_GetITStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT); -ITStatus HRTIM_GetCommonITStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT); - - -void HRTIM_DMACmd(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_DMA, FunctionalState NewState); - -void HRTIM_BurstModeCtl(HRTIM_TypeDef *hrtim, - uint32_t Enable); - -void HRTIM_SoftwareCapture(HRTIM_TypeDef *hrtim, - uint32_t TimerIdx, - uint32_t CaptureUnit); - -void HRTIM_SoftwareUpdate(HRTIM_TypeDef *hrtim, - uint32_t TimersToUpdate); - -void HRTIM_SoftwareReset(HRTIM_TypeDef *hrtim, - uint32_t TimersToReset); - - -uint32_t HRTIM_GetCapturedValue(HRTIM_TypeDef *hrtim, - uint32_t TimerIdx, - uint32_t CaptureUnit); - -void HRTIM_WaveformOutputConfig(HRTIM_TypeDef * HRTIM_, - uint32_t TimerIdx, - uint32_t Output, - HRTIM_OutputCfgTypeDef * pOutputCfg); - -void HRTIM_WaveformSetOutputLevel(HRTIM_TypeDef *hrtim, - uint32_t TimerIdx, - uint32_t Output, - uint32_t OutputLevel); - -uint32_t HRTIM_WaveformGetOutputLevel(HRTIM_TypeDef *hrtim, - uint32_t TimerIdx, - uint32_t Output); - -uint32_t HRTIM_WaveformGetOutputState(HRTIM_TypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t Output); - -uint32_t HRTIM_GetDelayedProtectionStatus(HRTIM_TypeDef *hrtim, - uint32_t TimerIdx, - uint32_t Output); - -uint32_t HRTIM_GetBurstStatus(HRTIM_TypeDef *hrtim); - -uint32_t HRTIM_GetCurrentPushPullStatus(HRTIM_TypeDef *hrtim, - uint32_t TimerIdx); - -uint32_t HRTIM_GetIdlePushPullStatus(HRTIM_TypeDef *hrtim, - uint32_t TimerIdx); -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F30x_HRTIM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_i2c.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1595 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_i2c.c - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Inter-Integrated circuit (I2C): - * + Initialization and Configuration - * + Communications handling - * + SMBUS management - * + I2C registers management - * + Data transfers management - * + DMA transfers management - * + Interrupts and flags management - * - * @verbatim - ============================================================================ - ##### How to use this driver ##### - ============================================================================ - [..] - (#) Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE) - function for I2C1 or I2C2. - (#) Enable SDA, SCL and SMBA (when used) GPIO clocks using - RCC_AHBPeriphClockCmd() function. - (#) Peripherals alternate function: - (++) Connect the pin to the desired peripherals' Alternate - Function (AF) using GPIO_PinAFConfig() function. - (++) Configure the desired pin in alternate function by: - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - (++) Select the type, OpenDrain and speed via - GPIO_PuPd, GPIO_OType and GPIO_Speed members - (++) Call GPIO_Init() function. - (#) Program the Mode, Timing , Own address, Ack and Acknowledged Address - using the I2C_Init() function. - (#) Optionally you can enable/configure the following parameters without - re-initialization (i.e there is no need to call again I2C_Init() function): - (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function. - (++) Enable the dual addressing mode using I2C_DualAddressCmd() function. - (++) Enable the general call using the I2C_GeneralCallCmd() function. - (++) Enable the clock stretching using I2C_StretchClockCmd() function. - (++) Enable the PEC Calculation using I2C_CalculatePEC() function. - (++) For SMBus Mode: - (+++) Enable the SMBusAlert pin using I2C_SMBusAlertCmd() function. - (#) Enable the NVIC and the corresponding interrupt using the function - I2C_ITConfig() if you need to use interrupt mode. - (#) When using the DMA mode - (++) Configure the DMA using DMA_Init() function. - (++) Active the needed channel Request using I2C_DMACmd() function. - (#) Enable the I2C using the I2C_Cmd() function. - (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the - transfers. - [..] - (@) When using I2C in Fast Mode Plus, SCL and SDA pin 20mA current drive capability - must be enabled by setting the driving capability control bit in SYSCFG. - - @endverbatim - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x_i2c.h" -#include "stm32f30x_rcc.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @defgroup I2C - * @brief I2C driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -#define CR1_CLEAR_MASK ((uint32_t)0x00CFE0FF) /*<! I2C CR1 clear register Mask */ -#define CR2_CLEAR_MASK ((uint32_t)0x07FF7FFF) /*<! I2C CR2 clear register Mask */ -#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! I2C TIMING clear register Mask */ -#define ERROR_IT_MASK ((uint32_t)0x00003F00) /*<! I2C Error interrupt register Mask */ -#define TC_IT_MASK ((uint32_t)0x000000C0) /*<! I2C TC interrupt register Mask */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup I2C_Private_Functions - * @{ - */ - - -/** @defgroup I2C_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides a set of functions allowing to initialize the I2C Mode, - I2C Timing, I2C filters, I2C Addressing mode, I2C OwnAddress1. - - [..] The I2C_Init() function follows the I2C configuration procedures (these procedures - are available in reference manual). - - [..] When the Software Reset is performed using I2C_SoftwareResetCmd() function, the internal - states machines are reset and communication control bits, as well as status bits come - back to their reset value. - - [..] Before enabling Stop mode using I2C_StopModeCmd() I2C Clock source must be set to - HSI and Digital filters must be disabled. - - [..] Before enabling Own Address 2 via I2C_DualAddressCmd() function, OA2 and mask should be - configured using I2C_OwnAddress2Config() function. - - [..] I2C_SlaveByteControlCmd() enable Slave byte control that allow user to get control of - each byte in slave mode when NBYTES is set to 0x01. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the I2Cx peripheral registers to their default reset values. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval None - */ -void I2C_DeInit(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - if (I2Cx == I2C1) - { - /* Enable I2C1 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); - /* Release I2C1 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); - } - else - { - /* Enable I2C2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); - /* Release I2C2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); - } -} - -/** - * @brief Initializes the I2Cx peripheral according to the specified - * parameters in the I2C_InitStruct. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that - * contains the configuration information for the specified I2C peripheral. - * @retval None - */ -void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_ANALOG_FILTER(I2C_InitStruct->I2C_AnalogFilter)); - assert_param(IS_I2C_DIGITAL_FILTER(I2C_InitStruct->I2C_DigitalFilter)); - assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); - assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); - assert_param(IS_I2C_ACK(I2C_InitStruct->I2C_Ack)); - assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); - - /* Disable I2Cx Peripheral */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE); - - /*---------------------------- I2Cx FILTERS Configuration ------------------*/ - /* Get the I2Cx CR1 value */ - tmpreg = I2Cx->CR1; - /* Clear I2Cx CR1 register */ - tmpreg &= CR1_CLEAR_MASK; - /* Configure I2Cx: analog and digital filter */ - /* Set ANFOFF bit according to I2C_AnalogFilter value */ - /* Set DFN bits according to I2C_DigitalFilter value */ - tmpreg |= (uint32_t)I2C_InitStruct->I2C_AnalogFilter |(I2C_InitStruct->I2C_DigitalFilter << 8); - - /* Write to I2Cx CR1 */ - I2Cx->CR1 = tmpreg; - - /*---------------------------- I2Cx TIMING Configuration -------------------*/ - /* Configure I2Cx: Timing */ - /* Set TIMINGR bits according to I2C_Timing */ - /* Write to I2Cx TIMING */ - I2Cx->TIMINGR = I2C_InitStruct->I2C_Timing & TIMING_CLEAR_MASK; - - /* Enable I2Cx Peripheral */ - I2Cx->CR1 |= I2C_CR1_PE; - - /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ - /* Clear tmpreg local variable */ - tmpreg = 0; - /* Clear OAR1 register */ - I2Cx->OAR1 = (uint32_t)tmpreg; - /* Clear OAR2 register */ - I2Cx->OAR2 = (uint32_t)tmpreg; - /* Configure I2Cx: Own Address1 and acknowledged address */ - /* Set OA1MODE bit according to I2C_AcknowledgedAddress value */ - /* Set OA1 bits according to I2C_OwnAddress1 value */ - tmpreg = (uint32_t)((uint32_t)I2C_InitStruct->I2C_AcknowledgedAddress | \ - (uint32_t)I2C_InitStruct->I2C_OwnAddress1); - /* Write to I2Cx OAR1 */ - I2Cx->OAR1 = tmpreg; - /* Enable Own Address1 acknowledgement */ - I2Cx->OAR1 |= I2C_OAR1_OA1EN; - - /*---------------------------- I2Cx MODE Configuration ---------------------*/ - /* Configure I2Cx: mode */ - /* Set SMBDEN and SMBHEN bits according to I2C_Mode value */ - tmpreg = I2C_InitStruct->I2C_Mode; - /* Write to I2Cx CR1 */ - I2Cx->CR1 |= tmpreg; - - /*---------------------------- I2Cx ACK Configuration ----------------------*/ - /* Get the I2Cx CR2 value */ - tmpreg = I2Cx->CR2; - /* Clear I2Cx CR2 register */ - tmpreg &= CR2_CLEAR_MASK; - /* Configure I2Cx: acknowledgement */ - /* Set NACK bit according to I2C_Ack value */ - tmpreg |= I2C_InitStruct->I2C_Ack; - /* Write to I2Cx CR2 */ - I2Cx->CR2 = tmpreg; -} - -/** - * @brief Fills each I2C_InitStruct member with its default value. - * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) -{ - /*---------------- Reset I2C init structure parameters values --------------*/ - /* Initialize the I2C_Timing member */ - I2C_InitStruct->I2C_Timing = 0; - /* Initialize the I2C_AnalogFilter member */ - I2C_InitStruct->I2C_AnalogFilter = I2C_AnalogFilter_Enable; - /* Initialize the I2C_DigitalFilter member */ - I2C_InitStruct->I2C_DigitalFilter = 0; - /* Initialize the I2C_Mode member */ - I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; - /* Initialize the I2C_OwnAddress1 member */ - I2C_InitStruct->I2C_OwnAddress1 = 0; - /* Initialize the I2C_Ack member */ - I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; - /* Initialize the I2C_AcknowledgedAddress member */ - I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; -} - -/** - * @brief Enables or disables the specified I2C peripheral. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C peripheral */ - I2Cx->CR1 |= I2C_CR1_PE; - } - else - { - /* Disable the selected I2C peripheral */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE); - } -} - - -/** - * @brief Enables or disables the specified I2C software reset. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval None - */ -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Disable peripheral */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE); - - /* Perform a dummy read to delay the disable of peripheral for minimum - 3 APB clock cycles to perform the software reset functionality */ - *(__IO uint32_t *)(uint32_t)I2Cx; - - /* Enable peripheral */ - I2Cx->CR1 |= I2C_CR1_PE; -} - -/** - * @brief Enables or disables the specified I2C interrupts. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg I2C_IT_ERRI: Error interrupt mask - * @arg I2C_IT_TCI: Transfer Complete interrupt mask - * @arg I2C_IT_STOPI: Stop Detection interrupt mask - * @arg I2C_IT_NACKI: Not Acknowledge received interrupt mask - * @arg I2C_IT_ADDRI: Address Match interrupt mask - * @arg I2C_IT_RXI: RX interrupt mask - * @arg I2C_IT_TXI: TX interrupt mask - * @param NewState: new state of the specified I2C interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_I2C_CONFIG_IT(I2C_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected I2C interrupts */ - I2Cx->CR1 |= I2C_IT; - } - else - { - /* Disable the selected I2C interrupts */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_IT); - } -} - -/** - * @brief Enables or disables the I2C Clock stretching. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx Clock stretching. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable clock stretching */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_NOSTRETCH); - } - else - { - /* Disable clock stretching */ - I2Cx->CR1 |= I2C_CR1_NOSTRETCH; - } -} - -/** - * @brief Enables or disables I2C wakeup from stop mode. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx stop mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable wakeup from stop mode */ - I2Cx->CR1 |= I2C_CR1_WUPEN; - } - else - { - /* Disable wakeup from stop mode */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_WUPEN); - } -} - -/** - * @brief Enables or disables the I2C own address 2. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C own address 2. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable own address 2 */ - I2Cx->OAR2 |= I2C_OAR2_OA2EN; - } - else - { - /* Disable own address 2 */ - I2Cx->OAR2 &= (uint32_t)~((uint32_t)I2C_OAR2_OA2EN); - } -} - -/** - * @brief Configures the I2C slave own address 2 and mask. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Address: specifies the slave address to be programmed. - * @param Mask: specifies own address 2 mask to be programmed. - * This parameter can be one of the following values: - * @arg I2C_OA2_NoMask: no mask. - * @arg I2C_OA2_Mask01: OA2[1] is masked and don't care. - * @arg I2C_OA2_Mask02: OA2[2:1] are masked and don't care. - * @arg I2C_OA2_Mask03: OA2[3:1] are masked and don't care. - * @arg I2C_OA2_Mask04: OA2[4:1] are masked and don't care. - * @arg I2C_OA2_Mask05: OA2[5:1] are masked and don't care. - * @arg I2C_OA2_Mask06: OA2[6:1] are masked and don't care. - * @arg I2C_OA2_Mask07: OA2[7:1] are masked and don't care. - * @retval None - */ -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_OWN_ADDRESS2(Address)); - assert_param(IS_I2C_OWN_ADDRESS2_MASK(Mask)); - - /* Get the old register value */ - tmpreg = I2Cx->OAR2; - - /* Reset I2Cx OA2 bit [7:1] and OA2MSK bit [1:0] */ - tmpreg &= (uint32_t)~((uint32_t)(I2C_OAR2_OA2 | I2C_OAR2_OA2MSK)); - - /* Set I2Cx SADD */ - tmpreg |= (uint32_t)(((uint32_t)Address & I2C_OAR2_OA2) | \ - (((uint32_t)Mask << 8) & I2C_OAR2_OA2MSK)) ; - - /* Store the new register value */ - I2Cx->OAR2 = tmpreg; -} - -/** - * @brief Enables or disables the I2C general call mode. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C general call mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable general call mode */ - I2Cx->CR1 |= I2C_CR1_GCEN; - } - else - { - /* Disable general call mode */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_GCEN); - } -} - -/** - * @brief Enables or disables the I2C slave byte control. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C slave byte control. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable slave byte control */ - I2Cx->CR1 |= I2C_CR1_SBC; - } - else - { - /* Disable slave byte control */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_SBC); - } -} - -/** - * @brief Configures the slave address to be transmitted after start generation. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Address: specifies the slave address to be programmed. - * @note This function should be called before generating start condition. - * @retval None - */ -void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_SLAVE_ADDRESS(Address)); - - /* Get the old register value */ - tmpreg = I2Cx->CR2; - - /* Reset I2Cx SADD bit [9:0] */ - tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_SADD); - - /* Set I2Cx SADD */ - tmpreg |= (uint32_t)((uint32_t)Address & I2C_CR2_SADD); - - /* Store the new register value */ - I2Cx->CR2 = tmpreg; -} - -/** - * @brief Enables or disables the I2C 10-bit addressing mode for the master. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C 10-bit addressing mode. - * This parameter can be: ENABLE or DISABLE. - * @note This function should be called before generating start condition. - * @retval None - */ -void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable 10-bit addressing mode */ - I2Cx->CR2 |= I2C_CR2_ADD10; - } - else - { - /* Disable 10-bit addressing mode */ - I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_ADD10); - } -} - -/** - * @} - */ - - -/** @defgroup I2C_Group2 Communications handling functions - * @brief Communications handling functions - * -@verbatim - =============================================================================== - ##### Communications handling functions ##### - =============================================================================== - [..] This section provides a set of functions that handles I2C communication. - - [..] Automatic End mode is enabled using I2C_AutoEndCmd() function. When Reload - mode is enabled via I2C_ReloadCmd() AutoEnd bit has no effect. - - [..] I2C_NumberOfBytesConfig() function set the number of bytes to be transferred, - this configuration should be done before generating start condition in master - mode. - - [..] When switching from master write operation to read operation in 10Bit addressing - mode, master can only sends the 1st 7 bits of the 10 bit address, followed by - Read direction by enabling HEADR bit using I2C_10BitAddressHeader() function. - - [..] In master mode, when transferring more than 255 bytes Reload mode should be used - to handle communication. In the first phase of transfer, Nbytes should be set to - 255. After transferring these bytes TCR flag is set and I2C_TransferHandling() - function should be called to handle remaining communication. - - [..] In master mode, when software end mode is selected when all data is transferred - TC flag is set I2C_TransferHandling() function should be called to generate STOP - or generate ReStart. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the I2C automatic end mode (stop condition is - * automatically sent when nbytes data are transferred). - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C automatic end mode. - * This parameter can be: ENABLE or DISABLE. - * @note This function has effect if Reload mode is disabled. - * @retval None - */ -void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Auto end mode */ - I2Cx->CR2 |= I2C_CR2_AUTOEND; - } - else - { - /* Disable Auto end mode */ - I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_AUTOEND); - } -} - -/** - * @brief Enables or disables the I2C nbytes reload mode. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the nbytes reload mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Auto Reload mode */ - I2Cx->CR2 |= I2C_CR2_RELOAD; - } - else - { - /* Disable Auto Reload mode */ - I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RELOAD); - } -} - -/** - * @brief Configures the number of bytes to be transmitted/received. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Number_Bytes: specifies the number of bytes to be programmed. - * @retval None - */ -void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Get the old register value */ - tmpreg = I2Cx->CR2; - - /* Reset I2Cx Nbytes bit [7:0] */ - tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_NBYTES); - - /* Set I2Cx Nbytes */ - tmpreg |= (uint32_t)(((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES); - - /* Store the new register value */ - I2Cx->CR2 = tmpreg; -} - -/** - * @brief Configures the type of transfer request for the master. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_Direction: specifies the transfer request direction to be programmed. - * This parameter can be one of the following values: - * @arg I2C_Direction_Transmitter: Master request a write transfer - * @arg I2C_Direction_Receiver: Master request a read transfer - * @retval None - */ -void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction) -{ -/* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DIRECTION(I2C_Direction)); - - /* Test on the direction to set/reset the read/write bit */ - if (I2C_Direction == I2C_Direction_Transmitter) - { - /* Request a write Transfer */ - I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RD_WRN); - } - else - { - /* Request a read Transfer */ - I2Cx->CR2 |= I2C_CR2_RD_WRN; - } -} - -/** - * @brief Generates I2Cx communication START condition. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C START condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Generate a START condition */ - I2Cx->CR2 |= I2C_CR2_START; - } - else - { - /* Disable the START condition generation */ - I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_START); - } -} - -/** - * @brief Generates I2Cx communication STOP condition. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C STOP condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Generate a STOP condition */ - I2Cx->CR2 |= I2C_CR2_STOP; - } - else - { - /* Disable the STOP condition generation */ - I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_STOP); - } -} - -/** - * @brief Enables or disables the I2C 10-bit header only mode with read direction. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C 10-bit header only mode. - * This parameter can be: ENABLE or DISABLE. - * @note This mode can be used only when switching from master transmitter mode - * to master receiver mode. - * @retval None - */ -void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable 10-bit header only mode */ - I2Cx->CR2 |= I2C_CR2_HEAD10R; - } - else - { - /* Disable 10-bit header only mode */ - I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_HEAD10R); - } -} - -/** - * @brief Generates I2C communication Acknowledge. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the Acknowledge. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable ACK generation */ - I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_NACK); - } - else - { - /* Enable NACK generation */ - I2Cx->CR2 |= I2C_CR2_NACK; - } -} - -/** - * @brief Returns the I2C slave matched address . - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval The value of the slave matched address . - */ -uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Return the slave matched address in the SR1 register */ - return (uint8_t)(((uint32_t)I2Cx->ISR & I2C_ISR_ADDCODE) >> 16) ; -} - -/** - * @brief Returns the I2C slave received request. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval The value of the received request. - */ -uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx) -{ - uint32_t tmpreg = 0; - uint16_t direction = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Return the slave matched address in the SR1 register */ - tmpreg = (uint32_t)(I2Cx->ISR & I2C_ISR_DIR); - - /* If write transfer is requested */ - if (tmpreg == 0) - { - /* write transfer is requested */ - direction = I2C_Direction_Transmitter; - } - else - { - /* Read transfer is requested */ - direction = I2C_Direction_Receiver; - } - return direction; -} - -/** - * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Address: specifies the slave address to be programmed. - * @param Number_Bytes: specifies the number of bytes to be programmed. - * This parameter must be a value between 0 and 255. - * @param ReloadEndMode: new state of the I2C START condition generation. - * This parameter can be one of the following values: - * @arg I2C_Reload_Mode: Enable Reload mode . - * @arg I2C_AutoEnd_Mode: Enable Automatic end mode. - * @arg I2C_SoftEnd_Mode: Enable Software end mode. - * @param StartStopMode: new state of the I2C START condition generation. - * This parameter can be one of the following values: - * @arg I2C_No_StartStop: Don't Generate stop and start condition. - * @arg I2C_Generate_Stop: Generate stop condition (Number_Bytes should be set to 0). - * @arg I2C_Generate_Start_Read: Generate Restart for read request. - * @arg I2C_Generate_Start_Write: Generate Restart for write request. - * @retval None - */ -void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_SLAVE_ADDRESS(Address)); - assert_param(IS_RELOAD_END_MODE(ReloadEndMode)); - assert_param(IS_START_STOP_MODE(StartStopMode)); - - /* Get the CR2 register value */ - tmpreg = I2Cx->CR2; - - /* clear tmpreg specific bits */ - tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)); - - /* update tmpreg */ - tmpreg |= (uint32_t)(((uint32_t)Address & I2C_CR2_SADD) | (((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES) | \ - (uint32_t)ReloadEndMode | (uint32_t)StartStopMode); - - /* update CR2 register */ - I2Cx->CR2 = tmpreg; -} - -/** - * @} - */ - - -/** @defgroup I2C_Group3 SMBUS management functions - * @brief SMBUS management functions - * -@verbatim - =============================================================================== - ##### SMBUS management functions ##### - =============================================================================== - [..] This section provides a set of functions that handles SMBus communication - and timeouts detection. - - [..] The SMBus Device default address (0b1100 001) is enabled by calling I2C_Init() - function and setting I2C_Mode member of I2C_InitTypeDef() structure to - I2C_Mode_SMBusDevice. - - [..] The SMBus Host address (0b0001 000) is enabled by calling I2C_Init() - function and setting I2C_Mode member of I2C_InitTypeDef() structure to - I2C_Mode_SMBusHost. - - [..] The Alert Response Address (0b0001 100) is enabled using I2C_SMBusAlertCmd() - function. - - [..] To detect cumulative SCL stretch in master and slave mode, TIMEOUTB should be - configured (in accordance to SMBus specification) using I2C_TimeoutBConfig() - function then I2C_ExtendedClockTimeoutCmd() function should be called to enable - the detection. - - [..] SCL low timeout is detected by configuring TIMEOUTB using I2C_TimeoutBConfig() - function followed by the call of I2C_ClockTimeoutCmd(). When adding to this - procedure the call of I2C_IdleClockTimeoutCmd() function, Bus Idle condition - (both SCL and SDA high) is detected also. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables I2C SMBus alert. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx SMBus alert. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable SMBus alert */ - I2Cx->CR1 |= I2C_CR1_ALERTEN; - } - else - { - /* Disable SMBus alert */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_ALERTEN); - } -} - -/** - * @brief Enables or disables I2C Clock Timeout (SCL Timeout detection). - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx clock Timeout. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Clock Timeout */ - I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIMOUTEN; - } - else - { - /* Disable Clock Timeout */ - I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMOUTEN); - } -} - -/** - * @brief Enables or disables I2C Extended Clock Timeout (SCL cumulative Timeout detection). - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx Extended clock Timeout. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Clock Timeout */ - I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TEXTEN; - } - else - { - /* Disable Clock Timeout */ - I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TEXTEN); - } -} - -/** - * @brief Enables or disables I2C Idle Clock Timeout (Bus idle SCL and SDA - * high detection). - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx Idle clock Timeout. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Clock Timeout */ - I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIDLE; - } - else - { - /* Disable Clock Timeout */ - I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIDLE); - } -} - -/** - * @brief Configures the I2C Bus Timeout A (SCL Timeout when TIDLE = 0 or Bus - * idle SCL and SDA high when TIDLE = 1). - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Timeout: specifies the TimeoutA to be programmed. - * @retval None - */ -void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_TIMEOUT(Timeout)); - - /* Get the old register value */ - tmpreg = I2Cx->TIMEOUTR; - - /* Reset I2Cx TIMEOUTA bit [11:0] */ - tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTA); - - /* Set I2Cx TIMEOUTA */ - tmpreg |= (uint32_t)((uint32_t)Timeout & I2C_TIMEOUTR_TIMEOUTA) ; - - /* Store the new register value */ - I2Cx->TIMEOUTR = tmpreg; -} - -/** - * @brief Configures the I2C Bus Timeout B (SCL cumulative Timeout). - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Timeout: specifies the TimeoutB to be programmed. - * @retval None - */ -void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_TIMEOUT(Timeout)); - - /* Get the old register value */ - tmpreg = I2Cx->TIMEOUTR; - - /* Reset I2Cx TIMEOUTB bit [11:0] */ - tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTB); - - /* Set I2Cx TIMEOUTB */ - tmpreg |= (uint32_t)(((uint32_t)Timeout << 16) & I2C_TIMEOUTR_TIMEOUTB) ; - - /* Store the new register value */ - I2Cx->TIMEOUTR = tmpreg; -} - -/** - * @brief Enables or disables I2C PEC calculation. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx PEC calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable PEC calculation */ - I2Cx->CR1 |= I2C_CR1_PECEN; - } - else - { - /* Disable PEC calculation */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PECEN); - } -} - -/** - * @brief Enables or disables I2C PEC transmission/reception request. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx PEC request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable PEC transmission/reception request */ - I2Cx->CR1 |= I2C_CR2_PECBYTE; - } - else - { - /* Disable PEC transmission/reception request */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR2_PECBYTE); - } -} - -/** - * @brief Returns the I2C PEC. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval The value of the PEC . - */ -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Return the slave matched address in the SR1 register */ - return (uint8_t)((uint32_t)I2Cx->PECR & I2C_PECR_PEC); -} - -/** - * @} - */ - - -/** @defgroup I2C_Group4 I2C registers management functions - * @brief I2C registers management functions - * -@verbatim - =============================================================================== - ##### I2C registers management functions ##### - =============================================================================== - [..] This section provides a functions that allow user the management of - I2C registers. - -@endverbatim - * @{ - */ - - /** - * @brief Reads the specified I2C register and returns its value. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_Register: specifies the register to read. - * This parameter can be one of the following values: - * @arg I2C_Register_CR1: CR1 register. - * @arg I2C_Register_CR2: CR2 register. - * @arg I2C_Register_OAR1: OAR1 register. - * @arg I2C_Register_OAR2: OAR2 register. - * @arg I2C_Register_TIMINGR: TIMING register. - * @arg I2C_Register_TIMEOUTR: TIMEOUTR register. - * @arg I2C_Register_ISR: ISR register. - * @arg I2C_Register_ICR: ICR register. - * @arg I2C_Register_PECR: PECR register. - * @arg I2C_Register_RXDR: RXDR register. - * @arg I2C_Register_TXDR: TXDR register. - * @retval The value of the read register. - */ -uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_REGISTER(I2C_Register)); - - tmp = (uint32_t)I2Cx; - tmp += I2C_Register; - - /* Return the selected register value */ - return (*(__IO uint32_t *) tmp); -} - -/** - * @} - */ - -/** @defgroup I2C_Group5 Data transfers management functions - * @brief Data transfers management functions - * -@verbatim - =============================================================================== - ##### Data transfers management functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to manage - the I2C data transfers. - - [..] The read access of the I2C_RXDR register can be done using - the I2C_ReceiveData() function and returns the received value. - Whereas a write access to the I2C_TXDR can be done using I2C_SendData() - function and stores the written data into TXDR. -@endverbatim - * @{ - */ - -/** - * @brief Sends a data byte through the I2Cx peripheral. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Data: Byte to be transmitted.. - * @retval None - */ -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Write in the DR register the data to be sent */ - I2Cx->TXDR = (uint8_t)Data; -} - -/** - * @brief Returns the most recent received data by the I2Cx peripheral. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval The value of the received data. - */ -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Return the data in the DR register */ - return (uint8_t)I2Cx->RXDR; -} - -/** - * @} - */ - - -/** @defgroup I2C_Group6 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - ##### DMA transfers management functions ##### - =============================================================================== - [..] This section provides two functions that can be used only in DMA mode. - [..] In DMA Mode, the I2C communication can be managed by 2 DMA Channel - requests: - (#) I2C_DMAReq_Tx: specifies the Tx buffer DMA transfer request. - (#) I2C_DMAReq_Rx: specifies the Rx buffer DMA transfer request. - [..] In this Mode it is advised to use the following function: - (+) I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState); -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the I2C DMA interface. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_DMAReq: specifies the I2C DMA transfer request to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg I2C_DMAReq_Tx: Tx DMA transfer request - * @arg I2C_DMAReq_Rx: Rx DMA transfer request - * @param NewState: new state of the selected I2C DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_I2C_DMA_REQ(I2C_DMAReq)); - - if (NewState != DISABLE) - { - /* Enable the selected I2C DMA requests */ - I2Cx->CR1 |= I2C_DMAReq; - } - else - { - /* Disable the selected I2C DMA requests */ - I2Cx->CR1 &= (uint32_t)~I2C_DMAReq; - } -} -/** - * @} - */ - - -/** @defgroup I2C_Group7 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - [..] This section provides functions allowing to configure the I2C Interrupts - sources and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode(refer I2C_Group6) . - - *** Polling Mode *** - ==================== - [..] In Polling Mode, the I2C communication can be managed by 15 flags: - (#) I2C_FLAG_TXE: to indicate the status of Transmit data register empty flag. - (#) I2C_FLAG_TXIS: to indicate the status of Transmit interrupt status flag . - (#) I2C_FLAG_RXNE: to indicate the status of Receive data register not empty flag. - (#) I2C_FLAG_ADDR: to indicate the status of Address matched flag (slave mode). - (#) I2C_FLAG_NACKF: to indicate the status of NACK received flag. - (#) I2C_FLAG_STOPF: to indicate the status of STOP detection flag. - (#) I2C_FLAG_TC: to indicate the status of Transfer complete flag(master mode). - (#) I2C_FLAG_TCR: to indicate the status of Transfer complete reload flag. - (#) I2C_FLAG_BERR: to indicate the status of Bus error flag. - (#) I2C_FLAG_ARLO: to indicate the status of Arbitration lost flag. - (#) I2C_FLAG_OVR: to indicate the status of Overrun/Underrun flag. - (#) I2C_FLAG_PECERR: to indicate the status of PEC error in reception flag. - (#) I2C_FLAG_TIMEOUT: to indicate the status of Timeout or Tlow detection flag. - (#) I2C_FLAG_ALERT: to indicate the status of SMBus Alert flag. - (#) I2C_FLAG_BUSY: to indicate the status of Bus busy flag. - - [..] In this Mode it is advised to use the following functions: - (+) FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); - (+) void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); - - [..] - (@)Do not use the BUSY flag to handle each data transmission or reception.It is - better to use the TXIS and RXNE flags instead. - - *** Interrupt Mode *** - ====================== - [..] In Interrupt Mode, the I2C communication can be managed by 7 interrupt sources - and 15 pending bits: - [..] Interrupt Source: - (#) I2C_IT_ERRI: specifies the interrupt source for the Error interrupt. - (#) I2C_IT_TCI: specifies the interrupt source for the Transfer Complete interrupt. - (#) I2C_IT_STOPI: specifies the interrupt source for the Stop Detection interrupt. - (#) I2C_IT_NACKI: specifies the interrupt source for the Not Acknowledge received interrupt. - (#) I2C_IT_ADDRI: specifies the interrupt source for the Address Match interrupt. - (#) I2C_IT_RXI: specifies the interrupt source for the RX interrupt. - (#) I2C_IT_TXI: specifies the interrupt source for the TX interrupt. - - [..] Pending Bits: - (#) I2C_IT_TXIS: to indicate the status of Transmit interrupt status flag. - (#) I2C_IT_RXNE: to indicate the status of Receive data register not empty flag. - (#) I2C_IT_ADDR: to indicate the status of Address matched flag (slave mode). - (#) I2C_IT_NACKF: to indicate the status of NACK received flag. - (#) I2C_IT_STOPF: to indicate the status of STOP detection flag. - (#) I2C_IT_TC: to indicate the status of Transfer complete flag (master mode). - (#) I2C_IT_TCR: to indicate the status of Transfer complete reload flag. - (#) I2C_IT_BERR: to indicate the status of Bus error flag. - (#) I2C_IT_ARLO: to indicate the status of Arbitration lost flag. - (#) I2C_IT_OVR: to indicate the status of Overrun/Underrun flag. - (#) I2C_IT_PECERR: to indicate the status of PEC error in reception flag. - (#) I2C_IT_TIMEOUT: to indicate the status of Timeout or Tlow detection flag. - (#) I2C_IT_ALERT: to indicate the status of SMBus Alert flag. - - [..] In this Mode it is advised to use the following functions: - (+) void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); - (+) ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified I2C flag is set or not. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg I2C_FLAG_TXE: Transmit data register empty - * @arg I2C_FLAG_TXIS: Transmit interrupt status - * @arg I2C_FLAG_RXNE: Receive data register not empty - * @arg I2C_FLAG_ADDR: Address matched (slave mode) - * @arg I2C_FLAG_NACKF: NACK received flag - * @arg I2C_FLAG_STOPF: STOP detection flag - * @arg I2C_FLAG_TC: Transfer complete (master mode) - * @arg I2C_FLAG_TCR: Transfer complete reload - * @arg I2C_FLAG_BERR: Bus error - * @arg I2C_FLAG_ARLO: Arbitration lost - * @arg I2C_FLAG_OVR: Overrun/Underrun - * @arg I2C_FLAG_PECERR: PEC error in reception - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag - * @arg I2C_FLAG_ALERT: SMBus Alert - * @arg I2C_FLAG_BUSY: Bus busy - * @retval The new state of I2C_FLAG (SET or RESET). - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - uint32_t tmpreg = 0; - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); - - /* Get the ISR register value */ - tmpreg = I2Cx->ISR; - - /* Get flag status */ - tmpreg &= I2C_FLAG; - - if(tmpreg != 0) - { - /* I2C_FLAG is set */ - bitstatus = SET; - } - else - { - /* I2C_FLAG is reset */ - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the I2Cx's pending flags. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg I2C_FLAG_ADDR: Address matched (slave mode) - * @arg I2C_FLAG_NACKF: NACK received flag - * @arg I2C_FLAG_STOPF: STOP detection flag - * @arg I2C_FLAG_BERR: Bus error - * @arg I2C_FLAG_ARLO: Arbitration lost - * @arg I2C_FLAG_OVR: Overrun/Underrun - * @arg I2C_FLAG_PECERR: PEC error in reception - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag - * @arg I2C_FLAG_ALERT: SMBus Alert - * @retval The new state of I2C_FLAG (SET or RESET). - */ -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); - - /* Clear the selected flag */ - I2Cx->ICR = I2C_FLAG; - } - -/** - * @brief Checks whether the specified I2C interrupt has occurred or not. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt source to check. - * This parameter can be one of the following values: - * @arg I2C_IT_TXIS: Transmit interrupt status - * @arg I2C_IT_RXNE: Receive data register not empty - * @arg I2C_IT_ADDR: Address matched (slave mode) - * @arg I2C_IT_NACKF: NACK received flag - * @arg I2C_IT_STOPF: STOP detection flag - * @arg I2C_IT_TC: Transfer complete (master mode) - * @arg I2C_IT_TCR: Transfer complete reload - * @arg I2C_IT_BERR: Bus error - * @arg I2C_IT_ARLO: Arbitration lost - * @arg I2C_IT_OVR: Overrun/Underrun - * @arg I2C_IT_PECERR: PEC error in reception - * @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag - * @arg I2C_IT_ALERT: SMBus Alert - * @retval The new state of I2C_IT (SET or RESET). - */ -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - uint32_t tmpreg = 0; - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_IT(I2C_IT)); - - /* Check if the interrupt source is enabled or not */ - /* If Error interrupt */ - if((uint32_t)(I2C_IT & ERROR_IT_MASK)) - { - enablestatus = (uint32_t)((I2C_CR1_ERRIE) & (I2Cx->CR1)); - } - /* If TC interrupt */ - else if((uint32_t)(I2C_IT & TC_IT_MASK)) - { - enablestatus = (uint32_t)((I2C_CR1_TCIE) & (I2Cx->CR1)); - } - else - { - enablestatus = (uint32_t)((I2C_IT) & (I2Cx->CR1)); - } - - /* Get the ISR register value */ - tmpreg = I2Cx->ISR; - - /* Get flag status */ - tmpreg &= I2C_IT; - - /* Check the status of the specified I2C flag */ - if((tmpreg != RESET) && enablestatus) - { - /* I2C_IT is set */ - bitstatus = SET; - } - else - { - /* I2C_IT is reset */ - bitstatus = RESET; - } - - /* Return the I2C_IT status */ - return bitstatus; -} - -/** - * @brief Clears the I2Cx's interrupt pending bits. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg I2C_IT_ADDR: Address matched (slave mode) - * @arg I2C_IT_NACKF: NACK received flag - * @arg I2C_IT_STOPF: STOP detection flag - * @arg I2C_IT_BERR: Bus error - * @arg I2C_IT_ARLO: Arbitration lost - * @arg I2C_IT_OVR: Overrun/Underrun - * @arg I2C_IT_PECERR: PEC error in reception - * @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag - * @arg I2C_IT_ALERT: SMBus Alert - * @retval The new state of I2C_IT (SET or RESET). - */ -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_IT(I2C_IT)); - - /* Clear the selected flag */ - I2Cx->ICR = I2C_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_i2c.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,487 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_i2c.h - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file contains all the functions prototypes for the I2C firmware - * library. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F30x_I2C_H -#define __STM32F30x_I2C_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief I2C Init structure definition - */ - -typedef struct -{ - uint32_t I2C_Timing; /*!< Specifies the I2C_TIMINGR_register value. - This parameter calculated by referring to I2C initialization - section in Reference manual*/ - - uint32_t I2C_AnalogFilter; /*!< Enables or disables analog noise filter. - This parameter can be a value of @ref I2C_Analog_Filter */ - - uint32_t I2C_DigitalFilter; /*!< Configures the digital noise filter. - This parameter can be a number between 0x00 and 0x0F */ - - uint32_t I2C_Mode; /*!< Specifies the I2C mode. - This parameter can be a value of @ref I2C_mode */ - - uint32_t I2C_OwnAddress1; /*!< Specifies the device own address 1. - This parameter can be a 7-bit or 10-bit address */ - - uint32_t I2C_Ack; /*!< Enables or disables the acknowledgement. - This parameter can be a value of @ref I2C_acknowledgement */ - - uint32_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. - This parameter can be a value of @ref I2C_acknowledged_address */ -}I2C_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - - -/** @defgroup I2C_Exported_Constants - * @{ - */ - -#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ - ((PERIPH) == I2C2)) - -/** @defgroup I2C_Analog_Filter - * @{ - */ - -#define I2C_AnalogFilter_Enable ((uint32_t)0x00000000) -#define I2C_AnalogFilter_Disable I2C_CR1_ANFOFF - -#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_AnalogFilter_Enable) || \ - ((FILTER) == I2C_AnalogFilter_Disable)) -/** - * @} - */ - -/** @defgroup I2C_Digital_Filter - * @{ - */ - -#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F) -/** - * @} - */ - -/** @defgroup I2C_mode - * @{ - */ - -#define I2C_Mode_I2C ((uint32_t)0x00000000) -#define I2C_Mode_SMBusDevice I2C_CR1_SMBDEN -#define I2C_Mode_SMBusHost I2C_CR1_SMBHEN - -#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ - ((MODE) == I2C_Mode_SMBusDevice) || \ - ((MODE) == I2C_Mode_SMBusHost)) -/** - * @} - */ - -/** @defgroup I2C_acknowledgement - * @{ - */ - -#define I2C_Ack_Enable ((uint32_t)0x00000000) -#define I2C_Ack_Disable I2C_CR2_NACK - -#define IS_I2C_ACK(ACK) (((ACK) == I2C_Ack_Enable) || \ - ((ACK) == I2C_Ack_Disable)) -/** - * @} - */ - -/** @defgroup I2C_acknowledged_address - * @{ - */ - -#define I2C_AcknowledgedAddress_7bit ((uint32_t)0x00000000) -#define I2C_AcknowledgedAddress_10bit I2C_OAR1_OA1MODE - -#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ - ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) -/** - * @} - */ - -/** @defgroup I2C_own_address1 - * @{ - */ - -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) -/** - * @} - */ - -/** @defgroup I2C_transfer_direction - * @{ - */ - -#define I2C_Direction_Transmitter ((uint16_t)0x0000) -#define I2C_Direction_Receiver ((uint16_t)0x0400) - -#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ - ((DIRECTION) == I2C_Direction_Receiver)) -/** - * @} - */ - -/** @defgroup I2C_DMA_transfer_requests - * @{ - */ - -#define I2C_DMAReq_Tx I2C_CR1_TXDMAEN -#define I2C_DMAReq_Rx I2C_CR1_RXDMAEN - -#define IS_I2C_DMA_REQ(REQ) ((((REQ) & (uint32_t)0xFFFF3FFF) == 0x00) && ((REQ) != 0x00)) -/** - * @} - */ - -/** @defgroup I2C_slave_address - * @{ - */ - -#define IS_I2C_SLAVE_ADDRESS(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF) -/** - * @} - */ - - -/** @defgroup I2C_own_address2 - * @{ - */ - -#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) - -/** - * @} - */ - -/** @defgroup I2C_own_address2_mask - * @{ - */ - -#define I2C_OA2_NoMask ((uint8_t)0x00) -#define I2C_OA2_Mask01 ((uint8_t)0x01) -#define I2C_OA2_Mask02 ((uint8_t)0x02) -#define I2C_OA2_Mask03 ((uint8_t)0x03) -#define I2C_OA2_Mask04 ((uint8_t)0x04) -#define I2C_OA2_Mask05 ((uint8_t)0x05) -#define I2C_OA2_Mask06 ((uint8_t)0x06) -#define I2C_OA2_Mask07 ((uint8_t)0x07) - -#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NoMask) || \ - ((MASK) == I2C_OA2_Mask01) || \ - ((MASK) == I2C_OA2_Mask02) || \ - ((MASK) == I2C_OA2_Mask03) || \ - ((MASK) == I2C_OA2_Mask04) || \ - ((MASK) == I2C_OA2_Mask05) || \ - ((MASK) == I2C_OA2_Mask06) || \ - ((MASK) == I2C_OA2_Mask07)) - -/** - * @} - */ - -/** @defgroup I2C_timeout - * @{ - */ - -#define IS_I2C_TIMEOUT(TIMEOUT) ((TIMEOUT) <= (uint16_t)0x0FFF) - -/** - * @} - */ - -/** @defgroup I2C_registers - * @{ - */ - -#define I2C_Register_CR1 ((uint8_t)0x00) -#define I2C_Register_CR2 ((uint8_t)0x04) -#define I2C_Register_OAR1 ((uint8_t)0x08) -#define I2C_Register_OAR2 ((uint8_t)0x0C) -#define I2C_Register_TIMINGR ((uint8_t)0x10) -#define I2C_Register_TIMEOUTR ((uint8_t)0x14) -#define I2C_Register_ISR ((uint8_t)0x18) -#define I2C_Register_ICR ((uint8_t)0x1C) -#define I2C_Register_PECR ((uint8_t)0x20) -#define I2C_Register_RXDR ((uint8_t)0x24) -#define I2C_Register_TXDR ((uint8_t)0x28) - -#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ - ((REGISTER) == I2C_Register_CR2) || \ - ((REGISTER) == I2C_Register_OAR1) || \ - ((REGISTER) == I2C_Register_OAR2) || \ - ((REGISTER) == I2C_Register_TIMINGR) || \ - ((REGISTER) == I2C_Register_TIMEOUTR) || \ - ((REGISTER) == I2C_Register_ISR) || \ - ((REGISTER) == I2C_Register_ICR) || \ - ((REGISTER) == I2C_Register_PECR) || \ - ((REGISTER) == I2C_Register_RXDR) || \ - ((REGISTER) == I2C_Register_TXDR)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_ERRI I2C_CR1_ERRIE -#define I2C_IT_TCI I2C_CR1_TCIE -#define I2C_IT_STOPI I2C_CR1_STOPIE -#define I2C_IT_NACKI I2C_CR1_NACKIE -#define I2C_IT_ADDRI I2C_CR1_ADDRIE -#define I2C_IT_RXI I2C_CR1_RXIE -#define I2C_IT_TXI I2C_CR1_TXIE - -#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint32_t)0xFFFFFF01) == 0x00) && ((IT) != 0x00)) - -/** - * @} - */ - -/** @defgroup I2C_flags_definition - * @{ - */ - -#define I2C_FLAG_TXE I2C_ISR_TXE -#define I2C_FLAG_TXIS I2C_ISR_TXIS -#define I2C_FLAG_RXNE I2C_ISR_RXNE -#define I2C_FLAG_ADDR I2C_ISR_ADDR -#define I2C_FLAG_NACKF I2C_ISR_NACKF -#define I2C_FLAG_STOPF I2C_ISR_STOPF -#define I2C_FLAG_TC I2C_ISR_TC -#define I2C_FLAG_TCR I2C_ISR_TCR -#define I2C_FLAG_BERR I2C_ISR_BERR -#define I2C_FLAG_ARLO I2C_ISR_ARLO -#define I2C_FLAG_OVR I2C_ISR_OVR -#define I2C_FLAG_PECERR I2C_ISR_PECERR -#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT -#define I2C_FLAG_ALERT I2C_ISR_ALERT -#define I2C_FLAG_BUSY I2C_ISR_BUSY - -#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFF4000) == 0x00) && ((FLAG) != 0x00)) - -#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_TXIS) || \ - ((FLAG) == I2C_FLAG_RXNE) || ((FLAG) == I2C_FLAG_ADDR) || \ - ((FLAG) == I2C_FLAG_NACKF) || ((FLAG) == I2C_FLAG_STOPF) || \ - ((FLAG) == I2C_FLAG_TC) || ((FLAG) == I2C_FLAG_TCR) || \ - ((FLAG) == I2C_FLAG_BERR) || ((FLAG) == I2C_FLAG_ARLO) || \ - ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_PECERR) || \ - ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_ALERT) || \ - ((FLAG) == I2C_FLAG_BUSY)) - -/** - * @} - */ - - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_TXIS I2C_ISR_TXIS -#define I2C_IT_RXNE I2C_ISR_RXNE -#define I2C_IT_ADDR I2C_ISR_ADDR -#define I2C_IT_NACKF I2C_ISR_NACKF -#define I2C_IT_STOPF I2C_ISR_STOPF -#define I2C_IT_TC I2C_ISR_TC -#define I2C_IT_TCR I2C_ISR_TCR -#define I2C_IT_BERR I2C_ISR_BERR -#define I2C_IT_ARLO I2C_ISR_ARLO -#define I2C_IT_OVR I2C_ISR_OVR -#define I2C_IT_PECERR I2C_ISR_PECERR -#define I2C_IT_TIMEOUT I2C_ISR_TIMEOUT -#define I2C_IT_ALERT I2C_ISR_ALERT - -#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFFFFC001) == 0x00) && ((IT) != 0x00)) - -#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_TXIS) || ((IT) == I2C_IT_RXNE) || \ - ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_NACKF) || \ - ((IT) == I2C_IT_STOPF) || ((IT) == I2C_IT_TC) || \ - ((IT) == I2C_IT_TCR) || ((IT) == I2C_IT_BERR) || \ - ((IT) == I2C_IT_ARLO) || ((IT) == I2C_IT_OVR) || \ - ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_TIMEOUT) || \ - ((IT) == I2C_IT_ALERT)) - - -/** - * @} - */ - -/** @defgroup I2C_ReloadEndMode_definition - * @{ - */ - -#define I2C_Reload_Mode I2C_CR2_RELOAD -#define I2C_AutoEnd_Mode I2C_CR2_AUTOEND -#define I2C_SoftEnd_Mode ((uint32_t)0x00000000) - - -#define IS_RELOAD_END_MODE(MODE) (((MODE) == I2C_Reload_Mode) || \ - ((MODE) == I2C_AutoEnd_Mode) || \ - ((MODE) == I2C_SoftEnd_Mode)) - - -/** - * @} - */ - -/** @defgroup I2C_StartStopMode_definition - * @{ - */ - -#define I2C_No_StartStop ((uint32_t)0x00000000) -#define I2C_Generate_Stop I2C_CR2_STOP -#define I2C_Generate_Start_Read (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) -#define I2C_Generate_Start_Write I2C_CR2_START - - -#define IS_START_STOP_MODE(MODE) (((MODE) == I2C_Generate_Stop) || \ - ((MODE) == I2C_Generate_Start_Read) || \ - ((MODE) == I2C_Generate_Start_Write) || \ - ((MODE) == I2C_No_StartStop)) - - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - - -/* Initialization and Configuration functions *********************************/ -void I2C_DeInit(I2C_TypeDef* I2Cx); -void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx); -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState); -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask); -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address); -void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); - -/* Communications handling functions ******************************************/ -void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes); -void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction); -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); -uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx); -uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx); -void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode); - -/* SMBUS management functions ************************************************/ -void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout); -void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout); -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); - -/* I2C registers management functions *****************************************/ -uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); - -/* Data transfers management functions ****************************************/ -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); - -/* DMA transfers management functions *****************************************/ -void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); - - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F30x_I2C_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_iwdg.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,298 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_iwdg.c - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Independent watchdog (IWDG) peripheral: - * + Prescaler and Counter configuration - * + IWDG activation - * + Flag management - * - @verbatim - - =============================================================================== - ##### IWDG features ##### - =============================================================================== - [..] The IWDG can be started by either software or hardware (configurable - through option byte). - [..] The IWDG is clocked by its own dedicated low-speed clock (LSI) and - thus stays active even if the main clock fails. - Once the IWDG is started, the LSI is forced ON and cannot be disabled - (LSI cannot be disabled too), and the counter starts counting down from - the reset value of 0xFFF. When it reaches the end of count value (0x000) - a system reset is generated. - The IWDG counter should be reloaded at regular intervals to prevent - an MCU reset. - [..] The IWDG is implemented in the VDD voltage domain that is still functional - in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). - [..] IWDGRST flag in RCC_CSR register can be used to inform when a IWDG - reset occurs. - [..] Min-max timeout value @41KHz (LSI): ~0.1ms / ~25.5s - The IWDG timeout may vary due to LSI frequency dispersion. STM32F30x - devices provide the capability to measure the LSI frequency (LSI clock - connected internally to TIM16 CH1 input capture). The measured value - can be used to have an IWDG timeout with an acceptable accuracy. - For more information, please refer to the STM32F30x Reference manual. - - ##### How to use this driver ##### - =============================================================================== - [..] This driver allows to use IWDG peripheral with either window option enabled - or disabled. To do so follow one of the two procedures below. - (#) Window option is enabled: - (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used - in software mode (no need to enable the LSI, it will be enabled - by hardware). - (++) Enable write access to IWDG_PR and IWDG_RLR registers using - IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function. - (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function. - (++) Configure the IWDG counter value using IWDG_SetReload() function. - This value will be loaded in the IWDG counter each time the counter - is reloaded, then the IWDG will start counting down from this value. - (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function. - (++) Configure the IWDG refresh window using IWDG_SetWindowValue() function. - - (#) Window option is disabled: - (++) Enable write access to IWDG_PR and IWDG_RLR registers using - IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function. - (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function. - (++) Configure the IWDG counter value using IWDG_SetReload() function. - This value will be loaded in the IWDG counter each time the counter - is reloaded, then the IWDG will start counting down from this value. - (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function. - (++) reload the IWDG counter at regular intervals during normal operation - to prevent an MCU reset, using IWDG_ReloadCounter() function. - (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used - in software mode (no need to enable the LSI, it will be enabled - by hardware). - - @endverbatim - - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x_iwdg.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @defgroup IWDG - * @brief IWDG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* ---------------------- IWDG registers bit mask ----------------------------*/ -/* KR register bit mask */ -#define KR_KEY_RELOAD ((uint16_t)0xAAAA) -#define KR_KEY_ENABLE ((uint16_t)0xCCCC) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup IWDG_Private_Functions - * @{ - */ - -/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions - * @brief Prescaler and Counter configuration functions - * -@verbatim - =============================================================================== - ##### Prescaler and Counter configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. - * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. - * This parameter can be one of the following values: - * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers - * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers - * @retval None - */ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) -{ - /* Check the parameters */ - assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); - IWDG->KR = IWDG_WriteAccess; -} - -/** - * @brief Sets IWDG Prescaler value. - * @param IWDG_Prescaler: specifies the IWDG Prescaler value. - * This parameter can be one of the following values: - * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 - * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 - * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 - * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 - * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 - * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 - * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 - * @retval None - */ -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); - IWDG->PR = IWDG_Prescaler; -} - -/** - * @brief Sets IWDG Reload value. - * @param Reload: specifies the IWDG Reload value. - * This parameter must be a number between 0 and 0x0FFF. - * @retval None - */ -void IWDG_SetReload(uint16_t Reload) -{ - /* Check the parameters */ - assert_param(IS_IWDG_RELOAD(Reload)); - IWDG->RLR = Reload; -} - -/** - * @brief Reloads IWDG counter with value defined in the reload register - * (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_ReloadCounter(void) -{ - IWDG->KR = KR_KEY_RELOAD; -} - - -/** - * @brief Sets the IWDG window value. - * @param WindowValue: specifies the window value to be compared to the downcounter. - * @retval None - */ -void IWDG_SetWindowValue(uint16_t WindowValue) -{ - /* Check the parameters */ - assert_param(IS_IWDG_WINDOW_VALUE(WindowValue)); - IWDG->WINR = WindowValue; -} - -/** - * @} - */ - -/** @defgroup IWDG_Group2 IWDG activation function - * @brief IWDG activation function - * -@verbatim - =============================================================================== - ##### IWDG activation function ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_Enable(void) -{ - IWDG->KR = KR_KEY_ENABLE; -} - -/** - * @} - */ - -/** @defgroup IWDG_Group3 Flag management function - * @brief Flag management function - * -@verbatim - =============================================================================== - ##### Flag management function ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified IWDG flag is set or not. - * @param IWDG_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg IWDG_FLAG_PVU: Prescaler Value Update on going - * @arg IWDG_FLAG_RVU: Reload Value Update on going - * @arg IWDG_FLAG_WVU: Counter Window Value Update on going - * @retval The new state of IWDG_FLAG (SET or RESET). - */ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_IWDG_FLAG(IWDG_FLAG)); - if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_iwdg.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,163 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_iwdg.h - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file contains all the functions prototypes for the IWDG - * firmware library. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F30x_IWDG_H -#define __STM32F30x_IWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup IWDG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup IWDG_Exported_Constants - * @{ - */ - -/** @defgroup IWDG_WriteAccess - * @{ - */ - -#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) -#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) -#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ - ((ACCESS) == IWDG_WriteAccess_Disable)) -/** - * @} - */ - -/** @defgroup IWDG_prescaler - * @{ - */ - -#define IWDG_Prescaler_4 ((uint8_t)0x00) -#define IWDG_Prescaler_8 ((uint8_t)0x01) -#define IWDG_Prescaler_16 ((uint8_t)0x02) -#define IWDG_Prescaler_32 ((uint8_t)0x03) -#define IWDG_Prescaler_64 ((uint8_t)0x04) -#define IWDG_Prescaler_128 ((uint8_t)0x05) -#define IWDG_Prescaler_256 ((uint8_t)0x06) -#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ - ((PRESCALER) == IWDG_Prescaler_8) || \ - ((PRESCALER) == IWDG_Prescaler_16) || \ - ((PRESCALER) == IWDG_Prescaler_32) || \ - ((PRESCALER) == IWDG_Prescaler_64) || \ - ((PRESCALER) == IWDG_Prescaler_128)|| \ - ((PRESCALER) == IWDG_Prescaler_256)) -/** - * @} - */ - -/** @defgroup IWDG_Flag - * @{ - */ - -#define IWDG_FLAG_PVU ((uint16_t)0x0001) -#define IWDG_FLAG_RVU ((uint16_t)0x0002) -#define IWDG_FLAG_WVU ((uint16_t)0x0002) -#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU) || \ - ((FLAG) == IWDG_FLAG_WVU)) -/** - * @} - */ - -/** @defgroup IWDG_Reload_Value - * @{ - */ -#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) - -/** - * @} - */ - -/** @defgroup IWDG_CounterWindow_Value - * @{ - */ -#define IS_IWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Prescaler and Counter configuration functions ******************************/ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); -void IWDG_SetReload(uint16_t Reload); -void IWDG_ReloadCounter(void); -void IWDG_SetWindowValue(uint16_t WindowValue); - -/* IWDG activation function ***************************************************/ -void IWDG_Enable(void); - -/* Flag management function ***************************************************/ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F30x_IWDG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_misc.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,240 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_misc.c - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file provides all the miscellaneous firmware functions (add-on - * to CMSIS functions). - * - @verbatim - - =============================================================================== - ##### How to configure Interrupts using driver ##### - =============================================================================== - [..] This section provide functions allowing to configure the NVIC interrupts - (IRQ). The Cortex-M4 exceptions are managed by CMSIS functions. - (#) Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig() - function according to the following table. - The table below gives the allowed values of the pre-emption priority - and subpriority according to the Priority Grouping configuration - performed by NVIC_PriorityGroupConfig function. - - (#) Enable and Configure the priority of the selected IRQ Channels. - [..] - (@) When the NVIC_PriorityGroup_0 is selected, it will no any nested interrupt, - the IRQ priority will be managed only by subpriority. - The sub-priority is only used to sort pending exception priorities, - and does not affect active exceptions. - (@) Lower priority values gives higher priority. - (@) Priority Order: - (#@) Lowest Preemption priority. - (#@) Lowest Subpriority. - (#@) Lowest hardware priority (IRQn position). - - @endverbatim - - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x_misc.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @defgroup MISC - * @brief MISC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup MISC_Private_Functions - * @{ - */ - -/** - * @brief Configures the priority grouping: pre-emption priority and subpriority. - * @param NVIC_PriorityGroup: specifies the priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority. - * 4 bits for subpriority. - * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority. - * 3 bits for subpriority. - * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority. - * 2 bits for subpriority. - * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority. - * 1 bits for subpriority. - * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority. - * 0 bits for subpriority. - * @note When NVIC_PriorityGroup_0 is selected, it will no be any nested - * interrupt. This interrupts priority is managed only with subpriority. - * @retval None - */ -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); - - /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ - SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; -} - -/** - * @brief Initializes the NVIC peripheral according to the specified - * parameters in the NVIC_InitStruct. - * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() - * function should be called before. - * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains - * the configuration information for the specified NVIC peripheral. - * @retval None - */ -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) -{ - uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); - assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); - assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); - - if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) - { - /* Compute the Corresponding IRQ Priority --------------------------------*/ - tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; - tmppre = (0x4 - tmppriority); - tmpsub = tmpsub >> tmppriority; - - tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; - tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; - tmppriority = tmppriority << 0x04; - - NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; - - /* Enable the Selected IRQ Channels --------------------------------------*/ - NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } - else - { - /* Disable the Selected IRQ Channels -------------------------------------*/ - NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } -} - -/** - * @brief Sets the vector table location and Offset. - * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. - * This parameter can be one of the following values: - * @arg NVIC_VectTab_RAM - * @arg NVIC_VectTab_FLASH - * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200. - * @retval None - */ -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) -{ - /* Check the parameters */ - assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); - assert_param(IS_NVIC_OFFSET(Offset)); - - SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); -} - -/** - * @brief Selects the condition for the system to enter low power mode. - * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. - * This parameter can be one of the following values: - * @arg NVIC_LP_SEVONPEND - * @arg NVIC_LP_SLEEPDEEP - * @arg NVIC_LP_SLEEPONEXIT - * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_NVIC_LP(LowPowerMode)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - SCB->SCR |= LowPowerMode; - } - else - { - SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); - } -} - -/** - * @brief Configures the SysTick clock source. - * @param SysTick_CLKSource: specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); - if (SysTick_CLKSource == SysTick_CLKSource_HCLK) - { - SysTick->CTRL |= SysTick_CLKSource_HCLK; - } - else - { - SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_misc.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,214 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_misc.h - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file contains all the functions prototypes for the miscellaneous - * firmware library functions (add-on to CMSIS functions). - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F30x_MISC_H -#define __STM32F30x_MISC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup MISC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief NVIC Init Structure definition - */ - -typedef struct -{ - uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. - This parameter can be a value of @ref IRQn_Type (For - the complete STM32 Devices IRQ Channels list, please - refer to stm32f30x.h file) */ - - uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel - specified in NVIC_IRQChannel. This parameter can be a value - between 0 and 15. - A lower priority value indicates a higher priority */ - - - uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified - in NVIC_IRQChannel. This parameter can be a value - between 0 and 15. - A lower priority value indicates a higher priority */ - - FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel - will be enabled or disabled. - This parameter can be set either to ENABLE or DISABLE */ -} NVIC_InitTypeDef; - -/** - * -@verbatim - The table below gives the allowed values of the pre-emption priority and subpriority according - to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function - ============================================================================================================================ - NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description - ============================================================================================================================ - NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority - | | | 4 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority - | | | 3 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority - | | | 2 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority - | | | 1 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority - | | | 0 bits for subpriority - ============================================================================================================================ -@endverbatim -*/ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup MISC_Exported_Constants - * @{ - */ - -/** @defgroup MISC_Vector_Table_Base - * @{ - */ - -#define NVIC_VectTab_RAM ((uint32_t)0x20000000) -#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) -#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ - ((VECTTAB) == NVIC_VectTab_FLASH)) -/** - * @} - */ - -/** @defgroup MISC_System_Low_Power - * @{ - */ - -#define NVIC_LP_SEVONPEND ((uint8_t)0x10) -#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) -#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) -#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ - ((LP) == NVIC_LP_SLEEPDEEP) || \ - ((LP) == NVIC_LP_SLEEPONEXIT)) -/** - * @} - */ - -/** @defgroup MISC_Preemption_Priority_Group - * @{ - */ - -#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ - -#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ - ((GROUP) == NVIC_PriorityGroup_1) || \ - ((GROUP) == NVIC_PriorityGroup_2) || \ - ((GROUP) == NVIC_PriorityGroup_3) || \ - ((GROUP) == NVIC_PriorityGroup_4)) - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) - -/** - * @} - */ - -/** @defgroup MISC_SysTick_clock_source - */ - -#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) -#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ - ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F30x_MISC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_opamp.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,585 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_opamp.c - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the operational amplifiers (OPAMP1,...OPAMP4) peripheral: - * + OPAMP Configuration - * + OPAMP calibration - * - @verbatim - - ============================================================================== - ##### OPAMP Peripheral Features ##### - ============================================================================== - - [..] - The device integrates 4 operational amplifiers OPAMP1, OPAMP2, OPAMP3 and OPAMP4: - - (+) The OPAMPs non inverting input can be selected among the list shown by - table below. - - (+) The OPAMPs inverting input can be selected among the list shown by - table below. - - (+) The OPAMPs outputs can be internally connected to the inverting input - (follower mode) - (+) The OPAMPs outputs can be internally connected to resistor feedback - output (Programmable Gain Amplifier mode) - - (+) The OPAMPs outputs can be internally connected to ADC - - (+) The OPAMPs can be calibrated to compensate the offset compensation - - (+) Timer-controlled Mux for automatic switch of inverting and - non-inverting input - - OPAMPs inverting/non-inverting inputs: - +--------------------------------------------------------------+ - | | | OPAMP1 | OPAMP2 | OPAMP3 | OPAMP4 | - |-----------------|--------|--------|--------|--------|--------| - | | PGA | OK | OK | OK | OK | - | Inverting Input | Vout | OK | OK | OK | OK | - | | IO1 | PC5 | PC5 | PB10 | PB10 | - | | IO2 | PA3 | PA5 | PB2 | PD8 | - |-----------------|--------|--------|--------|--------|--------| - | | IO1 | PA7 | PD14 | PB13 | PD11 | - | Non Inverting | IO2 | PA5 | PB14 | PA5 | PB11 | - | Input | IO3 | PA3 | PB0 | PA1 | PA4 | - | | IO4 | PA1 | PA7 | PB0 | PB13 | - +--------------------------------------------------------------+ - - ##### How to use this driver ##### - ============================================================================== - [..] - This driver provides functions to configure and program the OPAMP - of all STM32F30x devices. - - To use the OPAMP, perform the following steps: - - (#) Enable the SYSCFG APB clock to get write access to OPAMP - register using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - - (#) Configure the OPAMP input in analog mode using GPIO_Init() - - (#) Configure the OPAMP using OPAMP_Init() function: - (++) Select the inverting input - (++) Select the non-inverting inverting input - - (#) Enable the OPAMP using OPAMP_Cmd() function - - @endverbatim - - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x_opamp.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @defgroup OPAMP - * @brief OPAMP driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define OPAMP_CSR_DEFAULT_MASK ((uint32_t)0xFFFFFF93) -#define OPAMP_CSR_TIMERMUX_MASK ((uint32_t)0xFFFFF8FF) -#define OPAMP_CSR_TRIMMING_MASK ((uint32_t)0x0000001F) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup OPAMP_Private_Functions - * @{ - */ - -/** @defgroup OPAMP_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes OPAMP peripheral registers to their default reset values. - * @note Deinitialization can't be performed if the OPAMP configuration is locked. - * To unlock the configuration, perform a system reset. - * @param OPAMP_Selection: the selected OPAMP. - * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4 - * to select the OPAMP peripheral. - * @param None - * @retval None - */ -void OPAMP_DeInit(uint32_t OPAMP_Selection) -{ - /*!< Set OPAMP_CSR register to reset value */ - *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = ((uint32_t)0x00000000); -} - -/** - * @brief Initializes the OPAMP peripheral according to the specified parameters - * in OPAMP_InitStruct - * @note If the selected OPAMP is locked, initialization can't be performed. - * To unlock the configuration, perform a system reset. - * @param OPAMP_Selection: the selected OPAMP. - * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4 - * to select the OPAMP peripheral. - * @param OPAMP_InitStruct: pointer to an OPAMP_InitTypeDef structure that contains - * the configuration information for the specified OPAMP peripheral. - * - OPAMP_InvertingInput specifies the inverting input of OPAMP - * - OPAMP_NonInvertingInput specifies the non inverting input of OPAMP - * @retval None - */ -void OPAMP_Init(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection)); - assert_param(IS_OPAMP_INVERTING_INPUT(OPAMP_InitStruct->OPAMP_InvertingInput)); - assert_param(IS_OPAMP_NONINVERTING_INPUT(OPAMP_InitStruct->OPAMP_NonInvertingInput)); - - /*!< Get the OPAMPx_CSR register value */ - tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection); - - /*!< Clear the inverting and non inverting bits selection bits */ - tmpreg &= (uint32_t) (OPAMP_CSR_DEFAULT_MASK); - - /*!< Configure OPAMP: inverting and non inverting inputs */ - tmpreg |= (uint32_t)(OPAMP_InitStruct->OPAMP_InvertingInput | OPAMP_InitStruct->OPAMP_NonInvertingInput); - - /*!< Write to OPAMPx_CSR register */ - *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = tmpreg; -} - -/** - * @brief Fills each OPAMP_InitStruct member with its default value. - * @param OPAMP_InitStruct: pointer to an OPAMP_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void OPAMP_StructInit(OPAMP_InitTypeDef* OPAMP_InitStruct) -{ - OPAMP_InitStruct->OPAMP_NonInvertingInput = OPAMP_NonInvertingInput_IO1; - OPAMP_InitStruct->OPAMP_InvertingInput = OPAMP_InvertingInput_IO1; -} - -/** - * @brief Configure the feedback resistor gain. - * @note If the selected OPAMP is locked, gain configuration can't be performed. - * To unlock the configuration, perform a system reset. - * @param OPAMP_Selection: the selected OPAMP. - * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4 - * to select the OPAMP peripheral. - * @param NewState: new state of the OPAMP peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void OPAMP_PGAConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_PGAGain, uint32_t OPAMP_PGAConnect) -{ - /* Check the parameters */ - assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection)); - assert_param(IS_OPAMP_PGAGAIN(OPAMP_PGAGain)); - assert_param(IS_OPAMP_PGACONNECT(OPAMP_PGAConnect)); - - /* Reset the configuration bits */ - *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_PGGAIN); - - /* Set the new configuration */ - *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_PGAGain | OPAMP_PGAConnect); -} - -/** - * @brief Configure the OPAMP's internal reference. - * @note This feature is used when calibration enabled or OPAMP's reference - * connected to the non inverting input. - * @note If the selected OPAMP is locked, Vref configuration can't be performed. - * To unlock the configuration, perform a system reset. - * @param OPAMP_Selection: the selected OPAMP. - * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4 - * to select the OPAMP peripheral. - * @param OPAMP_Vref: This parameter can be: - * OPAMP_Vref_3VDDA: OPMAP Vref = 3.3% VDDA - * OPAMP_Vref_10VDDA: OPMAP Vref = 10% VDDA - * OPAMP_Vref_50VDDA: OPMAP Vref = 50% VDDA - * OPAMP_Vref_90VDDA: OPMAP Vref = 90% VDDA - * @retval None - */ -void OPAMP_VrefConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Vref) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection)); - assert_param(IS_OPAMP_VREF(OPAMP_Vref)); - - /*!< Get the OPAMPx_CSR register value */ - tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection); - - /*!< Clear the CALSEL bits */ - tmpreg &= (uint32_t) (~OPAMP_CSR_CALSEL); - - /*!< Configure OPAMP reference */ - tmpreg |= (uint32_t)(OPAMP_Vref); - - /*!< Write to OPAMPx_CSR register */ - *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = tmpreg; -} - -/** - * @brief Connnect the internal reference to the OPAMP's non inverting input. - * @note If the selected OPAMP is locked, Vref configuration can't be performed. - * To unlock the configuration, perform a system reset. - * @param OPAMP_Selection: the selected OPAMP. - * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4 - * to select the OPAMP peripheral. - * @param NewState: new state of the OPAMP peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void OPAMP_VrefConnectNonInvertingInput(uint32_t OPAMP_Selection, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Connnect the internal reference to the OPAMP's non inverting input */ - *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_FORCEVP); - } - else - { - /* Disconnnect the internal reference to the OPAMP's non inverting input */ - *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_FORCEVP); - } -} - -/** - * @brief Enables or disables connecting the OPAMP's internal reference to ADC. - * @note If the selected OPAMP is locked, Vref connection can't be performed. - * To unlock the configuration, perform a system reset. - * @param NewState: new state of the Vrefint output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void OPAMP_VrefConnectADCCmd(uint32_t OPAMP_Selection, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable output internal reference */ - *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_TSTREF); - } - else - { - /* Disable output internal reference */ - *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_TSTREF); - } -} - -/** - * @brief Configure the OPAMP peripheral (secondary inputs) for timer-controlled - * mux mode according to the specified parameters in OPAMP_InitStruct. - * @note If the selected OPAMP is locked, timer-controlled mux configuration - * can't be performed. - * To unlock the configuration, perform a system reset. - * @param OPAMP_Selection: the selected OPAMP. - * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4 - * to select the OPAMP peripheral. - * @param OPAMP_InitStruct: pointer to an OPAMP_InitTypeDef structure that contains - * the configuration information for the specified OPAMP peripheral. - * - OPAMP_InvertingInput specifies the inverting input of OPAMP - * - OPAMP_NonInvertingInput specifies the non inverting input of OPAMP - * @note PGA and Vout can't be selected as seconadry inverting input. - * @retval None - */ -void OPAMP_TimerControlledMuxConfig(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection)); - assert_param(IS_OPAMP_SECONDARY_INVINPUT(OPAMP_InitStruct->OPAMP_InvertingInput)); - assert_param(IS_OPAMP_NONINVERTING_INPUT(OPAMP_InitStruct->OPAMP_NonInvertingInput)); - - /*!< Get the OPAMPx_CSR register value */ - tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection); - - /*!< Clear the secondary inverting bit, secondary non inverting bit and TCMEN bits */ - tmpreg &= (uint32_t) (OPAMP_CSR_TIMERMUX_MASK); - - /*!< Configure OPAMP: secondary inverting and non inverting inputs */ - tmpreg |= (uint32_t)((uint32_t)(OPAMP_InitStruct->OPAMP_InvertingInput<<3) | (uint32_t)(OPAMP_InitStruct->OPAMP_NonInvertingInput<<7)); - - /*!< Write to OPAMPx_CSR register */ - *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = tmpreg; -} - -/** - * @brief Enable or disable the timer-controlled mux mode. - * @note If the selected OPAMP is locked, enable/disable can't be performed. - * To unlock the configuration, perform a system reset. - * @param OPAMP_Selection: the selected OPAMP. - * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4 - * to select the OPAMP peripheral. - * @param NewState: new state of the OPAMP peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void OPAMP_TimerControlledMuxCmd(uint32_t OPAMP_Selection, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the timer-controlled Mux mode */ - *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_TCMEN); - } - else - { - /* Disable the timer-controlled Mux mode */ - *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_TCMEN); - } -} - -/** - * @brief Enable or disable the OPAMP peripheral. - * @note If the selected OPAMP is locked, enable/disable can't be performed. - * To unlock the configuration, perform a system reset. - * @param OPAMP_Selection: the selected OPAMP. - * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4 - * to select the OPAMP peripheral. - * @param NewState: new state of the OPAMP peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected OPAMPx peripheral */ - *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_OPAMPxEN); - } - else - { - /* Disable the selected OPAMPx peripheral */ - *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_OPAMPxEN); - } -} - -/** - * @brief Return the output level (high or low) during calibration of the selected OPAMP. - * @param OPAMP_Selection: the selected OPAMP. - * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4 - * to select the OPAMP peripheral. - * - OPAMP output is low when the non-inverting input is at a lower - * voltage than the inverting input - * - OPAMP output is high when the non-inverting input is at a higher - * voltage than the inverting input - * @note OPAMP ouput level is provided only during calibration phase. - * @retval Returns the selected OPAMP output level: low or high. - * - */ -uint32_t OPAMP_GetOutputLevel(uint32_t OPAMP_Selection) -{ - uint32_t opampout = 0x0; - - /* Check the parameters */ - assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection)); - - /* Check if selected OPAMP output is high */ - if ((*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) & (OPAMP_CSR_OUTCAL)) != 0) - { - opampout = OPAMP_OutputLevel_High; - } - else - { - opampout = OPAMP_OutputLevel_Low; - } - - /* Return the OPAMP output level */ - return (uint32_t)(opampout); -} - -/** - * @brief Select the trimming mode. - * @param OffsetTrimming: the selected offset trimming mode. - * This parameter can be one of the following values: - * @arg OPAMP_Trimming_Factory: factory trimming values are used for offset - * calibration - * @arg OPAMP_Trimming_User: user trimming values are used for offset - * calibration - * @note When OffsetTrimming_User is selected, use OPAMP_OffsetTrimConfig() - * function or OPAMP_OffsetTrimLowPowerConfig() function to adjust - * trimming value. - * @retval None - */ -void OPAMP_OffsetTrimModeSelect(uint32_t OPAMP_Selection, uint32_t OPAMP_Trimming) -{ - /* Check the parameters */ - assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection)); - assert_param(IS_OPAMP_TRIMMING(OPAMP_Trimming)); - - /* Reset USERTRIM bit */ - *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (~(uint32_t) (OPAMP_CSR_USERTRIM)); - - /* Select trimming mode */ - *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= OPAMP_Trimming; -} - -/** - * @brief Configure the trimming value of the OPAMP. - * @param OPAMP_Selection: the selected OPAMP. - * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4 - * to select the OPAMP peripheral. - * @param OPAMP_Input: the selected OPAMP input. - * This parameter can be one of the following values: - * @arg OPAMP_Input_Inverting: Inverting input is selected to configure the trimming value - * @arg OPAMP_Input_NonInverting: Non inverting input is selected to configure the trimming value - * @param OPAMP_TrimValue: the trimming value. This parameter can be any value lower - * or equal to 0x0000001F. - * @retval None - */ -void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection)); - assert_param(IS_OPAMP_INPUT(OPAMP_Input)); - assert_param(IS_OPAMP_TRIMMINGVALUE(OPAMP_TrimValue)); - - /*!< Get the OPAMPx_CSR register value */ - tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection); - - /*!< Clear the trimming bits */ - tmpreg &= ((uint32_t)~(OPAMP_CSR_TRIMMING_MASK<<OPAMP_Input)); - - /*!< Configure the new trimming value */ - tmpreg |= (uint32_t)(OPAMP_TrimValue<<OPAMP_Input); - - /*!< Write to OPAMPx_CSR register */ - *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = tmpreg; -} - -/** - * @brief Start or stop the calibration of selected OPAMP peripheral. - * @note If the selected OPAMP is locked, start/stop can't be performed. - * To unlock the configuration, perform a system reset. - * @param OPAMP_Selection: the selected OPAMP. - * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4 - * to select the OPAMP peripheral. - * @param NewState: new state of the OPAMP peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void OPAMP_StartCalibration(uint32_t OPAMP_Selection, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Start the OPAMPx calibration */ - *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_CALON); - } - else - { - /* Stop the OPAMPx calibration */ - *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_CALON); - } -} - -/** - * @} - */ - -/** @defgroup OPAMP_Group2 OPAMP configuration locking function - * @brief OPAMP1,...OPAMP4 configuration locking function - * OPAMP1,...OPAMP4 configuration can be locked each separately. - * Unlocking is performed by system reset. - * -@verbatim - =============================================================================== - ##### Configuration Lock function ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Lock the selected OPAMP configuration. - * @note Locking the configuration means that all control bits are read-only. - * To unlock the OPAMP configuration, perform a system reset. - * @param OPAMP_Selection: the selected OPAMP. - * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4 - * to select the OPAMP peripheral. - * @retval None - */ -void OPAMP_LockConfig(uint32_t OPAMP_Selection) -{ - /* Check the parameter */ - assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection)); - - /* Set the lock bit corresponding to selected OPAMP */ - *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_LOCK); -} - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_opamp.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,287 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_opamp.h - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file contains all the functions prototypes for the operational - * amplifiers (OPAMP) firmware library. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F30x_OPAMP_H -#define __STM32F30x_OPAMP_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup OPAMP - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief OPAMP Init structure definition - */ - -typedef struct -{ - - uint32_t OPAMP_InvertingInput; /*!< Selects the inverting input of the operational amplifier. - This parameter can be a value of @ref OPAMP_InvertingInput */ - - uint32_t OPAMP_NonInvertingInput; /*!< Selects the non inverting input of the operational amplifier. - This parameter can be a value of @ref OPAMP_NonInvertingInput */ - -}OPAMP_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup OPAMP_Exported_Constants - * @{ - */ - -/** @defgroup OPAMP_Selection - * @{ - */ - -#define OPAMP_Selection_OPAMP1 ((uint32_t)0x00000000) /*!< OPAMP1 Selection */ -#define OPAMP_Selection_OPAMP2 ((uint32_t)0x00000004) /*!< OPAMP2 Selection */ -#define OPAMP_Selection_OPAMP3 ((uint32_t)0x00000008) /*!< OPAMP3 Selection */ -#define OPAMP_Selection_OPAMP4 ((uint32_t)0x0000000C) /*!< OPAMP4 Selection */ - -#define IS_OPAMP_ALL_PERIPH(PERIPH) (((PERIPH) == OPAMP_Selection_OPAMP1) || \ - ((PERIPH) == OPAMP_Selection_OPAMP2) || \ - ((PERIPH) == OPAMP_Selection_OPAMP3) || \ - ((PERIPH) == OPAMP_Selection_OPAMP4)) - -/** - * @} - */ - -/** @defgroup OPAMP_InvertingInput - * @{ - */ - -#define OPAMP_InvertingInput_IO1 ((uint32_t)0x00000000) /*!< IO1 (PC5 for OPAMP1 and OPAMP2, PB10 for OPAMP3 and OPAMP4) - connected to OPAMPx inverting input */ -#define OPAMP_InvertingInput_IO2 OPAMP_CSR_VMSEL_0 /*!< IO2 (PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PD8 for OPAMP4) - connected to OPAMPx inverting input */ -#define OPAMP_InvertingInput_PGA OPAMP_CSR_VMSEL_1 /*!< Resistor feedback output connected to OPAMPx inverting input (PGA mode) */ -#define OPAMP_InvertingInput_Vout OPAMP_CSR_VMSEL /*!< Vout connected to OPAMPx inverting input (follower mode) */ - -#define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_InvertingInput_IO1) || \ - ((INPUT) == OPAMP_InvertingInput_IO2) || \ - ((INPUT) == OPAMP_InvertingInput_PGA) || \ - ((INPUT) == OPAMP_InvertingInput_Vout)) -/** - * @} - */ - -/** @defgroup OPAMP_NonInvertingInput - * @{ - */ - -#define OPAMP_NonInvertingInput_IO1 ((uint32_t)0x00000000) /*!< IO1 (PA7 for OPAMP1, PD14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4) - connected to OPAMPx non inverting input */ -#define OPAMP_NonInvertingInput_IO2 OPAMP_CSR_VPSEL_0 /*!< IO2 (PA5 for OPAMP1, PB14 for OPAMP2, PA5 for OPAMP3, PB11 for OPAMP4) - connected to OPAMPx non inverting input */ -#define OPAMP_NonInvertingInput_IO3 OPAMP_CSR_VPSEL_1 /*!< IO3 (PA3 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PA4 for OPAMP4) - connected to OPAMPx non inverting input */ -#define OPAMP_NonInvertingInput_IO4 OPAMP_CSR_VPSEL /*!< IO4 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4) - connected to OPAMPx non inverting input */ - -#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NonInvertingInput_IO1) || \ - ((INPUT) == OPAMP_NonInvertingInput_IO2) || \ - ((INPUT) == OPAMP_NonInvertingInput_IO3) || \ - ((INPUT) == OPAMP_NonInvertingInput_IO4)) -/** - * @} - */ - -/** @defgroup OPAMP_PGAGain_Config - * @{ - */ - -#define OPAMP_OPAMP_PGAGain_2 ((uint32_t)0x00000000) -#define OPAMP_OPAMP_PGAGain_4 OPAMP_CSR_PGGAIN_0 -#define OPAMP_OPAMP_PGAGain_8 OPAMP_CSR_PGGAIN_1 -#define OPAMP_OPAMP_PGAGain_16 ((uint32_t)0x0000C000) - -#define IS_OPAMP_PGAGAIN(GAIN) (((GAIN) == OPAMP_OPAMP_PGAGain_2) || \ - ((GAIN) == OPAMP_OPAMP_PGAGain_4) || \ - ((GAIN) == OPAMP_OPAMP_PGAGain_8) || \ - ((GAIN) == OPAMP_OPAMP_PGAGain_16)) -/** - * @} - */ - -/** @defgroup OPAMP_PGAConnect_Config - * @{ - */ - -#define OPAMP_PGAConnect_No ((uint32_t)0x00000000) -#define OPAMP_PGAConnect_IO1 OPAMP_CSR_PGGAIN_3 -#define OPAMP_PGAConnect_IO2 ((uint32_t)0x00030000) - -#define IS_OPAMP_PGACONNECT(CONNECT) (((CONNECT) == OPAMP_PGAConnect_No) || \ - ((CONNECT) == OPAMP_PGAConnect_IO1) || \ - ((CONNECT) == OPAMP_PGAConnect_IO2)) -/** - * @} - */ - -/** @defgroup OPAMP_SecondaryInvertingInput - * @{ - */ - -#define IS_OPAMP_SECONDARY_INVINPUT(INVINPUT) (((INVINPUT) == OPAMP_InvertingInput_IO1) || \ - ((INVINPUT) == OPAMP_InvertingInput_IO2)) -/** - * @} - */ - -/** @defgroup OPAMP_Input - * @{ - */ - -#define OPAMP_Input_Inverting ((uint32_t)0x00000018) /*!< Inverting input */ -#define OPAMP_Input_NonInverting ((uint32_t)0x00000013) /*!< Non inverting input */ - -#define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_Input_Inverting) || \ - ((INPUT) == OPAMP_Input_NonInverting)) - -/** - * @} - */ - -/** @defgroup OPAMP_Vref - * @{ - */ - -#define OPAMP_Vref_3VDDA ((uint32_t)0x00000000) /*!< OPMAP Vref = 3.3% VDDA */ -#define OPAMP_Vref_10VDDA OPAMP_CSR_CALSEL_0 /*!< OPMAP Vref = 10% VDDA */ -#define OPAMP_Vref_50VDDA OPAMP_CSR_CALSEL_1 /*!< OPMAP Vref = 50% VDDA */ -#define OPAMP_Vref_90VDDA OPAMP_CSR_CALSEL /*!< OPMAP Vref = 90% VDDA */ - -#define IS_OPAMP_VREF(VREF) (((VREF) == OPAMP_Vref_3VDDA) || \ - ((VREF) == OPAMP_Vref_10VDDA) || \ - ((VREF) == OPAMP_Vref_50VDDA) || \ - ((VREF) == OPAMP_Vref_90VDDA)) - -/** - * @} - */ - -/** @defgroup OPAMP_Trimming - */ - -#define OPAMP_Trimming_Factory ((uint32_t)0x00000000) /*!< Factory trimming */ -#define OPAMP_Trimming_User OPAMP_CSR_USERTRIM /*!< User trimming */ - -#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_Trimming_Factory) || \ - ((TRIMMING) == OPAMP_Trimming_User)) - -/** - * @} - */ - -/** @defgroup OPAMP_TrimValue - * @{ - */ - -#define IS_OPAMP_TRIMMINGVALUE(VALUE) ((VALUE) <= 0x0000001F) /*!< Trimming value */ - -/** - * @} - */ - -/** @defgroup OPAMP_OutputLevel - * @{ - */ - -#define OPAMP_OutputLevel_High OPAMP_CSR_OUTCAL -#define OPAMP_OutputLevel_Low ((uint32_t)0x00000000) - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the OPAMP configuration to the default reset state ***/ -void OPAMP_DeInit(uint32_t OPAMP_Selection); - -/* Initialization and Configuration functions *********************************/ -void OPAMP_Init(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct); -void OPAMP_StructInit(OPAMP_InitTypeDef* OPAMP_InitStruct); -void OPAMP_PGAConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_PGAGain, uint32_t OPAMP_PGAConnect); -void OPAMP_VrefConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Vref); -void OPAMP_VrefConnectADCCmd(uint32_t OPAMP_Selection, FunctionalState NewState); -void OPAMP_TimerControlledMuxConfig(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct); -void OPAMP_TimerControlledMuxCmd(uint32_t OPAMP_Selection, FunctionalState NewState); -void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState); -uint32_t OPAMP_GetOutputLevel(uint32_t OPAMP_Selection); - -/* Calibration functions ******************************************************/ -void OPAMP_VrefConnectNonInvertingInput(uint32_t OPAMP_Selection, FunctionalState NewState); -void OPAMP_OffsetTrimModeSelect(uint32_t OPAMP_Selection, uint32_t OPAMP_Trimming); -void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue); -void OPAMP_StartCalibration(uint32_t OPAMP_Selection, FunctionalState NewState); - -/* OPAMP configuration locking function ***************************************/ -void OPAMP_LockConfig(uint32_t OPAMP_Selection); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F30x_OPAMP_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_pwr.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,548 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_pwr.c - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Power Controller (PWR) peripheral: - * + Backup Domain Access - * + PVD configuration - * + WakeUp pins configuration - * + Low Power modes configuration - * + Flags management - * - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x_pwr.h" -#include "stm32f30x_rcc.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @defgroup PWR - * @brief PWR driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* --------- PWR registers bit address in the alias region ---------- */ -#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) - -/* --- CR Register ---*/ - -/* Alias word address of DBP bit */ -#define CR_OFFSET (PWR_OFFSET + 0x00) -#define DBP_BitNumber 0x08 -#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) - -/* Alias word address of PVDE bit */ -#define PVDE_BitNumber 0x04 -#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) - -/* ------------------ PWR registers bit mask ------------------------ */ - -/* CR register bit mask */ -#define CR_DS_MASK ((uint32_t)0xFFFFFFFC) -#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup PWR_Private_Functions - * @{ - */ - -/** @defgroup PWR_Group1 Backup Domain Access function - * @brief Backup Domain Access function - * -@verbatim - ============================================================================== - ##### Backup Domain Access function ##### - ============================================================================== - - [..] After reset, the Backup Domain Registers (RCC BDCR Register, RTC registers - and RTC backup registers) are protected against possible stray write accesses. - [..] To enable access to Backup domain use the PWR_BackupAccessCmd(ENABLE) function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the PWR peripheral registers to their default reset values. - * @param None - * @retval None - */ -void PWR_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); -} - -/** - * @brief Enables or disables access to the RTC and backup registers. - * @note If the HSE divided by 32 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @param NewState: new state of the access to the RTC and backup registers. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_BackupAccessCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group2 PVD configuration functions - * @brief PVD configuration functions - * -@verbatim - =============================================================================== - ##### PVD configuration functions ##### - ============================================================================== - [..] - (+) The PVD is used to monitor the VDD power supply by comparing it to a threshold - selected by the PVD Level (PLS[2:0] bits in the PWR_CR). - (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the - PVD threshold. This event is internally connected to the EXTI line16 - and can generate an interrupt if enabled through the EXTI registers. - (+) The PVD is stopped in Standby mode. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param PWR_PVDLevel: specifies the PVD detection level - * This parameter can be one of the following values: - * @arg PWR_PVDLevel_0: PVD detection level set to 2.18V - * @arg PWR_PVDLevel_1: PVD detection level set to 2.28V - * @arg PWR_PVDLevel_2: PVD detection level set to 2.38V - * @arg PWR_PVDLevel_3: PVD detection level set to 2.48V - * @arg PWR_PVDLevel_4: PVD detection level set to 2.58V - * @arg PWR_PVDLevel_5: PVD detection level set to 2.68V - * @arg PWR_PVDLevel_6: PVD detection level set to 2.78V - * @arg PWR_PVDLevel_7: PVD detection level set to 2.88V - * @retval None - */ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); - - tmpreg = PWR->CR; - - /* Clear PLS[7:5] bits */ - tmpreg &= CR_PLS_MASK; - - /* Set PLS[7:5] bits according to PWR_PVDLevel value */ - tmpreg |= PWR_PVDLevel; - - /* Store the new value */ - PWR->CR = tmpreg; -} - -/** - * @brief Enables or disables the Power Voltage Detector(PVD). - * @param NewState: new state of the PVD. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_PVDCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group3 WakeUp pins configuration functions - * @brief WakeUp pins configuration functions - * -@verbatim - =============================================================================== - ##### WakeUp pins configuration functions ##### - =============================================================================== - [..] - (+) WakeUp pins are used to wakeup the system from Standby mode. These pins are - forced in input pull down configuration and are active on rising edges. - (+) There are three WakeUp pins: WakeUp Pin 1 on PA.00, WakeUp Pin 2 on PC.13 and - WakeUp Pin 3 on PE.06. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the WakeUp Pin functionality. - * @param PWR_WakeUpPin: specifies the WakeUpPin. - * This parameter can be: PWR_WakeUpPin_1, PWR_WakeUpPin_2 or PWR_WakeUpPin_3. - * @param NewState: new state of the WakeUp Pin functionality. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the EWUPx pin */ - PWR->CSR |= PWR_WakeUpPin; - } - else - { - /* Disable the EWUPx pin */ - PWR->CSR &= ~PWR_WakeUpPin; - } -} - -/** - * @} - */ - - -/** @defgroup PWR_Group4 Low Power modes configuration functions - * @brief Low Power modes configuration functions - * -@verbatim - =============================================================================== - ##### Low Power modes configuration functions ##### - ============================================================================== - - [..] The devices feature three low-power modes: - (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running. - (+) Stop mode: all clocks are stopped, regulator running, regulator in low power mode - (+) Standby mode: VCORE domain powered off - - *** Sleep mode *** - ================== - [..] - (+) Entry: - (++) The Sleep mode is entered by executing the WFE() or WFI() instructions. - (+) Exit: - (++) Any peripheral interrupt acknowledged by the nested vectored interrupt - controller (NVIC) can wake up the device from Sleep mode. - - *** Stop mode *** - ================= - [..] In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the HSI, - and the HSE RC oscillators are disabled. Internal SRAM and register - contents are preserved. - The voltage regulator can be configured either in normal or low-power mode. - - (+) Entry: - (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) - function with regulator in LowPower or with Regulator ON. - (+) Exit: - (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode - or any internal IPs (I2C or UASRT) wakeup event. - - *** Standby mode *** - ==================== - [..] The Standby mode allows to achieve the lowest power consumption. It is based - on the Cortex-M4 deepsleep mode, with the voltage regulator disabled. - The VCORE domain is consequently powered off. The PLL, the HSI, and the HSE - oscillator are also switched off. SRAM and register - contents are lost except for the Backup domain (RTC registers, RTC backup - registers and Standby circuitry). - - [..] The voltage regulator is OFF. - - (+) Entry: - (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function. - (+) Exit: - (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, - tamper event, time-stamp event, external reset in NRST pin, IWDG reset. - - *** Auto-wakeup (AWU) from low-power mode *** - ============================================= - [..] The MCU can be woken up from low-power mode by an RTC Alarm event, a tamper - event, a time-stamp event, or a comparator event, without depending on an - external interrupt (Auto-wakeup mode). - - (+) RTC auto-wakeup (AWU) from the Stop mode - (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to: - (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function - (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() - and RTC_AlarmCmd() functions. - (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it - is necessary to: - (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() - function. - (+++) Configure the RTC to detect the tamper or time stamp event using the - RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() - functions. - - (+) RTC auto-wakeup (AWU) from the Standby mode - (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to: - (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function. - (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() - and RTC_AlarmCmd() functions. - (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it - is necessary to: - (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() - function. - (+++) Configure the RTC to detect the tamper or time stamp event using the - RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() - functions. - - (+) Comparator auto-wakeup (AWU) from the Stop mode - (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to: - (+++) Configure the correspondant comparator EXTI Line to be sensitive to - the selected edges (falling, rising or falling and rising) - (Interrupt or Event modes) using the EXTI_Init() function. - (+++) Configure the comparator to generate the event. - -@endverbatim - * @{ - */ - -/** - * @brief Enters Sleep mode. - * @note In Sleep mode, all I/O pins keep the same state as in Run mode. - * @param PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction - * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction - * @retval None - */ -void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry) -{ - /* Check the parameters */ - assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry)); - - /* Clear SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); - - /* Select SLEEP mode entry -------------------------------------------------*/ - if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __WFE(); - } -} - -/** - * @brief Enters STOP mode. - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * @note When exiting Stop mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as system clock. - * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. - * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. - * @param PWR_Regulator: specifies the regulator state in STOP mode. - * This parameter can be one of the following values: - * @arg PWR_Regulator_ON: STOP mode with regulator ON - * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode - * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction - * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction - * @retval None - */ -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(PWR_Regulator)); - assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); - - /* Select the regulator state in STOP mode ---------------------------------*/ - tmpreg = PWR->CR; - /* Clear PDDS and LPDSR bits */ - tmpreg &= CR_DS_MASK; - - /* Set LPDSR bit according to PWR_Regulator value */ - tmpreg |= PWR_Regulator; - - /* Store the new value */ - PWR->CR = tmpreg; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Select STOP mode entry --------------------------------------------------*/ - if(PWR_STOPEntry == PWR_STOPEntry_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __WFE(); - } - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); -} - -/** - * @brief Enters STANDBY mode. - * @note In Standby mode, all I/O pins are high impedance except for: - * @note Reset pad (still available) - * @note RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper, - * time-stamp, RTC Alarm out, or RTC clock calibration out. - * @note WKUP pin 1 (PA0) and WKUP pin 3 (PE6), if enabled. - * @param None - * @retval None - */ -void PWR_EnterSTANDBYMode(void) -{ - /* Clear Wakeup flag */ - PWR->CR |= PWR_CR_CWUF; - - /* Select STANDBY mode */ - PWR->CR |= PWR_CR_PDDS; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - -/* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM ) - __force_stores(); -#endif - /* Request Wait For Interrupt */ - __WFI(); -} - -/** - * @} - */ - -/** @defgroup PWR_Group5 Flags management functions - * @brief Flags management functions - * -@verbatim - =============================================================================== - ##### Flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified PWR flag is set or not. - * @param PWR_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event - * was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), - * RTC Tamper event, RTC TimeStamp event or RTC Wakeup. - * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was - * resumed from StandBy mode. - * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled - * by the PWR_PVDCmd() function. - * @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag. This - * flag indicates the state of the internal voltage reference, VREFINT. - * @retval The new state of PWR_FLAG (SET or RESET). - */ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); - - if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the PWR's pending flags. - * @param PWR_FLAG: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag - * @arg PWR_FLAG_SB: StandBy flag - * @retval None - */ -void PWR_ClearFlag(uint32_t PWR_FLAG) -{ - /* Check the parameters */ - assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); - - PWR->CR |= PWR_FLAG << 2; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_pwr.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,197 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_pwr.h - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file contains all the functions prototypes for the PWR firmware - * library. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F30x_PWR_H -#define __STM32F30x_PWR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup PWR - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Constants - * @{ - */ - -/** @defgroup PWR_PVD_detection_level - * @{ - */ - -#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0 -#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1 -#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2 -#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3 -#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4 -#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5 -#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6 -#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 - -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \ - ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \ - ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \ - ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7)) -/** - * @} - */ - -/** @defgroup PWR_WakeUp_Pins - * @{ - */ - -#define PWR_WakeUpPin_1 PWR_CSR_EWUP1 -#define PWR_WakeUpPin_2 PWR_CSR_EWUP2 -#define PWR_WakeUpPin_3 PWR_CSR_EWUP3 -#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \ - ((PIN) == PWR_WakeUpPin_2) || \ - ((PIN) == PWR_WakeUpPin_3)) -/** - * @} - */ - - -/** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode - * @{ - */ - -#define PWR_Regulator_ON ((uint32_t)0x00000000) -#define PWR_Regulator_LowPower PWR_CR_LPSDSR -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ - ((REGULATOR) == PWR_Regulator_LowPower)) -/** - * @} - */ - -/** @defgroup PWR_SLEEP_mode_entry - * @{ - */ - -#define PWR_SLEEPEntry_WFI ((uint8_t)0x01) -#define PWR_SLEEPEntry_WFE ((uint8_t)0x02) -#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE)) - -/** - * @} - */ - -/** @defgroup PWR_STOP_mode_entry - * @{ - */ - -#define PWR_STOPEntry_WFI ((uint8_t)0x01) -#define PWR_STOPEntry_WFE ((uint8_t)0x02) -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) - -/** - * @} - */ - -/** @defgroup PWR_Flag - * @{ - */ - -#define PWR_FLAG_WU PWR_CSR_WUF -#define PWR_FLAG_SB PWR_CSR_SBF -#define PWR_FLAG_PVDO PWR_CSR_PVDO -#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF - -#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ - ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY)) - -#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the PWR configuration to the default reset state ******/ -void PWR_DeInit(void); - -/* Backup Domain Access function **********************************************/ -void PWR_BackupAccessCmd(FunctionalState NewState); - -/* PVD configuration functions ************************************************/ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); -void PWR_PVDCmd(FunctionalState NewState); - -/* WakeUp pins configuration functions ****************************************/ -void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState); - -/* Low Power modes configuration functions ************************************/ -void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry); -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); -void PWR_EnterSTANDBYMode(void); - -/* Flags management functions *************************************************/ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); -void PWR_ClearFlag(uint32_t PWR_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F30x_PWR_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_rcc.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1961 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_rcc.c - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Reset and clock control (RCC) peripheral: - * + Internal/external clocks, PLL, CSS and MCO configuration - * + System, AHB and APB busses clocks configuration - * + Peripheral clocks configuration - * + Interrupts and flags management - * - @verbatim - - =============================================================================== - ##### RCC specific features ##### - =============================================================================== - [..] After reset the device is running from HSI (8 MHz) with Flash 0 WS, - all peripherals are off except internal SRAM, Flash and SWD. - (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; - all peripherals mapped on these busses are running at HSI speed. - (+) The clock for all peripherals is switched off, except the SRAM and FLASH. - (+) All GPIOs are in input floating state, except the SWD pins which - are assigned to be used for debug purpose. - [..] Once the device starts from reset, the user application has to: - (+) Configure the clock source to be used to drive the System clock - (if the application needs higher frequency/performance). - (+) Configure the System clock frequency and Flash settings. - (+) Configure the AHB and APB busses prescalers. - (+) Enable the clock for the peripheral(s) to be used. - (+) Configure the clock source(s) for peripherals which clocks are not - derived from the System clock (ADC, TIM, I2C, USART, RTC and IWDG). - - @endverbatim - - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x_rcc.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @defgroup RCC - * @brief RCC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* ------------ RCC registers bit address in the alias region ----------- */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) - -/* --- CR Register ---*/ - -/* Alias word address of HSION bit */ -#define CR_OFFSET (RCC_OFFSET + 0x00) -#define HSION_BitNumber 0x00 -#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) - -/* Alias word address of PLLON bit */ -#define PLLON_BitNumber 0x18 -#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) - -/* Alias word address of CSSON bit */ -#define CSSON_BitNumber 0x13 -#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) - -/* --- CFGR Register ---*/ -/* Alias word address of USBPRE bit */ -#define CFGR_OFFSET (RCC_OFFSET + 0x04) -#define USBPRE_BitNumber 0x16 -#define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) -/* Alias word address of I2SSRC bit */ -#define I2SSRC_BitNumber 0x17 -#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4)) - -/* --- BDCR Register ---*/ - -/* Alias word address of RTCEN bit */ -#define BDCR_OFFSET (RCC_OFFSET + 0x20) -#define RTCEN_BitNumber 0x0F -#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) - -/* Alias word address of BDRST bit */ -#define BDRST_BitNumber 0x10 -#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) - -/* --- CSR Register ---*/ - -/* Alias word address of LSION bit */ -#define CSR_OFFSET (RCC_OFFSET + 0x24) -#define LSION_BitNumber 0x00 -#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) - -/* ---------------------- RCC registers bit mask ------------------------ */ -/* RCC Flag Mask */ -#define FLAG_MASK ((uint8_t)0x1F) - -/* CFGR register byte 3 (Bits[31:23]) base address */ -#define CFGR_BYTE3_ADDRESS ((uint32_t)0x40021007) - -/* CIR register byte 2 (Bits[15:8]) base address */ -#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009) - -/* CIR register byte 3 (Bits[23:16]) base address */ -#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A) - -/* CR register byte 2 (Bits[23:16]) base address */ -#define CR_BYTE2_ADDRESS ((uint32_t)0x40021002) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; -const uint16_t ADCPrescTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256, 0, 0, 0, 0 }; - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RCC_Private_Functions - * @{ - */ - -/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions - * @brief Internal and external clocks, PLL, CSS and MCO configuration functions - * -@verbatim - =============================================================================== - ##### Internal-external clocks, PLL, CSS and MCO configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to configure the internal/external - clocks, PLL, CSS and MCO. - (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly - or through the PLL as System clock source. - The HSI clock can be used also to clock the USART and I2C peripherals. - (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC - clock source. - (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or - through the PLL as System clock source. Can be used also as RTC clock source. - (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. - LSE can be used also to clock the USART peripherals. - (#) PLL (clocked by HSI or HSE), for System clock. - (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs - (HSE used directly or through PLL as System clock source), the System clock - is automatically switched to HSI and an interrupt is generated if enabled. - The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) - exception vector. - (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE, - PLL clock on PA8 pin. - -@endverbatim - * @{ - */ - -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * @note HSI ON and used as system clock source - * @note HSE and PLL OFF - * @note AHB, APB1 and APB2 prescalers set to 1. - * @note CSS and MCO OFF - * @note All interrupts disabled - * @note However, this function doesn't modify the configuration of the - * @note Peripheral clocks - * @note LSI, LSE and RTC clocks - * @param None - * @retval None - */ -void RCC_DeInit(void) -{ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */ - RCC->CFGR &= (uint32_t)0xF8FFC000; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */ - RCC->CFGR &= (uint32_t)0xFF80FFFF; - - /* Reset PREDIV1[3:0] and ADCPRE[13:4] bits */ - RCC->CFGR2 &= (uint32_t)0xFFFFC000; - - /* Reset USARTSW[1:0], I2CSW and TIMSW bits */ - RCC->CFGR3 &= (uint32_t)0xF00ECCC; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; -} - -/** - * @brief Configures the External High Speed oscillator (HSE). - * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application - * software should wait on HSERDY flag to be set indicating that HSE clock - * is stable and can be used to clock the PLL and/or system clock. - * @note HSE state can not be changed if it is used directly or through the - * PLL as system clock. In this case, you have to select another source - * of the system clock then change the HSE state (ex. disable it). - * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. - * @note This function resets the CSSON bit, so if the Clock security system(CSS) - * was previously enabled you have to enable it again after calling this - * function. - * @param RCC_HSE: specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after - * 6 HSE oscillator clock cycles. - * @arg RCC_HSE_ON: turn ON the HSE oscillator - * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock - * @retval None - */ -void RCC_HSEConfig(uint8_t RCC_HSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_HSE)); - - /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ - *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE_OFF; - - /* Set the new HSE configuration -------------------------------------------*/ - *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE; - -} - -/** - * @brief Waits for HSE start-up. - * @note This function waits on HSERDY flag to be set and return SUCCESS if - * this flag is set, otherwise returns ERROR if the timeout is reached - * and this flag is not set. The timeout value is defined by the constant - * HSE_STARTUP_TIMEOUT in stm32f30x.h file. You can tailor it depending - * on the HSE crystal used in your application. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: HSE oscillator is stable and ready to use - * - ERROR: HSE oscillator not yet ready - */ -ErrorStatus RCC_WaitForHSEStartUp(void) -{ - __IO uint32_t StartUpCounter = 0; - ErrorStatus status = ERROR; - FlagStatus HSEStatus = RESET; - - /* Wait till HSE is ready and if timeout is reached exit */ - do - { - HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); - StartUpCounter++; - } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); - - if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - return (status); -} - -/** - * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI RC. - * Refer to the Application Note AN3300 for more details on how to - * calibrate the HSI. - * @param HSICalibrationValue: specifies the HSI calibration trimming value. - * This parameter must be a number between 0 and 0x1F. - * @retval None - */ -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue)); - - tmpreg = RCC->CR; - - /* Clear HSITRIM[4:0] bits */ - tmpreg &= ~RCC_CR_HSITRIM; - - /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ - tmpreg |= (uint32_t)HSICalibrationValue << 3; - - /* Store the new value */ - RCC->CR = tmpreg; -} - -/** - * @brief Enables or disables the Internal High Speed oscillator (HSI). - * @note After enabling the HSI, the application software should wait on - * HSIRDY flag to be set indicating that HSI clock is stable and can - * be used to clock the PLL and/or system clock. - * @note HSI can not be stopped if it is used directly or through the PLL - * as system clock. In this case, you have to select another source - * of the system clock then stop the HSI. - * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. - * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. - * @param NewState: new state of the HSI. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_HSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the External Low Speed oscillator (LSE). - * @note As the LSE is in the Backup domain and write access is denied to this - * domain after reset, you have to enable write access using - * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE - * (to be done once after reset). - * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application - * software should wait on LSERDY flag to be set indicating that LSE clock - * is stable and can be used to clock the RTC. - * @param RCC_LSE: specifies the new state of the LSE. - * This parameter can be one of the following values: - * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after - * 6 LSE oscillator clock cycles. - * @arg RCC_LSE_ON: turn ON the LSE oscillator - * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock - * @retval None - */ -void RCC_LSEConfig(uint32_t RCC_LSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_LSE)); - - /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ - /* Reset LSEON bit */ - RCC->BDCR &= ~(RCC_BDCR_LSEON); - - /* Reset LSEBYP bit */ - RCC->BDCR &= ~(RCC_BDCR_LSEBYP); - - /* Configure LSE */ - RCC->BDCR |= RCC_LSE; -} - -/** - * @brief Configures the External Low Speed oscillator (LSE) drive capability. - * @param RCC_LSEDrive: specifies the new state of the LSE drive capability. - * This parameter can be one of the following values: - * @arg RCC_LSEDrive_Low: LSE oscillator low drive capability. - * @arg RCC_LSEDrive_MediumLow: LSE oscillator medium low drive capability. - * @arg RCC_LSEDrive_MediumHigh: LSE oscillator medium high drive capability. - * @arg RCC_LSEDrive_High: LSE oscillator high drive capability. - * @retval None - */ -void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive) -{ - /* Check the parameters */ - assert_param(IS_RCC_LSE_DRIVE(RCC_LSEDrive)); - - /* Clear LSEDRV[1:0] bits */ - RCC->BDCR &= ~(RCC_BDCR_LSEDRV); - - /* Set the LSE Drive */ - RCC->BDCR |= RCC_LSEDrive; -} - -/** - * @brief Enables or disables the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on - * LSIRDY flag to be set indicating that LSI clock is stable and can - * be used to clock the IWDG and/or the RTC. - * @note LSI can not be disabled if the IWDG is running. - * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. - * @param NewState: new state of the LSI. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_LSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the PLL clock source and multiplication factor. - * @note This function must be used only when the PLL is disabled. - * @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as - * PLL source). - * @param RCC_PLLSource: specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as - * PLL clock entry - * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock source - * @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock - * This parameter can be RCC_PLLMul_x where x:[2,16] - * - * @retval None - */ -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); - assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); - - /* Clear PLL Source [16] and Multiplier [21:18] bits */ - RCC->CFGR &= ~(RCC_CFGR_PLLMULL | RCC_CFGR_PLLSRC); - - /* Set the PLL Source and Multiplier */ - RCC->CFGR |= (uint32_t)(RCC_PLLSource | RCC_PLLMul); -} - -/** - * @brief Enables or disables the PLL. - * @note After enabling the PLL, the application software should wait on - * PLLRDY flag to be set indicating that PLL clock is stable and can - * be used as system clock source. - * @note The PLL can not be disabled if it is used as system clock source - * @note The PLL is disabled by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the PLL. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLLCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the PREDIV1 division factor. - * @note This function must be used only when the PLL is disabled. - * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor. - * This parameter can be RCC_PREDIV1_Divx where x:[1,16] - * @retval None - */ -void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div)); - - tmpreg = RCC->CFGR2; - /* Clear PREDIV1[3:0] bits */ - tmpreg &= ~(RCC_CFGR2_PREDIV1); - - /* Set the PREDIV1 division factor */ - tmpreg |= RCC_PREDIV1_Div; - - /* Store the new value */ - RCC->CFGR2 = tmpreg; -} - -/** - * @brief Enables or disables the Clock Security System. - * @note If a failure is detected on the HSE oscillator clock, this oscillator - * is automatically disabled and an interrupt is generated to inform the - * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. - * @param NewState: new state of the Clock Security System. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ClockSecuritySystemCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; -} - -#ifdef STM32F303xC -/** - * @brief Selects the clock source to output on MCO pin (PA8). - * @note PA8 should be configured in alternate function mode. - * @param RCC_MCOSource: specifies the clock source to output. - * This parameter can be one of the following values: - * @arg RCC_MCOSource_NoClock: No clock selected. - * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected. - * @arg RCC_MCOSource_LSI: LSI oscillator clock selected. - * @arg RCC_MCOSource_LSE: LSE oscillator clock selected. - * @arg RCC_MCOSource_SYSCLK: System clock selected. - * @arg RCC_MCOSource_HSI: HSI oscillator clock selected. - * @arg RCC_MCOSource_HSE: HSE oscillator clock selected. - * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected. - * @arg RCC_MCOSource_PLLCLK: PLL clock selected. - * @arg RCC_MCOSource_HSI48: HSI48 clock selected. - * @retval None - */ -void RCC_MCOConfig(uint8_t RCC_MCOSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource)); - - /* Get CFGR value */ - tmpreg = RCC->CFGR; - /* Clear MCO[3:0] bits */ - tmpreg &= ~(RCC_CFGR_MCO | RCC_CFGR_PLLNODIV); - /* Set the RCC_MCOSource */ - tmpreg |= RCC_MCOSource<<24; - /* Store the new value */ - RCC->CFGR = tmpreg; -} -#else - -/** - * @brief Selects the clock source to output on MCO pin (PA8) and the corresponding - * prescsaler. - * @note PA8 should be configured in alternate function mode. - * @param RCC_MCOSource: specifies the clock source to output. - * This parameter can be one of the following values: - * @arg RCC_MCOSource_NoClock: No clock selected. - * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected. - * @arg RCC_MCOSource_LSI: LSI oscillator clock selected. - * @arg RCC_MCOSource_LSE: LSE oscillator clock selected. - * @arg RCC_MCOSource_SYSCLK: System clock selected. - * @arg RCC_MCOSource_HSI: HSI oscillator clock selected. - * @arg RCC_MCOSource_HSE: HSE oscillator clock selected. - * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected. - * @arg RCC_MCOSource_PLLCLK: PLL clock selected. - * @arg RCC_MCOSource_HSI48: HSI48 clock selected. - * @param RCC_MCOPrescaler: specifies the prescaler on MCO pin. - * This parameter can be one of the following values: - * @arg RCC_MCOPrescaler_1: MCO clock is divided by 1. - * @arg RCC_MCOPrescaler_2: MCO clock is divided by 2. - * @arg RCC_MCOPrescaler_4: MCO clock is divided by 4. - * @arg RCC_MCOPrescaler_8: MCO clock is divided by 8. - * @arg RCC_MCOPrescaler_16: MCO clock is divided by 16. - * @arg RCC_MCOPrescaler_32: MCO clock is divided by 32. - * @arg RCC_MCOPrescaler_64: MCO clock is divided by 64. - * @arg RCC_MCOPrescaler_128: MCO clock is divided by 128. - * @retval None - */ -void RCC_MCOConfig(uint8_t RCC_MCOSource, uint32_t RCC_MCOPrescaler) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource)); - assert_param(IS_RCC_MCO_PRESCALER(RCC_MCOPrescaler)); - - /* Get CFGR value */ - tmpreg = RCC->CFGR; - /* Clear MCOPRE[2:0] bits */ - tmpreg &= ~(RCC_CFGR_MCO_PRE | RCC_CFGR_MCO | RCC_CFGR_PLLNODIV); - /* Set the RCC_MCOSource and RCC_MCOPrescaler */ - tmpreg |= (RCC_MCOPrescaler | RCC_MCOSource<<24); - /* Store the new value */ - RCC->CFGR = tmpreg; -} -#endif /* STM32F303xC */ - -/** - * @} - */ - -/** @defgroup RCC_Group2 System AHB, APB1 and APB2 busses clocks configuration functions - * @brief System, AHB and APB busses clocks configuration functions - * -@verbatim - =============================================================================== - ##### System, AHB, APB1 and APB2 busses clocks configuration functions ##### - =============================================================================== - [..] This section provide functions allowing to configure the System, AHB, APB1 and - APB2 busses clocks. - (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, - HSE and PLL. - The AHB clock (HCLK) is derived from System clock through configurable prescaler - and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO). - APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through - configurable prescalers and used to clock the peripherals mapped on these busses. - You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. - - (#) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 72 MHz. - Depending on the maximum frequency, the FLASH wait states (WS) should be - adapted accordingly: - +---------------------------------+ - | Wait states | HCLK clock | - | (Latency) | frequency (MHz) | - |-------------- |-----------------| - |0WS(1CPU cycle)| 0 < HCLK <= 24 | - |---------------|-----------------| - |1WS(2CPU cycle)|24 < HCLK <=48 | - |---------------|-----------------| - |2WS(3CPU cycle)|48 < HCLK <= 72 | - +---------------------------------+ - - (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and - prefetch is disabled. - [..] - (@) All the peripheral clocks are derived from the System clock (SYSCLK) - except: - (+@) The FLASH program/erase clock which is always HSI 8MHz clock. - (+@) The USB 48 MHz clock which is derived from the PLL VCO clock. - (+@) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE. - (+@) The I2C clock which can be derived as well from HSI 8MHz clock. - (+@) The ADC clock which is derived from PLL output. - (+@) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC - (HSE divided by a programmable prescaler). The System clock (SYSCLK) - frequency must be higher or equal to the RTC clock frequency. - (+@) IWDG clock which is always the LSI clock. - [..] It is recommended to use the following software sequences to tune the number - of wait states needed to access the Flash memory with the CPU frequency (HCLK). - (+) Increasing the CPU frequency - (++) Program the Flash Prefetch buffer, using "FLASH_PrefetchBufferCmd(ENABLE)" - function - (++) Check that Flash Prefetch buffer activation is taken into account by - reading FLASH_ACR using the FLASH_GetPrefetchBufferStatus() function - (++) Program Flash WS to 1 or 2, using "FLASH_SetLatency()" function - (++) Check that the new number of WS is taken into account by reading FLASH_ACR - (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function - (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function - (++) Check that the new CPU clock source is taken into account by reading - the clock source status, using "RCC_GetSYSCLKSource()" function - (+) Decreasing the CPU frequency - (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function - (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function - (++) Check that the new CPU clock source is taken into account by reading - the clock source status, using "RCC_GetSYSCLKSource()" function - (++) Program the new number of WS, using "FLASH_SetLatency()" function - (++) Check that the new number of WS is taken into account by reading FLASH_ACR - (++) Disable the Flash Prefetch buffer using "FLASH_PrefetchBufferCmd(DISABLE)" - function - (++) Check that Flash Prefetch buffer deactivation is taken into account by reading FLASH_ACR - using the FLASH_GetPrefetchBufferStatus() function. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the system clock (SYSCLK). - * @note The HSI is used (enabled by hardware) as system clock source after - * startup from Reset, wake-up from STOP and STANDBY mode, or in case - * of failure of the HSE used directly or indirectly as system clock - * (if the Clock Security System CSS is enabled). - * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after startup delay or PLL locked). - * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source will be ready. - * You can use RCC_GetSYSCLKSource() function to know which clock is - * currently used as system clock source. - * @param RCC_SYSCLKSource: specifies the clock source used as system clock source - * This parameter can be one of the following values: - * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source - * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source - * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source - * @retval None - */ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); - - tmpreg = RCC->CFGR; - - /* Clear SW[1:0] bits */ - tmpreg &= ~RCC_CFGR_SW; - - /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ - tmpreg |= RCC_SYSCLKSource; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Returns the clock source used as system clock. - * @param None - * @retval The clock source used as system clock. The returned value can be one - * of the following values: - * - 0x00: HSI used as system clock - * - 0x04: HSE used as system clock - * - 0x08: PLL used as system clock - */ -uint8_t RCC_GetSYSCLKSource(void) -{ - return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS)); -} - -/** - * @brief Configures the AHB clock (HCLK). - * @note Depending on the device voltage range, the software has to set correctly - * these bits to ensure that the system frequency does not exceed the - * maximum allowed frequency (for more details refer to section above - * "CPU, AHB and APB busses clocks configuration functions"). - * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from - * the system clock (SYSCLK). - * This parameter can be one of the following values: - * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK - * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 - * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 - * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 - * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 - * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 - * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 - * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 - * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 - * @retval None - */ -void RCC_HCLKConfig(uint32_t RCC_SYSCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_HCLK(RCC_SYSCLK)); - - tmpreg = RCC->CFGR; - - /* Clear HPRE[3:0] bits */ - tmpreg &= ~RCC_CFGR_HPRE; - - /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ - tmpreg |= RCC_SYSCLK; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the Low Speed APB clock (PCLK1). - * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB1 clock = HCLK - * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK1Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - - tmpreg = RCC->CFGR; - /* Clear PPRE1[2:0] bits */ - tmpreg &= ~RCC_CFGR_PPRE1; - - /* Set PPRE1[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the High Speed APB clock (PCLK2). - * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB2 clock = HCLK - * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK2Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - - tmpreg = RCC->CFGR; - /* Clear PPRE2[2:0] bits */ - tmpreg &= ~RCC_CFGR_PPRE2; - /* Set PPRE2[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK << 3; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Returns the frequencies of the System, AHB, APB2 and APB1 busses clocks. - * - * @note This function returns the frequencies of : - * System, AHB, APB2 and APB1 busses clocks, ADC1/2/3/4 clocks, - * USART1/2/3/4/5 clocks, I2C1/2 clocks and TIM1/8 Clocks. - * - * @note The frequency returned by this function is not the real frequency - * in the chip. It is calculated based on the predefined constant and - * the source selected by RCC_SYSCLKConfig(). - * - * @note If SYSCLK source is HSI, function returns constant HSI_VALUE(*) - * - * @note If SYSCLK source is HSE, function returns constant HSE_VALUE(**) - * - * @note If SYSCLK source is PLL, function returns constant HSE_VALUE(**) - * or HSI_VALUE(*) multiplied by the PLL factors. - * - * @note (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value - * 8 MHz) but the real value may vary depending on the variations - * in voltage and temperature, refer to RCC_AdjustHSICalibrationValue(). - * - * @note (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * return wrong result. - * - * @note The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold - * the clocks frequencies. - * - * @note This function can be used by the user application to compute the - * baudrate for the communication peripherals or configure other parameters. - * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function - * must be called to update the structure's field. Otherwise, any - * configuration based on this function will be incorrect. - * - * @retval None - */ -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0, presc = 0, pllclk = 0; - uint32_t apb2presc = 0, ahbpresc = 0; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock */ - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock */ - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock */ - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; - pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - pllmull = ( pllmull >> 18) + 2; - - if (pllsource == 0x00) - { - /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - pllclk = (HSI_VALUE >> 1) * pllmull; - } - else - { - prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; - /* HSE oscillator clock selected as PREDIV1 clock entry */ - pllclk = (HSE_VALUE / prediv1factor) * pllmull; - } - RCC_Clocks->SYSCLK_Frequency = pllclk; - break; - default: /* HSI used as system clock */ - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - } - /* Compute HCLK, PCLK clocks frequencies -----------------------------------*/ - /* Get HCLK prescaler */ - tmp = RCC->CFGR & RCC_CFGR_HPRE; - tmp = tmp >> 4; - ahbpresc = APBAHBPrescTable[tmp]; - /* HCLK clock frequency */ - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> ahbpresc; - - /* Get PCLK1 prescaler */ - tmp = RCC->CFGR & RCC_CFGR_PPRE1; - tmp = tmp >> 8; - presc = APBAHBPrescTable[tmp]; - /* PCLK1 clock frequency */ - RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - - /* Get PCLK2 prescaler */ - tmp = RCC->CFGR & RCC_CFGR_PPRE2; - tmp = tmp >> 11; - apb2presc = APBAHBPrescTable[tmp]; - /* PCLK2 clock frequency */ - RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> apb2presc; - - /* Get ADC12CLK prescaler */ - tmp = RCC->CFGR2 & RCC_CFGR2_ADCPRE12; - tmp = tmp >> 4; - presc = ADCPrescTable[tmp & 0x0F]; - if (((tmp & 0x10) != 0) && (presc != 0)) - { - /* ADC12CLK clock frequency is derived from PLL clock */ - RCC_Clocks->ADC12CLK_Frequency = pllclk / presc; - } - else - { - /* ADC12CLK clock frequency is AHB clock */ - RCC_Clocks->ADC12CLK_Frequency = RCC_Clocks->SYSCLK_Frequency; - } - - /* Get ADC34CLK prescaler */ - tmp = RCC->CFGR2 & RCC_CFGR2_ADCPRE34; - tmp = tmp >> 9; - presc = ADCPrescTable[tmp & 0x0F]; - if (((tmp & 0x10) != 0) && (presc != 0)) - { - /* ADC34CLK clock frequency is derived from PLL clock */ - RCC_Clocks->ADC34CLK_Frequency = pllclk / presc; - } - else - { - /* ADC34CLK clock frequency is AHB clock */ - RCC_Clocks->ADC34CLK_Frequency = RCC_Clocks->SYSCLK_Frequency; - } - - /* I2C1CLK clock frequency */ - if((RCC->CFGR3 & RCC_CFGR3_I2C1SW) != RCC_CFGR3_I2C1SW) - { - /* I2C1 Clock is HSI Osc. */ - RCC_Clocks->I2C1CLK_Frequency = HSI_VALUE; - } - else - { - /* I2C1 Clock is System Clock */ - RCC_Clocks->I2C1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency; - } - - /* I2C2CLK clock frequency */ - if((RCC->CFGR3 & RCC_CFGR3_I2C2SW) != RCC_CFGR3_I2C2SW) - { - /* I2C2 Clock is HSI Osc. */ - RCC_Clocks->I2C2CLK_Frequency = HSI_VALUE; - } - else - { - /* I2C2 Clock is System Clock */ - RCC_Clocks->I2C2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency; - } - - /* I2C3CLK clock frequency */ - if((RCC->CFGR3 & RCC_CFGR3_I2C3SW) != RCC_CFGR3_I2C3SW) - { - /* I2C3 Clock is HSI Osc. */ - RCC_Clocks->I2C3CLK_Frequency = HSI_VALUE; - } - else - { - /* I2C3 Clock is System Clock */ - RCC_Clocks->I2C3CLK_Frequency = RCC_Clocks->SYSCLK_Frequency; - } - - /* TIM1CLK clock frequency */ - if(((RCC->CFGR3 & RCC_CFGR3_TIM1SW) == RCC_CFGR3_TIM1SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \ - && (apb2presc == ahbpresc)) - { - /* TIM1 Clock is 2 * pllclk */ - RCC_Clocks->TIM1CLK_Frequency = pllclk * 2; - } - else - { - /* TIM1 Clock is APB2 clock. */ - RCC_Clocks->TIM1CLK_Frequency = RCC_Clocks->PCLK2_Frequency; - } - - /* TIM1CLK clock frequency */ - if(((RCC->CFGR3 & RCC_CFGR3_HRTIM1SW) == RCC_CFGR3_HRTIM1SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \ - && (apb2presc == ahbpresc)) - { - /* HRTIM1 Clock is 2 * pllclk */ - RCC_Clocks->HRTIM1CLK_Frequency = pllclk * 2; - } - else - { - /* HRTIM1 Clock is APB2 clock. */ - RCC_Clocks->HRTIM1CLK_Frequency = RCC_Clocks->PCLK2_Frequency; - } - - /* TIM8CLK clock frequency */ - if(((RCC->CFGR3 & RCC_CFGR3_TIM8SW) == RCC_CFGR3_TIM8SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \ - && (apb2presc == ahbpresc)) - { - /* TIM8 Clock is 2 * pllclk */ - RCC_Clocks->TIM8CLK_Frequency = pllclk * 2; - } - else - { - /* TIM8 Clock is APB2 clock. */ - RCC_Clocks->TIM8CLK_Frequency = RCC_Clocks->PCLK2_Frequency; - } - - /* TIM15CLK clock frequency */ - if(((RCC->CFGR3 & RCC_CFGR3_TIM15SW) == RCC_CFGR3_TIM15SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \ - && (apb2presc == ahbpresc)) - { - /* TIM15 Clock is 2 * pllclk */ - RCC_Clocks->TIM15CLK_Frequency = pllclk * 2; - } - else - { - /* TIM15 Clock is APB2 clock. */ - RCC_Clocks->TIM15CLK_Frequency = RCC_Clocks->PCLK2_Frequency; - } - - /* TIM16CLK clock frequency */ - if(((RCC->CFGR3 & RCC_CFGR3_TIM16SW) == RCC_CFGR3_TIM16SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \ - && (apb2presc == ahbpresc)) - { - /* TIM16 Clock is 2 * pllclk */ - RCC_Clocks->TIM16CLK_Frequency = pllclk * 2; - } - else - { - /* TIM16 Clock is APB2 clock. */ - RCC_Clocks->TIM16CLK_Frequency = RCC_Clocks->PCLK2_Frequency; - } - - /* TIM17CLK clock frequency */ - if(((RCC->CFGR3 & RCC_CFGR3_TIM17SW) == RCC_CFGR3_TIM17SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \ - && (apb2presc == ahbpresc)) - { - /* TIM17 Clock is 2 * pllclk */ - RCC_Clocks->TIM17CLK_Frequency = pllclk * 2; - } - else - { - /* TIM17 Clock is APB2 clock. */ - RCC_Clocks->TIM16CLK_Frequency = RCC_Clocks->PCLK2_Frequency; - } - - /* USART1CLK clock frequency */ - if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == 0x0) - { -#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F301x8) || defined(STM32F302x8) - /* USART1 Clock is PCLK1 instead of PCLK2 (limitation described in the - STM32F302/01/34 x4/x6/x8 respective erratasheets) */ - RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK1_Frequency; -#else - /* USART Clock is PCLK2 */ - RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK2_Frequency; -#endif - } - else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_0) - { - /* USART Clock is System Clock */ - RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency; - } - else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_1) - { - /* USART Clock is LSE Osc. */ - RCC_Clocks->USART1CLK_Frequency = LSE_VALUE; - } - else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW) - { - /* USART Clock is HSI Osc. */ - RCC_Clocks->USART1CLK_Frequency = HSI_VALUE; - } - - /* USART2CLK clock frequency */ - if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == 0x0) - { - /* USART Clock is PCLK */ - RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->PCLK1_Frequency; - } - else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_0) - { - /* USART Clock is System Clock */ - RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency; - } - else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_1) - { - /* USART Clock is LSE Osc. */ - RCC_Clocks->USART2CLK_Frequency = LSE_VALUE; - } - else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW) - { - /* USART Clock is HSI Osc. */ - RCC_Clocks->USART2CLK_Frequency = HSI_VALUE; - } - - /* USART3CLK clock frequency */ - if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == 0x0) - { - /* USART Clock is PCLK */ - RCC_Clocks->USART3CLK_Frequency = RCC_Clocks->PCLK1_Frequency; - } - else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW_0) - { - /* USART Clock is System Clock */ - RCC_Clocks->USART3CLK_Frequency = RCC_Clocks->SYSCLK_Frequency; - } - else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW_1) - { - /* USART Clock is LSE Osc. */ - RCC_Clocks->USART3CLK_Frequency = LSE_VALUE; - } - else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW) - { - /* USART Clock is HSI Osc. */ - RCC_Clocks->USART3CLK_Frequency = HSI_VALUE; - } - - /* UART4CLK clock frequency */ - if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == 0x0) - { - /* USART Clock is PCLK */ - RCC_Clocks->UART4CLK_Frequency = RCC_Clocks->PCLK1_Frequency; - } - else if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == RCC_CFGR3_UART4SW_0) - { - /* USART Clock is System Clock */ - RCC_Clocks->UART4CLK_Frequency = RCC_Clocks->SYSCLK_Frequency; - } - else if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == RCC_CFGR3_UART4SW_1) - { - /* USART Clock is LSE Osc. */ - RCC_Clocks->UART4CLK_Frequency = LSE_VALUE; - } - else if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == RCC_CFGR3_UART4SW) - { - /* USART Clock is HSI Osc. */ - RCC_Clocks->UART4CLK_Frequency = HSI_VALUE; - } - - /* UART5CLK clock frequency */ - if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == 0x0) - { - /* USART Clock is PCLK */ - RCC_Clocks->UART5CLK_Frequency = RCC_Clocks->PCLK1_Frequency; - } - else if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == RCC_CFGR3_UART5SW_0) - { - /* USART Clock is System Clock */ - RCC_Clocks->UART5CLK_Frequency = RCC_Clocks->SYSCLK_Frequency; - } - else if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == RCC_CFGR3_UART5SW_1) - { - /* USART Clock is LSE Osc. */ - RCC_Clocks->UART5CLK_Frequency = LSE_VALUE; - } - else if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == RCC_CFGR3_UART5SW) - { - /* USART Clock is HSI Osc. */ - RCC_Clocks->UART5CLK_Frequency = HSI_VALUE; - } -} - -/** - * @} - */ - -/** @defgroup RCC_Group3 Peripheral clocks configuration functions - * @brief Peripheral clocks configuration functions - * -@verbatim - =============================================================================== - ##### Peripheral clocks configuration functions ##### - =============================================================================== - [..] This section provide functions allowing to configure the Peripheral clocks. - (#) The RTC clock which is derived from the LSE, LSI or HSE_Div32 - (HSE divided by 32). - (#) After restart from Reset or wakeup from STANDBY, all peripherals are - off except internal SRAM, Flash and SWD. Before to start using - a peripheral you have to enable its interface clock. You can do this - using RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() - and RCC_APB1PeriphClockCmd() functions. - (#) To reset the peripherals configuration (to the default state after - device reset) you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() - and RCC_APB1PeriphResetCmd() functions. -@endverbatim - * @{ - */ - -/** - * @brief Configures the ADC clock (ADCCLK). - * @param RCC_PLLCLK: defines the ADC clock divider. This clock is derived from - * the PLL Clock. - * This parameter can be one of the following values: - * @arg RCC_ADC12PLLCLK_OFF: ADC12 clock disabled - * @arg RCC_ADC12PLLCLK_Div1: ADC12 clock = PLLCLK/1 - * @arg RCC_ADC12PLLCLK_Div2: ADC12 clock = PLLCLK/2 - * @arg RCC_ADC12PLLCLK_Div4: ADC12 clock = PLLCLK/4 - * @arg RCC_ADC12PLLCLK_Div6: ADC12 clock = PLLCLK/6 - * @arg RCC_ADC12PLLCLK_Div8: ADC12 clock = PLLCLK/8 - * @arg RCC_ADC12PLLCLK_Div10: ADC12 clock = PLLCLK/10 - * @arg RCC_ADC12PLLCLK_Div12: ADC12 clock = PLLCLK/12 - * @arg RCC_ADC12PLLCLK_Div16: ADC12 clock = PLLCLK/16 - * @arg RCC_ADC12PLLCLK_Div32: ADC12 clock = PLLCLK/32 - * @arg RCC_ADC12PLLCLK_Div64: ADC12 clock = PLLCLK/64 - * @arg RCC_ADC12PLLCLK_Div128: ADC12 clock = PLLCLK/128 - * @arg RCC_ADC12PLLCLK_Div256: ADC12 clock = PLLCLK/256 - * @arg RCC_ADC34PLLCLK_OFF: ADC34 clock disabled - * @arg RCC_ADC34PLLCLK_Div1: ADC34 clock = PLLCLK/1 - * @arg RCC_ADC34PLLCLK_Div2: ADC34 clock = PLLCLK/2 - * @arg RCC_ADC34PLLCLK_Div4: ADC34 clock = PLLCLK/4 - * @arg RCC_ADC34PLLCLK_Div6: ADC34 clock = PLLCLK/6 - * @arg RCC_ADC34PLLCLK_Div8: ADC34 clock = PLLCLK/8 - * @arg RCC_ADC34PLLCLK_Div10: ADC34 clock = PLLCLK/10 - * @arg RCC_ADC34PLLCLK_Div12: ADC34 clock = PLLCLK/12 - * @arg RCC_ADC34PLLCLK_Div16: ADC34 clock = PLLCLK/16 - * @arg RCC_ADC34PLLCLK_Div32: ADC34 clock = PLLCLK/32 - * @arg RCC_ADC34PLLCLK_Div64: ADC34 clock = PLLCLK/64 - * @arg RCC_ADC34PLLCLK_Div128: ADC34 clock = PLLCLK/128 - * @arg RCC_ADC34PLLCLK_Div256: ADC34 clock = PLLCLK/256 - * @retval None - */ -void RCC_ADCCLKConfig(uint32_t RCC_PLLCLK) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RCC_ADCCLK(RCC_PLLCLK)); - - tmp = (RCC_PLLCLK >> 28); - - /* Clears ADCPRE34 bits */ - if (tmp != 0) - { - RCC->CFGR2 &= ~RCC_CFGR2_ADCPRE34; - } - /* Clears ADCPRE12 bits */ - else - { - RCC->CFGR2 &= ~RCC_CFGR2_ADCPRE12; - } - /* Set ADCPRE bits according to RCC_PLLCLK value */ - RCC->CFGR2 |= RCC_PLLCLK; -} - -/** - * @brief Configures the I2C clock (I2CCLK). - * @param RCC_I2CCLK: defines the I2C clock source. This clock is derived - * from the HSI or System clock. - * This parameter can be one of the following values: - * @arg RCC_I2CxCLK_HSI: I2Cx clock = HSI - * @arg RCC_I2CxCLK_SYSCLK: I2Cx clock = System Clock - * (x can be 1 or 2 or 3). - * @retval None - */ -void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RCC_I2CCLK(RCC_I2CCLK)); - - tmp = (RCC_I2CCLK >> 28); - - /* Clear I2CSW bit */ - switch (tmp) - { - case 0x00: - RCC->CFGR3 &= ~RCC_CFGR3_I2C1SW; - break; - case 0x01: - RCC->CFGR3 &= ~RCC_CFGR3_I2C2SW; - break; - case 0x02: - RCC->CFGR3 &= ~RCC_CFGR3_I2C3SW; - break; - default: - break; - } - - /* Set I2CSW bits according to RCC_I2CCLK value */ - RCC->CFGR3 |= RCC_I2CCLK; -} - -/** - * @brief Configures the TIMx clock sources(TIMCLK). - * @note The configuration of the TIMx clock source is only possible when the - * SYSCLK = PLL and HCLK and PCLK2 clocks are not divided in respect to SYSCLK - * @note If one of the previous conditions is missed, the TIM clock source - * configuration is lost and calling again this function becomes mandatory. - * @param RCC_TIMCLK: defines the TIMx clock source. - * This parameter can be one of the following values: - * @arg RCC_TIMxCLK_HCLK: TIMx clock = APB high speed clock (doubled frequency - * when prescaled) - * @arg RCC_TIMxCLK_PLLCLK: TIMx clock = PLL output (running up to 144 MHz) - * (x can be 1, 8, 15, 16, 17). - * @retval None - */ -void RCC_TIMCLKConfig(uint32_t RCC_TIMCLK) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RCC_TIMCLK(RCC_TIMCLK)); - - tmp = (RCC_TIMCLK >> 28); - - /* Clear TIMSW bit */ - - switch (tmp) - { - case 0x00: - RCC->CFGR3 &= ~RCC_CFGR3_TIM1SW; - break; - case 0x01: - RCC->CFGR3 &= ~RCC_CFGR3_TIM8SW; - break; - case 0x02: - RCC->CFGR3 &= ~RCC_CFGR3_TIM15SW; - break; - case 0x03: - RCC->CFGR3 &= ~RCC_CFGR3_TIM16SW; - break; - case 0x04: - RCC->CFGR3 &= ~RCC_CFGR3_TIM17SW; - break; - default: - break; - } - - /* Set I2CSW bits according to RCC_TIMCLK value */ - RCC->CFGR3 |= RCC_TIMCLK; -} - -/** - * @brief Configures the HRTIM1 clock sources(HRTIM1CLK). - * @note The configuration of the HRTIM1 clock source is only possible when the - * SYSCLK = PLL and HCLK and PCLK2 clocks are not divided in respect to SYSCLK - * @note If one of the previous conditions is missed, the TIM clock source - * configuration is lost and calling again this function becomes mandatory. - * @param RCC_HRTIMCLK: defines the TIMx clock source. - * This parameter can be one of the following values: - * @arg RCC_HRTIM1CLK_HCLK: TIMx clock = APB high speed clock (doubled frequency - * when prescaled) - * @arg RCC_HRTIM1CLK_PLLCLK: TIMx clock = PLL output (running up to 144 MHz) - * (x can be 1 or 8). - * @retval None - */ -void RCC_HRTIM1CLKConfig(uint32_t RCC_HRTIMCLK) -{ - /* Check the parameters */ - assert_param(IS_RCC_HRTIMCLK(RCC_HRTIMCLK)); - - /* Clear HRTIMSW bit */ - RCC->CFGR3 &= ~RCC_CFGR3_HRTIM1SW; - - /* Set HRTIMSW bits according to RCC_HRTIMCLK value */ - RCC->CFGR3 |= RCC_HRTIMCLK; -} - -/** - * @brief Configures the USART clock (USARTCLK). - * @param RCC_USARTCLK: defines the USART clock source. This clock is derived - * from the HSI or System clock. - * This parameter can be one of the following values: - * @arg RCC_USARTxCLK_PCLK: USART clock = APB Clock (PCLK) - * @arg RCC_USARTxCLK_SYSCLK: USART clock = System Clock - * @arg RCC_USARTxCLK_LSE: USART clock = LSE Clock - * @arg RCC_USARTxCLK_HSI: USART clock = HSI Clock - * (x can be 1, 2, 3, 4 or 5). - * @retval None - */ -void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RCC_USARTCLK(RCC_USARTCLK)); - - tmp = (RCC_USARTCLK >> 28); - - /* Clear USARTSW[1:0] bit */ - switch (tmp) - { - case 0x01: /* clear USART1SW */ - RCC->CFGR3 &= ~RCC_CFGR3_USART1SW; - break; - case 0x02: /* clear USART2SW */ - RCC->CFGR3 &= ~RCC_CFGR3_USART2SW; - break; - case 0x03: /* clear USART3SW */ - RCC->CFGR3 &= ~RCC_CFGR3_USART3SW; - break; - case 0x04: /* clear UART4SW */ - RCC->CFGR3 &= ~RCC_CFGR3_UART4SW; - break; - case 0x05: /* clear UART5SW */ - RCC->CFGR3 &= ~RCC_CFGR3_UART5SW; - break; - default: - break; - } - - /* Set USARTSW bits according to RCC_USARTCLK value */ - RCC->CFGR3 |= RCC_USARTCLK; -} - -/** - * @brief Configures the USB clock (USBCLK). - * @param RCC_USBCLKSource: specifies the USB clock source. This clock is - * derived from the PLL output. - * This parameter can be one of the following values: - * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB - * clock source - * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source - * @retval None - */ -void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource)); - - *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource; -} - -/** - * @brief Configures the RTC clock (RTCCLK). - * @note As the RTC clock configuration bits are in the Backup domain and write - * access is denied to this domain after reset, you have to enable write - * access using PWR_BackupAccessCmd(ENABLE) function before to configure - * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it can't be changed unless the RTC - * is reset using RCC_BackupResetCmd function, or by a Power On Reset (POR) - * - * @param RCC_RTCCLKSource: specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock - * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock - * @arg RCC_RTCCLKSource_HSE_Div32: HSE divided by 32 selected as RTC clock - * - * @note If the LSE or LSI is used as RTC clock source, the RTC continues to - * work in STOP and STANDBY modes, and can be used as wakeup source. - * However, when the HSE clock is used as RTC clock source, the RTC - * cannot be used in STOP and STANDBY modes. - * @note The maximum input clock frequency for RTC is 2MHz (when using HSE as - * RTC clock source). - * @retval None - */ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); - - /* Select the RTC clock source */ - RCC->BDCR |= RCC_RTCCLKSource; -} - -/** - * @brief Configures the I2S clock source (I2SCLK). - * @note This function must be called before enabling the SPI2 and SPI3 clocks. - * @param RCC_I2SCLKSource: specifies the I2S clock source. - * This parameter can be one of the following values: - * @arg RCC_I2S2CLKSource_SYSCLK: SYSCLK clock used as I2S clock source - * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin - * used as I2S clock source - * @retval None - */ -void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource)); - - *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource; -} - -/** - * @brief Enables or disables the RTC clock. - * @note This function must be used only after the RTC clock source was selected - * using the RCC_RTCCLKConfig function. - * @param NewState: new state of the RTC clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_RTCCLKCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; -} - -/** - * @brief Forces or releases the Backup domain reset. - * @note This function resets the RTC peripheral (including the backup registers) - * and the RTC clock source selection in RCC_BDCR register. - * @param NewState: new state of the Backup domain reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_BackupResetCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the AHB peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHBPeriph_GPIOA - * @arg RCC_AHBPeriph_GPIOB - * @arg RCC_AHBPeriph_GPIOC - * @arg RCC_AHBPeriph_GPIOD - * @arg RCC_AHBPeriph_GPIOE - * @arg RCC_AHBPeriph_GPIOF - * @arg RCC_AHBPeriph_TS - * @arg RCC_AHBPeriph_CRC - * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode) - * @arg RCC_AHBPeriph_SRAM - * @arg RCC_AHBPeriph_DMA2 - * @arg RCC_AHBPeriph_DMA1 - * @arg RCC_AHBPeriph_ADC34 - * @arg RCC_AHBPeriph_ADC12 - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHBENR |= RCC_AHBPeriph; - } - else - { - RCC->AHBENR &= ~RCC_AHBPeriph; - } -} - -/** - * @brief Enables or disables the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_SYSCFG - * @arg RCC_APB2Periph_SPI1 - * @arg RCC_APB2Periph_USART1 - * @arg RCC_APB2Periph_TIM15 - * @arg RCC_APB2Periph_TIM16 - * @arg RCC_APB2Periph_TIM17 - * @arg RCC_APB2Periph_TIM1 - * @arg RCC_APB2Periph_TIM8 - * @arg RCC_APB2Periph_HRTIM1 - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB2ENR |= RCC_APB2Periph; - } - else - { - RCC->APB2ENR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2 - * @arg RCC_APB1Periph_TIM3 - * @arg RCC_APB1Periph_TIM4 - * @arg RCC_APB1Periph_TIM6 - * @arg RCC_APB1Periph_TIM7 - * @arg RCC_APB1Periph_WWDG - * @arg RCC_APB1Periph_SPI2 - * @arg RCC_APB1Periph_SPI3 - * @arg RCC_APB1Periph_USART2 - * @arg RCC_APB1Periph_USART3 - * @arg RCC_APB1Periph_UART4 - * @arg RCC_APB1Periph_UART5 - * @arg RCC_APB1Periph_I2C1 - * @arg RCC_APB1Periph_I2C2 - * @arg RCC_APB1Periph_USB - * @arg RCC_APB1Periph_CAN1 - * @arg RCC_APB1Periph_PWR - * @arg RCC_APB1Periph_DAC1 - * @arg RCC_APB1Periph_DAC2 - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB1ENR |= RCC_APB1Periph; - } - else - { - RCC->APB1ENR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Forces or releases AHB peripheral reset. - * @param RCC_AHBPeriph: specifies the AHB peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_AHBPeriph_GPIOA - * @arg RCC_AHBPeriph_GPIOB - * @arg RCC_AHBPeriph_GPIOC - * @arg RCC_AHBPeriph_GPIOD - * @arg RCC_AHBPeriph_GPIOE - * @arg RCC_AHBPeriph_GPIOF - * @arg RCC_AHBPeriph_TS - * @arg RCC_AHBPeriph_ADC34 - * @arg RCC_AHBPeriph_ADC12 - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB_RST_PERIPH(RCC_AHBPeriph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHBRSTR |= RCC_AHBPeriph; - } - else - { - RCC->AHBRSTR &= ~RCC_AHBPeriph; - } -} - -/** - * @brief Forces or releases High Speed APB (APB2) peripheral reset. - * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_SYSCFG - * @arg RCC_APB2Periph_SPI1 - * @arg RCC_APB2Periph_USART1 - * @arg RCC_APB2Periph_TIM15 - * @arg RCC_APB2Periph_TIM16 - * @arg RCC_APB2Periph_TIM17 - * @arg RCC_APB2Periph_TIM1 - * @arg RCC_APB2Periph_TIM8 - * @arg RCC_APB2Periph_HRTIM1 - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB2RSTR |= RCC_APB2Periph; - } - else - { - RCC->APB2RSTR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Forces or releases Low Speed APB (APB1) peripheral reset. - * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2 - * @arg RCC_APB1Periph_TIM3 - * @arg RCC_APB1Periph_TIM4 - * @arg RCC_APB1Periph_TIM6 - * @arg RCC_APB1Periph_TIM7 - * @arg RCC_APB1Periph_WWDG - * @arg RCC_APB1Periph_SPI2 - * @arg RCC_APB1Periph_SPI3 - * @arg RCC_APB1Periph_USART2 - * @arg RCC_APB1Periph_USART3 - * @arg RCC_APB1Periph_UART4 - * @arg RCC_APB1Periph_UART5 - * @arg RCC_APB1Periph_I2C1 - * @arg RCC_APB1Periph_I2C2 - * @arg RCC_APB1Periph_I2C3 - * @arg RCC_APB1Periph_USB - * @arg RCC_APB1Periph_CAN1 - * @arg RCC_APB1Periph_PWR - * @arg RCC_APB1Periph_DAC - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB1RSTR |= RCC_APB1Periph; - } - else - { - RCC->APB1RSTR &= ~RCC_APB1Periph; - } -} - -/** - * @} - */ - -/** @defgroup RCC_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified RCC interrupts. - * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled - * and if the HSE clock fails, the CSS interrupt occurs and an NMI is - * automatically generated. The NMI will be executed indefinitely, and - * since NMI has higher priority than any other IRQ (and main program) - * the application will be stacked in the NMI ISR unless the CSS interrupt - * pending bit is cleared. - * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @param NewState: new state of the specified RCC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_IT(RCC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Perform Byte access to RCC_CIR[13:8] bits to enable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; - } - else - { - /* Perform Byte access to RCC_CIR[13:8] bits to disable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; - } -} - -/** - * @brief Checks whether the specified RCC flag is set or not. - * @param RCC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready - * @arg RCC_FLAG_PLLRDY: PLL clock ready - * @arg RCC_FLAG_MCOF: MCO Flag - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready - * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset - * @arg RCC_FLAG_PINRST: Pin reset - * @arg RCC_FLAG_PORRST: POR/PDR reset - * @arg RCC_FLAG_SFTRST: Software reset - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset - * @arg RCC_FLAG_LPWRRST: Low Power reset - * @retval The new state of RCC_FLAG (SET or RESET). - */ -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) -{ - uint32_t tmp = 0; - uint32_t statusreg = 0; - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_FLAG(RCC_FLAG)); - - /* Get the RCC register index */ - tmp = RCC_FLAG >> 5; - - if (tmp == 0) /* The flag to check is in CR register */ - { - statusreg = RCC->CR; - } - else if (tmp == 1) /* The flag to check is in BDCR register */ - { - statusreg = RCC->BDCR; - } - else if (tmp == 4) /* The flag to check is in CFGR register */ - { - statusreg = RCC->CFGR; - } - else /* The flag to check is in CSR register */ - { - statusreg = RCC->CSR; - } - - /* Get the flag position */ - tmp = RCC_FLAG & FLAG_MASK; - - if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the RCC reset flags. - * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, - * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST. - * @param None - * @retval None - */ -void RCC_ClearFlag(void) -{ - /* Set RMVF bit to clear the reset flags */ - RCC->CSR |= RCC_CSR_RMVF; -} - -/** - * @brief Checks whether the specified RCC interrupt has occurred or not. - * @param RCC_IT: specifies the RCC interrupt source to check. - * This parameter can be one of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval The new state of RCC_IT (SET or RESET). - */ -ITStatus RCC_GetITStatus(uint8_t RCC_IT) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_GET_IT(RCC_IT)); - - /* Check the status of the specified RCC interrupt */ - if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the RCC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the RCC's interrupt pending bits. - * @param RCC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval None - */ -void RCC_ClearITPendingBit(uint8_t RCC_IT) -{ - /* Check the parameters */ - assert_param(IS_RCC_CLEAR_IT(RCC_IT)); - - /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt - pending bits */ - *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_rcc.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,709 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_rcc.h - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file contains all the functions prototypes for the RCC - * firmware library. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F30x_RCC_H -#define __STM32F30x_RCC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -typedef struct -{ - uint32_t SYSCLK_Frequency; - uint32_t HCLK_Frequency; - uint32_t PCLK1_Frequency; - uint32_t PCLK2_Frequency; - uint32_t ADC12CLK_Frequency; - uint32_t ADC34CLK_Frequency; - uint32_t I2C1CLK_Frequency; - uint32_t I2C2CLK_Frequency; - uint32_t I2C3CLK_Frequency; - uint32_t TIM1CLK_Frequency; - uint32_t HRTIM1CLK_Frequency; - uint32_t TIM8CLK_Frequency; - uint32_t USART1CLK_Frequency; - uint32_t USART2CLK_Frequency; - uint32_t USART3CLK_Frequency; - uint32_t UART4CLK_Frequency; - uint32_t UART5CLK_Frequency; - uint32_t TIM15CLK_Frequency; - uint32_t TIM16CLK_Frequency; - uint32_t TIM17CLK_Frequency; -}RCC_ClocksTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Constants - * @{ - */ - -/** @defgroup RCC_HSE_configuration - * @{ - */ - -#define RCC_HSE_OFF ((uint8_t)0x00) -#define RCC_HSE_ON ((uint8_t)0x01) -#define RCC_HSE_Bypass ((uint8_t)0x05) -#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ - ((HSE) == RCC_HSE_Bypass)) - -/** - * @} - */ - -/** @defgroup RCC_PLL_Clock_Source - * @{ - */ - -#define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2 -#define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_PREDIV1 - -#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ - ((SOURCE) == RCC_PLLSource_PREDIV1)) -/** - * @} - */ - -/** @defgroup RCC_PLL_Multiplication_Factor - * @{ - */ - -#define RCC_PLLMul_2 RCC_CFGR_PLLMULL2 -#define RCC_PLLMul_3 RCC_CFGR_PLLMULL3 -#define RCC_PLLMul_4 RCC_CFGR_PLLMULL4 -#define RCC_PLLMul_5 RCC_CFGR_PLLMULL5 -#define RCC_PLLMul_6 RCC_CFGR_PLLMULL6 -#define RCC_PLLMul_7 RCC_CFGR_PLLMULL7 -#define RCC_PLLMul_8 RCC_CFGR_PLLMULL8 -#define RCC_PLLMul_9 RCC_CFGR_PLLMULL9 -#define RCC_PLLMul_10 RCC_CFGR_PLLMULL10 -#define RCC_PLLMul_11 RCC_CFGR_PLLMULL11 -#define RCC_PLLMul_12 RCC_CFGR_PLLMULL12 -#define RCC_PLLMul_13 RCC_CFGR_PLLMULL13 -#define RCC_PLLMul_14 RCC_CFGR_PLLMULL14 -#define RCC_PLLMul_15 RCC_CFGR_PLLMULL15 -#define RCC_PLLMul_16 RCC_CFGR_PLLMULL16 -#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ - ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ - ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ - ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ - ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ - ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ - ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ - ((MUL) == RCC_PLLMul_16)) -/** - * @} - */ - -/** @defgroup RCC_PREDIV1_division_factor - * @{ - */ -#define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1 -#define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2 -#define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3 -#define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4 -#define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5 -#define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6 -#define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7 -#define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8 -#define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9 -#define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10 -#define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11 -#define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12 -#define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13 -#define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14 -#define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15 -#define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16 - -#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ - ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ - ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ - ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ - ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ - ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ - ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ - ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source - * @{ - */ - -#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI -#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE -#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL -#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ - ((SOURCE) == RCC_SYSCLKSource_HSE) || \ - ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) -/** - * @} - */ - -/** @defgroup RCC_AHB_Clock_Source - * @{ - */ - -#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1 -#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2 -#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4 -#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8 -#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16 -#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64 -#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128 -#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256 -#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512 -#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ - ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ - ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ - ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ - ((HCLK) == RCC_SYSCLK_Div512)) -/** - * @} - */ - -/** @defgroup RCC_APB1_APB2_clock_source - * @{ - */ - -#define RCC_HCLK_Div1 ((uint32_t)0x00000000) -#define RCC_HCLK_Div2 ((uint32_t)0x00000400) -#define RCC_HCLK_Div4 ((uint32_t)0x00000500) -#define RCC_HCLK_Div8 ((uint32_t)0x00000600) -#define RCC_HCLK_Div16 ((uint32_t)0x00000700) -#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ - ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ - ((PCLK) == RCC_HCLK_Div16)) -/** - * @} - */ - -/** @defgroup RCC_ADC_clock_source - * @{ - */ - -/* ADC1 & ADC2 */ -#define RCC_ADC12PLLCLK_OFF ((uint32_t)0x00000000) -#define RCC_ADC12PLLCLK_Div1 ((uint32_t)0x00000100) -#define RCC_ADC12PLLCLK_Div2 ((uint32_t)0x00000110) -#define RCC_ADC12PLLCLK_Div4 ((uint32_t)0x00000120) -#define RCC_ADC12PLLCLK_Div6 ((uint32_t)0x00000130) -#define RCC_ADC12PLLCLK_Div8 ((uint32_t)0x00000140) -#define RCC_ADC12PLLCLK_Div10 ((uint32_t)0x00000150) -#define RCC_ADC12PLLCLK_Div12 ((uint32_t)0x00000160) -#define RCC_ADC12PLLCLK_Div16 ((uint32_t)0x00000170) -#define RCC_ADC12PLLCLK_Div32 ((uint32_t)0x00000180) -#define RCC_ADC12PLLCLK_Div64 ((uint32_t)0x00000190) -#define RCC_ADC12PLLCLK_Div128 ((uint32_t)0x000001A0) -#define RCC_ADC12PLLCLK_Div256 ((uint32_t)0x000001B0) - -/* ADC3 & ADC4 */ -#define RCC_ADC34PLLCLK_OFF ((uint32_t)0x10000000) -#define RCC_ADC34PLLCLK_Div1 ((uint32_t)0x10002000) -#define RCC_ADC34PLLCLK_Div2 ((uint32_t)0x10002200) -#define RCC_ADC34PLLCLK_Div4 ((uint32_t)0x10002400) -#define RCC_ADC34PLLCLK_Div6 ((uint32_t)0x10002600) -#define RCC_ADC34PLLCLK_Div8 ((uint32_t)0x10002800) -#define RCC_ADC34PLLCLK_Div10 ((uint32_t)0x10002A00) -#define RCC_ADC34PLLCLK_Div12 ((uint32_t)0x10002C00) -#define RCC_ADC34PLLCLK_Div16 ((uint32_t)0x10002E00) -#define RCC_ADC34PLLCLK_Div32 ((uint32_t)0x10003000) -#define RCC_ADC34PLLCLK_Div64 ((uint32_t)0x10003200) -#define RCC_ADC34PLLCLK_Div128 ((uint32_t)0x10003400) -#define RCC_ADC34PLLCLK_Div256 ((uint32_t)0x10003600) - -#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_Div1) || \ - ((ADCCLK) == RCC_ADC12PLLCLK_Div2) || ((ADCCLK) == RCC_ADC12PLLCLK_Div4) || \ - ((ADCCLK) == RCC_ADC12PLLCLK_Div6) || ((ADCCLK) == RCC_ADC12PLLCLK_Div8) || \ - ((ADCCLK) == RCC_ADC12PLLCLK_Div10) || ((ADCCLK) == RCC_ADC12PLLCLK_Div12) || \ - ((ADCCLK) == RCC_ADC12PLLCLK_Div16) || ((ADCCLK) == RCC_ADC12PLLCLK_Div32) || \ - ((ADCCLK) == RCC_ADC12PLLCLK_Div64) || ((ADCCLK) == RCC_ADC12PLLCLK_Div128) || \ - ((ADCCLK) == RCC_ADC12PLLCLK_Div256) || ((ADCCLK) == RCC_ADC34PLLCLK_OFF) || \ - ((ADCCLK) == RCC_ADC34PLLCLK_Div1) || ((ADCCLK) == RCC_ADC34PLLCLK_Div2) || \ - ((ADCCLK) == RCC_ADC34PLLCLK_Div4) || ((ADCCLK) == RCC_ADC34PLLCLK_Div6) || \ - ((ADCCLK) == RCC_ADC34PLLCLK_Div8) || ((ADCCLK) == RCC_ADC34PLLCLK_Div10) || \ - ((ADCCLK) == RCC_ADC34PLLCLK_Div12) || ((ADCCLK) == RCC_ADC34PLLCLK_Div16) || \ - ((ADCCLK) == RCC_ADC34PLLCLK_Div32) || ((ADCCLK) == RCC_ADC34PLLCLK_Div64) || \ - ((ADCCLK) == RCC_ADC34PLLCLK_Div128) || ((ADCCLK) == RCC_ADC34PLLCLK_Div256)) - -/** - * @} - */ - -/** @defgroup RCC_TIM_clock_source - * @{ - */ - -#define RCC_TIM1CLK_HCLK ((uint32_t)0x00000000) -#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW - -#define RCC_TIM8CLK_HCLK ((uint32_t)0x10000000) -#define RCC_TIM8CLK_PLLCLK ((uint32_t)0x10000200) - -#define RCC_TIM15CLK_HCLK ((uint32_t)0x20000000) -#define RCC_TIM15CLK_PLLCLK ((uint32_t)0x20000400) - -#define RCC_TIM16CLK_HCLK ((uint32_t)0x30000000) -#define RCC_TIM16CLK_PLLCLK ((uint32_t)0x30000800) - -#define RCC_TIM17CLK_HCLK ((uint32_t)0x40000000) -#define RCC_TIM17CLK_PLLCLK ((uint32_t)0x40002000) - -#define IS_RCC_TIMCLK(TIMCLK) (((TIMCLK) == RCC_TIM1CLK_HCLK) || ((TIMCLK) == RCC_TIM1CLK_PLLCLK) || \ - ((TIMCLK) == RCC_TIM8CLK_HCLK) || ((TIMCLK) == RCC_TIM8CLK_PLLCLK) || \ - ((TIMCLK) == RCC_TIM15CLK_HCLK) || ((TIMCLK) == RCC_TIM15CLK_PLLCLK) || \ - ((TIMCLK) == RCC_TIM16CLK_HCLK) || ((TIMCLK) == RCC_TIM16CLK_PLLCLK) || \ - ((TIMCLK) == RCC_TIM17CLK_HCLK) || ((TIMCLK) == RCC_TIM17CLK_PLLCLK)) - -/** - * @} - */ - -/** @defgroup RCC_HRTIM_clock_source - * @{ - */ - -#define RCC_HRTIM1CLK_HCLK ((uint32_t)0x00000000) -#define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW - -#define IS_RCC_HRTIMCLK(HRTIMCLK) (((HRTIMCLK) == RCC_HRTIM1CLK_HCLK) || ((HRTIMCLK) == RCC_HRTIM1CLK_PLLCLK)) - -/** - * @} - */ - -/** @defgroup RCC_I2C_clock_source - * @{ - */ - -#define RCC_I2C1CLK_HSI ((uint32_t)0x00000000) -#define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW - -#define RCC_I2C2CLK_HSI ((uint32_t)0x10000000) -#define RCC_I2C2CLK_SYSCLK ((uint32_t)0x10000020) - -#define RCC_I2C3CLK_HSI ((uint32_t)0x20000000) -#define RCC_I2C3CLK_SYSCLK ((uint32_t)0x20000040) - -#define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK) || \ - ((I2CCLK) == RCC_I2C2CLK_HSI) || ((I2CCLK) == RCC_I2C2CLK_SYSCLK) || \ - ((I2CCLK) == RCC_I2C3CLK_HSI) || ((I2CCLK) == RCC_I2C3CLK_SYSCLK)) - -/** - * @} - */ - -/** @defgroup RCC_USART_clock_source - * @{ - */ - -#define RCC_USART1CLK_PCLK ((uint32_t)0x10000000) -#define RCC_USART1CLK_SYSCLK ((uint32_t)0x10000001) -#define RCC_USART1CLK_LSE ((uint32_t)0x10000002) -#define RCC_USART1CLK_HSI ((uint32_t)0x10000003) - -#define RCC_USART2CLK_PCLK ((uint32_t)0x20000000) -#define RCC_USART2CLK_SYSCLK ((uint32_t)0x20010000) -#define RCC_USART2CLK_LSE ((uint32_t)0x20020000) -#define RCC_USART2CLK_HSI ((uint32_t)0x20030000) - -#define RCC_USART3CLK_PCLK ((uint32_t)0x30000000) -#define RCC_USART3CLK_SYSCLK ((uint32_t)0x30040000) -#define RCC_USART3CLK_LSE ((uint32_t)0x30080000) -#define RCC_USART3CLK_HSI ((uint32_t)0x300C0000) - -#define RCC_UART4CLK_PCLK ((uint32_t)0x40000000) -#define RCC_UART4CLK_SYSCLK ((uint32_t)0x40100000) -#define RCC_UART4CLK_LSE ((uint32_t)0x40200000) -#define RCC_UART4CLK_HSI ((uint32_t)0x40300000) - -#define RCC_UART5CLK_PCLK ((uint32_t)0x50000000) -#define RCC_UART5CLK_SYSCLK ((uint32_t)0x50400000) -#define RCC_UART5CLK_LSE ((uint32_t)0x50800000) -#define RCC_UART5CLK_HSI ((uint32_t)0x50C00000) - -#define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \ - ((USARTCLK) == RCC_USART1CLK_LSE) || ((USARTCLK) == RCC_USART1CLK_HSI) ||\ - ((USARTCLK) == RCC_USART2CLK_PCLK) || ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \ - ((USARTCLK) == RCC_USART2CLK_LSE) || ((USARTCLK) == RCC_USART2CLK_HSI) || \ - ((USARTCLK) == RCC_USART3CLK_PCLK) || ((USARTCLK) == RCC_USART3CLK_SYSCLK) || \ - ((USARTCLK) == RCC_USART3CLK_LSE) || ((USARTCLK) == RCC_USART3CLK_HSI) || \ - ((USARTCLK) == RCC_UART4CLK_PCLK) || ((USARTCLK) == RCC_UART4CLK_SYSCLK) || \ - ((USARTCLK) == RCC_UART4CLK_LSE) || ((USARTCLK) == RCC_UART4CLK_HSI) || \ - ((USARTCLK) == RCC_UART5CLK_PCLK) || ((USARTCLK) == RCC_UART5CLK_SYSCLK) || \ - ((USARTCLK) == RCC_UART5CLK_LSE) || ((USARTCLK) == RCC_UART5CLK_HSI)) - -/** - * @} - */ - -/** @defgroup RCC_Interrupt_Source - * @{ - */ - -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_LSERDY ((uint8_t)0x02) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_CSS ((uint8_t)0x80) - -#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00)) - -#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ - ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ - ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) - - -#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00)) - -/** - * @} - */ - -/** @defgroup RCC_LSE_configuration - * @{ - */ - -#define RCC_LSE_OFF ((uint32_t)0x00000000) -#define RCC_LSE_ON RCC_BDCR_LSEON -#define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP)) -#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ - ((LSE) == RCC_LSE_Bypass)) -/** - * @} - */ - -/** @defgroup RCC_RTC_Clock_Source - * @{ - */ - -#define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE -#define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI -#define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE - -#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ - ((SOURCE) == RCC_RTCCLKSource_LSI) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div32)) -/** - * @} - */ - -/** @defgroup RCC_I2S_Clock_Source - * @{ - */ -#define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) -#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01) - -#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) - -/** @defgroup RCC_LSE_Drive_Configuration - * @{ - */ - -#define RCC_LSEDrive_Low ((uint32_t)0x00000000) -#define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0 -#define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1 -#define RCC_LSEDrive_High RCC_BDCR_LSEDRV -#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \ - ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High)) -/** - * @} - */ - -/** @defgroup RCC_AHB_Peripherals - * @{ - */ - -#define RCC_AHBPeriph_ADC34 RCC_AHBENR_ADC34EN -#define RCC_AHBPeriph_ADC12 RCC_AHBENR_ADC12EN -#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN -#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN -#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN -#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN -#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN -#define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN -#define RCC_AHBPeriph_TS RCC_AHBENR_TSEN -#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN -#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN -#define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN -#define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN -#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN - -#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xCE81FFA8) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xCE81FFFF) == 0x00) && ((PERIPH) != 0x00)) - -/** - * @} - */ - -/** @defgroup RCC_APB2_Peripherals - * @{ - */ - -#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN -#define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN -#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN -#define RCC_APB2Periph_TIM8 RCC_APB2ENR_TIM8EN -#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN -#define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN -#define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN -#define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN -#define RCC_APB2Periph_HRTIM1 RCC_APB2ENR_HRTIM1 - -#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xDFF887FE) == 0x00) && ((PERIPH) != 0x00)) - -/** - * @} - */ - -/** @defgroup RCC_APB1_Peripherals - * @{ - */ -#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN -#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN -#define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN -#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN -#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN -#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN -#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN -#define RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN -#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN -#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN -#define RCC_APB1Periph_UART4 RCC_APB1ENR_UART4EN -#define RCC_APB1Periph_UART5 RCC_APB1ENR_UART5EN -#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN -#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN -#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN -#define RCC_APB1Periph_CAN1 RCC_APB1ENR_CAN1EN -#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN -#define RCC_APB1Periph_DAC1 RCC_APB1ENR_DAC1EN -#define RCC_APB1Periph_I2C3 RCC_APB1ENR_I2C3EN -#define RCC_APB1Periph_DAC2 RCC_APB1ENR_DAC2EN -#define RCC_APB1Periph_DAC RCC_APB1Periph_DAC1 - - -#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x890137C8) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_MCO_Clock_Source - * @{ - */ - -#define RCC_MCOSource_NoClock ((uint8_t)0x00) -#define RCC_MCOSource_LSI ((uint8_t)0x02) -#define RCC_MCOSource_LSE ((uint8_t)0x03) -#define RCC_MCOSource_SYSCLK ((uint8_t)0x04) -#define RCC_MCOSource_HSI ((uint8_t)0x05) -#define RCC_MCOSource_HSE ((uint8_t)0x06) -#define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07) - -#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) ||((SOURCE) == RCC_MCOSource_SYSCLK) ||\ - ((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_HSE) || \ - ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE) || \ - ((SOURCE) == RCC_MCOSource_PLLCLK_Div2)) -/** - * @} - */ - -/** @defgroup RCC_MCOPrescaler - * @{ - */ - -#define RCC_MCOPrescaler_1 RCC_CFGR_MCO_PRE_1 -#define RCC_MCOPrescaler_2 RCC_CFGR_MCO_PRE_2 -#define RCC_MCOPrescaler_4 RCC_CFGR_MCO_PRE_4 -#define RCC_MCOPrescaler_8 RCC_CFGR_MCO_PRE_8 -#define RCC_MCOPrescaler_16 RCC_CFGR_MCO_PRE_16 -#define RCC_MCOPrescaler_32 RCC_CFGR_MCO_PRE_32 -#define RCC_MCOPrescaler_64 RCC_CFGR_MCO_PRE_64 -#define RCC_MCOPrescaler_128 RCC_CFGR_MCO_PRE_128 - -#define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1) || \ - ((PRESCALER) == RCC_MCOPrescaler_2) || \ - ((PRESCALER) == RCC_MCOPrescaler_4) || \ - ((PRESCALER) == RCC_MCOPrescaler_8) || \ - ((PRESCALER) == RCC_MCOPrescaler_16) || \ - ((PRESCALER) == RCC_MCOPrescaler_32) || \ - ((PRESCALER) == RCC_MCOPrescaler_64) || \ - ((PRESCALER) == RCC_MCOPrescaler_128)) -/** - * @} - */ - -/** @defgroup RCC_USB_Device_clock_source - * @{ - */ - -#define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) -#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) - -#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ - ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) -/** - * @} - */ - -/** @defgroup RCC_Flag - * @{ - */ -#define RCC_FLAG_HSIRDY ((uint8_t)0x01) -#define RCC_FLAG_HSERDY ((uint8_t)0x11) -#define RCC_FLAG_PLLRDY ((uint8_t)0x19) -#define RCC_FLAG_MCOF ((uint8_t)0x9C) -#define RCC_FLAG_LSERDY ((uint8_t)0x21) -#define RCC_FLAG_LSIRDY ((uint8_t)0x41) -#define RCC_FLAG_OBLRST ((uint8_t)0x59) -#define RCC_FLAG_PINRST ((uint8_t)0x5A) -#define RCC_FLAG_PORRST ((uint8_t)0x5B) -#define RCC_FLAG_SFTRST ((uint8_t)0x5C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x5D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x5E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x5F) - -#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ - ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ - ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \ - ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ - ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ - ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \ - ((FLAG) == RCC_FLAG_MCOF)) - -#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the RCC clock configuration to the default reset state */ -void RCC_DeInit(void); - -/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ -void RCC_HSEConfig(uint8_t RCC_HSE); -ErrorStatus RCC_WaitForHSEStartUp(void); -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); -void RCC_HSICmd(FunctionalState NewState); -void RCC_LSEConfig(uint32_t RCC_LSE); -void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive); -void RCC_LSICmd(FunctionalState NewState); -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); -void RCC_PLLCmd(FunctionalState NewState); -void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div); -void RCC_ClockSecuritySystemCmd(FunctionalState NewState); -#ifdef STM32F303xC - void RCC_MCOConfig(uint8_t RCC_MCOSource); -#else - void RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler); -#endif /* STM32F303xC */ - -/* System, AHB and APB busses clocks configuration functions ******************/ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); -uint8_t RCC_GetSYSCLKSource(void); -void RCC_HCLKConfig(uint32_t RCC_SYSCLK); -void RCC_PCLK1Config(uint32_t RCC_HCLK); -void RCC_PCLK2Config(uint32_t RCC_HCLK); -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); - -/* Peripheral clocks configuration functions **********************************/ -void RCC_ADCCLKConfig(uint32_t RCC_PLLCLK); -void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK); -void RCC_TIMCLKConfig(uint32_t RCC_TIMCLK); -void RCC_HRTIM1CLKConfig(uint32_t RCC_HRTIMCLK); -void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); -void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK); -void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); - -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); -void RCC_RTCCLKCmd(FunctionalState NewState); -void RCC_BackupResetCmd(FunctionalState NewState); - -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); - -void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); -void RCC_ClearFlag(void); -ITStatus RCC_GetITStatus(uint8_t RCC_IT); -void RCC_ClearITPendingBit(uint8_t RCC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F30x_RCC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_rtc.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2608 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_rtc.c - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Real-Time Clock (RTC) peripheral: - * + Initialization - * + Calendar (Time and Date) configuration - * + Alarms (Alarm A and Alarm B) configuration - * + WakeUp Timer configuration - * + Daylight Saving configuration - * + Output pin Configuration - * + Smooth digital Calibration configuration - * + TimeStamp configuration - * + Tampers configuration - * + Backup Data Registers configuration - * + Output Type Config configuration - * + Shift control synchronisation - * + Interrupts and flags management - * - @verbatim - - =============================================================================== - ##### RTC Operating Condition ##### - =============================================================================== - [..] The real-time clock (RTC) and the RTC backup registers can be powered - from the VBAT voltage when the main VDD supply is powered off. - To retain the content of the RTC backup registers and supply the RTC - when VDD is turned off, VBAT pin can be connected to an optional - standby voltage supplied by a battery or by another source. - - [..] To allow the RTC to operate even when the main digital supply (VDD) - is turned off, the VBAT pin powers the following blocks: - (#) The RTC - (#) The LSE oscillator - (#) PC13 to PC15 I/Os (when available) - - [..] When the backup domain is supplied by VDD (analog switch connected - to VDD), the following functions are available: - (#) PC14 and PC15 can be used as either GPIO or LSE pins - (#) PC13 can be used as a GPIO or as the RTC_AF pin - - [..] When the backup domain is supplied by VBAT (analog switch connected - to VBAT because VDD is not present), the following functions are available: - (#) PC14 and PC15 can be used as LSE pins only - (#) PC13 can be used as the RTC_AF pin - - ##### Backup Domain Reset ##### - =============================================================================== - [..] The backup domain reset sets all RTC registers and the RCC_BDCR - register to their reset values. - A backup domain reset is generated when one of the following events - occurs: - (#) Software reset, triggered by setting the BDRST bit in the - RCC Backup domain control register (RCC_BDCR). You can use the - RCC_BackupResetCmd(). - (#) VDD or VBAT power on, if both supplies have previously been - powered off. - - ##### Backup Domain Access ##### - =============================================================================== - [..] After reset, the backup domain (RTC registers and RTC backup data - registers) is protected against possible unwanted write accesses. - [..] To enable access to the Backup Domain and RTC registers, proceed as follows: - (#) Enable the Power Controller (PWR) APB1 interface clock using the - RCC_APB1PeriphClockCmd() function. - (#) Enable access to Backup domain using the PWR_BackupAccessCmd() function. - (#) Select the RTC clock source using the RCC_RTCCLKConfig() function. - (#) Enable RTC Clock using the RCC_RTCCLKCmd() function. - - ##### How to use this driver ##### - =============================================================================== - [..] - (+) Enable the backup domain access (see description in the section above) - (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and - RTC hour format using the RTC_Init() function. - - *** Time and Date configuration *** - =================================== - [..] - (+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime() - and RTC_SetDate() functions. - (+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate() - functions. - (+) To read the RTC subsecond, use the RTC_GetSubSecond() function. - (+) Use the RTC_DayLightSavingConfig() function to add or sub one - hour to the RTC Calendar. - - *** Alarm configuration *** - =========================== - [..] - (+) To configure the RTC Alarm use the RTC_SetAlarm() function. - (+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function. - (+) To read the RTC Alarm, use the RTC_GetAlarm() function. - (+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function. - - *** RTC Wakeup configuration *** - ================================ - [..] - (+) Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig() - function. - (+) Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() - function - (+) Enable the RTC WakeUp using the RTC_WakeUpCmd() function - (+) To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() - function. - - *** Outputs configuration *** - ============================= - [..] The RTC has 2 different outputs: - (+) AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B - and WaKeUp signals. - To output the selected RTC signal on RTC_AF pin, use the - RTC_OutputConfig() function. - (+) AFO_CALIB: this output is 512Hz signal or 1Hz . - To output the RTC Clock on RTC_AF pin, use the RTC_CalibOutputCmd() - function. - - *** Smooth digital Calibration configuration *** - ================================================ - [..] - (+) Configure the RTC Original Digital Calibration Value and the corresponding - calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig() - function. - - *** TimeStamp configuration *** - =============================== - [..] - (+) Configure the RTC_AF trigger and enables the RTC TimeStamp - using the RTC_TimeStampCmd() function. - (+) To read the RTC TimeStamp Time and Date register, use the - RTC_GetTimeStamp() function. - (+) To read the RTC TimeStamp SubSecond register, use the - RTC_GetTimeStampSubSecond() function. - - *** Tamper configuration *** - ============================ - [..] - (+) Configure the Tamper filter count using RTC_TamperFilterConfig() - function. - (+) Configure the RTC Tamper trigger Edge or Level according to the Tamper - filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() function. - (+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig() - function. - (+) Configure the Tamper precharge or discharge duration using - RTC_TamperPinsPrechargeDuration() function. - (+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function. - (+) Enable the RTC Tamper using the RTC_TamperCmd() function. - (+) Enable the Time stamp on Tamper detection event using - RTC_TSOnTamperDetecCmd() function. - - *** Backup Data Registers configuration *** - =========================================== - [..] - (+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister() - function. - (+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister() - function. - - ##### RTC and low power modes ##### - =============================================================================== - [..] The MCU can be woken up from a low power mode by an RTC alternate - function. - [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), - RTC wakeup, RTC tamper event detection and RTC time stamp event detection. - These RTC alternate functions can wake up the system from the Stop - and Standby lowpower modes. - The system can also wake up from low power modes without depending - on an external interrupt (Auto-wakeup mode), by using the RTC alarm - or the RTC wakeup events. - [..] The RTC provides a programmable time base for waking up from the - Stop or Standby mode at regular intervals. - Wakeup from STOP and Standby modes is possible only when the RTC - clock source is LSE or LSI. - - ##### Selection of RTC_AF alternate functions ##### - =============================================================================== - [..] The RTC_AF pin (PC13) can be used for the following purposes: - (+) Wakeup pin 2 (WKUP2) using the PWR_WakeUpPinCmd() function. - (+) AFO_ALARM output - (+) AFO_CALIB output - (+) AFI_TAMPER - (+) AFI_TIMESTAMP - - +------------------------------------------------------------------------------------------+ - | Pin |RTC ALARM |RTC CALIB |RTC TAMPER |RTC TIMESTAMP |PC13MODE| PC13VALUE | - | configuration | OUTPUT | OUTPUT | INPUT | INPUT | bit | bit | - | and function | ENABLED | ENABLED | ENABLED | ENABLED | | | - |-----------------|----------|----------|-----------|--------------|--------|--------------| - | Alarm out | | | | | Don't | | - | output OD | 1 |Don't care|Don't care | Don't care | care | 0 | - |-----------------|----------|----------|-----------|--------------|--------|--------------| - | Alarm out | | | | | Don't | | - | output PP | 1 |Don't care|Don't care | Don't care | care | 1 | - |-----------------|----------|----------|-----------|--------------|--------|--------------| - | Calibration out | | | | | Don't | | - | output PP | 0 | 1 |Don't care | Don't care | care | Don't care | - |-----------------|----------|----------|-----------|--------------|--------|--------------| - | TAMPER input | | | | | Don't | | - | floating | 0 | 0 | 1 | 0 | care | Don't care | - |-----------------|----------|----------|-----------|--------------|--------|--------------| - | TIMESTAMP and | | | | | Don't | | - | TAMPER input | 0 | 0 | 1 | 1 | care | Don't care | - | floating | | | | | | | - |-----------------|----------|----------|-----------|--------------|--------|--------------| - | TIMESTAMP input | | | | | Don't | | - | floating | 0 | 0 | 0 | 1 | care | Don't care | - |-----------------|----------|----------|-----------|--------------|--------|--------------| - | Output PP | 0 | 0 | 0 | 0 | 1 | PC13 output | - | Forced | | | | | | | - |-----------------|----------|----------|-----------|--------------|--------|--------------| - | Wakeup Pin or | 0 | 0 | 0 | 0 | 0 | Don't care | - | Standard GPIO | | | | | | | - +------------------------------------------------------------------------------------------+ - - @endverbatim - - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x_rtc.h" -#include "stm32f30x_rcc.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @defgroup RTC - * @brief RTC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* Masks Definition */ -#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) -#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) -#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) -#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) -#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \ - RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \ - RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \ - RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \ - RTC_FLAG_TAMP2F | RTC_FLAG_TAMP3F | RTC_FLAG_RECALPF | \ - RTC_FLAG_SHPF)) - -#define INITMODE_TIMEOUT ((uint32_t) 0x00002000) -#define SYNCHRO_TIMEOUT ((uint32_t) 0x00008000) -#define RECALPF_TIMEOUT ((uint32_t) 0x00001000) -#define SHPF_TIMEOUT ((uint32_t) 0x00002000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static uint8_t RTC_ByteToBcd2(uint8_t Value); -static uint8_t RTC_Bcd2ToByte(uint8_t Value); - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RTC_Private_Functions - * @{ - */ - -/** @defgroup RTC_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provide functions allowing to initialize and configure the RTC - Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers - Write protection, enter and exit the RTC initialization mode, RTC registers - synchronization check and reference clock detection enable. - (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is - split into 2 programmable prescalers to minimize power consumption. - (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler. - (++) When both prescalers are used, it is recommended to configure the - asynchronous prescaler to a high value to minimize consumption. - (#) All RTC registers are Write protected. Writing to the RTC registers - is enabled by writing a key into the Write Protection register, RTC_WPR. - (#) To Configure the RTC Calendar, user application should enter initialization - mode. In this mode, the calendar counter is stopped and its value - can be updated. When the initialization sequence is complete, the - calendar restarts counting after 4 RTCCLK cycles. - (#) To read the calendar through the shadow registers after Calendar - initialization, calendar update or after wakeup from low power modes - the software must first clear the RSF flag. The software must then - wait until it is set again before reading the calendar, which means - that the calendar registers have been correctly copied into the RTC_TR - and RTC_DR shadow registers. The RTC_WaitForSynchro() function - implements the above software sequence (RSF clear and RSF check). - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the RTC registers to their default reset values. - * @note This function doesn't reset the RTC Clock source and RTC Backup Data - * registers. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are deinitialized - * - ERROR: RTC registers are not deinitialized - */ -ErrorStatus RTC_DeInit(void) -{ - __IO uint32_t wutcounter = 0x00; - uint32_t wutwfstatus = 0x00; - ErrorStatus status = ERROR; - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Reset TR, DR and CR registers */ - RTC->TR = (uint32_t)0x00000000; - RTC->DR = (uint32_t)0x00002101; - - /* Reset All CR bits except CR[2:0] */ - RTC->CR &= (uint32_t)0x00000007; - - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - do - { - wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; - wutcounter++; - } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) - { - status = ERROR; - } - else - { - /* Reset all RTC CR register bits */ - RTC->CR &= (uint32_t)0x00000000; - RTC->WUTR = (uint32_t)0x0000FFFF; - RTC->PRER = (uint32_t)0x007F00FF; - RTC->ALRMAR = (uint32_t)0x00000000; - RTC->ALRMBR = (uint32_t)0x00000000; - RTC->SHIFTR = (uint32_t)0x00000000; - RTC->CALR = (uint32_t)0x00000000; - RTC->ALRMASSR = (uint32_t)0x00000000; - RTC->ALRMBSSR = (uint32_t)0x00000000; - - /* Reset ISR register and exit initialization mode */ - RTC->ISR = (uint32_t)0x00000000; - - /* Reset Tamper and alternate functions configuration register */ - RTC->TAFCR = 0x00000000; - - /* Wait till the RTC RSF flag is set */ - if (RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Initializes the RTC registers according to the specified parameters - * in RTC_InitStruct. - * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains - * the configuration information for the RTC peripheral. - * @note The RTC Prescaler register is write protected and can be written in - * initialization mode only. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are initialized - * - ERROR: RTC registers are not initialized - */ -ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat)); - assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv)); - assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Clear RTC CR FMT Bit */ - RTC->CR &= ((uint32_t)~(RTC_CR_FMT)); - /* Set RTC_CR register */ - RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat)); - - /* Configure the RTC PRER */ - RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv); - RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_InitStruct member with its default value. - * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct) -{ - /* Initialize the RTC_HourFormat member */ - RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24; - - /* Initialize the RTC_AsynchPrediv member */ - RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F; - - /* Initialize the RTC_SynchPrediv member */ - RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; -} - -/** - * @brief Enables or disables the RTC registers write protection. - * @note All the RTC registers are write protected except for RTC_ISR[13:8], - * RTC_TAFCR and RTC_BKPxR. - * @note Writing a wrong key reactivates the write protection. - * @note The protection mechanism is not affected by system reset. - * @param NewState: new state of the write protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_WriteProtectionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - } - else - { - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - } -} - -/** - * @brief Enters the RTC Initialization mode. - * @note The RTC Initialization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC is in Init mode - * - ERROR: RTC is not in Init mode - */ -ErrorStatus RTC_EnterInitMode(void) -{ - __IO uint32_t initcounter = 0x00; - ErrorStatus status = ERROR; - uint32_t initstatus = 0x00; - - /* Check if the Initialization mode is set */ - if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET) - { - /* Set the Initialization mode */ - RTC->ISR = (uint32_t)RTC_INIT_MASK; - - /* Wait till RTC is in INIT state and if Time out is reached exit */ - do - { - initstatus = RTC->ISR & RTC_ISR_INITF; - initcounter++; - } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_INITF) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - } - else - { - status = SUCCESS; - } - - return (status); -} - -/** - * @brief Exits the RTC Initialization mode. - * @note When the initialization sequence is complete, the calendar restarts - * counting after 4 RTCCLK cycles. - * @note The RTC Initialization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @param None - * @retval None - */ -void RTC_ExitInitMode(void) -{ - /* Exit Initialization mode */ - RTC->ISR &= (uint32_t)~RTC_ISR_INIT; -} - -/** - * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are - * synchronized with RTC APB clock. - * @note The RTC Resynchronization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @note To read the calendar through the shadow registers after Calendar - * initialization, calendar update or after wakeup from low power modes - * the software must first clear the RSF flag. - * The software must then wait until it is set again before reading - * the calendar, which means that the calendar registers have been - * correctly copied into the RTC_TR and RTC_DR shadow registers. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are synchronised - * - ERROR: RTC registers are not synchronised - */ -ErrorStatus RTC_WaitForSynchro(void) -{ - __IO uint32_t synchrocounter = 0; - ErrorStatus status = ERROR; - uint32_t synchrostatus = 0x00; - - if ((RTC->CR & RTC_CR_BYPSHAD) != RESET) - { - /* Bypass shadow mode */ - status = SUCCESS; - } - else - { - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear RSF flag */ - RTC->ISR &= (uint32_t)RTC_RSF_MASK; - - /* Wait the registers to be synchronised */ - do - { - synchrostatus = RTC->ISR & RTC_ISR_RSF; - synchrocounter++; - } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_RSF) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - } - - return (status); -} - -/** - * @brief Enables or disables the RTC reference clock detection. - * @param NewState: new state of the RTC reference clock. - * This parameter can be: ENABLE or DISABLE. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC reference clock detection is enabled - * - ERROR: RTC reference clock detection is disabled - */ -ErrorStatus RTC_RefClockCmd(FunctionalState NewState) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - if (NewState != DISABLE) - { - /* Enable the RTC reference clock detection */ - RTC->CR |= RTC_CR_REFCKON; - } - else - { - /* Disable the RTC reference clock detection */ - RTC->CR &= ~RTC_CR_REFCKON; - } - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Enables or Disables the Bypass Shadow feature. - * @note When the Bypass Shadow is enabled the calendar value are taken - * directly from the Calendar counter. - * @param NewState: new state of the Bypass Shadow feature. - * This parameter can be: ENABLE or DISABLE. - * @retval None -*/ -void RTC_BypassShadowCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Set the BYPSHAD bit */ - RTC->CR |= (uint8_t)RTC_CR_BYPSHAD; - } - else - { - /* Reset the BYPSHAD bit */ - RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @} - */ - -/** @defgroup RTC_Group2 Time and Date configuration functions - * @brief Time and Date configuration functions - * -@verbatim - =============================================================================== - ##### Time and Date configuration functions ##### - =============================================================================== - [..] This section provide functions allowing to program and read the RTC Calendar - (Time and Date). - -@endverbatim - * @{ - */ - -/** - * @brief Set the RTC current time. - * @param RTC_Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains - * the time configuration information for the RTC. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Time register is configured - * - ERROR: RTC Time register is not configured - */ -ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) -{ - uint32_t tmpreg = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - if (RTC_Format == RTC_Format_BIN) - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours)); - assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); - } - else - { - RTC_TimeStruct->RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours)); - } - assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes)); - assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds)); - } - else - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); - } - else - { - RTC_TimeStruct->RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours))); - } - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds))); - } - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \ - ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \ - ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \ - ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); - } - else - { - tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \ - (((uint32_t)RTC_TimeStruct->RTC_H12) << 16)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Set the RTC_TR register */ - RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if ((RTC->CR & RTC_CR_BYPSHAD) == RESET) - { - if (RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - else - { - status = SUCCESS; - } - - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_TimeStruct member with its default value - * (Time = 00h:00min:00sec). - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct) -{ - /* Time = 00h:00min:00sec */ - RTC_TimeStruct->RTC_H12 = RTC_H12_AM; - RTC_TimeStruct->RTC_Hours = 0; - RTC_TimeStruct->RTC_Minutes = 0; - RTC_TimeStruct->RTC_Seconds = 0; -} - -/** - * @brief Get the RTC current Time. - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will - * contain the returned current time configuration. - * @retval None - */ -void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the RTC_TR register */ - tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); - RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); - RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); - RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the structure parameters to Binary format */ - RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); - RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes); - RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds); - } -} - -/** - * @brief Gets the RTC current Calendar Subseconds value. - * @note This function freeze the Time and Date registers after reading the - * SSR register. - * @param None - * @retval RTC current Calendar Subseconds value. - */ -uint32_t RTC_GetSubSecond(void) -{ - uint32_t tmpreg = 0; - - /* Get subseconds values from the correspondent registers*/ - tmpreg = (uint32_t)(RTC->SSR); - - /* Read DR register to unfroze calendar registers */ - (void) (RTC->DR); - - return (tmpreg); -} - -/** - * @brief Set the RTC current date. - * @param RTC_Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains - * the date configuration information for the RTC. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Date register is configured - * - ERROR: RTC Date register is not configured - */ -ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) -{ - uint32_t tmpreg = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10)) - { - RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A; - } - if (RTC_Format == RTC_Format_BIN) - { - assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year)); - assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month)); - assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date)); - } - else - { - assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year))); - tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); - assert_param(IS_RTC_MONTH(tmpreg)); - tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); - assert_param(IS_RTC_DATE(tmpreg)); - } - assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay)); - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \ - (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \ - ((uint32_t)RTC_DateStruct->RTC_Date) | \ - (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); - } - else - { - tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \ - ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Set the RTC_DR register */ - RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if ((RTC->CR & RTC_CR_BYPSHAD) == RESET) - { - if (RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - else - { - status = SUCCESS; - } - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_DateStruct member with its default value - * (Monday, January 01 xx00). - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct) -{ - /* Monday, January 01 xx00 */ - RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday; - RTC_DateStruct->RTC_Date = 1; - RTC_DateStruct->RTC_Month = RTC_Month_January; - RTC_DateStruct->RTC_Year = 0; -} - -/** - * @brief Get the RTC current date. - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will - * contain the returned current date configuration. - * @retval None - */ -void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the RTC_TR register */ - tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); - RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); - RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU)); - RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the structure parameters to Binary format */ - RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year); - RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); - RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); - RTC_DateStruct->RTC_WeekDay = (uint8_t)(RTC_DateStruct->RTC_WeekDay); - } -} - -/** - * @} - */ - -/** @defgroup RTC_Group3 Alarms configuration functions - * @brief Alarms (Alarm A and Alarm B) configuration functions - * -@verbatim - =============================================================================== - ##### Alarms (Alarm A and Alarm B) configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to program and read the RTC Alarms. - -@endverbatim - * @{ - */ - -/** - * @brief Set the specified RTC Alarm. - * @note The Alarm register can only be written when the corresponding Alarm - * is disabled (Use the RTC_AlarmCmd(DISABLE)). - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_Alarm: specifies the alarm to be configured. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that - * contains the alarm configuration parameters. - * @retval None - */ -void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - assert_param(IS_RTC_ALARM(RTC_Alarm)); - assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask)); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel)); - - if (RTC_Format == RTC_Format_BIN) - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); - assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); - } - else - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); - } - assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)); - assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)); - - if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); - } - } - else - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); - } - else - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours))); - } - - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds))); - - if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); - } - else - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); - } - } - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); - } - else - { - tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Alarm register */ - if (RTC_Alarm == RTC_Alarm_A) - { - RTC->ALRMAR = (uint32_t)tmpreg; - } - else - { - RTC->ALRMBR = (uint32_t)tmpreg; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Fills each RTC_AlarmStruct member with its default value - * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = - * all fields are masked). - * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which - * will be initialized. - * @retval None - */ -void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - /* Alarm Time Settings : Time = 00h:00mn:00sec */ - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0; - - /* Alarm Date Settings : Date = 1st day of the month */ - RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date; - RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1; - - /* Alarm Masks Settings : Mask = all fields are not masked */ - RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None; -} - -/** - * @brief Get the RTC Alarm value and masks. - * @param RTC_Format: specifies the format of the output parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_Alarm: specifies the alarm to be read. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will - * contains the output alarm configuration values. - * @retval None - */ -void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - assert_param(IS_RTC_ALARM(RTC_Alarm)); - - /* Get the RTC_ALRMxR register */ - if (RTC_Alarm == RTC_Alarm_A) - { - tmpreg = (uint32_t)(RTC->ALRMAR); - } - else - { - tmpreg = (uint32_t)(RTC->ALRMBR); - } - - /* Fill the structure with the read parameters */ - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \ - RTC_ALRMAR_HU)) >> 16); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \ - RTC_ALRMAR_MNU)) >> 8); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \ - RTC_ALRMAR_SU)); - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); - RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); - RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); - RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All); - - if (RTC_Format == RTC_Format_BIN) - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Hours); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Minutes); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Seconds); - RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - } -} - -/** - * @brief Enables or disables the specified RTC Alarm. - * @param RTC_Alarm: specifies the alarm to be configured. - * This parameter can be any combination of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param NewState: new state of the specified alarm. - * This parameter can be: ENABLE or DISABLE. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Alarm is enabled/disabled - * - ERROR: RTC Alarm is not enabled/disabled - */ -ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState) -{ - __IO uint32_t alarmcounter = 0x00; - uint32_t alarmstatus = 0x00; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_CMD_ALARM(RTC_Alarm)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Alarm state */ - if (NewState != DISABLE) - { - RTC->CR |= (uint32_t)RTC_Alarm; - - status = SUCCESS; - } - else - { - /* Disable the Alarm in RTC_CR register */ - RTC->CR &= (uint32_t)~RTC_Alarm; - - /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - do - { - alarmstatus = RTC->ISR & (RTC_Alarm >> 8); - alarmcounter++; - } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00)); - - if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Configures the RTC AlarmA/B Subseconds value and mask. - * @note This function is performed only when the Alarm is disabled. - * @param RTC_Alarm: specifies the alarm to be configured. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param RTC_AlarmSubSecondValue: specifies the Subseconds value. - * This parameter can be a value from 0 to 0x00007FFF. - * @param RTC_AlarmSubSecondMask: specifies the Subseconds Mask. - * This parameter can be any combination of the following values: - * @arg RTC_AlarmSubSecondMask_All : All Alarm SS fields are masked. - * There is no comparison on sub seconds for Alarm. - * @arg RTC_AlarmSubSecondMask_SS14_1 : SS[14:1] are don't care in Alarm comparison. - * Only SS[0] is compared - * @arg RTC_AlarmSubSecondMask_SS14_2 : SS[14:2] are don't care in Alarm comparison. - * Only SS[1:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_3 : SS[14:3] are don't care in Alarm comparison. - * Only SS[2:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_4 : SS[14:4] are don't care in Alarm comparison. - * Only SS[3:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_5 : SS[14:5] are don't care in Alarm comparison. - * Only SS[4:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_6 : SS[14:6] are don't care in Alarm comparison. - * Only SS[5:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_7 : SS[14:7] are don't care in Alarm comparison. - * Only SS[6:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_8 : SS[14:8] are don't care in Alarm comparison. - * Only SS[7:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_9 : SS[14:9] are don't care in Alarm comparison. - * Only SS[8:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison. - * Only SS[9:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison. - * Only SS[10:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison. - * Only SS[11:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison. - * Only SS[12:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14 : SS[14] is don't care in Alarm comparison. - * Only SS[13:0] are compared - * @arg RTC_AlarmSubSecondMask_None : SS[14:0] are compared and must match - * to activate alarm - * @retval None - */ -void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_ALARM(RTC_Alarm)); - assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue)); - assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Alarm A or Alarm B SubSecond registers */ - tmpreg = (uint32_t) (uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask); - - if (RTC_Alarm == RTC_Alarm_A) - { - /* Configure the AlarmA SubSecond register */ - RTC->ALRMASSR = tmpreg; - } - else - { - /* Configure the Alarm B SubSecond register */ - RTC->ALRMBSSR = tmpreg; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - -} - -/** - * @brief Gets the RTC Alarm Subseconds value. - * @param RTC_Alarm: specifies the alarm to be read. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param None - * @retval RTC Alarm Subseconds value. - */ -uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm) -{ - uint32_t tmpreg = 0; - - /* Get the RTC_ALRMxR register */ - if (RTC_Alarm == RTC_Alarm_A) - { - tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS); - } - else - { - tmpreg = (uint32_t)((RTC->ALRMBSSR) & RTC_ALRMBSSR_SS); - } - - return (tmpreg); -} - -/** - * @} - */ - -/** @defgroup RTC_Group4 WakeUp Timer configuration functions - * @brief WakeUp Timer configuration functions - * -@verbatim - =============================================================================== - ##### WakeUp Timer configuration functions ##### - =============================================================================== - [..] This section provide functions allowing to program and read the RTC WakeUp. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC Wakeup clock source. - * @note The WakeUp Clock source can only be changed when the RTC WakeUp - * is disabled (Use the RTC_WakeUpCmd(DISABLE)). - * @param RTC_WakeUpClock: Wakeup Clock source. - * This parameter can be one of the following values: - * @arg RTC_WakeUpClock_RTCCLK_Div16: RTC Wakeup Counter Clock = RTCCLK/16 - * @arg RTC_WakeUpClock_RTCCLK_Div8: RTC Wakeup Counter Clock = RTCCLK/8 - * @arg RTC_WakeUpClock_RTCCLK_Div4: RTC Wakeup Counter Clock = RTCCLK/4 - * @arg RTC_WakeUpClock_RTCCLK_Div2: RTC Wakeup Counter Clock = RTCCLK/2 - * @arg RTC_WakeUpClock_CK_SPRE_16bits: RTC Wakeup Counter Clock = CK_SPRE - * @arg RTC_WakeUpClock_CK_SPRE_17bits: RTC Wakeup Counter Clock = CK_SPRE - * @retval None - */ -void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock) -{ - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the Wakeup Timer clock source bits in CR register */ - RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL; - - /* Configure the clock source */ - RTC->CR |= (uint32_t)RTC_WakeUpClock; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Configures the RTC Wakeup counter. - * @note The RTC WakeUp counter can only be written when the RTC WakeUp - * is disabled (Use the RTC_WakeUpCmd(DISABLE)). - * @param RTC_WakeUpCounter: specifies the WakeUp counter. - * This parameter can be a value from 0x0000 to 0xFFFF. - * @retval None - */ -void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter) -{ - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Wakeup Timer counter */ - RTC->WUTR = (uint32_t)RTC_WakeUpCounter; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Returns the RTC WakeUp timer counter value. - * @param None - * @retval The RTC WakeUp Counter value. - */ -uint32_t RTC_GetWakeUpCounter(void) -{ - /* Get the counter value */ - return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT)); -} - -/** - * @brief Enables or Disables the RTC WakeUp timer. - * @param NewState: new state of the WakeUp timer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -ErrorStatus RTC_WakeUpCmd(FunctionalState NewState) -{ - __IO uint32_t wutcounter = 0x00; - uint32_t wutwfstatus = 0x00; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Enable the Wakeup Timer */ - RTC->CR |= (uint32_t)RTC_CR_WUTE; - status = SUCCESS; - } - else - { - /* Disable the Wakeup Timer */ - RTC->CR &= (uint32_t)~RTC_CR_WUTE; - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - do - { - wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; - wutcounter++; - } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @} - */ - -/** @defgroup RTC_Group5 Daylight Saving configuration functions - * @brief Daylight Saving configuration functions - * -@verbatim - =============================================================================== - ##### Daylight Saving configuration functions ##### - =============================================================================== - [..] This section provide functions allowing to configure the RTC DayLight Saving. - -@endverbatim - * @{ - */ - -/** - * @brief Adds or substract one hour from the current time. - * @param RTC_DayLightSaveOperation: the value of hour adjustment. - * This parameter can be one of the following values: - * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time) - * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time) - * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit - * in CR register to store the operation. - * This parameter can be one of the following values: - * @arg RTC_StoreOperation_Reset: BCK Bit Reset - * @arg RTC_StoreOperation_Set: BCK Bit Set - * @retval None - */ -void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation) -{ - /* Check the parameters */ - assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving)); - assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the bits to be configured */ - RTC->CR &= (uint32_t)~(RTC_CR_BCK); - - /* Configure the RTC_CR register */ - RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation); - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Returns the RTC Day Light Saving stored operation. - * @param None - * @retval RTC Day Light Saving stored operation. - * - RTC_StoreOperation_Reset - * - RTC_StoreOperation_Set - */ -uint32_t RTC_GetStoreOperation(void) -{ - return (RTC->CR & RTC_CR_BCK); -} - -/** - * @} - */ - -/** @defgroup RTC_Group6 Output pin Configuration function - * @brief Output pin Configuration function - * -@verbatim - =============================================================================== - ##### Output pin Configuration function ##### - =============================================================================== - [..] This section provide functions allowing to configure the RTC Output source. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC output source (AFO_ALARM). - * @param RTC_Output: Specifies which signal will be routed to the RTC output. - * This parameter can be one of the following values: - * @arg RTC_Output_Disable: No output selected - * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output - * @arg RTC_Output_AlarmB: signal of AlarmB mapped to output - * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output - * @param RTC_OutputPolarity: Specifies the polarity of the output signal. - * This parameter can be one of the following: - * @arg RTC_OutputPolarity_High: The output pin is high when the - * ALRAF/ALRBF/WUTF is high (depending on OSEL) - * @arg RTC_OutputPolarity_Low: The output pin is low when the - * ALRAF/ALRBF/WUTF is high (depending on OSEL) - * @retval None - */ -void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity) -{ - /* Check the parameters */ - assert_param(IS_RTC_OUTPUT(RTC_Output)); - assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the bits to be configured */ - RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL); - - /* Configure the output selection and polarity */ - RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity); - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @} - */ - -/** @defgroup RTC_Group7 Digital Calibration configuration functions - * @brief Digital Calibration configuration functions - * -@verbatim - =============================================================================== - ##### Digital Calibration configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the RTC clock to be output through the relative - * pin. - * @param NewState: new state of the digital calibration Output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_CalibOutputCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Enable the RTC clock output */ - RTC->CR |= (uint32_t)RTC_CR_COE; - } - else - { - /* Disable the RTC clock output */ - RTC->CR &= (uint32_t)~RTC_CR_COE; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param RTC_CalibOutput : Select the Calibration output Selection . - * This parameter can be one of the following values: - * @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz. - * @arg RTC_CalibOutput_1Hz : A signal has a regular waveform at 1Hz. - * @retval None -*/ -void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput) -{ - /* Check the parameters */ - assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /*clear flags before config*/ - RTC->CR &= (uint32_t)~(RTC_CR_COSEL); - - /* Configure the RTC_CR register */ - RTC->CR |= (uint32_t)RTC_CalibOutput; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Configures the Smooth Calibration Settings. - * @param RTC_SmoothCalibPeriod : Select the Smooth Calibration Period. - * This parameter can be can be one of the following values: - * @arg RTC_SmoothCalibPeriod_32sec : The smooth calibration periode is 32s. - * @arg RTC_SmoothCalibPeriod_16sec : The smooth calibration periode is 16s. - * @arg RTC_SmoothCalibPeriod_8sec : The smooth calibartion periode is 8s. - * @param RTC_SmoothCalibPlusPulses : Select to Set or reset the CALP bit. - * This parameter can be one of the following values: - * @arg RTC_SmoothCalibPlusPulses_Set : Add one RTCCLK puls every 2**11 pulses. - * @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added. - * @param RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits. - * This parameter can be one any value from 0 to 0x000001FF. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Calib registers are configured - * - ERROR: RTC Calib registers are not configured -*/ -ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, - uint32_t RTC_SmoothCalibPlusPulses, - uint32_t RTC_SmouthCalibMinusPulsesValue) -{ - ErrorStatus status = ERROR; - uint32_t recalpfcount = 0; - - /* Check the parameters */ - assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod)); - assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses)); - assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* check if a calibration is pending*/ - if ((RTC->ISR & RTC_ISR_RECALPF) != RESET) - { - /* wait until the Calibration is completed*/ - while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT)) - { - recalpfcount++; - } - } - - /* check if the calibration pending is completed or if there is no calibration operation at all*/ - if ((RTC->ISR & RTC_ISR_RECALPF) == RESET) - { - /* Configure the Smooth calibration settings */ - RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue); - - status = SUCCESS; - } - else - { - status = ERROR; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return (ErrorStatus)(status); -} - -/** - * @} - */ - - -/** @defgroup RTC_Group8 TimeStamp configuration functions - * @brief TimeStamp configuration functions - * -@verbatim - =============================================================================== - ##### TimeStamp configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or Disables the RTC TimeStamp functionality with the - * specified time stamp pin stimulating edge. - * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is - * activated. - * This parameter can be one of the following: - * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising - * edge of the related pin. - * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the - * falling edge of the related pin. - * @param NewState: new state of the TimeStamp. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - /* Get the new configuration */ - if (NewState != DISABLE) - { - tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE); - } - else - { - tmpreg |= (uint32_t)(RTC_TimeStampEdge); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Time Stamp TSEDGE and Enable bits */ - RTC->CR = (uint32_t)tmpreg; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Gets the RTC TimeStamp value and masks. - * @param RTC_Format: specifies the format of the output parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will - * contains the TimeStamp time values. - * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will - * contains the TimeStamp date values. - * @retval None - */ -void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, - RTC_DateTypeDef* RTC_StampDateStruct) -{ - uint32_t tmptime = 0, tmpdate = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the TimeStamp time and date registers values */ - tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK); - tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK); - - /* Fill the Time structure fields with the read parameters */ - RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); - RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); - RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); - RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); - - /* Fill the Date structure fields with the read parameters */ - RTC_StampDateStruct->RTC_Year = 0; - RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); - RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); - RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the Time structure parameters to Binary format */ - RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours); - RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes); - RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds); - - /* Convert the Date structure parameters to Binary format */ - RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month); - RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date); - RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay); - } -} - -/** - * @brief Gets the RTC timestamp Subseconds value. - * @param None - * @retval RTC current timestamp Subseconds value. - */ -uint32_t RTC_GetTimeStampSubSecond(void) -{ - /* Get timestamp subseconds values from the correspondent registers */ - return (uint32_t)(RTC->TSSSR); -} - -/** - * @} - */ - -/** @defgroup RTC_Group9 Tampers configuration functions - * @brief Tampers configuration functions - * -@verbatim - =============================================================================== - ##### Tampers configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the select Tamper pin edge. - * @param RTC_Tamper: Selected tamper pin. - * This parameter can be any combination of the following values: - * @arg RTC_Tamper_1: Select Tamper 1. - * @arg RTC_Tamper_2: Select Tamper 2. - * @arg RTC_Tamper_3: Select Tamper 3. - * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that - * stimulates tamper event. - * This parameter can be one of the following values: - * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event. - * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event. - * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event. - * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event. - * @retval None - */ -void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(RTC_Tamper)); - assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger)); - - /* Check if the active level for Tamper is rising edge (Low level)*/ - if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge) - { - /* Configure the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1)); - } - else - { - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1); - } -} - -/** - * @brief Enables or Disables the Tamper detection. - * @param RTC_Tamper: Selected tamper pin. - * This parameter can be any combination of the following values: - * @arg RTC_Tamper_1: Select Tamper 1. - * @arg RTC_Tamper_2: Select Tamper 2. - * @arg RTC_Tamper_3: Select Tamper 3. - * @param NewState: new state of the tamper pin. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(RTC_Tamper)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected Tamper pin */ - RTC->TAFCR |= (uint32_t)RTC_Tamper; - } - else - { - /* Disable the selected Tamper pin */ - RTC->TAFCR &= (uint32_t)~RTC_Tamper; - } -} - -/** - * @brief Configures the Tampers Filter. - * @param RTC_TamperFilter: Specifies the tampers filter. - * This parameter can be one of the following values: - * @arg RTC_TamperFilter_Disable: Tamper filter is disabled. - * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive - * samples at the active level - * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive - * samples at the active level - * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive - * samples at the active level - * @retval None - */ -void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter)); - - /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT); - - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)RTC_TamperFilter; -} - -/** - * @brief Configures the Tampers Sampling Frequency. - * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency. - * This parameter can be one of the following values: - * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 32768 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 16384 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 8192 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 4096 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 2048 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 1024 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 512 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 256 - * @retval None - */ -void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq)); - - /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ); - - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq; -} - -/** - * @brief Configures the Tampers Pins input Precharge Duration. - * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input - * Precharge Duration. - * This parameter can be one of the following values: - * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle - * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle - * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle - * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle - * @retval None - */ -void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration)); - - /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH); - - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration; -} - -/** - * @brief Enables or Disables the TimeStamp on Tamper Detection Event. - * @note The timestamp is valid even the TSE bit in tamper control register - * is reset. - * @param NewState: new state of the timestamp on tamper event. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Save timestamp on tamper detection event */ - RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS; - } - else - { - /* Tamper detection does not cause a timestamp to be saved */ - RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS; - } -} - -/** - * @brief Enables or Disables the Precharge of Tamper pin. - * @param NewState: new state of tamper pull up. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TamperPullUpCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable precharge of the selected Tamper pin */ - RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS; - } - else - { - /* Disable precharge of the selected Tamper pin */ - RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS; - } -} - -/** - * @} - */ - -/** @defgroup RTC_Group10 Backup Data Registers configuration functions - * @brief Backup Data Registers configuration functions - * -@verbatim - =============================================================================== - ##### Backup Data Registers configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Writes a data in a specified RTC Backup data register. - * @param RTC_BKP_DR: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 15 to - * specify the register. - * @param Data: Data to be written in the specified RTC Backup data register. - * @retval None - */ -void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(RTC_BKP_DR)); - - tmp = RTC_BASE + 0x50; - tmp += (RTC_BKP_DR * 4); - - /* Write the specified register */ - *(__IO uint32_t *)tmp = (uint32_t)Data; -} - -/** - * @brief Reads data from the specified RTC Backup data Register. - * @param RTC_BKP_DR: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 15 to - * specify the register. - * @retval None - */ -uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(RTC_BKP_DR)); - - tmp = RTC_BASE + 0x50; - tmp += (RTC_BKP_DR * 4); - - /* Read the specified register */ - return (*(__IO uint32_t *)tmp); -} - -/** - * @} - */ - -/** @defgroup RTC_Group11 Output Type Config configuration functions - * @brief Output Type Config configuration functions - * -@verbatim - =============================================================================== - ##### Output Type Config configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC Output Pin mode. - * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode. - * This parameter can be one of the following values: - * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in - * Open Drain mode. - * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in - * Push Pull mode. - * @retval None - */ -void RTC_OutputTypeConfig(uint32_t RTC_OutputType) -{ - /* Check the parameters */ - assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType)); - - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE); - RTC->TAFCR |= (uint32_t)(RTC_OutputType); -} - -/** - * @} - */ - -/** @defgroup RTC_Group12 Shift control synchronisation functions - * @brief Shift control synchronisation functions - * -@verbatim - =============================================================================== - ##### Shift control synchronisation functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the Synchronization Shift Control Settings. - * @note When REFCKON is set, firmware must not write to Shift control register - * @param RTC_ShiftAdd1S : Select to add or not 1 second to the time Calendar. - * This parameter can be one of the following values : - * @arg RTC_ShiftAdd1S_Set : Add one second to the clock calendar. - * @arg RTC_ShiftAdd1S_Reset: No effect. - * @param RTC_ShiftSubFS: Select the number of Second Fractions to Substitute. - * This parameter can be one any value from 0 to 0x7FFF. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Shift registers are configured - * - ERROR: RTC Shift registers are not configured -*/ -ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS) -{ - ErrorStatus status = ERROR; - uint32_t shpfcount = 0; - - /* Check the parameters */ - assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S)); - assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Check if a Shift is pending*/ - if ((RTC->ISR & RTC_ISR_SHPF) != RESET) - { - /* Wait until the shift is completed*/ - while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT)) - { - shpfcount++; - } - } - - /* Check if the Shift pending is completed or if there is no Shift operation at all*/ - if ((RTC->ISR & RTC_ISR_SHPF) == RESET) - { - /* check if the reference clock detection is disabled */ - if((RTC->CR & RTC_CR_REFCKON) == RESET) - { - /* Configure the Shift settings */ - RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S); - - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - else - { - status = ERROR; - } - } - else - { - status = ERROR; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return (ErrorStatus)(status); -} - -/** - * @} - */ - -/** @defgroup RTC_Group13 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - [..] All RTC interrupts are connected to the EXTI controller. - (+) To enable the RTC Alarm interrupt, the following sequence is required: - (++) Configure and enable the EXTI Line 17 in interrupt mode and select - the rising edge sensitivity using the EXTI_Init() function. - (++) Configure and enable the RTC_Alarm IRQ channel in the NVIC using - the NVIC_Init() function. - (++) Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) - using the RTC_SetAlarm() and RTC_AlarmCmd() functions. - (+) To enable the RTC Wakeup interrupt, the following sequence is required: - (++) Configure and enable the EXTI Line 20 in interrupt mode and select - the rising edge sensitivity using the EXTI_Init() function. - (++) Configure and enable the RTC_WKUP IRQ channel in the NVIC using - the NVIC_Init() function. - (++) Configure the RTC to generate the RTC wakeup timer event using the - RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() - functions. - (+) To enable the RTC Tamper interrupt, the following sequence is required: - (++) Configure and enable the EXTI Line 19 in interrupt mode and select - the rising edge sensitivity using the EXTI_Init() function. - (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using - the NVIC_Init() function. - (++) Configure the RTC to detect the RTC tamper event using the - RTC_TamperTriggerConfig() and RTC_TamperCmd() functions. - (+) To enable the RTC TimeStamp interrupt, the following sequence is required: - (++) Configure and enable the EXTI Line 19 in interrupt mode and select - the rising edge sensitivity using the EXTI_Init() function. - (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using - the NVIC_Init() function. - (++) Configure the RTC to detect the RTC time-stamp event using the - RTC_TimeStampCmd() functions. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified RTC interrupts. - * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt mask - * @arg RTC_IT_WUT: WakeUp Timer interrupt mask - * @arg RTC_IT_ALRB: Alarm B interrupt mask - * @arg RTC_IT_ALRA: Alarm A interrupt mask - * @arg RTC_IT_TAMP: Tamper event interrupt mask - * @param NewState: new state of the specified RTC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RTC_CONFIG_IT(RTC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Configure the Interrupts in the RTC_CR register */ - RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE); - /* Configure the Tamper Interrupt in the RTC_TAFCR */ - RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE); - } - else - { - /* Configure the Interrupts in the RTC_CR register */ - RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE); - /* Configure the Tamper Interrupt in the RTC_TAFCR */ - RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE); - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Checks whether the specified RTC flag is set or not. - * @param RTC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg RTC_FLAG_RECALPF: RECALPF event flag - * @arg RTC_FLAG_TAMP3F: Tamper 3 event flag - * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag - * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag - * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag - * @arg RTC_FLAG_TSF: Time Stamp event flag - * @arg RTC_FLAG_WUTF: WakeUp Timer flag - * @arg RTC_FLAG_ALRBF: Alarm B flag - * @arg RTC_FLAG_ALRAF: Alarm A flag - * @arg RTC_FLAG_INITF: Initialization mode flag - * @arg RTC_FLAG_RSF: Registers Synchronized flag - * @arg RTC_FLAG_INITS: Registers Configured flag - * @argRTC_FLAG_SHPF : Shift operation pending flag. - * @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag - * @arg RTC_FLAG_ALRBWF: Alarm B Write flag - * @arg RTC_FLAG_ALRAWF: Alarm A write flag - * @retval The new state of RTC_FLAG (SET or RESET). - */ -FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); - - /* Get all the flags */ - tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK); - - /* Return the status of the flag */ - if ((tmpreg & RTC_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC's pending flags. - * @param RTC_FLAG: specifies the RTC flag to clear. - * This parameter can be any combination of the following values: - * @arg RTC_FLAG_TAMP3F: Tamper 3 event flag - * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag - * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag - * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag - * @arg RTC_FLAG_TSF: Time Stamp event flag - * @arg RTC_FLAG_WUTF: WakeUp Timer flag - * @arg RTC_FLAG_ALRBF: Alarm B flag - * @arg RTC_FLAG_ALRAF: Alarm A flag - * @arg RTC_FLAG_RSF: Registers Synchronized flag - * @retval None - */ -void RTC_ClearFlag(uint32_t RTC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); - - /* Clear the Flags in the RTC_ISR register */ - RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0001FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); -} - -/** - * @brief Checks whether the specified RTC interrupt has occurred or not. - * @param RTC_IT: specifies the RTC interrupt source to check. - * This parameter can be one of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt - * @arg RTC_IT_WUT: WakeUp Timer interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_TAMP1: Tamper1 event interrupt - * @arg RTC_IT_TAMP2: Tamper2 event interrupt - * @arg RTC_IT_TAMP3: Tamper3 event interrupt - * @retval The new state of RTC_IT (SET or RESET). - */ -ITStatus RTC_GetITStatus(uint32_t RTC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_RTC_GET_IT(RTC_IT)); - - /* Get the TAMPER Interrupt enable bit and pending bit */ - tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE)); - - /* Get the Interrupt enable Status */ - enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & ((RTC_IT >> (RTC_IT >> 18)) >> 15))); - - /* Get the Interrupt pending bit */ - tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4))); - - /* Get the status of the Interrupt */ - if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC's interrupt pending bits. - * @param RTC_IT: specifies the RTC interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt - * @arg RTC_IT_WUT: WakeUp Timer interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_TAMP1: Tamper1 event interrupt - * @arg RTC_IT_TAMP2: Tamper2 event interrupt - * @arg RTC_IT_TAMP3: Tamper3 event interrupt - * @retval None - */ -void RTC_ClearITPendingBit(uint32_t RTC_IT) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_CLEAR_IT(RTC_IT)); - - /* Get the RTC_ISR Interrupt pending bits mask */ - tmpreg = (uint32_t)(RTC_IT >> 4); - - /* Clear the interrupt pending bits in the RTC_ISR register */ - RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); -} - -/** - * @} - */ - -/** - * @brief Converts a 2 digit decimal to BCD format. - * @param Value: Byte to be converted. - * @retval Converted byte - */ -static uint8_t RTC_ByteToBcd2(uint8_t Value) -{ - uint8_t bcdhigh = 0; - - while (Value >= 10) - { - bcdhigh++; - Value -= 10; - } - - return ((uint8_t)(bcdhigh << 4) | Value); -} - -/** - * @brief Convert from 2 digit BCD to Binary. - * @param Value: BCD value to be converted. - * @retval Converted word - */ -static uint8_t RTC_Bcd2ToByte(uint8_t Value) -{ - uint8_t tmp = 0; - tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; - return (tmp + (Value & (uint8_t)0x0F)); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_rtc.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,862 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_rtc.h - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file contains all the functions prototypes for the RTC firmware - * library. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F30x_RTC_H -#define __STM32F30x_RTC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RTC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief RTC Init structures definition - */ -typedef struct -{ - uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format. - This parameter can be a value of @ref RTC_Hour_Formats */ - - uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. - This parameter must be set to a value lower than 0x7F */ - - uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. - This parameter must be set to a value lower than 0x1FFF */ -}RTC_InitTypeDef; - -/** - * @brief RTC Time structure definition - */ -typedef struct -{ - uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour. - This parameter must be set to a value in the 0-12 range - if the RTC_HourFormat_12 is selected or 0-23 range if - the RTC_HourFormat_24 is selected. */ - - uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes. - This parameter must be set to a value in the 0-59 range. */ - - uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds. - This parameter must be set to a value in the 0-59 range. */ - - uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time. - This parameter can be a value of @ref RTC_AM_PM_Definitions */ -}RTC_TimeTypeDef; - -/** - * @brief RTC Date structure definition - */ -typedef struct -{ - uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay. - This parameter can be a value of @ref RTC_WeekDay_Definitions */ - - uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format). - This parameter can be a value of @ref RTC_Month_Date_Definitions */ - - uint8_t RTC_Date; /*!< Specifies the RTC Date. - This parameter must be set to a value in the 1-31 range. */ - - uint8_t RTC_Year; /*!< Specifies the RTC Date Year. - This parameter must be set to a value in the 0-99 range. */ -}RTC_DateTypeDef; - -/** - * @brief RTC Alarm structure definition - */ -typedef struct -{ - RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */ - - uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks. - This parameter can be a value of @ref RTC_AlarmMask_Definitions */ - - uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. - This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ - - uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. - If the Alarm Date is selected, this parameter - must be set to a value in the 1-31 range. - If the Alarm WeekDay is selected, this - parameter can be a value of @ref RTC_WeekDay_Definitions */ -}RTC_AlarmTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RTC_Exported_Constants - * @{ - */ - - -/** @defgroup RTC_Hour_Formats - * @{ - */ -#define RTC_HourFormat_24 ((uint32_t)0x00000000) -#define RTC_HourFormat_12 ((uint32_t)0x00000040) -#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \ - ((FORMAT) == RTC_HourFormat_24)) -/** - * @} - */ - -/** @defgroup RTC_Asynchronous_Predivider - * @{ - */ -#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F) - -/** - * @} - */ - - -/** @defgroup RTC_Synchronous_Predivider - * @{ - */ -#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF) - -/** - * @} - */ - -/** @defgroup RTC_Time_Definitions - * @{ - */ -#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12)) -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23) -#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59) -#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59) - -/** - * @} - */ - -/** @defgroup RTC_AM_PM_Definitions - * @{ - */ -#define RTC_H12_AM ((uint8_t)0x00) -#define RTC_H12_PM ((uint8_t)0x40) -#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM)) - -/** - * @} - */ - -/** @defgroup RTC_Year_Date_Definitions - * @{ - */ -#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99) - -/** - * @} - */ - -/** @defgroup RTC_Month_Date_Definitions - * @{ - */ - -/* Coded in BCD format */ -#define RTC_Month_January ((uint8_t)0x01) -#define RTC_Month_February ((uint8_t)0x02) -#define RTC_Month_March ((uint8_t)0x03) -#define RTC_Month_April ((uint8_t)0x04) -#define RTC_Month_May ((uint8_t)0x05) -#define RTC_Month_June ((uint8_t)0x06) -#define RTC_Month_July ((uint8_t)0x07) -#define RTC_Month_August ((uint8_t)0x08) -#define RTC_Month_September ((uint8_t)0x09) -#define RTC_Month_October ((uint8_t)0x10) -#define RTC_Month_November ((uint8_t)0x11) -#define RTC_Month_December ((uint8_t)0x12) -#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12)) -#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31)) - -/** - * @} - */ - -/** @defgroup RTC_WeekDay_Definitions - * @{ - */ - -#define RTC_Weekday_Monday ((uint8_t)0x01) -#define RTC_Weekday_Tuesday ((uint8_t)0x02) -#define RTC_Weekday_Wednesday ((uint8_t)0x03) -#define RTC_Weekday_Thursday ((uint8_t)0x04) -#define RTC_Weekday_Friday ((uint8_t)0x05) -#define RTC_Weekday_Saturday ((uint8_t)0x06) -#define RTC_Weekday_Sunday ((uint8_t)0x07) -#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ - ((WEEKDAY) == RTC_Weekday_Tuesday) || \ - ((WEEKDAY) == RTC_Weekday_Wednesday) || \ - ((WEEKDAY) == RTC_Weekday_Thursday) || \ - ((WEEKDAY) == RTC_Weekday_Friday) || \ - ((WEEKDAY) == RTC_Weekday_Saturday) || \ - ((WEEKDAY) == RTC_Weekday_Sunday)) -/** - * @} - */ - - -/** @defgroup RTC_Alarm_Definitions - * @{ - */ -#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31)) -#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ - ((WEEKDAY) == RTC_Weekday_Tuesday) || \ - ((WEEKDAY) == RTC_Weekday_Wednesday) || \ - ((WEEKDAY) == RTC_Weekday_Thursday) || \ - ((WEEKDAY) == RTC_Weekday_Friday) || \ - ((WEEKDAY) == RTC_Weekday_Saturday) || \ - ((WEEKDAY) == RTC_Weekday_Sunday)) - -/** - * @} - */ - - -/** @defgroup RTC_AlarmDateWeekDay_Definitions - * @{ - */ -#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000) -#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000) - -#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \ - ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay)) - -/** - * @} - */ - - -/** @defgroup RTC_AlarmMask_Definitions - * @{ - */ -#define RTC_AlarmMask_None ((uint32_t)0x00000000) -#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000) -#define RTC_AlarmMask_Hours ((uint32_t)0x00800000) -#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000) -#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080) -#define RTC_AlarmMask_All ((uint32_t)0x80808080) -#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) - -/** - * @} - */ - -/** @defgroup RTC_Alarms_Definitions - * @{ - */ -#define RTC_Alarm_A ((uint32_t)0x00000100) -#define RTC_Alarm_B ((uint32_t)0x00000200) -#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B)) -#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET) - -/** - * @} - */ - -/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions - * @{ - */ -#define RTC_AlarmSubSecondMask_All ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. - There is no comparison on sub seconds - for Alarm */ -#define RTC_AlarmSubSecondMask_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm - comparison. Only SS[0] is compared. */ -#define RTC_AlarmSubSecondMask_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm - comparison. Only SS[1:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm - comparison. Only SS[2:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm - comparison. Only SS[3:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm - comparison. Only SS[4:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm - comparison. Only SS[5:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm - comparison. Only SS[6:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm - comparison. Only SS[7:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm - comparison. Only SS[8:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm - comparison. Only SS[9:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm - comparison. Only SS[10:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm - comparison.Only SS[11:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm - comparison. Only SS[12:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm - comparison.Only SS[13:0] are compared */ -#define RTC_AlarmSubSecondMask_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match - to activate alarm. */ -#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14) || \ - ((MASK) == RTC_AlarmSubSecondMask_None)) -/** - * @} - */ - -/** @defgroup RTC_Alarm_Sub_Seconds_Value - * @{ - */ - -#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF) - -/** - * @} - */ - -/** @defgroup RTC_Wakeup_Timer_Definitions - * @{ - */ -#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000) -#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001) -#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002) -#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003) -#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004) -#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006) -#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \ - ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \ - ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits)) -#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) -/** - * @} - */ - -/** @defgroup RTC_Time_Stamp_Edges_definitions - * @{ - */ -#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000) -#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008) -#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \ - ((EDGE) == RTC_TimeStampEdge_Falling)) -/** - * @} - */ - -/** @defgroup RTC_Output_selection_Definitions - * @{ - */ -#define RTC_Output_Disable ((uint32_t)0x00000000) -#define RTC_Output_AlarmA ((uint32_t)0x00200000) -#define RTC_Output_AlarmB ((uint32_t)0x00400000) -#define RTC_Output_WakeUp ((uint32_t)0x00600000) - -#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \ - ((OUTPUT) == RTC_Output_AlarmA) || \ - ((OUTPUT) == RTC_Output_AlarmB) || \ - ((OUTPUT) == RTC_Output_WakeUp)) - -/** - * @} - */ - -/** @defgroup RTC_Output_Polarity_Definitions - * @{ - */ -#define RTC_OutputPolarity_High ((uint32_t)0x00000000) -#define RTC_OutputPolarity_Low ((uint32_t)0x00100000) -#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \ - ((POL) == RTC_OutputPolarity_Low)) -/** - * @} - */ - -/** @defgroup RTC_Digital_Calibration_Definitions - * @{ - */ -#define RTC_CalibSign_Positive ((uint32_t)0x00000000) -#define RTC_CalibSign_Negative ((uint32_t)0x00000080) -#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \ - ((SIGN) == RTC_CalibSign_Negative)) -#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20) - -/** - * @} - */ - - /** @defgroup RTC_Calib_Output_selection_Definitions - * @{ - */ -#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000) -#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000) -#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \ - ((OUTPUT) == RTC_CalibOutput_1Hz)) -/** - * @} - */ - -/** @defgroup RTC_Smooth_calib_period_Definitions - * @{ - */ -#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation - period is 32s, else 2exp20 RTCCLK seconds */ -#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation - period is 16s, else 2exp19 RTCCLK seconds */ -#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation - period is 8s, else 2exp18 RTCCLK seconds */ -#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \ - ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \ - ((PERIOD) == RTC_SmoothCalibPeriod_8sec)) - -/** - * @} - */ - -/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions - * @{ - */ -#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added - during a X -second window = Y - CALM[8:0]. - with Y = 512, 256, 128 when X = 32, 16, 8 */ -#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited - during a 32-second window = CALM[8:0]. */ -#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \ - ((PLUS) == RTC_SmoothCalibPlusPulses_Reset)) - -/** - * @} - */ - -/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions - * @{ - */ -#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) - -/** - * @} - */ - -/** @defgroup RTC_DayLightSaving_Definitions - * @{ - */ -#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000) -#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000) -#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \ - ((SAVE) == RTC_DayLightSaving_ADD1H)) - -#define RTC_StoreOperation_Reset ((uint32_t)0x00000000) -#define RTC_StoreOperation_Set ((uint32_t)0x00040000) -#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \ - ((OPERATION) == RTC_StoreOperation_Set)) -/** - * @} - */ - -/** @defgroup RTC_Tamper_Trigger_Definitions - * @{ - */ -#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000) -#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001) -#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000) -#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001) -#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \ - ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \ - ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \ - ((TRIGGER) == RTC_TamperTrigger_HighLevel)) - -/** - * @} - */ - -/** @defgroup RTC_Tamper_Filter_Definitions - * @{ - */ -#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ - -#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2 - consecutive samples at the active level */ -#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4 - consecutive samples at the active level */ -#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8 - consecutive samples at the active leve. */ -#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \ - ((FILTER) == RTC_TamperFilter_2Sample) || \ - ((FILTER) == RTC_TamperFilter_4Sample) || \ - ((FILTER) == RTC_TamperFilter_8Sample)) -/** - * @} - */ - -/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions - * @{ - */ -#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 32768 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 16384 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 8192 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 4096 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 2048 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 1024 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 512 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 256 */ -#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256)) - -/** - * @} - */ - - /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions - * @{ - */ -#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before - sampling during 1 RTCCLK cycle */ -#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before - sampling during 2 RTCCLK cycles */ -#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before - sampling during 4 RTCCLK cycles */ -#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before - sampling during 8 RTCCLK cycles */ - -#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \ - ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \ - ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \ - ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK)) -/** - * @} - */ - -/** @defgroup RTC_Tamper_Pins_Definitions - * @{ - */ -#define RTC_Tamper_1 RTC_TAFCR_TAMP1E /*!< Tamper detection enable for - input tamper 1 */ -#define RTC_Tamper_2 RTC_TAFCR_TAMP2E /*!< Tamper detection enable for - input tamper 2 */ -#define RTC_Tamper_3 RTC_TAFCR_TAMP3E /*!< Tamper detection enable for - input tamper 3 */ - -#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET)) - - -/** - * @} - */ - -/** @defgroup RTC_Output_Type_ALARM_OUT - * @{ - */ -#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000) -#define RTC_OutputType_PushPull ((uint32_t)0x00040000) -#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \ - ((TYPE) == RTC_OutputType_PushPull)) - -/** - * @} - */ - -/** @defgroup RTC_Add_1_Second_Parameter_Definitions - * @{ - */ -#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000) -#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000) -#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \ - ((SEL) == RTC_ShiftAdd1S_Set)) -/** - * @} - */ - -/** @defgroup RTC_Substract_Fraction_Of_Second_Value - * @{ - */ -#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) - -/** - * @} - */ - -/** @defgroup RTC_Backup_Registers_Definitions - * @{ - */ - -#define RTC_BKP_DR0 ((uint32_t)0x00000000) -#define RTC_BKP_DR1 ((uint32_t)0x00000001) -#define RTC_BKP_DR2 ((uint32_t)0x00000002) -#define RTC_BKP_DR3 ((uint32_t)0x00000003) -#define RTC_BKP_DR4 ((uint32_t)0x00000004) -#define RTC_BKP_DR5 ((uint32_t)0x00000005) -#define RTC_BKP_DR6 ((uint32_t)0x00000006) -#define RTC_BKP_DR7 ((uint32_t)0x00000007) -#define RTC_BKP_DR8 ((uint32_t)0x00000008) -#define RTC_BKP_DR9 ((uint32_t)0x00000009) -#define RTC_BKP_DR10 ((uint32_t)0x0000000A) -#define RTC_BKP_DR11 ((uint32_t)0x0000000B) -#define RTC_BKP_DR12 ((uint32_t)0x0000000C) -#define RTC_BKP_DR13 ((uint32_t)0x0000000D) -#define RTC_BKP_DR14 ((uint32_t)0x0000000E) -#define RTC_BKP_DR15 ((uint32_t)0x0000000F) -#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \ - ((BKP) == RTC_BKP_DR1) || \ - ((BKP) == RTC_BKP_DR2) || \ - ((BKP) == RTC_BKP_DR3) || \ - ((BKP) == RTC_BKP_DR4) || \ - ((BKP) == RTC_BKP_DR5) || \ - ((BKP) == RTC_BKP_DR6) || \ - ((BKP) == RTC_BKP_DR7) || \ - ((BKP) == RTC_BKP_DR8) || \ - ((BKP) == RTC_BKP_DR9) || \ - ((BKP) == RTC_BKP_DR10) || \ - ((BKP) == RTC_BKP_DR11) || \ - ((BKP) == RTC_BKP_DR12) || \ - ((BKP) == RTC_BKP_DR13) || \ - ((BKP) == RTC_BKP_DR14) || \ - ((BKP) == RTC_BKP_DR15)) -/** - * @} - */ - -/** @defgroup RTC_Input_parameter_format_definitions - * @{ - */ -#define RTC_Format_BIN ((uint32_t)0x000000000) -#define RTC_Format_BCD ((uint32_t)0x000000001) -#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD)) - -/** - * @} - */ - -/** @defgroup RTC_Flags_Definitions - * @{ - */ -#define RTC_FLAG_RECALPF ((uint32_t)0x00010000) -#define RTC_FLAG_TAMP3F ((uint32_t)0x00008000) -#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000) -#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000) -#define RTC_FLAG_TSOVF ((uint32_t)0x00001000) -#define RTC_FLAG_TSF ((uint32_t)0x00000800) -#define RTC_FLAG_WUTF ((uint32_t)0x00000400) -#define RTC_FLAG_ALRBF ((uint32_t)0x00000200) -#define RTC_FLAG_ALRAF ((uint32_t)0x00000100) -#define RTC_FLAG_INITF ((uint32_t)0x00000040) -#define RTC_FLAG_RSF ((uint32_t)0x00000020) -#define RTC_FLAG_INITS ((uint32_t)0x00000010) -#define RTC_FLAG_SHPF ((uint32_t)0x00000008) -#define RTC_FLAG_WUTWF ((uint32_t)0x00000004) -#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002) -#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001) -#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \ - ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \ - ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \ - ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \ - ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \ - ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_TAMP2F) || \ - ((FLAG) == RTC_FLAG_TAMP3F) || ((FLAG) == RTC_FLAG_RECALPF) || \ - ((FLAG) == RTC_FLAG_SHPF)) -#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET)) - -/** - * @} - */ - -/** @defgroup RTC_Interrupts_Definitions - * @{ - */ -#define RTC_IT_TS ((uint32_t)0x00008000) -#define RTC_IT_WUT ((uint32_t)0x00004000) -#define RTC_IT_ALRB ((uint32_t)0x00002000) -#define RTC_IT_ALRA ((uint32_t)0x00001000) -#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */ -#define RTC_IT_TAMP1 ((uint32_t)0x00020000) -#define RTC_IT_TAMP2 ((uint32_t)0x00040000) -#define RTC_IT_TAMP3 ((uint32_t)0x00080000) - - -#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET)) -#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \ - ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \ - ((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_TAMP2) || \ - ((IT) == RTC_IT_TAMP3)) -#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF10FFF) == (uint32_t)RESET)) - -/** - * @} - */ - -/** - * @} - */ - - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the RTC configuration to the default reset state *****/ -ErrorStatus RTC_DeInit(void); - - -/* Initialization and Configuration functions *********************************/ -ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct); -void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct); -void RTC_WriteProtectionCmd(FunctionalState NewState); -ErrorStatus RTC_EnterInitMode(void); -void RTC_ExitInitMode(void); -ErrorStatus RTC_WaitForSynchro(void); -ErrorStatus RTC_RefClockCmd(FunctionalState NewState); -void RTC_BypassShadowCmd(FunctionalState NewState); - -/* Time and Date configuration functions **************************************/ -ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); -void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct); -void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); -uint32_t RTC_GetSubSecond(void); -ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); -void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct); -void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); - -/* Alarms (Alarm A and Alarm B) configuration functions **********************/ -void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); -void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct); -void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); -ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState); -void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask); -uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm); - -/* WakeUp Timer configuration functions ***************************************/ -void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock); -void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter); -uint32_t RTC_GetWakeUpCounter(void); -ErrorStatus RTC_WakeUpCmd(FunctionalState NewState); - -/* Daylight Saving configuration functions ************************************/ -void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation); -uint32_t RTC_GetStoreOperation(void); - -/* Output pin Configuration function ******************************************/ -void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity); - -/* Digital Calibration configuration functions ********************************/ -void RTC_CalibOutputCmd(FunctionalState NewState); -void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput); -ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, - uint32_t RTC_SmoothCalibPlusPulses, - uint32_t RTC_SmouthCalibMinusPulsesValue); - -/* TimeStamp configuration functions ******************************************/ -void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState); -void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, - RTC_DateTypeDef* RTC_StampDateStruct); -uint32_t RTC_GetTimeStampSubSecond(void); - -/* Tampers configuration functions ********************************************/ -void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger); -void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState); -void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter); -void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq); -void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration); -void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState); -void RTC_TamperPullUpCmd(FunctionalState NewState); - -/* Backup Data Registers configuration functions ******************************/ -void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data); -uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR); - -/* Output Type Config configuration functions *********************************/ -void RTC_OutputTypeConfig(uint32_t RTC_OutputType); - -/* RTC_Shift_control_synchonisation_functions *********************************/ -ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS); - -/* Interrupts and flags management functions **********************************/ -void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState); -FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG); -void RTC_ClearFlag(uint32_t RTC_FLAG); -ITStatus RTC_GetITStatus(uint32_t RTC_IT); -void RTC_ClearITPendingBit(uint32_t RTC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F30x_RTC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_spi.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1420 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_spi.c - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Serial peripheral interface (SPI): - * + Initialization and Configuration - * + Data transfers functions - * + Hardware CRC Calculation - * + DMA transfers management - * + Interrupts and flags management - * - * @verbatim - - - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable peripheral clock using RCC_APBPeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) - function for SPI1 or using RCC_APBPeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) - function for SPI2. - (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHBPeriphClockCmd() - function. - (#) Peripherals alternate function: - (++) Connect the pin to the desired peripherals' Alternate - Function (AF) using GPIO_PinAFConfig() function. - (++) Configure the desired pin in alternate function by: - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF. - (++) Select the type, pull-up/pull-down and output speed via - GPIO_PuPd, GPIO_OType and GPIO_Speed members. - (++) Call GPIO_Init() function. - (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave - Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() - function in SPI mode. In I2S mode, program the Mode, Standard, Data Format, - MCLK Output, Audio frequency and Polarity using I2S_Init() function. - (#) Configure the FIFO threshold using SPI_RxFIFOThresholdConfig() to select - at which threshold the RXNE event is generated. - (#) Enable the NVIC and the corresponding interrupt using the function - SPI_I2S_ITConfig() if you need to use interrupt mode. - (#) When using the DMA mode - (++) Configure the DMA using DMA_Init() function. - (++) Active the needed channel Request using SPI_I2S_DMACmd() function. - (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using - I2S_Cmd(). - (#) Enable the DMA using the DMA_Cmd() function when using DMA mode. - (#) Optionally you can enable/configure the following parameters without - re-initialization (i.e there is no need to call again SPI_Init() function): - (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx) - is programmed as Data direction parameter using the SPI_Init() function - it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx - using the SPI_BiDirectionalLineConfig() function. - (++) When SPI_NSS_Soft is selected as Slave Select Management parameter - using the SPI_Init() function it can be possible to manage the - NSS internal signal using the SPI_NSSInternalSoftwareConfig() function. - (++) Reconfigure the data size using the SPI_DataSizeConfig() function. - (++) Enable or disable the SS output using the SPI_SSOutputCmd() function. - (#) To use the CRC Hardware calculation feature refer to the Peripheral - CRC hardware Calculation subsection. - [..] It is possible to use SPI in I2S full duplex mode, in this case, each SPI - peripheral is able to manage sending and receiving data simultaneously - using two data lines. Each SPI peripheral has an extended block called I2Sxext - (ie. I2S2ext for SPI2 and I2S3ext for SPI3). - The extension block is not a full SPI IP, it is used only as I2S slave to - implement full duplex mode. The extension block uses the same clock sources - as its master. - To configure I2S full duplex you have to: - (#) Configure SPIx in I2S mode (I2S_Init() function) as described above. - (#) Call the I2S_FullDuplexConfig() function using the same strucutre passed to - I2S_Init() function. - (#) Call I2S_Cmd() for SPIx then for its extended block. - (#) Configure interrupts or DMA requests and to get/clear flag status, - use I2Sxext instance for the extension block. - [..] Functions that can be called with I2Sxext instances are: - I2S_Cmd(), I2S_FullDuplexConfig(), SPI_I2S_ReceiveData16(), SPI_I2S_SendData16(), - SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_I2S_GetFlagStatus(), SPI_I2S_ClearFlag(), - SPI_I2S_GetITStatus() and SPI_I2S_ClearITPendingBit(). - [..] Example: To use SPI3 in Full duplex mode (SPI3 is Master Tx, I2S3ext is Slave Rx): - [..] RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE); - I2S_StructInit(&I2SInitStruct); - I2SInitStruct.Mode = I2S_Mode_MasterTx; - I2S_Init(SPI3, &I2SInitStruct); - I2S_FullDuplexConfig(SPI3ext, &I2SInitStruct) - I2S_Cmd(SPI3, ENABLE); - I2S_Cmd(SPI3ext, ENABLE); - ... - while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET) - {} - SPI_I2S_SendData16(SPI3, txdata[i]); - ... - while (SPI_I2S_GetFlagStatus(I2S3ext, SPI_FLAG_RXNE) == RESET) - {} - rxdata[i] = SPI_I2S_ReceiveData16(I2S3ext); - ... - [..] - (@) In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd() - just after calling the function SPI_Init(). - - @endverbatim - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x_spi.h" -#include "stm32f30x_rcc.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @defgroup SPI - * @brief SPI driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* SPI registers Masks */ -#define CR1_CLEAR_MASK ((uint16_t)0x3040) -#define CR2_LDMA_MASK ((uint16_t)0x9FFF) - -#define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SPI_Private_Functions - * @{ - */ - -/** @defgroup SPI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides a set of functions allowing to initialize the SPI Direction, - SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud - Rate Prescaler, SPI First Bit and SPI CRC Polynomial. - [..] The SPI_Init() function follows the SPI configuration procedures for Master mode - and Slave mode (details for these procedures are available in reference manual). - [..] When the Software NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Soft) is selected, - use the following function to manage the NSS bit: - void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); - [..] In Master mode, when the Hardware NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Hard) - is selected, use the follwoing function to enable the NSS output feature. - void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); - [..] The NSS pulse mode can be managed by the SPI TI mode when enabling it using the - following function: void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); - And it can be managed by software in the SPI Motorola mode using this function: - void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); - [..] This section provides also functions to initialize the I2S Mode, Standard, - Data Format, MCLK Output, Audio frequency and Polarity. - [..] The I2S_Init() function follows the I2S configuration procedures for Master mode - and Slave mode. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the SPIx peripheral registers to their default - * reset values. - * @param SPIx: To select the SPIx peripheral, where x can be: 1, 2 or 3 - * in SPI mode. - * @retval None - */ -void SPI_I2S_DeInit(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - if (SPIx == SPI1) - { - /* Enable SPI1 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); - /* Release SPI1 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); - } - else if (SPIx == SPI2) - { - /* Enable SPI2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); - /* Release SPI2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); - } - else - { - if (SPIx == SPI3) - { - /* Enable SPI3 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); - /* Release SPI3 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); - } - } -} - -/** - * @brief Fills each SPI_InitStruct member with its default value. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized. - * @retval None - */ -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) -{ -/*--------------- Reset SPI init structure parameters values -----------------*/ - /* Initialize the SPI_Direction member */ - SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; - /* Initialize the SPI_Mode member */ - SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; - /* Initialize the SPI_DataSize member */ - SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; - /* Initialize the SPI_CPOL member */ - SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; - /* Initialize the SPI_CPHA member */ - SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; - /* Initialize the SPI_NSS member */ - SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; - /* Initialize the SPI_BaudRatePrescaler member */ - SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - /* Initialize the SPI_FirstBit member */ - SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; - /* Initialize the SPI_CRCPolynomial member */ - SPI_InitStruct->SPI_CRCPolynomial = 7; -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the SPI_InitStruct. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral. - * @retval None - */ -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) -{ - uint16_t tmpreg = 0; - - /* check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Check the SPI parameters */ - assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); - assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); - assert_param(IS_SPI_DATA_SIZE(SPI_InitStruct->SPI_DataSize)); - assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); - assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); - assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); - assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); - assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); - assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); - - /* Configuring the SPI in master mode */ - if(SPI_InitStruct->SPI_Mode == SPI_Mode_Master) - { -/*---------------------------- SPIx CR1 Configuration ------------------------*/ - /* Get the SPIx CR1 value */ - tmpreg = SPIx->CR1; - /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ - tmpreg &= CR1_CLEAR_MASK; - /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler - master/slave mode, CPOL and CPHA */ - /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ - /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ - /* Set LSBFirst bit according to SPI_FirstBit value */ - /* Set BR bits according to SPI_BaudRatePrescaler value */ - /* Set CPOL bit according to SPI_CPOL value */ - /* Set CPHA bit according to SPI_CPHA value */ - tmpreg |= (uint16_t)((uint16_t)(SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode) | - (uint16_t)((uint16_t)(SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA) | - (uint16_t)((uint16_t)(SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler) | - SPI_InitStruct->SPI_FirstBit))); - /* Write to SPIx CR1 */ - SPIx->CR1 = tmpreg; - /*-------------------------Data Size Configuration -----------------------*/ - /* Get the SPIx CR2 value */ - tmpreg = SPIx->CR2; - /* Clear DS[3:0] bits */ - tmpreg &= (uint16_t)~SPI_CR2_DS; - /* Configure SPIx: Data Size */ - tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize); - /* Write to SPIx CR2 */ - SPIx->CR2 = tmpreg; - } - /* Configuring the SPI in slave mode */ - else - { -/*---------------------------- Data size Configuration -----------------------*/ - /* Get the SPIx CR2 value */ - tmpreg = SPIx->CR2; - /* Clear DS[3:0] bits */ - tmpreg &= (uint16_t)~SPI_CR2_DS; - /* Configure SPIx: Data Size */ - tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize); - /* Write to SPIx CR2 */ - SPIx->CR2 = tmpreg; -/*---------------------------- SPIx CR1 Configuration ------------------------*/ - /* Get the SPIx CR1 value */ - tmpreg = SPIx->CR1; - /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ - tmpreg &= CR1_CLEAR_MASK; - /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler - master/salve mode, CPOL and CPHA */ - /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ - /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ - /* Set LSBFirst bit according to SPI_FirstBit value */ - /* Set BR bits according to SPI_BaudRatePrescaler value */ - /* Set CPOL bit according to SPI_CPOL value */ - /* Set CPHA bit according to SPI_CPHA value */ - tmpreg |= (uint16_t)((uint16_t)(SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode) | - (uint16_t)((uint16_t)(SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA) | - (uint16_t)((uint16_t)(SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler) | - SPI_InitStruct->SPI_FirstBit))); - - /* Write to SPIx CR1 */ - SPIx->CR1 = tmpreg; - } - - /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ - SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD); - -/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ - /* Write to SPIx CRCPOLY */ - SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; -} - -/** - * @brief Fills each I2S_InitStruct member with its default value. - * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) -{ -/*--------------- Reset I2S init structure parameters values -----------------*/ - /* Initialize the I2S_Mode member */ - I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; - - /* Initialize the I2S_Standard member */ - I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; - - /* Initialize the I2S_DataFormat member */ - I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; - - /* Initialize the I2S_MCLKOutput member */ - I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; - - /* Initialize the I2S_AudioFreq member */ - I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; - - /* Initialize the I2S_CPOL member */ - I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the I2S_InitStruct. - * @param SPIx:To select the SPIx peripheral, where x can be: 2 or 3 - * in I2S mode. - * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral - * configured in I2S mode. - * @note - * The function calculates the optimal prescaler needed to obtain the most - * accurate audio frequency (depending on the I2S clock source, the PLL values - * and the product configuration). But in case the prescaler value is greater - * than 511, the default value (0x02) will be configured instead. - * @retval None - */ -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) -{ - uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; - uint32_t tmp = 0; - RCC_ClocksTypeDef RCC_Clocks; - uint32_t sourceclock = 0; - - /* Check the I2S parameters */ - assert_param(IS_SPI_23_PERIPH(SPIx)); - assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); - assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); - assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); - assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); - assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); - assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); - -/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ - /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK; - SPIx->I2SPR = 0x0002; - - /* Get the I2SCFGR register value */ - tmpreg = SPIx->I2SCFGR; - - /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ - if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) - { - i2sodd = (uint16_t)0; - i2sdiv = (uint16_t)2; - } - /* If the requested audio frequency is not the default, compute the prescaler */ - else - { - /* Check the frame length (For the Prescaler computing) */ - if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) - { - /* Packet length is 16 bits */ - packetlength = 1; - } - else - { - /* Packet length is 32 bits */ - packetlength = 2; - } - - /* I2S Clock source is System clock: Get System Clock frequency */ - RCC_GetClocksFreq(&RCC_Clocks); - - /* Get the source clock value: based on System Clock value */ - sourceclock = RCC_Clocks.SYSCLK_Frequency; - - /* Compute the Real divider depending on the MCLK output state with a floating point */ - if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) - { - /* MCLK output is enabled */ - tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - else - { - /* MCLK output is disabled */ - tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - - /* Remove the floating point */ - tmp = tmp / 10; - - /* Check the parity of the divider */ - i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); - - /* Compute the i2sdiv prescaler */ - i2sdiv = (uint16_t)((tmp - i2sodd) / 2); - - /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ - i2sodd = (uint16_t) (i2sodd << 8); - } - - /* Test if the divider is 1 or 0 or greater than 0xFF */ - if ((i2sdiv < 2) || (i2sdiv > 0xFF)) - { - /* Set the default values */ - i2sdiv = 2; - i2sodd = 0; - } - - /* Write to SPIx I2SPR register the computed value */ - SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); - - /* Configure the I2S with the SPI_InitStruct values */ - tmpreg |= (uint16_t)((uint16_t)(SPI_I2SCFGR_I2SMOD | I2S_InitStruct->I2S_Mode) | \ - (uint16_t)((uint16_t)((uint16_t)(I2S_InitStruct->I2S_Standard |I2S_InitStruct->I2S_DataFormat) |\ - I2S_InitStruct->I2S_CPOL))); - - /* Write to SPIx I2SCFGR */ - SPIx->I2SCFGR = tmpreg; -} - -/** - * @brief Enables or disables the specified SPI peripheral. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral */ - SPIx->CR1 |= SPI_CR1_SPE; - } - else - { - /* Disable the selected SPI peripheral */ - SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE); - } -} - -/** - * @brief Enables or disables the TI Mode. - * @note This function can be called only after the SPI_Init() function has - * been called. - * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA - * are not taken into consideration and are configured by hardware - * respectively to the TI mode requirements. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the selected SPI TI communication mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TI mode for the selected SPI peripheral */ - SPIx->CR2 |= SPI_CR2_FRF; - } - else - { - /* Disable the TI mode for the selected SPI peripheral */ - SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRF); - } -} - -/** - * @brief Enables or disables the specified SPI peripheral (in I2S mode). - * @param SPIx:To select the SPIx peripheral, where x can be: 2 or 3 in - * I2S mode or I2Sxext for I2S full duplex mode. - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_23_PERIPH_EXT(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral in I2S mode */ - SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE; - } - else - { - /* Disable the selected SPI peripheral in I2S mode */ - SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE); - } -} - -/** - * @brief Configures the data size for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_DataSize: specifies the SPI data size. - * For the SPIx peripheral this parameter can be one of the following values: - * @arg SPI_DataSize_4b: Set data size to 4 bits - * @arg SPI_DataSize_5b: Set data size to 5 bits - * @arg SPI_DataSize_6b: Set data size to 6 bits - * @arg SPI_DataSize_7b: Set data size to 7 bits - * @arg SPI_DataSize_8b: Set data size to 8 bits - * @arg SPI_DataSize_9b: Set data size to 9 bits - * @arg SPI_DataSize_10b: Set data size to 10 bits - * @arg SPI_DataSize_11b: Set data size to 11 bits - * @arg SPI_DataSize_12b: Set data size to 12 bits - * @arg SPI_DataSize_13b: Set data size to 13 bits - * @arg SPI_DataSize_14b: Set data size to 14 bits - * @arg SPI_DataSize_15b: Set data size to 15 bits - * @arg SPI_DataSize_16b: Set data size to 16 bits - * @retval None - */ -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) -{ - uint16_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DATA_SIZE(SPI_DataSize)); - /* Read the CR2 register */ - tmpreg = SPIx->CR2; - /* Clear DS[3:0] bits */ - tmpreg &= (uint16_t)~SPI_CR2_DS; - /* Set new DS[3:0] bits value */ - tmpreg |= SPI_DataSize; - SPIx->CR2 = tmpreg; -} - -/** - * @brief Configures the FIFO reception threshold for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_RxFIFOThreshold: specifies the FIFO reception threshold. - * This parameter can be one of the following values: - * @arg SPI_RxFIFOThreshold_HF: RXNE event is generated if the FIFO - * level is greater or equal to 1/2. - * @arg SPI_RxFIFOThreshold_QF: RXNE event is generated if the FIFO - * level is greater or equal to 1/4. - * @retval None - */ -void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_RX_FIFO_THRESHOLD(SPI_RxFIFOThreshold)); - - /* Clear FRXTH bit */ - SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRXTH); - - /* Set new FRXTH bit value */ - SPIx->CR2 |= SPI_RxFIFOThreshold; -} - -/** - * @brief Selects the data transfer direction in bidirectional mode for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. - * This parameter can be one of the following values: - * @arg SPI_Direction_Tx: Selects Tx transmission direction - * @arg SPI_Direction_Rx: Selects Rx receive direction - * @retval None - */ -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DIRECTION(SPI_Direction)); - if (SPI_Direction == SPI_Direction_Tx) - { - /* Set the Tx only mode */ - SPIx->CR1 |= SPI_Direction_Tx; - } - else - { - /* Set the Rx only mode */ - SPIx->CR1 &= SPI_Direction_Rx; - } -} - -/** - * @brief Configures internally by software the NSS pin for the selected SPI. - * @note This function can be called only after the SPI_Init() function has - * been called. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. - * This parameter can be one of the following values: - * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally - * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally - * @retval None - */ -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); - - if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) - { - /* Set NSS pin internally by software */ - SPIx->CR1 |= SPI_NSSInternalSoft_Set; - } - else - { - /* Reset NSS pin internally by software */ - SPIx->CR1 &= SPI_NSSInternalSoft_Reset; - } -} - -/** - * @brief Configures the full duplex mode for the I2Sx peripheral using its - * extension I2Sxext according to the specified parameters in the - * I2S_InitStruct. - * @param I2Sxext: where x can be 2 or 3 to select the I2S peripheral extension block. - * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that - * contains the configuration information for the specified I2S peripheral - * extension. - * - * @note The structure pointed by I2S_InitStruct parameter should be the same - * used for the master I2S peripheral. In this case, if the master is - * configured as transmitter, the slave will be receiver and vice versa. - * Or you can force a different mode by modifying the field I2S_Mode to the - * value I2S_SlaveRx or I2S_SlaveTx indepedently of the master configuration. - * - * @note The I2S full duplex extension can be configured in slave mode only. - * - * @retval None - */ -void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct) -{ - uint16_t tmpreg = 0, tmp = 0; - - /* Check the I2S parameters */ - assert_param(IS_I2S_EXT_PERIPH(I2Sxext)); - assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); - assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); - assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); - assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); - -/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ - /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - I2Sxext->I2SCFGR &= I2SCFGR_CLEAR_MASK; - I2Sxext->I2SPR = 0x0002; - - /* Get the I2SCFGR register value */ - tmpreg = I2Sxext->I2SCFGR; - - /* Get the mode to be configured for the extended I2S */ - if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx)) - { - tmp = I2S_Mode_SlaveRx; - } - else - { - if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveRx)) - { - tmp = I2S_Mode_SlaveTx; - } - } - - - /* Configure the I2S with the SPI_InitStruct values */ - tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \ - (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ - (uint16_t)I2S_InitStruct->I2S_CPOL)))); - - /* Write to SPIx I2SCFGR */ - I2Sxext->I2SCFGR = tmpreg; -} - -/** - * @brief Enables or disables the SS output for the selected SPI. - * @note This function can be called only after the SPI_Init() function has - * been called and the NSS hardware management mode is selected. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx SS output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI SS output */ - SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE; - } - else - { - /* Disable the selected SPI SS output */ - SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE); - } -} - -/** - * @brief Enables or disables the NSS pulse management mode. - * @note This function can be called only after the SPI_Init() function has - * been called. - * @note When TI mode is selected, the control bits NSSP is not taken into - * consideration and are configured by hardware respectively to the - * TI mode requirements. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the NSS pulse management mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the NSS pulse management mode */ - SPIx->CR2 |= SPI_CR2_NSSP; - } - else - { - /* Disable the NSS pulse management mode */ - SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_NSSP); - } -} - -/** - * @} - */ - -/** @defgroup SPI_Group2 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### Data transfers functions ##### - =============================================================================== - [..] This section provides a set of functions allowing to manage the SPI or I2S - data transfers. - [..] In reception, data are received and then stored into an internal Rx buffer while - In transmission, data are first stored into an internal Tx buffer before being - transmitted. - [..] The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData() - function and returns the Rx buffered value. Whereas a write access to the SPI_DR - can be done using SPI_I2S_SendData() function and stores the written data into - Tx buffer. - -@endverbatim - * @{ - */ - -/** - * @brief Transmits a Data through the SPIx peripheral. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param Data: Data to be transmitted. - * @retval None - */ -void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data) -{ - uint32_t spixbase = 0x00; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - spixbase = (uint32_t)SPIx; - spixbase += 0x0C; - - *(__IO uint8_t *) spixbase = Data; -} - -/** - * @brief Transmits a Data through the SPIx/I2Sx peripheral. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param Data: Data to be transmitted. - * @retval None - */ -void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - - SPIx->DR = (uint16_t)Data; -} - -/** - * @brief Returns the most recent received data by the SPIx peripheral. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval The value of the received data. - */ -uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx) -{ - uint32_t spixbase = 0x00; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - - spixbase = (uint32_t)SPIx; - spixbase += 0x0C; - - return *(__IO uint8_t *) spixbase; -} - -/** - * @brief Returns the most recent received data by the SPIx peripheral. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @retval The value of the received data. - */ -uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - - return SPIx->DR; -} -/** - * @} - */ - -/** @defgroup SPI_Group3 Hardware CRC Calculation functions - * @brief Hardware CRC Calculation functions - * -@verbatim - =============================================================================== - ##### Hardware CRC Calculation functions ##### - =============================================================================== - [..] This section provides a set of functions allowing to manage the SPI CRC hardware - calculation. - [..] SPI communication using CRC is possible through the following procedure: - (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, - Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() - function. - (#) Enable the CRC calculation using the SPI_CalculateCRC() function. - (#) Enable the SPI using the SPI_Cmd() function - (#) Before writing the last data to the TX buffer, set the CRCNext bit using the - SPI_TransmitCRC() function to indicate that after transmission of the last - data, the CRC should be transmitted. - (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT - bit is reset. The CRC is also received and compared against the SPI_RXCRCR - value. - If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt - can be generated when the SPI_I2S_IT_ERR interrupt is enabled. - [..] - (@) - (+@) It is advised to don't read the calculate CRC values during the communication. - (+@) When the SPI is in slave mode, be careful to enable CRC calculation only - when the clock is stable, that is, when the clock is in the steady state. - If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive - to the SCK slave input clock as soon as CRCEN is set, and this, whatever - the value of the SPE bit. - (+@) With high bitrate frequencies, be careful when transmitting the CRC. - As the number of used CPU cycles has to be as low as possible in the CRC - transfer phase, it is forbidden to call software functions in the CRC - transmission sequence to avoid errors in the last data and CRC reception. - In fact, CRCNEXT bit has to be written before the end of the transmission/reception - of the last data. - (+@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the - degradation of the SPI speed performance due to CPU accesses impacting the - SPI bandwidth. - (+@) When the STM32F30x are configured as slaves and the NSS hardware mode is - used, the NSS pin needs to be kept low between the data phase and the CRC - phase. - (+@) When the SPI is configured in slave mode with the CRC feature enabled, CRC - calculation takes place even if a high level is applied on the NSS pin. - This may happen for example in case of a multislave environment where the - communication master addresses slaves alternately. - (+@) Between a slave deselection (high level on NSS) and a new slave selection - (low level on NSS), the CRC value should be cleared on both master and slave - sides in order to resynchronize the master and slave for their respective - CRC calculation. - [..] - (@) To clear the CRC, follow the procedure below: - (#@) Disable SPI using the SPI_Cmd() function. - (#@) Disable the CRC calculation using the SPI_CalculateCRC() function. - (#@) Enable the CRC calculation using the SPI_CalculateCRC() function. - (#@) Enable SPI using the SPI_Cmd() function. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the CRC calculation length for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_CRCLength: specifies the SPI CRC calculation length. - * This parameter can be one of the following values: - * @arg SPI_CRCLength_8b: Set CRC Calculation to 8 bits - * @arg SPI_CRCLength_16b: Set CRC Calculation to 16 bits - * @retval None - */ -void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_CRC_LENGTH(SPI_CRCLength)); - - /* Clear CRCL bit */ - SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCL); - - /* Set new CRCL bit value */ - SPIx->CR1 |= SPI_CRCLength; -} - -/** - * @brief Enables or disables the CRC value calculation of the transferred bytes. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx CRC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected SPI CRC calculation */ - SPIx->CR1 |= SPI_CR1_CRCEN; - } - else - { - /* Disable the selected SPI CRC calculation */ - SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN); - } -} - -/** - * @brief Transmits the SPIx CRC value. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval None - */ -void SPI_TransmitCRC(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Enable the selected SPI CRC transmission */ - SPIx->CR1 |= SPI_CR1_CRCNEXT; -} - -/** - * @brief Returns the transmit or the receive CRC register value for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_CRC: specifies the CRC register to be read. - * This parameter can be one of the following values: - * @arg SPI_CRC_Tx: Selects Tx CRC register - * @arg SPI_CRC_Rx: Selects Rx CRC register - * @retval The selected CRC register value.. - */ -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) -{ - uint16_t crcreg = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_CRC(SPI_CRC)); - - if (SPI_CRC != SPI_CRC_Rx) - { - /* Get the Tx CRC register */ - crcreg = SPIx->TXCRCR; - } - else - { - /* Get the Rx CRC register */ - crcreg = SPIx->RXCRCR; - } - /* Return the selected CRC register */ - return crcreg; -} - -/** - * @brief Returns the CRC Polynomial register value for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval The CRC Polynomial register value. - */ -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Return the CRC polynomial register */ - return SPIx->CRCPR; -} - -/** - * @} - */ - -/** @defgroup SPI_Group4 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - ##### DMA transfers management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the SPIx/I2Sx DMA interface. - * @param SPIx:To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request - * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request - * @param NewState: new state of the selected SPI DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_DMA_REQ(SPI_I2S_DMAReq)); - - if (NewState != DISABLE) - { - /* Enable the selected SPI DMA requests */ - SPIx->CR2 |= SPI_I2S_DMAReq; - } - else - { - /* Disable the selected SPI DMA requests */ - SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; - } -} - -/** - * @brief Configures the number of data to transfer type(Even/Odd) for the DMA - * last transfers and for the selected SPI. - * @note This function have a meaning only if DMA mode is selected and if - * the packing mode is used (data length <= 8 and DMA transfer size halfword) - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_LastDMATransfer: specifies the SPI last DMA transfers state. - * This parameter can be one of the following values: - * @arg SPI_LastDMATransfer_TxEvenRxEven: Number of data for transmission Even - * and number of data for reception Even. - * @arg SPI_LastDMATransfer_TxOddRxEven: Number of data for transmission Odd - * and number of data for reception Even. - * @arg SPI_LastDMATransfer_TxEvenRxOdd: Number of data for transmission Even - * and number of data for reception Odd. - * @arg SPI_LastDMATransfer_TxOddRxOdd: RNumber of data for transmission Odd - * and number of data for reception Odd. - * @retval None - */ -void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_LAST_DMA_TRANSFER(SPI_LastDMATransfer)); - - /* Clear LDMA_TX and LDMA_RX bits */ - SPIx->CR2 &= CR2_LDMA_MASK; - - /* Set new LDMA_TX and LDMA_RX bits value */ - SPIx->CR2 |= SPI_LastDMATransfer; -} - -/** - * @} - */ - -/** @defgroup SPI_Group5 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - [..] This section provides a set of functions allowing to configure the SPI/I2S - Interrupts sources and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. - - *** Polling Mode *** - ==================== - [..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags: - (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register. - (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register. - (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI. - (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur. - (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur. - (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur. - (#) SPI_I2S_FLAG_FRE: to indicate a Frame Format error occurs. - (#) I2S_FLAG_UDR: to indicate an Underrun error occurs. - (#) I2S_FLAG_CHSIDE: to indicate Channel Side. - [..] - (@) Do not use the BSY flag to handle each data transmission or reception. - It is better to use the TXE and RXNE flags instead. - [..] In this Mode it is advised to use the following functions: - (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); - (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); - - *** Interrupt Mode *** - ====================== - [..] In Interrupt Mode, the SPI/I2S communication can be managed by 3 interrupt sources - and 5 pending bits: - [..] Pending Bits: - (#) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register. - (#) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register. - (#) SPI_I2S_IT_OVR : to indicate if an Overrun error occur. - (#) I2S_IT_UDR : to indicate an Underrun Error occurs. - (#) SPI_I2S_FLAG_FRE : to indicate a Frame Format error occurs. - [..] Interrupt Source: - (#) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty - interrupt. - (#) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not - empty interrupt. - (#) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt. - [..] In this Mode it is advised to use the following functions: - (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); - (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - - *** FIFO Status *** - =================== - [..] It is possible to monitor the FIFO status when a transfer is ongoing using the - following function: - (+) uint32_t SPI_GetFIFOStatus(uint8_t SPI_FIFO_Direction); - - *** DMA Mode *** - ================ - [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests: - (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request. - (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request. - [..] In this Mode it is advised to use the following function: - (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified SPI/I2S interrupts. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask - * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask - * @arg SPI_I2S_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified SPI interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) -{ - uint16_t itpos = 0, itmask = 0 ; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); - - /* Get the SPI IT index */ - itpos = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = (uint16_t)1 << (uint16_t)itpos; - - if (NewState != DISABLE) - { - /* Enable the selected SPI interrupt */ - SPIx->CR2 |= itmask; - } - else - { - /* Disable the selected SPI interrupt */ - SPIx->CR2 &= (uint16_t)~itmask; - } -} - -/** - * @brief Returns the current SPIx Transmission FIFO filled level. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval The Transmission FIFO filling state. - * - SPI_TransmissionFIFOStatus_Empty: when FIFO is empty - * - SPI_TransmissionFIFOStatus_1QuarterFull: if more than 1 quarter-full. - * - SPI_TransmissionFIFOStatus_HalfFull: if more than 1 half-full. - * - SPI_TransmissionFIFOStatus_Full: when FIFO is full. - */ -uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx) -{ - /* Get the SPIx Transmission FIFO level bits */ - return (uint16_t)((SPIx->SR & SPI_SR_FTLVL)); -} - -/** - * @brief Returns the current SPIx Reception FIFO filled level. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval The Reception FIFO filling state. - * - SPI_ReceptionFIFOStatus_Empty: when FIFO is empty - * - SPI_ReceptionFIFOStatus_1QuarterFull: if more than 1 quarter-full. - * - SPI_ReceptionFIFOStatus_HalfFull: if more than 1 half-full. - * - SPI_ReceptionFIFOStatus_Full: when FIFO is full. - */ -uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx) -{ - /* Get the SPIx Reception FIFO level bits */ - return (uint16_t)((SPIx->SR & SPI_SR_FRLVL)); -} - -/** - * @brief Checks whether the specified SPI flag is set or not. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_FLAG: specifies the SPI flag to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. - * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. - * @arg SPI_I2S_FLAG_BSY: Busy flag. - * @arg SPI_I2S_FLAG_OVR: Overrun flag. - * @arg SPI_I2S_FLAG_MODF: Mode Fault flag. - * @arg SPI_I2S_FLAG_CRCERR: CRC Error flag. - * @arg SPI_I2S_FLAG_FRE: TI frame format error flag. - * @arg I2S_FLAG_UDR: Underrun Error flag. - * @arg I2S_FLAG_CHSIDE: Channel Side flag. - * @retval The new state of SPI_I2S_FLAG (SET or RESET). - */ -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); - - /* Check the status of the specified SPI flag */ - if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) - { - /* SPI_I2S_FLAG is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_FLAG is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) flag. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_FLAG: specifies the SPI flag to clear. - * This function clears only CRCERR flag. - * @note OVR (OverRun error) flag is cleared by software sequence: a read - * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). - * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a - * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). - * @retval None - */ -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_SPI_CLEAR_FLAG(SPI_I2S_FLAG)); - - /* Clear the selected SPI CRC Error (CRCERR) flag */ - SPIx->SR = (uint16_t)~SPI_I2S_FLAG; -} - -/** - * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_IT: specifies the SPI interrupt source to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. - * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. - * @arg SPI_IT_MODF: Mode Fault interrupt. - * @arg SPI_I2S_IT_OVR: Overrun interrupt. - * @arg I2S_IT_UDR: Underrun interrupt. - * @arg SPI_I2S_IT_FRE: Format Error interrupt. - * @retval The new state of SPI_I2S_IT (SET or RESET). - */ -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itpos = 0, itmask = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); - - /* Get the SPI_I2S_IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Get the SPI_I2S_IT IT mask */ - itmask = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = 0x01 << itmask; - - /* Get the SPI_I2S_IT enable bit status */ - enablestatus = (SPIx->CR2 & itmask) ; - - /* Check the status of the specified SPI interrupt */ - if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) - { - /* SPI_I2S_IT is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_IT is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_IT status */ - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_spi.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,616 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_spi.h - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file contains all the functions prototypes for the SPI - * firmware library. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F30x_SPI_H -#define __STM32F30x_SPI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief SPI Init structure definition - */ - -typedef struct -{ - uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be a value of @ref SPI_data_direction */ - - uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave). - This parameter can be a value of @ref SPI_mode */ - - uint16_t SPI_DataSize; /*!< Specifies the SPI data size. - This parameter can be a value of @ref SPI_data_size */ - - uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ - - uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_Clock_Phase */ - - uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by - hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_Slave_Select_management */ - - uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be - used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_BaudRate_Prescaler. - @note The communication clock is derived from the master - clock. The slave clock does not need to be set. */ - - uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SPI_MSB_LSB_transmission */ - - uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ -}SPI_InitTypeDef; - - -/** - * @brief I2S Init structure definition - */ - -typedef struct -{ - uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. - This parameter can be a value of @ref I2S_Mode */ - - uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. - This parameter can be a value of @ref I2S_Standard */ - - uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. - This parameter can be a value of @ref I2S_Data_Format */ - - uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. - This parameter can be a value of @ref I2S_MCLK_Output */ - - uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. - This parameter can be a value of @ref I2S_Audio_Frequency */ - - uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. - This parameter can be a value of @ref I2S_Clock_Polarity */ -}I2S_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SPI_Exported_Constants - * @{ - */ - -#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ - ((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3)) - -#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \ - ((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3) || \ - ((PERIPH) == I2S2ext) || \ - ((PERIPH) == I2S3ext)) - -#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3)) - -#define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3) || \ - ((PERIPH) == I2S2ext) || \ - ((PERIPH) == I2S3ext)) - -#define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \ - ((PERIPH) == I2S3ext)) - -/** @defgroup SPI_data_direction - * @{ - */ - -#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) -#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) -#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) -#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) -#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ - ((MODE) == SPI_Direction_2Lines_RxOnly) || \ - ((MODE) == SPI_Direction_1Line_Rx) || \ - ((MODE) == SPI_Direction_1Line_Tx)) -/** - * @} - */ - -/** @defgroup SPI_mode - * @{ - */ - -#define SPI_Mode_Master ((uint16_t)0x0104) -#define SPI_Mode_Slave ((uint16_t)0x0000) -#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ - ((MODE) == SPI_Mode_Slave)) -/** - * @} - */ - -/** @defgroup SPI_data_size - * @{ - */ - -#define SPI_DataSize_4b ((uint16_t)0x0300) -#define SPI_DataSize_5b ((uint16_t)0x0400) -#define SPI_DataSize_6b ((uint16_t)0x0500) -#define SPI_DataSize_7b ((uint16_t)0x0600) -#define SPI_DataSize_8b ((uint16_t)0x0700) -#define SPI_DataSize_9b ((uint16_t)0x0800) -#define SPI_DataSize_10b ((uint16_t)0x0900) -#define SPI_DataSize_11b ((uint16_t)0x0A00) -#define SPI_DataSize_12b ((uint16_t)0x0B00) -#define SPI_DataSize_13b ((uint16_t)0x0C00) -#define SPI_DataSize_14b ((uint16_t)0x0D00) -#define SPI_DataSize_15b ((uint16_t)0x0E00) -#define SPI_DataSize_16b ((uint16_t)0x0F00) -#define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \ - ((SIZE) == SPI_DataSize_5b) || \ - ((SIZE) == SPI_DataSize_6b) || \ - ((SIZE) == SPI_DataSize_7b) || \ - ((SIZE) == SPI_DataSize_8b) || \ - ((SIZE) == SPI_DataSize_9b) || \ - ((SIZE) == SPI_DataSize_10b) || \ - ((SIZE) == SPI_DataSize_11b) || \ - ((SIZE) == SPI_DataSize_12b) || \ - ((SIZE) == SPI_DataSize_13b) || \ - ((SIZE) == SPI_DataSize_14b) || \ - ((SIZE) == SPI_DataSize_15b) || \ - ((SIZE) == SPI_DataSize_16b)) -/** - * @} - */ - -/** @defgroup SPI_CRC_length - * @{ - */ - -#define SPI_CRCLength_8b ((uint16_t)0x0000) -#define SPI_CRCLength_16b ((uint16_t)0x0800) -#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \ - ((LENGTH) == SPI_CRCLength_16b)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Polarity - * @{ - */ - -#define SPI_CPOL_Low ((uint16_t)0x0000) -#define SPI_CPOL_High ((uint16_t)0x0002) -#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ - ((CPOL) == SPI_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Phase - * @{ - */ - -#define SPI_CPHA_1Edge ((uint16_t)0x0000) -#define SPI_CPHA_2Edge ((uint16_t)0x0001) -#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ - ((CPHA) == SPI_CPHA_2Edge)) -/** - * @} - */ - -/** @defgroup SPI_Slave_Select_management - * @{ - */ - -#define SPI_NSS_Soft ((uint16_t)0x0200) -#define SPI_NSS_Hard ((uint16_t)0x0000) -#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ - ((NSS) == SPI_NSS_Hard)) -/** - * @} - */ - -/** @defgroup SPI_BaudRate_Prescaler - * @{ - */ - -#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) -#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) -#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) -#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) -#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) -#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) -#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) -#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_256)) -/** - * @} - */ - -/** @defgroup SPI_MSB_LSB_transmission - * @{ - */ - -#define SPI_FirstBit_MSB ((uint16_t)0x0000) -#define SPI_FirstBit_LSB ((uint16_t)0x0080) -#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ - ((BIT) == SPI_FirstBit_LSB)) -/** - * @} - */ - -/** @defgroup I2S_Mode - * @{ - */ - -#define I2S_Mode_SlaveTx ((uint16_t)0x0000) -#define I2S_Mode_SlaveRx ((uint16_t)0x0100) -#define I2S_Mode_MasterTx ((uint16_t)0x0200) -#define I2S_Mode_MasterRx ((uint16_t)0x0300) -#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ - ((MODE) == I2S_Mode_SlaveRx) || \ - ((MODE) == I2S_Mode_MasterTx)|| \ - ((MODE) == I2S_Mode_MasterRx)) -/** - * @} - */ - -/** @defgroup I2S_Standard - * @{ - */ - -#define I2S_Standard_Phillips ((uint16_t)0x0000) -#define I2S_Standard_MSB ((uint16_t)0x0010) -#define I2S_Standard_LSB ((uint16_t)0x0020) -#define I2S_Standard_PCMShort ((uint16_t)0x0030) -#define I2S_Standard_PCMLong ((uint16_t)0x00B0) -#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ - ((STANDARD) == I2S_Standard_MSB) || \ - ((STANDARD) == I2S_Standard_LSB) || \ - ((STANDARD) == I2S_Standard_PCMShort) || \ - ((STANDARD) == I2S_Standard_PCMLong)) -/** - * @} - */ - -/** @defgroup I2S_Data_Format - * @{ - */ - -#define I2S_DataFormat_16b ((uint16_t)0x0000) -#define I2S_DataFormat_16bextended ((uint16_t)0x0001) -#define I2S_DataFormat_24b ((uint16_t)0x0003) -#define I2S_DataFormat_32b ((uint16_t)0x0005) -#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ - ((FORMAT) == I2S_DataFormat_16bextended) || \ - ((FORMAT) == I2S_DataFormat_24b) || \ - ((FORMAT) == I2S_DataFormat_32b)) -/** - * @} - */ - -/** @defgroup I2S_MCLK_Output - * @{ - */ - -#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) -#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) -#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ - ((OUTPUT) == I2S_MCLKOutput_Disable)) -/** - * @} - */ - -/** @defgroup I2S_Audio_Frequency - * @{ - */ - -#define I2S_AudioFreq_192k ((uint32_t)192000) -#define I2S_AudioFreq_96k ((uint32_t)96000) -#define I2S_AudioFreq_48k ((uint32_t)48000) -#define I2S_AudioFreq_44k ((uint32_t)44100) -#define I2S_AudioFreq_32k ((uint32_t)32000) -#define I2S_AudioFreq_22k ((uint32_t)22050) -#define I2S_AudioFreq_16k ((uint32_t)16000) -#define I2S_AudioFreq_11k ((uint32_t)11025) -#define I2S_AudioFreq_8k ((uint32_t)8000) -#define I2S_AudioFreq_Default ((uint32_t)2) - -#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ - ((FREQ) <= I2S_AudioFreq_192k)) || \ - ((FREQ) == I2S_AudioFreq_Default)) -/** - * @} - */ - -/** @defgroup I2S_Clock_Polarity - * @{ - */ - -#define I2S_CPOL_Low ((uint16_t)0x0000) -#define I2S_CPOL_High ((uint16_t)0x0008) -#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ - ((CPOL) == I2S_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_FIFO_reception_threshold - * @{ - */ - -#define SPI_RxFIFOThreshold_HF ((uint16_t)0x0000) -#define SPI_RxFIFOThreshold_QF ((uint16_t)0x1000) -#define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \ - ((THRESHOLD) == SPI_RxFIFOThreshold_QF)) -/** - * @} - */ - -/** @defgroup SPI_I2S_DMA_transfer_requests - * @{ - */ - -#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) -#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) -#define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00)) -/** - * @} - */ - -/** @defgroup SPI_last_DMA_transfers - * @{ - */ - -#define SPI_LastDMATransfer_TxEvenRxEven ((uint16_t)0x0000) -#define SPI_LastDMATransfer_TxOddRxEven ((uint16_t)0x4000) -#define SPI_LastDMATransfer_TxEvenRxOdd ((uint16_t)0x2000) -#define SPI_LastDMATransfer_TxOddRxOdd ((uint16_t)0x6000) -#define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \ - ((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \ - ((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \ - ((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd)) -/** - * @} - */ -/** @defgroup SPI_NSS_internal_software_management - * @{ - */ - -#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) -#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) -#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ - ((INTERNAL) == SPI_NSSInternalSoft_Reset)) -/** - * @} - */ - -/** @defgroup SPI_CRC_Transmit_Receive - * @{ - */ - -#define SPI_CRC_Tx ((uint8_t)0x00) -#define SPI_CRC_Rx ((uint8_t)0x01) -#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) -/** - * @} - */ - -/** @defgroup SPI_direction_transmit_receive - * @{ - */ - -#define SPI_Direction_Rx ((uint16_t)0xBFFF) -#define SPI_Direction_Tx ((uint16_t)0x4000) -#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ - ((DIRECTION) == SPI_Direction_Tx)) -/** - * @} - */ - -/** @defgroup SPI_I2S_interrupts_definition - * @{ - */ - -#define SPI_I2S_IT_TXE ((uint8_t)0x71) -#define SPI_I2S_IT_RXNE ((uint8_t)0x60) -#define SPI_I2S_IT_ERR ((uint8_t)0x50) - -#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_I2S_IT_RXNE) || \ - ((IT) == SPI_I2S_IT_ERR)) - -#define I2S_IT_UDR ((uint8_t)0x53) -#define SPI_IT_MODF ((uint8_t)0x55) -#define SPI_I2S_IT_OVR ((uint8_t)0x56) -#define SPI_I2S_IT_FRE ((uint8_t)0x58) - -#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \ - ((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR)) -/** - * @} - */ - - -/** @defgroup SPI_transmission_fifo_status_level - * @{ - */ - -#define SPI_TransmissionFIFOStatus_Empty ((uint16_t)0x0000) -#define SPI_TransmissionFIFOStatus_1QuarterFull ((uint16_t)0x0800) -#define SPI_TransmissionFIFOStatus_HalfFull ((uint16_t)0x1000) -#define SPI_TransmissionFIFOStatus_Full ((uint16_t)0x1800) - -/** - * @} - */ - -/** @defgroup SPI_reception_fifo_status_level - * @{ - */ -#define SPI_ReceptionFIFOStatus_Empty ((uint16_t)0x0000) -#define SPI_ReceptionFIFOStatus_1QuarterFull ((uint16_t)0x0200) -#define SPI_ReceptionFIFOStatus_HalfFull ((uint16_t)0x0400) -#define SPI_ReceptionFIFOStatus_Full ((uint16_t)0x0600) - -/** - * @} - */ - - -/** @defgroup SPI_I2S_flags_definition - * @{ - */ - -#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) -#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) -#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) -#define I2S_FLAG_UDR ((uint16_t)0x0008) -#define SPI_FLAG_CRCERR ((uint16_t)0x0010) -#define SPI_FLAG_MODF ((uint16_t)0x0020) -#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) -#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) -#define SPI_I2S_FLAG_FRE ((uint16_t)0x0100) - - - -#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) -#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ - ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ - ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \ - ((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \ - ((FLAG) == I2S_FLAG_UDR)) -/** - * @} - */ - -/** @defgroup SPI_CRC_polynomial - * @{ - */ - -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the SPI configuration to the default reset state*******/ -void SPI_I2S_DeInit(SPI_TypeDef* SPIx); - -/* Initialization and Configuration functions *********************************/ -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); -void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); -void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold); -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct); - -/* Data transfers functions ***************************************************/ -void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data); -void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data); -uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx); -uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx); - -/* Hardware CRC Calculation functions *****************************************/ -void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength); -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_TransmitCRC(SPI_TypeDef* SPIx); -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); - -/* DMA transfers management functions *****************************************/ -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); -void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer); - -/* Interrupts and flags management functions **********************************/ -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); -uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx); -uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx); -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F30x_SPI_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_syscfg.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,533 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_syscfg.c - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the SYSCFG peripheral: - * + Remapping the memory mapped at 0x00000000 - * + Remapping the DMA channels - * + Enabling I2C fast mode plus driving capability for I2C plus - * + Remapping USB interrupt line - * + Configuring the EXTI lines connection to the GPIO port - * + Configuring the CLASSB requirements - * - @verbatim - - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] The SYSCFG registers can be accessed only when the SYSCFG - interface APB clock is enabled. - [..] To enable SYSCFG APB clock use: - RCC_APBPeriphClockCmd(RCC_APBPeriph_SYSCFG, ENABLE); - - @endverbatim - - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x_syscfg.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @defgroup SYSCFG - * @brief SYSCFG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Reset value od SYSCFG_CFGR1 register */ -#define CFGR1_CLEAR_MASK ((uint32_t)0x7C000000) - -/* ------------ SYSCFG registers bit address in the alias region -------------*/ -#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) - -/* --- CFGR1 Register ---*/ -/* Alias word address of USB_IT_RMP bit */ -#define CFGR1_OFFSET (SYSCFG_OFFSET + 0x00) -#define USBITRMP_BitNumber 0x05 -#define CFGR1_USBITRMP_BB (PERIPH_BB_BASE + (CFGR1_OFFSET * 32) + (USBITRMP_BitNumber * 4)) - -/* --- CFGR2 Register ---*/ -/* Alias word address of BYP_ADDR_PAR bit */ -#define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18) -#define BYPADDRPAR_BitNumber 0x04 -#define CFGR1_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (BYPADDRPAR_BitNumber * 4)) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SYSCFG_Private_Functions - * @{ - */ - -/** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions - * @brief SYSCFG Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### SYSCFG Initialization and Configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the SYSCFG registers to their default reset values. - * @param None - * @retval None - * @note MEM_MODE bits are not affected by APB reset. - * MEM_MODE bits took the value from the user option bytes. - */ -void SYSCFG_DeInit(void) -{ - /* Reset SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */ - SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE; - /* Set FPU Interrupt Enable bits to default value */ - SYSCFG->CFGR1 |= 0x7C000000; - /* Reset RAM Write protection bits to default value */ - SYSCFG->RCR = 0x00000000; - /* Set EXTICRx registers to reset value */ - SYSCFG->EXTICR[0] = 0; - SYSCFG->EXTICR[1] = 0; - SYSCFG->EXTICR[2] = 0; - SYSCFG->EXTICR[3] = 0; - /* Set CFGR2 register to reset value */ - SYSCFG->CFGR2 = 0; - /* Set CFGR3 register to reset value */ - SYSCFG->CFGR3 = 0; -} - -/** - * @brief Configures the memory mapping at address 0x00000000. - * @param SYSCFG_MemoryRemap: selects the memory remapping. - * This parameter can be one of the following values: - * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 - * @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000 - * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000 - * @retval None - */ -void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap) -{ - uint32_t tmpcfgr1 = 0; - - /* Check the parameter */ - assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap)); - - /* Get CFGR1 register value */ - tmpcfgr1 = SYSCFG->CFGR1; - - /* Clear MEM_MODE bits */ - tmpcfgr1 &= (uint32_t) (~SYSCFG_CFGR1_MEM_MODE); - - /* Set the new MEM_MODE bits value */ - tmpcfgr1 |= (uint32_t) SYSCFG_MemoryRemap; - - /* Set CFGR1 register with the new memory remap configuration */ - SYSCFG->CFGR1 = tmpcfgr1; -} - -/** - * @brief Configures the DMA channels remapping. - * @param SYSCFG_DMARemap: selects the DMA channels remap. - * This parameter can be one of the following values: - * @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from DMA1 channel1 to channel2 - * @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from DMA1 channel3 to channel4 - * @arg SYSCFG_DMARemap_TIM6DAC1Ch1: Remap TIM6/DAC1 DMA requests from DMA2 channel 3 to DMA1 channel 3 - * @arg SYSCFG_DMARemap_TIM7DAC1Ch2: Remap TIM7/DAC2 DMA requests from DMA2 channel 4 to DMA1 channel 4 - * @arg SYSCFG_DMARemap_ADC2ADC4: Remap ADC2 and ADC4 DMA requests from DMA2 channel1/channel3 to channel3/channel4 - * @arg SYSCFG_DMARemap_DAC2Ch1: Remap DAC2 DMA requests to DMA1 channel5 - * @arg SYSCFG_DMARemapCh2_SPI1_RX: Remap SPI1 RX DMA1 CH2 requests - * @arg SYSCFG_DMARemapCh4_SPI1_RX: Remap SPI1 RX DMA CH4 requests - * @arg SYSCFG_DMARemapCh6_SPI1_RX: Remap SPI1 RX DMA CH6 requests - * @arg SYSCFG_DMARemapCh3_SPI1_TX: Remap SPI1 TX DMA CH2 requests - * @arg SYSCFG_DMARemapCh5_SPI1_TX: Remap SPI1 TX DMA CH5 requests - * @arg SYSCFG_DMARemapCh7_SPI1_TX: Remap SPI1 TX DMA CH7 requests - * @arg SYSCFG_DMARemapCh7_I2C1_RX: Remap I2C1 RX DMA CH7 requests - * @arg SYSCFG_DMARemapCh3_I2C1_RX: Remap I2C1 RX DMA CH3 requests - * @arg SYSCFG_DMARemapCh5_I2C1_RX: Remap I2C1 RX DMA CH5 requests - * @arg SYSCFG_DMARemapCh6_I2C1_TX: Remap I2C1 TX DMA CH6 requests - * @arg SYSCFG_DMARemapCh2_I2C1_TX: Remap I2C1 TX DMA CH2 requests - * @arg SYSCFG_DMARemapCh4_I2C1_TX: Remap I2C1 TX DMA CH4 requests - * @arg SYSCFG_DMARemapCh4_ADC2: Remap ADC2 DMA1 Ch4 requests - * @arg SYSCFG_DMARemapCh2_ADC2: Remap ADC2 DMA1 Ch2 requests - * @param NewState: new state of the DMA channel remapping. - * This parameter can be: Enable or Disable. - * @note When enabled, DMA channel of the selected peripheral is remapped - * @note When disabled, Default DMA channel is mapped to the selected peripheral - * @note - * By default TIM17 DMA requests is mapped to channel 1 - * use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable) - * to remap TIM17 DMA requests to DMA1 channel 2 - * use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable) - * to map TIM17 DMA requests to DMA1 channel 1 (default mapping) - * @retval None - */ -void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if ((SYSCFG_DMARemap & 0x80000000)!= 0x80000000) - { - if (NewState != DISABLE) - { - /* Remap the DMA channel */ - SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap; - } - else - { - /* use the default DMA channel mapping */ - SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap); - } - } - else - { - if (NewState != DISABLE) - { - /* Remap the DMA channel */ - SYSCFG->CFGR3 |= (uint32_t)SYSCFG_DMARemap; - } - else - { - /* use the default DMA channel mapping */ - SYSCFG->CFGR3 &= (uint32_t)(~SYSCFG_DMARemap); - } - } -} - -/** - * @brief Configures the remapping capabilities of DAC/TIM triggers. - * @param SYSCFG_TriggerRemap: selects the trigger to be remapped. - * This parameter can be one of the following values: - * @arg SYSCFG_TriggerRemap_DACTIM3: Remap DAC trigger from TIM8 to TIM3 - * @arg SYSCFG_TriggerRemap_TIM1TIM17: Remap TIM1 ITR3 from TIM4 TRGO to TIM17 OC - * @arg SYSCFG_TriggerRemap_DACHRTIM1_TRIG1: Remap DAC trigger to HRTIM1 TRIG1 - * @arg SYSCFG_TriggerRemap_DACHRTIM1_TRIG2: Remap DAC trigger to HRTIM1 TRIG2 - * @param NewState: new state of the trigger mapping. - * This parameter can be: ENABLE or DISABLE. - * @note ENABLE: Enable fast mode plus driving capability for selected pin - * @note DISABLE: Disable fast mode plus driving capability for selected pin - * @retval None - */ -void SYSCFG_TriggerRemapConfig(uint32_t SYSCFG_TriggerRemap, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_TRIGGER_REMAP(SYSCFG_TriggerRemap)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if ((SYSCFG_TriggerRemap & 0x80000000)!= 0x80000000) - { - if (NewState != DISABLE) - { - /* Remap the trigger */ - SYSCFG->CFGR1 |= (uint32_t)SYSCFG_TriggerRemap; - } - else - { - /* Use the default trigger mapping */ - SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_TriggerRemap); - } - } - else - { - if (NewState != DISABLE) - { - /* Remap the trigger */ - SYSCFG->CFGR3 |= (uint32_t)SYSCFG_TriggerRemap; - } - else - { - /* Use the default trigger mapping */ - SYSCFG->CFGR3 &= (uint32_t)(~SYSCFG_TriggerRemap); - } - } -} - -/** - * @brief Configures the remapping capabilities of encoder mode. - * @ note This feature implement the so-called M/T method for measuring speed - * and position using quadrature encoders. - * @param SYSCFG_EncoderRemap: selects the remap option for encoder mode. - * This parameter can be one of the following values: - * @arg SYSCFG_EncoderRemap_No: No remap - * @arg SYSCFG_EncoderRemap_TIM2: Timer 2 IC1 and IC2 connected to TIM15 IC1 and IC2 - * @arg SYSCFG_EncoderRemap_TIM3: Timer 3 IC1 and IC2 connected to TIM15 IC1 and IC2 - * @arg SYSCFG_EncoderRemap_TIM4: Timer 4 IC1 and IC2 connected to TIM15 IC1 and IC2 - * @retval None - */ -void SYSCFG_EncoderRemapConfig(uint32_t SYSCFG_EncoderRemap) -{ - /* Check the parameter */ - assert_param(IS_SYSCFG_ENCODER_REMAP(SYSCFG_EncoderRemap)); - - /* Reset the encoder mode remapping bits */ - SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_CFGR1_ENCODER_MODE); - - /* Set the selected configuration */ - SYSCFG->CFGR1 |= (uint32_t)(SYSCFG_EncoderRemap); -} - -/** - * @brief Remaps the USB interrupt lines. - * @param NewState: new state of the mapping of USB interrupt lines. - * This parameter can be: - * @param ENABLE: Remap the USB interrupt line as following: - * @arg USB Device High Priority (USB_HP) interrupt mapped to line 74. - * @arg USB Device Low Priority (USB_LP) interrupt mapped to line 75. - * @arg USB Wakeup Interrupt (USB_WKUP) interrupt mapped to line 76. - * @param DISABLE: Use the default USB interrupt line: - * @arg USB Device High Priority (USB_HP) interrupt mapped to line 19. - * @arg USB Device Low Priority (USB_LP) interrupt mapped to line 20. - * @arg USB Wakeup Interrupt (USB_WKUP) interrupt mapped to line 42. - * @retval None - */ -void SYSCFG_USBInterruptLineRemapCmd(FunctionalState NewState) -{ - /* Check the parameter */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Remap the USB interupt lines */ - *(__IO uint32_t *) CFGR1_USBITRMP_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the I2C fast mode plus driving capability. - * @param SYSCFG_I2CFastModePlus: selects the pin. - * This parameter can be one of the following values: - * @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6 - * @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7 - * @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8 - * @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9 - * @arg SYSCFG_I2CFastModePlus_I2C1: Configure fast mode plus driving capability for I2C1 pins - * @arg SYSCFG_I2CFastModePlus_I2C2: Configure fast mode plus driving capability for I2C2 pins - * @param NewState: new state of the DMA channel remapping. - * This parameter can be: - * @arg ENABLE: Enable fast mode plus driving capability for selected I2C pin - * @arg DISABLE: Disable fast mode plus driving capability for selected I2C pin - * @note For I2C1, fast mode plus driving capability can be enabled on all selected - * I2C1 pins using SYSCFG_I2CFastModePlus_I2C1 parameter or independently - * on each one of the following pins PB6, PB7, PB8 and PB9. - * @note For remaing I2C1 pins (PA14, PA15...) fast mode plus driving capability - * can be enabled only by using SYSCFG_I2CFastModePlus_I2C1 parameter. - * @note For all I2C2 pins fast mode plus driving capability can be enabled - * only by using SYSCFG_I2CFastModePlus_I2C2 parameter. - * @retval None - */ -void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable fast mode plus driving capability for selected I2C pin */ - SYSCFG->CFGR1 |= (uint32_t)SYSCFG_I2CFastModePlus; - } - else - { - /* Disable fast mode plus driving capability for selected I2C pin */ - SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_I2CFastModePlus); - } -} - -/** - * @brief Enables or disables the selected SYSCFG interrupts. - * @param SYSCFG_IT: specifies the SYSCFG interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg SYSCFG_IT_IXC: Inexact Interrupt - * @arg SYSCFG_IT_IDC: Input denormal Interrupt - * @arg SYSCFG_IT_OFC: Overflow Interrupt - * @arg SYSCFG_IT_UFC: Underflow Interrupt - * @arg SYSCFG_IT_DZC: Divide-by-zero Interrupt - * @arg SYSCFG_IT_IOC: Invalid operation Interrupt - * @param NewState: new state of the specified SYSCFG interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SYSCFG_ITConfig(uint32_t SYSCFG_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SYSCFG_IT(SYSCFG_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected SYSCFG interrupts */ - SYSCFG->CFGR1 |= SYSCFG_IT; - } - else - { - /* Disable the selected SYSCFG interrupts */ - SYSCFG->CFGR1 &= ((uint32_t)~SYSCFG_IT); - } -} - -/** - * @brief Selects the GPIO pin used as EXTI Line. - * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source - * for EXTI lines where x can be (A, B, C, D, E or F). - * @param EXTI_PinSourcex: specifies the EXTI line to be configured. - * This parameter can be EXTI_PinSourcex where x can be (0..15) - * @retval None - */ -void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex) -{ - uint32_t tmp = 0x00; - - /* Check the parameters */ - assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx)); - assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex)); - - tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)); - SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp; - SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03))); -} - -/** - * @brief Connects the selected parameter to the break input of TIM1. - * @note The selected configuration is locked and can be unlocked by system reset - * @param SYSCFG_Break: selects the configuration to be connected to break - * input of TIM1 - * This parameter can be any combination of the following values: - * @arg SYSCFG_Break_PVD: PVD interrupt is connected to the break input of TIM1. - * @arg SYSCFG_Break_SRAMParity: SRAM Parity error is connected to the break input of TIM1. - * @arg SYSCFG_Break_HardFault: Lockup output of CortexM4 is connected to the break input of TIM1. - * @retval None - */ -void SYSCFG_BreakConfig(uint32_t SYSCFG_Break) -{ - /* Check the parameter */ - assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break)); - - SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break; -} - -/** - * @brief Disables the parity check on RAM. - * @note Disabling the parity check on RAM locks the configuration bit. - * To re-enable the parity check on RAM perform a system reset. - * @param None - * @retval None - */ -void SYSCFG_BypassParityCheckDisable(void) -{ - /* Disable the adddress parity check on RAM */ - *(__IO uint32_t *) CFGR1_BYPADDRPAR_BB = (uint32_t)0x00000001; -} - -/** - * @brief Enables the ICODE SRAM write protection. - * @note Enabling the ICODE SRAM write protection locks the configuration bit. - * To disable the ICODE SRAM write protection perform a system reset. - * @param None - * @retval None - */ -void SYSCFG_SRAMWRPEnable(uint32_t SYSCFG_SRAMWRP) -{ - /* Check the parameter */ - assert_param(IS_SYSCFG_PAGE(SYSCFG_SRAMWRP)); - - /* Enable the write-protection on the selected ICODE SRAM page */ - SYSCFG->RCR |= (uint32_t)SYSCFG_SRAMWRP; -} - -/** - * @brief Checks whether the specified SYSCFG flag is set or not. - * @param SYSCFG_Flag: specifies the SYSCFG flag to check. - * This parameter can be one of the following values: - * @arg SYSCFG_FLAG_PE: SRAM parity error flag. - * @retval The new state of SYSCFG_Flag (SET or RESET). - */ -FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameter */ - assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag)); - - /* Check the status of the specified SPI flag */ - if ((SYSCFG->CFGR2 & SYSCFG_CFGR2_SRAM_PE) != (uint32_t)RESET) - { - /* SYSCFG_Flag is set */ - bitstatus = SET; - } - else - { - /* SYSCFG_Flag is reset */ - bitstatus = RESET; - } - /* Return the SYSCFG_Flag status */ - return bitstatus; -} - -/** - * @brief Clears the selected SYSCFG flag. - * @param SYSCFG_Flag: selects the flag to be cleared. - * This parameter can be any combination of the following values: - * @arg SYSCFG_FLAG_PE: SRAM parity error flag. - * @retval None - */ -void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag) -{ - /* Check the parameter */ - assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag)); - - SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Flag; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_syscfg.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,355 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_syscfg.h - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file contains all the functions prototypes for the SYSCFG firmware - * library. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*!< Define to prevent recursive inclusion -----------------------------------*/ -#ifndef __STM32F30x_SYSCFG_H -#define __STM32F30x_SYSCFG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/*!< Includes ----------------------------------------------------------------*/ -#include "stm32f30x.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SYSCFG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SYSCFG_Exported_Constants - * @{ - */ - -/** @defgroup SYSCFG_EXTI_Port_Sources - * @{ - */ -#define EXTI_PortSourceGPIOA ((uint8_t)0x00) -#define EXTI_PortSourceGPIOB ((uint8_t)0x01) -#define EXTI_PortSourceGPIOC ((uint8_t)0x02) -#define EXTI_PortSourceGPIOD ((uint8_t)0x03) -#define EXTI_PortSourceGPIOE ((uint8_t)0x04) -#define EXTI_PortSourceGPIOF ((uint8_t)0x05) - -#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOF)) -/** - * @} - */ - -/** @defgroup SYSCFG_EXTI_Pin_sources - * @{ - */ -#define EXTI_PinSource0 ((uint8_t)0x00) -#define EXTI_PinSource1 ((uint8_t)0x01) -#define EXTI_PinSource2 ((uint8_t)0x02) -#define EXTI_PinSource3 ((uint8_t)0x03) -#define EXTI_PinSource4 ((uint8_t)0x04) -#define EXTI_PinSource5 ((uint8_t)0x05) -#define EXTI_PinSource6 ((uint8_t)0x06) -#define EXTI_PinSource7 ((uint8_t)0x07) -#define EXTI_PinSource8 ((uint8_t)0x08) -#define EXTI_PinSource9 ((uint8_t)0x09) -#define EXTI_PinSource10 ((uint8_t)0x0A) -#define EXTI_PinSource11 ((uint8_t)0x0B) -#define EXTI_PinSource12 ((uint8_t)0x0C) -#define EXTI_PinSource13 ((uint8_t)0x0D) -#define EXTI_PinSource14 ((uint8_t)0x0E) -#define EXTI_PinSource15 ((uint8_t)0x0F) - -#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \ - ((PINSOURCE) == EXTI_PinSource1) || \ - ((PINSOURCE) == EXTI_PinSource2) || \ - ((PINSOURCE) == EXTI_PinSource3) || \ - ((PINSOURCE) == EXTI_PinSource4) || \ - ((PINSOURCE) == EXTI_PinSource5) || \ - ((PINSOURCE) == EXTI_PinSource6) || \ - ((PINSOURCE) == EXTI_PinSource7) || \ - ((PINSOURCE) == EXTI_PinSource8) || \ - ((PINSOURCE) == EXTI_PinSource9) || \ - ((PINSOURCE) == EXTI_PinSource10) || \ - ((PINSOURCE) == EXTI_PinSource11) || \ - ((PINSOURCE) == EXTI_PinSource12) || \ - ((PINSOURCE) == EXTI_PinSource13) || \ - ((PINSOURCE) == EXTI_PinSource14) || \ - ((PINSOURCE) == EXTI_PinSource15)) -/** - * @} - */ - -/** @defgroup SYSCFG_Memory_Remap_Config - * @{ - */ -#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00) -#define SYSCFG_MemoryRemap_SystemMemory ((uint8_t)0x01) -#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03) - - -#define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \ - ((REMAP) == SYSCFG_MemoryRemap_SRAM)) - -/** - * @} - */ - -/** @defgroup SYSCFG_DMA_Remap_Config - * @{ - */ -#define SYSCFG_DMARemap_TIM17 SYSCFG_CFGR1_TIM17_DMA_RMP /*!< Remap TIM17 DMA requests from channel1 to channel2 */ -#define SYSCFG_DMARemap_TIM16 SYSCFG_CFGR1_TIM16_DMA_RMP /*!< Remap TIM16 DMA requests from channel3 to channel4 */ -#define SYSCFG_DMARemap_ADC2ADC4 SYSCFG_CFGR1_ADC24_DMA_RMP /*!< Remap ADC2 and ADC4 DMA requests */ - -#define SYSCFG_DMARemap_TIM6DAC1Ch1 SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP /* Remap TIM6/DAC1 Ch1 DMA requests */ -#define SYSCFG_DMARemap_TIM7DAC1Ch2 SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP /* Remap TIM7/DAC1 Ch2 DMA requests */ -#define SYSCFG_DMARemap_DAC2Ch1 SYSCFG_CFGR1_DAC2Ch1_DMA_RMP /* Remap DAC2 Ch1 DMA requests */ - -#define SYSCFG_DMARemapCh2_SPI1_RX ((uint32_t)0x80000003) /* Remap SPI1 RX DMA CH2 requests */ -#define SYSCFG_DMARemapCh4_SPI1_RX ((uint32_t)0x80000001) /* Remap SPI1 RX DMA CH4 requests */ -#define SYSCFG_DMARemapCh6_SPI1_RX ((uint32_t)0x80000002) /* Remap SPI1 RX DMA CH6 requests */ - -#define SYSCFG_DMARemapCh3_SPI1_TX ((uint32_t)0x8000000C) /* Remap SPI1 TX DMA CH2 requests */ -#define SYSCFG_DMARemapCh5_SPI1_TX ((uint32_t)0x80000004) /* Remap SPI1 TX DMA CH5 requests */ -#define SYSCFG_DMARemapCh7_SPI1_TX ((uint32_t)0x80000008) /* Remap SPI1 TX DMA CH7 requests */ - -#define SYSCFG_DMARemapCh7_I2C1_RX ((uint32_t)0x80000030) /* Remap I2C1 RX DMA CH7 requests */ -#define SYSCFG_DMARemapCh3_I2C1_RX ((uint32_t)0x80000010) /* Remap I2C1 RX DMA CH3 requests */ -#define SYSCFG_DMARemapCh5_I2C1_RX ((uint32_t)0x80000020) /* Remap I2C1 RX DMA CH5 requests */ - -#define SYSCFG_DMARemapCh6_I2C1_TX ((uint32_t)0x800000C0) /* Remap I2C1 TX DMA CH6 requests */ -#define SYSCFG_DMARemapCh2_I2C1_TX ((uint32_t)0x80000040) /* Remap I2C1 TX DMA CH2 requests */ -#define SYSCFG_DMARemapCh4_I2C1_TX ((uint32_t)0x80000080) /* Remap I2C1 TX DMA CH4 requests */ - -#define SYSCFG_DMARemapCh4_ADC2 ((uint32_t)0x80000300) /* Remap ADC2 DMA1 Ch4 requests */ -#define SYSCFG_DMARemapCh2_ADC2 ((uint32_t)0x80000200) /* Remap ADC2 DMA1 Ch2 requests */ - -/* SYSCFG_DMA_Remap_Legacy */ -#define SYSCFG_DMARemap_TIM6DAC1 SYSCFG_DMARemap_TIM6DAC1Ch1 /*!< Remap TIM6/DAC1 DMA requests */ -#define SYSCFG_DMARemap_TIM7DAC2 SYSCFG_DMARemap_TIM7DAC1Ch2 /*!< Remap TIM7/DAC2 DMA requests */ - -#define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMARemap_TIM17) || \ - ((REMAP) == SYSCFG_DMARemap_TIM16) || \ - ((REMAP) == SYSCFG_DMARemap_ADC2ADC4) || \ - ((REMAP) == SYSCFG_DMARemap_TIM6DAC1Ch1) || \ - ((REMAP) == SYSCFG_DMARemap_TIM7DAC1Ch2) || \ - ((REMAP) == SYSCFG_DMARemap_DAC2Ch1) || \ - ((REMAP) == SYSCFG_DMARemapCh2_SPI1_RX) || \ - ((REMAP) == SYSCFG_DMARemapCh4_SPI1_RX) || \ - ((REMAP) == SYSCFG_DMARemapCh6_SPI1_RX) || \ - ((REMAP) == SYSCFG_DMARemapCh5_SPI1_TX) || \ - ((REMAP) == SYSCFG_DMARemapCh5_SPI1_TX) || \ - ((REMAP) == SYSCFG_DMARemapCh7_SPI1_TX) || \ - ((REMAP) == SYSCFG_DMARemapCh7_I2C1_RX) || \ - ((REMAP) == SYSCFG_DMARemapCh3_I2C1_RX) || \ - ((REMAP) == SYSCFG_DMARemapCh5_I2C1_RX) || \ - ((REMAP) == SYSCFG_DMARemapCh6_I2C1_TX) || \ - ((REMAP) == SYSCFG_DMARemapCh2_I2C1_TX) || \ - ((REMAP) == SYSCFG_DMARemapCh4_I2C1_TX) || \ - ((REMAP) == SYSCFG_DMARemapCh4_ADC2) || \ - ((REMAP) == SYSCFG_DMARemapCh2_ADC2)) - -/** - * @} - */ - -/** @defgroup SYSCFG_Trigger_Remap_Config - * @{ - */ -#define SYSCFG_TriggerRemap_DACTIM3 SYSCFG_CFGR1_DAC1_TRIG1_RMP /*!< Remap DAC trigger to TIM3 */ -#define SYSCFG_TriggerRemap_TIM1TIM17 SYSCFG_CFGR1_TIM1_ITR3_RMP /*!< Remap TIM1 ITR3 to TIM17 OC */ -#define SYSCFG_TriggerRemap_DACHRTIM1_TRIG1 ((uint32_t)0x80010000) /*!< Remap DAC trigger to HRTIM1 TRIG1 */ -#define SYSCFG_TriggerRemap_DACHRTIM1_TRIG2 ((uint32_t)0x80020000) /*!< Remap DAC trigger to HRTIM1 TRIG2 */ - -#define IS_SYSCFG_TRIGGER_REMAP(REMAP) (((REMAP) == SYSCFG_TriggerRemap_DACTIM3) || \ - ((REMAP) == SYSCFG_TriggerRemap_DACHRTIM1_TRIG1) || \ - ((REMAP) == SYSCFG_TriggerRemap_DACHRTIM1_TRIG2) || \ - ((REMAP) == SYSCFG_TriggerRemap_TIM1TIM17)) - -/** - * @} - */ - -/** @defgroup SYSCFG_EncoderRemap_Config - * @{ - */ -#define SYSCFG_EncoderRemap_No ((uint32_t)0x00000000) /*!< No redirection */ -#define SYSCFG_EncoderRemap_TIM2 SYSCFG_CFGR1_ENCODER_MODE_0 /*!< Timer 2 IC1 and IC2 connected to TIM15 IC1 and IC2 */ -#define SYSCFG_EncoderRemap_TIM3 SYSCFG_CFGR1_ENCODER_MODE_1 /*!< Timer 3 IC1 and IC2 connected to TIM15 IC1 and IC2 */ -#define SYSCFG_EncoderRemap_TIM4 SYSCFG_CFGR1_ENCODER_MODE /*!< Timer 4 IC1 and IC2 connected to TIM15 IC1 and IC2 */ - -#define IS_SYSCFG_ENCODER_REMAP(REMAP) (((REMAP) == SYSCFG_EncoderRemap_No) || \ - ((REMAP) == SYSCFG_EncoderRemap_TIM2) || \ - ((REMAP) == SYSCFG_EncoderRemap_TIM3) || \ - ((REMAP) == SYSCFG_EncoderRemap_TIM4)) - -/** - * @} - */ - -/** @defgroup SYSCFG_I2C_FastModePlus_Config - * @{ - */ -#define SYSCFG_I2CFastModePlus_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ -#define SYSCFG_I2CFastModePlus_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ -#define SYSCFG_I2CFastModePlus_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ -#define SYSCFG_I2CFastModePlus_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ -#define SYSCFG_I2CFastModePlus_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ -#define SYSCFG_I2CFastModePlus_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ - -#define IS_SYSCFG_I2C_FMP(PIN) (((PIN) == SYSCFG_I2CFastModePlus_PB6) || \ - ((PIN) == SYSCFG_I2CFastModePlus_PB7) || \ - ((PIN) == SYSCFG_I2CFastModePlus_PB8) || \ - ((PIN) == SYSCFG_I2CFastModePlus_PB9) || \ - ((PIN) == SYSCFG_I2CFastModePlus_I2C1) || \ - ((PIN) == SYSCFG_I2CFastModePlus_I2C2)) - -/** - * @} - */ - -/** @defgroup SYSCFG_FPU_Interrupt_Config - * @{ - */ -#define SYSCFG_IT_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Inexact Interrupt enable (interrupt disabled by default) */ -#define SYSCFG_IT_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Input denormal Interrupt enable */ -#define SYSCFG_IT_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Overflow Interrupt enable */ -#define SYSCFG_IT_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Underflow Interrupt enable */ -#define SYSCFG_IT_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Divide-by-zero Interrupt enable */ -#define SYSCFG_IT_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Invalid operation Interrupt enable */ - -#define IS_SYSCFG_IT(IT) ((((IT) & (uint32_t)0x03FFFFFF) == 0) && ((IT) != 0)) - -/** - * @} - */ - -/** @defgroup SYSCFG_Lock_Config - * @{ - */ -#define SYSCFG_Break_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */ -#define SYSCFG_Break_SRAMParity SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */ -#define SYSCFG_Break_Lockup SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */ - -#define IS_SYSCFG_LOCK_CONFIG(CONFIG) (((CONFIG) == SYSCFG_Break_PVD) || \ - ((CONFIG) == SYSCFG_Break_SRAMParity) || \ - ((CONFIG) == SYSCFG_Break_Lockup)) - -/** - * @} - */ - -/** @defgroup SYSCFG_SRAMWRP_Config - * @{ - */ -#define SYSCFG_SRAMWRP_Page0 SYSCFG_RCR_PAGE0 /*!< ICODE SRAM Write protection page 0 */ -#define SYSCFG_SRAMWRP_Page1 SYSCFG_RCR_PAGE1 /*!< ICODE SRAM Write protection page 1 */ -#define SYSCFG_SRAMWRP_Page2 SYSCFG_RCR_PAGE2 /*!< ICODE SRAM Write protection page 2 */ -#define SYSCFG_SRAMWRP_Page3 SYSCFG_RCR_PAGE3 /*!< ICODE SRAM Write protection page 3 */ -#define SYSCFG_SRAMWRP_Page4 SYSCFG_RCR_PAGE4 /*!< ICODE SRAM Write protection page 4 */ -#define SYSCFG_SRAMWRP_Page5 SYSCFG_RCR_PAGE5 /*!< ICODE SRAM Write protection page 5 */ -#define SYSCFG_SRAMWRP_Page6 SYSCFG_RCR_PAGE6 /*!< ICODE SRAM Write protection page 6 */ -#define SYSCFG_SRAMWRP_Page7 SYSCFG_RCR_PAGE7 /*!< ICODE SRAM Write protection page 7 */ - -#define IS_SYSCFG_PAGE(PAGE)((((PAGE) & (uint32_t)0xFFFFFF00) == 0x00000000) && ((PAGE) != 0x00000000)) - -/** - * @} - */ - -/** @defgroup SYSCFG_flags_definition - * @{ - */ - -#define SYSCFG_FLAG_PE SYSCFG_CFGR2_SRAM_PE - -#define IS_SYSCFG_FLAG(FLAG) (((FLAG) == SYSCFG_FLAG_PE)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the SYSCFG configuration to the default reset state **/ -void SYSCFG_DeInit(void); - -/* SYSCFG configuration functions *********************************************/ -void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap); -void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState); -void SYSCFG_TriggerRemapConfig(uint32_t SYSCFG_TriggerRemap, FunctionalState NewState); -void SYSCFG_EncoderRemapConfig(uint32_t SYSCFG_EncoderRemap); -void SYSCFG_USBInterruptLineRemapCmd(FunctionalState NewState); -void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState); -void SYSCFG_ITConfig(uint32_t SYSCFG_IT, FunctionalState NewState); -void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex); -void SYSCFG_BreakConfig(uint32_t SYSCFG_Break); -void SYSCFG_BypassParityCheckDisable(void); -void SYSCFG_SRAMWRPEnable(uint32_t SYSCFG_SRAMWRP); -FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag); -void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F30x_SYSCFG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_tim.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,4005 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_tim.c - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the TIM peripheral: - * + TimeBase management - * + Output Compare management - * + Input Capture management - * + Advanced-control timers (TIM1 and TIM8) specific features - * + Interrupts, DMA and flags management - * + Clocks management - * + Synchronization management - * + Specific interface management - * + Specific remapping management - * - @verbatim - - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] This driver provides functions to configure and program the TIM - of all stm32f30x devices. - These functions are split in 9 groups: - - (#) TIM TimeBase management: this group includes all needed functions - to configure the TM Timebase unit: - (++) Set/Get Prescaler - (++) Set/Get Autoreload - (++) Counter modes configuration - (++) Set Clock division - (++) Select the One Pulse mode - (++) Update Request Configuration - (++) Update Disable Configuration - (++) Auto-Preload Configuration - (++) Enable/Disable the counter - - (#) TIM Output Compare management: this group includes all needed - functions to configure the Capture/Compare unit used in Output - compare mode: - (++) Configure each channel, independently, in Output Compare mode - (++) Select the output compare modes - (++) Select the Polarities of each channel - (++) Set/Get the Capture/Compare register values - (++) Select the Output Compare Fast mode - (++) Select the Output Compare Forced mode - (++) Output Compare-Preload Configuration - (++) Clear Output Compare Reference - (++) Select the OCREF Clear signal - (++) Enable/Disable the Capture/Compare Channels - - (#) TIM Input Capture management: this group includes all needed - functions to configure the Capture/Compare unit used in - Input Capture mode: - (++) Configure each channel in input capture mode - (++) Configure Channel1/2 in PWM Input mode - (++) Set the Input Capture Prescaler - (++) Get the Capture/Compare values - - (#) Advanced-control timers (TIM1 and TIM8) specific features - (++) Configures the Break input, dead time, Lock level, the OSSI, - the OSSR State and the AOE(automatic output enable) - (++) Enable/Disable the TIM peripheral Main Outputs - (++) Select the Commutation event - (++) Set/Reset the Capture Compare Preload Control bit - - (#) TIM interrupts, DMA and flags management - (++) Enable/Disable interrupt sources - (++) Get flags status - (++) Clear flags/ Pending bits - (++) Enable/Disable DMA requests - (++) Configure DMA burst mode - (++) Select CaptureCompare DMA request - - (#) TIM clocks management: this group includes all needed functions - to configure the clock controller unit: - (++) Select internal/External clock - (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx - - (#) TIM synchronization management: this group includes all needed - functions to configure the Synchronization unit: - (++) Select Input Trigger - (++) Select Output Trigger - (++) Select Master Slave Mode - (++) ETR Configuration when used as external trigger - - (#) TIM specific interface management, this group includes all - needed functions to use the specific TIM interface: - (++) Encoder Interface Configuration - (++) Select Hall Sensor - - (#) TIM specific remapping management includes the Remapping - configuration of specific timers - - @endverbatim - - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x_tim.h" -#include "stm32f30x_rcc.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @defgroup TIM - * @brief TIM driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ---------------------- TIM registers bit mask ------------------------ */ -#define SMCR_ETR_MASK ((uint16_t)0x00FF) -#define CCMR_OFFSET ((uint16_t)0x0018) -#define CCER_CCE_SET ((uint16_t)0x0001) -#define CCER_CCNE_SET ((uint16_t)0x0004) -#define CCMR_OC13M_MASK ((uint32_t)0xFFFEFF8F) -#define CCMR_OC24M_MASK ((uint32_t)0xFEFF8FFF) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup TIM_Private_Functions - * @{ - */ - -/** @defgroup TIM_Group1 TimeBase management functions - * @brief TimeBase management functions - * -@verbatim - =============================================================================== - ##### TimeBase management functions ##### - =============================================================================== - - - *** TIM Driver: how to use it in Timing(Time base) Mode *** - ============================================================ - [..] - To use the Timer in Timing(Time base) mode, the following steps are mandatory: - - (#) Enable TIM clock using - RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function - (#) Fill the TIM_TimeBaseInitStruct with the desired parameters. - (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure - the Time Base unit - with the corresponding configuration - (#) Enable the NVIC if you need to generate the update interrupt. - (#) Enable the corresponding interrupt using the function - TIM_ITConfig(TIMx, TIM_IT_Update) - (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - [..] - (@) All other functions can be used separately to modify, if needed, - a specific feature of the Timer. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the TIMx peripheral registers to their default reset values. - * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. - * @retval None - - */ -void TIM_DeInit(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - if (TIMx == TIM1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); - } - else if (TIMx == TIM2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); - } - else if (TIMx == TIM3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); - } - else if (TIMx == TIM4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); - } - else if (TIMx == TIM6) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); - } - else if (TIMx == TIM7) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); - } - else if (TIMx == TIM8) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); - } - else if (TIMx == TIM15) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE); - } - else if (TIMx == TIM16) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE); - } - else - { - if (TIMx == TIM17) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE); - } - } -} - -/** - * @brief Initializes the TIMx Time Base Unit peripheral according to - * the specified parameters in the TIM_TimeBaseInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - uint16_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); - assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); - - tmpcr1 = TIMx->CR1; - - if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || - (TIMx == TIM3)|| (TIMx == TIM4)) - { - /* Select the Counter Mode */ - tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS)); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; - } - - if((TIMx != TIM6) && (TIMx != TIM7)) - { - /* Set the clock division */ - tmpcr1 &= (uint16_t)(~TIM_CR1_CKD); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; - } - - TIMx->CR1 = tmpcr1; - - /* Set the Autoreload value */ - TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; - - /* Set the Prescaler value */ - TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; - - if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15) || - (TIMx == TIM16) || (TIMx == TIM17)) - { - /* Set the Repetition Counter value */ - TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; - } - - /* Generate an update event to reload the Prescaler - and the repetition counter(only for TIM1 and TIM8) value immediatly */ - TIMx->EGR = TIM_PSCReloadMode_Immediate; -} - -/** - * @brief Fills each TIM_TimeBaseInitStruct member with its default value. - * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef - * structure which will be initialized. - * @retval None - */ -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - /* Set the default configuration */ - TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF; - TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; - TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; - TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; -} - -/** - * @brief Configures the TIMx Prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. - * @param Prescaler: specifies the Prescaler Register value - * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode - * This parameter can be one of the following values: - * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. - * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly. - * @retval None - */ -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); - /* Set the Prescaler value */ - TIMx->PSC = Prescaler; - /* Set or reset the UG Bit */ - TIMx->EGR = TIM_PSCReloadMode; -} - -/** - * @brief Specifies the TIMx Counter Mode to be used. - * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. - * @param TIM_CounterMode: specifies the Counter Mode to be used - * This parameter can be one of the following values: - * @arg TIM_CounterMode_Up: TIM Up Counting Mode - * @arg TIM_CounterMode_Down: TIM Down Counting Mode - * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 - * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 - * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 - * @retval None - */ -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) -{ - uint16_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); - - tmpcr1 = TIMx->CR1; - - /* Reset the CMS and DIR Bits */ - tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS); - - /* Set the Counter Mode */ - tmpcr1 |= TIM_CounterMode; - - /* Write to TIMx CR1 register */ - TIMx->CR1 = tmpcr1; -} - -/** - * @brief Sets the TIMx Counter Register value - * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. - * @param Counter: specifies the Counter register new value. - * @retval None - */ -void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Set the Counter Register value */ - TIMx->CNT = Counter; -} - -/** - * @brief Sets the TIMx Autoreload Register value - * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. - * @param Autoreload: specifies the Autoreload register new value. - * @retval None - */ -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Set the Autoreload Register value */ - TIMx->ARR = Autoreload; -} - -/** - * @brief Gets the TIMx Counter value. - * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. - * @retval Counter Register value - */ -uint32_t TIM_GetCounter(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Get the Counter Register value */ - return TIMx->CNT; -} - -/** - * @brief Gets the TIMx Prescaler value. - * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. - * @retval Prescaler Register value. - */ -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Get the Prescaler Register value */ - return TIMx->PSC; -} - -/** - * @brief Enables or Disables the TIMx Update event. - * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. - * @param NewState: new state of the TIMx UDIS bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the Update Disable Bit */ - TIMx->CR1 |= TIM_CR1_UDIS; - } - else - { - /* Reset the Update Disable Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS; - } -} - -/** - * @brief Configures the TIMx Update Request Interrupt source. - * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_UpdateSource: specifies the Update source. - * This parameter can be one of the following values: - * @arg TIM_UpdateSource_Regular: Source of update is the counter - * overflow/underflow or the setting of UG bit, or an update - * generation through the slave mode controller. - * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow. - * @retval None - */ -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); - - if (TIM_UpdateSource != TIM_UpdateSource_Global) - { - /* Set the URS Bit */ - TIMx->CR1 |= TIM_CR1_URS; - } - else - { - /* Reset the URS Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_URS; - } -} - -/** - * @brief Sets or resets the update interrupt flag (UIF)status bit Remapping. - * when sets, reading TIMx_CNT register returns UIF bit instead of CNT[31] - * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. - * @param NewState: new state of the UIFREMAP bit. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_UIFRemap(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TIM Counter */ - TIMx->CR1 |= TIM_CR1_UIFREMAP; - } - else - { - /* Disable the TIM Counter */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_UIFREMAP; - } -} - -/** - * @brief Enables or disables TIMx peripheral Preload register on ARR. - * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. - * @param NewState: new state of the TIMx peripheral Preload register - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the ARR Preload Bit */ - TIMx->CR1 |= TIM_CR1_ARPE; - } - else - { - /* Reset the ARR Preload Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE; - } -} - -/** - * @brief Selects the TIMx's One Pulse Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_OPMode: specifies the OPM Mode to be used. - * This parameter can be one of the following values: - * @arg TIM_OPMode_Single - * @arg TIM_OPMode_Repetitive - * @retval None - */ -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); - - /* Reset the OPM Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM; - - /* Configure the OPM Mode */ - TIMx->CR1 |= TIM_OPMode; -} - -/** - * @brief Sets the TIMx Clock Division value. - * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17, to select the TIM peripheral. - * @param TIM_CKD: specifies the clock division value. - * This parameter can be one of the following value: - * @arg TIM_CKD_DIV1: TDTS = Tck_tim - * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim - * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim - * @retval None - */ -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_CKD_DIV(TIM_CKD)); - - /* Reset the CKD Bits */ - TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD); - - /* Set the CKD value */ - TIMx->CR1 |= TIM_CKD; -} - -/** - * @brief Enables or disables the specified TIM peripheral. - * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select - * the TIMx peripheral. - * @param NewState: new state of the TIMx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TIM Counter */ - TIMx->CR1 |= TIM_CR1_CEN; - } - else - { - /* Disable the TIM Counter */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group2 Output Compare management functions - * @brief Output Compare management functions - * -@verbatim - =============================================================================== - ##### Output Compare management functions ##### - =============================================================================== - - *** TIM Driver: how to use it in Output Compare Mode *** - ======================================================== - [..] - To use the Timer in Output Compare mode, the following steps are mandatory: - - (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function - - (#) Configure the TIM pins by configuring the corresponding GPIO pins - - (#) Configure the Time base unit as described in the first part of this driver, - if needed, else the Timer will run with the default configuration: - (++) Autoreload value = 0xFFFF - (++) Prescaler value = 0x0000 - (++) Counter mode = Up counting - (++) Clock Division = TIM_CKD_DIV1 - (#) Fill the TIM_OCInitStruct with the desired parameters including: - (++) The TIM Output Compare mode: TIM_OCMode - (++) TIM Output State: TIM_OutputState - (++) TIM Pulse value: TIM_Pulse - (++) TIM Output Compare Polarity : TIM_OCPolarity - - (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the - corresponding configuration - - (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - [..] - (@) All other functions can be used separately to modify, if needed, - a specific feature of the Timer. - - (@) In case of PWM mode, this function is mandatory: - TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); - - (@) If the corresponding interrupt or DMA request are needed, the user should: - (#@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). - (#@) Enable the corresponding interrupt (or DMA request) using the function - TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIMx Channel1 according to the specified parameters in - * the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17, to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= (uint32_t)~TIM_CCMR1_OC1M; - tmpccmrx &= (uint32_t)~TIM_CCMR1_CC1S; - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint32_t)~TIM_CCER_CC1P; - /* Set the Output Compare Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; - - /* Set the Output State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputState; - - if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM15) || (TIMx == TIM16) || (TIMx == TIM17)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint32_t)~TIM_CCER_CC1NP; - /* Set the Output N Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; - /* Reset the Output N State */ - tmpccer &= (uint32_t)~TIM_CCER_CC1NE; - - /* Set the Output N State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputNState; - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint32_t)~TIM_CR2_OIS1; - tmpcr2 &= (uint32_t)~TIM_CR2_OIS1N; - /* Set the Output Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; - /* Set the Output N Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel2 according to the specified parameters - * in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint32_t)~TIM_CCMR1_OC2M; - tmpccmrx &= (uint32_t)~TIM_CCMR1_CC2S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint32_t)~TIM_CCER_CC2P; - /* Set the Output Compare Polarity */ - tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 4); - - /* Set the Output State */ - tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 4); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint32_t)~TIM_CCER_CC2NP; - /* Set the Output N Polarity */ - tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNPolarity << 4); - /* Reset the Output N State */ - tmpccer &= (uint32_t)~TIM_CCER_CC2NE; - - /* Set the Output N State */ - tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputNState << 4); - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint32_t)~TIM_CR2_OIS2; - tmpcr2 &= (uint32_t)~TIM_CR2_OIS2N; - /* Set the Output Idle state */ - tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 2); - /* Set the Output N Idle state */ - tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNIdleState << 2); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel3 according to the specified parameters - * in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 3: Reset the CC2E Bit */ - TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint32_t)~TIM_CCMR2_OC3M; - tmpccmrx &= (uint32_t)~TIM_CCMR2_CC3S; - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint32_t)~TIM_CCER_CC3P; - /* Set the Output Compare Polarity */ - tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 8); - - /* Set the Output State */ - tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 8); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint32_t)~TIM_CCER_CC3NP; - /* Set the Output N Polarity */ - tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNPolarity << 8); - /* Reset the Output N State */ - tmpccer &= (uint32_t)~TIM_CCER_CC3NE; - - /* Set the Output N State */ - tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputNState << 8); - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint32_t)~TIM_CR2_OIS3; - tmpcr2 &= (uint32_t)~TIM_CR2_OIS3N; - /* Set the Output Idle state */ - tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 4); - /* Set the Output N Idle state */ - tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNIdleState << 4); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel4 according to the specified parameters - * in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint32_t)~TIM_CCMR2_OC4M; - tmpccmrx &= (uint32_t)~TIM_CCMR2_CC4S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint32_t)~TIM_CCER_CC4P; - /* Set the Output Compare Polarity */ - tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 12); - - /* Set the Output State */ - tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 12); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - /* Reset the Output Compare IDLE State */ - tmpcr2 &=(uint32_t) ~TIM_CR2_OIS4; - /* Set the Output Idle state */ - tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 6); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel5 according to the specified parameters - * in the TIM_OCInitStruct. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC5Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 5: Reset the CC5E Bit */ - TIMx->CCER &= (uint32_t)~TIM_CCER_CC5E; /* to be verified*/ - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR3 register value */ - tmpccmrx = TIMx->CCMR3; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint32_t)~TIM_CCMR3_OC5M; - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode); - - /* Reset the Output Polarity level */ - tmpccer &= (uint32_t)~TIM_CCER_CC5P; - /* Set the Output Compare Polarity */ - tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 16); - - /* Set the Output State */ - tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 16); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - /* Reset the Output Compare IDLE State */ - tmpcr2 &=(uint32_t) ~TIM_CR2_OIS5; - /* Set the Output Idle state */ - tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 16); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR3 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR5 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel6 according to the specified parameters - * in the TIM_OCInitStruct. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC6Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 5: Reset the CC5E Bit */ - TIMx->CCER &= (uint32_t)~TIM_CCER_CC6E; /* to be verified*/ - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR3 register value */ - tmpccmrx = TIMx->CCMR3; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint32_t)~TIM_CCMR3_OC6M; - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint32_t)~TIM_CCER_CC6P; - /* Set the Output Compare Polarity */ - tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 20); - - /* Set the Output State */ - tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 20); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - /* Reset the Output Compare IDLE State */ - tmpcr2 &=(uint32_t) ~TIM_CR2_OIS6; - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 18); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR3 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR6 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Selects the TIM Group Channel 5 and Channel 1, - OC1REFC is the logical AND of OC1REFC and OC5REF. - * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral - * @param NewState: new state of the Commutation event. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectGC5C1(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the GC5C1 Bit */ - TIMx->CCR5 |= TIM_CCR5_GC5C1; - } - else - { - /* Reset the GC5C1 Bit */ - TIMx->CCR5 &= (uint32_t)~TIM_CCR5_GC5C1; - } -} - -/** - * @brief Selects the TIM Group Channel 5 and Channel 2, - OC2REFC is the logical AND of OC2REFC and OC5REF. - * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral - * @param NewState: new state of the Commutation event. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectGC5C2(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the GC5C2 Bit */ - TIMx->CCR5 |= TIM_CCR5_GC5C2; - } - else - { - /* Reset the GC5C2 Bit */ - TIMx->CCR5 &= (uint32_t)~TIM_CCR5_GC5C2; - } -} - - -/** - * @brief Selects the TIM Group Channel 5 and Channel 3, - OC3REFC is the logical AND of OC3REFC and OC5REF. - * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral - * @param NewState: new state of the Commutation event. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectGC5C3(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the GC5C3 Bit */ - TIMx->CCR5 |= TIM_CCR5_GC5C3; - } - else - { - /* Reset the GC5C3 Bit */ - TIMx->CCR5 &= (uint32_t)~TIM_CCR5_GC5C3; - } -} - -/** - * @brief Fills each TIM_OCInitStruct member with its default value. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - /* Set the default configuration */ - TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; - TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; - TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; - TIM_OCInitStruct->TIM_Pulse = 0x00000000; - TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; - TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; -} - -/** - * @brief Selects the TIM Output Compare Mode. - * @note This function disables the selected channel before changing the Output - * Compare Mode. If needed, user has to enable this channel using - * TIM_CCxCmd() and TIM_CCxNCmd() functions. - * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_OCMode: specifies the TIM Output Compare Mode. - * This parameter can be one of the following values: - * @arg TIM_OCMode_Timing - * @arg TIM_OCMode_Active - * @arg TIM_OCMode_Toggle - * @arg TIM_OCMode_PWM1 - * @arg TIM_OCMode_PWM2 - * @arg TIM_ForcedAction_Active - * @arg TIM_ForcedAction_InActive - * @arg TIM_OCMode_Retrigerrable_OPM1 - * @arg TIM_OCMode_Retrigerrable_OPM2 - * @arg TIM_OCMode_Combined_PWM1 - * @arg TIM_OCMode_Combined_PWM2 - * @arg TIM_OCMode_Asymmetric_PWM1 - * @arg TIM_OCMode_Asymmetric_PWM2 - * @retval None - */ -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint32_t TIM_OCMode) -{ - uint32_t tmp = 0; - uint16_t tmp1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_OCM(TIM_OCMode)); - - tmp = (uint32_t) TIMx; - tmp += CCMR_OFFSET; - - tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel; - - /* Disable the Channel: Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t) ~tmp1; - - if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) - { - tmp += (TIM_Channel>>1); - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK; - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= TIM_OCMode; - } - else - { - tmp += (uint32_t)(TIM_Channel - (uint32_t)4)>> (uint32_t)1; - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK; - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= (uint32_t)(TIM_OCMode << 8); - } -} - -/** - * @brief Sets the TIMx Capture Compare1 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. - * @param Compare1: specifies the Capture Compare1 register new value. - * @retval None - */ -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - - /* Set the Capture Compare1 Register value */ - TIMx->CCR1 = Compare1; -} - -/** - * @brief Sets the TIMx Capture Compare2 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM - * peripheral. - * @param Compare2: specifies the Capture Compare2 register new value. - * @retval None - */ -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Set the Capture Compare2 Register value */ - TIMx->CCR2 = Compare2; -} - -/** - * @brief Sets the TIMx Capture Compare3 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param Compare3: specifies the Capture Compare3 register new value. - * @retval None - */ -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Set the Capture Compare3 Register value */ - TIMx->CCR3 = Compare3; -} - -/** - * @brief Sets the TIMx Capture Compare4 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param Compare4: specifies the Capture Compare4 register new value. - * @retval None - */ -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Set the Capture Compare4 Register value */ - TIMx->CCR4 = Compare4; -} - -/** - * @brief Sets the TIMx Capture Compare5 Register value - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param Compare5: specifies the Capture Compare5 register new value. - * @retval None - */ -void TIM_SetCompare5(TIM_TypeDef* TIMx, uint32_t Compare5) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - - /* Set the Capture Compare5 Register value */ - TIMx->CCR5 = Compare5; -} - -/** - * @brief Sets the TIMx Capture Compare6 Register value - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param Compare6: specifies the Capture Compare5 register new value. - * @retval None - */ -void TIM_SetCompare6(TIM_TypeDef* TIMx, uint32_t Compare6) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - - /* Set the Capture Compare6 Register value */ - TIMx->CCR6 = Compare6; -} - -/** - * @brief Forces the TIMx output 1 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC1REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. - * @retval None - */ -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint32_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1M Bits */ - tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1M; - - /* Configure The Forced output Mode */ - tmpccmr1 |= TIM_ForcedAction; - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 2 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM - * peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC2REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. - * @retval None - */ -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint32_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2M Bits */ - tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC2M; - - /* Configure The Forced output Mode */ - tmpccmr1 |= ((uint32_t)TIM_ForcedAction << 8); - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 3 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC3REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. - * @retval None - */ -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint32_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC1M Bits */ - tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC3M; - - /* Configure The Forced output Mode */ - tmpccmr2 |= TIM_ForcedAction; - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Forces the TIMx output 4 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC4REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. - * @retval None - */ -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint32_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC2M Bits */ - tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC4M; - - /* Configure The Forced output Mode */ - tmpccmr2 |= ((uint32_t)TIM_ForcedAction << 8); - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Forces the TIMx output 5 waveform to active or inactive level. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC5REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC5REF. - * @retval None - */ -void TIM_ForcedOC5Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint32_t tmpccmr3 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr3 = TIMx->CCMR3; - - /* Reset the OC5M Bits */ - tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC5M; - - /* Configure The Forced output Mode */ - tmpccmr3 |= (uint32_t)(TIM_ForcedAction); - - /* Write to TIMx CCMR3 register */ - TIMx->CCMR3 = tmpccmr3; -} - -/** - * @brief Forces the TIMx output 6 waveform to active or inactive level. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC5REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC5REF. - * @retval None - */ -void TIM_ForcedOC6Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint32_t tmpccmr3 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr3 = TIMx->CCMR3; - - /* Reset the OC6M Bits */ - tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC6M; - - /* Configure The Forced output Mode */ - tmpccmr3 |= ((uint32_t)TIM_ForcedAction << 8); - - /* Write to TIMx CCMR3 register */ - TIMx->CCMR3 = tmpccmr3; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR1. - * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint32_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1PE Bit */ - tmpccmr1 &= (uint32_t)(~TIM_CCMR1_OC1PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= TIM_OCPreload; - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR2. - * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM - * peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint32_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2PE Bit */ - tmpccmr1 &= (uint32_t)(~TIM_CCMR1_OC2PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= ((uint32_t)TIM_OCPreload << 8); - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR3. - * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint32_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC3PE Bit */ - tmpccmr2 &= (uint32_t)(~TIM_CCMR2_OC3PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= TIM_OCPreload; - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR4. - * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint32_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC4PE Bit */ - tmpccmr2 &= (uint32_t)(~TIM_CCMR2_OC4PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= ((uint32_t)TIM_OCPreload << 8); - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR5. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC5PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint32_t tmpccmr3 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr3 = TIMx->CCMR3; - - /* Reset the OC5PE Bit */ - tmpccmr3 &= (uint32_t)(~TIM_CCMR3_OC5PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr3 |= (uint32_t)(TIM_OCPreload); - - /* Write to TIMx CCMR3 register */ - TIMx->CCMR3 = tmpccmr3; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR6. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC6PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint32_t tmpccmr3 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr3 = TIMx->CCMR3; - - /* Reset the OC5PE Bit */ - tmpccmr3 &= (uint32_t)(~TIM_CCMR3_OC6PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr3 |= ((uint32_t)TIM_OCPreload << 8); - - /* Write to TIMx CCMR3 register */ - TIMx->CCMR3 = tmpccmr3; -} - -/** - * @brief Configures the TIMx Output Compare 1 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint32_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1FE Bit */ - tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1FE; - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= TIM_OCFast; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 2 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM - * peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint32_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2FE Bit */ - tmpccmr1 &= (uint32_t)(~TIM_CCMR1_OC2FE); - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= ((uint32_t)TIM_OCFast << 8); - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 3 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint32_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC3FE Bit */ - tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC3FE; - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= TIM_OCFast; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 4 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint32_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC4FE Bit */ - tmpccmr2 &= (uint32_t)(~TIM_CCMR2_OC4FE); - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= ((uint32_t)TIM_OCFast << 8); - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF1 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint32_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1CE Bit */ - tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= TIM_OCClear; - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF2 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM - * peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint32_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2CE Bit */ - tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC2CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= ((uint32_t)TIM_OCClear << 8); - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF3 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint32_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC3CE Bit */ - tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC3CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= TIM_OCClear; - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF4 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint32_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC4CE Bit */ - tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC4CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= ((uint32_t)TIM_OCClear << 8); - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF5 signal on an external event - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC5Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint32_t tmpccmr3 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr3 = TIMx->CCMR3; - - /* Reset the OC5CE Bit */ - tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC5CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr3 |= (uint32_t)(TIM_OCClear); - - /* Write to TIMx CCMR3 register */ - TIMx->CCMR3 = tmpccmr3; -} - -/** - * @brief Clears or safeguards the OCREF6 signal on an external event - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC6Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint32_t tmpccmr3 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr3 = TIMx->CCMR3; - - /* Reset the OC5CE Bit */ - tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC6CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr3 |= ((uint32_t)TIM_OCClear << 8); - - /* Write to TIMx CCMR3 register */ - TIMx->CCMR3 = tmpccmr3; -} - -/** - * @brief Selects the OCReference Clear source. - * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_OCReferenceClear: specifies the OCReference Clear source. - * This parameter can be one of the following values: - * @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF. - * @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input. - * @retval None - */ -void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear)); - - /* Set the TIM_OCReferenceClear source */ - TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS); - TIMx->SMCR |= TIM_OCReferenceClear; -} - -/** - * @brief Configures the TIMx channel 1 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC1 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint32_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC1P Bit */ - tmpccer &= (uint32_t)(~TIM_CCER_CC1P); - tmpccer |= TIM_OCPolarity; - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 1N polarity. - * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC1N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint32_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC1NP Bit */ - tmpccer &= (uint32_t)~TIM_CCER_CC1NP; - tmpccer |= TIM_OCNPolarity; - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 2 polarity. - * @param TIMx: where x can be 1, 2, 3, 4 8 or 15 to select the TIM - * peripheral. - * @param TIM_OCPolarity: specifies the OC2 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint32_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC2P Bit */ - tmpccer &= (uint32_t)(~TIM_CCER_CC2P); - tmpccer |= ((uint32_t)TIM_OCPolarity << 4); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 2N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC2N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint32_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC2NP Bit */ - tmpccer &= (uint32_t)~TIM_CCER_CC2NP; - tmpccer |= ((uint32_t)TIM_OCNPolarity << 4); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 3 polarity. - * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC3 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint32_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC3P Bit */ - tmpccer &= (uint32_t)~TIM_CCER_CC3P; - tmpccer |= ((uint32_t)TIM_OCPolarity << 8); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 3N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC3N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint32_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC3NP Bit */ - tmpccer &= (uint32_t)~TIM_CCER_CC3NP; - tmpccer |= ((uint32_t)TIM_OCNPolarity << 8); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 4 polarity. - * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC4 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint32_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC4P Bit */ - tmpccer &= (uint32_t)~TIM_CCER_CC4P; - tmpccer |= ((uint32_t)TIM_OCPolarity << 12); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 5 polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC5 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC5PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint32_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC5P Bit */ - tmpccer &= (uint32_t)~TIM_CCER_CC5P; - tmpccer |= ((uint32_t)TIM_OCPolarity << 16); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 6 polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC6 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC6PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint32_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC6P Bit */ - tmpccer &= (uint32_t)~TIM_CCER_CC6P; - tmpccer |= ((uint32_t)TIM_OCPolarity << 20); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel x. - * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @arg TIM_Channel_5: TIM Channel 5 - * @arg TIM_Channel_6: TIM Channel 6 - * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. - * @retval None - */ -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_CCX(TIM_CCx)); - - tmp = (uint32_t)CCER_CCE_SET << (uint32_t)TIM_Channel; - - /* Reset the CCxE Bit */ - TIMx->CCER &= (uint32_t)(~tmp); - - /* Set or reset the CCxE Bit */ - TIMx->CCER |= ((uint32_t)TIM_CCx << (uint32_t)TIM_Channel); -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel xN. - * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. - * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. - * @retval None - */ -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_CCXN(TIM_CCxN)); - - tmp = (uint32_t)CCER_CCNE_SET << (uint32_t)TIM_Channel; - - /* Reset the CCxNE Bit */ - TIMx->CCER &= (uint32_t) ~tmp; - - /* Set or reset the CCxNE Bit */ - TIMx->CCER |= ((uint32_t)TIM_CCxN << (uint32_t)TIM_Channel); -} -/** - * @} - */ - -/** @defgroup TIM_Group3 Input Capture management functions - * @brief Input Capture management functions - * -@verbatim - =============================================================================== - ##### Input Capture management functions ##### - =============================================================================== - - *** TIM Driver: how to use it in Input Capture Mode *** - ======================================================= - [..] - To use the Timer in Input Capture mode, the following steps are mandatory: - - (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function - - (#) Configure the TIM pins by configuring the corresponding GPIO pins - - (#) Configure the Time base unit as described in the first part of this driver, - if needed, else the Timer will run with the default configuration: - (++) Autoreload value = 0xFFFF - (++) Prescaler value = 0x0000 - (++) Counter mode = Up counting - (++) Clock Division = TIM_CKD_DIV1 - - (#) Fill the TIM_ICInitStruct with the desired parameters including: - (++) TIM Channel: TIM_Channel - (++) TIM Input Capture polarity: TIM_ICPolarity - (++) TIM Input Capture selection: TIM_ICSelection - (++) TIM Input Capture Prescaler: TIM_ICPrescaler - (++) TIM Input CApture filter value: TIM_ICFilter - - (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the - corresponding configuration and to measure only frequency or duty cycle of the input signal, - or, - Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the - corresponding configuration and to measure the frequency and the duty cycle of the input signal - - (#) Enable the NVIC or the DMA to read the measured frequency. - - (#) Enable the corresponding interrupt (or DMA request) to read the Captured value, - using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) - - (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - - (#) Use TIM_GetCapturex(TIMx); to read the captured value. - [..] - (@) All other functions can be used separately to modify, if needed, - a specific feature of the Timer. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIM peripheral according to the specified parameters - * in the TIM_ICInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); - assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); - assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); - - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) - { - /* TI2 Configuration */ - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) - { - /* TI3 Configuration */ - TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - /* TI4 Configuration */ - TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Fills each TIM_ICInitStruct member with its default value. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Set the default configuration */ - TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; - TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; - TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; - TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; - TIM_ICInitStruct->TIM_ICFilter = 0x00; -} - -/** - * @brief Configures the TIM peripheral according to the specified parameters - * in the TIM_ICInitStruct to measure an external PWM signal. - * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM - * peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - uint16_t icoppositepolarity = TIM_ICPolarity_Rising; - uint16_t icoppositeselection = TIM_ICSelection_DirectTI; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Select the Opposite Input Polarity */ - if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) - { - icoppositepolarity = TIM_ICPolarity_Falling; - } - else - { - icoppositepolarity = TIM_ICPolarity_Rising; - } - /* Select the Opposite Input */ - if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) - { - icoppositeselection = TIM_ICSelection_IndirectTI; - } - else - { - icoppositeselection = TIM_ICSelection_DirectTI; - } - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI2 Configuration */ - TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - /* TI2 Configuration */ - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI1 Configuration */ - TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Gets the TIMx Input Capture 1 value. - * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. - * @retval Capture Compare 1 Register value. - */ -uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - - /* Get the Capture 1 Register value */ - return TIMx->CCR1; -} - -/** - * @brief Gets the TIMx Input Capture 2 value. - * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM - * peripheral. - * @retval Capture Compare 2 Register value. - */ -uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Get the Capture 2 Register value */ - return TIMx->CCR2; -} - -/** - * @brief Gets the TIMx Input Capture 3 value. - * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. - * @retval Capture Compare 3 Register value. - */ -uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Get the Capture 3 Register value */ - return TIMx->CCR3; -} - -/** - * @brief Gets the TIMx Input Capture 4 value. - * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. - * @retval Capture Compare 4 Register value. - */ -uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Get the Capture 4 Register value */ - return TIMx->CCR4; -} - -/** - * @brief Sets the TIMx Input Capture 1 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC1PSC Bits */ - TIMx->CCMR1 &= (uint32_t)~TIM_CCMR1_IC1PSC; - - /* Set the IC1PSC value */ - TIMx->CCMR1 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 2 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM - * peripheral. - * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC2PSC Bits */ - TIMx->CCMR1 &= (uint32_t)~TIM_CCMR1_IC2PSC; - - /* Set the IC2PSC value */ - TIMx->CCMR1 |= (uint32_t)((uint32_t)TIM_ICPSC << 8); -} - -/** - * @brief Sets the TIMx Input Capture 3 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC3PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC; - - /* Set the IC3PSC value */ - TIMx->CCMR2 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 4 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC4PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC; - - /* Set the IC4PSC value */ - TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); -} -/** - * @} - */ - -/** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features - * @brief Advanced-control timers (TIM1 and TIM8) specific features - * -@verbatim - =============================================================================== - ##### Advanced-control timers (TIM1 and TIM8) specific features ##### - =============================================================================== - - *** TIM Driver: how to use the Break feature *** - ================================================ - [..] - After configuring the Timer channel(s) in the appropriate Output Compare mode: - - (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer - Break Polarity, dead time, Lock level, the OSSI/OSSR State and the - AOE(automatic output enable). - - (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer - - (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) - - (#) Once the break even occurs, the Timer's output signals are put in reset - state or in a known state (according to the configuration made in - TIM_BDTRConfig() function). - -@endverbatim - * @{ - */ - -/** - * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State - * and the AOE(automatic output enable). - * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that - * contains the BDTR Register configuration information for the TIM peripheral. - * @retval None - */ -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); - assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); - assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); - assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); - assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); - assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); - - /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | - TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | - TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | - TIM_BDTRInitStruct->TIM_AutomaticOutput; -} - -/** - * @brief Configures the Break1 feature. - * @param TIMx: where x can be 1 or 8 to select the TIM - * @param TIM_Break1Polarity: specifies the Break1 polarity. - * This parameter can be one of the following values: - * @arg TIM_Break1Polarity_Low: Break1 input is active low - * @arg TIM_Break1Polarity_High: Break1 input is active high - * @param TIM_Break1Filter: specifies the Break1 filter value. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_Break1Config(TIM_TypeDef* TIMx, uint32_t TIM_Break1Polarity, uint8_t TIM_Break1Filter) -{ /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_BREAK1_FILTER(TIM_Break1Filter)); - - /* Reset the BKP and BKF Bits */ - TIMx->BDTR &= (uint32_t)~ (TIM_BDTR_BKP | TIM_BDTR_BKF); - /* Configure the Break1 polarity and filter */ - TIMx->BDTR |= TIM_Break1Polarity |((uint32_t)TIM_Break1Filter << 16); -} - -/** - * @brief Configures the Break2 feature. - * @param TIMx: where x can be 1 or 8 to select the TIM - * @param TIM_Break2Polarity: specifies the Break2 polarity. - * This parameter can be one of the following values: - * @arg TIM_Break2Polarity_Low: Break2 input is active low - * @arg TIM_Break2Polarity_High: Break2 input is active high - * @param TIM_Break2Filter: specifies the Break2 filter value. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_Break2Config(TIM_TypeDef* TIMx, uint32_t TIM_Break2Polarity, uint8_t TIM_Break2Filter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_BREAK2_FILTER(TIM_Break2Filter)); - - /* Reset the BKP and BKF Bits */ - TIMx->BDTR &= (uint32_t)~ (TIM_BDTR_BK2P | TIM_BDTR_BK2F); - - /* Configure the Break1 polarity and filter */ - TIMx->BDTR |= TIM_Break2Polarity |((uint32_t)TIM_Break2Filter << 20); -} - -/** - * @brief Enables or disables the TIM Break1 input. - * @param TIMx: where x can be 1, 8, 1, 16 or 17 to select the TIMx peripheral. - * @param NewState: new state of the TIM Break1 input. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_Break1Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Break1 */ - TIMx->BDTR |= TIM_BDTR_BKE; - } - else - { - /* Disable the Break1 */ - TIMx->BDTR &= (uint32_t)~TIM_BDTR_BKE; - } -} - -/** - * @brief Enables or disables the TIM Break2 input. - * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral. - * @param NewState: new state of the TIM Break2 input. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_Break2Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Break1 */ - TIMx->BDTR |= TIM_BDTR_BK2E; - } - else - { - /* Disable the Break1 */ - TIMx->BDTR &= (uint32_t)~TIM_BDTR_BK2E; - } -} - -/** - * @brief Fills each TIM_BDTRInitStruct member with its default value. - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which - * will be initialized. - * @retval None - */ -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) -{ - /* Set the default configuration */ - TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; - TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; - TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; - TIM_BDTRInitStruct->TIM_DeadTime = 0x00; - TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; - TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; - TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; -} - -/** - * @brief Enables or disables the TIM peripheral Main Outputs. - * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral. - * @param NewState: new state of the TIM peripheral Main Outputs. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TIM Main Output */ - TIMx->BDTR |= TIM_BDTR_MOE; - } - else - { - /* Disable the TIM Main Output */ - TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE; - } -} - -/** - * @brief Selects the TIM peripheral Commutation event. - * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral - * @param NewState: new state of the Commutation event. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the COM Bit */ - TIMx->CR2 |= TIM_CR2_CCUS; - } - else - { - /* Reset the COM Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS; - } -} - -/** - * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. - * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral - * @param NewState: new state of the Capture Compare Preload Control bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the CCPC Bit */ - TIMx->CR2 |= TIM_CR2_CCPC; - } - else - { - /* Reset the CCPC Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group5 Interrupts DMA and flags management functions - * @brief Interrupts, DMA and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts, DMA and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified TIM interrupts. - * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIMx peripheral. - * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * - * @note For TIM6 and TIM7 only the parameter TIM_IT_Update can be used - * @note For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update, - * TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. - * @note For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can - * be used: TIM_IT_Update or TIM_IT_CC1 - * @note TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8 - * - * @param NewState: new state of the TIM interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IT(TIM_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Interrupt sources */ - TIMx->DIER |= TIM_IT; - } - else - { - /* Disable the Interrupt sources */ - TIMx->DIER &= (uint16_t)~TIM_IT; - } -} - -/** - * @brief Configures the TIMx event to be generate by software. - * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_EventSource: specifies the event source. - * This parameter can be one or more of the following values: - * @arg TIM_EventSource_Update: Timer update Event source - * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EventSource_COM: Timer COM event source - * @arg TIM_EventSource_Trigger: Timer Trigger Event source - * @arg TIM_EventSource_Break: Timer Break event source - * - * @note TIM6 and TIM7 can only generate an update event. - * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. - * - * @retval None - */ -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); - - /* Set the event sources */ - TIMx->EGR = TIM_EventSource; -} - -/** - * @brief Checks whether the specified TIM flag is set or not. - * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_CC5: TIM Capture Compare 5 Flag - * @arg TIM_FLAG_CC6: TIM Capture Compare 6 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag - * - * @note TIM6 and TIM7 can have only one update flag. - * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. - * - * @retval The new state of TIM_FLAG (SET or RESET). - */ -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint32_t TIM_FLAG) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); - - - if ((TIMx->SR & TIM_FLAG) != RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's pending flags. - * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_CC5: TIM Capture Compare 5 Flag - * @arg TIM_FLAG_CC6: TIM Capture Compare 6 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag - * - * @note TIM6 and TIM7 can have only one update flag. - * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. - * - * @retval None - */ -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Clear the flags */ - TIMx->SR = (uint16_t)~TIM_FLAG; -} - -/** - * @brief Checks whether the TIM interrupt has occurred or not. - * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_IT: specifies the TIM interrupt source to check. - * This parameter can be one of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * - * @note TIM6 and TIM7 can generate only an update interrupt. - * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. - * - * @retval The new state of the TIM_IT(SET or RESET). - */ -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itstatus = 0x0, itenable = 0x0; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_IT(TIM_IT)); - - itstatus = TIMx->SR & TIM_IT; - - itenable = TIMx->DIER & TIM_IT; - if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's interrupt pending bits. - * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_IT: specifies the pending bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM1 update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * - * @note TIM6 and TIM7 can generate only an update interrupt. - * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. - * - * @retval None - */ -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Clear the IT pending Bit */ - TIMx->SR = (uint16_t)~TIM_IT; -} - -/** - * @brief Configures the TIMx's DMA interface. - * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. - * @param TIM_DMABase: DMA Base address. - * This parameter can be one of the following values: - * @arg TIM_DMABase_CR1 - * @arg TIM_DMABase_CR2 - * @arg TIM_DMABase_SMCR - * @arg TIM_DMABase_DIER - * @arg TIM1_DMABase_SR - * @arg TIM_DMABase_EGR - * @arg TIM_DMABase_CCMR1 - * @arg TIM_DMABase_CCMR2 - * @arg TIM_DMABase_CCER - * @arg TIM_DMABase_CNT - * @arg TIM_DMABase_PSC - * @arg TIM_DMABase_ARR - * @arg TIM_DMABase_RCR - * @arg TIM_DMABase_CCR1 - * @arg TIM_DMABase_CCR2 - * @arg TIM_DMABase_CCR3 - * @arg TIM_DMABase_CCR4 - * @arg TIM_DMABase_BDTR - * @arg TIM_DMABase_DCR - * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value - * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. - * @retval None - */ -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); - assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); - - /* Set the DMA Base and the DMA Burst Length */ - TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; -} - -/** - * @brief Enables or disables the TIMx's DMA Requests. - * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_DMASource: specifies the DMA Request sources. - * This parameter can be any combination of the following values: - * @arg TIM_DMA_Update: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_Trigger: TIM Trigger DMA source - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA sources */ - TIMx->DIER |= TIM_DMASource; - } - else - { - /* Disable the DMA sources */ - TIMx->DIER &= (uint16_t)~TIM_DMASource; - } -} - -/** - * @brief Selects the TIMx peripheral Capture Compare DMA source. - * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. - * @param NewState: new state of the Capture Compare DMA source - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the CCDS Bit */ - TIMx->CR2 |= TIM_CR2_CCDS; - } - else - { - /* Reset the CCDS Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group6 Clocks management functions - * @brief Clocks management functions - * -@verbatim - =============================================================================== - ##### Clocks management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIMx internal Clock - * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM - * peripheral. - * @retval None - */ -void TIM_InternalClockConfig(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Disable slave mode to clock the prescaler directly with the internal clock */ - TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS; -} - -/** - * @brief Configures the TIMx Internal Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM - * peripheral. - * @param TIM_InputTriggerSource: Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @retval None - */ -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); - - /* Select the Internal Trigger */ - TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); - - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the TIMx Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 - * to select the TIM peripheral. - * @param TIM_TIxExternalCLKSource: Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector - * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 - * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 - * @param TIM_ICPolarity: specifies the TIx Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param ICFilter: specifies the filter value. - * This parameter must be a value between 0x0 and 0xF. - * @retval None - */ -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); - assert_param(IS_TIM_IC_FILTER(ICFilter)); - - /* Configure the Timer Input Clock Source */ - if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) - { - TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - else - { - TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - /* Select the Trigger source */ - TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the External clock Mode1 - * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - - /* Reset the SMS Bits */ - tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; - - /* Select the External clock mode1 */ - tmpsmcr |= TIM_SlaveMode_External1; - - /* Select the Trigger selection : ETRF */ - tmpsmcr &= (uint16_t)~TIM_SMCR_TS; - tmpsmcr |= TIM_TS_ETRF; - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Configures the External clock Mode2 - * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - - /* Enable the External clock mode2 */ - TIMx->SMCR |= TIM_SMCR_ECE; -} -/** - * @} - */ - -/** @defgroup TIM_Group7 Synchronization management functions - * @brief Synchronization management functions - * -@verbatim - =============================================================================== - ##### Synchronization management functions ##### - =============================================================================== - - *** TIM Driver: how to use it in synchronization Mode *** - ========================================================= - [..] Case of two/several Timers - - (#) Configure the Master Timers using the following functions: - (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); - (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); - (#) Configure the Slave Timers using the following functions: - (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); - (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); - - [..] Case of Timers and external trigger(ETR pin) - - (#) Configure the External trigger using this function: - (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); - (#) Configure the Slave Timers using the following functions: - (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); - (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); - -@endverbatim - * @{ - */ - -/** - * @brief Selects the Input Trigger source - * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 - * to select the TIM peripheral. - * @param TIM_InputTriggerSource: The Input Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input - * @retval None - */ -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - - /* Reset the TS Bits */ - tmpsmcr &= (uint16_t)~TIM_SMCR_TS; - - /* Set the Input Trigger source */ - tmpsmcr |= TIM_InputTriggerSource; - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Selects the TIMx Trigger Output Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8 or 15 to select the TIM peripheral. - * - * @param TIM_TRGOSource: specifies the Trigger Output source. - * This parameter can be one of the following values: - * - * - For all TIMx - * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO) - * - * - For all TIMx except TIM6 and TIM7 - * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag - * is to be set, as soon as a capture or compare match occurs(TRGO) - * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO) - * - * @retval None - */ -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST7_PERIPH(TIMx)); - assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); - - /* Reset the MMS Bits */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS; - /* Select the TRGO source */ - TIMx->CR2 |= TIM_TRGOSource; -} - -/** - * @brief Selects the TIMx Trigger Output Mode2 (TRGO2). - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * - * @param TIM_TRGO2Source: specifies the Trigger Output source. - * This parameter can be one of the following values: - * - * - For all TIMx - * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO2) - * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO2) - * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO2) - * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag - * is to be set, as soon as a capture or compare match occurs(TRGO2) - * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO2) - * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO2) - * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO2) - * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO2) - * @arg TIM_TRGO2Source_OC4Ref_RisingFalling: OC4Ref Rising and Falling are used as the trigger output(TRGO2) - * @arg TIM_TRGO2Source_OC6Ref_RisingFalling: OC6Ref Rising and Falling are used as the trigger output(TRGO2) - * @arg TIM_TRGO2Source_OC4RefRising_OC6RefRising: OC4Ref Rising and OC6Ref Rising are used as the trigger output(TRGO2) - * @arg TIM_TRGO2Source_OC4RefRising_OC6RefFalling: OC4Ref Rising and OC6Ref Falling are used as the trigger output(TRGO2) - * @arg TIM_TRGO2Source_OC5RefRising_OC6RefRising: OC5Ref Rising and OC6Ref Rising are used as the trigger output(TRGO2) - * @arg TIM_TRGO2Source_OC5RefRising_OC6RefFalling: OC5Ref Rising and OC6Ref Falling are used as the trigger output(TRGO2) - * - * @retval None - */ -void TIM_SelectOutputTrigger2(TIM_TypeDef* TIMx, uint32_t TIM_TRGO2Source) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_TRGO2_SOURCE(TIM_TRGO2Source)); - - /* Reset the MMS Bits */ - TIMx->CR2 &= (uint32_t)~TIM_CR2_MMS2; - /* Select the TRGO source */ - TIMx->CR2 |= TIM_TRGO2Source; -} - -/** - * @brief Selects the TIMx Slave Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM peripheral. - * @param TIM_SlaveMode: specifies the Timer Slave Mode. - * This parameter can be one of the following values: - * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize - * the counter and triggers an update of the registers - * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high - * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI - * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter - * @arg TIM_SlaveMode_Combined_ResetTrigger: Rising edge of the selected trigger input (TRGI) - * reinitializes the counter, generates an update - * of the registers and starts the counter. - * @retval None - */ -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_SlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); - - /* Reset the SMS Bits */ - TIMx->SMCR &= (uint32_t)~TIM_SMCR_SMS; - - /* Select the Slave Mode */ - TIMx->SMCR |= (uint32_t)TIM_SlaveMode; -} - -/** - * @brief Sets or Resets the TIMx Master/Slave Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM peripheral. - * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. - * This parameter can be one of the following values: - * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer - * and its slaves (through TRGO) - * @arg TIM_MasterSlaveMode_Disable: No action - * @retval None - */ -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); - - /* Reset the MSM Bit */ - TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM; - - /* Set or Reset the MSM Bit */ - TIMx->SMCR |= TIM_MasterSlaveMode; -} - -/** - * @brief Configures the TIMx External Trigger (ETR). - * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - - tmpsmcr = TIMx->SMCR; - - /* Reset the ETR Bits */ - tmpsmcr &= SMCR_ETR_MASK; - - /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} -/** - * @} - */ - -/** @defgroup TIM_Group8 Specific interface management functions - * @brief Specific interface management functions - * -@verbatim - =============================================================================== - ##### Specific interface management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIMx Encoder Interface. - * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM - * peripheral. - * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. - * This parameter can be one of the following values: - * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. - * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. - * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending - * on the level of the other input. - * @param TIM_IC1Polarity: specifies the IC1 Polarity - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @param TIM_IC2Polarity: specifies the IC2 Polarity - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @retval None - */ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) -{ - uint16_t tmpsmcr = 0; - uint16_t tmpccmr1 = 0; - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Set the encoder Mode */ - tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; - tmpsmcr |= TIM_EncoderMode; - - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S); - tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; - - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P); - tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Enables or disables the TIMx's Hall sensor interface. - * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM - * peripheral. - * @param NewState: new state of the TIMx Hall sensor interface. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the TI1S Bit */ - TIMx->CR2 |= TIM_CR2_TI1S; - } - else - { - /* Reset the TI1S Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group9 Specific remapping management function - * @brief Specific remapping management function - * -@verbatim - =============================================================================== - ##### Specific remapping management function ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIM16 Remapping input Capabilities. - * @param TIMx: where x can be 1, 8 or 16 to select the TIM peripheral. - * @param TIM_Remap: specifies the TIM input reampping source. - * This parameter can be one of the following values: - * @arg TIM16_GPIO: TIM16 Channel 1 is connected to GPIO. - * @arg TIM16_RTC_CLK: TIM16 Channel 1 is connected to RTC input clock. - * @arg TIM16_HSE_DIV32: TIM16 Channel 1 is connected to HSE/32 clock. - * @arg TIM16_MCO: TIM16 Channel 1 is connected to MCO clock. - * @arg TIM1_ADC1_AWDG1: TIM1 ETR is connected to ADC1 AWDG1. - * @arg TIM1_ADC1_AWDG2: TIM1 ETR is connected to ADC1 AWDG2. - * @arg TIM1_ADC1_AWDG3: TIM1 ETR is connected to ADC1 AWDG3. - * @arg TIM1_ADC4_AWDG1: TIM1 ETR is connected to ADC4 AWDG1. - * @arg TIM1_ADC4_AWDG2: TIM1 ETR is connected to ADC4 AWDG2. - * @arg TIM1_ADC4_AWDG3: TIM1 ETR is connected to ADC4 AWDG3. - * @arg TIM8_ADC2_AWDG1: TIM8 ETR is connected to ADC2 AWDG1. - * @arg TIM8_ADC2_AWDG2: TIM8 ETR is connected to ADC2 AWDG2. - * @arg TIM8_ADC2_AWDG3: TIM8 ETR is connected to ADC2 AWDG3. - * @arg TIM8_ADC4_AWDG1: TIM8 ETR is connected to ADC4 AWDG1. - * @arg TIM8_ADC4_AWDG2: TIM8 ETR is connected to ADC4 AWDG2. - * @arg TIM8_ADC4_AWDG3: TIM8 ETR is connected to ADC4 AWDG3. - * @retval : None - */ -void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_REMAP(TIM_Remap)); - - /* Set the Timer remapping configuration */ - TIMx->OR = TIM_Remap; -} -/** - * @} - */ - -/** - * @brief Configure the TI1 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 - * to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint32_t tmpccmr1 = 0, tmpccer = 0; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Select the Input and set the filter */ - tmpccmr1 &= ((uint32_t)~TIM_CCMR1_CC1S) & ((uint32_t)~TIM_CCMR1_IC1F); - tmpccmr1 |= (uint32_t)(TIM_ICSelection | (uint32_t)((uint32_t)TIM_ICFilter << 4)); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= (uint32_t)(TIM_ICPolarity | (uint32_t)TIM_CCER_CC1E); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint32_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 4); - - /* Select the Input and set the filter */ - tmpccmr1 &= ((uint32_t)~TIM_CCMR1_CC2S) & ((uint32_t)~TIM_CCMR1_IC2F); - tmpccmr1 |= (uint32_t)((uint32_t)TIM_ICFilter << 12); - tmpccmr1 |= (uint32_t)((uint32_t)TIM_ICSelection << 8); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 8); - - /* Select the Input and set the filter */ - tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F); - tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI4 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 12); - - /* Select the Input and set the filter */ - tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F); - tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); - tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); - - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer ; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_tim.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1344 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_tim.h - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file contains all the functions prototypes for the TIM firmware - * library. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F30x_TIM_H -#define __STM32F30x_TIM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x.h" - -/** @addtogroup stm32f30x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup TIM - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief TIM Time Base Init structure definition - * @note This structure is used with all TIMx except for TIM6 and TIM7. - */ - -typedef struct -{ - uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter must be a number between 0x0000 and 0xFFFF. */ - - uint16_t TIM_ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_Clock_Division_CKD */ - - uint16_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_TimeBaseInitTypeDef; - -/** - * @brief TIM Output Compare Init structure definition - */ - -typedef struct -{ - uint32_t TIM_OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_State */ - - uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_N_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_OCInitTypeDef; - -/** - * @brief TIM Input Capture Init structure definition - */ - -typedef struct -{ - - uint16_t TIM_Channel; /*!< Specifies the TIM channel. - This parameter can be a value of @ref TIM_Channel */ - - uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint16_t TIM_ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between 0x0 and 0xF */ -} TIM_ICInitTypeDef; - -/** - * @brief BDTR structure definition - * @note This structure is used only with TIM1 and TIM8. - */ - -typedef struct -{ - - uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. - This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ - - uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. - This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ - - uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. - This parameter can be a value of @ref TIM_Lock_level */ - - uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the - switching-on of the outputs. - This parameter can be a number between 0x00 and 0xFF */ - - uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. - This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - - uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. - This parameter can be a value of @ref TIM_Break_Polarity */ - - uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ -} TIM_BDTRInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup TIM_Exported_constants - * @{ - */ - -#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM15) || \ - ((PERIPH) == TIM16) || \ - ((PERIPH) == TIM17)) -/* LIST1: TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16 and TIM17 */ -#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM15) || \ - ((PERIPH) == TIM16) || \ - ((PERIPH) == TIM17)) - -/* LIST2: TIM1, TIM2, TIM3, TIM4, TIM8 and TIM15 */ -#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM15)) -/* LIST3: TIM1, TIM2, TIM3, TIM4 and TIM8 */ -#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM8)) -/* LIST4: TIM1 and TIM8 */ -#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) ||\ - ((PERIPH) == TIM8)) -/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */ -#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM8)) -/* LIST6: TIM1, TIM8, TIM15, TIM16 and TIM17 */ -#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM15) || \ - ((PERIPH) == TIM16) || \ - ((PERIPH) == TIM17)) - -/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */ -#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM15)) -/* LIST8: TIM16 (option register) */ -#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM16)|| \ - ((PERIPH) == TIM1)||\ - ((PERIPH) == TIM8)) - -/** @defgroup TIM_Output_Compare_and_PWM_modes - * @{ - */ - -#define TIM_OCMode_Timing ((uint32_t)0x00000) -#define TIM_OCMode_Active ((uint32_t)0x00010) -#define TIM_OCMode_Inactive ((uint32_t)0x00020) -#define TIM_OCMode_Toggle ((uint32_t)0x00030) -#define TIM_OCMode_PWM1 ((uint32_t)0x00060) -#define TIM_OCMode_PWM2 ((uint32_t)0x00070) - -#define TIM_OCMode_Retrigerrable_OPM1 ((uint32_t)0x10000) -#define TIM_OCMode_Retrigerrable_OPM2 ((uint32_t)0x10010) -#define TIM_OCMode_Combined_PWM1 ((uint32_t)0x10040) -#define TIM_OCMode_Combined_PWM2 ((uint32_t)0x10050) -#define TIM_OCMode_Asymmetric_PWM1 ((uint32_t)0x10060) -#define TIM_OCMode_Asymmetric_PWM2 ((uint32_t)0x10070) - -#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2) || \ - ((MODE) == TIM_OCMode_Retrigerrable_OPM1) || \ - ((MODE) == TIM_OCMode_Retrigerrable_OPM2) || \ - ((MODE) == TIM_OCMode_Combined_PWM1) || \ - ((MODE) == TIM_OCMode_Combined_PWM2) || \ - ((MODE) == TIM_OCMode_Asymmetric_PWM1) || \ - ((MODE) == TIM_OCMode_Asymmetric_PWM2)) - -#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2) || \ - ((MODE) == TIM_ForcedAction_Active) || \ - ((MODE) == TIM_ForcedAction_InActive) || \ - ((MODE) == TIM_OCMode_Retrigerrable_OPM1) || \ - ((MODE) == TIM_OCMode_Retrigerrable_OPM2) || \ - ((MODE) == TIM_OCMode_Combined_PWM1) || \ - ((MODE) == TIM_OCMode_Combined_PWM2) || \ - ((MODE) == TIM_OCMode_Asymmetric_PWM1) || \ - ((MODE) == TIM_OCMode_Asymmetric_PWM2)) -/** - * @} - */ - -/** @defgroup TIM_One_Pulse_Mode - * @{ - */ - -#define TIM_OPMode_Single ((uint16_t)0x0008) -#define TIM_OPMode_Repetitive ((uint16_t)0x0000) -#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ - ((MODE) == TIM_OPMode_Repetitive)) -/** - * @} - */ - -/** @defgroup TIM_Channel - * @{ - */ - -#define TIM_Channel_1 ((uint16_t)0x0000) -#define TIM_Channel_2 ((uint16_t)0x0004) -#define TIM_Channel_3 ((uint16_t)0x0008) -#define TIM_Channel_4 ((uint16_t)0x000C) -#define TIM_Channel_5 ((uint16_t)0x0010) -#define TIM_Channel_6 ((uint16_t)0x0014) - -#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3) || \ - ((CHANNEL) == TIM_Channel_4)) - -#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2)) -#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3)) -/** - * @} - */ - -/** @defgroup TIM_Clock_Division_CKD - * @{ - */ - -#define TIM_CKD_DIV1 ((uint16_t)0x0000) -#define TIM_CKD_DIV2 ((uint16_t)0x0100) -#define TIM_CKD_DIV4 ((uint16_t)0x0200) -#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ - ((DIV) == TIM_CKD_DIV2) || \ - ((DIV) == TIM_CKD_DIV4)) -/** - * @} - */ - -/** @defgroup TIM_Counter_Mode - * @{ - */ - -#define TIM_CounterMode_Up ((uint16_t)0x0000) -#define TIM_CounterMode_Down ((uint16_t)0x0010) -#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) -#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) -#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) -#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ - ((MODE) == TIM_CounterMode_Down) || \ - ((MODE) == TIM_CounterMode_CenterAligned1) || \ - ((MODE) == TIM_CounterMode_CenterAligned2) || \ - ((MODE) == TIM_CounterMode_CenterAligned3)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Polarity - * @{ - */ - -#define TIM_OCPolarity_High ((uint16_t)0x0000) -#define TIM_OCPolarity_Low ((uint16_t)0x0002) -#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ - ((POLARITY) == TIM_OCPolarity_Low)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Polarity - * @{ - */ - -#define TIM_OCNPolarity_High ((uint16_t)0x0000) -#define TIM_OCNPolarity_Low ((uint16_t)0x0008) -#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ - ((POLARITY) == TIM_OCNPolarity_Low)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_State - * @{ - */ - -#define TIM_OutputState_Disable ((uint16_t)0x0000) -#define TIM_OutputState_Enable ((uint16_t)0x0001) -#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ - ((STATE) == TIM_OutputState_Enable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_State - * @{ - */ - -#define TIM_OutputNState_Disable ((uint16_t)0x0000) -#define TIM_OutputNState_Enable ((uint16_t)0x0004) -#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ - ((STATE) == TIM_OutputNState_Enable)) -/** - * @} - */ - -/** @defgroup TIM_Capture_Compare_State - * @{ - */ - -#define TIM_CCx_Enable ((uint16_t)0x0001) -#define TIM_CCx_Disable ((uint16_t)0x0000) -#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ - ((CCX) == TIM_CCx_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Capture_Compare_N_State - * @{ - */ - -#define TIM_CCxN_Enable ((uint16_t)0x0004) -#define TIM_CCxN_Disable ((uint16_t)0x0000) -#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ - ((CCXN) == TIM_CCxN_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Break_Input_enable_disable - * @{ - */ - -#define TIM_Break_Enable ((uint16_t)0x1000) -#define TIM_Break_Disable ((uint16_t)0x0000) -#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ - ((STATE) == TIM_Break_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Break1_Input_enable_disable - * @{ - */ - -#define TIM_Break1_Enable ((uint32_t)0x00001000) -#define TIM_Break1_Disable ((uint32_t)0x00000000) -#define IS_TIM_BREAK1_STATE(STATE) (((STATE) == TIM_Break1_Enable) || \ - ((STATE) == TIM_Break1_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Break2_Input_enable_disable - * @{ - */ - -#define TIM_Break2_Enable ((uint32_t)0x01000000) -#define TIM_Break2_Disable ((uint32_t)0x00000000) -#define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_Break2_Enable) || \ - ((STATE) == TIM_Break2_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Break_Polarity - * @{ - */ - -#define TIM_BreakPolarity_Low ((uint16_t)0x0000) -#define TIM_BreakPolarity_High ((uint16_t)0x2000) -#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ - ((POLARITY) == TIM_BreakPolarity_High)) -/** - * @} - */ - -/** @defgroup TIM_Break1_Polarity - * @{ - */ - -#define TIM_Break1Polarity_Low ((uint32_t)0x00000000) -#define TIM_Break1Polarity_High ((uint32_t)0x00002000) -#define IS_TIM_BREAK1_POLARITY(POLARITY) (((POLARITY) == TIM_Break1Polarity_Low) || \ - ((POLARITY) == TIM_Break1Polarity_High)) -/** - * @} - */ - -/** @defgroup TIM_Break2_Polarity - * @{ - */ - -#define TIM_Break2Polarity_Low ((uint32_t)0x00000000) -#define TIM_Break2Polarity_High ((uint32_t)0x02000000) -#define IS_TIM_BREAK2_POLARITY(POLARITY) (((POLARITY) == TIM_Break2Polarity_Low) || \ - ((POLARITY) == TIM_Break2Polarity_High)) -/** - * @} - */ - -/** @defgroup TIM_Break1_Filter - * @{ - */ - -#define IS_TIM_BREAK1_FILTER(FILTER) ((FILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_Break2_Filter - * @{ - */ - -#define IS_TIM_BREAK2_FILTER(FILTER) ((FILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_AOE_Bit_Set_Reset - * @{ - */ - -#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) -#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) -#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ - ((STATE) == TIM_AutomaticOutput_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Lock_level - * @{ - */ - -#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) -#define TIM_LOCKLevel_1 ((uint16_t)0x0100) -#define TIM_LOCKLevel_2 ((uint16_t)0x0200) -#define TIM_LOCKLevel_3 ((uint16_t)0x0300) -#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ - ((LEVEL) == TIM_LOCKLevel_1) || \ - ((LEVEL) == TIM_LOCKLevel_2) || \ - ((LEVEL) == TIM_LOCKLevel_3)) -/** - * @} - */ - -/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state - * @{ - */ - -#define TIM_OSSIState_Enable ((uint16_t)0x0400) -#define TIM_OSSIState_Disable ((uint16_t)0x0000) -#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ - ((STATE) == TIM_OSSIState_Disable)) -/** - * @} - */ - -/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state - * @{ - */ - -#define TIM_OSSRState_Enable ((uint16_t)0x0800) -#define TIM_OSSRState_Disable ((uint16_t)0x0000) -#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ - ((STATE) == TIM_OSSRState_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Idle_State - * @{ - */ - -#define TIM_OCIdleState_Set ((uint16_t)0x0100) -#define TIM_OCIdleState_Reset ((uint16_t)0x0000) -#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ - ((STATE) == TIM_OCIdleState_Reset)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Idle_State - * @{ - */ - -#define TIM_OCNIdleState_Set ((uint16_t)0x0200) -#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) -#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ - ((STATE) == TIM_OCNIdleState_Reset)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Polarity - * @{ - */ - -#define TIM_ICPolarity_Rising ((uint16_t)0x0000) -#define TIM_ICPolarity_Falling ((uint16_t)0x0002) -#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) -#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ - ((POLARITY) == TIM_ICPolarity_Falling)|| \ - ((POLARITY) == TIM_ICPolarity_BothEdge)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Selection - * @{ - */ - -#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively. */ -#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ -#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ - ((SELECTION) == TIM_ICSelection_IndirectTI) || \ - ((SELECTION) == TIM_ICSelection_TRC)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Prescaler - * @{ - */ - -#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ -#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ -#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ -#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ -#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ - ((PRESCALER) == TIM_ICPSC_DIV2) || \ - ((PRESCALER) == TIM_ICPSC_DIV4) || \ - ((PRESCALER) == TIM_ICPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_interrupt_sources - * @{ - */ - -#define TIM_IT_Update ((uint16_t)0x0001) -#define TIM_IT_CC1 ((uint16_t)0x0002) -#define TIM_IT_CC2 ((uint16_t)0x0004) -#define TIM_IT_CC3 ((uint16_t)0x0008) -#define TIM_IT_CC4 ((uint16_t)0x0010) -#define TIM_IT_COM ((uint16_t)0x0020) -#define TIM_IT_Trigger ((uint16_t)0x0040) -#define TIM_IT_Break ((uint16_t)0x0080) -#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) - -#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ - ((IT) == TIM_IT_CC1) || \ - ((IT) == TIM_IT_CC2) || \ - ((IT) == TIM_IT_CC3) || \ - ((IT) == TIM_IT_CC4) || \ - ((IT) == TIM_IT_COM) || \ - ((IT) == TIM_IT_Trigger) || \ - ((IT) == TIM_IT_Break)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Base_address - * @{ - */ - -#define TIM_DMABase_CR1 ((uint16_t)0x0000) -#define TIM_DMABase_CR2 ((uint16_t)0x0001) -#define TIM_DMABase_SMCR ((uint16_t)0x0002) -#define TIM_DMABase_DIER ((uint16_t)0x0003) -#define TIM_DMABase_SR ((uint16_t)0x0004) -#define TIM_DMABase_EGR ((uint16_t)0x0005) -#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) -#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) -#define TIM_DMABase_CCER ((uint16_t)0x0008) -#define TIM_DMABase_CNT ((uint16_t)0x0009) -#define TIM_DMABase_PSC ((uint16_t)0x000A) -#define TIM_DMABase_ARR ((uint16_t)0x000B) -#define TIM_DMABase_RCR ((uint16_t)0x000C) -#define TIM_DMABase_CCR1 ((uint16_t)0x000D) -#define TIM_DMABase_CCR2 ((uint16_t)0x000E) -#define TIM_DMABase_CCR3 ((uint16_t)0x000F) -#define TIM_DMABase_CCR4 ((uint16_t)0x0010) -#define TIM_DMABase_BDTR ((uint16_t)0x0011) -#define TIM_DMABase_DCR ((uint16_t)0x0012) -#define TIM_DMABase_OR ((uint16_t)0x0013) -#define TIM_DMABase_CCMR3 ((uint16_t)0x0014) -#define TIM_DMABase_CCR5 ((uint16_t)0x0015) -#define TIM_DMABase_CCR6 ((uint16_t)0x0016) -#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ - ((BASE) == TIM_DMABase_CR2) || \ - ((BASE) == TIM_DMABase_SMCR) || \ - ((BASE) == TIM_DMABase_DIER) || \ - ((BASE) == TIM_DMABase_SR) || \ - ((BASE) == TIM_DMABase_EGR) || \ - ((BASE) == TIM_DMABase_CCMR1) || \ - ((BASE) == TIM_DMABase_CCMR2) || \ - ((BASE) == TIM_DMABase_CCER) || \ - ((BASE) == TIM_DMABase_CNT) || \ - ((BASE) == TIM_DMABase_PSC) || \ - ((BASE) == TIM_DMABase_ARR) || \ - ((BASE) == TIM_DMABase_RCR) || \ - ((BASE) == TIM_DMABase_CCR1) || \ - ((BASE) == TIM_DMABase_CCR2) || \ - ((BASE) == TIM_DMABase_CCR3) || \ - ((BASE) == TIM_DMABase_CCR4) || \ - ((BASE) == TIM_DMABase_BDTR) || \ - ((BASE) == TIM_DMABase_DCR) || \ - ((BASE) == TIM_DMABase_OR) || \ - ((BASE) == TIM_DMABase_CCMR3) || \ - ((BASE) == TIM_DMABase_CCR5) || \ - ((BASE) == TIM_DMABase_CCR6)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Burst_Length - * @{ - */ - -#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) -#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) -#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) -#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) -#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) -#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) -#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) -#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) -#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) -#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) -#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) -#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) -#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) -#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) -#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) -#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) -#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) -#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) -#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ - ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_18Transfers)) -/** - * @} - */ - -/** @defgroup TIM_DMA_sources - * @{ - */ - -#define TIM_DMA_Update ((uint16_t)0x0100) -#define TIM_DMA_CC1 ((uint16_t)0x0200) -#define TIM_DMA_CC2 ((uint16_t)0x0400) -#define TIM_DMA_CC3 ((uint16_t)0x0800) -#define TIM_DMA_CC4 ((uint16_t)0x1000) -#define TIM_DMA_COM ((uint16_t)0x2000) -#define TIM_DMA_Trigger ((uint16_t)0x4000) -#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Prescaler - * @{ - */ - -#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) -#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) -#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) -#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) -#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_Internal_Trigger_Selection - * @{ - */ - -#define TIM_TS_ITR0 ((uint16_t)0x0000) -#define TIM_TS_ITR1 ((uint16_t)0x0010) -#define TIM_TS_ITR2 ((uint16_t)0x0020) -#define TIM_TS_ITR3 ((uint16_t)0x0030) -#define TIM_TS_TI1F_ED ((uint16_t)0x0040) -#define TIM_TS_TI1FP1 ((uint16_t)0x0050) -#define TIM_TS_TI2FP2 ((uint16_t)0x0060) -#define TIM_TS_ETRF ((uint16_t)0x0070) -#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_TI1F_ED) || \ - ((SELECTION) == TIM_TS_TI1FP1) || \ - ((SELECTION) == TIM_TS_TI2FP2) || \ - ((SELECTION) == TIM_TS_ETRF)) -#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3)) -/** - * @} - */ - -/** @defgroup TIM_TIx_External_Clock_Source - * @{ - */ - -#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) -#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) -#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) - -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Polarity - * @{ - */ -#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) -#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) -#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ - ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) -/** - * @} - */ - -/** @defgroup TIM_Prescaler_Reload_Mode - * @{ - */ - -#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) -#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) -#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ - ((RELOAD) == TIM_PSCReloadMode_Immediate)) -/** - * @} - */ - -/** @defgroup TIM_Forced_Action - * @{ - */ - -#define TIM_ForcedAction_Active ((uint16_t)0x0050) -#define TIM_ForcedAction_InActive ((uint16_t)0x0040) -#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ - ((ACTION) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_Encoder_Mode - * @{ - */ - -#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) -#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) -#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) -#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ - ((MODE) == TIM_EncoderMode_TI2) || \ - ((MODE) == TIM_EncoderMode_TI12)) -/** - * @} - */ - - -/** @defgroup TIM_Event_Source - * @{ - */ - -#define TIM_EventSource_Update ((uint16_t)0x0001) -#define TIM_EventSource_CC1 ((uint16_t)0x0002) -#define TIM_EventSource_CC2 ((uint16_t)0x0004) -#define TIM_EventSource_CC3 ((uint16_t)0x0008) -#define TIM_EventSource_CC4 ((uint16_t)0x0010) -#define TIM_EventSource_COM ((uint16_t)0x0020) -#define TIM_EventSource_Trigger ((uint16_t)0x0040) -#define TIM_EventSource_Break ((uint16_t)0x0080) -#define TIM_EventSource_Break2 ((uint16_t)0x0100) -#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFE00) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_Update_Source - * @{ - */ - -#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow - or the setting of UG bit, or an update generation - through the slave mode controller. */ -#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ -#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ - ((SOURCE) == TIM_UpdateSource_Regular)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Preload_State - * @{ - */ - -#define TIM_OCPreload_Enable ((uint16_t)0x0008) -#define TIM_OCPreload_Disable ((uint16_t)0x0000) -#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ - ((STATE) == TIM_OCPreload_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Fast_State - * @{ - */ - -#define TIM_OCFast_Enable ((uint16_t)0x0004) -#define TIM_OCFast_Disable ((uint16_t)0x0000) -#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ - ((STATE) == TIM_OCFast_Disable)) - -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Clear_State - * @{ - */ - -#define TIM_OCClear_Enable ((uint16_t)0x0080) -#define TIM_OCClear_Disable ((uint16_t)0x0000) -#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ - ((STATE) == TIM_OCClear_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Output_Source - * @{ - */ - -#define TIM_TRGOSource_Reset ((uint16_t)0x0000) -#define TIM_TRGOSource_Enable ((uint16_t)0x0010) -#define TIM_TRGOSource_Update ((uint16_t)0x0020) -#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) -#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) -#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) -#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) -#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) -#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ - ((SOURCE) == TIM_TRGOSource_Enable) || \ - ((SOURCE) == TIM_TRGOSource_Update) || \ - ((SOURCE) == TIM_TRGOSource_OC1) || \ - ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC4Ref)) - - -#define TIM_TRGO2Source_Reset ((uint32_t)0x00000000) -#define TIM_TRGO2Source_Enable ((uint32_t)0x00100000) -#define TIM_TRGO2Source_Update ((uint32_t)0x00200000) -#define TIM_TRGO2Source_OC1 ((uint32_t)0x00300000) -#define TIM_TRGO2Source_OC1Ref ((uint32_t)0x00400000) -#define TIM_TRGO2Source_OC2Ref ((uint32_t)0x00500000) -#define TIM_TRGO2Source_OC3Ref ((uint32_t)0x00600000) -#define TIM_TRGO2Source_OC4Ref ((uint32_t)0x00700000) -#define TIM_TRGO2Source_OC5Ref ((uint32_t)0x00800000) -#define TIM_TRGO2Source_OC6Ref ((uint32_t)0x00900000) -#define TIM_TRGO2Source_OC4Ref_RisingFalling ((uint32_t)0x00A00000) -#define TIM_TRGO2Source_OC6Ref_RisingFalling ((uint32_t)0x00B00000) -#define TIM_TRGO2Source_OC4RefRising_OC6RefRising ((uint32_t)0x00C00000) -#define TIM_TRGO2Source_OC4RefRising_OC6RefFalling ((uint32_t)0x00D00000) -#define TIM_TRGO2Source_OC5RefRising_OC6RefRising ((uint32_t)0x00E00000) -#define TIM_TRGO2Source_OC5RefRising_OC6RefFalling ((uint32_t)0x00F00000) -#define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2Source_Reset) || \ - ((SOURCE) == TIM_TRGO2Source_Enable) || \ - ((SOURCE) == TIM_TRGO2Source_Update) || \ - ((SOURCE) == TIM_TRGO2Source_OC1) || \ - ((SOURCE) == TIM_TRGO2Source_OC1Ref) || \ - ((SOURCE) == TIM_TRGO2Source_OC2Ref) || \ - ((SOURCE) == TIM_TRGO2Source_OC3Ref) || \ - ((SOURCE) == TIM_TRGO2Source_OC4Ref) || \ - ((SOURCE) == TIM_TRGO2Source_OC5Ref) || \ - ((SOURCE) == TIM_TRGO2Source_OC6Ref) || \ - ((SOURCE) == TIM_TRGO2Source_OC4Ref_RisingFalling) || \ - ((SOURCE) == TIM_TRGO2Source_OC6Ref_RisingFalling) || \ - ((SOURCE) == TIM_TRGO2Source_OC4RefRising_OC6RefRising) || \ - ((SOURCE) == TIM_TRGO2Source_OC4RefRising_OC6RefFalling) || \ - ((SOURCE) == TIM_TRGO2Source_OC5RefRising_OC6RefRising) || \ - ((SOURCE) == TIM_TRGO2Source_OC5RefRising_OC6RefFalling)) -/** - * @} - */ - -/** @defgroup TIM_Slave_Mode - * @{ - */ - -#define TIM_SlaveMode_Reset ((uint32_t)0x00004) -#define TIM_SlaveMode_Gated ((uint32_t)0x00005) -#define TIM_SlaveMode_Trigger ((uint32_t)0x00006) -#define TIM_SlaveMode_External1 ((uint32_t)0x00007) -#define TIM_SlaveMode_Combined_ResetTrigger ((uint32_t)0x10000) -#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ - ((MODE) == TIM_SlaveMode_Gated) || \ - ((MODE) == TIM_SlaveMode_Trigger) || \ - ((MODE) == TIM_SlaveMode_External1) || \ - ((MODE) == TIM_SlaveMode_Combined_ResetTrigger)) -/** - * @} - */ - -/** @defgroup TIM_Master_Slave_Mode - * @{ - */ - -#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) -#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) -#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ - ((STATE) == TIM_MasterSlaveMode_Disable)) -/** - * @} - */ -/** @defgroup TIM_Remap - * @{ - */ -#define TIM16_GPIO ((uint16_t)0x0000) -#define TIM16_RTC_CLK ((uint16_t)0x0001) -#define TIM16_HSEDiv32 ((uint16_t)0x0002) -#define TIM16_MCO ((uint16_t)0x0003) - -#define TIM1_ADC1_AWDG1 ((uint16_t)0x0001) -#define TIM1_ADC1_AWDG2 ((uint16_t)0x0002) -#define TIM1_ADC1_AWDG3 ((uint16_t)0x0003) -#define TIM1_ADC4_AWDG1 ((uint16_t)0x0004) -#define TIM1_ADC4_AWDG2 ((uint16_t)0x0008) -#define TIM1_ADC4_AWDG3 ((uint16_t)0x000C) - -#define TIM8_ADC2_AWDG1 ((uint16_t)0x0001) -#define TIM8_ADC2_AWDG2 ((uint16_t)0x0002) -#define TIM8_ADC2_AWDG3 ((uint16_t)0x0003) -#define TIM8_ADC3_AWDG1 ((uint16_t)0x0004) -#define TIM8_ADC3_AWDG2 ((uint16_t)0x0008) -#define TIM8_ADC3_AWDG3 ((uint16_t)0x000C) - -#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM16_GPIO)|| \ - ((TIM_REMAP) == TIM16_RTC_CLK) || \ - ((TIM_REMAP) == TIM16_HSEDiv32) || \ - ((TIM_REMAP) == TIM16_MCO) ||\ - ((TIM_REMAP) == TIM1_ADC1_AWDG1) ||\ - ((TIM_REMAP) == TIM1_ADC1_AWDG2) ||\ - ((TIM_REMAP) == TIM1_ADC1_AWDG3) ||\ - ((TIM_REMAP) == TIM1_ADC4_AWDG1) ||\ - ((TIM_REMAP) == TIM1_ADC4_AWDG2) ||\ - ((TIM_REMAP) == TIM1_ADC4_AWDG3) ||\ - ((TIM_REMAP) == TIM8_ADC2_AWDG1) ||\ - ((TIM_REMAP) == TIM8_ADC2_AWDG2) ||\ - ((TIM_REMAP) == TIM8_ADC2_AWDG3) ||\ - ((TIM_REMAP) == TIM8_ADC3_AWDG1) ||\ - ((TIM_REMAP) == TIM8_ADC3_AWDG2) ||\ - ((TIM_REMAP) == TIM8_ADC3_AWDG3)) - -/** - * @} - */ -/** @defgroup TIM_Flags - * @{ - */ - -#define TIM_FLAG_Update ((uint32_t)0x00001) -#define TIM_FLAG_CC1 ((uint32_t)0x00002) -#define TIM_FLAG_CC2 ((uint32_t)0x00004) -#define TIM_FLAG_CC3 ((uint32_t)0x00008) -#define TIM_FLAG_CC4 ((uint32_t)0x00010) -#define TIM_FLAG_COM ((uint32_t)0x00020) -#define TIM_FLAG_Trigger ((uint32_t)0x00040) -#define TIM_FLAG_Break ((uint32_t)0x00080) -#define TIM_FLAG_Break2 ((uint32_t)0x00100) -#define TIM_FLAG_CC1OF ((uint32_t)0x00200) -#define TIM_FLAG_CC2OF ((uint32_t)0x00400) -#define TIM_FLAG_CC3OF ((uint32_t)0x00800) -#define TIM_FLAG_CC4OF ((uint32_t)0x01000) -#define TIM_FLAG_CC5 ((uint32_t)0x10000) -#define TIM_FLAG_CC6 ((uint32_t)0x20000) -#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ - ((FLAG) == TIM_FLAG_CC1) || \ - ((FLAG) == TIM_FLAG_CC2) || \ - ((FLAG) == TIM_FLAG_CC3) || \ - ((FLAG) == TIM_FLAG_CC4) || \ - ((FLAG) == TIM_FLAG_COM) || \ - ((FLAG) == TIM_FLAG_Trigger) || \ - ((FLAG) == TIM_FLAG_Break) || \ - ((FLAG) == TIM_FLAG_Break2) || \ - ((FLAG) == TIM_FLAG_CC1OF) || \ - ((FLAG) == TIM_FLAG_CC2OF) || \ - ((FLAG) == TIM_FLAG_CC3OF) || \ - ((FLAG) == TIM_FLAG_CC4OF) ||\ - ((FLAG) == TIM_FLAG_CC5) ||\ - ((FLAG) == TIM_FLAG_CC6)) - -#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint32_t)0xE000) == 0x0000) && ((TIM_FLAG) != 0x0000)) -/** - * @} - */ - -/** @defgroup TIM_OCReferenceClear - * @{ - */ -#define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008) -#define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000) -#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \ - ((SOURCE) == TIM_OCReferenceClear_OCREFCLR)) - -/** @defgroup TIM_Input_Capture_Filer_Value - * @{ - */ - -#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Filter - * @{ - */ - -#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_Legacy - * @{ - */ - -#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer -#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers -#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers -#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers -#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers -#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers -#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers -#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers -#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers -#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers -#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers -#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers -#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers -#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers -#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers -#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers -#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers -#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* TimeBase management ********************************************************/ -void TIM_DeInit(TIM_TypeDef* TIMx); -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); -void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter); -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload); -uint32_t TIM_GetCounter(TIM_TypeDef* TIMx); -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); -void TIM_UIFRemap(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Output Compare management **************************************************/ -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC5Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC6Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_SelectGC5C1(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectGC5C2(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectGC5C3(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint32_t TIM_OCMode); -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1); -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2); -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3); -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4); -void TIM_SetCompare5(TIM_TypeDef* TIMx, uint32_t Compare5); -void TIM_SetCompare6(TIM_TypeDef* TIMx, uint32_t Compare6); -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC5Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC6Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC5PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC6PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC5Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC6Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear); -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC5PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC6PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); - -/* Input Capture management ***************************************************/ -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx); -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); - -/* Advanced-control timers (TIM1 and TIM8) specific features ******************/ -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); -void TIM_Break1Config(TIM_TypeDef* TIMx, uint32_t TIM_Break1Polarity, uint8_t TIM_Break1Filter); -void TIM_Break2Config(TIM_TypeDef* TIMx, uint32_t TIM_Break2Polarity, uint8_t TIM_Break2Filter); -void TIM_Break1Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_Break2Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Interrupts, DMA and flags management ***************************************/ -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint32_t TIM_FLAG); -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Clocks management **********************************************************/ -void TIM_InternalClockConfig(TIM_TypeDef* TIMx); -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter); -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); - -/* Synchronization management *************************************************/ -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); -void TIM_SelectOutputTrigger2(TIM_TypeDef* TIMx, uint32_t TIM_TRGO2Source); -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_SlaveMode); -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); - -/* Specific interface management **********************************************/ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Specific remapping management **********************************************/ -void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F30x_TIM_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_usart.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2094 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_usart.c - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Universal synchronous asynchronous receiver - * transmitter (USART): - * + Initialization and Configuration - * + STOP Mode - * + AutoBaudRate - * + Data transfers - * + Multi-Processor Communication - * + LIN mode - * + Half-duplex mode - * + Smartcard mode - * + IrDA mode - * + RS485 mode - * + DMA transfers management - * + Interrupts and flags management - * - * @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE) - function for USART1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) - function for USART2, USART3, UART4 and UART5. - (#) According to the USART mode, enable the GPIO clocks using - RCC_AHBPeriphClockCmd() function. (The I/O can be TX, RX, CTS, - or and SCLK). - (#) Peripheral's alternate function: - (++) Connect the pin to the desired peripherals' Alternate - Function (AF) using GPIO_PinAFConfig() function. - (++) Configure the desired pin in alternate function by: - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF. - (++) Select the type, pull-up/pull-down and output speed via - GPIO_PuPd, GPIO_OType and GPIO_Speed members. - (++) Call GPIO_Init() function. - (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware - flow control and Mode(Receiver/Transmitter) using the SPI_Init() - function. - (#) For synchronous mode, enable the clock and program the polarity, - phase and last bit using the USART_ClockInit() function. - (#) Enable the USART using the USART_Cmd() function. - (#) Enable the NVIC and the corresponding interrupt using the function - USART_ITConfig() if you need to use interrupt mode. - (#) When using the DMA mode: - (++) Configure the DMA using DMA_Init() function. - (++) Activate the needed channel Request using USART_DMACmd() function. - (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode. - [..] - Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections - for more details. - - @endverbatim - - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x_usart.h" -#include "stm32f30x_rcc.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @defgroup USART - * @brief USART driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/*!< USART CR1 register clear Mask ((~(uint32_t)0xFFFFE6F3)) */ -#define CR1_CLEAR_MASK ((uint32_t)(USART_CR1_M | USART_CR1_PCE | \ - USART_CR1_PS | USART_CR1_TE | \ - USART_CR1_RE)) - -/*!< USART CR2 register clock bits clear Mask ((~(uint32_t)0xFFFFF0FF)) */ -#define CR2_CLOCK_CLEAR_MASK ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \ - USART_CR2_CPHA | USART_CR2_LBCL)) - -/*!< USART CR3 register clear Mask ((~(uint32_t)0xFFFFFCFF)) */ -#define CR3_CLEAR_MASK ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) - -/*!< USART Interrupts mask */ -#define IT_MASK ((uint32_t)0x000000FF) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup USART_Private_Functions - * @{ - */ - -/** @defgroup USART_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USART - in asynchronous and in synchronous modes. - (+) For the asynchronous mode only these parameters can be configured: - (++) Baud Rate. - (++) Word Length. - (++) Stop Bit. - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible USART frame formats are as listed in the following table: - [..] - +-------------------------------------------------------------+ - | M bit | PCE bit | USART frame | - |---------------------|---------------------------------------| - | 0 | 0 | | SB | 8 bit data | STB | | - |---------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|-----------|---------------------------------------| - | 1 | 0 | | SB | 9 bit data | STB | | - |---------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ - [..] - (++) Hardware flow control. - (++) Receiver/transmitter modes. - [..] The USART_Init() function follows the USART asynchronous configuration - procedure(details for the procedure are available in reference manual. - (+) For the synchronous mode in addition to the asynchronous mode parameters - these parameters should be also configured: - (++) USART Clock Enabled. - (++) USART polarity. - (++) USART phase. - (++) USART LastBit. - [..] These parameters can be configured using the USART_ClockInit() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the USARTx peripheral registers to their default reset values. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @retval None - */ -void USART_DeInit(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - if (USARTx == USART1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); - } - else if (USARTx == USART2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); - } - else if (USARTx == USART3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); - } - else if (USARTx == UART4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); - } - else - { - if (USARTx == UART5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); - } - } -} - -/** - * @brief Initializes the USARTx peripheral according to the specified - * parameters in the USART_InitStruct . - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure - * that contains the configuration information for the specified USART peripheral. - * @retval None - */ -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) -{ - uint32_t divider = 0, apbclock = 0, tmpreg = 0; - RCC_ClocksTypeDef RCC_ClocksStatus; - - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); - assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); - assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); - assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); - assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); - assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); - - /* Disable USART */ - USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE); - - /*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - /* Clear STOP[13:12] bits */ - tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP); - - /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ - /* Set STOP[13:12] bits according to USART_StopBits value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; - - /* Write to USART CR2 */ - USARTx->CR2 = tmpreg; - - /*---------------------------- USART CR1 Configuration -----------------------*/ - tmpreg = USARTx->CR1; - /* Clear M, PCE, PS, TE and RE bits */ - tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK); - - /* Configure the USART Word Length, Parity and mode ----------------------- */ - /* Set the M bits according to USART_WordLength value */ - /* Set PCE and PS bits according to USART_Parity value */ - /* Set TE and RE bits according to USART_Mode value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | - USART_InitStruct->USART_Mode; - - /* Write to USART CR1 */ - USARTx->CR1 = tmpreg; - - /*---------------------------- USART CR3 Configuration -----------------------*/ - tmpreg = USARTx->CR3; - /* Clear CTSE and RTSE bits */ - tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK); - - /* Configure the USART HFC -------------------------------------------------*/ - /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ - tmpreg |= USART_InitStruct->USART_HardwareFlowControl; - - /* Write to USART CR3 */ - USARTx->CR3 = tmpreg; - - /*---------------------------- USART BRR Configuration -----------------------*/ - /* Configure the USART Baud Rate -------------------------------------------*/ - RCC_GetClocksFreq(&RCC_ClocksStatus); - - if (USARTx == USART1) - { - apbclock = RCC_ClocksStatus.USART1CLK_Frequency; - } - else if (USARTx == USART2) - { - apbclock = RCC_ClocksStatus.USART2CLK_Frequency; - } - else if (USARTx == USART3) - { - apbclock = RCC_ClocksStatus.USART3CLK_Frequency; - } - else if (USARTx == UART4) - { - apbclock = RCC_ClocksStatus.UART4CLK_Frequency; - } - else - { - apbclock = RCC_ClocksStatus.UART5CLK_Frequency; - } - - /* Determine the integer part */ - if ((USARTx->CR1 & USART_CR1_OVER8) != 0) - { - /* (divider * 10) computing in case Oversampling mode is 8 Samples */ - divider = (uint32_t)((2 * apbclock) / (USART_InitStruct->USART_BaudRate)); - tmpreg = (uint32_t)((2 * apbclock) % (USART_InitStruct->USART_BaudRate)); - } - else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ - { - /* (divider * 10) computing in case Oversampling mode is 16 Samples */ - divider = (uint32_t)((apbclock) / (USART_InitStruct->USART_BaudRate)); - tmpreg = (uint32_t)((apbclock) % (USART_InitStruct->USART_BaudRate)); - } - - /* round the divider : if fractional part i greater than 0.5 increment divider */ - if (tmpreg >= (USART_InitStruct->USART_BaudRate) / 2) - { - divider++; - } - - /* Implement the divider in case Oversampling mode is 8 Samples */ - if ((USARTx->CR1 & USART_CR1_OVER8) != 0) - { - /* get the LSB of divider and shift it to the right by 1 bit */ - tmpreg = (divider & (uint16_t)0x000F) >> 1; - - /* update the divider value */ - divider = (divider & (uint16_t)0xFFF0) | tmpreg; - } - - /* Write to USART BRR */ - USARTx->BRR = (uint16_t)divider; -} - -/** - * @brief Fills each USART_InitStruct member with its default value. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure - * which will be initialized. - * @retval None - */ -void USART_StructInit(USART_InitTypeDef* USART_InitStruct) -{ - /* USART_InitStruct members default value */ - USART_InitStruct->USART_BaudRate = 9600; - USART_InitStruct->USART_WordLength = USART_WordLength_8b; - USART_InitStruct->USART_StopBits = USART_StopBits_1; - USART_InitStruct->USART_Parity = USART_Parity_No ; - USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; -} - -/** - * @brief Initializes the USARTx peripheral Clock according to the - * specified parameters in the USART_ClockInitStruct. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef - * structure that contains the configuration information for the specified - * USART peripheral. - * @retval None - */ -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); - assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); - assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); - assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); -/*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - /* Clear CLKEN, CPOL, CPHA, LBCL and SSM bits */ - tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK); - /* Configure the USART Clock, CPOL, CPHA, LastBit and SSM ------------*/ - /* Set CLKEN bit according to USART_Clock value */ - /* Set CPOL bit according to USART_CPOL value */ - /* Set CPHA bit according to USART_CPHA value */ - /* Set LBCL bit according to USART_LastBit value */ - tmpreg |= (uint32_t)(USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | - USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit); - /* Write to USART CR2 */ - USARTx->CR2 = tmpreg; -} - -/** - * @brief Fills each USART_ClockInitStruct member with its default value. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef - * structure which will be initialized. - * @retval None - */ -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - /* USART_ClockInitStruct members default value */ - USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; - USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; - USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; - USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; -} - -/** - * @brief Enables or disables the specified USART peripheral. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param NewState: new state of the USARTx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected USART by setting the UE bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_UE; - } - else - { - /* Disable the selected USART by clearing the UE bit in the CR1 register */ - USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE); - } -} - -/** - * @brief Enables or disables the USART's transmitter or receiver. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param USART_Direction: specifies the USART direction. - * This parameter can be any combination of the following values: - * @arg USART_Mode_Tx: USART Transmitter - * @arg USART_Mode_Rx: USART Receiver - * @param NewState: new state of the USART transfer direction. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_MODE(USART_DirectionMode)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the USART's transfer interface by setting the TE and/or RE bits - in the USART CR1 register */ - USARTx->CR1 |= USART_DirectionMode; - } - else - { - /* Disable the USART's transfer interface by clearing the TE and/or RE bits - in the USART CR3 register */ - USARTx->CR1 &= (uint32_t)~USART_DirectionMode; - } -} - -/** - * @brief Enables or disables the USART's 8x oversampling mode. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param NewState: new state of the USART 8x oversampling mode. - * This parameter can be: ENABLE or DISABLE. - * @note - * This function has to be called before calling USART_Init() - * function in order to have correct baudrate Divider value. - * @retval None - */ -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_OVER8; - } - else - { - /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ - USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_OVER8); - } -} - -/** - * @brief Enables or disables the USART's one bit sampling method. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param NewState: new state of the USART one bit sampling method. - * This parameter can be: ENABLE or DISABLE. - * @note - * This function has to be called before calling USART_Cmd() function. - * @retval None - */ -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the one bit method by setting the ONEBIT bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_ONEBIT; - } - else - { - /* Disable the one bit method by clearing the ONEBIT bit in the CR3 register */ - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT); - } -} - -/** - * @brief Enables or disables the USART's most significant bit first - * transmitted/received following the start bit. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param NewState: new state of the USART most significant bit first - * transmitted/received following the start bit. - * This parameter can be: ENABLE or DISABLE. - * @note - * This function has to be called before calling USART_Cmd() function. - * @retval None - */ -void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the most significant bit first transmitted/received following the - start bit by setting the MSBFIRST bit in the CR2 register */ - USARTx->CR2 |= USART_CR2_MSBFIRST; - } - else - { - /* Disable the most significant bit first transmitted/received following the - start bit by clearing the MSBFIRST bit in the CR2 register */ - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_MSBFIRST); - } -} - -/** - * @brief Enables or disables the binary data inversion. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param NewState: new defined levels for the USART data. - * This parameter can be: ENABLE or DISABLE. - * @arg ENABLE: Logical data from the data register are send/received in negative - * logic. (1=L, 0=H). The parity bit is also inverted. - * @arg DISABLE: Logical data from the data register are send/received in positive - * logic. (1=H, 0=L) - * @note - * This function has to be called before calling USART_Cmd() function. - * @retval None - */ -void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the binary data inversion feature by setting the DATAINV bit in - the CR2 register */ - USARTx->CR2 |= USART_CR2_DATAINV; - } - else - { - /* Disable the binary data inversion feature by clearing the DATAINV bit in - the CR2 register */ - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_DATAINV); - } -} - -/** - * @brief Enables or disables the Pin(s) active level inversion. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param USART_InvPin: specifies the USART pin(s) to invert. - * This parameter can be any combination of the following values: - * @arg USART_InvPin_Tx: USART Tx pin active level inversion. - * @arg USART_InvPin_Rx: USART Rx pin active level inversion. - * @param NewState: new active level status for the USART pin(s). - * This parameter can be: ENABLE or DISABLE. - * - ENABLE: pin(s) signal values are inverted (Vdd =0, Gnd =1). - * - DISABLE: pin(s) signal works using the standard logic levels (Vdd =1, Gnd =0). - * @note - * This function has to be called before calling USART_Cmd() function. - * @retval None - */ -void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_INVERSTION_PIN(USART_InvPin)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the active level inversion for selected pins by setting the TXINV - and/or RXINV bits in the USART CR2 register */ - USARTx->CR2 |= USART_InvPin; - } - else - { - /* Disable the active level inversion for selected requests by clearing the - TXINV and/or RXINV bits in the USART CR2 register */ - USARTx->CR2 &= (uint32_t)~USART_InvPin; - } -} - -/** - * @brief Enables or disables the swap Tx/Rx pins. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param NewState: new state of the USARTx TX/RX pins pinout. - * This parameter can be: ENABLE or DISABLE. - * @arg ENABLE: The TX and RX pins functions are swapped. - * @arg DISABLE: TX/RX pins are used as defined in standard pinout - * @note - * This function has to be called before calling USART_Cmd() function. - * @retval None - */ -void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the SWAP feature by setting the SWAP bit in the CR2 register */ - USARTx->CR2 |= USART_CR2_SWAP; - } - else - { - /* Disable the SWAP feature by clearing the SWAP bit in the CR2 register */ - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_SWAP); - } -} - -/** - * @brief Enables or disables the receiver Time Out feature. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param NewState: new state of the USARTx receiver Time Out. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the receiver time out feature by setting the RTOEN bit in the CR2 - register */ - USARTx->CR2 |= USART_CR2_RTOEN; - } - else - { - /* Disable the receiver time out feature by clearing the RTOEN bit in the CR2 - register */ - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_RTOEN); - } -} - -/** - * @brief Sets the receiver Time Out value. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param USART_ReceiverTimeOut: specifies the Receiver Time Out value. - * @retval None - */ -void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_TIMEOUT(USART_ReceiverTimeOut)); - - /* Clear the receiver Time Out value by clearing the RTO[23:0] bits in the RTOR - register */ - USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_RTO); - /* Set the receiver Time Out value by setting the RTO[23:0] bits in the RTOR - register */ - USARTx->RTOR |= USART_ReceiverTimeOut; -} - -/** - * @brief Sets the system clock prescaler. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param USART_Prescaler: specifies the prescaler clock. - * @note - * This function has to be called before calling USART_Cmd() function. - * @retval None - */ -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Clear the USART prescaler */ - USARTx->GTPR &= USART_GTPR_GT; - /* Set the USART prescaler */ - USARTx->GTPR |= USART_Prescaler; -} - -/** - * @} - */ - - -/** @defgroup USART_Group2 STOP Mode functions - * @brief STOP Mode functions - * -@verbatim - =============================================================================== - ##### STOP Mode functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to manage - WakeUp from STOP mode. - - [..] The USART is able to WakeUp from Stop Mode if USART clock is set to HSI - or LSI. - - [..] The WakeUp source is configured by calling USART_StopModeWakeUpSourceConfig() - function. - - [..] After configuring the source of WakeUp and before entering in Stop Mode - USART_STOPModeCmd() function should be called to allow USART WakeUp. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified USART peripheral in STOP Mode. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param NewState: new state of the USARTx peripheral state in stop mode. - * This parameter can be: ENABLE or DISABLE. - * @note - * This function has to be called when USART clock is set to HSI or LSE. - * @retval None - */ -void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected USART in STOP mode by setting the UESM bit in the CR1 - register */ - USARTx->CR1 |= USART_CR1_UESM; - } - else - { - /* Disable the selected USART in STOP mode by clearing the UE bit in the CR1 - register */ - USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UESM); - } -} - -/** - * @brief Selects the USART WakeUp method form stop mode. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param USART_WakeUp: specifies the selected USART wakeup method. - * This parameter can be one of the following values: - * @arg USART_WakeUpSource_AddressMatch: WUF active on address match. - * @arg USART_WakeUpSource_StartBit: WUF active on Start bit detection. - * @arg USART_WakeUpSource_RXNE: WUF active on RXNE. - * @note - * This function has to be called before calling USART_Cmd() function. - * @retval None - */ -void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_STOPMODE_WAKEUPSOURCE(USART_WakeUpSource)); - - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_WUS); - USARTx->CR3 |= USART_WakeUpSource; -} - -/** - * @} - */ - - -/** @defgroup USART_Group3 AutoBaudRate functions - * @brief AutoBaudRate functions - * -@verbatim - =============================================================================== - ##### AutoBaudRate functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to manage - the AutoBaudRate detections. - - [..] Before Enabling AutoBaudRate detection using USART_AutoBaudRateCmd () - The character patterns used to calculate baudrate must be chosen by calling - USART_AutoBaudRateConfig() function. These function take as parameter : - (#)USART_AutoBaudRate_StartBit : any character starting with a bit 1. - (#)USART_AutoBaudRate_FallingEdge : any character starting with a 10xx bit pattern. - - [..] At any later time, another request for AutoBaudRate detection can be performed - using USART_RequestCmd() function. - - [..] The AutoBaudRate detection is monitored by the status of ABRF flag which indicate - that the AutoBaudRate detection is completed. In addition to ABRF flag, the ABRE flag - indicate that this procedure is completed without success. USART_GetFlagStatus () - function should be used to monitor the status of these flags. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the Auto Baud Rate. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param NewState: new state of the USARTx auto baud rate. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the auto baud rate feature by setting the ABREN bit in the CR2 - register */ - USARTx->CR2 |= USART_CR2_ABREN; - } - else - { - /* Disable the auto baud rate feature by clearing the ABREN bit in the CR2 - register */ - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABREN); - } -} - -/** - * @brief Selects the USART auto baud rate method. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param USART_AutoBaudRate: specifies the selected USART auto baud rate method. - * This parameter can be one of the following values: - * @arg USART_AutoBaudRate_StartBit: Start Bit duration measurement. - * @arg USART_AutoBaudRate_FallingEdge: Falling edge to falling edge measurement. - * @arg USART_AutoBaudRate_0x7FFrame: 0x7F frame. - * @arg USART_AutoBaudRate_0x55Frame: 0x55 frame. - * @note - * This function has to be called before calling USART_Cmd() function. - * @retval None - */ -void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_AUTOBAUDRATE_MODE(USART_AutoBaudRate)); - - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABRMODE); - USARTx->CR2 |= USART_AutoBaudRate; -} - -/** - * @} - */ - - -/** @defgroup USART_Group4 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### Data transfers functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to manage - the USART data transfers. - [..] During an USART reception, data shifts in least significant bit first - through the RX pin. When a transmission is taking place, a write instruction to - the USART_TDR register stores the data in the shift register. - [..] The read access of the USART_RDR register can be done using - the USART_ReceiveData() function and returns the RDR value. - Whereas a write access to the USART_TDR can be done using USART_SendData() - function and stores the written data into TDR. - -@endverbatim - * @{ - */ - -/** - * @brief Transmits single data through the USARTx peripheral. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param Data: the data to transmit. - * @retval None - */ -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DATA(Data)); - - /* Transmit Data */ - USARTx->TDR = (Data & (uint16_t)0x01FF); -} - -/** - * @brief Returns the most recent received data by the USARTx peripheral. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @retval The received data. - */ -uint16_t USART_ReceiveData(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Receive Data */ - return (uint16_t)(USARTx->RDR & (uint16_t)0x01FF); -} - -/** - * @} - */ - -/** @defgroup USART_Group5 MultiProcessor Communication functions - * @brief Multi-Processor Communication functions - * -@verbatim - =============================================================================== - ##### Multi-Processor Communication functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USART - multiprocessor communication. - [..] For instance one of the USARTs can be the master, its TX output is - connected to the RX input of the other USART. The others are slaves, - their respective TX outputs are logically ANDed together and connected - to the RX input of the master. USART multiprocessor communication is - possible through the following procedure: - (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity, - Mode transmitter or Mode receiver and hardware flow control values - using the USART_Init() function. - (#) Configures the USART address using the USART_SetAddress() function. - (#) Configures the wake up methode (USART_WakeUp_IdleLine or - USART_WakeUp_AddressMark) using USART_WakeUpConfig() function only - for the slaves. - (#) Enable the USART using the USART_Cmd() function. - (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() - function. - [..] The USART Slave exit from mute mode when receive the wake up condition. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the address of the USART node. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param USART_Address: Indicates the address of the USART node. - * @retval None - */ -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Clear the USART address */ - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADD); - /* Set the USART address node */ - USARTx->CR2 |=((uint32_t)USART_Address << (uint32_t)0x18); -} - -/** - * @brief Enables or disables the USART's mute mode. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param NewState: new state of the USART mute mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the USART mute mode by setting the MME bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_MME; - } - else - { - /* Disable the USART mute mode by clearing the MME bit in the CR1 register */ - USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_MME); - } -} - -/** - * @brief Selects the USART WakeUp method from mute mode. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param USART_WakeUp: specifies the USART wakeup method. - * This parameter can be one of the following values: - * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection - * @arg USART_WakeUp_AddressMark: WakeUp by an address mark - * @retval None - */ -void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_MUTEMODE_WAKEUP(USART_WakeUp)); - - USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_WAKE); - USARTx->CR1 |= USART_WakeUp; -} - -/** - * @brief Configure the the USART Address detection length. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param USART_AddressLength: specifies the USART address length detection. - * This parameter can be one of the following values: - * @arg USART_AddressLength_4b: 4-bit address length detection - * @arg USART_AddressLength_7b: 7-bit address length detection - * @retval None - */ -void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_ADDRESS_DETECTION(USART_AddressLength)); - - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADDM7); - USARTx->CR2 |= USART_AddressLength; -} - -/** - * @} - */ - -/** @defgroup USART_Group6 LIN mode functions - * @brief LIN mode functions - * -@verbatim - =============================================================================== - ##### LIN mode functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USART - LIN Mode communication. - [..] In LIN mode, 8-bit data format with 1 stop bit is required in accordance - with the LIN standard. - [..] Only this LIN Feature is supported by the USART IP: - (+) LIN Master Synchronous Break send capability and LIN slave break - detection capability : 13-bit break generation and 10/11 bit break - detection. - [..] USART LIN Master transmitter communication is possible through the - following procedure: - (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, - Mode transmitter or Mode receiver and hardware flow control values - using the USART_Init() function. - (#) Enable the LIN mode using the USART_LINCmd() function. - (#) Enable the USART using the USART_Cmd() function. - (#) Send the break character using USART_SendBreak() function. - [..] USART LIN Master receiver communication is possible through the - following procedure: - (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, - Mode transmitter or Mode receiver and hardware flow control values - using the USART_Init() function. - (#) Configures the break detection length - using the USART_LINBreakDetectLengthConfig() function. - (#) Enable the LIN mode using the USART_LINCmd() function. - (#) Enable the USART using the USART_Cmd() function. - [..] - (@) In LIN mode, the following bits must be kept cleared: - (+@) CLKEN in the USART_CR2 register. - (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the USART LIN Break detection length. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param USART_LINBreakDetectLength: specifies the LIN break detection length. - * This parameter can be one of the following values: - * @arg USART_LINBreakDetectLength_10b: 10-bit break detection - * @arg USART_LINBreakDetectLength_11b: 11-bit break detection - * @retval None - */ -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); - - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_LBDL); - USARTx->CR2 |= USART_LINBreakDetectLength; -} - -/** - * @brief Enables or disables the USART's LIN mode. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param NewState: new state of the USART LIN mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - USARTx->CR2 |= USART_CR2_LINEN; - } - else - { - /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_LINEN); - } -} - -/** - * @} - */ - -/** @defgroup USART_Group7 Halfduplex mode function - * @brief Half-duplex mode function - * -@verbatim - =============================================================================== - ##### Half-duplex mode function ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USART - Half-duplex communication. - [..] The USART can be configured to follow a single-wire half-duplex protocol - where the TX and RX lines are internally connected. - [..] USART Half duplex communication is possible through the following procedure: - (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter - or Mode receiver and hardware flow control values using the USART_Init() - function. - (#) Configures the USART address using the USART_SetAddress() function. - (#) Enable the half duplex mode using USART_HalfDuplexCmd() function. - (#) Enable the USART using the USART_Cmd() function. - [..] - (@) The RX pin is no longer used. - (@) In Half-duplex mode the following bits must be kept cleared: - (+@) LINEN and CLKEN bits in the USART_CR2 register. - (+@) SCEN and IREN bits in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the USART's Half Duplex communication. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param NewState: new state of the USART Communication. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_HDSEL; - } - else - { - /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_HDSEL); - } -} - -/** - * @} - */ - - -/** @defgroup USART_Group8 Smartcard mode functions - * @brief Smartcard mode functions - * -@verbatim - =============================================================================== - ##### Smartcard mode functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USART - Smartcard communication. - [..] The Smartcard interface is designed to support asynchronous protocol - Smartcards as defined in the ISO 7816-3 standard. The USART can provide - a clock to the smartcard through the SCLK output. In smartcard mode, - SCLK is not associated to the communication but is simply derived from - the internal peripheral input clock through a 5-bit prescaler. - [..] Smartcard communication is possible through the following procedure: - (#) Configures the Smartcard Prsecaler using the USART_SetPrescaler() - function. - (#) Configures the Smartcard Guard Time using the USART_SetGuardTime() - function. - (#) Program the USART clock using the USART_ClockInit() function as following: - (++) USART Clock enabled. - (++) USART CPOL Low. - (++) USART CPHA on first edge. - (++) USART Last Bit Clock Enabled. - (#) Program the Smartcard interface using the USART_Init() function as - following: - (++) Word Length = 9 Bits. - (++) 1.5 Stop Bit. - (++) Even parity. - (++) BaudRate = 12096 baud. - (++) Hardware flow control disabled (RTS and CTS signals). - (++) Tx and Rx enabled - (#) Optionally you can enable the parity error interrupt using - the USART_ITConfig() function. - (#) Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function. - (#) Enable the Smartcard interface using the USART_SmartCardCmd() function. - (#) Enable the USART using the USART_Cmd() function. - [..] - Please refer to the ISO 7816-3 specification for more details. - [..] - (@) It is also possible to choose 0.5 stop bit for receiving but it is - recommended to use 1.5 stop bits for both transmitting and receiving - to avoid switching between the two configurations. - (@) In smartcard mode, the following bits must be kept cleared: - (+@) LINEN bit in the USART_CR2 register. - (+@) HDSEL and IREN bits in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the specified USART guard time. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3. - * @param USART_GuardTime: specifies the guard time. - * @retval None - */ -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - - /* Clear the USART Guard time */ - USARTx->GTPR &= USART_GTPR_PSC; - /* Set the USART guard time */ - USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); -} - -/** - * @brief Enables or disables the USART's Smart Card mode. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3. - * @param NewState: new state of the Smart Card mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the SC mode by setting the SCEN bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_SCEN; - } - else - { - /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_SCEN); - } -} - -/** - * @brief Enables or disables NACK transmission. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3. - * @param NewState: new state of the NACK transmission. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_NACK; - } - else - { - /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_NACK); - } -} - -/** - * @brief Sets the Smart Card number of retries in transmit and receive. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3. - * @param USART_AutoCount: specifies the Smart Card auto retry count. - * @retval None - */ -void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_USART_AUTO_RETRY_COUNTER(USART_AutoCount)); - /* Clear the USART auto retry count */ - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_SCARCNT); - /* Set the USART auto retry count*/ - USARTx->CR3 |= (uint32_t)((uint32_t)USART_AutoCount << 0x11); -} - -/** - * @brief Sets the Smart Card Block length. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3. - * @param USART_BlockLength: specifies the Smart Card block length. - * @retval None - */ -void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - - /* Clear the Smart card block length */ - USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_BLEN); - /* Set the Smart Card block length */ - USARTx->RTOR |= (uint32_t)((uint32_t)USART_BlockLength << 0x18); -} - -/** - * @} - */ - -/** @defgroup USART_Group9 IrDA mode functions - * @brief IrDA mode functions - * -@verbatim - =============================================================================== - ##### IrDA mode functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USART - IrDA communication. - [..] IrDA is a half duplex communication protocol. If the Transmitter is busy, - any data on the IrDA receive line will be ignored by the IrDA decoder - and if the Receiver is busy, data on the TX from the USART to IrDA will - not be encoded by IrDA. While receiving data, transmission should be - avoided as the data to be transmitted could be corrupted. - [..] IrDA communication is possible through the following procedure: - (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, - Transmitter/Receiver modes and hardware flow control values using - the USART_Init() function. - (#) Configures the IrDA pulse width by configuring the prescaler using - the USART_SetPrescaler() function. - (#) Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal - mode using the USART_IrDAConfig() function. - (#) Enable the IrDA using the USART_IrDACmd() function. - (#) Enable the USART using the USART_Cmd() function. - [..] - (@) A pulse of width less than two and greater than one PSC period(s) may or - may not be rejected. - (@) The receiver set up time should be managed by software. The IrDA physical - layer specification specifies a minimum of 10 ms delay between - transmission and reception (IrDA is a half duplex protocol). - (@) In IrDA mode, the following bits must be kept cleared: - (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register. - (+@) SCEN and HDSEL bits in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the USART's IrDA interface. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param USART_IrDAMode: specifies the IrDA mode. - * This parameter can be one of the following values: - * @arg USART_IrDAMode_LowPower - * @arg USART_IrDAMode_Normal - * @retval None - */ -void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); - - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_IRLP); - USARTx->CR3 |= USART_IrDAMode; -} - -/** - * @brief Enables or disables the USART's IrDA interface. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param NewState: new state of the IrDA mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_IREN; - } - else - { - /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_IREN); - } -} -/** - * @} - */ - -/** @defgroup USART_Group10 RS485 mode function - * @brief RS485 mode function - * -@verbatim - =============================================================================== - ##### RS485 mode functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USART - RS485 flow control. - [..] RS485 flow control (Driver enable feature) handling is possible through - the following procedure: - (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, - Transmitter/Receiver modes and hardware flow control values using - the USART_Init() function. - (#) Enable the Driver Enable using the USART_DECmd() function. - (#) Configures the Driver Enable polarity using the USART_DEPolarityConfig() - function. - (#) Configures the Driver Enable assertion time using USART_SetDEAssertionTime() - function and deassertion time using the USART_SetDEDeassertionTime() - function. - (#) Enable the USART using the USART_Cmd() function. - [..] - (@) The assertion and dessertion times are expressed in sample time units (1/8 or - 1/16 bit time, depending on the oversampling rate). - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the USART's DE functionality. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param NewState: new state of the driver enable mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the DE functionality by setting the DEM bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_DEM; - } - else - { - /* Disable the DE functionality by clearing the DEM bit in the CR3 register */ - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEM); - } -} - -/** - * @brief Configures the USART's DE polarity - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param USART_DEPolarity: specifies the DE polarity. - * This parameter can be one of the following values: - * @arg USART_DEPolarity_Low - * @arg USART_DEPolarity_High - * @retval None - */ -void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DE_POLARITY(USART_DEPolarity)); - - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEP); - USARTx->CR3 |= USART_DEPolarity; -} - -/** - * @brief Sets the specified RS485 DE assertion time - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param USART_AssertionTime: specifies the time between the activation of the DE - * signal and the beginning of the start bit - * @retval None - */ -void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEAssertionTime)); - - /* Clear the DE assertion time */ - USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEAT); - /* Set the new value for the DE assertion time */ - USARTx->CR1 |=((uint32_t)USART_DEAssertionTime << (uint32_t)0x15); -} - -/** - * @brief Sets the specified RS485 DE deassertion time - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param USART_DeassertionTime: specifies the time between the middle of the last - * stop bit in a transmitted message and the de-activation of the DE signal - * @retval None - */ -void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEDeassertionTime)); - - /* Clear the DE deassertion time */ - USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEDT); - /* Set the new value for the DE deassertion time */ - USARTx->CR1 |=((uint32_t)USART_DEDeassertionTime << (uint32_t)0x10); -} - -/** - * @} - */ - -/** @defgroup USART_Group11 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - ##### DMA transfers management functions ##### - =============================================================================== - [..] This section provides two functions that can be used only in DMA mode. - [..] In DMA Mode, the USART communication can be managed by 2 DMA Channel - requests: - (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request. - (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request. - [..] In this Mode it is advised to use the following function: - (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, - FunctionalState NewState). -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the USART's DMA interface. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4. - * @param USART_DMAReq: specifies the DMA request. - * This parameter can be any combination of the following values: - * @arg USART_DMAReq_Tx: USART DMA transmit request - * @arg USART_DMAReq_Rx: USART DMA receive request - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_1234_PERIPH(USARTx)); - assert_param(IS_USART_DMAREQ(USART_DMAReq)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA transfer for selected requests by setting the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 |= USART_DMAReq; - } - else - { - /* Disable the DMA transfer for selected requests by clearing the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 &= (uint32_t)~USART_DMAReq; - } -} - -/** - * @brief Enables or disables the USART's DMA interface when reception error occurs. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4. - * @param USART_DMAOnError: specifies the DMA status in case of reception error. - * This parameter can be any combination of the following values: - * @arg USART_DMAOnError_Enable: DMA receive request enabled when the USART DMA - * reception error is asserted. - * @arg USART_DMAOnError_Disable: DMA receive request disabled when the USART DMA - * reception error is asserted. - * @retval None - */ -void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError) -{ - /* Check the parameters */ - assert_param(IS_USART_1234_PERIPH(USARTx)); - assert_param(IS_USART_DMAONERROR(USART_DMAOnError)); - - /* Clear the DMA Reception error detection bit */ - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DDRE); - /* Set the new value for the DMA Reception error detection bit */ - USARTx->CR3 |= USART_DMAOnError; -} - -/** - * @} - */ - -/** @defgroup USART_Group12 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to configure the - USART Interrupts sources, Requests and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to - manage the communication: Polling mode, Interrupt mode. - - *** Polling Mode *** - ==================== - [..] In Polling Mode, the SPI communication can be managed by these flags: - (#) USART_FLAG_REACK: to indicate the status of the Receive Enable - acknowledge flag - (#) USART_FLAG_TEACK: to indicate the status of the Transmit Enable - acknowledge flag. - (#) USART_FLAG_WUF: to indicate the status of the Wake up flag. - (#) USART_FLAG_RWU: to indicate the status of the Receive Wake up flag. - (#) USART_FLAG_SBK: to indicate the status of the Send Break flag. - (#) USART_FLAG_CMF: to indicate the status of the Character match flag. - (#) USART_FLAG_BUSY: to indicate the status of the Busy flag. - (#) USART_FLAG_ABRF: to indicate the status of the Auto baud rate flag. - (#) USART_FLAG_ABRE: to indicate the status of the Auto baud rate error flag. - (#) USART_FLAG_EOBF: to indicate the status of the End of block flag. - (#) USART_FLAG_RTOF: to indicate the status of the Receive time out flag. - (#) USART_FLAG_nCTSS: to indicate the status of the Inverted nCTS input - bit status. - (#) USART_FLAG_TXE: to indicate the status of the transmit buffer register. - (#) USART_FLAG_RXNE: to indicate the status of the receive buffer register. - (#) USART_FLAG_TC: to indicate the status of the transmit operation. - (#) USART_FLAG_IDLE: to indicate the status of the Idle Line. - (#) USART_FLAG_CTS: to indicate the status of the nCTS input. - (#) USART_FLAG_LBD: to indicate the status of the LIN break detection. - (#) USART_FLAG_NE: to indicate if a noise error occur. - (#) USART_FLAG_FE: to indicate if a frame error occur. - (#) USART_FLAG_PE: to indicate if a parity error occur. - (#) USART_FLAG_ORE: to indicate if an Overrun error occur. - [..] In this Mode it is advised to use the following functions: - (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG). - (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG). - - *** Interrupt Mode *** - ====================== - [..] In Interrupt Mode, the USART communication can be managed by 8 interrupt - sources and 10 pending bits: - (+) Pending Bits: - (##) USART_IT_WU: to indicate the status of the Wake up interrupt. - (##) USART_IT_CM: to indicate the status of Character match interrupt. - (##) USART_IT_EOB: to indicate the status of End of block interrupt. - (##) USART_IT_RTO: to indicate the status of Receive time out interrupt. - (##) USART_IT_CTS: to indicate the status of CTS change interrupt. - (##) USART_IT_LBD: to indicate the status of LIN Break detection interrupt. - (##) USART_IT_TC: to indicate the status of Transmission complete interrupt. - (##) USART_IT_IDLE: to indicate the status of IDLE line detected interrupt. - (##) USART_IT_ORE: to indicate the status of OverRun Error interrupt. - (##) USART_IT_NE: to indicate the status of Noise Error interrupt. - (##) USART_IT_FE: to indicate the status of Framing Error interrupt. - (##) USART_IT_PE: to indicate the status of Parity Error interrupt. - - (+) Interrupt Source: - (##) USART_IT_WU: specifies the interrupt source for Wake up interrupt. - (##) USART_IT_CM: specifies the interrupt source for Character match - interrupt. - (##) USART_IT_EOB: specifies the interrupt source for End of block - interrupt. - (##) USART_IT_RTO: specifies the interrupt source for Receive time-out - interrupt. - (##) USART_IT_CTS: specifies the interrupt source for CTS change interrupt. - (##) USART_IT_LBD: specifies the interrupt source for LIN Break - detection interrupt. - (##) USART_IT_TXE: specifies the interrupt source for Tansmit Data - Register empty interrupt. - (##) USART_IT_TC: specifies the interrupt source for Transmission - complete interrupt. - (##) USART_IT_RXNE: specifies the interrupt source for Receive Data - register not empty interrupt. - (##) USART_IT_IDLE: specifies the interrupt source for Idle line - detection interrupt. - (##) USART_IT_PE: specifies the interrupt source for Parity Error interrupt. - (##) USART_IT_ERR: specifies the interrupt source for Error interrupt - (Frame error, noise error, overrun error) - -@@- Some parameters are coded in order to use them as interrupt - source or as pending bits. - [..] In this Mode it is advised to use the following functions: - (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState). - (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT). - (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT). - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified USART interrupts. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg USART_IT_WU: Wake up interrupt. - * @arg USART_IT_CM: Character match interrupt. - * @arg USART_IT_EOB: End of block interrupt. - * @arg USART_IT_RTO: Receive time out interrupt. - * @arg USART_IT_CTS: CTS change interrupt. - * @arg USART_IT_LBD: LIN Break detection interrupt. - * @arg USART_IT_TXE: Tansmit Data Register empty interrupt. - * @arg USART_IT_TC: Transmission complete interrupt. - * @arg USART_IT_RXNE: Receive Data register not empty interrupt. - * @arg USART_IT_IDLE: Idle line detection interrupt. - * @arg USART_IT_PE: Parity Error interrupt. - * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @param NewState: new state of the specified USARTx interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState) -{ - uint32_t usartreg = 0, itpos = 0, itmask = 0; - uint32_t usartxbase = 0; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CONFIG_IT(USART_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - usartxbase = (uint32_t)USARTx; - - /* Get the USART register index */ - usartreg = (((uint16_t)USART_IT) >> 0x08); - - /* Get the interrupt position */ - itpos = USART_IT & IT_MASK; - itmask = (((uint32_t)0x01) << itpos); - - if (usartreg == 0x02) /* The IT is in CR2 register */ - { - usartxbase += 0x04; - } - else if (usartreg == 0x03) /* The IT is in CR3 register */ - { - usartxbase += 0x08; - } - else /* The IT is in CR1 register */ - { - } - if (NewState != DISABLE) - { - *(__IO uint32_t*)usartxbase |= itmask; - } - else - { - *(__IO uint32_t*)usartxbase &= ~itmask; - } -} - -/** - * @brief Enables the specified USART's Request. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param USART_Request: specifies the USART request. - * This parameter can be any combination of the following values: - * @arg USART_Request_TXFRQ: Transmit data flush ReQuest - * @arg USART_Request_RXFRQ: Receive data flush ReQuest - * @arg USART_Request_MMRQ: Mute Mode ReQuest - * @arg USART_Request_SBKRQ: Send Break ReQuest - * @arg USART_Request_ABRRQ: Auto Baud Rate ReQuest - * @param NewState: new state of the DMA interface when reception error occurs. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_REQUEST(USART_Request)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the USART ReQuest by setting the dedicated request bit in the RQR - register.*/ - USARTx->RQR |= USART_Request; - } - else - { - /* Disable the USART ReQuest by clearing the dedicated request bit in the RQR - register.*/ - USARTx->RQR &= (uint32_t)~USART_Request; - } -} - -/** - * @brief Enables or disables the USART's Overrun detection. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param USART_OVRDetection: specifies the OVR detection status in case of OVR error. - * This parameter can be any combination of the following values: - * @arg USART_OVRDetection_Enable: OVR error detection enabled when the USART OVR error - * is asserted. - * @arg USART_OVRDetection_Disable: OVR error detection disabled when the USART OVR error - * is asserted. - * @retval None - */ -void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_OVRDETECTION(USART_OVRDetection)); - - /* Clear the OVR detection bit */ - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_OVRDIS); - /* Set the new value for the OVR detection bit */ - USARTx->CR3 |= USART_OVRDetection; -} - -/** - * @brief Checks whether the specified USART flag is set or not. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param USART_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg USART_FLAG_REACK: Receive Enable acknowledge flag. - * @arg USART_FLAG_TEACK: Transmit Enable acknowledge flag. - * @arg USART_FLAG_WUF: Wake up flag. - * @arg USART_FLAG_RWU: Receive Wake up flag. - * @arg USART_FLAG_SBK: Send Break flag. - * @arg USART_FLAG_CMF: Character match flag. - * @arg USART_FLAG_BUSY: Busy flag. - * @arg USART_FLAG_ABRF: Auto baud rate flag. - * @arg USART_FLAG_ABRE: Auto baud rate error flag. - * @arg USART_FLAG_EOBF: End of block flag. - * @arg USART_FLAG_RTOF: Receive time out flag. - * @arg USART_FLAG_nCTSS: Inverted nCTS input bit status. - * @arg USART_FLAG_CTS: CTS Change flag. - * @arg USART_FLAG_LBD: LIN Break detection flag. - * @arg USART_FLAG_TXE: Transmit data register empty flag. - * @arg USART_FLAG_TC: Transmission Complete flag. - * @arg USART_FLAG_RXNE: Receive data register not empty flag. - * @arg USART_FLAG_IDLE: Idle Line detection flag. - * @arg USART_FLAG_ORE: OverRun Error flag. - * @arg USART_FLAG_NE: Noise Error flag. - * @arg USART_FLAG_FE: Framing Error flag. - * @arg USART_FLAG_PE: Parity Error flag. - * @retval The new state of USART_FLAG (SET or RESET). - */ -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_FLAG(USART_FLAG)); - - if ((USARTx->ISR & USART_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the USARTx's pending flags. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param USART_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg USART_FLAG_WUF: Wake up flag. - * @arg USART_FLAG_CMF: Character match flag. - * @arg USART_FLAG_EOBF: End of block flag. - * @arg USART_FLAG_RTOF: Receive time out flag. - * @arg USART_FLAG_CTS: CTS Change flag. - * @arg USART_FLAG_LBD: LIN Break detection flag. - * @arg USART_FLAG_TC: Transmission Complete flag. - * @arg USART_FLAG_IDLE: IDLE line detected flag. - * @arg USART_FLAG_ORE: OverRun Error flag. - * @arg USART_FLAG_NE: Noise Error flag. - * @arg USART_FLAG_FE: Framing Error flag. - * @arg USART_FLAG_PE: Parity Errorflag. - * - * @note - * - RXNE pending bit is cleared by a read to the USART_RDR register - * (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register USART_RQR - * (USART_RequestCmd()). - * - TC flag can be also cleared by software sequence: a read operation to - * USART_SR register (USART_GetFlagStatus()) followed by a write operation - * to USART_TDR register (USART_SendData()). - * - TXE flag is cleared by a write to the USART_TDR register - * (USART_SendData()) or by writing 1 to the TXFRQ in the register USART_RQR - * (USART_RequestCmd()). - * - SBKF flag is cleared by 1 to the SBKRQ in the register USART_RQR - * (USART_RequestCmd()). - * @retval None - */ -void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); - - USARTx->ICR = USART_FLAG; -} - -/** - * @brief Checks whether the specified USART interrupt has occurred or not. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param USART_IT: specifies the USART interrupt source to check. - * This parameter can be one of the following values: - * @arg USART_IT_WU: Wake up interrupt. - * @arg USART_IT_CM: Character match interrupt. - * @arg USART_IT_EOB: End of block interrupt. - * @arg USART_IT_RTO: Receive time out interrupt. - * @arg USART_IT_CTS: CTS change interrupt. - * @arg USART_IT_LBD: LIN Break detection interrupt. - * @arg USART_IT_TXE: Tansmit Data Register empty interrupt. - * @arg USART_IT_TC: Transmission complete interrupt. - * @arg USART_IT_RXNE: Receive Data register not empty interrupt. - * @arg USART_IT_IDLE: Idle line detection interrupt. - * @arg USART_IT_ORE: OverRun Error interrupt. - * @arg USART_IT_NE: Noise Error interrupt. - * @arg USART_IT_FE: Framing Error interrupt. - * @arg USART_IT_PE: Parity Error interrupt. - * @retval The new state of USART_IT (SET or RESET). - */ -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT) -{ - uint32_t bitpos = 0, itmask = 0, usartreg = 0; - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_GET_IT(USART_IT)); - - /* Get the USART register index */ - usartreg = (((uint16_t)USART_IT) >> 0x08); - /* Get the interrupt position */ - itmask = USART_IT & IT_MASK; - itmask = (uint32_t)0x01 << itmask; - - if (usartreg == 0x01) /* The IT is in CR1 register */ - { - itmask &= USARTx->CR1; - } - else if (usartreg == 0x02) /* The IT is in CR2 register */ - { - itmask &= USARTx->CR2; - } - else /* The IT is in CR3 register */ - { - itmask &= USARTx->CR3; - } - - bitpos = USART_IT >> 0x10; - bitpos = (uint32_t)0x01 << bitpos; - bitpos &= USARTx->ISR; - if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/** - * @brief Clears the USARTx's interrupt pending bits. - * @param USARTx: Select the USART peripheral. This parameter can be one of the - * following values: USART1 or USART2 or USART3 or UART4 or UART5. - * @param USART_IT: specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg USART_IT_WU: Wake up interrupt. - * @arg USART_IT_CM: Character match interrupt. - * @arg USART_IT_EOB: End of block interrupt. - * @arg USART_IT_RTO: Receive time out interrupt. - * @arg USART_IT_CTS: CTS change interrupt. - * @arg USART_IT_LBD: LIN Break detection interrupt. - * @arg USART_IT_TC: Transmission complete interrupt. - * @arg USART_IT_IDLE: IDLE line detected interrupt. - * @arg USART_IT_ORE: OverRun Error interrupt. - * @arg USART_IT_NE: Noise Error interrupt. - * @arg USART_IT_FE: Framing Error interrupt. - * @arg USART_IT_PE: Parity Error interrupt. - * @note - * - RXNE pending bit is cleared by a read to the USART_RDR register - * (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register USART_RQR - * (USART_RequestCmd()). - * - TC pending bit can be also cleared by software sequence: a read - * operation to USART_SR register (USART_GetITStatus()) followed by a write - * operation to USART_TDR register (USART_SendData()). - * - TXE pending bit is cleared by a write to the USART_TDR register - * (USART_SendData()) or by writing 1 to the TXFRQ in the register USART_RQR - * (USART_RequestCmd()). - * @retval None - */ -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT) -{ - uint32_t bitpos = 0, itmask = 0; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_IT(USART_IT)); - - bitpos = USART_IT >> 0x10; - itmask = ((uint32_t)0x01 << (uint32_t)bitpos); - USARTx->ICR = (uint32_t)itmask; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_usart.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,617 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_usart.h - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file contains all the functions prototypes for the USART - * firmware library. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F30x_USART_H -#define __STM32F30x_USART_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup USART - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - - - -/** - * @brief USART Init Structure definition - */ - -typedef struct -{ - uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) - - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */ - - uint32_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_Word_Length */ - - uint32_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_Stop_Bits */ - - uint32_t USART_Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref USART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint32_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_Mode */ - - uint32_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref USART_Hardware_Flow_Control*/ -} USART_InitTypeDef; - -/** - * @brief USART Clock Init Structure definition - */ - -typedef struct -{ - uint32_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. - This parameter can be a value of @ref USART_Clock */ - - uint32_t USART_CPOL; /*!< Specifies the steady state of the serial clock. - This parameter can be a value of @ref USART_Clock_Polarity */ - - uint32_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_Clock_Phase */ - - uint32_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_Last_Bit */ -} USART_ClockInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup USART_Exported_Constants - * @{ - */ - -#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3) || \ - ((PERIPH) == UART4) || \ - ((PERIPH) == UART5)) - -#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3)) - -#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3) || \ - ((PERIPH) == UART4)) - - -/** @defgroup USART_Word_Length - * @{ - */ - -#define USART_WordLength_8b ((uint32_t)0x00000000) -#define USART_WordLength_9b USART_CR1_M -#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ - ((LENGTH) == USART_WordLength_9b)) -/** - * @} - */ - -/** @defgroup USART_Stop_Bits - * @{ - */ - -#define USART_StopBits_1 ((uint32_t)0x00000000) -#define USART_StopBits_2 USART_CR2_STOP_1 -#define USART_StopBits_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) -#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ - ((STOPBITS) == USART_StopBits_2) || \ - ((STOPBITS) == USART_StopBits_1_5)) -/** - * @} - */ - -/** @defgroup USART_Parity - * @{ - */ - -#define USART_Parity_No ((uint32_t)0x00000000) -#define USART_Parity_Even USART_CR1_PCE -#define USART_Parity_Odd (USART_CR1_PCE | USART_CR1_PS) -#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ - ((PARITY) == USART_Parity_Even) || \ - ((PARITY) == USART_Parity_Odd)) -/** - * @} - */ - -/** @defgroup USART_Mode - * @{ - */ - -#define USART_Mode_Rx USART_CR1_RE -#define USART_Mode_Tx USART_CR1_TE -#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && \ - ((MODE) != (uint32_t)0x00)) -/** - * @} - */ - -/** @defgroup USART_Hardware_Flow_Control - * @{ - */ - -#define USART_HardwareFlowControl_None ((uint32_t)0x00000000) -#define USART_HardwareFlowControl_RTS USART_CR3_RTSE -#define USART_HardwareFlowControl_CTS USART_CR3_CTSE -#define USART_HardwareFlowControl_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) -#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ - (((CONTROL) == USART_HardwareFlowControl_None) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS) || \ - ((CONTROL) == USART_HardwareFlowControl_CTS) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) -/** - * @} - */ - -/** @defgroup USART_Clock - * @{ - */ - -#define USART_Clock_Disable ((uint32_t)0x00000000) -#define USART_Clock_Enable USART_CR2_CLKEN -#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ - ((CLOCK) == USART_Clock_Enable)) -/** - * @} - */ - -/** @defgroup USART_Clock_Polarity - * @{ - */ - -#define USART_CPOL_Low ((uint32_t)0x00000000) -#define USART_CPOL_High USART_CR2_CPOL -#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) - -/** - * @} - */ - -/** @defgroup USART_Clock_Phase - * @{ - */ - -#define USART_CPHA_1Edge ((uint32_t)0x00000000) -#define USART_CPHA_2Edge USART_CR2_CPHA -#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) - -/** - * @} - */ - -/** @defgroup USART_Last_Bit - * @{ - */ - -#define USART_LastBit_Disable ((uint32_t)0x00000000) -#define USART_LastBit_Enable USART_CR2_LBCL -#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ - ((LASTBIT) == USART_LastBit_Enable)) -/** - * @} - */ - -/** @defgroup USART_DMA_Requests - * @{ - */ - -#define USART_DMAReq_Tx USART_CR3_DMAT -#define USART_DMAReq_Rx USART_CR3_DMAR -#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint32_t)0xFFFFFF3F) == 0x00) && \ - ((DMAREQ) != (uint32_t)0x00)) - -/** - * @} - */ - -/** @defgroup USART_DMA_Recception_Error - * @{ - */ - -#define USART_DMAOnError_Enable ((uint32_t)0x00000000) -#define USART_DMAOnError_Disable USART_CR3_DDRE -#define IS_USART_DMAONERROR(DMAERROR) (((DMAERROR) == USART_DMAOnError_Disable)|| \ - ((DMAERROR) == USART_DMAOnError_Enable)) -/** - * @} - */ - -/** @defgroup USART_MuteMode_WakeUp_methods - * @{ - */ - -#define USART_WakeUp_IdleLine ((uint32_t)0x00000000) -#define USART_WakeUp_AddressMark USART_CR1_WAKE -#define IS_USART_MUTEMODE_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ - ((WAKEUP) == USART_WakeUp_AddressMark)) -/** - * @} - */ - -/** @defgroup USART_Address_Detection - * @{ - */ - -#define USART_AddressLength_4b ((uint32_t)0x00000000) -#define USART_AddressLength_7b USART_CR2_ADDM7 -#define IS_USART_ADDRESS_DETECTION(ADDRESS) (((ADDRESS) == USART_AddressLength_4b) || \ - ((ADDRESS) == USART_AddressLength_7b)) -/** - * @} - */ - -/** @defgroup USART_StopMode_WakeUp_methods - * @{ - */ - -#define USART_WakeUpSource_AddressMatch ((uint32_t)0x00000000) -#define USART_WakeUpSource_StartBit USART_CR3_WUS_1 -#define USART_WakeUpSource_RXNE (uint32_t)(USART_CR3_WUS_0 | USART_CR3_WUS_1) -#define IS_USART_STOPMODE_WAKEUPSOURCE(SOURCE) (((SOURCE) == USART_WakeUpSource_AddressMatch) || \ - ((SOURCE) == USART_WakeUpSource_StartBit) || \ - ((SOURCE) == USART_WakeUpSource_RXNE)) -/** - * @} - */ - -/** @defgroup USART_LIN_Break_Detection_Length - * @{ - */ - -#define USART_LINBreakDetectLength_10b ((uint32_t)0x00000000) -#define USART_LINBreakDetectLength_11b USART_CR2_LBDL -#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ - (((LENGTH) == USART_LINBreakDetectLength_10b) || \ - ((LENGTH) == USART_LINBreakDetectLength_11b)) -/** - * @} - */ - -/** @defgroup USART_IrDA_Low_Power - * @{ - */ - -#define USART_IrDAMode_LowPower USART_CR3_IRLP -#define USART_IrDAMode_Normal ((uint32_t)0x00000000) -#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ - ((MODE) == USART_IrDAMode_Normal)) -/** - * @} - */ - -/** @defgroup USART_DE_Polarity - * @{ - */ - -#define USART_DEPolarity_High ((uint32_t)0x00000000) -#define USART_DEPolarity_Low USART_CR3_DEP -#define IS_USART_DE_POLARITY(POLARITY) (((POLARITY) == USART_DEPolarity_Low) || \ - ((POLARITY) == USART_DEPolarity_High)) -/** - * @} - */ - -/** @defgroup USART_Inversion_Pins - * @{ - */ - -#define USART_InvPin_Tx USART_CR2_TXINV -#define USART_InvPin_Rx USART_CR2_RXINV -#define IS_USART_INVERSTION_PIN(PIN) ((((PIN) & (uint32_t)0xFFFCFFFF) == 0x00) && \ - ((PIN) != (uint32_t)0x00)) - -/** - * @} - */ - -/** @defgroup USART_AutoBaudRate_Mode - * @{ - */ - -#define USART_AutoBaudRate_StartBit ((uint32_t)0x00000000) -#define USART_AutoBaudRate_FallingEdge USART_CR2_ABRMODE_0 -#define USART_AutoBaudRate_0x7FFrame USART_CR2_ABRMODE_1 -#define USART_AutoBaudRate_0x55Frame (USART_CR2_ABRMODE_0 | USART_CR2_ABRMODE_1) -#define IS_USART_AUTOBAUDRATE_MODE(MODE) (((MODE) == USART_AutoBaudRate_StartBit) || \ - ((MODE) == USART_AutoBaudRate_FallingEdge) || \ - ((MODE) == USART_AutoBaudRate_0x7FFrame) || \ - ((MODE) == USART_AutoBaudRate_0x55Frame)) -/** - * @} - */ - -/** @defgroup USART_OVR_DETECTION - * @{ - */ - -#define USART_OVRDetection_Enable ((uint32_t)0x00000000) -#define USART_OVRDetection_Disable USART_CR3_OVRDIS -#define IS_USART_OVRDETECTION(OVR) (((OVR) == USART_OVRDetection_Enable)|| \ - ((OVR) == USART_OVRDetection_Disable)) -/** - * @} - */ -/** @defgroup USART_Request - * @{ - */ - -#define USART_Request_ABRRQ USART_RQR_ABRRQ -#define USART_Request_SBKRQ USART_RQR_SBKRQ -#define USART_Request_MMRQ USART_RQR_MMRQ -#define USART_Request_RXFRQ USART_RQR_RXFRQ -#define USART_Request_TXFRQ USART_RQR_TXFRQ - -#define IS_USART_REQUEST(REQUEST) (((REQUEST) == USART_Request_TXFRQ) || \ - ((REQUEST) == USART_Request_RXFRQ) || \ - ((REQUEST) == USART_Request_MMRQ) || \ - ((REQUEST) == USART_Request_SBKRQ) || \ - ((REQUEST) == USART_Request_ABRRQ)) -/** - * @} - */ - -/** @defgroup USART_Flags - * @{ - */ -#define USART_FLAG_REACK USART_ISR_REACK -#define USART_FLAG_TEACK USART_ISR_TEACK -#define USART_FLAG_WU USART_ISR_WUF -#define USART_FLAG_RWU USART_ISR_RWU -#define USART_FLAG_SBK USART_ISR_SBKF -#define USART_FLAG_CM USART_ISR_CMF -#define USART_FLAG_BUSY USART_ISR_BUSY -#define USART_FLAG_ABRF USART_ISR_ABRF -#define USART_FLAG_ABRE USART_ISR_ABRE -#define USART_FLAG_EOB USART_ISR_EOBF -#define USART_FLAG_RTO USART_ISR_RTOF -#define USART_FLAG_nCTSS USART_ISR_CTS -#define USART_FLAG_CTS USART_ISR_CTSIF -#define USART_FLAG_LBD USART_ISR_LBD -#define USART_FLAG_TXE USART_ISR_TXE -#define USART_FLAG_TC USART_ISR_TC -#define USART_FLAG_RXNE USART_ISR_RXNE -#define USART_FLAG_IDLE USART_ISR_IDLE -#define USART_FLAG_ORE USART_ISR_ORE -#define USART_FLAG_NE USART_ISR_NE -#define USART_FLAG_FE USART_ISR_FE -#define USART_FLAG_PE USART_ISR_PE -#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ - ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ - ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ - ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ - ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \ - ((FLAG) == USART_FLAG_nCTSS) || ((FLAG) == USART_FLAG_RTO) || \ - ((FLAG) == USART_FLAG_EOB) || ((FLAG) == USART_FLAG_ABRE) || \ - ((FLAG) == USART_FLAG_ABRF) || ((FLAG) == USART_FLAG_BUSY) || \ - ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_SBK) || \ - ((FLAG) == USART_FLAG_RWU) || ((FLAG) == USART_FLAG_WU) || \ - ((FLAG) == USART_FLAG_TEACK)|| ((FLAG) == USART_FLAG_REACK)) - -#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG) == USART_FLAG_WU) || ((FLAG) == USART_FLAG_TC) || \ - ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_ORE) || \ - ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \ - ((FLAG) == USART_FLAG_LBD) || ((FLAG) == USART_FLAG_CTS) || \ - ((FLAG) == USART_FLAG_RTO) || ((FLAG) == USART_FLAG_EOB) || \ - ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_PE)) -/** - * @} - */ - -/** @defgroup USART_Interrupt_definition - * @brief USART Interrupt definition - * USART_IT possible values - * Elements values convention: 0xZZZZYYXX - * XX: Position of the corresponding Interrupt - * YY: Register index - * ZZZZ: Flag position - * @{ - */ - -#define USART_IT_WU ((uint32_t)0x00140316) -#define USART_IT_CM ((uint32_t)0x0011010E) -#define USART_IT_EOB ((uint32_t)0x000C011B) -#define USART_IT_RTO ((uint32_t)0x000B011A) -#define USART_IT_PE ((uint32_t)0x00000108) -#define USART_IT_TXE ((uint32_t)0x00070107) -#define USART_IT_TC ((uint32_t)0x00060106) -#define USART_IT_RXNE ((uint32_t)0x00050105) -#define USART_IT_IDLE ((uint32_t)0x00040104) -#define USART_IT_LBD ((uint32_t)0x00080206) -#define USART_IT_CTS ((uint32_t)0x0009030A) -#define USART_IT_ERR ((uint32_t)0x00000300) -#define USART_IT_ORE ((uint32_t)0x00030300) -#define USART_IT_NE ((uint32_t)0x00020300) -#define USART_IT_FE ((uint32_t)0x00010300) - -#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR) || \ - ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \ - ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU)) - -#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ - ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE) || \ - ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \ - ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU)) - -#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_PE) || \ - ((IT) == USART_IT_FE) || ((IT) == USART_IT_NE) || \ - ((IT) == USART_IT_ORE) || ((IT) == USART_IT_IDLE) || \ - ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || \ - ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \ - ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU)) -/** - * @} - */ - -/** @defgroup USART_Global_definition - * @{ - */ - -#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x005B8D81)) -#define IS_USART_DE_ASSERTION_DEASSERTION_TIME(TIME) ((TIME) <= 0x1F) -#define IS_USART_AUTO_RETRY_COUNTER(COUNTER) ((COUNTER) <= 0x7) -#define IS_USART_TIMEOUT(TIMEOUT) ((TIMEOUT) <= 0x00FFFFFF) -#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Initialization and Configuration functions *********************************/ -void USART_DeInit(USART_TypeDef* USARTx); -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); -void USART_StructInit(USART_InitTypeDef* USART_InitStruct); -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState); -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState); -void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut); - -/* STOP Mode functions ********************************************************/ -void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource); - -/* AutoBaudRate functions *****************************************************/ -void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate); - -/* Data transfers functions ***************************************************/ -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); -uint16_t USART_ReceiveData(USART_TypeDef* USARTx); - -/* Multi-Processor Communication functions ************************************/ -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); -void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp); -void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength); -/* LIN mode functions *********************************************************/ -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength); -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* Half-duplex mode function **************************************************/ -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* Smartcard mode functions ***************************************************/ -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); -void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount); -void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength); - -/* IrDA mode functions ********************************************************/ -void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode); -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* RS485 mode functions *******************************************************/ -void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity); -void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime); -void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime); - -/* DMA transfers management functions *****************************************/ -void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState); -void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError); - -/* Interrupts and flags management functions **********************************/ -void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState); -void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState); -void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection); -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG); -void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG); -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT); -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F30x_USART_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_wwdg.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,314 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_wwdg.c - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Window watchdog (WWDG) peripheral: - * + Prescaler, Refresh window and Counter configuration - * + WWDG activation - * + Interrupts and flags management - * - * @verbatim - * - ============================================================================== - ##### WWDG features ##### - ============================================================================== - - [..] Once enabled the WWDG generates a system reset on expiry of a programmed - time period, unless the program refreshes the counter (downcounter) - before to reach 0x3F value (i.e. a reset is generated when the counter - value rolls over from 0x40 to 0x3F). - [..] An MCU reset is also generated if the counter value is refreshed - before the counter has reached the refresh window value. This - implies that the counter must be refreshed in a limited window. - - [..] Once enabled the WWDG cannot be disabled except by a system reset. - - [..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG - reset occurs. - - [..] The WWDG counter input clock is derived from the APB clock divided - by a programmable prescaler. - - [..] WWDG counter clock = PCLK1 / Prescaler. - [..] WWDG timeout = (WWDG counter clock) * (counter value). - - [..] Min-max timeout value @36MHz (PCLK1): ~114us / ~58.3ms. - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) - function. - - (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function. - - (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function. - - (#) Set the WWDG counter value and start it using WWDG_Enable() function. - When the WWDG is enabled the counter value should be configured to - a value greater than 0x40 to prevent generating an immediate reset. - - (#) Optionally you can enable the Early wakeup interrupt which is - generated when the counter reach 0x40. - Once enabled this interrupt cannot be disabled except by a system reset. - - (#) Then the application program must refresh the WWDG counter at regular - intervals during normal operation to prevent an MCU reset, using - WWDG_SetCounter() function. This operation must occur only when - the counter value is lower than the refresh window value, - programmed using WWDG_SetWindowValue(). - - @endverbatim - - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x_wwdg.h" -#include "stm32f30x_rcc.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @defgroup WWDG - * @brief WWDG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* --------------------- WWDG registers bit mask ---------------------------- */ -/* CFR register bit mask */ -#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F) -#define CFR_W_MASK ((uint32_t)0xFFFFFF80) -#define BIT_MASK ((uint8_t)0x7F) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup WWDG_Private_Functions - * @{ - */ - -/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions - * @brief Prescaler, Refresh window and Counter configuration functions - * -@verbatim - ============================================================================== - ##### Prescaler, Refresh window and Counter configuration functions ##### - ============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the WWDG peripheral registers to their default reset values. - * @param None - * @retval None - */ -void WWDG_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); -} - -/** - * @brief Sets the WWDG Prescaler. - * @param WWDG_Prescaler: specifies the WWDG Prescaler. - * This parameter can be one of the following values: - * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 - * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 - * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 - * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 - * @retval None - */ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); - /* Clear WDGTB[1:0] bits */ - tmpreg = WWDG->CFR & CFR_WDGTB_MASK; - /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ - tmpreg |= WWDG_Prescaler; - /* Store the new value */ - WWDG->CFR = tmpreg; -} - -/** - * @brief Sets the WWDG window value. - * @param WindowValue: specifies the window value to be compared to the downcounter. - * This parameter value must be lower than 0x80. - * @retval None - */ -void WWDG_SetWindowValue(uint8_t WindowValue) -{ - __IO uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); - /* Clear W[6:0] bits */ - - tmpreg = WWDG->CFR & CFR_W_MASK; - - /* Set W[6:0] bits according to WindowValue value */ - tmpreg |= WindowValue & (uint32_t) BIT_MASK; - - /* Store the new value */ - WWDG->CFR = tmpreg; -} - -/** - * @brief Enables the WWDG Early Wakeup interrupt(EWI). - * @note Once enabled this interrupt cannot be disabled except by a system reset. - * @param None - * @retval None - */ -void WWDG_EnableIT(void) -{ - WWDG->CFR |= WWDG_CFR_EWI; -} - -/** - * @brief Sets the WWDG counter value. - * @param Counter: specifies the watchdog counter value. - * This parameter must be a number between 0x40 and 0x7F (to prevent generating - * an immediate reset). - * @retval None - */ -void WWDG_SetCounter(uint8_t Counter) -{ - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - /* Write to T[6:0] bits to configure the counter value, no need to do - a read-modify-write; writing a 0 to WDGA bit does nothing */ - WWDG->CR = Counter & BIT_MASK; -} - -/** - * @} - */ - -/** @defgroup WWDG_Group2 WWDG activation functions - * @brief WWDG activation functions - * -@verbatim - ============================================================================== - ##### WWDG activation function ##### - ============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables WWDG and load the counter value. - * @param Counter: specifies the watchdog counter value. - * This parameter must be a number between 0x40 and 0x7F (to prevent generating - * an immediate reset). - * @retval None - */ -void WWDG_Enable(uint8_t Counter) -{ - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - WWDG->CR = WWDG_CR_WDGA | Counter; -} - -/** - * @} - */ - -/** @defgroup WWDG_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - ============================================================================== - ##### Interrupts and flags management functions ##### - ============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the Early Wakeup interrupt flag is set or not. - * @param None - * @retval The new state of the Early Wakeup interrupt flag (SET or RESET). - */ -FlagStatus WWDG_GetFlagStatus(void) -{ - FlagStatus bitstatus = RESET; - - if ((WWDG->SR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears Early Wakeup interrupt flag. - * @param None - * @retval None - */ -void WWDG_ClearFlag(void) -{ - WWDG->SR = (uint32_t)RESET; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_wwdg.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,119 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f30x_wwdg.h - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief This file contains all the functions prototypes for the WWDG - * firmware library. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F30x_WWDG_H -#define __STM32F30x_WWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f30x.h" - -/** @addtogroup STM32F30x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup WWDG - * @{ - */ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup WWDG_Exported_Constants - * @{ - */ - -/** @defgroup WWDG_Prescaler - * @{ - */ - -#define WWDG_Prescaler_1 ((uint32_t)0x00000000) -#define WWDG_Prescaler_2 ((uint32_t)0x00000080) -#define WWDG_Prescaler_4 ((uint32_t)0x00000100) -#define WWDG_Prescaler_8 ((uint32_t)0x00000180) -#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ - ((PRESCALER) == WWDG_Prescaler_2) || \ - ((PRESCALER) == WWDG_Prescaler_4) || \ - ((PRESCALER) == WWDG_Prescaler_8)) -#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) -#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -/* Function used to set the WWDG configuration to the default reset state ****/ -void WWDG_DeInit(void); - -/* Prescaler, Refresh window and Counter configuration functions **************/ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); -void WWDG_SetWindowValue(uint8_t WindowValue); -void WWDG_EnableIT(void); -void WWDG_SetCounter(uint8_t Counter); - -/* WWDG activation functions **************************************************/ -void WWDG_Enable(uint8_t Counter); - -/* Interrupts and flags management functions **********************************/ -FlagStatus WWDG_GetFlagStatus(void); -void WWDG_ClearFlag(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F30x_WWDG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/system_stm32f30x.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,478 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f30x.c - * @author MCD Application Team - * @version V1.0.0 - * @date 05-March-2014 - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. - * This file contains the system clock configuration for STM32F30x devices, - * and is generated by the clock configuration tool - * stm32f30x_Clock_Configuration_V1.0.0.xls - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier - * and Divider factors, AHB/APBx prescalers and Flash settings), - * depending on the configuration made in the clock xls tool. - * This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f30x.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the HSI (8 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32f30x.s" file, to - * configure the system clock before to branch to main program. - * - * 3. If the system clock source selected by user fails to startup, the SystemInit() - * function will do nothing and HSI still used as system clock source. User can - * add some code to deal with this issue inside the SetSysClock() function. - * - * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define - * in "stm32f30x.h" file. When HSE is used as system clock source, directly or - * through PLL, and you are using different crystal you have to adapt the HSE - * value to your own configuration. - * - * 5. This file configures the system clock as follows: - *----------------------------------------------------------------------------- - * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI - * | (external 8 MHz clock) | (internal 8 MHz) - * | 2- PLL_HSE_XTAL | - * | (external 8 MHz xtal) | - *----------------------------------------------------------------------------- - * SYSCLK(MHz) | 72 | 64 - *----------------------------------------------------------------------------- - * AHBCLK (MHz) | 72 | 64 - *----------------------------------------------------------------------------- - * APB1CLK (MHz) | 36 | 32 - *----------------------------------------------------------------------------- - * APB2CLK (MHz) | 72 | 64 - *----------------------------------------------------------------------------- - * USB capable (48 MHz precise clock) | YES | NO - *----------------------------------------------------------------------------- - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f30x_system - * @{ - */ - -/** @addtogroup STM32F30x_System_Private_Includes - * @{ - */ - -#include "stm32f30x.h" - -/** - * @} - */ - -/** @addtogroup STM32F30x_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F30x_System_Private_Defines - * @{ - */ - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -/** - * @} - */ - -/** @addtogroup STM32F30x_System_Private_Macros - * @{ - */ - -/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ -#define USE_PLL_HSE_EXTC (1) /* Use external clock */ -#define USE_PLL_HSE_XTAL (1) /* Use external xtal */ - -/** - * @} - */ - -/** @addtogroup STM32F30x_System_Private_Variables - * @{ - */ - -uint32_t SystemCoreClock = 64000000; /* Default with HSI. Will be updated if HSE is used */ - -const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - -/** - * @} - */ - -/** @addtogroup STM32F30x_System_Private_FunctionPrototypes - * @{ - */ - -void SetSysClock(void); - -#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) -uint8_t SetSysClock_PLL_HSE(uint8_t bypass); -#endif - -uint8_t SetSysClock_PLL_HSI(void); - -/** - * @} - */ - -/** @addtogroup STM32F30x_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemFrequency variable. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - #endif - - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR &= 0xF87FC00C; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */ - RCC->CFGR &= (uint32_t)0xFF80FFFF; - - /* Reset PREDIV1[3:0] bits */ - RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; - - /* Reset USARTSW[1:0], I2CSW and TIMs bits */ - RCC->CFGR3 &= (uint32_t)0xFF00FCCC; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; - - /* Configure the System clock source, PLL Multiplier and Divider factors, - AHB/APBx prescalers and Flash settings */ - SetSysClock(); - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value - * 8 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock */ - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; - pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - pllmull = ( pllmull >> 18) + 2; - - if (pllsource == 0x00) - { - /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; - } - else - { - prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; - /* HSE oscillator clock selected as PREDIV1 clock entry */ - SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; - } - break; - default: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK clock frequency ----------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -void SetSysClock(void) -{ - /* 1- Try to start with HSE and external clock */ -#if USE_PLL_HSE_EXTC != 0 - if (SetSysClock_PLL_HSE(1) == 0) -#endif - { - /* 2- If fail try to start with HSE and external xtal */ - #if USE_PLL_HSE_XTAL != 0 - if (SetSysClock_PLL_HSE(0) == 0) - #endif - { - /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI() == 0) - { - while(1) - { - // [TODO] Put something here to tell the user that a problem occured... - } - } - } - } - - /* Output SYSCLK on MCO pin(PA8) for debugging purpose */ - /* - // Enable GPIOA clock - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); - // Configure MCO pin (PA8) - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(GPIOA, &GPIO_InitStructure); - // Select the clock to output - RCC_MCOConfig(RCC_MCOSource_SYSCLK, RCC_MCOPrescaler_1); - */ -} - -#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSE(uint8_t bypass) -{ - __IO uint32_t StartUpCounter = 0; - __IO uint32_t HSEStatus = 0; - - /* Bypass HSE: can be done only if HSE is OFF */ - RCC->CR &= ((uint32_t)~RCC_CR_HSEON); /* To be sure HSE is OFF */ - if (bypass != 0) - { - RCC->CR |= ((uint32_t)RCC_CR_HSEBYP); - } - else - { - RCC->CR &= ((uint32_t)~RCC_CR_HSEBYP); - } - - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - /* Check if HSE has started correctly */ - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - /* Enable prefetch buffer and set flash latency - 0WS for 0 < SYSCLK <= 24 MHz - 1WS for 24 < SYSCLK <= 48 MHz - 2WS for 48 < SYSCLK <= 72 MHz */ - FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1; /* 2 WS */ - - /* Warning: values are obtained with external xtal or clock = 8 MHz */ - /* SYSCLK = 72 MHz (8 MHz * 9) */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9 - | RCC_CFGR_HPRE_DIV1 /* HCLK = 72 MHz */ - | RCC_CFGR_PPRE2_DIV1 /* PCLK2 = 72 MHz */ - | RCC_CFGR_PPRE1_DIV2); /* PCLK1 = 36 MHz */ - /* USBCLK = 48 MHz (72 MHz / 1.5) --> USB OK */ - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) - { - } - - return 1; // OK - } - else - { - return 0; // FAIL - } -} -#endif - -/******************************************************************************/ -/* PLL (clocked by HSI) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSI(void) -{ - /* At this stage the HSI is already enabled and used as System clock source */ - - /* Enable prefetch buffer and set flash latency - 0WS for 0 < SYSCLK <= 24 MHz - 1WS for 24 < SYSCLK <= 48 MHz - 2WS for 48 < SYSCLK <= 72 MHz */ - FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1; /* 2 WS */ - - /* SYSCLK = 64 MHz (8 MHz / 2 * 16) */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL16 - | RCC_CFGR_HPRE_DIV1 /* HCLK = 64 MHz */ - | RCC_CFGR_PPRE2_DIV1 /* PCLK2 = 64 MHz */ - | RCC_CFGR_PPRE1_DIV2); /* PCLK1 = 32 MHz */ - /* USBCLK = 42.667 MHz (64 MHz / 1.5) --> USB NOT POSSIBLE */ - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) - { - } - - return 1; // OK -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/system_stm32f30x.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,86 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f30x.h - * @author MCD Application Team - * @version V1.1.0 - * @date 27-February-2014 - * @brief CMSIS Cortex-M4 Device System Source File for STM32F30x devices. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f30x_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32F30X_H -#define __SYSTEM_STM32F30X_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/** @addtogroup STM32F30x_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32F30X_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4XX/TOOLCHAIN_ARM_STD/STM32F407.sct Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,17 +0,0 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x08000000 0x00100000 { ; load region size_region - ER_IROM1 0x08000000 0x00100000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x10000000 0x00010000 { ; CCM - } - RW_IRAM2 0x20000188 0x0001FE78 { - .ANY (+RW +ZI) - } -} -
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4XX/TOOLCHAIN_ARM_STD/startup_STM32F40x.S Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,369 +0,0 @@ -;/***************************************************************************** -; * @file: startup_STM32F40x.s -; * @purpose: CMSIS Cortex-M4 Core Device Startup File -; * for the ST STM32F40x Device Series -; * @version: V1.20 -; * @date: 16. January 2012 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M4 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - - -__initial_sp EQU 0x20020000 ; Top of RAM - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD CRYP_IRQHandler ; CRYP crypto - DCD HASH_RNG_IRQHandler ; Hash and Rng - DCD FPU_IRQHandler ; FPU - - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FSMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT CRYP_IRQHandler [WEAK] - EXPORT HASH_RNG_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FSMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -CRYP_IRQHandler -HASH_RNG_IRQHandler -FPU_IRQHandler - - B . - - ENDP - - - ALIGN - END
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4XX/TOOLCHAIN_ARM_STD/sys.cpp Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,31 +0,0 @@ -/* mbed Microcontroller Library - stackheap - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * Setup a fixed single stack/heap memory model, - * between the top of the RW/ZI region and the stackpointer - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rt_misc.h> -#include <stdint.h> - -extern char Image$$RW_IRAM1$$ZI$$Limit[]; - -extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { - uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; - uint32_t sp_limit = __current_sp(); - - zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned - - struct __initial_stackheap r; - r.heap_base = zi_limit; - r.heap_limit = sp_limit; - return r; -} - -#ifdef __cplusplus -} -#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4XX/TOOLCHAIN_GCC_ARM/STM32F407.ld Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,151 +0,0 @@ -/* Linker script for STM32F407 */ - -/* Linker script to configure memory regions. */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K - RAM (rwx) : ORIGIN = 0x20000188, LENGTH = 0x1FE78 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY): - { - __end__ = .; - end = __end__; - *(.heap*) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} -
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4XX/TOOLCHAIN_GCC_ARM/startup_STM32F40x.S Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,320 +0,0 @@ -/* File: startup_STM32F40x.S - * Purpose: startup file for Cortex-M4 devices. Should use with - * GCC for ARM Embedded Processors - * Version: V1.4 - * Date: 09 July 2012 - * - * Copyright (c) 2011, 2012, ARM Limited - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * Neither the name of the ARM Limited nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - .syntax unified - .arch armv7-m - - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 0xc00 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .if Heap_Size - .space Heap_Size - .endif - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .isr_vector - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External interrupts */ - .long WWDG_IRQHandler /* Window WatchDog */ - .long PVD_IRQHandler /* PVD through EXTI Line detection */ - .long TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .long RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .long FLASH_IRQHandler /* FLASH */ - .long RCC_IRQHandler /* RCC */ - .long EXTI0_IRQHandler /* EXTI Line0 */ - .long EXTI1_IRQHandler /* EXTI Line1 */ - .long EXTI2_IRQHandler /* EXTI Line2 */ - .long EXTI3_IRQHandler /* EXTI Line3 */ - .long EXTI4_IRQHandler /* EXTI Line4 */ - .long DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .long DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .long DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .long DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .long DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .long DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .long DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .long ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .long CAN1_TX_IRQHandler /* CAN1 TX */ - .long CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .long CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .long CAN1_SCE_IRQHandler /* CAN1 SCE */ - .long EXTI9_5_IRQHandler /* External Line[9:5]s */ - .long TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .long TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .long TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .long TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .long TIM2_IRQHandler /* TIM2 */ - .long TIM3_IRQHandler /* TIM3 */ - .long TIM4_IRQHandler /* TIM4 */ - .long I2C1_EV_IRQHandler /* I2C1 Event */ - .long I2C1_ER_IRQHandler /* I2C1 Error */ - .long I2C2_EV_IRQHandler /* I2C2 Event */ - .long I2C2_ER_IRQHandler /* I2C2 Error */ - .long SPI1_IRQHandler /* SPI1 */ - .long SPI2_IRQHandler /* SPI2 */ - .long USART1_IRQHandler /* USART1 */ - .long USART2_IRQHandler /* USART2 */ - .long USART3_IRQHandler /* USART3 */ - .long EXTI15_10_IRQHandler /* External Line[15:10]s */ - .long RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .long OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .long TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .long TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .long TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .long TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .long DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .long FSMC_IRQHandler /* FSMC */ - .long SDIO_IRQHandler /* SDIO */ - .long TIM5_IRQHandler /* TIM5 */ - .long SPI3_IRQHandler /* SPI3 */ - .long UART4_IRQHandler /* UART4 */ - .long UART5_IRQHandler /* UART5 */ - .long TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ - .long TIM7_IRQHandler /* TIM7 */ - .long DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .long DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .long DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .long DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .long DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .long ETH_IRQHandler /* Ethernet */ - .long ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ - .long CAN2_TX_IRQHandler /* CAN2 TX */ - .long CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .long CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .long CAN2_SCE_IRQHandler /* CAN2 SCE */ - .long OTG_FS_IRQHandler /* USB OTG FS */ - .long DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .long DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .long DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .long USART6_IRQHandler /* USART6 */ - .long I2C3_EV_IRQHandler /* I2C3 event */ - .long I2C3_ER_IRQHandler /* I2C3 error */ - .long OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ - .long OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ - .long OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ - .long OTG_HS_IRQHandler /* USB OTG HS */ - .long DCMI_IRQHandler /* DCMI */ - .long CRYP_IRQHandler /* CRYP crypto */ - .long HASH_RNG_IRQHandler /* Hash and Rng */ - .long FPU_IRQHandler /* FPU */ - - .size __isr_vector, . - __isr_vector - - .text - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -.LC0: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .LC0 - - ldr r0, =SystemInit - blx r0 - ldr r0, =_start - bx r0 - .pool - .size Reset_Handler, . - Reset_Handler - - .text -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_default_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - .type \handler_name, %function -\handler_name : - b . - .size \handler_name, . - \handler_name - .endm - - def_default_handler NMI_Handler - def_default_handler HardFault_Handler - def_default_handler MemManage_Handler - def_default_handler BusFault_Handler - def_default_handler UsageFault_Handler - def_default_handler SVC_Handler - def_default_handler DebugMon_Handler - def_default_handler PendSV_Handler - def_default_handler SysTick_Handler - def_default_handler Default_Handler - - .macro def_irq_default_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_default_handler WWDG_IRQHandler - def_irq_default_handler PVD_IRQHandler - def_irq_default_handler TAMP_STAMP_IRQHandler - def_irq_default_handler RTC_WKUP_IRQHandler - def_irq_default_handler FLASH_IRQHandler - def_irq_default_handler RCC_IRQHandler - def_irq_default_handler EXTI0_IRQHandler - def_irq_default_handler EXTI1_IRQHandler - def_irq_default_handler EXTI2_IRQHandler - def_irq_default_handler EXTI3_IRQHandler - def_irq_default_handler EXTI4_IRQHandler - def_irq_default_handler DMA1_Stream0_IRQHandler - def_irq_default_handler DMA1_Stream1_IRQHandler - def_irq_default_handler DMA1_Stream2_IRQHandler - def_irq_default_handler DMA1_Stream3_IRQHandler - def_irq_default_handler DMA1_Stream4_IRQHandler - def_irq_default_handler DMA1_Stream5_IRQHandler - def_irq_default_handler DMA1_Stream6_IRQHandler - def_irq_default_handler ADC_IRQHandler - def_irq_default_handler CAN1_TX_IRQHandler - def_irq_default_handler CAN1_RX0_IRQHandler - def_irq_default_handler CAN1_RX1_IRQHandler - def_irq_default_handler CAN1_SCE_IRQHandler - def_irq_default_handler EXTI9_5_IRQHandler - def_irq_default_handler TIM1_BRK_TIM9_IRQHandler - def_irq_default_handler TIM1_UP_TIM10_IRQHandler - def_irq_default_handler TIM1_TRG_COM_TIM11_IRQHandler - def_irq_default_handler TIM1_CC_IRQHandler - def_irq_default_handler TIM2_IRQHandler - def_irq_default_handler TIM3_IRQHandler - def_irq_default_handler TIM4_IRQHandler - def_irq_default_handler I2C1_EV_IRQHandler - def_irq_default_handler I2C1_ER_IRQHandler - def_irq_default_handler I2C2_EV_IRQHandler - def_irq_default_handler I2C2_ER_IRQHandler - def_irq_default_handler SPI1_IRQHandler - def_irq_default_handler SPI2_IRQHandler - def_irq_default_handler USART1_IRQHandler - def_irq_default_handler USART2_IRQHandler - def_irq_default_handler USART3_IRQHandler - def_irq_default_handler EXTI15_10_IRQHandler - def_irq_default_handler RTC_Alarm_IRQHandler - def_irq_default_handler OTG_FS_WKUP_IRQHandler - def_irq_default_handler TIM8_BRK_TIM12_IRQHandler - def_irq_default_handler TIM8_UP_TIM13_IRQHandler - def_irq_default_handler TIM8_TRG_COM_TIM14_IRQHandler - def_irq_default_handler TIM8_CC_IRQHandler - def_irq_default_handler DMA1_Stream7_IRQHandler - def_irq_default_handler FSMC_IRQHandler - def_irq_default_handler SDIO_IRQHandler - def_irq_default_handler TIM5_IRQHandler - def_irq_default_handler SPI3_IRQHandler - def_irq_default_handler UART4_IRQHandler - def_irq_default_handler UART5_IRQHandler - def_irq_default_handler TIM6_DAC_IRQHandler - def_irq_default_handler TIM7_IRQHandler - def_irq_default_handler DMA2_Stream0_IRQHandler - def_irq_default_handler DMA2_Stream1_IRQHandler - def_irq_default_handler DMA2_Stream2_IRQHandler - def_irq_default_handler DMA2_Stream3_IRQHandler - def_irq_default_handler DMA2_Stream4_IRQHandler - def_irq_default_handler ETH_IRQHandler - def_irq_default_handler ETH_WKUP_IRQHandler - def_irq_default_handler CAN2_TX_IRQHandler - def_irq_default_handler CAN2_RX0_IRQHandler - def_irq_default_handler CAN2_RX1_IRQHandler - def_irq_default_handler CAN2_SCE_IRQHandler - def_irq_default_handler OTG_FS_IRQHandler - def_irq_default_handler DMA2_Stream5_IRQHandler - def_irq_default_handler DMA2_Stream6_IRQHandler - def_irq_default_handler DMA2_Stream7_IRQHandler - def_irq_default_handler USART6_IRQHandler - def_irq_default_handler I2C3_EV_IRQHandler - def_irq_default_handler I2C3_ER_IRQHandler - def_irq_default_handler OTG_HS_EP1_OUT_IRQHandler - def_irq_default_handler OTG_HS_EP1_IN_IRQHandler - def_irq_default_handler OTG_HS_WKUP_IRQHandler - def_irq_default_handler OTG_HS_IRQHandler - def_irq_default_handler DCMI_IRQHandler - def_irq_default_handler CRYP_IRQHandler - def_irq_default_handler HASH_RNG_IRQHandler - def_irq_default_handler FPU_IRQHandler - def_irq_default_handler DEF_IRQHandler - - .end
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4XX/TOOLCHAIN_IAR/STM32F407.icf Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,38 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; -define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x20000187; /* Aligned on 8 bytes */ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000188; -define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; -/*-Sizes-*/ -/*Heap 1/4 of ram and stack 1/8*/ -define symbol __ICFEDIT_size_cstack__ = 0x4000; -define symbol __ICFEDIT_size_heap__ = 0x8000; -/**** End of ICF editor section. ###ICF###*/ - -define symbol __region_RAM1_start__ = 0x10000000; -define symbol __region_RAM1_end__ = 0x1000FFFF; - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region RAM1_region = mem:[from __region_RAM1_start__ to __region_RAM1_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram };
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4XX/TOOLCHAIN_IAR/startup_STM32F40x.S Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,636 +0,0 @@ -;/******************** (C) COPYRIGHT 2013 STMicroelectronics ******************** -;* File Name : startup_stm32f40xx.s -;* Author : MCD Application Team -;* Version : V1.2.0RC2 -;* Date : 20-February-2013 -;* Description : STM32F40xx/41xx devices vector table for EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address. -;* - Configure the system clock and the external SRAM mounted on -;* STM324xG-EVAL board to be used as data memory (optional, -;* to be enabled by user) -;* - Branches to main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* -;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); -;* You may not use this file except in compliance with the License. -;* You may obtain a copy of the License at: -;* -;* http://www.st.com/software_license_agreement_liberty_v2 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;* -;*******************************************************************************/ -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD CRYP_IRQHandler ; CRYP crypto - DCD HASH_RNG_IRQHandler ; Hash and Rng - DCD FPU_IRQHandler ; FPU - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - PUBWEAK PVD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PVD_IRQHandler - B PVD_IRQHandler - - PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TAMP_STAMP_IRQHandler - B TAMP_STAMP_IRQHandler - - PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_WKUP_IRQHandler - B RTC_WKUP_IRQHandler - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RCC_IRQHandler - B RCC_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream0_IRQHandler - B DMA1_Stream0_IRQHandler - - PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream1_IRQHandler - B DMA1_Stream1_IRQHandler - - PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream2_IRQHandler - B DMA1_Stream2_IRQHandler - - PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream3_IRQHandler - B DMA1_Stream3_IRQHandler - - PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream4_IRQHandler - B DMA1_Stream4_IRQHandler - - PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream5_IRQHandler - B DMA1_Stream5_IRQHandler - - PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream6_IRQHandler - B DMA1_Stream6_IRQHandler - - PUBWEAK ADC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC_IRQHandler - B ADC_IRQHandler - - PUBWEAK CAN1_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_TX_IRQHandler - B CAN1_TX_IRQHandler - - PUBWEAK CAN1_RX0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_RX0_IRQHandler - B CAN1_RX0_IRQHandler - - PUBWEAK CAN1_RX1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_RX1_IRQHandler - B CAN1_RX1_IRQHandler - - PUBWEAK CAN1_SCE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_SCE_IRQHandler - B CAN1_SCE_IRQHandler - - PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI9_5_IRQHandler - B EXTI9_5_IRQHandler - - PUBWEAK TIM1_BRK_TIM9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_BRK_TIM9_IRQHandler - B TIM1_BRK_TIM9_IRQHandler - - PUBWEAK TIM1_UP_TIM10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_UP_TIM10_IRQHandler - B TIM1_UP_TIM10_IRQHandler - - PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_TRG_COM_TIM11_IRQHandler - B TIM1_TRG_COM_TIM11_IRQHandler - - PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_CC_IRQHandler - B TIM1_CC_IRQHandler - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - PUBWEAK TIM4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM4_IRQHandler - B TIM4_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_EV_IRQHandler - B I2C2_EV_IRQHandler - - PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_ER_IRQHandler - B I2C2_ER_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK USART3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART3_IRQHandler - B USART3_IRQHandler - - PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI15_10_IRQHandler - B EXTI15_10_IRQHandler - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_FS_WKUP_IRQHandler - B OTG_FS_WKUP_IRQHandler - - PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_BRK_TIM12_IRQHandler - B TIM8_BRK_TIM12_IRQHandler - - PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_UP_TIM13_IRQHandler - B TIM8_UP_TIM13_IRQHandler - - PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_TRG_COM_TIM14_IRQHandler - B TIM8_TRG_COM_TIM14_IRQHandler - - PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_CC_IRQHandler - B TIM8_CC_IRQHandler - - PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream7_IRQHandler - B DMA1_Stream7_IRQHandler - - PUBWEAK FSMC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FSMC_IRQHandler - B FSMC_IRQHandler - - PUBWEAK SDIO_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SDIO_IRQHandler - B SDIO_IRQHandler - - PUBWEAK TIM5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM5_IRQHandler - B TIM5_IRQHandler - - PUBWEAK SPI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI3_IRQHandler - B SPI3_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART4_IRQHandler - B UART4_IRQHandler - - PUBWEAK UART5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART5_IRQHandler - B UART5_IRQHandler - - PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM6_DAC_IRQHandler - B TIM6_DAC_IRQHandler - - PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM7_IRQHandler - B TIM7_IRQHandler - - PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream0_IRQHandler - B DMA2_Stream0_IRQHandler - - PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream1_IRQHandler - B DMA2_Stream1_IRQHandler - - PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream2_IRQHandler - B DMA2_Stream2_IRQHandler - - PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream3_IRQHandler - B DMA2_Stream3_IRQHandler - - PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream4_IRQHandler - B DMA2_Stream4_IRQHandler - - PUBWEAK ETH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ETH_IRQHandler - B ETH_IRQHandler - - PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ETH_WKUP_IRQHandler - B ETH_WKUP_IRQHandler - - PUBWEAK CAN2_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_TX_IRQHandler - B CAN2_TX_IRQHandler - - PUBWEAK CAN2_RX0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_RX0_IRQHandler - B CAN2_RX0_IRQHandler - - PUBWEAK CAN2_RX1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_RX1_IRQHandler - B CAN2_RX1_IRQHandler - - PUBWEAK CAN2_SCE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_SCE_IRQHandler - B CAN2_SCE_IRQHandler - - PUBWEAK OTG_FS_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_FS_IRQHandler - B OTG_FS_IRQHandler - - PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream5_IRQHandler - B DMA2_Stream5_IRQHandler - - PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream6_IRQHandler - B DMA2_Stream6_IRQHandler - - PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream7_IRQHandler - B DMA2_Stream7_IRQHandler - - PUBWEAK USART6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART6_IRQHandler - B USART6_IRQHandler - - PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C3_EV_IRQHandler - B I2C3_EV_IRQHandler - - PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C3_ER_IRQHandler - B I2C3_ER_IRQHandler - - PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_EP1_OUT_IRQHandler - B OTG_HS_EP1_OUT_IRQHandler - - PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_EP1_IN_IRQHandler - B OTG_HS_EP1_IN_IRQHandler - - PUBWEAK OTG_HS_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_WKUP_IRQHandler - B OTG_HS_WKUP_IRQHandler - - PUBWEAK OTG_HS_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_IRQHandler - B OTG_HS_IRQHandler - - PUBWEAK DCMI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DCMI_IRQHandler - B DCMI_IRQHandler - - PUBWEAK CRYP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CRYP_IRQHandler - B CRYP_IRQHandler - - PUBWEAK HASH_RNG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -HASH_RNG_IRQHandler - B HASH_RNG_IRQHandler - - PUBWEAK FPU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FPU_IRQHandler - B FPU_IRQHandler - - END -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4XX/cmsis.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,14 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in STM32F407 specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "stm32f4xx.h" -#include "cmsis_nvic.h" - -#endif -
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4XX/cmsis_nvic.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,33 +0,0 @@ -/* mbed Microcontroller Library - cmsis_nvic for STM32F4 - * Copyright (c) 2009-2011 ARM Limited. All rights reserved. - * - * CMSIS-style functionality to support dynamic vectors - */ -#include "cmsis_nvic.h" - -#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM - -static unsigned char vtor_relocated; - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { - uint32_t *vectors = (uint32_t*)SCB->VTOR; - uint32_t i; - - // Copy and switch to dynamic vectors if the first time called - if (!vtor_relocated) { - uint32_t *old_vectors = vectors; - vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; - for (i=0; i<NVIC_NUM_VECTORS; i++) { - vectors[i] = old_vectors[i]; - } - SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; - vtor_relocated = 1; - } - vectors[IRQn + 16] = vector; -} - -uint32_t NVIC_GetVector(IRQn_Type IRQn) { - uint32_t *vectors = (uint32_t*)SCB->VTOR; - return vectors[IRQn + 16]; -} -
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4XX/cmsis_nvic.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,26 +0,0 @@ -/* mbed Microcontroller Library - cmsis_nvic - * Copyright (c) 2009-2011 ARM Limited. All rights reserved. - * - * CMSIS-style functionality to support dynamic vectors - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#define NVIC_NUM_VECTORS (16 + 82) // CORE + MCU Peripherals -#define NVIC_USER_IRQ_OFFSET 16 - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); -uint32_t NVIC_GetVector(IRQn_Type IRQn); - -#ifdef __cplusplus -} -#endif - -#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4XX/stm32f4xx.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,7155 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx.h - * @author MCD Application Team - * @version V1.1.0 - * @date 11-January-2013 - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32F4xx devices. - * - * The file is the unique include file that the application programmer - * is using in the C source code, usually in main.c. This file contains: - * - Configuration section that allows to select: - * - The device used in the target application - * - To use or not the peripheral's drivers in application code(i.e. - * code will be based on direct access to peripheral's registers - * rather than drivers API), this option is controlled by - * "#define USE_STDPERIPH_DRIVER" - * - To change few application-specific parameters such as the HSE - * crystal frequency - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral's registers hardware - * - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f4xx - * @{ - */ - -#ifndef __STM32F4xx_H -#define __STM32F4xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/* Uncomment the line below according to the target STM32 device used in your - application - */ - -#if !defined (STM32F4XX) && !defined (STM32F40XX) && !defined (STM32F427X) - #define STM32F40XX /*!< STM32F40xx/41xx Devices */ - /* #define STM32F427X */ /*!< STM32F427x/437x Devices*/ -#endif - - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ - -#if !defined (STM32F4XX) && !defined (STM32F40XX) && !defined (STM32F427X) - #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" -#endif - -#if !defined (USE_STDPERIPH_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_STDPERIPH_DRIVER */ -#endif /* USE_STDPERIPH_DRIVER */ - -/** - * @brief In the following line adjust the value of External High Speed oscillator (HSE) - used in your application - - Tip: To avoid modifying this file each time you need to use different HSE, you - can define the HSE value in your toolchain compiler preprocessor. - */ - -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - Timeout value - */ -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ -#endif /* HSE_STARTUP_TIMEOUT */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief STM32F4XX Standard Peripherals Library version number V1.1.0 - */ -#define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ -#define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\ - |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\ - |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\ - |(__STM32F4XX_STDPERIPH_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ -#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ - -/** - * @brief STM32F4XX Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum IRQn -{ -/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ -/****** STM32 specific Interrupt Numbers **********************************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ - DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ - DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ - DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ - DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ - DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ - DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ - ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ - OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ - OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ - OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - DCMI_IRQn = 78, /*!< DCMI global interrupt */ - CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ - HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ - -#ifdef STM32F40XX - FPU_IRQn = 81 /*!< FPU global interrupt */ -#endif /* STM32F40XX */ - -#ifdef STM32F427X - FPU_IRQn = 81, /*!< FPU global interrupt */ - UART7_IRQn = 82, /*!< UART7 global interrupt */ - UART8_IRQn = 83, /*!< UART8 global interrupt */ - SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ - SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ - SPI6_IRQn = 86 /*!< SPI6 global Interrupt */ -#endif /* STM32F427X */ - -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ -#include "system_stm32f4xx.h" -#include <stdint.h> - -/** @addtogroup Exported_types - * @{ - */ -/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef const int32_t sc32; /*!< Read Only */ -typedef const int16_t sc16; /*!< Read Only */ -typedef const int8_t sc8; /*!< Read Only */ - -typedef __IO int32_t vs32; -typedef __IO int16_t vs16; -typedef __IO int8_t vs8; - -typedef __I int32_t vsc32; /*!< Read Only */ -typedef __I int16_t vsc16; /*!< Read Only */ -typedef __I int8_t vsc8; /*!< Read Only */ - -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef const uint32_t uc32; /*!< Read Only */ -typedef const uint16_t uc16; /*!< Read Only */ -typedef const uint8_t uc8; /*!< Read Only */ - -typedef __IO uint32_t vu32; -typedef __IO uint16_t vu16; -typedef __IO uint8_t vu8; - -typedef __I uint32_t vuc32; /*!< Read Only */ -typedef __I uint16_t vuc16; /*!< Read Only */ -typedef __I uint8_t vuc8; /*!< Read Only */ - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -/** - * @} - */ - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ - __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ - __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ - __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ - __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ - __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ - __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual - AND triple modes, Address offset: ADC1 base address + 0x308 */ -} ADC_Common_TypeDef; - - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ - __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ - __IO uint32_t TDLR; /*!< CAN mailbox data low register */ - __IO uint32_t TDHR; /*!< CAN mailbox data high register */ -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ - __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ - __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ - __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ - __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ - __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ - __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ - __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ - __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ - __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ - __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ - __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ - uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ - CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ - uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ - __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ - __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ - uint32_t RESERVED2; /*!< Reserved, 0x208 */ - __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ - uint32_t RESERVED3; /*!< Reserved, 0x210 */ - __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ - uint32_t RESERVED4; /*!< Reserved, 0x218 */ - __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ - CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ -} CAN_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, 0x05 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DCMI - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ - __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ - __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ - __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ - __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ - __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ - __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ - __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ - __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ - __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ - __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ -} DCMI_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DMA stream x configuration register */ - __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ - __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ -} DMA_Stream_TypeDef; - -typedef struct -{ - __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ - __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ - __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ - __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ -} DMA_TypeDef; - -/** - * @brief Ethernet MAC - */ - -typedef struct -{ - __IO uint32_t MACCR; - __IO uint32_t MACFFR; - __IO uint32_t MACHTHR; - __IO uint32_t MACHTLR; - __IO uint32_t MACMIIAR; - __IO uint32_t MACMIIDR; - __IO uint32_t MACFCR; - __IO uint32_t MACVLANTR; /* 8 */ - uint32_t RESERVED0[2]; - __IO uint32_t MACRWUFFR; /* 11 */ - __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; - __IO uint32_t MACSR; /* 15 */ - __IO uint32_t MACIMR; - __IO uint32_t MACA0HR; - __IO uint32_t MACA0LR; - __IO uint32_t MACA1HR; - __IO uint32_t MACA1LR; - __IO uint32_t MACA2HR; - __IO uint32_t MACA2LR; - __IO uint32_t MACA3HR; - __IO uint32_t MACA3LR; /* 24 */ - uint32_t RESERVED2[40]; - __IO uint32_t MMCCR; /* 65 */ - __IO uint32_t MMCRIR; - __IO uint32_t MMCTIR; - __IO uint32_t MMCRIMR; - __IO uint32_t MMCTIMR; /* 69 */ - uint32_t RESERVED3[14]; - __IO uint32_t MMCTGFSCCR; /* 84 */ - __IO uint32_t MMCTGFMSCCR; - uint32_t RESERVED4[5]; - __IO uint32_t MMCTGFCR; - uint32_t RESERVED5[10]; - __IO uint32_t MMCRFCECR; - __IO uint32_t MMCRFAECR; - uint32_t RESERVED6[10]; - __IO uint32_t MMCRGUFCR; - uint32_t RESERVED7[334]; - __IO uint32_t PTPTSCR; - __IO uint32_t PTPSSIR; - __IO uint32_t PTPTSHR; - __IO uint32_t PTPTSLR; - __IO uint32_t PTPTSHUR; - __IO uint32_t PTPTSLUR; - __IO uint32_t PTPTSAR; - __IO uint32_t PTPTTHR; - __IO uint32_t PTPTTLR; - __IO uint32_t RESERVED8; - __IO uint32_t PTPTSSR; - uint32_t RESERVED9[565]; - __IO uint32_t DMABMR; - __IO uint32_t DMATPDR; - __IO uint32_t DMARPDR; - __IO uint32_t DMARDLAR; - __IO uint32_t DMATDLAR; - __IO uint32_t DMASR; - __IO uint32_t DMAOMR; - __IO uint32_t DMAIER; - __IO uint32_t DMAMFBOCR; - __IO uint32_t DMARSWTR; - uint32_t RESERVED10[8]; - __IO uint32_t DMACHTDR; - __IO uint32_t DMACHRDR; - __IO uint32_t DMACHTBAR; - __IO uint32_t DMACHRBAR; -} ETH_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ - __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ - __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ - __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ - __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ -} FLASH_TypeDef; - -/** - * @brief Flexible Static Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FSMC_Bank1_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ -} FSMC_Bank1E_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank2 - */ - -typedef struct -{ - __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ - __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ - __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ - __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ - uint32_t RESERVED0; /*!< Reserved, 0x70 */ - __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ -} FSMC_Bank2_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank3 - */ - -typedef struct -{ - __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ - __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ - __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ - __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ - uint32_t RESERVED0; /*!< Reserved, 0x90 */ - __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ -} FSMC_Bank3_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank4 - */ - -typedef struct -{ - __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ - __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ - __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ - __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ - __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ -} FSMC_Bank4_TypeDef; - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ - __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ -} GPIO_TypeDef; - -/** - * @brief System configuration controller - */ - -typedef struct -{ - __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ - __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ - __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ - uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ - __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ -} SYSCFG_TypeDef; - -/** - * @brief Inter-integrated Circuit Interface - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ - __IO uint16_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ - uint16_t RESERVED9; /*!< Reserved, 0x26 */ -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ - __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ -} IWDG_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ - __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ - __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ - __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ - __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ - __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ - __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ - __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ - uint32_t RESERVED0; /*!< Reserved, 0x1C */ - __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ - __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ - __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ - __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ - __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ - uint32_t RESERVED2; /*!< Reserved, 0x3C */ - __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ - __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ - uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ - __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ - __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ - __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ - uint32_t RESERVED4; /*!< Reserved, 0x5C */ - __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ - __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ - uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ - __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ - __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ - uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ - __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ - __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ - -#ifdef STM32F427X - uint32_t RESERVED7; /*!< Reserved, 0x88 */ - __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */ -#endif /* STM32F427X */ - -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ - uint32_t RESERVED7; /*!< Reserved, 0x4C */ - __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ - __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ - __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ - __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ - __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ - __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ - __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ - __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ - __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ - __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ - __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ - __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ - __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ - __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ - __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ - __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ - __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ - __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ - __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ - __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ -} RTC_TypeDef; - -/** - * @brief SD host Interface - */ - -typedef struct -{ - __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ - __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ - __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ - __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ - __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ - __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ - __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ - __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ - __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ - __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ - __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ - __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ - __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ - __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ - __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ - __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ - uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ - __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ - uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ - __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ -} SDIO_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ -} SPI_TypeDef; - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - uint16_t RESERVED11; /*!< Reserved, 0x46 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ - uint16_t RESERVED14; /*!< Reserved, 0x52 */ -} TIM_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ -} USART_TypeDef; - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ - __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ -} WWDG_TypeDef; - -/** - * @brief Crypto Processor - */ - -typedef struct -{ - __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ - __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ - __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ - __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ - __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ - __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ - __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ - __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ - __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ - __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ - __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ - __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ - __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ - __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ - __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ - __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ - __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ - __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ - __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */ - __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */ - __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */ - __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */ - __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */ - __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */ - __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */ - __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */ - __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */ - __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */ - __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */ - __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */ - __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */ - __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */ - __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */ - __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */ -} CRYP_TypeDef; - -/** - * @brief HASH - */ - -typedef struct -{ - __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ - __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ - __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ - __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ - __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ - __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ - uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ - __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ -} HASH_TypeDef; - -/** - * @brief HASH_DIGEST - */ - -typedef struct -{ - __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ -} HASH_DIGEST_TypeDef; - -/** - * @brief RNG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ -} RNG_TypeDef; - -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */ -#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ -#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */ -#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ -#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ -#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ -#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ - -#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */ -#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ -#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */ -#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ -#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ - -/* Legacy defines */ -#define SRAM_BASE SRAM1_BASE -#define SRAM_BB_BASE SRAM1_BB_BASE - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) - -/*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) -#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) -#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) -#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) -#define UART7_BASE (APB1PERIPH_BASE + 0x7800) -#define UART8_BASE (APB1PERIPH_BASE + 0x7C00) - -/*!< APB2 peripherals */ -#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) -#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) -#define USART1_BASE (APB2PERIPH_BASE + 0x1000) -#define USART6_BASE (APB2PERIPH_BASE + 0x1400) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) -#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) -#define ADC_BASE (APB2PERIPH_BASE + 0x2300) -#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define SPI4_BASE (APB2PERIPH_BASE + 0x3400) -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) -#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) -#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) -#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) -#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) -#define SPI5_BASE (APB2PERIPH_BASE + 0x5000) -#define SPI6_BASE (APB2PERIPH_BASE + 0x5400) - -/*!< AHB1 peripherals */ -#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) -#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) -#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) -#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) -#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) -#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) -#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) -#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) -#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) - -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) -#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) -#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) -#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) -#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) -#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) -#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) -#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) -#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) -#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) -#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) -#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) -#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) -#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) -#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) -#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) -#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) -#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) -#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) -#define ETH_BASE (AHB1PERIPH_BASE + 0x8000) -#define ETH_MAC_BASE (ETH_BASE) -#define ETH_MMC_BASE (ETH_BASE + 0x0100) -#define ETH_PTP_BASE (ETH_BASE + 0x0700) -#define ETH_DMA_BASE (ETH_BASE + 0x1000) - -/*!< AHB2 peripherals */ -#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) -#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) -#define HASH_BASE (AHB2PERIPH_BASE + 0x60400) -#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710) -#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) - -/*!< FSMC Bankx registers base address */ -#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) -#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) -#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) -#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) -#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) - -/* Debug MCU registers base address */ -#define DBGMCU_BASE ((uint32_t )0xE0042000) - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define TIM12 ((TIM_TypeDef *) TIM12_BASE) -#define TIM13 ((TIM_TypeDef *) TIM13_BASE) -#define TIM14 ((TIM_TypeDef *) TIM14_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define I2C3 ((I2C_TypeDef *) I2C3_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define UART7 ((USART_TypeDef *) UART7_BASE) -#define UART8 ((USART_TypeDef *) UART8_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define USART6 ((USART_TypeDef *) USART6_BASE) -#define ADC ((ADC_Common_TypeDef *) ADC_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define SPI4 ((SPI_TypeDef *) SPI4_BASE) -#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) -#define SPI5 ((SPI_TypeDef *) SPI5_BASE) -#define SPI6 ((SPI_TypeDef *) SPI6_BASE) - -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) -#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) - -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) -#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) -#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) -#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) -#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) -#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) -#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) -#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) -#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) -#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) -#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) -#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) -#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) -#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) -#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) -#define DCMI ((DCMI_TypeDef *) DCMI_BASE) -#define CRYP ((CRYP_TypeDef *) CRYP_BASE) -#define HASH ((HASH_TypeDef *) HASH_BASE) -#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE) -#define RNG ((RNG_TypeDef *) RNG_BASE) -#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) -#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) -#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) -#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) -#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter */ -/* */ -/******************************************************************************/ -/******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD ((uint8_t)0x01) /*!<Analog watchdog flag */ -#define ADC_SR_EOC ((uint8_t)0x02) /*!<End of conversion */ -#define ADC_SR_JEOC ((uint8_t)0x04) /*!<Injected channel end of conversion */ -#define ADC_SR_JSTRT ((uint8_t)0x08) /*!<Injected channel Start flag */ -#define ADC_SR_STRT ((uint8_t)0x10) /*!<Regular channel Start flag */ -#define ADC_SR_OVR ((uint8_t)0x20) /*!<Overrun flag */ - -/******************* Bit definition for ADC_CR1 register ********************/ -#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */ -#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */ -#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */ -#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */ -#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */ -#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */ -#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */ -#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */ -#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */ -#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */ -#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */ -#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */ -#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */ -#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */ -#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */ -#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */ -#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */ -#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */ -#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */ -#define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */ -#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */ -#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */ -#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */ - -/******************* Bit definition for ADC_CR2 register ********************/ -#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */ -#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */ -#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */ -#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */ -#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */ -#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */ -#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */ -#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */ -#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */ -#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */ -#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */ -#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */ -#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */ -#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */ -#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */ -#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */ -#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */ -#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */ -#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */ -#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */ -#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */ -#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */ -#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */ -#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */ - -/****************** Bit definition for ADC_SMPR1 register *******************/ -#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */ -#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */ -#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */ -#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */ -#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */ -#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */ -#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */ -#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */ -#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */ -#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */ -#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */ -#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */ -#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */ -#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */ -#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */ -#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */ -#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */ -#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */ -#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */ -#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */ -#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */ -#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */ -#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */ -#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */ -#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */ -#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */ -#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */ -#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */ -#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */ -#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */ -#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */ -#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */ -#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */ -#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */ -#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */ -#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */ - -/****************** Bit definition for ADC_SMPR2 register *******************/ -#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */ -#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */ -#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */ -#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */ -#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */ -#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */ -#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */ -#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */ -#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */ -#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */ -#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */ -#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */ -#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */ -#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */ -#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */ -#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */ -#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */ -#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */ -#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */ -#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */ -#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */ -#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */ -#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */ -#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */ -#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */ -#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */ -#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */ -#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */ -#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */ -#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */ -#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */ -#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */ -#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */ -#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */ -#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */ -#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */ -#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */ -#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */ -#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */ - -/****************** Bit definition for ADC_JOFR1 register *******************/ -#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 1 */ - -/****************** Bit definition for ADC_JOFR2 register *******************/ -#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 2 */ - -/****************** Bit definition for ADC_JOFR3 register *******************/ -#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 3 */ - -/****************** Bit definition for ADC_JOFR4 register *******************/ -#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 4 */ - -/******************* Bit definition for ADC_HTR register ********************/ -#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!<Analog watchdog high threshold */ - -/******************* Bit definition for ADC_LTR register ********************/ -#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!<Analog watchdog low threshold */ - -/******************* Bit definition for ADC_SQR1 register *******************/ -#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */ -#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */ -#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */ -#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */ -#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */ -#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */ -#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */ -#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */ -#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */ -#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */ -#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */ -#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */ -#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */ -#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */ -#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */ -#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */ -#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */ -#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */ -#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */ -#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */ -#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */ -#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */ -#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */ -#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */ -#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */ -#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */ -#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */ -#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */ -#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */ - -/******************* Bit definition for ADC_SQR2 register *******************/ -#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */ -#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */ -#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */ -#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */ -#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */ -#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */ -#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */ -#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */ -#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */ -#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */ -#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */ -#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */ -#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */ -#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */ -#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */ -#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */ -#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */ -#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */ -#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */ -#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */ -#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */ -#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */ -#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */ -#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */ -#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */ -#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */ -#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */ -#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */ -#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */ -#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */ -#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */ -#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */ -#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */ -#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */ -#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */ -#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */ - -/******************* Bit definition for ADC_SQR3 register *******************/ -#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */ -#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */ -#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */ -#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */ -#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */ -#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */ -#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */ -#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */ -#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */ -#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */ -#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */ -#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */ -#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */ -#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */ -#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */ -#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */ -#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */ -#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */ -#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */ -#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */ -#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */ -#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */ -#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */ -#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */ -#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */ -#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */ -#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */ -#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */ -#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */ -#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */ -#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */ -#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */ -#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */ -#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */ -#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */ -#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */ - -/******************* Bit definition for ADC_JSQR register *******************/ -#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */ -#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */ -#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */ -#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */ -#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */ -#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */ -#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */ -#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */ -#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */ -#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */ -#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */ -#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */ -#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */ -#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */ -#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */ -#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */ -#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */ -#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */ -#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */ -#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */ -#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */ -#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */ -#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */ -#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */ -#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */ -#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */ -#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */ - -/******************* Bit definition for ADC_JDR1 register *******************/ -#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */ - -/******************* Bit definition for ADC_JDR2 register *******************/ -#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */ - -/******************* Bit definition for ADC_JDR3 register *******************/ -#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */ - -/******************* Bit definition for ADC_JDR4 register *******************/ -#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */ - -/******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */ -#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */ - -/******************* Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */ -#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */ -#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */ -#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */ -#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */ -#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */ -#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */ -#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */ -#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */ -#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */ -#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */ -#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */ -#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */ -#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */ -#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */ -#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */ -#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */ -#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */ - -/******************* Bit definition for ADC_CCR register ********************/ -#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */ -#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */ -#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */ -#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */ -#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */ -#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */ -#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */ -#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */ -#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */ -#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */ -#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */ -#define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */ -#define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */ -#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */ -#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */ -#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */ -#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */ -#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */ -#define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */ -#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */ - -/******************* Bit definition for ADC_CDR register ********************/ -#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */ -#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */ - -/******************************************************************************/ -/* */ -/* Controller Area Network */ -/* */ -/******************************************************************************/ -/*!<CAN control and status registers */ -/******************* Bit definition for CAN_MCR register ********************/ -#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */ -#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */ -#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */ -#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */ -#define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */ -#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */ -#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */ -#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */ -#define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */ - -/******************* Bit definition for CAN_MSR register ********************/ -#define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */ -#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */ -#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */ -#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */ -#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */ -#define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */ -#define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */ -#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */ -#define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */ - -/******************* Bit definition for CAN_TSR register ********************/ -#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */ -#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */ -#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */ -#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */ -#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */ -#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */ -#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */ -#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */ -#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */ -#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */ -#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */ -#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */ -#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */ -#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */ -#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */ -#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */ - -#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */ -#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */ -#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */ -#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */ - -#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */ -#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */ -#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */ -#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */ - -/******************* Bit definition for CAN_RF0R register *******************/ -#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */ -#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */ -#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */ -#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */ - -/******************* Bit definition for CAN_RF1R register *******************/ -#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */ -#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */ -#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */ -#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */ - -/******************** Bit definition for CAN_IER register *******************/ -#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */ -#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */ -#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */ -#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */ -#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */ -#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */ -#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */ -#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */ -#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */ -#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */ -#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */ -#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */ -#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */ -#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */ - -/******************** Bit definition for CAN_ESR register *******************/ -#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */ -#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */ -#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */ - -#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */ -#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */ -#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */ -#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */ - -#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */ -#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */ - -/******************* Bit definition for CAN_BTR register ********************/ -#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */ -#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */ -#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */ -#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */ -#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */ -#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */ - -/*!<Mailbox registers */ -/****************** Bit definition for CAN_TI0R register ********************/ -#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ -#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ -#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ -#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ -#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ - -/****************** Bit definition for CAN_TDT0R register *******************/ -#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ -#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ -#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ - -/****************** Bit definition for CAN_TDL0R register *******************/ -#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ -#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ -#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ -#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ - -/****************** Bit definition for CAN_TDH0R register *******************/ -#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ -#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ -#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ -#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ - -/******************* Bit definition for CAN_TI1R register *******************/ -#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ -#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ -#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ -#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ -#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_TDT1R register ******************/ -#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ -#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ -#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ - -/******************* Bit definition for CAN_TDL1R register ******************/ -#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ -#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ -#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ -#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ - -/******************* Bit definition for CAN_TDH1R register ******************/ -#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ -#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ -#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ -#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ - -/******************* Bit definition for CAN_TI2R register *******************/ -#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ -#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ -#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ -#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */ -#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_TDT2R register ******************/ -#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ -#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ -#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ - -/******************* Bit definition for CAN_TDL2R register ******************/ -#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ -#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ -#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ -#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ - -/******************* Bit definition for CAN_TDH2R register ******************/ -#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ -#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ -#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ -#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ - -/******************* Bit definition for CAN_RI0R register *******************/ -#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ -#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ -#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ -#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_RDT0R register ******************/ -#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ -#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */ -#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ - -/******************* Bit definition for CAN_RDL0R register ******************/ -#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ -#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ -#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ -#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ - -/******************* Bit definition for CAN_RDH0R register ******************/ -#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ -#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ -#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ -#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ - -/******************* Bit definition for CAN_RI1R register *******************/ -#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ -#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ -#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */ -#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ - -/******************* Bit definition for CAN_RDT1R register ******************/ -#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ -#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */ -#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ - -/******************* Bit definition for CAN_RDL1R register ******************/ -#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ -#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ -#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ -#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ - -/******************* Bit definition for CAN_RDH1R register ******************/ -#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ -#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ -#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ -#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ - -/*!<CAN filter registers */ -/******************* Bit definition for CAN_FMR register ********************/ -#define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */ - -/******************* Bit definition for CAN_FM1R register *******************/ -#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */ -#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */ -#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */ -#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */ -#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */ -#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */ -#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */ -#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */ -#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */ -#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */ -#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */ -#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */ -#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */ -#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */ -#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */ - -/******************* Bit definition for CAN_FS1R register *******************/ -#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */ -#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */ -#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */ -#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */ -#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */ -#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */ -#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */ -#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */ -#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */ -#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */ -#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */ -#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */ -#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */ -#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */ -#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */ - -/****************** Bit definition for CAN_FFA1R register *******************/ -#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */ -#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */ -#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */ -#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */ -#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */ -#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */ -#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */ -#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */ -#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */ -#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */ -#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */ -#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */ -#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */ -#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */ -#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */ - -/******************* Bit definition for CAN_FA1R register *******************/ -#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */ -#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */ -#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */ -#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */ -#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */ -#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */ -#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */ -#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */ -#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */ -#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */ -#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */ -#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */ -#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */ -#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */ -#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */ - -/******************* Bit definition for CAN_F0R1 register *******************/ -#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F1R1 register *******************/ -#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F2R1 register *******************/ -#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F3R1 register *******************/ -#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F4R1 register *******************/ -#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F5R1 register *******************/ -#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F6R1 register *******************/ -#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F7R1 register *******************/ -#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F8R1 register *******************/ -#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F9R1 register *******************/ -#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F10R1 register ******************/ -#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F11R1 register ******************/ -#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F12R1 register ******************/ -#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F13R1 register ******************/ -#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F0R2 register *******************/ -#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F1R2 register *******************/ -#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F2R2 register *******************/ -#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F3R2 register *******************/ -#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F4R2 register *******************/ -#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F5R2 register *******************/ -#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F6R2 register *******************/ -#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F7R2 register *******************/ -#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F8R2 register *******************/ -#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F9R2 register *******************/ -#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F10R2 register ******************/ -#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F11R2 register ******************/ -#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F12R2 register ******************/ -#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************* Bit definition for CAN_F13R2 register ******************/ -#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ -#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ -#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ -#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ -#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ -#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ -#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ -#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ -#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ -#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ -#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ -#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ -#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ -#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ -#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ -#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ -#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ -#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ -#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ -#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ -#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ -#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ -#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ -#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ -#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ -#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ -#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ -#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ -#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ -#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ -#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ -#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ - -/******************************************************************************/ -/* */ -/* CRC calculation unit */ -/* */ -/******************************************************************************/ -/******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ - - -/******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ - - -/******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ - -/******************************************************************************/ -/* */ -/* Crypto Processor */ -/* */ -/******************************************************************************/ -/******************* Bits definition for CRYP_CR register ********************/ -#define CRYP_CR_ALGODIR ((uint32_t)0x00000004) - -#define CRYP_CR_ALGOMODE ((uint32_t)0x00080038) -#define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008) -#define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010) -#define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020) -#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000) -#define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008) -#define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010) -#define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018) -#define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020) -#define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028) -#define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030) -#define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038) - -#define CRYP_CR_DATATYPE ((uint32_t)0x000000C0) -#define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040) -#define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080) -#define CRYP_CR_KEYSIZE ((uint32_t)0x00000300) -#define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100) -#define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200) -#define CRYP_CR_FFLUSH ((uint32_t)0x00004000) -#define CRYP_CR_CRYPEN ((uint32_t)0x00008000) - -#define CRYP_CR_GCM_CCMPH ((uint32_t)0x00030000) -#define CRYP_CR_GCM_CCMPH_0 ((uint32_t)0x00010000) -#define CRYP_CR_GCM_CCMPH_1 ((uint32_t)0x00020000) -#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000) - -/****************** Bits definition for CRYP_SR register *********************/ -#define CRYP_SR_IFEM ((uint32_t)0x00000001) -#define CRYP_SR_IFNF ((uint32_t)0x00000002) -#define CRYP_SR_OFNE ((uint32_t)0x00000004) -#define CRYP_SR_OFFU ((uint32_t)0x00000008) -#define CRYP_SR_BUSY ((uint32_t)0x00000010) -/****************** Bits definition for CRYP_DMACR register ******************/ -#define CRYP_DMACR_DIEN ((uint32_t)0x00000001) -#define CRYP_DMACR_DOEN ((uint32_t)0x00000002) -/***************** Bits definition for CRYP_IMSCR register ******************/ -#define CRYP_IMSCR_INIM ((uint32_t)0x00000001) -#define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002) -/****************** Bits definition for CRYP_RISR register *******************/ -#define CRYP_RISR_OUTRIS ((uint32_t)0x00000001) -#define CRYP_RISR_INRIS ((uint32_t)0x00000002) -/****************** Bits definition for CRYP_MISR register *******************/ -#define CRYP_MISR_INMIS ((uint32_t)0x00000001) -#define CRYP_MISR_OUTMIS ((uint32_t)0x00000002) - -/******************************************************************************/ -/* */ -/* Digital to Analog Converter */ -/* */ -/******************************************************************************/ -/******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */ -#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */ -#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */ - -#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */ -#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */ -#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */ -#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */ - -#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */ -#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */ - -#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ -#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */ -#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */ -#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */ -#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */ - -#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */ -#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */ -#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */ -#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */ - -#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */ -#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */ -#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */ -#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */ - -#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */ -#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */ - -#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ -#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */ -#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */ -#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */ -#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */ - -#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */ - -/***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */ -#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */ - -/***************** Bit definition for DAC_DHR12R1 register ******************/ -#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12L1 register ******************/ -#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DHR8R1 register ******************/ -#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12R2 register ******************/ -#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12L2 register ******************/ -#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DHR8R2 register ******************/ -#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12RD register ******************/ -#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */ -#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */ - -/***************** Bit definition for DAC_DHR12LD register ******************/ -#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */ -#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DHR8RD register ******************/ -#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */ -#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */ - -/******************* Bit definition for DAC_DOR1 register *******************/ -#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */ - -/******************* Bit definition for DAC_DOR2 register *******************/ -#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */ - -/******************** Bit definition for DAC_SR register ********************/ -#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */ -#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */ - -/******************************************************************************/ -/* */ -/* Debug MCU */ -/* */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* DCMI */ -/* */ -/******************************************************************************/ -/******************** Bits definition for DCMI_CR register ******************/ -#define DCMI_CR_CAPTURE ((uint32_t)0x00000001) -#define DCMI_CR_CM ((uint32_t)0x00000002) -#define DCMI_CR_CROP ((uint32_t)0x00000004) -#define DCMI_CR_JPEG ((uint32_t)0x00000008) -#define DCMI_CR_ESS ((uint32_t)0x00000010) -#define DCMI_CR_PCKPOL ((uint32_t)0x00000020) -#define DCMI_CR_HSPOL ((uint32_t)0x00000040) -#define DCMI_CR_VSPOL ((uint32_t)0x00000080) -#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100) -#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200) -#define DCMI_CR_EDM_0 ((uint32_t)0x00000400) -#define DCMI_CR_EDM_1 ((uint32_t)0x00000800) -#define DCMI_CR_CRE ((uint32_t)0x00001000) -#define DCMI_CR_ENABLE ((uint32_t)0x00004000) - -/******************** Bits definition for DCMI_SR register ******************/ -#define DCMI_SR_HSYNC ((uint32_t)0x00000001) -#define DCMI_SR_VSYNC ((uint32_t)0x00000002) -#define DCMI_SR_FNE ((uint32_t)0x00000004) - -/******************** Bits definition for DCMI_RISR register ****************/ -#define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001) -#define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002) -#define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004) -#define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008) -#define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010) - -/******************** Bits definition for DCMI_IER register *****************/ -#define DCMI_IER_FRAME_IE ((uint32_t)0x00000001) -#define DCMI_IER_OVF_IE ((uint32_t)0x00000002) -#define DCMI_IER_ERR_IE ((uint32_t)0x00000004) -#define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008) -#define DCMI_IER_LINE_IE ((uint32_t)0x00000010) - -/******************** Bits definition for DCMI_MISR register ****************/ -#define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001) -#define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002) -#define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004) -#define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008) -#define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010) - -/******************** Bits definition for DCMI_ICR register *****************/ -#define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001) -#define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002) -#define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004) -#define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008) -#define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010) - -/******************************************************************************/ -/* */ -/* DMA Controller */ -/* */ -/******************************************************************************/ -/******************** Bits definition for DMA_SxCR register *****************/ -#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000) -#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000) -#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000) -#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000) -#define DMA_SxCR_MBURST ((uint32_t)0x01800000) -#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000) -#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000) -#define DMA_SxCR_PBURST ((uint32_t)0x00600000) -#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000) -#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000) -#define DMA_SxCR_ACK ((uint32_t)0x00100000) -#define DMA_SxCR_CT ((uint32_t)0x00080000) -#define DMA_SxCR_DBM ((uint32_t)0x00040000) -#define DMA_SxCR_PL ((uint32_t)0x00030000) -#define DMA_SxCR_PL_0 ((uint32_t)0x00010000) -#define DMA_SxCR_PL_1 ((uint32_t)0x00020000) -#define DMA_SxCR_PINCOS ((uint32_t)0x00008000) -#define DMA_SxCR_MSIZE ((uint32_t)0x00006000) -#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000) -#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000) -#define DMA_SxCR_PSIZE ((uint32_t)0x00001800) -#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800) -#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000) -#define DMA_SxCR_MINC ((uint32_t)0x00000400) -#define DMA_SxCR_PINC ((uint32_t)0x00000200) -#define DMA_SxCR_CIRC ((uint32_t)0x00000100) -#define DMA_SxCR_DIR ((uint32_t)0x000000C0) -#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040) -#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080) -#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020) -#define DMA_SxCR_TCIE ((uint32_t)0x00000010) -#define DMA_SxCR_HTIE ((uint32_t)0x00000008) -#define DMA_SxCR_TEIE ((uint32_t)0x00000004) -#define DMA_SxCR_DMEIE ((uint32_t)0x00000002) -#define DMA_SxCR_EN ((uint32_t)0x00000001) - -/******************** Bits definition for DMA_SxCNDTR register **************/ -#define DMA_SxNDT ((uint32_t)0x0000FFFF) -#define DMA_SxNDT_0 ((uint32_t)0x00000001) -#define DMA_SxNDT_1 ((uint32_t)0x00000002) -#define DMA_SxNDT_2 ((uint32_t)0x00000004) -#define DMA_SxNDT_3 ((uint32_t)0x00000008) -#define DMA_SxNDT_4 ((uint32_t)0x00000010) -#define DMA_SxNDT_5 ((uint32_t)0x00000020) -#define DMA_SxNDT_6 ((uint32_t)0x00000040) -#define DMA_SxNDT_7 ((uint32_t)0x00000080) -#define DMA_SxNDT_8 ((uint32_t)0x00000100) -#define DMA_SxNDT_9 ((uint32_t)0x00000200) -#define DMA_SxNDT_10 ((uint32_t)0x00000400) -#define DMA_SxNDT_11 ((uint32_t)0x00000800) -#define DMA_SxNDT_12 ((uint32_t)0x00001000) -#define DMA_SxNDT_13 ((uint32_t)0x00002000) -#define DMA_SxNDT_14 ((uint32_t)0x00004000) -#define DMA_SxNDT_15 ((uint32_t)0x00008000) - -/******************** Bits definition for DMA_SxFCR register ****************/ -#define DMA_SxFCR_FEIE ((uint32_t)0x00000080) -#define DMA_SxFCR_FS ((uint32_t)0x00000038) -#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008) -#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010) -#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020) -#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004) -#define DMA_SxFCR_FTH ((uint32_t)0x00000003) -#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001) -#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002) - -/******************** Bits definition for DMA_LISR register *****************/ -#define DMA_LISR_TCIF3 ((uint32_t)0x08000000) -#define DMA_LISR_HTIF3 ((uint32_t)0x04000000) -#define DMA_LISR_TEIF3 ((uint32_t)0x02000000) -#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000) -#define DMA_LISR_FEIF3 ((uint32_t)0x00400000) -#define DMA_LISR_TCIF2 ((uint32_t)0x00200000) -#define DMA_LISR_HTIF2 ((uint32_t)0x00100000) -#define DMA_LISR_TEIF2 ((uint32_t)0x00080000) -#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000) -#define DMA_LISR_FEIF2 ((uint32_t)0x00010000) -#define DMA_LISR_TCIF1 ((uint32_t)0x00000800) -#define DMA_LISR_HTIF1 ((uint32_t)0x00000400) -#define DMA_LISR_TEIF1 ((uint32_t)0x00000200) -#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100) -#define DMA_LISR_FEIF1 ((uint32_t)0x00000040) -#define DMA_LISR_TCIF0 ((uint32_t)0x00000020) -#define DMA_LISR_HTIF0 ((uint32_t)0x00000010) -#define DMA_LISR_TEIF0 ((uint32_t)0x00000008) -#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004) -#define DMA_LISR_FEIF0 ((uint32_t)0x00000001) - -/******************** Bits definition for DMA_HISR register *****************/ -#define DMA_HISR_TCIF7 ((uint32_t)0x08000000) -#define DMA_HISR_HTIF7 ((uint32_t)0x04000000) -#define DMA_HISR_TEIF7 ((uint32_t)0x02000000) -#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000) -#define DMA_HISR_FEIF7 ((uint32_t)0x00400000) -#define DMA_HISR_TCIF6 ((uint32_t)0x00200000) -#define DMA_HISR_HTIF6 ((uint32_t)0x00100000) -#define DMA_HISR_TEIF6 ((uint32_t)0x00080000) -#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000) -#define DMA_HISR_FEIF6 ((uint32_t)0x00010000) -#define DMA_HISR_TCIF5 ((uint32_t)0x00000800) -#define DMA_HISR_HTIF5 ((uint32_t)0x00000400) -#define DMA_HISR_TEIF5 ((uint32_t)0x00000200) -#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100) -#define DMA_HISR_FEIF5 ((uint32_t)0x00000040) -#define DMA_HISR_TCIF4 ((uint32_t)0x00000020) -#define DMA_HISR_HTIF4 ((uint32_t)0x00000010) -#define DMA_HISR_TEIF4 ((uint32_t)0x00000008) -#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004) -#define DMA_HISR_FEIF4 ((uint32_t)0x00000001) - -/******************** Bits definition for DMA_LIFCR register ****************/ -#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000) -#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000) -#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000) -#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000) -#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000) -#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000) -#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000) -#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000) -#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000) -#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000) -#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800) -#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400) -#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200) -#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100) -#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040) -#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020) -#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010) -#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008) -#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004) -#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001) - -/******************** Bits definition for DMA_HIFCR register ****************/ -#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000) -#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000) -#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000) -#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000) -#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000) -#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000) -#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000) -#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000) -#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000) -#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000) -#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800) -#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400) -#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200) -#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100) -#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040) -#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020) -#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010) -#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008) -#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004) -#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001) - - -/******************************************************************************/ -/* */ -/* External Interrupt/Event Controller */ -/* */ -/******************************************************************************/ -/******************* Bit definition for EXTI_IMR register *******************/ -#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ -#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ -#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ -#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ -#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ -#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ -#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ -#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ -#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ -#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ -#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ -#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ -#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ -#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ -#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ -#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ -#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ -#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ -#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ -#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ - -/******************* Bit definition for EXTI_EMR register *******************/ -#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ -#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ -#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ -#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ -#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ -#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ -#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ -#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ -#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ -#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ -#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ -#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ -#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ -#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ -#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ -#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ -#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ -#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ -#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ -#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ - -/****************** Bit definition for EXTI_RTSR register *******************/ -#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ -#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ -#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ -#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ -#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ -#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ -#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ -#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ -#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ -#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ -#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ -#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ -#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ -#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ -#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ -#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ -#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ -#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ -#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ - -/****************** Bit definition for EXTI_FTSR register *******************/ -#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ -#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ -#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ -#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ -#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ -#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ -#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ -#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ -#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ -#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ -#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ -#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ -#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ -#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ -#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ -#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ -#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ -#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ -#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ - -/****************** Bit definition for EXTI_SWIER register ******************/ -#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ -#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ -#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ -#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ -#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ -#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ -#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ -#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ -#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ -#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ -#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ -#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ -#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ -#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ -#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ -#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ -#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ -#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ -#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ -#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ - -/******************* Bit definition for EXTI_PR register ********************/ -#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ -#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ -#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ -#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ -#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ -#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ -#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ -#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ -#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ -#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ -#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ -#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ -#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ -#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ -#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ -#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ -#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ -#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ -#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ -#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ - -/******************************************************************************/ -/* */ -/* FLASH */ -/* */ -/******************************************************************************/ -/******************* Bits definition for FLASH_ACR register *****************/ -#define FLASH_ACR_LATENCY ((uint32_t)0x0000000F) -#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000) -#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001) -#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002) -#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003) -#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004) -#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005) -#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006) -#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007) - -#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100) -#define FLASH_ACR_ICEN ((uint32_t)0x00000200) -#define FLASH_ACR_DCEN ((uint32_t)0x00000400) -#define FLASH_ACR_ICRST ((uint32_t)0x00000800) -#define FLASH_ACR_DCRST ((uint32_t)0x00001000) -#define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) -#define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03) - -/******************* Bits definition for FLASH_SR register ******************/ -#define FLASH_SR_EOP ((uint32_t)0x00000001) -#define FLASH_SR_SOP ((uint32_t)0x00000002) -#define FLASH_SR_WRPERR ((uint32_t)0x00000010) -#define FLASH_SR_PGAERR ((uint32_t)0x00000020) -#define FLASH_SR_PGPERR ((uint32_t)0x00000040) -#define FLASH_SR_PGSERR ((uint32_t)0x00000080) -#define FLASH_SR_BSY ((uint32_t)0x00010000) - -/******************* Bits definition for FLASH_CR register ******************/ -#define FLASH_CR_PG ((uint32_t)0x00000001) -#define FLASH_CR_SER ((uint32_t)0x00000002) -#define FLASH_CR_MER ((uint32_t)0x00000004) -#define FLASH_CR_MER1 FLASH_CR_MER -#define FLASH_CR_SNB ((uint32_t)0x000000F8) -#define FLASH_CR_SNB_0 ((uint32_t)0x00000008) -#define FLASH_CR_SNB_1 ((uint32_t)0x00000010) -#define FLASH_CR_SNB_2 ((uint32_t)0x00000020) -#define FLASH_CR_SNB_3 ((uint32_t)0x00000040) -#define FLASH_CR_SNB_4 ((uint32_t)0x00000040) -#define FLASH_CR_PSIZE ((uint32_t)0x00000300) -#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100) -#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200) -#define FLASH_CR_MER2 ((uint32_t)0x00008000) -#define FLASH_CR_STRT ((uint32_t)0x00010000) -#define FLASH_CR_EOPIE ((uint32_t)0x01000000) -#define FLASH_CR_LOCK ((uint32_t)0x80000000) - -/******************* Bits definition for FLASH_OPTCR register ***************/ -#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001) -#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002) -#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004) -#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008) -#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C) -#define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020) -#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040) -#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080) -#define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00) -#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100) -#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200) -#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400) -#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800) -#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000) -#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000) -#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000) -#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000) -#define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000) -#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000) -#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000) -#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000) -#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000) -#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000) -#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000) -#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000) -#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000) -#define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000) -#define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000) -#define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000) -#define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000) - -/****************** Bits definition for FLASH_OPTCR1 register ***************/ -#define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000) -#define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000) -#define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000) -#define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000) -#define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000) -#define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000) -#define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000) -#define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000) -#define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000) -#define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000) -#define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000) -#define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000) -#define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000) - - -/******************************************************************************/ -/* */ -/* Flexible Static Memory Controller */ -/* */ -/******************************************************************************/ -/****************** Bit definition for FSMC_BCR1 register *******************/ -#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ -#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ - -#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ -#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ - -#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ -#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ - -#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ -#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ -#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */ -#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ -#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ -#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ -#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ -#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ -#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ -#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ - -/****************** Bit definition for FSMC_BCR2 register *******************/ -#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ -#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ - -#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ -#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ - -#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ -#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ - -#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ -#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ -#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */ -#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ -#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ -#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ -#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ -#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ -#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ -#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ - -/****************** Bit definition for FSMC_BCR3 register *******************/ -#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ -#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ - -#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ -#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ - -#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ -#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ - -#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ -#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ -#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */ -#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ -#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ -#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ -#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ -#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ -#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ -#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ - -/****************** Bit definition for FSMC_BCR4 register *******************/ -#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ -#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ - -#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ -#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ - -#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ -#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ - -#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ -#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ -#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */ -#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ -#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ -#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ -#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ -#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ -#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ -#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ - -/****************** Bit definition for FSMC_BTR1 register ******************/ -#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ -#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ -#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ -#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ - -#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ -#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ -#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ -#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ - -#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ -#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ -#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ -#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ - -#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ -#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ -#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ -#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ - -#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ -#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ -#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ -#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ - -#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ -#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ -#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ -#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ - -#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ -#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ - -/****************** Bit definition for FSMC_BTR2 register *******************/ -#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ -#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ -#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ -#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ - -#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ -#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ -#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ -#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ - -#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ -#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ -#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ -#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ - -#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ -#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ -#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ -#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ - -#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ -#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ -#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ -#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ - -#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ -#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ -#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ -#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ - -#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ -#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ - -/******************* Bit definition for FSMC_BTR3 register *******************/ -#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ -#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ -#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ -#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ - -#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ -#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ -#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ -#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ - -#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ -#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ -#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ -#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ - -#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ -#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ -#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ -#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ - -#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ -#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ -#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ -#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ - -#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ -#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ -#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ -#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ - -#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ -#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ - -/****************** Bit definition for FSMC_BTR4 register *******************/ -#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ -#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ -#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ -#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ - -#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ -#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ -#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ -#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ - -#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ -#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ -#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ -#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ - -#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ -#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ -#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ -#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ - -#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ -#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ -#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ -#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ - -#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ -#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ -#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ -#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ - -#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ -#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ - -/****************** Bit definition for FSMC_BWTR1 register ******************/ -#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ -#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ -#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ -#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ - -#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ -#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ -#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ -#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ - -#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ -#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ -#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ -#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ - -#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ -#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ -#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ -#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ - -#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ -#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ -#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ -#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ - -#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ -#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ - -/****************** Bit definition for FSMC_BWTR2 register ******************/ -#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ -#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ -#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ -#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ - -#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ -#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ -#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ -#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ - -#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ -#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ -#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ -#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ - -#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ -#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/ -#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ -#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ - -#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ -#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ -#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ -#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ - -#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ -#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ - -/****************** Bit definition for FSMC_BWTR3 register ******************/ -#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ -#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ -#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ -#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ - -#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ -#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ -#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ -#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ - -#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ -#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ -#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ -#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ - -#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ -#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ -#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ -#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ - -#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ -#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ -#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ -#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ - -#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ -#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ - -/****************** Bit definition for FSMC_BWTR4 register ******************/ -#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ -#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ -#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ -#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ - -#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ -#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ -#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ -#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ - -#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ -#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ -#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ -#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ - -#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ -#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ -#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ -#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ - -#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ -#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ -#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ -#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ - -#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ -#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ - -/****************** Bit definition for FSMC_PCR2 register *******************/ -#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */ -#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */ -#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */ - -#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */ -#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ -#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ - -#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */ - -#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */ -#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */ -#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */ -#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */ -#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */ - -#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */ -#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */ -#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */ -#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */ -#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */ - -#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */ -#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ -#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ -#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ - -/****************** Bit definition for FSMC_PCR3 register *******************/ -#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */ -#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */ -#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */ - -#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */ -#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ -#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ - -#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */ - -#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */ -#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */ -#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */ -#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */ -#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */ - -#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */ -#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */ -#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */ -#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */ -#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */ - -#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */ -#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ -#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ -#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ - -/****************** Bit definition for FSMC_PCR4 register *******************/ -#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */ -#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */ -#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */ - -#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */ -#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ -#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ - -#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */ - -#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */ -#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */ -#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */ -#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */ -#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */ - -#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */ -#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */ -#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */ -#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */ -#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */ - -#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */ -#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ -#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ -#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ - -/******************* Bit definition for FSMC_SR2 register *******************/ -#define FSMC_SR2_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */ -#define FSMC_SR2_ILS ((uint8_t)0x02) /*!<Interrupt Level status */ -#define FSMC_SR2_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */ -#define FSMC_SR2_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */ -#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */ -#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */ -#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!<FIFO empty */ - -/******************* Bit definition for FSMC_SR3 register *******************/ -#define FSMC_SR3_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */ -#define FSMC_SR3_ILS ((uint8_t)0x02) /*!<Interrupt Level status */ -#define FSMC_SR3_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */ -#define FSMC_SR3_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */ -#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */ -#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */ -#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!<FIFO empty */ - -/******************* Bit definition for FSMC_SR4 register *******************/ -#define FSMC_SR4_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */ -#define FSMC_SR4_ILS ((uint8_t)0x02) /*!<Interrupt Level status */ -#define FSMC_SR4_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */ -#define FSMC_SR4_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */ -#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */ -#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */ -#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!<FIFO empty */ - -/****************** Bit definition for FSMC_PMEM2 register ******************/ -#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */ -#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */ -#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */ -#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */ -#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */ -#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */ -#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */ -#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */ -#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */ - -#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */ -#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */ -#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */ -#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */ -#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */ -#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */ -#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */ -#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */ -#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */ - -#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */ -#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */ -#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */ -#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */ -#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */ -#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */ -#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */ -#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */ -#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */ - -#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ -#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */ -#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */ -#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */ -#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */ -#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */ -#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */ -#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */ -#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */ - -/****************** Bit definition for FSMC_PMEM3 register ******************/ -#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */ -#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */ -#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */ -#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */ -#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */ -#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */ -#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */ -#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */ -#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */ - -#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */ -#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */ -#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */ -#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */ -#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */ -#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */ -#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */ -#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */ -#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */ - -#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */ -#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */ -#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */ -#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */ -#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */ -#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */ -#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */ -#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */ -#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */ - -#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ -#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */ -#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */ -#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */ -#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */ -#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */ -#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */ -#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */ -#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */ - -/****************** Bit definition for FSMC_PMEM4 register ******************/ -#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */ -#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */ -#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */ -#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */ -#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */ -#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */ -#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */ -#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */ -#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */ - -#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */ -#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */ -#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */ -#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */ -#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */ -#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */ -#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */ -#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */ -#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */ - -#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */ -#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */ -#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */ -#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */ -#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */ -#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */ -#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */ -#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */ -#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */ - -#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */ -#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */ -#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */ -#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */ -#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */ -#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */ -#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */ -#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */ -#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */ - -/****************** Bit definition for FSMC_PATT2 register ******************/ -#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */ -#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */ -#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */ -#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */ -#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */ -#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */ -#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */ -#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */ -#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */ - -#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ -#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */ -#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */ -#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */ -#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */ -#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */ -#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */ -#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */ -#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */ - -#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ -#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */ -#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */ -#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */ -#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */ -#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */ -#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */ -#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */ -#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */ - -#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ -#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */ -#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */ -#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */ -#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */ -#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */ -#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */ -#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */ -#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */ - -/****************** Bit definition for FSMC_PATT3 register ******************/ -#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */ -#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */ -#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */ -#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */ -#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */ -#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */ -#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */ -#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */ -#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */ - -#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ -#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */ -#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */ -#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */ -#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */ -#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */ -#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */ -#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */ -#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */ - -#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ -#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */ -#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */ -#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */ -#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */ -#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */ -#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */ -#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */ -#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */ - -#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ -#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */ -#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */ -#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */ -#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */ -#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */ -#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */ -#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */ -#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */ - -/****************** Bit definition for FSMC_PATT4 register ******************/ -#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */ -#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */ -#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */ -#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */ -#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */ -#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */ -#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */ -#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */ -#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */ - -#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */ -#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */ -#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */ -#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */ -#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */ -#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */ -#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */ -#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */ -#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */ - -#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */ -#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */ -#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */ -#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */ -#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */ -#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */ -#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */ -#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */ -#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */ - -#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */ -#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */ -#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */ -#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */ -#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */ -#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */ -#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */ -#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */ -#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */ - -/****************** Bit definition for FSMC_PIO4 register *******************/ -#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */ -#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */ -#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */ -#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */ -#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */ -#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */ -#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */ -#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */ -#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */ - -#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */ -#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */ -#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */ -#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */ -#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */ -#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */ -#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */ -#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */ -#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */ - -#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */ -#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */ -#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */ -#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */ -#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */ -#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */ -#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */ -#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */ -#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */ - -#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */ -#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */ -#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */ -#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */ -#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */ -#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */ -#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */ -#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */ -#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */ - -/****************** Bit definition for FSMC_ECCR2 register ******************/ -#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */ - -/****************** Bit definition for FSMC_ECCR3 register ******************/ -#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */ - - -/******************************************************************************/ -/* */ -/* General Purpose I/O */ -/* */ -/******************************************************************************/ -/****************** Bits definition for GPIO_MODER register *****************/ -#define GPIO_MODER_MODER0 ((uint32_t)0x00000003) -#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001) -#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002) - -#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C) -#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004) -#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008) - -#define GPIO_MODER_MODER2 ((uint32_t)0x00000030) -#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010) -#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020) - -#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0) -#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040) -#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080) - -#define GPIO_MODER_MODER4 ((uint32_t)0x00000300) -#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100) -#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200) - -#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00) -#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400) -#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800) - -#define GPIO_MODER_MODER6 ((uint32_t)0x00003000) -#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000) -#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000) - -#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000) -#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000) -#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000) - -#define GPIO_MODER_MODER8 ((uint32_t)0x00030000) -#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000) -#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000) - -#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000) -#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000) -#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000) - -#define GPIO_MODER_MODER10 ((uint32_t)0x00300000) -#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000) -#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000) - -#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000) -#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000) -#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000) - -#define GPIO_MODER_MODER12 ((uint32_t)0x03000000) -#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000) -#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000) - -#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000) -#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000) -#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000) - -#define GPIO_MODER_MODER14 ((uint32_t)0x30000000) -#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000) -#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000) - -#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000) -#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000) -#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000) - -/****************** Bits definition for GPIO_OTYPER register ****************/ -#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001) -#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002) -#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004) -#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008) -#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010) -#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020) -#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040) -#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080) -#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100) -#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200) -#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400) -#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800) -#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000) -#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000) -#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000) -#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000) - -/****************** Bits definition for GPIO_OSPEEDR register ***************/ -#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003) -#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001) -#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002) - -#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C) -#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004) -#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008) - -#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030) -#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010) -#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020) - -#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0) -#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040) -#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080) - -#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300) -#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100) -#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200) - -#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00) -#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400) -#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800) - -#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000) -#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000) -#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000) - -#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000) -#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000) -#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000) - -#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000) -#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000) -#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000) - -#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000) -#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000) -#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000) - -#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000) -#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000) -#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000) - -#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000) -#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000) -#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000) - -#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000) -#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000) -#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000) - -#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000) -#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000) -#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000) - -#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000) -#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000) -#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000) - -#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000) -#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000) -#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000) - -/****************** Bits definition for GPIO_PUPDR register *****************/ -#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003) -#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001) -#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002) - -#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C) -#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004) -#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008) - -#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030) -#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010) -#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020) - -#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0) -#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040) -#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080) - -#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300) -#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100) -#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200) - -#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00) -#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400) -#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800) - -#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000) -#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000) -#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000) - -#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000) -#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000) -#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000) - -#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000) -#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000) -#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000) - -#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000) -#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000) -#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000) - -#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000) -#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000) -#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000) - -#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000) -#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000) -#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000) - -#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000) -#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000) -#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000) - -#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000) -#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000) -#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000) - -#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000) -#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000) -#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000) - -#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000) -#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000) -#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000) - -/****************** Bits definition for GPIO_IDR register *******************/ -#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001) -#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002) -#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004) -#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008) -#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010) -#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020) -#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040) -#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080) -#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100) -#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200) -#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400) -#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800) -#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000) -#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000) -#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000) -#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000) -/* Old GPIO_IDR register bits definition, maintained for legacy purpose */ -#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0 -#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1 -#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2 -#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3 -#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4 -#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5 -#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6 -#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7 -#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8 -#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9 -#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10 -#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11 -#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12 -#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13 -#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14 -#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15 - -/****************** Bits definition for GPIO_ODR register *******************/ -#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001) -#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002) -#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004) -#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008) -#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010) -#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020) -#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040) -#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080) -#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100) -#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200) -#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400) -#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800) -#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000) -#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000) -#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000) -#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000) -/* Old GPIO_ODR register bits definition, maintained for legacy purpose */ -#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0 -#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1 -#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2 -#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3 -#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4 -#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5 -#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6 -#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7 -#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8 -#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9 -#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10 -#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11 -#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12 -#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13 -#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14 -#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15 - -/****************** Bits definition for GPIO_BSRR register ******************/ -#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001) -#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002) -#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004) -#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008) -#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010) -#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020) -#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040) -#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080) -#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100) -#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200) -#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400) -#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800) -#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000) -#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000) -#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000) -#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000) -#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000) -#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000) -#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000) -#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000) -#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000) -#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000) -#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000) -#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000) -#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000) -#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000) -#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000) -#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000) -#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000) -#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000) -#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000) -#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000) - -/******************************************************************************/ -/* */ -/* HASH */ -/* */ -/******************************************************************************/ -/****************** Bits definition for HASH_CR register ********************/ -#define HASH_CR_INIT ((uint32_t)0x00000004) -#define HASH_CR_DMAE ((uint32_t)0x00000008) -#define HASH_CR_DATATYPE ((uint32_t)0x00000030) -#define HASH_CR_DATATYPE_0 ((uint32_t)0x00000010) -#define HASH_CR_DATATYPE_1 ((uint32_t)0x00000020) -#define HASH_CR_MODE ((uint32_t)0x00000040) -#define HASH_CR_ALGO ((uint32_t)0x00040080) -#define HASH_CR_ALGO_0 ((uint32_t)0x00000080) -#define HASH_CR_ALGO_1 ((uint32_t)0x00040000) -#define HASH_CR_NBW ((uint32_t)0x00000F00) -#define HASH_CR_NBW_0 ((uint32_t)0x00000100) -#define HASH_CR_NBW_1 ((uint32_t)0x00000200) -#define HASH_CR_NBW_2 ((uint32_t)0x00000400) -#define HASH_CR_NBW_3 ((uint32_t)0x00000800) -#define HASH_CR_DINNE ((uint32_t)0x00001000) -#define HASH_CR_MDMAT ((uint32_t)0x00002000) -#define HASH_CR_LKEY ((uint32_t)0x00010000) - -/****************** Bits definition for HASH_STR register *******************/ -#define HASH_STR_NBW ((uint32_t)0x0000001F) -#define HASH_STR_NBW_0 ((uint32_t)0x00000001) -#define HASH_STR_NBW_1 ((uint32_t)0x00000002) -#define HASH_STR_NBW_2 ((uint32_t)0x00000004) -#define HASH_STR_NBW_3 ((uint32_t)0x00000008) -#define HASH_STR_NBW_4 ((uint32_t)0x00000010) -#define HASH_STR_DCAL ((uint32_t)0x00000100) - -/****************** Bits definition for HASH_IMR register *******************/ -#define HASH_IMR_DINIM ((uint32_t)0x00000001) -#define HASH_IMR_DCIM ((uint32_t)0x00000002) - -/****************** Bits definition for HASH_SR register ********************/ -#define HASH_SR_DINIS ((uint32_t)0x00000001) -#define HASH_SR_DCIS ((uint32_t)0x00000002) -#define HASH_SR_DMAS ((uint32_t)0x00000004) -#define HASH_SR_BUSY ((uint32_t)0x00000008) - -/******************************************************************************/ -/* */ -/* Inter-integrated Circuit Interface */ -/* */ -/******************************************************************************/ -/******************* Bit definition for I2C_CR1 register ********************/ -#define I2C_CR1_PE ((uint16_t)0x0001) /*!<Peripheral Enable */ -#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!<SMBus Mode */ -#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!<SMBus Type */ -#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!<ARP Enable */ -#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!<PEC Enable */ -#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!<General Call Enable */ -#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!<Clock Stretching Disable (Slave mode) */ -#define I2C_CR1_START ((uint16_t)0x0100) /*!<Start Generation */ -#define I2C_CR1_STOP ((uint16_t)0x0200) /*!<Stop Generation */ -#define I2C_CR1_ACK ((uint16_t)0x0400) /*!<Acknowledge Enable */ -#define I2C_CR1_POS ((uint16_t)0x0800) /*!<Acknowledge/PEC Position (for data reception) */ -#define I2C_CR1_PEC ((uint16_t)0x1000) /*!<Packet Error Checking */ -#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!<SMBus Alert */ -#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!<Software Reset */ - -/******************* Bit definition for I2C_CR2 register ********************/ -#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */ -#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!<Bit 0 */ -#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!<Bit 1 */ -#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!<Bit 2 */ -#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!<Bit 3 */ -#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!<Bit 4 */ -#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!<Bit 5 */ - -#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!<Error Interrupt Enable */ -#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!<Event Interrupt Enable */ -#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!<Buffer Interrupt Enable */ -#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!<DMA Requests Enable */ -#define I2C_CR2_LAST ((uint16_t)0x1000) /*!<DMA Last Transfer */ - -/******************* Bit definition for I2C_OAR1 register *******************/ -#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!<Interface Address */ -#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!<Interface Address */ - -#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!<Bit 0 */ -#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!<Bit 1 */ -#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!<Bit 2 */ -#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!<Bit 3 */ -#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!<Bit 4 */ -#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!<Bit 5 */ -#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!<Bit 6 */ -#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!<Bit 7 */ -#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!<Bit 8 */ -#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!<Bit 9 */ - -#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!<Addressing Mode (Slave mode) */ - -/******************* Bit definition for I2C_OAR2 register *******************/ -#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!<Dual addressing mode enable */ -#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!<Interface address */ - -/******************** Bit definition for I2C_DR register ********************/ -#define I2C_DR_DR ((uint8_t)0xFF) /*!<8-bit Data Register */ - -/******************* Bit definition for I2C_SR1 register ********************/ -#define I2C_SR1_SB ((uint16_t)0x0001) /*!<Start Bit (Master mode) */ -#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!<Address sent (master mode)/matched (slave mode) */ -#define I2C_SR1_BTF ((uint16_t)0x0004) /*!<Byte Transfer Finished */ -#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!<10-bit header sent (Master mode) */ -#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!<Stop detection (Slave mode) */ -#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!<Data Register not Empty (receivers) */ -#define I2C_SR1_TXE ((uint16_t)0x0080) /*!<Data Register Empty (transmitters) */ -#define I2C_SR1_BERR ((uint16_t)0x0100) /*!<Bus Error */ -#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!<Arbitration Lost (master mode) */ -#define I2C_SR1_AF ((uint16_t)0x0400) /*!<Acknowledge Failure */ -#define I2C_SR1_OVR ((uint16_t)0x0800) /*!<Overrun/Underrun */ -#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!<PEC Error in reception */ -#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!<Timeout or Tlow Error */ -#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!<SMBus Alert */ - -/******************* Bit definition for I2C_SR2 register ********************/ -#define I2C_SR2_MSL ((uint16_t)0x0001) /*!<Master/Slave */ -#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!<Bus Busy */ -#define I2C_SR2_TRA ((uint16_t)0x0004) /*!<Transmitter/Receiver */ -#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!<General Call Address (Slave mode) */ -#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!<SMBus Device Default Address (Slave mode) */ -#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!<SMBus Host Header (Slave mode) */ -#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!<Dual Flag (Slave mode) */ -#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!<Packet Error Checking Register */ - -/******************* Bit definition for I2C_CCR register ********************/ -#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */ -#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!<Fast Mode Duty Cycle */ -#define I2C_CCR_FS ((uint16_t)0x8000) /*!<I2C Master Mode Selection */ - -/****************** Bit definition for I2C_TRISE register *******************/ -#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */ - -/****************** Bit definition for I2C_FLTR register *******************/ -#define I2C_FLTR_DNF ((uint8_t)0x0F) /*!<Digital Noise Filter */ -#define I2C_FLTR_ANOFF ((uint8_t)0x10) /*!<Analog Noise Filter OFF */ - -/******************************************************************************/ -/* */ -/* Independent WATCHDOG */ -/* */ -/******************************************************************************/ -/******************* Bit definition for IWDG_KR register ********************/ -#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!<Key value (write only, read 0000h) */ - -/******************* Bit definition for IWDG_PR register ********************/ -#define IWDG_PR_PR ((uint8_t)0x07) /*!<PR[2:0] (Prescaler divider) */ -#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!<Bit 0 */ -#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!<Bit 1 */ -#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!<Bit 2 */ - -/******************* Bit definition for IWDG_RLR register *******************/ -#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!<Watchdog counter reload value */ - -/******************* Bit definition for IWDG_SR register ********************/ -#define IWDG_SR_PVU ((uint8_t)0x01) /*!<Watchdog prescaler value update */ -#define IWDG_SR_RVU ((uint8_t)0x02) /*!<Watchdog counter reload value update */ - - -/******************************************************************************/ -/* */ -/* Power Control */ -/* */ -/******************************************************************************/ -/******************** Bit definition for PWR_CR register ********************/ -#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */ -#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */ -#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */ -#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */ -#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */ - -#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */ - -/*!< PVD level configuration */ -#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */ -#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */ -#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */ -#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */ -#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */ -#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */ -#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */ -#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */ - -#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */ -#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */ -#define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */ -#define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main regulator Low Voltage Scaling in Stop mode */ - -#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */ -#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */ - -/* Legacy define */ -#define PWR_CR_PMODE PWR_CR_VOS - -/******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */ -#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */ -#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */ -#define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */ -#define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */ -#define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */ -#define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */ - -/* Legacy define */ -#define PWR_CSR_REGRDY PWR_CSR_VOSRDY - -/******************************************************************************/ -/* */ -/* Reset and Clock Control */ -/* */ -/******************************************************************************/ -/******************** Bit definition for RCC_CR register ********************/ -#define RCC_CR_HSION ((uint32_t)0x00000001) -#define RCC_CR_HSIRDY ((uint32_t)0x00000002) - -#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) -#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */ -#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */ -#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */ -#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */ -#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */ - -#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) -#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */ -#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */ -#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */ -#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */ -#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */ -#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */ -#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */ -#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */ - -#define RCC_CR_HSEON ((uint32_t)0x00010000) -#define RCC_CR_HSERDY ((uint32_t)0x00020000) -#define RCC_CR_HSEBYP ((uint32_t)0x00040000) -#define RCC_CR_CSSON ((uint32_t)0x00080000) -#define RCC_CR_PLLON ((uint32_t)0x01000000) -#define RCC_CR_PLLRDY ((uint32_t)0x02000000) -#define RCC_CR_PLLI2SON ((uint32_t)0x04000000) -#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000) - - -/******************** Bit definition for RCC_PLLCFGR register ***************/ -#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F) -#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001) -#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002) -#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004) -#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008) -#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010) -#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020) - -#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0) -#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040) -#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080) -#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100) -#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200) -#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400) -#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800) -#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000) -#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000) -#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000) - -#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000) -#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000) -#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000) - -#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000) -#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000) -#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000) - -#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000) -#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000) -#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000) -#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000) -#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000) - -/******************** Bit definition for RCC_CFGR register ******************/ -/*!< SW configuration */ -#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ -#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ -#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ -#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ - -/*!< SWS configuration */ -#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ -#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ - -/*!< HPRE configuration */ -#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ -#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ -#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ -#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ -#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ -#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ -#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ -#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ -#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ -#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ - -/*!< PPRE1 configuration */ -#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */ -#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */ - -#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */ - -/*!< PPRE2 configuration */ -#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */ -#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */ - -#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */ - -/*!< RTCPRE configuration */ -#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000) -#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000) -#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000) -#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000) -#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000) -#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000) - -/*!< MCO1 configuration */ -#define RCC_CFGR_MCO1 ((uint32_t)0x00600000) -#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000) -#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000) - -#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000) - -#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000) -#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000) -#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000) -#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000) - -#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000) -#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000) -#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000) -#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000) - -#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000) -#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000) -#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000) - -/******************** Bit definition for RCC_CIR register *******************/ -#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) -#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) -#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) -#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) -#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) -#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020) -#define RCC_CIR_CSSF ((uint32_t)0x00000080) -#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) -#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) -#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) -#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) -#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) -#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000) -#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) -#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) -#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) -#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) -#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) -#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000) -#define RCC_CIR_CSSC ((uint32_t)0x00800000) - -/******************** Bit definition for RCC_AHB1RSTR register **************/ -#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001) -#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002) -#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004) -#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008) -#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010) -#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020) -#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040) -#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080) -#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100) -#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000) -#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000) -#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000) -#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000) -#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000) - -/******************** Bit definition for RCC_AHB2RSTR register **************/ -#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001) -#define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010) -#define RCC_AHB2RSTR_HASHRST ((uint32_t)0x00000020) - /* maintained for legacy purpose */ - #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST -#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040) -#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080) - -/******************** Bit definition for RCC_AHB3RSTR register **************/ -#define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001) - -/******************** Bit definition for RCC_APB1RSTR register **************/ -#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) -#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) -#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) -#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) -#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) -#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) -#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) -#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) -#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) -#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) -#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) -#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) -#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) -#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) -#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) -#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) -#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) -#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) -#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000) -#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) -#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) -#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) -#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) -#define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000) -#define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000) - -/******************** Bit definition for RCC_APB2RSTR register **************/ -#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001) -#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002) -#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010) -#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020) -#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100) -#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800) -#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) -#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000) -#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000) -#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000) -#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000) -#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000) -#define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000) -#define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000) - -/* Old SPI1RST bit definition, maintained for legacy purpose */ -#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST - -/******************** Bit definition for RCC_AHB1ENR register ***************/ -#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001) -#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002) -#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004) -#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008) -#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010) -#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020) -#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040) -#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080) -#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100) -#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000) -#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000) -#define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000) -#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000) -#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000) -#define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000) -#define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000) -#define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000) -#define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000) -#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000) -#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000) - -/******************** Bit definition for RCC_AHB2ENR register ***************/ -#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001) -#define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010) -#define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020) -#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040) -#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080) - -/******************** Bit definition for RCC_AHB3ENR register ***************/ -#define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001) - -/******************** Bit definition for RCC_APB1ENR register ***************/ -#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) -#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) -#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) -#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) -#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) -#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) -#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) -#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) -#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) -#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) -#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) -#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) -#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) -#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) -#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) -#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) -#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) -#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) -#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000) -#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) -#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) -#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) -#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) -#define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000) -#define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000) - -/******************** Bit definition for RCC_APB2ENR register ***************/ -#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001) -#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002) -#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010) -#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020) -#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100) -#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200) -#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400) -#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800) -#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) -#define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000) -#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000) -#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000) -#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000) -#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000) -#define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000) -#define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000) - -/******************** Bit definition for RCC_AHB1LPENR register *************/ -#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001) -#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002) -#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004) -#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008) -#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010) -#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020) -#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040) -#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080) -#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100) -#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000) -#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000) -#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000) -#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000) -#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000) -#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000) -#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000) -#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000) -#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000) -#define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000) -#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000) -#define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000) -#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000) -#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000) - -/******************** Bit definition for RCC_AHB2LPENR register *************/ -#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001) -#define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010) -#define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020) -#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040) -#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080) - -/******************** Bit definition for RCC_AHB3LPENR register *************/ -#define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001) - -/******************** Bit definition for RCC_APB1LPENR register *************/ -#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) -#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) -#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) -#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008) -#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) -#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) -#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040) -#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080) -#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100) -#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) -#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) -#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000) -#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) -#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) -#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000) -#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000) -#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) -#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) -#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000) -#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000) -#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000) -#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) -#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) -#define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000) -#define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000) - -/******************** Bit definition for RCC_APB2LPENR register *************/ -#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001) -#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002) -#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010) -#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020) -#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100) -#define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200) -#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400) -#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800) -#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) -#define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000) -#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000) -#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000) -#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000) -#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000) -#define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000) -#define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000) - -/******************** Bit definition for RCC_BDCR register ******************/ -#define RCC_BDCR_LSEON ((uint32_t)0x00000001) -#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) -#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) - -#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) -#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) -#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) - -#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) -#define RCC_BDCR_BDRST ((uint32_t)0x00010000) - -/******************** Bit definition for RCC_CSR register *******************/ -#define RCC_CSR_LSION ((uint32_t)0x00000001) -#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) -#define RCC_CSR_RMVF ((uint32_t)0x01000000) -#define RCC_CSR_BORRSTF ((uint32_t)0x02000000) -#define RCC_CSR_PADRSTF ((uint32_t)0x04000000) -#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) -#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) -#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000) -#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) -#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) - -/******************** Bit definition for RCC_SSCGR register *****************/ -#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF) -#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000) -#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000) -#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000) - -/******************** Bit definition for RCC_PLLI2SCFGR register ************/ -#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0) -#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000) - -/******************** Bit definition for RCC_DCKCFGR register ***************/ -#define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000) - - -/******************************************************************************/ -/* */ -/* RNG */ -/* */ -/******************************************************************************/ -/******************** Bits definition for RNG_CR register *******************/ -#define RNG_CR_RNGEN ((uint32_t)0x00000004) -#define RNG_CR_IE ((uint32_t)0x00000008) - -/******************** Bits definition for RNG_SR register *******************/ -#define RNG_SR_DRDY ((uint32_t)0x00000001) -#define RNG_SR_CECS ((uint32_t)0x00000002) -#define RNG_SR_SECS ((uint32_t)0x00000004) -#define RNG_SR_CEIS ((uint32_t)0x00000020) -#define RNG_SR_SEIS ((uint32_t)0x00000040) - -/******************************************************************************/ -/* */ -/* Real-Time Clock (RTC) */ -/* */ -/******************************************************************************/ -/******************** Bits definition for RTC_TR register *******************/ -#define RTC_TR_PM ((uint32_t)0x00400000) -#define RTC_TR_HT ((uint32_t)0x00300000) -#define RTC_TR_HT_0 ((uint32_t)0x00100000) -#define RTC_TR_HT_1 ((uint32_t)0x00200000) -#define RTC_TR_HU ((uint32_t)0x000F0000) -#define RTC_TR_HU_0 ((uint32_t)0x00010000) -#define RTC_TR_HU_1 ((uint32_t)0x00020000) -#define RTC_TR_HU_2 ((uint32_t)0x00040000) -#define RTC_TR_HU_3 ((uint32_t)0x00080000) -#define RTC_TR_MNT ((uint32_t)0x00007000) -#define RTC_TR_MNT_0 ((uint32_t)0x00001000) -#define RTC_TR_MNT_1 ((uint32_t)0x00002000) -#define RTC_TR_MNT_2 ((uint32_t)0x00004000) -#define RTC_TR_MNU ((uint32_t)0x00000F00) -#define RTC_TR_MNU_0 ((uint32_t)0x00000100) -#define RTC_TR_MNU_1 ((uint32_t)0x00000200) -#define RTC_TR_MNU_2 ((uint32_t)0x00000400) -#define RTC_TR_MNU_3 ((uint32_t)0x00000800) -#define RTC_TR_ST ((uint32_t)0x00000070) -#define RTC_TR_ST_0 ((uint32_t)0x00000010) -#define RTC_TR_ST_1 ((uint32_t)0x00000020) -#define RTC_TR_ST_2 ((uint32_t)0x00000040) -#define RTC_TR_SU ((uint32_t)0x0000000F) -#define RTC_TR_SU_0 ((uint32_t)0x00000001) -#define RTC_TR_SU_1 ((uint32_t)0x00000002) -#define RTC_TR_SU_2 ((uint32_t)0x00000004) -#define RTC_TR_SU_3 ((uint32_t)0x00000008) - -/******************** Bits definition for RTC_DR register *******************/ -#define RTC_DR_YT ((uint32_t)0x00F00000) -#define RTC_DR_YT_0 ((uint32_t)0x00100000) -#define RTC_DR_YT_1 ((uint32_t)0x00200000) -#define RTC_DR_YT_2 ((uint32_t)0x00400000) -#define RTC_DR_YT_3 ((uint32_t)0x00800000) -#define RTC_DR_YU ((uint32_t)0x000F0000) -#define RTC_DR_YU_0 ((uint32_t)0x00010000) -#define RTC_DR_YU_1 ((uint32_t)0x00020000) -#define RTC_DR_YU_2 ((uint32_t)0x00040000) -#define RTC_DR_YU_3 ((uint32_t)0x00080000) -#define RTC_DR_WDU ((uint32_t)0x0000E000) -#define RTC_DR_WDU_0 ((uint32_t)0x00002000) -#define RTC_DR_WDU_1 ((uint32_t)0x00004000) -#define RTC_DR_WDU_2 ((uint32_t)0x00008000) -#define RTC_DR_MT ((uint32_t)0x00001000) -#define RTC_DR_MU ((uint32_t)0x00000F00) -#define RTC_DR_MU_0 ((uint32_t)0x00000100) -#define RTC_DR_MU_1 ((uint32_t)0x00000200) -#define RTC_DR_MU_2 ((uint32_t)0x00000400) -#define RTC_DR_MU_3 ((uint32_t)0x00000800) -#define RTC_DR_DT ((uint32_t)0x00000030) -#define RTC_DR_DT_0 ((uint32_t)0x00000010) -#define RTC_DR_DT_1 ((uint32_t)0x00000020) -#define RTC_DR_DU ((uint32_t)0x0000000F) -#define RTC_DR_DU_0 ((uint32_t)0x00000001) -#define RTC_DR_DU_1 ((uint32_t)0x00000002) -#define RTC_DR_DU_2 ((uint32_t)0x00000004) -#define RTC_DR_DU_3 ((uint32_t)0x00000008) - -/******************** Bits definition for RTC_CR register *******************/ -#define RTC_CR_COE ((uint32_t)0x00800000) -#define RTC_CR_OSEL ((uint32_t)0x00600000) -#define RTC_CR_OSEL_0 ((uint32_t)0x00200000) -#define RTC_CR_OSEL_1 ((uint32_t)0x00400000) -#define RTC_CR_POL ((uint32_t)0x00100000) -#define RTC_CR_COSEL ((uint32_t)0x00080000) -#define RTC_CR_BCK ((uint32_t)0x00040000) -#define RTC_CR_SUB1H ((uint32_t)0x00020000) -#define RTC_CR_ADD1H ((uint32_t)0x00010000) -#define RTC_CR_TSIE ((uint32_t)0x00008000) -#define RTC_CR_WUTIE ((uint32_t)0x00004000) -#define RTC_CR_ALRBIE ((uint32_t)0x00002000) -#define RTC_CR_ALRAIE ((uint32_t)0x00001000) -#define RTC_CR_TSE ((uint32_t)0x00000800) -#define RTC_CR_WUTE ((uint32_t)0x00000400) -#define RTC_CR_ALRBE ((uint32_t)0x00000200) -#define RTC_CR_ALRAE ((uint32_t)0x00000100) -#define RTC_CR_DCE ((uint32_t)0x00000080) -#define RTC_CR_FMT ((uint32_t)0x00000040) -#define RTC_CR_BYPSHAD ((uint32_t)0x00000020) -#define RTC_CR_REFCKON ((uint32_t)0x00000010) -#define RTC_CR_TSEDGE ((uint32_t)0x00000008) -#define RTC_CR_WUCKSEL ((uint32_t)0x00000007) -#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) -#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) -#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) - -/******************** Bits definition for RTC_ISR register ******************/ -#define RTC_ISR_RECALPF ((uint32_t)0x00010000) -#define RTC_ISR_TAMP1F ((uint32_t)0x00002000) -#define RTC_ISR_TSOVF ((uint32_t)0x00001000) -#define RTC_ISR_TSF ((uint32_t)0x00000800) -#define RTC_ISR_WUTF ((uint32_t)0x00000400) -#define RTC_ISR_ALRBF ((uint32_t)0x00000200) -#define RTC_ISR_ALRAF ((uint32_t)0x00000100) -#define RTC_ISR_INIT ((uint32_t)0x00000080) -#define RTC_ISR_INITF ((uint32_t)0x00000040) -#define RTC_ISR_RSF ((uint32_t)0x00000020) -#define RTC_ISR_INITS ((uint32_t)0x00000010) -#define RTC_ISR_SHPF ((uint32_t)0x00000008) -#define RTC_ISR_WUTWF ((uint32_t)0x00000004) -#define RTC_ISR_ALRBWF ((uint32_t)0x00000002) -#define RTC_ISR_ALRAWF ((uint32_t)0x00000001) - -/******************** Bits definition for RTC_PRER register *****************/ -#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) -#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF) - -/******************** Bits definition for RTC_WUTR register *****************/ -#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF) - -/******************** Bits definition for RTC_CALIBR register ***************/ -#define RTC_CALIBR_DCS ((uint32_t)0x00000080) -#define RTC_CALIBR_DC ((uint32_t)0x0000001F) - -/******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) -#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) -#define RTC_ALRMAR_DT ((uint32_t)0x30000000) -#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) -#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) -#define RTC_ALRMAR_DU ((uint32_t)0x0F000000) -#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) -#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) -#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) -#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) -#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) -#define RTC_ALRMAR_PM ((uint32_t)0x00400000) -#define RTC_ALRMAR_HT ((uint32_t)0x00300000) -#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) -#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) -#define RTC_ALRMAR_HU ((uint32_t)0x000F0000) -#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) -#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) -#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) -#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) -#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) -#define RTC_ALRMAR_MNT ((uint32_t)0x00007000) -#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) -#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) -#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) -#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00) -#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) -#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) -#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) -#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) -#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) -#define RTC_ALRMAR_ST ((uint32_t)0x00000070) -#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) -#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) -#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) -#define RTC_ALRMAR_SU ((uint32_t)0x0000000F) -#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) -#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) -#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) -#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) - -/******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000) -#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000) -#define RTC_ALRMBR_DT ((uint32_t)0x30000000) -#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000) -#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000) -#define RTC_ALRMBR_DU ((uint32_t)0x0F000000) -#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000) -#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000) -#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000) -#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000) -#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000) -#define RTC_ALRMBR_PM ((uint32_t)0x00400000) -#define RTC_ALRMBR_HT ((uint32_t)0x00300000) -#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000) -#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000) -#define RTC_ALRMBR_HU ((uint32_t)0x000F0000) -#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000) -#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000) -#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000) -#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000) -#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000) -#define RTC_ALRMBR_MNT ((uint32_t)0x00007000) -#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000) -#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000) -#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000) -#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00) -#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100) -#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200) -#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400) -#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800) -#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080) -#define RTC_ALRMBR_ST ((uint32_t)0x00000070) -#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010) -#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020) -#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040) -#define RTC_ALRMBR_SU ((uint32_t)0x0000000F) -#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001) -#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002) -#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004) -#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008) - -/******************** Bits definition for RTC_WPR register ******************/ -#define RTC_WPR_KEY ((uint32_t)0x000000FF) - -/******************** Bits definition for RTC_SSR register ******************/ -#define RTC_SSR_SS ((uint32_t)0x0000FFFF) - -/******************** Bits definition for RTC_SHIFTR register ***************/ -#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) -#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) - -/******************** Bits definition for RTC_TSTR register *****************/ -#define RTC_TSTR_PM ((uint32_t)0x00400000) -#define RTC_TSTR_HT ((uint32_t)0x00300000) -#define RTC_TSTR_HT_0 ((uint32_t)0x00100000) -#define RTC_TSTR_HT_1 ((uint32_t)0x00200000) -#define RTC_TSTR_HU ((uint32_t)0x000F0000) -#define RTC_TSTR_HU_0 ((uint32_t)0x00010000) -#define RTC_TSTR_HU_1 ((uint32_t)0x00020000) -#define RTC_TSTR_HU_2 ((uint32_t)0x00040000) -#define RTC_TSTR_HU_3 ((uint32_t)0x00080000) -#define RTC_TSTR_MNT ((uint32_t)0x00007000) -#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000) -#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000) -#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000) -#define RTC_TSTR_MNU ((uint32_t)0x00000F00) -#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100) -#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200) -#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400) -#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800) -#define RTC_TSTR_ST ((uint32_t)0x00000070) -#define RTC_TSTR_ST_0 ((uint32_t)0x00000010) -#define RTC_TSTR_ST_1 ((uint32_t)0x00000020) -#define RTC_TSTR_ST_2 ((uint32_t)0x00000040) -#define RTC_TSTR_SU ((uint32_t)0x0000000F) -#define RTC_TSTR_SU_0 ((uint32_t)0x00000001) -#define RTC_TSTR_SU_1 ((uint32_t)0x00000002) -#define RTC_TSTR_SU_2 ((uint32_t)0x00000004) -#define RTC_TSTR_SU_3 ((uint32_t)0x00000008) - -/******************** Bits definition for RTC_TSDR register *****************/ -#define RTC_TSDR_WDU ((uint32_t)0x0000E000) -#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000) -#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000) -#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000) -#define RTC_TSDR_MT ((uint32_t)0x00001000) -#define RTC_TSDR_MU ((uint32_t)0x00000F00) -#define RTC_TSDR_MU_0 ((uint32_t)0x00000100) -#define RTC_TSDR_MU_1 ((uint32_t)0x00000200) -#define RTC_TSDR_MU_2 ((uint32_t)0x00000400) -#define RTC_TSDR_MU_3 ((uint32_t)0x00000800) -#define RTC_TSDR_DT ((uint32_t)0x00000030) -#define RTC_TSDR_DT_0 ((uint32_t)0x00000010) -#define RTC_TSDR_DT_1 ((uint32_t)0x00000020) -#define RTC_TSDR_DU ((uint32_t)0x0000000F) -#define RTC_TSDR_DU_0 ((uint32_t)0x00000001) -#define RTC_TSDR_DU_1 ((uint32_t)0x00000002) -#define RTC_TSDR_DU_2 ((uint32_t)0x00000004) -#define RTC_TSDR_DU_3 ((uint32_t)0x00000008) - -/******************** Bits definition for RTC_TSSSR register ****************/ -#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF) - -/******************** Bits definition for RTC_CAL register *****************/ -#define RTC_CALR_CALP ((uint32_t)0x00008000) -#define RTC_CALR_CALW8 ((uint32_t)0x00004000) -#define RTC_CALR_CALW16 ((uint32_t)0x00002000) -#define RTC_CALR_CALM ((uint32_t)0x000001FF) -#define RTC_CALR_CALM_0 ((uint32_t)0x00000001) -#define RTC_CALR_CALM_1 ((uint32_t)0x00000002) -#define RTC_CALR_CALM_2 ((uint32_t)0x00000004) -#define RTC_CALR_CALM_3 ((uint32_t)0x00000008) -#define RTC_CALR_CALM_4 ((uint32_t)0x00000010) -#define RTC_CALR_CALM_5 ((uint32_t)0x00000020) -#define RTC_CALR_CALM_6 ((uint32_t)0x00000040) -#define RTC_CALR_CALM_7 ((uint32_t)0x00000080) -#define RTC_CALR_CALM_8 ((uint32_t)0x00000100) - -/******************** Bits definition for RTC_TAFCR register ****************/ -#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000) -#define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000) -#define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000) -#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000) -#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000) -#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000) -#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000) -#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800) -#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800) -#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000) -#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700) -#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100) -#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200) -#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400) -#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080) -#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004) -#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002) -#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001) - -/******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000) -#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000) -#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000) -#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000) -#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000) -#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF) - -/******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000) -#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000) -#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000) -#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000) -#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000) -#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF) - -/******************** Bits definition for RTC_BKP0R register ****************/ -#define RTC_BKP0R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP1R register ****************/ -#define RTC_BKP1R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP2R register ****************/ -#define RTC_BKP2R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP3R register ****************/ -#define RTC_BKP3R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP4R register ****************/ -#define RTC_BKP4R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP5R register ****************/ -#define RTC_BKP5R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP6R register ****************/ -#define RTC_BKP6R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP7R register ****************/ -#define RTC_BKP7R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP8R register ****************/ -#define RTC_BKP8R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP9R register ****************/ -#define RTC_BKP9R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP10R register ***************/ -#define RTC_BKP10R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP11R register ***************/ -#define RTC_BKP11R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP12R register ***************/ -#define RTC_BKP12R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP13R register ***************/ -#define RTC_BKP13R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP14R register ***************/ -#define RTC_BKP14R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP15R register ***************/ -#define RTC_BKP15R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP16R register ***************/ -#define RTC_BKP16R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP17R register ***************/ -#define RTC_BKP17R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP18R register ***************/ -#define RTC_BKP18R ((uint32_t)0xFFFFFFFF) - -/******************** Bits definition for RTC_BKP19R register ***************/ -#define RTC_BKP19R ((uint32_t)0xFFFFFFFF) - - -/******************************************************************************/ -/* */ -/* SD host Interface */ -/* */ -/******************************************************************************/ -/****************** Bit definition for SDIO_POWER register ******************/ -#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */ -#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!<Bit 0 */ -#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!<Bit 1 */ - -/****************** Bit definition for SDIO_CLKCR register ******************/ -#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!<Clock divide factor */ -#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!<Clock enable bit */ -#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!<Power saving configuration bit */ -#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!<Clock divider bypass enable bit */ - -#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */ -#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!<Bit 0 */ -#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!<Bit 1 */ - -#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!<SDIO_CK dephasing selection bit */ -#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!<HW Flow Control enable */ - -/******************* Bit definition for SDIO_ARG register *******************/ -#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */ - -/******************* Bit definition for SDIO_CMD register *******************/ -#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!<Command Index */ - -#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */ -#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */ -#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */ - -#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!<CPSM Waits for Interrupt Request */ -#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */ -#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */ -#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!<SD I/O suspend command */ -#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!<Enable CMD completion */ -#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!<Not Interrupt Enable */ -#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!<CE-ATA command */ - -/***************** Bit definition for SDIO_RESPCMD register *****************/ -#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!<Response command index */ - -/****************** Bit definition for SDIO_RESP0 register ******************/ -#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ - -/****************** Bit definition for SDIO_RESP1 register ******************/ -#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ - -/****************** Bit definition for SDIO_RESP2 register ******************/ -#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ - -/****************** Bit definition for SDIO_RESP3 register ******************/ -#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ - -/****************** Bit definition for SDIO_RESP4 register ******************/ -#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ - -/****************** Bit definition for SDIO_DTIMER register *****************/ -#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */ - -/****************** Bit definition for SDIO_DLEN register *******************/ -#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */ - -/****************** Bit definition for SDIO_DCTRL register ******************/ -#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!<Data transfer enabled bit */ -#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!<Data transfer direction selection */ -#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!<Data transfer mode selection */ -#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!<DMA enabled bit */ - -#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */ -#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!<Bit 0 */ -#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!<Bit 1 */ -#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!<Bit 2 */ -#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!<Bit 3 */ - -#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!<Read wait start */ -#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!<Read wait stop */ -#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!<Read wait mode */ -#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!<SD I/O enable functions */ - -/****************** Bit definition for SDIO_DCOUNT register *****************/ -#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */ - -/****************** Bit definition for SDIO_STA register ********************/ -#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */ -#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */ -#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */ -#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */ -#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */ -#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */ -#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */ -#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */ -#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */ -#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */ -#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */ -#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */ -#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */ -#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */ -#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ -#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */ -#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */ -#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */ -#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */ -#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */ -#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */ -#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */ -#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */ -#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */ - -/******************* Bit definition for SDIO_ICR register *******************/ -#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */ -#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */ -#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */ -#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */ -#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */ -#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */ -#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */ -#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */ -#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */ -#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */ -#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */ -#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */ -#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */ - -/****************** Bit definition for SDIO_MASK register *******************/ -#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */ -#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */ -#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */ -#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */ -#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */ -#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */ -#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */ -#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */ -#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */ -#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */ -#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */ -#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */ -#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */ -#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */ -#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */ -#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */ -#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */ -#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */ -#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */ -#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */ -#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */ -#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */ -#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */ -#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */ - -/***************** Bit definition for SDIO_FIFOCNT register *****************/ -#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */ - -/****************** Bit definition for SDIO_FIFO register *******************/ -#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */ - -/******************************************************************************/ -/* */ -/* Serial Peripheral Interface */ -/* */ -/******************************************************************************/ -/******************* Bit definition for SPI_CR1 register ********************/ -#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!<Clock Phase */ -#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!<Clock Polarity */ -#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!<Master Selection */ - -#define SPI_CR1_BR ((uint16_t)0x0038) /*!<BR[2:0] bits (Baud Rate Control) */ -#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!<Bit 0 */ -#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!<Bit 1 */ -#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!<Bit 2 */ - -#define SPI_CR1_SPE ((uint16_t)0x0040) /*!<SPI Enable */ -#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!<Frame Format */ -#define SPI_CR1_SSI ((uint16_t)0x0100) /*!<Internal slave select */ -#define SPI_CR1_SSM ((uint16_t)0x0200) /*!<Software slave management */ -#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!<Receive only */ -#define SPI_CR1_DFF ((uint16_t)0x0800) /*!<Data Frame Format */ -#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!<Transmit CRC next */ -#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!<Hardware CRC calculation enable */ -#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!<Output enable in bidirectional mode */ -#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!<Bidirectional data mode enable */ - -/******************* Bit definition for SPI_CR2 register ********************/ -#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!<Rx Buffer DMA Enable */ -#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!<Tx Buffer DMA Enable */ -#define SPI_CR2_SSOE ((uint8_t)0x04) /*!<SS Output Enable */ -#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!<Error Interrupt Enable */ -#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!<RX buffer Not Empty Interrupt Enable */ -#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!<Tx buffer Empty Interrupt Enable */ - -/******************** Bit definition for SPI_SR register ********************/ -#define SPI_SR_RXNE ((uint8_t)0x01) /*!<Receive buffer Not Empty */ -#define SPI_SR_TXE ((uint8_t)0x02) /*!<Transmit buffer Empty */ -#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!<Channel side */ -#define SPI_SR_UDR ((uint8_t)0x08) /*!<Underrun flag */ -#define SPI_SR_CRCERR ((uint8_t)0x10) /*!<CRC Error flag */ -#define SPI_SR_MODF ((uint8_t)0x20) /*!<Mode fault */ -#define SPI_SR_OVR ((uint8_t)0x40) /*!<Overrun flag */ -#define SPI_SR_BSY ((uint8_t)0x80) /*!<Busy flag */ - -/******************** Bit definition for SPI_DR register ********************/ -#define SPI_DR_DR ((uint16_t)0xFFFF) /*!<Data Register */ - -/******************* Bit definition for SPI_CRCPR register ******************/ -#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!<CRC polynomial register */ - -/****************** Bit definition for SPI_RXCRCR register ******************/ -#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!<Rx CRC Register */ - -/****************** Bit definition for SPI_TXCRCR register ******************/ -#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!<Tx CRC Register */ - -/****************** Bit definition for SPI_I2SCFGR register *****************/ -#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */ - -#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */ -#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */ -#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */ - -#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */ - -#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */ -#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */ -#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */ - -#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */ - -#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */ -#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */ -#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */ - -#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */ -#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */ - -/****************** Bit definition for SPI_I2SPR register *******************/ -#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */ -#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */ -#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */ - -/******************************************************************************/ -/* */ -/* SYSCFG */ -/* */ -/******************************************************************************/ -/****************** Bit definition for SYSCFG_MEMRMP register ***************/ -#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */ -#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) -#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) -#define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004) - -#define SYSCFG_MEMRMP_UFB_MODE ((uint32_t)0x00000100) /*!< User Flash Bank mode */ - -/****************** Bit definition for SYSCFG_PMC register ******************/ -#define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */ -/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */ -#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL - -/***************** Bit definition for SYSCFG_EXTICR1 register ***************/ -#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!<EXTI 0 configuration */ -#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!<EXTI 1 configuration */ -#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!<EXTI 2 configuration */ -#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!<EXTI 3 configuration */ -/** - * @brief EXTI0 configuration - */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!<PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!<PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!<PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!<PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!<PE[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!<PF[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!<PG[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007) /*!<PH[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PI ((uint16_t)0x0008) /*!<PI[0] pin */ - -/** - * @brief EXTI1 configuration - */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!<PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!<PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!<PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!<PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!<PE[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!<PF[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!<PG[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070) /*!<PH[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PI ((uint16_t)0x0080) /*!<PI[1] pin */ - -/** - * @brief EXTI2 configuration - */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!<PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!<PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!<PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!<PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!<PE[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!<PF[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!<PG[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0700) /*!<PH[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PI ((uint16_t)0x0800) /*!<PI[2] pin */ - -/** - * @brief EXTI3 configuration - */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!<PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!<PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!<PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!<PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!<PE[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!<PF[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!<PG[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PH ((uint16_t)0x7000) /*!<PH[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PI ((uint16_t)0x8000) /*!<PI[3] pin */ - -/***************** Bit definition for SYSCFG_EXTICR2 register ***************/ -#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!<EXTI 4 configuration */ -#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!<EXTI 5 configuration */ -#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!<EXTI 6 configuration */ -#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!<EXTI 7 configuration */ -/** - * @brief EXTI4 configuration - */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!<PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!<PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!<PC[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!<PD[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!<PE[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!<PF[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!<PG[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PH ((uint16_t)0x0007) /*!<PH[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PI ((uint16_t)0x0008) /*!<PI[4] pin */ - -/** - * @brief EXTI5 configuration - */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!<PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!<PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!<PC[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!<PD[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!<PE[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!<PF[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!<PG[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PH ((uint16_t)0x0070) /*!<PH[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PI ((uint16_t)0x0080) /*!<PI[5] pin */ - -/** - * @brief EXTI6 configuration - */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!<PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!<PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!<PC[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!<PD[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!<PE[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!<PF[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!<PG[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PH ((uint16_t)0x0700) /*!<PH[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PI ((uint16_t)0x0800) /*!<PI[6] pin */ - -/** - * @brief EXTI7 configuration - */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!<PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!<PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!<PC[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!<PD[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!<PE[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!<PF[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!<PG[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PH ((uint16_t)0x7000) /*!<PH[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PI ((uint16_t)0x8000) /*!<PI[7] pin */ - -/***************** Bit definition for SYSCFG_EXTICR3 register ***************/ -#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!<EXTI 8 configuration */ -#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!<EXTI 9 configuration */ -#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!<EXTI 10 configuration */ -#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!<EXTI 11 configuration */ - -/** - * @brief EXTI8 configuration - */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!<PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!<PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!<PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!<PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!<PE[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!<PF[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!<PG[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PH ((uint16_t)0x0007) /*!<PH[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PI ((uint16_t)0x0008) /*!<PI[8] pin */ - -/** - * @brief EXTI9 configuration - */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!<PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!<PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!<PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!<PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!<PE[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!<PF[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!<PG[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PH ((uint16_t)0x0070) /*!<PH[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PI ((uint16_t)0x0080) /*!<PI[9] pin */ - -/** - * @brief EXTI10 configuration - */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!<PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!<PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!<PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!<PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!<PE[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!<PF[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!<PG[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PH ((uint16_t)0x0700) /*!<PH[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PI ((uint16_t)0x0800) /*!<PI[10] pin */ - -/** - * @brief EXTI11 configuration - */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!<PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!<PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!<PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!<PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!<PE[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!<PF[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!<PG[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PH ((uint16_t)0x7000) /*!<PH[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PI ((uint16_t)0x8000) /*!<PI[11] pin */ - -/***************** Bit definition for SYSCFG_EXTICR4 register ***************/ -#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!<EXTI 12 configuration */ -#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!<EXTI 13 configuration */ -#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!<EXTI 14 configuration */ -#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!<EXTI 15 configuration */ -/** - * @brief EXTI12 configuration - */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!<PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!<PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!<PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!<PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!<PE[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!<PF[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!<PG[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PH ((uint16_t)0x0007) /*!<PH[12] pin */ - -/** - * @brief EXTI13 configuration - */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!<PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!<PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!<PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!<PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!<PE[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!<PF[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!<PG[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PH ((uint16_t)0x0070) /*!<PH[13] pin */ - -/** - * @brief EXTI14 configuration - */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!<PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!<PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!<PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!<PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!<PE[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!<PF[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!<PG[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PH ((uint16_t)0x0700) /*!<PH[14] pin */ - -/** - * @brief EXTI15 configuration - */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!<PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!<PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!<PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!<PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!<PE[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!<PF[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!<PG[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PH ((uint16_t)0x7000) /*!<PH[15] pin */ - -/****************** Bit definition for SYSCFG_CMPCR register ****************/ -#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */ -#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */ - -/******************************************************************************/ -/* */ -/* TIM */ -/* */ -/******************************************************************************/ -/******************* Bit definition for TIM_CR1 register ********************/ -#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */ -#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */ -#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */ -#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */ -#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */ - -#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */ -#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */ -#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */ - -#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */ - -#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */ -#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */ -#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */ - -/******************* Bit definition for TIM_CR2 register ********************/ -#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */ -#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */ -#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */ - -#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */ -#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */ -#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */ -#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */ - -#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */ -#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */ -#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */ -#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */ -#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */ -#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */ -#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */ -#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */ - -/******************* Bit definition for TIM_SMCR register *******************/ -#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */ -#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */ -#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */ -#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */ - -#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */ -#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */ -#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */ -#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */ - -#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */ - -#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */ -#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */ -#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */ -#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */ -#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */ - -#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */ -#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */ -#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */ - -#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */ -#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */ - -/******************* Bit definition for TIM_DIER register *******************/ -#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */ -#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */ -#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */ -#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */ -#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */ -#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */ -#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */ -#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */ -#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */ -#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */ -#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */ -#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */ -#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */ -#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */ -#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */ - -/******************** Bit definition for TIM_SR register ********************/ -#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */ -#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */ -#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */ -#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */ -#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */ -#define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */ -#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */ -#define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */ -#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */ -#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */ -#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */ -#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */ - -/******************* Bit definition for TIM_EGR register ********************/ -#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */ -#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */ -#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */ -#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */ -#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */ -#define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */ -#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */ -#define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */ - -/****************** Bit definition for TIM_CCMR1 register *******************/ -#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ -#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */ -#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */ - -#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */ -#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */ - -#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ -#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */ -#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */ -#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */ - -#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */ - -#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ -#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */ -#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */ - -#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */ -#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */ - -#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ -#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */ -#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */ -#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */ - -#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */ - -/*----------------------------------------------------------------------------*/ - -#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ -#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */ -#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */ - -#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ -#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */ -#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */ -#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */ -#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */ - -#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ -#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */ -#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */ - -#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ -#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */ -#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */ -#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */ -#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */ - -/****************** Bit definition for TIM_CCMR2 register *******************/ -#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ -#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */ -#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */ - -#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */ -#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */ - -#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ -#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */ -#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */ -#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */ - -#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */ - -#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ -#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */ -#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */ - -#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */ -#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */ - -#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ -#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */ -#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */ -#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */ - -#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */ - -/*----------------------------------------------------------------------------*/ - -#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ -#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */ -#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */ - -#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ -#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */ -#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */ -#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */ -#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */ - -#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ -#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */ -#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */ - -#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ -#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */ -#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */ -#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */ -#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */ - -/******************* Bit definition for TIM_CCER register *******************/ -#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */ -#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */ -#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */ -#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */ -#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */ -#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */ -#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */ -#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */ -#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */ -#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */ -#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */ -#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */ -#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */ -#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */ -#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */ - -/******************* Bit definition for TIM_CNT register ********************/ -#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */ - -/******************* Bit definition for TIM_PSC register ********************/ -#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */ - -/******************* Bit definition for TIM_ARR register ********************/ -#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */ - -/******************* Bit definition for TIM_RCR register ********************/ -#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */ - -/******************* Bit definition for TIM_CCR1 register *******************/ -#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */ - -/******************* Bit definition for TIM_CCR2 register *******************/ -#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */ - -/******************* Bit definition for TIM_CCR3 register *******************/ -#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */ - -/******************* Bit definition for TIM_CCR4 register *******************/ -#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */ - -/******************* Bit definition for TIM_BDTR register *******************/ -#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ -#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */ -#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */ -#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */ -#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */ -#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */ -#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */ -#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */ -#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */ - -#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */ -#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */ -#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */ - -#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */ -#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */ -#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */ -#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */ -#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */ -#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */ - -/******************* Bit definition for TIM_DCR register ********************/ -#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */ -#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */ -#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */ -#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */ -#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */ -#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */ - -#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */ -#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */ -#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */ -#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */ -#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */ -#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */ - -/******************* Bit definition for TIM_DMAR register *******************/ -#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */ - -/******************* Bit definition for TIM_OR register *********************/ -#define TIM_OR_TI4_RMP ((uint16_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */ -#define TIM_OR_TI4_RMP_0 ((uint16_t)0x0040) /*!<Bit 0 */ -#define TIM_OR_TI4_RMP_1 ((uint16_t)0x0080) /*!<Bit 1 */ -#define TIM_OR_ITR1_RMP ((uint16_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */ -#define TIM_OR_ITR1_RMP_0 ((uint16_t)0x0400) /*!<Bit 0 */ -#define TIM_OR_ITR1_RMP_1 ((uint16_t)0x0800) /*!<Bit 1 */ - - -/******************************************************************************/ -/* */ -/* Universal Synchronous Asynchronous Receiver Transmitter */ -/* */ -/******************************************************************************/ -/******************* Bit definition for USART_SR register *******************/ -#define USART_SR_PE ((uint16_t)0x0001) /*!<Parity Error */ -#define USART_SR_FE ((uint16_t)0x0002) /*!<Framing Error */ -#define USART_SR_NE ((uint16_t)0x0004) /*!<Noise Error Flag */ -#define USART_SR_ORE ((uint16_t)0x0008) /*!<OverRun Error */ -#define USART_SR_IDLE ((uint16_t)0x0010) /*!<IDLE line detected */ -#define USART_SR_RXNE ((uint16_t)0x0020) /*!<Read Data Register Not Empty */ -#define USART_SR_TC ((uint16_t)0x0040) /*!<Transmission Complete */ -#define USART_SR_TXE ((uint16_t)0x0080) /*!<Transmit Data Register Empty */ -#define USART_SR_LBD ((uint16_t)0x0100) /*!<LIN Break Detection Flag */ -#define USART_SR_CTS ((uint16_t)0x0200) /*!<CTS Flag */ - -/******************* Bit definition for USART_DR register *******************/ -#define USART_DR_DR ((uint16_t)0x01FF) /*!<Data value */ - -/****************** Bit definition for USART_BRR register *******************/ -#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!<Fraction of USARTDIV */ -#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!<Mantissa of USARTDIV */ - -/****************** Bit definition for USART_CR1 register *******************/ -#define USART_CR1_SBK ((uint16_t)0x0001) /*!<Send Break */ -#define USART_CR1_RWU ((uint16_t)0x0002) /*!<Receiver wakeup */ -#define USART_CR1_RE ((uint16_t)0x0004) /*!<Receiver Enable */ -#define USART_CR1_TE ((uint16_t)0x0008) /*!<Transmitter Enable */ -#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!<IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!<RXNE Interrupt Enable */ -#define USART_CR1_TCIE ((uint16_t)0x0040) /*!<Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!<PE Interrupt Enable */ -#define USART_CR1_PEIE ((uint16_t)0x0100) /*!<PE Interrupt Enable */ -#define USART_CR1_PS ((uint16_t)0x0200) /*!<Parity Selection */ -#define USART_CR1_PCE ((uint16_t)0x0400) /*!<Parity Control Enable */ -#define USART_CR1_WAKE ((uint16_t)0x0800) /*!<Wakeup method */ -#define USART_CR1_M ((uint16_t)0x1000) /*!<Word length */ -#define USART_CR1_UE ((uint16_t)0x2000) /*!<USART Enable */ -#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!<USART Oversampling by 8 enable */ - -/****************** Bit definition for USART_CR2 register *******************/ -#define USART_CR2_ADD ((uint16_t)0x000F) /*!<Address of the USART node */ -#define USART_CR2_LBDL ((uint16_t)0x0020) /*!<LIN Break Detection Length */ -#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!<LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL ((uint16_t)0x0100) /*!<Last Bit Clock pulse */ -#define USART_CR2_CPHA ((uint16_t)0x0200) /*!<Clock Phase */ -#define USART_CR2_CPOL ((uint16_t)0x0400) /*!<Clock Polarity */ -#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!<Clock Enable */ - -#define USART_CR2_STOP ((uint16_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */ -#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!<Bit 0 */ -#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!<Bit 1 */ - -#define USART_CR2_LINEN ((uint16_t)0x4000) /*!<LIN mode enable */ - -/****************** Bit definition for USART_CR3 register *******************/ -#define USART_CR3_EIE ((uint16_t)0x0001) /*!<Error Interrupt Enable */ -#define USART_CR3_IREN ((uint16_t)0x0002) /*!<IrDA mode Enable */ -#define USART_CR3_IRLP ((uint16_t)0x0004) /*!<IrDA Low-Power */ -#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!<Half-Duplex Selection */ -#define USART_CR3_NACK ((uint16_t)0x0010) /*!<Smartcard NACK enable */ -#define USART_CR3_SCEN ((uint16_t)0x0020) /*!<Smartcard mode enable */ -#define USART_CR3_DMAR ((uint16_t)0x0040) /*!<DMA Enable Receiver */ -#define USART_CR3_DMAT ((uint16_t)0x0080) /*!<DMA Enable Transmitter */ -#define USART_CR3_RTSE ((uint16_t)0x0100) /*!<RTS Enable */ -#define USART_CR3_CTSE ((uint16_t)0x0200) /*!<CTS Enable */ -#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!<CTS Interrupt Enable */ -#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!<USART One bit method enable */ - -/****************** Bit definition for USART_GTPR register ******************/ -#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */ -#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!<Bit 0 */ -#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!<Bit 1 */ -#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!<Bit 2 */ -#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!<Bit 3 */ -#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!<Bit 4 */ -#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!<Bit 5 */ -#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!<Bit 6 */ -#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!<Bit 7 */ - -#define USART_GTPR_GT ((uint16_t)0xFF00) /*!<Guard time value */ - -/******************************************************************************/ -/* */ -/* Window WATCHDOG */ -/* */ -/******************************************************************************/ -/******************* Bit definition for WWDG_CR register ********************/ -#define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */ -#define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */ -#define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */ -#define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */ -#define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */ -#define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */ -#define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */ -#define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */ - -#define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */ - -/******************* Bit definition for WWDG_CFR register *******************/ -#define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */ -#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */ -#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */ -#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */ -#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */ -#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */ -#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */ -#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */ - -#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */ -#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */ -#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */ - -#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */ - -/******************* Bit definition for WWDG_SR register ********************/ -#define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */ - - -/******************************************************************************/ -/* */ -/* DBG */ -/* */ -/******************************************************************************/ -/******************** Bit definition for DBGMCU_IDCODE register *************/ -#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) -#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) - -/******************** Bit definition for DBGMCU_CR register *****************/ -#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) -#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) -#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) -#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) - -#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) -#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */ -#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */ - -/******************** Bit definition for DBGMCU_APB1_FZ register ************/ -#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) -#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) -#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) -#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008) -#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) -#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) -#define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040) -#define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080) -#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) -#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) -#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) -#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) -#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) -#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) -#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000) -#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000) -#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000) -/* Old IWDGSTOP bit definition, maintained for legacy purpose */ -#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP - -/******************** Bit definition for DBGMCU_APB2_FZ register ************/ -#define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001) -#define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002) -#define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000) -#define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000) -#define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000) - -/******************************************************************************/ -/* */ -/* Ethernet MAC Registers bits definitions */ -/* */ -/******************************************************************************/ -/* Bit definition for Ethernet MAC Control Register register */ -#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ -#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ -#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ -#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ - #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ - #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ - #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ - #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ - #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ - #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ - #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ -#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ -#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ -#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ -#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ -#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ -#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ -#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ -#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ -#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling - a transmission attempt during retries after a collision: 0 =< r <2^k */ - #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ - #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ - #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ - #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ -#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ -#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ -#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ - -/* Bit definition for Ethernet MAC Frame Filter Register */ -#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ -#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ -#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ -#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ -#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ - #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ - #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ - #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ -#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ -#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ -#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ -#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ -#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ -#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ - -/* Bit definition for Ethernet MAC Hash Table High Register */ -#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ - -/* Bit definition for Ethernet MAC Hash Table Low Register */ -#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ - -/* Bit definition for Ethernet MAC MII Address Register */ -#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ -#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ -#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ - #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ - #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */ - #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ - #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ - #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */ -#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ -#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ - -/* Bit definition for Ethernet MAC MII Data Register */ -#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ - -/* Bit definition for Ethernet MAC Flow Control Register */ -#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ -#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ -#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ - #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ - #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ - #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ - #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ -#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ -#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ -#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ -#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ - -/* Bit definition for Ethernet MAC VLAN Tag Register */ -#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ -#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ - -/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ -#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ -/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. - Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ -/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask - Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask - Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask - Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask - Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - - RSVD - Filter1 Command - RSVD - Filter0 Command - Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset - Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 - Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ - -/* Bit definition for Ethernet MAC PMT Control and Status Register */ -#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ -#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ -#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ -#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ -#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ -#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ -#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ - -/* Bit definition for Ethernet MAC Status Register */ -#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ -#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ -#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ -#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ -#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ - -/* Bit definition for Ethernet MAC Interrupt Mask Register */ -#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ -#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ - -/* Bit definition for Ethernet MAC Address0 High Register */ -#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ - -/* Bit definition for Ethernet MAC Address0 Low Register */ -#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ - -/* Bit definition for Ethernet MAC Address1 High Register */ -#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ -#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ -#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ - #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ - #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ - #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ - #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ - #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ - #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ -#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ - -/* Bit definition for Ethernet MAC Address1 Low Register */ -#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ - -/* Bit definition for Ethernet MAC Address2 High Register */ -#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ -#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ -#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ - #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ - #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ - #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ - #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ - #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ - #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ -#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ - -/* Bit definition for Ethernet MAC Address2 Low Register */ -#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ - -/* Bit definition for Ethernet MAC Address3 High Register */ -#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ -#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ -#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ - #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ - #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ - #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ - #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ - #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ - #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ -#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ - -/* Bit definition for Ethernet MAC Address3 Low Register */ -#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ - -/******************************************************************************/ -/* Ethernet MMC Registers bits definition */ -/******************************************************************************/ - -/* Bit definition for Ethernet MMC Contol Register */ -#define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */ -#define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */ -#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ -#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ -#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ -#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ - -/* Bit definition for Ethernet MMC Receive Interrupt Register */ -#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ -#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ -#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Transmit Interrupt Register */ -#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ -#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ -#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ -#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ -#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ -#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ -#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ -#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ -#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ -#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ - -/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ -#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ - -/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ -#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ - -/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ -#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ - -/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ -#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ - -/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ -#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ - -/******************************************************************************/ -/* Ethernet PTP Registers bits definition */ -/******************************************************************************/ - -/* Bit definition for Ethernet PTP Time Stamp Contol Register */ -#define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */ -#define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */ -#define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */ -#define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */ -#define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */ -#define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */ -#define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */ -#define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */ -#define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */ - -#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ -#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ -#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ -#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ -#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ -#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ - -/* Bit definition for Ethernet PTP Sub-Second Increment Register */ -#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ - -/* Bit definition for Ethernet PTP Time Stamp High Register */ -#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ - -/* Bit definition for Ethernet PTP Time Stamp Low Register */ -#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ -#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ - -/* Bit definition for Ethernet PTP Time Stamp High Update Register */ -#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ - -/* Bit definition for Ethernet PTP Time Stamp Low Update Register */ -#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ -#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ - -/* Bit definition for Ethernet PTP Time Stamp Addend Register */ -#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ - -/* Bit definition for Ethernet PTP Target Time High Register */ -#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ - -/* Bit definition for Ethernet PTP Target Time Low Register */ -#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ - -/* Bit definition for Ethernet PTP Time Stamp Status Register */ -#define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */ -#define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */ - -/******************************************************************************/ -/* Ethernet DMA Registers bits definition */ -/******************************************************************************/ - -/* Bit definition for Ethernet DMA Bus Mode Register */ -#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ -#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ -#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ -#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ - #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ - #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ - #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ - #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ - #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ - #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ - #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ - #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ - #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ - #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ - #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ - #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ -#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ -#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ - #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ -#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ - #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ - #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ - #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ - #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ - #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ - #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ - #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ - #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ - #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ - #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ - #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ - #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ -#define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */ -#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ -#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ -#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ - -/* Bit definition for Ethernet DMA Transmit Poll Demand Register */ -#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ - -/* Bit definition for Ethernet DMA Receive Poll Demand Register */ -#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ - -/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ -#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ - -/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ -#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ - -/* Bit definition for Ethernet DMA Status Register */ -#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ -#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ -#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ -#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ - /* combination with EBS[2:0] for GetFlagStatus function */ - #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ - #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ - #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ -#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ - #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ - #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ - #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ - #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ - #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ - #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ -#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ - #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ - #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ - #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ - #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ - #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ - #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ -#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ -#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ -#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ -#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ -#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ -#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ -#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ -#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ -#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ -#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ -#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ -#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ -#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ -#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ -#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ - -/* Bit definition for Ethernet DMA Operation Mode Register */ -#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ -#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ -#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ -#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ -#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ -#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ - #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ - #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ - #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ - #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ - #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ - #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ - #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ - #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ -#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ -#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ -#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ -#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ - #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ - #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ - #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ - #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ -#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ -#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ - -/* Bit definition for Ethernet DMA Interrupt Enable Register */ -#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ -#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ -#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ -#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ -#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ -#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ -#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ -#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ -#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ -#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ -#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ -#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ -#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ -#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ -#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ - -/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ -#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ -#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ -#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ -#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ - -/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ -#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ - -/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ -#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ - -/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ -#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ - -/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ -#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ - -/** - * - */ - - /** - * @} - */ - -#ifdef USE_STDPERIPH_DRIVER - #include "stm32f4xx_conf.h" -#endif /* USE_STDPERIPH_DRIVER */ - -/** @addtogroup Exported_macro - * @{ - */ - -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32F4xx_H */ - -/** - * @} - */ - - /** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4XX/system_stm32f4xx.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,573 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f4xx.c - * @author MCD Application Team - * @version V1.1.0 - * @date 11-January-2013 - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. - * This file contains the system clock configuration for STM32F4xx devices, - * and is generated by the clock configuration tool - * stm32f4xx_Clock_Configuration_V1.1.0.xls - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier - * and Divider factors, AHB/APBx prescalers and Flash settings), - * depending on the configuration made in the clock xls tool. - * This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f4xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the HSI (16 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to - * configure the system clock before to branch to main program. - * - * 3. If the system clock source selected by user fails to startup, the SystemInit() - * function will do nothing and HSI still used as system clock source. User can - * add some code to deal with this issue inside the SetSysClock() function. - * - * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define - * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or - * through PLL, and you are using different crystal you have to adapt the HSE - * value to your own configuration. - * - * 5. This file configures the system clock as follows: - *============================================================================= - *============================================================================= - * Supported STM32F40xx/41xx/427x/437x devices - *----------------------------------------------------------------------------- - * System Clock source | PLL (HSE) - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 168000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 168000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 4 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 2 - *----------------------------------------------------------------------------- - * HSE Frequency(Hz) | 8000000 - *----------------------------------------------------------------------------- - * PLL_M | 8 - *----------------------------------------------------------------------------- - * PLL_N | 336 - *----------------------------------------------------------------------------- - * PLL_P | 2 - *----------------------------------------------------------------------------- - * PLL_Q | 7 - *----------------------------------------------------------------------------- - * PLLI2S_N | 271 - *----------------------------------------------------------------------------- - * PLLI2S_R | 2 - *----------------------------------------------------------------------------- - * I2S input clock | NA - *----------------------------------------------------------------------------- - * VDD(V) | 3.3 - *----------------------------------------------------------------------------- - * Main regulator output voltage | Scale1 mode - *----------------------------------------------------------------------------- - * Flash Latency(WS) | 5 - *----------------------------------------------------------------------------- - * Prefetch Buffer | ON - *----------------------------------------------------------------------------- - * Instruction cache | ON - *----------------------------------------------------------------------------- - * Data cache | ON - *----------------------------------------------------------------------------- - * Require 48MHz for USB OTG FS, | Disabled - * SDIO and RNG clock | - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f4xx_system - * @{ - */ - -/** @addtogroup STM32F4xx_System_Private_Includes - * @{ - */ - -#include "stm32f4xx.h" - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Defines - * @{ - */ - -/************************* Miscellaneous Configuration ************************/ -/*!< Uncomment the following line if you need to use external SRAM mounted - on STM324xG_EVAL/STM324x7I_EVAL boards as data memory */ -/* #define DATA_IN_ExtSRAM */ - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -/******************************************************************************/ - -/************************* PLL Parameters *************************************/ -/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ -#define PLL_M 8 -#define PLL_N 336 - -/* SYSCLK = PLL_VCO / PLL_P */ -#define PLL_P 2 - -/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ -#define PLL_Q 7 - -#define PLLI2S_N 271 -#define PLLI2S_R 2 - -/******************************************************************************/ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Variables - * @{ - */ - - uint32_t SystemCoreClock = 168000000; - -const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes - * @{ - */ - -static void SetSysClock(void); -#ifdef DATA_IN_ExtSRAM - static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemFrequency variable. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - #endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; - -#ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM */ - - /* Configure the System clock source, PLL Multiplier and Divider factors, - AHB/APBx prescalers and Flash settings ----------------------------------*/ - SetSysClock(); - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N - SYSCLK = PLL_VCO / PLL_P - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - SystemCoreClock = pllvco/pllp; - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK frequency --------------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @Note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -static void SetSysClock(void) -{ -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */ - RCC->APB1ENR |= RCC_APB1ENR_PWREN; - PWR->CR |= PWR_CR_VOS; - - /* HCLK = SYSCLK / 1*/ - RCC->CFGR |= RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK / 2*/ - RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; - - /* PCLK1 = HCLK / 4*/ - RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; - - /* Configure the main PLL */ - RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | - (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); - - /* Enable the main PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till the main PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Configure the I2S PLL */ - RCC->PLLI2SCFGR = (PLLI2S_N << 6) | (PLLI2S_R << 28); - - /* Enable the I2S PLL */ - RCC->CR |= RCC_CR_PLLI2SON; - - /* Wait until the I2S PLL is ready */ - while (!(RCC->CR & RCC_CR_PLLI2SRDY)); - - /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ - FLASH->ACR = FLASH_ACR_PRFTEN |FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; - - /* Select the main PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= RCC_CFGR_SW_PLL; - - /* Wait till the main PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } - -} - -/** - * @brief Setup the external memory controller. Called in startup_stm32f4xx.s - * before jump to __main - * @param None - * @retval None - */ -#ifdef DATA_IN_ExtSRAM -/** - * @brief Setup the external memory controller. - * Called in startup_stm32f4xx.s before jump to main. - * This function configures the external SRAM mounted on STM324xG_EVAL/STM324x7I boards - * This SRAM will be used as program data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ -/*-- GPIOs Configuration -----------------------------------------------------*/ -/* - +-------------------+--------------------+------------------+------------------+ - + SRAM pins assignment + - +-------------------+--------------------+------------------+------------------+ - | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | - | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | - | PD4 <-> FSMC_NOE | PE2 <-> FSMC_A23 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | - | PD5 <-> FSMC_NWE | PE3 <-> FSMC_A19 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | - | PD8 <-> FSMC_D13 | PE4 <-> FSMC_A20 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | - | PD9 <-> FSMC_D14 | PE5 <-> FSMC_A21 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | - | PD10 <-> FSMC_D15 | PE6 <-> FSMC_A22 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | - | PD11 <-> FSMC_A16 | PE7 <-> FSMC_D4 | PF13 <-> FSMC_A7 |------------------+ - | PD12 <-> FSMC_A17 | PE8 <-> FSMC_D5 | PF14 <-> FSMC_A8 | - | PD13 <-> FSMC_A18 | PE9 <-> FSMC_D6 | PF15 <-> FSMC_A9 | - | PD14 <-> FSMC_D0 | PE10 <-> FSMC_D7 |------------------+ - | PD15 <-> FSMC_D1 | PE11 <-> FSMC_D8 | - +-------------------| PE12 <-> FSMC_D9 | - | PE13 <-> FSMC_D10 | - | PE14 <-> FSMC_D11 | - | PE15 <-> FSMC_D12 | - +--------------------+ -*/ - /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ - RCC->AHB1ENR |= 0x00000078; - - /* Connect PDx pins to FSMC Alternate function */ - GPIOD->AFR[0] = 0x00cc00cc; - GPIOD->AFR[1] = 0xcccccccc; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xaaaa0a0a; - /* Configure PDx pins speed to 100 MHz */ - GPIOD->OSPEEDR = 0xffff0f0f; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FSMC Alternate function */ - GPIOE->AFR[0] = 0xcccccccc; - GPIOE->AFR[1] = 0xcccccccc; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xaaaaaaaa; - /* Configure PEx pins speed to 100 MHz */ - GPIOE->OSPEEDR = 0xffffffff; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FSMC Alternate function */ - GPIOF->AFR[0] = 0x00cccccc; - GPIOF->AFR[1] = 0xcccc0000; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xaa000aaa; - /* Configure PFx pins speed to 100 MHz */ - GPIOF->OSPEEDR = 0xff000fff; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FSMC Alternate function */ - GPIOG->AFR[0] = 0x00cccccc; - GPIOG->AFR[1] = 0x000000c0; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0x00080aaa; - /* Configure PGx pins speed to 100 MHz */ - GPIOG->OSPEEDR = 0x000c0fff; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - -/*-- FSMC Configuration ------------------------------------------------------*/ - /* Enable the FSMC interface clock */ - RCC->AHB3ENR |= 0x00000001; - - /* Configure and enable Bank1_SRAM2 */ - FSMC_Bank1->BTCR[2] = 0x00001011; - FSMC_Bank1->BTCR[3] = 0x00000201; - FSMC_Bank1E->BWTR[2] = 0x0fffffff; -/* - Bank1_SRAM2 is configured as follow: - - p.FSMC_AddressSetupTime = 1; - p.FSMC_AddressHoldTime = 0; - p.FSMC_DataSetupTime = 2; - p.FSMC_BusTurnAroundDuration = 0; - p.FSMC_CLKDivision = 0; - p.FSMC_DataLatency = 0; - p.FSMC_AccessMode = FSMC_AccessMode_A; - - FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; - FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; - FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; - FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; - FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; - FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; - FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; -*/ -} -#endif /* DATA_IN_ExtSRAM */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4XX/system_stm32f4xx.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,105 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f4xx.h - * @author MCD Application Team - * @version V1.1.0 - * @date 11-January-2013 - * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f4xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32F4XX_H -#define __SYSTEM_STM32F4XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32F4xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32F4xx_System_Exported_types - * @{ - */ - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32F4XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/device.h Wed Apr 27 19:30:12 2016 +0100 +++ b/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/device.h Fri Apr 29 01:15:11 2016 +0100 @@ -24,45 +24,50 @@ #endif /* <-Take measures about optimization problems of web compiler */ -#define DEVICE_PORTIN 1 -#define DEVICE_PORTOUT 1 -#define DEVICE_PORTINOUT 1 +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 -#define DEVICE_INTERRUPTIN 1 - -#define DEVICE_ANALOGIN 1 -#define DEVICE_ANALOGOUT 0 +#define DEVICE_INTERRUPTIN 1 -#define DEVICE_SERIAL 1 -#define DEVICE_SERIAL_FC 1 +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 -#define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 1 +#define DEVICE_SERIAL 1 +#define DEVICE_SERIAL_FC 1 +#define DEVICE_SERIAL_ASYNCH 1 -#define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 1 +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 +#define DEVICE_I2C_ASYNCH 1 -#define DEVICE_CAN 1 - -#define DEVICE_RTC 1 +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 +#define DEVICE_SPI_ASYNCH 1 +#define TRANSACTION_QUEUE_SIZE_SPI 16 -#define DEVICE_ETHERNET 1 +#define DEVICE_CAN 1 + +#define DEVICE_RTC 1 -#define DEVICE_PWMOUT 1 +#define DEVICE_ETHERNET 1 + +#define DEVICE_PWMOUT 1 -#define DEVICE_SEMIHOST 0 -#define DEVICE_LOCALFILESYSTEM 0 -#define DEVICE_ID_LENGTH 32 -#define DEVICE_MAC_OFFSET 20 +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 32 +#define DEVICE_MAC_OFFSET 20 -#define DEVICE_SLEEP 0 +#define DEVICE_SLEEP 0 -#define DEVICE_DEBUG_AWARENESS 0 +#define DEVICE_DEBUG_AWARENESS 0 -#define DEVICE_STDIO_MESSAGES 1 +#define DEVICE_STDIO_MESSAGES 1 -#define DEVICE_ERROR_PATTERN 1 +#define DEVICE_ERROR_PATTERN 1 #include "objects.h" +#include "dma_api.h" #endif
--- a/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c Wed Apr 27 19:30:12 2016 +0100 +++ b/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c Fri Apr 29 01:15:11 2016 +0100 @@ -14,6 +14,7 @@ * limitations under the License. */ #include "mbed_assert.h" +#include "dma_api.h" #include "i2c_api.h" #include "cmsis.h" #include "pinmap.h" @@ -26,7 +27,7 @@ volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST; #define REG(N) \ - RIIC[obj->i2c]->RIICn##N + RIIC[obj->i2c.i2c]->RIICn##N /* RIICnCR1 */ #define CR1_RST (1 << 6) @@ -74,7 +75,6 @@ {NC , NC, 0} }; - static inline int i2c_status(i2c_t *obj) { return REG(SR2.UINT8[0]); } @@ -89,9 +89,9 @@ REG(SER.UINT8[0]) = 0x00; // no slave addr enabled /* set frequency */ - REG(MR1.UINT8[0]) |= obj->pclk_bit; - REG(BRL.UINT8[0]) = obj->width_low; - REG(BRH.UINT8[0]) = obj->width_hi; + REG(MR1.UINT8[0]) |= obj->i2c.pclk_bit; + REG(BRL.UINT8[0]) = obj->i2c.width_low; + REG(BRH.UINT8[0]) = obj->i2c.width_hi; REG(MR2.UINT8[0]) = 0x07; REG(MR3.UINT8[0]) = 0x00; @@ -205,7 +205,7 @@ static inline void i2c_power_enable(i2c_t *obj) { volatile uint8_t dummy; - switch ((int)obj->i2c) { + switch ((int)obj->i2c.i2c) { case I2C_0: CPGSTBCR9 &= ~(0x80); break; @@ -226,8 +226,8 @@ /* determine the I2C to use */ I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - obj->i2c = pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT((int)obj->i2c != NC); + obj->i2c.i2c = pinmap_merge(i2c_sda, i2c_scl); + MBED_ASSERT((int)obj->i2c.i2c != NC); /* enable power */ i2c_power_enable(obj); @@ -238,7 +238,7 @@ pinmap_pinout(sda, PinMap_I2C_SDA); pinmap_pinout(scl, PinMap_I2C_SCL); - obj->last_stop_flag = 1; + obj->i2c.last_stop_flag = 1; } inline int i2c_start(i2c_t *obj) { @@ -246,7 +246,7 @@ while ((REG(CR2.UINT32) & CR2_BBSY) != 0) { timeout ++; - if (timeout >= obj->bbsy_wait_cnt) { + if (timeout >= obj->i2c.bbsy_wait_cnt) { break; } } @@ -277,7 +277,7 @@ (void)i2c_set_STOP(obj); (void)i2c_wait_STOP(obj); i2c_set_SR2_NACKF_STOP(obj); - obj->last_stop_flag = 1; + obj->i2c.last_stop_flag = 1; } static inline int i2c_do_write(i2c_t *obj, int value) { @@ -395,16 +395,16 @@ wait_utime = (L_time * 2) * 1000000; /* 1 wait of BBSY bit is about 0.3us. if it's below 0.3us, wait count is set as 1. */ if (wait_utime <= 0.3) { - obj->bbsy_wait_cnt = 1; + obj->i2c.bbsy_wait_cnt = 1; } else { - obj->bbsy_wait_cnt = (int)(wait_utime / 0.3); + obj->i2c.bbsy_wait_cnt = (int)(wait_utime / 0.3); } /* I2C Rate */ - obj->pclk_bit = (uint8_t)(0x10 * wk_cks); /* P_phi / xx */ - obj->width_low = (uint8_t)(tmp_L_width | 0x000000E0); - obj->width_hi = (uint8_t)(tmp_H_width | 0x000000E0); + obj->i2c.pclk_bit = (uint8_t)(0x10 * wk_cks); /* P_phi / xx */ + obj->i2c.width_low = (uint8_t)(tmp_L_width | 0x000000E0); + obj->i2c.width_hi = (uint8_t)(tmp_H_width | 0x000000E0); /* full reset */ i2c_reg_reset(obj); @@ -421,14 +421,14 @@ } i2c_set_MR3_ACK(obj); /* There is a STOP condition for last processing */ - if (obj->last_stop_flag != 0) { + if (obj->i2c.last_stop_flag != 0) { status = i2c_start(obj); if (status != 0) { i2c_set_err_noslave(obj); return I2C_ERROR_BUS_BUSY; } } - obj->last_stop_flag = stop; + obj->i2c.last_stop_flag = stop; /* Send Slave address */ status = i2c_read_address_write(obj, (address | 0x01)); if (status != 0) { @@ -445,7 +445,7 @@ value = REG(DRR.UINT32); (void)i2c_wait_STOP(obj); i2c_set_SR2_NACKF_STOP(obj); - obj->last_stop_flag = 1; + obj->i2c.last_stop_flag = 1; return I2C_ERROR_NO_SLAVE; } /* Read in all except last byte */ @@ -470,7 +470,7 @@ data[count] = (char)value; } } else if (length == 2) { - /* Set MR3 WATI bit is 1 */ + /* Set MR3 WAIT bit is 1 */ REG(MR3.UINT32) |= MR3_WAIT; /* dummy read */ value = REG(DRR.UINT32); @@ -485,7 +485,7 @@ count++; } else { /* length == 1 */ - /* Set MR3 WATI bit is 1 */; + /* Set MR3 WAIT bit is 1 */; REG(MR3.UINT32) |= MR3_WAIT; i2c_set_MR3_NACK(obj); /* dummy read */ @@ -532,14 +532,14 @@ } /* There is a STOP condition for last processing */ - if (obj->last_stop_flag != 0) { + if (obj->i2c.last_stop_flag != 0) { status = i2c_start(obj); if (status != 0) { i2c_set_err_noslave(obj); return I2C_ERROR_BUS_BUSY; } } - obj->last_stop_flag = stop; + obj->i2c.last_stop_flag = stop; /* Send Slave address */ status = i2c_do_write(obj, address); if (status != 0) { @@ -749,3 +749,392 @@ void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { REG(SAR0.UINT32) = (address & 0xfffffffe); } + +#if DEVICE_I2C_ASYNCH + +#define IRQ_NUM 4 +#define IRQ_TX 0 +#define IRQ_RX 1 +#define IRQ_ERR1 2 +#define IRQ_ERR2 3 + +static void i2c_irqs_set(i2c_t *obj, uint32_t enable); + +static void i2c0_tx_irq(void); +static void i2c1_tx_irq(void); +static void i2c2_tx_irq(void); +static void i2c3_tx_irq(void); +static void i2c0_rx_irq(void); +static void i2c1_rx_irq(void); +static void i2c2_rx_irq(void); +static void i2c3_rx_irq(void); +static void i2c0_al_irq(void); +static void i2c1_al_irq(void); +static void i2c2_al_irq(void); +static void i2c3_al_irq(void); +static void i2c0_to_irq(void); +static void i2c1_to_irq(void); +static void i2c2_to_irq(void); +static void i2c3_to_irq(void); + +static const IRQn_Type irq_set_tbl[RIIC_COUNT][IRQ_NUM] = { + {INTIICTEI0_IRQn, INTIICRI0_IRQn, INTIICALI0_IRQn, INTIICTMOI0_IRQn}, + {INTIICTEI1_IRQn, INTIICRI1_IRQn, INTIICALI1_IRQn, INTIICTMOI1_IRQn}, + {INTIICTEI2_IRQn, INTIICRI2_IRQn, INTIICALI2_IRQn, INTIICTMOI2_IRQn}, + {INTIICTEI3_IRQn, INTIICRI3_IRQn, INTIICALI3_IRQn, INTIICTMOI3_IRQn}, +}; + +static const IRQHandler hander_set_tbl[RIIC_COUNT][IRQ_NUM] = { + {i2c0_tx_irq, i2c0_rx_irq, i2c0_al_irq, i2c0_to_irq}, + {i2c1_tx_irq, i2c1_rx_irq, i2c1_al_irq, i2c1_to_irq}, + {i2c2_tx_irq, i2c2_rx_irq, i2c2_al_irq, i2c2_to_irq}, + {i2c3_tx_irq, i2c3_rx_irq, i2c3_al_irq, i2c3_to_irq}, +}; + +struct i2c_global_data_s { + i2c_t *async_obj; + uint32_t async_callback, event, shouldStop, address; +}; + +static struct i2c_global_data_s i2c_data[RIIC_COUNT]; + +static void i2c_transfer_finished(i2c_t *obj) +{ + i2c_irqs_set(obj, 0); + uint32_t index = obj->i2c.i2c; + i2c_data[index].event = I2C_EVENT_TRANSFER_COMPLETE; + i2c_data[index].async_obj = NULL; + ((void (*)())i2c_data[index].async_callback)(); +} + +static void i2c_tx_irq(IRQn_Type irq_num, uint32_t index) +{ + i2c_t *obj = i2c_data[index].async_obj; + if ((REG(SR2.UINT32) & SR2_NACKF)) { + /* Slave sends NACK */ + i2c_set_err_noslave(obj); + i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK; + i2c_abort_asynch(obj); + ((void (*)())i2c_data[index].async_callback)(); + return; + } + if (obj->tx_buff.pos == obj->tx_buff.length) { + /* All datas have tranferred */ + + /* Clear TEND */ + REG(SR2.UINT32) &= ~(SR2_TEND); + + /* If not repeated start, send stop. */ + if (i2c_data[index].shouldStop && obj->rx_buff.length == 0) { + (void)i2c_set_STOP(obj); + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + i2c_transfer_finished(obj); + } else { + (void)i2c_restart(obj); + (void)i2c_wait_START(obj); + /* SR2.START = 0 */ + REG(SR2.UINT32) &= ~SR2_START; + if (obj->rx_buff.length) { + /* Ready to read */ + i2c_set_MR3_ACK(obj); + + /* Disable INTRIICTEI */ + REG(IER.UINT8[0]) &= ~(1 << 6); + + /* Send Slave address */ + if (i2c_read_address_write(obj, (i2c_data[index].address | 0x01)) != 0) { + i2c_set_err_noslave(obj); + i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE; + i2c_abort_asynch(obj); + ((void (*)())i2c_data[index].async_callback)(); + return; + } + } else { + i2c_transfer_finished(obj); + } + } + } else { + /* Send next 1 byte */ + if (i2c_do_write(obj, *(uint8_t *)obj->tx_buff.buffer) != 0) { + i2c_set_err_noslave(obj); + i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE; + i2c_abort_asynch(obj); + ((void (*)())i2c_data[index].async_callback)(); + return; + } + obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + 1; + ++obj->tx_buff.pos; + } +} + +static void i2c_rx_irq(IRQn_Type irq_num, uint32_t index) +{ + i2c_t *obj = i2c_data[index].async_obj; + if (obj->rx_buff.pos == SIZE_MAX) { + if ((REG(SR2.UINT32) & SR2_NACKF) != 0) { + /* Slave sends NACK */ + (void)i2c_set_STOP(obj); + /* dummy read */ + if (REG(DRR.UINT32)) {} + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + obj->i2c.last_stop_flag = 1; + + i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK; + i2c_abort_asynch(obj); + ((void (*)())i2c_data[index].async_callback)(); + return; + } + if (obj->rx_buff.length == 1) { + /* length == 1 */ + /* Set MR3 WAIT bit is 1 */; + REG(MR3.UINT32) |= MR3_WAIT; + i2c_set_MR3_NACK(obj); + } else if (obj->rx_buff.length == 2) { + /* Set MR3 WAIT bit is 1 */ + REG(MR3.UINT32) |= MR3_WAIT; + } + /* dummy read */ + if (REG(DRR.UINT32)) {} + obj->rx_buff.pos = 0; + return; + } + if ((REG(SR2.UINT32) & SR2_NACKF) != 0) { + /* Slave sends NACK */ + i2c_set_err_noslave(obj); + i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK; + i2c_abort_asynch(obj); + ((void (*)())i2c_data[index].async_callback)(); + return; + } else { + switch (obj->rx_buff.length - obj->rx_buff.pos) { + case 1: + /* Finished */ + /* If not repeated start, send stop. */ + if (i2c_data[index].shouldStop) { + (void)i2c_set_STOP(obj); + /* RIICnDRR read */ + *(uint8_t *)obj->rx_buff.buffer = REG(DRR.UINT32) & 0xFF; + /* RIICnMR3.WAIT = 0 */ + REG(MR3.UINT32) &= ~MR3_WAIT; + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + } else { + (void)i2c_restart(obj); + /* RIICnDRR read */ + *(uint8_t *)obj->rx_buff.buffer = REG(DRR.UINT32) & 0xFF; + /* RIICnMR3.WAIT = 0 */ + REG(MR3.UINT32) &= ~MR3_WAIT; + (void)i2c_wait_START(obj); + /* SR2.START = 0 */ + REG(SR2.UINT32) &= ~SR2_START; + } + + i2c_transfer_finished(obj); + return; + + case 2: + i2c_set_MR3_NACK(obj); + break; + + case 3: + /* this time is befor last byte read */ + /* Set MR3 WAIT bit is 1 */ + REG(MR3.UINT32) |= MR3_WAIT; + break; + + default: + i2c_set_MR3_ACK(obj); + break; + } + *(uint8_t *)obj->rx_buff.buffer = REG(DRR.UINT32) & 0xFF; + obj->rx_buff.buffer = (uint8_t *)obj->rx_buff.buffer + 1; + ++obj->rx_buff.pos; + } +} + +static void i2c_err_irq(IRQn_Type irq_num, uint32_t index) +{ + i2c_t *obj = i2c_data[index].async_obj; + i2c_abort_asynch(obj); + i2c_data[index].event = I2C_EVENT_ERROR; + ((void (*)())i2c_data[index].async_callback)(); +} + +/* TX handler */ +static void i2c0_tx_irq(void) +{ + i2c_tx_irq(INTIICTEI0_IRQn, 0); +} + +static void i2c1_tx_irq(void) +{ + i2c_tx_irq(INTIICTEI1_IRQn, 1); +} + +static void i2c2_tx_irq(void) +{ + i2c_tx_irq(INTIICTEI2_IRQn, 2); +} + +static void i2c3_tx_irq(void) +{ + i2c_tx_irq(INTIICTEI3_IRQn, 3); +} + +/* RX handler */ +static void i2c0_rx_irq(void) +{ + i2c_rx_irq(INTIICRI0_IRQn, 0); +} + +static void i2c1_rx_irq(void) +{ + i2c_rx_irq(INTIICRI1_IRQn, 1); +} + +static void i2c2_rx_irq(void) +{ + i2c_rx_irq(INTIICRI2_IRQn, 2); +} + +static void i2c3_rx_irq(void) +{ + i2c_rx_irq(INTIICRI3_IRQn, 3); +} + +/* Arbitration Lost handler */ +static void i2c0_al_irq(void) +{ + i2c_err_irq(INTIICALI0_IRQn, 0); +} + +static void i2c1_al_irq(void) +{ + i2c_err_irq(INTIICALI1_IRQn, 1); +} + +static void i2c2_al_irq(void) +{ + i2c_err_irq(INTIICALI2_IRQn, 2); +} + +static void i2c3_al_irq(void) +{ + i2c_err_irq(INTIICALI3_IRQn, 3); +} + +/* Timeout handler */ +static void i2c0_to_irq(void) +{ + i2c_err_irq(INTIICTMOI0_IRQn, 0); +} + +static void i2c1_to_irq(void) +{ + i2c_err_irq(INTIICTMOI1_IRQn, 1); +} + +static void i2c2_to_irq(void) +{ + i2c_err_irq(INTIICTMOI2_IRQn, 2); +} + +static void i2c3_to_irq(void) +{ + i2c_err_irq(INTIICTMOI3_IRQn, 3); +} + +static void i2c_irqs_set(i2c_t *obj, uint32_t enable) +{ + int i; + const IRQn_Type *irqTable = irq_set_tbl[obj->i2c.i2c]; + const IRQHandler *handlerTable = hander_set_tbl[obj->i2c.i2c]; + for (i = 0; i < IRQ_NUM; ++i) { + if (enable) { + InterruptHandlerRegister(irqTable[i], handlerTable[i]); + GIC_SetPriority(irqTable[i], 5); + GIC_EnableIRQ(irqTable[i]); + } else { + GIC_DisableIRQ(irqTable[i]); + } + } + REG(IER.UINT8[0]) = enable ? 0x63 : 0x00; +} + +/****************************************************************************** + * ASYNCHRONOUS HAL + ******************************************************************************/ + +void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint) +{ + MBED_ASSERT(obj); + MBED_ASSERT(tx ? tx_length : 1); + MBED_ASSERT(rx ? rx_length : 1); + MBED_ASSERT((REG(SER.UINT32) & SER_SAR0E) == 0); /* Slave mode */ + + obj->tx_buff.buffer = (void *)tx; + obj->tx_buff.length = tx_length; + obj->tx_buff.pos = 0; + obj->tx_buff.width = 8; + obj->rx_buff.buffer = rx; + obj->rx_buff.length = rx_length; + obj->rx_buff.pos = SIZE_MAX; + obj->rx_buff.width = 8; + i2c_data[obj->i2c.i2c].async_obj = obj; + i2c_data[obj->i2c.i2c].async_callback = handler; + i2c_data[obj->i2c.i2c].event = 0; + i2c_data[obj->i2c.i2c].shouldStop = stop; + i2c_data[obj->i2c.i2c].address = address; + i2c_irqs_set(obj, 1); + + /* There is a STOP condition for last processing */ + if (obj->i2c.last_stop_flag != 0) { + if (i2c_start(obj) != 0) { + i2c_set_err_noslave(obj); + i2c_data[obj->i2c.i2c].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE; + i2c_abort_asynch(obj); + ((void (*)())handler)(); + return; + } + } + obj->i2c.last_stop_flag = stop; + + if (rx_length && tx_length == 0) { + /* Ready to read */ + i2c_set_MR3_ACK(obj); + + /* Disable INTRIICTEI */ + REG(IER.UINT8[0]) &= ~(1 << 6); + + address |= 0x01; + } + /* Send Slave address */ + if (i2c_do_write(obj, address) != 0) { + i2c_set_err_noslave(obj); + i2c_data[obj->i2c.i2c].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE; + i2c_abort_asynch(obj); + ((void (*)())handler)(); + return; + } +} + +uint32_t i2c_irq_handler_asynch(i2c_t *obj) +{ + return i2c_data[obj->i2c.i2c].event; +} + +uint8_t i2c_active(i2c_t *obj) +{ + return i2c_data[obj->i2c.i2c].async_obj != NULL; +} + +void i2c_abort_asynch(i2c_t *obj) +{ + i2c_data[obj->i2c.i2c].async_obj = NULL; + i2c_irqs_set(obj, 0); + i2c_reg_reset(obj); +} + +#endif
--- a/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/objects.h Wed Apr 27 19:30:12 2016 +0100 +++ b/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/objects.h Fri Apr 29 01:15:11 2016 +0100 @@ -41,6 +41,7 @@ struct spi_s { struct st_rspi *spi; uint32_t bits; + int index; }; struct gpio_irq_s {
--- a/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c Wed Apr 27 19:30:12 2016 +0100 +++ b/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c Fri Apr 29 01:15:11 2016 +0100 @@ -33,7 +33,7 @@ #define PCLK (66666666) // Define the peripheral clock P1 frequency. #define UART_NUM 8 -#define IRQ_NUM 2 +#define IRQ_NUM 4 static void uart0_tx_irq(void); static void uart1_tx_irq(void); @@ -51,7 +51,18 @@ static void uart5_rx_irq(void); static void uart6_rx_irq(void); static void uart7_rx_irq(void); +static void uart0_er_irq(void); +static void uart1_er_irq(void); +static void uart2_er_irq(void); +static void uart3_er_irq(void); +static void uart4_er_irq(void); +static void uart5_er_irq(void); +static void uart6_er_irq(void); +static void uart7_er_irq(void); +static void serial_put_done(serial_t *obj); +static uint8_t serial_available_buffer(serial_t *obj); +static void serial_irq_err_set(serial_t *obj, uint32_t enable); static const PinMap PinMap_UART_TX[] = { {P2_14 , UART0, 6}, @@ -115,31 +126,34 @@ struct serial_global_data_s { uint32_t serial_irq_id; gpio_t sw_rts, sw_cts; - uint8_t count, rx_irq_set_flow, rx_irq_set_api; + uint8_t rx_irq_set_flow, rx_irq_set_api; + serial_t *tranferring_obj, *receiving_obj; + uint32_t async_tx_callback, async_rx_callback; + int event, wanted_rx_events; }; static struct serial_global_data_s uart_data[UART_NUM]; static const IRQn_Type irq_set_tbl[UART_NUM][IRQ_NUM] = { - {SCIFRXI0_IRQn, SCIFTXI0_IRQn}, - {SCIFRXI1_IRQn, SCIFTXI1_IRQn}, - {SCIFRXI2_IRQn, SCIFTXI2_IRQn}, - {SCIFRXI3_IRQn, SCIFTXI3_IRQn}, - {SCIFRXI4_IRQn, SCIFTXI4_IRQn}, - {SCIFRXI5_IRQn, SCIFTXI5_IRQn}, - {SCIFRXI6_IRQn, SCIFTXI6_IRQn}, - {SCIFRXI7_IRQn, SCIFTXI7_IRQn} + {SCIFRXI0_IRQn, SCIFTXI0_IRQn, SCIFBRI0_IRQn, SCIFERI0_IRQn}, + {SCIFRXI1_IRQn, SCIFTXI1_IRQn, SCIFBRI1_IRQn, SCIFERI1_IRQn}, + {SCIFRXI2_IRQn, SCIFTXI2_IRQn, SCIFBRI2_IRQn, SCIFERI2_IRQn}, + {SCIFRXI3_IRQn, SCIFTXI3_IRQn, SCIFBRI3_IRQn, SCIFERI3_IRQn}, + {SCIFRXI4_IRQn, SCIFTXI4_IRQn, SCIFBRI4_IRQn, SCIFERI4_IRQn}, + {SCIFRXI5_IRQn, SCIFTXI5_IRQn, SCIFBRI5_IRQn, SCIFERI5_IRQn}, + {SCIFRXI6_IRQn, SCIFTXI6_IRQn, SCIFBRI6_IRQn, SCIFERI6_IRQn}, + {SCIFRXI7_IRQn, SCIFTXI7_IRQn, SCIFBRI7_IRQn, SCIFERI7_IRQn} }; static const IRQHandler hander_set_tbl[UART_NUM][IRQ_NUM] = { - {uart0_rx_irq, uart0_tx_irq}, - {uart1_rx_irq, uart1_tx_irq}, - {uart2_rx_irq, uart2_tx_irq}, - {uart3_rx_irq, uart3_tx_irq}, - {uart4_rx_irq, uart4_tx_irq}, - {uart5_rx_irq, uart5_tx_irq}, - {uart6_rx_irq, uart6_tx_irq}, - {uart7_rx_irq, uart7_tx_irq} + {uart0_rx_irq, uart0_tx_irq, uart0_er_irq, uart0_er_irq}, + {uart1_rx_irq, uart1_tx_irq, uart1_er_irq, uart1_er_irq}, + {uart2_rx_irq, uart2_tx_irq, uart2_er_irq, uart2_er_irq}, + {uart3_rx_irq, uart3_tx_irq, uart3_er_irq, uart3_er_irq}, + {uart4_rx_irq, uart4_tx_irq, uart4_er_irq, uart4_er_irq}, + {uart5_rx_irq, uart5_tx_irq, uart5_er_irq, uart5_er_irq}, + {uart6_rx_irq, uart6_tx_irq, uart6_er_irq, uart6_er_irq}, + {uart7_rx_irq, uart7_tx_irq, uart7_er_irq, uart7_er_irq} }; static __IO uint16_t *SCSCR_MATCH[] = { @@ -175,7 +189,7 @@ MBED_ASSERT((int)uart != NC); - obj->uart = (struct st_scif *)SCIF[uart]; + obj->serial.uart = (struct st_scif *)SCIF[uart]; // enable power switch (uart) { case UART0: @@ -208,42 +222,42 @@ /* ==== SCIF initial setting ==== */ /* ---- Serial control register (SCSCR) setting ---- */ /* B'00 : Internal CLK */ - obj->uart->SCSCR = 0x0000u; /* SCIF transmitting and receiving operations stop */ + obj->serial.uart->SCSCR = 0x0000u; /* SCIF transmitting and receiving operations stop */ /* ---- FIFO control register (SCFCR) setting ---- */ /* Transmit FIFO reset & Receive FIFO data register reset */ - obj->uart->SCFCR = 0x0006; + obj->serial.uart->SCFCR = 0x0006; /* ---- Serial status register (SCFSR) setting ---- */ - dummy = obj->uart->SCFSR; - obj->uart->SCFSR = (dummy & 0xFF6Cu); /* ER,BRK,DR bit clear */ + dummy = obj->serial.uart->SCFSR; + obj->serial.uart->SCFSR = (dummy & 0xFF6Cu); /* ER,BRK,DR bit clear */ /* ---- Line status register (SCLSR) setting ---- */ /* ORER bit clear */ - obj->uart->SCLSR = 0; + obj->serial.uart->SCLSR = 0; /* ---- Serial extension mode register (SCEMR) setting ---- b7 BGDM - Baud rate generator double-speed mode : Normal mode b0 ABCS - Base clock select in asynchronous mode : Base clock is 16 times the bit rate */ - obj->uart->SCEMR = 0x0000u; + obj->serial.uart->SCEMR = 0x0000u; /* ---- Bit rate register (SCBRR) setting ---- */ serial_baud (obj, 9600); serial_format(obj, 8, ParityNone, 1); /* ---- FIFO control register (SCFCR) setting ---- */ - obj->uart->SCFCR = 0x0030u; + obj->serial.uart->SCFCR = 0x0030u; /* ---- Serial port register (SCSPTR) setting ---- b1 SPB2IO - Serial port break output : disabled b0 SPB2DT - Serial port break data : High-level */ - obj->uart->SCSPTR = 0x0003u; // SPB2IO = 1, SPB2DT = 1 + obj->serial.uart->SCSPTR = 0x0003u; // SPB2IO = 1, SPB2DT = 1 /* ---- Line status register (SCLSR) setting ---- b0 ORER - Overrun error detect : clear */ - if (obj->uart->SCLSR & 0x0001) { - obj->uart->SCLSR = 0u; // ORER clear + if (obj->serial.uart->SCLSR & 0x0001) { + obj->serial.uart->SCLSR = 0u; // ORER clear } // pinout the chosen uart @@ -252,36 +266,36 @@ switch (uart) { case UART0: - obj->index = 0; + obj->serial.index = 0; break; case UART1: - obj->index = 1; + obj->serial.index = 1; break; case UART2: - obj->index = 2; + obj->serial.index = 2; break; case UART3: - obj->index = 3; + obj->serial.index = 3; break; case UART4: - obj->index = 4; + obj->serial.index = 4; break; case UART5: - obj->index = 5; + obj->serial.index = 5; break; case UART6: - obj->index = 6; + obj->serial.index = 6; break; case UART7: - obj->index = 7; + obj->serial.index = 7; break; } - uart_data[obj->index].sw_rts.pin = NC; - uart_data[obj->index].sw_cts.pin = NC; + uart_data[obj->serial.index].sw_rts.pin = NC; + uart_data[obj->serial.index].sw_cts.pin = NC; /* ---- Serial control register (SCSCR) setting ---- */ /* Setting the TE and RE bits enables the TxD and RxD pins to be used. */ - obj->uart->SCSCR = 0x00F0; + obj->serial.uart->SCSCR = 0x0070; is_stdio_uart = (uart == STDIO_UART) ? (1) : (0); @@ -292,7 +306,7 @@ } void serial_free(serial_t *obj) { - uart_data[obj->index].serial_irq_id = 0; + uart_data[obj->serial.index].serial_irq_id = 0; } // serial_baud @@ -300,49 +314,49 @@ void serial_baud(serial_t *obj, int baudrate) { uint16_t DL; - obj->uart->SCSMR &= ~0x0003; + obj->serial.uart->SCSMR &= ~0x0003; if (baudrate > 32552) { - obj->uart->SCEMR = 0x0081; // BGDM = 1, ABCS = 1 + obj->serial.uart->SCEMR = 0x0081; // BGDM = 1, ABCS = 1 DL = PCLK / (8 * baudrate); if (DL > 0) { DL--; } - obj->uart->SCBRR = (uint8_t)DL; + obj->serial.uart->SCBRR = (uint8_t)DL; } else if (baudrate > 16276) { - obj->uart->SCEMR = 0x0080; // BGDM = 1 - obj->uart->SCBRR = PCLK / (16 * baudrate) - 1; + obj->serial.uart->SCEMR = 0x0080; // BGDM = 1 + obj->serial.uart->SCBRR = PCLK / (16 * baudrate) - 1; } else if (baudrate > 8138) { - obj->uart->SCEMR = 0x0000; - obj->uart->SCBRR = PCLK / (32 * baudrate) - 1; + obj->serial.uart->SCEMR = 0x0000; + obj->serial.uart->SCBRR = PCLK / (32 * baudrate) - 1; } else if (baudrate > 4169) { - obj->uart->SCSMR |= 0x0001; - obj->uart->SCEMR = 0x0080; // BGDM = 1 - obj->uart->SCBRR = PCLK / (64 * baudrate) - 1; + obj->serial.uart->SCSMR |= 0x0001; + obj->serial.uart->SCEMR = 0x0080; // BGDM = 1 + obj->serial.uart->SCBRR = PCLK / (64 * baudrate) - 1; } else if (baudrate > 2034) { - obj->uart->SCSMR |= 0x0001; - obj->uart->SCEMR = 0x0000; - obj->uart->SCBRR = PCLK / (128 * baudrate) - 1; + obj->serial.uart->SCSMR |= 0x0001; + obj->serial.uart->SCEMR = 0x0000; + obj->serial.uart->SCBRR = PCLK / (128 * baudrate) - 1; } else if (baudrate > 1017) { - obj->uart->SCSMR |= 0x0002; - obj->uart->SCEMR = 0x0080; // BGDM = 1 - obj->uart->SCBRR = PCLK / (256 * baudrate) - 1; + obj->serial.uart->SCSMR |= 0x0002; + obj->serial.uart->SCEMR = 0x0080; // BGDM = 1 + obj->serial.uart->SCBRR = PCLK / (256 * baudrate) - 1; } else if (baudrate > 508) { - obj->uart->SCSMR |= 0x0002; - obj->uart->SCEMR = 0x0000; - obj->uart->SCBRR = PCLK / (512 * baudrate) - 1; + obj->serial.uart->SCSMR |= 0x0002; + obj->serial.uart->SCEMR = 0x0000; + obj->serial.uart->SCBRR = PCLK / (512 * baudrate) - 1; } else if (baudrate > 254) { - obj->uart->SCSMR |= 0x0003; - obj->uart->SCEMR = 0x0080; // BGDM = 1 - obj->uart->SCBRR = PCLK / (1024 * baudrate) - 1; + obj->serial.uart->SCSMR |= 0x0003; + obj->serial.uart->SCEMR = 0x0080; // BGDM = 1 + obj->serial.uart->SCBRR = PCLK / (1024 * baudrate) - 1; } else if (baudrate > 127) { - obj->uart->SCSMR |= 0x0003; - obj->uart->SCEMR = 0x0000; - obj->uart->SCBRR = PCLK / (2048 * baudrate) - 1; + obj->serial.uart->SCSMR |= 0x0003; + obj->serial.uart->SCEMR = 0x0000; + obj->serial.uart->SCBRR = PCLK / (2048 * baudrate) - 1; } else { - obj->uart->SCSMR |= 0x0003; - obj->uart->SCEMR = 0x0000; - obj->uart->SCBRR = 0xFFu; + obj->serial.uart->SCSMR |= 0x0003; + obj->serial.uart->SCEMR = 0x0000; + obj->serial.uart->SCBRR = 0xFFu; } } @@ -384,7 +398,7 @@ break; } - obj->uart->SCSMR = data_bits << 6 + obj->serial.uart->SCSMR = data_bits << 6 | parity_enable << 5 | parity_select << 4 | stop_bits << 3; @@ -397,25 +411,131 @@ static void uart_tx_irq(IRQn_Type irq_num, uint32_t index) { __IO uint16_t *dmy_rd_scscr; __IO uint16_t *dmy_rd_scfsr; - + serial_t *obj; + int i; + dmy_rd_scscr = SCSCR_MATCH[index]; *dmy_rd_scscr &= 0x007B; // Clear TIE and Write to bit15~8,2 is always 0 dmy_rd_scfsr = SCFSR_MATCH[index]; - *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0020); // Clear TDFE - + *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0020); // Set TEND + + obj = uart_data[index].tranferring_obj; + if (obj) { + i = obj->tx_buff.length - obj->tx_buff.pos; + if (0 < i) { + if (serial_available_buffer(obj) < i) { + i = serial_available_buffer(obj); + } + do { + uint8_t c = *(uint8_t *)obj->tx_buff.buffer; + obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + 1; + ++obj->tx_buff.pos; + obj->serial.uart->SCFTDR = c; + } while (--i); + serial_put_done(obj); + } else { + uart_data[index].tranferring_obj = NULL; + uart_data[index].event = SERIAL_EVENT_TX_COMPLETE; + ((void (*)())uart_data[index].async_tx_callback)(); + } + } + irq_handler(uart_data[index].serial_irq_id, TxIrq); } static void uart_rx_irq(IRQn_Type irq_num, uint32_t index) { __IO uint16_t *dmy_rd_scscr; __IO uint16_t *dmy_rd_scfsr; - + serial_t *obj; + int c; + dmy_rd_scscr = SCSCR_MATCH[index]; *dmy_rd_scscr &= 0x00B3; // Clear RIE,REIE and Write to bit15~8,2 is always 0 dmy_rd_scfsr = SCFSR_MATCH[index]; *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0003); // Clear RDF,DR + + obj = uart_data[index].receiving_obj; + if (obj) { + if (obj->serial.uart->SCLSR & 1) { + if (uart_data[index].wanted_rx_events & SERIAL_EVENT_RX_OVERRUN_ERROR) { + serial_rx_abort_asynch(obj); + uart_data[index].event = SERIAL_EVENT_RX_OVERRUN_ERROR; + ((void (*)())uart_data[index].async_rx_callback)(); + } + return; + } + c = serial_getc(obj); + if (c != -1) { + ((uint8_t *)obj->rx_buff.buffer)[obj->rx_buff.pos] = c; + ++obj->rx_buff.pos; + if (c == obj->char_match && ! obj->char_found) { + obj->char_found = 1; + if (obj->rx_buff.pos == obj->rx_buff.length) { + if (uart_data[index].wanted_rx_events & SERIAL_EVENT_RX_COMPLETE) { + uart_data[index].event = SERIAL_EVENT_RX_COMPLETE; + } + } + if (uart_data[index].wanted_rx_events & SERIAL_EVENT_RX_CHARACTER_MATCH) { + uart_data[index].event |= SERIAL_EVENT_RX_CHARACTER_MATCH; + } + if (uart_data[index].event) { + uart_data[index].receiving_obj = NULL; + ((void (*)())uart_data[index].async_rx_callback)(); + } + } else if (obj->rx_buff.pos == obj->rx_buff.length) { + uart_data[index].receiving_obj = NULL; + if (uart_data[index].wanted_rx_events & SERIAL_EVENT_RX_COMPLETE) { + uart_data[index].event = SERIAL_EVENT_RX_COMPLETE; + ((void (*)())uart_data[index].async_rx_callback)(); + } + } + } else { + serial_rx_abort_asynch(obj); + if (uart_data[index].wanted_rx_events & (SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR)) { + uart_data[index].event = SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR; + if (obj->serial.uart->SCFSR & 1 << 2) { + uart_data[index].event = SERIAL_EVENT_RX_PARITY_ERROR; + } else if (obj->serial.uart->SCFSR & 1 << 3) { + uart_data[index].event = SERIAL_EVENT_RX_FRAMING_ERROR; + } + ((void (*)())uart_data[index].async_rx_callback)(); + } + return; + } + } + + irq_handler(uart_data[index].serial_irq_id, RxIrq); +} - irq_handler(uart_data[index].serial_irq_id, RxIrq); +static void uart_err_irq(IRQn_Type irq_num, uint32_t index) { + serial_t *obj = uart_data[index].receiving_obj; + int was_masked, err_read; + + if (obj) { + serial_irq_err_set(obj, 0); + if (uart_data[index].wanted_rx_events & (SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR)) { + uart_data[index].event = SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR; + if (obj->serial.uart->SCFSR & 1 << 2) { + uart_data[index].event = SERIAL_EVENT_RX_PARITY_ERROR; + } else if (obj->serial.uart->SCFSR & 1 << 3) { + uart_data[index].event = SERIAL_EVENT_RX_FRAMING_ERROR; + } + ((void (*)())uart_data[index].async_rx_callback)(); + } + serial_rx_abort_asynch(obj); + + was_masked = __disable_irq(); + if (obj->serial.uart->SCFSR & 0x93) { + err_read = obj->serial.uart->SCFSR; + obj->serial.uart->SCFSR = (err_read & ~0x93); + } + if (obj->serial.uart->SCLSR & 1) { + obj->serial.uart->SCLSR = 0; + } + if (!was_masked) { + __enable_irq(); + } + } } /* TX handler */ @@ -468,39 +588,83 @@ static void uart7_rx_irq(void) { uart_rx_irq(SCIFRXI7_IRQn, 7); } +/* Error handler */ +static void uart0_er_irq(void) +{ + uart_err_irq(SCIFERI0_IRQn, 0); +} +static void uart1_er_irq(void) +{ + uart_err_irq(SCIFERI0_IRQn, 1); +} +static void uart2_er_irq(void) +{ + uart_err_irq(SCIFERI0_IRQn, 2); +} +static void uart3_er_irq(void) +{ + uart_err_irq(SCIFERI0_IRQn, 3); +} +static void uart4_er_irq(void) +{ + uart_err_irq(SCIFERI0_IRQn, 4); +} +static void uart5_er_irq(void) +{ + uart_err_irq(SCIFERI0_IRQn, 5); +} +static void uart6_er_irq(void) +{ + uart_err_irq(SCIFERI0_IRQn, 6); +} +static void uart7_er_irq(void) +{ + uart_err_irq(SCIFERI0_IRQn, 7); +} void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { irq_handler = handler; - uart_data[obj->index].serial_irq_id = id; + uart_data[obj->serial.index].serial_irq_id = id; +} + +static void serial_irq_set_irq(IRQn_Type IRQn, IRQHandler handler, uint32_t enable) +{ + if (enable) { + InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler); + GIC_SetPriority(IRQn, 5); + GIC_EnableIRQ(IRQn); + } else { + GIC_DisableIRQ(IRQn); + } } static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) { IRQn_Type IRQn; IRQHandler handler; - IRQn = irq_set_tbl[obj->index][irq]; - handler = hander_set_tbl[obj->index][irq]; + IRQn = irq_set_tbl[obj->serial.index][irq]; + handler = hander_set_tbl[obj->serial.index][irq]; - if ((obj->index >= 0) && (obj->index <= 7)) { - if (enable) { - InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler); - GIC_SetPriority(IRQn, 5); - GIC_EnableIRQ(IRQn); - } else { - GIC_DisableIRQ(IRQn); - } + if ((obj->serial.index >= 0) && (obj->serial.index <= 7)) { + serial_irq_set_irq(IRQn, handler, enable); } } +static void serial_irq_err_set(serial_t *obj, uint32_t enable) +{ + serial_irq_set_irq(irq_set_tbl[obj->serial.index][2], hander_set_tbl[obj->serial.index][2], enable); + serial_irq_set_irq(irq_set_tbl[obj->serial.index][3], hander_set_tbl[obj->serial.index][3], enable); +} + void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { if (RxIrq == irq) { - uart_data[obj->index].rx_irq_set_api = enable; + uart_data[obj->serial.index].rx_irq_set_api = enable; } serial_irq_set_internal(obj, irq, enable); } static void serial_flow_irq_set(serial_t *obj, uint32_t enable) { - uart_data[obj->index].rx_irq_set_flow = enable; + uart_data[obj->serial.index].rx_irq_set_flow = enable; serial_irq_set_internal(obj, RxIrq, enable); } @@ -517,29 +681,29 @@ #else was_masked = __disable_irq(); #endif /* __ICCARM__ */ - if (obj->uart->SCFSR & 0x93) { - err_read = obj->uart->SCFSR; - obj->uart->SCFSR = (err_read & ~0x93); + if (obj->serial.uart->SCFSR & 0x93) { + err_read = obj->serial.uart->SCFSR; + obj->serial.uart->SCFSR = (err_read & ~0x93); } - obj->uart->SCSCR |= 0x0040; // Set RIE + obj->serial.uart->SCSCR |= 0x0040; // Set RIE if (!was_masked) { __enable_irq(); } - if (obj->uart->SCLSR & 0x0001) { - obj->uart->SCLSR = 0u; // ORER clear + if (obj->serial.uart->SCLSR & 0x0001) { + obj->serial.uart->SCLSR = 0u; // ORER clear } while (!serial_readable(obj)); - data = obj->uart->SCFRDR & 0xff; + data = obj->serial.uart->SCFRDR & 0xff; #if defined ( __ICCARM__ ) was_masked = __disable_irq_iar(); #else was_masked = __disable_irq(); #endif /* __ICCARM__ */ - err_read = obj->uart->SCFSR; - obj->uart->SCFSR = (err_read & 0xfffD); // Clear RDF + err_read = obj->serial.uart->SCFSR; + obj->serial.uart->SCFSR = (err_read & 0xfffD); // Clear RDF if (!was_masked) { __enable_irq(); } @@ -551,39 +715,35 @@ } void serial_putc(serial_t *obj, int c) { - uint16_t dummy_read; + while (!serial_writable(obj)); + obj->serial.uart->SCFTDR = c; + serial_put_done(obj); +} + +static void serial_put_done(serial_t *obj) +{ int was_masked; - + volatile uint16_t dummy_read; + #if defined ( __ICCARM__ ) was_masked = __disable_irq_iar(); #else was_masked = __disable_irq(); #endif /* __ICCARM__ */ - obj->uart->SCSCR |= 0x0080; // Set TIE + dummy_read = obj->serial.uart->SCFSR; + obj->serial.uart->SCFSR = (dummy_read & 0xff9f); // Clear TEND/TDFE + obj->serial.uart->SCSCR |= 0x0080; // Set TIE if (!was_masked) { __enable_irq(); } - while (!serial_writable(obj)); - obj->uart->SCFTDR = c; -#if defined ( __ICCARM__ ) - was_masked = __disable_irq_iar(); -#else - was_masked = __disable_irq(); -#endif /* __ICCARM__ */ - dummy_read = obj->uart->SCFSR; - obj->uart->SCFSR = (dummy_read & 0xff9f); // Clear TEND/TDFE - if (!was_masked) { - __enable_irq(); - } - uart_data[obj->index].count++; } int serial_readable(serial_t *obj) { - return ((obj->uart->SCFSR & 0x02) != 0); // RDF + return ((obj->serial.uart->SCFSR & 0x02) != 0); // RDF } int serial_writable(serial_t *obj) { - return ((obj->uart->SCFSR & 0x20) != 0); // TDFE + return ((obj->serial.uart->SCFSR & 0x20) != 0); // TDFE } void serial_clear(serial_t *obj) { @@ -594,9 +754,9 @@ was_masked = __disable_irq(); #endif /* __ICCARM__ */ - obj->uart->SCFCR |= 0x06; // TFRST = 1, RFRST = 1 - obj->uart->SCFCR &= ~0x06; // TFRST = 0, RFRST = 0 - obj->uart->SCFSR &= ~0x0093u; // ER, BRK, RDF, DR = 0 + obj->serial.uart->SCFCR |= 0x06; // TFRST = 1, RFRST = 1 + obj->serial.uart->SCFCR &= ~0x06; // TFRST = 0, RFRST = 0 + obj->serial.uart->SCFSR &= ~0x0093u; // ER, BRK, RDF, DR = 0 if (!was_masked) { __enable_irq(); @@ -615,8 +775,8 @@ was_masked = __disable_irq(); #endif /* __ICCARM__ */ // TxD Output(L) - obj->uart->SCSPTR &= ~0x0001u; // SPB2DT = 0 - obj->uart->SCSCR &= ~0x0020u; // TE = 0 (Output disable) + obj->serial.uart->SCSPTR &= ~0x0001u; // SPB2DT = 0 + obj->serial.uart->SCSCR &= ~0x0020u; // TE = 0 (Output disable) if (!was_masked) { __enable_irq(); } @@ -629,8 +789,8 @@ #else was_masked = __disable_irq(); #endif /* __ICCARM__ */ - obj->uart->SCSCR |= 0x0020u; // TE = 1 (Output enable) - obj->uart->SCSPTR |= 0x0001u; // SPB2DT = 1 + obj->serial.uart->SCSCR |= 0x0020u; // TE = 1 (Output enable) + obj->serial.uart->SCSPTR |= 0x0001u; // SPB2DT = 1 if (!was_masked) { __enable_irq(); } @@ -648,7 +808,7 @@ #else was_masked = __disable_irq(); #endif /* __ICCARM__ */ - obj->uart->SCFCR = 0x0008u; // CTS/RTS enable + obj->serial.uart->SCFCR = 0x0008u; // CTS/RTS enable if (!was_masked) { __enable_irq(); } @@ -660,13 +820,118 @@ #else was_masked = __disable_irq(); #endif /* __ICCARM__ */ - obj->uart->SCFCR = 0x0000u; // CTS/RTS diable + obj->serial.uart->SCFCR = 0x0000u; // CTS/RTS diable if (!was_masked) { __enable_irq(); } } } +static uint8_t serial_available_buffer(serial_t *obj) +{ + return 1; + /* Faster but unstable way */ + /* + uint16_t ret = 16 - ((obj->serial.uart->SCFDR >> 8) & 0x1F); + while (ret == 0) { + ret = 16 - ((obj->serial.uart->SCFDR >> 8) & 0x1F); + } + MBED_ASSERT(0 < ret && ret <= 16); + return ret; + */ +} +#if DEVICE_SERIAL_ASYNCH + +/****************************************************************************** + * ASYNCHRONOUS HAL + ******************************************************************************/ + +int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) +{ + int i; + buffer_t *buf = &obj->tx_buff; + struct serial_global_data_s *data = uart_data + obj->serial.index; + + if (tx_length == 0) { + return 0; + } + + buf->buffer = (void *)tx; + buf->length = tx_length * tx_width / 8; + buf->pos = 0; + buf->width = tx_width; + data->tranferring_obj = obj; + data->async_tx_callback = handler; + serial_irq_set(obj, TxIrq, 1); + + while (!serial_writable(obj)); + i = buf->length; + if (serial_available_buffer(obj) < i) { + i = serial_available_buffer(obj); + } + do { + uint8_t c = *(uint8_t *)buf->buffer; + obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + 1; + ++buf->pos; + obj->serial.uart->SCFTDR = c; + } while (--i); + serial_put_done(obj); + + return buf->length; +} +void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint) +{ + buffer_t *buf = &obj->rx_buff; + struct serial_global_data_s *data = uart_data + obj->serial.index; + + if (rx_length == 0) { + return; + } + + buf->buffer = rx; + buf->length = rx_length * rx_width / 8; + buf->pos = 0; + buf->width = rx_width; + obj->char_match = char_match; + obj->char_found = 0; + data->receiving_obj = obj; + data->async_rx_callback = handler; + data->event = 0; + data->wanted_rx_events = event; + + serial_irq_set(obj, RxIrq, 1); + serial_irq_err_set(obj, 1); +} +uint8_t serial_tx_active(serial_t *obj) +{ + return uart_data[obj->serial.index].tranferring_obj != NULL; +} + +uint8_t serial_rx_active(serial_t *obj) +{ + return uart_data[obj->serial.index].receiving_obj != NULL; +} + +int serial_irq_handler_asynch(serial_t *obj) +{ + return uart_data[obj->serial.index].event; +} + +void serial_tx_abort_asynch(serial_t *obj) +{ + uart_data[obj->serial.index].tranferring_obj = NULL; + obj->serial.uart->SCFCR |= 1 << 2; + obj->serial.uart->SCFCR &= ~(1 << 2); +} + +void serial_rx_abort_asynch(serial_t *obj) +{ + uart_data[obj->serial.index].receiving_obj = NULL; + obj->serial.uart->SCFCR |= 1 << 1; + obj->serial.uart->SCFCR &= ~(1 << 1); +} + +#endif
--- a/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c Wed Apr 27 19:30:12 2016 +0100 +++ b/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c Fri Apr 29 01:15:11 2016 +0100 @@ -76,11 +76,12 @@ uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso); uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel); uint32_t spi = pinmap_merge(spi_data, spi_cntl); - + MBED_ASSERT((int)spi != NC); - - obj->spi = (struct st_rspi *)RSPI[spi]; - + + obj->spi.spi = (struct st_rspi *)RSPI[spi]; + obj->spi.index = spi; + // enable power and clocking switch (spi) { case SPI_0: CPGSTBCR10 &= ~(0x80); break; @@ -89,18 +90,18 @@ case SPI_3: CPGSTBCR10 &= ~(0x10); break; } dummy = CPGSTBCR10; - - obj->spi->SPCR = 0x00; // CTRL to 0 - obj->spi->SPSCR = 0x00; // no sequential operation - obj->spi->SSLP = 0x00; // SSL 'L' active - obj->spi->SPDCR = 0x20; // byte access - obj->spi->SPCKD = 0x00; // SSL -> enable CLK delay : 1RSPCK - obj->spi->SSLND = 0x00; // CLK end -> SSL neg delay : 1RSPCK - obj->spi->SPND = 0x00; // delay between CMD : 1RSPCK + 2P1CLK - obj->spi->SPPCR = 0x20; // MOSI Idle fixed value equals 0 - obj->spi->SPBFCR = 0xf0; // and set trigger count: read 1, write 1 - obj->spi->SPBFCR = 0x30; // and reset buffer - + + obj->spi.spi->SPCR = 0x00; // CTRL to 0 + obj->spi.spi->SPSCR = 0x00; // no sequential operation + obj->spi.spi->SSLP = 0x00; // SSL 'L' active + obj->spi.spi->SPDCR = 0x20; // byte access + obj->spi.spi->SPCKD = 0x00; // SSL -> enable CLK delay : 1RSPCK + obj->spi.spi->SSLND = 0x00; // CLK end -> SSL neg delay : 1RSPCK + obj->spi.spi->SPND = 0x00; // delay between CMD : 1RSPCK + 2P1CLK + obj->spi.spi->SPPCR = 0x20; // MOSI Idle fixed value equals 0 + obj->spi.spi->SPBFCR = 0xf0; // and set trigger count: read 1, write 1 + obj->spi.spi->SPBFCR = 0x30; // and reset buffer + // pin out the spi pins pinmap_pinout(mosi, PinMap_SPI_MOSI); pinmap_pinout(miso, PinMap_SPI_MISO); @@ -120,7 +121,7 @@ uint16_t mask = 0xf03; uint16_t wk_spcmd0; uint8_t splw; - + switch (mode) { case 0: case 1: @@ -132,7 +133,7 @@ error("SPI format error"); return; } - + switch (bits) { case 8: DSS = 0x7; @@ -153,18 +154,18 @@ tmp |= phase; tmp |= (polarity << 1); tmp |= (DSS << 8); - obj->bits = bits; - + obj->spi.bits = bits; + spi_disable(obj); - wk_spcmd0 = obj->spi->SPCMD0; + wk_spcmd0 = obj->spi.spi->SPCMD0; wk_spcmd0 &= ~mask; wk_spcmd0 |= (mask & tmp); - obj->spi->SPCMD0 = wk_spcmd0; - obj->spi->SPDCR = splw; + obj->spi.spi->SPCMD0 = wk_spcmd0; + obj->spi.spi->SPDCR = splw; if (slave) { - obj->spi->SPCR &=~(1 << 3); // MSTR to 0 + obj->spi.spi->SPCR &=~(1 << 3); // MSTR to 0 } else { - obj->spi->SPCR |= (1 << 3); // MSTR to 1 + obj->spi.spi->SPCR |= (1 << 3); // MSTR to 1 } spi_enable(obj); } @@ -177,21 +178,21 @@ uint32_t hz_min; uint16_t mask = 0x000c; uint16_t wk_spcmd0; - + /* set PCLK */ if (RZ_A1_IsClockMode0() == false) { pclk_base = CM1_RENESAS_RZ_A1_P1_CLK; } else { pclk_base = CM0_RENESAS_RZ_A1_P1_CLK; } - + hz_min = pclk_base / 2 / 256 / 8; hz_max = pclk_base / 2; if ((hz < hz_min) || (hz > hz_max)) { error("Couldn't setup requested SPI frequency"); return; } - + div = (pclk_base / hz / 2); while (div > 256) { div >>= 1; @@ -199,53 +200,53 @@ } div -= 1; brdv = (brdv << 2); - + spi_disable(obj); - obj->spi->SPBR = div; - wk_spcmd0 = obj->spi->SPCMD0; + obj->spi.spi->SPBR = div; + wk_spcmd0 = obj->spi.spi->SPCMD0; wk_spcmd0 &= ~mask; wk_spcmd0 |= (mask & brdv); - obj->spi->SPCMD0 = wk_spcmd0; + obj->spi.spi->SPCMD0 = wk_spcmd0; spi_enable(obj); } static inline void spi_disable(spi_t *obj) { - obj->spi->SPCR &= ~(1 << 6); // SPE to 0 + obj->spi.spi->SPCR &= ~(1 << 6); // SPE to 0 } static inline void spi_enable(spi_t *obj) { - obj->spi->SPCR |= (1 << 6); // SPE to 1 + obj->spi.spi->SPCR |= (1 << 6); // SPE to 1 } static inline int spi_readable(spi_t *obj) { - return obj->spi->SPSR & (1 << 7); // SPRF + return obj->spi.spi->SPSR & (1 << 7); // SPRF } static inline int spi_tend(spi_t *obj) { - return obj->spi->SPSR & (1 << 6); // TEND + return obj->spi.spi->SPSR & (1 << 6); // TEND } static inline void spi_write(spi_t *obj, int value) { - if (obj->bits == 8) { - obj->spi->SPDR.UINT8[0] = (uint8_t)value; - } else if (obj->bits == 16) { - obj->spi->SPDR.UINT16[0] = (uint16_t)value; + if (obj->spi.bits == 8) { + obj->spi.spi->SPDR.UINT8[0] = (uint8_t)value; + } else if (obj->spi.bits == 16) { + obj->spi.spi->SPDR.UINT16[0] = (uint16_t)value; } else { - obj->spi->SPDR.UINT32 = (uint32_t)value; + obj->spi.spi->SPDR.UINT32 = (uint32_t)value; } } static inline int spi_read(spi_t *obj) { int read_data; - - if (obj->bits == 8) { - read_data = obj->spi->SPDR.UINT8[0]; - } else if (obj->bits == 16) { - read_data = obj->spi->SPDR.UINT16[0]; + + if (obj->spi.bits == 8) { + read_data = obj->spi.spi->SPDR.UINT8[0]; + } else if (obj->spi.bits == 16) { + read_data = obj->spi.spi->SPDR.UINT16[0]; } else { - read_data = obj->spi->SPDR.UINT32; + read_data = obj->spi.spi->SPDR.UINT32; } - + return read_data; } @@ -270,3 +271,307 @@ int spi_busy(spi_t *obj) { return 0; } + +#if DEVICE_SPI_ASYNCH + +#define IRQ_NUM 2 + +static void spi_irqs_set(spi_t *obj, uint32_t enable); +static void spi_async_write(spi_t *obj); +static void spi_async_read(spi_t *obj); + +static void spi0_rx_irq(void); +static void spi1_rx_irq(void); +static void spi2_rx_irq(void); +static void spi3_rx_irq(void); +static void spi4_rx_irq(void); +static void spi0_er_irq(void); +static void spi1_er_irq(void); +static void spi2_er_irq(void); +static void spi3_er_irq(void); +static void spi4_er_irq(void); + +static const IRQn_Type irq_set_tbl[RSPI_COUNT][IRQ_NUM] = { + {RSPISPRI0_IRQn, RSPISPEI0_IRQn}, + {RSPISPRI1_IRQn, RSPISPEI1_IRQn}, + {RSPISPRI2_IRQn, RSPISPEI2_IRQn}, + {RSPISPRI3_IRQn, RSPISPEI3_IRQn}, + {RSPISPRI4_IRQn, RSPISPEI4_IRQn} +}; + +static const IRQHandler hander_set_tbl[RSPI_COUNT][IRQ_NUM] = { + {spi0_rx_irq, spi0_er_irq}, + {spi1_rx_irq, spi1_er_irq}, + {spi2_rx_irq, spi2_er_irq}, + {spi3_rx_irq, spi3_er_irq}, + {spi4_rx_irq, spi4_er_irq} +}; + +struct spi_global_data_s { + spi_t *async_obj; + uint32_t async_callback, event, wanted_events; +}; + +static struct spi_global_data_s spi_data[RSPI_COUNT]; + +static void spi_rx_irq(IRQn_Type irq_num, uint32_t index) +{ + spi_t *obj = spi_data[index].async_obj; + if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) { + spi_async_read(obj); + } else { + if (obj->rx_buff.buffer && obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) { + spi_data[obj->spi.index].event = SPI_EVENT_INTERNAL_TRANSFER_COMPLETE; + if (spi_data[obj->spi.index].wanted_events & SPI_EVENT_COMPLETE) { + spi_data[obj->spi.index].event |= SPI_EVENT_COMPLETE; + } + spi_irqs_set(obj, 0); + spi_data[obj->spi.index].async_obj = NULL; + ((void (*)())spi_data[obj->spi.index].async_callback)(); + return; + } + spi_read(obj); + } + if (obj->tx_buff.buffer) { + if (obj->tx_buff.pos == obj->tx_buff.length) { + spi_data[obj->spi.index].event = SPI_EVENT_INTERNAL_TRANSFER_COMPLETE; + if (spi_data[obj->spi.index].wanted_events & SPI_EVENT_COMPLETE) { + spi_data[obj->spi.index].event |= SPI_EVENT_COMPLETE; + } + spi_irqs_set(obj, 0); + spi_data[obj->spi.index].async_obj = NULL; + ((void (*)())spi_data[obj->spi.index].async_callback)(); + } else { + spi_async_write(obj); + } + } else { + if (obj->rx_buff.pos == obj->rx_buff.length) { + spi_data[obj->spi.index].event = SPI_EVENT_INTERNAL_TRANSFER_COMPLETE; + if (spi_data[obj->spi.index].wanted_events & SPI_EVENT_COMPLETE) { + spi_data[obj->spi.index].event |= SPI_EVENT_COMPLETE; + } + spi_irqs_set(obj, 0); + spi_data[obj->spi.index].async_obj = NULL; + ((void (*)())spi_data[obj->spi.index].async_callback)(); + } else { + spi_async_write(obj); + } + } +} + +static void spi_err_irq(IRQn_Type irq_num, uint32_t index) +{ + spi_t *obj = spi_data[index].async_obj; + spi_abort_asynch(obj); + spi_data[index].event = SPI_EVENT_ERROR; + if (spi_data[index].wanted_events & SPI_EVENT_ERROR) { + ((void (*)())spi_data[index].async_callback)(); + } +} + +static void spi0_rx_irq(void) +{ + spi_rx_irq(RSPISPRI0_IRQn, 0); +} + +static void spi1_rx_irq(void) +{ + spi_rx_irq(RSPISPRI1_IRQn, 1); +} + +static void spi2_rx_irq(void) +{ + spi_rx_irq(RSPISPRI2_IRQn, 2); +} + +static void spi3_rx_irq(void) +{ + spi_rx_irq(RSPISPRI3_IRQn, 3); +} + +static void spi4_rx_irq(void) +{ + spi_rx_irq(RSPISPRI4_IRQn, 4); +} + +static void spi0_er_irq(void) +{ + spi_err_irq(RSPISPEI0_IRQn, 0); +} + +static void spi1_er_irq(void) +{ + spi_err_irq(RSPISPEI1_IRQn, 1); +} + +static void spi2_er_irq(void) +{ + spi_err_irq(RSPISPEI2_IRQn, 2); +} + +static void spi3_er_irq(void) +{ + spi_err_irq(RSPISPEI3_IRQn, 3); +} + +static void spi4_er_irq(void) +{ + spi_err_irq(RSPISPEI4_IRQn, 4); +} + +static void spi_irqs_set(spi_t *obj, uint32_t enable) +{ + int i; + const IRQn_Type *irqTable = irq_set_tbl[obj->spi.index]; + const IRQHandler *handlerTable = hander_set_tbl[obj->spi.index]; + for (i = 0; i < IRQ_NUM; ++i) { + if (enable) { + InterruptHandlerRegister(irqTable[i], handlerTable[i]); + GIC_SetPriority(irqTable[i], 5); + GIC_EnableIRQ(irqTable[i]); + } else { + GIC_DisableIRQ(irqTable[i]); + } + } + if (enable) { + obj->spi.spi->SPCR |= (1 << 4) | (1 << 7); + } else { + obj->spi.spi->SPCR &= ~((1 << 4) | (1 << 7)); + } +} + +static void spi_async_write(spi_t *obj) +{ + uint8_t **width8; + uint16_t **width16; + uint32_t **width32; + + if (obj->tx_buff.buffer) { + switch (obj->tx_buff.width) { + case 8: + width8 = (uint8_t **)&obj->tx_buff.buffer; + spi_write(obj, **width8); + ++*width8; + obj->tx_buff.pos += sizeof(uint8_t); + break; + + case 16: + width16 = (uint16_t **)&obj->tx_buff.buffer; + spi_write(obj, **width16); + ++*width16; + obj->tx_buff.pos += sizeof(uint16_t); + break; + + case 32: + width32 = (uint32_t **)&obj->tx_buff.buffer; + spi_write(obj, **width32); + ++*width32; + obj->tx_buff.pos += sizeof(uint32_t); + break; + + default: + MBED_ASSERT(0); + break; + } + } else { + spi_write(obj, SPI_FILL_WORD); + } +} + +static void spi_async_read(spi_t *obj) +{ + uint8_t **width8; + uint16_t **width16; + uint32_t **width32; + + switch (obj->rx_buff.width) { + case 8: + width8 = (uint8_t **)&obj->rx_buff.buffer; + **width8 = spi_read(obj); + ++*width8; + obj->rx_buff.pos += sizeof(uint8_t); + break; + + case 16: + width16 = (uint16_t **)&obj->rx_buff.buffer; + **width16 = spi_read(obj); + ++*width16; + obj->rx_buff.pos += sizeof(uint16_t); + break; + + case 32: + width32 = (uint32_t **)&obj->rx_buff.buffer; + **width32 = spi_read(obj); + ++*width32; + obj->rx_buff.pos += sizeof(uint32_t); + break; + + default: + MBED_ASSERT(0); + break; + } +} + +/****************************************************************************** + * ASYNCHRONOUS HAL + ******************************************************************************/ + +void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint) +{ + int i; + MBED_ASSERT(obj); + MBED_ASSERT(tx || rx); + MBED_ASSERT(tx && ! rx ? tx_length : 1); + MBED_ASSERT(rx && ! tx ? rx_length : 1); + MBED_ASSERT(obj->spi.spi->SPCR & (1 << 3)); /* Slave mode */ + MBED_ASSERT(bit_width == 8 || bit_width == 16 || bit_width == 32); + + if (tx_length) { + obj->tx_buff.buffer = (void *)tx; + } else { + obj->tx_buff.buffer = NULL; + } + obj->tx_buff.length = tx_length * bit_width / 8; + obj->tx_buff.pos = 0; + obj->tx_buff.width = bit_width; + if (rx_length) { + obj->rx_buff.buffer = rx; + } else { + obj->rx_buff.buffer = NULL; + } + obj->rx_buff.length = rx_length * bit_width / 8; + obj->rx_buff.pos = 0; + obj->rx_buff.width = bit_width; + for (i = 0; i < obj->rx_buff.length; i++) { + ((uint8_t *)obj->rx_buff.buffer)[i] = SPI_FILL_WORD; + } + + spi_data[obj->spi.index].async_callback = handler; + spi_data[obj->spi.index].async_obj = obj; + spi_data[obj->spi.index].event = 0; + spi_data[obj->spi.index].wanted_events = event; + + spi_irqs_set(obj, 1); + + spi_async_write(obj); +} + +uint32_t spi_irq_handler_asynch(spi_t *obj) +{ + return spi_data[obj->spi.index].event; +} + +uint8_t spi_active(spi_t *obj) +{ + return spi_data[obj->spi.index].async_obj != NULL; +} + +void spi_abort_asynch(spi_t *obj) +{ + spi_disable(obj); + spi_irqs_set(obj, 0); + spi_data[obj->spi.index].async_obj = NULL; + spi_enable(obj); +} + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/PeripheralNames.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,182 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART0, + UART1, + UART2, + UART3, + UART4, + UART5, + UART6, + UART7, +} UARTName; + +// PWMType & 1 == 1 then have to use PWDTR[12] == 1 +typedef enum { + PWM1A = 0, + PWM1B, + PWM1C, + PWM1D, + PWM1E, + PWM1F, + PWM1G, + PWM1H, + PWM2A = 0x10, + PWM2B, + PWM2C, + PWM2D, + PWM2E, + PWM2F, + PWM2G, + PWM2H, +} PWMType; + +typedef enum { + TIOC0A = 0, + TIOC0B, + TIOC0C, + TIOC0D, + TIOC1A = 0x10, + TIOC1B, + TIOC2A = 0x20, + TIOC2B, + TIOC3A = 0x30, + TIOC3B, + TIOC3C, + TIOC3D, + TIOC4A = 0x40, + TIOC4B, + TIOC4C, + TIOC4D, +} MTU2_PWMType; + +typedef enum { + PWM0_PIN = 0, + PWM1_PIN, + PWM2_PIN, + PWM3_PIN, + PWM4_PIN, + PWM5_PIN, + PWM6_PIN, + PWM7_PIN, + PWM8_PIN, + PWM9_PIN, + PWM10_PIN, + PWM11_PIN, + PWM12_PIN, +#ifdef MAX_PERI + PWM13_PIN, + PWM14_PIN, + PWM15_PIN, + MTU2_PWM0_PIN = 0x20, + MTU2_PWM1_PIN, + MTU2_PWM2_PIN, + MTU2_PWM3_PIN, + MTU2_PWM4_PIN, + MTU2_PWM5_PIN, + MTU2_PWM6_PIN, + MTU2_PWM7_PIN, + MTU2_PWM8_PIN, + MTU2_PWM9_PIN, + MTU2_PWM10_PIN, + MTU2_PWM11_PIN, + MTU2_PWM12_PIN, + MTU2_PWM13_PIN, + MTU2_PWM14_PIN, + MTU2_PWM15_PIN, + MTU2_PWM16_PIN, + MTU2_PWM17_PIN, + MTU2_PWM18_PIN, + MTU2_PWM19_PIN, + MTU2_PWM20_PIN, + MTU2_PWM21_PIN, + MTU2_PWM22_PIN, + MTU2_PWM23_PIN, + MTU2_PWM23_PIN, + MTU2_PWM24_PIN, + MTU2_PWM25_PIN, + MTU2_PWM26_PIN, +#else + MTU2_PWM0_PIN = 0x20, + MTU2_PWM1_PIN, + MTU2_PWM2_PIN, + MTU2_PWM3_PIN, + MTU2_PWM4_PIN, + MTU2_PWM5_PIN, + MTU2_PWM6_PIN, + MTU2_PWM7_PIN, + MTU2_PWM8_PIN, + MTU2_PWM9_PIN, + MTU2_PWM10_PIN, + MTU2_PWM11_PIN, +#endif +} PWMName; + +typedef enum { + AN0= 0, + AN1= 1, + AN2= 2, + AN3= 3, + AN4= 4, + AN5= 5, + AN6= 6, + AN7= 7, +} ADCName; + +typedef enum { + SPI_1 = 1, + SPI_2, + SPI_3, + SPI_4, +} SPIName; + +typedef enum { + I2C_0 = 0, + I2C_1, + I2C_2, + I2C_3 +} I2CName; + +typedef enum { + CAN_0 = 0, + CAN_1, + CAN_2, + CAN_3, + CAN_4 +} CANName; + + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART3 + + + +#ifdef __cplusplus +} +#endif + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/PinNames.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,79 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 4 + +typedef enum { + P0_0 = 0, P0_1, P0_2, P0_3, P0_4, P0_5, + P1_0 = 16, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, + P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, + P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, + P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, + P5_0, P5_1, P5_2, P5_3, P5_4, P5_5, P5_6, P5_7, P5_8, P5_9, P5_10, + P6_0 = 96, P6_1, P6_2, P6_3, P6_4, P6_5, P6_6, P6_7, P6_8, P6_9, P6_10, P6_11, P6_12, P6_13, P6_14, P6_15, + P7_0, P7_1, P7_2, P7_3, P7_4, P7_5, P7_6, P7_7, P7_8, P7_9, P7_10, P7_11, P7_12, P7_13, P7_14, P7_15, + P8_0, P8_1, P8_2, P8_3, P8_4, P8_5, P8_6, P8_7, P8_8, P8_9, P8_10, P8_11, P8_12, P8_13, P8_14, P8_15, + P9_0, P9_1, P9_2, P9_3, P9_4, P9_5, P9_6, P9_7, + + // mbed Pin Names + LED1 = P7_1, + LED_RED = LED1, + // mbed led alias to keep some test happy, becasue physically they are no LED2,LED3 & LED4 on the board + LED2 = LED1, + LED3 = LED2, + LED4 = LED3, + + I2C_SCL = P1_0, + I2C_SDA = P1_1, + + USBTX = P8_8, + USBRX = P8_9, + + //USER_BUTTON0 = P6_0, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullUp = 0, + PullDown = 3, + PullNone = 2, + OpenDrain = 4, + PullDefault = PullDown +} PinMode; + +#define PINGROUP(pin) (((pin)>>PORT_SHIFT)&0x0f) +#define PINNO(pin) ((pin)&0x0f) + +#ifdef __cplusplus +} +#endif + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/PortNames.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,37 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + Port0 = 0, + Port1 = 1, + Port3 = 3, + Port4 = 4, + Port5 = 5, + Port7 = 7, + Port8 = 8, + Port9 = 9 +} PortName; + +#ifdef __cplusplus +} +#endif +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/TARGET_MBED_VKRZA1H/reserved_pins.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,6 @@ +#ifndef RESERVED_PINS_H +#define RESERVED_PINS_H + +#define TARGET_RESERVED_PINS {} + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/analogin_api.c Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,133 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "analogin_api.h" + +#include "cmsis.h" +#include "pinmap.h" + +#include "adc_iodefine.h" +#include "cpg_iodefine.h" + +#define ANALOGIN_MEDIAN_FILTER 0 + +#ifdef MAX_PERI +static const PinMap PinMap_ADC[] = { + {P1_8, AN0, 1}, + {P1_9, AN1, 1}, + {P1_10, AN2, 1}, + {P1_11, AN3, 1}, + {P1_12, AN4, 1}, + {P1_13, AN5, 1}, + {P1_14, AN6, 1}, + {P1_15, AN7, 1}, + {NC, NC, 0} +}; +#else +static const PinMap PinMap_ADC[] = { + {P1_8, AN0, 1}, + {P1_9, AN1, 1}, + {P1_10, AN2, 1}, + {P1_11, AN3, 1}, + {P1_12, AN4, 1}, + {P1_13, AN5, 1}, + {P1_15, AN7, 1}, + {NC, NC, 0} +}; +#endif + +static volatile uint16_t *ADCDR[] = { + &ADCADDRA, + &ADCADDRB, + &ADCADDRC, + &ADCADDRD, + &ADCADDRE, + &ADCADDRF, + &ADCADDRG, + &ADCADDRH, +}; + +void analogin_init(analogin_t *obj, PinName pin) { + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); + MBED_ASSERT(obj->adc != (ADCName)NC); + + CPGSTBCR3 &= ~(1 << 1); + CPGSTBCR6 &= ~(1 << 7); + + // 15: ADF 14: ADIE 13: ADST, [12:9] TRGS..0 + // [8:6] CKS 010 :: 340tclk + // [5:3] MDS 000 :: single mode + // [2:0] CH 000 :: AN0 + ADCADCSR = 0x0080; + + pinmap_pinout(pin, PinMap_ADC); +} + +static inline uint32_t adc_read(analogin_t *obj) { + volatile uint16_t data; + + // Select the appropriate channel and start conversion + ADCADCSR &= 0xfff8; + ADCADCSR |= (1 << 13 | (obj->adc & 0x7)); + + // Wait end of conversion + do { + data = ADCADCSR; + } while (((data & (1 << 15)) == 0) || ((data & (1 << 13)) != 0)); + + // clear flag + ADCADCSR &= ~(1 << 15); + + return ((*(ADCDR[obj->adc])) >> 4) & 0x0FFF; // 12 bits range +} + +#if ANALOGIN_MEDIAN_FILTER +static inline void order(uint32_t *a, uint32_t *b) { + if (*a > *b) { + uint32_t t = *a; + *a = *b; + *b = t; + } +} +#endif + +static inline uint32_t adc_read_u32(analogin_t *obj) { + uint32_t value; +#if ANALOGIN_MEDIAN_FILTER + uint32_t v1 = adc_read(obj); + uint32_t v2 = adc_read(obj); + uint32_t v3 = adc_read(obj); + order(&v1, &v2); + order(&v2, &v3); + order(&v1, &v2); + value = v2; +#else + value = adc_read(obj); +#endif + return value; +} + +uint16_t analogin_read_u16(analogin_t *obj) { + uint32_t value = adc_read_u32(obj); + + return (value << 4) | ((value >> 8) & 0x000F); // 12-bit to 16-bit conversion +} + +float analogin_read(analogin_t *obj) { + uint32_t value = adc_read_u32(obj); + + return (float)value * (1.0f / (float)0x0FFF); // 12 bits range +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/can_api.c Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,1026 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include <string.h> +#include "mbed_assert.h" +#include "can_api.h" +#include "RZ_A1_Init.h" +#include "cmsis.h" +#include "pinmap.h" +#include "rscan0_iodefine.h" +#include "r_typedefs.h" +#include "VKRZA1H.h" + +#define CAN_NUM 5 +#define CAN_SND_RCV 2 +#define IRQ_NUM 8 + +static void can_rec_irq(uint32_t ch); +static void can_trx_irq(uint32_t ch); +static void can_err_irq(uint32_t ch, CanIrqType type); +static void can0_rec_irq(void); +static void can1_rec_irq(void); +static void can2_rec_irq(void); +static void can3_rec_irq(void); +static void can4_rec_irq(void); +static void can0_trx_irq(void); +static void can1_trx_irq(void); +static void can2_trx_irq(void); +static void can3_trx_irq(void); +static void can4_trx_irq(void); +static void can0_err_warning_irq(void); +static void can1_err_warning_irq(void); +static void can2_err_warning_irq(void); +static void can3_err_warning_irq(void); +static void can4_err_warning_irq(void); +static void can0_overrun_irq(void); +static void can1_overrun_irq(void); +static void can2_overrun_irq(void); +static void can3_overrun_irq(void); +static void can4_overrun_irq(void); +static void can0_passive_irq(void); +static void can1_passive_irq(void); +static void can2_passive_irq(void); +static void can3_passive_irq(void); +static void can4_passive_irq(void); +static void can0_arb_lost_irq(void); +static void can1_arb_lost_irq(void); +static void can2_arb_lost_irq(void); +static void can3_arb_lost_irq(void); +static void can4_arb_lost_irq(void); +static void can0_bus_err_irq(void); +static void can1_bus_err_irq(void); +static void can2_bus_err_irq(void); +static void can3_bus_err_irq(void); +static void can4_bus_err_irq(void); +static void can_reset_reg(can_t *obj); +static void can_reset_recv_rule(can_t *obj); +static void can_reset_buffer(can_t *obj); +static void can_reconfigure_channel(void); +static void can_set_frequency(can_t *obj, int f); +static void can_set_global_mode(int mode); +static void can_set_channel_mode(uint32_t ch, int mode); + +typedef enum { + CAN_SEND = 0, + CAN_RECV +} CANfunc; + +typedef enum { + GL_OPE = 0, + GL_RESET, + GL_TEST +} Globalmode; + +typedef enum { + CH_COMM = 0, + CH_RESET, + CH_HOLD +} Channelmode; + +typedef struct { + IRQn_Type int_num; /* Interrupt number */ + IRQHandler handler; /* Interrupt handler */ +} can_info_int_t; + +static can_irq_handler irq_handler; +static uint32_t can_irq_id[CAN_NUM]; +static int can_initialized[CAN_NUM] = {0}; + +#ifdef MAX_PERI +static const PinMap PinMap_CAN_RD[] = { + {P7_8 , CAN_0, 4}, + {P9_1 , CAN_0, 3}, + {P1_4 , CAN_1, 3}, + {P5_9 , CAN_1, 5}, + {P7_11 , CAN_1, 4}, + {P4_9 , CAN_2, 6}, + {P6_4 , CAN_2, 3}, + {P7_2 , CAN_2, 5}, + {P2_12 , CAN_3, 5}, + {P4_2 , CAN_3, 4}, + {P1_5 , CAN_4, 3}, + {P2_14 , CAN_4, 5}, + {NC , NC , 0} +}; + +static const PinMap PinMap_CAN_TD[] = { + {P7_9 , CAN_0, 4}, + {P9_0 , CAN_0, 3}, + {P5_10 , CAN_1, 5}, + {P7_10 , CAN_1, 4}, + {P4_8 , CAN_2, 6}, + {P6_5 , CAN_2, 3}, + {P7_3 , CAN_2, 5}, + {P2_13 , CAN_3, 5}, + {P4_3 , CAN_3, 4}, + {P4_11 , CAN_4, 6}, + {P8_10 , CAN_4, 5}, + {NC , NC , 0} +}; +#else +static const PinMap PinMap_CAN_RD[] = { + {P9_1 , CAN_0, 3}, + {P1_4 , CAN_1, 3}, + {P5_9 , CAN_1, 5}, + {P4_2 , CAN_3, 4}, + {P1_5 , CAN_4, 3}, + {NC , NC , 0} +}; + +static const PinMap PinMap_CAN_TD[] = { + {P9_0 , CAN_0, 3}, + {P5_10 , CAN_1, 5}, + {P4_3 , CAN_3, 4}, + {P8_10 , CAN_4, 5}, + {NC , NC , 0} +}; +#endif + +static __IO uint32_t *CTR_MATCH[] = { + &RSCAN0C0CTR, + &RSCAN0C1CTR, + &RSCAN0C2CTR, + &RSCAN0C3CTR, + &RSCAN0C4CTR, +}; + +static __IO uint32_t *CFG_MATCH[] = { + &RSCAN0C0CFG, + &RSCAN0C1CFG, + &RSCAN0C2CFG, + &RSCAN0C3CFG, + &RSCAN0C4CFG, +}; + +static __IO uint32_t *RFCC_MATCH[] = { + &RSCAN0RFCC0, + &RSCAN0RFCC1, + &RSCAN0RFCC2, + &RSCAN0RFCC3, + &RSCAN0RFCC4, + &RSCAN0RFCC5, + &RSCAN0RFCC6, + &RSCAN0RFCC7 +}; + +static __IO uint32_t *TXQCC_MATCH[] = { + &RSCAN0TXQCC0, + &RSCAN0TXQCC1, + &RSCAN0TXQCC2, + &RSCAN0TXQCC3, + &RSCAN0TXQCC4, +}; + +static __IO uint32_t *THLCC_MATCH[] = { + &RSCAN0THLCC0, + &RSCAN0THLCC1, + &RSCAN0THLCC2, + &RSCAN0THLCC3, + &RSCAN0THLCC4, +}; + +static __IO uint32_t *STS_MATCH[] = { + &RSCAN0C0STS, + &RSCAN0C1STS, + &RSCAN0C2STS, + &RSCAN0C3STS, + &RSCAN0C4STS, +}; + +static __IO uint32_t *ERFL_MATCH[] = { + &RSCAN0C0ERFL, + &RSCAN0C1ERFL, + &RSCAN0C2ERFL, + &RSCAN0C3ERFL, + &RSCAN0C4ERFL, +}; + +static __IO uint32_t *CFCC_TBL[CAN_NUM][CAN_SND_RCV] = { + { &RSCAN0CFCC0 , &RSCAN0CFCC1 }, + { &RSCAN0CFCC3 , &RSCAN0CFCC4 }, + { &RSCAN0CFCC6 , &RSCAN0CFCC7 }, + { &RSCAN0CFCC9 , &RSCAN0CFCC10 }, + { &RSCAN0CFCC12, &RSCAN0CFCC13 } +}; + +static __IO uint32_t *CFSTS_TBL[CAN_NUM][CAN_SND_RCV] = { + { &RSCAN0CFSTS0 , &RSCAN0CFSTS1 }, + { &RSCAN0CFSTS3 , &RSCAN0CFSTS4 }, + { &RSCAN0CFSTS6 , &RSCAN0CFSTS7 }, + { &RSCAN0CFSTS9 , &RSCAN0CFSTS10 }, + { &RSCAN0CFSTS12, &RSCAN0CFSTS13 } +}; + +static __IO uint32_t *CFPCTR_TBL[CAN_NUM][CAN_SND_RCV] = { + { &RSCAN0CFPCTR0 , &RSCAN0CFPCTR1 }, + { &RSCAN0CFPCTR3 , &RSCAN0CFPCTR4 }, + { &RSCAN0CFPCTR6 , &RSCAN0CFPCTR7 }, + { &RSCAN0CFPCTR9 , &RSCAN0CFPCTR10 }, + { &RSCAN0CFPCTR12, &RSCAN0CFPCTR13 } +}; + +static __IO uint32_t *CFID_TBL[CAN_NUM][CAN_SND_RCV] = { + { &RSCAN0CFID0 , &RSCAN0CFID1 }, + { &RSCAN0CFID3 , &RSCAN0CFID4 }, + { &RSCAN0CFID6 , &RSCAN0CFID7 }, + { &RSCAN0CFID9 , &RSCAN0CFID10 }, + { &RSCAN0CFID12, &RSCAN0CFID13 } +}; + +static __IO uint32_t *CFPTR_TBL[CAN_NUM][CAN_SND_RCV] = { + { &RSCAN0CFPTR0 , &RSCAN0CFPTR1 }, + { &RSCAN0CFPTR3 , &RSCAN0CFPTR4 }, + { &RSCAN0CFPTR6 , &RSCAN0CFPTR7 }, + { &RSCAN0CFPTR9 , &RSCAN0CFPTR10 }, + { &RSCAN0CFPTR12, &RSCAN0CFPTR13 } +}; + +static __IO uint32_t *CFDF0_TBL[CAN_NUM][CAN_SND_RCV] = { + { &RSCAN0CFDF00 , &RSCAN0CFDF01 }, + { &RSCAN0CFDF03 , &RSCAN0CFDF04 }, + { &RSCAN0CFDF06 , &RSCAN0CFDF07 }, + { &RSCAN0CFDF09 , &RSCAN0CFDF010 }, + { &RSCAN0CFDF012, &RSCAN0CFDF013 } +}; + +static __IO uint32_t *CFDF1_TBL[CAN_NUM][CAN_SND_RCV] = { + { &RSCAN0CFDF10 , &RSCAN0CFDF11 }, + { &RSCAN0CFDF13 , &RSCAN0CFDF14 }, + { &RSCAN0CFDF16 , &RSCAN0CFDF17 }, + { &RSCAN0CFDF19 , &RSCAN0CFDF110 }, + { &RSCAN0CFDF112, &RSCAN0CFDF113 } +}; + +static const can_info_int_t can_int_info[CAN_NUM][IRQ_NUM] = +{ + { /* ch0 */ + { INTRCAN0REC_IRQn, can0_rec_irq }, /* RxIrq */ + { INTRCAN0TRX_IRQn, can0_trx_irq }, /* TxIrq */ + { INTRCAN0ERR_IRQn, can0_err_warning_irq }, /* EwIrq */ + { INTRCAN0ERR_IRQn, can0_overrun_irq }, /* DoIrq */ + { INTRCAN0ERR_IRQn, NULL }, /* WuIrq(not supported) */ + { INTRCAN0ERR_IRQn, can0_passive_irq }, /* EpIrq */ + { INTRCAN0ERR_IRQn, can0_arb_lost_irq }, /* AlIrq */ + { INTRCAN0ERR_IRQn, can0_bus_err_irq } /* BeIrq */ + }, + { /* ch1 */ + { INTRCAN1REC_IRQn, can1_rec_irq }, /* RxIrq */ + { INTRCAN1TRX_IRQn, can1_trx_irq }, /* TxIrq */ + { INTRCAN1ERR_IRQn, can1_err_warning_irq }, /* EwIrq */ + { INTRCAN1ERR_IRQn, can1_overrun_irq }, /* DoIrq */ + { INTRCAN1ERR_IRQn, NULL }, /* WuIrq(not supported) */ + { INTRCAN1ERR_IRQn, can1_passive_irq }, /* EpIrq */ + { INTRCAN1ERR_IRQn, can1_arb_lost_irq }, /* AlIrq */ + { INTRCAN1ERR_IRQn, can1_bus_err_irq } /* BeIrq */ + }, + { /* ch2 */ + { INTRCAN2REC_IRQn, can2_rec_irq }, /* RxIrq */ + { INTRCAN2TRX_IRQn, can2_trx_irq }, /* TxIrq */ + { INTRCAN2ERR_IRQn, can2_err_warning_irq }, /* EwIrq */ + { INTRCAN2ERR_IRQn, can2_overrun_irq }, /* DoIrq */ + { INTRCAN2ERR_IRQn, NULL }, /* WuIrq(not supported) */ + { INTRCAN2ERR_IRQn, can2_passive_irq }, /* EpIrq */ + { INTRCAN2ERR_IRQn, can2_arb_lost_irq }, /* AlIrq */ + { INTRCAN2ERR_IRQn, can2_bus_err_irq } /* BeIrq */ + }, + { /* ch3 */ + { INTRCAN3REC_IRQn, can3_rec_irq }, /* RxIrq */ + { INTRCAN3TRX_IRQn, can3_trx_irq }, /* TxIrq */ + { INTRCAN3ERR_IRQn, can3_err_warning_irq }, /* EwIrq */ + { INTRCAN3ERR_IRQn, can3_overrun_irq }, /* DoIrq */ + { INTRCAN3ERR_IRQn, NULL }, /* WuIrq(not supported) */ + { INTRCAN3ERR_IRQn, can3_passive_irq }, /* EpIrq */ + { INTRCAN3ERR_IRQn, can3_arb_lost_irq }, /* AlIrq */ + { INTRCAN3ERR_IRQn, can3_bus_err_irq } /* BeIrq */ + }, + { /* ch4 */ + { INTRCAN4REC_IRQn, can4_rec_irq }, /* RxIrq */ + { INTRCAN4TRX_IRQn, can4_trx_irq }, /* TxIrq */ + { INTRCAN4ERR_IRQn, can4_err_warning_irq }, /* EwIrq */ + { INTRCAN4ERR_IRQn, can4_overrun_irq }, /* DoIrq */ + { INTRCAN4ERR_IRQn, NULL }, /* WuIrq(not supported) */ + { INTRCAN4ERR_IRQn, can4_passive_irq }, /* EpIrq */ + { INTRCAN4ERR_IRQn, can4_arb_lost_irq }, /* AlIrq */ + { INTRCAN4ERR_IRQn, can4_bus_err_irq } /* BeIrq */ + } +}; + +static __IO uint32_t *dmy_gaflid = &RSCAN0GAFLID0; +static __IO uint32_t *dmy_gaflm = &RSCAN0GAFLM0; +static __IO uint32_t *dmy_gaflp0 = &RSCAN0GAFLP00; +static __IO uint32_t *dmy_gaflp1 = &RSCAN0GAFLP10; + +void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) { + irq_handler = handler; + can_irq_id[obj->ch] = id; +} + +void can_irq_free(can_t *obj) { + can_irq_id[obj->ch] = 0; +} + +void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) { + __IO uint32_t *dmy_ctr; + + /* Wake-up Irq is not supported */ + if (type != IRQ_WAKEUP) { + if (enable) { + dmy_ctr = CTR_MATCH[obj->ch]; + if (type == IRQ_ERROR) { + /* EWIE interrupts is enable */ + *dmy_ctr |= 0x00000200; + } else if (type == IRQ_OVERRUN) { + /* OLIE interrupts is enable */ + *dmy_ctr |= 0x00002000; + } else if (type == IRQ_PASSIVE) { + /* EPIE interrupts is enable */ + *dmy_ctr |= 0x00000400; + } else if (type == IRQ_ARB) { + /* ALIE interrupts is enable */ + *dmy_ctr |= 0x00008000; + } else if (type == IRQ_BUS) { + /* BEIE interrupts is enable */ + *dmy_ctr |= 0x00000100; + } + InterruptHandlerRegister(can_int_info[obj->ch][type].int_num, can_int_info[obj->ch][type].handler); + GIC_SetPriority(can_int_info[obj->ch][type].int_num, 5); + GIC_EnableIRQ(can_int_info[obj->ch][type].int_num); + } else { + GIC_DisableIRQ(can_int_info[obj->ch][type].int_num); + } + } +} + +static void can_rec_irq(uint32_t ch) { + __IO uint32_t *dmy_cfsts; + + dmy_cfsts = CFSTS_TBL[ch][CAN_RECV]; + *dmy_cfsts &= 0xFFFFFFF7; // Clear CFRXIF + + irq_handler(can_irq_id[ch], IRQ_RX); +} + +static void can_trx_irq(uint32_t ch) { + __IO uint32_t *dmy_cfsts; + + dmy_cfsts = CFSTS_TBL[ch][CAN_SEND]; + *dmy_cfsts &= 0xFFFFFFEF; // Clear CFTXIF + + irq_handler(can_irq_id[ch], IRQ_TX); +} + +static void can_err_irq(uint32_t ch, CanIrqType type) { + __IO uint32_t *dmy_erfl; + int val = 1; + + dmy_erfl = ERFL_MATCH[ch]; + switch (type) { + case IRQ_ERROR: + *dmy_erfl &= 0xFFFFFFFD; // Clear EWF + break; + case IRQ_OVERRUN: + *dmy_erfl &= 0xFFFFFFDF; // Clear OVLF + break; + case IRQ_PASSIVE: + *dmy_erfl &= 0xFFFFFFFB; // Clear EPF + break; + case IRQ_ARB: + *dmy_erfl &= 0xFFFFFF7F; // Clear ALF + break; + case IRQ_BUS: + *dmy_erfl &= 0xFFFF00FF; // Clear ADERRAB0ERRAB1ERRACERRAAERRAFERRASERR + *dmy_erfl &= 0xFFFFFFFE; // Clear BEF + break; + case IRQ_WAKEUP: + /* not supported */ + /* fall through */ + default: + val = 0; + break; + } + if (val == 1) { + irq_handler(can_irq_id[ch], type); + } +} + +static void can0_rec_irq(void) { + can_rec_irq(CAN_0); +} + +static void can1_rec_irq(void) { + can_rec_irq(CAN_1); +} + +static void can2_rec_irq(void) { + can_rec_irq(CAN_2); +} + +static void can3_rec_irq(void) { + can_rec_irq(CAN_3); +} + +static void can4_rec_irq(void) { + can_rec_irq(CAN_4); +} + +static void can0_trx_irq(void) { + can_trx_irq(CAN_0); +} + +static void can1_trx_irq(void) { + can_trx_irq(CAN_1); +} + +static void can2_trx_irq(void) { + can_trx_irq(CAN_2); +} + +static void can3_trx_irq(void) { + can_trx_irq(CAN_3); +} + +static void can4_trx_irq(void) { + can_trx_irq(CAN_4); +} + +static void can0_err_warning_irq(void) { + can_err_irq(CAN_0, IRQ_ERROR); +} + +static void can1_err_warning_irq(void) { + can_err_irq(CAN_1, IRQ_ERROR); +} + +static void can2_err_warning_irq(void) { + can_err_irq(CAN_2, IRQ_ERROR); +} + +static void can3_err_warning_irq(void) { + can_err_irq(CAN_3, IRQ_ERROR); +} + +static void can4_err_warning_irq(void) { + can_err_irq(CAN_4, IRQ_ERROR); +} + +static void can0_overrun_irq(void) { + can_err_irq(CAN_0, IRQ_OVERRUN); +} + +static void can1_overrun_irq(void) { + can_err_irq(CAN_1, IRQ_OVERRUN); +} + +static void can2_overrun_irq(void) { + can_err_irq(CAN_2, IRQ_OVERRUN); +} + +static void can3_overrun_irq(void) { + can_err_irq(CAN_3, IRQ_OVERRUN); +} + +static void can4_overrun_irq(void) { + can_err_irq(CAN_4, IRQ_OVERRUN); +} + +static void can0_passive_irq(void) { + can_err_irq(CAN_0, IRQ_PASSIVE); +} + +static void can1_passive_irq(void) { + can_err_irq(CAN_1, IRQ_PASSIVE); +} + +static void can2_passive_irq(void) { + can_err_irq(CAN_2, IRQ_PASSIVE); +} + +static void can3_passive_irq(void) { + can_err_irq(CAN_3, IRQ_PASSIVE); +} + +static void can4_passive_irq(void) { + can_err_irq(CAN_4, IRQ_PASSIVE); +} + +static void can0_arb_lost_irq(void) { + can_err_irq(CAN_0, IRQ_ARB); +} + +static void can1_arb_lost_irq(void) { + can_err_irq(CAN_1, IRQ_ARB); +} + +static void can2_arb_lost_irq(void) { + can_err_irq(CAN_2, IRQ_ARB); +} + +static void can3_arb_lost_irq(void) { + can_err_irq(CAN_3, IRQ_ARB); +} + +static void can4_arb_lost_irq(void) { + can_err_irq(CAN_4, IRQ_ARB); +} + +static void can0_bus_err_irq(void) { + can_err_irq(CAN_0, IRQ_BUS); +} + +static void can1_bus_err_irq(void) { + can_err_irq(CAN_1, IRQ_BUS); +} + +static void can2_bus_err_irq(void) { + can_err_irq(CAN_2, IRQ_BUS); +} + +static void can3_bus_err_irq(void) { + can_err_irq(CAN_3, IRQ_BUS); +} + +static void can4_bus_err_irq(void) { + can_err_irq(CAN_4, IRQ_BUS); +} + +void can_init(can_t *obj, PinName rd, PinName td) { + __IO uint32_t *dmy_ctr; + + /* determine the CAN to use */ + uint32_t can_rx = pinmap_peripheral(rd, PinMap_CAN_RD); + uint32_t can_tx = pinmap_peripheral(td, PinMap_CAN_TD); + obj->ch = pinmap_merge(can_tx, can_rx); + MBED_ASSERT((int)obj->ch != NC); + + /* enable CAN clock */ + CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP32); + /* Has CAN RAM initialisation completed ? */ + while ((RSCAN0GSTS & 0x08) == 0x08) { + __NOP(); + } + /* clear Global Stop mode bit */ + RSCAN0GCTR &= 0xFFFFFFFB; + /* clear Channel Stop mode bit */ + dmy_ctr = CTR_MATCH[obj->ch]; + *dmy_ctr &= 0xFFFFFFFB; + /* Enter global reset mode */ + can_set_global_mode(GL_RESET); + /* Enter channel reset mode */ + can_set_channel_mode(obj->ch, CH_RESET); + /* reset register */ + can_reset_reg(obj); + + can_initialized[obj->ch] = 1; + /* reconfigure channel which is already initialized */ + can_reconfigure_channel(); + + /* pin out the can pins */ + pinmap_pinout(rd, PinMap_CAN_RD); + pinmap_pinout(td, PinMap_CAN_TD); +} + +void can_free(can_t *obj) { + /* disable CAN clock */ + CPGSTBCR3 |= CPG_STBCR3_BIT_MSTP32; +} + +int can_frequency(can_t *obj, int f) { + int retval = 0; + + if (f <= 1000000) { + /* less than 1Mhz */ + /* set Channel Reset mode */ + can_set_channel_mode(obj->ch, CH_RESET); + can_set_frequency(obj, f); + /* set Channel Communication mode */ + can_set_channel_mode(obj->ch, CH_COMM); + retval = 1; + } + + return retval; +} + +void can_reset(can_t *obj) { + /* Enter global reset mode */ + can_set_global_mode(GL_RESET); + /* Enter channel reset mode */ + can_set_channel_mode(obj->ch, CH_RESET); + /* reset register */ + can_reset_reg(obj); + /* reconfigure channel which is already initialized */ + can_reconfigure_channel(); +} + +int can_write(can_t *obj, CAN_Message msg, int cc) { + __IO uint32_t *dmy_sts; + __IO uint32_t *dmy_cfsts; + __IO uint32_t *dmy_cfid; + __IO uint32_t *dmy_cfptr; + __IO uint32_t *dmy_cfdf0; + __IO uint32_t *dmy_cfdf1; + __IO uint32_t *dmy_cfpctr; + int retval = 0; + + /* Wait to become channel communication mode */ + dmy_sts = STS_MATCH[obj->ch]; + while ((*dmy_sts & 0x07) != 0) { + __NOP(); + } + + if (((msg.format == CANStandard) && (msg.id <= 0x07FF)) || ((msg.format == CANExtended) && (msg.id <= 0x03FFFF))) { + /* send/receive FIFO buffer isn't full */ + dmy_cfsts = CFSTS_TBL[obj->ch][CAN_SEND]; + if ((*dmy_cfsts & 0x02) != 0x02) { + /* set format, frame type and send/receive FIFO buffer ID(b10-0 or b28-11) */ + dmy_cfid = CFID_TBL[obj->ch][CAN_SEND]; + *dmy_cfid = ((msg.format << 31) | (msg.type << 30)); + if (msg.format == CANStandard) { + *dmy_cfid |= (msg.id & 0x07FF); + } else { + *dmy_cfid |= ((msg.id & 0x03FFFF) << 11); + } + /* set length */ + dmy_cfptr = CFPTR_TBL[obj->ch][CAN_SEND]; + *dmy_cfptr = msg.len << 28; + /* set data */ + dmy_cfdf0 = CFDF0_TBL[obj->ch][CAN_SEND]; + memcpy((void *)dmy_cfdf0, &msg.data[0], 4); + dmy_cfdf1 = CFDF1_TBL[obj->ch][CAN_SEND]; + memcpy((void *)dmy_cfdf1, &msg.data[4], 4); + /* send request */ + dmy_cfpctr = CFPCTR_TBL[obj->ch][CAN_SEND]; + *dmy_cfpctr = 0xFF; + retval = 1; + } + } + + return retval; +} + +int can_read(can_t *obj, CAN_Message *msg, int handle) { + __IO uint32_t *dmy_sts; + __IO uint32_t *dmy_cfsts; + __IO uint32_t *dmy_cfid; + __IO uint32_t *dmy_cfptr; + __IO uint32_t *dmy_cfdf0; + __IO uint32_t *dmy_cfdf1; + __IO uint32_t *dmy_cfpctr; + int retval = 0; + + /* Wait to become channel communication mode */ + dmy_sts = STS_MATCH[obj->ch]; + while ((*dmy_sts & 0x07) != 0) { + __NOP(); + } + + /* send/receive FIFO buffer isn't empty */ + dmy_cfsts = CFSTS_TBL[obj->ch][CAN_RECV]; + while ((*dmy_cfsts & 0x01) != 0x01) { + /* get format, frame type and send/receive FIFO buffer ID(b10-0 or b28-11) */ + dmy_cfid = CFID_TBL[obj->ch][CAN_RECV]; + msg->format = (CANFormat)(*dmy_cfid >> 31); + msg->type = (CANType)(*dmy_cfid >> 30); + if (msg->format == CANStandard) { + msg->id = (*dmy_cfid & 0x07FF); + } else { + msg->id = ((*dmy_cfid >> 11) & 0x03FFFF); + } + /* get length */ + dmy_cfptr = CFPTR_TBL[obj->ch][CAN_RECV]; + msg->len = (unsigned char)(*dmy_cfptr >> 28); + /* get data */ + dmy_cfdf0 = CFDF0_TBL[obj->ch][CAN_RECV]; + memcpy(&msg->data[0], (void *)dmy_cfdf0, 4); + dmy_cfdf1 = CFDF1_TBL[obj->ch][CAN_RECV]; + memcpy(&msg->data[4], (void *)dmy_cfdf1, 4); + /* receive(next data) request */ + dmy_cfpctr = CFPCTR_TBL[obj->ch][CAN_RECV]; + *dmy_cfpctr = 0xFF; + retval = 1; + } + + return retval; +} + +unsigned char can_rderror(can_t *obj) { + __IO uint32_t *dmy_sts; + + dmy_sts = STS_MATCH[obj->ch]; + return (unsigned char)((*dmy_sts >> 16) & 0xFF); +} + +unsigned char can_tderror(can_t *obj) { + __IO uint32_t *dmy_sts; + + dmy_sts = STS_MATCH[obj->ch]; + return (unsigned char)((*dmy_sts >> 24) & 0xFF); +} + +int can_mode(can_t *obj, CanMode mode) { + __IO uint32_t *dmy_ctr; + __IO uint32_t *dmy_sts; + __IO uint32_t *dmy_cfcc; + int ch_cnt; + can_t *tmp_obj; + tmp_obj = obj; + int retval = 1; + + switch (mode) { + case MODE_RESET: + can_set_global_mode(GL_RESET); + can_set_channel_mode(obj->ch, CH_RESET); + for (ch_cnt = 0; ch_cnt < CAN_NUM; ch_cnt++) { + can_initialized[ch_cnt] = 0; + } + break; + case MODE_NORMAL: + can_set_global_mode(GL_OPE); + can_set_channel_mode(obj->ch, CH_COMM); + break; + case MODE_SILENT: + can_set_channel_mode(obj->ch, CH_HOLD); + /* set listen only mode, enable communication test mode */ + dmy_ctr = CTR_MATCH[obj->ch]; + *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x03000000); + can_set_channel_mode(obj->ch, CH_COMM); + break; + case MODE_TEST_LOCAL: + can_set_channel_mode(obj->ch, CH_HOLD); + /* set self test mode 0, enable communication test mode */ + dmy_ctr = CTR_MATCH[obj->ch]; + *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x05000000); + can_set_channel_mode(obj->ch, CH_COMM); + break; + case MODE_TEST_GLOBAL: + /* set the channel between the communication test on channel 1 and channel 2 */ + /* set Channel Hold mode */ + for (tmp_obj->ch = CAN_1; tmp_obj->ch <= CAN_2; tmp_obj->ch++) { + dmy_sts = STS_MATCH[tmp_obj->ch]; + if ((*dmy_sts & 0x04) == 0x04) { + /* Channel Stop mode */ + /* clear Channel Stop mode bit */ + dmy_ctr = CTR_MATCH[tmp_obj->ch]; + *dmy_ctr &= 0xFFFFFFFB; + can_set_channel_mode(tmp_obj->ch, CH_RESET); + } + can_set_channel_mode(tmp_obj->ch, CH_HOLD); + } + can_set_global_mode(GL_TEST); + /* enable communication test between channel1 and channel2 */ + RSCAN0GTSTCFG = 0x06; + RSCAN0GTSTCTR = 0x01; + /* send and receive setting of channel1 and channel2 */ + for (tmp_obj->ch = CAN_1; tmp_obj->ch <= CAN_2; tmp_obj->ch++) { + can_reset_buffer(tmp_obj); + /* set global interrrupt */ + /* THLEIE, MEIE and DEIE interrupts are disable */ + RSCAN0GCTR &= 0xFFFFF8FF; + /* BLIE, OLIE, BORIE and BOEIE interrupts are disable */ + /* TAIE, ALIE, EPIE, EWIE and BEIE interrupts are enable */ + dmy_ctr = CTR_MATCH[tmp_obj->ch]; + *dmy_ctr &= 0x00018700; + can_set_global_mode(GL_OPE); + can_set_channel_mode(tmp_obj->ch, CH_COMM); + /* Use send/receive FIFO buffer */ + dmy_cfcc = CFCC_TBL[tmp_obj->ch][CAN_SEND]; + *dmy_cfcc |= 0x01; + dmy_cfcc = CFCC_TBL[tmp_obj->ch][CAN_RECV]; + *dmy_cfcc |= 0x01; + } + break; + case MODE_TEST_SILENT: + /* not supported */ + /* fall through */ + default: + retval = 0; + break; + } + + return retval; +} + +int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) { + int retval = 0; + + if ((format == CANStandard) || (format == CANExtended)) { + if (((format == CANStandard) && (id <= 0x07FF)) || ((format == CANExtended) && (id <= 0x03FFFF))) { + /* set Global Reset mode and Channel Reset mode */ + can_set_global_mode(GL_RESET); + can_set_channel_mode(obj->ch, CH_RESET); + /* enable receive rule table writing */ + RSCAN0GAFLECTR = 0x00000100; + /* set the page number of receive rule table(page number = 0) */ + RSCAN0GAFLECTR |= (obj->ch * 4); + /* set IDE format */ + *dmy_gaflid = (format << 31); + if (format == CANExtended) { + /* set receive rule ID for bit28-11 */ + *dmy_gaflid |= (id << 11); + } else { + /* set receive rule ID for bit10-0 */ + *dmy_gaflid |= id; + } + /* set ID mask bit */ + *dmy_gaflm = (0xC0000000 | mask); + /* disable receive rule table writing */ + RSCAN0GAFLECTR &= 0xFFFFFEFF; + /* reconfigure channel which is already initialized */ + can_reconfigure_channel(); + retval = 1; + } + } + + return retval; +} + +void can_monitor(can_t *obj, int silent) { + __IO uint32_t *dmy_ctr; + + /* set Channel Hold mode */ + can_set_channel_mode(obj->ch, CH_HOLD); + if (silent) { + /* set listen only mode, enable communication test mode */ + dmy_ctr = CTR_MATCH[obj->ch]; + *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x03000000); + can_set_channel_mode(obj->ch, CH_COMM); + } else { + /* set normal test mode, disable communication test mode */ + dmy_ctr = CTR_MATCH[obj->ch]; + *dmy_ctr &= 0x00FFFFFF; + /* reset register */ + can_reset_reg(obj); + /* reconfigure channel which is already initialized */ + can_reconfigure_channel(); + } +} + +static void can_reset_reg(can_t *obj) { + __IO uint32_t *dmy_ctr; + + /* time stamp source uses peripheral clock (pclk(P1_phi)/2), CAN clock uses clkc(P1_phi/2), */ + /* mirror off, DLC not transfer, DLC check permit, transmit buffer priority, clock source not divided */ + RSCAN0GCFG = 0x00000003; + /* set default frequency at 100k */ + can_set_frequency(obj, 100000); + /* set receive rule */ + can_reset_recv_rule(obj); + /* set buffer */ + can_reset_buffer(obj); + /* set global interrrupt */ + /* THLEIE, MEIE and DEIE interrupts are disable */ + RSCAN0GCTR &= 0xFFFFF8FF; + /* ALIE, BLIE, OLIE, BORIE, BOEIE, EPIE, EWIE and BEIE interrupts are disable */ + dmy_ctr = CTR_MATCH[obj->ch]; + *dmy_ctr &= 0xFFFF00FF; +} + +static void can_reset_recv_rule(can_t *obj) { + /* number of receive rules of each chanel = 64 */ + RSCAN0GAFLCFG0 = 0x40404040; + RSCAN0GAFLCFG1 = 0x40000000; + /* enable receive rule table writing */ + RSCAN0GAFLECTR = 0x00000100; + /* set the page number of receive rule table(ex: id ch = 1, page number = 4) */ + RSCAN0GAFLECTR |= (obj->ch * 4); + /* set standard ID, data frame and receive rule ID */ + *dmy_gaflid = 0x07FF; + /* IDE bit, RTR bit and ID bit(28-0) are not compared */ + *dmy_gaflm = 0; + /* DLC check is 1 bytes, not use a receive buffer */ + *dmy_gaflp0 = 0x10000000; + /* use a send/receive FIFO buffer(ex: if ch = 1, FIFO buffer number = 4 and bit = 12) */ + *dmy_gaflp1 = (1 << ((obj->ch + 3) * 3)); + /* disable receive rule table writing */ + RSCAN0GAFLECTR &= 0xFFFFFEFF; +} + +static void can_reset_buffer(can_t *obj) { + __IO uint32_t *dmy_rfcc; + __IO uint32_t *dmy_cfcc; + __IO uint32_t *dmy_txqcc; + __IO uint32_t *dmy_thlcc; + int cnt; + + /* set linked send buffer number(ex: if ch = 1 and mode = send, buffer number = 16), interval timer is pclk/2 */ + /* number of rows of send/receive FIFO buffer = 4 */ + dmy_cfcc = CFCC_TBL[obj->ch][CAN_SEND]; + *dmy_cfcc = 0x00011100; /* send/receive FIFO mode is send */ + dmy_cfcc = CFCC_TBL[obj->ch][CAN_RECV]; + *dmy_cfcc = 0x00001100; /* send/receive FIFO mode is receive */ + /* receive buffer is not used */ + RSCAN0RMNB = 0; + /* receive FIFO buffer is not used */ + for (cnt = 0; cnt < 8; cnt++) { + dmy_rfcc = RFCC_MATCH[cnt]; + *dmy_rfcc = 0; + } + /* send queue is not used */ + dmy_txqcc = TXQCC_MATCH[obj->ch]; + *dmy_txqcc = 0; + /* send history is not used */ + dmy_thlcc = THLCC_MATCH[obj->ch]; + *dmy_thlcc = 0; + + /* CFTXIE and CFRXIE interrupts are enable */ + dmy_cfcc = CFCC_TBL[obj->ch][CAN_SEND]; + *dmy_cfcc |= 0x04; + dmy_cfcc = CFCC_TBL[obj->ch][CAN_RECV]; + *dmy_cfcc |= 0x02; + /* TMIEp interrupt is disable */ + RSCAN0TMIEC0 = 0x00000000; + RSCAN0TMIEC1 = 0x00000000; + RSCAN0TMIEC2 = 0x00000000; +} + +static void can_reconfigure_channel(void) { + __IO uint32_t *dmy_cfcc; + int ch_cnt; + + for (ch_cnt = 0; ch_cnt < CAN_NUM; ch_cnt++) { + if (can_initialized[ch_cnt] == 1) { + /* set Global Operation mode and Channel Communication mode */ + can_set_global_mode(GL_OPE); + can_set_channel_mode(ch_cnt, CH_COMM); + /* Use send/receive FIFO buffer */ + dmy_cfcc = CFCC_TBL[ch_cnt][CAN_SEND]; + *dmy_cfcc |= 0x01; + dmy_cfcc = CFCC_TBL[ch_cnt][CAN_RECV]; + *dmy_cfcc |= 0x01; + } + } +} + +static void can_set_frequency(can_t *obj, int f) { + __IO uint32_t *dmy_cfg; + int oldfreq = 0; + int newfreq = 0; + uint32_t clkc_val; + uint8_t tmp_tq; + uint8_t tq = 0; + uint8_t tmp_brp; + uint8_t brp = 0; + uint8_t tseg1 = 0; + uint8_t tseg2 = 0; + + /* set clkc */ + if (RZ_A1_IsClockMode0() == false) { + clkc_val = CM1_RENESAS_RZ_A1_P1_CLK / 2; + } else { + clkc_val = CM0_RENESAS_RZ_A1_P1_CLK / 2; + } + /* calculate BRP bit and Choose max value of calculated frequency */ + for (tmp_tq = 8; tmp_tq <= 25; tmp_tq++) { + /* f = fCAN / ((BRP+1) * Tq) */ + /* BRP = (fCAN / (f * Tq)) - 1 */ + tmp_brp = ((clkc_val / (f * tmp_tq)) - 1) + 1; // carry(decimal point is carry) + newfreq = clkc_val / ((tmp_brp + 1) * tmp_tq); + if (newfreq >= oldfreq) { + oldfreq = newfreq; + tq = tmp_tq; + brp = tmp_brp; + } + } + /* calculate TSEG1 bit and TSEG2 bit */ + tseg1 = (tq - 1) * 0.666666667; + tseg2 = (tq - 1) - tseg1; + /* set RSCAN0CmCFG register */ + dmy_cfg = CFG_MATCH[obj->ch]; + *dmy_cfg = ((tseg2 - 1) << 20) | ((tseg1 - 1) << 16) | brp; +} + +static void can_set_global_mode(int mode) { + /* set Global mode */ + RSCAN0GCTR = ((RSCAN0GCTR & 0xFFFFFFFC) | mode); + /* Wait to cahnge into Global XXXX mode */ + while ((RSCAN0GSTS & 0x07) != mode) { + __NOP(); + } +} + +static void can_set_channel_mode(uint32_t ch, int mode) { + __IO uint32_t *dmy_ctr; + __IO uint32_t *dmy_sts; + + /* set Channel mode */ + dmy_ctr = CTR_MATCH[ch]; + *dmy_ctr = ((*dmy_ctr & 0xFFFFFFFC) | mode); + /* Wait to cahnge into Channel XXXX mode */ + dmy_sts = STS_MATCH[ch]; + while ((*dmy_sts & 0x07) != mode) { + __NOP(); + } +} +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/device.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,68 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +/* ->Take measures about optimization problems of web compiler */ + /* Web compiler has problem that inlining code may not be generated correctly */ + /* when "-O3 -Otime" was specified. */ +#if defined(__CC_ARM) && (__ARMCC_VERSION <= 5040027) +#pragma Ospace +#endif +/* <-Take measures about optimization problems of web compiler */ + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 1 +#define DEVICE_SERIAL_FC 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 1 + +#define DEVICE_RTC 1 + +#define DEVICE_ETHERNET 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 32 +#define DEVICE_MAC_OFFSET 20 + +#define DEVICE_SLEEP 0 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_PATTERN 1 + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/ethernet_api.c Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,695 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include <string.h> +#include "ethernet_api.h" +#include "cmsis.h" +#include "mbed_interface.h" +#include "toolchain.h" +#include "mbed_error.h" +#include "ether_iodefine.h" +#include "ethernetext_api.h" + +/* Descriptor info */ +#define NUM_OF_TX_DESCRIPTOR (16) +#define NUM_OF_RX_DESCRIPTOR (16) +#define SIZE_OF_BUFFER (1600) /* Must be an integral multiple of 32 */ +#define MAX_SEND_SIZE (1514) +/* Ethernet Descriptor Value Define */ +#define TD0_TFP_TOP_BOTTOM (0x30000000) +#define TD0_TACT (0x80000000) +#define TD0_TDLE (0x40000000) +#define RD0_RACT (0x80000000) +#define RD0_RDLE (0x40000000) +#define RD0_RFE (0x08000000) +#define RD0_RCSE (0x04000000) +#define RD0_RFS (0x03FF0000) +#define RD0_RCS (0x0000FFFF) +#define RD0_RFS_RFOF (0x02000000) +#define RD0_RFS_RUAF (0x00400000) +#define RD0_RFS_RRF (0x00100000) +#define RD0_RFS_RTLF (0x00080000) +#define RD0_RFS_RTSF (0x00040000) +#define RD0_RFS_PRE (0x00020000) +#define RD0_RFS_CERF (0x00010000) +#define RD0_RFS_ERROR (RD0_RFS_RFOF | RD0_RFS_RUAF | RD0_RFS_RRF | RD0_RFS_RTLF | \ + RD0_RFS_RTSF | RD0_RFS_PRE | RD0_RFS_CERF) +#define RD1_RDL_MSK (0x0000FFFF) +/* PHY Register */ +#define BASIC_MODE_CONTROL_REG (0) +#define BASIC_MODE_STATUS_REG (1) +#define PHY_IDENTIFIER1_REG (2) +#define PHY_IDENTIFIER2_REG (3) +#define PHY_SP_CTL_STS_REG (31) +/* MII management interface access */ +#define PHY_ADDR (0) /* Confirm the pin connection of the PHY-LSI */ +#define PHY_ST (1) +#define PHY_WRITE (1) +#define PHY_READ (2) +#define MDC_WAIT (6) /* 400ns/4 */ +#define BASIC_STS_MSK_LINK (0x0004) /* Link Status */ +#define BASIC_STS_MSK_AUTO_CMP (0x0020) /* Auto-Negotiate Complete */ +#define M_PHY_ID (0xFFFFFFF0) +#define PHY_ID_LAN8710A (0x0007C0F0) +/* ETHERPIR0 */ +#define PIR0_MDI (0x00000008) +#define PIR0_MDO (0x00000004) +#define PIR0_MMD (0x00000002) +#define PIR0_MDC (0x00000001) +#define PIR0_MDC_HIGH (0x00000001) +#define PIR0_MDC_LOW (0x00000000) +/* ETHEREDRRR0 */ +#define EDRRR0_RR (0x00000001) +/* ETHEREDTRR0 */ +#define EDTRR0_TR (0x00000003) +/* software wait */ +#define LOOP_100us (6700) /* Loop counter for software wait 6666=100us/((1/400MHz)*6cyc) */ + +#define EDMAC_EESIPR_INI_RECV (0x0205001F) /* 0x02000000 : Detect reception suspended */ + /* 0x00040000 : Detect frame reception */ + /* 0x00010000 : Receive FIFO overflow */ + /* 0x00000010 : Residual bit frame reception */ + /* 0x00000008 : Long frame reception */ + /* 0x00000004 : Short frame reception */ + /* 0x00000002 : PHY-LSI reception error */ + /* 0x00000001 : Receive frame CRC error */ +#define EDMAC_EESIPR_INI_EtherC (0x00400000) /* 0x00400000 : E-MAC status register */ + +/* Send descriptor */ +typedef struct tag_edmac_send_desc { + uint32_t td0; + uint32_t td1; + uint8_t *td2; + uint32_t padding4; +} edmac_send_desc_t; + +/* Receive descriptor */ +typedef struct tag_edmac_recv_desc { + uint32_t rd0; + uint32_t rd1; + uint8_t *rd2; + uint32_t padding4; +} edmac_recv_desc_t; + +/* memory */ +/* The whole transmit/receive descriptors (must be allocated in 16-byte boundaries) */ +/* Transmit/receive buffers (must be allocated in 16-byte boundaries) */ +#if defined(__ICCARM__) +#pragma data_alignment=16 +static uint8_t ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) + + (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) + + (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) + + (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)] //16 bytes aligned! + @ ".mirrorram"; +#else +static uint8_t ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) + + (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) + + (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) + + (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)] + __attribute((section("NC_BSS"),aligned(16))); //16 bytes aligned! +#endif +static int32_t rx_read_offset; /* read offset */ +static int32_t tx_wite_offset; /* write offset */ +static uint32_t send_top_index; +static uint32_t recv_top_index; +static int32_t Interrupt_priority; +static edmac_send_desc_t *p_eth_desc_dsend = NULL; +static edmac_recv_desc_t *p_eth_desc_drecv = NULL; +static edmac_recv_desc_t *p_recv_end_desc = NULL; +static ethernetext_cb_fnc *p_recv_cb_fnc = NULL; +static char mac_addr[6] = {0x00, 0x02, 0xF7, 0xF0, 0x00, 0x00}; /* MAC Address */ +static uint32_t phy_id = 0; +static uint32_t start_stop = 1; /* 0:stop 1:start */ + +/* function */ +static void lan_reg_reset(void); +static void lan_desc_create(void); +static void lan_reg_set(int32_t link); +static uint16_t phy_reg_read(uint16_t reg_addr); +static void phy_reg_write(uint16_t reg_addr, uint16_t data); +static void mii_preamble(void); +static void mii_cmd(uint16_t reg_addr, uint32_t option); +static void mii_reg_read(uint16_t *data); +static void mii_reg_write(uint16_t data); +static void mii_z(void); +static void mii_write_1(void); +static void mii_write_0(void); +static void set_ether_pir(uint32_t set_data); +static void wait_100us(int32_t wait_cnt); + + +int ethernetext_init(ethernet_cfg_t *p_ethcfg) { + int32_t i; + uint16_t val; + + CPGSTBCR7 &= ~(CPG_STBCR7_BIT_MSTP74); /* enable ETHER clock */ + + /* -->4F<-- P1_14(ET_COL) */ + GPIOPMC1 |= 0x4000; + GPIOPFCAE1 &= ~0x4000; + GPIOPFCE1 |= 0x4000; + GPIOPFC1 |= 0x4000; + GPIOPIPC1 |= 0x4000; + + /* -->2F<-- P2_0(ET_TXCLK), P2_1(ET_TXER), P2_2(ET_TXEN), P2_3(ET_CRS), P2_4(ET_TXD0), + P2_5(ET_TXD1), P2_6(ET_TXD2), P2_7(ET_TXD3), P2_8(ET_RXD0), P2_9(ET_RXD1), P2_10(ET_RXD2) P2_11(ET_RXD3) */ + GPIOPMC2 |= 0x0FFF; + GPIOPFCAE2 &= ~0x0FFF; + GPIOPFCE2 &= ~0x0FFF; + GPIOPFC2 |= 0x0FFF; + GPIOPIPC2 |= 0x0FFF; + + /* -->3F<-- P3_3(ET_MDIO), P3_4(ET_RXCLK), P3_5(ET_RXER), P3_6(ET_RXDV) */ + GPIOPMC3 |= 0x0078; + GPIOPFCAE3 &= ~0x0078; + GPIOPFCE3 &= ~0x0078; + GPIOPFC3 |= 0x0078; + GPIOPIPC3 |= 0x0078; + + /* -->3F<-- P7_0(ET_MDC) */ + GPIOPMC7 |= 0x0001; + GPIOPFCAE7 &= ~0x0001; + GPIOPFCE7 |= 0x0001; + GPIOPFC7 &= ~0x0001; + GPIOPIPC7 |= 0x0001; + + /* Resets the E-MAC,E-DMAC */ + lan_reg_reset(); + + /* Resets the PHY-LSI */ + phy_reg_write(BASIC_MODE_CONTROL_REG, 0x8000); + for (i = 10000; i > 0; i--) { + val = phy_reg_read(BASIC_MODE_CONTROL_REG); + if (((uint32_t)val & 0x8000uL) == 0) { + break; /* Reset complete */ + } + } + + phy_id = ((uint32_t)phy_reg_read(PHY_IDENTIFIER1_REG) << 16) + | (uint32_t)phy_reg_read(PHY_IDENTIFIER2_REG); + + Interrupt_priority = p_ethcfg->int_priority; + p_recv_cb_fnc = p_ethcfg->recv_cb; + start_stop = 1; + + if (p_ethcfg->ether_mac != NULL) { + (void)memcpy(mac_addr, p_ethcfg->ether_mac, sizeof(mac_addr)); + } else { + ethernet_address(mac_addr); /* Get MAC Address */ + } + + return 0; +} + +void ethernetext_start_stop(int32_t mode) { + if (mode == 1) { + /* start */ + ETHEREDTRR0 |= EDTRR0_TR; + ETHEREDRRR0 |= EDRRR0_RR; + start_stop = 1; + } else { + /* stop */ + ETHEREDTRR0 &= ~EDTRR0_TR; + ETHEREDRRR0 &= ~EDRRR0_RR; + start_stop = 0; + } +} + +int ethernetext_chk_link_mode(void) { + int32_t link; + uint16_t data; + + if ((phy_id & M_PHY_ID) == PHY_ID_LAN8710A) { + data = phy_reg_read(PHY_SP_CTL_STS_REG); + switch (((uint32_t)data >> 2) & 0x00000007) { + case 0x0001: + link = HALF_10M; + break; + case 0x0005: + link = FULL_10M; + break; + case 0x0002: + link = HALF_TX; + break; + case 0x0006: + link = FULL_TX; + break; + default: + link = NEGO_FAIL; + break; + } + } else { + link = NEGO_FAIL; + } + + return link; +} + +void ethernetext_set_link_mode(int32_t link) { + lan_reg_reset(); /* Resets the E-MAC,E-DMAC */ + lan_desc_create(); /* Initialize of buffer memory */ + lan_reg_set(link); /* E-DMAC, E-MAC initialization */ +} + +int ethernet_init() { + ethernet_cfg_t ethcfg; + + ethcfg.int_priority = 5; + ethcfg.recv_cb = NULL; + ethcfg.ether_mac = NULL; + ethernetext_init(ðcfg); + ethernet_set_link(-1, 0); /* Auto-Negotiation */ + + return 0; +} + +void ethernet_free() { + ETHERARSTR |= 0x00000001; /* ETHER software reset */ + CPGSTBCR7 |= CPG_STBCR7_BIT_MSTP74; /* disable ETHER clock */ +} + +int ethernet_write(const char *data, int slen) { + edmac_send_desc_t *p_send_desc; + int32_t copy_size; + + if ((p_eth_desc_dsend == NULL) || (data == NULL) || (slen < 0) + || (tx_wite_offset < 0) || (tx_wite_offset >= MAX_SEND_SIZE)) { + copy_size = 0; + } else { + p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */ + if ((p_send_desc->td0 & TD0_TACT) != 0) { + copy_size = 0; + } else { + copy_size = MAX_SEND_SIZE - tx_wite_offset; + if (copy_size > slen) { + copy_size = slen; + } + (void)memcpy(&p_send_desc->td2[tx_wite_offset], data, copy_size); + tx_wite_offset += copy_size; + } + } + + return copy_size; +} + +int ethernet_send() { + edmac_send_desc_t *p_send_desc; + int32_t ret; + + if ((p_eth_desc_dsend == NULL) || (tx_wite_offset <= 0)) { + ret = 0; + } else { + /* Transfer 1 frame */ + p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */ + + /* Sets the frame length */ + p_send_desc->td1 = ((uint32_t)tx_wite_offset << 16); + tx_wite_offset = 0; + + /* Sets the transmit descriptor to transmit again */ + p_send_desc->td0 &= (TD0_TACT | TD0_TDLE | TD0_TFP_TOP_BOTTOM); + p_send_desc->td0 |= TD0_TACT; + if ((start_stop == 1) && ((ETHEREDTRR0 & EDTRR0_TR) != EDTRR0_TR)) { + ETHEREDTRR0 |= EDTRR0_TR; + } + + /* Update the current descriptor */ + send_top_index++; + if (send_top_index >= NUM_OF_TX_DESCRIPTOR) { + send_top_index = 0; + } + ret = 1; + } + + return ret; +} + +int ethernet_receive() { + edmac_recv_desc_t *p_recv_desc; + int32_t receive_size = 0; + + if (p_eth_desc_drecv != NULL) { + if (p_recv_end_desc != NULL) { + /* Sets the receive descriptor to receive again */ + p_recv_end_desc->rd0 &= (RD0_RACT | RD0_RDLE); + p_recv_end_desc->rd0 |= RD0_RACT; + if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) { + ETHEREDRRR0 |= EDRRR0_RR; + } + p_recv_end_desc = NULL; + } + + p_recv_desc = &p_eth_desc_drecv[recv_top_index]; /* Current descriptor */ + if ((p_recv_desc->rd0 & RD0_RACT) == 0) { + /* Receives 1 frame */ + if (((p_recv_desc->rd0 & RD0_RFE) != 0) && ((p_recv_desc->rd0 & RD0_RFS_ERROR) != 0)) { + /* Receive frame error */ + /* Sets the receive descriptor to receive again */ + p_recv_desc->rd0 &= (RD0_RACT | RD0_RDLE); + p_recv_desc->rd0 |= RD0_RACT; + if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) { + ETHEREDRRR0 |= EDRRR0_RR; + } + } else { + /* Copies the received frame */ + rx_read_offset = 0; + p_recv_end_desc = p_recv_desc; + receive_size = (p_recv_desc->rd1 & RD1_RDL_MSK); /* number of bytes received */ + } + + /* Update the current descriptor */ + recv_top_index++; + if (recv_top_index >= NUM_OF_TX_DESCRIPTOR) { + recv_top_index = 0; + } + } + } + + return receive_size; +} + +int ethernet_read(char *data, int dlen) { + edmac_recv_desc_t *p_recv_desc = p_recv_end_desc; /* Read top descriptor */ + int32_t copy_size; + + if ((data == NULL) || (dlen < 0) || (p_recv_desc == NULL)) { + copy_size = 0; + } else { + copy_size = (p_recv_desc->rd1 & RD1_RDL_MSK) - rx_read_offset; + if (copy_size > dlen) { + copy_size = dlen; + } + (void)memcpy(data, &p_recv_desc->rd2[rx_read_offset], (size_t)copy_size); + rx_read_offset += copy_size; + } + + return copy_size; +} + +void ethernet_address(char *mac) { + if (mac != NULL) { + mbed_mac_address(mac); /* Get MAC Address */ + } +} + +int ethernet_link(void) { + int32_t ret; + uint16_t data; + + data = phy_reg_read(BASIC_MODE_STATUS_REG); + if (((uint32_t)data & BASIC_STS_MSK_LINK) != 0) { + ret = 1; + } else { + ret = 0; + } + + return ret; +} + +void ethernet_set_link(int speed, int duplex) { + uint16_t data; + int32_t i; + int32_t link; + + if ((speed < 0) || (speed > 1)) { + data = 0x1000; /* Auto-Negotiation Enable */ + phy_reg_write(BASIC_MODE_CONTROL_REG, data); + for (i = 0; i < 1000; i++) { + data = phy_reg_read(BASIC_MODE_STATUS_REG); + if (((uint32_t)data & BASIC_STS_MSK_AUTO_CMP) != 0) { + break; + } + wait_100us(10); + } + } else { + data = (uint16_t)(((uint32_t)speed << 13) | ((uint32_t)duplex << 8)); + phy_reg_write(BASIC_MODE_CONTROL_REG, data); + wait_100us(1); + } + + link = ethernetext_chk_link_mode(); + ethernetext_set_link_mode(link); +} + +void INT_Ether(void) { + uint32_t stat_edmac; + uint32_t stat_etherc; + + /* Clear the interrupt request flag */ + stat_edmac = (ETHEREESR0 & ETHEREESIPR0); /* Targets are restricted to allowed interrupts */ + ETHEREESR0 = stat_edmac; + /* Reception-related */ + if (stat_edmac & EDMAC_EESIPR_INI_RECV) { + if (p_recv_cb_fnc != NULL) { + p_recv_cb_fnc(); + } + } + /* E-MAC-related */ + if (stat_edmac & EDMAC_EESIPR_INI_EtherC) { + /* Clear the interrupt request flag */ + stat_etherc = (ETHERECSR0 & ETHERECSIPR0); /* Targets are restricted to allowed interrupts */ + ETHERECSR0 = stat_etherc; + } +} + +static void lan_reg_reset(void) { + volatile int32_t j = 400; /* Wait for B dia 256 cycles ((I dia/B dia)*256)/6cyc = 8*256/6 = 342 */ + + ETHERARSTR |= 0x00000001; /* ETHER software reset */ + while (j--) { + /* Do Nothing */ + } + + ETHEREDSR0 |= 0x00000003; /* E-DMAC software reset */ + ETHEREDMR0 |= 0x00000003; /* Set SWRR and SWRT simultaneously */ + + /* Check clear software reset */ + while ((ETHEREDMR0 & 0x00000003) != 0) { + /* Do Nothing */ + } +} + +static void lan_desc_create(void) { + int32_t i; + uint8_t *p_memory_top; + + (void)memset((void *)ethernet_nc_memory, 0, sizeof(ethernet_nc_memory)); + p_memory_top = ethernet_nc_memory; + + /* Descriptor area configuration */ + p_eth_desc_dsend = (edmac_send_desc_t *)p_memory_top; + p_memory_top += (sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR); + p_eth_desc_drecv = (edmac_recv_desc_t *)p_memory_top; + p_memory_top += (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR); + + /* Transmit descriptor */ + for (i = 0; i < NUM_OF_TX_DESCRIPTOR; i++) { + p_eth_desc_dsend[i].td2 = p_memory_top; /* TD2 TBA */ + p_memory_top += SIZE_OF_BUFFER; + p_eth_desc_dsend[i].td1 = 0; /* TD1 TDL */ + p_eth_desc_dsend[i].td0 = TD0_TFP_TOP_BOTTOM; /* TD0:1frame/1buf1buf, transmission disabled */ + } + p_eth_desc_dsend[i - 1].td0 |= TD0_TDLE; /* Set the last descriptor */ + + /* Receive descriptor */ + for (i = 0; i < NUM_OF_RX_DESCRIPTOR; i++) { + p_eth_desc_drecv[i].rd2 = p_memory_top; /* RD2 RBA */ + p_memory_top += SIZE_OF_BUFFER; + p_eth_desc_drecv[i].rd1 = ((uint32_t)SIZE_OF_BUFFER << 16); /* RD1 RBL */ + p_eth_desc_drecv[i].rd0 = RD0_RACT; /* RD0:reception enabled */ + } + p_eth_desc_drecv[i - 1].rd0 |= RD0_RDLE; /* Set the last descriptor */ + + /* Initialize descriptor management information */ + send_top_index = 0; + recv_top_index = 0; + rx_read_offset = 0; + tx_wite_offset = 0; + p_recv_end_desc = NULL; +} + +static void lan_reg_set(int32_t link) { + /* MAC address setting */ + ETHERMAHR0 = ((uint32_t)mac_addr[0] << 24) + | ((uint32_t)mac_addr[1] << 16) + | ((uint32_t)mac_addr[2] << 8) + | (uint32_t)mac_addr[3]; + ETHERMALR0 = ((uint32_t)mac_addr[4] << 8) + | (uint32_t)mac_addr[5]; + + /* E-DMAC */ + ETHERTDLAR0 = (uint32_t)&p_eth_desc_dsend[0]; + ETHERRDLAR0 = (uint32_t)&p_eth_desc_drecv[0]; + ETHERTDFAR0 = (uint32_t)&p_eth_desc_dsend[0]; + ETHERRDFAR0 = (uint32_t)&p_eth_desc_drecv[0]; + ETHERTDFXR0 = (uint32_t)&p_eth_desc_dsend[NUM_OF_TX_DESCRIPTOR - 1]; + ETHERRDFXR0 = (uint32_t)&p_eth_desc_drecv[NUM_OF_RX_DESCRIPTOR - 1]; + ETHERTDFFR0 |= 0x00000001; /* TDLF Transmit Descriptor Queue Last Flag : Last descriptor (1) */ + ETHERRDFFR0 |= 0x00000001; /* RDLF Receive Descriptor Queue Last Flag : Last descriptor (1) */ + ETHEREDMR0 |= 0x00000040; /* Little endian */ + ETHERTRSCER0 &= ~0x0003009F; /* All clear */ + ETHERTFTR0 &= ~0x000007FF; /* TFT[10:0] Transmit FIFO Threshold : Store and forward modes (H'000) */ + ETHERFDR0 |= 0x00000707; /* Transmit FIFO Size:2048 bytes, Receive FIFO Size:2048 bytes */ + ETHERRMCR0 |= 0x00000001; /* RNC Receive Enable Control : Continuous reception enabled (1) */ + ETHERFCFTR0 &= ~0x001F00FF; + ETHERFCFTR0 |= 0x00070007; + ETHERRPADIR0 &= ~0x001FFFFF; /* Padding Size:No padding insertion, Padding Slot:Inserts at first byte */ + + /* E-MAC */ + ETHERECMR0 &= ~0x04BF2063; /* All clear */ + ETHERRFLR0 &= ~0x0003FFFF; /* RFL[17:0] Receive Frame Length : 1518 bytes (H'00000) */ + ETHERAPR0 &= ~0x0000FFFF; /* AP[15:0] Automatic PAUSE : Flow control is disabled (H'0000) */ + ETHERMPR0 &= ~0x0000FFFF; /* MP[15:0] Manual PAUSE : Flow control is disabled (H'0000) */ + ETHERTPAUSER0 &= ~0x0000FFFF; /* Upper Limit for Automatic PAUSE Frame : Retransmit count is unlimited */ + ETHERCSMR &= ~0xC000003F; /* The result of checksum is not written back to the receive descriptor */ + if ((link == FULL_TX) || (link == FULL_10M) || (link == NEGO_FAIL)) { + ETHERECMR0 |= 0x00000002; /* Set to full-duplex mode */ + } else { + ETHERECMR0 &= ~0x00000002; /* Set to half-duplex mode */ + } + + /* Interrupt-related */ + if (p_recv_cb_fnc != NULL) { + ETHEREESR0 |= 0xFF7F009F; /* Clear all status (by writing 1) */ + ETHEREESIPR0 |= 0x00040000; /* FR Frame Reception (1) */ + ETHERECSR0 |= 0x00000011; /* Clear all status (clear by writing 1) */ + ETHERECSIPR0 &= ~0x00000011; /* PFROIP Disable, ICDIP Disable */ + InterruptHandlerRegister(ETHERI_IRQn, INT_Ether); /* Ethernet interrupt handler registration */ + GIC_SetPriority(ETHERI_IRQn, Interrupt_priority); /* Ethernet interrupt priority */ + GIC_EnableIRQ(ETHERI_IRQn); /* Enables the E-DMAC interrupt */ + } + + ETHERECMR0 |= 0x00000060; /* RE Enable, TE Enable */ + + /* Enable transmission/reception */ + if ((start_stop == 1) && ((ETHEREDRRR0 & 0x00000001) == 0)) { + ETHEREDRRR0 |= 0x00000001; /* RR */ + } +} + +static uint16_t phy_reg_read(uint16_t reg_addr) { + uint16_t data; + + mii_preamble(); + mii_cmd(reg_addr, PHY_READ); + mii_z(); + mii_reg_read(&data); + mii_z(); + + return data; +} + +static void phy_reg_write(uint16_t reg_addr, uint16_t data) { + mii_preamble(); + mii_cmd(reg_addr, PHY_WRITE); + mii_write_1(); + mii_write_0(); + mii_reg_write(data); + mii_z(); +} + +static void mii_preamble(void) { + int32_t i = 32; + + for (i = 32; i > 0; i--) { + /* 1 is output via the MII (Media Independent Interface) block. */ + mii_write_1(); + } +} + +static void mii_cmd(uint16_t reg_addr, uint32_t option) { + int32_t i; + uint16_t data = 0; + + data |= (PHY_ST << 14); /* ST code */ + data |= (option << 12); /* OP code */ + data |= (PHY_ADDR << 7); /* PHY Address */ + data |= (uint16_t)(reg_addr << 2); /* Reg Address */ + for (i = 14; i > 0; i--) { + if ((data & 0x8000) == 0) { + mii_write_0(); + } else { + mii_write_1(); + } + data <<= 1; + } +} + +static void mii_reg_read(uint16_t *data) { + int32_t i; + uint16_t reg_data = 0; + + /* Data are read in one bit at a time */ + for (i = 16; i > 0; i--) { + set_ether_pir(PIR0_MDC_LOW); + set_ether_pir(PIR0_MDC_HIGH); + reg_data <<= 1; + reg_data |= (uint16_t)((ETHERPIR0 & PIR0_MDI) >> 3); /* MDI read */ + set_ether_pir(PIR0_MDC_HIGH); + set_ether_pir(PIR0_MDC_LOW); + } + *data = reg_data; +} + +static void mii_reg_write(uint16_t data) { + int32_t i; + + /* Data are written one bit at a time */ + for (i = 16; i > 0; i--) { + if ((data & 0x8000) == 0) { + mii_write_0(); + } else { + mii_write_1(); + } + data <<= 1; + } +} + +static void mii_z(void) { + set_ether_pir(PIR0_MDC_LOW); + set_ether_pir(PIR0_MDC_HIGH); + set_ether_pir(PIR0_MDC_HIGH); + set_ether_pir(PIR0_MDC_LOW); +} + +static void mii_write_1(void) { + set_ether_pir(PIR0_MDO | PIR0_MMD); + set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC); + set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC); + set_ether_pir(PIR0_MDO | PIR0_MMD); +} + +static void mii_write_0(void) { + set_ether_pir(PIR0_MMD); + set_ether_pir(PIR0_MMD | PIR0_MDC); + set_ether_pir(PIR0_MMD | PIR0_MDC); + set_ether_pir(PIR0_MMD); +} + +static void set_ether_pir(uint32_t set_data) { + int32_t i; + + for (i = MDC_WAIT; i > 0; i--) { + ETHERPIR0 = set_data; + } +} + +static void wait_100us(int32_t wait_cnt) { + volatile int32_t j = LOOP_100us * wait_cnt; + + while (--j) { + /* Do Nothing */ + } +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/ethernetext_api.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,20 @@ + +/* PHY link mode */ +#define NEGO_FAIL (0) +#define HALF_10M (1) +#define FULL_10M (2) +#define HALF_TX (3) +#define FULL_TX (4) + +typedef void (ethernetext_cb_fnc)(void); + +typedef struct tag_ethernet_cfg { + int int_priority; + ethernetext_cb_fnc *recv_cb; + char *ether_mac; +} ethernet_cfg_t; + +extern int ethernetext_init(ethernet_cfg_t *p_ethcfg); +extern void ethernetext_start_stop(int32_t mode); +extern int ethernetext_chk_link_mode(void); +extern void ethernetext_set_link_mode(int32_t link);
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_addrdefine.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,22 @@ +#ifndef __GPIO_ADDRDEFINE__ +#define __GPIO_ADDRDEFINE__ + +#define GPIO_BASE ((long)0xFCFE3000uL) /* GPIO */ + +#define PORT(n) (volatile unsigned short *)(GPIO_BASE + 0x000 + ((n)*4)) +#define PSR(n) (volatile unsigned long *)(GPIO_BASE + 0x100 + ((n)*4)) +#define PPR(n) (volatile unsigned short *)(GPIO_BASE + 0x200 + ((n)*4)) +#define PM(n) (volatile unsigned short *)(GPIO_BASE + 0x300 + ((n)*4)) +#define PMC(n) (volatile unsigned short *)(GPIO_BASE + 0x400 + ((n)*4)) +#define PFC(n) (volatile unsigned short *)(GPIO_BASE + 0x500 + ((n)*4)) +#define PFCE(n) (volatile unsigned short *)(GPIO_BASE + 0x600 + ((n)*4)) +#define PNOT(n) (volatile unsigned short *)(GPIO_BASE + 0x700 + ((n)*4)) +#define PMSR(n) (volatile unsigned long *)(GPIO_BASE + 0x800 + ((n)*4)) +#define PMCSR(n) (volatile unsigned long *)(GPIO_BASE + 0x900 + ((n)*4)) +#define PFCAE(n) (volatile unsigned short *)(GPIO_BASE + 0xa00 + ((n)*4)) +#define PIBC(n) (volatile unsigned short *)(GPIO_BASE + 0x4000 +((n)*4)) +#define PBDC(n) (volatile unsigned short *)(GPIO_BASE + 0x4100 +((n)*4)) +#define PIPC(n) (volatile unsigned short *)(GPIO_BASE + 0x4200 +((n)*4)) + +#endif/*__GPIO_ADDRDEFINE__*/ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_api.c Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,57 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" +#include "pinmap.h" +#include "gpio_addrdefine.h" + + +uint32_t gpio_set(PinName pin) { + pin_function(pin, 0); + return (1 << PINNO(pin)); +} + +void gpio_init(gpio_t *obj, PinName pin) { + int group ; + obj->pin = pin; + if(pin == NC) return; + + obj->mask = gpio_set(pin); + + group = PINGROUP(pin); + if (group > 9) return; + + obj->reg_set = (volatile uint32_t *) PSR(group); + obj->reg_in = (volatile uint32_t *) PPR(group); + obj->reg_dir = (volatile uint32_t *)PMSR(group); + obj->reg_buf = (volatile uint32_t *)PIBC(group); +} + +void gpio_mode(gpio_t *obj, PinMode mode) { +/* Pull up and Pull down settings aren't supported because RZ/A1H doesn't have pull up/down for pins(signals). */ +} + +void gpio_dir(gpio_t *obj, PinDirection direction) { + switch (direction) { + case PIN_INPUT : + *obj->reg_dir = (obj->mask << 16) | obj->mask; + *obj->reg_buf |= obj->mask; + break; + case PIN_OUTPUT: + *obj->reg_dir = (obj->mask << 16) | 0; + *obj->reg_buf &= ~obj->mask; + break; + } +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_irq_api.c Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,222 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include <stddef.h> + +#include "gpio_irq_api.h" +#include "intc_iodefine.h" +#include "pinmap.h" +#include "cmsis.h" +#include "gpio_addrdefine.h" + +#define CHANNEL_NUM 8 + +static void gpio_irq0(void); +static void gpio_irq1(void); +static void gpio_irq2(void); +static void gpio_irq3(void); +static void gpio_irq4(void); +static void gpio_irq5(void); +static void gpio_irq6(void); +static void gpio_irq7(void); + +static gpio_irq_t *channel_obj[CHANNEL_NUM] = {NULL}; +static gpio_irq_handler irq_handler; +static const int nIRQn_h = 32; +extern PinName gpio_multi_guard; + +enum { + IRQ0,IRQ1, + IRQ2,IRQ3, + IRQ4,IRQ5, + IRQ6,IRQ7, + +} IRQNo; + +static const IRQHandler irq_tbl[CHANNEL_NUM] = { + &gpio_irq0, + &gpio_irq1, + &gpio_irq2, + &gpio_irq3, + &gpio_irq4, + &gpio_irq5, + &gpio_irq6, + &gpio_irq7, +}; + +#ifdef MAX_PERI +static const PinMap PinMap_IRQ[] = { + {P1_0, IRQ0, 4}, {P4_8, IRQ0, 8}, {P6_8, IRQ0, 8}, {P7_9, IRQ0, 8}, {P8_2, IRQ0, 5}, {P2_14, IRQ0, 8}, {P5_8, IRQ0, 2}, {P9_1, IRQ0, 4}, + {P1_1, IRQ1, 4}, {P4_9, IRQ1, 8}, {P6_9, IRQ1, 8}, {P7_8, IRQ1, 8}, {P8_3, IRQ1, 6}, {P2_15, IRQ1, 8}, + {P1_2, IRQ2, 4}, {P4_10, IRQ2, 8}, {P6_10, IRQ2, 8}, {P7_10, IRQ2, 8}, {P1_8, IRQ2, 3}, {P3_0, IRQ2, 3}, {P5_9, IRQ2, 4}, {P6_3, IRQ2, 4}, + {P1_3, IRQ3, 4}, {P4_11, IRQ3, 8}, {P6_11, IRQ3, 8}, {P7_11, IRQ3, 8}, {P1_9, IRQ3, 3}, {P6_4, IRQ3, 4}, + {P1_4, IRQ4, 4}, {P4_12, IRQ4, 8}, {P6_12, IRQ4, 8}, {P7_12, IRQ4, 8}, {P1_10, IRQ4, 3}, {P3_3, IRQ4, 3}, {P6_1, IRQ4, 4}, + {P1_5, IRQ5, 4}, {P4_13, IRQ5, 8}, {P6_13, IRQ5, 8}, {P7_13, IRQ5, 8}, {P1_11, IRQ5, 3}, {P2_0, IRQ5, 6}, {P6_0, IRQ5, 6}, {P8_7, IRQ5, 4}, + {P1_6, IRQ6, 4}, {P4_14, IRQ6, 8}, {P6_14, IRQ6, 8}, {P7_14, IRQ6, 8}, {P2_12, IRQ6, 6}, {P3_1, IRQ6, 3}, {P3_9, IRQ6, 8}, {P5_6, IRQ6, 6}, + {P1_7, IRQ7, 4}, {P4_15, IRQ7, 8}, {P6_15, IRQ7, 8}, {P6_2, IRQ7, 4}, {P2_13, IRQ7, 8}, + {NC, NC, 0} +}; +#else +static const PinMap PinMap_IRQ[] = { + {P9_1, IRQ0, 4}, + {P1_2, IRQ2, 4}, {P1_8, IRQ2, 3}, {P3_0, IRQ2, 3}, {P5_9, IRQ2, 4}, + {P1_3, IRQ3, 4}, {P1_9, IRQ3, 3}, + {P1_4, IRQ4, 4}, {P1_10, IRQ4, 3}, + {P1_5, IRQ5, 4}, {P1_11, IRQ5, 3}, + {P3_1, IRQ6, 3}, {P3_9, IRQ6, 8}, {P5_6, IRQ6, 6}, + {NC, NC, 0} +}; +#endif + +static void handle_interrupt_in(int irq_num) { + uint16_t irqs; + uint16_t edge_req; + gpio_irq_t *obj; + gpio_irq_event irq_event; + + irqs = INTCIRQRR; + if (irqs & (1 << irq_num)) { + obj = channel_obj[irq_num]; + if (obj != NULL) { + edge_req = ((INTCICR1 >> (obj->ch * 2)) & 3); + if (edge_req == 1) { + irq_event = IRQ_FALL; + } else if (edge_req == 2) { + irq_event = IRQ_RISE; + } else { + uint32_t mask = (1 << (obj->pin & 0x0F)); + __I uint32_t *reg_in = (volatile uint32_t *) PPR((int)PINGROUP(obj->pin)); + + if ((*reg_in & mask) == 0) { + irq_event = IRQ_FALL; + } else { + irq_event = IRQ_RISE; + } + } + irq_handler(obj->port, irq_event); + } + INTCIRQRR &= ~(1 << irq_num); + } +} + +static void gpio_irq0(void) { + handle_interrupt_in(0); +} + +static void gpio_irq1(void) { + handle_interrupt_in(1); +} + +static void gpio_irq2(void) { + handle_interrupt_in(2); +} + +static void gpio_irq3(void) { + handle_interrupt_in(3); +} + +static void gpio_irq4(void) { + handle_interrupt_in(4); +} + +static void gpio_irq5(void) { + handle_interrupt_in(5); +} + +static void gpio_irq6(void) { + handle_interrupt_in(6); +} + +static void gpio_irq7(void) { + handle_interrupt_in(7); +} + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { + int shift; + if (pin == NC) return -1; + + obj->ch = pinmap_peripheral(pin, PinMap_IRQ); + obj->pin = (int)pin ; + obj->port = (int)id ; + + shift = obj->ch*2; + channel_obj[obj->ch] = obj; + irq_handler = handler; + + pinmap_pinout(pin, PinMap_IRQ); + gpio_multi_guard = pin; /* Set multi guard */ + + // INTC settings + InterruptHandlerRegister((IRQn_Type)(nIRQn_h+obj->ch), (void (*)(uint32_t))irq_tbl[obj->ch]); + INTCICR1 &= ~(0x3 << shift); + INTCICR1 |= (0x3 << shift); + GIC_SetPriority((IRQn_Type)(nIRQn_h+obj->ch), 5); + GIC_EnableIRQ((IRQn_Type)(nIRQn_h+obj->ch)); + obj->int_enable = 1; + __enable_irq(); + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) { + channel_obj[obj->ch] = NULL; +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { + int shift = obj->ch*2; + uint16_t val = event == IRQ_RISE ? 2 : + event == IRQ_FALL ? 1 : 0; + uint16_t work_icr_val; + + /* check edge interrupt setting */ + work_icr_val = INTCICR1; + if (enable == 1) { + /* Set interrupt serect */ + work_icr_val |= (val << shift); + } else { + /* Clear interrupt serect */ + work_icr_val &= ~(val << shift); + } + + if ((work_icr_val & (3 << shift)) == 0) { + /* No edge interrupt setting */ + GIC_DisableIRQ((IRQn_Type)(nIRQn_h+obj->ch)); + /* Clear Interrupt flags */ + INTCIRQRR &= ~(1 << obj->ch); + INTCICR1 = work_icr_val; + } else if (obj->int_enable == 1) { + INTCICR1 = work_icr_val; + GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch)); + } else { + INTCICR1 = work_icr_val; + } +} + +void gpio_irq_enable(gpio_irq_t *obj) { + int shift = obj->ch*2; + uint16_t work_icr_val = INTCICR1; + + /* check edge interrupt setting */ + if ((work_icr_val & (3 << shift)) != 0) { + GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch)); + } + obj->int_enable = 1; +} + +void gpio_irq_disable(gpio_irq_t *obj) { + GIC_DisableIRQ((IRQn_Type)(nIRQn_h + obj->ch)); + obj->int_enable = 0; +} +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_object.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,51 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "mbed_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName pin; + uint32_t mask; + + __IO uint32_t *reg_dir; + __IO uint32_t *reg_set; + __I uint32_t *reg_in; + __IO uint32_t *reg_buf; +} gpio_t; + +static inline void gpio_write(gpio_t *obj, int value) { + *obj->reg_set = (obj->mask << 16) | ((value != 0) ? obj->mask : 0); +} + +static inline int gpio_read(gpio_t *obj) { + return ((*obj->reg_in & obj->mask) ? 1 : 0); +} + +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + +#ifdef __cplusplus +} +#endif + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/i2c_api.c Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,753 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "i2c_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "r_typedefs.h" + +#include "riic_iodefine.h" +#include "RZ_A1_Init.h" +#include "VKRZA1H.h" + +volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST; + +#define REG(N) \ + RIIC[obj->i2c]->RIICn##N + +/* RIICnCR1 */ +#define CR1_RST (1 << 6) +#define CR1_ICE (1 << 7) + +/* RIICnCR2 */ +#define CR2_ST (1 << 1) +#define CR2_RS (1 << 2) +#define CR2_SP (1 << 3) +#define CR2_TRS (1 << 5) +#define CR2_BBSY (1 << 7) + +/* RIICnMR3 */ +#define MR3_ACKBT (1 << 3) +#define MR3_ACKWP (1 << 4) +#define MR3_WAIT (1 << 6) + +/* RIICnSER */ +#define SER_SAR0E (1 << 0) + +/* RIICnSR1 */ +#define SR1_AAS0 (1 << 0) + +/* RIICnSR2 */ +#define SR2_START (1 << 2) +#define SR2_STOP (1 << 3) +#define SR2_NACKF (1 << 4) +#define SR2_RDRF (1 << 5) +#define SR2_TEND (1 << 6) +#define SR2_TDRE (1 << 7) + +#define WAIT_TIMEOUT (3600000) /* Loop counter : Time-out is about 1s. By 3600000 loops, measured value is 969ms. */ + +static const PinMap PinMap_I2C_SDA[] = { + {P1_1 , I2C_0, 1}, + {P1_3 , I2C_1, 1}, + {P1_5 , I2C_2, 1}, + {P1_7 , I2C_3, 1}, + {NC , NC , 0} +}; + +static const PinMap PinMap_I2C_SCL[] = { + {P1_0 , I2C_0, 1}, + {P1_2 , I2C_1, 1}, + {P1_4 , I2C_2, 1}, + {P1_6 , I2C_3, 1}, + {NC , NC, 0} +}; + + +static inline int i2c_status(i2c_t *obj) { + return REG(SR2.UINT8[0]); +} + +static void i2c_reg_reset(i2c_t *obj) { + /* full reset */ + REG(CR1.UINT8[0]) &= ~CR1_ICE; // CR1.ICE off + REG(CR1.UINT8[0]) |= CR1_RST; // CR1.IICRST on + REG(CR1.UINT8[0]) |= CR1_ICE; // CR1.ICE on + + REG(MR1.UINT8[0]) = 0x08; // P_phi /x 9bit (including Ack) + REG(SER.UINT8[0]) = 0x00; // no slave addr enabled + + /* set frequency */ + REG(MR1.UINT8[0]) |= obj->pclk_bit; + REG(BRL.UINT8[0]) = obj->width_low; + REG(BRH.UINT8[0]) = obj->width_hi; + + REG(MR2.UINT8[0]) = 0x07; + REG(MR3.UINT8[0]) = 0x00; + + REG(FER.UINT8[0]) = 0x72; // SCLE, NFE enabled, TMOT + REG(IER.UINT8[0]) = 0x00; // no interrupt + + REG(CR1.UINT32) &= ~CR1_RST; // CR1.IICRST negate reset +} + +static inline int i2c_wait_RDRF(i2c_t *obj) { + int timeout = 0; + + /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ + while ((i2c_status(obj) & SR2_RDRF) == 0) { + timeout ++; + if (timeout >= WAIT_TIMEOUT) { + return -1; + } + } + + return 0; +} + +static int i2c_wait_TDRE(i2c_t *obj) { + int timeout = 0; + + /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ + while ((i2c_status(obj) & SR2_TDRE) == 0) { + timeout ++; + if (timeout >= WAIT_TIMEOUT) { + return -1; + } + } + + return 0; +} + +static int i2c_wait_TEND(i2c_t *obj) { + int timeout = 0; + + /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ + while ((i2c_status(obj) & SR2_TEND) == 0) { + timeout ++; + if (timeout >= WAIT_TIMEOUT) { + return -1; + } + } + + return 0; +} + + +static int i2c_wait_START(i2c_t *obj) { + int timeout = 0; + + /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ + while ((i2c_status(obj) & SR2_START) == 0) { + timeout ++; + if (timeout >= WAIT_TIMEOUT) { + return -1; + } + } + + return 0; +} + +static int i2c_wait_STOP(i2c_t *obj) { + int timeout = 0; + + /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ + while ((i2c_status(obj) & SR2_STOP) == 0) { + timeout ++; + if (timeout >= WAIT_TIMEOUT) { + return -1; + } + } + + return 0; +} + +static int i2c_set_STOP(i2c_t *obj) { + /* SR2.STOP = 0 */ + REG(SR2.UINT32) &= ~SR2_STOP; + /* Stop condition */ + REG(CR2.UINT32) |= CR2_SP; + + return 0; +} + +static void i2c_set_SR2_NACKF_STOP(i2c_t *obj) { + /* SR2.NACKF = 0 */ + REG(SR2.UINT32) &= ~SR2_NACKF; + /* SR2.STOP = 0 */ + REG(SR2.UINT32) &= ~SR2_STOP; +} + +static void i2c_set_MR3_NACK(i2c_t *obj) { + /* send a NOT ACK */ + REG(MR3.UINT32) |= MR3_ACKWP; + REG(MR3.UINT32) |= MR3_ACKBT; + REG(MR3.UINT32) &= ~MR3_ACKWP; +} + +static void i2c_set_MR3_ACK(i2c_t *obj) { + /* send a ACK */ + REG(MR3.UINT32) |= MR3_ACKWP; + REG(MR3.UINT32) &= ~MR3_ACKBT; + REG(MR3.UINT32) &= ~MR3_ACKWP; +} + +static inline void i2c_power_enable(i2c_t *obj) { + volatile uint8_t dummy; + switch ((int)obj->i2c) { + case I2C_0: + CPGSTBCR9 &= ~(0x80); + break; + case I2C_1: + CPGSTBCR9 &= ~(0x40); + break; + case I2C_2: + CPGSTBCR9 &= ~(0x20); + break; + case I2C_3: + CPGSTBCR9 &= ~(0x10); + break; + } + dummy = CPGSTBCR9; +} + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) { + /* determine the I2C to use */ + I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); + I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); + obj->i2c = pinmap_merge(i2c_sda, i2c_scl); + MBED_ASSERT((int)obj->i2c != NC); + + /* enable power */ + i2c_power_enable(obj); + + /* set default frequency at 100k */ + i2c_frequency(obj, 100000); + + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + + obj->last_stop_flag = 1; +} + +inline int i2c_start(i2c_t *obj) { + int timeout = 0; + + while ((REG(CR2.UINT32) & CR2_BBSY) != 0) { + timeout ++; + if (timeout >= obj->bbsy_wait_cnt) { + break; + } + } + /* Start Condition */ + REG(CR2.UINT8[0]) |= CR2_ST; + + return 0; +} + +static inline int i2c_restart(i2c_t *obj) { + /* SR2.START = 0 */ + REG(SR2.UINT32) &= ~SR2_START; + /* ReStart condition */ + REG(CR2.UINT32) |= CR2_RS; + + return 0; +} + +inline int i2c_stop(i2c_t *obj) { + (void)i2c_set_STOP(obj); + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + + return 0; +} + +static void i2c_set_err_noslave(i2c_t *obj) { + (void)i2c_set_STOP(obj); + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + obj->last_stop_flag = 1; +} + +static inline int i2c_do_write(i2c_t *obj, int value) { + int timeout = 0; + + /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ + while ((i2c_status(obj) & SR2_TDRE) == 0) { + timeout ++; + if (timeout >= WAIT_TIMEOUT) { + return -1; + } + } + /* write the data */ + REG(DRT.UINT32) = value; + + return 0; +} + +static inline int i2c_read_address_write(i2c_t *obj, int value) { + int status; + + status = i2c_wait_TDRE(obj); + if (status == 0) { + /* write the data */ + REG(DRT.UINT32) = value; + } + + return status; + +} + +static inline int i2c_do_read(i2c_t *obj, int last) { + if (last == 2) { + /* this time is befor last byte read */ + /* Set MR3 WAIT bit is 1 */; + REG(MR3.UINT32) |= MR3_WAIT; + } else if (last == 1) { + i2c_set_MR3_NACK(obj); + } else { + i2c_set_MR3_ACK(obj); + } + + /* return the data */ + return (REG(DRR.UINT32) & 0xFF); +} + +void i2c_frequency(i2c_t *obj, int hz) { + float64_t pclk_val; + float64_t wait_utime; + volatile float64_t bps; + volatile float64_t L_time; /* H Width period */ + volatile float64_t H_time; /* L Width period */ + uint32_t tmp_L_width; + uint32_t tmp_H_width; + uint32_t remainder; + uint32_t wk_cks = 0; + + /* set PCLK */ + if (false == RZ_A1_IsClockMode0()) { + pclk_val = (float64_t)CM1_RENESAS_RZ_A1_P0_CLK; + } else { + pclk_val = (float64_t)CM0_RENESAS_RZ_A1_P0_CLK; + } + + /* Min 10kHz, Max 400kHz */ + if (hz < 10000) { + bps = 10000; + } else if (hz > 400000) { + bps = 400000; + } else { + bps = (float64_t)hz; + } + + /* Calculation L width time */ + L_time = (1 / (2 * bps)); /* Harf period of frequency */ + H_time = L_time; + + /* Check I2C mode of Speed */ + if (bps > 100000) { + /* Fast-mode */ + L_time -= 102E-9; /* Falling time of SCL clock. */ + H_time -= 138E-9; /* Rising time of SCL clock. */ + /* Check L wideth */ + if (L_time < 1.3E-6) { + /* Wnen L width less than 1.3us */ + /* Subtract Rise up and down time for SCL from H/L width */ + L_time = 1.3E-6; + H_time = (1 / bps) - L_time - 138E-9 - 102E-9; + } + } + + tmp_L_width = (uint32_t)(L_time * pclk_val * 10); + tmp_L_width >>= 1; + wk_cks++; + while (tmp_L_width >= 341) { + tmp_L_width >>= 1; + wk_cks++; + } + remainder = tmp_L_width % 10; + tmp_L_width = ((tmp_L_width + 9) / 10) - 3; /* carry */ + + tmp_H_width = (uint32_t)(H_time * pclk_val * 10); + tmp_H_width >>= wk_cks; + if (remainder == 0) { + tmp_H_width = ((tmp_H_width + 9) / 10) - 3; /* carry */ + } else { + remainder += tmp_H_width % 10; + tmp_H_width = (tmp_H_width / 10) - 3; + if (remainder > 10) { + tmp_H_width += 1; /* fine adjustment */ + } + } + /* timeout of BBSY bit is minimum low width by frequency */ + /* so timeout calculates "(low width) * 2" by frequency */ + wait_utime = (L_time * 2) * 1000000; + /* 1 wait of BBSY bit is about 0.3us. if it's below 0.3us, wait count is set as 1. */ + if (wait_utime <= 0.3) { + obj->bbsy_wait_cnt = 1; + } else { + obj->bbsy_wait_cnt = (int)(wait_utime / 0.3); + } + + + /* I2C Rate */ + obj->pclk_bit = (uint8_t)(0x10 * wk_cks); /* P_phi / xx */ + obj->width_low = (uint8_t)(tmp_L_width | 0x000000E0); + obj->width_hi = (uint8_t)(tmp_H_width | 0x000000E0); + + /* full reset */ + i2c_reg_reset(obj); +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { + int count = 0; + int status; + int value; + volatile uint32_t work_reg = 0; + + if(length <= 0) { + return 0; + } + i2c_set_MR3_ACK(obj); + /* There is a STOP condition for last processing */ + if (obj->last_stop_flag != 0) { + status = i2c_start(obj); + if (status != 0) { + i2c_set_err_noslave(obj); + return I2C_ERROR_BUS_BUSY; + } + } + obj->last_stop_flag = stop; + /* Send Slave address */ + status = i2c_read_address_write(obj, (address | 0x01)); + if (status != 0) { + i2c_set_err_noslave(obj); + return I2C_ERROR_NO_SLAVE; + } + /* wait RDRF */ + status = i2c_wait_RDRF(obj); + /* check ACK/NACK */ + if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) { + /* Slave sends NACK */ + (void)i2c_set_STOP(obj); + /* dummy read */ + value = REG(DRR.UINT32); + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + obj->last_stop_flag = 1; + return I2C_ERROR_NO_SLAVE; + } + /* Read in all except last byte */ + if (length > 2) { + /* dummy read */ + value = REG(DRR.UINT32); + for (count = 0; count < (length - 1); count++) { + /* wait for it to arrive */ + status = i2c_wait_RDRF(obj); + if (status != 0) { + i2c_set_err_noslave(obj); + return I2C_ERROR_NO_SLAVE; + } + /* Recieve the data */ + if (count == (length - 2)) { + value = i2c_do_read(obj, 1); + } else if ((length >= 3) && (count == (length - 3))) { + value = i2c_do_read(obj, 2); + } else { + value = i2c_do_read(obj, 0); + } + data[count] = (char)value; + } + } else if (length == 2) { + /* Set MR3 WATI bit is 1 */ + REG(MR3.UINT32) |= MR3_WAIT; + /* dummy read */ + value = REG(DRR.UINT32); + /* wait for it to arrive */ + status = i2c_wait_RDRF(obj); + if (status != 0) { + i2c_set_err_noslave(obj); + return I2C_ERROR_NO_SLAVE; + } + i2c_set_MR3_NACK(obj); + data[count] = (char)REG(DRR.UINT32); + count++; + } else { + /* length == 1 */ + /* Set MR3 WATI bit is 1 */; + REG(MR3.UINT32) |= MR3_WAIT; + i2c_set_MR3_NACK(obj); + /* dummy read */ + value = REG(DRR.UINT32); + } + /* wait for it to arrive */ + status = i2c_wait_RDRF(obj); + if (status != 0) { + i2c_set_err_noslave(obj); + return I2C_ERROR_NO_SLAVE; + } + + /* If not repeated start, send stop. */ + if (stop) { + (void)i2c_set_STOP(obj); + /* RIICnDRR read */ + value = (REG(DRR.UINT32) & 0xFF); + data[count] = (char)value; + /* RIICnMR3.WAIT = 0 */ + REG(MR3.UINT32) &= ~MR3_WAIT; + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + } else { + (void)i2c_restart(obj); + /* RIICnDRR read */ + value = (REG(DRR.UINT32) & 0xFF); + data[count] = (char)value; + /* RIICnMR3.WAIT = 0 */ + REG(MR3.UINT32) &= ~MR3_WAIT; + (void)i2c_wait_START(obj); + /* SR2.START = 0 */ + REG(SR2.UINT32) &= ~SR2_START; + } + + return length; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { + int cnt; + int status; + + if(length <= 0) { + return 0; + } + + /* There is a STOP condition for last processing */ + if (obj->last_stop_flag != 0) { + status = i2c_start(obj); + if (status != 0) { + i2c_set_err_noslave(obj); + return I2C_ERROR_BUS_BUSY; + } + } + obj->last_stop_flag = stop; + /* Send Slave address */ + status = i2c_do_write(obj, address); + if (status != 0) { + i2c_set_err_noslave(obj); + return I2C_ERROR_NO_SLAVE; + } + /* Wait send end */ + status = i2c_wait_TEND(obj); + if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) { + /* Slave sends NACK */ + i2c_set_err_noslave(obj); + return I2C_ERROR_NO_SLAVE; + } + /* Send Write data */ + for (cnt=0; cnt<length; cnt++) { + status = i2c_do_write(obj, data[cnt]); + if(status != 0) { + i2c_set_err_noslave(obj); + return cnt; + } else { + /* Wait send end */ + status = i2c_wait_TEND(obj); + if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) { + /* Slave sends NACK */ + i2c_set_err_noslave(obj); + return I2C_ERROR_NO_SLAVE; + } + } + } + /* If not repeated start, send stop. */ + if (stop) { + (void)i2c_set_STOP(obj); + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + } else { + (void)i2c_restart(obj); + (void)i2c_wait_START(obj); + /* SR2.START = 0 */ + REG(SR2.UINT32) &= ~SR2_START; + + } + + return length; +} + +void i2c_reset(i2c_t *obj) { + (void)i2c_set_STOP(obj); + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); +} + +int i2c_byte_read(i2c_t *obj, int last) { + int status; + int data; + + data = i2c_do_read(obj, last); + /* wait for it to arrive */ + status = i2c_wait_RDRF(obj); + if (status != 0) { + i2c_set_SR2_NACKF_STOP(obj); + return I2C_ERROR_NO_SLAVE; + } + + return data; +} + +int i2c_byte_write(i2c_t *obj, int data) { + int ack = 0; + int status; + int timeout = 0; + + status = i2c_do_write(obj, (data & 0xFF)); + if (status != 0) { + i2c_set_SR2_NACKF_STOP(obj); + } else { + while (((i2c_status(obj) & SR2_RDRF) == 0) && ((i2c_status(obj) & SR2_TEND) == 0)) { + timeout++; + if (timeout >= WAIT_TIMEOUT) { + return ack; + } + } + /* check ACK/NACK */ + if ((REG(SR2.UINT32) & SR2_NACKF) != 0) { + /* NACK */ + i2c_set_SR2_NACKF_STOP(obj); + } else { + ack = 1; + } + } + + return ack; +} + +void i2c_slave_mode(i2c_t *obj, int enable_slave) { + if (enable_slave != 0) { + REG(SER.UINT32) |= SER_SAR0E; // only slave addr 0 is enabled + } else { + REG(SER.UINT32) &= ~SER_SAR0E; // no slave addr enabled + } +} + +int i2c_slave_receive(i2c_t *obj) { + int status; + int retval; + + status = (REG(SR1.UINT8[0]) & SR1_AAS0); + status |= (REG(CR2.UINT8[0]) & CR2_TRS) >> 4; + + switch(status) { + case 0x01: + /* the master is writing to this slave */ + retval = 3; + break; + case 0x02: + /* the master is writing to all slave */ + retval = 2; + break; + case 0x03: + /* the master has requested a read from this slave */ + retval = 1; + break; + default : + /* no data */ + retval = 0; + break; + } + + return retval; +} + +int i2c_slave_read(i2c_t *obj, char *data, int length) { + int timeout = 0; + int count; + int break_flg = 0; + + if(length <= 0) { + return 0; + } + for (count = 0; ((count < (length + 1)) && (break_flg == 0)); count++) { + /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ + while (((i2c_status(obj) & SR2_STOP) != 0) || ((i2c_status(obj) & SR2_RDRF) == 0)) { + if ((i2c_status(obj) & SR2_STOP) != 0) { + break_flg = 1; + break; + } + timeout ++; + if (timeout >= WAIT_TIMEOUT) { + return -1; + } + } + if (break_flg == 0) { + if (count == 0) { + /* dummy read */ + (void)REG(DRR.UINT32); + } else { + data[count - 1] = (char)(REG(DRR.UINT32) & 0xFF); + } + } + } + if (break_flg == 0) { + (void)i2c_wait_STOP(obj); + } else { + if ((i2c_status(obj) & SR2_RDRF) != 0) { + if (count <= 1) { + /* fail safe */ + /* dummy read */ + (void)REG(DRR.UINT32); + } else { + data[count - 2] = (char)(REG(DRR.UINT32) & 0xFF); + } + } + } + /* SR2.STOP = 0 */ + REG(SR2.UINT32) &= ~SR2_STOP; + + return (count - 1); +} + +int i2c_slave_write(i2c_t *obj, const char *data, int length) { + int count = 0; + int status = 0; + + if(length <= 0) { + return 0; + } + + while ((count < length) && (status == 0)) { + status = i2c_do_write(obj, data[count]); + if(status == 0) { + /* Wait send end */ + status = i2c_wait_TEND(obj); + if ((status != 0) || ((count < (length - 1)) && ((REG(SR2.UINT32) & SR2_NACKF) != 0))) { + /* NACK */ + break; + } + } + count++; + } + /* dummy read */ + (void)REG(DRR.UINT32); + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + + return count; +} + +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { + REG(SAR0.UINT32) = (address & 0xfffffffe); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/objects.h Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,84 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include <stdint.h> +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" +#include "gpio_object.h" +#include "rspi_iodefine.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct i2c_s { + uint32_t i2c; + uint32_t dummy; + uint8_t pclk_bit; + uint8_t width_low; + uint8_t width_hi; + int bbsy_wait_cnt; + int last_stop_flag; +}; + +struct spi_s { + struct st_rspi *spi; + uint32_t bits; +}; + +struct gpio_irq_s { + uint32_t port; + uint32_t pin; + uint32_t ch; + uint8_t int_enable; +}; + +struct port_s { + __IO uint32_t *reg_dir; + __IO uint32_t *reg_out; + __I uint32_t *reg_in; + __IO uint32_t *reg_buf; + PortName port; + uint32_t mask; +}; + +struct serial_s { + struct st_scif *uart; + int index; +}; + +struct pwmout_s { + uint32_t ch; + PWMName pwm; +}; + +struct analogin_s { + ADCName adc; +}; + +struct can_s { + uint32_t ch; +}; + +#ifdef __cplusplus +} +#endif + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/pinmap.c Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,192 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "pinmap.h" +#include "mbed_error.h" +#include "gpio_addrdefine.h" + +PinName gpio_multi_guard = (PinName)NC; /* If set pin name here, setting of the "pin" is just one time */ + +typedef struct { + PinName pin; + int function; + int pm; +} PinFunc; + +#ifdef MAX_PERI +static const PinFunc PIPC_0_tbl[] = { +// pin func pm + {P4_0 , 2 , -1}, /* TIOC0A */ + {P5_0 , 6 , -1}, /* TIOC0A */ + {P7_0 , 7 , -1}, /* TIOC0A */ + {P4_1 , 2 , -1}, /* TIOC0B */ + {P5_1 , 6 , -1}, /* TIOC0B */ + {P7_1 , 7 , -1}, /* TIOC0B */ + {P4_2 , 2 , -1}, /* TIOC0C */ + {P5_5 , 6 , -1}, /* TIOC0C */ + {P7_2 , 7 , -1}, /* TIOC0C */ + {P4_3 , 2 , -1}, /* TIOC0D */ + {P5_7 , 6 , -1}, /* TIOC0D */ + {P7_3 , 7 , -1}, /* TIOC0D */ + {P2_11 , 5 , -1}, /* TIOC1A */ + {P6_0 , 5 , -1}, /* TIOC1A */ + {P7_4 , 7 , -1}, /* TIOC1A */ + {P8_8 , 5 , -1}, /* TIOC1A */ + {P9_7 , 4 , -1}, /* TIOC1A */ + {P2_12 , 8 , -1}, /* TIOC1B */ + {P5_2 , 6 , -1}, /* TIOC1B */ + {P6_1 , 5 , -1}, /* TIOC1B */ + {P7_5 , 7 , -1}, /* TIOC1B */ + {P8_9 , 5 , -1}, /* TIOC1B */ + {P2_1 , 6 , -1}, /* TIOC2A */ + {P6_2 , 6 , -1}, /* TIOC2A */ + {P7_6 , 7 , -1}, /* TIOC2A */ + {P8_14 , 4 , -1}, /* TIOC2A */ + {P2_2 , 6 , -1}, /* TIOC2B */ + {P6_3 , 6 , -1}, /* TIOC2B */ + {P7_7 , 7 , -1}, /* TIOC2B */ + {P8_15 , 4 , -1}, /* TIOC2B */ + {P3_4 , 6 , -1}, /* TIOC3A */ + {P7_8 , 7 , -1}, /* TIOC3A */ + {P8_10 , 4 , -1}, /* TIOC3A */ + {P3_5 , 6 , -1}, /* TIOC3B */ + {P7_9 , 7 , -1}, /* TIOC3B */ + {P8_11 , 4 , -1}, /* TIOC3B */ + {P3_6 , 6 , -1}, /* TIOC3C */ + {P5_3 , 6 , -1}, /* TIOC3C */ + {P7_10 , 7 , -1}, /* TIOC3C */ + {P8_12 , 4 , -1}, /* TIOC3C */ + {P3_7 , 6 , -1}, /* TIOC3D */ + {P5_4 , 6 , -1}, /* TIOC3D */ + {P7_11 , 7 , -1}, /* TIOC3D */ + {P8_13 , 4 , -1}, /* TIOC3D */ + {P3_8 , 6 , -1}, /* TIOC4A */ + {P4_4 , 3 , -1}, /* TIOC4A */ + {P7_12 , 7 , -1}, /* TIOC4A */ + {P3_9 , 6 , -1}, /* TIOC4B */ + {P4_5 , 3 , -1}, /* TIOC4B */ + {P7_13 , 7 , -1}, /* TIOC4B */ + {P3_10 , 6 , -1}, /* TIOC4C */ + {P4_6 , 3 , -1}, /* TIOC4C */ + {P7_14 , 7 , -1}, /* TIOC4C */ + {P3_11 , 6 , -1}, /* TIOC4D */ + {P4_7 , 3 , -1}, /* TIOC4D */ + {P7_15 , 7 , -1}, /* TIOC4D */ + {P5_7 , 1 , 1 }, /* TXOUT0M */ + {P5_6 , 1 , 1 }, /* TXOUT0P */ + {P5_5 , 1 , 1 }, /* TXOUT1M */ + {P5_4 , 1 , 1 }, /* TXOUT1P */ + {P5_3 , 1 , 1 }, /* TXOUT2M */ + {P5_2 , 1 , 1 }, /* TXOUT2P */ + {P5_1 , 1 , 1 }, /* TXCLKOUTM */ + {P5_0 , 1 , 1 }, /* TXCLKOUTP */ + {P2_11 , 4 , 0 }, /* SSITxD0 */ + {P4_7 , 5 , 0 }, /* SSITxD0 */ + {P7_4 , 6 , 0 }, /* SSITxD1 */ + {P4_15 , 6 , 0 }, /* SSITxD3 */ + {P7_11 , 2 , 0 }, /* SSITxD3 */ + {P2_7 , 4 , 0 }, /* SSITxD5 */ + {P4_11 , 5 , 0 }, /* SSITxD5 */ + {P8_10 , 8 , 0 }, /* SSITxD5 */ + {P3_7 , 8 , 0 }, /* WDTOVF */ + {NC , 0 , -1} +}; +#else +static const PinFunc PIPC_0_tbl[] = { + // pin func pm + {P4_0 , 2 , -1}, // TIOC0A + {P5_0 , 6 , -1}, // TIOC0A + {P4_2 , 2 , -1}, // TIOC0C + {P5_5 , 6 , -1}, // TIOC0C + // + {P8_14 , 4 , -1}, // TIOC2A + // + {P8_10 , 4 , -1}, // TIOC3A + {P5_3 , 6 , -1}, // TIOC3C + {P8_12 , 4 , -1}, // TIOC3C + // + {P3_8 , 6 , -1}, // TIOC4A + {P4_4 , 3 , -1}, // TIOC4A + {P3_10 , 6 , -1}, // TIOC4C + {P4_6 , 3 , -1}, // TIOC4C + // + {P5_7 , 1 , 1 }, // TXOUT0M + {P5_6 , 1 , 1 }, // TXOUT0P + {P5_5 , 1 , 1 }, // TXOUT1M + {P5_4 , 1 , 1 }, // TXOUT1P + {P5_3 , 1 , 1 }, // TXOUT2M + {P5_2 , 1 , 1 }, // TXOUT2P + {P5_1 , 1 , 1 }, // TXCLKOUTM + {P5_0 , 1 , 1 }, // TXCLKOUTP + {P4_7 , 5 , 0 }, // SSITxD0 + {P8_10 , 8 , 0 }, // SSITxD5 + {P3_7 , 8 , 0 }, // WDTOVF + {NC , 0 , -1} +}; +#endif + +void pin_function(PinName pin, int function) { + if (pin == (PinName)NC) return; + + int n = pin >> 4; + int bitmask = 1<<(pin & 0xf); + const PinFunc * Pipc_0_func = PIPC_0_tbl; + int pipc_data = 1; + + if (gpio_multi_guard != pin) { + if (function == 0) { + // means GPIO mode + *PMC(n) &= ~bitmask; + } else { + // alt-function mode + --function; + + if (function & (1 << 2)) { *PFCAE(n) |= bitmask;}else { *PFCAE(n) &= ~bitmask;} + if (function & (1 << 1)) { *PFCE(n) |= bitmask;}else { *PFCE(n) &= ~bitmask;} + if (function & (1 << 0)) { *PFC(n) |= bitmask;}else { *PFC(n) &= ~bitmask;} + + while (Pipc_0_func->pin != NC) { + if ((Pipc_0_func->pin == pin) && ((Pipc_0_func->function - 1) == function)) { + pipc_data = 0; + if (Pipc_0_func->pm == 0) { + *PMSR(n) = (bitmask << 16) | 0; + } else if (Pipc_0_func->pm == 1) { + *PMSR(n) = (bitmask << 16) | bitmask; + } else { + // Do Nothing + } + break; + } + Pipc_0_func++; + } + if (pipc_data == 1) { + *PIPC(n) |= bitmask; + } else { + *PIPC(n) &= ~bitmask; + } + + if (P1_0 <= pin && pin <= P1_7 && function == 0) { + *PBDC(n) |= bitmask; + } + *PMC(n) |= bitmask; + } + } else { + gpio_multi_guard = (PinName)NC; + } +} + +void pin_mode(PinName pin, PinMode mode) { +// if (pin == (PinName)NC) { return; } +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/port_api.c Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,74 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "port_api.h" +#include "pinmap.h" +#include "gpio_api.h" +#include "gpio_addrdefine.h" + +PinName port_pin(PortName port, int pin_n) { + return (PinName)((port*0x10)+pin_n); +} + +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { + obj->port = port; + obj->mask = mask; + + obj->reg_dir = (volatile uint32_t *)PMSR(port); + obj->reg_out = (volatile uint32_t *)PORT(port); + obj->reg_in = (volatile uint32_t *)PPR(port); + obj->reg_buf = (volatile uint32_t *)PIBC(port); + // Do not use masking, because it prevents the use of the unmasked pins + // port_reg->FIOMASK = ~mask; + + uint32_t i; + // The function is set per pin: reuse gpio logic + for (i=0; i<32; i++) { + if (obj->mask & (1<<i)) { + gpio_set(port_pin(obj->port, i)); + } + } + + port_dir(obj, dir); +} + +void port_mode(port_t *obj, PinMode mode) { + uint32_t i; + // The mode is set per pin: reuse pinmap logic + for (i=0; i<32; i++) { + if (obj->mask & (1<<i)) { + pin_mode(port_pin(obj->port, i), mode); + } + } +} + +void port_dir(port_t *obj, PinDirection dir) { + switch (dir) { + case PIN_INPUT : *obj->reg_dir = (obj->mask << 16) | obj->mask; + *obj->reg_buf |= obj->mask; + break; + case PIN_OUTPUT: *obj->reg_dir = (obj->mask << 16) | ~obj->mask; + *obj->reg_buf &= ~obj->mask; + break; + } +} + +void port_write(port_t *obj, int value) { + *obj->reg_out = (obj->mask << 16) | (value & obj->mask); +} + +int port_read(port_t *obj) { + return (*obj->reg_in & obj->mask); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/pwmout_api.c Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,705 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "pwmout_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "RZ_A1_Init.h" +#include "cpg_iodefine.h" +#include "pwm_iodefine.h" +#include "gpio_addrdefine.h" + +#ifdef MAX_PERI +#define MTU2_PWM_NUM 27 +#define MTU2_PWM_SIGNAL 2 +#define MTU2_PWM_OFFSET 0x20 + +// PORT ID, PWM ID, Pin function +static const PinMap PinMap_PWM[] = { + // TIOC0 A,C + {P4_0 , MTU2_PWM0_PIN , 2}, //TIOC0A + {P5_0 , MTU2_PWM1_PIN , 6}, //TIOC0A + {P7_0 , MTU2_PWM2_PIN , 7}, //TIOC0A + {P4_2 , MTU2_PWM3_PIN , 2}, //TIOC0C + {P5_5 , MTU2_PWM4_PIN , 6}, //TIOC0C + {P7_2 , MTU2_PWM5_PIN , 7}, //TIOC0C + //TIOC1 A + {P2_11 , MTU2_PWM6_PIN , 5}, //TIOC1A + {P6_0 , MTU2_PWM7_PIN , 5}, //TIOC1A + {P7_4 , MTU2_PWM8_PIN , 7}, //TIOC1A + {P8_8 , MTU2_PWM9_PIN , 5}, //TIOC1A + {P9_7 , MTU2_PWM10_PIN , 4}, //TIOC1A + //TIOC2 A + {P2_1 , MTU2_PWM11_PIN , 6}, //TIOC2A + {P6_2 , MTU2_PWM12_PIN , 6}, //TIOC2A + {P7_6 , MTU2_PWM13_PIN , 7}, //TIOC2A + {P8_14 , MTU2_PWM14_PIN , 4}, //TIOC2A + //TIOC3 A,C + {P3_4 , MTU2_PWM15_PIN , 6}, //TIOC3A + {P7_8 , MTU2_PWM16_PIN , 7}, //TIOC3A + {P8_10 , MTU2_PWM17_PIN , 4}, //TIOC3A + {P3_6 , MTU2_PWM18_PIN , 6}, //TIOC3C + {P7_10 , MTU2_PWM19_PIN , 7}, //TIOC3C + {P8_12 , MTU2_PWM20_PIN , 4}, //TIOC3C + //TIOC4 A,C + {P3_8 , MTU2_PWM21_PIN , 6}, //TIOC4A + {P4_4 , MTU2_PWM22_PIN , 3}, //TIOC4A + {P7_12 , MTU2_PWM23_PIN , 7}, //TIOC4A + {P3_10 , MTU2_PWM24_PIN , 6}, //TIOC4C + {P4_6 , MTU2_PWM25_PIN , 3}, //TIOC4C + {P7_14 , MTU2_PWM26_PIN , 7}, //TIOC4C + //PWM1 + {P8_8 , PWM0_PIN , 6}, //PWM1A + {P8_9 , PWM1_PIN , 6}, //PWM1B + {P8_10 , PWM2_PIN , 6}, //PWM1C + {P8_11 , PWM3_PIN , 6}, //PWM1D + {P8_12 , PWM4_PIN , 6}, //PWM1E + {P8_13 , PWM5_PIN , 6}, //PWM1F + {P8_14 , PWM6_PIN , 6}, //PWM1G + {P8_15 , PWM7_PIN , 6}, //PWM1H + //PWM2 + {P3_0 , PWM8_PIN , 7}, //PWM2A + {P3_1 , PWM9_PIN , 7}, //PWM2B + {P3_2 , PWM10_PIN , 7}, //PWM2C + {P3_3 , PWM11_PIN , 7}, //PWM2D + {P4_4 , PWM12_PIN , 4}, //PWM2E + {P4_5 , PWM13_PIN , 4}, //PWM2F + {P4_6 , PWM14_PIN , 4}, //PWM2G + {P4_7 , PWM15_PIN , 4}, //PWM2H + {NC , NC , 0} +}; + +static const PWMType PORT[] = { + PWM1A, // PWM0_PIN + PWM1B, // PWM1_PIN + PWM1C, // PWM2_PIN + PWM1D, // PWM3_PIN + PWM1E, // PWM4_PIN + PWM1F, // PWM5_PIN + PWM1G, // PWM6_PIN + PWM1H, // PWM7_PIN + PWM2A, // PWM8_PIN + PWM2B, // PWM9_PIN + PWM2C, // PWM10_PIN + PWM2D, // PWM11_PIN + PWM2E, // PWM12_PIN + PWM2F, // PWM13_PIN + PWM2G, // PWM14_PIN + PWM2H, // PWM15_PIN +}; + +static const MTU2_PWMType MTU2_PORT[] = { + TIOC0A, // MTU2_PWM0_PIN + TIOC0A, // MTU2_PWM1_PIN + TIOC0A, // MTU2_PWM2_PIN + TIOC0C, // MTU2_PWM3_PIN + TIOC0C, // MTU2_PWM4_PIN + TIOC0C, // MTU2_PWM5_PIN + TIOC1A, // MTU2_PWM6_PIN + TIOC1A, // MTU2_PWM7_PIN + TIOC1A, // MTU2_PWM8_PIN + TIOC1A, // MTU2_PWM9_PIN + TIOC1A, // MTU2_PWM10_PIN + TIOC2A, // MTU2_PWM11_PIN + TIOC2A, // MTU2_PWM12_PIN + TIOC2A, // MTU2_PWM13_PIN + TIOC2A, // MTU2_PWM14_PIN + TIOC3A, // MTU2_PWM15_PIN + TIOC3A, // MTU2_PWM16_PIN + TIOC3A, // MTU2_PWM17_PIN + TIOC3C, // MTU2_PWM18_PIN + TIOC3C, // MTU2_PWM19_PIN + TIOC3C, // MTU2_PWM20_PIN + TIOC4A, // MTU2_PWM21_PIN + TIOC4A, // MTU2_PWM22_PIN + TIOC4A, // MTU2_PWM23_PIN + TIOC4C, // MTU2_PWM24_PIN + TIOC4C, // MTU2_PWM25_PIN + TIOC4C, // MTU2_PWM26_PIN +}; + +static __IO uint16_t *PWM_MATCH[] = { + &PWMPWBFR_1A, // PWM0_PIN + &PWMPWBFR_1A, // PWM1_PIN + &PWMPWBFR_1C, // PWM2_PIN + &PWMPWBFR_1C, // PWM3_PIN + &PWMPWBFR_1E, // PWM4_PIN + &PWMPWBFR_1E, // PWM5_PIN + &PWMPWBFR_1G, // PWM6_PIN + &PWMPWBFR_1G, // PWM7_PIN + &PWMPWBFR_2A, // PWM8_PIN + &PWMPWBFR_2A, // PWM9_PIN + &PWMPWBFR_2C, // PWM10_PIN + &PWMPWBFR_2C, // PWM11_PIN + &PWMPWBFR_2E, // PWM12_PIN + &PWMPWBFR_2E, // PWM13_PIN + &PWMPWBFR_2G, // PWM14_PIN + &PWMPWBFR_2G, // PWM15_PIN +}; + +static __IO uint16_t *MTU2_PWM_MATCH[MTU2_PWM_NUM][MTU2_PWM_SIGNAL] = { + { &MTU2TGRA_0, &MTU2TGRB_0 } // MTU2_PWM0_PIN + { &MTU2TGRA_0, &MTU2TGRB_0 } // MTU2_PWM1_PIN + { &MTU2TGRA_0, &MTU2TGRB_0 } // MTU2_PWM2_PIN + { &MTU2TGRC_0, &MTU2TGRD_0 } // MTU2_PWM3_PIN + { &MTU2TGRC_0, &MTU2TGRD_0 } // MTU2_PWM4_PIN + { &MTU2TGRC_0, &MTU2TGRD_0 } // MTU2_PWM5_PIN + { &MTU2TGRA_1, &MTU2TGRB_1 } // MTU2_PWM6_PIN + { &MTU2TGRA_1, &MTU2TGRB_1 } // MTU2_PWM7_PIN + { &MTU2TGRA_1, &MTU2TGRB_1 } // MTU2_PWM8_PIN + { &MTU2TGRA_1, &MTU2TGRB_1 } // MTU2_PWM9_PIN + { &MTU2TGRA_1, &MTU2TGRB_1 } // MTU2_PWM10_PIN + { &MTU2TGRA_2, &MTU2TGRB_2 } // MTU2_PWM11_PIN + { &MTU2TGRA_2, &MTU2TGRB_2 } // MTU2_PWM12_PIN + { &MTU2TGRA_2, &MTU2TGRB_2 } // MTU2_PWM13_PIN + { &MTU2TGRA_2, &MTU2TGRB_2 } // MTU2_PWM14_PIN + { &MTU2TGRA_3, &MTU2TGRB_3 } // MTU2_PWM15_PIN + { &MTU2TGRA_3, &MTU2TGRB_3 } // MTU2_PWM16_PIN + { &MTU2TGRA_3, &MTU2TGRB_3 } // MTU2_PWM17_PIN + { &MTU2TGRC_3, &MTU2TGRD_3 } // MTU2_PWM18_PIN + { &MTU2TGRC_3, &MTU2TGRD_3 } // MTU2_PWM19_PIN + { &MTU2TGRC_3, &MTU2TGRD_3 } // MTU2_PWM20_PIN + { &MTU2TGRA_4, &MTU2TGRB_2 } // MTU2_PWM21_PIN + { &MTU2TGRA_4, &MTU2TGRB_2 } // MTU2_PWM22_PIN + { &MTU2TGRA_4, &MTU2TGRB_2 } // MTU2_PWM23_PIN + { &MTU2TGRC_4, &MTU2TGRD_4 } // MTU2_PWM24_PIN + { &MTU2TGRC_4, &MTU2TGRD_4 } // MTU2_PWM25_PIN + { &MTU2TGRC_4, &MTU2TGRD_4 } // MTU2_PWM26_PIN +}; +#else +#define MTU2_PWM_NUM 12 +#define MTU2_PWM_SIGNAL 2 +#define MTU2_PWM_OFFSET 0x20 + +// PORT ID, PWM ID, Pin function +static const PinMap PinMap_PWM[] = { + //TIOC0 A,C + {P4_0 , MTU2_PWM0_PIN , 2}, //TIOC0A + {P5_0 , MTU2_PWM1_PIN , 6}, //TIOC0A + {P4_2 , MTU2_PWM2_PIN , 2}, //TIOC0C + {P5_5 , MTU2_PWM3_PIN , 6}, //TIOC0C + //TIOC2 A + {P8_14 , MTU2_PWM4_PIN , 4}, //TIOC2A + //TIOC3 A,C + {P8_10 , MTU2_PWM5_PIN , 4}, //TIOC3A + {P5_3 , MTU2_PWM6_PIN , 6}, //TIOC3C + {P8_12 , MTU2_PWM7_PIN , 4}, //TIOC3C + //TIOC4 A,C + {P3_8 , MTU2_PWM8_PIN , 6}, //TIOC4A + {P4_4 , MTU2_PWM9_PIN , 3}, //TIOC4A + {P3_10 , MTU2_PWM10_PIN , 6}, //TIOC4C + {P4_6 , MTU2_PWM11_PIN , 3}, //TIOC4C + //PWM1 + {P8_10 , PWM0_PIN , 6}, //PWM1C + {P8_11 , PWM1_PIN , 6}, //PWM1D + {P8_12 , PWM2_PIN , 6}, //PWM1E + {P8_13 , PWM3_PIN , 6}, //PWM1F + {P8_14 , PWM4_PIN , 6}, //PWM1G + {P8_15 , PWM5_PIN , 6}, //PWM1H + //PWM2 + {P3_0 , PWM6_PIN , 7}, //PWM2A + {P3_1 , PWM7_PIN , 7}, //PWM2B + {P3_2 , PWM8_PIN , 7}, //PWM2C + {P4_4 , PWM9_PIN , 4}, //PWM2E + {P4_5 , PWM10_PIN , 4}, //PWM2F + {P4_6 , PWM11_PIN , 4}, //PWM2G + {P4_7 , PWM12_PIN , 4}, //PWM2H + {NC , NC , 0} +}; + +static const PWMType PORT[] = { + PWM1C, // PWM0_PIN + PWM1D, // PWM1_PIN + PWM1E, // PWM2_PIN + PWM1F, // PWM3_PIN + PWM1G, // PWM4_PIN + PWM1H, // PWM5_PIN + PWM2A, // PWM6_PIN + PWM2B, // PWM7_PIN + PWM2C, // PWM8_PIN + PWM2E, // PWM9_PIN + PWM2F, // PWM10_PIN + PWM2G, // PWM11_PIN + PWM2H, // PWM12_PIN +}; + +static const MTU2_PWMType MTU2_PORT[] = { + TIOC0A, // MTU2_PWM0_PIN + TIOC0A, // MTU2_PWM1_PIN + TIOC0C, // MTU2_PWM2_PIN + TIOC0C, // MTU2_PWM3_PIN + TIOC2A, // MTU2_PWM4_PIN + TIOC3A, // MTU2_PWM5_PIN + TIOC3C, // MTU2_PWM6_PIN + TIOC3C, // MTU2_PWM7_PIN + TIOC4A, // MTU2_PWM8_PIN + TIOC4A, // MTU2_PWM9_PIN + TIOC4C, // MTU2_PWM10_PIN + TIOC4C, // MTU2_PWM11_PIN +}; + +static __IO uint16_t *PWM_MATCH[] = { + &PWMPWBFR_1C, // PWM0_PIN + &PWMPWBFR_1C, // PWM1_PIN + &PWMPWBFR_1E, // PWM2_PIN + &PWMPWBFR_1E, // PWM3_PIN + &PWMPWBFR_1G, // PWM4_PIN + &PWMPWBFR_1G, // PWM5_PIN + &PWMPWBFR_2A, // PWM6_PIN + &PWMPWBFR_2A, // PWM7_PIN + &PWMPWBFR_2C, // PWM8_PIN + &PWMPWBFR_2E, // PWM9_PIN + &PWMPWBFR_2E, // PWM10_PIN + &PWMPWBFR_2G, // PWM11_PIN + &PWMPWBFR_2G, // PWM12_PIN +}; + +static __IO uint16_t *MTU2_PWM_MATCH[MTU2_PWM_NUM][MTU2_PWM_SIGNAL] = { + { &MTU2TGRA_0, &MTU2TGRB_0 }, // MTU2_PWM0_PIN + { &MTU2TGRA_0, &MTU2TGRB_0 }, // MTU2_PWM1_PIN + { &MTU2TGRC_0, &MTU2TGRD_0 }, // MTU2_PWM2_PIN + { &MTU2TGRC_0, &MTU2TGRD_0 }, // MTU2_PWM3_PIN + { &MTU2TGRA_2, &MTU2TGRB_2 }, // MTU2_PWM4_PIN + { &MTU2TGRA_3, &MTU2TGRB_3 }, // MTU2_PWM5_PIN + { &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM6_PIN + { &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM7_PIN + { &MTU2TGRA_4, &MTU2TGRB_2 }, // MTU2_PWM8_PIN + { &MTU2TGRA_4, &MTU2TGRB_2 }, // MTU2_PWM9_PIN + { &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM10_PIN + { &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM11_PIN +}; +#endif + + +static __IO uint8_t *TCR_MATCH[] = { + &MTU2TCR_0, + &MTU2TCR_1, + &MTU2TCR_2, + &MTU2TCR_3, + &MTU2TCR_4, +}; + +static __IO uint8_t *TIORH_MATCH[] = { + &MTU2TIORH_0, + &MTU2TIOR_1, + &MTU2TIOR_2, + &MTU2TIORH_3, + &MTU2TIORH_4, +}; + +static __IO uint8_t *TIORL_MATCH[] = { + &MTU2TIORL_0, + NULL, + NULL, + &MTU2TIORL_3, + &MTU2TIORL_4, +}; + +static __IO uint16_t *TGRA_MATCH[] = { + &MTU2TGRA_0, + &MTU2TGRA_1, + &MTU2TGRA_2, + &MTU2TGRA_3, + &MTU2TGRA_4, +}; + +static __IO uint16_t *TGRC_MATCH[] = { + &MTU2TGRC_0, + NULL, + NULL, + &MTU2TGRC_3, + &MTU2TGRC_4, +}; + +static __IO uint8_t *TMDR_MATCH[] = { + &MTU2TMDR_0, + &MTU2TMDR_1, + &MTU2TMDR_2, + &MTU2TMDR_3, + &MTU2TMDR_4, +}; + +static int MAX_PERIOD[] = { + 125000, + 503000, + 2000000, + 2000000, + 2000000, +}; + +typedef enum { + MODE_PWM = 0, + MODE_MTU2 +} PWMmode; + +typedef enum { + MTU2_PULSE = 0, + MTU2_PERIOD +} MTU2Signal; + +static int pwm_mode = MODE_PWM; +static uint16_t init_period_ch1 = 0; +static uint16_t init_period_ch2 = 0; +static uint16_t init_mtu2_period_ch[5] = {0}; +static int32_t period_ch1 = 1; +static int32_t period_ch2 = 1; +static int32_t mtu2_period_ch[5] = {1, 1, 1, 1, 1}; + +void pwmout_init(pwmout_t* obj, PinName pin) { + // determine the channel + PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); + MBED_ASSERT(pwm != (PWMName)NC); + + if (pwm >= MTU2_PWM_OFFSET) { + /* PWM by MTU2 */ + int tmp_pwm; + + pwm_mode = MODE_MTU2; + // power on + CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP33); + + obj->pwm = pwm; + tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET); + if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000040) == 0x00000040) { + obj->ch = 4; + MTU2TOER |= 0x36; + } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000030) == 0x00000030) { + obj->ch = 3; + MTU2TOER |= 0x09; + } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000020) == 0x00000020) { + obj->ch = 2; + } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000010) == 0x00000010) { + obj->ch = 1; + } else { + obj->ch = 0; + } + // Wire pinout + pinmap_pinout(pin, PinMap_PWM); + + int bitmask = 1 << (pin & 0xf); + + *PMSR(PINGROUP(pin)) = (bitmask << 16) | 0; + + // default duty 0.0f + pwmout_write(obj, 0); + if (init_mtu2_period_ch[obj->ch] == 0) { + // default period 1ms + pwmout_period_us(obj, 1000); + init_mtu2_period_ch[obj->ch] = 1; + } + } else { + /* PWM */ + pwm_mode = MODE_PWM; + // power on + CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP30); + + obj->pwm = pwm; + if (((uint32_t)PORT[obj->pwm] & 0x00000010) == 0x00000010) { + obj->ch = 2; + PWMPWPR_2_BYTE_L = 0x00; + } else { + obj->ch = 1; + PWMPWPR_1_BYTE_L = 0x00; + } + + // Wire pinout + pinmap_pinout(pin, PinMap_PWM); + + // default to 491us: standard for servos, and fine for e.g. brightness control + pwmout_write(obj, 0); + if ((obj->ch == 2) && (init_period_ch2 == 0)) { + pwmout_period_us(obj, 491); + init_period_ch2 = 1; + } + if ((obj->ch == 1) && (init_period_ch1 == 0)) { + pwmout_period_us(obj, 491); + init_period_ch1 = 1; + } + } +} + +void pwmout_free(pwmout_t* obj) { + pwmout_write(obj, 0); +} + +void pwmout_write(pwmout_t* obj, float value) { + uint32_t wk_cycle; + uint16_t v; + + if (pwm_mode == MODE_MTU2) { + /* PWM by MTU2 */ + int tmp_pwm; + + if (value < 0.0f) { + value = 0.0f; + } else if (value > 1.0f) { + value = 1.0f; + } else { + // Do Nothing + } + tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET); + wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff; + // set channel match to percentage + *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)((float)wk_cycle * value); + } else { + /* PWM */ + if (value < 0.0f) { + value = 0.0f; + } else if (value > 1.0f) { + value = 1.0f; + } else { + // Do Nothing + } + + if (obj->ch == 2) { + wk_cycle = PWMPWCYR_2 & 0x03ff; + } else { + wk_cycle = PWMPWCYR_1 & 0x03ff; + } + + // set channel match to percentage + v = (uint16_t)((float)wk_cycle * value); + *PWM_MATCH[obj->pwm] = (v | ((PORT[obj->pwm] & 1) << 12)); + } +} + +float pwmout_read(pwmout_t* obj) { + uint32_t wk_cycle; + float value; + + if (pwm_mode == MODE_MTU2) { + /* PWM by MTU2 */ + uint32_t wk_pulse; + int tmp_pwm; + + tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET); + wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff; + wk_pulse = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] & 0xffff; + value = ((float)wk_pulse / (float)wk_cycle); + } else { + /* PWM */ + if (obj->ch == 2) { + wk_cycle = PWMPWCYR_2 & 0x03ff; + } else { + wk_cycle = PWMPWCYR_1 & 0x03ff; + } + value = ((float)(*PWM_MATCH[obj->pwm] & 0x03ff) / (float)wk_cycle); + } + + return (value > 1.0f) ? (1.0f) : (value); +} + +void pwmout_period(pwmout_t* obj, float seconds) { + pwmout_period_us(obj, seconds * 1000000.0f); +} + +void pwmout_period_ms(pwmout_t* obj, int ms) { + pwmout_period_us(obj, ms * 1000); +} + +static void set_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){ + uint16_t wk_pwmpbfr; + float value; + uint16_t v; + + wk_pwmpbfr = *p_pwmpbfr; + value = ((float)(wk_pwmpbfr & 0x03ff) / (float)last_cycle); + v = (uint16_t)((float)new_cycle * value); + *p_pwmpbfr = (v | (wk_pwmpbfr & 0x1000)); +} + +static void set_mtu2_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){ + uint16_t wk_pwmpbfr; + float value; + + wk_pwmpbfr = *p_pwmpbfr; + value = ((float)(wk_pwmpbfr & 0xffff) / (float)last_cycle); + *p_pwmpbfr = (uint16_t)((float)new_cycle * value); +} + +// Set the PWM period, keeping the duty cycle the same. +void pwmout_period_us(pwmout_t* obj, int us) { + uint64_t wk_cycle_mtu2; + uint32_t pclk_base; + uint32_t wk_cycle; + uint32_t wk_cks = 0; + uint16_t wk_last_cycle; + int max_us = 0; + + if (pwm_mode == MODE_MTU2) { + /* PWM by MTU2 */ + int tmp_pwm; + uint16_t tmp_tgra; + uint16_t tmp_tgrc; + uint8_t tmp_tcr_up; + uint8_t tmp_tstr_sp; + uint8_t tmp_tstr_st; + + max_us = MAX_PERIOD[obj->ch]; + if (us > max_us) { + us = max_us; + } else if (us < 1) { + us = 1; + } else { + // Do Nothing + } + + if (RZ_A1_IsClockMode0() == false) { + pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK; + } else { + pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK; + } + + wk_cycle_mtu2 = (uint64_t)pclk_base * us; + while (wk_cycle_mtu2 >= 65535000000) { + if ((obj->ch == 1) && (wk_cks == 3)) { + wk_cks+=2; + } else if ((obj->ch == 2) && (wk_cks == 3)) { + wk_cycle_mtu2 >>= 2; + wk_cks+=3; + } + wk_cycle_mtu2 >>= 2; + wk_cks++; + } + wk_cycle = (uint32_t)(wk_cycle_mtu2 / 1000000); + + tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET); + if (((uint8_t)MTU2_PORT[tmp_pwm] & 0x02) == 0x02) { + tmp_tcr_up = 0xC0; + } else { + tmp_tcr_up = 0x40; + } + if ((obj->ch == 4) || (obj->ch == 3)) { + tmp_tstr_sp = ~(0x38 | (1 << (obj->ch + 3))); + tmp_tstr_st = (1 << (obj->ch + 3)); + } else { + tmp_tstr_sp = ~(0x38 | (1 << obj->ch)); + tmp_tstr_st = (1 << obj->ch); + } + // Counter Stop + MTU2TSTR &= tmp_tstr_sp; + wk_last_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff; + *TCR_MATCH[obj->ch] = tmp_tcr_up | wk_cks; + *TIORH_MATCH[obj->ch] = 0x21; + if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) { + *TIORL_MATCH[obj->ch] = 0x21; + } + *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] = (uint16_t)wk_cycle; // Set period + + // Set duty again(TGRA) + tmp_tgra = *TGRA_MATCH[obj->ch]; + set_mtu2_duty_again(&tmp_tgra, wk_last_cycle, wk_cycle); + if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) { + // Set duty again(TGRC) + tmp_tgrc = *TGRC_MATCH[obj->ch]; + set_mtu2_duty_again(&tmp_tgrc, wk_last_cycle, wk_cycle); + } + *TMDR_MATCH[obj->ch] = 0x02; // PWM mode 1 + + // Counter Start + MTU2TSTR |= tmp_tstr_st; + // Save for future use + mtu2_period_ch[obj->ch] = us; + } else { + /* PWM */ + if (us > 491) { + us = 491; + } else if (us < 1) { + us = 1; + } else { + // Do Nothing + } + + if (RZ_A1_IsClockMode0() == false) { + pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK / 10000; + } else { + pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK / 10000; + } + + wk_cycle = pclk_base * us; + while (wk_cycle >= 102350) { + wk_cycle >>= 1; + wk_cks++; + } + wk_cycle = (wk_cycle + 50) / 100; + + if (obj->ch == 2) { + wk_last_cycle = PWMPWCYR_2 & 0x03ff; + PWMPWCR_2_BYTE_L = 0xc0 | wk_cks; + PWMPWCYR_2 = (uint16_t)wk_cycle; + + // Set duty again + set_duty_again(&PWMPWBFR_2A, wk_last_cycle, wk_cycle); + set_duty_again(&PWMPWBFR_2C, wk_last_cycle, wk_cycle); + set_duty_again(&PWMPWBFR_2E, wk_last_cycle, wk_cycle); + set_duty_again(&PWMPWBFR_2G, wk_last_cycle, wk_cycle); + + // Counter Start + PWMPWCR_2_BYTE_L |= 0x08; + + // Save for future use + period_ch2 = us; + } else { + wk_last_cycle = PWMPWCYR_1 & 0x03ff; + PWMPWCR_1_BYTE_L = 0xc0 | wk_cks; + PWMPWCYR_1 = (uint16_t)wk_cycle; + + // Set duty again + set_duty_again(&PWMPWBFR_1A, wk_last_cycle, wk_cycle); + set_duty_again(&PWMPWBFR_1C, wk_last_cycle, wk_cycle); + set_duty_again(&PWMPWBFR_1E, wk_last_cycle, wk_cycle); + set_duty_again(&PWMPWBFR_1G, wk_last_cycle, wk_cycle); + + // Counter Start + PWMPWCR_1_BYTE_L |= 0x08; + + // Save for future use + period_ch1 = us; + } + } +} + +void pwmout_pulsewidth(pwmout_t* obj, float seconds) { + pwmout_pulsewidth_us(obj, seconds * 1000000.0f); +} + +void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { + pwmout_pulsewidth_us(obj, ms * 1000); +} + +void pwmout_pulsewidth_us(pwmout_t* obj, int us) { + float value = 0; + + if (pwm_mode == MODE_MTU2) { + /* PWM by MTU2 */ + if (mtu2_period_ch[obj->ch] != 0) { + value = (float)us / (float)mtu2_period_ch[obj->ch]; + } + } else { + /* PWM */ + if (obj->ch == 2) { + if (period_ch2 != 0) { + value = (float)us / (float)period_ch2; + } + } else { + if (period_ch1 != 0) { + value = (float)us / (float)period_ch1; + } + } + + pwmout_write(obj, value); + } +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/rtc_api.c Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,408 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed_assert.h" +#include "device.h" + +#if DEVICE_RTC + +#define USE_RTCX1_CLK +//#define USE_EXTAL_CLK +//#define USE_RTCX3_CLK + +#include "rtc_api.h" +#include "rtc_iodefine.h" + + +#define RCR1_VAL_ON (0x08u) // AIE = 1 +#define RCR1_VAL_OFF (0x00u) +#define RCR3_VAL (0x00u) +#define RCR5_VAL (0x00u) + +#ifdef USE_RTCX1_CLK +#define RCR2_VAL_ALLSTOP (0x08u) +#define RCR2_VAL_START (0x09u) // START = 1 +#define RCR2_VAL_RESET (0x0Au) // RESET = 1 +#define RCR5_VAL_RTCX1 (0x00u) // RCKSEL = clock rtc from RTCX1(32.768 kHz) +#elif defined(USE_EXTAL_CLK) +#define RCR2_VAL_ALLSTOP (0x00u) +#define RCR2_VAL_START (0x01u) // START = 1 +#define RCR2_VAL_RESET (0x02u) // RESET = 1 +#define RCR5_VAL_EXTAL (0x01u) // RCKSEL = clock rtc from EXTAL +#define RFRH_VAL_13333 (0x8003u) // 13.3333MHz (= 64Hz * 0x32DCD) +#define RFRL_VAL_13333 (0x2DCDu) // +#elif defined(USE_RTCX3_CLK) +#define RCR2_VAL_ALLSTOP (0x08u) +#define RCR2_VAL_START (0x09u) // START = 1 +#define RCR2_VAL_RESET (0x0Au) // RESET = 1 +#define RCR5_VAL_RTCX3 (0x02u) // RCKSEL = clock rtc from RTCX3(4.000 MHz) +#define RFRH_VAL_4000 (0x8000u) // 4.000MHz (= 64Hz * 0xF424) +#define RFRL_VAL_4000 (0xF424u) // +#else +#error Select RTC clock input ! +#endif + +#define RFRH_VAL_MAX (0x0007u) // MAX value (= 128Hz * 0x7FFFF) +#define RFRL_VAL_MAX (0xFFFFu) // + +#define MASK_00_03_POS (0x000Fu) +#define MASK_04_07_POS (0x00F0u) +#define MASK_08_11_POS (0x0F00u) +#define MASK_12_15_POS (0xF000u) +#define MASK_16_20_POS (0x000F0000u) +#define SHIFT_1_HBYTE (4u) +#define SHIFT_2_HBYTE (8u) +#define SHIFT_3_HBYTE (12u) +#define SHIFT_1BYTE (8u) +#define SHIFT_2BYTE (16u) + +#define TIME_ERROR_VAL (0xFFFFFFFFu) + +static int rtc_dec8_to_hex(uint8_t dec_val, uint8_t offset, int *hex_val); +static int rtc_dec16_to_hex(uint16_t dec_val, uint16_t offset, int *hex_val); +static uint8_t rtc_hex8_to_dec(uint8_t hex_val); +static uint16_t rtc_hex16_to_dec(uint16_t hex_val); + + +/* + * Setup the RTC based on a time structure. + * The rtc_init function should be executed first. + * [in] + * None. + * [out] + * None. + */ +void rtc_init(void) { + volatile uint8_t dummy_read; + + CPG.STBCR6 &= ~(CPG_STBCR6_BIT_MSTP60); + + // Set control register + RTC.RCR2 = RCR2_VAL_ALLSTOP; + RTC.RCR1 = RCR1_VAL_ON; + RTC.RCR3 = RCR3_VAL; + +#ifdef USE_RTCX1_CLK + RTC.RCR5 = RCR5_VAL_RTCX1; + RTC.RFRH = 0; + RTC.RFRL = 0; +#elif defined(USE_EXTAL_CLK) + RTC.RCR5 = RCR5_VAL_EXTAL; + RTC.RFRH = RFRH_VAL_13333; + RTC.RFRL = RFRL_VAL_13333; +#else + RTC.RCR5 = RCR5_VAL_RTCX3; + RTC.RFRH = RFRH_VAL_4000; + RTC.RFRL = RFRL_VAL_4000; +#endif + // Dummy read + dummy_read = RTC.RCR2; + dummy_read = RTC.RCR2; + + RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1 + + // Dummy read + dummy_read = RTC.RCR2; + dummy_read = RTC.RCR2; + + // Set timer and alarm. Default value :01-01-1970 00:00:00 + RTC.RSECCNT = 0; + RTC.RMINCNT = 0; + RTC.RHRCNT = 0; + RTC.RWKCNT = 0; + RTC.RDAYCNT = 1; + RTC.RMONCNT = 1; + RTC.RYRCNT = 0x1970; + RTC.RSECAR = 0; + RTC.RMINAR = 0; + RTC.RHRAR = 0; + RTC.RWKAR = 0; + RTC.RDAYAR = 1; + RTC.RMONAR = 1; + RTC.RYRAR = 0x1970; + + // Dummy read + dummy_read = RTC.RYRCNT; + dummy_read = RTC.RYRCNT; + +} + + +/* + * Release the RTC based on a time structure. + * [in] + * None. + * [out] + * None. + */ +void rtc_free(void) { + volatile uint8_t dummy_read; + + // Set control register + RTC.RCR2 = RCR2_VAL_ALLSTOP; + RTC.RCR1 = RCR1_VAL_OFF; + RTC.RCR3 = RCR3_VAL; + RTC.RCR5 = RCR5_VAL; + RTC.RFRH = RFRH_VAL_MAX; + RTC.RFRL = RFRL_VAL_MAX; + + // Dummy read + dummy_read = RTC.RCR2; + dummy_read = RTC.RCR2; + RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1 + + // Dummy read + dummy_read = RTC.RCR2; + dummy_read = RTC.RCR2; + + // Set timer and alarm. Default value :01-01-1970 00:00:00 + RTC.RSECCNT = 0; + RTC.RMINCNT = 0; + RTC.RHRCNT = 0; + RTC.RWKCNT = 0; + RTC.RDAYCNT = 1; + RTC.RMONCNT = 1; + RTC.RYRCNT = 0x1970; + RTC.RSECAR = 0; + RTC.RMINAR = 0; + RTC.RHRAR = 0; + RTC.RWKAR = 0; + RTC.RDAYAR = 1; + RTC.RMONAR = 1; + RTC.RYRAR = 0x1970; + + // Dummy read + dummy_read = RTC.RYRCNT; + dummy_read = RTC.RYRCNT; + +} + + +/* + * Check the RTC has been enabled. + * Clock Control Register RTC.RCR1(bit3): 0 = Disabled, 1 = Enabled. + * [in] + * None. + * [out] + * 0:Disabled, 1:Enabled. + */ +int rtc_isenabled(void) { + int ret_val = 0; + + if ((RTC.RCR1 & RCR1_VAL_ON) != 0) { // RTC ON ? + ret_val = 1; + } + + return ret_val; +} + + +/* + * RTC read function. + * [in] + * None. + * [out] + * UNIX timestamp value. + */ +time_t rtc_read(void) { + + struct tm timeinfo; + int err = 0; + uint8_t tmp_regdata; + time_t t; + + if (rtc_isenabled() != 0) { + RTC.RCR1 &= ~0x10u; // CIE = 0 + do { + // before reading process + tmp_regdata = RTC.RCR1; + tmp_regdata &= ~0x80u; // CF = 0 + tmp_regdata |= 0x01u; // AF = 1 + RTC.RCR1 = tmp_regdata; + + // Read RTC register + err = rtc_dec8_to_hex(RTC.RSECCNT , 0 , &timeinfo.tm_sec); + err += rtc_dec8_to_hex(RTC.RMINCNT , 0 , &timeinfo.tm_min); + err += rtc_dec8_to_hex(RTC.RHRCNT , 0 , &timeinfo.tm_hour); + err += rtc_dec8_to_hex(RTC.RDAYCNT , 0 , &timeinfo.tm_mday); + err += rtc_dec8_to_hex(RTC.RMONCNT , 1 , &timeinfo.tm_mon); + err += rtc_dec16_to_hex(RTC.RYRCNT , 1900 , &timeinfo.tm_year); + } while ((RTC.RCR1 & 0x80u) != 0); + } else { + err = 1; + } + + if (err == 0) { + // Convert to timestamp + t = mktime(&timeinfo); + } else { + // Error + t = TIME_ERROR_VAL; + } + + return t; +} + +/* + * Dec(8bit) to Hex function for RTC. + * [in] + * dec_val:Decimal value (from 0x00 to 0x99). + * offset:Subtract offset from dec_val. + * hex_val:Pointer of output hexadecimal value. + * [out] + * 0:Success + * 1:Error + */ +static int rtc_dec8_to_hex(uint8_t dec_val, uint8_t offset, int *hex_val) { + int err = 0; + uint8_t ret_val; + + if (hex_val != NULL) { + if (((dec_val & MASK_04_07_POS) >= (0x0A << SHIFT_1_HBYTE)) || + ((dec_val & MASK_00_03_POS) >= 0x0A)) { + err = 1; + } else { + ret_val = ((dec_val & MASK_04_07_POS) >> SHIFT_1_HBYTE) * 10 + + (dec_val & MASK_00_03_POS); + if (ret_val < offset) { + err = 1; + } else { + *hex_val = ret_val - offset; + } + } + } else { + err = 1; + } + + return err; +} + +/* + * Dec(16bit) to Hex function for RTC + * [in] + * dec_val:Decimal value (from 0x0000 to 0x9999). + * offset:Subtract offset from dec_val. + * hex_val:Pointer of output hexadecimal value. + * [out] + * 0:Success + * 1:Error + */ +static int rtc_dec16_to_hex(uint16_t dec_val, uint16_t offset, int *hex_val) { + int err = 0; + uint16_t ret_val; + + if (hex_val != NULL) { + if (((dec_val & MASK_12_15_POS) >= (0x0A << SHIFT_3_HBYTE)) || + ((dec_val & MASK_08_11_POS) >= (0x0A << SHIFT_2_HBYTE)) || + ((dec_val & MASK_04_07_POS) >= (0x0A << SHIFT_1_HBYTE)) || + ((dec_val & MASK_00_03_POS) >= 0x0A)) { + err = 1; + *hex_val = 0; + } else { + ret_val = (((dec_val & MASK_12_15_POS)) >> SHIFT_3_HBYTE) * 1000 + + (((dec_val & MASK_08_11_POS)) >> SHIFT_2_HBYTE) * 100 + + (((dec_val & MASK_04_07_POS)) >> SHIFT_1_HBYTE) * 10 + + (dec_val & MASK_00_03_POS); + if (ret_val < offset) { + err = 1; + } else { + *hex_val = ret_val - offset; + } + } + } else { + err = 1; + } + return err; +} + +/* + * RTC write function + * [in] + * t:UNIX timestamp value + * [out] + * None. + */ +void rtc_write(time_t t) { + + struct tm *timeinfo = localtime(&t); + volatile uint16_t dummy_read; + + if (rtc_isenabled() != 0) { + RTC.RCR2 = RCR2_VAL_ALLSTOP; + dummy_read = (uint16_t)RTC.RCR2; + dummy_read = (uint16_t)RTC.RCR2; + RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1 + dummy_read = (uint16_t)RTC.RCR2; + dummy_read = (uint16_t)RTC.RCR2; + + RTC.RSECCNT = rtc_hex8_to_dec(timeinfo->tm_sec); + RTC.RMINCNT = rtc_hex8_to_dec(timeinfo->tm_min); + RTC.RHRCNT = rtc_hex8_to_dec(timeinfo->tm_hour); + RTC.RDAYCNT = rtc_hex8_to_dec(timeinfo->tm_mday); + RTC.RMONCNT = rtc_hex8_to_dec(timeinfo->tm_mon + 1); + RTC.RYRCNT = rtc_hex16_to_dec(timeinfo->tm_year + 1900); + dummy_read = (uint16_t)RTC.RYRCNT; + dummy_read = (uint16_t)RTC.RYRCNT; + + RTC.RCR2 = RCR2_VAL_START; // START = 1 + + dummy_read = (uint16_t)RTC.RCR2; + dummy_read = (uint16_t)RTC.RCR2; + } +} + +/* + * HEX to Dec(8bit) function for RTC. + * [in] + * hex_val:Hexadecimal value. + * [out] + * decimal value:From 0x00 to 0x99. + */ +static uint8_t rtc_hex8_to_dec(uint8_t hex_val) { + uint32_t calc_data; + + calc_data = hex_val / 10 * 0x10; + calc_data += hex_val % 10; + + if (calc_data > 0x99) { + calc_data = 0; + } + + return (uint8_t)calc_data; +} + +/* + * HEX to Dec(16bit) function for RTC. + * [in] + * hex_val:Hexadecimal value. + * [out] + * decimal value:From 0x0000 to 0x9999. + */ +static uint16_t rtc_hex16_to_dec(uint16_t hex_val) { + uint32_t calc_data; + calc_data = hex_val / 1000 * 0x1000; + calc_data += ((hex_val / 100) % 10) * 0x100; + calc_data += ((hex_val / 10) % 10) * 0x10; + calc_data += hex_val % 10; + + if (calc_data > 0x9999) { + calc_data = 0; + } + return (uint16_t)calc_data; + +} + +#endif /* DEVICE_RTC */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/serial_api.c Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,732 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// math.h required for floating point operations for baud rate calculation +#include "mbed_assert.h" +#include <math.h> +#include <string.h> +#include <stdlib.h> + +#include "serial_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "gpio_api.h" + +#include "scif_iodefine.h" +#include "cpg_iodefine.h" + +/****************************************************************************** + * INITIALIZATION + ******************************************************************************/ +#define PCLK (66666666) // Define the peripheral clock P1 frequency. + +#define UART_NUM 8 +#define IRQ_NUM 2 + +static void uart0_tx_irq(void); +static void uart1_tx_irq(void); +static void uart2_tx_irq(void); +static void uart3_tx_irq(void); +static void uart4_tx_irq(void); +static void uart5_tx_irq(void); +static void uart6_tx_irq(void); +static void uart7_tx_irq(void); +static void uart0_rx_irq(void); +static void uart1_rx_irq(void); +static void uart2_rx_irq(void); +static void uart3_rx_irq(void); +static void uart4_rx_irq(void); +static void uart5_rx_irq(void); +static void uart6_rx_irq(void); +static void uart7_rx_irq(void); + +#ifdef MAX_PERI +static const PinMap PinMap_UART_TX[] = { + {P2_14 , UART0, 6}, + {P4_9 , UART0, 7}, + {P6_9 , UART0, 5}, + {P2_5 , UART1, 6}, + {P4_12 , UART1, 7}, + {P6_12 , UART1, 5}, + {P9_3 , UART1, 4}, + {P3_0 , UART2, 6}, + {P3_1 , UART2, 4}, + {P4_2 , UART2, 5}, + {P4_14 , UART2, 7}, + {P6_3 , UART2, 7}, + {P8_6 , UART2, 7}, + {P3_5 , UART3, 7}, + {P5_3 , UART3, 5}, + {P6_1 , UART3, 7}, + {P8_8 , UART3, 7}, + {P5_0 , UART4, 5}, + {P7_1 , UART4, 4}, + {P8_14 , UART4, 7}, + {P6_6 , UART5, 5}, + {P8_1 , UART5, 4}, + {P8_13 , UART5, 5}, + {P5_6 , UART6, 5}, + {P6_14 , UART6, 4}, + {P7_4 , UART7, 4}, + {NC , NC , 0} +}; + +static const PinMap PinMap_UART_RX[] = { + {P2_15 , UART0, 6}, + {P4_10 , UART0, 7}, + {P6_10 , UART0, 5}, + {P2_6 , UART1, 6}, + {P4_13 , UART1, 7}, + {P6_13 , UART1, 5}, + {P9_4 , UART1, 4}, + {P3_2 , UART2, 4}, + {P4_3 , UART2, 5}, + {P4_15 , UART2, 7}, + {P6_2 , UART2, 7}, + {P8_4 , UART2, 7}, + {P3_6 , UART3, 7}, + {P5_4 , UART3, 5}, + {P6_0 , UART3, 7}, + {P8_9 , UART3, 7}, + {P5_1 , UART4, 5}, + {P7_2 , UART4, 4}, + {P8_15 , UART4, 7}, + {P6_7 , UART5, 5}, + {P8_2 , UART5, 4}, + {P8_11 , UART5, 5}, + {P5_7 , UART6, 5}, + {P6_15 , UART6, 4}, + {P7_5 , UART7, 4}, + {NC , NC , 0} +}; + +static const PinMap PinMap_UART_CTS[] = { + {P2_3 , UART1, 6}, + {P9_5 , UART1, 4}, + {P6_3 , UART5, 5}, + {P7_15 , UART5, 4}, + {P7_6 , UART7, 4}, + {NC , NC , 0} +}; +static const PinMap PinMap_UART_RTS[] = { + {P2_7 , UART1, 6}, + {P9_6 , UART1, 4}, + {P6_4 , UART5, 5}, + {P8_3 , UART5, 4}, + {P7_7 , UART7, 4}, + {NC , NC , 0} +}; +#else +static const PinMap PinMap_UART_TX[] = { + {P3_0 , UART2, 6}, + {P3_1 , UART2, 4}, + {P4_2 , UART2, 5}, + {P5_3 , UART3, 5}, + {P8_8 , UART3, 7}, + {P5_0 , UART4, 5}, + {P8_14 , UART4, 7}, + {P8_13 , UART5, 5}, + {P5_6 , UART6, 5}, + {NC , NC , 0} +}; + +static const PinMap PinMap_UART_RX[] = { + {P3_2 , UART2, 4}, + {P4_3 , UART2, 5}, + {P5_4 , UART3, 5}, + {P8_9 , UART3, 7}, + {P5_1 , UART4, 5}, + {P8_15 , UART4, 7}, + {P8_11 , UART5, 5}, + {P5_7 , UART6, 5}, + {NC , NC , 0} +}; + +static const PinMap PinMap_UART_CTS[] = { + {NC , NC , 0} +}; +static const PinMap PinMap_UART_RTS[] = { + {NC , NC , 0} +}; +#endif + +static const struct st_scif *SCIF[] = SCIF_ADDRESS_LIST; +static uart_irq_handler irq_handler; + +int stdio_uart_inited = 0; +serial_t stdio_uart; + +struct serial_global_data_s { + uint32_t serial_irq_id; + gpio_t sw_rts, sw_cts; + uint8_t count, rx_irq_set_flow, rx_irq_set_api; +}; + +static struct serial_global_data_s uart_data[UART_NUM]; + +static const IRQn_Type irq_set_tbl[UART_NUM][IRQ_NUM] = { + {SCIFRXI0_IRQn, SCIFTXI0_IRQn}, + {SCIFRXI1_IRQn, SCIFTXI1_IRQn}, + {SCIFRXI2_IRQn, SCIFTXI2_IRQn}, + {SCIFRXI3_IRQn, SCIFTXI3_IRQn}, + {SCIFRXI4_IRQn, SCIFTXI4_IRQn}, + {SCIFRXI5_IRQn, SCIFTXI5_IRQn}, + {SCIFRXI6_IRQn, SCIFTXI6_IRQn}, + {SCIFRXI7_IRQn, SCIFTXI7_IRQn} +}; + +static const IRQHandler hander_set_tbl[UART_NUM][IRQ_NUM] = { + {uart0_rx_irq, uart0_tx_irq}, + {uart1_rx_irq, uart1_tx_irq}, + {uart2_rx_irq, uart2_tx_irq}, + {uart3_rx_irq, uart3_tx_irq}, + {uart4_rx_irq, uart4_tx_irq}, + {uart5_rx_irq, uart5_tx_irq}, + {uart6_rx_irq, uart6_tx_irq}, + {uart7_rx_irq, uart7_tx_irq} +}; + +static __IO uint16_t *SCSCR_MATCH[] = { + &SCSCR_0, + &SCSCR_1, + &SCSCR_2, + &SCSCR_3, + &SCSCR_4, + &SCSCR_5, + &SCSCR_6, + &SCSCR_7, +}; + +static __IO uint16_t *SCFSR_MATCH[] = { + &SCFSR_0, + &SCFSR_1, + &SCFSR_2, + &SCFSR_3, + &SCFSR_4, + &SCFSR_5, + &SCFSR_6, + &SCFSR_7, +}; + + +void serial_init(serial_t *obj, PinName tx, PinName rx) { + volatile uint8_t dummy ; + int is_stdio_uart = 0; + // determine the UART to use + uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); + uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); + uint32_t uart = pinmap_merge(uart_tx, uart_rx); + + MBED_ASSERT((int)uart != NC); + + obj->uart = (struct st_scif *)SCIF[uart]; + // enable power + switch (uart) { + case UART0: + CPG.STBCR4 &= ~(1 << 7); + break; + case UART1: + CPG.STBCR4 &= ~(1 << 6); + break; + case UART2: + CPG.STBCR4 &= ~(1 << 5); + break; + case UART3: + CPG.STBCR4 &= ~(1 << 4); + break; + case UART4: + CPG.STBCR4 &= ~(1 << 3); + break; + case UART5: + CPG.STBCR4 &= ~(1 << 2); + break; + case UART6: + CPG.STBCR4 &= ~(1 << 1); + break; + case UART7: + CPG.STBCR4 &= ~(1 << 0); + break; + } + dummy = CPG.STBCR4; + + /* if this uart has been previously configured to tx, wait tx completion befor loading new configuration */ + if(obj->uart->SCSCR & 0xA0) + while(!(obj->uart->SCFSR & 0x0040)); + + /* ==== SCIF initial setting ==== */ + /* ---- Serial control register (SCSCR) setting ---- */ + /* B'00 : Internal CLK */ + obj->uart->SCSCR = 0x0000u; /* SCIF transmitting and receiving operations stop */ + + /* ---- FIFO control register (SCFCR) setting ---- */ + /* Transmit FIFO reset & Receive FIFO data register reset */ + obj->uart->SCFCR = 0x0006; + + /* ---- Serial status register (SCFSR) setting ---- */ + dummy = obj->uart->SCFSR; + obj->uart->SCFSR = (dummy & 0xFF6Cu); /* ER,BRK,DR bit clear */ + + /* ---- Line status register (SCLSR) setting ---- */ + /* ORER bit clear */ + obj->uart->SCLSR = 0; + + /* ---- Serial extension mode register (SCEMR) setting ---- + b7 BGDM - Baud rate generator double-speed mode : Normal mode + b0 ABCS - Base clock select in asynchronous mode : Base clock is 16 times the bit rate */ + obj->uart->SCEMR = 0x0000u; + + /* ---- Bit rate register (SCBRR) setting ---- */ + serial_baud (obj, 9600); + serial_format(obj, 8, ParityNone, 1); + + /* ---- FIFO control register (SCFCR) setting ---- */ + obj->uart->SCFCR = 0x0030u; + + /* ---- Serial port register (SCSPTR) setting ---- + b1 SPB2IO - Serial port break output : disabled + b0 SPB2DT - Serial port break data : High-level */ + obj->uart->SCSPTR = 0x0003u; // SPB2IO = 1, SPB2DT = 1 + + /* ---- Line status register (SCLSR) setting ---- + b0 ORER - Overrun error detect : clear */ + + if (obj->uart->SCLSR & 0x0001) { + obj->uart->SCLSR = 0u; // ORER clear + } + + // pinout the chosen uart + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + switch (uart) { + case UART0: + obj->index = 0; + break; + case UART1: + obj->index = 1; + break; + case UART2: + obj->index = 2; + break; + case UART3: + obj->index = 3; + break; + case UART4: + obj->index = 4; + break; + case UART5: + obj->index = 5; + break; + case UART6: + obj->index = 6; + break; + case UART7: + obj->index = 7; + break; + } + uart_data[obj->index].sw_rts.pin = NC; + uart_data[obj->index].sw_cts.pin = NC; + + /* ---- Serial control register (SCSCR) setting ---- */ + /* Setting the TE and RE bits enables the TxD and RxD pins to be used. */ + obj->uart->SCSCR = (((uart_tx != (uint32_t)NC)? 0xA0 : 0) | ((uart_rx != (uint32_t)NC)? 0x50 : 0 )); //0x00F0; + + is_stdio_uart = (uart == STDIO_UART) ? (1) : (0); + + if (is_stdio_uart) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj) { + uart_data[obj->index].serial_irq_id = 0; +} + +// serial_baud +// set the baud rate, taking in to account the current SystemFrequency +void serial_baud(serial_t *obj, int baudrate) { + uint16_t DL; + + obj->uart->SCSMR &= ~0x0003; + + if (baudrate > 32552) { + obj->uart->SCEMR = 0x0081; // BGDM = 1, ABCS = 1 + DL = PCLK / (8 * baudrate); + if (DL > 0) { + DL--; + } + obj->uart->SCBRR = (uint8_t)DL; + } else if (baudrate > 16276) { + obj->uart->SCEMR = 0x0080; // BGDM = 1 + obj->uart->SCBRR = PCLK / (16 * baudrate) - 1; + } else if (baudrate > 8138) { + obj->uart->SCEMR = 0x0000; + obj->uart->SCBRR = PCLK / (32 * baudrate) - 1; + } else if (baudrate > 4169) { + obj->uart->SCSMR |= 0x0001; + obj->uart->SCEMR = 0x0080; // BGDM = 1 + obj->uart->SCBRR = PCLK / (64 * baudrate) - 1; + } else if (baudrate > 2034) { + obj->uart->SCSMR |= 0x0001; + obj->uart->SCEMR = 0x0000; + obj->uart->SCBRR = PCLK / (128 * baudrate) - 1; + } else if (baudrate > 1017) { + obj->uart->SCSMR |= 0x0002; + obj->uart->SCEMR = 0x0080; // BGDM = 1 + obj->uart->SCBRR = PCLK / (256 * baudrate) - 1; + } else if (baudrate > 508) { + obj->uart->SCSMR |= 0x0002; + obj->uart->SCEMR = 0x0000; + obj->uart->SCBRR = PCLK / (512 * baudrate) - 1; + } else if (baudrate > 254) { + obj->uart->SCSMR |= 0x0003; + obj->uart->SCEMR = 0x0080; // BGDM = 1 + obj->uart->SCBRR = PCLK / (1024 * baudrate) - 1; + } else if (baudrate > 127) { + obj->uart->SCSMR |= 0x0003; + obj->uart->SCEMR = 0x0000; + obj->uart->SCBRR = PCLK / (2048 * baudrate) - 1; + } else { + obj->uart->SCSMR |= 0x0003; + obj->uart->SCEMR = 0x0000; + obj->uart->SCBRR = 0xFFu; + } +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { + int parity_enable; + int parity_select; + + MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits + MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 5: 5 data bits ... 3: 8 data bits + MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || + (parity == ParityForced1) || (parity == ParityForced0)); + + stop_bits = (stop_bits == 1)? 0: + (stop_bits == 2)? 1: + 0; // must not to be + + data_bits = (data_bits == 8)? 0: + (data_bits == 7)? 1: + 0; // must not to be + + switch (parity) { + case ParityNone: + parity_enable = 0; + parity_select = 0; + break; + case ParityOdd: + parity_enable = 1; + parity_select = 1; + break; + case ParityEven: + parity_enable = 1; + parity_select = 0; + break; + case ParityForced1: + case ParityForced0: + default: + parity_enable = 0; + parity_select = 0; + break; + } + + obj->uart->SCSMR = data_bits << 6 + | parity_enable << 5 + | parity_select << 4 + | stop_bits << 3; +} + +/****************************************************************************** + * INTERRUPTS HANDLING + ******************************************************************************/ + +static void uart_tx_irq(IRQn_Type irq_num, uint32_t index) { + __IO uint16_t *dmy_rd_scscr; + __IO uint16_t *dmy_rd_scfsr; + + dmy_rd_scscr = SCSCR_MATCH[index]; + *dmy_rd_scscr &= 0x007B; // Clear TIE and Write to bit15~8,2 is always 0 + dmy_rd_scfsr = SCFSR_MATCH[index]; + *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0020); // Clear TDFE + + irq_handler(uart_data[index].serial_irq_id, TxIrq); +} + +static void uart_rx_irq(IRQn_Type irq_num, uint32_t index) { + __IO uint16_t *dmy_rd_scscr; + __IO uint16_t *dmy_rd_scfsr; + + dmy_rd_scscr = SCSCR_MATCH[index]; + *dmy_rd_scscr &= 0x00B3; // Clear RIE,REIE and Write to bit15~8,2 is always 0 + dmy_rd_scfsr = SCFSR_MATCH[index]; + *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0003); // Clear RDF,DR + + irq_handler(uart_data[index].serial_irq_id, RxIrq); +} + +/* TX handler */ +static void uart0_tx_irq(void) { + uart_tx_irq(SCIFTXI0_IRQn, 0); +} +static void uart1_tx_irq(void) { + uart_tx_irq(SCIFTXI1_IRQn, 1); +} +static void uart2_tx_irq(void) { + uart_tx_irq(SCIFTXI2_IRQn, 2); +} +static void uart3_tx_irq(void) { + uart_tx_irq(SCIFTXI3_IRQn, 3); +} +static void uart4_tx_irq(void) { + uart_tx_irq(SCIFTXI4_IRQn, 4); +} +static void uart5_tx_irq(void) { + uart_tx_irq(SCIFTXI5_IRQn, 5); +} +static void uart6_tx_irq(void) { + uart_tx_irq(SCIFTXI6_IRQn, 6); +} +static void uart7_tx_irq(void) { + uart_tx_irq(SCIFTXI7_IRQn, 7); +} +/* RX handler */ +static void uart0_rx_irq(void) { + uart_rx_irq(SCIFRXI0_IRQn, 0); +} +static void uart1_rx_irq(void) { + uart_rx_irq(SCIFRXI1_IRQn, 1); +} +static void uart2_rx_irq(void) { + uart_rx_irq(SCIFRXI2_IRQn, 2); +} +static void uart3_rx_irq(void) { + uart_rx_irq(SCIFRXI3_IRQn, 3); +} +static void uart4_rx_irq(void) { + uart_rx_irq(SCIFRXI4_IRQn, 4); +} +static void uart5_rx_irq(void) { + uart_rx_irq(SCIFRXI5_IRQn, 5); +} +static void uart6_rx_irq(void) { + uart_rx_irq(SCIFRXI6_IRQn, 6); +} +static void uart7_rx_irq(void) { + uart_rx_irq(SCIFRXI7_IRQn, 7); +} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { + irq_handler = handler; + uart_data[obj->index].serial_irq_id = id; +} + +static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) { + IRQn_Type IRQn; + IRQHandler handler; + + IRQn = irq_set_tbl[obj->index][irq]; + handler = hander_set_tbl[obj->index][irq]; + + if ((obj->index >= 0) && (obj->index <= 7)) { + if (enable) { + InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler); + GIC_SetPriority(IRQn, 5); + GIC_EnableIRQ(IRQn); + } else { + GIC_DisableIRQ(IRQn); + } + } +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { + if (RxIrq == irq) { + uart_data[obj->index].rx_irq_set_api = enable; + } + serial_irq_set_internal(obj, irq, enable); +} + +static void serial_flow_irq_set(serial_t *obj, uint32_t enable) { + uart_data[obj->index].rx_irq_set_flow = enable; + serial_irq_set_internal(obj, RxIrq, enable); +} + +/****************************************************************************** + * READ/WRITE + ******************************************************************************/ +int serial_getc(serial_t *obj) { + uint16_t err_read; + int data; + int was_masked; + +#if defined ( __ICCARM__ ) + was_masked = __disable_irq_iar(); +#else + was_masked = __disable_irq(); +#endif /* __ICCARM__ */ + if (obj->uart->SCFSR & 0x93) { + err_read = obj->uart->SCFSR; + obj->uart->SCFSR = (err_read & ~0x93); + } + obj->uart->SCSCR |= 0x0040; // Set RIE + if (!was_masked) { + __enable_irq(); + } + + if (obj->uart->SCLSR & 0x0001) { + obj->uart->SCLSR = 0u; // ORER clear + } + + while (!serial_readable(obj)); + data = obj->uart->SCFRDR & 0xff; + +#if defined ( __ICCARM__ ) + was_masked = __disable_irq_iar(); +#else + was_masked = __disable_irq(); +#endif /* __ICCARM__ */ + err_read = obj->uart->SCFSR; + obj->uart->SCFSR = (err_read & 0xfffD); // Clear RDF + if (!was_masked) { + __enable_irq(); + } + + if (err_read & 0x80) { + data = -1; //err + } + return data; +} + +void serial_putc(serial_t *obj, int c) { + uint16_t dummy_read; + int was_masked; + +#if defined ( __ICCARM__ ) + was_masked = __disable_irq_iar(); +#else + was_masked = __disable_irq(); +#endif /* __ICCARM__ */ + obj->uart->SCSCR |= 0x0080; // Set TIE + if (!was_masked) { + __enable_irq(); + } + while (!serial_writable(obj)); + obj->uart->SCFTDR = c; +#if defined ( __ICCARM__ ) + was_masked = __disable_irq_iar(); +#else + was_masked = __disable_irq(); +#endif /* __ICCARM__ */ + dummy_read = obj->uart->SCFSR; + obj->uart->SCFSR = (dummy_read & 0xff9f); // Clear TEND/TDFE + if (!was_masked) { + __enable_irq(); + } + uart_data[obj->index].count++; +} + +int serial_readable(serial_t *obj) { + return ((obj->uart->SCFSR & 0x02) != 0); // RDF +} + +int serial_writable(serial_t *obj) { + return ((obj->uart->SCFSR & 0x20) != 0); // TDFE +} + +void serial_clear(serial_t *obj) { + int was_masked; +#if defined ( __ICCARM__ ) + was_masked = __disable_irq_iar(); +#else + was_masked = __disable_irq(); +#endif /* __ICCARM__ */ + + obj->uart->SCFCR |= 0x06; // TFRST = 1, RFRST = 1 + obj->uart->SCFCR &= ~0x06; // TFRST = 0, RFRST = 0 + obj->uart->SCFSR &= ~0x0093u; // ER, BRK, RDF, DR = 0 + + if (!was_masked) { + __enable_irq(); + } +} + +void serial_pinout_tx(PinName tx) { + pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) { + int was_masked; +#if defined ( __ICCARM__ ) + was_masked = __disable_irq_iar(); +#else + was_masked = __disable_irq(); +#endif /* __ICCARM__ */ + // TxD Output(L) + obj->uart->SCSPTR &= ~0x0001u; // SPB2DT = 0 + obj->uart->SCSCR &= ~0x0020u; // TE = 0 (Output disable) + if (!was_masked) { + __enable_irq(); + } +} + +void serial_break_clear(serial_t *obj) { + int was_masked; +#if defined ( __ICCARM__ ) + was_masked = __disable_irq_iar(); +#else + was_masked = __disable_irq(); +#endif /* __ICCARM__ */ + obj->uart->SCSCR |= 0x0020u; // TE = 1 (Output enable) + obj->uart->SCSPTR |= 0x0001u; // SPB2DT = 1 + if (!was_masked) { + __enable_irq(); + } +} + +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) { + // determine the UART to use + int was_masked; + + serial_flow_irq_set(obj, 0); + + if (type == FlowControlRTSCTS) { +#if defined ( __ICCARM__ ) + was_masked = __disable_irq_iar(); +#else + was_masked = __disable_irq(); +#endif /* __ICCARM__ */ + obj->uart->SCFCR = 0x0008u; // CTS/RTS enable + if (!was_masked) { + __enable_irq(); + } + pinmap_pinout(rxflow, PinMap_UART_RTS); + pinmap_pinout(txflow, PinMap_UART_CTS); + } else { +#if defined ( __ICCARM__ ) + was_masked = __disable_irq_iar(); +#else + was_masked = __disable_irq(); +#endif /* __ICCARM__ */ + obj->uart->SCFCR = 0x0000u; // CTS/RTS diable + if (!was_masked) { + __enable_irq(); + } + } +} + + + +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/spi_api.c Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,328 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include <math.h> + +#include "spi_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "RZ_A1_Init.h" + + +#ifdef MAX_PERI +static const PinMap PinMap_SPI_SCLK[] = { + {P2_12 , SPI_0, 2}, + {P7_15 , SPI_0, 2}, + {P4_4 , SPI_1, 2}, + {P6_4 , SPI_1, 7}, + {P8_3 , SPI_2, 3}, + {P8_14 , SPI_2, 5}, + {P3_0 , SPI_3, 8}, + {P5_0 , SPI_3, 8}, + {P2_8 , SPI_4, 8}, + {P4_0 , SPI_4, 7}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_SSEL[] = { + {P2_13 , SPI_0, 2}, + {P8_0 , SPI_0, 2}, + {P4_5 , SPI_1, 2}, + {P6_5 , SPI_1, 7}, + {P8_4 , SPI_2, 3}, + {P8_15 , SPI_2, 5}, + {P3_1 , SPI_3, 8}, + {P5_1 , SPI_3, 8}, + {P2_9 , SPI_4, 8}, + {P4_1 , SPI_4, 7}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_MOSI[] = { + {P2_14 , SPI_0, 2}, + {P8_1 , SPI_0, 2}, + {P4_6 , SPI_1, 2}, + {P6_6 , SPI_1, 7}, + {P8_5 , SPI_2, 3}, + {P9_0 , SPI_2, 5}, + {P3_2 , SPI_3, 8}, + {P5_2 , SPI_3, 8}, + {P2_10 , SPI_4, 8}, + {P4_2 , SPI_4, 7}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_MISO[] = { + {P2_15 , SPI_0, 2}, + {P8_2 , SPI_0, 2}, + {P4_7 , SPI_1, 2}, + {P6_7 , SPI_1, 7}, + {P8_6 , SPI_2, 3}, + {P9_1 , SPI_2, 5}, + {P3_3 , SPI_3, 8}, + {P5_3 , SPI_3, 8}, + {P2_11 , SPI_4, 8}, + {P4_3 , SPI_4, 7}, + {NC , NC , 0} +}; +#else +static const PinMap PinMap_SPI_SCLK[] = { + {P4_4 , SPI_1, 2}, + {P8_14 , SPI_2, 5}, + {P5_0 , SPI_3, 8}, + {P4_0 , SPI_4, 7}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_SSEL[] = { + {P4_5 , SPI_1, 2}, + {P8_15 , SPI_2, 5}, + {P5_1 , SPI_3, 8}, + {P4_1 , SPI_4, 7}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_MOSI[] = { + {P4_6 , SPI_1, 2}, + {P9_0 , SPI_2, 5}, + {P5_2 , SPI_3, 8}, + {P4_2 , SPI_4, 7}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_MISO[] = { + {P4_7 , SPI_1, 2}, + {P9_1 , SPI_2, 5}, + {P5_3 , SPI_3, 8}, + {P4_3 , SPI_4, 7}, + {NC , NC , 0} +}; +#endif + + +static const struct st_rspi *RSPI[] = RSPI_ADDRESS_LIST; + +static inline void spi_disable(spi_t *obj); +static inline void spi_enable(spi_t *obj); +static inline int spi_readable(spi_t *obj); +static inline void spi_write(spi_t *obj, int value); +static inline int spi_read(spi_t *obj); + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { + // determine the SPI to use + volatile uint8_t dummy; + uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI); + uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO); + uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK); + uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL); + uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso); + uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel); + uint32_t spi = pinmap_merge(spi_data, spi_cntl); + + MBED_ASSERT((int)spi != NC); + + obj->spi = (struct st_rspi *)RSPI[spi]; + + // enable power and clocking + switch (spi) { + case SPI_1: CPGSTBCR10 &= ~(0x40); break; + case SPI_2: CPGSTBCR10 &= ~(0x20); break; + case SPI_3: CPGSTBCR10 &= ~(0x10); break; + case SPI_4: CPGSTBCR10 &= ~(0x08); break; + } + dummy = CPGSTBCR10; + + obj->spi->SPCR = 0x00; // CTRL to 0 + obj->spi->SPSCR = 0x00; // no sequential operation + obj->spi->SSLP = 0x00; // SSL 'L' active + obj->spi->SPDCR = 0x20; // byte access + obj->spi->SPCKD = 0x00; // SSL -> enable CLK delay : 1RSPCK + obj->spi->SSLND = 0x00; // CLK end -> SSL neg delay : 1RSPCK + obj->spi->SPND = 0x00; // delay between CMD : 1RSPCK + 2P1CLK + obj->spi->SPPCR = 0x20; // MOSI Idle fixed value equals 0 + obj->spi->SPBFCR = 0xf0; // and set trigger count: read 1, write 1 + obj->spi->SPBFCR = 0x30; // and reset buffer + + // pin out the spi pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + if ((int)ssel != NC) { + pinmap_pinout(ssel, PinMap_SPI_SSEL); + } +} + +void spi_free(spi_t *obj) {} + +void spi_format(spi_t *obj, int bits, int mode, int slave) { + int DSS; // DSS (data select size) + int polarity = (mode & 0x2) ? 1 : 0; + int phase = (mode & 0x1) ? 1 : 0; + uint16_t tmp = 0; + uint16_t mask = 0xf03; + uint16_t wk_spcmd0; + uint8_t splw; + + switch (mode) { + case 0: + case 1: + case 2: + case 3: + // Do Nothing + break; + default: + error("SPI format error"); + return; + } + + switch (bits) { + case 8: + DSS = 0x7; + splw = 0x20; + break; + case 16: + DSS = 0xf; + splw = 0x40; + break; + case 32: + DSS = 0x2; + splw = 0x60; + break; + default: + error("SPI module don't support other than 8/16/32bits"); + return; + } + tmp |= phase; + tmp |= (polarity << 1); + tmp |= (DSS << 8); + obj->bits = bits; + + spi_disable(obj); + wk_spcmd0 = obj->spi->SPCMD0; + wk_spcmd0 &= ~mask; + wk_spcmd0 |= (mask & tmp); + obj->spi->SPCMD0 = wk_spcmd0; + obj->spi->SPDCR = splw; + if (slave) { + obj->spi->SPCR &=~(1 << 3); // MSTR to 0 + } else { + obj->spi->SPCR |= (1 << 3); // MSTR to 1 + } + spi_enable(obj); +} + +void spi_frequency(spi_t *obj, int hz) { + uint32_t pclk_base; + uint32_t div; + uint32_t brdv = 0; + uint32_t hz_max; + uint32_t hz_min; + uint16_t mask = 0x000c; + uint16_t wk_spcmd0; + + /* set PCLK */ + if (RZ_A1_IsClockMode0() == false) { + pclk_base = CM1_RENESAS_RZ_A1_P1_CLK; + } else { + pclk_base = CM0_RENESAS_RZ_A1_P1_CLK; + } + + hz_min = pclk_base / 2 / 256 / 8; + hz_max = pclk_base / 2; + if ((hz < hz_min) || (hz > hz_max)) { + error("Couldn't setup requested SPI frequency"); + return; + } + + div = (pclk_base / hz / 2); + while (div > 256) { + div >>= 1; + brdv++; + } + div -= 1; + brdv = (brdv << 2); + + spi_disable(obj); + obj->spi->SPBR = div; + wk_spcmd0 = obj->spi->SPCMD0; + wk_spcmd0 &= ~mask; + wk_spcmd0 |= (mask & brdv); + obj->spi->SPCMD0 = wk_spcmd0; + spi_enable(obj); +} + +static inline void spi_disable(spi_t *obj) { + obj->spi->SPCR &= ~(1 << 6); // SPE to 0 +} + +static inline void spi_enable(spi_t *obj) { + obj->spi->SPCR |= (1 << 6); // SPE to 1 +} + +static inline int spi_readable(spi_t *obj) { + return obj->spi->SPSR & (1 << 7); // SPRF +} + +static inline int spi_tend(spi_t *obj) { + return obj->spi->SPSR & (1 << 6); // TEND +} + +static inline void spi_write(spi_t *obj, int value) { + if (obj->bits == 8) { + obj->spi->SPDR.UINT8[0] = (uint8_t)value; + } else if (obj->bits == 16) { + obj->spi->SPDR.UINT16[0] = (uint16_t)value; + } else { + obj->spi->SPDR.UINT32 = (uint32_t)value; + } +} + +static inline int spi_read(spi_t *obj) { + int read_data; + + if (obj->bits == 8) { + read_data = obj->spi->SPDR.UINT8[0]; + } else if (obj->bits == 16) { + read_data = obj->spi->SPDR.UINT16[0]; + } else { + read_data = obj->spi->SPDR.UINT32; + } + + return read_data; +} + +int spi_master_write(spi_t *obj, int value) { + spi_write(obj, value); + while(!spi_tend(obj)); + return spi_read(obj); +} + +int spi_slave_receive(spi_t *obj) { + return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0); +} + +int spi_slave_read(spi_t *obj) { + return spi_read(obj); +} + +void spi_slave_write(spi_t *obj, int value) { + spi_write(obj, value); +} + +int spi_busy(spi_t *obj) { + return 0; +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/us_ticker.c Fri Apr 29 01:15:11 2016 +0100 @@ -0,0 +1,139 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include <stddef.h> +#include "us_ticker_api.h" +#include "PeripheralNames.h" +#include "ostm_iodefine.h" + +#include "RZ_A1_Init.h" +#include "VKRZA1H.h" + +#define US_TICKER_TIMER_IRQn (OSTMI1TINT_IRQn) +#define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */ + +#define US_TICKER_CLOCK_US_DEV (1000000) + +int us_ticker_inited = 0; +static double count_clock = 0; +static uint32_t last_read = 0; +static uint32_t wrap_arround = 0; +static uint64_t ticker_us_last64 = 0; + +void us_ticker_interrupt(void) { + us_ticker_irq_handler(); +} + +void us_ticker_init(void) { + if (us_ticker_inited) return; + us_ticker_inited = 1; + + /* set Counter Clock(us) */ + if (false == RZ_A1_IsClockMode0()) { + count_clock = ((double)CM1_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV); + } else { + count_clock = ((double)CM0_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV); + } + + /* Power Control for Peripherals */ + CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP50); /* enable OSTM1 clock */ + + // timer settings + OSTM1TT = 0x01; /* Stop the counter and clears the OSTM1TE bit. */ + OSTM1CTL = 0x02; /* Free running timer mode. Interrupt disabled when star counter */ + + OSTM1TS = 0x1; /* Start the counter and sets the OSTM0TE bit. */ + + // INTC settings + InterruptHandlerRegister(US_TICKER_TIMER_IRQn, (void (*)(uint32_t))us_ticker_interrupt); + GIC_SetPriority(US_TICKER_TIMER_IRQn, 5); + GIC_EnableIRQ(US_TICKER_TIMER_IRQn); +} + +static uint64_t ticker_read_counter64(void) { + uint32_t cnt_val; + uint64_t cnt_val64; + + if (!us_ticker_inited) + us_ticker_init(); + + /* read counter */ + cnt_val = OSTM1CNT; + if (last_read > cnt_val) { + wrap_arround++; + } + last_read = cnt_val; + cnt_val64 = ((uint64_t)wrap_arround << 32) + cnt_val; + + return cnt_val64; +} + +uint32_t us_ticker_read() { + uint64_t cnt_val64; + uint64_t us_val64; + int check_irq_masked; + +#if defined ( __ICCARM__) + check_irq_masked = __disable_irq_iar(); +#else + check_irq_masked = __disable_irq(); +#endif /* __ICCARM__ */ + + cnt_val64 = ticker_read_counter64(); + us_val64 = (cnt_val64 / count_clock); + ticker_us_last64 = us_val64; + + if (!check_irq_masked) { + __enable_irq(); + } + + /* clock to us */ + return (uint32_t)us_val64; +} + +void us_ticker_set_interrupt(timestamp_t timestamp) { + // set match value + uint64_t timestamp64; + uint64_t set_cmp_val64; + volatile uint32_t set_cmp_val; + uint64_t count_val_64; + + /* calc compare mach timestamp */ + timestamp64 = (ticker_us_last64 & 0xFFFFFFFF00000000) + timestamp; + if (timestamp < (ticker_us_last64 & 0x00000000FFFFFFFF)) { + /* This event is wrap arround */ + timestamp64 += 0x100000000; + } + + /* calc compare mach timestamp */ + set_cmp_val64 = timestamp64 * count_clock; + set_cmp_val = (uint32_t)(set_cmp_val64 & 0x00000000FFFFFFFF); + count_val_64 = ticker_read_counter64(); + if (set_cmp_val64 <= (count_val_64 + 500)) { + GIC_SetPendingIRQ(US_TICKER_TIMER_IRQn); + GIC_EnableIRQ(US_TICKER_TIMER_IRQn); + return; + } + OSTM1CMP = set_cmp_val; + GIC_EnableIRQ(US_TICKER_TIMER_IRQn); +} + +void us_ticker_disable_interrupt(void) { + GIC_DisableIRQ(US_TICKER_TIMER_IRQn); +} + +void us_ticker_clear_interrupt(void) { + GIC_ClearPendingIRQ(US_TICKER_TIMER_IRQn); +}
--- a/targets/hal/TARGET_STM/TARGET_STM32F3XX/PeripheralNames.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,79 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ADC_1 = (int)ADC1_BASE -} ADCName; - -typedef enum { - DAC_1 = (int)DAC_BASE -} DACName; - -typedef enum { - UART_1 = (int)USART1_BASE, - UART_2 = (int)USART2_BASE, - UART_3 = (int)USART3_BASE -} UARTName; - -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - -typedef enum { - SPI_2 = (int)SPI2_BASE, - SPI_3 = (int)SPI3_BASE -} SPIName; - -typedef enum { - I2C_1 = (int)I2C1_BASE, - I2C_2 = (int)I2C2_BASE, - I2C_3 = (int)I2C3_BASE -} I2CName; - -typedef enum { - PWM_1 = (int)TIM1_BASE, - PWM_15 = (int)TIM15_BASE, - PWM_16 = (int)TIM16_BASE, - PWM_17 = (int)TIM17_BASE -} PWMName; - -#ifdef __cplusplus -} -#endif - -#endif
--- a/targets/hal/TARGET_STM/TARGET_STM32F3XX/PinNames.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,180 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// MODE (see GPIOMode_TypeDef structure) -// OTYPE (see GPIOOType_TypeDef structure) -// PUPD (see GPIOPuPd_TypeDef structure) -// AFNUM (see AF_mapping constant table, 0xFF is not used) -#define STM_PIN_DATA(MODE, OTYPE, PUPD, AFNUM) (((AFNUM)<<8)|((PUPD)<<4)|((OTYPE)<<2)|((MODE)<<0)) -#define STM_PIN_MODE(X) (((X)>>0) & 0x3) -#define STM_PIN_OTYPE(X) (((X)>>2) & 0x1) -#define STM_PIN_PUPD(X) (((X)>>4) & 0x3) -#define STM_PIN_AFNUM(X) (((X)>>8) & 0xF) - -// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H) -// Low nibble = pin number -#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF) -#define STM_PIN(X) ((uint32_t)(X) & 0xF) - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -typedef enum { - PA_0 = 0x00, - PA_1 = 0x01, - PA_2 = 0x02, - PA_3 = 0x03, - PA_4 = 0x04, - PA_5 = 0x05, - PA_6 = 0x06, - PA_7 = 0x07, - PA_8 = 0x08, - PA_9 = 0x09, - PA_10 = 0x0A, - PA_11 = 0x0B, - PA_12 = 0x0C, - PA_13 = 0x0D, - PA_14 = 0x0E, - PA_15 = 0x0F, - - PB_0 = 0x10, - PB_1 = 0x11, - PB_2 = 0x12, - PB_3 = 0x13, - PB_4 = 0x14, - PB_5 = 0x15, - PB_6 = 0x16, - PB_7 = 0x17, - PB_8 = 0x18, - PB_9 = 0x19, - PB_10 = 0x1A, - PB_11 = 0x1B, - PB_12 = 0x1C, - PB_13 = 0x1D, - PB_14 = 0x1E, - PB_15 = 0x1F, - - PC_0 = 0x20, - PC_1 = 0x21, - PC_2 = 0x22, - PC_3 = 0x23, - PC_4 = 0x24, - PC_5 = 0x25, - PC_6 = 0x26, - PC_7 = 0x27, - PC_8 = 0x28, - PC_9 = 0x29, - PC_10 = 0x2A, - PC_11 = 0x2B, - PC_12 = 0x2C, - PC_13 = 0x2D, - PC_14 = 0x2E, - PC_15 = 0x2F, - - PD_0 = 0x30, - PD_1 = 0x31, - PD_2 = 0x32, - PD_3 = 0x33, - PD_4 = 0x34, - PD_5 = 0x35, - PD_6 = 0x36, - PD_7 = 0x37, - PD_8 = 0x38, - PD_9 = 0x39, - PD_10 = 0x3A, - PD_11 = 0x3B, - PD_12 = 0x3C, - PD_13 = 0x3D, - PD_14 = 0x3E, - PD_15 = 0x3F, - - PE_0 = 0x40, - PE_1 = 0x41, - PE_2 = 0x42, - PE_3 = 0x43, - PE_4 = 0x44, - PE_5 = 0x45, - PE_6 = 0x46, - PE_7 = 0x47, - PE_8 = 0x48, - PE_9 = 0x49, - PE_10 = 0x4A, - PE_11 = 0x4B, - PE_12 = 0x4C, - PE_13 = 0x4D, - PE_14 = 0x4E, - PE_15 = 0x4F, - - PF_0 = 0x50, - PF_1 = 0x51, - PF_2 = 0x52, - PF_3 = 0x53, - PF_4 = 0x54, - PF_5 = 0x55, - PF_6 = 0x56, - PF_7 = 0x57, - PF_8 = 0x58, - PF_9 = 0x59, - PF_10 = 0x5A, - PF_11 = 0x5B, - PF_12 = 0x5C, - PF_13 = 0x5D, - PF_14 = 0x5E, - PF_15 = 0x5F, - - LED1 = PE_9, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -typedef enum { - PullNone = 0, - PullUp = 1, - PullDown = 2, - OpenDrain = 3, - PullDefault = PullNone -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif
--- a/targets/hal/TARGET_STM/TARGET_STM32F3XX/PortNames.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,49 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PortA = 0, - PortB = 1, - PortC = 2, - PortD = 3, - PortE = 4, - PortF = 5 -} PortName; - -#ifdef __cplusplus -} -#endif -#endif
--- a/targets/hal/TARGET_STM/TARGET_STM32F3XX/analogin_api.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,191 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "mbed_assert.h" -#include "analogin_api.h" -#include "wait_api.h" - -#if DEVICE_ANALOGIN - -#include "cmsis.h" -#include "pinmap.h" - -static const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN1 - {PA_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN2 - {PA_2, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN3 - {PA_3, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN4 - {PA_4, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN5 - {PC_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN6 - {PC_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN7 - {PC_2, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN8 - {PC_3, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN9 - {PA_6, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN10 - {PB_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN11 - {PB_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN12 - {PB_13, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN13 - {PB_11, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN14 - {PA_7, ADC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // ADC_IN15 - {NC, NC, 0} -}; - -int adc_inited = 0; - -void analogin_init(analogin_t *obj, PinName pin) { - - ADC_TypeDef *adc; - ADC_InitTypeDef ADC_InitStructure; - ADC_CommonInitTypeDef ADC_CommonInitStructure; - - // Get the peripheral name from the pin and assign it to the object - obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - MBED_ASSERT(obj->adc == (ADCName)NC); - - // Configure GPIO - pinmap_pinout(pin, PinMap_ADC); - - // Save pin number for the read function - obj->pin = pin; - - // The ADC initialization is done once - if (adc_inited == 0) { - adc_inited = 1; - - // Get ADC registers structure address - adc = (ADC_TypeDef *)(obj->adc); - - // Enable ADC clock - RCC_ADCCLKConfig(RCC_ADC12PLLCLK_Div1); - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_ADC12, ENABLE); - - // Calibration - ADC_VoltageRegulatorCmd(adc, ENABLE); - wait_us(10); - ADC_SelectCalibrationMode(adc, ADC_CalibrationMode_Single); - ADC_StartCalibration(adc); - while (ADC_GetCalibrationStatus(adc) != RESET) {} - - // Configure ADC - ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent; - ADC_CommonInitStructure.ADC_Clock = ADC_Clock_AsynClkMode; - ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled; - ADC_CommonInitStructure.ADC_DMAMode = ADC_DMAMode_OneShot; - ADC_CommonInitStructure.ADC_TwoSamplingDelay = 0; - ADC_CommonInit(adc, &ADC_CommonInitStructure); - - ADC_InitStructure.ADC_ContinuousConvMode = ADC_ContinuousConvMode_Disable; - ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b; - ADC_InitStructure.ADC_ExternalTrigConvEvent = ADC_ExternalTrigConvEvent_0; - ADC_InitStructure.ADC_ExternalTrigEventEdge = ADC_ExternalTrigEventEdge_None; - ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; - ADC_InitStructure.ADC_OverrunMode = ADC_OverrunMode_Disable; - ADC_InitStructure.ADC_AutoInjMode = ADC_AutoInjec_Disable; - ADC_InitStructure.ADC_NbrOfRegChannel = 1; - ADC_Init(adc, &ADC_InitStructure); - - // Enable ADC - ADC_Cmd(adc, ENABLE); - - while (!ADC_GetFlagStatus(adc, ADC_FLAG_RDY)) {} - } -} - -static inline uint16_t adc_read(analogin_t *obj) { - // Get ADC registers structure address - ADC_TypeDef *adc = (ADC_TypeDef *)(obj->adc); - uint8_t channel = 0; - - // Configure ADC channel - switch (obj->pin) { - case PA_0: - channel = ADC_Channel_1; - break; - case PA_1: - channel = ADC_Channel_2; - break; - case PA_2: - channel = ADC_Channel_3; - break; - case PA_3: - channel = ADC_Channel_4; - break; - case PA_4: - channel = ADC_Channel_5; - break; - case PC_0: - channel = ADC_Channel_6; - break; - case PC_1: - channel = ADC_Channel_7; - break; - case PC_2: - channel = ADC_Channel_8; - break; - case PC_3: - channel = ADC_Channel_9; - break; - case PA_6: - channel = ADC_Channel_10; - break; - case PB_0: - channel = ADC_Channel_11; - break; - case PB_1: - channel = ADC_Channel_12; - break; - case PB_13: - channel = ADC_Channel_13; - break; - case PB_11: - channel = ADC_Channel_14; - break; - case PA_7: - channel = ADC_Channel_15; - break; - default: - return 0; - } - - ADC_RegularChannelConfig(adc, channel, 1, ADC_SampleTime_7Cycles5); - - ADC_StartConversion(adc); // Start conversion - - while (ADC_GetFlagStatus(adc, ADC_FLAG_EOC) == RESET); // Wait end of conversion - - return (ADC_GetConversionValue(adc)); // Get conversion value -} - -uint16_t analogin_read_u16(analogin_t *obj) { - return (adc_read(obj)); -} - -float analogin_read(analogin_t *obj) { - uint16_t value = adc_read(obj); - return (float)value * (1.0f / (float)0xFFF); // 12 bits range -} - -#endif
--- a/targets/hal/TARGET_STM/TARGET_STM32F3XX/analogout_api.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,110 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "mbed_assert.h" -#include "analogout_api.h" - -#if DEVICE_ANALOGOUT - -#include "cmsis.h" -#include "pinmap.h" - -#define RANGE_12BIT (0xFFF) - -static const PinMap PinMap_DAC[] = { - {PA_4, DAC_1, STM_PIN_DATA(GPIO_Mode_AN, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)}, // DAC_OUT1 - {NC, NC, 0} -}; - -void analogout_init(dac_t *obj, PinName pin) { - DAC_TypeDef *dac; - DAC_InitTypeDef DAC_InitStructure; - - // Get the peripheral name (DAC_1, ...) from the pin and assign it to the object - obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); - MBED_ASSERT(obj->dac == (DACName)NC); - - dac = (DAC_TypeDef *)(obj->dac); - - // Configure GPIO - pinmap_pinout(pin, PinMap_DAC); - - // Save the channel for the write and read functions - obj->channel = pin; - - // Enable DAC clock - RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE); - - // Configure and enable DAC channel - DAC_StructInit(&DAC_InitStructure); - DAC_Init(dac, DAC_Channel_1, &DAC_InitStructure); - DAC_Cmd(dac, DAC_Channel_1, ENABLE); - - analogout_write_u16(obj, 0); -} - -void analogout_free(dac_t *obj) { -} - -static inline void dac_write(dac_t *obj, uint16_t value) { - DAC_TypeDef *dac = (DAC_TypeDef *)(obj->dac); - DAC_SetChannel1Data(dac, DAC_Align_12b_R, value); -} - -static inline int dac_read(dac_t *obj) { - DAC_TypeDef *dac = (DAC_TypeDef *)(obj->dac); - return (int)DAC_GetDataOutputValue(dac, DAC_Channel_1); -} - -void analogout_write(dac_t *obj, float value) { - if (value < 0.0f) { - dac_write(obj, 0); // Min value - } else if (value > 1.0f) { - dac_write(obj, (uint16_t)RANGE_12BIT); // Max value - } else { - dac_write(obj, (uint16_t)(value * (float)RANGE_12BIT)); - } -} - -void analogout_write_u16(dac_t *obj, uint16_t value) { - if (value > (uint16_t)RANGE_12BIT) { - dac_write(obj, (uint16_t)RANGE_12BIT); // Max value - } else { - dac_write(obj, value); - } -} - -float analogout_read(dac_t *obj) { - uint32_t value = dac_read(obj); - return (float)value * (1.0f / (float)RANGE_12BIT); -} - -uint16_t analogout_read_u16(dac_t *obj) { - return (uint16_t)dac_read(obj); -} - -#endif // DEVICE_ANALOGOUT
--- a/targets/hal/TARGET_STM/TARGET_STM32F3XX/device.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,71 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_PORTIN 1 -#define DEVICE_PORTOUT 1 -#define DEVICE_PORTINOUT 1 - -#define DEVICE_INTERRUPTIN 1 - -#define DEVICE_ANALOGIN 1 -#define DEVICE_ANALOGOUT 1 - -#define DEVICE_SERIAL 1 - -#define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 0 // Not yet supported - -#define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 0 // Not yet supported - -#define DEVICE_RTC 1 - -#define DEVICE_PWMOUT 1 - -#define DEVICE_SLEEP 1 - -//======================================= - -#define DEVICE_SEMIHOST 0 - -#define DEVICE_LOCALFILESYSTEM 0 -#define DEVICE_ID_LENGTH 24 - -#define DEVICE_DEBUG_AWARENESS 0 - -#define DEVICE_STDIO_MESSAGES 1 - -#define DEVICE_ERROR_RED 0 - -#include "objects.h" - -#endif
--- a/targets/hal/TARGET_STM/TARGET_STM32F3XX/gpio_api.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,74 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "gpio_api.h" -#include "pinmap.h" -#include "mbed_error.h" - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -uint32_t gpio_set(PinName pin) { - MBED_ASSERT(pin != (PinName)NC); - - pin_function(pin, STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF)); - - return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask -} - -void gpio_init(gpio_t *obj, PinName pin) { - obj->pin = pin; - if (pin == (PinName)NC) - return; - - uint32_t port_index = STM_PORT(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Fill GPIO object structure for future use - obj->mask = gpio_set(pin); - obj->reg_in = &gpio->IDR; - obj->reg_set = &gpio->BSRR; - obj->reg_clr = &gpio->BRR; -} - -void gpio_mode(gpio_t *obj, PinMode mode) { - pin_mode(obj->pin, mode); -} - -void gpio_dir(gpio_t *obj, PinDirection direction) { - MBED_ASSERT(obj->pin != (PinName)NC); - if (direction == PIN_OUTPUT) { - pin_function(obj->pin, STM_PIN_DATA(GPIO_Mode_OUT, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)); - } else { // PIN_INPUT - pin_function(obj->pin, STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF)); - } -}
--- a/targets/hal/TARGET_STM/TARGET_STM32F3XX/gpio_irq_api.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,255 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include <stddef.h> -#include "cmsis.h" - -#include "gpio_irq_api.h" -#include "pinmap.h" -#include "mbed_error.h" - -#define EDGE_NONE (0) -#define EDGE_RISE (1) -#define EDGE_FALL (2) -#define EDGE_BOTH (3) - -#define CHANNEL_NUM (7) - -static uint32_t channel_ids[CHANNEL_NUM] = {0, 0, 0, 0, 0, 0, 0}; -static uint32_t channel_gpio[CHANNEL_NUM] = {0, 0, 0, 0, 0, 0, 0}; -static uint32_t channel_pin[CHANNEL_NUM] = {0, 0, 0, 0, 0, 0, 0}; - -static gpio_irq_handler irq_handler; - -static void handle_interrupt_in(uint32_t irq_index) { - // Retrieve the gpio and pin that generate the irq - GPIO_TypeDef *gpio = (GPIO_TypeDef *)(channel_gpio[irq_index]); - uint32_t pin = (uint32_t)(1 << channel_pin[irq_index]); - - // Clear interrupt flag - if (EXTI_GetITStatus(channel_pin[irq_index]) != RESET) { - EXTI_ClearITPendingBit(channel_pin[irq_index]); - } - - if (channel_ids[irq_index] == 0) return; - - // Check which edge has generated the irq - if ((gpio->IDR & pin) == 0) { - irq_handler(channel_ids[irq_index], IRQ_FALL); - } else { - irq_handler(channel_ids[irq_index], IRQ_RISE); - } -} - -static void gpio_irq0(void) { - handle_interrupt_in(0); // EXTI line 0 -} - -static void gpio_irq1(void) { - handle_interrupt_in(1); // EXTI line 1 -} - -static void gpio_irq2(void) { - handle_interrupt_in(2); // EXTI line 2 -} - -static void gpio_irq3(void) { - handle_interrupt_in(3); // EXTI line 3 -} - -static void gpio_irq4(void) { - handle_interrupt_in(4); // EXTI line 4 -} - -static void gpio_irq5(void) { - handle_interrupt_in(5); // EXTI lines 5 to 9 -} - -static void gpio_irq6(void) { - handle_interrupt_in(6); // EXTI lines 10 to 15 -} - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - uint32_t irq_index; - - if (pin == NC) return -1; - - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Select irq number and interrupt routine - switch (pin_index) { - case 0: - irq_n = EXTI0_IRQn; - vector = (uint32_t)&gpio_irq0; - irq_index = 0; - break; - case 1: - irq_n = EXTI1_IRQn; - vector = (uint32_t)&gpio_irq1; - irq_index = 1; - break; - case 2: - irq_n = EXTI2_TS_IRQn; - vector = (uint32_t)&gpio_irq2; - irq_index = 2; - break; - case 3: - irq_n = EXTI3_IRQn; - vector = (uint32_t)&gpio_irq3; - irq_index = 3; - break; - case 4: - irq_n = EXTI4_IRQn; - vector = (uint32_t)&gpio_irq4; - irq_index = 4; - break; - case 5: - case 6: - case 7: - case 8: - case 9: - irq_n = EXTI9_5_IRQn; - vector = (uint32_t)&gpio_irq5; - irq_index = 5; - break; - case 10: - case 11: - case 12: - case 13: - case 14: - case 15: - irq_n = EXTI15_10_IRQn; - vector = (uint32_t)&gpio_irq6; - irq_index = 6; - break; - default: - error("This pin is not supported with InterruptIn."); - return -1; - } - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - - // Enable SYSCFG clock - RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - - // Connect EXTI line to pin - SYSCFG_EXTILineConfig(port_index, pin_index); - - // Configure EXTI line - EXTI_InitTypeDef EXTI_InitStructure; - EXTI_InitStructure.EXTI_Line = pin_index; - EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_InitStructure.EXTI_LineCmd = ENABLE; - EXTI_Init(&EXTI_InitStructure); - - // Enable and set EXTI interrupt to the lowest priority - NVIC_InitTypeDef NVIC_InitStructure; - NVIC_InitStructure.NVIC_IRQChannel = irq_n; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); - - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - // Save informations for future use - obj->irq_n = irq_n; - obj->irq_index = irq_index; - obj->event = EDGE_NONE; - channel_ids[irq_index] = id; - channel_gpio[irq_index] = gpio_add; - channel_pin[irq_index] = pin_index; - - irq_handler = handler; - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) { - channel_ids[obj->irq_index] = 0; - channel_gpio[obj->irq_index] = 0; - channel_pin[obj->irq_index] = 0; - // Disable EXTI line - EXTI_InitTypeDef EXTI_InitStructure; - EXTI_StructInit(&EXTI_InitStructure); - EXTI_Init(&EXTI_InitStructure); - obj->event = EDGE_NONE; -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { - EXTI_InitTypeDef EXTI_InitStructure; - - EXTI_InitStructure.EXTI_Line = channel_pin[obj->irq_index]; - EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; - - if (event == IRQ_RISE) { - if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) { - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling; - obj->event = EDGE_BOTH; - } else { // NONE or RISE - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; - obj->event = EDGE_RISE; - } - } - - if (event == IRQ_FALL) { - if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) { - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling; - obj->event = EDGE_BOTH; - } else { // NONE or FALL - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; - obj->event = EDGE_FALL; - } - } - - if (enable) { - EXTI_InitStructure.EXTI_LineCmd = ENABLE; - } else { - EXTI_InitStructure.EXTI_LineCmd = DISABLE; - } - - EXTI_Init(&EXTI_InitStructure); -} - -void gpio_irq_enable(gpio_irq_t *obj) { - NVIC_EnableIRQ(obj->irq_n); -} - -void gpio_irq_disable(gpio_irq_t *obj) { - NVIC_DisableIRQ(obj->irq_n); - obj->event = EDGE_NONE; -}
--- a/targets/hal/TARGET_STM/TARGET_STM32F3XX/gpio_object.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,73 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - uint32_t mask; - __IO uint16_t *reg_in; - __IO uint32_t *reg_set; - __IO uint16_t *reg_clr; -} gpio_t; - -static inline void gpio_write(gpio_t *obj, int value) { - MBED_ASSERT(obj->pin != (PinName)NC); - if (value) { - *obj->reg_set = obj->mask; - } else { - *obj->reg_clr = obj->mask; - } -} - -static inline int gpio_read(gpio_t *obj) { - MBED_ASSERT(obj->pin != (PinName)NC); - return ((*obj->reg_in & obj->mask) ? 1 : 0); -} - -static inline int gpio_is_connected(const gpio_t *obj) { - return obj->pin != (PinName)NC; -} - -#ifdef __cplusplus -} -#endif - -#endif
--- a/targets/hal/TARGET_STM/TARGET_STM32F3XX/i2c_api.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,354 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "i2c_api.h" - -#if DEVICE_I2C - -#include "cmsis.h" -#include "pinmap.h" - -/* Timeout values for flags and events waiting loops. These timeouts are - not based on accurate values, they just guarantee that the application will - not remain stuck if the I2C communication is corrupted. */ -#define FLAG_TIMEOUT ((int)0x1000) -#define LONG_TIMEOUT ((int)0x8000) - -static const PinMap PinMap_I2C_SDA[] = { - {PA_10, I2C_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_4)}, - {PA_14, I2C_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_4)}, - {PB_5, I2C_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_8)}, - {PB_7, I2C_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_4)}, - {PB_9, I2C_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_4)}, - {PC_9, I2C_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_3)}, - {PF_0, I2C_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_4)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_I2C_SCL[] = { - {PA_8, I2C_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_3)}, - {PA_9, I2C_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_4)}, - {PA_15, I2C_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_4)}, - {PB_6, I2C_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_4)}, - {PB_8, I2C_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_4)}, - {PF_1, I2C_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_OD, GPIO_PuPd_UP, GPIO_AF_4)}, - {NC, NC, 0} -}; - -void i2c_init(i2c_t *obj, PinName sda, PinName scl) { - // Determine the I2C to use - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - - obj->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT(obj->i2c != (I2CName)NC); - - // Enable I2C clock - if (obj->i2c == I2C_1) { - RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE); - } - if (obj->i2c == I2C_2) { - RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C2, ENABLE); - } - if (obj->i2c == I2C_3) { - RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C3, ENABLE); - } - - // Configure I2C pins - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(scl, OpenDrain); - pinmap_pinout(sda, PinMap_I2C_SDA); - pin_mode(sda, OpenDrain); - - // Reset to clear pending flags if any - i2c_reset(obj); - - // I2C configuration - i2c_frequency(obj, 100000); // 100 kHz per default -} - -void i2c_frequency(i2c_t *obj, int hz) { - MBED_ASSERT((hz == 100000) || (hz == 200000) || (hz == 400000) || (hz == 1000000)); - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - I2C_InitTypeDef I2C_InitStructure; - uint32_t tim; - - // Disable the Fast Mode Plus capability - RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); // Enable SYSCFG clock - SYSCFG_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus_I2C1, DISABLE); - SYSCFG_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus_I2C2, DISABLE); - - /* - Values calculated with I2C_Timing_Configuration_V1.0.1.xls file (see AN4235) - * Standard mode (up to 100 kHz) - * Fast Mode (up to 400 kHz) - * Fast Mode Plus (up to 1 MHz) - Below values obtained with: - - I2C clock source = 8 MHz (HSI clock per default) - - Analog filter delay = ON - - Digital filter coefficient = 0 - - Rise time = 100 ns - - Fall time = 10ns - */ - switch (hz) { - case 100000: - tim = 0x00201D2B; // Standard mode - break; - case 200000: - tim = 0x0010021E; // Fast Mode - break; - case 400000: - tim = 0x0010020A; // Fast Mode - break; - case 1000000: - tim = 0x00100001; // Fast Mode Plus - // Enable the Fast Mode Plus capability - if (obj->i2c == I2C_1) { - SYSCFG_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus_I2C1, ENABLE); - } - if (obj->i2c == I2C_2) { - SYSCFG_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus_I2C2, ENABLE); - } - break; - default: - break; - } - - // I2C configuration - I2C_DeInit(i2c); - I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; - I2C_InitStructure.I2C_AnalogFilter = I2C_AnalogFilter_Enable; - I2C_InitStructure.I2C_DigitalFilter = 0x00; - I2C_InitStructure.I2C_OwnAddress1 = 0x00; - I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; - I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; - I2C_InitStructure.I2C_Timing = tim; - I2C_Init(i2c, &I2C_InitStructure); - - I2C_Cmd(i2c, ENABLE); -} - -inline int i2c_start(i2c_t *obj) { - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // Test BUSY Flag - timeout = LONG_TIMEOUT; - while (I2C_GetFlagStatus(i2c, I2C_ISR_BUSY) != RESET) { - timeout--; - if (timeout == 0) { - return 0; - } - } - - I2C_GenerateSTART(i2c, ENABLE); - - return 0; -} - -inline int i2c_stop(i2c_t *obj) { - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - - I2C_GenerateSTOP(i2c, ENABLE); - - return 0; -} - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int count; - int value; - - if (length == 0) return 0; - - // Configure slave address, nbytes, reload, end mode and start or stop generation - I2C_TransferHandling(i2c, address, length, I2C_AutoEnd_Mode, I2C_Generate_Start_Read); - - // Read all bytes - for (count = 0; count < length; count++) { - value = i2c_byte_read(obj, 0); - data[count] = (char)value; - } - - return length; -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - //int timeout; - int count; - - if (length == 0) return 0; - - // [TODO] The stop is always sent even with I2C_SoftEnd_Mode. To be corrected. - - // Configure slave address, nbytes, reload, end mode and start or stop generation - //if (stop) { - I2C_TransferHandling(i2c, address, length, I2C_AutoEnd_Mode, I2C_Generate_Start_Write); - //} - //else { - // I2C_TransferHandling(i2c, address, length, I2C_SoftEnd_Mode, I2C_Generate_Start_Write); - //} - - // Write all bytes - for (count = 0; count < length; count++) { - if (i2c_byte_write(obj, data[count]) != 1) { - i2c_stop(obj); - return 0; - } - } - - /* - if (stop) { - // Wait until STOPF flag is set - timeout = LONG_TIMEOUT; - while (I2C_GetFlagStatus(i2c, I2C_ISR_STOPF) == RESET) { - timeout--; - if (timeout == 0) { - return 0; - } - } - // Clear STOPF flag - I2C_ClearFlag(i2c, I2C_ICR_STOPCF); - } - */ - - return count; -} - -int i2c_byte_read(i2c_t *obj, int last) { - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - uint8_t data; - int timeout; - - // Wait until the byte is received - timeout = FLAG_TIMEOUT; - while (I2C_GetFlagStatus(i2c, I2C_ISR_RXNE) == RESET) { - timeout--; - if (timeout == 0) { - return 0; - } - } - - data = I2C_ReceiveData(i2c); - - return (int)data; -} - -int i2c_byte_write(i2c_t *obj, int data) { - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // Wait until the previous byte is transmitted - timeout = FLAG_TIMEOUT; - while (I2C_GetFlagStatus(i2c, I2C_ISR_TXIS) == RESET) { - timeout--; - if (timeout == 0) { - return 0; - } - } - - I2C_SendData(i2c, (uint8_t)data); - - return 1; -} - -void i2c_reset(i2c_t *obj) { - if (obj->i2c == I2C_1) { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); - } - if (obj->i2c == I2C_2) { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); - } - if (obj->i2c == I2C_3) { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C3, DISABLE); - } -} - -#if DEVICE_I2CSLAVE - -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - uint16_t tmpreg; - - // Get the old register value - tmpreg = i2c->OAR1; - // Reset address bits - tmpreg &= 0xFC00; - // Set new address - tmpreg |= (uint16_t)((uint16_t)address & (uint16_t)0x00FE); // 7-bits - // Store the new register value - i2c->OAR1 = tmpreg; -} - -void i2c_slave_mode(i2c_t *obj, int enable_slave) { - // Nothing to do -} - -// See I2CSlave.h -#define NoData 0 // the slave has not been addressed -#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter) -#define WriteGeneral 2 // the master is writing to all slave -#define WriteAddressed 3 // the master is writing to this slave (slave = receiver) - -int i2c_slave_receive(i2c_t *obj) { - // TO BE DONE - return (0); -} - -int i2c_slave_read(i2c_t *obj, char *data, int length) { - int count = 0; - - // Read all bytes - for (count = 0; count < length; count++) { - data[count] = i2c_byte_read(obj, 0); - } - - return count; -} - -int i2c_slave_write(i2c_t *obj, const char *data, int length) { - int count = 0; - - // Write all bytes - for (count = 0; count < length; count++) { - i2c_byte_write(obj, data[count]); - } - - return count; -} - - -#endif // DEVICE_I2CSLAVE - -#endif // DEVICE_I2C
--- a/targets/hal/TARGET_STM/TARGET_STM32F3XX/mbed_overrides.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,35 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -extern void SystemCoreClockUpdate(void); - -// This function is called after RAM initialization and before main. -void mbed_sdk_init() { - // Update the SystemCoreClock variable. - SystemCoreClockUpdate(); -}
--- a/targets/hal/TARGET_STM/TARGET_STM32F3XX/objects.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,102 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct gpio_irq_s { - IRQn_Type irq_n; - uint32_t irq_index; - uint32_t event; -}; - -struct port_s { - PortName port; - uint32_t mask; - PinDirection direction; - __IO uint16_t *reg_in; - __IO uint16_t *reg_out; -}; - -struct analogin_s { - ADCName adc; - PinName pin; -}; - -struct dac_s { - DACName dac; - PinName channel; -}; - -struct serial_s { - UARTName uart; - int index; // Used by irq - uint32_t baudrate; - uint32_t databits; - uint32_t stopbits; - uint32_t parity; -}; - -struct spi_s { - SPIName spi; - uint32_t bits; - uint32_t cpol; - uint32_t cpha; - uint32_t mode; - uint32_t nss; - uint32_t br_presc; -}; - -struct i2c_s { - I2CName i2c; -}; - -struct pwmout_s { - PWMName pwm; - PinName pin; - uint32_t period; - uint32_t pulse; -}; - -#include "gpio_object.h" - -#ifdef __cplusplus -} -#endif - -#endif
--- a/targets/hal/TARGET_STM/TARGET_STM32F3XX/pinmap.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,135 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "pinmap.h" -#include "PortNames.h" -#include "mbed_error.h" - -// Enable GPIO clock and return GPIO base address -uint32_t Set_GPIO_Clock(uint32_t port_idx) { - uint32_t gpio_add; - switch (port_idx) { - case PortA: - gpio_add = GPIOA_BASE; - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); - break; - case PortB: - gpio_add = GPIOB_BASE; - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE); - break; - case PortC: - gpio_add = GPIOC_BASE; - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOC, ENABLE); - break; - case PortD: - gpio_add = GPIOD_BASE; - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOD, ENABLE); - break; - case PortE: - gpio_add = GPIOE_BASE; - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOE, ENABLE); - break; - case PortF: - gpio_add = GPIOF_BASE; - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOF, ENABLE); - break; - default: - gpio_add = 0; - error("Port number is not correct."); - break; - } - return gpio_add; -} - -/** - * Configure pin (mode, speed, output type and pull-up/pull-down) - */ -void pin_function(PinName pin, int data) { - MBED_ASSERT(pin != (PinName)NC); - - // Get the pin informations - uint32_t mode = STM_PIN_MODE(data); - uint32_t otype = STM_PIN_OTYPE(data); - uint32_t pupd = STM_PIN_PUPD(data); - uint32_t afnum = STM_PIN_AFNUM(data); - - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Configure Alternate Function - // Warning: Must be done before the GPIO is initialized - if (afnum != 0xFF) { - GPIO_PinAFConfig(gpio, (uint16_t)pin_index, afnum); - } - - // Configure GPIO - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = (uint16_t)(1 << pin_index); - GPIO_InitStructure.GPIO_Mode = (GPIOMode_TypeDef)mode; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_Level_3; - GPIO_InitStructure.GPIO_OType = (GPIOOType_TypeDef)otype; - GPIO_InitStructure.GPIO_PuPd = (GPIOPuPd_TypeDef)pupd; - GPIO_Init(gpio, &GPIO_InitStructure); - - // [TODO] Disconnect JTAG-DP + SW-DP signals. - // Warning: Need to reconnect under reset - //if ((pin == PA_13) || (pin == PA_14)) { - // - //} - //if ((pin == PA_15) || (pin == PB_3) || (pin == PB_4)) { - // - //} -} - -/** - * Configure pin pull-up/pull-down - */ -void pin_mode(PinName pin, PinMode mode) { - MBED_ASSERT(pin != (PinName)NC); - - uint32_t port_index = STM_PORT(pin); - uint32_t pin_index = STM_PIN(pin); - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Configure pull-up/pull-down resistors - uint32_t pupd = (uint32_t)mode; - if (pupd > 2) - pupd = 0; // Open-drain = No pull-up/No pull-down - gpio->PUPDR &= (uint32_t)(~(GPIO_PUPDR_PUPDR0 << (pin_index * 2))); - gpio->PUPDR |= (uint32_t)(pupd << (pin_index * 2)); - -}
--- a/targets/hal/TARGET_STM/TARGET_STM32F3XX/port_api.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,97 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "port_api.h" -#include "pinmap.h" -#include "gpio_api.h" -#include "mbed_error.h" - -#if DEVICE_PORTIN || DEVICE_PORTOUT - -extern uint32_t Set_GPIO_Clock(uint32_t port_idx); - -// high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...) -// low nibble = pin number -PinName port_pin(PortName port, int pin_n) { - return (PinName)(pin_n + (port << 4)); -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { - uint32_t port_index = (uint32_t)port; - - // Enable GPIO clock - uint32_t gpio_add = Set_GPIO_Clock(port_index); - GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add; - - // Fill PORT object structure for future use - obj->port = port; - obj->mask = mask; - obj->direction = dir; - obj->reg_in = &gpio->IDR; - obj->reg_out = &gpio->ODR; - - port_dir(obj, dir); -} - -void port_dir(port_t *obj, PinDirection dir) { - uint32_t i; - obj->direction = dir; - for (i = 0; i < 16; i++) { // Process all pins - if (obj->mask & (1 << i)) { // If the pin is used - if (dir == PIN_OUTPUT) { - pin_function(port_pin(obj->port, i), STM_PIN_DATA(GPIO_Mode_OUT, GPIO_OType_PP, GPIO_PuPd_NOPULL, 0xFF)); - } else { // PIN_INPUT - pin_function(port_pin(obj->port, i), STM_PIN_DATA(GPIO_Mode_IN, 0, GPIO_PuPd_NOPULL, 0xFF)); - } - } - } -} - -void port_mode(port_t *obj, PinMode mode) { - uint32_t i; - for (i = 0; i < 16; i++) { // Process all pins - if (obj->mask & (1 << i)) { // If the pin is used - pin_mode(port_pin(obj->port, i), mode); - } - } -} - -void port_write(port_t *obj, int value) { - *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask); -} - -int port_read(port_t *obj) { - if (obj->direction == PIN_OUTPUT) { - return (*obj->reg_out & obj->mask); - } else { // PIN_INPUT - return (*obj->reg_in & obj->mask); - } -} - -#endif
--- a/targets/hal/TARGET_STM/TARGET_STM32F3XX/pwmout_api.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,274 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "pwmout_api.h" - -#include "cmsis.h" -#include "pinmap.h" - -// TIM2 cannot be used because already used by the us_ticker -static const PinMap PinMap_PWM[] = { -// {PA_0, PWM_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM2_CH1 -// {PA_1, PWM_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM2_CH2 - {PA_1, PWM_15, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_9)}, // TIM15_CH1N - {PA_2, PWM_15, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_9)}, // TIM15_CH1 - {PA_3, PWM_15, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_9)}, // TIM15_CH2 -// {PA_5, PWM_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM2_CH1 - {PA_6, PWM_16, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM16_CH1 - {PA_7, PWM_17, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM17_CH1 -// {PA_7, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_6)}, // TIM1_CH1N - {PA_8, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_6)}, // TIM1_CH1 - {PA_9, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_6)}, // TIM1_CH2 -// {PA_9, PWM_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_10)}, // TIM2_CH3 - {PA_10, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_6)}, // TIM1_CH3 -// {PA_10, PWM_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_10)}, // TIM2_CH4 - {PA_11, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_11)}, // TIM1_CH4 -// {PA_11, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_6)}, // TIM1_CH1N - {PA_12, PWM_16, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM16_CH1 -// {PA_12, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_6)}, // TIM1_CH2N - {PA_13, PWM_16, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM16_CH1N -// {PA_15, PWM_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM2_CH1 - - {PB_0, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_6)}, // TIM1_CH2N - {PB_1, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_6)}, // TIM1_CH3N -// {PB_3, PWM_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM2_CH2 - {PB_4, PWM_16, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM16_CH1 - {PB_5, PWM_17, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_10)}, // TIM17_CH1 - {PB_6, PWM_16, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM16_CH1N - {PB_7, PWM_17, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM17_CH1N - {PB_8, PWM_16, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM16_CH1 - {PB_9, PWM_17, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM17_CH1 -// {PB_10, PWM_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM2_CH3 -// {PB_11, PWM_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM2_CH4 - {PB_13, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_6)}, // TIM1_CH1N - {PB_14, PWM_15, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM15_CH1 -// {PB_14, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_6)}, // TIM1_CH2N - {PB_15, PWM_15, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_1)}, // TIM15_CH2 -// {PB_15, PWM_15, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_2)}, // TIM15_CH1N -// {PB_15, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_4)}, // TIM1_CH3N - - {PC_0, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_2)}, // TIM1_CH1 - {PC_1, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_2)}, // TIM1_CH2 - {PC_2, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_2)}, // TIM1_CH3 - {PC_3, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_2)}, // TIM1_CH4 - {PC_13, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_4)}, // TIM1_CH1N - - {PF_0, PWM_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_6)}, // TIM1_CH3N - - {NC, NC, 0} -}; - -void pwmout_init(pwmout_t* obj, PinName pin) { - // Get the peripheral name from the pin and assign it to the object - obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); - MBED_ASSERT(obj->pwm == (PWMName)NC); - - // Enable TIM clock - if (obj->pwm == PWM_1) RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE); - if (obj->pwm == PWM_15) RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM15, ENABLE); - if (obj->pwm == PWM_16) RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM16, ENABLE); - if (obj->pwm == PWM_17) RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM17, ENABLE); - - // Configure GPIO - pinmap_pinout(pin, PinMap_PWM); - - obj->pin = pin; - obj->period = 0; - obj->pulse = 0; - - pwmout_period_us(obj, 20000); // 20 ms per default -} - -void pwmout_free(pwmout_t* obj) { - TIM_TypeDef *tim = (TIM_TypeDef *)(obj->pwm); - TIM_DeInit(tim); -} - -void pwmout_write(pwmout_t* obj, float value) { - TIM_TypeDef *tim = (TIM_TypeDef *)(obj->pwm); - TIM_OCInitTypeDef TIM_OCInitStructure; - - if (value < (float)0.0) { - value = (float)0.0; - } else if (value > (float)1.0) { - value = (float)1.0; - } - - obj->pulse = (uint32_t)((float)obj->period * value); - - // Configure channels - TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; - TIM_OCInitStructure.TIM_Pulse = obj->pulse; - TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; - TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCPolarity_High; - TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Reset; - TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCNIdleState_Reset; - - switch (obj->pin) { - // Channels 1 -// case PA_0: - case PA_2: -// case PA_5: - case PA_6: - case PA_7: - case PA_8: - case PA_12: -// case PA_15: - case PB_4: - case PB_5: - case PB_8: - case PB_9: - case PB_14: - case PC_0: - TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; - TIM_OC1PreloadConfig(tim, TIM_OCPreload_Enable); - TIM_OC1Init(tim, &TIM_OCInitStructure); - break; - // Channels 1N - case PA_1: -// case PA_7: -// case PA_11: - case PA_13: - case PB_6: - case PB_7: - case PB_13: -// case PB_15: - case PC_13: - TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable; - TIM_OC1PreloadConfig(tim, TIM_OCPreload_Enable); - TIM_OC1Init(tim, &TIM_OCInitStructure); - break; - // Channels 2 -// case PA_1: - case PA_3: - case PA_9: -// case PB_3: - case PB_15: - case PC_1: - TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; - TIM_OC2PreloadConfig(tim, TIM_OCPreload_Enable); - TIM_OC2Init(tim, &TIM_OCInitStructure); - break; - // Channels 2N -// case PA_12: - case PB_0: -// case PB_14: - TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable; - TIM_OC2PreloadConfig(tim, TIM_OCPreload_Enable); - TIM_OC2Init(tim, &TIM_OCInitStructure); - break; - // Channels 3 -// case PA_9: - case PA_10: -// case PB_10: - case PC_2: - TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; - TIM_OC3PreloadConfig(tim, TIM_OCPreload_Enable); - TIM_OC3Init(tim, &TIM_OCInitStructure); - break; - // Channels 3N - case PB_1: - case PF_0: -// case PB_15: - TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable; - TIM_OC3PreloadConfig(tim, TIM_OCPreload_Enable); - TIM_OC3Init(tim, &TIM_OCInitStructure); - break; - // Channels 4 -// case PA_10: - case PA_11: -// case PB_11: - case PC_3: - TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; - TIM_OC4PreloadConfig(tim, TIM_OCPreload_Enable); - TIM_OC4Init(tim, &TIM_OCInitStructure); - break; - default: - return; - } -} - -float pwmout_read(pwmout_t* obj) { - float value = 0; - if (obj->period > 0) { - value = (float)(obj->pulse) / (float)(obj->period); - } - return ((value > (float)1.0) ? ((float)1.0) : (value)); -} - -void pwmout_period(pwmout_t* obj, float seconds) { - pwmout_period_us(obj, seconds * 1000000.0f); -} - -void pwmout_period_ms(pwmout_t* obj, int ms) { - pwmout_period_us(obj, ms * 1000); -} - -void pwmout_period_us(pwmout_t* obj, int us) { - TIM_TypeDef *tim = (TIM_TypeDef *)(obj->pwm); - TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; - float dc = pwmout_read(obj); - - TIM_Cmd(tim, DISABLE); - - obj->period = us; - - TIM_TimeBaseStructInit(&TIM_TimeBaseStructure); - TIM_TimeBaseStructure.TIM_Period = obj->period - 1; - TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick - TIM_TimeBaseStructure.TIM_ClockDivision = 0; - TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInit(tim, &TIM_TimeBaseStructure); - - // Set duty cycle again - pwmout_write(obj, dc); - - TIM_ARRPreloadConfig(tim, ENABLE); - - // Warning: Main Output must be enabled on TIM1, TIM8, TIM5, TIM6 and TIM17 - if ((obj->pwm == PWM_1) || (obj->pwm == PWM_15) || (obj->pwm == PWM_16) || (obj->pwm == PWM_17)) { - TIM_CtrlPWMOutputs(tim, ENABLE); - } - - TIM_Cmd(tim, ENABLE); -} - -void pwmout_pulsewidth(pwmout_t* obj, float seconds) { - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { - pwmout_pulsewidth_us(obj, ms * 1000); -} - -void pwmout_pulsewidth_us(pwmout_t* obj, int us) { - float value = (float)us / (float)obj->period; - pwmout_write(obj, value); -}
--- a/targets/hal/TARGET_STM/TARGET_STM32F3XX/rtc_api.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,138 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "rtc_api.h" - -static int rtc_inited = 0; - -void rtc_init(void) { - RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); // Enable PWR clock - - PWR_BackupAccessCmd(ENABLE); // Enable access to RTC - - // Be sure to start correctly - RCC_BackupResetCmd(ENABLE); - RCC_BackupResetCmd(DISABLE); - - // Note: the LSI is used as RTC source clock - // The RTC Clock may vary due to LSI frequency dispersion. - RCC_LSICmd(ENABLE); // Enable LSI - - while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) {} // Wait until ready - - RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI); // Select LSI as RTC Clock Source - - RCC_RTCCLKCmd(ENABLE); // Enable RTC Clock - - RTC_WaitForSynchro(); // Wait for RTC registers synchronization - - uint32_t lsi_freq = 40000; // [TODO] To be measured precisely using a timer input capture - - RTC_InitTypeDef RTC_InitStructure; - RTC_InitStructure.RTC_AsynchPrediv = 127; - RTC_InitStructure.RTC_SynchPrediv = (lsi_freq / 128) - 1; - RTC_InitStructure.RTC_HourFormat = RTC_HourFormat_24; - RTC_Init(&RTC_InitStructure); - - rtc_inited = 1; -} - -void rtc_free(void) { - RCC_DeInit(); // Resets the RCC clock configuration to the default reset state - rtc_inited = 0; -} - -int rtc_isenabled(void) { - return rtc_inited; -} - -/* - RTC Registers - RTC_WeekDay 1=monday, 2=tuesday, ..., 7=sunday - RTC_Month 1=january, 2=february, ..., 12=december - RTC_Date day of the month 1-31 - RTC_Year year 0-99 - struct tm - tm_sec seconds after the minute 0-61 - tm_min minutes after the hour 0-59 - tm_hour hours since midnight 0-23 - tm_mday day of the month 1-31 - tm_mon months since January 0-11 - tm_year years since 1900 - tm_wday days since Sunday 0-6 - tm_yday days since January 1 0-365 - tm_isdst Daylight Saving Time flag -*/ -time_t rtc_read(void) { - RTC_DateTypeDef dateStruct; - RTC_TimeTypeDef timeStruct; - struct tm timeinfo; - - // Read actual date and time - RTC_GetTime(RTC_Format_BIN, &timeStruct); - RTC_GetDate(RTC_Format_BIN, &dateStruct); - - // Setup a tm structure based on the RTC - timeinfo.tm_wday = dateStruct.RTC_WeekDay; - timeinfo.tm_mon = dateStruct.RTC_Month - 1; - timeinfo.tm_mday = dateStruct.RTC_Date; - timeinfo.tm_year = dateStruct.RTC_Year + 100; - timeinfo.tm_hour = timeStruct.RTC_Hours; - timeinfo.tm_min = timeStruct.RTC_Minutes; - timeinfo.tm_sec = timeStruct.RTC_Seconds; - - // Convert to timestamp - time_t t = mktime(&timeinfo); - - return t; -} - -void rtc_write(time_t t) { - RTC_DateTypeDef dateStruct; - RTC_TimeTypeDef timeStruct; - - // Convert the time into a tm - struct tm *timeinfo = localtime(&t); - - // Fill RTC structures - dateStruct.RTC_WeekDay = timeinfo->tm_wday; - dateStruct.RTC_Month = timeinfo->tm_mon + 1; - dateStruct.RTC_Date = timeinfo->tm_mday; - dateStruct.RTC_Year = timeinfo->tm_year - 100; - timeStruct.RTC_Hours = timeinfo->tm_hour; - timeStruct.RTC_Minutes = timeinfo->tm_min; - timeStruct.RTC_Seconds = timeinfo->tm_sec; - timeStruct.RTC_H12 = RTC_HourFormat_24; - - // Change the RTC current date/time - PWR_BackupAccessCmd(ENABLE); // Enable access to RTC - RTC_SetDate(RTC_Format_BIN, &dateStruct); - RTC_SetTime(RTC_Format_BIN, &timeStruct); - PWR_BackupAccessCmd(DISABLE); // Disable access to RTC -}
--- a/targets/hal/TARGET_STM/TARGET_STM32F3XX/serial_api.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,312 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "serial_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include <string.h> - -static const PinMap PinMap_UART_TX[] = { - {PA_2, UART_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)}, - {PA_9, UART_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)}, - {PA_14, UART_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)}, - {PB_3, UART_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)}, - {PB_6, UART_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)}, - {PB_9, UART_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)}, - {PB_10, UART_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)}, - {PC_4, UART_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)}, - {PC_10, UART_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_UART_RX[] = { - {PA_3, UART_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)}, - {PA_10, UART_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)}, - {PA_15, UART_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)}, - {PB_4, UART_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)}, - {PB_7, UART_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)}, - {PB_8, UART_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)}, - {PB_11, UART_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)}, - {PC_5, UART_1, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)}, - {PC_11, UART_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_UP, GPIO_AF_7)}, - {NC, NC, 0} -}; - -#define UART_NUM (2) - -static uint32_t serial_irq_ids[UART_NUM] = {0}; - -static uart_irq_handler irq_handler; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -static void init_usart(serial_t *obj) { - USART_TypeDef *usart = (USART_TypeDef *)(obj->uart); - USART_InitTypeDef USART_InitStructure; - - USART_Cmd(usart, DISABLE); - - USART_InitStructure.USART_BaudRate = obj->baudrate; - USART_InitStructure.USART_WordLength = obj->databits; - USART_InitStructure.USART_StopBits = obj->stopbits; - USART_InitStructure.USART_Parity = obj->parity; - USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_Init(usart, &USART_InitStructure); - - USART_Cmd(usart, ENABLE); -} - -void serial_init(serial_t *obj, PinName tx, PinName rx) { - // Determine the UART to use - UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); - UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); - - // Get the peripheral name from the pin and assign it to the object - obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj->uart != (UARTName)NC); - - // Enable USART clock - if (obj->uart == UART_1) { - RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); - } - if (obj->uart == UART_2) { - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); - } - if (obj->uart == UART_3) { - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); - } - - // Configure the UART pins - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - // Configure UART - obj->baudrate = 9600; - obj->databits = USART_WordLength_8b; - obj->stopbits = USART_StopBits_1; - obj->parity = USART_Parity_No; - - init_usart(obj); - - // The index is used by irq - if (obj->uart == UART_1) obj->index = 0; - if (obj->uart == UART_2) obj->index = 1; - if (obj->uart == UART_3) obj->index = 2; - - // For stdio management - if (obj->uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } - -} - -void serial_free(serial_t *obj) { - serial_irq_ids[obj->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) { - obj->baudrate = baudrate; - init_usart(obj); -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { - if (data_bits == 8) { - obj->databits = USART_WordLength_8b; - } else { - obj->databits = USART_WordLength_9b; - } - - switch (parity) { - case ParityOdd: - case ParityForced0: - obj->parity = USART_Parity_Odd; - break; - case ParityEven: - case ParityForced1: - obj->parity = USART_Parity_Even; - break; - default: // ParityNone - obj->parity = USART_Parity_No; - break; - } - - if (stop_bits == 2) { - obj->stopbits = USART_StopBits_2; - } else { - obj->stopbits = USART_StopBits_1; - } - - init_usart(obj); -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ - -// not api -static void uart_irq(USART_TypeDef* usart, int id) { - if (serial_irq_ids[id] != 0) { - if (USART_GetITStatus(usart, USART_IT_TC) != RESET) { - irq_handler(serial_irq_ids[id], TxIrq); - USART_ClearITPendingBit(usart, USART_IT_TC); - } - if (USART_GetITStatus(usart, USART_IT_RXNE) != RESET) { - irq_handler(serial_irq_ids[id], RxIrq); - USART_ClearITPendingBit(usart, USART_IT_RXNE); - } - } -} - -static void uart1_irq(void) { - uart_irq((USART_TypeDef*)UART_1, 0); -} -static void uart2_irq(void) { - uart_irq((USART_TypeDef*)UART_2, 1); -} -static void uart3_irq(void) { - uart_irq((USART_TypeDef*)UART_3, 2); -} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - USART_TypeDef *usart = (USART_TypeDef *)(obj->uart); - - if (obj->uart == UART_1) { - irq_n = USART1_IRQn; - vector = (uint32_t)&uart1_irq; - } - - if (obj->uart == UART_2) { - irq_n = USART2_IRQn; - vector = (uint32_t)&uart2_irq; - } - - if (obj->uart == UART_3) { - irq_n = USART3_IRQn; - vector = (uint32_t)&uart3_irq; - } - - if (enable) { - - if (irq == RxIrq) { - USART_ITConfig(usart, USART_IT_RXNE, ENABLE); - } else { // TxIrq - USART_ITConfig(usart, USART_IT_TC, ENABLE); - } - - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - - } else { // disable - - int all_disabled = 0; - - if (irq == RxIrq) { - USART_ITConfig(usart, USART_IT_RXNE, DISABLE); - // Check if TxIrq is disabled too - if ((usart->CR1 & USART_CR1_TXEIE) == 0) all_disabled = 1; - } else { // TxIrq - USART_ITConfig(usart, USART_IT_TXE, DISABLE); - // Check if RxIrq is disabled too - if ((usart->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1; - } - - if (all_disabled) NVIC_DisableIRQ(irq_n); - - } -} - -/****************************************************************************** - * READ/WRITE - ******************************************************************************/ - -int serial_getc(serial_t *obj) { - USART_TypeDef *usart = (USART_TypeDef *)(obj->uart); - while (!serial_readable(obj)); - return (int)(USART_ReceiveData(usart)); -} - -void serial_putc(serial_t *obj, int c) { - USART_TypeDef *usart = (USART_TypeDef *)(obj->uart); - while (!serial_writable(obj)); - USART_SendData(usart, (uint16_t)c); -} - -int serial_readable(serial_t *obj) { - int status; - USART_TypeDef *usart = (USART_TypeDef *)(obj->uart); - // Check if data is received - status = ((USART_GetFlagStatus(usart, USART_FLAG_RXNE) != RESET) ? 1 : 0); - return status; -} - -int serial_writable(serial_t *obj) { - int status; - USART_TypeDef *usart = (USART_TypeDef *)(obj->uart); - // Check if data is transmitted - status = ((USART_GetFlagStatus(usart, USART_FLAG_TXE) != RESET) ? 1 : 0); - return status; -} - -void serial_clear(serial_t *obj) { - USART_TypeDef *usart = (USART_TypeDef *)(obj->uart); - USART_ClearFlag(usart, USART_FLAG_TXE); - USART_ClearFlag(usart, USART_FLAG_RXNE); -} - -void serial_pinout_tx(PinName tx) { - pinmap_pinout(tx, PinMap_UART_TX); -} - -void serial_break_set(serial_t *obj) { - USART_TypeDef *usart = (USART_TypeDef *)(obj->uart); - USART_RequestCmd(usart, USART_Request_SBKRQ, ENABLE); -} - -void serial_break_clear(serial_t *obj) { - USART_TypeDef *usart = (USART_TypeDef *)(obj->uart); - USART_RequestCmd(usart, USART_Request_SBKRQ, DISABLE); - USART_ClearFlag(usart, USART_FLAG_SBK); -}
--- a/targets/hal/TARGET_STM/TARGET_STM32F3XX/sleep.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,55 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "sleep_api.h" -#include "cmsis.h" - -// This function is in the system_stm32f30x.c file -extern void SetSysClock(void); - -// MCU SLEEP mode -void sleep(void) { - // Enable PWR clock - RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); - - // Request to enter SLEEP mode - PWR_EnterSleepMode(PWR_SLEEPEntry_WFI); -} - -// MCU STOP mode -void deepsleep(void) { - // Enable PWR clock - RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); - - // Enter Stop Mode - PWR_EnterSTOPMode(PWR_Regulator_LowPower, PWR_STOPEntry_WFI); - - // After wake-up from STOP reconfigure the PLL - SetSysClock(); -}
--- a/targets/hal/TARGET_STM/TARGET_STM32F3XX/spi_api.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,273 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "spi_api.h" - -#if DEVICE_SPI - -#include <math.h> -#include "cmsis.h" -#include "pinmap.h" - -static const PinMap PinMap_SPI_MOSI[] = { - {PA_11, SPI_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_5)}, - {PB_5, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_6)}, - {PB_15, SPI_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_5)}, - {PC_12, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_6)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_MISO[] = { - {PA_10, SPI_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_5)}, - {PB_4, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_6)}, - {PB_14, SPI_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_5)}, - {PC_11, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_6)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_SCLK[] = { - {PB_3, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_6)}, - {PB_13, SPI_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_5)}, - {PC_10, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_6)}, - {PF_1, SPI_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_5)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_SSEL[] = { - {PA_4, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_6)}, - {PA_15, SPI_3, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_6)}, - {PB_12, SPI_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_5)}, - {PF_0, SPI_2, STM_PIN_DATA(GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_DOWN, GPIO_AF_5)}, - {NC, NC, 0} -}; - -static void init_spi(spi_t *obj) { - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - SPI_InitTypeDef SPI_InitStructure; - - SPI_Cmd(spi, DISABLE); - - SPI_InitStructure.SPI_Mode = obj->mode; - SPI_InitStructure.SPI_NSS = obj->nss; - SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; - SPI_InitStructure.SPI_DataSize = obj->bits; - SPI_InitStructure.SPI_CPOL = obj->cpol; - SPI_InitStructure.SPI_CPHA = obj->cpha; - SPI_InitStructure.SPI_BaudRatePrescaler = obj->br_presc; - SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; - SPI_InitStructure.SPI_CRCPolynomial = 7; - SPI_Init(spi, &SPI_InitStructure); - - SPI_RxFIFOThresholdConfig(spi, SPI_RxFIFOThreshold_QF); - - SPI_Cmd(spi, ENABLE); -} - -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { - // Determine the SPI to use - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - - SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); - SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); - - obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl); - - MBED_ASSERT(obj->spi != (SPIName)NC); - - // Enable SPI clock - if (obj->spi == SPI_2) { - RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE); - } - if (obj->spi == SPI_3) { - RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE); - } - - // Configure the SPI pins - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - - // Save new values - obj->bits = SPI_DataSize_8b; - obj->cpol = SPI_CPOL_Low; - obj->cpha = SPI_CPHA_1Edge; - obj->br_presc = SPI_BaudRatePrescaler_256; - - if (ssel != NC) { - pinmap_pinout(ssel, PinMap_SPI_SSEL); - } else { - obj->nss = SPI_NSS_SOFT; - } - - init_spi(obj); -} - -void spi_free(spi_t *obj) { - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - SPI_I2S_DeInit(spi); -} - -void spi_format(spi_t *obj, int bits, int mode, int slave) { - // Save new values - if (bits == 8) { - obj->bits = SPI_DataSize_8b; - } else { - obj->bits = SPI_DataSize_16b; - } - - switch (mode) { - case 0: - obj->cpol = SPI_CPOL_Low; - obj->cpha = SPI_CPHA_1Edge; - break; - case 1: - obj->cpol = SPI_CPOL_Low; - obj->cpha = SPI_CPHA_2Edge; - break; - case 2: - obj->cpol = SPI_CPOL_High; - obj->cpha = SPI_CPHA_1Edge; - break; - default: - obj->cpol = SPI_CPOL_High; - obj->cpha = SPI_CPHA_2Edge; - break; - } - - if (obj->nss != SPI_NSS_SOFT) { - obj->nss = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT; - } - - obj->mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER; - - init_spi(obj); -} - -void spi_frequency(spi_t *obj, int hz) { - // Values depend of PCLK1: 32 MHz if HSI is used, 36 MHz if HSE is used - if (hz < 250000) { - obj->br_presc = SPI_BaudRatePrescaler_256; // 125 kHz - 141 kHz - } else if ((hz >= 250000) && (hz < 500000)) { - obj->br_presc = SPI_BaudRatePrescaler_128; // 250 kHz - 280 kHz - } else if ((hz >= 500000) && (hz < 1000000)) { - obj->br_presc = SPI_BaudRatePrescaler_64; // 500 kHz - 560 kHz - } else if ((hz >= 1000000) && (hz < 2000000)) { - obj->br_presc = SPI_BaudRatePrescaler_32; // 1 MHz - 1.13 MHz - } else if ((hz >= 2000000) && (hz < 4000000)) { - obj->br_presc = SPI_BaudRatePrescaler_16; // 2 MHz - 2.25 MHz - } else if ((hz >= 4000000) && (hz < 8000000)) { - obj->br_presc = SPI_BaudRatePrescaler_8; // 4 MHz - 4.5 MHz - } else if ((hz >= 8000000) && (hz < 16000000)) { - obj->br_presc = SPI_BaudRatePrescaler_4; // 8 MHz - 9 MHz - } else { // >= 16000000 - obj->br_presc = SPI_BaudRatePrescaler_2; // 16 MHz - 18 MHz - } - init_spi(obj); -} - -static inline int ssp_readable(spi_t *obj) { - int status; - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - // Check if data is received - status = ((SPI_I2S_GetFlagStatus(spi, SPI_I2S_FLAG_RXNE) != RESET) ? 1 : 0); - return status; -} - -static inline int ssp_writeable(spi_t *obj) { - int status; - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - // Check if data is transmitted - status = ((SPI_I2S_GetFlagStatus(spi, SPI_I2S_FLAG_TXE) != RESET) ? 1 : 0); - return status; -} - -static inline void ssp_write(spi_t *obj, int value) { - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_writeable(obj)); - if (obj->bits == SPI_DataSize_8b) { - SPI_SendData8(spi, (uint8_t)value); - } else { - SPI_I2S_SendData16(spi, (uint16_t)value); - } -} - -static inline int ssp_read(spi_t *obj) { - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_readable(obj)); - if (obj->bits == SPI_DataSize_8b) { - return (int)SPI_ReceiveData8(spi); - } else { - return (int)SPI_I2S_ReceiveData16(spi); - } -} - -static inline int ssp_busy(spi_t *obj) { - int status; - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - status = ((SPI_I2S_GetFlagStatus(spi, SPI_I2S_FLAG_BSY) != RESET) ? 1 : 0); - return status; -} - -int spi_master_write(spi_t *obj, int value) { - ssp_write(obj, value); - return ssp_read(obj); -} - -int spi_slave_receive(spi_t *obj) { - return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0); -}; - -int spi_slave_read(spi_t *obj) { - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - if (obj->bits == SPI_DataSize_8b) { - return (int)SPI_ReceiveData8(spi); - } else { - return (int)SPI_I2S_ReceiveData16(spi); - } -} - -void spi_slave_write(spi_t *obj, int value) { - SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); - while (!ssp_writeable(obj)); - if (obj->bits == SPI_DataSize_8b) { - SPI_SendData8(spi, (uint8_t)value); - } else { - SPI_I2S_SendData16(spi, (uint16_t)value); - } -} - -int spi_busy(spi_t *obj) { - return ssp_busy(obj); -} - -#endif
--- a/targets/hal/TARGET_STM/TARGET_STM32F3XX/us_ticker.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,81 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include <stddef.h> -#include "us_ticker_api.h" -#include "PeripheralNames.h" - -// 32-bit timer selection -#define TIM_MST TIM2 -#define TIM_MST_IRQ TIM2_IRQn -#define TIM_MST_RCC RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE) - -static int us_ticker_inited = 0; - -void us_ticker_init(void) { - TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; - - if (us_ticker_inited) return; - us_ticker_inited = 1; - - // Enable timer clock - TIM_MST_RCC; - - // Configure time base - TIM_TimeBaseStructInit(&TIM_TimeBaseStructure); - TIM_TimeBaseStructure.TIM_Period = 0xFFFFFFFF; - TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 �s tick - TIM_TimeBaseStructure.TIM_ClockDivision = 0; - TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInit(TIM_MST, &TIM_TimeBaseStructure); - - NVIC_SetVector(TIM_MST_IRQ, (uint32_t)us_ticker_irq_handler); - NVIC_EnableIRQ(TIM_MST_IRQ); - - // Enable timer - TIM_Cmd(TIM_MST, ENABLE); -} - -uint32_t us_ticker_read() { - if (!us_ticker_inited) us_ticker_init(); - return TIM_MST->CNT; -} - -void us_ticker_set_interrupt(timestamp_t timestamp) { - // Set new output compare value - TIM_SetCompare1(TIM_MST, (uint32_t)timestamp); - // Enable IT - TIM_ITConfig(TIM_MST, TIM_IT_CC1, ENABLE); -} - -void us_ticker_disable_interrupt(void) { - TIM_ITConfig(TIM_MST, TIM_IT_CC1, DISABLE); -} - -void us_ticker_clear_interrupt(void) { - TIM_ClearITPendingBit(TIM_MST, TIM_IT_CC1); -}
--- a/targets/hal/TARGET_STM/TARGET_STM32F4XX/PeripheralNames.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,88 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - UART_1 = (int)USART1_BASE, - UART_2 = (int)USART2_BASE, - UART_3 = (int)USART3_BASE, - UART_4 = (int)UART4_BASE, - UART_5 = (int)UART5_BASE, - UART_6 = (int)USART6_BASE -} UARTName; - -typedef enum { - ADC0_0 = 0, - ADC0_1, - ADC0_2, - ADC0_3, - ADC0_4, - ADC0_5, - ADC0_6, - ADC0_7, - ADC0_8, - ADC0_9, - ADC0_10, - ADC0_11, - ADC0_12, - ADC0_13, - ADC0_14, - ADC0_15 -} ADCName; - -typedef enum { - DAC_0 = 0, - DAC_1 -} DACName; - -typedef enum { - SPI_1 = (int)SPI1_BASE, - SPI_2 = (int)SPI2_BASE, - SPI_3 = (int)SPI3_BASE, -} SPIName; - -typedef enum { - I2C_1 = (int)I2C1_BASE, - I2C_2 = (int)I2C2_BASE, - I2C_3 = (int)I2C3_BASE -} I2CName; - -typedef enum { - PWM_1 = 1, - PWM_2, - PWM_3, - PWM_4, - PWM_5, - PWM_6 -} PWMName; - -typedef enum { - CAN_1 = (int)CAN1_BASE, - CAN_2 = (int)CAN2_BASE -} CANName; - -#ifdef __cplusplus -} -#endif - -#endif
--- a/targets/hal/TARGET_STM/TARGET_STM32F4XX/PinNames.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,69 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define STM_PIN_DATA(MODE, FUNC) (((MODE) << 8) | (FUNC)) -#define STM_PIN_MODE(X) ((X) >> 8) -#define STM_PIN_FUNC(X) ((X) & 0xFF) - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 6 - -typedef enum { - // STM32 Pin Names - PA_0 = 0, PA_1, PA_2, PA_3, PA_4, PA_5, PA_6, PA_7, PA_8, PA_9, PA_10, PA_11, PA_12, PA_13, PA_14, PA_15, - PB_0, PB_1, PB_2, PB_3, PB_4, PB_5, PB_6, PB_7, PB_8, PB_9, PB_10, PB_11, PB_12, PB_13, PB_14, PB_15, - PC_0, PC_1, PC_2, PC_3, PC_4, PC_5, PC_6, PC_7, PC_8, PC_9, PC_10, PC_11, PC_12, PC_13, PC_14, PC_15, - PD_0, PD_1, PD_2, PD_3, PD_4, PD_5, PD_6, PD_7, PD_8, PD_9, PD_10, PD_11, PD_12, PD_13, PD_14, PD_15, - PE_0, PE_1, PE_2, PE_3, PE_4, PE_5, PE_6, PE_7, PE_8, PE_9, PE_10, PE_11, PE_12, PE_13, PE_14, PE_15, - PF_0, PF_1, PF_2, PF_3, PF_4, PF_5, PF_6, PF_7, PF_8, PF_9, PF_10, PF_11, PF_12, PF_13, PF_14, PF_15, - PH_0, PH_1, PH_2, PH_3, PH_4, PH_5, PH_6, PH_7, PH_8, PH_9, PH_10, PH_11, - - LED1 = PD_13, - LED2 = PD_12, - LED3 = PD_13, - LED4 = PD_12, - LED5 = PD_14, - LED6 = PD_15, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -typedef enum { - PullNone = 0, - PullUp = 1, - PullDown = 2, - OpenDrain = 3, - PullDefault = PullDown -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif
--- a/targets/hal/TARGET_STM/TARGET_STM32F4XX/PortNames.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,38 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PortA = 0, - PortB = 1, - PortC = 2, - PortD = 3, - PortE = 4, - PortF = 5, - PortG = 6, - PortH = 7, - PortI = 8 -} PortName; - -#ifdef __cplusplus -} -#endif -#endif
--- a/targets/hal/TARGET_STM/TARGET_STM32F4XX/analogin_api.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,96 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "analogin_api.h" - -#if DEVICE_ANALOGIN - -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" - -#define ADC_10BIT_RANGE 0x3FF -#define ADC_12BIT_RANGE 0xFFF - -static const PinMap PinMap_ADC[] = { - {PA_0, ADC0_0, STM_PIN_DATA(3, 0)}, - {PA_1, ADC0_1, STM_PIN_DATA(3, 0)}, - {PA_2, ADC0_2, STM_PIN_DATA(3, 0)}, - {PA_3, ADC0_3, STM_PIN_DATA(3, 0)}, - {PA_4, ADC0_4, STM_PIN_DATA(3, 0)}, - {PA_5, ADC0_5, STM_PIN_DATA(3, 0)}, - {PA_6, ADC0_6, STM_PIN_DATA(3, 0)}, - {PA_7, ADC0_7, STM_PIN_DATA(3, 0)}, - {PB_0, ADC0_8, STM_PIN_DATA(3, 0)}, - {PB_1, ADC0_9, STM_PIN_DATA(3, 0)}, - {PC_0, ADC0_10, STM_PIN_DATA(3, 0)}, - {PC_1, ADC0_11, STM_PIN_DATA(3, 0)}, - {PC_2, ADC0_12, STM_PIN_DATA(3, 0)}, - {PC_3, ADC0_13, STM_PIN_DATA(3, 0)}, - {PC_4, ADC0_14, STM_PIN_DATA(3, 0)}, - {PC_5, ADC0_15, STM_PIN_DATA(3, 0)}, - {NC, NC, 0} -}; - -# define ADC_RANGE ADC_12BIT_RANGE - -void analogin_init(analogin_t *obj, PinName pin) { - obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - MBED_ASSERT(obj->adc != (uint32_t)NC); - - // ensure power is turned on - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN; - RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; - - // Enable the ADC - ADC1->CR2 |= ADC_CR2_ADON; - - pinmap_pinout(pin, PinMap_ADC); -} - -static inline uint32_t adc_read(analogin_t *obj) { - // Select the appropriate channel - ADC1->SQR3 = (int) obj->adc; - - // Start conversion - ADC1->CR2 |= ADC_CR2_SWSTART; - - // Wait for conversion to finish - while (!(ADC1->SR & ADC_SR_EOC)); - - uint32_t data = ADC1->DR; - return data; // 12 bit -} - -static inline uint32_t adc_read_u32(analogin_t *obj) { - uint32_t value; - value = adc_read(obj); - return value; -} - -uint16_t analogin_read_u16(analogin_t *obj) { - uint32_t value = adc_read_u32(obj); - - return (value << 4) | ((value >> 8) & 0x000F); // 12 bit -} - -float analogin_read(analogin_t *obj) { - uint32_t value = adc_read_u32(obj); - return (float)value * (1.0f / (float)ADC_RANGE); -} - -#endif
--- a/targets/hal/TARGET_STM/TARGET_STM32F4XX/device.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,48 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_PORTIN 1 -#define DEVICE_PORTOUT 1 -#define DEVICE_PORTINOUT 1 - -#define DEVICE_INTERRUPTIN 0 - -#define DEVICE_ANALOGIN 1 -#define DEVICE_ANALOGOUT 0 - -#define DEVICE_SERIAL 0 - -#define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 0 - -#define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 1 - -#define DEVICE_CAN 0 - -#define DEVICE_RTC 0 - -#define DEVICE_ETHERNET 0 - -#define DEVICE_PWMOUT 0 - -#define DEVICE_SLEEP 0 - -#include "objects.h" - -#endif
--- a/targets/hal/TARGET_STM/TARGET_STM32F4XX/gpio_api.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,61 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "gpio_api.h" -#include "pinmap.h" - -uint32_t gpio_set(PinName pin) { - MBED_ASSERT(pin != (PinName)NC); - uint32_t port_index = (uint32_t) pin >> 4; - - // Enable GPIO peripheral clock - RCC->AHB1ENR |= 1 << port_index; - - pin_function(pin, STM_PIN_DATA(0, 0)); - return 1 << ((uint32_t) pin & 0xF); -} - -void gpio_init(gpio_t *obj, PinName pin) { - obj->pin = pin; - if (pin == (PinName)NC) - return; - - obj->mask = gpio_set(pin); - - uint32_t port_index = (uint32_t) pin >> 4; - - GPIO_TypeDef *port_reg = (GPIO_TypeDef *) (GPIOA_BASE + (port_index << 10)); - obj->reg_mode = &port_reg->MODER; - obj->reg_set = &port_reg->BSRRL; - obj->reg_clr = &port_reg->BSRRH; - obj->reg_in = &port_reg->IDR; -} - -void gpio_mode(gpio_t *obj, PinMode mode) { - pin_mode(obj->pin, mode); -} - -void gpio_dir(gpio_t *obj, PinDirection direction) { - MBED_ASSERT(obj->pin != (PinName)NC); - switch (direction) { - case PIN_INPUT : - pin_function(obj->pin, STM_PIN_DATA(0, 0)); - break; - case PIN_OUTPUT: - pin_function(obj->pin, STM_PIN_DATA(1, 0)); - break; - } -}
--- a/targets/hal/TARGET_STM/TARGET_STM32F4XX/gpio_object.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,57 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - uint32_t mask; - - __IO uint32_t *reg_mode; - __IO uint16_t *reg_set; - __IO uint16_t *reg_clr; - __I uint32_t *reg_in; - __O uint32_t *reg_out; -} gpio_t; - -static inline void gpio_write(gpio_t *obj, int value) { - MBED_ASSERT(obj->pin != (PinName)NC); - if (value) - *obj->reg_set = obj->mask; - else - *obj->reg_clr = obj->mask; -} - -static inline int gpio_read(gpio_t *obj) { - MBED_ASSERT(obj->pin != (PinName)NC); - return ((*obj->reg_in & obj->mask) ? 1 : 0); -} - -static inline int gpio_is_connected(const gpio_t *obj) { - return obj->pin != (PinName)NC; -} - -#ifdef __cplusplus -} -#endif - -#endif
--- a/targets/hal/TARGET_STM/TARGET_STM32F4XX/i2c_api.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,294 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "i2c_api.h" - -#if DEVICE_I2C - -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" - -static const PinMap PinMap_I2C_SDA[] = { - {PB_7, I2C_1, STM_PIN_DATA(2, 4)}, - {PB_9, I2C_1, STM_PIN_DATA(2, 4)}, - {PB_11, I2C_2, STM_PIN_DATA(2, 4)}, - {PC_9, I2C_3, STM_PIN_DATA(2, 4)}, - {PF_0, I2C_2, STM_PIN_DATA(2, 4)}, - {PH_5, I2C_2, STM_PIN_DATA(2, 4)}, - {PH_8, I2C_3, STM_PIN_DATA(2, 4)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_I2C_SCL[] = { - {PA_8, I2C_3, STM_PIN_DATA(2, 4)}, - {PB_6, I2C_1, STM_PIN_DATA(2, 4)}, - {PB_8, I2C_1, STM_PIN_DATA(2, 4)}, - {PB_10, I2C_2, STM_PIN_DATA(2, 4)}, - {PF_1, I2C_2, STM_PIN_DATA(2, 4)}, - {PH_4, I2C_2, STM_PIN_DATA(2, 4)}, - {PH_7, I2C_3, STM_PIN_DATA(2, 4)}, - {NC, NC, 0} -}; - -static const uint32_t I2C_addr_offset[2][4] = { - {0x0C, 0x20, 0x24, 0x28}, - {0x30, 0x34, 0x38, 0x3C} -}; - - -static inline void i2c_interface_enable(i2c_t *obj) { - obj->i2c->CR1 |= I2C_CR1_PE; -} - -static inline void i2c_interface_disable(i2c_t *obj) { - obj->i2c->CR1 &= ~I2C_CR1_PE; -} - - -static inline void i2c_power_enable(i2c_t *obj) { - switch ((int)obj->i2c) { - case I2C_1: - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN; - RCC->APB1ENR |= RCC_APB1ENR_I2C1EN; - break; - case I2C_2: - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOFEN | - RCC_AHB1ENR_GPIOHEN; - RCC->APB1ENR |= RCC_APB1ENR_I2C2EN; - break; - case I2C_3: - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOCEN | - RCC_AHB1ENR_GPIOHEN; - RCC->APB1ENR |= RCC_APB1ENR_I2C3EN; - break; - } -} - -static inline void i2c_wait_status(i2c_t *obj, uint32_t sr1_mask, - uint32_t sr2_mask) { - while (!(((obj->i2c->SR1 & sr1_mask) >= sr1_mask) && - ((obj->i2c->SR2 & sr2_mask) == sr2_mask))); -} - -// Wait until the slave address has been acknowledged -static inline void i2c_wait_addr_tx(i2c_t *obj) { - uint32_t sr1_mask = I2C_SR1_ADDR | I2C_SR1_TXE; - uint32_t sr2_mask = I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA; - i2c_wait_status(obj, sr1_mask, sr2_mask); -} - -// Wait until the slave address has been acknowledged -static inline void i2c_wait_addr_rx(i2c_t *obj) { - uint32_t sr1_mask = I2C_SR1_ADDR; - uint32_t sr2_mask = I2C_SR2_MSL | I2C_SR2_BUSY; - i2c_wait_status(obj, sr1_mask, sr2_mask); -} - - -// Wait until a byte has been sent -static inline void i2c_wait_send(i2c_t *obj) { - uint32_t sr1_mask = I2C_SR1_BTF | I2C_SR1_TXE; - uint32_t sr2_mask = I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA; - i2c_wait_status(obj, sr1_mask, sr2_mask); -} - -// Wait until a byte has been received -static inline void i2c_wait_receive(i2c_t *obj) { - uint32_t sr1_mask = I2C_SR1_RXNE; - uint32_t sr2_mask = I2C_SR2_MSL | I2C_SR2_BUSY; - i2c_wait_status(obj, sr1_mask, sr2_mask); -} - -// Wait until the start condition has been accepted -static inline void i2c_wait_start(i2c_t *obj) { - uint32_t sr1_mask = I2C_SR1_SB; - uint32_t sr2_mask = I2C_SR2_MSL | I2C_SR2_BUSY; - i2c_wait_status(obj, sr1_mask, sr2_mask); -} - -void i2c_init(i2c_t *obj, PinName sda, PinName scl) { - // determine the SPI to use - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - obj->i2c = (I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT((int)obj->i2c != NC); - - // enable power - i2c_power_enable(obj); - - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - - pin_mode(sda, OpenDrain); - pin_mode(scl, OpenDrain); - - // Force reset if the bus is stuck in the BUSY state - if (obj->i2c->SR2 & I2C_SR2_BUSY) { - obj->i2c->CR1 |= I2C_CR1_SWRST; - obj->i2c->CR1 &= ~I2C_CR1_SWRST; - } - - // Set the peripheral clock frequency - obj->i2c->CR2 |= 42; - - // set default frequency at 100k - i2c_frequency(obj, 100000); - i2c_interface_enable(obj); -} - -inline int i2c_start(i2c_t *obj) { - // Wait until we are not busy any more - while (obj->i2c->SR2 & I2C_SR2_BUSY); - - // Generate the start condition - obj->i2c->CR1 |= I2C_CR1_START; - i2c_wait_start(obj); - - return 0; -} - -inline int i2c_stop(i2c_t *obj) { - // Generate the stop condition - obj->i2c->CR1 |= I2C_CR1_STOP; - return 0; -} - - -static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) { - obj->i2c->DR = value; - return 0; -} - -static inline int i2c_do_read(i2c_t *obj, int last) { - if(last) { - // Don't acknowledge the byte - obj->i2c->CR1 &= ~(I2C_CR1_ACK); - } else { - // Acknowledge the byte - obj->i2c->CR1 |= I2C_CR1_ACK; - } - - // Wait until we receive the byte - i2c_wait_receive(obj); - - int data = obj->i2c->DR; - return data; -} - -void i2c_frequency(i2c_t *obj, int hz) { - i2c_interface_disable(obj); - obj->i2c->CCR &= ~(I2C_CCR_CCR | I2C_CCR_FS); - if (hz > 100000) { - // Fast Mode - obj->i2c->CCR |= I2C_CCR_FS; - int result = 42000000 / (hz * 3); - obj->i2c->CCR |= result & I2C_CCR_CCR; - obj->i2c->TRISE = ((42 * 300) / 1000) + 1; - } - else { - // Standard mode - obj->i2c->CCR &= ~I2C_CCR_FS; - int result = 42000000 / (hz << 1); - result = result < 0x4 ? 0x4 : result; - obj->i2c->CCR |= result & I2C_CCR_CCR; - obj->i2c->TRISE = 42 + 1; - } - i2c_interface_enable(obj); -} - -// The I2C does a read or a write as a whole operation -// There are two types of error conditions it can encounter -// 1) it can not obtain the bus -// 2) it gets error responses at part of the transmission -// -// We tackle them as follows: -// 1) we retry until we get the bus. we could have a "timeout" if we can not get it -// which basically turns it in to a 2) -// 2) on error, we use the standard error mechanisms to report/debug -// -// Therefore an I2C transaction should always complete. If it doesn't it is usually -// because something is setup wrong (e.g. wiring), and we don't need to programatically -// check for that - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { - int count; - - i2c_start(obj); - - // Send the slave address - i2c_do_write(obj, (address | 0x01), 1); - - // Wait until we have transmitted and the ADDR byte is set - i2c_wait_addr_rx(obj); - - // Read in all except last byte - for (count = 0; count < (length - 1); count++) { - int value = i2c_do_read(obj, 0); - data[count] = (char) value; - } - - // read in last byte - int value = i2c_do_read(obj, 1); - data[count] = (char) value; - - // If not repeated start, send stop. - if (stop) { - i2c_stop(obj); - } - - return length; -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { - int i; - - i2c_start(obj); - - // Send the slave address - i2c_do_write(obj, (address & 0xFE), 1); - i2c_wait_addr_tx(obj); - - for (i=0; i<length; i++) { - i2c_do_write(obj, data[i], 0); - i2c_wait_send(obj); - } - - // If not repeated start, send stop. - if (stop) { - i2c_stop(obj); - } - - return length; -} - -void i2c_reset(i2c_t *obj) { - i2c_stop(obj); -} - -int i2c_byte_read(i2c_t *obj, int last) { - return (i2c_do_read(obj, last) & 0xFF); -} - -int i2c_byte_write(i2c_t *obj, int data) { - i2c_do_write(obj, (data & 0xFF), 0); - i2c_wait_send(obj); - - // TODO: Should return whether write has been acknowledged - return 1; -} - -#endif
--- a/targets/hal/TARGET_STM/TARGET_STM32F4XX/objects.h Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,81 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct gpio_irq_s { - uint32_t port; - uint32_t pin; - uint32_t ch; -}; - -struct port_s { - __IO uint32_t *reg_mode; - __IO uint32_t *reg_in; - __IO uint32_t *reg_out; - __IO uint16_t *reg_set; - __IO uint16_t *reg_clr; - PortName port; - uint32_t mask; - PinDirection direction; -}; - -struct pwmout_s { - __IO uint32_t *MR; - PWMName pwm; -}; - -struct serial_s { - USART_TypeDef *uart; - int index; -}; - -struct analogin_s { - ADCName adc; -}; - -struct dac_s { - DACName dac; -}; - -struct can_s { - CAN_TypeDef *dev; -}; - -struct i2c_s { - I2C_TypeDef *i2c; -}; - -struct spi_s { - SPI_TypeDef *spi; -}; - -#include "gpio_object.h" - -#ifdef __cplusplus -} -#endif - -#endif
--- a/targets/hal/TARGET_STM/TARGET_STM32F4XX/pinmap.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,74 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "pinmap.h" -#include "mbed_error.h" - -/** - * Set the pin into input, output, alternate function or analog mode - */ -void pin_function(PinName pin, int data) { - MBED_ASSERT(pin != (PinName)NC); - - int mode = STM_PIN_MODE(data); - int func = STM_PIN_FUNC(data); - - uint32_t pin_number = (uint32_t)pin; - int port_index = pin_number >> 4; - int pin_index = (pin_number & 0xF); - GPIO_TypeDef * gpio = ((GPIO_TypeDef *) (GPIOA_BASE + (port_index << 10))); - - // MODE - int offset = pin_index << 1; - gpio->MODER &= ~(0x3 << offset); - gpio->MODER |= mode << offset; - - // Set high-speed mode - gpio->OSPEEDR &= ~(0x3 << offset); - gpio->OSPEEDR |= (0x2 << offset); - - // FUNCTION - // Bottom seven pins are in AFR[0], top seven in AFR[1] - offset = (pin_index & 0x7) << 2; - if (pin_index <= 0x7) { - gpio->AFR[0] &= ~(0xF << offset); - gpio->AFR[0] |= func << offset; - } - else { - gpio->AFR[1] &= ~(0xF << offset); - gpio->AFR[1] |= func << offset; - } -} - -void pin_mode(PinName pin, PinMode mode) { - MBED_ASSERT(pin != (PinName)NC); - - uint32_t pin_number = (uint32_t)pin; - int port_index = pin_number >> 4; - int pin_index = (pin_number & 0xF); - int offset = pin_index << 1; - - GPIO_TypeDef * gpio = ((GPIO_TypeDef *) (GPIOA_BASE + (port_index << 10))); - if (mode == OpenDrain) { - gpio->OTYPER |= 1 << pin_index; - } - else { - gpio->OTYPER &= ~(1 << pin_index); - gpio->PUPDR &= ~(0x3 << offset); - gpio->PUPDR |= mode << offset; - } -} -
--- a/targets/hal/TARGET_STM/TARGET_STM32F4XX/port_api.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,83 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "port_api.h" -#include "pinmap.h" -#include "gpio_api.h" - -#if DEVICE_PORTIN || DEVICE_PORTOUT - -PinName port_pin(PortName port, int pin_n) { - return pin_n + (port << 4); -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { - obj->port = port; - obj->mask = mask; - - uint32_t port_index = (uint32_t) port; - - GPIO_TypeDef *port_reg = (GPIO_TypeDef *)(GPIOA_BASE + (port_index << 10)); - // Enable GPIO peripheral clock - RCC->AHB1ENR |= 1 << port_index; - - obj->reg_mode = &port_reg->MODER; - obj->reg_set = &port_reg->BSRRH; - obj->reg_clr = &port_reg->BSRRL; - obj->reg_in = &port_reg->IDR; - obj->reg_out = &port_reg->ODR; - - port_dir(obj, dir); -} - -void port_mode(port_t *obj, PinMode mode) { - uint32_t i; - // The mode is set per pin: reuse pinmap logic - for (i=0; i<16; i++) { - if (obj->mask & (1<<i)) { - pin_mode(port_pin(obj->port, i), mode); - } - } -} - -void port_dir(port_t *obj, PinDirection dir) { - obj->direction = dir; - uint32_t tmp = *obj->reg_mode; - for (int i=0; i<16; i++) { - if (obj->mask & (1 << i)) { - // Clear the mode bits (i.e. set to input) - tmp &= ~(0x3 << (i << 1)); - if (dir == PIN_OUTPUT) { - // Set to output - tmp |= 0x1 << (i << 1); - } - } - } - *obj->reg_mode = tmp; -} - -void port_write(port_t *obj, int value) { - *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask); -} - -int port_read(port_t *obj) { - switch (obj->direction) { - case PIN_OUTPUT: return *obj->reg_out & obj->mask; - case PIN_INPUT: return *obj->reg_in & obj->mask; - } - return 0; -} - -#endif
--- a/targets/hal/TARGET_STM/TARGET_STM32F4XX/spi_api.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,221 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "spi_api.h" - -#if DEVICE_SPI -#include <math.h> - -#include "cmsis.h" -#include "pinmap.h" - -static const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI_1, STM_PIN_DATA(2, 5)}, - {PB_3, SPI_1, STM_PIN_DATA(2, 5)}, - {PB_3, SPI_3, STM_PIN_DATA(2, 6)}, - {PB_10, SPI_2, STM_PIN_DATA(2, 5)}, - {PB_13, SPI_2, STM_PIN_DATA(2, 5)}, - {PC_10, SPI_3, STM_PIN_DATA(2, 6)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI_1, STM_PIN_DATA(2, 5)}, - {PB_5, SPI_1, STM_PIN_DATA(2, 5)}, - {PB_5, SPI_3, STM_PIN_DATA(2, 6)}, - {PB_15, SPI_2, STM_PIN_DATA(2, 5)}, - {PC_3, SPI_2, STM_PIN_DATA(2, 5)}, - {PC_12, SPI_3, STM_PIN_DATA(2, 6)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI_1, STM_PIN_DATA(2, 5)}, - {PB_4, SPI_1, STM_PIN_DATA(2, 5)}, - {PB_4, SPI_3, STM_PIN_DATA(2, 6)}, - {PB_14, SPI_2, STM_PIN_DATA(2, 5)}, - {PC_2, SPI_2, STM_PIN_DATA(2, 5)}, - {PC_11, SPI_3, STM_PIN_DATA(2, 6)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SPI_SSEL[] = { - {PA_4, SPI_1, STM_PIN_DATA(2, 5)}, - {PA_4, SPI_3, STM_PIN_DATA(2, 6)}, - {PA_15, SPI_1, STM_PIN_DATA(2, 5)}, - {PA_15, SPI_3, STM_PIN_DATA(2, 6)}, - {PB_9, SPI_2, STM_PIN_DATA(2, 5)}, - {PB_12, SPI_2, STM_PIN_DATA(2, 5)}, - {NC, NC, 0} -}; - - -static inline int ssp_disable(spi_t *obj); -static inline int ssp_enable(spi_t *obj); - -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { - // determine the SPI to use - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); - SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); - obj->spi = (SPI_TypeDef*)pinmap_merge(spi_data, spi_cntl); - MBED_ASSERT((int)obj->spi != NC); - - // enable power and clocking - switch ((int)obj->spi) { - case SPI_1: - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN; - RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; - break; - case SPI_2: - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN; - RCC->APB1ENR |= RCC_APB1ENR_SPI2EN; - break; - case SPI_3: - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN; - RCC->APB1ENR |= RCC_APB1ENR_SPI3EN; - break; - } - - // pin out the spi pins - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - if (ssel != NC) { - pinmap_pinout(ssel, PinMap_SPI_SSEL); - } else { - // Use software slave management - obj->spi->CR1 |= SPI_CR1_SSM | SPI_CR1_SSI; - } -} - -void spi_free(spi_t *obj) {} - -void spi_format(spi_t *obj, int bits, int mode, int slave) { - MBED_ASSERT(((bits == 8) || (bits == 16)) && ((mode >= 0) && (mode <= 3))); - ssp_disable(obj); - - int polarity = (mode & 0x2) ? 1 : 0; - int phase = (mode & 0x1) ? 1 : 0; - - obj->spi->CR1 &= ~0x807; - obj->spi->CR1 |= ((phase) ? 1 : 0) << 0 | - ((polarity) ? 1 : 0) << 1 | - ((slave) ? 0: 1) << 2 | - ((bits == 16) ? 1 : 0) << 11; - - if (slave) { - // Use software slave management - obj->spi->CR1 |= SPI_CR1_SSM | SPI_CR1_SSI; - } - - if (obj->spi->SR & SPI_SR_MODF) { - obj->spi->CR1 = obj->spi->CR1; - } - - ssp_enable(obj); -} - -void spi_frequency(spi_t *obj, int hz) { - ssp_disable(obj); - - // SPI1 runs from PCLK2, which runs at SystemCoreClock / 2. SPI2 and SPI3 - // run from PCLK1, which runs at SystemCoreClock / 4. - uint32_t PCLK = SystemCoreClock; - switch ((int)obj->spi) { - case SPI_1: PCLK = PCLK >> 1; break; - case SPI_2: PCLK = PCLK >> 2; break; - case SPI_3: PCLK = PCLK >> 2; break; - } - - // Choose the baud rate divisor (between 2 and 256) - uint32_t divisor = PCLK / hz; - - // Find the nearest power-of-2 - divisor = divisor > 0 ? divisor-1 : 0; - divisor |= divisor >> 1; - divisor |= divisor >> 2; - divisor |= divisor >> 4; - divisor |= divisor >> 8; - divisor |= divisor >> 16; - divisor++; - - uint32_t baud_rate = __builtin_ffs(divisor) - 1; - baud_rate = baud_rate > 0x7 ? 0x7 : baud_rate; - - obj->spi->CR1 &= ~(0x7 << 3); - obj->spi->CR1 |= baud_rate << 3; - - ssp_enable(obj); -} - -static inline int ssp_disable(spi_t *obj) { - // TODO: Follow the instructions in 25.3.8 for safely disabling the SPI - return obj->spi->CR1 &= ~SPI_CR1_SPE; -} - -static inline int ssp_enable(spi_t *obj) { - return obj->spi->CR1 |= SPI_CR1_SPE; -} - -static inline int ssp_readable(spi_t *obj) { - return obj->spi->SR & SPI_SR_RXNE; -} - -static inline int ssp_writeable(spi_t *obj) { - return obj->spi->SR & SPI_SR_TXE; -} - -static inline void ssp_write(spi_t *obj, int value) { - while (!ssp_writeable(obj)); - obj->spi->DR = value; -} - -static inline int ssp_read(spi_t *obj) { - while (!ssp_readable(obj)); - return obj->spi->DR; -} - -static inline int ssp_busy(spi_t *obj) { - return (obj->spi->SR & SPI_SR_BSY) ? (1) : (0); -} - -int spi_master_write(spi_t *obj, int value) { - ssp_write(obj, value); - return ssp_read(obj); -} - -int spi_slave_receive(spi_t *obj) { - return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0); -}; - -int spi_slave_read(spi_t *obj) { - return obj->spi->DR; -} - -void spi_slave_write(spi_t *obj, int value) { - while (ssp_writeable(obj) == 0) ; - obj->spi->DR = value; -} - -int spi_busy(spi_t *obj) { - return ssp_busy(obj); -} - -#endif
--- a/targets/hal/TARGET_STM/TARGET_STM32F4XX/us_ticker.c Wed Apr 27 19:30:12 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,63 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include <stddef.h> -#include "us_ticker_api.h" -#include "PeripheralNames.h" - -#define US_TICKER_TIMER TIM2 -#define US_TICKER_TIMER_IRQn TIM2_IRQn - -int us_ticker_inited = 0; - -void us_ticker_init(void) { - if (us_ticker_inited) return; - us_ticker_inited = 1; - - RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; - - uint32_t PCLK = SystemCoreClock / 4; - - uint32_t prescale = PCLK / 1000000; // default to 1MHz (1 us ticks) - US_TICKER_TIMER->PSC = prescale - 1; - US_TICKER_TIMER->CR1 |= TIM_CR1_CEN; - // Trigger an update - this needs to happen after the counter is enabled. - US_TICKER_TIMER->EGR |= TIM_EGR_UG; - - NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler); - NVIC_EnableIRQ(US_TICKER_TIMER_IRQn); -} - -uint32_t us_ticker_read() { - if (!us_ticker_inited) - us_ticker_init(); - - return US_TICKER_TIMER->CNT; -} - -void us_ticker_set_interrupt(timestamp_t timestamp) { - // set match value - US_TICKER_TIMER->CCR1 = (uint32_t)timestamp; - // enable compare interrupt - US_TICKER_TIMER->DIER |= TIM_DIER_CC1IE; -} - -void us_ticker_disable_interrupt(void) { - US_TICKER_TIMER->DIER &= ~TIM_DIER_CC1IE; -} - -void us_ticker_clear_interrupt(void) { - US_TICKER_TIMER->SR &= ~TIM_SR_CC1IF; -}